diff --git a/src_SSITH_P3/Verilog_RTL/mkAluDispToRegFifo.v b/src_SSITH_P3/Verilog_RTL/mkAluDispToRegFifo.v index a697760..eee29a5 100644 --- a/src_SSITH_P3/Verilog_RTL/mkAluDispToRegFifo.v +++ b/src_SSITH_P3/Verilog_RTL/mkAluDispToRegFifo.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:54:34 BST 2020 +// On Thu Jul 2 02:57:22 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkAluExeToFinFifo.v b/src_SSITH_P3/Verilog_RTL/mkAluExeToFinFifo.v index c089657..93ce9d9 100644 --- a/src_SSITH_P3/Verilog_RTL/mkAluExeToFinFifo.v +++ b/src_SSITH_P3/Verilog_RTL/mkAluExeToFinFifo.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:54:35 BST 2020 +// On Thu Jul 2 02:57:23 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkAluRegToExeFifo.v b/src_SSITH_P3/Verilog_RTL/mkAluRegToExeFifo.v index f47c1b6..f841252 100644 --- a/src_SSITH_P3/Verilog_RTL/mkAluRegToExeFifo.v +++ b/src_SSITH_P3/Verilog_RTL/mkAluRegToExeFifo.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:54:34 BST 2020 +// On Thu Jul 2 02:57:23 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkBht.v b/src_SSITH_P3/Verilog_RTL/mkBht.v index aceaf5a..1c572c0 100644 --- a/src_SSITH_P3/Verilog_RTL/mkBht.v +++ b/src_SSITH_P3/Verilog_RTL/mkBht.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:53:27 BST 2020 +// On Thu Jul 2 02:55:23 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkCore.v b/src_SSITH_P3/Verilog_RTL/mkCore.v index 8016884..e9a044b 100644 --- a/src_SSITH_P3/Verilog_RTL/mkCore.v +++ b/src_SSITH_P3/Verilog_RTL/mkCore.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jul 1 17:06:51 BST 2020 +// On Thu Jul 2 02:58:25 BST 2020 // // // Ports: @@ -3539,7 +3539,7 @@ module mkCore(CLK, MUX_fetchStage$redirect_1__VAL_1, MUX_fetchStage$redirect_1__VAL_6; wire [64 : 0] MUX_f_csr_rsps$enq_1__VAL_3, MUX_f_fpr_rsps$enq_1__VAL_3; - wire [63 : 0] MUX_commitStage_rg_serial_num$write_1__VAL_2, + wire [63 : 0] MUX_commitStage_rg_serial_num$write_1__VAL_1, MUX_commitStage_rg_serial_num$write_1__VAL_3, MUX_csrf_minstret_ehr_data_lat_0$wset_1__VAL_2, MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1, @@ -3694,7 +3694,7 @@ module mkCore(CLK, MUX_epochManager$updatePrevEpoch_0_update_1__SEL_2, MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2, MUX_f_run_halt_rsps$enq_1__SEL_1, - MUX_flush_reservation$write_1__SEL_1, + MUX_flush_reservation$write_1__SEL_2, MUX_flush_tlbs$write_1__SEL_1, MUX_regRenamingTable$rename_0_getRename_1__SEL_1, MUX_regRenamingTable$rename_0_getRename_1__SEL_2, @@ -3716,47 +3716,48 @@ module mkCore(CLK, MUX_sbAggr$setReady_4_put_1__SEL_2, MUX_sbCons$setReady_3_put_1__SEL_1, MUX_sbCons$setReady_3_put_1__SEL_2, - MUX_sbCons$setReady_3_put_1__SEL_3; + MUX_sbCons$setReady_3_put_1__SEL_3, + MUX_started$write_1__SEL_1; // declarations used by system tasks // synopsys translate_off - reg [63 : 0] v__h213413; - reg [63 : 0] v__h215682; - reg [63 : 0] v__h271939; - reg [63 : 0] v__h347457; - reg [63 : 0] v__h423783; + reg [63 : 0] v__h213411; + reg [63 : 0] v__h215680; + reg [63 : 0] v__h271938; + reg [63 : 0] v__h347456; + reg [63 : 0] v__h423782; // synopsys translate_on // remaining internal signals reg [515 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5488; reg [127 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d4891; - reg [65 : 0] thin_address__h858473, thin_address__h899109; - reg [63 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q365, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q366, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q293, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q294, + reg [65 : 0] thin_address__h858472, thin_address__h899107; + reg [63 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q367, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q368, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q295, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q296, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q297, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q298, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q306, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q307, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q299, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q300, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q308, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q309, CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q18, CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q19, CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q20, CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q21, - CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q370, - CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q371, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q319, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q299, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q300, + CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q372, + CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q373, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q321, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q301, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q302, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q303, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q304, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q309, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q310, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q305, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q306, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q311, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q312, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q313, CASE_coreFix_memExe_lsqfirstLd_BIT_37_0_coreF_ETC__q33, CASE_coreFix_memExe_lsqfirstLd_BIT_37_0_mmio__ETC__q35, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14095, @@ -3769,33 +3770,33 @@ module mkCore(CLK, SEL_ARR_coreFix_memExe_forwardQ_data_0_216_BIT_ETC___d2234, SEL_ARR_coreFix_memExe_memRespLdQ_data_0_133_B_ETC___d2147, SEL_ARR_coreFix_memExe_memRespLdQ_data_0_133_B_ETC___d2151, - addr__h505615, - addr__h843950, - addr__h887459, - data_out__h1019990, - trap_val__h996887, - x__h264732; + addr__h505614, + addr__h843948, + addr__h887458, + data_out__h1020024, + trap_val__h996922, + x__h264730; reg [51 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q28, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q30, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q32, - CASE_guard04483_0b0_theResult___snd12395_BITS__ETC__q233, - CASE_guard04483_0b0_theResult___snd12395_BITS__ETC__q234, - CASE_guard13795_0b0_sfdin22015_BITS_56_TO_5_0b_ETC__q235, - CASE_guard13795_0b0_sfdin22015_BITS_56_TO_5_0b_ETC__q236, - CASE_guard22864_0b0_theResult___snd30800_BITS__ETC__q237, - CASE_guard22864_0b0_theResult___snd30800_BITS__ETC__q238, - CASE_guard26326_0b0_theResult___snd34238_BITS__ETC__q227, - CASE_guard26326_0b0_theResult___snd34238_BITS__ETC__q228, - CASE_guard35638_0b0_sfdin43858_BITS_56_TO_5_0b_ETC__q229, - CASE_guard35638_0b0_sfdin43858_BITS_56_TO_5_0b_ETC__q230, - CASE_guard44707_0b0_theResult___snd52643_BITS__ETC__q231, - CASE_guard44707_0b0_theResult___snd52643_BITS__ETC__q232, - CASE_guard65179_0b0_theResult___snd73091_BITS__ETC__q217, - CASE_guard65179_0b0_theResult___snd73091_BITS__ETC__q218, - CASE_guard74491_0b0_sfdin82711_BITS_56_TO_5_0b_ETC__q219, - CASE_guard74491_0b0_sfdin82711_BITS_56_TO_5_0b_ETC__q220, - CASE_guard83560_0b0_theResult___snd91496_BITS__ETC__q221, - CASE_guard83560_0b0_theResult___snd91496_BITS__ETC__q222, + CASE_guard04480_0b0_theResult___snd12392_BITS__ETC__q233, + CASE_guard04480_0b0_theResult___snd12392_BITS__ETC__q234, + CASE_guard13792_0b0_sfdin22012_BITS_56_TO_5_0b_ETC__q235, + CASE_guard13792_0b0_sfdin22012_BITS_56_TO_5_0b_ETC__q236, + CASE_guard22861_0b0_theResult___snd30797_BITS__ETC__q237, + CASE_guard22861_0b0_theResult___snd30797_BITS__ETC__q238, + CASE_guard26323_0b0_theResult___snd34235_BITS__ETC__q225, + CASE_guard26323_0b0_theResult___snd34235_BITS__ETC__q226, + CASE_guard35635_0b0_sfdin43855_BITS_56_TO_5_0b_ETC__q229, + CASE_guard35635_0b0_sfdin43855_BITS_56_TO_5_0b_ETC__q230, + CASE_guard44704_0b0_theResult___snd52640_BITS__ETC__q231, + CASE_guard44704_0b0_theResult___snd52640_BITS__ETC__q232, + CASE_guard65176_0b0_theResult___snd73088_BITS__ETC__q217, + CASE_guard65176_0b0_theResult___snd73088_BITS__ETC__q218, + CASE_guard74488_0b0_sfdin82708_BITS_56_TO_5_0b_ETC__q219, + CASE_guard74488_0b0_sfdin82708_BITS_56_TO_5_0b_ETC__q220, + CASE_guard83557_0b0_theResult___snd91493_BITS__ETC__q221, + CASE_guard83557_0b0_theResult___snd91493_BITS__ETC__q222, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13270, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13297, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13316, @@ -3809,108 +3810,108 @@ module mkCore(CLK, IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d17257; reg [31 : 0] SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1872, SEL_ARR_mmio_dataRespQ_data_0_389_BITS_31_TO_0_ETC___d2040, - x__h264887; - reg [29 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_22_ETC__q348, - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_817_ETC__q288, - CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q342, - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_22_ETC__q359, - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_817_ETC__q283, - CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q353, - CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q368, - CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q364, + x__h264885; + reg [29 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_22_ETC__q350, + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_817_ETC__q290, + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q344, + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_22_ETC__q361, + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_817_ETC__q285, + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q355, + CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q370, + CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q366, IF_fetchStage_pipelines_0_first__0256_BITS_268_ETC___d20382, IF_fetchStage_pipelines_1_first__0265_BITS_268_ETC___d21343; - reg [22 : 0] CASE_guard02939_0b0_theResult___snd10962_BITS__ETC__q66, - CASE_guard02939_0b0_theResult___snd10962_BITS__ETC__q67, - CASE_guard22215_0b0_sfdin30308_BITS_56_TO_34_0_ETC__q96, - CASE_guard22215_0b0_sfdin30308_BITS_56_TO_34_0_ETC__q97, - CASE_guard30922_0b0_theResult___snd38921_BITS__ETC__q94, - CASE_guard30922_0b0_theResult___snd38921_BITS__ETC__q95, - CASE_guard39852_0b0_sfdin48074_BITS_56_TO_34_0_ETC__q98, - CASE_guard39852_0b0_sfdin48074_BITS_56_TO_34_0_ETC__q99, - CASE_guard48688_0b0_theResult___snd56711_BITS__ETC__q100, - CASE_guard48688_0b0_theResult___snd56711_BITS__ETC__q101, - CASE_guard67962_0b0_sfdin76055_BITS_56_TO_34_0_ETC__q129, - CASE_guard67962_0b0_sfdin76055_BITS_56_TO_34_0_ETC__q130, - CASE_guard76464_0b0_sfdin84559_BITS_56_TO_34_0_ETC__q61, - CASE_guard76464_0b0_sfdin84559_BITS_56_TO_34_0_ETC__q62, - CASE_guard76669_0b0_theResult___snd84668_BITS__ETC__q131, - CASE_guard76669_0b0_theResult___snd84668_BITS__ETC__q132, - CASE_guard85173_0b0_theResult___snd93172_BITS__ETC__q59, - CASE_guard85173_0b0_theResult___snd93172_BITS__ETC__q60, - CASE_guard85599_0b0_sfdin93821_BITS_56_TO_34_0_ETC__q133, - CASE_guard85599_0b0_sfdin93821_BITS_56_TO_34_0_ETC__q134, - CASE_guard94103_0b0_sfdin02325_BITS_56_TO_34_0_ETC__q63, - CASE_guard94103_0b0_sfdin02325_BITS_56_TO_34_0_ETC__q64, - CASE_guard94435_0b0_theResult___snd02458_BITS__ETC__q135, - CASE_guard94435_0b0_theResult___snd02458_BITS__ETC__q136, - _theResult___fst_sfd__h576437, - _theResult___fst_sfd__h585160, - _theResult___fst_sfd__h593742, - _theResult___fst_sfd__h602926, - _theResult___fst_sfd__h611562, - _theResult___fst_sfd__h622188, - _theResult___fst_sfd__h630909, - _theResult___fst_sfd__h639491, - _theResult___fst_sfd__h648675, - _theResult___fst_sfd__h657311, - _theResult___fst_sfd__h667935, - _theResult___fst_sfd__h676656, - _theResult___fst_sfd__h685238, - _theResult___fst_sfd__h694422, - _theResult___fst_sfd__h703058; - reg [17 : 0] CASE_csrf_mepcc_reg_data_rl_BITS_52_TO_35_2621_ETC__q277, - CASE_csrf_sepcc_reg_data_rl_BITS_52_TO_35_2621_ETC__q276, - thin_otype__h858478, - thin_otype__h899114; + reg [22 : 0] CASE_guard02937_0b0_theResult___snd10960_BITS__ETC__q65, + CASE_guard02937_0b0_theResult___snd10960_BITS__ETC__q66, + CASE_guard22213_0b0_sfdin30306_BITS_56_TO_34_0_ETC__q96, + CASE_guard22213_0b0_sfdin30306_BITS_56_TO_34_0_ETC__q97, + CASE_guard30920_0b0_theResult___snd38919_BITS__ETC__q94, + CASE_guard30920_0b0_theResult___snd38919_BITS__ETC__q95, + CASE_guard39850_0b0_sfdin48072_BITS_56_TO_34_0_ETC__q98, + CASE_guard39850_0b0_sfdin48072_BITS_56_TO_34_0_ETC__q99, + CASE_guard48686_0b0_theResult___snd56709_BITS__ETC__q101, + CASE_guard48686_0b0_theResult___snd56709_BITS__ETC__q102, + CASE_guard67960_0b0_sfdin76053_BITS_56_TO_34_0_ETC__q131, + CASE_guard67960_0b0_sfdin76053_BITS_56_TO_34_0_ETC__q132, + CASE_guard76462_0b0_sfdin84557_BITS_56_TO_34_0_ETC__q61, + CASE_guard76462_0b0_sfdin84557_BITS_56_TO_34_0_ETC__q62, + CASE_guard76667_0b0_theResult___snd84666_BITS__ETC__q129, + CASE_guard76667_0b0_theResult___snd84666_BITS__ETC__q130, + CASE_guard85171_0b0_theResult___snd93170_BITS__ETC__q59, + CASE_guard85171_0b0_theResult___snd93170_BITS__ETC__q60, + CASE_guard85597_0b0_sfdin93819_BITS_56_TO_34_0_ETC__q133, + CASE_guard85597_0b0_sfdin93819_BITS_56_TO_34_0_ETC__q134, + CASE_guard94101_0b0_sfdin02323_BITS_56_TO_34_0_ETC__q63, + CASE_guard94101_0b0_sfdin02323_BITS_56_TO_34_0_ETC__q64, + CASE_guard94433_0b0_theResult___snd02456_BITS__ETC__q135, + CASE_guard94433_0b0_theResult___snd02456_BITS__ETC__q136, + _theResult___fst_sfd__h576435, + _theResult___fst_sfd__h585158, + _theResult___fst_sfd__h593740, + _theResult___fst_sfd__h602924, + _theResult___fst_sfd__h611560, + _theResult___fst_sfd__h622186, + _theResult___fst_sfd__h630907, + _theResult___fst_sfd__h639489, + _theResult___fst_sfd__h648673, + _theResult___fst_sfd__h657309, + _theResult___fst_sfd__h667933, + _theResult___fst_sfd__h676654, + _theResult___fst_sfd__h685236, + _theResult___fst_sfd__h694420, + _theResult___fst_sfd__h703056; + reg [17 : 0] CASE_csrf_mepcc_reg_data_rl_BITS_52_TO_35_2621_ETC__q279, + CASE_csrf_sepcc_reg_data_rl_BITS_52_TO_35_2621_ETC__q278, + thin_otype__h858477, + thin_otype__h899112; reg [15 : 0] SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1885, SEL_ARR_mmio_dataRespQ_data_0_389_BITS_15_TO_0_ETC___d2052; - reg [13 : 0] thin_addrBits__h858474, - thin_addrBits__h899110, - thin_bounds_baseBits__h860422, - thin_bounds_baseBits__h900516, - thin_bounds_topBits__h860421, - thin_bounds_topBits__h900515; - reg [12 : 0] CASE_coreFix_memExe_lsqfirstLd_BITS_15_TO_14__ETC__q339, - CASE_coreFix_memExe_lsqfirstSt_BITS_12_TO_11__ETC__q335, - CASE_robdeqPort_0_deq_data_BITS_273_TO_272_0__ETC__q326; - reg [11 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q350, - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_728_ETC__q290, - CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q344, - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q361, - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_728_ETC__q285, - CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q355, + reg [13 : 0] thin_addrBits__h858473, + thin_addrBits__h899108, + thin_bounds_baseBits__h860421, + thin_bounds_baseBits__h900514, + thin_bounds_topBits__h860420, + thin_bounds_topBits__h900513; + reg [12 : 0] CASE_coreFix_memExe_lsqfirstLd_BITS_15_TO_14__ETC__q341, + CASE_coreFix_memExe_lsqfirstSt_BITS_12_TO_11__ETC__q337, + CASE_robdeqPort_0_deq_data_BITS_273_TO_272_0__ETC__q328; + reg [11 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q352, + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_728_ETC__q292, + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q346, + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q363, + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_728_ETC__q287, + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q357, CASE_fetchStagepipelines_0_first_BITS_179_TO__ETC__q254, CASE_fetchStagepipelines_1_first_BITS_179_TO__ETC__q259; - reg [10 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_19_ETC__q349, - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_787_ETC__q289, - CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q343, - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_19_ETC__q360, - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_787_ETC__q284, - CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q354, + reg [10 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_19_ETC__q351, + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_787_ETC__q291, + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q345, + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_19_ETC__q362, + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_787_ETC__q286, + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q356, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q27, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q29, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q31, CASE_fetchStagepipelines_0_first_BITS_238_TO__ETC__q256, CASE_fetchStagepipelines_1_first_BITS_238_TO__ETC__q264, - CASE_guard04483_0b0_theResult___fst_exp12444_0_ETC__q172, - CASE_guard04483_0b0_theResult___fst_exp12444_0_ETC__q173, - CASE_guard13795_0b0_theResult___fst_exp22021_0_ETC__q201, - CASE_guard13795_0b0_theResult___fst_exp22021_0_ETC__q202, - CASE_guard22864_0b0_theResult___fst_exp30854_0_ETC__q203, - CASE_guard22864_0b0_theResult___fst_exp30854_0_ETC__q204, - CASE_guard26326_0b0_theResult___fst_exp34287_0_ETC__q155, - CASE_guard26326_0b0_theResult___fst_exp34287_0_ETC__q156, - CASE_guard35638_0b0_theResult___fst_exp43864_0_ETC__q223, - CASE_guard35638_0b0_theResult___fst_exp43864_0_ETC__q224, - CASE_guard44707_0b0_theResult___fst_exp52697_0_ETC__q225, - CASE_guard44707_0b0_theResult___fst_exp52697_0_ETC__q226, - CASE_guard65179_0b0_theResult___fst_exp73140_0_ETC__q195, - CASE_guard65179_0b0_theResult___fst_exp73140_0_ETC__q196, - CASE_guard74491_0b0_theResult___fst_exp82717_0_ETC__q199, - CASE_guard74491_0b0_theResult___fst_exp82717_0_ETC__q200, - CASE_guard83560_0b0_theResult___fst_exp91550_0_ETC__q197, - CASE_guard83560_0b0_theResult___fst_exp91550_0_ETC__q198, + CASE_guard04480_0b0_theResult___fst_exp12441_0_ETC__q172, + CASE_guard04480_0b0_theResult___fst_exp12441_0_ETC__q173, + CASE_guard13792_0b0_theResult___fst_exp22018_0_ETC__q203, + CASE_guard13792_0b0_theResult___fst_exp22018_0_ETC__q204, + CASE_guard22861_0b0_theResult___fst_exp30851_0_ETC__q201, + CASE_guard22861_0b0_theResult___fst_exp30851_0_ETC__q202, + CASE_guard26323_0b0_theResult___fst_exp34284_0_ETC__q155, + CASE_guard26323_0b0_theResult___fst_exp34284_0_ETC__q156, + CASE_guard35635_0b0_theResult___fst_exp43861_0_ETC__q223, + CASE_guard35635_0b0_theResult___fst_exp43861_0_ETC__q224, + CASE_guard44704_0b0_theResult___fst_exp52694_0_ETC__q227, + CASE_guard44704_0b0_theResult___fst_exp52694_0_ETC__q228, + CASE_guard65176_0b0_theResult___fst_exp73137_0_ETC__q195, + CASE_guard65176_0b0_theResult___fst_exp73137_0_ETC__q196, + CASE_guard74488_0b0_theResult___fst_exp82714_0_ETC__q197, + CASE_guard74488_0b0_theResult___fst_exp82714_0_ETC__q198, + CASE_guard83557_0b0_theResult___fst_exp91547_0_ETC__q199, + CASE_guard83557_0b0_theResult___fst_exp91547_0_ETC__q200, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13170, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13213, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13244, @@ -3920,79 +3921,79 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14655, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14693, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14724; - reg [7 : 0] CASE_guard02939_0b0_theResult___fst_exp11016_0_ETC__q57, - CASE_guard02939_0b0_theResult___fst_exp11016_0_ETC__q58, - CASE_guard22215_0b0_theResult___fst_exp30314_0_ETC__q81, - CASE_guard22215_0b0_theResult___fst_exp30314_0_ETC__q82, - CASE_guard30922_0b0_theResult___fst_exp38970_0_ETC__q79, - CASE_guard30922_0b0_theResult___fst_exp38970_0_ETC__q80, - CASE_guard39852_0b0_theResult___fst_exp48080_0_ETC__q87, - CASE_guard39852_0b0_theResult___fst_exp48080_0_ETC__q88, - CASE_guard48688_0b0_theResult___fst_exp56765_0_ETC__q92, - CASE_guard48688_0b0_theResult___fst_exp56765_0_ETC__q93, - CASE_guard67962_0b0_theResult___fst_exp76061_0_ETC__q116, - CASE_guard67962_0b0_theResult___fst_exp76061_0_ETC__q117, - CASE_guard76464_0b0_theResult___fst_exp84565_0_ETC__q46, - CASE_guard76464_0b0_theResult___fst_exp84565_0_ETC__q47, - CASE_guard76669_0b0_theResult___fst_exp84717_0_ETC__q114, - CASE_guard76669_0b0_theResult___fst_exp84717_0_ETC__q115, - CASE_guard85173_0b0_theResult___fst_exp93221_0_ETC__q44, - CASE_guard85173_0b0_theResult___fst_exp93221_0_ETC__q45, - CASE_guard85599_0b0_theResult___fst_exp93827_0_ETC__q122, - CASE_guard85599_0b0_theResult___fst_exp93827_0_ETC__q123, - CASE_guard94103_0b0_theResult___fst_exp02331_0_ETC__q52, - CASE_guard94103_0b0_theResult___fst_exp02331_0_ETC__q53, - CASE_guard94435_0b0_theResult___fst_exp02512_0_ETC__q127, - CASE_guard94435_0b0_theResult___fst_exp02512_0_ETC__q128, + reg [7 : 0] CASE_guard02937_0b0_theResult___fst_exp11014_0_ETC__q57, + CASE_guard02937_0b0_theResult___fst_exp11014_0_ETC__q58, + CASE_guard22213_0b0_theResult___fst_exp30312_0_ETC__q81, + CASE_guard22213_0b0_theResult___fst_exp30312_0_ETC__q82, + CASE_guard30920_0b0_theResult___fst_exp38968_0_ETC__q79, + CASE_guard30920_0b0_theResult___fst_exp38968_0_ETC__q80, + CASE_guard39850_0b0_theResult___fst_exp48078_0_ETC__q87, + CASE_guard39850_0b0_theResult___fst_exp48078_0_ETC__q88, + CASE_guard48686_0b0_theResult___fst_exp56763_0_ETC__q92, + CASE_guard48686_0b0_theResult___fst_exp56763_0_ETC__q93, + CASE_guard67960_0b0_theResult___fst_exp76059_0_ETC__q116, + CASE_guard67960_0b0_theResult___fst_exp76059_0_ETC__q117, + CASE_guard76462_0b0_theResult___fst_exp84563_0_ETC__q46, + CASE_guard76462_0b0_theResult___fst_exp84563_0_ETC__q47, + CASE_guard76667_0b0_theResult___fst_exp84715_0_ETC__q114, + CASE_guard76667_0b0_theResult___fst_exp84715_0_ETC__q115, + CASE_guard85171_0b0_theResult___fst_exp93219_0_ETC__q44, + CASE_guard85171_0b0_theResult___fst_exp93219_0_ETC__q45, + CASE_guard85597_0b0_theResult___fst_exp93825_0_ETC__q122, + CASE_guard85597_0b0_theResult___fst_exp93825_0_ETC__q123, + CASE_guard94101_0b0_theResult___fst_exp02329_0_ETC__q52, + CASE_guard94101_0b0_theResult___fst_exp02329_0_ETC__q53, + CASE_guard94433_0b0_theResult___fst_exp02510_0_ETC__q127, + CASE_guard94433_0b0_theResult___fst_exp02510_0_ETC__q128, SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1907, SEL_ARR_mmio_dataRespQ_data_0_389_BITS_7_TO_0__ETC___d2073, - _theResult___fst_exp__h576436, - _theResult___fst_exp__h585159, - _theResult___fst_exp__h593741, - _theResult___fst_exp__h602925, - _theResult___fst_exp__h611561, - _theResult___fst_exp__h622187, - _theResult___fst_exp__h630908, - _theResult___fst_exp__h639490, - _theResult___fst_exp__h648674, - _theResult___fst_exp__h657310, - _theResult___fst_exp__h667934, - _theResult___fst_exp__h676655, - _theResult___fst_exp__h685237, - _theResult___fst_exp__h694421, - _theResult___fst_exp__h703057; - reg [5 : 0] CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q340, + _theResult___fst_exp__h576434, + _theResult___fst_exp__h585157, + _theResult___fst_exp__h593739, + _theResult___fst_exp__h602923, + _theResult___fst_exp__h611559, + _theResult___fst_exp__h622185, + _theResult___fst_exp__h630906, + _theResult___fst_exp__h639488, + _theResult___fst_exp__h648672, + _theResult___fst_exp__h657308, + _theResult___fst_exp__h667932, + _theResult___fst_exp__h676653, + _theResult___fst_exp__h685235, + _theResult___fst_exp__h694419, + _theResult___fst_exp__h703055; + reg [5 : 0] CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q342, CASE_mmio_cRqQ_data_0_BITS_150_TO_149_0_mmio_c_ETC__q1, - CASE_mmio_dataReqQ_data_0_BITS_150_TO_149_0_mm_ETC__q331, - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012; - reg [4 : 0] CASE_basicExec_7743_BITS_270_TO_266_0_basicExe_ETC__q357, - CASE_basicExec_9859_BITS_270_TO_266_0_basicExe_ETC__q346, - CASE_capChecks_160_BITS_4_TO_0_0_capChecks_160_ETC__q292, + CASE_mmio_dataReqQ_data_0_BITS_150_TO_149_0_mm_ETC__q333, + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014; + reg [4 : 0] CASE_basicExec_7743_BITS_270_TO_266_0_basicExe_ETC__q359, + CASE_basicExec_9859_BITS_270_TO_266_0_basicExe_ETC__q348, + CASE_capChecks_160_BITS_4_TO_0_0_capChecks_160_ETC__q294, CASE_checkForException_0654_BITS_4_TO_0_0_chec_ETC__q257, CASE_commitStage_commitTrap_BITS_36_TO_32_0_co_ETC__q25, - CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_12_ETC__q351, - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_715_ETC__q291, - CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q345, - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_12_ETC__q362, - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_715_ETC__q286, - CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q356, - CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q337, - CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q338, - CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q333, - CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q334, + CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_12_ETC__q353, + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_715_ETC__q293, + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q347, + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_12_ETC__q364, + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_715_ETC__q288, + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q358, + CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q339, + CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q340, + CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q335, + CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q336, CASE_csrf_mccsr_reg_BITS_4_TO_0_0_csrf_mccsr_r_ETC__q24, - CASE_f_csr_reqsD_OUT_BITS_9_TO_5_0_f_csr_reqs_ETC__q329, + CASE_f_csr_reqsD_OUT_BITS_9_TO_5_0_f_csr_reqs_ETC__q331, CASE_fetchStagepipelines_0_first_BITS_166_TO__ETC__q253, CASE_fetchStagepipelines_1_first_BITS_166_TO__ETC__q263, - CASE_robdeqPort_0_deq_data_BITS_265_TO_261_0__ETC__q324, - CASE_robdeqPort_0_deq_data_BITS_265_TO_261_0__ETC__q325, - CASE_robdeqPort_0_deq_data_BITS_95_TO_326_BITS_ETC__q330, + CASE_robdeqPort_0_deq_data_BITS_265_TO_261_0__ETC__q326, + CASE_robdeqPort_0_deq_data_BITS_265_TO_261_0__ETC__q327, + CASE_robdeqPort_0_deq_data_BITS_95_TO_327_BITS_ETC__q332, IF_fetchStage_pipelines_0_first__0256_BITS_265_ETC___d22045, IF_fetchStage_pipelines_1_first__0265_BITS_265_ETC___d22190, - cause_code__h995320, - i__h995336, - t__h212841, - t__h215127; + cause_code__h995318, + i__h995334, + t__h212839, + t__h215125; reg [3 : 0] CASE_IF_coreFix_aluExe_0_dispToRegQ_first__838_ETC__q248, CASE_IF_coreFix_aluExe_0_regToExeQ_first__9457_ETC__q250, CASE_IF_coreFix_aluExe_0_rsAlu_dispatchData__8_ETC__q246, @@ -4002,9 +4003,9 @@ module mkCore(CLK, CASE_IF_fetchStage_pipelines_0_first__0256_BIT_ETC__q252, CASE_IF_fetchStage_pipelines_1_first__0265_BIT_ETC__q261, CASE_checkForException_0654_BITS_4_TO_0_0_0_1__ETC__q258, - CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q336, - CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q332, - CASE_robdeqPort_0_deq_data_BITS_264_TO_261_0__ETC__q323, + CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q338, + CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q334, + CASE_robdeqPort_0_deq_data_BITS_264_TO_261_0__ETC__q325, IF_checkForException_0654_BITS_3_TO_0_0907_EQ__ETC___d20927, IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d18527, IF_coreFix_aluExe_0_regToExeQ_first__9457_BITS_ETC___d19515, @@ -4017,10 +4018,10 @@ module mkCore(CLK, IF_fetchStage_pipelines_0_first__0256_BIT_69_0_ETC___d20812, IF_fetchStage_pipelines_1_first__0265_BITS_236_ETC___d21371, IF_fetchStage_pipelines_1_first__0265_BITS_265_ETC___d22191, - IF_rob_deqPort_0_deq_data__2261_BIT_294_3454_T_ETC___d23476, - i__h995510, - thin_perms_soft__h858713, - thin_perms_soft__h899289; + IF_rob_deqPort_0_deq_data__2261_BIT_294_3456_T_ETC___d23478, + i__h995534, + thin_perms_soft__h858712, + thin_perms_soft__h899287; reg [2 : 0] CASE_IF_coreFix_aluExe_0_dispToRegQ_first__838_ETC__q247, CASE_IF_coreFix_aluExe_0_regToExeQ_first__9457_ETC__q249, CASE_IF_coreFix_aluExe_0_rsAlu_dispatchData__8_ETC__q245, @@ -4029,16 +4030,16 @@ module mkCore(CLK, CASE_IF_coreFix_aluExe_1_rsAlu_dispatchData__5_ETC__q241, CASE_IF_fetchStage_pipelines_0_first__0256_BIT_ETC__q251, CASE_IF_fetchStage_pipelines_1_first__0265_BIT_ETC__q260, - CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_19_ETC__q347, - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_791_ETC__q287, - CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q341, - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_19_ETC__q358, - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_791_ETC__q282, - CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q352, - CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q367, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q281, - CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q363, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q318, + CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_19_ETC__q349, + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_791_ETC__q289, + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q343, + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_19_ETC__q360, + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_791_ETC__q284, + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q354, + CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q369, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q283, + CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q365, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q320, CASE_fetchStagepipelines_0_first_BITS_242_TO__ETC__q255, CASE_fetchStagepipelines_1_first_BITS_242_TO__ETC__q262, IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d18559, @@ -4050,16 +4051,18 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14868, IF_fetchStage_pipelines_0_first__0256_BITS_232_ETC___d20442, IF_fetchStage_pipelines_1_first__0265_BITS_232_ETC___d21403, - x__h501097, - x__h508765; - reg [1 : 0] CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q314, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q369, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q316, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q320, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q312, - thin_reserved__h858477, - thin_reserved__h899113; - reg CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q158, + x__h501096, + x__h508764; + reg [1 : 0] CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q316, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q371, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q318, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q322, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q314, + thin_reserved__h858476, + thin_reserved__h899111; + reg CASE_commitStage_commitTrap_BITS_44_TO_43_0_NO_ETC__q277, + CASE_commitStage_commitTrap_BITS_44_TO_43_0_cs_ETC__q276, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q158, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q160, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q162, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q175, @@ -4074,21 +4077,21 @@ module mkCore(CLK, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q212, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q214, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q216, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q305, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q315, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q321, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q322, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q307, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q317, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q323, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q324, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q37, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q38, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q39, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q317, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q278, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q279, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q319, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q280, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q308, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q313, - CASE_coreFix_memExe_forwardQ_deqP_0_coreFix_me_ETC__q328, - CASE_coreFix_memExe_memRespLdQ_deqP_0_coreFix__ETC__q327, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q281, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q282, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q310, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q315, + CASE_coreFix_memExe_forwardQ_deqP_0_coreFix_me_ETC__q329, + CASE_coreFix_memExe_memRespLdQ_deqP_0_coreFix__ETC__q330, CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q274, CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q275, CASE_fetchStage_pipelines_0_canDeq__0254_AND_N_ETC__q270, @@ -4099,46 +4102,46 @@ module mkCore(CLK, CASE_fetchStagepipelines_1_first_BITS_265_TO__ETC__q267, CASE_fetchStagepipelines_1_first_BITS_265_TO__ETC__q271, CASE_fetchStagepipelines_1_first_BITS_268_TO__ETC__q273, - CASE_guard02939_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q74, - CASE_guard02939_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q73, - CASE_guard04483_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q184, - CASE_guard04483_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q174, - CASE_guard13795_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q180, - CASE_guard13795_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q176, - CASE_guard22215_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q103, - CASE_guard22215_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q102, - CASE_guard22864_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q182, - CASE_guard22864_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q178, - CASE_guard26326_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q157, - CASE_guard30922_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q105, - CASE_guard30922_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q104, - CASE_guard35638_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q159, - CASE_guard39852_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q107, - CASE_guard39852_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q106, - CASE_guard44707_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q161, - CASE_guard48688_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q109, - CASE_guard48688_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q108, - CASE_guard65179_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q215, - CASE_guard65179_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q205, - CASE_guard67962_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q139, - CASE_guard67962_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q137, - CASE_guard74491_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q211, - CASE_guard74491_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q207, - CASE_guard76464_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q68, - CASE_guard76464_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q65, - CASE_guard76669_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q140, - CASE_guard76669_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q138, - CASE_guard83560_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q213, - CASE_guard83560_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q209, - CASE_guard85173_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q70, - CASE_guard85173_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q69, - CASE_guard85599_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q142, - CASE_guard85599_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q141, - CASE_guard94103_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q72, - CASE_guard94103_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q71, - CASE_guard94435_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q144, - CASE_guard94435_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q143, - CASE_k45030_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q268, + CASE_guard02937_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q74, + CASE_guard02937_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q73, + CASE_guard04480_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q184, + CASE_guard04480_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q176, + CASE_guard13792_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q180, + CASE_guard13792_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q174, + CASE_guard22213_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q103, + CASE_guard22213_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q100, + CASE_guard22861_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q182, + CASE_guard22861_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q178, + CASE_guard26323_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q157, + CASE_guard30920_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q105, + CASE_guard30920_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q104, + CASE_guard35635_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q159, + CASE_guard39850_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q107, + CASE_guard39850_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q106, + CASE_guard44704_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q161, + CASE_guard48686_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q109, + CASE_guard48686_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q108, + CASE_guard65176_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q215, + CASE_guard65176_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q205, + CASE_guard67960_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q138, + CASE_guard67960_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q137, + CASE_guard74488_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q211, + CASE_guard74488_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q207, + CASE_guard76462_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q68, + CASE_guard76462_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q67, + CASE_guard76667_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q140, + CASE_guard76667_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q139, + CASE_guard83557_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q213, + CASE_guard83557_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q209, + CASE_guard85171_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q70, + CASE_guard85171_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q69, + CASE_guard85597_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q142, + CASE_guard85597_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q141, + CASE_guard94101_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q72, + CASE_guard94101_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q71, + CASE_guard94433_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q144, + CASE_guard94433_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q143, + CASE_k45028_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q268, IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19204, IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19240, IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19249, @@ -4243,12 +4246,12 @@ module mkCore(CLK, wire [515 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5171, IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d5172, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d7137, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d24448; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d24450; wire [511 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d4943; wire [457 : 0] coreFix_memExe_lsq_getOrigBE_coreFix_memExe_re_ETC___d4250; wire [383 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5169, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d7127, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d24438; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d24440; wire [294 : 0] fetchStage_pipelines_0_first__0256_BIT_167_059_ETC___d21145; wire [278 : 0] IF_coreFix_memExe_lsq_getOrigBE_coreFix_memExe_ETC___d4249; wire [265 : 0] prepareBoundsCheck___d4244; @@ -4269,27 +4272,27 @@ module mkCore(CLK, IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d5560; wire [128 : 0] amoExec___d4922, amoExec___d773, - new_pc__h872925, - new_pc__h912073, - next_pc__h1012222, - pc__h963242, - v__h1012261, - v__h1012970, - x__h879903, - x__h914620; + new_pc__h872924, + new_pc__h912071, + next_pc__h1012257, + pc__h963240, + v__h1012296, + v__h1013005, + x__h879902, + x__h914618; wire [127 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5165, SEXT_SEL_ARR_SEL_ARR_coreFix_memExe_dMem_cache_ETC___d4881, SEXT_SEL_ARR_SEL_ARR_coreFix_memExe_dMem_cache_ETC___d4889, coreFix_memExe_regToExeQ_first__645_BITS_140_T_ETC___d4070, - x__h183399, - x__h199251; + x__h183397, + x__h199249; wire [109 : 0] IF_fetchStage_pipelines_0_first__0256_BITS_238_ETC___d20622, IF_fetchStage_pipelines_1_first__0265_BITS_238_ETC___d21583; wire [85 : 0] IF_coreFix_memExe_dispToRegQ_first__686_BIT_10_ETC___d3580; wire [71 : 0] IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19395, IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d17261, - IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d23335, - IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d23198; + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d23337, + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d23200; wire [68 : 0] execFpuSimple___d15207; wire [66 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d7036; wire [65 : 0] IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__840_ETC___d18813, @@ -4308,91 +4311,91 @@ module mkCore(CLK, IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16423, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3048, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3417, - addTop__h239973, - addTop__h241130, - addTop__h254754, - address__h1000151, - address__h1000495, - address__h999494, - address__h999838, + addTop__h239970, + addTop__h241127, + addTop__h254751, + address__h1000186, + address__h1000530, + address__h999529, + address__h999873, coreFix_memExe_dTlb_procResp__257_BITS_452_TO__ETC___d4407, coreFix_memExe_regToExeQ_first__645_BITS_220_T_ETC___d3766, coreFix_memExe_regToExeQ_first__645_BITS_383_T_ETC___d3704, - cr_address__h866671, - cr_address__h867219, - cr_address__h906357, - cr_address__h906905, - data_address__h1018717, - data_address__h1019571, - in__h239804, - in__h240961, - in__h254585, - in__h854154, - in__h854459, - in__h855147, - in__h855451, - in__h855977, - in__h997656, - pc_address__h994739, - pointer__h242638, - res_address__h126822, - res_address__h139734, - res_address__h178898, - res_address__h197663, - res_address__h216422, - res_address__h235323, - res_address__h567346, - res_address__h568198, - res_address__h613955, - res_address__h659702, - res_address__h705511, - res_address__h706371, - res_address__h848644, - res_address__h892145, - result__h240600, - result__h241757, - result__h255381, - result_d_address__h1008566, - result_d_address__h1008969, - result_d_address__h1009386, - result_d_address__h1009789, - result_d_address__h1010458, - result_d_address__h1031617, - result_d_address__h1032020, - result_d_address__h1032437, - result_d_address__h1032840, - result_d_address__h1033507, - result_d_address__h242849, - ret__h239977, - ret__h241134, - ret__h254758, - x__h1000345, - x__h1000649, - x__h235746, - x__h239822, - x__h239970, - x__h240979, - x__h241127, - x__h248120, - x__h254603, - x__h254751, - x__h854172, - x__h854477, - x__h855165, - x__h855469, - x__h855995, - x__h997674, - x__h999688, - x__h999992, - y__h239821, - y__h240978, - y__h254602, - y__h854171, - y__h854476, - y__h855164, - y__h855468, - y__h855994, - y__h997673; + cr_address__h866670, + cr_address__h867218, + cr_address__h906355, + cr_address__h906903, + data_address__h1018751, + data_address__h1019605, + in__h239801, + in__h240958, + in__h254582, + in__h854153, + in__h854458, + in__h855146, + in__h855450, + in__h855976, + in__h997691, + pc_address__h994737, + pointer__h242635, + res_address__h126821, + res_address__h139733, + res_address__h178896, + res_address__h197661, + res_address__h216420, + res_address__h235320, + res_address__h567343, + res_address__h568196, + res_address__h613953, + res_address__h659700, + res_address__h705509, + res_address__h706369, + res_address__h848642, + res_address__h892144, + result__h240597, + result__h241754, + result__h255378, + result_d_address__h1008601, + result_d_address__h1009004, + result_d_address__h1009421, + result_d_address__h1009824, + result_d_address__h1010493, + result_d_address__h1031651, + result_d_address__h1032054, + result_d_address__h1032471, + result_d_address__h1032874, + result_d_address__h1033541, + result_d_address__h242846, + ret__h239974, + ret__h241131, + ret__h254755, + x__h1000027, + x__h1000380, + x__h1000684, + x__h235743, + x__h239819, + x__h239967, + x__h240976, + x__h241124, + x__h248117, + x__h254600, + x__h254748, + x__h854171, + x__h854476, + x__h855164, + x__h855468, + x__h855994, + x__h997709, + x__h999723, + y__h239818, + y__h240975, + y__h254599, + y__h854170, + y__h854475, + y__h855163, + y__h855467, + y__h855993, + y__h997708; wire [63 : 0] IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13324, IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12485, IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12486, @@ -4412,214 +4415,214 @@ module mkCore(CLK, IF_coreFix_memExe_lsq_firstLd__498_BIT_113_513_ETC___d2078, IF_coreFix_memExe_lsq_firstLd__498_BIT_117_521_ETC___d1913, IF_coreFix_memExe_lsq_firstLd__498_BIT_117_521_ETC___d2079, - IF_csrf_mtcc_reg_read__6198_BIT_86_2807_AND_NO_ETC___d22905, - IF_csrf_stcc_reg_read__6046_BIT_86_2736_AND_NO_ETC___d22904, - IF_rob_deqPort_0_canDeq__3598_THEN_IF_NOT_rob__ETC___d23719, - SEXT__0_CONCAT_IF_INV_commitStage_commitTrap_2_ETC___d22677, + IF_csrf_mtcc_reg_read__6198_BIT_86_2809_AND_NO_ETC___d22907, + IF_csrf_stcc_reg_read__6046_BIT_86_2738_AND_NO_ETC___d22906, + IF_rob_deqPort_0_canDeq__3600_THEN_IF_NOT_rob__ETC___d23721, + SEXT__0_CONCAT_IF_INV_commitStage_commitTrap_2_ETC___d22678, SEXT__0_CONCAT_IF_csrf_mepcc_reg_data_lat_0_wh_ETC___d16261, SEXT__0_CONCAT_IF_csrf_sepcc_reg_data_lat_0_wh_ETC___d16109, SEXT__0_CONCAT_csrf_mtcc_reg_read__6198_BITS_8_ETC___d16222, SEXT__0_CONCAT_csrf_rg_dpc_read__6343_BITS_85__ETC___d16367, SEXT__0_CONCAT_csrf_stcc_reg_read__6046_BITS_8_ETC___d16070, - _18446744073709551615_SL_csrf_mtcc_reg_read__61_ETC___d22824, - _18446744073709551615_SL_csrf_stcc_reg_read__60_ETC___d22755, - _theResult___fst__h836129, - _theResult___snd__h836130, - a___1__h835848, - a___1__h836134, - a__h835707, - addBase__h1008585, - addBase__h1008988, - addBase__h1009405, - addBase__h1009808, - addBase__h1010478, - addBase__h239864, - addBase__h241021, - addBase__h254645, - addr__h148439, - addr__h152015, - addr__h235317, - addr__h989736, - address__h1013682, - address__h999428, - address__h999478, - b___1__h835849, - b___1__h836179, - b__h835708, - base__h999389, - base__h999443, - bot__h1008588, - bot__h1008991, - bot__h1009408, - bot__h1009811, - bot__h1010481, - csrf_mtcc_reg_read__6198_BITS_149_TO_86_2811_A_ETC___d22814, - csrf_stcc_reg_read__6046_BITS_149_TO_86_2740_A_ETC___d22743, - data___1__h705533, - data___1__h706393, - data__h567680, - data__h613440, - data__h659187, - data__h705001, - data__h705833, - data__h705864, - fcsr_csr__read__h849219, - fflags_csr__read__h849194, - frm_csr__read__h849205, - mask__h1000157, - mask__h999500, - mcause_csr__read__h850886, - mcounteren_csr__read__h850620, - medeleg_csr__read__h850223, - mideleg_csr__read__h850321, - mie_csr__read__h850448, - mip_csr__read__h851125, - mstatus_csr__read__h850062, - n__read__h1014112, + _18446744073709551615_SL_csrf_mtcc_reg_read__61_ETC___d22826, + _18446744073709551615_SL_csrf_stcc_reg_read__60_ETC___d22757, + _theResult___fst__h836126, + _theResult___snd__h836127, + a___1__h835845, + a___1__h836131, + a__h835704, + addBase__h1008620, + addBase__h1009023, + addBase__h1009440, + addBase__h1009843, + addBase__h1010513, + addBase__h239861, + addBase__h241018, + addBase__h254642, + addr__h148438, + addr__h152014, + addr__h235314, + addr__h989734, + address__h1013717, + address__h999463, + address__h999513, + b___1__h835846, + b___1__h836176, + b__h835705, + base__h999424, + base__h999478, + bot__h1008623, + bot__h1009026, + bot__h1009443, + bot__h1009846, + bot__h1010516, + csrf_mtcc_reg_read__6198_BITS_149_TO_86_2813_A_ETC___d22816, + csrf_stcc_reg_read__6046_BITS_149_TO_86_2742_A_ETC___d22745, + data___1__h705531, + data___1__h706391, + data__h567678, + data__h613438, + data__h659185, + data__h704999, + data__h705831, + data__h705862, + fcsr_csr__read__h849218, + fflags_csr__read__h849193, + frm_csr__read__h849204, + mask__h1000192, + mask__h999535, + mcause_csr__read__h850885, + mcounteren_csr__read__h850619, + medeleg_csr__read__h850222, + mideleg_csr__read__h850320, + mie_csr__read__h850447, + mip_csr__read__h851124, + mstatus_csr__read__h850061, + n__read__h1014147, n__read__h7908, - newAddrDiff__h1000158, - newAddrDiff__h1000502, - newAddrDiff__h999501, - newAddrDiff__h999845, - offset__h242628, - q___1__h706458, - rVal1__h714520, - rVal2__h714521, - r___1__h706484, - res_data__h568238, - res_data__h568243, - res_data__h613992, - res_data__h613997, - res_data__h659739, - res_data__h659744, - resp_addr__h509111, - rg_tdata1__read__h852226, - robdeqPort_0_deq_data_BITS_95_TO_32__q16, - satp_csr__read__h849916, - scause_csr__read__h849713, - scounteren_csr__read__h849573, - sie_csr__read__h849485, - sip_csr__read__h849853, - sstatus_csr__read__h849415, - thin_address__h999382, - tmpAddr__h242837, - trap_val__h997040, - upd__h1014188, + newAddrDiff__h1000193, + newAddrDiff__h1000537, + newAddrDiff__h999536, + newAddrDiff__h999880, + offset__h242625, + q___1__h706456, + rVal1__h714517, + rVal2__h714518, + r___1__h706482, + res_data__h568236, + res_data__h568241, + res_data__h613990, + res_data__h613995, + res_data__h659737, + res_data__h659742, + resp_addr__h509110, + rg_tdata1__read__h852225, + robdeqPort_0_deq_data_BITS_95_TO_32__q17, + satp_csr__read__h849915, + scause_csr__read__h849712, + scounteren_csr__read__h849572, + sie_csr__read__h849484, + sip_csr__read__h849852, + sstatus_csr__read__h849414, + thin_address__h999417, + tmpAddr__h242834, + trap_val__h997075, + upd__h1014223, upd__h3066, upd__h3676, upd__h7977, - value__h239694, - value__h239858, - value__h240851, - value__h241015, - value__h254475, - value__h254639, - x__h1008496, - x__h1008899, - x__h1009316, - x__h1009719, - x__h1010388, - x__h1031547, - x__h1031950, - x__h1032367, - x__h1032770, - x__h1033437, - x__h127303, - x__h140219, - x__h183481, - x__h202232, - x__h216798, - x__h239712, - x__h239714, - x__h240869, - x__h240871, - x__h242777, - x__h254493, - x__h254495, - x__h714429, - x__h714430, - x__h714431, - x__h854233, - x__h854235, - x__h855226, - x__h855228, - x__h866848, - x__h867396, + value__h239691, + value__h239855, + value__h240848, + value__h241012, + value__h254472, + value__h254636, + x__h1008531, + x__h1008934, + x__h1009351, + x__h1009754, + x__h1010423, + x__h1031581, + x__h1031984, + x__h1032401, + x__h1032804, + x__h1033471, + x__h127302, + x__h140218, + x__h183479, + x__h202230, + x__h216796, + x__h239709, + x__h239711, + x__h240866, + x__h240868, + x__h242774, + x__h254490, + x__h254492, + x__h714426, + x__h714427, + x__h714428, + x__h854232, + x__h854234, + x__h855225, + x__h855227, + x__h866847, + x__h867395, + x__h895986, x__h895988, - x__h895990, + x__h896270, x__h896272, - x__h896274, + x__h896615, x__h896617, - x__h896619, - x__h906534, - x__h907082, - x__h994911, - x__h997587, - x__h997589, + x__h906532, + x__h907080, + x__h994909, + x__h997622, + x__h997624, x_addr__h19883, x_addr__h44252, - x_addr__h535374, - x_quotient__h705747, - x_reg_ifc__read__h849324, - x_remainder__h705748, - y__h1000274, - y__h1016339, - y__h999617, - y_avValue__h710475, - y_avValue__h711108, - y_avValue__h711735, - y_avValue_snd_snd_snd_snd_snd__h1015810, - y_avValue_snd_snd_snd_snd_snd__h1016392, - y_avValue_snd_snd_snd_snd_snd__h1016421; + x_addr__h535372, + x_quotient__h705745, + x_reg_ifc__read__h849323, + x_remainder__h705746, + y__h1000309, + y__h1016374, + y__h999652, + y_avValue__h710472, + y_avValue__h711105, + y_avValue__h711732, + y_avValue_snd_snd_snd_snd_snd__h1015845, + y_avValue_snd_snd_snd_snd_snd__h1016427, + y_avValue_snd_snd_snd_snd_snd__h1016456; wire [62 : 0] IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14033, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14803, - r1__read__h853107, - r1__read__h853511, - r1__read__h854204, - r1__read__h854516, - r1__read__h854749, - r1__read__h854921, - r1__read__h855197, - r1__read__h855508; - wire [61 : 0] r1__read__h853109, - r1__read__h853513, - r1__read__h854206, - r1__read__h854518, - r1__read__h854751, - r1__read__h854897, - r1__read__h854923, - r1__read__h855199, - r1__read__h855510; - wire [60 : 0] r1__read__h854753, - r1__read__h854899, - r1__read__h854925, - r1__read__h855512; - wire [59 : 0] r1__read__h853111, - r1__read__h853515, - r1__read__h854520, - r1__read__h854755, - r1__read__h854927, - r1__read__h855514; + r1__read__h853106, + r1__read__h853510, + r1__read__h854203, + r1__read__h854515, + r1__read__h854748, + r1__read__h854920, + r1__read__h855196, + r1__read__h855507; + wire [61 : 0] r1__read__h853108, + r1__read__h853512, + r1__read__h854205, + r1__read__h854517, + r1__read__h854750, + r1__read__h854896, + r1__read__h854922, + r1__read__h855198, + r1__read__h855509; + wire [60 : 0] r1__read__h854752, + r1__read__h854898, + r1__read__h854924, + r1__read__h855511; + wire [59 : 0] r1__read__h853110, + r1__read__h853514, + r1__read__h854519, + r1__read__h854754, + r1__read__h854926, + r1__read__h855513; wire [58 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5496, IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5538, IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d6974, - r1__read__h853113, - r1__read__h853517, - r1__read__h854509, - r1__read__h854522, - r1__read__h854757, - r1__read__h854929, - r1__read__h855501, - r1__read__h855516; + r1__read__h853112, + r1__read__h853516, + r1__read__h854508, + r1__read__h854521, + r1__read__h854756, + r1__read__h854928, + r1__read__h855500, + r1__read__h855515; wire [57 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d7211, - r1__read__h853115, - r1__read__h853519, - r1__read__h854524, - r1__read__h854759, - r1__read__h854901, - r1__read__h854931, - r1__read__h855518, - y__h422565; + r1__read__h853114, + r1__read__h853518, + r1__read__h854523, + r1__read__h854758, + r1__read__h854900, + r1__read__h854930, + r1__read__h855517, + y__h422564; wire [56 : 0] IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q110, IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q40, IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q75, @@ -4647,195 +4650,195 @@ module mkCore(CLK, _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d10078, _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d11475, _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d8681, - _theResult____h576454, - _theResult____h594093, - _theResult____h622205, - _theResult____h639842, - _theResult____h667952, - _theResult____h685589, - _theResult____h735628, - _theResult____h774481, - _theResult____h813785, - _theResult___snd__h584576, + _theResult____h576452, + _theResult____h594091, + _theResult____h622203, + _theResult____h639840, + _theResult____h667950, + _theResult____h685587, + _theResult____h735625, + _theResult____h774478, + _theResult____h813782, + _theResult___snd__h584574, + _theResult___snd__h584585, _theResult___snd__h584587, - _theResult___snd__h584589, - _theResult___snd__h584599, - _theResult___snd__h584605, - _theResult___snd__h584628, + _theResult___snd__h584597, + _theResult___snd__h584603, + _theResult___snd__h584626, + _theResult___snd__h593170, _theResult___snd__h593172, - _theResult___snd__h593174, - _theResult___snd__h593181, - _theResult___snd__h593187, - _theResult___snd__h593210, - _theResult___snd__h602342, + _theResult___snd__h593179, + _theResult___snd__h593185, + _theResult___snd__h593208, + _theResult___snd__h602340, + _theResult___snd__h602351, _theResult___snd__h602353, - _theResult___snd__h602355, - _theResult___snd__h602365, - _theResult___snd__h602371, - _theResult___snd__h602394, - _theResult___snd__h610962, - _theResult___snd__h610976, - _theResult___snd__h610982, - _theResult___snd__h611000, - _theResult___snd__h630325, + _theResult___snd__h602363, + _theResult___snd__h602369, + _theResult___snd__h602392, + _theResult___snd__h610960, + _theResult___snd__h610974, + _theResult___snd__h610980, + _theResult___snd__h610998, + _theResult___snd__h630323, + _theResult___snd__h630334, _theResult___snd__h630336, - _theResult___snd__h630338, - _theResult___snd__h630348, - _theResult___snd__h630354, - _theResult___snd__h630377, + _theResult___snd__h630346, + _theResult___snd__h630352, + _theResult___snd__h630375, + _theResult___snd__h638919, _theResult___snd__h638921, - _theResult___snd__h638923, - _theResult___snd__h638930, - _theResult___snd__h638936, - _theResult___snd__h638959, - _theResult___snd__h648091, + _theResult___snd__h638928, + _theResult___snd__h638934, + _theResult___snd__h638957, + _theResult___snd__h648089, + _theResult___snd__h648100, _theResult___snd__h648102, - _theResult___snd__h648104, - _theResult___snd__h648114, - _theResult___snd__h648120, - _theResult___snd__h648143, - _theResult___snd__h656711, - _theResult___snd__h656725, - _theResult___snd__h656731, - _theResult___snd__h656749, - _theResult___snd__h676072, + _theResult___snd__h648112, + _theResult___snd__h648118, + _theResult___snd__h648141, + _theResult___snd__h656709, + _theResult___snd__h656723, + _theResult___snd__h656729, + _theResult___snd__h656747, + _theResult___snd__h676070, + _theResult___snd__h676081, _theResult___snd__h676083, - _theResult___snd__h676085, - _theResult___snd__h676095, - _theResult___snd__h676101, - _theResult___snd__h676124, + _theResult___snd__h676093, + _theResult___snd__h676099, + _theResult___snd__h676122, + _theResult___snd__h684666, _theResult___snd__h684668, - _theResult___snd__h684670, - _theResult___snd__h684677, - _theResult___snd__h684683, - _theResult___snd__h684706, - _theResult___snd__h693838, + _theResult___snd__h684675, + _theResult___snd__h684681, + _theResult___snd__h684704, + _theResult___snd__h693836, + _theResult___snd__h693847, _theResult___snd__h693849, - _theResult___snd__h693851, - _theResult___snd__h693861, - _theResult___snd__h693867, - _theResult___snd__h693890, - _theResult___snd__h702458, - _theResult___snd__h702472, - _theResult___snd__h702478, - _theResult___snd__h702496, - _theResult___snd__h734238, - _theResult___snd__h734240, - _theResult___snd__h734247, - _theResult___snd__h734253, - _theResult___snd__h734276, - _theResult___snd__h743875, - _theResult___snd__h743886, - _theResult___snd__h743888, - _theResult___snd__h743898, - _theResult___snd__h743904, - _theResult___snd__h743927, - _theResult___snd__h752643, - _theResult___snd__h752657, - _theResult___snd__h752663, - _theResult___snd__h752681, - _theResult___snd__h773091, - _theResult___snd__h773093, - _theResult___snd__h773100, - _theResult___snd__h773106, - _theResult___snd__h773129, - _theResult___snd__h782728, - _theResult___snd__h782739, - _theResult___snd__h782741, - _theResult___snd__h782751, - _theResult___snd__h782757, - _theResult___snd__h782780, - _theResult___snd__h791496, - _theResult___snd__h791510, - _theResult___snd__h791516, - _theResult___snd__h791534, - _theResult___snd__h812395, - _theResult___snd__h812397, - _theResult___snd__h812404, - _theResult___snd__h812410, - _theResult___snd__h812433, - _theResult___snd__h822032, - _theResult___snd__h822043, - _theResult___snd__h822045, - _theResult___snd__h822055, - _theResult___snd__h822061, - _theResult___snd__h822084, - _theResult___snd__h830800, - _theResult___snd__h830814, - _theResult___snd__h830820, - _theResult___snd__h830838, - r1__read__h854761, - r1__read__h854903, - r1__read__h854933, - r1__read__h855520, - result__h594706, - result__h640455, - result__h686202, - result__h736241, - result__h775094, - result__h814398, - sfd__h568849, - sfd__h614603, - sfd__h660350, - sfd__h715261, - sfd__h754255, - sfd__h793559, - sfdin__h584559, - sfdin__h602325, - sfdin__h630308, - sfdin__h648074, - sfdin__h676055, - sfdin__h693821, - sfdin__h743858, - sfdin__h782711, - sfdin__h822015, - x__h594803, - x__h640552, - x__h686299, - x__h736336, - x__h775189, - x__h814493; + _theResult___snd__h693859, + _theResult___snd__h693865, + _theResult___snd__h693888, + _theResult___snd__h702456, + _theResult___snd__h702470, + _theResult___snd__h702476, + _theResult___snd__h702494, + _theResult___snd__h734235, + _theResult___snd__h734237, + _theResult___snd__h734244, + _theResult___snd__h734250, + _theResult___snd__h734273, + _theResult___snd__h743872, + _theResult___snd__h743883, + _theResult___snd__h743885, + _theResult___snd__h743895, + _theResult___snd__h743901, + _theResult___snd__h743924, + _theResult___snd__h752640, + _theResult___snd__h752654, + _theResult___snd__h752660, + _theResult___snd__h752678, + _theResult___snd__h773088, + _theResult___snd__h773090, + _theResult___snd__h773097, + _theResult___snd__h773103, + _theResult___snd__h773126, + _theResult___snd__h782725, + _theResult___snd__h782736, + _theResult___snd__h782738, + _theResult___snd__h782748, + _theResult___snd__h782754, + _theResult___snd__h782777, + _theResult___snd__h791493, + _theResult___snd__h791507, + _theResult___snd__h791513, + _theResult___snd__h791531, + _theResult___snd__h812392, + _theResult___snd__h812394, + _theResult___snd__h812401, + _theResult___snd__h812407, + _theResult___snd__h812430, + _theResult___snd__h822029, + _theResult___snd__h822040, + _theResult___snd__h822042, + _theResult___snd__h822052, + _theResult___snd__h822058, + _theResult___snd__h822081, + _theResult___snd__h830797, + _theResult___snd__h830811, + _theResult___snd__h830817, + _theResult___snd__h830835, + r1__read__h854760, + r1__read__h854902, + r1__read__h854932, + r1__read__h855519, + result__h594704, + result__h640453, + result__h686200, + result__h736238, + result__h775091, + result__h814395, + sfd__h568847, + sfd__h614601, + sfd__h660348, + sfd__h715258, + sfd__h754252, + sfd__h793556, + sfdin__h584557, + sfdin__h602323, + sfdin__h630306, + sfdin__h648072, + sfdin__h676053, + sfdin__h693819, + sfdin__h743855, + sfdin__h782708, + sfdin__h822012, + x__h594801, + x__h640550, + x__h686297, + x__h736333, + x__h775186, + x__h814490; wire [55 : 0] coreFix_memExe_dispToRegQ_first__686_BIT_102_6_ETC___d3579, - r1__read__h853117, - r1__read__h853521, - r1__read__h854526, - r1__read__h854763, - r1__read__h854935, - r1__read__h855522; + r1__read__h853116, + r1__read__h853520, + r1__read__h854525, + r1__read__h854762, + r1__read__h854934, + r1__read__h855521; wire [54 : 0] IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19394, IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d17260, - r1__read__h853119, - r1__read__h853523, - r1__read__h854528, - r1__read__h854765, - r1__read__h854937, - r1__read__h855524; - wire [53 : 0] r1__read__h854874, - r1__read__h854905, - r1__read__h854939, - r1__read__h855526, - sfd__h734305, - sfd__h743956, - sfd__h752716, - sfd__h773158, - sfd__h782809, - sfd__h791569, - sfd__h812462, - sfd__h822113, - sfd__h830873, - value__h577076, - value__h622825, - value__h668572; + r1__read__h853118, + r1__read__h853522, + r1__read__h854527, + r1__read__h854764, + r1__read__h854936, + r1__read__h855523; + wire [53 : 0] r1__read__h854873, + r1__read__h854904, + r1__read__h854938, + r1__read__h855525, + sfd__h734302, + sfd__h743953, + sfd__h752713, + sfd__h773155, + sfd__h782806, + sfd__h791566, + sfd__h812459, + sfd__h822110, + sfd__h830870, + value__h577074, + value__h622823, + value__h668570; wire [52 : 0] IF_coreFix_memExe_dispToRegQ_first__686_BIT_10_ETC___d3578, INV_coreFix_aluExe_0_regToExeQ_first__9457_BIT_ETC___d19771, INV_coreFix_aluExe_0_regToExeQ_first__9457_BIT_ETC___d19835, INV_coreFix_aluExe_1_regToExeQ_first__7341_BIT_ETC___d17655, INV_coreFix_aluExe_1_regToExeQ_first__7341_BIT_ETC___d17719, - r1__read__h854767, - r1__read__h854876, - r1__read__h854907, - r1__read__h854941, - r1__read__h855528; + r1__read__h854766, + r1__read__h854875, + r1__read__h854906, + r1__read__h854940, + r1__read__h855527; wire [51 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13291, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13293, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14000, @@ -4857,107 +4860,107 @@ module mkCore(CLK, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13323, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14032, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14802, - _theResult___fst_sfd__h719215, + _theResult___fst_sfd__h719212, + _theResult___fst_sfd__h735040, _theResult___fst_sfd__h735043, - _theResult___fst_sfd__h735046, + _theResult___fst_sfd__h744691, _theResult___fst_sfd__h744694, - _theResult___fst_sfd__h744697, + _theResult___fst_sfd__h753475, _theResult___fst_sfd__h753478, - _theResult___fst_sfd__h753481, - _theResult___fst_sfd__h753490, - _theResult___fst_sfd__h753496, - _theResult___fst_sfd__h758068, + _theResult___fst_sfd__h753487, + _theResult___fst_sfd__h753493, + _theResult___fst_sfd__h758065, + _theResult___fst_sfd__h773893, _theResult___fst_sfd__h773896, - _theResult___fst_sfd__h773899, + _theResult___fst_sfd__h783544, _theResult___fst_sfd__h783547, - _theResult___fst_sfd__h783550, + _theResult___fst_sfd__h792328, _theResult___fst_sfd__h792331, - _theResult___fst_sfd__h792334, - _theResult___fst_sfd__h792343, - _theResult___fst_sfd__h792349, - _theResult___fst_sfd__h797372, + _theResult___fst_sfd__h792340, + _theResult___fst_sfd__h792346, + _theResult___fst_sfd__h797369, + _theResult___fst_sfd__h813197, _theResult___fst_sfd__h813200, - _theResult___fst_sfd__h813203, + _theResult___fst_sfd__h822848, _theResult___fst_sfd__h822851, - _theResult___fst_sfd__h822854, + _theResult___fst_sfd__h831632, _theResult___fst_sfd__h831635, - _theResult___fst_sfd__h831638, - _theResult___fst_sfd__h831647, - _theResult___fst_sfd__h831653, - _theResult___sfd__h734943, - _theResult___sfd__h744594, - _theResult___sfd__h753378, - _theResult___sfd__h773796, - _theResult___sfd__h783447, - _theResult___sfd__h792231, - _theResult___sfd__h813100, - _theResult___sfd__h822751, - _theResult___sfd__h831535, - _theResult___snd_fst_sfd__h715215, - _theResult___snd_fst_sfd__h735049, - _theResult___snd_fst_sfd__h753484, - _theResult___snd_fst_sfd__h754209, - _theResult___snd_fst_sfd__h773902, - _theResult___snd_fst_sfd__h792337, - _theResult___snd_fst_sfd__h793513, - _theResult___snd_fst_sfd__h813206, - _theResult___snd_fst_sfd__h831641, - mask__h239974, - mask__h241131, - mask__h254755, - out___1_sfd__h714963, - out___1_sfd__h753957, - out___1_sfd__h793261, - out_sfd__h734946, - out_sfd__h744597, - out_sfd__h753381, - out_sfd__h773799, - out_sfd__h783450, - out_sfd__h792234, - out_sfd__h813103, - out_sfd__h822754, - out_sfd__h831538; - wire [50 : 0] r1__read__h853121, r1__read__h854769; + _theResult___fst_sfd__h831644, + _theResult___fst_sfd__h831650, + _theResult___sfd__h734940, + _theResult___sfd__h744591, + _theResult___sfd__h753375, + _theResult___sfd__h773793, + _theResult___sfd__h783444, + _theResult___sfd__h792228, + _theResult___sfd__h813097, + _theResult___sfd__h822748, + _theResult___sfd__h831532, + _theResult___snd_fst_sfd__h715212, + _theResult___snd_fst_sfd__h735046, + _theResult___snd_fst_sfd__h753481, + _theResult___snd_fst_sfd__h754206, + _theResult___snd_fst_sfd__h773899, + _theResult___snd_fst_sfd__h792334, + _theResult___snd_fst_sfd__h793510, + _theResult___snd_fst_sfd__h813203, + _theResult___snd_fst_sfd__h831638, + mask__h239971, + mask__h241128, + mask__h254752, + out___1_sfd__h714960, + out___1_sfd__h753954, + out___1_sfd__h793258, + out_sfd__h734943, + out_sfd__h744594, + out_sfd__h753378, + out_sfd__h773796, + out_sfd__h783447, + out_sfd__h792231, + out_sfd__h813100, + out_sfd__h822751, + out_sfd__h831535; + wire [50 : 0] r1__read__h853120, r1__read__h854768; wire [49 : 0] coreFix_memExe_dTlbprocResp_BITS_450_TO_401_P_ETC__q7, coreFix_memExe_regToExeQfirst_BITS_218_TO_169_ETC__q5, coreFix_memExe_regToExeQfirst_BITS_381_TO_332_ETC__q3, - highBitsfilter__h1008372, - highBitsfilter__h1008775, - highBitsfilter__h1009192, - highBitsfilter__h1009595, - highBitsfilter__h1010264, - highOffsetBits__h1008373, - highOffsetBits__h1008776, - highOffsetBits__h1009193, - highOffsetBits__h1009596, - highOffsetBits__h1010265, - highOffsetBits__h1031424, - highOffsetBits__h1031827, - highOffsetBits__h1032244, - highOffsetBits__h1032647, - highOffsetBits__h1033314, - highOffsetBits__h242647, - mask__h239865, - mask__h241022, - mask__h254646, - r1__read__h854878, - signBits__h1008370, - signBits__h1031421, - signBits__h242644, - x__h1008400, - x__h1031451, - x__h242674; - wire [48 : 0] r1__read__h853123, r1__read__h854771, r1__read__h854880; - wire [47 : 0] r1__read__h854882; - wire [46 : 0] r1__read__h853125, r1__read__h854773; - wire [45 : 0] r1__read__h853127, r1__read__h854775; - wire [44 : 0] r1__read__h853129, r1__read__h854777; - wire [43 : 0] r1__read__h853131, r1__read__h854779; - wire [42 : 0] r1__read__h854781; - wire [41 : 0] r1__read__h854783; - wire [40 : 0] r1__read__h854785; - wire [38 : 0] IF_csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_c_ETC___d22876; - wire [37 : 0] r1__read__h854884; + highBitsfilter__h1008407, + highBitsfilter__h1008810, + highBitsfilter__h1009227, + highBitsfilter__h1009630, + highBitsfilter__h1010299, + highOffsetBits__h1008408, + highOffsetBits__h1008811, + highOffsetBits__h1009228, + highOffsetBits__h1009631, + highOffsetBits__h1010300, + highOffsetBits__h1031458, + highOffsetBits__h1031861, + highOffsetBits__h1032278, + highOffsetBits__h1032681, + highOffsetBits__h1033348, + highOffsetBits__h242644, + mask__h239862, + mask__h241019, + mask__h254643, + r1__read__h854877, + signBits__h1008405, + signBits__h1031455, + signBits__h242641, + x__h1008435, + x__h1031485, + x__h242671; + wire [48 : 0] r1__read__h853122, r1__read__h854770, r1__read__h854879; + wire [47 : 0] r1__read__h854881; + wire [46 : 0] r1__read__h853124, r1__read__h854772; + wire [45 : 0] r1__read__h853126, r1__read__h854774; + wire [44 : 0] r1__read__h853128, r1__read__h854776; + wire [43 : 0] r1__read__h853130, r1__read__h854778; + wire [42 : 0] r1__read__h854780; + wire [41 : 0] r1__read__h854782; + wire [40 : 0] r1__read__h854784; + wire [38 : 0] IF_csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_c_ETC___d22878; + wire [37 : 0] r1__read__h854883; wire [33 : 0] IF_INV_IF_coreFix_memExe_lsq_firstLd__498_BITS_ETC___d1954, IF_INV_IF_coreFix_memExe_lsq_firstLd__498_BITS_ETC___d2120, IF_INV_coreFix_memExe_lsq_respLd_159_BITS_108__ETC___d2210, @@ -4980,41 +4983,41 @@ module mkCore(CLK, wire [31 : 0] IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q145, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q23, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q22, - coreFix_memExe_regToExeQfirst_BITS_434_TO_403__q17, - data05833_BITS_31_TO_0__q26, - r1__read__h853133, - r1__read__h854787, - x__h568253, - x__h614007, + coreFix_memExe_regToExeQfirst_BITS_434_TO_403__q15, + data05831_BITS_31_TO_0__q26, + r1__read__h853132, + r1__read__h854786, + x__h568251, + x__h614005, x__h65639, - x__h659754, + x__h659752, x_data__h60140; - wire [29 : 0] r1__read__h853135, r1__read__h854789; - wire [27 : 0] r1__read__h854791; - wire [25 : 0] IF_IF_csrf_prv_reg_read__0286_ULE_1_2614_AND_I_ETC___d22894, + wire [29 : 0] r1__read__h853134, r1__read__h854788; + wire [27 : 0] r1__read__h854790; + wire [25 : 0] IF_IF_csrf_prv_reg_read__0286_ULE_1_2614_AND_I_ETC___d22896, IF_coreFix_aluExe_0_exeToFinQ_first__9946_BIT__ETC___d20111, IF_coreFix_aluExe_0_exeToFinQ_first__9946_BIT__ETC___d20142, IF_coreFix_aluExe_1_exeToFinQ_first__7830_BIT__ETC___d17996, IF_coreFix_aluExe_1_exeToFinQ_first__7830_BIT__ETC___d18027, IF_coreFix_memExe_regToExeQ_first__645_BIT_103_ETC___d4017, - IF_csrf_mepcc_reg_read_wget__3540_BIT_34_3552__ETC___d23562, - IF_csrf_rg_dpc_read__6343_BIT_34_4349_THEN_csr_ETC___d24357, - IF_csrf_sepcc_reg_read_wget__3506_BIT_34_3518__ETC___d23528; - wire [24 : 0] sfd__h584657, - sfd__h593239, - sfd__h602423, - sfd__h611035, - sfd__h630406, - sfd__h638988, - sfd__h648172, - sfd__h656784, - sfd__h676153, - sfd__h684735, - sfd__h693919, - sfd__h702531, - value__h719844, - value__h758697, - value__h798001; + IF_csrf_mepcc_reg_read_wget__3542_BIT_34_3554__ETC___d23564, + IF_csrf_rg_dpc_read__6343_BIT_34_4351_THEN_csr_ETC___d24359, + IF_csrf_sepcc_reg_read_wget__3508_BIT_34_3520__ETC___d23530; + wire [24 : 0] sfd__h584655, + sfd__h593237, + sfd__h602421, + sfd__h611033, + sfd__h630404, + sfd__h638986, + sfd__h648170, + sfd__h656782, + sfd__h676151, + sfd__h684733, + sfd__h693917, + sfd__h702529, + value__h719841, + value__h758694, + value__h797998; wire [22 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d10477, IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d10479, IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11874, @@ -5039,68 +5042,68 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9101, IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9145, IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9147, - _theResult___fst_sfd__h585163, - _theResult___fst_sfd__h593745, - _theResult___fst_sfd__h602929, - _theResult___fst_sfd__h611565, - _theResult___fst_sfd__h611574, - _theResult___fst_sfd__h611580, - _theResult___fst_sfd__h630912, - _theResult___fst_sfd__h639494, - _theResult___fst_sfd__h648678, - _theResult___fst_sfd__h657314, - _theResult___fst_sfd__h657323, - _theResult___fst_sfd__h657329, - _theResult___fst_sfd__h676659, - _theResult___fst_sfd__h685241, - _theResult___fst_sfd__h694425, - _theResult___fst_sfd__h703061, - _theResult___fst_sfd__h703070, - _theResult___fst_sfd__h703076, - _theResult___sfd__h585082, - _theResult___sfd__h593664, - _theResult___sfd__h602848, - _theResult___sfd__h611484, - _theResult___sfd__h611586, - _theResult___sfd__h630831, - _theResult___sfd__h639413, - _theResult___sfd__h648597, - _theResult___sfd__h657233, - _theResult___sfd__h657335, - _theResult___sfd__h676578, - _theResult___sfd__h685160, - _theResult___sfd__h694344, - _theResult___sfd__h702980, - _theResult___sfd__h703082, - _theResult___snd_fst_sfd__h568799, - _theResult___snd_fst_sfd__h593748, - _theResult___snd_fst_sfd__h611568, - _theResult___snd_fst_sfd__h614553, - _theResult___snd_fst_sfd__h639497, - _theResult___snd_fst_sfd__h657317, - _theResult___snd_fst_sfd__h660300, - _theResult___snd_fst_sfd__h685244, - _theResult___snd_fst_sfd__h703064, - f1_sfd__h714900, - f2_sfd__h753894, - f3_sfd__h793198, - out_f_sfd__h611863, - out_f_sfd__h657612, - out_f_sfd__h703359, - out_sfd__h585085, - out_sfd__h593667, - out_sfd__h602851, - out_sfd__h611487, - out_sfd__h630834, - out_sfd__h639416, - out_sfd__h648600, - out_sfd__h657236, - out_sfd__h676581, - out_sfd__h685163, - out_sfd__h694347, - out_sfd__h702983; - wire [19 : 0] r1__read__h854726; - wire [18 : 0] INV_commitStage_commitTrap_BITS_217_TO_199__q15, + _theResult___fst_sfd__h585161, + _theResult___fst_sfd__h593743, + _theResult___fst_sfd__h602927, + _theResult___fst_sfd__h611563, + _theResult___fst_sfd__h611572, + _theResult___fst_sfd__h611578, + _theResult___fst_sfd__h630910, + _theResult___fst_sfd__h639492, + _theResult___fst_sfd__h648676, + _theResult___fst_sfd__h657312, + _theResult___fst_sfd__h657321, + _theResult___fst_sfd__h657327, + _theResult___fst_sfd__h676657, + _theResult___fst_sfd__h685239, + _theResult___fst_sfd__h694423, + _theResult___fst_sfd__h703059, + _theResult___fst_sfd__h703068, + _theResult___fst_sfd__h703074, + _theResult___sfd__h585080, + _theResult___sfd__h593662, + _theResult___sfd__h602846, + _theResult___sfd__h611482, + _theResult___sfd__h611584, + _theResult___sfd__h630829, + _theResult___sfd__h639411, + _theResult___sfd__h648595, + _theResult___sfd__h657231, + _theResult___sfd__h657333, + _theResult___sfd__h676576, + _theResult___sfd__h685158, + _theResult___sfd__h694342, + _theResult___sfd__h702978, + _theResult___sfd__h703080, + _theResult___snd_fst_sfd__h568797, + _theResult___snd_fst_sfd__h593746, + _theResult___snd_fst_sfd__h611566, + _theResult___snd_fst_sfd__h614551, + _theResult___snd_fst_sfd__h639495, + _theResult___snd_fst_sfd__h657315, + _theResult___snd_fst_sfd__h660298, + _theResult___snd_fst_sfd__h685242, + _theResult___snd_fst_sfd__h703062, + f1_sfd__h714897, + f2_sfd__h753891, + f3_sfd__h793195, + out_f_sfd__h611861, + out_f_sfd__h657610, + out_f_sfd__h703357, + out_sfd__h585083, + out_sfd__h593665, + out_sfd__h602849, + out_sfd__h611485, + out_sfd__h630832, + out_sfd__h639414, + out_sfd__h648598, + out_sfd__h657234, + out_sfd__h676579, + out_sfd__h685161, + out_sfd__h694345, + out_sfd__h702981; + wire [19 : 0] r1__read__h854725; + wire [18 : 0] INV_commitStage_commitTrap_BITS_217_TO_199__q16, INV_coreFix_aluExe_0_regToExeQfirst_BITS_157__ETC__q14, INV_coreFix_aluExe_0_regToExeQfirst_BITS_286__ETC__q13, INV_coreFix_aluExe_1_regToExeQfirst_BITS_157__ETC__q12, @@ -5108,8 +5111,8 @@ module mkCore(CLK, INV_coreFix_memExe_lsqrespLd_BITS_108_TO_90__q10, INV_coreFix_memExe_respLrScAmoQ_data_0_BITS_10_ETC__q8, INV_mmio_dataRespQ_data_0_BITS_108_TO_90__q9, - INV_x83399_BITS_108_TO_90__q34, - INV_x99251_BITS_108_TO_90__q36; + INV_x83397_BITS_108_TO_90__q34, + INV_x99249_BITS_108_TO_90__q36; wire [17 : 0] IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__840_ETC___d19042, IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__840_ETC___d19043, IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__564_ETC___d16647, @@ -5126,43 +5129,43 @@ module mkCore(CLK, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3559; wire [15 : 0] IF_IF_NOT_csrf_prv_reg_read__0286_EQ_3_0287_02_ETC___d20323, IF_coreFix_memExe_dispToRegQ_first__686_BIT_10_ETC___d3536, - _theResult____h920232, - base__h239699, - base__h240856, - base__h254480, - base__h854220, - base__h855213, - base__h895975, - base__h896259, - base__h896604, - base__h997574, - enabled_ints___1__h920757, - enabled_ints__h920803, - newAddrBits__h1008555, - newAddrBits__h1008958, - newAddrBits__h1009375, - newAddrBits__h1009778, - newAddrBits__h1010447, - newAddrBits__h1031606, - newAddrBits__h1032009, - newAddrBits__h1032426, - newAddrBits__h1032829, - newAddrBits__h1033496, - offset__h239700, - offset__h240857, - offset__h254481, - offset__h854221, - offset__h855214, - offset__h895976, - offset__h896260, - offset__h896605, - offset__h997575, - pend_ints__h920230, - x__h240072, - x__h241229, - x__h254853, - x__h896542, - y__h920769; + _theResult____h920230, + base__h239696, + base__h240853, + base__h254477, + base__h854219, + base__h855212, + base__h895973, + base__h896257, + base__h896602, + base__h997609, + enabled_ints___1__h920755, + enabled_ints__h920801, + newAddrBits__h1008590, + newAddrBits__h1008993, + newAddrBits__h1009410, + newAddrBits__h1009813, + newAddrBits__h1010482, + newAddrBits__h1031640, + newAddrBits__h1032043, + newAddrBits__h1032460, + newAddrBits__h1032863, + newAddrBits__h1033530, + offset__h239697, + offset__h240854, + offset__h254478, + offset__h854220, + offset__h855213, + offset__h895974, + offset__h896258, + offset__h896603, + offset__h997610, + pend_ints__h920228, + x__h240069, + x__h241226, + x__h254850, + x__h896540, + y__h920767; wire [13 : 0] IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__840_ETC___d18828, IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__840_ETC___d18829, IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__564_ETC___d16433, @@ -5184,85 +5187,85 @@ module mkCore(CLK, IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16438, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3068, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3425, - b_base__h127528, - b_base__h140444, - b_base__h183706, - b_base__h202457, - b_base__h217023, - b_base__h867086, - b_base__h867634, - b_base__h906772, - b_base__h907320, - b_base__h995136, + b_base__h127527, + b_base__h140443, + b_base__h183704, + b_base__h202455, + b_base__h217021, + b_base__h867085, + b_base__h867633, + b_base__h906770, + b_base__h907318, + b_base__h995134, checkForException___d20654, checkForException___d21604, - cr_addrBits__h866672, - cr_addrBits__h867220, - cr_addrBits__h906358, - cr_addrBits__h906906, - data_addrBits__h1018718, - data_addrBits__h1019572, - pc_addrBits__h994740, - r1__read_BITS_13_TO_0___h920779, - repBoundBits__h242653, - res_addrBits__h126823, - res_addrBits__h139735, - res_addrBits__h178899, - res_addrBits__h197664, - res_addrBits__h216423, - res_addrBits__h235324, - res_addrBits__h567347, - res_addrBits__h568199, - res_addrBits__h613956, - res_addrBits__h659703, - res_addrBits__h705512, - res_addrBits__h706372, - res_addrBits__h848645, - res_addrBits__h892146, - result_d_addrBits__h1008567, - result_d_addrBits__h1008970, - result_d_addrBits__h1009387, - result_d_addrBits__h1009790, - result_d_addrBits__h1010459, - result_d_addrBits__h1031618, - result_d_addrBits__h1032021, - result_d_addrBits__h1032438, - result_d_addrBits__h1032841, - result_d_addrBits__h1033508, - toBoundsM1__h1008383, - toBoundsM1__h1008786, - toBoundsM1__h1009203, - toBoundsM1__h1009606, - toBoundsM1__h1010275, - toBoundsM1__h242657, - toBounds__h1008382, - toBounds__h1008785, - toBounds__h1009202, - toBounds__h1009605, - toBounds__h1010274, - toBounds__h242656, - x1_avValue_new_pcc_capFat_bounds_baseBits__h1000887, - x__h1000884, - x__h127501, - x__h127521, - x__h140417, - x__h140437, - x__h183679, - x__h183699, - x__h202430, - x__h202450, - x__h216996, - x__h217016, - x__h867059, - x__h867079, - x__h867607, - x__h867627, - x__h906745, - x__h906765, - x__h907293, - x__h907313, - x__h995109, - x__h995129; + cr_addrBits__h866671, + cr_addrBits__h867219, + cr_addrBits__h906356, + cr_addrBits__h906904, + data_addrBits__h1018752, + data_addrBits__h1019606, + pc_addrBits__h994738, + r1__read_BITS_13_TO_0___h920777, + repBoundBits__h242650, + res_addrBits__h126822, + res_addrBits__h139734, + res_addrBits__h178897, + res_addrBits__h197662, + res_addrBits__h216421, + res_addrBits__h235321, + res_addrBits__h567344, + res_addrBits__h568197, + res_addrBits__h613954, + res_addrBits__h659701, + res_addrBits__h705510, + res_addrBits__h706370, + res_addrBits__h848643, + res_addrBits__h892145, + result_d_addrBits__h1008602, + result_d_addrBits__h1009005, + result_d_addrBits__h1009422, + result_d_addrBits__h1009825, + result_d_addrBits__h1010494, + result_d_addrBits__h1031652, + result_d_addrBits__h1032055, + result_d_addrBits__h1032472, + result_d_addrBits__h1032875, + result_d_addrBits__h1033542, + toBoundsM1__h1008418, + toBoundsM1__h1008821, + toBoundsM1__h1009238, + toBoundsM1__h1009641, + toBoundsM1__h1010310, + toBoundsM1__h242654, + toBounds__h1008417, + toBounds__h1008820, + toBounds__h1009237, + toBounds__h1009640, + toBounds__h1010309, + toBounds__h242653, + x1_avValue_new_pcc_capFat_bounds_baseBits__h1000922, + x__h1000919, + x__h127500, + x__h127520, + x__h140416, + x__h140436, + x__h183677, + x__h183697, + x__h202428, + x__h202448, + x__h216994, + x__h217014, + x__h867058, + x__h867078, + x__h867606, + x__h867626, + x__h906743, + x__h906763, + x__h907291, + x__h907311, + x__h995107, + x__h995127; wire [12 : 0] IF_IF_coreFix_memExe_dTlb_procResp__257_BIT_27_ETC___d4757, IF_NOT_renameStage_rg_m_halt_req_0283_BIT_4_02_ETC___d20987, IF_NOT_renameStage_rg_m_halt_req_0283_BIT_4_02_ETC___d20988, @@ -5298,45 +5301,45 @@ module mkCore(CLK, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d10074, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d11471, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d8677, - b_top__h127527, - b_top__h140443, - b_top__h183705, - b_top__h202456, - b_top__h217022, - b_top__h867085, - b_top__h867633, - b_top__h906771, - b_top__h907319, - b_top__h995135, + b_top__h127526, + b_top__h140442, + b_top__h183703, + b_top__h202454, + b_top__h217020, + b_top__h867084, + b_top__h867632, + b_top__h906769, + b_top__h907317, + b_top__h995133, capChecks___d4160, - renaming_spec_bits__h968741, - result__h915810, - result__h915861, - spec_bits__h973792, - topBits__h127430, - topBits__h140346, - topBits__h183608, - topBits__h202359, - topBits__h216925, - topBits__h866987, - topBits__h867535, - topBits__h906673, - topBits__h907221, - topBits__h995038, - w__h915805, - x__h594836, - x__h640585, - x__h686332, - x__h736369, - x__h775222, - x__h814526, - x__h915809, - x__h915860, - y__h915839, - y__h973805, - y_avValue_snd_fst__h963385, - y_avValue_snd_fst__h963427, - y_avValue_snd_fst__h963469; + renaming_spec_bits__h968739, + result__h915808, + result__h915859, + spec_bits__h973790, + topBits__h127429, + topBits__h140345, + topBits__h183606, + topBits__h202357, + topBits__h216923, + topBits__h866986, + topBits__h867534, + topBits__h906671, + topBits__h907219, + topBits__h995036, + w__h915803, + x__h594834, + x__h640583, + x__h686330, + x__h736366, + x__h775219, + x__h814523, + x__h915807, + x__h915858, + y__h915837, + y__h973803, + y_avValue_snd_fst__h963383, + y_avValue_snd_fst__h963425, + y_avValue_snd_fst__h963467; wire [10 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13207, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13209, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13917, @@ -5360,103 +5363,103 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q152, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q169, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q192, - _theResult___exp__h734942, - _theResult___exp__h744593, - _theResult___exp__h753377, - _theResult___exp__h773795, - _theResult___exp__h783446, - _theResult___exp__h792230, - _theResult___exp__h813099, - _theResult___exp__h822750, - _theResult___exp__h831534, - _theResult___fst_exp__h719214, - _theResult___fst_exp__h734278, + _theResult___exp__h734939, + _theResult___exp__h744590, + _theResult___exp__h753374, + _theResult___exp__h773792, + _theResult___exp__h783443, + _theResult___exp__h792227, + _theResult___exp__h813096, + _theResult___exp__h822747, + _theResult___exp__h831531, + _theResult___fst_exp__h719211, + _theResult___fst_exp__h734275, + _theResult___fst_exp__h734281, _theResult___fst_exp__h734284, - _theResult___fst_exp__h734287, + _theResult___fst_exp__h735039, _theResult___fst_exp__h735042, - _theResult___fst_exp__h735045, - _theResult___fst_exp__h743864, - _theResult___fst_exp__h743929, + _theResult___fst_exp__h743861, + _theResult___fst_exp__h743926, + _theResult___fst_exp__h743932, _theResult___fst_exp__h743935, - _theResult___fst_exp__h743938, + _theResult___fst_exp__h744690, _theResult___fst_exp__h744693, - _theResult___fst_exp__h744696, - _theResult___fst_exp__h752649, - _theResult___fst_exp__h752688, + _theResult___fst_exp__h752646, + _theResult___fst_exp__h752685, + _theResult___fst_exp__h752691, _theResult___fst_exp__h752694, - _theResult___fst_exp__h752697, + _theResult___fst_exp__h753474, _theResult___fst_exp__h753477, - _theResult___fst_exp__h753480, + _theResult___fst_exp__h753486, _theResult___fst_exp__h753489, - _theResult___fst_exp__h753492, - _theResult___fst_exp__h758067, - _theResult___fst_exp__h773131, + _theResult___fst_exp__h758064, + _theResult___fst_exp__h773128, + _theResult___fst_exp__h773134, _theResult___fst_exp__h773137, - _theResult___fst_exp__h773140, + _theResult___fst_exp__h773892, _theResult___fst_exp__h773895, - _theResult___fst_exp__h773898, - _theResult___fst_exp__h782717, - _theResult___fst_exp__h782782, + _theResult___fst_exp__h782714, + _theResult___fst_exp__h782779, + _theResult___fst_exp__h782785, _theResult___fst_exp__h782788, - _theResult___fst_exp__h782791, + _theResult___fst_exp__h783543, _theResult___fst_exp__h783546, - _theResult___fst_exp__h783549, - _theResult___fst_exp__h791502, - _theResult___fst_exp__h791541, + _theResult___fst_exp__h791499, + _theResult___fst_exp__h791538, + _theResult___fst_exp__h791544, _theResult___fst_exp__h791547, - _theResult___fst_exp__h791550, + _theResult___fst_exp__h792327, _theResult___fst_exp__h792330, - _theResult___fst_exp__h792333, + _theResult___fst_exp__h792339, _theResult___fst_exp__h792342, - _theResult___fst_exp__h792345, - _theResult___fst_exp__h797371, - _theResult___fst_exp__h812435, + _theResult___fst_exp__h797368, + _theResult___fst_exp__h812432, + _theResult___fst_exp__h812438, _theResult___fst_exp__h812441, - _theResult___fst_exp__h812444, + _theResult___fst_exp__h813196, _theResult___fst_exp__h813199, - _theResult___fst_exp__h813202, - _theResult___fst_exp__h822021, - _theResult___fst_exp__h822086, + _theResult___fst_exp__h822018, + _theResult___fst_exp__h822083, + _theResult___fst_exp__h822089, _theResult___fst_exp__h822092, - _theResult___fst_exp__h822095, + _theResult___fst_exp__h822847, _theResult___fst_exp__h822850, - _theResult___fst_exp__h822853, - _theResult___fst_exp__h830806, - _theResult___fst_exp__h830845, + _theResult___fst_exp__h830803, + _theResult___fst_exp__h830842, + _theResult___fst_exp__h830848, _theResult___fst_exp__h830851, - _theResult___fst_exp__h830854, + _theResult___fst_exp__h831631, _theResult___fst_exp__h831634, - _theResult___fst_exp__h831637, + _theResult___fst_exp__h831643, _theResult___fst_exp__h831646, - _theResult___fst_exp__h831649, - _theResult___snd_fst_exp__h735048, - _theResult___snd_fst_exp__h753483, - _theResult___snd_fst_exp__h773901, - _theResult___snd_fst_exp__h792336, - _theResult___snd_fst_exp__h813205, - _theResult___snd_fst_exp__h831640, + _theResult___snd_fst_exp__h735045, + _theResult___snd_fst_exp__h753480, + _theResult___snd_fst_exp__h773898, + _theResult___snd_fst_exp__h792333, + _theResult___snd_fst_exp__h813202, + _theResult___snd_fst_exp__h831637, coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q83, coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q48, coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q118, - din_inc___2_exp__h753537, - din_inc___2_exp__h753572, - din_inc___2_exp__h753598, - din_inc___2_exp__h792390, - din_inc___2_exp__h792425, - din_inc___2_exp__h792451, - din_inc___2_exp__h831694, - din_inc___2_exp__h831729, - din_inc___2_exp__h831755, - out_exp__h734945, - out_exp__h744596, - out_exp__h753380, - out_exp__h773798, - out_exp__h783449, - out_exp__h792233, - out_exp__h813102, - out_exp__h822753, - out_exp__h831537, - x__h998861; + din_inc___2_exp__h753534, + din_inc___2_exp__h753569, + din_inc___2_exp__h753595, + din_inc___2_exp__h792387, + din_inc___2_exp__h792422, + din_inc___2_exp__h792448, + din_inc___2_exp__h831691, + din_inc___2_exp__h831726, + din_inc___2_exp__h831752, + out_exp__h734942, + out_exp__h744593, + out_exp__h753377, + out_exp__h773795, + out_exp__h783446, + out_exp__h792230, + out_exp__h813099, + out_exp__h822750, + out_exp__h831534, + x__h998896; wire [9 : 0] IF_coreFix_memExe_dispToRegQ_first__686_BIT_10_ETC___d3635; wire [8 : 0] IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d10392, IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d11789, @@ -5512,128 +5515,128 @@ module mkCore(CLK, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q89, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q54, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q124, - _theResult___exp__h585081, - _theResult___exp__h593663, - _theResult___exp__h602847, - _theResult___exp__h611483, - _theResult___exp__h611585, - _theResult___exp__h630830, - _theResult___exp__h639412, - _theResult___exp__h648596, - _theResult___exp__h657232, - _theResult___exp__h657334, - _theResult___exp__h676577, - _theResult___exp__h685159, - _theResult___exp__h694343, - _theResult___exp__h702979, - _theResult___exp__h703081, - _theResult___fst_exp__h584565, - _theResult___fst_exp__h584630, - _theResult___fst_exp__h584636, - _theResult___fst_exp__h584639, - _theResult___fst_exp__h585162, - _theResult___fst_exp__h593212, - _theResult___fst_exp__h593218, - _theResult___fst_exp__h593221, - _theResult___fst_exp__h593744, - _theResult___fst_exp__h602331, - _theResult___fst_exp__h602396, - _theResult___fst_exp__h602402, - _theResult___fst_exp__h602405, - _theResult___fst_exp__h602928, - _theResult___fst_exp__h610968, - _theResult___fst_exp__h611007, - _theResult___fst_exp__h611013, - _theResult___fst_exp__h611016, - _theResult___fst_exp__h611564, - _theResult___fst_exp__h611573, - _theResult___fst_exp__h611576, - _theResult___fst_exp__h630314, - _theResult___fst_exp__h630379, - _theResult___fst_exp__h630385, - _theResult___fst_exp__h630388, - _theResult___fst_exp__h630911, - _theResult___fst_exp__h638961, - _theResult___fst_exp__h638967, - _theResult___fst_exp__h638970, - _theResult___fst_exp__h639493, - _theResult___fst_exp__h648080, - _theResult___fst_exp__h648145, - _theResult___fst_exp__h648151, - _theResult___fst_exp__h648154, - _theResult___fst_exp__h648677, - _theResult___fst_exp__h656717, - _theResult___fst_exp__h656756, - _theResult___fst_exp__h656762, - _theResult___fst_exp__h656765, - _theResult___fst_exp__h657313, - _theResult___fst_exp__h657322, - _theResult___fst_exp__h657325, - _theResult___fst_exp__h676061, - _theResult___fst_exp__h676126, - _theResult___fst_exp__h676132, - _theResult___fst_exp__h676135, - _theResult___fst_exp__h676658, - _theResult___fst_exp__h684708, - _theResult___fst_exp__h684714, - _theResult___fst_exp__h684717, - _theResult___fst_exp__h685240, - _theResult___fst_exp__h693827, - _theResult___fst_exp__h693892, - _theResult___fst_exp__h693898, - _theResult___fst_exp__h693901, - _theResult___fst_exp__h694424, - _theResult___fst_exp__h702464, - _theResult___fst_exp__h702503, - _theResult___fst_exp__h702509, - _theResult___fst_exp__h702512, - _theResult___fst_exp__h703060, - _theResult___fst_exp__h703069, - _theResult___fst_exp__h703072, - _theResult___snd_fst_exp__h593747, - _theResult___snd_fst_exp__h611567, - _theResult___snd_fst_exp__h639496, - _theResult___snd_fst_exp__h657316, - _theResult___snd_fst_exp__h685243, - _theResult___snd_fst_exp__h703063, - din_inc___2_exp__h611598, - din_inc___2_exp__h611622, - din_inc___2_exp__h611652, - din_inc___2_exp__h611676, - din_inc___2_exp__h657347, - din_inc___2_exp__h657371, - din_inc___2_exp__h657401, - din_inc___2_exp__h657425, - din_inc___2_exp__h703094, - din_inc___2_exp__h703118, - din_inc___2_exp__h703148, - din_inc___2_exp__h703172, - f1_exp14899_MINUS_127__q148, - f1_exp__h714899, - f2_exp53893_MINUS_127__q188, - f2_exp__h753893, - f3_exp93197_MINUS_127__q165, - f3_exp__h793197, - out_exp__h585084, - out_exp__h593666, - out_exp__h602850, - out_exp__h611486, - out_exp__h630833, - out_exp__h639415, - out_exp__h648599, - out_exp__h657235, - out_exp__h676580, - out_exp__h685162, - out_exp__h694346, - out_exp__h702982, - out_f_exp__h611862, - out_f_exp__h657611, - out_f_exp__h703358, - x__h853092; + _theResult___exp__h585079, + _theResult___exp__h593661, + _theResult___exp__h602845, + _theResult___exp__h611481, + _theResult___exp__h611583, + _theResult___exp__h630828, + _theResult___exp__h639410, + _theResult___exp__h648594, + _theResult___exp__h657230, + _theResult___exp__h657332, + _theResult___exp__h676575, + _theResult___exp__h685157, + _theResult___exp__h694341, + _theResult___exp__h702977, + _theResult___exp__h703079, + _theResult___fst_exp__h584563, + _theResult___fst_exp__h584628, + _theResult___fst_exp__h584634, + _theResult___fst_exp__h584637, + _theResult___fst_exp__h585160, + _theResult___fst_exp__h593210, + _theResult___fst_exp__h593216, + _theResult___fst_exp__h593219, + _theResult___fst_exp__h593742, + _theResult___fst_exp__h602329, + _theResult___fst_exp__h602394, + _theResult___fst_exp__h602400, + _theResult___fst_exp__h602403, + _theResult___fst_exp__h602926, + _theResult___fst_exp__h610966, + _theResult___fst_exp__h611005, + _theResult___fst_exp__h611011, + _theResult___fst_exp__h611014, + _theResult___fst_exp__h611562, + _theResult___fst_exp__h611571, + _theResult___fst_exp__h611574, + _theResult___fst_exp__h630312, + _theResult___fst_exp__h630377, + _theResult___fst_exp__h630383, + _theResult___fst_exp__h630386, + _theResult___fst_exp__h630909, + _theResult___fst_exp__h638959, + _theResult___fst_exp__h638965, + _theResult___fst_exp__h638968, + _theResult___fst_exp__h639491, + _theResult___fst_exp__h648078, + _theResult___fst_exp__h648143, + _theResult___fst_exp__h648149, + _theResult___fst_exp__h648152, + _theResult___fst_exp__h648675, + _theResult___fst_exp__h656715, + _theResult___fst_exp__h656754, + _theResult___fst_exp__h656760, + _theResult___fst_exp__h656763, + _theResult___fst_exp__h657311, + _theResult___fst_exp__h657320, + _theResult___fst_exp__h657323, + _theResult___fst_exp__h676059, + _theResult___fst_exp__h676124, + _theResult___fst_exp__h676130, + _theResult___fst_exp__h676133, + _theResult___fst_exp__h676656, + _theResult___fst_exp__h684706, + _theResult___fst_exp__h684712, + _theResult___fst_exp__h684715, + _theResult___fst_exp__h685238, + _theResult___fst_exp__h693825, + _theResult___fst_exp__h693890, + _theResult___fst_exp__h693896, + _theResult___fst_exp__h693899, + _theResult___fst_exp__h694422, + _theResult___fst_exp__h702462, + _theResult___fst_exp__h702501, + _theResult___fst_exp__h702507, + _theResult___fst_exp__h702510, + _theResult___fst_exp__h703058, + _theResult___fst_exp__h703067, + _theResult___fst_exp__h703070, + _theResult___snd_fst_exp__h593745, + _theResult___snd_fst_exp__h611565, + _theResult___snd_fst_exp__h639494, + _theResult___snd_fst_exp__h657314, + _theResult___snd_fst_exp__h685241, + _theResult___snd_fst_exp__h703061, + din_inc___2_exp__h611596, + din_inc___2_exp__h611620, + din_inc___2_exp__h611650, + din_inc___2_exp__h611674, + din_inc___2_exp__h657345, + din_inc___2_exp__h657369, + din_inc___2_exp__h657399, + din_inc___2_exp__h657423, + din_inc___2_exp__h703092, + din_inc___2_exp__h703116, + din_inc___2_exp__h703146, + din_inc___2_exp__h703170, + f1_exp14896_MINUS_127__q148, + f1_exp__h714896, + f2_exp53890_MINUS_127__q188, + f2_exp__h753890, + f3_exp93194_MINUS_127__q165, + f3_exp__h793194, + out_exp__h585082, + out_exp__h593664, + out_exp__h602848, + out_exp__h611484, + out_exp__h630831, + out_exp__h639413, + out_exp__h648597, + out_exp__h657233, + out_exp__h676578, + out_exp__h685160, + out_exp__h694344, + out_exp__h702980, + out_f_exp__h611860, + out_f_exp__h657609, + out_f_exp__h703356, + x__h853091; wire [6 : 0] NOT_coreFix_aluExe_0_dispToRegQ_first__8383_BI_ETC___d19436, NOT_coreFix_aluExe_1_dispToRegQ_first__5620_BI_ETC___d17320, - x__h244678, - x__h999587; + x__h244675, + x__h999622; wire [5 : 0] IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d11164, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d8370, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d9767, @@ -5659,22 +5662,22 @@ module mkCore(CLK, IF_fetchStage_pipelines_0_first__0256_BITS_265_ETC___d22051, IF_fetchStage_pipelines_1_first__0265_BITS_265_ETC___d22194, NOT_coreFix_memExe_dispToRegQ_first__686_BIT_1_ETC___d3634, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d24474, + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d24476, fetchStage_pipelines_0_first__0256_BIT_167_059_ETC___d20616, fetchStage_pipelines_1_first__0265_BIT_167_155_ETC___d21577, - x__h1000218, - x__h1000905, - x__h127341, - x__h140257, - x__h183519, - x__h202270, - x__h216836, - x__h866886, - x__h867434, - x__h906572, - x__h907120, - x__h994949, - x__h999561; + x__h1000253, + x__h1000940, + x__h127340, + x__h140256, + x__h183517, + x__h202268, + x__h216834, + x__h866885, + x__h867433, + x__h906570, + x__h907118, + x__h994947, + x__h999596; wire [4 : 0] IF_IF_coreFix_aluExe_0_exeToFinQ_first__9946_B_ETC___d20090, IF_IF_coreFix_aluExe_0_exeToFinQ_first__9946_B_ETC___d20091, IF_IF_coreFix_aluExe_1_exeToFinQ_first__7830_B_ETC___d17975, @@ -5701,7 +5704,7 @@ module mkCore(CLK, IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17739, IF_NOT_fetchStage_pipelines_0_first__0256_BITS_ETC___d22088, IF_NOT_fetchStage_pipelines_1_first__0265_BITS_ETC___d22242, - IF_rob_deqPort_0_canDeq__3598_THEN_IF_NOT_rob__ETC___d23825, + IF_rob_deqPort_0_canDeq__3600_THEN_IF_NOT_rob__ETC___d23827, _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d10694, _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d12091, _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d9297, @@ -5717,51 +5720,51 @@ module mkCore(CLK, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d10706, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d12103, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d9309, - cause_code__h996858, + cause_code__h996893, coreFix_memExe_regToExeQ_first__645_BITS_383_T_ETC___d4123, csrf_ddc_reg_read__051_BITS_85_TO_83_145_ULT_c_ETC___d4156, - fflags__h1016316, - r1__read__h855837, - res_fflags__h568239, - res_fflags__h613993, - res_fflags__h659740, + fflags__h1016351, + r1__read__h855836, + res_fflags__h568237, + res_fflags__h613991, + res_fflags__h659738, rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19181, rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16786, - x__h148991, - x__h152125, - x__h249478, - x__h249490, - x__h249502, - x__h249514, - x__h249526, - x__h249538, - x__h249550, - x__h249562, - x__h249574, - x__h249586, - x__h249598, - x__h249610, - x__h249622, - x__h249634, - x__h249646, - y__h249479, - y__h249491, - y__h249503, - y__h249515, - y__h249527, - y__h249539, - y__h249551, - y__h249563, - y__h249575, - y__h249587, - y__h249599, - y__h249611, - y__h249623, - y__h249635, - y__h249647, - y_avValue_snd_fst__h1015794, - y_avValue_snd_fst__h1016376, - y_avValue_snd_fst__h1016405; + x__h148990, + x__h152124, + x__h249475, + x__h249487, + x__h249499, + x__h249511, + x__h249523, + x__h249535, + x__h249547, + x__h249559, + x__h249571, + x__h249583, + x__h249595, + x__h249607, + x__h249619, + x__h249631, + x__h249643, + y__h249476, + y__h249488, + y__h249500, + y__h249512, + y__h249524, + y__h249536, + y__h249548, + y__h249560, + y__h249572, + y__h249584, + y__h249596, + y__h249608, + y__h249620, + y__h249632, + y__h249644, + y_avValue_snd_fst__h1015829, + y_avValue_snd_fst__h1016411, + y_avValue_snd_fst__h1016440; wire [3 : 0] IF_IF_coreFix_aluExe_0_dispToRegQ_first__8383__ETC___d19433, IF_IF_coreFix_aluExe_1_dispToRegQ_first__5620__ETC___d17317, IF_IF_renameStage_rg_m_halt_req_0283_BIT_4_028_ETC___d20977, @@ -5806,7 +5809,7 @@ module mkCore(CLK, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3390, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3433, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3632, - vm_mode_reg__read__h854732; + vm_mode_reg__read__h854731; wire [2 : 0] IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__840_ETC___d19088, IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__840_ETC___d19089, IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__564_ETC___d16693, @@ -5822,58 +5825,58 @@ module mkCore(CLK, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3327, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3589, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d7096, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d24407, - _theResult_____2__h515368, - dcsr_cause__h994364, - next_deqP___1__h515613, - repBound__h237318, - repBound__h239003, - repBound__h248218, - repBound__h248743, - repBound__h854076, - repBound__h854398, - repBound__h855069, - repBound__h855390, - repBound__h855899, - repBound__h857577, - repBound__h860539, - repBound__h860557, - repBound__h867140, - repBound__h867688, - repBound__h898286, - repBound__h900613, - repBound__h900631, - repBound__h906826, - repBound__h907374, - repBound__h997599, - tb__h867137, - tb__h867685, - tb__h906823, - tb__h907371, - tmp_expBotHalf__h127296, - tmp_expBotHalf__h140212, - tmp_expBotHalf__h183474, - tmp_expBotHalf__h202225, - tmp_expBotHalf__h216791, - tmp_expBotHalf__h866840, - tmp_expBotHalf__h867388, - tmp_expBotHalf__h906526, - tmp_expBotHalf__h907074, - tmp_expBotHalf__h994904, - tmp_expTopHalf__h127294, - tmp_expTopHalf__h140210, - tmp_expTopHalf__h183472, - tmp_expTopHalf__h202223, - tmp_expTopHalf__h216789, - tmp_expTopHalf__h866838, - tmp_expTopHalf__h867386, - tmp_expTopHalf__h906524, - tmp_expTopHalf__h907072, - tmp_expTopHalf__h994902, - v__h514824, - v__h515019, - x__h521675, - x_decodeInfo_frm__h926248; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d24409, + _theResult_____2__h515366, + dcsr_cause__h994362, + next_deqP___1__h515611, + repBound__h237315, + repBound__h239000, + repBound__h248215, + repBound__h248740, + repBound__h854075, + repBound__h854397, + repBound__h855068, + repBound__h855389, + repBound__h855898, + repBound__h857576, + repBound__h860538, + repBound__h860556, + repBound__h867139, + repBound__h867687, + repBound__h898284, + repBound__h900611, + repBound__h900629, + repBound__h906824, + repBound__h907372, + repBound__h997634, + tb__h867136, + tb__h867684, + tb__h906821, + tb__h907369, + tmp_expBotHalf__h127295, + tmp_expBotHalf__h140211, + tmp_expBotHalf__h183472, + tmp_expBotHalf__h202223, + tmp_expBotHalf__h216789, + tmp_expBotHalf__h866839, + tmp_expBotHalf__h867387, + tmp_expBotHalf__h906524, + tmp_expBotHalf__h907072, + tmp_expBotHalf__h994902, + tmp_expTopHalf__h127293, + tmp_expTopHalf__h140209, + tmp_expTopHalf__h183470, + tmp_expTopHalf__h202221, + tmp_expTopHalf__h216787, + tmp_expTopHalf__h866837, + tmp_expTopHalf__h867385, + tmp_expTopHalf__h906522, + tmp_expTopHalf__h907070, + tmp_expTopHalf__h994900, + v__h514822, + v__h515017, + x__h521673, + x_decodeInfo_frm__h926246; wire [1 : 0] IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__840_ETC___d19029, IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__840_ETC___d19030, IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__564_ETC___d16634, @@ -5884,113 +5887,113 @@ module mkCore(CLK, IF_NOT_coreFix_memExe_bypassWire_0_whas__704_7_ETC___d3547, IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17182, IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17176, - IF_rob_deqPort_0_canDeq__3598_THEN_IF_NOT_rob__ETC___d23847, + IF_rob_deqPort_0_canDeq__3600_THEN_IF_NOT_rob__ETC___d23849, IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d19034, IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16639, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3269, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3551, - IF_sfdin02325_BIT_33_THEN_2_ELSE_0__q51, - IF_sfdin22015_BIT_4_THEN_2_ELSE_0__q168, - IF_sfdin30308_BIT_33_THEN_2_ELSE_0__q76, - IF_sfdin43858_BIT_4_THEN_2_ELSE_0__q151, - IF_sfdin48074_BIT_33_THEN_2_ELSE_0__q86, - IF_sfdin76055_BIT_33_THEN_2_ELSE_0__q111, - IF_sfdin82711_BIT_4_THEN_2_ELSE_0__q191, - IF_sfdin84559_BIT_33_THEN_2_ELSE_0__q41, - IF_sfdin93821_BIT_33_THEN_2_ELSE_0__q121, - IF_theResult___snd02458_BIT_33_THEN_2_ELSE_0__q126, - IF_theResult___snd10962_BIT_33_THEN_2_ELSE_0__q56, - IF_theResult___snd12395_BIT_4_THEN_2_ELSE_0__q164, - IF_theResult___snd30800_BIT_4_THEN_2_ELSE_0__q171, - IF_theResult___snd34238_BIT_4_THEN_2_ELSE_0__q147, - IF_theResult___snd38921_BIT_33_THEN_2_ELSE_0__q78, - IF_theResult___snd52643_BIT_4_THEN_2_ELSE_0__q154, - IF_theResult___snd56711_BIT_33_THEN_2_ELSE_0__q91, - IF_theResult___snd73091_BIT_4_THEN_2_ELSE_0__q187, - IF_theResult___snd84668_BIT_33_THEN_2_ELSE_0__q113, - IF_theResult___snd91496_BIT_4_THEN_2_ELSE_0__q194, - IF_theResult___snd93172_BIT_33_THEN_2_ELSE_0__q43, - carry_out__h127432, - carry_out__h140348, - carry_out__h183610, - carry_out__h202361, - carry_out__h216927, - carry_out__h866989, - carry_out__h867537, - carry_out__h906675, - carry_out__h907223, - carry_out__h995040, + IF_sfdin02323_BIT_33_THEN_2_ELSE_0__q51, + IF_sfdin22012_BIT_4_THEN_2_ELSE_0__q168, + IF_sfdin30306_BIT_33_THEN_2_ELSE_0__q76, + IF_sfdin43855_BIT_4_THEN_2_ELSE_0__q151, + IF_sfdin48072_BIT_33_THEN_2_ELSE_0__q86, + IF_sfdin76053_BIT_33_THEN_2_ELSE_0__q111, + IF_sfdin82708_BIT_4_THEN_2_ELSE_0__q191, + IF_sfdin84557_BIT_33_THEN_2_ELSE_0__q41, + IF_sfdin93819_BIT_33_THEN_2_ELSE_0__q121, + IF_theResult___snd02456_BIT_33_THEN_2_ELSE_0__q126, + IF_theResult___snd10960_BIT_33_THEN_2_ELSE_0__q56, + IF_theResult___snd12392_BIT_4_THEN_2_ELSE_0__q164, + IF_theResult___snd30797_BIT_4_THEN_2_ELSE_0__q171, + IF_theResult___snd34235_BIT_4_THEN_2_ELSE_0__q147, + IF_theResult___snd38919_BIT_33_THEN_2_ELSE_0__q78, + IF_theResult___snd52640_BIT_4_THEN_2_ELSE_0__q154, + IF_theResult___snd56709_BIT_33_THEN_2_ELSE_0__q91, + IF_theResult___snd73088_BIT_4_THEN_2_ELSE_0__q187, + IF_theResult___snd84666_BIT_33_THEN_2_ELSE_0__q113, + IF_theResult___snd91493_BIT_4_THEN_2_ELSE_0__q194, + IF_theResult___snd93170_BIT_33_THEN_2_ELSE_0__q43, + carry_out__h127431, + carry_out__h140347, + carry_out__h183608, + carry_out__h202359, + carry_out__h216925, + carry_out__h866988, + carry_out__h867536, + carry_out__h906673, + carry_out__h907221, + carry_out__h995038, coreFix_memExe_dTlbprocResp_BITS_292_TO_291__q6, coreFix_memExe_regToExeQfirst_BITS_223_TO_222__q2, coreFix_memExe_regToExeQfirst_BITS_60_TO_59__q4, - cr_reserved__h866675, - cr_reserved__h867223, - cr_reserved__h906361, - cr_reserved__h906909, - guard__h576464, - guard__h585173, - guard__h594103, - guard__h602939, - guard__h622215, - guard__h630922, - guard__h639852, - guard__h648688, - guard__h667962, - guard__h676669, - guard__h685599, - guard__h694435, - guard__h726326, - guard__h735638, - guard__h744707, - guard__h765179, - guard__h774491, - guard__h783560, - guard__h804483, - guard__h813795, - guard__h822864, - impliedTopBits__h127434, - impliedTopBits__h140350, - impliedTopBits__h183612, - impliedTopBits__h202363, - impliedTopBits__h216929, - impliedTopBits__h866991, - impliedTopBits__h867539, - impliedTopBits__h906677, - impliedTopBits__h907225, - impliedTopBits__h995042, - len_correction__h127433, - len_correction__h140349, - len_correction__h183611, - len_correction__h202362, - len_correction__h216928, - len_correction__h866990, - len_correction__h867538, - len_correction__h906676, - len_correction__h907224, - len_correction__h995041, - prv__h1017409, - prv__h1017453, - r1__read_BITS_13_TO_12___h926454, - sbIdx__h152016, - v__h836642, - v__h836652, - v__h837287, - wordIdx__h263233, - x__h1012282, - x__h1016564, - x__h127518, - x__h140434, - x__h183696, - x__h202447, - x__h217013, - x__h867076, - x__h867624, - x__h906762, - x__h907310, - x__h995126, - y_avValue_snd_snd_snd_fst__h1015804, - y_avValue_snd_snd_snd_fst__h1016386, - y_avValue_snd_snd_snd_fst__h1016415; + cr_reserved__h866674, + cr_reserved__h867222, + cr_reserved__h906359, + cr_reserved__h906907, + guard__h576462, + guard__h585171, + guard__h594101, + guard__h602937, + guard__h622213, + guard__h630920, + guard__h639850, + guard__h648686, + guard__h667960, + guard__h676667, + guard__h685597, + guard__h694433, + guard__h726323, + guard__h735635, + guard__h744704, + guard__h765176, + guard__h774488, + guard__h783557, + guard__h804480, + guard__h813792, + guard__h822861, + impliedTopBits__h127433, + impliedTopBits__h140349, + impliedTopBits__h183610, + impliedTopBits__h202361, + impliedTopBits__h216927, + impliedTopBits__h866990, + impliedTopBits__h867538, + impliedTopBits__h906675, + impliedTopBits__h907223, + impliedTopBits__h995040, + len_correction__h127432, + len_correction__h140348, + len_correction__h183609, + len_correction__h202360, + len_correction__h216926, + len_correction__h866989, + len_correction__h867537, + len_correction__h906674, + len_correction__h907222, + len_correction__h995039, + prv__h1017444, + prv__h1017488, + r1__read_BITS_13_TO_12___h926452, + sbIdx__h152015, + v__h836639, + v__h836649, + v__h837284, + wordIdx__h263231, + x__h1012317, + x__h1016599, + x__h127517, + x__h140433, + x__h183694, + x__h202445, + x__h217011, + x__h867075, + x__h867623, + x__h906760, + x__h907308, + x__h995124, + y_avValue_snd_snd_snd_fst__h1015839, + y_avValue_snd_snd_snd_fst__h1016421, + y_avValue_snd_snd_snd_fst__h1016450; wire IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d10589, IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d10639, IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d11986, @@ -6062,13 +6065,13 @@ module mkCore(CLK, IF_IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_w_ETC___d7806, IF_IF_fetchStage_pipelines_0_first__0256_BITS__ETC___d21231, IF_IF_fetchStage_pipelines_0_first__0256_BITS__ETC___d21876, - IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23130, - IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23174, - IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23269, - IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23311, - IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23424, - IF_INV_commitStage_commitTrap_2268_BITS_217_TO_ETC___d22661, - IF_INV_commitStage_commitTrap_2268_BITS_217_TO_ETC___d22663, + IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23132, + IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23176, + IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23271, + IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23313, + IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23426, + IF_INV_commitStage_commitTrap_2268_BITS_217_TO_ETC___d22662, + IF_INV_commitStage_commitTrap_2268_BITS_217_TO_ETC___d22664, IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19778, IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19779, IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19781, @@ -6261,7 +6264,7 @@ module mkCore(CLK, IF_NOT_fetchStage_pipelines_0_canDeq__0254_025_ETC___d21829, IF_NOT_fetchStage_pipelines_1_first__0265_BITS_ETC___d21741, IF_NOT_fetchStage_pipelines_1_first__0265_BITS_ETC___d21828, - IF_NOT_rob_deqPort_1_deq_data__3605_BIT_25_360_ETC___d23838, + IF_NOT_rob_deqPort_1_deq_data__3607_BIT_25_360_ETC___d23840, IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d13138, IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d13853, IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d14087, @@ -6380,11 +6383,11 @@ module mkCore(CLK, IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17132, IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17160, IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17227, - IF_csrf_mtcc_reg_read__6198_BITS_149_TO_86_281_ETC___d22840, - IF_csrf_mtcc_reg_read__6198_BITS_149_TO_86_281_ETC___d22843, - IF_csrf_mtcc_reg_read__6198_BITS_149_TO_86_281_ETC___d22865, - IF_csrf_mtcc_reg_read__6198_BITS_149_TO_86_281_ETC___d22868, - IF_csrf_mtcc_reg_read__6198_BIT_86_2807_AND_NO_ETC___d22871, + IF_csrf_mtcc_reg_read__6198_BITS_149_TO_86_281_ETC___d22842, + IF_csrf_mtcc_reg_read__6198_BITS_149_TO_86_281_ETC___d22845, + IF_csrf_mtcc_reg_read__6198_BITS_149_TO_86_281_ETC___d22867, + IF_csrf_mtcc_reg_read__6198_BITS_149_TO_86_281_ETC___d22870, + IF_csrf_mtcc_reg_read__6198_BIT_86_2809_AND_NO_ETC___d22873, IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16087, IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16089, IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16810, @@ -6402,16 +6405,16 @@ module mkCore(CLK, IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17126, IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17154, IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17221, - IF_csrf_stcc_reg_read__6046_BITS_149_TO_86_274_ETC___d22771, - IF_csrf_stcc_reg_read__6046_BITS_149_TO_86_274_ETC___d22774, - IF_csrf_stcc_reg_read__6046_BITS_149_TO_86_274_ETC___d22796, - IF_csrf_stcc_reg_read__6046_BITS_149_TO_86_274_ETC___d22799, - IF_csrf_stcc_reg_read__6046_BIT_86_2736_AND_NO_ETC___d22802, - IF_f_csr_reqs_first__3969_BIT_63_4123_THEN_NOT_ETC___d24133, - IF_f_csr_reqs_first__3969_BIT_63_4123_THEN_NOT_ETC___d24155, - IF_f_csr_reqs_first__3969_BIT_63_4123_THEN_NOT_ETC___d24213, - IF_f_csr_reqs_first__3969_BIT_63_4123_THEN_NOT_ETC___d24233, - IF_f_csr_reqs_first__3969_BIT_63_4123_THEN_NOT_ETC___d24304, + IF_csrf_stcc_reg_read__6046_BITS_149_TO_86_274_ETC___d22773, + IF_csrf_stcc_reg_read__6046_BITS_149_TO_86_274_ETC___d22776, + IF_csrf_stcc_reg_read__6046_BITS_149_TO_86_274_ETC___d22798, + IF_csrf_stcc_reg_read__6046_BITS_149_TO_86_274_ETC___d22801, + IF_csrf_stcc_reg_read__6046_BIT_86_2738_AND_NO_ETC___d22804, + IF_f_csr_reqs_first__3971_BIT_63_4125_THEN_NOT_ETC___d24135, + IF_f_csr_reqs_first__3971_BIT_63_4125_THEN_NOT_ETC___d24157, + IF_f_csr_reqs_first__3971_BIT_63_4125_THEN_NOT_ETC___d24215, + IF_f_csr_reqs_first__3971_BIT_63_4125_THEN_NOT_ETC___d24235, + IF_f_csr_reqs_first__3971_BIT_63_4125_THEN_NOT_ETC___d24306, IF_fetchStage_RDY_pipelines_0_first__0253_AND__ETC___d21186, IF_fetchStage_RDY_pipelines_1_first__0264_AND__ETC___d21743, IF_fetchStage_RDY_pipelines_1_first__0264_AND__ETC___d21818, @@ -6438,12 +6441,12 @@ module mkCore(CLK, IF_mmio_dataRespQ_enqReq_lat_1_whas__73_THEN_m_ETC___d182, IF_mmio_pRqQ_enqReq_lat_1_whas__56_THEN_mmio_p_ETC___d565, IF_mmio_pRsQ_enqReq_lat_1_whas__15_THEN_mmio_p_ETC___d424, - IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23133, - IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23179, - IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23272, - IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23316, - IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23430, - IF_rob_deqPort_1_canDeq__3602_THEN_IF_NOT_rob__ETC___d23839, + IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23135, + IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23181, + IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23274, + IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23318, + IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23432, + IF_rob_deqPort_1_canDeq__3604_THEN_IF_NOT_rob__ETC___d23841, IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18759, IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18859, IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18872, @@ -6525,7 +6528,7 @@ module mkCore(CLK, NOT_IF_IF_NOT_csrf_prv_reg_read__0286_EQ_3_028_ETC___d21068, NOT_IF_IF_NOT_csrf_prv_reg_read__0286_EQ_3_028_ETC___d21173, NOT_IF_IF_NOT_csrf_prv_reg_read__0286_EQ_3_028_ETC___d21631, - NOT_IF_NOT_rob_deqPort_0_canDeq__3598_3599_OR__ETC___d23844, + NOT_IF_NOT_rob_deqPort_0_canDeq__3600_3601_OR__ETC___d23846, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d12707, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d13437, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d14207, @@ -6539,11 +6542,11 @@ module mkCore(CLK, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15115, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15144, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15157, - NOT_IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN__ETC___d23314, - NOT_IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN__ETC___d23177, + NOT_IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN__ETC___d23316, + NOT_IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN__ETC___d23179, NOT_commitStage_commitTrap_2268_BITS_44_TO_43__ETC___d22534, NOT_commitStage_commitTrap_2268_BITS_44_TO_43__ETC___d22535, - NOT_commitStage_rg_run_state_2266_2267_AND_NOT_ETC___d23033, + NOT_commitStage_rg_run_state_2266_2267_AND_NOT_ETC___d23035, NOT_coreFix_aluExe_0_bypassWire_0_whas__8403_8_ETC___d18430, NOT_coreFix_aluExe_0_bypassWire_0_whas__8403_8_ETC___d18458, NOT_coreFix_aluExe_0_exeToFinQ_first__9946_BIT_ETC___d19993, @@ -6589,10 +6592,10 @@ module mkCore(CLK, NOT_csrf_fs_reg_read__6010_EQ_0_0640_0641_OR_N_ETC___d21066, NOT_csrf_fs_reg_read__6010_EQ_0_0640_0641_OR_N_ETC___d21171, NOT_csrf_fs_reg_read__6010_EQ_0_0640_0641_OR_N_ETC___d21629, - NOT_csrf_mtcc_reg_read__6198_BITS_33_TO_28_621_ETC___d22810, - NOT_csrf_prv_reg_read__0286_ULE_1_2614_2729_OR_ETC___d22734, - NOT_csrf_rg_dpc_read__6343_BITS_33_TO_28_6360__ETC___d23427, - NOT_csrf_stcc_reg_read__6046_BITS_33_TO_28_606_ETC___d22739, + NOT_csrf_mtcc_reg_read__6198_BITS_33_TO_28_621_ETC___d22812, + NOT_csrf_prv_reg_read__0286_ULE_1_2614_2730_OR_ETC___d22736, + NOT_csrf_rg_dpc_read__6343_BITS_33_TO_28_6360__ETC___d23429, + NOT_csrf_stcc_reg_read__6046_BITS_33_TO_28_606_ETC___d22741, NOT_fetchStage_pipelines_0_canDeq__0254_0255_O_ETC___d21283, NOT_fetchStage_pipelines_0_canDeq__0254_0255_O_ETC___d21723, NOT_fetchStage_pipelines_0_canDeq__0254_0255_O_ETC___d21792, @@ -6631,10 +6634,10 @@ module mkCore(CLK, NOT_renameStage_rg_m_halt_req_0283_BIT_4_0284__ETC___d21178, NOT_renameStage_rg_m_halt_req_0283_BIT_4_0284__ETC___d21789, NOT_renameStage_rg_m_halt_req_0283_BIT_4_0284__ETC___d21809, - NOT_rob_deqPort_0_canDeq__3598_3599_OR_rob_RDY_ETC___d23639, - NOT_rob_deqPort_0_canDeq__3598_3599_OR_rob_deq_ETC___d23818, - NOT_rob_deqPort_0_deq_data__2261_BITS_469_TO_4_ETC___d23022, - NOT_rob_deqPort_1_deq_data__3605_BIT_25_3606_3_ETC___d23636, + NOT_rob_deqPort_0_canDeq__3600_3601_OR_regRena_ETC___d23641, + NOT_rob_deqPort_0_canDeq__3600_3601_OR_rob_deq_ETC___d23820, + NOT_rob_deqPort_0_deq_data__2261_BITS_469_TO_4_ETC___d23024, + NOT_rob_deqPort_1_deq_data__3607_BIT_25_3608_3_ETC___d23638, NOT_specTagManager_canClaim__1149_1248_OR_NOT__ETC___d21921, NOT_specTagManager_canClaim__1149_1248_OR_NOT__ETC___d21990, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12798, @@ -6670,15 +6673,15 @@ module mkCore(CLK, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d11790, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d8603, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d8996, - _0_CONCAT_csrf_mtcc_reg_read__6198_BITS_149_TO__ETC___d22832, - _0_CONCAT_csrf_mtcc_reg_read__6198_BITS_149_TO__ETC___d22857, - _0_CONCAT_csrf_stcc_reg_read__6046_BITS_149_TO__ETC___d22763, - _0_CONCAT_csrf_stcc_reg_read__6046_BITS_149_TO__ETC___d22788, + _0_CONCAT_csrf_mtcc_reg_read__6198_BITS_149_TO__ETC___d22834, + _0_CONCAT_csrf_mtcc_reg_read__6198_BITS_149_TO__ETC___d22859, + _0_CONCAT_csrf_stcc_reg_read__6046_BITS_149_TO__ETC___d22765, + _0_CONCAT_csrf_stcc_reg_read__6046_BITS_149_TO__ETC___d22790, _0_OR_NOT_fetchStage_pipelines_0_first__0256_BI_ETC___d21841, _0_OR_NOT_fetchStage_pipelines_1_first__0265_BI_ETC___d21739, _0_OR_NOT_fetchStage_pipelines_1_first__0265_BI_ETC___d21934, _0b0_CONCAT_csrf_medeleg_28_26_reg_read__6161_6_ETC___d22642, - _0b0_CONCAT_csrf_mideleg_11_reg_read__6172_6173_ETC___d22644, + _0b0_CONCAT_csrf_mideleg_11_reg_read__6172_6173_ETC___d22645, _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10709, _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10734, _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10761, @@ -6733,12 +6736,12 @@ module mkCore(CLK, _dor1sbAggr$EN_setReady_3_put, _dor1sbCons$EN_setReady_0_put, _dor1sbCons$EN_setReady_1_put, - _theResult_____2__h526145, - _theResult_____2__h533238, - _theResult_____2__h543873, - _theResult_____2__h557706, - _theResult_____2__h561485, - cause_interrupt__h995318, + _theResult_____2__h526143, + _theResult_____2__h533236, + _theResult_____2__h543871, + _theResult_____2__h557704, + _theResult_____2__h561483, + cause_interrupt__h995316, commitStage_commitTrap_2268_BITS_44_TO_43_2461_ETC___d22501, commitStage_commitTrap_2268_BITS_44_TO_43_2461_ETC___d22508, commitStage_commitTrap_2268_BITS_44_TO_43_2461_ETC___d22613, @@ -7121,11 +7124,11 @@ module mkCore(CLK, coreFix_memExe_regToExeQ_first__645_BITS_259_T_ETC___d4110, coreFix_memExe_regToExeQ_first__645_BITS_265_T_ETC___d3717, coreFix_memExe_regToExeQ_first__645_BITS_383_T_ETC___d4113, - coreFix_memExe_stb_isEmpty__186_AND_coreFix_me_ETC___d23027, - cr_flags__h866674, - cr_flags__h867222, - cr_flags__h906360, - cr_flags__h906908, + coreFix_memExe_stb_isEmpty__186_AND_coreFix_me_ETC___d23029, + cr_flags__h866673, + cr_flags__h867221, + cr_flags__h906358, + cr_flags__h906906, csrf_ddc_reg_read__051_BITS_13_TO_11_140_ULT_c_ETC___d4144, csrf_ddc_reg_read__051_BITS_27_TO_25_142_ULT_c_ETC___d4143, csrf_ddc_reg_read__051_BITS_85_TO_83_145_ULT_c_ETC___d4146, @@ -7133,23 +7136,23 @@ module mkCore(CLK, csrf_fs_reg_read__6010_EQ_0_0640_AND_fetchStag_ETC___d21258, csrf_fs_reg_read__6010_EQ_0_0640_AND_fetchStag_ETC___d21700, csrf_mtcc_reg_read__6198_BITS_13_TO_11_6201_UL_ETC___d16203, - csrf_mtcc_reg_read__6198_BITS_149_TO_86_2811_A_ETC___d22821, - csrf_mtcc_reg_read__6198_BITS_149_TO_86_2811_A_ETC___d22849, + csrf_mtcc_reg_read__6198_BITS_149_TO_86_2813_A_ETC___d22823, + csrf_mtcc_reg_read__6198_BITS_149_TO_86_2813_A_ETC___d22851, csrf_mtcc_reg_read__6198_BITS_85_TO_83_6204_UL_ETC___d16205, - csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22647, + csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22648, csrf_prv_reg_read__0286_ULE_1___d22614, csrf_rg_dpc_read__6343_BITS_13_TO_11_6346_ULT__ETC___d16348, csrf_rg_dpc_read__6343_BITS_85_TO_83_6349_ULT__ETC___d16350, csrf_stcc_reg_read__6046_BITS_13_TO_11_6049_UL_ETC___d16051, - csrf_stcc_reg_read__6046_BITS_149_TO_86_2740_A_ETC___d22752, - csrf_stcc_reg_read__6046_BITS_149_TO_86_2740_A_ETC___d22780, + csrf_stcc_reg_read__6046_BITS_149_TO_86_2742_A_ETC___d22754, + csrf_stcc_reg_read__6046_BITS_149_TO_86_2742_A_ETC___d22782, csrf_stcc_reg_read__6046_BITS_85_TO_83_6052_UL_ETC___d16053, - f_csr_reqs_first__3969_BITS_63_TO_14_4122_XOR__ETC___d24136, - f_csr_reqs_first__3969_BITS_63_TO_14_4122_XOR__ETC___d24158, - f_csr_reqs_first__3969_BITS_63_TO_14_4122_XOR__ETC___d24216, - f_csr_reqs_first__3969_BITS_63_TO_14_4122_XOR__ETC___d24236, - f_csr_reqs_first__3969_BITS_63_TO_14_4122_XOR__ETC___d24307, - f_csr_rsps_i_notFull__3967_AND_f_csr_reqs_firs_ETC___d24072, + f_csr_reqs_first__3971_BITS_63_TO_14_4124_XOR__ETC___d24138, + f_csr_reqs_first__3971_BITS_63_TO_14_4124_XOR__ETC___d24160, + f_csr_reqs_first__3971_BITS_63_TO_14_4124_XOR__ETC___d24218, + f_csr_reqs_first__3971_BITS_63_TO_14_4124_XOR__ETC___d24238, + f_csr_reqs_first__3971_BITS_63_TO_14_4124_XOR__ETC___d24309, + f_csr_rsps_i_notFull__3969_AND_f_csr_reqs_firs_ETC___d24074, fetchStage_RDY_pipelines_0_first__0253_AND_fet_ETC___d21254, fetchStage_RDY_pipelines_1_deq__0268_AND_NOT_f_ETC___d21994, fetchStage_pipelines_0_canDeq__0254_AND_NOT_fe_ETC___d21932, @@ -7177,29 +7180,29 @@ module mkCore(CLK, fetchStage_pipelines_1_first__0265_BITS_268_TO_ETC___d21888, fetchStage_pipelines_1_first__0265_BITS_268_TO_ETC___d22174, fetchStage_pipelines_1_first__0265_BITS_273_TO_ETC___d21899, - guard__h594701, - guard__h640450, - guard__h686197, - guard__h736236, - guard__h775089, - guard__h814393, - idx__h968880, - k__h945030, + guard__h594699, + guard__h640448, + guard__h686195, + guard__h736233, + guard__h775086, + guard__h814390, + idx__h968878, + k__h945028, mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d20679, mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d21071, mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d21091, mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d22008, mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d22010, - next_deqP___1__h526390, - next_deqP___1__h533668, - next_deqP___1__h544303, - next_deqP___1__h557951, - next_deqP___1__h561730, - r1__read_BIT_20___h926960, - r__h853139, - r__h855583, - regRenamingTable_RDY_rename_0_claimRename__102_ETC___d21039, - regRenamingTable_RDY_rename_0_getRename__1027__ETC___d21854, + next_deqP___1__h526388, + next_deqP___1__h533666, + next_deqP___1__h544301, + next_deqP___1__h557949, + next_deqP___1__h561728, + r1__read_BIT_20___h926958, + r__h853138, + r__h855582, + regRenamingTable_RDY_rename_0_getRename__1028__ETC___d21039, + regRenamingTable_RDY_rename_0_getRename__1028__ETC___d21854, regRenamingTable_rename_0_canRename__1151_AND__ETC___d21180, regRenamingTable_rename_0_canRename__1151_AND__ETC___d21245, regRenamingTable_rename_0_canRename__1151_AND__ETC___d21249, @@ -7236,25 +7239,26 @@ module mkCore(CLK, rf_read_3_rd2_coreFix_memExe_dispToRegQ_first__ETC___d3592, rf_read_3_rd2_coreFix_memExe_dispToRegQ_first__ETC___d3600, rf_read_3_rd2_coreFix_memExe_dispToRegQ_first__ETC___d3609, - rg_core_run_state_read__0682_EQ_2_0683_AND_NOT_ETC___d23893, + rg_core_run_state_read__0682_EQ_2_0683_AND_NOT_ETC___d23895, rob_enqPort_1_canEnq__1634_AND_epochManager_ch_ETC___d21639, sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d12442, sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d12443, sbCons_lazyLookup_3_get_coreFix_memExe_dispToR_ETC___d2768, - v__h516844, - v__h517224, - v__h532563, - v__h532758, - v__h535012, - v__h535207, - v__h556032, - v__h556227, - v__h559811, - v__h560006, - x__h240141, - x__h241298, - x__h254922, - x__h836143; + v__h516842, + v__h517222, + v__h532561, + v__h532756, + v__h535010, + v__h535205, + v__h556030, + v__h556225, + v__h559809, + v__h560004, + value_BIT_52___h677325, + x__h240138, + x__h241295, + x__h254919, + x__h836140; // action method coreReq_start assign RDY_coreReq_start = !renameStage_rg_m_halt_req[4] ; @@ -7292,10 +7296,10 @@ module mkCore(CLK, // value method dCacheToParent_rsToP_first assign dCacheToParent_rsToP_first = - { CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q311, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q312, - !CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q313, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d24448 } ; + { CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q313, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q314, + !CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q315, + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d24450 } ; assign RDY_dCacheToParent_rsToP_first = !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty ; @@ -7313,9 +7317,9 @@ module mkCore(CLK, // value method dCacheToParent_rqToP_first assign dCacheToParent_rqToP_first = - { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q319, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q320, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d24474 } ; + { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q321, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q322, + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d24476 } ; assign RDY_dCacheToParent_rqToP_first = !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty ; @@ -9178,32 +9182,32 @@ module mkCore(CLK, // rule RL_sendDTlbReq assign CAN_FIRE_RL_sendDTlbReq = - coreFix_memExe_dTlb$RDY_toParent_rqToP_deq && coreFix_memExe_dTlb$RDY_toParent_rqToP_first && + coreFix_memExe_dTlb$RDY_toParent_rqToP_deq && l2Tlb$RDY_toChildren_rqFromC_put ; assign WILL_FIRE_RL_sendDTlbReq = CAN_FIRE_RL_sendDTlbReq ; // rule RL_sendITlbReq assign CAN_FIRE_RL_sendITlbReq = - fetchStage$RDY_iTlbIfc_toParent_rqToP_deq && + l2Tlb$RDY_toChildren_rqFromC_put && fetchStage$RDY_iTlbIfc_toParent_rqToP_first && - l2Tlb$RDY_toChildren_rqFromC_put ; + fetchStage$RDY_iTlbIfc_toParent_rqToP_deq ; assign WILL_FIRE_RL_sendITlbReq = CAN_FIRE_RL_sendITlbReq && !WILL_FIRE_RL_sendDTlbReq ; // rule RL_sendRsToDTlb assign CAN_FIRE_RL_sendRsToDTlb = - l2Tlb$RDY_toChildren_rsToC_deq && l2Tlb$RDY_toChildren_rsToC_first && + l2Tlb$RDY_toChildren_rsToC_deq && coreFix_memExe_dTlb$RDY_toParent_ldTransRsFromP_enq && l2Tlb$toChildren_rsToC_first[83] ; assign WILL_FIRE_RL_sendRsToDTlb = CAN_FIRE_RL_sendRsToDTlb ; // rule RL_sendRsToITlb assign CAN_FIRE_RL_sendRsToITlb = - fetchStage$RDY_iTlbIfc_toParent_rsFromP_enq && - l2Tlb$RDY_toChildren_rsToC_deq && l2Tlb$RDY_toChildren_rsToC_first && + l2Tlb$RDY_toChildren_rsToC_deq && + fetchStage$RDY_iTlbIfc_toParent_rsFromP_enq && !l2Tlb$toChildren_rsToC_first[83] ; assign WILL_FIRE_RL_sendRsToITlb = CAN_FIRE_RL_sendRsToITlb ; @@ -9215,16 +9219,16 @@ module mkCore(CLK, // rule RL_mkConnectionGetPut_1 assign CAN_FIRE_RL_mkConnectionGetPut_1 = - fetchStage$RDY_iTlbIfc_toParent_flush_request_get && - l2Tlb$RDY_toChildren_iTlbReqFlush_put ; + l2Tlb$RDY_toChildren_iTlbReqFlush_put && + fetchStage$RDY_iTlbIfc_toParent_flush_request_get ; assign WILL_FIRE_RL_mkConnectionGetPut_1 = CAN_FIRE_RL_mkConnectionGetPut_1 ; // rule RL_sendFlushDone assign CAN_FIRE_RL_sendFlushDone = - fetchStage$RDY_iTlbIfc_toParent_flush_response_put && coreFix_memExe_dTlb$RDY_toParent_flush_response_put && - l2Tlb$RDY_toChildren_flushDone_get ; + l2Tlb$RDY_toChildren_flushDone_get && + fetchStage$RDY_iTlbIfc_toParent_flush_response_put ; assign WILL_FIRE_RL_sendFlushDone = CAN_FIRE_RL_sendFlushDone ; // rule RL_sendRobEnqTime @@ -9245,7 +9249,7 @@ module mkCore(CLK, // rule RL_readyToFetch assign CAN_FIRE_RL_readyToFetch = fetchStage$RDY_done_flushing && - rg_core_run_state_read__0682_EQ_2_0683_AND_NOT_ETC___d23893 && + rg_core_run_state_read__0682_EQ_2_0683_AND_NOT_ETC___d23895 && !flush_brpred && fetchStage$iMemIfc_flush_done && fetchStage$flush_predictors_done ; @@ -9373,9 +9377,9 @@ module mkCore(CLK, // rule RL_mmio_sendInstReq assign CAN_FIRE_RL_mmio_sendInstReq = - !mmio_cRqQ_full && fetchStage$RDY_mmioIfc_instReq_deq && + !mmio_cRqQ_full && fetchStage$RDY_mmioIfc_instReq_first_snd && fetchStage$RDY_mmioIfc_instReq_first_fst && - fetchStage$RDY_mmioIfc_instReq_first_snd ; + fetchStage$RDY_mmioIfc_instReq_deq ; assign WILL_FIRE_RL_mmio_sendInstReq = CAN_FIRE_RL_mmio_sendInstReq && !WILL_FIRE_RL_mmio_sendDataReq ; @@ -9456,16 +9460,16 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doDeqLdQ_fault assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_fault = - rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_firstLd && - coreFix_memExe_lsq$RDY_deqLd && + rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_deqLd && + coreFix_memExe_lsq$RDY_firstLd && coreFix_memExe_lsq$firstLd[16] ; assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault = CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ; // rule RL_coreFix_memExe_doDeqLdQ_Ld_Mem assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem = - rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_firstLd && - coreFix_memExe_lsq$RDY_deqLd && + rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_deqLd && + coreFix_memExe_lsq$RDY_firstLd && !coreFix_memExe_lsq$firstLd[16] && !coreFix_memExe_lsq$firstLd[126] && !coreFix_memExe_lsq$firstLd[33] ; @@ -9697,7 +9701,7 @@ module mkCore(CLK, // rule RL_commitStage_doCommitTrap_flush assign CAN_FIRE_RL_commitStage_doCommitTrap_flush = - rob$RDY_deqPort_0_deq && rob$RDY_deqPort_0_deq_data && + rob$RDY_deqPort_0_deq_data && rob$RDY_deqPort_0_deq && (rob$deqPort_0_deq_data[12] || epochManager$RDY_incrementEpoch) && !commitStage_rg_run_state && @@ -9750,15 +9754,15 @@ module mkCore(CLK, // rule RL_rl_debug_csr_write assign CAN_FIRE_RL_rl_debug_csr_write = f_csr_reqs$EMPTY_N && - f_csr_rsps_i_notFull__3967_AND_f_csr_reqs_firs_ETC___d24072 && + f_csr_rsps_i_notFull__3969_AND_f_csr_reqs_firs_ETC___d24074 && rg_core_run_state == 2'd1 && f_csr_reqs$D_OUT[76] ; assign WILL_FIRE_RL_rl_debug_csr_write = CAN_FIRE_RL_rl_debug_csr_write ; // rule RL_commitStage_doCommitKilledLd assign CAN_FIRE_RL_commitStage_doCommitKilledLd = - rob$RDY_deqPort_0_deq && rob$RDY_deqPort_0_deq_data && - epochManager$RDY_incrementEpoch && + epochManager$RDY_incrementEpoch && rob$RDY_deqPort_0_deq_data && + rob$RDY_deqPort_0_deq && !commitStage_rg_run_state && !commitStage_commitTrap[238] && !rob$deqPort_0_deq_data[274] && @@ -9788,8 +9792,8 @@ module mkCore(CLK, // rule RL_commitStage_doCommitSystemInst assign CAN_FIRE_RL_commitStage_doCommitSystemInst = - coreFix_memExe_stb_isEmpty__186_AND_coreFix_me_ETC___d23027 && - NOT_commitStage_rg_run_state_2266_2267_AND_NOT_ETC___d23033 && + coreFix_memExe_stb_isEmpty__186_AND_coreFix_me_ETC___d23029 && + NOT_commitStage_rg_run_state_2266_2267_AND_NOT_ETC___d23035 && (rob$deqPort_0_deq_data[469:465] == 5'd0 || rob$deqPort_0_deq_data[469:465] == 5'd26 || rob$deqPort_0_deq_data[469:465] == 5'd22 || @@ -9832,8 +9836,8 @@ module mkCore(CLK, // rule RL_commitStage_doCommitNormalInst assign CAN_FIRE_RL_commitStage_doCommitNormalInst = rob$RDY_deqPort_0_deq_data && - NOT_rob_deqPort_0_canDeq__3598_3599_OR_rob_RDY_ETC___d23639 && - NOT_commitStage_rg_run_state_2266_2267_AND_NOT_ETC___d23033 && + NOT_rob_deqPort_0_canDeq__3600_3601_OR_regRena_ETC___d23641 && + NOT_commitStage_rg_run_state_2266_2267_AND_NOT_ETC___d23035 && rob$deqPort_0_deq_data[469:465] != 5'd0 && rob$deqPort_0_deq_data[469:465] != 5'd26 && rob$deqPort_0_deq_data[469:465] != 5'd22 && @@ -9993,8 +9997,8 @@ module mkCore(CLK, // rule RL_coreFix_aluExe_0_doDispatchAlu assign CAN_FIRE_RL_coreFix_aluExe_0_doDispatchAlu = coreFix_aluExe_0_dispToRegQ$RDY_enq && - coreFix_aluExe_0_rsAlu$RDY_dispatchData && - coreFix_aluExe_0_rsAlu$RDY_doDispatch ; + coreFix_aluExe_0_rsAlu$RDY_doDispatch && + coreFix_aluExe_0_rsAlu$RDY_dispatchData ; assign WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu = CAN_FIRE_RL_coreFix_aluExe_0_doDispatchAlu && !WILL_FIRE_RL_commitStage_doCommitKilledLd && @@ -10005,8 +10009,8 @@ module mkCore(CLK, // rule RL_coreFix_aluExe_1_doDispatchAlu assign CAN_FIRE_RL_coreFix_aluExe_1_doDispatchAlu = coreFix_aluExe_1_dispToRegQ$RDY_enq && - coreFix_aluExe_1_rsAlu$RDY_dispatchData && - coreFix_aluExe_1_rsAlu$RDY_doDispatch ; + coreFix_aluExe_1_rsAlu$RDY_doDispatch && + coreFix_aluExe_1_rsAlu$RDY_dispatchData ; assign WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu = CAN_FIRE_RL_coreFix_aluExe_1_doDispatchAlu && !WILL_FIRE_RL_commitStage_doCommitKilledLd && @@ -10018,8 +10022,8 @@ module mkCore(CLK, assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq = !coreFix_memExe_respLrScAmoQ_empty && rob$RDY_setExecuted_deqLSQ && - coreFix_memExe_lsq$RDY_firstLd && coreFix_memExe_lsq$RDY_deqLd && + coreFix_memExe_lsq$RDY_firstLd && coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd1 ; assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq = CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && @@ -10043,8 +10047,8 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doFinishMem assign CAN_FIRE_RL_coreFix_memExe_doFinishMem = rob$RDY_setExecuted_doFinishMem && - coreFix_memExe_dTlb$RDY_procResp && - coreFix_memExe_dTlb$RDY_deqProcResp ; + coreFix_memExe_dTlb$RDY_deqProcResp && + coreFix_memExe_dTlb$RDY_procResp ; assign WILL_FIRE_RL_coreFix_memExe_doFinishMem = CAN_FIRE_RL_coreFix_memExe_doFinishMem ; @@ -10132,16 +10136,16 @@ module mkCore(CLK, // rule RL_prepareCachesAndTlbs assign CAN_FIRE_RL_prepareCachesAndTlbs = (!flush_tlbs || - fetchStage$RDY_iTlbIfc_flush && - coreFix_memExe_dTlb$RDY_flush) && + coreFix_memExe_dTlb$RDY_flush && + fetchStage$RDY_iTlbIfc_flush) && (flush_reservation || flush_tlbs || update_vm_info) ; assign WILL_FIRE_RL_prepareCachesAndTlbs = CAN_FIRE_RL_prepareCachesAndTlbs ; // rule RL_rl_debug_resume assign CAN_FIRE_RL_rl_debug_resume = - commitStage_rg_run_state && fetchStage$RDY_iTlbIfc_flush && - coreFix_memExe_dTlb$RDY_flush && + commitStage_rg_run_state && coreFix_memExe_dTlb$RDY_flush && + fetchStage$RDY_iTlbIfc_flush && f_run_halt_reqs$EMPTY_N && f_run_halt_rsps$FULL_N && rg_core_run_state == 2'd1 && @@ -10149,9 +10153,7 @@ module mkCore(CLK, !f_gpr_reqs$EMPTY_N && !f_fpr_reqs$EMPTY_N && !f_csr_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_debug_resume = - CAN_FIRE_RL_rl_debug_resume && - !WILL_FIRE_RL_prepareCachesAndTlbs ; + assign WILL_FIRE_RL_rl_debug_resume = MUX_started$write_1__SEL_1 ; // rule RL_coreFix_memExe_doRegReadMem assign CAN_FIRE_RL_coreFix_memExe_doRegReadMem = @@ -10169,8 +10171,8 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doDispatchMem assign CAN_FIRE_RL_coreFix_memExe_doDispatchMem = coreFix_memExe_dispToRegQ$RDY_enq && - coreFix_memExe_rsMem$RDY_dispatchData && - coreFix_memExe_rsMem$RDY_doDispatch ; + coreFix_memExe_rsMem$RDY_doDispatch && + coreFix_memExe_rsMem$RDY_dispatchData ; assign WILL_FIRE_RL_coreFix_memExe_doDispatchMem = CAN_FIRE_RL_coreFix_memExe_doDispatchMem && !WILL_FIRE_RL_commitStage_doCommitKilledLd && @@ -10305,8 +10307,8 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doDeqStQ_fault assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_fault = - rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_firstSt && - coreFix_memExe_lsq$RDY_deqSt && + rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_deqSt && + coreFix_memExe_lsq$RDY_firstSt && coreFix_memExe_lsq$firstSt[13] ; assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault = CAN_FIRE_RL_coreFix_memExe_doDeqStQ_fault && @@ -10328,8 +10330,8 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doDeqStQ_Fence assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_Fence = - rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_firstSt && - coreFix_memExe_lsq$RDY_deqSt && + rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_deqSt && + coreFix_memExe_lsq$RDY_firstSt && !coreFix_memExe_lsq$firstSt[13] && coreFix_memExe_lsq$firstSt[240:239] == 2'd3 && (!coreFix_memExe_lsq$firstSt[233] || @@ -10356,8 +10358,8 @@ module mkCore(CLK, assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq = !coreFix_memExe_respLrScAmoQ_empty && rob$RDY_setExecuted_deqLSQ && - coreFix_memExe_lsq$RDY_firstSt && coreFix_memExe_lsq$RDY_deqSt && + coreFix_memExe_lsq$RDY_firstSt && coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd2 ; assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq = CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && @@ -10515,8 +10517,8 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doDeqStQ_St_Mem assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem = - coreFix_memExe_stb$RDY_enq && coreFix_memExe_lsq$RDY_firstSt && - coreFix_memExe_lsq$RDY_deqSt && + coreFix_memExe_stb$RDY_enq && coreFix_memExe_lsq$RDY_deqSt && + coreFix_memExe_lsq$RDY_firstSt && !coreFix_memExe_lsq$firstSt[13] && coreFix_memExe_lsq$firstSt[240:239] == 2'd0 && !coreFix_memExe_lsq$firstSt[159] && @@ -10536,7 +10538,7 @@ module mkCore(CLK, !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty && coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_send && coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_getEmptyEntryInit && - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q321 ; + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q323 ; assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer = CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer ; @@ -10565,7 +10567,7 @@ module mkCore(CLK, assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer = !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty && coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_send && - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q322 ; + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q324 ; assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer = CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer ; @@ -10741,8 +10743,8 @@ module mkCore(CLK, // rule RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv = coreFix_fpuMulDivExe_0_dispToRegQ$RDY_enq && - coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_dispatchData && - coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_doDispatch ; + coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_doDispatch && + coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_dispatchData ; assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv = CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv && !WILL_FIRE_RL_commitStage_doCommitKilledLd && @@ -10762,9 +10764,9 @@ module mkCore(CLK, // rule RL_renameStage_doRenaming_Trap assign CAN_FIRE_RL_renameStage_doRenaming_Trap = - rob$RDY_enqPort_0_enq && fetchStage$RDY_pipelines_0_deq && + epochManager$RDY_incrementEpoch && rob$RDY_enqPort_0_enq && fetchStage$RDY_pipelines_0_first && - epochManager$RDY_incrementEpoch && + fetchStage$RDY_pipelines_0_deq && mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d20679 && rob$isEmpty && rg_core_run_state == 2'd2 ; @@ -10777,9 +10779,9 @@ module mkCore(CLK, // rule RL_renameStage_doRenaming_SystemInst assign CAN_FIRE_RL_renameStage_doRenaming_SystemInst = - rob$RDY_enqPort_0_enq && - regRenamingTable$RDY_rename_0_getRename && - regRenamingTable_RDY_rename_0_claimRename__102_ETC___d21039 && + epochManager$RDY_incrementEpoch && + regRenamingTable$RDY_rename_0_claimRename && + regRenamingTable_RDY_rename_0_getRename__1028__ETC___d21039 && mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d21091 && rg_core_run_state == 2'd2 ; assign WILL_FIRE_RL_renameStage_doRenaming_SystemInst = @@ -10880,10 +10882,7 @@ module mkCore(CLK, WILL_FIRE_RL_commitStage_doCommitKilledLd || WILL_FIRE_RL_commitStage_doCommitTrap_flush ; assign MUX_coreFix_aluExe_0_rsAlu$enq_1__SEL_1 = - WILL_FIRE_RL_renameStage_doRenaming_SystemInst && - (fetchStage$pipelines_0_first[268:266] == 3'd0 || - fetchStage$pipelines_0_first[238:237] == 2'd1 || - fetchStage$pipelines_0_first[238:237] == 2'd0) ; + WILL_FIRE_RL_renameStage_doRenaming && _dfoo18 ; assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple && coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] ; @@ -11048,9 +11047,9 @@ module mkCore(CLK, assign MUX_csrf_external_int_en_vec_1$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - (IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + (IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd9 || - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd23) ; assign MUX_csrf_external_int_en_vec_3$write_1__SEL_1 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11058,9 +11057,9 @@ module mkCore(CLK, assign MUX_csrf_external_int_pend_vec_1$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - (IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + (IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd16 || - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd30) ; assign MUX_csrf_external_int_pend_vec_1$write_1__SEL_2 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11068,13 +11067,13 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd836) ; assign MUX_csrf_fflags_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitNormalInst && - NOT_IF_NOT_rob_deqPort_0_canDeq__3598_3599_OR__ETC___d23844 ; + NOT_IF_NOT_rob_deqPort_0_canDeq__3600_3601_OR__ETC___d23846 ; assign MUX_csrf_fflags_reg$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - (IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + (IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd0 || - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd2) ; assign MUX_csrf_fflags_reg$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11083,22 +11082,22 @@ module mkCore(CLK, assign MUX_csrf_frm_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - (IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + (IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd1 || - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd2) ; assign MUX_csrf_fs_reg$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - (IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + (IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd0 || - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd1 || - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd2 || - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd8 || - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd19) ; assign MUX_csrf_fs_reg$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11110,9 +11109,9 @@ module mkCore(CLK, assign MUX_csrf_ie_vec_0$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - (IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + (IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd8 || - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd19) ; assign MUX_csrf_ie_vec_0$write_1__SEL_2 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11123,7 +11122,7 @@ module mkCore(CLK, assign MUX_csrf_ie_vec_1$write_1__SEL_3 = WILL_FIRE_RL_commitStage_doCommitTrap_handle && commitStage_commitTrap_2268_BITS_44_TO_43_2461_ETC___d22613 && - csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22647 ; + csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22648 ; assign MUX_csrf_ie_vec_3$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo30 ; assign MUX_csrf_ie_vec_3$write_1__SEL_2 = @@ -11132,11 +11131,11 @@ module mkCore(CLK, assign MUX_csrf_ie_vec_3$write_1__SEL_3 = WILL_FIRE_RL_commitStage_doCommitTrap_handle && commitStage_commitTrap_2268_BITS_44_TO_43_2461_ETC___d22613 && - NOT_csrf_prv_reg_read__0286_ULE_1_2614_2729_OR_ETC___d22734 ; + NOT_csrf_prv_reg_read__0286_ULE_1_2614_2730_OR_ETC___d22736 ; assign MUX_csrf_mcause_code_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd28 ; assign MUX_csrf_mcause_code_reg$write_1__SEL_2 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11154,8 +11153,7 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd770 ; assign MUX_csrf_mepcc_reg_data_lat_1$wset_1__SEL_1 = - WILL_FIRE_RL_rl_debug_csr_write && - f_csr_reqs$D_OUT[75:64] == 12'd833 ; + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; assign MUX_csrf_mideleg_11_reg$write_1__SEL_1 = WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd771 ; @@ -11168,12 +11166,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd832 ; assign MUX_csrf_mtcc_reg$write_1__SEL_1 = - WILL_FIRE_RL_rl_debug_csr_write && - f_csr_reqs$D_OUT[75:64] == 12'd773 ; + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 ; assign MUX_csrf_mtval_csr$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd29 ; assign MUX_csrf_mtval_csr$write_1__SEL_2 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11193,12 +11190,12 @@ module mkCore(CLK, assign MUX_csrf_rg_dcsr$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd42 ; assign MUX_csrf_rg_dpc$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd43 ; assign MUX_csrf_rg_dpc$write_1__SEL_2 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11224,7 +11221,7 @@ module mkCore(CLK, assign MUX_csrf_scause_code_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd14 ; assign MUX_csrf_scause_code_reg$write_1__SEL_2 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11233,8 +11230,7 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd262 ; assign MUX_csrf_sepcc_reg_data_lat_1$wset_1__SEL_1 = - WILL_FIRE_RL_rl_debug_csr_write && - f_csr_reqs$D_OUT[75:64] == 12'd321 ; + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo36 ; assign MUX_csrf_spp_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo40 ; assign MUX_csrf_sscratch_csr$write_1__SEL_1 = @@ -11244,12 +11240,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd2049 ; assign MUX_csrf_stcc_reg$write_1__SEL_1 = - WILL_FIRE_RL_rl_debug_csr_write && - f_csr_reqs$D_OUT[75:64] == 12'd261 ; + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo38 ; assign MUX_csrf_stval_csr$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd15 ; assign MUX_csrf_stval_csr$write_1__SEL_2 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11267,7 +11262,7 @@ module mkCore(CLK, assign MUX_f_run_halt_rsps$enq_1__SEL_1 = WILL_FIRE_RL_rl_debug_halted || WILL_FIRE_RL_rl_debug_halt_req_already_halted ; - assign MUX_flush_reservation$write_1__SEL_1 = + assign MUX_flush_reservation$write_1__SEL_2 = WILL_FIRE_RL_prepareCachesAndTlbs && flush_reservation ; assign MUX_flush_tlbs$write_1__SEL_1 = WILL_FIRE_RL_prepareCachesAndTlbs && flush_tlbs ; @@ -11320,6 +11315,9 @@ module mkCore(CLK, coreFix_memExe_lsq$firstLd[106] ; assign MUX_sbCons$setReady_3_put_1__SEL_3 = MUX_rf$write_3_wr_1__PSEL_5 && coreFix_memExe_lsq$respLd[137] ; + assign MUX_started$write_1__SEL_1 = + CAN_FIRE_RL_rl_debug_resume && + !WILL_FIRE_RL_prepareCachesAndTlbs ; assign MUX_regRenamingTable$rename_0_getRename_1__VAL_2 = { 2'd2, f_gpr_reqs$D_OUT[68:64], 20'd345386 } ; assign MUX_regRenamingTable$rename_0_getRename_1__VAL_3 = @@ -11327,25 +11325,15 @@ module mkCore(CLK, assign MUX_commitStage_commitTrap$write_1__VAL_2 = { 1'd1, rob$deqPort_0_deq_data[630:502], - addr__h989736, - CASE_robdeqPort_0_deq_data_BITS_273_TO_272_0__ETC__q326, + addr__h989734, + CASE_robdeqPort_0_deq_data_BITS_273_TO_272_0__ETC__q328, rob$deqPort_0_deq_data[501:470] } ; - assign MUX_commitStage_rg_serial_num$write_1__VAL_2 = + assign MUX_commitStage_rg_serial_num$write_1__VAL_1 = commitStage_rg_serial_num + 64'd1 ; assign MUX_commitStage_rg_serial_num$write_1__VAL_3 = - commitStage_rg_serial_num + y__h1016339 ; + commitStage_rg_serial_num + y__h1016374 ; assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_1 = - { fetchStage$pipelines_0_first[273:269], - IF_fetchStage_pipelines_0_first__0256_BITS_268_ETC___d20382, - IF_fetchStage_pipelines_0_first__0256_BITS_238_ETC___d20622, - fetchStage$pipelines_0_first[329:306], - regRenamingTable$rename_0_getRename, - rob$enqPort_0_getEnqInstTag, - specTagManager$currentSpecBits, - 5'd10, - sbAggr$eagerLookup_0_get } ; - assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_2 = - (k__h945030 == 1'd0 && fetchStage$pipelines_0_canDeq && + (k__h945028 == 1'd0 && fetchStage$pipelines_0_canDeq && NOT_fetchStage_pipelines_0_first__0256_BITS_26_ETC___d22015) ? { fetchStage$pipelines_0_first[273:269], IF_fetchStage_pipelines_0_first__0256_BITS_268_ETC___d20382, @@ -11363,10 +11351,20 @@ module mkCore(CLK, fetchStage$pipelines_1_first[329:306], regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h968741, + renaming_spec_bits__h968739, fetchStage$pipelines_1_first[268:266] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; + assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_2 = + { fetchStage$pipelines_0_first[273:269], + IF_fetchStage_pipelines_0_first__0256_BITS_268_ETC___d20382, + IF_fetchStage_pipelines_0_first__0256_BITS_238_ETC___d20622, + fetchStage$pipelines_0_first[329:306], + regRenamingTable$rename_0_getRename, + rob$enqPort_0_getEnqInstTag, + specTagManager$currentSpecBits, + 5'd10, + sbAggr$eagerLookup_0_get } ; assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1 = { 1'd1, coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[31:25] } ; assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2 = @@ -11461,7 +11459,7 @@ module mkCore(CLK, assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_1 = { 521'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq[221:158], - x__h501097 } ; + x__h501096 } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_2 = { 521'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d7036 } ; @@ -11471,7 +11469,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_4 = { 2'd2, - addr__h505615, + addr__h505614, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d7144 } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_1 = { 1'd1, @@ -11488,12 +11486,12 @@ module mkCore(CLK, coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget : coreFix_memExe_reqLrScAmoQ_data_0_rl ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_2 = - { x__h148991, - addr__h148439, + { x__h148990, + addr__h148438, 158'h20AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_3 = - { x__h152125, - addr__h152015, + { x__h152124, + addr__h152014, 158'h32AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_1 = { 1'd1, @@ -11503,7 +11501,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[581:579] } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_1 = { 1'd1, - resp_addr__h509111, + resp_addr__h509110, 2'd0, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getData } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_2 = @@ -11511,8 +11509,8 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getRq, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getData } ; assign MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1 = - { prv__h1017453, - prv__h1017453 != 2'd3 && csrf_vm_mode_sv39_reg, + { prv__h1017488, + prv__h1017488 != 2'd3 && csrf_vm_mode_sv39_reg, csrf_mxr_reg, csrf_sum_reg, csrf_ppn_reg } ; @@ -11537,11 +11535,11 @@ module mkCore(CLK, coreFix_memExe_stb$search[128:0] : 129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; assign MUX_coreFix_memExe_lsq$respLd_2__VAL_1 = - { CASE_coreFix_memExe_memRespLdQ_deqP_0_coreFix__ETC__q327, + { CASE_coreFix_memExe_memRespLdQ_deqP_0_coreFix__ETC__q330, SEL_ARR_coreFix_memExe_memRespLdQ_data_0_133_B_ETC___d2147, SEL_ARR_coreFix_memExe_memRespLdQ_data_0_133_B_ETC___d2151 } ; assign MUX_coreFix_memExe_lsq$respLd_2__VAL_2 = - { CASE_coreFix_memExe_forwardQ_deqP_0_coreFix_me_ETC__q328, + { CASE_coreFix_memExe_forwardQ_deqP_0_coreFix_me_ETC__q329, SEL_ARR_coreFix_memExe_forwardQ_data_0_216_BIT_ETC___d2230, SEL_ARR_coreFix_memExe_forwardQ_data_0_216_BIT_ETC___d2234 } ; assign MUX_coreFix_memExe_memRespLdQ_enqReq_lat_0$wset_1__VAL_1 = @@ -11581,55 +11579,55 @@ module mkCore(CLK, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4854, IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d4891 } ; assign MUX_coreFix_trainBPQ_0$enq_1__VAL_1 = - { x__h914620, - new_pc__h912073, + { x__h914618, + new_pc__h912071, coreFix_aluExe_0_exeToFinQ$first[1066:1062], coreFix_aluExe_0_exeToFinQ$first[297], coreFix_aluExe_0_exeToFinQ$first[1040:1017], 1'd0, coreFix_aluExe_0_exeToFinQ$first[1016] } ; assign MUX_coreFix_trainBPQ_0$enq_1__VAL_2 = - { x__h914620, - new_pc__h912073, + { x__h914618, + new_pc__h912071, coreFix_aluExe_0_exeToFinQ$first[1066:1062], coreFix_aluExe_0_exeToFinQ$first[297], coreFix_aluExe_0_exeToFinQ$first[1040:1017], 1'd1, coreFix_aluExe_0_exeToFinQ$first[1016] } ; assign MUX_coreFix_trainBPQ_1$enq_1__VAL_1 = - { x__h879903, - new_pc__h872925, + { x__h879902, + new_pc__h872924, coreFix_aluExe_1_exeToFinQ$first[1066:1062], coreFix_aluExe_1_exeToFinQ$first[297], coreFix_aluExe_1_exeToFinQ$first[1040:1017], 1'd0, coreFix_aluExe_1_exeToFinQ$first[1016] } ; assign MUX_coreFix_trainBPQ_1$enq_1__VAL_2 = - { x__h879903, - new_pc__h872925, + { x__h879902, + new_pc__h872924, coreFix_aluExe_1_exeToFinQ$first[1066:1062], coreFix_aluExe_1_exeToFinQ$first[297], coreFix_aluExe_1_exeToFinQ$first[1040:1017], 1'd1, coreFix_aluExe_1_exeToFinQ$first[1016] } ; assign MUX_csrf_fflags_reg$write_1__VAL_1 = - csrf_fflags_reg | fflags__h1016316 ; + csrf_fflags_reg | fflags__h1016351 ; assign MUX_csrf_frm_reg$write_1__VAL_1 = - (IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + (IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd1) ? - robdeqPort_0_deq_data_BITS_95_TO_32__q16[2:0] : - robdeqPort_0_deq_data_BITS_95_TO_32__q16[7:5] ; + robdeqPort_0_deq_data_BITS_95_TO_32__q17[2:0] : + robdeqPort_0_deq_data_BITS_95_TO_32__q17[7:5] ; assign MUX_csrf_frm_reg$write_1__VAL_2 = (f_csr_reqs$D_OUT[75:64] == 12'd2) ? f_csr_reqs$D_OUT[2:0] : f_csr_reqs$D_OUT[7:5] ; - always@(IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 or - robdeqPort_0_deq_data_BITS_95_TO_32__q16) + always@(IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 or + robdeqPort_0_deq_data_BITS_95_TO_32__q17) begin - case (IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012) + case (IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014) 6'd0, 6'd1, 6'd2: MUX_csrf_fs_reg$write_1__VAL_2 = 2'b11; default: MUX_csrf_fs_reg$write_1__VAL_2 = - robdeqPort_0_deq_data_BITS_95_TO_32__q16[14:13]; + robdeqPort_0_deq_data_BITS_95_TO_32__q17[14:13]; endcase end always@(f_csr_reqs$D_OUT) @@ -11641,163 +11639,163 @@ module mkCore(CLK, end assign MUX_csrf_ie_vec_1$write_1__VAL_1 = (rob$deqPort_0_deq_data[469:465] == 5'd17 && - (IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + (IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd8 || - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd19)) ? - robdeqPort_0_deq_data_BITS_95_TO_32__q16[1] : + robdeqPort_0_deq_data_BITS_95_TO_32__q17[1] : csrf_prev_ie_vec_1 ; assign MUX_csrf_ie_vec_3$write_1__VAL_1 = (rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd19) ? - robdeqPort_0_deq_data_BITS_95_TO_32__q16[3] : + robdeqPort_0_deq_data_BITS_95_TO_32__q17[3] : csrf_prev_ie_vec_3 ; assign MUX_csrf_mccsr_reg$write_1__VAL_1 = { f_csr_reqs$D_OUT[15:10], - CASE_f_csr_reqsD_OUT_BITS_9_TO_5_0_f_csr_reqs_ETC__q329 } ; + CASE_f_csr_reqsD_OUT_BITS_9_TO_5_0_f_csr_reqs_ETC__q331 } ; assign MUX_csrf_mccsr_reg$write_1__VAL_2 = - { robdeqPort_0_deq_data_BITS_95_TO_32__q16[15:10], - CASE_robdeqPort_0_deq_data_BITS_95_TO_326_BITS_ETC__q330 } ; + { robdeqPort_0_deq_data_BITS_95_TO_32__q17[15:10], + CASE_robdeqPort_0_deq_data_BITS_95_TO_327_BITS_ETC__q332 } ; assign MUX_csrf_mepcc_reg_data_lat_1$wset_1__VAL_1 = - { f_csr_reqs_first__3969_BITS_63_TO_14_4122_XOR__ETC___d24236, - result_d_address__h1032840, - result_d_addrBits__h1032841, - IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d23335 } ; - assign MUX_csrf_mepcc_reg_data_lat_1$wset_1__VAL_2 = (rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd27) ? - { IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23316, - result_d_address__h1009789, - result_d_addrBits__h1009790, - IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d23335 } : + { IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23318, + result_d_address__h1009824, + result_d_addrBits__h1009825, + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d23337 } : rob$deqPort_0_deq_data[194:42] ; + assign MUX_csrf_mepcc_reg_data_lat_1$wset_1__VAL_2 = + { f_csr_reqs_first__3971_BITS_63_TO_14_4124_XOR__ETC___d24238, + result_d_address__h1032874, + result_d_addrBits__h1032875, + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d23337 } ; assign MUX_csrf_minstret_ehr_data_lat_0$wset_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ; assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1 = - n__read__h1014112 + 64'd1 ; + n__read__h1014147 + 64'd1 ; assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2 = - n__read__h1014112 + { 62'd0, x__h1016564 } ; + n__read__h1014147 + { 62'd0, x__h1016599 } ; assign MUX_csrf_mpp_reg$write_1__VAL_1 = (rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd19) ? MUX_csrf_minstret_ehr_data_lat_0$wset_1__VAL_2[12:11] : 2'd0 ; assign MUX_csrf_mtcc_reg$write_1__VAL_1 = - { f_csr_reqs_first__3969_BITS_63_TO_14_4122_XOR__ETC___d24216, - result_d_address__h1032437, - result_d_addrBits__h1032438, - csrf_mtcc_reg[71:0] } ; - assign MUX_csrf_mtcc_reg$write_1__VAL_2 = (rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd24) ? - { IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23272, - result_d_address__h1009386, - result_d_addrBits__h1009387, + { IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23274, + result_d_address__h1009421, + result_d_addrBits__h1009422, csrf_mtcc_reg[71:0] } : rob$deqPort_0_deq_data[194:42] ; + assign MUX_csrf_mtcc_reg$write_1__VAL_2 = + { f_csr_reqs_first__3971_BITS_63_TO_14_4124_XOR__ETC___d24218, + result_d_address__h1032471, + result_d_addrBits__h1032472, + csrf_mtcc_reg[71:0] } ; assign MUX_csrf_mtval_csr$write_1__VAL_1 = rob$deqPort_0_deq_data[95:32] ; - always@(commitStage_commitTrap or trap_val__h997040 or trap_val__h996887) + always@(commitStage_commitTrap or trap_val__h997075 or trap_val__h996922) begin case (commitStage_commitTrap[44:43]) - 2'd0: MUX_csrf_mtval_csr$write_1__VAL_3 = trap_val__h997040; - 2'd1: MUX_csrf_mtval_csr$write_1__VAL_3 = trap_val__h996887; + 2'd0: MUX_csrf_mtval_csr$write_1__VAL_3 = trap_val__h997075; + 2'd1: MUX_csrf_mtval_csr$write_1__VAL_3 = trap_val__h996922; default: MUX_csrf_mtval_csr$write_1__VAL_3 = 64'd0; endcase end assign MUX_csrf_prev_ie_vec_1$write_1__VAL_1 = rob$deqPort_0_deq_data[469:465] != 5'd17 || - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 != + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 != 6'd8 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 != + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 != 6'd19 || MUX_csrf_mtval_csr$write_1__VAL_1[5] ; assign MUX_csrf_prev_ie_vec_3$write_1__VAL_1 = rob$deqPort_0_deq_data[469:465] != 5'd17 || - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 != + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 != 6'd19 || MUX_csrf_mtval_csr$write_1__VAL_1[7] ; assign MUX_csrf_prv_reg$write_1__VAL_1 = (rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd42) ? MUX_csrf_mtval_csr$write_1__VAL_1[1:0] : ((rob$deqPort_0_deq_data[469:465] == 5'd24) ? - x__h1012282 : + x__h1012317 : csrf_mpp_reg) ; assign MUX_csrf_prv_reg$write_1__VAL_3 = - csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22647 ? + csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22648 ? 2'd1 : 2'd3 ; assign MUX_csrf_rg_dcsr$write_1__VAL_1 = rob$deqPort_0_deq_data[95:32] ; assign MUX_csrf_rg_dcsr$write_1__VAL_3 = { 32'b0, csrf_rg_dcsr[31:9], - dcsr_cause__h994364, + dcsr_cause__h994362, csrf_rg_dcsr[5:2], csrf_prv_reg } ; assign MUX_csrf_rg_dpc$write_1__VAL_1 = - { IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23430, - result_d_address__h1010458, - result_d_addrBits__h1010459, + { IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23432, + result_d_address__h1010493, + result_d_addrBits__h1010494, csrf_rg_dpc[71:0] } ; assign MUX_csrf_rg_dpc$write_1__VAL_2 = - { f_csr_reqs_first__3969_BITS_63_TO_14_4122_XOR__ETC___d24307, - result_d_address__h1033507, - result_d_addrBits__h1033508, + { f_csr_reqs_first__3971_BITS_63_TO_14_4124_XOR__ETC___d24309, + result_d_address__h1033541, + result_d_addrBits__h1033542, csrf_rg_dpc[71:0] } ; assign MUX_csrf_rg_dpc$write_1__VAL_3 = { commitStage_commitTrap[237], - pc_address__h994739, - pc_addrBits__h994740, + pc_address__h994737, + pc_addrBits__h994738, commitStage_commitTrap[236:221], commitStage_commitTrap[218], commitStage_commitTrap[220:219], ~commitStage_commitTrap[217:199], IF_INV_commitStage_commitTrap_2268_BITS_217_TO_ETC___d22580, - x__h995109, - x__h995129 } ; + x__h995107, + x__h995127 } ; assign MUX_csrf_rg_tselect$write_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ; assign MUX_csrf_sepcc_reg_data_lat_1$wset_1__VAL_1 = - { f_csr_reqs_first__3969_BITS_63_TO_14_4122_XOR__ETC___d24158, - result_d_address__h1032020, - result_d_addrBits__h1032021, - IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d23198 } ; - assign MUX_csrf_sepcc_reg_data_lat_1$wset_1__VAL_2 = (rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd13) ? - { IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23179, - result_d_address__h1008969, - result_d_addrBits__h1008970, - IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d23198 } : + { IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23181, + result_d_address__h1009004, + result_d_addrBits__h1009005, + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d23200 } : rob$deqPort_0_deq_data[194:42] ; + assign MUX_csrf_sepcc_reg_data_lat_1$wset_1__VAL_2 = + { f_csr_reqs_first__3971_BITS_63_TO_14_4124_XOR__ETC___d24160, + result_d_address__h1032054, + result_d_addrBits__h1032055, + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d23200 } ; assign MUX_csrf_spp_reg$write_1__VAL_1 = rob$deqPort_0_deq_data[469:465] == 5'd17 && - (IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + (IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd8 || - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd19) && MUX_csrf_rg_tselect$write_1__VAL_2[8] ; assign MUX_csrf_stcc_reg$write_1__VAL_1 = - { f_csr_reqs_first__3969_BITS_63_TO_14_4122_XOR__ETC___d24136, - result_d_address__h1031617, - result_d_addrBits__h1031618, - csrf_stcc_reg[71:0] } ; - assign MUX_csrf_stcc_reg$write_1__VAL_2 = (rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd10) ? - { IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23133, - result_d_address__h1008566, - result_d_addrBits__h1008567, + { IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23135, + result_d_address__h1008601, + result_d_addrBits__h1008602, csrf_stcc_reg[71:0] } : rob$deqPort_0_deq_data[194:42] ; + assign MUX_csrf_stcc_reg$write_1__VAL_2 = + { f_csr_reqs_first__3971_BITS_63_TO_14_4124_XOR__ETC___d24138, + result_d_address__h1031651, + result_d_addrBits__h1031652, + csrf_stcc_reg[71:0] } ; assign MUX_csrf_stval_csr$write_1__VAL_1 = rob$deqPort_0_deq_data[95:32] ; - assign MUX_f_csr_rsps$enq_1__VAL_3 = { 1'd1, data_out__h1019990 } ; + assign MUX_f_csr_rsps$enq_1__VAL_3 = { 1'd1, data_out__h1020024 } ; assign MUX_f_fpr_rsps$enq_1__VAL_3 = { 1'd1, rf$read_4_rd1[149:86] } ; assign MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 = { csrf_prv_reg, @@ -11806,21 +11804,21 @@ module mkCore(CLK, csrf_sum_reg, csrf_ppn_reg } ; assign MUX_fetchStage$redirect_1__VAL_1 = - { IF_csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_c_ETC___d22876[38:19], - ~IF_csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_c_ETC___d22876[18:0], - IF_IF_csrf_prv_reg_read__0286_ULE_1_2614_AND_I_ETC___d22894[25:17], - ~IF_IF_csrf_prv_reg_read__0286_ULE_1_2614_AND_I_ETC___d22894[16:15], - IF_IF_csrf_prv_reg_read__0286_ULE_1_2614_AND_I_ETC___d22894[14:3], - ~IF_IF_csrf_prv_reg_read__0286_ULE_1_2614_AND_I_ETC___d22894[2], - IF_IF_csrf_prv_reg_read__0286_ULE_1_2614_AND_I_ETC___d22894[1:0], - thin_address__h999382 } ; + { IF_csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_c_ETC___d22878[38:19], + ~IF_csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_c_ETC___d22878[18:0], + IF_IF_csrf_prv_reg_read__0286_ULE_1_2614_AND_I_ETC___d22896[25:17], + ~IF_IF_csrf_prv_reg_read__0286_ULE_1_2614_AND_I_ETC___d22896[16:15], + IF_IF_csrf_prv_reg_read__0286_ULE_1_2614_AND_I_ETC___d22896[14:3], + ~IF_IF_csrf_prv_reg_read__0286_ULE_1_2614_AND_I_ETC___d22896[2], + IF_IF_csrf_prv_reg_read__0286_ULE_1_2614_AND_I_ETC___d22896[1:0], + thin_address__h999417 } ; always@(rob$deqPort_0_deq_data or - next_pc__h1012222 or v__h1012261 or v__h1012970) + next_pc__h1012257 or v__h1012296 or v__h1013005) begin case (rob$deqPort_0_deq_data[469:465]) - 5'd24: MUX_fetchStage$redirect_1__VAL_5 = v__h1012261; - 5'd25: MUX_fetchStage$redirect_1__VAL_5 = v__h1012970; - default: MUX_fetchStage$redirect_1__VAL_5 = next_pc__h1012222; + 5'd24: MUX_fetchStage$redirect_1__VAL_5 = v__h1012296; + 5'd25: MUX_fetchStage$redirect_1__VAL_5 = v__h1013005; + default: MUX_fetchStage$redirect_1__VAL_5 = next_pc__h1012257; endcase end assign MUX_fetchStage$redirect_1__VAL_6 = @@ -11829,11 +11827,11 @@ module mkCore(CLK, csrf_rg_dpc[54:53], csrf_rg_dpc[55], ~csrf_rg_dpc[52:34], - IF_csrf_rg_dpc_read__6343_BIT_34_4349_THEN_csr_ETC___d24357[25:17], - ~IF_csrf_rg_dpc_read__6343_BIT_34_4349_THEN_csr_ETC___d24357[16:15], - IF_csrf_rg_dpc_read__6343_BIT_34_4349_THEN_csr_ETC___d24357[14:3], - ~IF_csrf_rg_dpc_read__6343_BIT_34_4349_THEN_csr_ETC___d24357[2], - IF_csrf_rg_dpc_read__6343_BIT_34_4349_THEN_csr_ETC___d24357[1:0], + IF_csrf_rg_dpc_read__6343_BIT_34_4351_THEN_csr_ETC___d24359[25:17], + ~IF_csrf_rg_dpc_read__6343_BIT_34_4351_THEN_csr_ETC___d24359[16:15], + IF_csrf_rg_dpc_read__6343_BIT_34_4351_THEN_csr_ETC___d24359[14:3], + ~IF_csrf_rg_dpc_read__6343_BIT_34_4351_THEN_csr_ETC___d24359[2], + IF_csrf_rg_dpc_read__6343_BIT_34_4351_THEN_csr_ETC___d24359[1:0], csrf_rg_dpc[149:86] } ; assign MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_1 = { 1'd1, @@ -11844,7 +11842,7 @@ module mkCore(CLK, assign MUX_mmio_cRqQ_enqReq_lat_0$wset_1__VAL_1 = { 1'd1, mmio_dataReqQ_data_0[214:151], - CASE_mmio_dataReqQ_data_0_BITS_150_TO_149_0_mm_ETC__q331, + CASE_mmio_dataReqQ_data_0_BITS_150_TO_149_0_mm_ETC__q333, mmio_dataReqQ_data_0[144:0] } ; assign MUX_mmio_cRqQ_enqReq_lat_0$wset_1__VAL_2 = { 1'd1, @@ -11867,38 +11865,38 @@ module mkCore(CLK, 112'hAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; assign MUX_rf$write_2_wr_2__VAL_1 = { 1'd0, - res_address__h567346, - res_addrBits__h567347, + res_address__h567343, + res_addrBits__h567344, 72'h00001FFFFF44000000 } ; assign MUX_rf$write_2_wr_2__VAL_2 = { 1'd0, - res_address__h568198, - res_addrBits__h568199, + res_address__h568196, + res_addrBits__h568197, 72'h00001FFFFF44000000 } ; assign MUX_rf$write_2_wr_2__VAL_3 = { 1'd0, - res_address__h613955, - res_addrBits__h613956, + res_address__h613953, + res_addrBits__h613954, 72'h00001FFFFF44000000 } ; assign MUX_rf$write_2_wr_2__VAL_4 = { 1'd0, - res_address__h659702, - res_addrBits__h659703, + res_address__h659700, + res_addrBits__h659701, 72'h00001FFFFF44000000 } ; assign MUX_rf$write_2_wr_2__VAL_5 = { 1'd0, - res_address__h705511, - res_addrBits__h705512, + res_address__h705509, + res_addrBits__h705510, 72'h00001FFFFF44000000 } ; assign MUX_rf$write_2_wr_2__VAL_6 = { 1'd0, - res_address__h706371, - res_addrBits__h706372, + res_address__h706369, + res_addrBits__h706370, 72'h00001FFFFF44000000 } ; assign MUX_rf$write_3_wr_2__VAL_1 = { coreFix_memExe_respLrScAmoQ_data_0[128], - res_address__h126822, - res_addrBits__h126823, + res_address__h126821, + res_addrBits__h126822, coreFix_memExe_respLrScAmoQ_data_0[127:112], coreFix_memExe_respLrScAmoQ_data_0[109], coreFix_memExe_respLrScAmoQ_data_0[111:110], @@ -11906,8 +11904,8 @@ module mkCore(CLK, IF_INV_coreFix_memExe_respLrScAmoQ_data_0_233__ETC___d1273 } ; assign MUX_rf$write_3_wr_2__VAL_2 = { mmio_dataRespQ_data_0[128], - res_address__h139734, - res_addrBits__h139735, + res_address__h139733, + res_addrBits__h139734, mmio_dataRespQ_data_0[127:112], mmio_dataRespQ_data_0[109], mmio_dataRespQ_data_0[111:110], @@ -11916,27 +11914,27 @@ module mkCore(CLK, assign MUX_rf$write_3_wr_2__VAL_3 = { coreFix_memExe_lsq$firstLd[125:110] == 16'd65535 && coreFix_memExe_respLrScAmoQ_data_0[128], - res_address__h178898, - res_addrBits__h178899, - x__h183399[127:112], - x__h183399[109], - x__h183399[111:110], - ~x__h183399[108:90], + res_address__h178896, + res_addrBits__h178897, + x__h183397[127:112], + x__h183397[109], + x__h183397[111:110], + ~x__h183397[108:90], IF_INV_IF_coreFix_memExe_lsq_firstLd__498_BITS_ETC___d1954 } ; assign MUX_rf$write_3_wr_2__VAL_4 = { coreFix_memExe_lsq$firstLd[125:110] == 16'd65535 && mmio_dataRespQ_data_0[128], - res_address__h197663, - res_addrBits__h197664, - x__h199251[127:112], - x__h199251[109], - x__h199251[111:110], - ~x__h199251[108:90], + res_address__h197661, + res_addrBits__h197662, + x__h199249[127:112], + x__h199249[109], + x__h199249[111:110], + ~x__h199249[108:90], IF_INV_IF_coreFix_memExe_lsq_firstLd__498_BITS_ETC___d2120 } ; assign MUX_rf$write_3_wr_2__VAL_5 = { coreFix_memExe_lsq$respLd[128], - res_address__h216422, - res_addrBits__h216423, + res_address__h216420, + res_addrBits__h216421, coreFix_memExe_lsq$respLd[127:112], coreFix_memExe_lsq$respLd[109], coreFix_memExe_lsq$respLd[111:110], @@ -11944,13 +11942,13 @@ module mkCore(CLK, IF_INV_coreFix_memExe_lsq_respLd_159_BITS_108__ETC___d2210 } ; assign MUX_rf$write_4_wr_2__VAL_1 = { 1'd1, - data_address__h1018717, - data_addrBits__h1018718, + data_address__h1018751, + data_addrBits__h1018752, 72'hFFFF1FFFFF44000000 } ; assign MUX_rf$write_4_wr_2__VAL_2 = { 1'd0, - data_address__h1019571, - data_addrBits__h1019572, + data_address__h1019605, + data_addrBits__h1019606, 72'h00001FFFFF44000000 } ; assign MUX_rob$enqPort_0_enq_1__VAL_1 = { fetchStage$pipelines_0_first[591:463], @@ -12005,22 +12003,22 @@ module mkCore(CLK, fetchStage_pipelines_0_first__0256_BIT_167_059_ETC___d21145 } ; assign MUX_rob$setExecuted_deqLSQ_2__VAL_2 = { 1'd1, - CASE_coreFix_memExe_lsqfirstSt_BITS_12_TO_11__ETC__q335 } ; + CASE_coreFix_memExe_lsqfirstSt_BITS_12_TO_11__ETC__q337 } ; assign MUX_rob$setExecuted_deqLSQ_2__VAL_6 = { 1'd1, - CASE_coreFix_memExe_lsqfirstLd_BITS_15_TO_14__ETC__q339 } ; + CASE_coreFix_memExe_lsqfirstLd_BITS_15_TO_14__ETC__q341 } ; assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_2 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[4:0] : - res_fflags__h568239 ; + res_fflags__h568237 ; assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_3 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[4:0] : - res_fflags__h613993 ; + res_fflags__h613991 ; assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_4 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[4:0] : - res_fflags__h659740 ; + res_fflags__h659738 ; // inlined wires assign csrf_minstret_ehr_data_lat_0$whas = @@ -12028,7 +12026,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd2818 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd32 ; assign csrf_minstret_ehr_data_lat_1$whas = WILL_FIRE_RL_commitStage_doCommitSystemInst || @@ -12038,24 +12036,24 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd2816 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd31 ; assign csrf_sepcc_reg_data_lat_1$wget = MUX_csrf_sepcc_reg_data_lat_1$wset_1__SEL_1 ? MUX_csrf_sepcc_reg_data_lat_1$wset_1__VAL_1 : MUX_csrf_sepcc_reg_data_lat_1$wset_1__VAL_2 ; assign csrf_sepcc_reg_data_lat_1$whas = + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo36 || WILL_FIRE_RL_rl_debug_csr_write && - f_csr_reqs$D_OUT[75:64] == 12'd321 || - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo36 ; + f_csr_reqs$D_OUT[75:64] == 12'd321 ; assign csrf_mepcc_reg_data_lat_1$wget = MUX_csrf_mepcc_reg_data_lat_1$wset_1__SEL_1 ? MUX_csrf_mepcc_reg_data_lat_1$wset_1__VAL_1 : MUX_csrf_mepcc_reg_data_lat_1$wset_1__VAL_2 ; assign csrf_mepcc_reg_data_lat_1$whas = + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 || WILL_FIRE_RL_rl_debug_csr_write && - f_csr_reqs$D_OUT[75:64] == 12'd833 || - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; + f_csr_reqs$D_OUT[75:64] == 12'd833 ; assign csrInstOrInterruptInflight_lat_0$whas = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 || @@ -12103,7 +12101,7 @@ module mkCore(CLK, assign mmio_pRqQ_enqReq_lat_0$wget = { 1'd1, mmioToPlatform_pRq_enq_x[38], - CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q340, + CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q342, mmioToPlatform_pRq_enq_x[31:0] } ; assign mmio_cRsQ_enqReq_lat_0$wget = { 1'd1, csrf_software_int_pend_vec_3 } ; @@ -12390,7 +12388,7 @@ module mkCore(CLK, // register commitStage_rg_serial_num always@(MUX_commitStage_rg_serial_num$write_1__SEL_1 or - MUX_commitStage_rg_serial_num$write_1__VAL_2 or + MUX_commitStage_rg_serial_num$write_1__VAL_1 or WILL_FIRE_RL_commitStage_doCommitSystemInst or WILL_FIRE_RL_commitStage_doCommitNormalInst or MUX_commitStage_rg_serial_num$write_1__VAL_3) @@ -12398,10 +12396,10 @@ module mkCore(CLK, case (1'b1) // synopsys parallel_case MUX_commitStage_rg_serial_num$write_1__SEL_1: commitStage_rg_serial_num$D_IN = - MUX_commitStage_rg_serial_num$write_1__VAL_2; + MUX_commitStage_rg_serial_num$write_1__VAL_1; WILL_FIRE_RL_commitStage_doCommitSystemInst: commitStage_rg_serial_num$D_IN = - MUX_commitStage_rg_serial_num$write_1__VAL_2; + MUX_commitStage_rg_serial_num$write_1__VAL_1; WILL_FIRE_RL_commitStage_doCommitNormalInst: commitStage_rg_serial_num$D_IN = MUX_commitStage_rg_serial_num$write_1__VAL_3; @@ -12434,8 +12432,8 @@ module mkCore(CLK, // register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$D_IN = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas ? - v__h837287 : - v__h836642 ; + v__h837284 : + v__h836639 ; assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$EN = 1'd1 ; // register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0 @@ -12533,7 +12531,7 @@ module mkCore(CLK, assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$D_IN = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl ? 3'd0 : - _theResult_____2__h515368 ; + _theResult_____2__h515366 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl @@ -12552,7 +12550,7 @@ module mkCore(CLK, assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$D_IN = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl ? 3'd0 : - v__h514824 ; + v__h514822 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl @@ -12594,7 +12592,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$D_IN = !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl && - _theResult_____2__h526145 ; + _theResult_____2__h526143 ; assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl @@ -12613,7 +12611,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$D_IN = !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl && - v__h516844 ; + v__h516842 ; assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl @@ -12710,7 +12708,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$D_IN = !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl && - _theResult_____2__h533238 ; + _theResult_____2__h533236 ; assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl @@ -12726,7 +12724,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$D_IN = !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl && - v__h532563 ; + v__h532561 ; assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl @@ -12746,7 +12744,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$D_IN = - { x_addr__h535374, + { x_addr__h535372, coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[518:517] : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[518:517], @@ -12773,7 +12771,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$D_IN = !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl && - _theResult_____2__h543873 ; + _theResult_____2__h543871 ; assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl @@ -12792,7 +12790,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$D_IN = !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl && - v__h535012 ; + v__h535010 ; assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl @@ -12868,7 +12866,7 @@ module mkCore(CLK, // register coreFix_memExe_forwardQ_deqP assign coreFix_memExe_forwardQ_deqP$D_IN = !coreFix_memExe_forwardQ_clearReq_rl && - _theResult_____2__h561485 ; + _theResult_____2__h561483 ; assign coreFix_memExe_forwardQ_deqP$EN = 1'd1 ; // register coreFix_memExe_forwardQ_deqReq_rl @@ -12883,7 +12881,7 @@ module mkCore(CLK, // register coreFix_memExe_forwardQ_enqP assign coreFix_memExe_forwardQ_enqP$D_IN = - !coreFix_memExe_forwardQ_clearReq_rl && v__h559811 ; + !coreFix_memExe_forwardQ_clearReq_rl && v__h559809 ; assign coreFix_memExe_forwardQ_enqP$EN = 1'd1 ; // register coreFix_memExe_forwardQ_enqReq_rl @@ -12924,7 +12922,7 @@ module mkCore(CLK, // register coreFix_memExe_memRespLdQ_deqP assign coreFix_memExe_memRespLdQ_deqP$D_IN = !coreFix_memExe_memRespLdQ_clearReq_rl && - _theResult_____2__h557706 ; + _theResult_____2__h557704 ; assign coreFix_memExe_memRespLdQ_deqP$EN = 1'd1 ; // register coreFix_memExe_memRespLdQ_deqReq_rl @@ -12939,7 +12937,7 @@ module mkCore(CLK, // register coreFix_memExe_memRespLdQ_enqP assign coreFix_memExe_memRespLdQ_enqP$D_IN = - !coreFix_memExe_memRespLdQ_clearReq_rl && v__h556032 ; + !coreFix_memExe_memRespLdQ_clearReq_rl && v__h556030 ; assign coreFix_memExe_memRespLdQ_enqP$EN = 1'd1 ; // register coreFix_memExe_memRespLdQ_enqReq_rl @@ -13104,7 +13102,7 @@ module mkCore(CLK, assign csrf_ddc_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd18 && - IF_rob_deqPort_0_deq_data__2261_BIT_294_3454_T_ETC___d23476 == + IF_rob_deqPort_0_deq_data__2261_BIT_294_3456_T_ETC___d23478 == 4'd1 ; // register csrf_external_int_en_vec_0 @@ -13132,7 +13130,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd772 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd23 ; // register csrf_external_int_pend_vec_0 @@ -13183,12 +13181,12 @@ module mkCore(CLK, assign csrf_fflags_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - (IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + (IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd0 || - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd2) || WILL_FIRE_RL_commitStage_doCommitNormalInst && - NOT_IF_NOT_rob_deqPort_0_canDeq__3598_3599_OR__ETC___d23844 || + NOT_IF_NOT_rob_deqPort_0_canDeq__3600_3601_OR__ETC___d23846 || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd1 || f_csr_reqs$D_OUT[75:64] == 12'd3) ; @@ -13201,9 +13199,9 @@ module mkCore(CLK, assign csrf_frm_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - (IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + (IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd1 || - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd2) || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd2 || @@ -13225,7 +13223,7 @@ module mkCore(CLK, assign csrf_fs_reg$EN = MUX_csrf_fs_reg$write_1__SEL_2 || WILL_FIRE_RL_commitStage_doCommitNormalInst && - NOT_IF_NOT_rob_deqPort_0_canDeq__3598_3599_OR__ETC___d23844 || + NOT_IF_NOT_rob_deqPort_0_canDeq__3600_3601_OR__ETC___d23846 || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd1 || f_csr_reqs$D_OUT[75:64] == 12'd2 || @@ -13258,13 +13256,13 @@ module mkCore(CLK, default: csrf_ie_vec_1$D_IN = 1'b0 /* unspecified value */ ; endcase assign csrf_ie_vec_1$EN = + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo40 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && commitStage_commitTrap_2268_BITS_44_TO_43_2461_ETC___d22613 && - csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22647 || + csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22648 || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd256 || - f_csr_reqs$D_OUT[75:64] == 12'd768) || - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo40 ; + f_csr_reqs$D_OUT[75:64] == 12'd768) ; // register csrf_ie_vec_3 always@(MUX_csrf_ie_vec_3$write_1__SEL_1 or @@ -13280,19 +13278,19 @@ module mkCore(CLK, default: csrf_ie_vec_3$D_IN = 1'b0 /* unspecified value */ ; endcase assign csrf_ie_vec_3$EN = + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo30 || WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && commitStage_commitTrap_2268_BITS_44_TO_43_2461_ETC___d22613 && - NOT_csrf_prv_reg_read__0286_ULE_1_2614_2729_OR_ETC___d22734 || - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo30 ; + NOT_csrf_prv_reg_read__0286_ULE_1_2614_2730_OR_ETC___d22736 ; // register csrf_mScratchC_reg assign csrf_mScratchC_reg$D_IN = rob$deqPort_0_deq_data[194:42] ; assign csrf_mScratchC_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd18 && - IF_rob_deqPort_0_deq_data__2261_BIT_294_3454_T_ETC___d23476 == + IF_rob_deqPort_0_deq_data__2261_BIT_294_3456_T_ETC___d23478 == 4'd8 ; // register csrf_mcause_code_reg @@ -13300,14 +13298,14 @@ module mkCore(CLK, MUX_csrf_stval_csr$write_1__VAL_1 or MUX_csrf_mcause_code_reg$write_1__SEL_2 or f_csr_reqs$D_OUT or - MUX_csrf_ie_vec_3$write_1__SEL_3 or cause_code__h995320) + MUX_csrf_ie_vec_3$write_1__SEL_3 or cause_code__h995318) case (1'b1) MUX_csrf_mcause_code_reg$write_1__SEL_1: csrf_mcause_code_reg$D_IN = MUX_csrf_stval_csr$write_1__VAL_1[4:0]; MUX_csrf_mcause_code_reg$write_1__SEL_2: csrf_mcause_code_reg$D_IN = f_csr_reqs$D_OUT[4:0]; MUX_csrf_ie_vec_3$write_1__SEL_3: - csrf_mcause_code_reg$D_IN = cause_code__h995320; + csrf_mcause_code_reg$D_IN = cause_code__h995318; default: csrf_mcause_code_reg$D_IN = 5'b01010 /* unspecified value */ ; endcase assign csrf_mcause_code_reg$EN = @@ -13315,10 +13313,10 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd834 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && commitStage_commitTrap_2268_BITS_44_TO_43_2461_ETC___d22613 && - NOT_csrf_prv_reg_read__0286_ULE_1_2614_2729_OR_ETC___d22734 || + NOT_csrf_prv_reg_read__0286_ULE_1_2614_2730_OR_ETC___d22736 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd28 ; // register csrf_mcause_interrupt_reg @@ -13326,7 +13324,7 @@ module mkCore(CLK, MUX_csrf_stval_csr$write_1__VAL_1 or MUX_csrf_mcause_code_reg$write_1__SEL_2 or f_csr_reqs$D_OUT or - MUX_csrf_ie_vec_3$write_1__SEL_3 or cause_interrupt__h995318) + MUX_csrf_ie_vec_3$write_1__SEL_3 or cause_interrupt__h995316) case (1'b1) MUX_csrf_mcause_code_reg$write_1__SEL_1: csrf_mcause_interrupt_reg$D_IN = @@ -13334,7 +13332,7 @@ module mkCore(CLK, MUX_csrf_mcause_code_reg$write_1__SEL_2: csrf_mcause_interrupt_reg$D_IN = f_csr_reqs$D_OUT[63]; MUX_csrf_ie_vec_3$write_1__SEL_3: - csrf_mcause_interrupt_reg$D_IN = cause_interrupt__h995318; + csrf_mcause_interrupt_reg$D_IN = cause_interrupt__h995316; default: csrf_mcause_interrupt_reg$D_IN = 1'b0 /* unspecified value */ ; endcase assign csrf_mcause_interrupt_reg$EN = @@ -13342,10 +13340,10 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd834 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && commitStage_commitTrap_2268_BITS_44_TO_43_2461_ETC___d22613 && - NOT_csrf_prv_reg_read__0286_ULE_1_2614_2729_OR_ETC___d22734 || + NOT_csrf_prv_reg_read__0286_ULE_1_2614_2730_OR_ETC___d22736 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd28 ; // register csrf_mccsr_reg @@ -13358,7 +13356,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd3008 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd37 ; // register csrf_mcounteren_cy_reg @@ -13371,7 +13369,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd774 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd25 ; // register csrf_mcounteren_ir_reg @@ -13384,7 +13382,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd774 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd25 ; // register csrf_mcounteren_tm_reg @@ -13397,7 +13395,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd774 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd25 ; // register csrf_mcycle_ehr_data_rl @@ -13414,7 +13412,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd770 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd21 ; // register csrf_medeleg_15_reg @@ -13427,7 +13425,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd770 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd21 ; // register csrf_medeleg_28_26_reg @@ -13440,7 +13438,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd770 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd21 ; // register csrf_medeleg_9_0_reg @@ -13453,7 +13451,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd770 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd21 ; // register csrf_mepcc_reg_data_rl @@ -13475,7 +13473,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd771 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd22 ; // register csrf_mideleg_1_0_reg @@ -13488,7 +13486,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd771 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd22 ; // register csrf_mideleg_5_3_reg @@ -13501,7 +13499,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd771 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd22 ; // register csrf_mideleg_9_7_reg @@ -13514,14 +13512,14 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd771 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd22 ; // register csrf_minstret_ehr_data_rl assign csrf_minstret_ehr_data_rl$D_IN = csrf_minstret_ehr_data_lat_1$whas ? upd__h3066 : - n__read__h1014112 ; + n__read__h1014147 ; assign csrf_minstret_ehr_data_rl$EN = 1'd1 ; // register csrf_mpp_reg @@ -13539,12 +13537,12 @@ module mkCore(CLK, default: csrf_mpp_reg$D_IN = 2'b10 /* unspecified value */ ; endcase assign csrf_mpp_reg$EN = + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo30 || WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && commitStage_commitTrap_2268_BITS_44_TO_43_2461_ETC___d22613 && - NOT_csrf_prv_reg_read__0286_ULE_1_2614_2729_OR_ETC___d22734 || - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo30 ; + NOT_csrf_prv_reg_read__0286_ULE_1_2614_2730_OR_ETC___d22736 ; // register csrf_mprv_reg assign csrf_mprv_reg$D_IN = @@ -13556,7 +13554,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd19 ; // register csrf_mscratch_csr @@ -13569,7 +13567,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd832 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd26 ; // register csrf_mtcc_reg @@ -13578,16 +13576,16 @@ module mkCore(CLK, MUX_csrf_mtcc_reg$write_1__VAL_1 : MUX_csrf_mtcc_reg$write_1__VAL_2 ; assign csrf_mtcc_reg$EN = + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 || WILL_FIRE_RL_rl_debug_csr_write && - f_csr_reqs$D_OUT[75:64] == 12'd773 || - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 ; + f_csr_reqs$D_OUT[75:64] == 12'd773 ; // register csrf_mtdc_reg assign csrf_mtdc_reg$D_IN = rob$deqPort_0_deq_data[194:42] ; assign csrf_mtdc_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd18 && - IF_rob_deqPort_0_deq_data__2261_BIT_294_3454_T_ETC___d23476 == + IF_rob_deqPort_0_deq_data__2261_BIT_294_3456_T_ETC___d23478 == 4'd7 ; // register csrf_mtval_csr @@ -13612,10 +13610,10 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd835 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && commitStage_commitTrap_2268_BITS_44_TO_43_2461_ETC___d22613 && - NOT_csrf_prv_reg_read__0286_ULE_1_2614_2729_OR_ETC___d22734 || + NOT_csrf_prv_reg_read__0286_ULE_1_2614_2730_OR_ETC___d22736 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd29 ; // register csrf_mxr_reg @@ -13639,7 +13637,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd384 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd17 ; // register csrf_prev_ie_vec_0 @@ -13668,13 +13666,13 @@ module mkCore(CLK, default: csrf_prev_ie_vec_1$D_IN = 1'b0 /* unspecified value */ ; endcase assign csrf_prev_ie_vec_1$EN = + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo40 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && commitStage_commitTrap_2268_BITS_44_TO_43_2461_ETC___d22613 && - csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22647 || + csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22648 || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd256 || - f_csr_reqs$D_OUT[75:64] == 12'd768) || - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo40 ; + f_csr_reqs$D_OUT[75:64] == 12'd768) ; // register csrf_prev_ie_vec_3 always@(MUX_csrf_prev_ie_vec_3$write_1__SEL_1 or @@ -13691,12 +13689,12 @@ module mkCore(CLK, default: csrf_prev_ie_vec_3$D_IN = 1'b0 /* unspecified value */ ; endcase assign csrf_prev_ie_vec_3$EN = + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo30 || WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && commitStage_commitTrap_2268_BITS_44_TO_43_2461_ETC___d22613 && - NOT_csrf_prv_reg_read__0286_ULE_1_2614_2729_OR_ETC___d22734 || - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo30 ; + NOT_csrf_prv_reg_read__0286_ULE_1_2614_2730_OR_ETC___d22736 ; // register csrf_prv_reg always@(MUX_csrf_prv_reg$write_1__SEL_1 or @@ -13715,11 +13713,11 @@ module mkCore(CLK, default: csrf_prv_reg$D_IN = 2'b10 /* unspecified value */ ; endcase assign csrf_prv_reg$EN = + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo24 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && commitStage_commitTrap_2268_BITS_44_TO_43_2461_ETC___d22613 || WILL_FIRE_RL_rl_debug_csr_write && - f_csr_reqs$D_OUT[75:64] == 12'd1968 || - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo24 ; + f_csr_reqs$D_OUT[75:64] == 12'd1968 ; // register csrf_rg_dcsr always@(MUX_csrf_rg_dcsr$write_1__SEL_1 or @@ -13745,7 +13743,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1968 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd42 ; // register csrf_rg_dpc @@ -13772,7 +13770,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1969 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd43 ; // register csrf_rg_dscratch0 @@ -13785,7 +13783,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1970 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd44 ; // register csrf_rg_dscratch1 @@ -13798,7 +13796,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1971 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd45 ; // register csrf_rg_tdata1_data @@ -13811,7 +13809,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1953 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd39 ; // register csrf_rg_tdata1_dmode @@ -13824,7 +13822,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1953 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd39 ; // register csrf_rg_tdata2 @@ -13837,7 +13835,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1954 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd40 ; // register csrf_rg_tdata3 @@ -13850,7 +13848,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1955 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd41 ; // register csrf_rg_tselect @@ -13863,7 +13861,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1952 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd38 ; // register csrf_sScratchC_reg @@ -13871,7 +13869,7 @@ module mkCore(CLK, assign csrf_sScratchC_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd18 && - IF_rob_deqPort_0_deq_data__2261_BIT_294_3454_T_ETC___d23476 == + IF_rob_deqPort_0_deq_data__2261_BIT_294_3456_T_ETC___d23478 == 4'd4 ; // register csrf_scause_code_reg @@ -13879,14 +13877,14 @@ module mkCore(CLK, MUX_csrf_stval_csr$write_1__VAL_1 or MUX_csrf_scause_code_reg$write_1__SEL_2 or f_csr_reqs$D_OUT or - MUX_csrf_ie_vec_1$write_1__SEL_3 or cause_code__h995320) + MUX_csrf_ie_vec_1$write_1__SEL_3 or cause_code__h995318) case (1'b1) MUX_csrf_scause_code_reg$write_1__SEL_1: csrf_scause_code_reg$D_IN = MUX_csrf_stval_csr$write_1__VAL_1[4:0]; MUX_csrf_scause_code_reg$write_1__SEL_2: csrf_scause_code_reg$D_IN = f_csr_reqs$D_OUT[4:0]; MUX_csrf_ie_vec_1$write_1__SEL_3: - csrf_scause_code_reg$D_IN = cause_code__h995320; + csrf_scause_code_reg$D_IN = cause_code__h995318; default: csrf_scause_code_reg$D_IN = 5'b01010 /* unspecified value */ ; endcase assign csrf_scause_code_reg$EN = @@ -13894,10 +13892,10 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd322 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && commitStage_commitTrap_2268_BITS_44_TO_43_2461_ETC___d22613 && - csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22647 || + csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22648 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd14 ; // register csrf_scause_interrupt_reg @@ -13905,7 +13903,7 @@ module mkCore(CLK, MUX_csrf_stval_csr$write_1__VAL_1 or MUX_csrf_scause_code_reg$write_1__SEL_2 or f_csr_reqs$D_OUT or - MUX_csrf_ie_vec_1$write_1__SEL_3 or cause_interrupt__h995318) + MUX_csrf_ie_vec_1$write_1__SEL_3 or cause_interrupt__h995316) case (1'b1) MUX_csrf_scause_code_reg$write_1__SEL_1: csrf_scause_interrupt_reg$D_IN = @@ -13913,7 +13911,7 @@ module mkCore(CLK, MUX_csrf_scause_code_reg$write_1__SEL_2: csrf_scause_interrupt_reg$D_IN = f_csr_reqs$D_OUT[63]; MUX_csrf_ie_vec_1$write_1__SEL_3: - csrf_scause_interrupt_reg$D_IN = cause_interrupt__h995318; + csrf_scause_interrupt_reg$D_IN = cause_interrupt__h995316; default: csrf_scause_interrupt_reg$D_IN = 1'b0 /* unspecified value */ ; endcase assign csrf_scause_interrupt_reg$EN = @@ -13921,10 +13919,10 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd322 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && commitStage_commitTrap_2268_BITS_44_TO_43_2461_ETC___d22613 && - csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22647 || + csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22648 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd14 ; // register csrf_scounteren_cy_reg @@ -13937,7 +13935,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd262 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd11 ; // register csrf_scounteren_ir_reg @@ -13950,7 +13948,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd262 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd11 ; // register csrf_scounteren_tm_reg @@ -13963,7 +13961,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd262 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd11 ; // register csrf_sepcc_reg_data_rl @@ -14000,7 +13998,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd772 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd23 ; // register csrf_software_int_pend_vec_0 @@ -14042,13 +14040,13 @@ module mkCore(CLK, default: csrf_spp_reg$D_IN = 1'b0 /* unspecified value */ ; endcase assign csrf_spp_reg$EN = + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo40 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && commitStage_commitTrap_2268_BITS_44_TO_43_2461_ETC___d22613 && - csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22647 || + csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22648 || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd256 || - f_csr_reqs$D_OUT[75:64] == 12'd768) || - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo40 ; + f_csr_reqs$D_OUT[75:64] == 12'd768) ; // register csrf_sscratch_csr assign csrf_sscratch_csr$D_IN = @@ -14060,7 +14058,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd320 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd12 ; // register csrf_stats_module_doStats @@ -14073,16 +14071,16 @@ module mkCore(CLK, MUX_csrf_stcc_reg$write_1__VAL_1 : MUX_csrf_stcc_reg$write_1__VAL_2 ; assign csrf_stcc_reg$EN = + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo38 || WILL_FIRE_RL_rl_debug_csr_write && - f_csr_reqs$D_OUT[75:64] == 12'd261 || - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo38 ; + f_csr_reqs$D_OUT[75:64] == 12'd261 ; // register csrf_stdc_reg assign csrf_stdc_reg$D_IN = rob$deqPort_0_deq_data[194:42] ; assign csrf_stdc_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd18 && - IF_rob_deqPort_0_deq_data__2261_BIT_294_3454_T_ETC___d23476 == + IF_rob_deqPort_0_deq_data__2261_BIT_294_3456_T_ETC___d23478 == 4'd3 ; // register csrf_stval_csr @@ -14107,10 +14105,10 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd323 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && commitStage_commitTrap_2268_BITS_44_TO_43_2461_ETC___d22613 && - csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22647 || + csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22648 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd15 ; // register csrf_sum_reg @@ -14153,7 +14151,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd772 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd23 ; // register csrf_timer_int_pend_vec_0 @@ -14187,7 +14185,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd19 ; // register csrf_tvm_reg @@ -14200,7 +14198,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd19 ; // register csrf_tw_reg @@ -14213,7 +14211,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd19 ; // register csrf_vm_mode_sv39_reg @@ -14226,7 +14224,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd384 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd17 ; // register flush_brpred @@ -14244,10 +14242,10 @@ module mkCore(CLK, WILL_FIRE_RL_flushCaches ; // register flush_reservation - assign flush_reservation$D_IN = !MUX_flush_reservation$write_1__SEL_1 ; + assign flush_reservation$D_IN = !MUX_flush_reservation$write_1__SEL_2 ; assign flush_reservation$EN = - WILL_FIRE_RL_prepareCachesAndTlbs && flush_reservation || WILL_FIRE_RL_commitStage_doCommitTrap_handle && _dfoo20 || + WILL_FIRE_RL_prepareCachesAndTlbs && flush_reservation || WILL_FIRE_RL_commitStage_doCommitSystemInst ; // register flush_tlbs @@ -14259,7 +14257,7 @@ module mkCore(CLK, WILL_FIRE_RL_commitStage_doCommitSystemInst && (rob$deqPort_0_deq_data[469:465] == 5'd21 || rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd17) ; // register mmio_cRqQ_clearReq_rl @@ -14626,19 +14624,19 @@ module mkCore(CLK, assign update_vm_info$D_IN = !MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1 ; assign update_vm_info$EN = - WILL_FIRE_RL_prepareCachesAndTlbs && update_vm_info || WILL_FIRE_RL_commitStage_doCommitTrap_handle && _dfoo20 || + WILL_FIRE_RL_prepareCachesAndTlbs && update_vm_info || WILL_FIRE_RL_commitStage_doCommitSystemInst ; // submodule coreFix_aluExe_0_dispToRegQ assign coreFix_aluExe_0_dispToRegQ$enq_x = { coreFix_aluExe_0_rsAlu$dispatchData[234:230], - CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q342, - CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q343, - coreFix_aluExe_0_rsAlu$dispatchData[188:141], CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q344, - coreFix_aluExe_0_rsAlu$dispatchData[128], CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q345, + coreFix_aluExe_0_rsAlu$dispatchData[188:141], + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q346, + coreFix_aluExe_0_rsAlu$dispatchData[128], + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q347, coreFix_aluExe_0_rsAlu$dispatchData[122:90], coreFix_aluExe_0_rsAlu$dispatchData[65:21], coreFix_aluExe_0_rsAlu$dispatchData[89:66], @@ -14692,7 +14690,7 @@ module mkCore(CLK, coreFix_aluExe_0_regToExeQ$first[822:818] == 5'd18, basicExec___d19859[932:770], basicExec___d19859[606:271], - CASE_basicExec_9859_BITS_270_TO_266_0_basicExe_ETC__q346, + CASE_basicExec_9859_BITS_270_TO_266_0_basicExe_ETC__q348, basicExec___d19859[265:0], coreFix_aluExe_0_regToExeQ$first[16:0] } ; assign coreFix_aluExe_0_exeToFinQ$specUpdate_correctSpeculation_mask = @@ -14734,12 +14732,12 @@ module mkCore(CLK, // submodule coreFix_aluExe_0_regToExeQ assign coreFix_aluExe_0_regToExeQ$enq_x = { coreFix_aluExe_0_dispToRegQ$first[230:226], - CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_22_ETC__q348, - CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_19_ETC__q349, + CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_22_ETC__q350, + CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_19_ETC__q351, coreFix_aluExe_0_dispToRegQ$first[184:137], - CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q350, + CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q352, coreFix_aluExe_0_dispToRegQ$first[124], - CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_12_ETC__q351, + CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_12_ETC__q353, coreFix_aluExe_0_dispToRegQ$first[118:86], coreFix_aluExe_0_dispToRegQ$first[61:17], NOT_coreFix_aluExe_0_dispToRegQ_first__8383_BI_ETC___d19448, @@ -14877,11 +14875,11 @@ module mkCore(CLK, endcase end assign coreFix_aluExe_0_rsAlu$EN_enq = + WILL_FIRE_RL_renameStage_doRenaming && _dfoo18 || WILL_FIRE_RL_renameStage_doRenaming_SystemInst && (fetchStage$pipelines_0_first[268:266] == 3'd0 || fetchStage$pipelines_0_first[238:237] == 2'd1 || - fetchStage$pipelines_0_first[238:237] == 2'd0) || - WILL_FIRE_RL_renameStage_doRenaming && _dfoo18 ; + fetchStage$pipelines_0_first[238:237] == 2'd0) ; assign coreFix_aluExe_0_rsAlu$EN_setRobEnqTime = 1'd1 ; assign coreFix_aluExe_0_rsAlu$EN_doDispatch = WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu ; @@ -14934,12 +14932,12 @@ module mkCore(CLK, // submodule coreFix_aluExe_1_dispToRegQ assign coreFix_aluExe_1_dispToRegQ$enq_x = { coreFix_aluExe_1_rsAlu$dispatchData[234:230], - CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q353, - CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q354, - coreFix_aluExe_1_rsAlu$dispatchData[188:141], CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q355, - coreFix_aluExe_1_rsAlu$dispatchData[128], CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q356, + coreFix_aluExe_1_rsAlu$dispatchData[188:141], + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q357, + coreFix_aluExe_1_rsAlu$dispatchData[128], + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q358, coreFix_aluExe_1_rsAlu$dispatchData[122:90], coreFix_aluExe_1_rsAlu$dispatchData[65:21], coreFix_aluExe_1_rsAlu$dispatchData[89:66], @@ -14992,7 +14990,7 @@ module mkCore(CLK, coreFix_aluExe_1_regToExeQ$first[822:818] == 5'd18, basicExec___d17743[932:770], basicExec___d17743[606:271], - CASE_basicExec_7743_BITS_270_TO_266_0_basicExe_ETC__q357, + CASE_basicExec_7743_BITS_270_TO_266_0_basicExe_ETC__q359, basicExec___d17743[265:0], coreFix_aluExe_1_regToExeQ$first[16:0] } ; assign coreFix_aluExe_1_exeToFinQ$specUpdate_correctSpeculation_mask = @@ -15034,12 +15032,12 @@ module mkCore(CLK, // submodule coreFix_aluExe_1_regToExeQ assign coreFix_aluExe_1_regToExeQ$enq_x = { coreFix_aluExe_1_dispToRegQ$first[230:226], - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_22_ETC__q359, - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_19_ETC__q360, + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_22_ETC__q361, + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_19_ETC__q362, coreFix_aluExe_1_dispToRegQ$first[184:137], - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q361, + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q363, coreFix_aluExe_1_dispToRegQ$first[124], - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_12_ETC__q362, + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_12_ETC__q364, coreFix_aluExe_1_dispToRegQ$first[118:86], coreFix_aluExe_1_dispToRegQ$first[61:17], NOT_coreFix_aluExe_1_dispToRegQ_first__5620_BI_ETC___d17332, @@ -15081,7 +15079,7 @@ module mkCore(CLK, // submodule coreFix_aluExe_1_rsAlu assign coreFix_aluExe_1_rsAlu$enq_x = - (k__h945030 == 1'd1 && fetchStage$pipelines_0_canDeq && + (k__h945028 == 1'd1 && fetchStage$pipelines_0_canDeq && NOT_fetchStage_pipelines_0_first__0256_BITS_26_ETC___d22015) ? { fetchStage$pipelines_0_first[273:269], IF_fetchStage_pipelines_0_first__0256_BITS_268_ETC___d20382, @@ -15099,7 +15097,7 @@ module mkCore(CLK, fetchStage$pipelines_1_first[329:306], regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h968741, + renaming_spec_bits__h968739, fetchStage$pipelines_1_first[268:266] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -15248,7 +15246,7 @@ module mkCore(CLK, // submodule coreFix_fpuMulDivExe_0_dispToRegQ assign coreFix_fpuMulDivExe_0_dispToRegQ$enq_x = - { CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q364, + { CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q366, coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[65:9] } ; assign coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_correctSpeculation_mask = IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d20197 ; @@ -15360,8 +15358,8 @@ module mkCore(CLK, assign coreFix_fpuMulDivExe_0_fpuExec_double_fma$request_put = { coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd2, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14095, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q365, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q366, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q367, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q368, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14868 } ; assign coreFix_fpuMulDivExe_0_fpuExec_double_fma$EN_request_put = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && @@ -15578,19 +15576,19 @@ module mkCore(CLK, // submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tdata = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? - _theResult___fst__h836129 : - a__h835707 ; + _theResult___fst__h836126 : + a__h835704 ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tuser = - { b__h835708 == 64'd0, - a__h835707, + { b__h835705 == 64'd0, + a__h835704, coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0, - x__h836143, - a__h835707[63], + x__h836140, + a__h835704[63], 8'd0 } ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_divisor_tdata = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? - _theResult___snd__h836130 : - b__h835708 ; + _theResult___snd__h836127 : + b__h835705 ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tvalid = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && coreFix_fpuMulDivExe_0_regToExeQ$first[254:252] == 3'd3 && @@ -15651,20 +15649,20 @@ module mkCore(CLK, 1'd1 ; // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned - assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$A = a__h835707 ; - assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$B = b__h835708 ; + assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$A = a__h835704 ; + assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$B = b__h835705 ; // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned$A = - a__h835707 ; + a__h835704 ; assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned$B = - b__h835708 ; + b__h835705 ; // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned$A = - a__h835707 ; + a__h835704 ; assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned$B = - b__h835708 ; + b__h835705 ; // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ always@(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1 or @@ -15691,11 +15689,11 @@ module mkCore(CLK, // submodule coreFix_fpuMulDivExe_0_regToExeQ assign coreFix_fpuMulDivExe_0_regToExeQ$enq_x = - { CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q368, + { CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q370, coreFix_fpuMulDivExe_0_dispToRegQ$first[32:12], - x__h714429, - x__h714430, - x__h714431, + x__h714426, + x__h714427, + x__h714428, coreFix_fpuMulDivExe_0_dispToRegQ$first[11:0] } ; assign coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_correctSpeculation_mask = IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d20197 ; @@ -15747,7 +15745,7 @@ module mkCore(CLK, { IF_fetchStage_pipelines_1_first__0265_BITS_268_ETC___d21343, regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h968741, + renaming_spec_bits__h968739, fetchStage$pipelines_1_first[268:266] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -15901,7 +15899,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget : coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq_n = - x__h501097 ; + x__h501096 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n = (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[583:582] == 2'd0) ? @@ -16011,7 +16009,7 @@ module mkCore(CLK, // submodule coreFix_memExe_dMem_cache_m_banks_0_pRqMshr assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit_r = { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d7056, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q369 } ; + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q371 } ; assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq_n = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[580:579] ; assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getState_n = @@ -16333,7 +16331,7 @@ module mkCore(CLK, (fetchStage$pipelines_0_canDeq && regRenamingTable_rename_0_canRename__1151_AND__ETC___d22059) ? specTagManager$currentSpecBits : - renaming_spec_bits__h968741 ; + renaming_spec_bits__h968739 ; assign coreFix_memExe_lsq$enqSt_dst = (fetchStage$pipelines_0_canDeq && regRenamingTable_rename_0_canRename__1151_AND__ETC___d22068) ? @@ -16353,7 +16351,7 @@ module mkCore(CLK, (fetchStage$pipelines_0_canDeq && regRenamingTable_rename_0_canRename__1151_AND__ETC___d22068) ? specTagManager$currentSpecBits : - renaming_spec_bits__h968741 ; + renaming_spec_bits__h968739 ; assign coreFix_memExe_lsq$getHit_t = MUX_coreFix_memExe_lsq$getHit_1__SEL_1 ? MUX_coreFix_memExe_lsq$getHit_1__VAL_1 : @@ -16382,8 +16380,8 @@ module mkCore(CLK, MUX_coreFix_memExe_lsq$respLd_2__VAL_2 ; assign coreFix_memExe_lsq$respLd_t = WILL_FIRE_RL_coreFix_memExe_doRespLdMem ? - t__h212841 : - t__h215127 ; + t__h212839 : + t__h215125 ; assign coreFix_memExe_lsq$setAtCommit_0_put = rob$deqPort_0_deq_data[24:19] ; assign coreFix_memExe_lsq$setAtCommit_1_put = @@ -16436,7 +16434,7 @@ module mkCore(CLK, ~IF_coreFix_memExe_regToExeQ_first__645_BIT_103_ETC___d4017[2], IF_coreFix_memExe_regToExeQ_first__645_BIT_103_ETC___d4017[1:0], coreFix_memExe_regToExeQ$first[218:155] } : - { pointer__h242638[3:0] == 4'd0 && + { pointer__h242635[3:0] == 4'd0 && coreFix_memExe_lsq$getOrigBE[0] && coreFix_memExe_lsq$getOrigBE[1] && coreFix_memExe_lsq$getOrigBE[2] && @@ -16606,7 +16604,7 @@ module mkCore(CLK, !fetchStage$pipelines_1_first[239], regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h968741, + renaming_spec_bits__h968739, fetchStage$pipelines_1_first[268:266] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -16828,7 +16826,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd2049 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd7 ; assign csrf_stats_module_writeQ$DEQ = EN_sendDoStats ; assign csrf_stats_module_writeQ$CLR = 1'b0 ; @@ -16839,7 +16837,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd2048 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd6 ; assign csrf_terminate_module_terminateQ$DEQ = EN_coreIndInv_terminate ; assign csrf_terminate_module_terminateQ$CLR = 1'b0 ; @@ -17019,9 +17017,9 @@ module mkCore(CLK, always@(MUX_commitStage_rg_serial_num$write_1__SEL_1 or MUX_fetchStage$redirect_1__VAL_1 or WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or - new_pc__h872925 or + new_pc__h872924 or WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or - new_pc__h912073 or + new_pc__h912071 or WILL_FIRE_RL_commitStage_doCommitKilledLd or rob$deqPort_0_deq_data or WILL_FIRE_RL_commitStage_doCommitSystemInst or @@ -17032,9 +17030,9 @@ module mkCore(CLK, MUX_commitStage_rg_serial_num$write_1__SEL_1: fetchStage$redirect_pc = MUX_fetchStage$redirect_1__VAL_1; WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T: - fetchStage$redirect_pc = new_pc__h872925; + fetchStage$redirect_pc = new_pc__h872924; WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T: - fetchStage$redirect_pc = new_pc__h912073; + fetchStage$redirect_pc = new_pc__h912071; WILL_FIRE_RL_commitStage_doCommitKilledLd: fetchStage$redirect_pc = rob$deqPort_0_deq_data[630:502]; WILL_FIRE_RL_commitStage_doCommitSystemInst: @@ -17224,7 +17222,7 @@ module mkCore(CLK, assign regRenamingTable$rename_1_claimRename_r = fetchStage$pipelines_1_first[96:70] ; assign regRenamingTable$rename_1_claimRename_sb = - renaming_spec_bits__h968741 ; + renaming_spec_bits__h968739 ; assign regRenamingTable$rename_1_getRename_r = fetchStage$pipelines_1_first[96:70] ; assign regRenamingTable$specUpdate_correctSpeculation_mask = @@ -17501,7 +17499,7 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__0265_BITS_265_ETC___d22188, IF_NOT_fetchStage_pipelines_1_first__0265_BITS_ETC___d22242, 7'd32, - renaming_spec_bits__h968741 } ; + renaming_spec_bits__h968739 } ; assign rob$getOrigPC_0_get_x = coreFix_aluExe_0_dispToRegQ$first[52:41] ; assign rob$getOrigPC_1_get_x = coreFix_aluExe_1_dispToRegQ$first[52:41] ; assign rob$getOrigPC_2_get_x = 12'h0 ; @@ -17585,29 +17583,29 @@ module mkCore(CLK, always@(WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple or coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first or WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma or - data__h567680 or + data__h567678 or WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv or - data__h613440 or + data__h613438 or WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt or - data__h659187 or + data__h659185 or WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul or - data__h705001 or - WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv or data__h705864) + data__h704999 or + WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv or data__h705862) begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple: rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[101:38]; WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma: - rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = data__h567680; + rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = data__h567678; WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv: - rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = data__h613440; + rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = data__h613438; WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt: - rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = data__h659187; + rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = data__h659185; WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul: - rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = data__h705001; + rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = data__h704999; WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv: - rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = data__h705864; + rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = data__h705862; default: rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase @@ -18064,11 +18062,11 @@ module mkCore(CLK, module_amoExec instance_amoExec_5(.amoExec_amo_inst({ mmio_pRqQ_data_0[35:32], 4'd8 }), .amoExec_wordIdx(2'd0), - .amoExec_current({ 128'd0, r__h855583 }), + .amoExec_current({ 128'd0, r__h855582 }), .amoExec_inpt({ 97'd0, x__h65639 }), .amoExec(amoExec___d773)); module_amoExec instance_amoExec_4(.amoExec_amo_inst(coreFix_memExe_dMem_cache_m_banks_0_processAmo[11:4]), - .amoExec_wordIdx(wordIdx__h263233), + .amoExec_wordIdx(wordIdx__h263231), .amoExec_current({ SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4854, { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4861, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4867 } }), @@ -18085,12 +18083,12 @@ module mkCore(CLK, fetchStage$pipelines_0_first[81:77], { fetchStage$pipelines_0_first[76], fetchStage$pipelines_0_first[75:70] } } }), - .checkForException_csrState({ x_decodeInfo_frm__h926248, - r1__read_BITS_13_TO_12___h926454 != + .checkForException_csrState({ x_decodeInfo_frm__h926246, + r1__read_BITS_13_TO_12___h926452 != 2'd0, - { prv__h1017409, + { prv__h1017444, csrf_tvm_reg, - { r1__read_BIT_20___h926960, + { r1__read_BIT_20___h926958, csrf_tsr_reg, { csrf_mcounteren_cy_reg, csrf_mcounteren_cy_reg && @@ -18116,12 +18114,12 @@ module mkCore(CLK, fetchStage$pipelines_1_first[81:77], { fetchStage$pipelines_1_first[76], fetchStage$pipelines_1_first[75:70] } } }), - .checkForException_csrState({ x_decodeInfo_frm__h926248, - r1__read_BITS_13_TO_12___h926454 != + .checkForException_csrState({ x_decodeInfo_frm__h926246, + r1__read_BITS_13_TO_12___h926452 != 2'd0, - { prv__h1017409, + { prv__h1017444, csrf_tvm_reg, - { r1__read_BIT_20___h926960, + { r1__read_BIT_20___h926958, csrf_tsr_reg, { csrf_mcounteren_cy_reg, csrf_mcounteren_cy_reg && @@ -18132,14 +18130,14 @@ module mkCore(CLK, { csrf_mcounteren_tm_reg, csrf_mcounteren_tm_reg && csrf_scounteren_tm_reg } } } } } }), - .checkForException_pcc(pc__h963242), + .checkForException_pcc(pc__h963240), .checkForException_fourByteInst(fetchStage$pipelines_1_first[98:97] == 2'b11), .checkForException(checkForException___d21604)); module_capChecks instance_capChecks_0(.capChecks_a(coreFix_memExe_regToExeQ$first[384:222]), .capChecks_b(coreFix_memExe_regToExeQ$first[221:59]), .capChecks_ddc({ csrf_ddc_reg, - repBound__h248743, + repBound__h248740, { csrf_ddc_reg_read__051_BITS_27_TO_25_142_ULT_c_ETC___d4143, csrf_ddc_reg_read__051_BITS_13_TO_11_140_ULT_c_ETC___d4144, csrf_ddc_reg_read__051_BITS_85_TO_83_145_ULT_c_ETC___d4156 } }), @@ -18150,84 +18148,84 @@ module mkCore(CLK, .prepareBoundsCheck_b(coreFix_memExe_regToExeQ$first[221:59]), .prepareBoundsCheck_pcc(163'h400000000000000000003FFFC7FFFFD10000003F0), .prepareBoundsCheck_ddc({ csrf_ddc_reg, - repBound__h248743, + repBound__h248740, { csrf_ddc_reg_read__051_BITS_27_TO_25_142_ULT_c_ETC___d4143, csrf_ddc_reg_read__051_BITS_13_TO_11_140_ULT_c_ETC___d4144, csrf_ddc_reg_read__051_BITS_85_TO_83_145_ULT_c_ETC___d4156 } }), - .prepareBoundsCheck_vaddr(tmpAddr__h242837), - .prepareBoundsCheck_size(x__h249478 + - y__h249479), + .prepareBoundsCheck_vaddr(tmpAddr__h242834), + .prepareBoundsCheck_size(x__h249475 + + y__h249476), .prepareBoundsCheck_toCheck(coreFix_memExe_regToExeQ$first[58:12]), .prepareBoundsCheck(prepareBoundsCheck___d4244)); module_execFpuSimple instance_execFpuSimple_3(.execFpuSimple_fpu_inst({ coreFix_fpuMulDivExe_0_regToExeQ$first[233:229], - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q281, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q283, coreFix_fpuMulDivExe_0_regToExeQ$first[225] }), - .execFpuSimple_rVal1(rVal1__h714520), - .execFpuSimple_rVal2(rVal2__h714521), + .execFpuSimple_rVal1(rVal1__h714517), + .execFpuSimple_rVal2(rVal2__h714518), .execFpuSimple(execFpuSimple___d15207)); module_basicExec instance_basicExec_8(.basicExec_dInst({ coreFix_aluExe_1_regToExeQ$first[822:818], - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_817_ETC__q283, - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_787_ETC__q284, + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_817_ETC__q285, + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_787_ETC__q286, coreFix_aluExe_1_regToExeQ$first[776:729], - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_728_ETC__q285, + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_728_ETC__q287, coreFix_aluExe_1_regToExeQ$first[716], - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_715_ETC__q286, + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_715_ETC__q288, coreFix_aluExe_1_regToExeQ$first[710:678] }), .basicExec_rVal1(coreFix_aluExe_1_regToExeQ$first[632:470]), .basicExec_rVal2(coreFix_aluExe_1_regToExeQ$first[469:307]), .basicExec_pcc({ coreFix_aluExe_1_regToExeQ$first[306], - { cr_address__h866671, - cr_addrBits__h866672, + { cr_address__h866670, + cr_addrBits__h866671, { coreFix_aluExe_1_regToExeQ$first[305:290], - { cr_flags__h866674, - cr_reserved__h866675 }, + { cr_flags__h866673, + cr_reserved__h866674 }, INV_coreFix_aluExe_1_regToExeQ_first__7341_BIT_ETC___d17655 } }, - repBound__h867140, + repBound__h867139, { IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17662, IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17663, IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17675 } }), .basicExec_ppc({ coreFix_aluExe_1_regToExeQ$first[177], - { cr_address__h867219, - cr_addrBits__h867220, + { cr_address__h867218, + cr_addrBits__h867219, { coreFix_aluExe_1_regToExeQ$first[176:161], - { cr_flags__h867222, - cr_reserved__h867223 }, + { cr_flags__h867221, + cr_reserved__h867222 }, INV_coreFix_aluExe_1_regToExeQ_first__7341_BIT_ETC___d17719 } }, - repBound__h867688, + repBound__h867687, { IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17726, IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17727, IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17739 } }), .basicExec_orig_inst(coreFix_aluExe_1_regToExeQ$first[48:17]), .basicExec(basicExec___d17743)); module_basicExec instance_basicExec_7(.basicExec_dInst({ coreFix_aluExe_0_regToExeQ$first[822:818], - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_817_ETC__q288, - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_787_ETC__q289, + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_817_ETC__q290, + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_787_ETC__q291, coreFix_aluExe_0_regToExeQ$first[776:729], - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_728_ETC__q290, + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_728_ETC__q292, coreFix_aluExe_0_regToExeQ$first[716], - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_715_ETC__q291, + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_715_ETC__q293, coreFix_aluExe_0_regToExeQ$first[710:678] }), .basicExec_rVal1(coreFix_aluExe_0_regToExeQ$first[632:470]), .basicExec_rVal2(coreFix_aluExe_0_regToExeQ$first[469:307]), .basicExec_pcc({ coreFix_aluExe_0_regToExeQ$first[306], - { cr_address__h906357, - cr_addrBits__h906358, + { cr_address__h906355, + cr_addrBits__h906356, { coreFix_aluExe_0_regToExeQ$first[305:290], - { cr_flags__h906360, - cr_reserved__h906361 }, + { cr_flags__h906358, + cr_reserved__h906359 }, INV_coreFix_aluExe_0_regToExeQ_first__9457_BIT_ETC___d19771 } }, - repBound__h906826, + repBound__h906824, { IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19778, IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19779, IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19791 } }), .basicExec_ppc({ coreFix_aluExe_0_regToExeQ$first[177], - { cr_address__h906905, - cr_addrBits__h906906, + { cr_address__h906903, + cr_addrBits__h906904, { coreFix_aluExe_0_regToExeQ$first[176:161], - { cr_flags__h906908, - cr_reserved__h906909 }, + { cr_flags__h906906, + cr_reserved__h906907 }, INV_coreFix_aluExe_0_regToExeQ_first__9457_BIT_ETC___d19835 } }, - repBound__h907374, + repBound__h907372, { IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19842, IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19843, IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19855 } }), @@ -18235,1191 +18233,1191 @@ module mkCore(CLK, .basicExec(basicExec___d19859)); assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q110 = _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d11166 ? - _theResult___snd__h676124 : - _theResult____h667952 ; + _theResult___snd__h676122 : + _theResult____h667950 ; assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q40 = _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d8372 ? - _theResult___snd__h584628 : - _theResult____h576454 ; + _theResult___snd__h584626 : + _theResult____h576452 ; assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q75 = _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d9769 ? - _theResult___snd__h630377 : - _theResult____h622205 ; + _theResult___snd__h630375 : + _theResult____h622203 ; assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q150 = _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d13048 ? - _theResult___snd__h743927 : - _theResult____h735628 ; + _theResult___snd__h743924 : + _theResult____h735625 ; assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q167 = _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d13763 ? - _theResult___snd__h822084 : - _theResult____h813785 ; + _theResult___snd__h822081 : + _theResult____h813782 ; assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q190 = _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14533 ? - _theResult___snd__h782780 : - _theResult____h774481 ; + _theResult___snd__h782777 : + _theResult____h774478 ; assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q120 = _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d11717 ? - _theResult___snd__h693890 : - _theResult____h685589 ; + _theResult___snd__h693888 : + _theResult____h685587 ; assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q50 = _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d8923 ? - _theResult___snd__h602394 : - _theResult____h594093 ; + _theResult___snd__h602392 : + _theResult____h594091 ; assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q85 = _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d10320 ? - _theResult___snd__h648143 : - _theResult____h639842 ; + _theResult___snd__h648141 : + _theResult____h639840 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q146 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d12736 ? - _theResult___snd__h734276 : + _theResult___snd__h734273 : 57'd0 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q153 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d13098 ? - _theResult___snd__h734276 : - _theResult___snd__h752681 ; + _theResult___snd__h734273 : + _theResult___snd__h752678 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q163 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d13466 ? - _theResult___snd__h812433 : + _theResult___snd__h812430 : 57'd0 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q170 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d13813 ? - _theResult___snd__h812433 : - _theResult___snd__h830838 ; + _theResult___snd__h812430 : + _theResult___snd__h830835 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q186 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14236 ? - _theResult___snd__h773129 : + _theResult___snd__h773126 : 57'd0 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q193 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14583 ? - _theResult___snd__h773129 : - _theResult___snd__h791534 ; + _theResult___snd__h773126 : + _theResult___snd__h791531 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q112 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d11397 ? - _theResult___snd__h684706 : + _theResult___snd__h684704 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q125 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d11790 ? - _theResult___snd__h684706 : - _theResult___snd__h702496 ; + _theResult___snd__h684704 : + _theResult___snd__h702494 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q42 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d8603 ? - _theResult___snd__h593210 : + _theResult___snd__h593208 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q55 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d8996 ? - _theResult___snd__h593210 : - _theResult___snd__h611000 ; + _theResult___snd__h593208 : + _theResult___snd__h610998 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q77 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d10000 ? - _theResult___snd__h638959 : + _theResult___snd__h638957 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q90 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d10393 ? - _theResult___snd__h638959 : - _theResult___snd__h656749 ; + _theResult___snd__h638957 : + _theResult___snd__h656747 ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d10589 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9533 ? - ((_theResult___fst_exp__h630314 == 8'd255) ? + ((_theResult___fst_exp__h630312 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10574) : - ((_theResult___fst_exp__h638970 == 8'd255) ? + ((_theResult___fst_exp__h638968 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10587) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d10639 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9533 ? - ((_theResult___fst_exp__h630314 == 8'd255) ? + ((_theResult___fst_exp__h630312 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10630) : - ((_theResult___fst_exp__h638970 == 8'd255) ? + ((_theResult___fst_exp__h638968 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10637) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d11986 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10930 ? - ((_theResult___fst_exp__h676061 == 8'd255) ? + ((_theResult___fst_exp__h676059 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11971) : - ((_theResult___fst_exp__h684717 == 8'd255) ? + ((_theResult___fst_exp__h684715 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11984) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d12036 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10930 ? - ((_theResult___fst_exp__h676061 == 8'd255) ? + ((_theResult___fst_exp__h676059 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12027) : - ((_theResult___fst_exp__h684717 == 8'd255) ? + ((_theResult___fst_exp__h684715 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12034) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d9192 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8136 ? - ((_theResult___fst_exp__h584565 == 8'd255) ? + ((_theResult___fst_exp__h584563 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9177) : - ((_theResult___fst_exp__h593221 == 8'd255) ? + ((_theResult___fst_exp__h593219 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9190) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d9242 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8136 ? - ((_theResult___fst_exp__h584565 == 8'd255) ? + ((_theResult___fst_exp__h584563 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9233) : - ((_theResult___fst_exp__h593221 == 8'd255) ? + ((_theResult___fst_exp__h593219 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9240) ; assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d11164 = - (_theResult____h667952[56] ? + (_theResult____h667950[56] ? 6'd0 : - (_theResult____h667952[55] ? + (_theResult____h667950[55] ? 6'd1 : - (_theResult____h667952[54] ? + (_theResult____h667950[54] ? 6'd2 : - (_theResult____h667952[53] ? + (_theResult____h667950[53] ? 6'd3 : - (_theResult____h667952[52] ? + (_theResult____h667950[52] ? 6'd4 : - (_theResult____h667952[51] ? + (_theResult____h667950[51] ? 6'd5 : - (_theResult____h667952[50] ? + (_theResult____h667950[50] ? 6'd6 : - (_theResult____h667952[49] ? + (_theResult____h667950[49] ? 6'd7 : - (_theResult____h667952[48] ? + (_theResult____h667950[48] ? 6'd8 : - (_theResult____h667952[47] ? + (_theResult____h667950[47] ? 6'd9 : - (_theResult____h667952[46] ? + (_theResult____h667950[46] ? 6'd10 : - (_theResult____h667952[45] ? + (_theResult____h667950[45] ? 6'd11 : - (_theResult____h667952[44] ? + (_theResult____h667950[44] ? 6'd12 : - (_theResult____h667952[43] ? + (_theResult____h667950[43] ? 6'd13 : - (_theResult____h667952[42] ? + (_theResult____h667950[42] ? 6'd14 : - (_theResult____h667952[41] ? + (_theResult____h667950[41] ? 6'd15 : - (_theResult____h667952[40] ? + (_theResult____h667950[40] ? 6'd16 : - (_theResult____h667952[39] ? + (_theResult____h667950[39] ? 6'd17 : - (_theResult____h667952[38] ? + (_theResult____h667950[38] ? 6'd18 : - (_theResult____h667952[37] ? + (_theResult____h667950[37] ? 6'd19 : - (_theResult____h667952[36] ? + (_theResult____h667950[36] ? 6'd20 : - (_theResult____h667952[35] ? + (_theResult____h667950[35] ? 6'd21 : - (_theResult____h667952[34] ? + (_theResult____h667950[34] ? 6'd22 : - (_theResult____h667952[33] ? + (_theResult____h667950[33] ? 6'd23 : - (_theResult____h667952[32] ? + (_theResult____h667950[32] ? 6'd24 : - (_theResult____h667952[31] ? + (_theResult____h667950[31] ? 6'd25 : - (_theResult____h667952[30] ? + (_theResult____h667950[30] ? 6'd26 : - (_theResult____h667952[29] ? + (_theResult____h667950[29] ? 6'd27 : - (_theResult____h667952[28] ? + (_theResult____h667950[28] ? 6'd28 : - (_theResult____h667952[27] ? + (_theResult____h667950[27] ? 6'd29 : - (_theResult____h667952[26] ? + (_theResult____h667950[26] ? 6'd30 : - (_theResult____h667952[25] ? + (_theResult____h667950[25] ? 6'd31 : - (_theResult____h667952[24] ? + (_theResult____h667950[24] ? 6'd32 : - (_theResult____h667952[23] ? + (_theResult____h667950[23] ? 6'd33 : - (_theResult____h667952[22] ? + (_theResult____h667950[22] ? 6'd34 : - (_theResult____h667952[21] ? + (_theResult____h667950[21] ? 6'd35 : - (_theResult____h667952[20] ? + (_theResult____h667950[20] ? 6'd36 : - (_theResult____h667952[19] ? + (_theResult____h667950[19] ? 6'd37 : - (_theResult____h667952[18] ? + (_theResult____h667950[18] ? 6'd38 : - (_theResult____h667952[17] ? + (_theResult____h667950[17] ? 6'd39 : - (_theResult____h667952[16] ? + (_theResult____h667950[16] ? 6'd40 : - (_theResult____h667952[15] ? + (_theResult____h667950[15] ? 6'd41 : - (_theResult____h667952[14] ? + (_theResult____h667950[14] ? 6'd42 : - (_theResult____h667952[13] ? + (_theResult____h667950[13] ? 6'd43 : - (_theResult____h667952[12] ? + (_theResult____h667950[12] ? 6'd44 : - (_theResult____h667952[11] ? + (_theResult____h667950[11] ? 6'd45 : - (_theResult____h667952[10] ? + (_theResult____h667950[10] ? 6'd46 : - (_theResult____h667952[9] ? + (_theResult____h667950[9] ? 6'd47 : - (_theResult____h667952[8] ? + (_theResult____h667950[8] ? 6'd48 : - (_theResult____h667952[7] ? + (_theResult____h667950[7] ? 6'd49 : - (_theResult____h667952[6] ? + (_theResult____h667950[6] ? 6'd50 : - (_theResult____h667952[5] ? + (_theResult____h667950[5] ? 6'd51 : - (_theResult____h667952[4] ? + (_theResult____h667950[4] ? 6'd52 : - (_theResult____h667952[3] ? + (_theResult____h667950[3] ? 6'd53 : - (_theResult____h667952[2] ? + (_theResult____h667950[2] ? 6'd54 : - (_theResult____h667952[1] ? + (_theResult____h667950[1] ? 6'd55 : - (_theResult____h667952[0] ? + (_theResult____h667950[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d8370 = - (_theResult____h576454[56] ? + (_theResult____h576452[56] ? 6'd0 : - (_theResult____h576454[55] ? + (_theResult____h576452[55] ? 6'd1 : - (_theResult____h576454[54] ? + (_theResult____h576452[54] ? 6'd2 : - (_theResult____h576454[53] ? + (_theResult____h576452[53] ? 6'd3 : - (_theResult____h576454[52] ? + (_theResult____h576452[52] ? 6'd4 : - (_theResult____h576454[51] ? + (_theResult____h576452[51] ? 6'd5 : - (_theResult____h576454[50] ? + (_theResult____h576452[50] ? 6'd6 : - (_theResult____h576454[49] ? + (_theResult____h576452[49] ? 6'd7 : - (_theResult____h576454[48] ? + (_theResult____h576452[48] ? 6'd8 : - (_theResult____h576454[47] ? + (_theResult____h576452[47] ? 6'd9 : - (_theResult____h576454[46] ? + (_theResult____h576452[46] ? 6'd10 : - (_theResult____h576454[45] ? + (_theResult____h576452[45] ? 6'd11 : - (_theResult____h576454[44] ? + (_theResult____h576452[44] ? 6'd12 : - (_theResult____h576454[43] ? + (_theResult____h576452[43] ? 6'd13 : - (_theResult____h576454[42] ? + (_theResult____h576452[42] ? 6'd14 : - (_theResult____h576454[41] ? + (_theResult____h576452[41] ? 6'd15 : - (_theResult____h576454[40] ? + (_theResult____h576452[40] ? 6'd16 : - (_theResult____h576454[39] ? + (_theResult____h576452[39] ? 6'd17 : - (_theResult____h576454[38] ? + (_theResult____h576452[38] ? 6'd18 : - (_theResult____h576454[37] ? + (_theResult____h576452[37] ? 6'd19 : - (_theResult____h576454[36] ? + (_theResult____h576452[36] ? 6'd20 : - (_theResult____h576454[35] ? + (_theResult____h576452[35] ? 6'd21 : - (_theResult____h576454[34] ? + (_theResult____h576452[34] ? 6'd22 : - (_theResult____h576454[33] ? + (_theResult____h576452[33] ? 6'd23 : - (_theResult____h576454[32] ? + (_theResult____h576452[32] ? 6'd24 : - (_theResult____h576454[31] ? + (_theResult____h576452[31] ? 6'd25 : - (_theResult____h576454[30] ? + (_theResult____h576452[30] ? 6'd26 : - (_theResult____h576454[29] ? + (_theResult____h576452[29] ? 6'd27 : - (_theResult____h576454[28] ? + (_theResult____h576452[28] ? 6'd28 : - (_theResult____h576454[27] ? + (_theResult____h576452[27] ? 6'd29 : - (_theResult____h576454[26] ? + (_theResult____h576452[26] ? 6'd30 : - (_theResult____h576454[25] ? + (_theResult____h576452[25] ? 6'd31 : - (_theResult____h576454[24] ? + (_theResult____h576452[24] ? 6'd32 : - (_theResult____h576454[23] ? + (_theResult____h576452[23] ? 6'd33 : - (_theResult____h576454[22] ? + (_theResult____h576452[22] ? 6'd34 : - (_theResult____h576454[21] ? + (_theResult____h576452[21] ? 6'd35 : - (_theResult____h576454[20] ? + (_theResult____h576452[20] ? 6'd36 : - (_theResult____h576454[19] ? + (_theResult____h576452[19] ? 6'd37 : - (_theResult____h576454[18] ? + (_theResult____h576452[18] ? 6'd38 : - (_theResult____h576454[17] ? + (_theResult____h576452[17] ? 6'd39 : - (_theResult____h576454[16] ? + (_theResult____h576452[16] ? 6'd40 : - (_theResult____h576454[15] ? + (_theResult____h576452[15] ? 6'd41 : - (_theResult____h576454[14] ? + (_theResult____h576452[14] ? 6'd42 : - (_theResult____h576454[13] ? + (_theResult____h576452[13] ? 6'd43 : - (_theResult____h576454[12] ? + (_theResult____h576452[12] ? 6'd44 : - (_theResult____h576454[11] ? + (_theResult____h576452[11] ? 6'd45 : - (_theResult____h576454[10] ? + (_theResult____h576452[10] ? 6'd46 : - (_theResult____h576454[9] ? + (_theResult____h576452[9] ? 6'd47 : - (_theResult____h576454[8] ? + (_theResult____h576452[8] ? 6'd48 : - (_theResult____h576454[7] ? + (_theResult____h576452[7] ? 6'd49 : - (_theResult____h576454[6] ? + (_theResult____h576452[6] ? 6'd50 : - (_theResult____h576454[5] ? + (_theResult____h576452[5] ? 6'd51 : - (_theResult____h576454[4] ? + (_theResult____h576452[4] ? 6'd52 : - (_theResult____h576454[3] ? + (_theResult____h576452[3] ? 6'd53 : - (_theResult____h576454[2] ? + (_theResult____h576452[2] ? 6'd54 : - (_theResult____h576454[1] ? + (_theResult____h576452[1] ? 6'd55 : - (_theResult____h576454[0] ? + (_theResult____h576452[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d9767 = - (_theResult____h622205[56] ? + (_theResult____h622203[56] ? 6'd0 : - (_theResult____h622205[55] ? + (_theResult____h622203[55] ? 6'd1 : - (_theResult____h622205[54] ? + (_theResult____h622203[54] ? 6'd2 : - (_theResult____h622205[53] ? + (_theResult____h622203[53] ? 6'd3 : - (_theResult____h622205[52] ? + (_theResult____h622203[52] ? 6'd4 : - (_theResult____h622205[51] ? + (_theResult____h622203[51] ? 6'd5 : - (_theResult____h622205[50] ? + (_theResult____h622203[50] ? 6'd6 : - (_theResult____h622205[49] ? + (_theResult____h622203[49] ? 6'd7 : - (_theResult____h622205[48] ? + (_theResult____h622203[48] ? 6'd8 : - (_theResult____h622205[47] ? + (_theResult____h622203[47] ? 6'd9 : - (_theResult____h622205[46] ? + (_theResult____h622203[46] ? 6'd10 : - (_theResult____h622205[45] ? + (_theResult____h622203[45] ? 6'd11 : - (_theResult____h622205[44] ? + (_theResult____h622203[44] ? 6'd12 : - (_theResult____h622205[43] ? + (_theResult____h622203[43] ? 6'd13 : - (_theResult____h622205[42] ? + (_theResult____h622203[42] ? 6'd14 : - (_theResult____h622205[41] ? + (_theResult____h622203[41] ? 6'd15 : - (_theResult____h622205[40] ? + (_theResult____h622203[40] ? 6'd16 : - (_theResult____h622205[39] ? + (_theResult____h622203[39] ? 6'd17 : - (_theResult____h622205[38] ? + (_theResult____h622203[38] ? 6'd18 : - (_theResult____h622205[37] ? + (_theResult____h622203[37] ? 6'd19 : - (_theResult____h622205[36] ? + (_theResult____h622203[36] ? 6'd20 : - (_theResult____h622205[35] ? + (_theResult____h622203[35] ? 6'd21 : - (_theResult____h622205[34] ? + (_theResult____h622203[34] ? 6'd22 : - (_theResult____h622205[33] ? + (_theResult____h622203[33] ? 6'd23 : - (_theResult____h622205[32] ? + (_theResult____h622203[32] ? 6'd24 : - (_theResult____h622205[31] ? + (_theResult____h622203[31] ? 6'd25 : - (_theResult____h622205[30] ? + (_theResult____h622203[30] ? 6'd26 : - (_theResult____h622205[29] ? + (_theResult____h622203[29] ? 6'd27 : - (_theResult____h622205[28] ? + (_theResult____h622203[28] ? 6'd28 : - (_theResult____h622205[27] ? + (_theResult____h622203[27] ? 6'd29 : - (_theResult____h622205[26] ? + (_theResult____h622203[26] ? 6'd30 : - (_theResult____h622205[25] ? + (_theResult____h622203[25] ? 6'd31 : - (_theResult____h622205[24] ? + (_theResult____h622203[24] ? 6'd32 : - (_theResult____h622205[23] ? + (_theResult____h622203[23] ? 6'd33 : - (_theResult____h622205[22] ? + (_theResult____h622203[22] ? 6'd34 : - (_theResult____h622205[21] ? + (_theResult____h622203[21] ? 6'd35 : - (_theResult____h622205[20] ? + (_theResult____h622203[20] ? 6'd36 : - (_theResult____h622205[19] ? + (_theResult____h622203[19] ? 6'd37 : - (_theResult____h622205[18] ? + (_theResult____h622203[18] ? 6'd38 : - (_theResult____h622205[17] ? + (_theResult____h622203[17] ? 6'd39 : - (_theResult____h622205[16] ? + (_theResult____h622203[16] ? 6'd40 : - (_theResult____h622205[15] ? + (_theResult____h622203[15] ? 6'd41 : - (_theResult____h622205[14] ? + (_theResult____h622203[14] ? 6'd42 : - (_theResult____h622205[13] ? + (_theResult____h622203[13] ? 6'd43 : - (_theResult____h622205[12] ? + (_theResult____h622203[12] ? 6'd44 : - (_theResult____h622205[11] ? + (_theResult____h622203[11] ? 6'd45 : - (_theResult____h622205[10] ? + (_theResult____h622203[10] ? 6'd46 : - (_theResult____h622205[9] ? + (_theResult____h622203[9] ? 6'd47 : - (_theResult____h622205[8] ? + (_theResult____h622203[8] ? 6'd48 : - (_theResult____h622205[7] ? + (_theResult____h622203[7] ? 6'd49 : - (_theResult____h622205[6] ? + (_theResult____h622203[6] ? 6'd50 : - (_theResult____h622205[5] ? + (_theResult____h622203[5] ? 6'd51 : - (_theResult____h622205[4] ? + (_theResult____h622203[4] ? 6'd52 : - (_theResult____h622205[3] ? + (_theResult____h622203[3] ? 6'd53 : - (_theResult____h622205[2] ? + (_theResult____h622203[2] ? 6'd54 : - (_theResult____h622205[1] ? + (_theResult____h622203[1] ? 6'd55 : - (_theResult____h622205[0] ? + (_theResult____h622203[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d13046 = - (_theResult____h735628[56] ? + (_theResult____h735625[56] ? 6'd0 : - (_theResult____h735628[55] ? + (_theResult____h735625[55] ? 6'd1 : - (_theResult____h735628[54] ? + (_theResult____h735625[54] ? 6'd2 : - (_theResult____h735628[53] ? + (_theResult____h735625[53] ? 6'd3 : - (_theResult____h735628[52] ? + (_theResult____h735625[52] ? 6'd4 : - (_theResult____h735628[51] ? + (_theResult____h735625[51] ? 6'd5 : - (_theResult____h735628[50] ? + (_theResult____h735625[50] ? 6'd6 : - (_theResult____h735628[49] ? + (_theResult____h735625[49] ? 6'd7 : - (_theResult____h735628[48] ? + (_theResult____h735625[48] ? 6'd8 : - (_theResult____h735628[47] ? + (_theResult____h735625[47] ? 6'd9 : - (_theResult____h735628[46] ? + (_theResult____h735625[46] ? 6'd10 : - (_theResult____h735628[45] ? + (_theResult____h735625[45] ? 6'd11 : - (_theResult____h735628[44] ? + (_theResult____h735625[44] ? 6'd12 : - (_theResult____h735628[43] ? + (_theResult____h735625[43] ? 6'd13 : - (_theResult____h735628[42] ? + (_theResult____h735625[42] ? 6'd14 : - (_theResult____h735628[41] ? + (_theResult____h735625[41] ? 6'd15 : - (_theResult____h735628[40] ? + (_theResult____h735625[40] ? 6'd16 : - (_theResult____h735628[39] ? + (_theResult____h735625[39] ? 6'd17 : - (_theResult____h735628[38] ? + (_theResult____h735625[38] ? 6'd18 : - (_theResult____h735628[37] ? + (_theResult____h735625[37] ? 6'd19 : - (_theResult____h735628[36] ? + (_theResult____h735625[36] ? 6'd20 : - (_theResult____h735628[35] ? + (_theResult____h735625[35] ? 6'd21 : - (_theResult____h735628[34] ? + (_theResult____h735625[34] ? 6'd22 : - (_theResult____h735628[33] ? + (_theResult____h735625[33] ? 6'd23 : - (_theResult____h735628[32] ? + (_theResult____h735625[32] ? 6'd24 : - (_theResult____h735628[31] ? + (_theResult____h735625[31] ? 6'd25 : - (_theResult____h735628[30] ? + (_theResult____h735625[30] ? 6'd26 : - (_theResult____h735628[29] ? + (_theResult____h735625[29] ? 6'd27 : - (_theResult____h735628[28] ? + (_theResult____h735625[28] ? 6'd28 : - (_theResult____h735628[27] ? + (_theResult____h735625[27] ? 6'd29 : - (_theResult____h735628[26] ? + (_theResult____h735625[26] ? 6'd30 : - (_theResult____h735628[25] ? + (_theResult____h735625[25] ? 6'd31 : - (_theResult____h735628[24] ? + (_theResult____h735625[24] ? 6'd32 : - (_theResult____h735628[23] ? + (_theResult____h735625[23] ? 6'd33 : - (_theResult____h735628[22] ? + (_theResult____h735625[22] ? 6'd34 : - (_theResult____h735628[21] ? + (_theResult____h735625[21] ? 6'd35 : - (_theResult____h735628[20] ? + (_theResult____h735625[20] ? 6'd36 : - (_theResult____h735628[19] ? + (_theResult____h735625[19] ? 6'd37 : - (_theResult____h735628[18] ? + (_theResult____h735625[18] ? 6'd38 : - (_theResult____h735628[17] ? + (_theResult____h735625[17] ? 6'd39 : - (_theResult____h735628[16] ? + (_theResult____h735625[16] ? 6'd40 : - (_theResult____h735628[15] ? + (_theResult____h735625[15] ? 6'd41 : - (_theResult____h735628[14] ? + (_theResult____h735625[14] ? 6'd42 : - (_theResult____h735628[13] ? + (_theResult____h735625[13] ? 6'd43 : - (_theResult____h735628[12] ? + (_theResult____h735625[12] ? 6'd44 : - (_theResult____h735628[11] ? + (_theResult____h735625[11] ? 6'd45 : - (_theResult____h735628[10] ? + (_theResult____h735625[10] ? 6'd46 : - (_theResult____h735628[9] ? + (_theResult____h735625[9] ? 6'd47 : - (_theResult____h735628[8] ? + (_theResult____h735625[8] ? 6'd48 : - (_theResult____h735628[7] ? + (_theResult____h735625[7] ? 6'd49 : - (_theResult____h735628[6] ? + (_theResult____h735625[6] ? 6'd50 : - (_theResult____h735628[5] ? + (_theResult____h735625[5] ? 6'd51 : - (_theResult____h735628[4] ? + (_theResult____h735625[4] ? 6'd52 : - (_theResult____h735628[3] ? + (_theResult____h735625[3] ? 6'd53 : - (_theResult____h735628[2] ? + (_theResult____h735625[2] ? 6'd54 : - (_theResult____h735628[1] ? + (_theResult____h735625[1] ? 6'd55 : - (_theResult____h735628[0] ? + (_theResult____h735625[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d13761 = - (_theResult____h813785[56] ? + (_theResult____h813782[56] ? 6'd0 : - (_theResult____h813785[55] ? + (_theResult____h813782[55] ? 6'd1 : - (_theResult____h813785[54] ? + (_theResult____h813782[54] ? 6'd2 : - (_theResult____h813785[53] ? + (_theResult____h813782[53] ? 6'd3 : - (_theResult____h813785[52] ? + (_theResult____h813782[52] ? 6'd4 : - (_theResult____h813785[51] ? + (_theResult____h813782[51] ? 6'd5 : - (_theResult____h813785[50] ? + (_theResult____h813782[50] ? 6'd6 : - (_theResult____h813785[49] ? + (_theResult____h813782[49] ? 6'd7 : - (_theResult____h813785[48] ? + (_theResult____h813782[48] ? 6'd8 : - (_theResult____h813785[47] ? + (_theResult____h813782[47] ? 6'd9 : - (_theResult____h813785[46] ? + (_theResult____h813782[46] ? 6'd10 : - (_theResult____h813785[45] ? + (_theResult____h813782[45] ? 6'd11 : - (_theResult____h813785[44] ? + (_theResult____h813782[44] ? 6'd12 : - (_theResult____h813785[43] ? + (_theResult____h813782[43] ? 6'd13 : - (_theResult____h813785[42] ? + (_theResult____h813782[42] ? 6'd14 : - (_theResult____h813785[41] ? + (_theResult____h813782[41] ? 6'd15 : - (_theResult____h813785[40] ? + (_theResult____h813782[40] ? 6'd16 : - (_theResult____h813785[39] ? + (_theResult____h813782[39] ? 6'd17 : - (_theResult____h813785[38] ? + (_theResult____h813782[38] ? 6'd18 : - (_theResult____h813785[37] ? + (_theResult____h813782[37] ? 6'd19 : - (_theResult____h813785[36] ? + (_theResult____h813782[36] ? 6'd20 : - (_theResult____h813785[35] ? + (_theResult____h813782[35] ? 6'd21 : - (_theResult____h813785[34] ? + (_theResult____h813782[34] ? 6'd22 : - (_theResult____h813785[33] ? + (_theResult____h813782[33] ? 6'd23 : - (_theResult____h813785[32] ? + (_theResult____h813782[32] ? 6'd24 : - (_theResult____h813785[31] ? + (_theResult____h813782[31] ? 6'd25 : - (_theResult____h813785[30] ? + (_theResult____h813782[30] ? 6'd26 : - (_theResult____h813785[29] ? + (_theResult____h813782[29] ? 6'd27 : - (_theResult____h813785[28] ? + (_theResult____h813782[28] ? 6'd28 : - (_theResult____h813785[27] ? + (_theResult____h813782[27] ? 6'd29 : - (_theResult____h813785[26] ? + (_theResult____h813782[26] ? 6'd30 : - (_theResult____h813785[25] ? + (_theResult____h813782[25] ? 6'd31 : - (_theResult____h813785[24] ? + (_theResult____h813782[24] ? 6'd32 : - (_theResult____h813785[23] ? + (_theResult____h813782[23] ? 6'd33 : - (_theResult____h813785[22] ? + (_theResult____h813782[22] ? 6'd34 : - (_theResult____h813785[21] ? + (_theResult____h813782[21] ? 6'd35 : - (_theResult____h813785[20] ? + (_theResult____h813782[20] ? 6'd36 : - (_theResult____h813785[19] ? + (_theResult____h813782[19] ? 6'd37 : - (_theResult____h813785[18] ? + (_theResult____h813782[18] ? 6'd38 : - (_theResult____h813785[17] ? + (_theResult____h813782[17] ? 6'd39 : - (_theResult____h813785[16] ? + (_theResult____h813782[16] ? 6'd40 : - (_theResult____h813785[15] ? + (_theResult____h813782[15] ? 6'd41 : - (_theResult____h813785[14] ? + (_theResult____h813782[14] ? 6'd42 : - (_theResult____h813785[13] ? + (_theResult____h813782[13] ? 6'd43 : - (_theResult____h813785[12] ? + (_theResult____h813782[12] ? 6'd44 : - (_theResult____h813785[11] ? + (_theResult____h813782[11] ? 6'd45 : - (_theResult____h813785[10] ? + (_theResult____h813782[10] ? 6'd46 : - (_theResult____h813785[9] ? + (_theResult____h813782[9] ? 6'd47 : - (_theResult____h813785[8] ? + (_theResult____h813782[8] ? 6'd48 : - (_theResult____h813785[7] ? + (_theResult____h813782[7] ? 6'd49 : - (_theResult____h813785[6] ? + (_theResult____h813782[6] ? 6'd50 : - (_theResult____h813785[5] ? + (_theResult____h813782[5] ? 6'd51 : - (_theResult____h813785[4] ? + (_theResult____h813782[4] ? 6'd52 : - (_theResult____h813785[3] ? + (_theResult____h813782[3] ? 6'd53 : - (_theResult____h813785[2] ? + (_theResult____h813782[2] ? 6'd54 : - (_theResult____h813785[1] ? + (_theResult____h813782[1] ? 6'd55 : - (_theResult____h813785[0] ? + (_theResult____h813782[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d14531 = - (_theResult____h774481[56] ? + (_theResult____h774478[56] ? 6'd0 : - (_theResult____h774481[55] ? + (_theResult____h774478[55] ? 6'd1 : - (_theResult____h774481[54] ? + (_theResult____h774478[54] ? 6'd2 : - (_theResult____h774481[53] ? + (_theResult____h774478[53] ? 6'd3 : - (_theResult____h774481[52] ? + (_theResult____h774478[52] ? 6'd4 : - (_theResult____h774481[51] ? + (_theResult____h774478[51] ? 6'd5 : - (_theResult____h774481[50] ? + (_theResult____h774478[50] ? 6'd6 : - (_theResult____h774481[49] ? + (_theResult____h774478[49] ? 6'd7 : - (_theResult____h774481[48] ? + (_theResult____h774478[48] ? 6'd8 : - (_theResult____h774481[47] ? + (_theResult____h774478[47] ? 6'd9 : - (_theResult____h774481[46] ? + (_theResult____h774478[46] ? 6'd10 : - (_theResult____h774481[45] ? + (_theResult____h774478[45] ? 6'd11 : - (_theResult____h774481[44] ? + (_theResult____h774478[44] ? 6'd12 : - (_theResult____h774481[43] ? + (_theResult____h774478[43] ? 6'd13 : - (_theResult____h774481[42] ? + (_theResult____h774478[42] ? 6'd14 : - (_theResult____h774481[41] ? + (_theResult____h774478[41] ? 6'd15 : - (_theResult____h774481[40] ? + (_theResult____h774478[40] ? 6'd16 : - (_theResult____h774481[39] ? + (_theResult____h774478[39] ? 6'd17 : - (_theResult____h774481[38] ? + (_theResult____h774478[38] ? 6'd18 : - (_theResult____h774481[37] ? + (_theResult____h774478[37] ? 6'd19 : - (_theResult____h774481[36] ? + (_theResult____h774478[36] ? 6'd20 : - (_theResult____h774481[35] ? + (_theResult____h774478[35] ? 6'd21 : - (_theResult____h774481[34] ? + (_theResult____h774478[34] ? 6'd22 : - (_theResult____h774481[33] ? + (_theResult____h774478[33] ? 6'd23 : - (_theResult____h774481[32] ? + (_theResult____h774478[32] ? 6'd24 : - (_theResult____h774481[31] ? + (_theResult____h774478[31] ? 6'd25 : - (_theResult____h774481[30] ? + (_theResult____h774478[30] ? 6'd26 : - (_theResult____h774481[29] ? + (_theResult____h774478[29] ? 6'd27 : - (_theResult____h774481[28] ? + (_theResult____h774478[28] ? 6'd28 : - (_theResult____h774481[27] ? + (_theResult____h774478[27] ? 6'd29 : - (_theResult____h774481[26] ? + (_theResult____h774478[26] ? 6'd30 : - (_theResult____h774481[25] ? + (_theResult____h774478[25] ? 6'd31 : - (_theResult____h774481[24] ? + (_theResult____h774478[24] ? 6'd32 : - (_theResult____h774481[23] ? + (_theResult____h774478[23] ? 6'd33 : - (_theResult____h774481[22] ? + (_theResult____h774478[22] ? 6'd34 : - (_theResult____h774481[21] ? + (_theResult____h774478[21] ? 6'd35 : - (_theResult____h774481[20] ? + (_theResult____h774478[20] ? 6'd36 : - (_theResult____h774481[19] ? + (_theResult____h774478[19] ? 6'd37 : - (_theResult____h774481[18] ? + (_theResult____h774478[18] ? 6'd38 : - (_theResult____h774481[17] ? + (_theResult____h774478[17] ? 6'd39 : - (_theResult____h774481[16] ? + (_theResult____h774478[16] ? 6'd40 : - (_theResult____h774481[15] ? + (_theResult____h774478[15] ? 6'd41 : - (_theResult____h774481[14] ? + (_theResult____h774478[14] ? 6'd42 : - (_theResult____h774481[13] ? + (_theResult____h774478[13] ? 6'd43 : - (_theResult____h774481[12] ? + (_theResult____h774478[12] ? 6'd44 : - (_theResult____h774481[11] ? + (_theResult____h774478[11] ? 6'd45 : - (_theResult____h774481[10] ? + (_theResult____h774478[10] ? 6'd46 : - (_theResult____h774481[9] ? + (_theResult____h774478[9] ? 6'd47 : - (_theResult____h774481[8] ? + (_theResult____h774478[8] ? 6'd48 : - (_theResult____h774481[7] ? + (_theResult____h774478[7] ? 6'd49 : - (_theResult____h774481[6] ? + (_theResult____h774478[6] ? 6'd50 : - (_theResult____h774481[5] ? + (_theResult____h774478[5] ? 6'd51 : - (_theResult____h774481[4] ? + (_theResult____h774478[4] ? 6'd52 : - (_theResult____h774481[3] ? + (_theResult____h774478[3] ? 6'd53 : - (_theResult____h774481[2] ? + (_theResult____h774478[2] ? 6'd54 : - (_theResult____h774481[1] ? + (_theResult____h774478[1] ? 6'd55 : - (_theResult____h774481[0] ? + (_theResult____h774478[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d10318 = - (_theResult____h639842[56] ? + (_theResult____h639840[56] ? 6'd0 : - (_theResult____h639842[55] ? + (_theResult____h639840[55] ? 6'd1 : - (_theResult____h639842[54] ? + (_theResult____h639840[54] ? 6'd2 : - (_theResult____h639842[53] ? + (_theResult____h639840[53] ? 6'd3 : - (_theResult____h639842[52] ? + (_theResult____h639840[52] ? 6'd4 : - (_theResult____h639842[51] ? + (_theResult____h639840[51] ? 6'd5 : - (_theResult____h639842[50] ? + (_theResult____h639840[50] ? 6'd6 : - (_theResult____h639842[49] ? + (_theResult____h639840[49] ? 6'd7 : - (_theResult____h639842[48] ? + (_theResult____h639840[48] ? 6'd8 : - (_theResult____h639842[47] ? + (_theResult____h639840[47] ? 6'd9 : - (_theResult____h639842[46] ? + (_theResult____h639840[46] ? 6'd10 : - (_theResult____h639842[45] ? + (_theResult____h639840[45] ? 6'd11 : - (_theResult____h639842[44] ? + (_theResult____h639840[44] ? 6'd12 : - (_theResult____h639842[43] ? + (_theResult____h639840[43] ? 6'd13 : - (_theResult____h639842[42] ? + (_theResult____h639840[42] ? 6'd14 : - (_theResult____h639842[41] ? + (_theResult____h639840[41] ? 6'd15 : - (_theResult____h639842[40] ? + (_theResult____h639840[40] ? 6'd16 : - (_theResult____h639842[39] ? + (_theResult____h639840[39] ? 6'd17 : - (_theResult____h639842[38] ? + (_theResult____h639840[38] ? 6'd18 : - (_theResult____h639842[37] ? + (_theResult____h639840[37] ? 6'd19 : - (_theResult____h639842[36] ? + (_theResult____h639840[36] ? 6'd20 : - (_theResult____h639842[35] ? + (_theResult____h639840[35] ? 6'd21 : - (_theResult____h639842[34] ? + (_theResult____h639840[34] ? 6'd22 : - (_theResult____h639842[33] ? + (_theResult____h639840[33] ? 6'd23 : - (_theResult____h639842[32] ? + (_theResult____h639840[32] ? 6'd24 : - (_theResult____h639842[31] ? + (_theResult____h639840[31] ? 6'd25 : - (_theResult____h639842[30] ? + (_theResult____h639840[30] ? 6'd26 : - (_theResult____h639842[29] ? + (_theResult____h639840[29] ? 6'd27 : - (_theResult____h639842[28] ? + (_theResult____h639840[28] ? 6'd28 : - (_theResult____h639842[27] ? + (_theResult____h639840[27] ? 6'd29 : - (_theResult____h639842[26] ? + (_theResult____h639840[26] ? 6'd30 : - (_theResult____h639842[25] ? + (_theResult____h639840[25] ? 6'd31 : - (_theResult____h639842[24] ? + (_theResult____h639840[24] ? 6'd32 : - (_theResult____h639842[23] ? + (_theResult____h639840[23] ? 6'd33 : - (_theResult____h639842[22] ? + (_theResult____h639840[22] ? 6'd34 : - (_theResult____h639842[21] ? + (_theResult____h639840[21] ? 6'd35 : - (_theResult____h639842[20] ? + (_theResult____h639840[20] ? 6'd36 : - (_theResult____h639842[19] ? + (_theResult____h639840[19] ? 6'd37 : - (_theResult____h639842[18] ? + (_theResult____h639840[18] ? 6'd38 : - (_theResult____h639842[17] ? + (_theResult____h639840[17] ? 6'd39 : - (_theResult____h639842[16] ? + (_theResult____h639840[16] ? 6'd40 : - (_theResult____h639842[15] ? + (_theResult____h639840[15] ? 6'd41 : - (_theResult____h639842[14] ? + (_theResult____h639840[14] ? 6'd42 : - (_theResult____h639842[13] ? + (_theResult____h639840[13] ? 6'd43 : - (_theResult____h639842[12] ? + (_theResult____h639840[12] ? 6'd44 : - (_theResult____h639842[11] ? + (_theResult____h639840[11] ? 6'd45 : - (_theResult____h639842[10] ? + (_theResult____h639840[10] ? 6'd46 : - (_theResult____h639842[9] ? + (_theResult____h639840[9] ? 6'd47 : - (_theResult____h639842[8] ? + (_theResult____h639840[8] ? 6'd48 : - (_theResult____h639842[7] ? + (_theResult____h639840[7] ? 6'd49 : - (_theResult____h639842[6] ? + (_theResult____h639840[6] ? 6'd50 : - (_theResult____h639842[5] ? + (_theResult____h639840[5] ? 6'd51 : - (_theResult____h639842[4] ? + (_theResult____h639840[4] ? 6'd52 : - (_theResult____h639842[3] ? + (_theResult____h639840[3] ? 6'd53 : - (_theResult____h639842[2] ? + (_theResult____h639840[2] ? 6'd54 : - (_theResult____h639842[1] ? + (_theResult____h639840[1] ? 6'd55 : - (_theResult____h639842[0] ? + (_theResult____h639840[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d11715 = - (_theResult____h685589[56] ? + (_theResult____h685587[56] ? 6'd0 : - (_theResult____h685589[55] ? + (_theResult____h685587[55] ? 6'd1 : - (_theResult____h685589[54] ? + (_theResult____h685587[54] ? 6'd2 : - (_theResult____h685589[53] ? + (_theResult____h685587[53] ? 6'd3 : - (_theResult____h685589[52] ? + (_theResult____h685587[52] ? 6'd4 : - (_theResult____h685589[51] ? + (_theResult____h685587[51] ? 6'd5 : - (_theResult____h685589[50] ? + (_theResult____h685587[50] ? 6'd6 : - (_theResult____h685589[49] ? + (_theResult____h685587[49] ? 6'd7 : - (_theResult____h685589[48] ? + (_theResult____h685587[48] ? 6'd8 : - (_theResult____h685589[47] ? + (_theResult____h685587[47] ? 6'd9 : - (_theResult____h685589[46] ? + (_theResult____h685587[46] ? 6'd10 : - (_theResult____h685589[45] ? + (_theResult____h685587[45] ? 6'd11 : - (_theResult____h685589[44] ? + (_theResult____h685587[44] ? 6'd12 : - (_theResult____h685589[43] ? + (_theResult____h685587[43] ? 6'd13 : - (_theResult____h685589[42] ? + (_theResult____h685587[42] ? 6'd14 : - (_theResult____h685589[41] ? + (_theResult____h685587[41] ? 6'd15 : - (_theResult____h685589[40] ? + (_theResult____h685587[40] ? 6'd16 : - (_theResult____h685589[39] ? + (_theResult____h685587[39] ? 6'd17 : - (_theResult____h685589[38] ? + (_theResult____h685587[38] ? 6'd18 : - (_theResult____h685589[37] ? + (_theResult____h685587[37] ? 6'd19 : - (_theResult____h685589[36] ? + (_theResult____h685587[36] ? 6'd20 : - (_theResult____h685589[35] ? + (_theResult____h685587[35] ? 6'd21 : - (_theResult____h685589[34] ? + (_theResult____h685587[34] ? 6'd22 : - (_theResult____h685589[33] ? + (_theResult____h685587[33] ? 6'd23 : - (_theResult____h685589[32] ? + (_theResult____h685587[32] ? 6'd24 : - (_theResult____h685589[31] ? + (_theResult____h685587[31] ? 6'd25 : - (_theResult____h685589[30] ? + (_theResult____h685587[30] ? 6'd26 : - (_theResult____h685589[29] ? + (_theResult____h685587[29] ? 6'd27 : - (_theResult____h685589[28] ? + (_theResult____h685587[28] ? 6'd28 : - (_theResult____h685589[27] ? + (_theResult____h685587[27] ? 6'd29 : - (_theResult____h685589[26] ? + (_theResult____h685587[26] ? 6'd30 : - (_theResult____h685589[25] ? + (_theResult____h685587[25] ? 6'd31 : - (_theResult____h685589[24] ? + (_theResult____h685587[24] ? 6'd32 : - (_theResult____h685589[23] ? + (_theResult____h685587[23] ? 6'd33 : - (_theResult____h685589[22] ? + (_theResult____h685587[22] ? 6'd34 : - (_theResult____h685589[21] ? + (_theResult____h685587[21] ? 6'd35 : - (_theResult____h685589[20] ? + (_theResult____h685587[20] ? 6'd36 : - (_theResult____h685589[19] ? + (_theResult____h685587[19] ? 6'd37 : - (_theResult____h685589[18] ? + (_theResult____h685587[18] ? 6'd38 : - (_theResult____h685589[17] ? + (_theResult____h685587[17] ? 6'd39 : - (_theResult____h685589[16] ? + (_theResult____h685587[16] ? 6'd40 : - (_theResult____h685589[15] ? + (_theResult____h685587[15] ? 6'd41 : - (_theResult____h685589[14] ? + (_theResult____h685587[14] ? 6'd42 : - (_theResult____h685589[13] ? + (_theResult____h685587[13] ? 6'd43 : - (_theResult____h685589[12] ? + (_theResult____h685587[12] ? 6'd44 : - (_theResult____h685589[11] ? + (_theResult____h685587[11] ? 6'd45 : - (_theResult____h685589[10] ? + (_theResult____h685587[10] ? 6'd46 : - (_theResult____h685589[9] ? + (_theResult____h685587[9] ? 6'd47 : - (_theResult____h685589[8] ? + (_theResult____h685587[8] ? 6'd48 : - (_theResult____h685589[7] ? + (_theResult____h685587[7] ? 6'd49 : - (_theResult____h685589[6] ? + (_theResult____h685587[6] ? 6'd50 : - (_theResult____h685589[5] ? + (_theResult____h685587[5] ? 6'd51 : - (_theResult____h685589[4] ? + (_theResult____h685587[4] ? 6'd52 : - (_theResult____h685589[3] ? + (_theResult____h685587[3] ? 6'd53 : - (_theResult____h685589[2] ? + (_theResult____h685587[2] ? 6'd54 : - (_theResult____h685589[1] ? + (_theResult____h685587[1] ? 6'd55 : - (_theResult____h685589[0] ? + (_theResult____h685587[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d8921 = - (_theResult____h594093[56] ? + (_theResult____h594091[56] ? 6'd0 : - (_theResult____h594093[55] ? + (_theResult____h594091[55] ? 6'd1 : - (_theResult____h594093[54] ? + (_theResult____h594091[54] ? 6'd2 : - (_theResult____h594093[53] ? + (_theResult____h594091[53] ? 6'd3 : - (_theResult____h594093[52] ? + (_theResult____h594091[52] ? 6'd4 : - (_theResult____h594093[51] ? + (_theResult____h594091[51] ? 6'd5 : - (_theResult____h594093[50] ? + (_theResult____h594091[50] ? 6'd6 : - (_theResult____h594093[49] ? + (_theResult____h594091[49] ? 6'd7 : - (_theResult____h594093[48] ? + (_theResult____h594091[48] ? 6'd8 : - (_theResult____h594093[47] ? + (_theResult____h594091[47] ? 6'd9 : - (_theResult____h594093[46] ? + (_theResult____h594091[46] ? 6'd10 : - (_theResult____h594093[45] ? + (_theResult____h594091[45] ? 6'd11 : - (_theResult____h594093[44] ? + (_theResult____h594091[44] ? 6'd12 : - (_theResult____h594093[43] ? + (_theResult____h594091[43] ? 6'd13 : - (_theResult____h594093[42] ? + (_theResult____h594091[42] ? 6'd14 : - (_theResult____h594093[41] ? + (_theResult____h594091[41] ? 6'd15 : - (_theResult____h594093[40] ? + (_theResult____h594091[40] ? 6'd16 : - (_theResult____h594093[39] ? + (_theResult____h594091[39] ? 6'd17 : - (_theResult____h594093[38] ? + (_theResult____h594091[38] ? 6'd18 : - (_theResult____h594093[37] ? + (_theResult____h594091[37] ? 6'd19 : - (_theResult____h594093[36] ? + (_theResult____h594091[36] ? 6'd20 : - (_theResult____h594093[35] ? + (_theResult____h594091[35] ? 6'd21 : - (_theResult____h594093[34] ? + (_theResult____h594091[34] ? 6'd22 : - (_theResult____h594093[33] ? + (_theResult____h594091[33] ? 6'd23 : - (_theResult____h594093[32] ? + (_theResult____h594091[32] ? 6'd24 : - (_theResult____h594093[31] ? + (_theResult____h594091[31] ? 6'd25 : - (_theResult____h594093[30] ? + (_theResult____h594091[30] ? 6'd26 : - (_theResult____h594093[29] ? + (_theResult____h594091[29] ? 6'd27 : - (_theResult____h594093[28] ? + (_theResult____h594091[28] ? 6'd28 : - (_theResult____h594093[27] ? + (_theResult____h594091[27] ? 6'd29 : - (_theResult____h594093[26] ? + (_theResult____h594091[26] ? 6'd30 : - (_theResult____h594093[25] ? + (_theResult____h594091[25] ? 6'd31 : - (_theResult____h594093[24] ? + (_theResult____h594091[24] ? 6'd32 : - (_theResult____h594093[23] ? + (_theResult____h594091[23] ? 6'd33 : - (_theResult____h594093[22] ? + (_theResult____h594091[22] ? 6'd34 : - (_theResult____h594093[21] ? + (_theResult____h594091[21] ? 6'd35 : - (_theResult____h594093[20] ? + (_theResult____h594091[20] ? 6'd36 : - (_theResult____h594093[19] ? + (_theResult____h594091[19] ? 6'd37 : - (_theResult____h594093[18] ? + (_theResult____h594091[18] ? 6'd38 : - (_theResult____h594093[17] ? + (_theResult____h594091[17] ? 6'd39 : - (_theResult____h594093[16] ? + (_theResult____h594091[16] ? 6'd40 : - (_theResult____h594093[15] ? + (_theResult____h594091[15] ? 6'd41 : - (_theResult____h594093[14] ? + (_theResult____h594091[14] ? 6'd42 : - (_theResult____h594093[13] ? + (_theResult____h594091[13] ? 6'd43 : - (_theResult____h594093[12] ? + (_theResult____h594091[12] ? 6'd44 : - (_theResult____h594093[11] ? + (_theResult____h594091[11] ? 6'd45 : - (_theResult____h594093[10] ? + (_theResult____h594091[10] ? 6'd46 : - (_theResult____h594093[9] ? + (_theResult____h594091[9] ? 6'd47 : - (_theResult____h594093[8] ? + (_theResult____h594091[8] ? 6'd48 : - (_theResult____h594093[7] ? + (_theResult____h594091[7] ? 6'd49 : - (_theResult____h594093[6] ? + (_theResult____h594091[6] ? 6'd50 : - (_theResult____h594093[5] ? + (_theResult____h594091[5] ? 6'd51 : - (_theResult____h594093[4] ? + (_theResult____h594091[4] ? 6'd52 : - (_theResult____h594093[3] ? + (_theResult____h594091[3] ? 6'd53 : - (_theResult____h594093[2] ? + (_theResult____h594091[2] ? 6'd54 : - (_theResult____h594093[1] ? + (_theResult____h594091[1] ? 6'd55 : - (_theResult____h594093[0] ? + (_theResult____h594091[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d13090 = - (_theResult___fst_exp__h743864 == 11'd2047) ? + (_theResult___fst_exp__h743861 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : @@ -19427,10 +19425,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard35638_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q159 : + CASE_guard35635_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q159 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q160) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d13805 = - (_theResult___fst_exp__h822021 == 11'd2047) ? + (_theResult___fst_exp__h822018 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -19438,10 +19436,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard13795_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q176 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q177) ; + CASE_guard13792_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q174 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q175) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d14073 = - (_theResult___fst_exp__h822021 == 11'd2047) ? + (_theResult___fst_exp__h822018 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -19449,10 +19447,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard13795_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q180 : + CASE_guard13792_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q180 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q181) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d14575 = - (_theResult___fst_exp__h782717 == 11'd2047) ? + (_theResult___fst_exp__h782714 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -19460,10 +19458,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard74491_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q207 : + CASE_guard74488_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q207 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q208) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d14842 = - (_theResult___fst_exp__h782717 == 11'd2047) ? + (_theResult___fst_exp__h782714 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -19471,404 +19469,404 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard74491_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q211 : + CASE_guard74488_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q211 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q212) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d10477 = - (guard__h622215 == 2'b0 || + (guard__h622213 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - sfdin__h630308[56:34] : - _theResult___sfd__h630831 ; + sfdin__h630306[56:34] : + _theResult___sfd__h630829 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d10479 = - (guard__h622215 == 2'b0) ? - sfdin__h630308[56:34] : + (guard__h622213 == 2'b0) ? + sfdin__h630306[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h630831 : - sfdin__h630308[56:34]) ; + _theResult___sfd__h630829 : + sfdin__h630306[56:34]) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11227 = - (guard__h667962 == 2'b0 || + (guard__h667960 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h676061 : - _theResult___exp__h676577 ; + _theResult___fst_exp__h676059 : + _theResult___exp__h676575 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11230 = - (guard__h667962 == 2'b0) ? - _theResult___fst_exp__h676061 : + (guard__h667960 == 2'b0) ? + _theResult___fst_exp__h676059 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h676577 : - _theResult___fst_exp__h676061) ; + _theResult___exp__h676575 : + _theResult___fst_exp__h676059) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11874 = - (guard__h667962 == 2'b0 || + (guard__h667960 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - sfdin__h676055[56:34] : - _theResult___sfd__h676578 ; + sfdin__h676053[56:34] : + _theResult___sfd__h676576 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11876 = - (guard__h667962 == 2'b0) ? - sfdin__h676055[56:34] : + (guard__h667960 == 2'b0) ? + sfdin__h676053[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h676578 : - sfdin__h676055[56:34]) ; + _theResult___sfd__h676576 : + sfdin__h676053[56:34]) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d8433 = - (guard__h576464 == 2'b0 || + (guard__h576462 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h584565 : - _theResult___exp__h585081 ; + _theResult___fst_exp__h584563 : + _theResult___exp__h585079 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d8436 = - (guard__h576464 == 2'b0) ? - _theResult___fst_exp__h584565 : + (guard__h576462 == 2'b0) ? + _theResult___fst_exp__h584563 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h585081 : - _theResult___fst_exp__h584565) ; + _theResult___exp__h585079 : + _theResult___fst_exp__h584563) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9080 = - (guard__h576464 == 2'b0 || + (guard__h576462 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - sfdin__h584559[56:34] : - _theResult___sfd__h585082 ; + sfdin__h584557[56:34] : + _theResult___sfd__h585080 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9082 = - (guard__h576464 == 2'b0) ? - sfdin__h584559[56:34] : + (guard__h576462 == 2'b0) ? + sfdin__h584557[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h585082 : - sfdin__h584559[56:34]) ; + _theResult___sfd__h585080 : + sfdin__h584557[56:34]) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9830 = - (guard__h622215 == 2'b0 || + (guard__h622213 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h630314 : - _theResult___exp__h630830 ; + _theResult___fst_exp__h630312 : + _theResult___exp__h630828 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9833 = - (guard__h622215 == 2'b0) ? - _theResult___fst_exp__h630314 : + (guard__h622213 == 2'b0) ? + _theResult___fst_exp__h630312 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h630830 : - _theResult___fst_exp__h630314) ; + _theResult___exp__h630828 : + _theResult___fst_exp__h630312) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13207 = - (guard__h735638 == 2'b0 || + (guard__h735635 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___fst_exp__h743864 : - _theResult___exp__h744593 ; + _theResult___fst_exp__h743861 : + _theResult___exp__h744590 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13209 = - (guard__h735638 == 2'b0) ? - _theResult___fst_exp__h743864 : + (guard__h735635 == 2'b0) ? + _theResult___fst_exp__h743861 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___exp__h744593 : - _theResult___fst_exp__h743864) ; + _theResult___exp__h744590 : + _theResult___fst_exp__h743861) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13291 = - (guard__h735638 == 2'b0 || + (guard__h735635 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - sfdin__h743858[56:5] : - _theResult___sfd__h744594 ; + sfdin__h743855[56:5] : + _theResult___sfd__h744591 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13293 = - (guard__h735638 == 2'b0) ? - sfdin__h743858[56:5] : + (guard__h735635 == 2'b0) ? + sfdin__h743855[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___sfd__h744594 : - sfdin__h743858[56:5]) ; + _theResult___sfd__h744591 : + sfdin__h743855[56:5]) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13917 = - (guard__h813795 == 2'b0 || + (guard__h813792 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___fst_exp__h822021 : - _theResult___exp__h822750 ; + _theResult___fst_exp__h822018 : + _theResult___exp__h822747 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13919 = - (guard__h813795 == 2'b0) ? - _theResult___fst_exp__h822021 : + (guard__h813792 == 2'b0) ? + _theResult___fst_exp__h822018 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___exp__h822750 : - _theResult___fst_exp__h822021) ; + _theResult___exp__h822747 : + _theResult___fst_exp__h822018) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14000 = - (guard__h813795 == 2'b0 || + (guard__h813792 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - sfdin__h822015[56:5] : - _theResult___sfd__h822751 ; + sfdin__h822012[56:5] : + _theResult___sfd__h822748 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14002 = - (guard__h813795 == 2'b0) ? - sfdin__h822015[56:5] : + (guard__h813792 == 2'b0) ? + sfdin__h822012[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___sfd__h822751 : - sfdin__h822015[56:5]) ; + _theResult___sfd__h822748 : + sfdin__h822012[56:5]) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14687 = - (guard__h774491 == 2'b0 || + (guard__h774488 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___fst_exp__h782717 : - _theResult___exp__h783446 ; + _theResult___fst_exp__h782714 : + _theResult___exp__h783443 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14689 = - (guard__h774491 == 2'b0) ? - _theResult___fst_exp__h782717 : + (guard__h774488 == 2'b0) ? + _theResult___fst_exp__h782714 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___exp__h783446 : - _theResult___fst_exp__h782717) ; + _theResult___exp__h783443 : + _theResult___fst_exp__h782714) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14770 = - (guard__h774491 == 2'b0 || + (guard__h774488 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - sfdin__h782711[56:5] : - _theResult___sfd__h783447 ; + sfdin__h782708[56:5] : + _theResult___sfd__h783444 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14772 = - (guard__h774491 == 2'b0) ? - sfdin__h782711[56:5] : + (guard__h774488 == 2'b0) ? + sfdin__h782708[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___sfd__h783447 : - sfdin__h782711[56:5]) ; + _theResult___sfd__h783444 : + sfdin__h782708[56:5]) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10377 = - (guard__h639852 == 2'b0 || + (guard__h639850 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h648080 : - _theResult___exp__h648596 ; + _theResult___fst_exp__h648078 : + _theResult___exp__h648594 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10379 = - (guard__h639852 == 2'b0) ? - _theResult___fst_exp__h648080 : + (guard__h639850 == 2'b0) ? + _theResult___fst_exp__h648078 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h648596 : - _theResult___fst_exp__h648080) ; + _theResult___exp__h648594 : + _theResult___fst_exp__h648078) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10523 = - (guard__h639852 == 2'b0 || + (guard__h639850 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - sfdin__h648074[56:34] : - _theResult___sfd__h648597 ; + sfdin__h648072[56:34] : + _theResult___sfd__h648595 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10525 = - (guard__h639852 == 2'b0) ? - sfdin__h648074[56:34] : + (guard__h639850 == 2'b0) ? + sfdin__h648072[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h648597 : - sfdin__h648074[56:34]) ; + _theResult___sfd__h648595 : + sfdin__h648072[56:34]) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11774 = - (guard__h685599 == 2'b0 || + (guard__h685597 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h693827 : - _theResult___exp__h694343 ; + _theResult___fst_exp__h693825 : + _theResult___exp__h694341 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11776 = - (guard__h685599 == 2'b0) ? - _theResult___fst_exp__h693827 : + (guard__h685597 == 2'b0) ? + _theResult___fst_exp__h693825 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h694343 : - _theResult___fst_exp__h693827) ; + _theResult___exp__h694341 : + _theResult___fst_exp__h693825) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11920 = - (guard__h685599 == 2'b0 || + (guard__h685597 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - sfdin__h693821[56:34] : - _theResult___sfd__h694344 ; + sfdin__h693819[56:34] : + _theResult___sfd__h694342 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11922 = - (guard__h685599 == 2'b0) ? - sfdin__h693821[56:34] : + (guard__h685597 == 2'b0) ? + sfdin__h693819[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h694344 : - sfdin__h693821[56:34]) ; + _theResult___sfd__h694342 : + sfdin__h693819[56:34]) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d8980 = - (guard__h594103 == 2'b0 || + (guard__h594101 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h602331 : - _theResult___exp__h602847 ; + _theResult___fst_exp__h602329 : + _theResult___exp__h602845 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d8982 = - (guard__h594103 == 2'b0) ? - _theResult___fst_exp__h602331 : + (guard__h594101 == 2'b0) ? + _theResult___fst_exp__h602329 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h602847 : - _theResult___fst_exp__h602331) ; + _theResult___exp__h602845 : + _theResult___fst_exp__h602329) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9126 = - (guard__h594103 == 2'b0 || + (guard__h594101 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - sfdin__h602325[56:34] : - _theResult___sfd__h602848 ; + sfdin__h602323[56:34] : + _theResult___sfd__h602846 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9128 = - (guard__h594103 == 2'b0) ? - sfdin__h602325[56:34] : + (guard__h594101 == 2'b0) ? + sfdin__h602323[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h602848 : - sfdin__h602325[56:34]) ; + _theResult___sfd__h602846 : + sfdin__h602323[56:34]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13164 = - (guard__h726326 == 2'b0 || + (guard__h726323 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___fst_exp__h734287 : - _theResult___exp__h734942 ; + _theResult___fst_exp__h734284 : + _theResult___exp__h734939 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13166 = - (guard__h726326 == 2'b0) ? - _theResult___fst_exp__h734287 : + (guard__h726323 == 2'b0) ? + _theResult___fst_exp__h734284 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___exp__h734942 : - _theResult___fst_exp__h734287) ; + _theResult___exp__h734939 : + _theResult___fst_exp__h734284) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13238 = - (guard__h744707 == 2'b0 || + (guard__h744704 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___fst_exp__h752697 : - _theResult___exp__h753377 ; + _theResult___fst_exp__h752694 : + _theResult___exp__h753374 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13240 = - (guard__h744707 == 2'b0) ? - _theResult___fst_exp__h752697 : + (guard__h744704 == 2'b0) ? + _theResult___fst_exp__h752694 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___exp__h753377 : - _theResult___fst_exp__h752697) ; + _theResult___exp__h753374 : + _theResult___fst_exp__h752694) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13264 = - (guard__h726326 == 2'b0 || + (guard__h726323 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___snd__h734238[56:5] : - _theResult___sfd__h734943 ; + _theResult___snd__h734235[56:5] : + _theResult___sfd__h734940 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13266 = - (guard__h726326 == 2'b0) ? - _theResult___snd__h734238[56:5] : + (guard__h726323 == 2'b0) ? + _theResult___snd__h734235[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___sfd__h734943 : - _theResult___snd__h734238[56:5]) ; + _theResult___sfd__h734940 : + _theResult___snd__h734235[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13310 = - (guard__h744707 == 2'b0 || + (guard__h744704 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___snd__h752643[56:5] : - _theResult___sfd__h753378 ; + _theResult___snd__h752640[56:5] : + _theResult___sfd__h753375 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13312 = - (guard__h744707 == 2'b0) ? - _theResult___snd__h752643[56:5] : + (guard__h744704 == 2'b0) ? + _theResult___snd__h752640[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___sfd__h753378 : - _theResult___snd__h752643[56:5]) ; + _theResult___sfd__h753375 : + _theResult___snd__h752640[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13879 = - (guard__h804483 == 2'b0 || + (guard__h804480 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___fst_exp__h812444 : - _theResult___exp__h813099 ; + _theResult___fst_exp__h812441 : + _theResult___exp__h813096 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13881 = - (guard__h804483 == 2'b0) ? - _theResult___fst_exp__h812444 : + (guard__h804480 == 2'b0) ? + _theResult___fst_exp__h812441 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___exp__h813099 : - _theResult___fst_exp__h812444) ; + _theResult___exp__h813096 : + _theResult___fst_exp__h812441) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13948 = - (guard__h822864 == 2'b0 || + (guard__h822861 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___fst_exp__h830854 : - _theResult___exp__h831534 ; + _theResult___fst_exp__h830851 : + _theResult___exp__h831531 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13950 = - (guard__h822864 == 2'b0) ? - _theResult___fst_exp__h830854 : + (guard__h822861 == 2'b0) ? + _theResult___fst_exp__h830851 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___exp__h831534 : - _theResult___fst_exp__h830854) ; + _theResult___exp__h831531 : + _theResult___fst_exp__h830851) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13974 = - (guard__h804483 == 2'b0 || + (guard__h804480 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___snd__h812395[56:5] : - _theResult___sfd__h813100 ; + _theResult___snd__h812392[56:5] : + _theResult___sfd__h813097 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13976 = - (guard__h804483 == 2'b0) ? - _theResult___snd__h812395[56:5] : + (guard__h804480 == 2'b0) ? + _theResult___snd__h812392[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___sfd__h813100 : - _theResult___snd__h812395[56:5]) ; + _theResult___sfd__h813097 : + _theResult___snd__h812392[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14019 = - (guard__h822864 == 2'b0 || + (guard__h822861 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___snd__h830800[56:5] : - _theResult___sfd__h831535 ; + _theResult___snd__h830797[56:5] : + _theResult___sfd__h831532 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14021 = - (guard__h822864 == 2'b0) ? - _theResult___snd__h830800[56:5] : + (guard__h822861 == 2'b0) ? + _theResult___snd__h830797[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___sfd__h831535 : - _theResult___snd__h830800[56:5]) ; + _theResult___sfd__h831532 : + _theResult___snd__h830797[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14649 = - (guard__h765179 == 2'b0 || + (guard__h765176 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___fst_exp__h773140 : - _theResult___exp__h773795 ; + _theResult___fst_exp__h773137 : + _theResult___exp__h773792 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14651 = - (guard__h765179 == 2'b0) ? - _theResult___fst_exp__h773140 : + (guard__h765176 == 2'b0) ? + _theResult___fst_exp__h773137 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___exp__h773795 : - _theResult___fst_exp__h773140) ; + _theResult___exp__h773792 : + _theResult___fst_exp__h773137) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14718 = - (guard__h783560 == 2'b0 || + (guard__h783557 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___fst_exp__h791550 : - _theResult___exp__h792230 ; + _theResult___fst_exp__h791547 : + _theResult___exp__h792227 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14720 = - (guard__h783560 == 2'b0) ? - _theResult___fst_exp__h791550 : + (guard__h783557 == 2'b0) ? + _theResult___fst_exp__h791547 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___exp__h792230 : - _theResult___fst_exp__h791550) ; + _theResult___exp__h792227 : + _theResult___fst_exp__h791547) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14744 = - (guard__h765179 == 2'b0 || + (guard__h765176 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___snd__h773091[56:5] : - _theResult___sfd__h773796 ; + _theResult___snd__h773088[56:5] : + _theResult___sfd__h773793 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14746 = - (guard__h765179 == 2'b0) ? - _theResult___snd__h773091[56:5] : + (guard__h765176 == 2'b0) ? + _theResult___snd__h773088[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___sfd__h773796 : - _theResult___snd__h773091[56:5]) ; + _theResult___sfd__h773793 : + _theResult___snd__h773088[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14789 = - (guard__h783560 == 2'b0 || + (guard__h783557 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___snd__h791496[56:5] : - _theResult___sfd__h792231 ; + _theResult___snd__h791493[56:5] : + _theResult___sfd__h792228 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14791 = - (guard__h783560 == 2'b0) ? - _theResult___snd__h791496[56:5] : + (guard__h783557 == 2'b0) ? + _theResult___snd__h791493[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___sfd__h792231 : - _theResult___snd__h791496[56:5]) ; + _theResult___sfd__h792228 : + _theResult___snd__h791493[56:5]) ; assign IF_IF_IF_NOT_csrf_prv_reg_read__0286_EQ_3_0287_ETC___d20929 = (IF_IF_NOT_csrf_prv_reg_read__0286_EQ_3_0287_02_ETC___d20323[0] || IF_IF_NOT_csrf_prv_reg_read__0286_EQ_3_0287_02_ETC___d20323[1] || @@ -20080,139 +20078,139 @@ module mkCore(CLK, IF_checkForException_0654_BITS_3_TO_0_0907_EQ__ETC___d20927 == 4'd9 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10052 = - (guard__h630922 == 2'b0 || + (guard__h630920 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h638970 : - _theResult___exp__h639412 ; + _theResult___fst_exp__h638968 : + _theResult___exp__h639410 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10054 = - (guard__h630922 == 2'b0) ? - _theResult___fst_exp__h638970 : + (guard__h630920 == 2'b0) ? + _theResult___fst_exp__h638968 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h639412 : - _theResult___fst_exp__h638970) ; + _theResult___exp__h639410 : + _theResult___fst_exp__h638968) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10446 = - (guard__h648688 == 2'b0 || + (guard__h648686 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h656765 : - _theResult___exp__h657232 ; + _theResult___fst_exp__h656763 : + _theResult___exp__h657230 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10448 = - (guard__h648688 == 2'b0) ? - _theResult___fst_exp__h656765 : + (guard__h648686 == 2'b0) ? + _theResult___fst_exp__h656763 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h657232 : - _theResult___fst_exp__h656765) ; + _theResult___exp__h657230 : + _theResult___fst_exp__h656763) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10496 = - (guard__h630922 == 2'b0 || + (guard__h630920 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___snd__h638921[56:34] : - _theResult___sfd__h639413 ; + _theResult___snd__h638919[56:34] : + _theResult___sfd__h639411 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10498 = - (guard__h630922 == 2'b0) ? - _theResult___snd__h638921[56:34] : + (guard__h630920 == 2'b0) ? + _theResult___snd__h638919[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h639413 : - _theResult___snd__h638921[56:34]) ; + _theResult___sfd__h639411 : + _theResult___snd__h638919[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10542 = - (guard__h648688 == 2'b0 || + (guard__h648686 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___snd__h656711[56:34] : - _theResult___sfd__h657233 ; + _theResult___snd__h656709[56:34] : + _theResult___sfd__h657231 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10544 = - (guard__h648688 == 2'b0) ? - _theResult___snd__h656711[56:34] : + (guard__h648686 == 2'b0) ? + _theResult___snd__h656709[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h657233 : - _theResult___snd__h656711[56:34]) ; + _theResult___sfd__h657231 : + _theResult___snd__h656709[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11449 = - (guard__h676669 == 2'b0 || + (guard__h676667 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h684717 : - _theResult___exp__h685159 ; + _theResult___fst_exp__h684715 : + _theResult___exp__h685157 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11451 = - (guard__h676669 == 2'b0) ? - _theResult___fst_exp__h684717 : + (guard__h676667 == 2'b0) ? + _theResult___fst_exp__h684715 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h685159 : - _theResult___fst_exp__h684717) ; + _theResult___exp__h685157 : + _theResult___fst_exp__h684715) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11843 = - (guard__h694435 == 2'b0 || + (guard__h694433 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h702512 : - _theResult___exp__h702979 ; + _theResult___fst_exp__h702510 : + _theResult___exp__h702977 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11845 = - (guard__h694435 == 2'b0) ? - _theResult___fst_exp__h702512 : + (guard__h694433 == 2'b0) ? + _theResult___fst_exp__h702510 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h702979 : - _theResult___fst_exp__h702512) ; + _theResult___exp__h702977 : + _theResult___fst_exp__h702510) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11893 = - (guard__h676669 == 2'b0 || + (guard__h676667 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___snd__h684668[56:34] : - _theResult___sfd__h685160 ; + _theResult___snd__h684666[56:34] : + _theResult___sfd__h685158 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11895 = - (guard__h676669 == 2'b0) ? - _theResult___snd__h684668[56:34] : + (guard__h676667 == 2'b0) ? + _theResult___snd__h684666[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h685160 : - _theResult___snd__h684668[56:34]) ; + _theResult___sfd__h685158 : + _theResult___snd__h684666[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11939 = - (guard__h694435 == 2'b0 || + (guard__h694433 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___snd__h702458[56:34] : - _theResult___sfd__h702980 ; + _theResult___snd__h702456[56:34] : + _theResult___sfd__h702978 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11941 = - (guard__h694435 == 2'b0) ? - _theResult___snd__h702458[56:34] : + (guard__h694433 == 2'b0) ? + _theResult___snd__h702456[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h702980 : - _theResult___snd__h702458[56:34]) ; + _theResult___sfd__h702978 : + _theResult___snd__h702456[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d8655 = - (guard__h585173 == 2'b0 || + (guard__h585171 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h593221 : - _theResult___exp__h593663 ; + _theResult___fst_exp__h593219 : + _theResult___exp__h593661 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d8657 = - (guard__h585173 == 2'b0) ? - _theResult___fst_exp__h593221 : + (guard__h585171 == 2'b0) ? + _theResult___fst_exp__h593219 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h593663 : - _theResult___fst_exp__h593221) ; + _theResult___exp__h593661 : + _theResult___fst_exp__h593219) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9049 = - (guard__h602939 == 2'b0 || + (guard__h602937 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h611016 : - _theResult___exp__h611483 ; + _theResult___fst_exp__h611014 : + _theResult___exp__h611481 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9051 = - (guard__h602939 == 2'b0) ? - _theResult___fst_exp__h611016 : + (guard__h602937 == 2'b0) ? + _theResult___fst_exp__h611014 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h611483 : - _theResult___fst_exp__h611016) ; + _theResult___exp__h611481 : + _theResult___fst_exp__h611014) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9099 = - (guard__h585173 == 2'b0 || + (guard__h585171 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___snd__h593172[56:34] : - _theResult___sfd__h593664 ; + _theResult___snd__h593170[56:34] : + _theResult___sfd__h593662 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9101 = - (guard__h585173 == 2'b0) ? - _theResult___snd__h593172[56:34] : + (guard__h585171 == 2'b0) ? + _theResult___snd__h593170[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h593664 : - _theResult___snd__h593172[56:34]) ; + _theResult___sfd__h593662 : + _theResult___snd__h593170[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9145 = - (guard__h602939 == 2'b0 || + (guard__h602937 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___snd__h610962[56:34] : - _theResult___sfd__h611484 ; + _theResult___snd__h610960[56:34] : + _theResult___sfd__h611482 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9147 = - (guard__h602939 == 2'b0) ? - _theResult___snd__h610962[56:34] : + (guard__h602937 == 2'b0) ? + _theResult___snd__h610960[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h611484 : - _theResult___snd__h610962[56:34]) ; + _theResult___sfd__h611482 : + _theResult___snd__h610960[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d13136 = - (_theResult___fst_exp__h752697 == 11'd2047) ? + (_theResult___fst_exp__h752694 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : @@ -20220,10 +20218,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard44707_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q161 : + CASE_guard44704_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q161 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q162) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d13851 = - (_theResult___fst_exp__h830854 == 11'd2047) ? + (_theResult___fst_exp__h830851 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -20231,10 +20229,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard22864_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q178 : + CASE_guard22861_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q178 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q179) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d14058 = - (_theResult___fst_exp__h812444 == 11'd2047) ? + (_theResult___fst_exp__h812441 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -20242,10 +20240,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard04483_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q184 : + CASE_guard04480_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q184 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q185) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d14085 = - (_theResult___fst_exp__h830854 == 11'd2047) ? + (_theResult___fst_exp__h830851 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -20253,10 +20251,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard22864_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q182 : + CASE_guard22861_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q182 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q183) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d14621 = - (_theResult___fst_exp__h791550 == 11'd2047) ? + (_theResult___fst_exp__h791547 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -20264,10 +20262,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard83560_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q209 : + CASE_guard83557_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q209 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q210) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d14827 = - (_theResult___fst_exp__h773140 == 11'd2047) ? + (_theResult___fst_exp__h773137 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -20275,10 +20273,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard65179_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q215 : + CASE_guard65176_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q215 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q216) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d14854 = - (_theResult___fst_exp__h791550 == 11'd2047) ? + (_theResult___fst_exp__h791547 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -20286,14 +20284,14 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard83560_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q213 : + CASE_guard83557_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q213 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q214) ; assign IF_IF_NOT_csrf_prv_reg_read__0286_EQ_3_0287_02_ETC___d20323 = - (_theResult____h920232 == 16'd0 && + (_theResult____h920230 == 16'd0 && (csrf_prv_reg == 2'd0 || csrf_prv_reg == 2'd1 && csrf_ie_vec_1)) ? - enabled_ints__h920803 : - _theResult____h920232 ; + enabled_ints__h920801 : + _theResult____h920230 ; assign IF_IF_NOT_csrf_prv_reg_read__0286_EQ_3_0287_02_ETC___d20676 = IF_IF_NOT_csrf_prv_reg_read__0286_EQ_3_0287_02_ETC___d20323[0] || IF_IF_NOT_csrf_prv_reg_read__0286_EQ_3_0287_02_ETC___d20323[1] || @@ -20738,148 +20736,148 @@ module mkCore(CLK, 5'd0 : IF_IF_coreFix_aluExe_1_exeToFinQ_first__7830_B_ETC___d17975 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d12734 = - ((f1_exp__h714899 == 8'd0) ? - (f1_sfd__h714900[22] ? + ((f1_exp__h714896 == 8'd0) ? + (f1_sfd__h714897[22] ? 6'd2 : - (f1_sfd__h714900[21] ? + (f1_sfd__h714897[21] ? 6'd3 : - (f1_sfd__h714900[20] ? + (f1_sfd__h714897[20] ? 6'd4 : - (f1_sfd__h714900[19] ? + (f1_sfd__h714897[19] ? 6'd5 : - (f1_sfd__h714900[18] ? + (f1_sfd__h714897[18] ? 6'd6 : - (f1_sfd__h714900[17] ? + (f1_sfd__h714897[17] ? 6'd7 : - (f1_sfd__h714900[16] ? + (f1_sfd__h714897[16] ? 6'd8 : - (f1_sfd__h714900[15] ? + (f1_sfd__h714897[15] ? 6'd9 : - (f1_sfd__h714900[14] ? + (f1_sfd__h714897[14] ? 6'd10 : - (f1_sfd__h714900[13] ? + (f1_sfd__h714897[13] ? 6'd11 : - (f1_sfd__h714900[12] ? + (f1_sfd__h714897[12] ? 6'd12 : - (f1_sfd__h714900[11] ? + (f1_sfd__h714897[11] ? 6'd13 : - (f1_sfd__h714900[10] ? + (f1_sfd__h714897[10] ? 6'd14 : - (f1_sfd__h714900[9] ? + (f1_sfd__h714897[9] ? 6'd15 : - (f1_sfd__h714900[8] ? + (f1_sfd__h714897[8] ? 6'd16 : - (f1_sfd__h714900[7] ? + (f1_sfd__h714897[7] ? 6'd17 : - (f1_sfd__h714900[6] ? + (f1_sfd__h714897[6] ? 6'd18 : - (f1_sfd__h714900[5] ? + (f1_sfd__h714897[5] ? 6'd19 : - (f1_sfd__h714900[4] ? + (f1_sfd__h714897[4] ? 6'd20 : - (f1_sfd__h714900[3] ? + (f1_sfd__h714897[3] ? 6'd21 : - (f1_sfd__h714900[2] ? + (f1_sfd__h714897[2] ? 6'd22 : - (f1_sfd__h714900[1] ? + (f1_sfd__h714897[1] ? 6'd23 : - (f1_sfd__h714900[0] ? + (f1_sfd__h714897[0] ? 6'd24 : 6'd57))))))))))))))))))))))) : 6'd1) - 6'd1 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13140 = - (f1_exp__h714899 == 8'd255 && f1_sfd__h714900 != 23'd0 || - (f1_exp__h714899 == 8'd255 || f1_exp__h714899 == 8'd0) && - f1_sfd__h714900 == 23'd0) ? + (f1_exp__h714896 == 8'd255 && f1_sfd__h714897 != 23'd0 || + (f1_exp__h714896 == 8'd255 || f1_exp__h714896 == 8'd0) && + f1_sfd__h714897 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - ((f1_exp__h714899 == 8'd0) ? + ((f1_exp__h714896 == 8'd0) ? IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d12795 : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d13138) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13323 = - (f1_exp__h714899 == 8'd255 && f1_sfd__h714900 != 23'd0) ? - _theResult___snd_fst_sfd__h715215 : - _theResult___fst_sfd__h753496 ; + (f1_exp__h714896 == 8'd255 && f1_sfd__h714897 != 23'd0) ? + _theResult___snd_fst_sfd__h715212 : + _theResult___fst_sfd__h753493 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13324 = { IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13140, - (f1_exp__h714899 == 8'd255) ? + (f1_exp__h714896 == 8'd255) ? 11'd2047 : - _theResult___fst_exp__h753492, + _theResult___fst_exp__h753489, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13323 } ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13464 = - ((f3_exp__h793197 == 8'd0) ? - (f3_sfd__h793198[22] ? + ((f3_exp__h793194 == 8'd0) ? + (f3_sfd__h793195[22] ? 6'd2 : - (f3_sfd__h793198[21] ? + (f3_sfd__h793195[21] ? 6'd3 : - (f3_sfd__h793198[20] ? + (f3_sfd__h793195[20] ? 6'd4 : - (f3_sfd__h793198[19] ? + (f3_sfd__h793195[19] ? 6'd5 : - (f3_sfd__h793198[18] ? + (f3_sfd__h793195[18] ? 6'd6 : - (f3_sfd__h793198[17] ? + (f3_sfd__h793195[17] ? 6'd7 : - (f3_sfd__h793198[16] ? + (f3_sfd__h793195[16] ? 6'd8 : - (f3_sfd__h793198[15] ? + (f3_sfd__h793195[15] ? 6'd9 : - (f3_sfd__h793198[14] ? + (f3_sfd__h793195[14] ? 6'd10 : - (f3_sfd__h793198[13] ? + (f3_sfd__h793195[13] ? 6'd11 : - (f3_sfd__h793198[12] ? + (f3_sfd__h793195[12] ? 6'd12 : - (f3_sfd__h793198[11] ? + (f3_sfd__h793195[11] ? 6'd13 : - (f3_sfd__h793198[10] ? + (f3_sfd__h793195[10] ? 6'd14 : - (f3_sfd__h793198[9] ? + (f3_sfd__h793195[9] ? 6'd15 : - (f3_sfd__h793198[8] ? + (f3_sfd__h793195[8] ? 6'd16 : - (f3_sfd__h793198[7] ? + (f3_sfd__h793195[7] ? 6'd17 : - (f3_sfd__h793198[6] ? + (f3_sfd__h793195[6] ? 6'd18 : - (f3_sfd__h793198[5] ? + (f3_sfd__h793195[5] ? 6'd19 : - (f3_sfd__h793198[4] ? + (f3_sfd__h793195[4] ? 6'd20 : - (f3_sfd__h793198[3] ? + (f3_sfd__h793195[3] ? 6'd21 : - (f3_sfd__h793198[2] ? + (f3_sfd__h793195[2] ? 6'd22 : - (f3_sfd__h793198[1] ? + (f3_sfd__h793195[1] ? 6'd23 : - (f3_sfd__h793198[0] ? + (f3_sfd__h793195[0] ? 6'd24 : 6'd57))))))))))))))))))))))) : 6'd1) - 6'd1 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13855 = - (f3_exp__h793197 == 8'd255 && f3_sfd__h793198 != 23'd0 || - (f3_exp__h793197 == 8'd255 || f3_exp__h793197 == 8'd0) && - f3_sfd__h793198 == 23'd0) ? + (f3_exp__h793194 == 8'd255 && f3_sfd__h793195 != 23'd0 || + (f3_exp__h793194 == 8'd255 || f3_exp__h793194 == 8'd0) && + f3_sfd__h793195 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - ((f3_exp__h793197 == 8'd0) ? + ((f3_exp__h793194 == 8'd0) ? IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d13510 : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d13853) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14032 = - (f3_exp__h793197 == 8'd255 && f3_sfd__h793198 != 23'd0) ? - _theResult___snd_fst_sfd__h793513 : - _theResult___fst_sfd__h831653 ; + (f3_exp__h793194 == 8'd255 && f3_sfd__h793195 != 23'd0) ? + _theResult___snd_fst_sfd__h793510 : + _theResult___fst_sfd__h831650 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14033 = - { (f3_exp__h793197 == 8'd255) ? + { (f3_exp__h793194 == 8'd255) ? 11'd2047 : - _theResult___fst_exp__h831649, + _theResult___fst_exp__h831646, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14032 } ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14088 = - (f3_exp__h793197 == 8'd0) ? + (f3_exp__h793194 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13391 ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13393 ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != @@ -20889,85 +20887,85 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14060) : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d14087 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14089 = - (f3_exp__h793197 == 8'd255 && f3_sfd__h793198 != 23'd0 || - (f3_exp__h793197 == 8'd255 || f3_exp__h793197 == 8'd0) && - f3_sfd__h793198 == 23'd0) ? + (f3_exp__h793194 == 8'd255 && f3_sfd__h793195 != 23'd0 || + (f3_exp__h793194 == 8'd255 || f3_exp__h793194 == 8'd0) && + f3_sfd__h793195 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14088 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14234 = - ((f2_exp__h753893 == 8'd0) ? - (f2_sfd__h753894[22] ? + ((f2_exp__h753890 == 8'd0) ? + (f2_sfd__h753891[22] ? 6'd2 : - (f2_sfd__h753894[21] ? + (f2_sfd__h753891[21] ? 6'd3 : - (f2_sfd__h753894[20] ? + (f2_sfd__h753891[20] ? 6'd4 : - (f2_sfd__h753894[19] ? + (f2_sfd__h753891[19] ? 6'd5 : - (f2_sfd__h753894[18] ? + (f2_sfd__h753891[18] ? 6'd6 : - (f2_sfd__h753894[17] ? + (f2_sfd__h753891[17] ? 6'd7 : - (f2_sfd__h753894[16] ? + (f2_sfd__h753891[16] ? 6'd8 : - (f2_sfd__h753894[15] ? + (f2_sfd__h753891[15] ? 6'd9 : - (f2_sfd__h753894[14] ? + (f2_sfd__h753891[14] ? 6'd10 : - (f2_sfd__h753894[13] ? + (f2_sfd__h753891[13] ? 6'd11 : - (f2_sfd__h753894[12] ? + (f2_sfd__h753891[12] ? 6'd12 : - (f2_sfd__h753894[11] ? + (f2_sfd__h753891[11] ? 6'd13 : - (f2_sfd__h753894[10] ? + (f2_sfd__h753891[10] ? 6'd14 : - (f2_sfd__h753894[9] ? + (f2_sfd__h753891[9] ? 6'd15 : - (f2_sfd__h753894[8] ? + (f2_sfd__h753891[8] ? 6'd16 : - (f2_sfd__h753894[7] ? + (f2_sfd__h753891[7] ? 6'd17 : - (f2_sfd__h753894[6] ? + (f2_sfd__h753891[6] ? 6'd18 : - (f2_sfd__h753894[5] ? + (f2_sfd__h753891[5] ? 6'd19 : - (f2_sfd__h753894[4] ? + (f2_sfd__h753891[4] ? 6'd20 : - (f2_sfd__h753894[3] ? + (f2_sfd__h753891[3] ? 6'd21 : - (f2_sfd__h753894[2] ? + (f2_sfd__h753891[2] ? 6'd22 : - (f2_sfd__h753894[1] ? + (f2_sfd__h753891[1] ? 6'd23 : - (f2_sfd__h753894[0] ? + (f2_sfd__h753891[0] ? 6'd24 : 6'd57))))))))))))))))))))))) : 6'd1) - 6'd1 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14625 = - (f2_exp__h753893 == 8'd255 && f2_sfd__h753894 != 23'd0 || - (f2_exp__h753893 == 8'd255 || f2_exp__h753893 == 8'd0) && - f2_sfd__h753894 == 23'd0) ? + (f2_exp__h753890 == 8'd255 && f2_sfd__h753891 != 23'd0 || + (f2_exp__h753890 == 8'd255 || f2_exp__h753890 == 8'd0) && + f2_sfd__h753891 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - ((f2_exp__h753893 == 8'd0) ? + ((f2_exp__h753890 == 8'd0) ? IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d14280 : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d14623) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14802 = - (f2_exp__h753893 == 8'd255 && f2_sfd__h753894 != 23'd0) ? - _theResult___snd_fst_sfd__h754209 : - _theResult___fst_sfd__h792349 ; + (f2_exp__h753890 == 8'd255 && f2_sfd__h753891 != 23'd0) ? + _theResult___snd_fst_sfd__h754206 : + _theResult___fst_sfd__h792346 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14803 = - { (f2_exp__h753893 == 8'd255) ? + { (f2_exp__h753890 == 8'd255) ? 11'd2047 : - _theResult___fst_exp__h792345, + _theResult___fst_exp__h792342, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14802 } ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14857 = - (f2_exp__h753893 == 8'd0) ? + (f2_exp__h753890 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14161 ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14163 ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != @@ -20977,15 +20975,15 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14829) : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d14856 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14858 = - (f2_exp__h753893 == 8'd255 && f2_sfd__h753894 != 23'd0 || - (f2_exp__h753893 == 8'd255 || f2_exp__h753893 == 8'd0) && - f2_sfd__h753894 == 23'd0) ? + (f2_exp__h753890 == 8'd255 && f2_sfd__h753891 != 23'd0 || + (f2_exp__h753890 == 8'd255 || f2_exp__h753890 == 8'd0) && + f2_sfd__h753891 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14857 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14913 = - (f1_exp__h714899 == 8'd0) ? + (f1_exp__h714896 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12661 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12663 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14892[4] : @@ -20993,7 +20991,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12799 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14909[4] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14954 = - (f2_exp__h753893 == 8'd0) ? + (f2_exp__h753890 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14161 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14163 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14933[4] : @@ -21001,7 +20999,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14284 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14950[4] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14998 = - (f3_exp__h793197 == 8'd0) ? + (f3_exp__h793194 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13391 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13393 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14977[4] : @@ -21009,7 +21007,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13514 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14994[4] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15013 = - (f1_exp__h714899 == 8'd0) ? + (f1_exp__h714896 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12661 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12663 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14892[3] : @@ -21017,7 +21015,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12799 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14909[3] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15023 = - (f2_exp__h753893 == 8'd0) ? + (f2_exp__h753890 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14161 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14163 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14933[3] : @@ -21025,7 +21023,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14284 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14950[3] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15034 = - (f3_exp__h793197 == 8'd0) ? + (f3_exp__h793194 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13391 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13393 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14977[3] : @@ -21033,70 +21031,70 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13514 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14994[3] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15053 = - (f1_exp__h714899 == 8'd0) ? + (f1_exp__h714896 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12661 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12663 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14892[2] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12798 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15051 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15067 = - (f2_exp__h753893 == 8'd0) ? + (f2_exp__h753890 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14161 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14163 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14933[2] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14283 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15065 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15082 = - (f3_exp__h793197 == 8'd0) ? + (f3_exp__h793194 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13391 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13393 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14977[2] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13513 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15080 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15099 = - (f1_exp__h714899 == 8'd0) ? + (f1_exp__h714896 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12661 && (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12663 || _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14892[1]) : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12798 && IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15097 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15111 = - (f2_exp__h753893 == 8'd0) ? + (f2_exp__h753890 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14161 && (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14163 || _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14933[1]) : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14283 && IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15109 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15124 = - (f3_exp__h793197 == 8'd0) ? + (f3_exp__h793194 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13391 && (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13393 || _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14977[1]) : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13513 && IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15122 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15141 = - (f1_exp__h714899 == 8'd0) ? + (f1_exp__h714896 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12661 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12663 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14892[0] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12798 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15139 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15153 = - (f2_exp__h753893 == 8'd0) ? + (f2_exp__h753890 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14161 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14163 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14933[0] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14283 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15151 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15166 = - (f3_exp__h793197 == 8'd0) ? + (f3_exp__h793194 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13391 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13393 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14977[0] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13513 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15164 ; assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_cRqR_ETC___d7249 = - _theResult_____2__h515368 == v__h514824 ; + _theResult_____2__h515366 == v__h514822 ; assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_cRqR_ETC___d7257 = IF_IF_coreFix_memExe_dMem_cache_m_banks_0_cRqR_ETC___d7249 && (IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d7227 || @@ -21111,7 +21109,7 @@ module mkCore(CLK, (IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d7240 || coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty) ; assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_from_ETC___d7340 = - _theResult_____2__h526145 == v__h516844 ; + _theResult_____2__h526143 == v__h516842 ; assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_from_ETC___d7349 = IF_IF_coreFix_memExe_dMem_cache_m_banks_0_from_ETC___d7340 && (IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d7321 || @@ -21140,9 +21138,9 @@ module mkCore(CLK, EN_dCacheToParent_fromP_enq ? coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[518:3] : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[518:3], - x__h521675 } ; + x__h521673 } ; assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_rqTo_ETC___d7500 = - _theResult_____2__h533238 == v__h532563 ; + _theResult_____2__h533236 == v__h532561 ; assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_rqTo_ETC___d7508 = IF_IF_coreFix_memExe_dMem_cache_m_banks_0_rqTo_ETC___d7500 && (IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d7480 || @@ -21157,7 +21155,7 @@ module mkCore(CLK, (IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d7493 || coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty) ; assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_rsTo_ETC___d7584 = - _theResult_____2__h543873 == v__h535012 ; + _theResult_____2__h543871 == v__h535010 ; assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_rsTo_ETC___d7592 = IF_IF_coreFix_memExe_dMem_cache_m_banks_0_rsTo_ETC___d7584 && (IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d7564 || @@ -21554,7 +21552,7 @@ module mkCore(CLK, 5'd15 : 5'd28))))))))))))) } ; assign IF_IF_coreFix_memExe_forwardQ_deqReq_lat_1_wha_ETC___d7870 = - _theResult_____2__h561485 == v__h559811 ; + _theResult_____2__h561483 == v__h559809 ; assign IF_IF_coreFix_memExe_forwardQ_deqReq_lat_1_wha_ETC___d7878 = IF_IF_coreFix_memExe_forwardQ_deqReq_lat_1_wha_ETC___d7870 && (IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d7851 || @@ -21569,7 +21567,7 @@ module mkCore(CLK, (IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d7864 || coreFix_memExe_forwardQ_empty) ; assign IF_IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_w_ETC___d7788 = - _theResult_____2__h557706 == v__h556032 ; + _theResult_____2__h557704 == v__h556030 ; assign IF_IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_w_ETC___d7796 = IF_IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_w_ETC___d7788 && (IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d7769 || @@ -21583,16 +21581,16 @@ module mkCore(CLK, !coreFix_memExe_memRespLdQ_enqReq_rl[134]) && (IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d7782 || coreFix_memExe_memRespLdQ_empty) ; - assign IF_IF_csrf_prv_reg_read__0286_ULE_1_2614_AND_I_ETC___d22894 = - (csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22647 ? + assign IF_IF_csrf_prv_reg_read__0286_ULE_1_2614_AND_I_ETC___d22896 = + (csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22648 ? !csrf_stcc_reg[34] : !csrf_mtcc_reg[34]) ? - { x__h1000884[11:0], - x1_avValue_new_pcc_capFat_bounds_baseBits__h1000887 } : - { x__h1000884[11:3], - x__h1000905[5:3], - x1_avValue_new_pcc_capFat_bounds_baseBits__h1000887[13:3], - x__h1000905[2:0] } ; + { x__h1000919[11:0], + x1_avValue_new_pcc_capFat_bounds_baseBits__h1000922 } : + { x__h1000919[11:3], + x__h1000940[5:3], + x1_avValue_new_pcc_capFat_bounds_baseBits__h1000922[13:3], + x__h1000940[2:0] } ; assign IF_IF_fetchStage_pipelines_0_first__0256_BITS__ETC___d21231 = IF_fetchStage_pipelines_0_first__0256_BITS_268_ETC___d21222 ? !csrf_rg_dcsr[2] && @@ -21832,48 +21830,48 @@ module mkCore(CLK, IF_IF_IF_NOT_csrf_prv_reg_read__0286_EQ_3_0287_ETC___d20929) ? 4'd0 : IF_IF_renameStage_rg_m_halt_req_0283_BIT_4_028_ETC___d20984 ; - assign IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23130 = - robdeqPort_0_deq_data_BITS_95_TO_32__q16[63] ? - x__h1008496[13:0] >= toBounds__h1008382 : - x__h1008496[13:0] <= toBoundsM1__h1008383 ; - assign IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23174 = + assign IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23132 = + robdeqPort_0_deq_data_BITS_95_TO_32__q17[63] ? + x__h1008531[13:0] >= toBounds__h1008417 : + x__h1008531[13:0] <= toBoundsM1__h1008418 ; + assign IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23176 = MUX_csrf_rg_dcsr$write_1__VAL_1[63] ? - x__h1008899[13:0] >= toBounds__h1008785 : - x__h1008899[13:0] <= toBoundsM1__h1008786 ; - assign IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23269 = - robdeqPort_0_deq_data_BITS_95_TO_32__q16[63] ? - x__h1009316[13:0] >= toBounds__h1009202 : - x__h1009316[13:0] <= toBoundsM1__h1009203 ; - assign IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23311 = + x__h1008934[13:0] >= toBounds__h1008820 : + x__h1008934[13:0] <= toBoundsM1__h1008821 ; + assign IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23271 = + robdeqPort_0_deq_data_BITS_95_TO_32__q17[63] ? + x__h1009351[13:0] >= toBounds__h1009237 : + x__h1009351[13:0] <= toBoundsM1__h1009238 ; + assign IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23313 = MUX_csrf_rg_dcsr$write_1__VAL_1[63] ? - x__h1009719[13:0] >= toBounds__h1009605 : - x__h1009719[13:0] <= toBoundsM1__h1009606 ; - assign IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23424 = - robdeqPort_0_deq_data_BITS_95_TO_32__q16[63] ? - x__h1010388[13:0] >= toBounds__h1010274 : - x__h1010388[13:0] <= toBoundsM1__h1010275 ; + x__h1009754[13:0] >= toBounds__h1009640 : + x__h1009754[13:0] <= toBoundsM1__h1009641 ; + assign IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23426 = + robdeqPort_0_deq_data_BITS_95_TO_32__q17[63] ? + x__h1010423[13:0] >= toBounds__h1010309 : + x__h1010423[13:0] <= toBoundsM1__h1010310 ; assign IF_INV_IF_coreFix_memExe_lsq_firstLd__498_BITS_ETC___d1954 = - { INV_x83399_BITS_108_TO_90__q34[0] ? x__h183519 : 6'd0, - x__h183679, - x__h183699 } ; + { INV_x83397_BITS_108_TO_90__q34[0] ? x__h183517 : 6'd0, + x__h183677, + x__h183697 } ; assign IF_INV_IF_coreFix_memExe_lsq_firstLd__498_BITS_ETC___d2120 = - { INV_x99251_BITS_108_TO_90__q36[0] ? x__h202270 : 6'd0, - x__h202430, - x__h202450 } ; + { INV_x99249_BITS_108_TO_90__q36[0] ? x__h202268 : 6'd0, + x__h202428, + x__h202448 } ; assign IF_INV_commitStage_commitTrap_2268_BITS_217_TO_ETC___d22580 = - INV_commitStage_commitTrap_BITS_217_TO_199__q15[0] ? - x__h994949 : + INV_commitStage_commitTrap_BITS_217_TO_199__q16[0] ? + x__h994947 : 6'd0 ; - assign IF_INV_commitStage_commitTrap_2268_BITS_217_TO_ETC___d22661 = - x__h995129[13:11] < repBound__h997599 ; - assign IF_INV_commitStage_commitTrap_2268_BITS_217_TO_ETC___d22663 = - pc_addrBits__h994740[13:11] < repBound__h997599 ; + assign IF_INV_commitStage_commitTrap_2268_BITS_217_TO_ETC___d22662 = + x__h995127[13:11] < repBound__h997634 ; + assign IF_INV_commitStage_commitTrap_2268_BITS_217_TO_ETC___d22664 = + pc_addrBits__h994738[13:11] < repBound__h997634 ; assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19778 = - tb__h906823 < repBound__h906826 ; + tb__h906821 < repBound__h906824 ; assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19779 = - x__h906765[13:11] < repBound__h906826 ; + x__h906763[13:11] < repBound__h906824 ; assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19781 = - cr_addrBits__h906358[13:11] < repBound__h906826 ; + cr_addrBits__h906356[13:11] < repBound__h906824 ; assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19791 = { IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19781, (IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19778 == @@ -21891,11 +21889,11 @@ module mkCore(CLK, 2'd1 : 2'd3) } ; assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19842 = - tb__h907371 < repBound__h907374 ; + tb__h907369 < repBound__h907372 ; assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19843 = - x__h907313[13:11] < repBound__h907374 ; + x__h907311[13:11] < repBound__h907372 ; assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19845 = - cr_addrBits__h906906[13:11] < repBound__h907374 ; + cr_addrBits__h906904[13:11] < repBound__h907372 ; assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19855 = { IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19845, (IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19842 == @@ -21913,11 +21911,11 @@ module mkCore(CLK, 2'd1 : 2'd3) } ; assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17662 = - tb__h867137 < repBound__h867140 ; + tb__h867136 < repBound__h867139 ; assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17663 = - x__h867079[13:11] < repBound__h867140 ; + x__h867078[13:11] < repBound__h867139 ; assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17665 = - cr_addrBits__h866672[13:11] < repBound__h867140 ; + cr_addrBits__h866671[13:11] < repBound__h867139 ; assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17675 = { IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17665, (IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17662 == @@ -21935,11 +21933,11 @@ module mkCore(CLK, 2'd1 : 2'd3) } ; assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17726 = - tb__h867685 < repBound__h867688 ; + tb__h867684 < repBound__h867687 ; assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17727 = - x__h867627[13:11] < repBound__h867688 ; + x__h867626[13:11] < repBound__h867687 ; assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17729 = - cr_addrBits__h867220[13:11] < repBound__h867688 ; + cr_addrBits__h867219[13:11] < repBound__h867687 ; assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17739 = { IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17729, (IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17726 == @@ -21958,26 +21956,26 @@ module mkCore(CLK, 2'd3) } ; assign IF_INV_coreFix_memExe_lsq_respLd_159_BITS_108__ETC___d2210 = { INV_coreFix_memExe_lsqrespLd_BITS_108_TO_90__q10[0] ? - x__h216836 : + x__h216834 : 6'd0, - x__h216996, - x__h217016 } ; + x__h216994, + x__h217014 } ; assign IF_INV_coreFix_memExe_respLrScAmoQ_data_0_233__ETC___d1273 = { INV_coreFix_memExe_respLrScAmoQ_data_0_BITS_10_ETC__q8[0] ? - x__h127341 : + x__h127340 : 6'd0, - x__h127501, - x__h127521 } ; + x__h127500, + x__h127520 } ; assign IF_INV_mmio_dataRespQ_data_0_389_BITS_108_TO_9_ETC___d1433 = { INV_mmio_dataRespQ_data_0_BITS_108_TO_90__q9[0] ? - x__h140257 : + x__h140256 : 6'd0, - x__h140417, - x__h140437 } ; + x__h140416, + x__h140436 } ; assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d12795 = (!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12661 || _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12663 || - _theResult___fst_exp__h734287 == 11'd2047) ? + _theResult___fst_exp__h734284 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : @@ -21985,12 +21983,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard26326_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q157 : + CASE_guard26323_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q157 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q158) ; assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d13510 = (!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13391 || _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13393 || - _theResult___fst_exp__h812444 == 11'd2047) ? + _theResult___fst_exp__h812441 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -21998,12 +21996,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard04483_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q174 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q175) ; + CASE_guard04480_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q176 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q177) ; assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d14280 = (!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14161 || _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14163 || - _theResult___fst_exp__h773140 == 11'd2047) ? + _theResult___fst_exp__h773137 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -22011,7 +22009,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard65179_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q205 : + CASE_guard65176_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q205 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q206) ; assign IF_NOT_IF_IF_NOT_csrf_prv_reg_read__0286_EQ_3__ETC___d20905 = IF_IF_NOT_csrf_prv_reg_read__0286_EQ_3_0287_02_ETC___d20323[0] ? @@ -23659,7 +23657,7 @@ module mkCore(CLK, checkForException___d20654[10:5], CASE_checkForException_0654_BITS_4_TO_0_0_chec_ETC__q257 } : IF_NOT_renameStage_rg_m_halt_req_0283_BIT_4_02_ETC___d20987 ; - assign IF_NOT_rob_deqPort_1_deq_data__3605_BIT_25_360_ETC___d23838 = + assign IF_NOT_rob_deqPort_1_deq_data__3607_BIT_25_360_ETC___d23840 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[274] || rob$deqPort_1_deq_data[469:465] == 5'd0 || @@ -23735,48 +23733,48 @@ module mkCore(CLK, assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15051 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12799 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14909[2] : - _theResult___fst_exp__h753480 == 11'd2047 && - _theResult___fst_sfd__h753481 == 52'd0 ; + _theResult___fst_exp__h753477 == 11'd2047 && + _theResult___fst_sfd__h753478 == 52'd0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15065 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14284 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14950[2] : - _theResult___fst_exp__h792333 == 11'd2047 && - _theResult___fst_sfd__h792334 == 52'd0 ; + _theResult___fst_exp__h792330 == 11'd2047 && + _theResult___fst_sfd__h792331 == 52'd0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15080 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13514 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14994[2] : - _theResult___fst_exp__h831637 == 11'd2047 && - _theResult___fst_sfd__h831638 == 52'd0 ; + _theResult___fst_exp__h831634 == 11'd2047 && + _theResult___fst_sfd__h831635 == 52'd0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15097 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12799 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14909[1] : - _theResult___fst_exp__h752697 == 11'd0 && - guard__h744707 != 2'b0 ; + _theResult___fst_exp__h752694 == 11'd0 && + guard__h744704 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15109 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14284 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14950[1] : - _theResult___fst_exp__h791550 == 11'd0 && - guard__h783560 != 2'b0 ; + _theResult___fst_exp__h791547 == 11'd0 && + guard__h783557 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15122 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13514 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14994[1] : - _theResult___fst_exp__h830854 == 11'd0 && - guard__h822864 != 2'b0 ; + _theResult___fst_exp__h830851 == 11'd0 && + guard__h822861 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15139 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12799 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14909[0] : - _theResult___fst_exp__h752697 != 11'd2047 && - guard__h744707 != 2'b0 ; + _theResult___fst_exp__h752694 != 11'd2047 && + guard__h744704 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15151 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14284 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14950[0] : - _theResult___fst_exp__h791550 != 11'd2047 && - guard__h783560 != 2'b0 ; + _theResult___fst_exp__h791547 != 11'd2047 && + guard__h783557 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15164 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13514 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14994[0] : - _theResult___fst_exp__h830854 != 11'd2047 && - guard__h822864 != 2'b0 ; + _theResult___fst_exp__h830851 != 11'd2047 && + guard__h822861 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d10392 = ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q84[7:0] == 8'd0) ? @@ -23786,35 +23784,35 @@ module mkCore(CLK, 9'd386 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d10619 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10073 ? - ((_theResult___fst_exp__h648080 == 8'd255) ? + ((_theResult___fst_exp__h648078 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10604) : - ((_theResult___fst_exp__h656765 == 8'd255) ? + ((_theResult___fst_exp__h656763 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10617) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d10656 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10073 ? - ((_theResult___fst_exp__h648080 == 8'd255) ? + ((_theResult___fst_exp__h648078 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10647) : - ((_theResult___fst_exp__h656765 == 8'd255) ? + ((_theResult___fst_exp__h656763 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10654) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d10752 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10073 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d10723[2] : - _theResult___fst_exp__h657313 == 8'd255 && - _theResult___fst_sfd__h657314 == 23'd0 ; + _theResult___fst_exp__h657311 == 8'd255 && + _theResult___fst_sfd__h657312 == 23'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d10765 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10073 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d10723[1] : - _theResult___fst_exp__h656765 == 8'd0 && - guard__h648688 != 2'b0 ; + _theResult___fst_exp__h656763 == 8'd0 && + guard__h648686 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d10778 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10073 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d10723[0] : - _theResult___fst_exp__h656765 != 8'd255 && - guard__h648688 != 2'b0 ; + _theResult___fst_exp__h656763 != 8'd255 && + guard__h648686 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d11789 = ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q119[7:0] == 8'd0) ? @@ -23824,35 +23822,35 @@ module mkCore(CLK, 9'd386 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d12016 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11470 ? - ((_theResult___fst_exp__h693827 == 8'd255) ? + ((_theResult___fst_exp__h693825 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12001) : - ((_theResult___fst_exp__h702512 == 8'd255) ? + ((_theResult___fst_exp__h702510 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12014) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d12053 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11470 ? - ((_theResult___fst_exp__h693827 == 8'd255) ? + ((_theResult___fst_exp__h693825 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12044) : - ((_theResult___fst_exp__h702512 == 8'd255) ? + ((_theResult___fst_exp__h702510 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12051) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d12149 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11470 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d12120[2] : - _theResult___fst_exp__h703060 == 8'd255 && - _theResult___fst_sfd__h703061 == 23'd0 ; + _theResult___fst_exp__h703058 == 8'd255 && + _theResult___fst_sfd__h703059 == 23'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d12162 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11470 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d12120[1] : - _theResult___fst_exp__h702512 == 8'd0 && - guard__h694435 != 2'b0 ; + _theResult___fst_exp__h702510 == 8'd0 && + guard__h694433 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d12175 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11470 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d12120[0] : - _theResult___fst_exp__h702512 != 8'd255 && - guard__h694435 != 2'b0 ; + _theResult___fst_exp__h702510 != 8'd255 && + guard__h694433 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8995 = ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q49[7:0] == 8'd0) ? @@ -23862,41 +23860,41 @@ module mkCore(CLK, 9'd386 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d9222 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8676 ? - ((_theResult___fst_exp__h602331 == 8'd255) ? + ((_theResult___fst_exp__h602329 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9207) : - ((_theResult___fst_exp__h611016 == 8'd255) ? + ((_theResult___fst_exp__h611014 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9220) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d9259 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8676 ? - ((_theResult___fst_exp__h602331 == 8'd255) ? + ((_theResult___fst_exp__h602329 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9250) : - ((_theResult___fst_exp__h611016 == 8'd255) ? + ((_theResult___fst_exp__h611014 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9257) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d9355 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8676 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d9326[2] : - _theResult___fst_exp__h611564 == 8'd255 && - _theResult___fst_sfd__h611565 == 23'd0 ; + _theResult___fst_exp__h611562 == 8'd255 && + _theResult___fst_sfd__h611563 == 23'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d9368 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8676 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d9326[1] : - _theResult___fst_exp__h611016 == 8'd0 && - guard__h602939 != 2'b0 ; + _theResult___fst_exp__h611014 == 8'd0 && + guard__h602937 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d9381 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8676 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d9326[0] : - _theResult___fst_exp__h611016 != 8'd255 && - guard__h602939 != 2'b0 ; + _theResult___fst_exp__h611014 != 8'd255 && + guard__h602937 != 2'b0 ; assign IF_SEXT_coreFix_memExe_regToExeQ_first__645_BI_ETC___d4095 = - offset__h242628[63] ? - x__h242777[13:0] >= toBounds__h242656 && - repBoundBits__h242653 != + offset__h242625[63] ? + x__h242774[13:0] >= toBounds__h242653 && + repBoundBits__h242650 != coreFix_memExe_regToExeQ$first[317:304] : - x__h242777[13:0] < toBoundsM1__h242657 ; + x__h242774[13:0] < toBoundsM1__h242654 ; assign IF_coreFix_aluExe_0_dispToRegQ_RDY_first__8382_ETC___d18414 = (coreFix_aluExe_0_dispToRegQ$RDY_first && coreFix_aluExe_0_bypassWire_0$whas && @@ -23984,24 +23982,24 @@ module mkCore(CLK, IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d18608 ; assign IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d18820 = coreFix_aluExe_0_dispToRegQ$first[137] ? - res_address__h892145 : + res_address__h892144 : ((coreFix_aluExe_0_dispToRegQ$first[85] && coreFix_aluExe_0_dispToRegQ$first[84:78] != 7'd0) ? IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18818 : 66'd0) ; assign IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d18835 = coreFix_aluExe_0_dispToRegQ$first[137] ? - res_addrBits__h892146 : + res_addrBits__h892145 : ((coreFix_aluExe_0_dispToRegQ$first[85] && coreFix_aluExe_0_dispToRegQ$first[84:78] != 7'd0) ? IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18833 : 14'd0) ; assign IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19394 = { coreFix_aluExe_0_dispToRegQ$first[124] ? - thin_reserved__h899113 : + thin_reserved__h899111 : 2'd0, coreFix_aluExe_0_dispToRegQ$first[124] ? - thin_otype__h899114 : + thin_otype__h899112 : 18'd262143, !coreFix_aluExe_0_dispToRegQ$first[124] || IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19382, @@ -24010,7 +24008,7 @@ module mkCore(CLK, 34'h344000000 } ; assign IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19395 = { coreFix_aluExe_0_dispToRegQ$first[124] ? - thin_perms_soft__h899289 : + thin_perms_soft__h899287 : 4'd0, coreFix_aluExe_0_dispToRegQ$first[124] && IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19240, @@ -24041,18 +24039,18 @@ module mkCore(CLK, IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19394 } ; assign IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19396 = { coreFix_aluExe_0_dispToRegQ$first[124] ? - thin_address__h899109 : + thin_address__h899107 : 66'd0, coreFix_aluExe_0_dispToRegQ$first[124] ? - thin_addrBits__h899110 : + thin_addrBits__h899108 : 14'd0, IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19395 } ; assign IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19417 = - thin_bounds_topBits__h900515[13:11] < repBound__h900631 ; + thin_bounds_topBits__h900513[13:11] < repBound__h900629 ; assign IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19419 = - thin_bounds_baseBits__h900516[13:11] < repBound__h900631 ; + thin_bounds_baseBits__h900514[13:11] < repBound__h900629 ; assign IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19422 = - thin_addrBits__h899110[13:11] < repBound__h900631 ; + thin_addrBits__h899108[13:11] < repBound__h900629 ; assign IF_coreFix_aluExe_0_exeToFinQ_first__9946_BIT__ETC___d20092 = { (coreFix_aluExe_0_exeToFinQ$first[282] && !coreFix_aluExe_0_exeToFinQ$first[294]) ? @@ -24299,24 +24297,24 @@ module mkCore(CLK, IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d15845 ; assign IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d16425 = coreFix_aluExe_1_dispToRegQ$first[137] ? - res_address__h848644 : + res_address__h848642 : ((coreFix_aluExe_1_dispToRegQ$first[85] && coreFix_aluExe_1_dispToRegQ$first[84:78] != 7'd0) ? IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16423 : 66'd0) ; assign IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d16440 = coreFix_aluExe_1_dispToRegQ$first[137] ? - res_addrBits__h848645 : + res_addrBits__h848643 : ((coreFix_aluExe_1_dispToRegQ$first[85] && coreFix_aluExe_1_dispToRegQ$first[84:78] != 7'd0) ? IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16438 : 14'd0) ; assign IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d17260 = { coreFix_aluExe_1_dispToRegQ$first[124] ? - thin_reserved__h858477 : + thin_reserved__h858476 : 2'd0, coreFix_aluExe_1_dispToRegQ$first[124] ? - thin_otype__h858478 : + thin_otype__h858477 : 18'd262143, !coreFix_aluExe_1_dispToRegQ$first[124] || IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d17235, @@ -24325,7 +24323,7 @@ module mkCore(CLK, 34'h344000000 } ; assign IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d17261 = { coreFix_aluExe_1_dispToRegQ$first[124] ? - thin_perms_soft__h858713 : + thin_perms_soft__h858712 : 4'd0, coreFix_aluExe_1_dispToRegQ$first[124] && IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d16898, @@ -24356,18 +24354,18 @@ module mkCore(CLK, IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d17260 } ; assign IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d17262 = { coreFix_aluExe_1_dispToRegQ$first[124] ? - thin_address__h858473 : + thin_address__h858472 : 66'd0, coreFix_aluExe_1_dispToRegQ$first[124] ? - thin_addrBits__h858474 : + thin_addrBits__h858473 : 14'd0, IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d17261 } ; assign IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d17301 = - thin_bounds_topBits__h860421[13:11] < repBound__h860557 ; + thin_bounds_topBits__h860420[13:11] < repBound__h860556 ; assign IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d17303 = - thin_bounds_baseBits__h860422[13:11] < repBound__h860557 ; + thin_bounds_baseBits__h860421[13:11] < repBound__h860556 ; assign IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d17306 = - thin_addrBits__h858474[13:11] < repBound__h860557 ; + thin_addrBits__h858473[13:11] < repBound__h860556 ; assign IF_coreFix_aluExe_1_exeToFinQ_first__7830_BIT__ETC___d17977 = { (coreFix_aluExe_1_exeToFinQ$first[282] && !coreFix_aluExe_1_exeToFinQ$first[294]) ? @@ -25151,8 +25149,8 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107] ; assign IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d20197 = coreFix_globalSpecUpdate_correctSpecTag_1$whas ? - result__h915810 : - w__h915805 ; + result__h915808 : + w__h915803 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5011 = (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == 3'd3 && @@ -25364,12 +25362,12 @@ module mkCore(CLK, 64'd0 : 64'd1 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d7203 = - !MUX_flush_reservation$write_1__SEL_1 && + !MUX_flush_reservation$write_1__SEL_2 && (coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget[58] : coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58]) ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d7211 = - MUX_flush_reservation$write_1__SEL_1 ? + MUX_flush_reservation$write_1__SEL_2 ? 58'h2AAAAAAAAAAAAAA : (coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget[57:0] : @@ -25626,15 +25624,15 @@ module mkCore(CLK, NOT_coreFix_memExe_dispToRegQ_first__686_BIT_1_ETC___d3634 } ; assign IF_coreFix_memExe_dispToRegQ_first__686_BIT_12_ETC___d3070 = coreFix_memExe_dispToRegQ$first[12] ? - res_addrBits__h235324 : + res_addrBits__h235321 : ((coreFix_memExe_dispToRegQ$first[110] && coreFix_memExe_dispToRegQ$first[109:103] != 7'd0) ? IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3068 : 14'd0) ; assign IF_coreFix_memExe_dispToRegQ_first__686_BIT_12_ETC___d3315 = { coreFix_memExe_dispToRegQ$first[12] ? - res_address__h235323 : - x__h235746, + res_address__h235320 : + x__h235743, IF_coreFix_memExe_dispToRegQ_first__686_BIT_12_ETC___d3070, coreFix_memExe_dispToRegQ$first[12] ? 4'd0 : @@ -25773,15 +25771,15 @@ module mkCore(CLK, IF_coreFix_memExe_lsq_firstLd__498_BIT_113_513_ETC___d2078 ; assign IF_coreFix_memExe_lsq_getOrigBE_coreFix_memExe_ETC___d4249 = { coreFix_memExe_lsq$getOrigBE[15] ? - pointer__h242638[3:0] != 4'd0 : + pointer__h242635[3:0] != 4'd0 : (coreFix_memExe_lsq$getOrigBE[7] ? - pointer__h242638[2:0] != 3'd0 : + pointer__h242635[2:0] != 3'd0 : (coreFix_memExe_lsq$getOrigBE[3] ? - pointer__h242638[1:0] != 2'd0 : + pointer__h242635[1:0] != 2'd0 : coreFix_memExe_lsq$getOrigBE[1] && - pointer__h242638[0])), + pointer__h242635[0])), capChecks___d4160[11:5], - CASE_capChecks_160_BITS_4_TO_0_0_capChecks_160_ETC__q292, + CASE_capChecks_160_BITS_4_TO_0_0_capChecks_160_ETC__q294, prepareBoundsCheck___d4244 } ; assign IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d7782 = WILL_FIRE_RL_coreFix_memExe_doRespLdMem || @@ -25811,10 +25809,10 @@ module mkCore(CLK, csrf_mepcc_reg_data_rl[13:0] ; assign IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16239 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16236[13:11] < - repBound__h855390 ; + repBound__h855389 ; assign IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16241 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16232[13:11] < - repBound__h855390 ; + repBound__h855389 ; assign IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16252 = MUX_csrf_ie_vec_3$write_1__SEL_3 ? MUX_csrf_rg_dpc$write_1__VAL_3[33:28] : @@ -25903,86 +25901,86 @@ module mkCore(CLK, MUX_csrf_ie_vec_3$write_1__SEL_3 ? MUX_csrf_rg_dpc$write_1__VAL_3[27:14] : csrf_mepcc_reg_data_rl[27:14] ; - assign IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d23335 = + assign IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d23337 = MUX_csrf_ie_vec_3$write_1__SEL_3 ? MUX_csrf_rg_dpc$write_1__VAL_3[71:0] : csrf_mepcc_reg_data_rl[71:0] ; - assign IF_csrf_mepcc_reg_read_wget__3540_BIT_34_3552__ETC___d23562 = + assign IF_csrf_mepcc_reg_read_wget__3542_BIT_34_3554__ETC___d23564 = csrf_mepcc_reg_data_rl[34] ? { csrf_mepcc_reg_data_rl[25:17], csrf_mepcc_reg_data_rl[33:31], csrf_mepcc_reg_data_rl[13:3], csrf_mepcc_reg_data_rl[30:28] } : csrf_mepcc_reg_data_rl[25:0] ; - assign IF_csrf_mtcc_reg_read__6198_BITS_149_TO_86_281_ETC___d22840 = - ((newAddrDiff__h1000158 == 64'd0) ? + assign IF_csrf_mtcc_reg_read__6198_BITS_149_TO_86_281_ETC___d22842 = + ((newAddrDiff__h1000193 == 64'd0) ? 2'd0 : - (csrf_mtcc_reg_read__6198_BITS_149_TO_86_2811_A_ETC___d22821 ? + (csrf_mtcc_reg_read__6198_BITS_149_TO_86_2813_A_ETC___d22823 ? 2'd3 : 2'd1)) == ((csrf_mtcc_reg_read__6198_BITS_85_TO_83_6204_UL_ETC___d16205 && - _0_CONCAT_csrf_mtcc_reg_read__6198_BITS_149_TO__ETC___d22832) ? + _0_CONCAT_csrf_mtcc_reg_read__6198_BITS_149_TO__ETC___d22834) ? 2'd0 : ((csrf_mtcc_reg_read__6198_BITS_85_TO_83_6204_UL_ETC___d16205 && - !_0_CONCAT_csrf_mtcc_reg_read__6198_BITS_149_TO__ETC___d22832) ? + !_0_CONCAT_csrf_mtcc_reg_read__6198_BITS_149_TO__ETC___d22834) ? 2'd1 : ((!csrf_mtcc_reg_read__6198_BITS_85_TO_83_6204_UL_ETC___d16205 && - _0_CONCAT_csrf_mtcc_reg_read__6198_BITS_149_TO__ETC___d22832) ? + _0_CONCAT_csrf_mtcc_reg_read__6198_BITS_149_TO__ETC___d22834) ? 2'd3 : 2'd0))) ; - assign IF_csrf_mtcc_reg_read__6198_BITS_149_TO_86_281_ETC___d22843 = - IF_csrf_mtcc_reg_read__6198_BITS_149_TO_86_281_ETC___d22840 && - (newAddrDiff__h1000158 == 64'd0 || - csrf_mtcc_reg_read__6198_BITS_149_TO_86_2811_A_ETC___d22821 || - newAddrDiff__h1000158 == - _18446744073709551615_SL_csrf_mtcc_reg_read__61_ETC___d22824) ; - assign IF_csrf_mtcc_reg_read__6198_BITS_149_TO_86_281_ETC___d22865 = - ((newAddrDiff__h1000502 == 64'd0) ? + assign IF_csrf_mtcc_reg_read__6198_BITS_149_TO_86_281_ETC___d22845 = + IF_csrf_mtcc_reg_read__6198_BITS_149_TO_86_281_ETC___d22842 && + (newAddrDiff__h1000193 == 64'd0 || + csrf_mtcc_reg_read__6198_BITS_149_TO_86_2813_A_ETC___d22823 || + newAddrDiff__h1000193 == + _18446744073709551615_SL_csrf_mtcc_reg_read__61_ETC___d22826) ; + assign IF_csrf_mtcc_reg_read__6198_BITS_149_TO_86_281_ETC___d22867 = + ((newAddrDiff__h1000537 == 64'd0) ? 2'd0 : - (csrf_mtcc_reg_read__6198_BITS_149_TO_86_2811_A_ETC___d22849 ? + (csrf_mtcc_reg_read__6198_BITS_149_TO_86_2813_A_ETC___d22851 ? 2'd3 : 2'd1)) == ((csrf_mtcc_reg_read__6198_BITS_85_TO_83_6204_UL_ETC___d16205 && - _0_CONCAT_csrf_mtcc_reg_read__6198_BITS_149_TO__ETC___d22857) ? + _0_CONCAT_csrf_mtcc_reg_read__6198_BITS_149_TO__ETC___d22859) ? 2'd0 : ((csrf_mtcc_reg_read__6198_BITS_85_TO_83_6204_UL_ETC___d16205 && - !_0_CONCAT_csrf_mtcc_reg_read__6198_BITS_149_TO__ETC___d22857) ? + !_0_CONCAT_csrf_mtcc_reg_read__6198_BITS_149_TO__ETC___d22859) ? 2'd1 : ((!csrf_mtcc_reg_read__6198_BITS_85_TO_83_6204_UL_ETC___d16205 && - _0_CONCAT_csrf_mtcc_reg_read__6198_BITS_149_TO__ETC___d22857) ? + _0_CONCAT_csrf_mtcc_reg_read__6198_BITS_149_TO__ETC___d22859) ? 2'd3 : 2'd0))) ; - assign IF_csrf_mtcc_reg_read__6198_BITS_149_TO_86_281_ETC___d22868 = - IF_csrf_mtcc_reg_read__6198_BITS_149_TO_86_281_ETC___d22865 && - (newAddrDiff__h1000502 == 64'd0 || - csrf_mtcc_reg_read__6198_BITS_149_TO_86_2811_A_ETC___d22849 || - newAddrDiff__h1000502 == - _18446744073709551615_SL_csrf_mtcc_reg_read__61_ETC___d22824) ; - assign IF_csrf_mtcc_reg_read__6198_BIT_86_2807_AND_NO_ETC___d22871 = - (csrf_mtcc_reg[86] && cause_interrupt__h995318) ? - (NOT_csrf_mtcc_reg_read__6198_BITS_33_TO_28_621_ETC___d22810 || - IF_csrf_mtcc_reg_read__6198_BITS_149_TO_86_281_ETC___d22843) && + assign IF_csrf_mtcc_reg_read__6198_BITS_149_TO_86_281_ETC___d22870 = + IF_csrf_mtcc_reg_read__6198_BITS_149_TO_86_281_ETC___d22867 && + (newAddrDiff__h1000537 == 64'd0 || + csrf_mtcc_reg_read__6198_BITS_149_TO_86_2813_A_ETC___d22851 || + newAddrDiff__h1000537 == + _18446744073709551615_SL_csrf_mtcc_reg_read__61_ETC___d22826) ; + assign IF_csrf_mtcc_reg_read__6198_BIT_86_2809_AND_NO_ETC___d22873 = + (csrf_mtcc_reg[86] && cause_interrupt__h995316) ? + (NOT_csrf_mtcc_reg_read__6198_BITS_33_TO_28_621_ETC___d22812 || + IF_csrf_mtcc_reg_read__6198_BITS_149_TO_86_281_ETC___d22845) && csrf_mtcc_reg[152] : - (NOT_csrf_mtcc_reg_read__6198_BITS_33_TO_28_621_ETC___d22810 || - IF_csrf_mtcc_reg_read__6198_BITS_149_TO_86_281_ETC___d22868) && + (NOT_csrf_mtcc_reg_read__6198_BITS_33_TO_28_621_ETC___d22812 || + IF_csrf_mtcc_reg_read__6198_BITS_149_TO_86_281_ETC___d22870) && csrf_mtcc_reg[152] ; - assign IF_csrf_mtcc_reg_read__6198_BIT_86_2807_AND_NO_ETC___d22905 = - (csrf_mtcc_reg[86] && cause_interrupt__h995318) ? - address__h999478 : - base__h999443 ; - assign IF_csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_c_ETC___d22876 = - csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22647 ? - { IF_csrf_stcc_reg_read__6046_BIT_86_2736_AND_NO_ETC___d22802, + assign IF_csrf_mtcc_reg_read__6198_BIT_86_2809_AND_NO_ETC___d22907 = + (csrf_mtcc_reg[86] && cause_interrupt__h995316) ? + address__h999513 : + base__h999478 ; + assign IF_csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_c_ETC___d22878 = + csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22648 ? + { IF_csrf_stcc_reg_read__6046_BIT_86_2738_AND_NO_ETC___d22804, csrf_stcc_reg[71:56], csrf_stcc_reg[54:53], csrf_stcc_reg[55], csrf_stcc_reg[52:34] } : - { IF_csrf_mtcc_reg_read__6198_BIT_86_2807_AND_NO_ETC___d22871, + { IF_csrf_mtcc_reg_read__6198_BIT_86_2809_AND_NO_ETC___d22873, csrf_mtcc_reg[71:56], csrf_mtcc_reg[54:53], csrf_mtcc_reg[55], csrf_mtcc_reg[52:34] } ; - assign IF_csrf_rg_dpc_read__6343_BIT_34_4349_THEN_csr_ETC___d24357 = + assign IF_csrf_rg_dpc_read__6343_BIT_34_4351_THEN_csr_ETC___d24359 = csrf_rg_dpc[34] ? { csrf_rg_dpc[25:17], csrf_rg_dpc[33:31], @@ -25999,10 +25997,10 @@ module mkCore(CLK, csrf_sepcc_reg_data_rl[13:0] ; assign IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16087 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16084[13:11] < - repBound__h854398 ; + repBound__h854397 ; assign IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16089 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16080[13:11] < - repBound__h854398 ; + repBound__h854397 ; assign IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16100 = MUX_csrf_ie_vec_1$write_1__SEL_3 ? MUX_csrf_rg_dpc$write_1__VAL_3[33:28] : @@ -26091,93 +26089,93 @@ module mkCore(CLK, MUX_csrf_ie_vec_1$write_1__SEL_3 ? MUX_csrf_rg_dpc$write_1__VAL_3[27:14] : csrf_sepcc_reg_data_rl[27:14] ; - assign IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d23198 = + assign IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d23200 = MUX_csrf_ie_vec_1$write_1__SEL_3 ? MUX_csrf_rg_dpc$write_1__VAL_3[71:0] : csrf_sepcc_reg_data_rl[71:0] ; - assign IF_csrf_sepcc_reg_read_wget__3506_BIT_34_3518__ETC___d23528 = + assign IF_csrf_sepcc_reg_read_wget__3508_BIT_34_3520__ETC___d23530 = csrf_sepcc_reg_data_rl[34] ? { csrf_sepcc_reg_data_rl[25:17], csrf_sepcc_reg_data_rl[33:31], csrf_sepcc_reg_data_rl[13:3], csrf_sepcc_reg_data_rl[30:28] } : csrf_sepcc_reg_data_rl[25:0] ; - assign IF_csrf_stcc_reg_read__6046_BITS_149_TO_86_274_ETC___d22771 = - ((newAddrDiff__h999501 == 64'd0) ? + assign IF_csrf_stcc_reg_read__6046_BITS_149_TO_86_274_ETC___d22773 = + ((newAddrDiff__h999536 == 64'd0) ? 2'd0 : - (csrf_stcc_reg_read__6046_BITS_149_TO_86_2740_A_ETC___d22752 ? + (csrf_stcc_reg_read__6046_BITS_149_TO_86_2742_A_ETC___d22754 ? 2'd3 : 2'd1)) == ((csrf_stcc_reg_read__6046_BITS_85_TO_83_6052_UL_ETC___d16053 && - _0_CONCAT_csrf_stcc_reg_read__6046_BITS_149_TO__ETC___d22763) ? + _0_CONCAT_csrf_stcc_reg_read__6046_BITS_149_TO__ETC___d22765) ? 2'd0 : ((csrf_stcc_reg_read__6046_BITS_85_TO_83_6052_UL_ETC___d16053 && - !_0_CONCAT_csrf_stcc_reg_read__6046_BITS_149_TO__ETC___d22763) ? + !_0_CONCAT_csrf_stcc_reg_read__6046_BITS_149_TO__ETC___d22765) ? 2'd1 : ((!csrf_stcc_reg_read__6046_BITS_85_TO_83_6052_UL_ETC___d16053 && - _0_CONCAT_csrf_stcc_reg_read__6046_BITS_149_TO__ETC___d22763) ? + _0_CONCAT_csrf_stcc_reg_read__6046_BITS_149_TO__ETC___d22765) ? 2'd3 : 2'd0))) ; - assign IF_csrf_stcc_reg_read__6046_BITS_149_TO_86_274_ETC___d22774 = - IF_csrf_stcc_reg_read__6046_BITS_149_TO_86_274_ETC___d22771 && - (newAddrDiff__h999501 == 64'd0 || - csrf_stcc_reg_read__6046_BITS_149_TO_86_2740_A_ETC___d22752 || - newAddrDiff__h999501 == - _18446744073709551615_SL_csrf_stcc_reg_read__60_ETC___d22755) ; - assign IF_csrf_stcc_reg_read__6046_BITS_149_TO_86_274_ETC___d22796 = - ((newAddrDiff__h999845 == 64'd0) ? + assign IF_csrf_stcc_reg_read__6046_BITS_149_TO_86_274_ETC___d22776 = + IF_csrf_stcc_reg_read__6046_BITS_149_TO_86_274_ETC___d22773 && + (newAddrDiff__h999536 == 64'd0 || + csrf_stcc_reg_read__6046_BITS_149_TO_86_2742_A_ETC___d22754 || + newAddrDiff__h999536 == + _18446744073709551615_SL_csrf_stcc_reg_read__60_ETC___d22757) ; + assign IF_csrf_stcc_reg_read__6046_BITS_149_TO_86_274_ETC___d22798 = + ((newAddrDiff__h999880 == 64'd0) ? 2'd0 : - (csrf_stcc_reg_read__6046_BITS_149_TO_86_2740_A_ETC___d22780 ? + (csrf_stcc_reg_read__6046_BITS_149_TO_86_2742_A_ETC___d22782 ? 2'd3 : 2'd1)) == ((csrf_stcc_reg_read__6046_BITS_85_TO_83_6052_UL_ETC___d16053 && - _0_CONCAT_csrf_stcc_reg_read__6046_BITS_149_TO__ETC___d22788) ? + _0_CONCAT_csrf_stcc_reg_read__6046_BITS_149_TO__ETC___d22790) ? 2'd0 : ((csrf_stcc_reg_read__6046_BITS_85_TO_83_6052_UL_ETC___d16053 && - !_0_CONCAT_csrf_stcc_reg_read__6046_BITS_149_TO__ETC___d22788) ? + !_0_CONCAT_csrf_stcc_reg_read__6046_BITS_149_TO__ETC___d22790) ? 2'd1 : ((!csrf_stcc_reg_read__6046_BITS_85_TO_83_6052_UL_ETC___d16053 && - _0_CONCAT_csrf_stcc_reg_read__6046_BITS_149_TO__ETC___d22788) ? + _0_CONCAT_csrf_stcc_reg_read__6046_BITS_149_TO__ETC___d22790) ? 2'd3 : 2'd0))) ; - assign IF_csrf_stcc_reg_read__6046_BITS_149_TO_86_274_ETC___d22799 = - IF_csrf_stcc_reg_read__6046_BITS_149_TO_86_274_ETC___d22796 && - (newAddrDiff__h999845 == 64'd0 || - csrf_stcc_reg_read__6046_BITS_149_TO_86_2740_A_ETC___d22780 || - newAddrDiff__h999845 == - _18446744073709551615_SL_csrf_stcc_reg_read__60_ETC___d22755) ; - assign IF_csrf_stcc_reg_read__6046_BIT_86_2736_AND_NO_ETC___d22802 = - (csrf_stcc_reg[86] && cause_interrupt__h995318) ? - (NOT_csrf_stcc_reg_read__6046_BITS_33_TO_28_606_ETC___d22739 || - IF_csrf_stcc_reg_read__6046_BITS_149_TO_86_274_ETC___d22774) && + assign IF_csrf_stcc_reg_read__6046_BITS_149_TO_86_274_ETC___d22801 = + IF_csrf_stcc_reg_read__6046_BITS_149_TO_86_274_ETC___d22798 && + (newAddrDiff__h999880 == 64'd0 || + csrf_stcc_reg_read__6046_BITS_149_TO_86_2742_A_ETC___d22782 || + newAddrDiff__h999880 == + _18446744073709551615_SL_csrf_stcc_reg_read__60_ETC___d22757) ; + assign IF_csrf_stcc_reg_read__6046_BIT_86_2738_AND_NO_ETC___d22804 = + (csrf_stcc_reg[86] && cause_interrupt__h995316) ? + (NOT_csrf_stcc_reg_read__6046_BITS_33_TO_28_606_ETC___d22741 || + IF_csrf_stcc_reg_read__6046_BITS_149_TO_86_274_ETC___d22776) && csrf_stcc_reg[152] : - (NOT_csrf_stcc_reg_read__6046_BITS_33_TO_28_606_ETC___d22739 || - IF_csrf_stcc_reg_read__6046_BITS_149_TO_86_274_ETC___d22799) && + (NOT_csrf_stcc_reg_read__6046_BITS_33_TO_28_606_ETC___d22741 || + IF_csrf_stcc_reg_read__6046_BITS_149_TO_86_274_ETC___d22801) && csrf_stcc_reg[152] ; - assign IF_csrf_stcc_reg_read__6046_BIT_86_2736_AND_NO_ETC___d22904 = - (csrf_stcc_reg[86] && cause_interrupt__h995318) ? - address__h999428 : - base__h999389 ; - assign IF_f_csr_reqs_first__3969_BIT_63_4123_THEN_NOT_ETC___d24133 = + assign IF_csrf_stcc_reg_read__6046_BIT_86_2738_AND_NO_ETC___d22906 = + (csrf_stcc_reg[86] && cause_interrupt__h995316) ? + address__h999463 : + base__h999424 ; + assign IF_f_csr_reqs_first__3971_BIT_63_4125_THEN_NOT_ETC___d24135 = f_csr_reqs$D_OUT[63] ? - x__h1031547[13:0] >= toBounds__h1008382 : - x__h1031547[13:0] <= toBoundsM1__h1008383 ; - assign IF_f_csr_reqs_first__3969_BIT_63_4123_THEN_NOT_ETC___d24155 = + x__h1031581[13:0] >= toBounds__h1008417 : + x__h1031581[13:0] <= toBoundsM1__h1008418 ; + assign IF_f_csr_reqs_first__3971_BIT_63_4125_THEN_NOT_ETC___d24157 = f_csr_reqs$D_OUT[63] ? - x__h1031950[13:0] >= toBounds__h1008785 : - x__h1031950[13:0] <= toBoundsM1__h1008786 ; - assign IF_f_csr_reqs_first__3969_BIT_63_4123_THEN_NOT_ETC___d24213 = + x__h1031984[13:0] >= toBounds__h1008820 : + x__h1031984[13:0] <= toBoundsM1__h1008821 ; + assign IF_f_csr_reqs_first__3971_BIT_63_4125_THEN_NOT_ETC___d24215 = f_csr_reqs$D_OUT[63] ? - x__h1032367[13:0] >= toBounds__h1009202 : - x__h1032367[13:0] <= toBoundsM1__h1009203 ; - assign IF_f_csr_reqs_first__3969_BIT_63_4123_THEN_NOT_ETC___d24233 = + x__h1032401[13:0] >= toBounds__h1009237 : + x__h1032401[13:0] <= toBoundsM1__h1009238 ; + assign IF_f_csr_reqs_first__3971_BIT_63_4125_THEN_NOT_ETC___d24235 = f_csr_reqs$D_OUT[63] ? - x__h1032770[13:0] >= toBounds__h1009605 : - x__h1032770[13:0] <= toBoundsM1__h1009606 ; - assign IF_f_csr_reqs_first__3969_BIT_63_4123_THEN_NOT_ETC___d24304 = + x__h1032804[13:0] >= toBounds__h1009640 : + x__h1032804[13:0] <= toBoundsM1__h1009641 ; + assign IF_f_csr_reqs_first__3971_BIT_63_4125_THEN_NOT_ETC___d24306 = f_csr_reqs$D_OUT[63] ? - x__h1033437[13:0] >= toBounds__h1010274 : - x__h1033437[13:0] <= toBoundsM1__h1010275 ; + x__h1033471[13:0] >= toBounds__h1010309 : + x__h1033471[13:0] <= toBoundsM1__h1010310 ; assign IF_fetchStage_RDY_pipelines_0_first__0253_AND__ETC___d21186 = (fetchStage$RDY_pipelines_0_first && (fetchStage$pipelines_0_first[268:266] != 3'd1 || @@ -26360,9 +26358,9 @@ module mkCore(CLK, IF_fetchStage_pipelines_0_first__0256_BITS_268_ETC___d21279 ; assign IF_fetchStage_pipelines_0_first__0256_BITS_268_ETC___d21867 = IF_fetchStage_pipelines_0_first__0256_BITS_268_ETC___d21860 || - rob$RDY_enqPort_0_enq && - regRenamingTable$RDY_rename_0_getRename && regRenamingTable$RDY_rename_0_claimRename && + regRenamingTable$RDY_rename_0_getRename && + rob$RDY_enqPort_0_enq && fetchStage$RDY_pipelines_0_deq && (fetchStage$pipelines_0_first[268:266] != 3'd1 || specTagManager$RDY_claimSpecTag) ; @@ -26513,9 +26511,9 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__0265_BITS_268_ETC___d21955 && IF_fetchStage_RDY_pipelines_1_first__0264_AND__ETC___d21743 && (IF_fetchStage_pipelines_1_first__0265_BITS_268_ETC___d21984 || - rob$RDY_enqPort_1_enq && - regRenamingTable$RDY_rename_1_getRename && regRenamingTable$RDY_rename_1_claimRename && + regRenamingTable$RDY_rename_1_getRename && + rob$RDY_enqPort_1_enq && fetchStage_RDY_pipelines_1_deq__0268_AND_NOT_f_ETC___d21994) ; assign IF_mmio_cRqQ_enqReq_lat_1_whas__87_THEN_mmio_c_ETC___d296 = mmio_cRqQ_enqReq_lat_0$whas ? @@ -26601,44 +26599,44 @@ module mkCore(CLK, !rf_read_3_rd2_coreFix_memExe_dispToRegQ_first__ETC___d3609) ? 2'd1 : 2'd3) } ; - assign IF_rob_deqPort_0_canDeq__3598_THEN_IF_NOT_rob__ETC___d23719 = + assign IF_rob_deqPort_0_canDeq__3600_THEN_IF_NOT_rob__ETC___d23721 = rob$deqPort_0_canDeq ? - y_avValue_snd_snd_snd_snd_snd__h1015810 : + y_avValue_snd_snd_snd_snd_snd__h1015845 : 64'd0 ; - assign IF_rob_deqPort_0_canDeq__3598_THEN_IF_NOT_rob__ETC___d23825 = - rob$deqPort_0_canDeq ? y_avValue_snd_fst__h1015794 : 5'd0 ; - assign IF_rob_deqPort_0_canDeq__3598_THEN_IF_NOT_rob__ETC___d23847 = + assign IF_rob_deqPort_0_canDeq__3600_THEN_IF_NOT_rob__ETC___d23827 = + rob$deqPort_0_canDeq ? y_avValue_snd_fst__h1015829 : 5'd0 ; + assign IF_rob_deqPort_0_canDeq__3600_THEN_IF_NOT_rob__ETC___d23849 = rob$deqPort_0_canDeq ? - y_avValue_snd_snd_snd_fst__h1015804 : + y_avValue_snd_snd_snd_fst__h1015839 : 2'd0 ; - assign IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23133 = - (highOffsetBits__h1008373 == 50'd0 && - IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23130 || - NOT_csrf_stcc_reg_read__6046_BITS_33_TO_28_606_ETC___d22739) && + assign IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23135 = + (highOffsetBits__h1008408 == 50'd0 && + IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23132 || + NOT_csrf_stcc_reg_read__6046_BITS_33_TO_28_606_ETC___d22741) && csrf_stcc_reg[152] ; - assign IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23179 = - (highOffsetBits__h1008776 == 50'd0 && - IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23174 || - NOT_IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN__ETC___d23177) && + assign IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23181 = + (highOffsetBits__h1008811 == 50'd0 && + IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23176 || + NOT_IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN__ETC___d23179) && IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16810 ; - assign IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23272 = - (highOffsetBits__h1009193 == 50'd0 && - IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23269 || - NOT_csrf_mtcc_reg_read__6198_BITS_33_TO_28_621_ETC___d22810) && + assign IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23274 = + (highOffsetBits__h1009228 == 50'd0 && + IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23271 || + NOT_csrf_mtcc_reg_read__6198_BITS_33_TO_28_621_ETC___d22812) && csrf_mtcc_reg[152] ; - assign IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23316 = - (highOffsetBits__h1009596 == 50'd0 && - IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23311 || - NOT_IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN__ETC___d23314) && + assign IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23318 = + (highOffsetBits__h1009631 == 50'd0 && + IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23313 || + NOT_IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN__ETC___d23316) && IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16818 ; - assign IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23430 = - (highOffsetBits__h1010265 == 50'd0 && - IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23424 || - NOT_csrf_rg_dpc_read__6343_BITS_33_TO_28_6360__ETC___d23427) && + assign IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23432 = + (highOffsetBits__h1010300 == 50'd0 && + IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23426 || + NOT_csrf_rg_dpc_read__6343_BITS_33_TO_28_6360__ETC___d23429) && csrf_rg_dpc[152] ; - assign IF_rob_deqPort_1_canDeq__3602_THEN_IF_NOT_rob__ETC___d23839 = + assign IF_rob_deqPort_1_canDeq__3604_THEN_IF_NOT_rob__ETC___d23841 = rob$deqPort_1_canDeq ? - IF_NOT_rob_deqPort_1_deq_data__3605_BIT_25_360_ETC___d23838 : + IF_NOT_rob_deqPort_1_deq_data__3607_BIT_25_360_ETC___d23840 : rob$deqPort_0_canDeq && rob$deqPort_0_deq_data[26] ; assign IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18759 = sbCons$lazyLookup_0_get[3] ? @@ -26768,7 +26766,7 @@ module mkCore(CLK, IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__840_ETC___d19071) ; assign IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d19093 = sbCons$lazyLookup_0_get[3] ? - repBound__h898286 : + repBound__h898284 : (NOT_coreFix_aluExe_0_bypassWire_0_whas__8403_8_ETC___d18430 ? coreFix_aluExe_0_bypassWire_3$wget[9:7] : IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__840_ETC___d19089) ; @@ -26799,7 +26797,7 @@ module mkCore(CLK, assign IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d19196 = sbCons$lazyLookup_0_get[2] ? { rf$read_0_rd2, - repBound__h900613, + repBound__h900611, rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19168, rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19169, rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19181 } : @@ -26934,7 +26932,7 @@ module mkCore(CLK, IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__564_ETC___d16676) ; assign IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16698 = sbCons$lazyLookup_1_get[3] ? - repBound__h857577 : + repBound__h857576 : (NOT_coreFix_aluExe_1_bypassWire_0_whas__5640_5_ETC___d15667 ? coreFix_aluExe_0_bypassWire_3$wget[9:7] : IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__564_ETC___d16694) ; @@ -26965,7 +26963,7 @@ module mkCore(CLK, assign IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16801 = sbCons$lazyLookup_1_get[2] ? { rf$read_1_rd2, - repBound__h860539, + repBound__h860538, rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16773, rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16774, rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16786 } : @@ -27100,7 +27098,7 @@ module mkCore(CLK, IF_NOT_coreFix_memExe_bypassWire_0_whas__704_7_ETC___d3305) ; assign IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3327 = sbCons$lazyLookup_3_get[3] ? - repBound__h237318 : + repBound__h237315 : (NOT_coreFix_memExe_bypassWire_0_whas__704_710__ETC___d2731 ? coreFix_aluExe_0_bypassWire_3$wget[9:7] : IF_NOT_coreFix_memExe_bypassWire_0_whas__704_7_ETC___d3323) ; @@ -27256,7 +27254,7 @@ module mkCore(CLK, IF_NOT_coreFix_memExe_bypassWire_0_whas__704_7_ETC___d3572) ; assign IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3589 = sbCons$lazyLookup_3_get[2] ? - repBound__h239003 : + repBound__h239000 : (NOT_coreFix_memExe_bypassWire_0_whas__704_710__ETC___d2758 ? coreFix_aluExe_0_bypassWire_3$wget[9:7] : IF_NOT_coreFix_memExe_bypassWire_0_whas__704_7_ETC___d3585) ; @@ -27284,64 +27282,64 @@ module mkCore(CLK, (NOT_coreFix_memExe_bypassWire_0_whas__704_710__ETC___d2758 ? coreFix_aluExe_0_bypassWire_3$wget[3:0] : IF_NOT_coreFix_memExe_bypassWire_0_whas__704_7_ETC___d3628) ; - assign IF_sfdin02325_BIT_33_THEN_2_ELSE_0__q51 = - sfdin__h602325[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin22015_BIT_4_THEN_2_ELSE_0__q168 = - sfdin__h822015[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin30308_BIT_33_THEN_2_ELSE_0__q76 = - sfdin__h630308[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin43858_BIT_4_THEN_2_ELSE_0__q151 = - sfdin__h743858[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin48074_BIT_33_THEN_2_ELSE_0__q86 = - sfdin__h648074[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin76055_BIT_33_THEN_2_ELSE_0__q111 = - sfdin__h676055[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin82711_BIT_4_THEN_2_ELSE_0__q191 = - sfdin__h782711[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin84559_BIT_33_THEN_2_ELSE_0__q41 = - sfdin__h584559[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin93821_BIT_33_THEN_2_ELSE_0__q121 = - sfdin__h693821[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd02458_BIT_33_THEN_2_ELSE_0__q126 = - _theResult___snd__h702458[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd10962_BIT_33_THEN_2_ELSE_0__q56 = - _theResult___snd__h610962[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd12395_BIT_4_THEN_2_ELSE_0__q164 = - _theResult___snd__h812395[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd30800_BIT_4_THEN_2_ELSE_0__q171 = - _theResult___snd__h830800[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd34238_BIT_4_THEN_2_ELSE_0__q147 = - _theResult___snd__h734238[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd38921_BIT_33_THEN_2_ELSE_0__q78 = - _theResult___snd__h638921[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd52643_BIT_4_THEN_2_ELSE_0__q154 = - _theResult___snd__h752643[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd56711_BIT_33_THEN_2_ELSE_0__q91 = - _theResult___snd__h656711[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd73091_BIT_4_THEN_2_ELSE_0__q187 = - _theResult___snd__h773091[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd84668_BIT_33_THEN_2_ELSE_0__q113 = - _theResult___snd__h684668[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd91496_BIT_4_THEN_2_ELSE_0__q194 = - _theResult___snd__h791496[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd93172_BIT_33_THEN_2_ELSE_0__q43 = - _theResult___snd__h593172[33] ? 2'd2 : 2'd0 ; - assign INV_commitStage_commitTrap_BITS_217_TO_199__q15 = + assign IF_sfdin02323_BIT_33_THEN_2_ELSE_0__q51 = + sfdin__h602323[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin22012_BIT_4_THEN_2_ELSE_0__q168 = + sfdin__h822012[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin30306_BIT_33_THEN_2_ELSE_0__q76 = + sfdin__h630306[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin43855_BIT_4_THEN_2_ELSE_0__q151 = + sfdin__h743855[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin48072_BIT_33_THEN_2_ELSE_0__q86 = + sfdin__h648072[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin76053_BIT_33_THEN_2_ELSE_0__q111 = + sfdin__h676053[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin82708_BIT_4_THEN_2_ELSE_0__q191 = + sfdin__h782708[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin84557_BIT_33_THEN_2_ELSE_0__q41 = + sfdin__h584557[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin93819_BIT_33_THEN_2_ELSE_0__q121 = + sfdin__h693819[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd02456_BIT_33_THEN_2_ELSE_0__q126 = + _theResult___snd__h702456[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd10960_BIT_33_THEN_2_ELSE_0__q56 = + _theResult___snd__h610960[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd12392_BIT_4_THEN_2_ELSE_0__q164 = + _theResult___snd__h812392[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd30797_BIT_4_THEN_2_ELSE_0__q171 = + _theResult___snd__h830797[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd34235_BIT_4_THEN_2_ELSE_0__q147 = + _theResult___snd__h734235[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd38919_BIT_33_THEN_2_ELSE_0__q78 = + _theResult___snd__h638919[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd52640_BIT_4_THEN_2_ELSE_0__q154 = + _theResult___snd__h752640[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd56709_BIT_33_THEN_2_ELSE_0__q91 = + _theResult___snd__h656709[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd73088_BIT_4_THEN_2_ELSE_0__q187 = + _theResult___snd__h773088[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd84666_BIT_33_THEN_2_ELSE_0__q113 = + _theResult___snd__h684666[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd91493_BIT_4_THEN_2_ELSE_0__q194 = + _theResult___snd__h791493[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd93170_BIT_33_THEN_2_ELSE_0__q43 = + _theResult___snd__h593170[33] ? 2'd2 : 2'd0 ; + assign INV_commitStage_commitTrap_BITS_217_TO_199__q16 = ~commitStage_commitTrap[217:199] ; assign INV_coreFix_aluExe_0_regToExeQ_first__9457_BIT_ETC___d19771 = { ~coreFix_aluExe_0_regToExeQ$first[286:268], INV_coreFix_aluExe_0_regToExeQfirst_BITS_286__ETC__q13[0] ? - x__h906572 : + x__h906570 : 6'd0, - x__h906745, - x__h906765 } ; + x__h906743, + x__h906763 } ; assign INV_coreFix_aluExe_0_regToExeQ_first__9457_BIT_ETC___d19835 = { ~coreFix_aluExe_0_regToExeQ$first[157:139], INV_coreFix_aluExe_0_regToExeQfirst_BITS_157__ETC__q14[0] ? - x__h907120 : + x__h907118 : 6'd0, - x__h907293, - x__h907313 } ; + x__h907291, + x__h907311 } ; assign INV_coreFix_aluExe_0_regToExeQfirst_BITS_157__ETC__q14 = ~coreFix_aluExe_0_regToExeQ$first[157:139] ; assign INV_coreFix_aluExe_0_regToExeQfirst_BITS_286__ETC__q13 = @@ -27349,17 +27347,17 @@ module mkCore(CLK, assign INV_coreFix_aluExe_1_regToExeQ_first__7341_BIT_ETC___d17655 = { ~coreFix_aluExe_1_regToExeQ$first[286:268], INV_coreFix_aluExe_1_regToExeQfirst_BITS_286__ETC__q11[0] ? - x__h866886 : + x__h866885 : 6'd0, - x__h867059, - x__h867079 } ; + x__h867058, + x__h867078 } ; assign INV_coreFix_aluExe_1_regToExeQ_first__7341_BIT_ETC___d17719 = { ~coreFix_aluExe_1_regToExeQ$first[157:139], INV_coreFix_aluExe_1_regToExeQfirst_BITS_157__ETC__q12[0] ? - x__h867434 : + x__h867433 : 6'd0, - x__h867607, - x__h867627 } ; + x__h867606, + x__h867626 } ; assign INV_coreFix_aluExe_1_regToExeQfirst_BITS_157__ETC__q12 = ~coreFix_aluExe_1_regToExeQ$first[157:139] ; assign INV_coreFix_aluExe_1_regToExeQfirst_BITS_286__ETC__q11 = @@ -27370,8 +27368,8 @@ module mkCore(CLK, ~coreFix_memExe_respLrScAmoQ_data_0[108:90] ; assign INV_mmio_dataRespQ_data_0_BITS_108_TO_90__q9 = ~mmio_dataRespQ_data_0[108:90] ; - assign INV_x83399_BITS_108_TO_90__q34 = ~x__h183399[108:90] ; - assign INV_x99251_BITS_108_TO_90__q36 = ~x__h199251[108:90] ; + assign INV_x83397_BITS_108_TO_90__q34 = ~x__h183397[108:90] ; + assign INV_x99249_BITS_108_TO_90__q36 = ~x__h199249[108:90] ; assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d10746 = !_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9532 || (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9533 ? @@ -27459,136 +27457,136 @@ module mkCore(CLK, !IF_IF_NOT_csrf_prv_reg_read__0286_EQ_3_0287_02_ETC___d20323[15] && !checkForException___d21604[13] && NOT_csrf_fs_reg_read__6010_EQ_0_0640_0641_OR_N_ETC___d21629 ; - assign NOT_IF_NOT_rob_deqPort_0_canDeq__3598_3599_OR__ETC___d23844 = - (fflags__h1016316 & csrf_fflags_reg) != fflags__h1016316 || - !r__h853139 && - (IF_rob_deqPort_1_canDeq__3602_THEN_IF_NOT_rob__ETC___d23839 || - fflags__h1016316 != 5'd0) ; + assign NOT_IF_NOT_rob_deqPort_0_canDeq__3600_3601_OR__ETC___d23846 = + (fflags__h1016351 & csrf_fflags_reg) != fflags__h1016351 || + !r__h853138 && + (IF_rob_deqPort_1_canDeq__3604_THEN_IF_NOT_rob__ETC___d23841 || + fflags__h1016351 != 5'd0) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d12707 = - !f1_sfd__h714900[21] && !f1_sfd__h714900[20] && - !f1_sfd__h714900[19] && - !f1_sfd__h714900[18] && - !f1_sfd__h714900[17] && - !f1_sfd__h714900[16] && - !f1_sfd__h714900[15] && - !f1_sfd__h714900[14] && - !f1_sfd__h714900[13] && - !f1_sfd__h714900[12] && - !f1_sfd__h714900[11] && - !f1_sfd__h714900[10] && - !f1_sfd__h714900[9] && - !f1_sfd__h714900[8] && - !f1_sfd__h714900[7] && - !f1_sfd__h714900[6] && - !f1_sfd__h714900[5] && - !f1_sfd__h714900[4] && - !f1_sfd__h714900[3] && - !f1_sfd__h714900[2] && - !f1_sfd__h714900[1] && - !f1_sfd__h714900[0] ; + !f1_sfd__h714897[21] && !f1_sfd__h714897[20] && + !f1_sfd__h714897[19] && + !f1_sfd__h714897[18] && + !f1_sfd__h714897[17] && + !f1_sfd__h714897[16] && + !f1_sfd__h714897[15] && + !f1_sfd__h714897[14] && + !f1_sfd__h714897[13] && + !f1_sfd__h714897[12] && + !f1_sfd__h714897[11] && + !f1_sfd__h714897[10] && + !f1_sfd__h714897[9] && + !f1_sfd__h714897[8] && + !f1_sfd__h714897[7] && + !f1_sfd__h714897[6] && + !f1_sfd__h714897[5] && + !f1_sfd__h714897[4] && + !f1_sfd__h714897[3] && + !f1_sfd__h714897[2] && + !f1_sfd__h714897[1] && + !f1_sfd__h714897[0] ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d13437 = - !f3_sfd__h793198[21] && !f3_sfd__h793198[20] && - !f3_sfd__h793198[19] && - !f3_sfd__h793198[18] && - !f3_sfd__h793198[17] && - !f3_sfd__h793198[16] && - !f3_sfd__h793198[15] && - !f3_sfd__h793198[14] && - !f3_sfd__h793198[13] && - !f3_sfd__h793198[12] && - !f3_sfd__h793198[11] && - !f3_sfd__h793198[10] && - !f3_sfd__h793198[9] && - !f3_sfd__h793198[8] && - !f3_sfd__h793198[7] && - !f3_sfd__h793198[6] && - !f3_sfd__h793198[5] && - !f3_sfd__h793198[4] && - !f3_sfd__h793198[3] && - !f3_sfd__h793198[2] && - !f3_sfd__h793198[1] && - !f3_sfd__h793198[0] ; + !f3_sfd__h793195[21] && !f3_sfd__h793195[20] && + !f3_sfd__h793195[19] && + !f3_sfd__h793195[18] && + !f3_sfd__h793195[17] && + !f3_sfd__h793195[16] && + !f3_sfd__h793195[15] && + !f3_sfd__h793195[14] && + !f3_sfd__h793195[13] && + !f3_sfd__h793195[12] && + !f3_sfd__h793195[11] && + !f3_sfd__h793195[10] && + !f3_sfd__h793195[9] && + !f3_sfd__h793195[8] && + !f3_sfd__h793195[7] && + !f3_sfd__h793195[6] && + !f3_sfd__h793195[5] && + !f3_sfd__h793195[4] && + !f3_sfd__h793195[3] && + !f3_sfd__h793195[2] && + !f3_sfd__h793195[1] && + !f3_sfd__h793195[0] ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d14207 = - !f2_sfd__h753894[21] && !f2_sfd__h753894[20] && - !f2_sfd__h753894[19] && - !f2_sfd__h753894[18] && - !f2_sfd__h753894[17] && - !f2_sfd__h753894[16] && - !f2_sfd__h753894[15] && - !f2_sfd__h753894[14] && - !f2_sfd__h753894[13] && - !f2_sfd__h753894[12] && - !f2_sfd__h753894[11] && - !f2_sfd__h753894[10] && - !f2_sfd__h753894[9] && - !f2_sfd__h753894[8] && - !f2_sfd__h753894[7] && - !f2_sfd__h753894[6] && - !f2_sfd__h753894[5] && - !f2_sfd__h753894[4] && - !f2_sfd__h753894[3] && - !f2_sfd__h753894[2] && - !f2_sfd__h753894[1] && - !f2_sfd__h753894[0] ; + !f2_sfd__h753891[21] && !f2_sfd__h753891[20] && + !f2_sfd__h753891[19] && + !f2_sfd__h753891[18] && + !f2_sfd__h753891[17] && + !f2_sfd__h753891[16] && + !f2_sfd__h753891[15] && + !f2_sfd__h753891[14] && + !f2_sfd__h753891[13] && + !f2_sfd__h753891[12] && + !f2_sfd__h753891[11] && + !f2_sfd__h753891[10] && + !f2_sfd__h753891[9] && + !f2_sfd__h753891[8] && + !f2_sfd__h753891[7] && + !f2_sfd__h753891[6] && + !f2_sfd__h753891[5] && + !f2_sfd__h753891[4] && + !f2_sfd__h753891[3] && + !f2_sfd__h753891[2] && + !f2_sfd__h753891[1] && + !f2_sfd__h753891[0] ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d14916 = - (f1_exp__h714899 != 8'd255 || f1_sfd__h714900 == 23'd0) && - (f1_exp__h714899 != 8'd255 || f1_sfd__h714900 != 23'd0) && - (f1_exp__h714899 != 8'd0 || f1_sfd__h714900 != 23'd0) && + (f1_exp__h714896 != 8'd255 || f1_sfd__h714897 == 23'd0) && + (f1_exp__h714896 != 8'd255 || f1_sfd__h714897 != 23'd0) && + (f1_exp__h714896 != 8'd0 || f1_sfd__h714897 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14913 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d14958 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d14916 | - ((f2_exp__h753893 != 8'd255 || f2_sfd__h753894 == 23'd0) && - (f2_exp__h753893 != 8'd255 || f2_sfd__h753894 != 23'd0) && - (f2_exp__h753893 != 8'd0 || f2_sfd__h753894 != 23'd0) && + ((f2_exp__h753890 != 8'd255 || f2_sfd__h753891 == 23'd0) && + (f2_exp__h753890 != 8'd255 || f2_sfd__h753891 != 23'd0) && + (f2_exp__h753890 != 8'd0 || f2_sfd__h753891 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14954) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15016 = - (f1_exp__h714899 != 8'd255 || f1_sfd__h714900 == 23'd0) && - (f1_exp__h714899 != 8'd255 || f1_sfd__h714900 != 23'd0) && - (f1_exp__h714899 != 8'd0 || f1_sfd__h714900 != 23'd0) && + (f1_exp__h714896 != 8'd255 || f1_sfd__h714897 == 23'd0) && + (f1_exp__h714896 != 8'd255 || f1_sfd__h714897 != 23'd0) && + (f1_exp__h714896 != 8'd0 || f1_sfd__h714897 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15013 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15027 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15016 | - ((f2_exp__h753893 != 8'd255 || f2_sfd__h753894 == 23'd0) && - (f2_exp__h753893 != 8'd255 || f2_sfd__h753894 != 23'd0) && - (f2_exp__h753893 != 8'd0 || f2_sfd__h753894 != 23'd0) && + ((f2_exp__h753890 != 8'd255 || f2_sfd__h753891 == 23'd0) && + (f2_exp__h753890 != 8'd255 || f2_sfd__h753891 != 23'd0) && + (f2_exp__h753890 != 8'd0 || f2_sfd__h753891 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15023) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15056 = - (f1_exp__h714899 != 8'd255 || f1_sfd__h714900 == 23'd0) && - (f1_exp__h714899 != 8'd255 || f1_sfd__h714900 != 23'd0) && - (f1_exp__h714899 != 8'd0 || f1_sfd__h714900 != 23'd0) && + (f1_exp__h714896 != 8'd255 || f1_sfd__h714897 == 23'd0) && + (f1_exp__h714896 != 8'd255 || f1_sfd__h714897 != 23'd0) && + (f1_exp__h714896 != 8'd0 || f1_sfd__h714897 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15053 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15071 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15056 | - ((f2_exp__h753893 != 8'd255 || f2_sfd__h753894 == 23'd0) && - (f2_exp__h753893 != 8'd255 || f2_sfd__h753894 != 23'd0) && - (f2_exp__h753893 != 8'd0 || f2_sfd__h753894 != 23'd0) && + ((f2_exp__h753890 != 8'd255 || f2_sfd__h753891 == 23'd0) && + (f2_exp__h753890 != 8'd255 || f2_sfd__h753891 != 23'd0) && + (f2_exp__h753890 != 8'd0 || f2_sfd__h753891 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15067) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15102 = - (f1_exp__h714899 != 8'd255 || f1_sfd__h714900 == 23'd0) && - (f1_exp__h714899 != 8'd255 || f1_sfd__h714900 != 23'd0) && - (f1_exp__h714899 != 8'd0 || f1_sfd__h714900 != 23'd0) && + (f1_exp__h714896 != 8'd255 || f1_sfd__h714897 == 23'd0) && + (f1_exp__h714896 != 8'd255 || f1_sfd__h714897 != 23'd0) && + (f1_exp__h714896 != 8'd0 || f1_sfd__h714897 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15099 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15115 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15102 | - ((f2_exp__h753893 != 8'd255 || f2_sfd__h753894 == 23'd0) && - (f2_exp__h753893 != 8'd255 || f2_sfd__h753894 != 23'd0) && - (f2_exp__h753893 != 8'd0 || f2_sfd__h753894 != 23'd0) && + ((f2_exp__h753890 != 8'd255 || f2_sfd__h753891 == 23'd0) && + (f2_exp__h753890 != 8'd255 || f2_sfd__h753891 != 23'd0) && + (f2_exp__h753890 != 8'd0 || f2_sfd__h753891 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15111) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15144 = - (f1_exp__h714899 != 8'd255 || f1_sfd__h714900 == 23'd0) && - (f1_exp__h714899 != 8'd255 || f1_sfd__h714900 != 23'd0) && - (f1_exp__h714899 != 8'd0 || f1_sfd__h714900 != 23'd0) && + (f1_exp__h714896 != 8'd255 || f1_sfd__h714897 == 23'd0) && + (f1_exp__h714896 != 8'd255 || f1_sfd__h714897 != 23'd0) && + (f1_exp__h714896 != 8'd0 || f1_sfd__h714897 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15141 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15157 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15144 | - ((f2_exp__h753893 != 8'd255 || f2_sfd__h753894 == 23'd0) && - (f2_exp__h753893 != 8'd255 || f2_sfd__h753894 != 23'd0) && - (f2_exp__h753893 != 8'd0 || f2_sfd__h753894 != 23'd0) && + ((f2_exp__h753890 != 8'd255 || f2_sfd__h753891 == 23'd0) && + (f2_exp__h753890 != 8'd255 || f2_sfd__h753891 != 23'd0) && + (f2_exp__h753890 != 8'd0 || f2_sfd__h753891 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15153) ; - assign NOT_IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN__ETC___d23314 = + assign NOT_IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN__ETC___d23316 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16252 >= 6'd50 ; - assign NOT_IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN__ETC___d23177 = + assign NOT_IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN__ETC___d23179 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16100 >= 6'd50 ; assign NOT_commitStage_commitTrap_2268_BITS_44_TO_43__ETC___d22534 = @@ -27611,7 +27609,7 @@ module mkCore(CLK, coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty && fetchStage$iTlbIfc_noPendingReq && coreFix_memExe_dTlb$noPendingReq ; - assign NOT_commitStage_rg_run_state_2266_2267_AND_NOT_ETC___d23033 = + assign NOT_commitStage_rg_run_state_2266_2267_AND_NOT_ETC___d23035 = !commitStage_rg_run_state && !commitStage_commitTrap[238] && !rob$deqPort_0_deq_data[274] && !rob$deqPort_0_deq_data[18] && @@ -28360,17 +28358,14 @@ module mkCore(CLK, (fetchStage$pipelines_1_first[305:274] != 32'h10500073 || !csrf_tw_reg || csrf_prv_reg == 2'd3) ; - assign NOT_csrf_mtcc_reg_read__6198_BITS_33_TO_28_621_ETC___d22810 = + assign NOT_csrf_mtcc_reg_read__6198_BITS_33_TO_28_621_ETC___d22812 = csrf_mtcc_reg[33:28] >= 6'd50 ; - assign NOT_csrf_prv_reg_read__0286_ULE_1_2614_2729_OR_ETC___d22734 = + assign NOT_csrf_prv_reg_read__0286_ULE_1_2614_2730_OR_ETC___d22736 = !csrf_prv_reg_read__0286_ULE_1___d22614 || - ((commitStage_commitTrap[44:43] == 2'd1) ? - !_0b0_CONCAT_csrf_medeleg_28_26_reg_read__6161_6_ETC___d22642 : - commitStage_commitTrap[44:43] == 2'd0 || - !_0b0_CONCAT_csrf_mideleg_11_reg_read__6172_6173_ETC___d22644) ; - assign NOT_csrf_rg_dpc_read__6343_BITS_33_TO_28_6360__ETC___d23427 = + CASE_commitStage_commitTrap_BITS_44_TO_43_0_NO_ETC__q277 ; + assign NOT_csrf_rg_dpc_read__6343_BITS_33_TO_28_6360__ETC___d23429 = csrf_rg_dpc[33:28] >= 6'd50 ; - assign NOT_csrf_stcc_reg_read__6046_BITS_33_TO_28_606_ETC___d22739 = + assign NOT_csrf_stcc_reg_read__6046_BITS_33_TO_28_606_ETC___d22741 = csrf_stcc_reg[33:28] >= 6'd50 ; assign NOT_fetchStage_pipelines_0_canDeq__0254_0255_O_ETC___d21283 = !fetchStage$pipelines_0_canDeq || @@ -28596,12 +28591,12 @@ module mkCore(CLK, epochManager$checkEpoch_1_check ; assign NOT_mmio_dataPendQ_empty_80_378_AND_rob_RDY_se_ETC___d1379 = !mmio_dataPendQ_empty && rob$RDY_setExecuted_deqLSQ && - coreFix_memExe_lsq$RDY_firstSt && - coreFix_memExe_lsq$RDY_deqSt ; + coreFix_memExe_lsq$RDY_deqSt && + coreFix_memExe_lsq$RDY_firstSt ; assign NOT_mmio_dataPendQ_empty_80_378_AND_rob_RDY_se_ETC___d2026 = !mmio_dataPendQ_empty && rob$RDY_setExecuted_deqLSQ && - coreFix_memExe_lsq$RDY_firstLd && - coreFix_memExe_lsq$RDY_deqLd ; + coreFix_memExe_lsq$RDY_deqLd && + coreFix_memExe_lsq$RDY_firstLd ; assign NOT_regRenamingTable_rename_0_canRename__1151__ETC___d21667 = !regRenamingTable$rename_0_canRename || fetchStage$pipelines_0_first[273:269] == 5'd0 || @@ -28669,14 +28664,14 @@ module mkCore(CLK, epochManager$checkEpoch_1_check && (!fetchStage$pipelines_0_canDeq || NOT_fetchStage_pipelines_0_first__0256_BITS_26_ETC___d21805) ; - assign NOT_rob_deqPort_0_canDeq__3598_3599_OR_rob_RDY_ETC___d23639 = + assign NOT_rob_deqPort_0_canDeq__3600_3601_OR_regRena_ETC___d23641 = (!rob$deqPort_0_canDeq || - rob$RDY_deqPort_0_deq && - regRenamingTable$RDY_commit_0_commit) && + regRenamingTable$RDY_commit_0_commit && + rob$RDY_deqPort_0_deq) && (!rob$deqPort_1_canDeq || rob$RDY_deqPort_1_deq_data && - NOT_rob_deqPort_1_deq_data__3605_BIT_25_3606_3_ETC___d23636) ; - assign NOT_rob_deqPort_0_canDeq__3598_3599_OR_rob_deq_ETC___d23818 = + NOT_rob_deqPort_1_deq_data__3607_BIT_25_3608_3_ETC___d23638) ; + assign NOT_rob_deqPort_0_canDeq__3600_3601_OR_rob_deq_ETC___d23820 = (!rob$deqPort_0_canDeq || rob$deqPort_0_deq_data[25] && !rob$deqPort_0_deq_data[18] && !rob$deqPort_0_deq_data[274] && @@ -28691,15 +28686,15 @@ module mkCore(CLK, rob$deqPort_0_deq_data[469:465] != 5'd24 && rob$deqPort_0_deq_data[469:465] != 5'd25) && rob$deqPort_1_canDeq ; - assign NOT_rob_deqPort_0_deq_data__2261_BITS_469_TO_4_ETC___d23022 = + assign NOT_rob_deqPort_0_deq_data__2261_BITS_469_TO_4_ETC___d23024 = rob$deqPort_0_deq_data[469:465] != 5'd17 || - (IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 != + (IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 != 6'd7 || csrf_stats_module_writeQ$FULL_N) && - (IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 != + (IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 != 6'd6 || csrf_terminate_module_terminateQ$FULL_N) ; - assign NOT_rob_deqPort_1_deq_data__3605_BIT_25_3606_3_ETC___d23636 = + assign NOT_rob_deqPort_1_deq_data__3607_BIT_25_3608_3_ETC___d23638 = !rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[274] || rob$deqPort_1_deq_data[469:465] == 5'd0 || @@ -28712,7 +28707,7 @@ module mkCore(CLK, rob$deqPort_1_deq_data[469:465] == 5'd20 || rob$deqPort_1_deq_data[469:465] == 5'd24 || rob$deqPort_1_deq_data[469:465] == 5'd25 || - rob$RDY_deqPort_1_deq && regRenamingTable$RDY_commit_1_commit ; + regRenamingTable$RDY_commit_1_commit && rob$RDY_deqPort_1_deq ; assign NOT_specTagManager_canClaim__1149_1248_OR_NOT__ETC___d21921 = !specTagManager$canClaim || !regRenamingTable$rename_0_canRename || @@ -28732,47 +28727,47 @@ module mkCore(CLK, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q38, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q39 } ; assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d7127 = - { CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q293, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q294, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q295, + { CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q295, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q296, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q297, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q298 } ; + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q298, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q299, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q300 } ; assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d7137 = { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d7096, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q305, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q307, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d7127, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q306, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q307 } ; + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q308, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q309 } ; assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d7144 = - { CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q314, - !CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q315, + { CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q316, + !CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q317, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d7137, - x__h508765 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d24474 = - { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q316, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q317, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q318 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d24407 = - { CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q278, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q279, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q280 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d24438 = - { CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q299, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q300, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q301, + x__h508764 } ; + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d24476 = + { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q318, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q319, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q320 } ; + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d24409 = + { CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q280, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q281, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q282 } ; + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d24440 = + { CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q301, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q302, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q303, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q304 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d24448 = - { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d24407, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q308, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d24438, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q309, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q310 } ; + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q304, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q305, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q306 } ; + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d24450 = + { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d24409, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q310, + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d24440, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q311, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q312 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12797 = - { {4{f1_exp14899_MINUS_127__q148[7]}}, - f1_exp14899_MINUS_127__q148 } ; + { {4{f1_exp14896_MINUS_127__q148[7]}}, + f1_exp14896_MINUS_127__q148 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12798 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12797 ^ 12'h800) <= @@ -28782,8 +28777,8 @@ module mkCore(CLK, 12'h800) < 12'd1026 ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13512 = - { {4{f3_exp93197_MINUS_127__q165[7]}}, - f3_exp93197_MINUS_127__q165 } ; + { {4{f3_exp93194_MINUS_127__q165[7]}}, + f3_exp93194_MINUS_127__q165 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13513 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13512 ^ 12'h800) <= @@ -28793,8 +28788,8 @@ module mkCore(CLK, 12'h800) < 12'd1026 ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14282 = - { {4{f2_exp53893_MINUS_127__q188[7]}}, - f2_exp53893_MINUS_127__q188 } ; + { {4{f2_exp53890_MINUS_127__q188[7]}}, + f2_exp53890_MINUS_127__q188 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14283 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14282 ^ 12'h800) <= @@ -28822,21 +28817,21 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q189[10:0] - 11'd1023 ; assign SEXT_SEL_ARR_SEL_ARR_coreFix_memExe_dMem_cache_ETC___d4881 = - { {64{x__h264732[63]}}, x__h264732 } ; + { {64{x__h264730[63]}}, x__h264730 } ; assign SEXT_SEL_ARR_SEL_ARR_coreFix_memExe_dMem_cache_ETC___d4889 = - { {96{x__h264887[31]}}, x__h264887 } ; - assign SEXT__0_CONCAT_IF_INV_commitStage_commitTrap_2_ETC___d22677 = - x__h997587 | in__h997656[63:0] ; + { {96{x__h264885[31]}}, x__h264885 } ; + assign SEXT__0_CONCAT_IF_INV_commitStage_commitTrap_2_ETC___d22678 = + x__h997622 | in__h997691[63:0] ; assign SEXT__0_CONCAT_IF_csrf_mepcc_reg_data_lat_0_wh_ETC___d16261 = - x__h855226 | in__h855451[63:0] ; + x__h855225 | in__h855450[63:0] ; assign SEXT__0_CONCAT_IF_csrf_sepcc_reg_data_lat_0_wh_ETC___d16109 = - x__h854233 | in__h854459[63:0] ; + x__h854232 | in__h854458[63:0] ; assign SEXT__0_CONCAT_csrf_mtcc_reg_read__6198_BITS_8_ETC___d16222 = - x__h896272 | in__h855147[63:0] ; + x__h896270 | in__h855146[63:0] ; assign SEXT__0_CONCAT_csrf_rg_dpc_read__6343_BITS_85__ETC___d16367 = - x__h896617 | in__h855977[63:0] ; + x__h896615 | in__h855976[63:0] ; assign SEXT__0_CONCAT_csrf_stcc_reg_read__6046_BITS_8_ETC___d16070 = - x__h895988 | in__h854154[63:0] ; + x__h895986 | in__h854153[63:0] ; assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10071 = { coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q83[10], coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q83 } ; @@ -28890,15 +28885,15 @@ module mkCore(CLK, 8'd127 ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d10694 = { 3'd0, - _theResult___fst_exp__h630314 == 8'd0 && - (sfdin__h630308[56:34] == 23'd0 || guard__h622215 != 2'b0), + _theResult___fst_exp__h630312 == 8'd0 && + (sfdin__h630306[56:34] == 23'd0 || guard__h622213 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h630911 == 8'd255 && - _theResult___fst_sfd__h630912 == 23'd0, + _theResult___fst_exp__h630909 == 8'd255 && + _theResult___fst_sfd__h630910 == 23'd0, 1'd0, - _theResult___fst_exp__h630314 != 8'd255 && - guard__h622215 != 2'b0 } ; + _theResult___fst_exp__h630312 != 8'd255 && + guard__h622213 != 2'b0 } ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d11166 = ({ 3'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d11164 } ^ @@ -28906,15 +28901,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d12091 = { 3'd0, - _theResult___fst_exp__h676061 == 8'd0 && - (sfdin__h676055[56:34] == 23'd0 || guard__h667962 != 2'b0), + _theResult___fst_exp__h676059 == 8'd0 && + (sfdin__h676053[56:34] == 23'd0 || guard__h667960 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h676658 == 8'd255 && - _theResult___fst_sfd__h676659 == 23'd0, + _theResult___fst_exp__h676656 == 8'd255 && + _theResult___fst_sfd__h676657 == 23'd0, 1'd0, - _theResult___fst_exp__h676061 != 8'd255 && - guard__h667962 != 2'b0 } ; + _theResult___fst_exp__h676059 != 8'd255 && + guard__h667960 != 2'b0 } ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d8372 = ({ 3'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d8370 } ^ @@ -28922,15 +28917,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d9297 = { 3'd0, - _theResult___fst_exp__h584565 == 8'd0 && - (sfdin__h584559[56:34] == 23'd0 || guard__h576464 != 2'b0), + _theResult___fst_exp__h584563 == 8'd0 && + (sfdin__h584557[56:34] == 23'd0 || guard__h576462 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h585162 == 8'd255 && - _theResult___fst_sfd__h585163 == 23'd0, + _theResult___fst_exp__h585160 == 8'd255 && + _theResult___fst_sfd__h585161 == 23'd0, 1'd0, - _theResult___fst_exp__h584565 != 8'd255 && - guard__h576464 != 2'b0 } ; + _theResult___fst_exp__h584563 != 8'd255 && + guard__h576462 != 2'b0 } ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d9769 = ({ 3'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d9767 } ^ @@ -28953,37 +28948,37 @@ module mkCore(CLK, 12'd2048 ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14909 = { 3'd0, - _theResult___fst_exp__h743864 == 11'd0 && - (sfdin__h743858[56:5] == 52'd0 || guard__h735638 != 2'b0), + _theResult___fst_exp__h743861 == 11'd0 && + (sfdin__h743855[56:5] == 52'd0 || guard__h735635 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h744696 == 11'd2047 && - _theResult___fst_sfd__h744697 == 52'd0, + _theResult___fst_exp__h744693 == 11'd2047 && + _theResult___fst_sfd__h744694 == 52'd0, 1'd0, - _theResult___fst_exp__h743864 != 11'd2047 && - guard__h735638 != 2'b0 } ; + _theResult___fst_exp__h743861 != 11'd2047 && + guard__h735635 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14950 = { 3'd0, - _theResult___fst_exp__h782717 == 11'd0 && - (sfdin__h782711[56:5] == 52'd0 || guard__h774491 != 2'b0), + _theResult___fst_exp__h782714 == 11'd0 && + (sfdin__h782708[56:5] == 52'd0 || guard__h774488 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h783549 == 11'd2047 && - _theResult___fst_sfd__h783550 == 52'd0, + _theResult___fst_exp__h783546 == 11'd2047 && + _theResult___fst_sfd__h783547 == 52'd0, 1'd0, - _theResult___fst_exp__h782717 != 11'd2047 && - guard__h774491 != 2'b0 } ; + _theResult___fst_exp__h782714 != 11'd2047 && + guard__h774488 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14994 = { 3'd0, - _theResult___fst_exp__h822021 == 11'd0 && - (sfdin__h822015[56:5] == 52'd0 || guard__h813795 != 2'b0), + _theResult___fst_exp__h822018 == 11'd0 && + (sfdin__h822012[56:5] == 52'd0 || guard__h813792 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h822853 == 11'd2047 && - _theResult___fst_sfd__h822854 == 52'd0, + _theResult___fst_exp__h822850 == 11'd2047 && + _theResult___fst_sfd__h822851 == 52'd0, 1'd0, - _theResult___fst_exp__h822021 != 11'd2047 && - guard__h813795 != 2'b0 } ; + _theResult___fst_exp__h822018 != 11'd2047 && + guard__h813792 != 2'b0 } ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d10320 = ({ 3'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d10318 } ^ @@ -28991,15 +28986,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d10723 = { 3'd0, - _theResult___fst_exp__h648080 == 8'd0 && - (sfdin__h648074[56:34] == 23'd0 || guard__h639852 != 2'b0), + _theResult___fst_exp__h648078 == 8'd0 && + (sfdin__h648072[56:34] == 23'd0 || guard__h639850 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h648677 == 8'd255 && - _theResult___fst_sfd__h648678 == 23'd0, + _theResult___fst_exp__h648675 == 8'd255 && + _theResult___fst_sfd__h648676 == 23'd0, 1'd0, - _theResult___fst_exp__h648080 != 8'd255 && - guard__h639852 != 2'b0 } ; + _theResult___fst_exp__h648078 != 8'd255 && + guard__h639850 != 2'b0 } ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d11717 = ({ 3'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d11715 } ^ @@ -29007,15 +29002,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d12120 = { 3'd0, - _theResult___fst_exp__h693827 == 8'd0 && - (sfdin__h693821[56:34] == 23'd0 || guard__h685599 != 2'b0), + _theResult___fst_exp__h693825 == 8'd0 && + (sfdin__h693819[56:34] == 23'd0 || guard__h685597 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h694424 == 8'd255 && - _theResult___fst_sfd__h694425 == 23'd0, + _theResult___fst_exp__h694422 == 8'd255 && + _theResult___fst_sfd__h694423 == 23'd0, 1'd0, - _theResult___fst_exp__h693827 != 8'd255 && - guard__h685599 != 2'b0 } ; + _theResult___fst_exp__h693825 != 8'd255 && + guard__h685597 != 2'b0 } ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d8923 = ({ 3'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d8921 } ^ @@ -29023,15 +29018,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d9326 = { 3'd0, - _theResult___fst_exp__h602331 == 8'd0 && - (sfdin__h602325[56:34] == 23'd0 || guard__h594103 != 2'b0), + _theResult___fst_exp__h602329 == 8'd0 && + (sfdin__h602323[56:34] == 23'd0 || guard__h594101 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h602928 == 8'd255 && - _theResult___fst_sfd__h602929 == 23'd0, + _theResult___fst_exp__h602926 == 8'd255 && + _theResult___fst_sfd__h602927 == 23'd0, 1'd0, - _theResult___fst_exp__h602331 != 8'd255 && - guard__h594103 != 2'b0 } ; + _theResult___fst_exp__h602329 != 8'd255 && + guard__h594101 != 2'b0 } ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d12736 = ({ 6'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d12734 } ^ @@ -29067,37 +29062,37 @@ module mkCore(CLK, 12'h800) ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14892 = { 3'd0, - _theResult___fst_exp__h734287 == 11'd0 && - guard__h726326 != 2'b0, + _theResult___fst_exp__h734284 == 11'd0 && + guard__h726323 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h735045 == 11'd2047 && - _theResult___fst_sfd__h735046 == 52'd0, + _theResult___fst_exp__h735042 == 11'd2047 && + _theResult___fst_sfd__h735043 == 52'd0, 1'd0, - _theResult___fst_exp__h734287 != 11'd2047 && - guard__h726326 != 2'b0 } ; + _theResult___fst_exp__h734284 != 11'd2047 && + guard__h726323 != 2'b0 } ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14933 = { 3'd0, - _theResult___fst_exp__h773140 == 11'd0 && - guard__h765179 != 2'b0, + _theResult___fst_exp__h773137 == 11'd0 && + guard__h765176 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h773898 == 11'd2047 && - _theResult___fst_sfd__h773899 == 52'd0, + _theResult___fst_exp__h773895 == 11'd2047 && + _theResult___fst_sfd__h773896 == 52'd0, 1'd0, - _theResult___fst_exp__h773140 != 11'd2047 && - guard__h765179 != 2'b0 } ; + _theResult___fst_exp__h773137 != 11'd2047 && + guard__h765176 != 2'b0 } ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14977 = { 3'd0, - _theResult___fst_exp__h812444 == 11'd0 && - guard__h804483 != 2'b0, + _theResult___fst_exp__h812441 == 11'd0 && + guard__h804480 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h813202 == 11'd2047 && - _theResult___fst_sfd__h813203 == 52'd0, + _theResult___fst_exp__h813199 == 11'd2047 && + _theResult___fst_sfd__h813200 == 52'd0, 1'd0, - _theResult___fst_exp__h812444 != 11'd2047 && - guard__h804483 != 2'b0 } ; + _theResult___fst_exp__h812441 != 11'd2047 && + guard__h804480 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d10000 = ({ 3'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d9998 } ^ @@ -29111,15 +29106,15 @@ module mkCore(CLK, 9'h100) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d10706 = { 3'd0, - _theResult___fst_exp__h638970 == 8'd0 && - guard__h630922 != 2'b0, + _theResult___fst_exp__h638968 == 8'd0 && + guard__h630920 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h639493 == 8'd255 && - _theResult___fst_sfd__h639494 == 23'd0, + _theResult___fst_exp__h639491 == 8'd255 && + _theResult___fst_sfd__h639492 == 23'd0, 1'd0, - _theResult___fst_exp__h638970 != 8'd255 && - guard__h630922 != 2'b0 } ; + _theResult___fst_exp__h638968 != 8'd255 && + guard__h630920 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d11397 = ({ 3'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d11395 } ^ @@ -29133,15 +29128,15 @@ module mkCore(CLK, 9'h100) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d12103 = { 3'd0, - _theResult___fst_exp__h684717 == 8'd0 && - guard__h676669 != 2'b0, + _theResult___fst_exp__h684715 == 8'd0 && + guard__h676667 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h685240 == 8'd255 && - _theResult___fst_sfd__h685241 == 23'd0, + _theResult___fst_exp__h685238 == 8'd255 && + _theResult___fst_sfd__h685239 == 23'd0, 1'd0, - _theResult___fst_exp__h684717 != 8'd255 && - guard__h676669 != 2'b0 } ; + _theResult___fst_exp__h684715 != 8'd255 && + guard__h676667 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d8603 = ({ 3'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d8601 } ^ @@ -29155,15 +29150,15 @@ module mkCore(CLK, 9'h100) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d9309 = { 3'd0, - _theResult___fst_exp__h593221 == 8'd0 && - guard__h585173 != 2'b0, + _theResult___fst_exp__h593219 == 8'd0 && + guard__h585171 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h593744 == 8'd255 && - _theResult___fst_sfd__h593745 == 23'd0, + _theResult___fst_exp__h593742 == 8'd255 && + _theResult___fst_sfd__h593743 == 23'd0, 1'd0, - _theResult___fst_exp__h593221 != 8'd255 && - guard__h585173 != 2'b0 } ; + _theResult___fst_exp__h593219 != 8'd255 && + guard__h585171 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_memExe_dTlb_procResp__257__ETC___d4668 = { 2'd0, (coreFix_memExe_dTlb$procResp[277] && @@ -29183,18 +29178,18 @@ module mkCore(CLK, 1'd0, csrf_timer_int_en_vec_1 & csrf_timer_int_pend_vec_1, 1'd0 } ; - assign _0_CONCAT_csrf_mtcc_reg_read__6198_BITS_149_TO__ETC___d22832 = - x__h1000345[13:11] < repBound__h855069 ; - assign _0_CONCAT_csrf_mtcc_reg_read__6198_BITS_149_TO__ETC___d22857 = - x__h1000649[13:11] < repBound__h855069 ; - assign _0_CONCAT_csrf_stcc_reg_read__6046_BITS_149_TO__ETC___d22763 = - x__h999688[13:11] < repBound__h854076 ; - assign _0_CONCAT_csrf_stcc_reg_read__6046_BITS_149_TO__ETC___d22788 = - x__h999992[13:11] < repBound__h854076 ; + assign _0_CONCAT_csrf_mtcc_reg_read__6198_BITS_149_TO__ETC___d22834 = + x__h1000380[13:11] < repBound__h855068 ; + assign _0_CONCAT_csrf_mtcc_reg_read__6198_BITS_149_TO__ETC___d22859 = + x__h1000684[13:11] < repBound__h855068 ; + assign _0_CONCAT_csrf_stcc_reg_read__6046_BITS_149_TO__ETC___d22765 = + x__h999723[13:11] < repBound__h854075 ; + assign _0_CONCAT_csrf_stcc_reg_read__6046_BITS_149_TO__ETC___d22790 = + x__h1000027[13:11] < repBound__h854075 ; assign _0_OR_NOT_fetchStage_pipelines_0_first__0256_BI_ETC___d21841 = (fetchStage$pipelines_0_first[268:266] != 3'd1 || specTagManager$RDY_nextSpecTag) && - CASE_k45030_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q268 ; + CASE_k45028_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q268 ; assign _0_OR_NOT_fetchStage_pipelines_1_first__0265_BI_ETC___d21739 = (fetchStage$pipelines_1_first[268:266] != 3'd1 || !fetchStage$pipelines_0_canDeq || @@ -29208,37 +29203,37 @@ module mkCore(CLK, specTagManager$RDY_nextSpecTag) && CASE_fetchStage_pipelines_0_canDeq__0254_AND_N_ETC__q270 ; assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d12804 = - sfd__h715261 >> + sfd__h715258 >> _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d12800 ; assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d13519 = - sfd__h793559 >> + sfd__h793556 >> _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d13515 ; assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d14289 = - sfd__h754255 >> + sfd__h754252 >> _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d14285 ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d10078 = - sfd__h614603 >> + sfd__h614601 >> (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d10074[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d10074) ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d11475 = - sfd__h660350 >> + sfd__h660348 >> (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d11471[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d11471) ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d8681 = - sfd__h568849 >> + sfd__h568847 >> (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d8677[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d8677) ; assign _0b0_CONCAT_csrf_medeleg_28_26_reg_read__6161_6_ETC___d22642 = - medeleg_csr__read__h850223[i__h995336] ; - assign _0b0_CONCAT_csrf_mideleg_11_reg_read__6172_6173_ETC___d22644 = - mideleg_csr__read__h850321[i__h995510] ; - assign _18446744073709551615_SL_csrf_mtcc_reg_read__61_ETC___d22824 = - mask__h1000157 ^ y__h1000274 ; - assign _18446744073709551615_SL_csrf_stcc_reg_read__60_ETC___d22755 = - mask__h999500 ^ y__h999617 ; + medeleg_csr__read__h850222[i__h995334] ; + assign _0b0_CONCAT_csrf_mideleg_11_reg_read__6172_6173_ETC___d22645 = + mideleg_csr__read__h850320[i__h995534] ; + assign _18446744073709551615_SL_csrf_mtcc_reg_read__61_ETC___d22826 = + mask__h1000192 ^ y__h1000309 ; + assign _18446744073709551615_SL_csrf_stcc_reg_read__60_ETC___d22757 = + mask__h999535 ^ y__h999652 ; assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10709 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9532 && (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9533 ? @@ -29644,51 +29639,51 @@ module mkCore(CLK, assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12660 = 12'd3970 - { 7'd0, - f1_sfd__h714900[22] ? + f1_sfd__h714897[22] ? 5'd0 : - (f1_sfd__h714900[21] ? + (f1_sfd__h714897[21] ? 5'd1 : - (f1_sfd__h714900[20] ? + (f1_sfd__h714897[20] ? 5'd2 : - (f1_sfd__h714900[19] ? + (f1_sfd__h714897[19] ? 5'd3 : - (f1_sfd__h714900[18] ? + (f1_sfd__h714897[18] ? 5'd4 : - (f1_sfd__h714900[17] ? + (f1_sfd__h714897[17] ? 5'd5 : - (f1_sfd__h714900[16] ? + (f1_sfd__h714897[16] ? 5'd6 : - (f1_sfd__h714900[15] ? + (f1_sfd__h714897[15] ? 5'd7 : - (f1_sfd__h714900[14] ? + (f1_sfd__h714897[14] ? 5'd8 : - (f1_sfd__h714900[13] ? + (f1_sfd__h714897[13] ? 5'd9 : - (f1_sfd__h714900[12] ? + (f1_sfd__h714897[12] ? 5'd10 : - (f1_sfd__h714900[11] ? + (f1_sfd__h714897[11] ? 5'd11 : - (f1_sfd__h714900[10] ? + (f1_sfd__h714897[10] ? 5'd12 : - (f1_sfd__h714900[9] ? + (f1_sfd__h714897[9] ? 5'd13 : - (f1_sfd__h714900[8] ? + (f1_sfd__h714897[8] ? 5'd14 : - (f1_sfd__h714900[7] ? + (f1_sfd__h714897[7] ? 5'd15 : - (f1_sfd__h714900[6] ? + (f1_sfd__h714897[6] ? 5'd16 : - (f1_sfd__h714900[5] ? + (f1_sfd__h714897[5] ? 5'd17 : - (f1_sfd__h714900[4] ? + (f1_sfd__h714897[4] ? 5'd18 : - (f1_sfd__h714900[3] ? + (f1_sfd__h714897[3] ? 5'd19 : - (f1_sfd__h714900[2] ? + (f1_sfd__h714897[2] ? 5'd20 : - (f1_sfd__h714900[1] ? + (f1_sfd__h714897[1] ? 5'd21 : - (f1_sfd__h714900[0] ? + (f1_sfd__h714897[0] ? 5'd22 : 5'd23)))))))))))))))))))))) } ; assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12661 = @@ -29702,51 +29697,51 @@ module mkCore(CLK, assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13390 = 12'd3970 - { 7'd0, - f3_sfd__h793198[22] ? + f3_sfd__h793195[22] ? 5'd0 : - (f3_sfd__h793198[21] ? + (f3_sfd__h793195[21] ? 5'd1 : - (f3_sfd__h793198[20] ? + (f3_sfd__h793195[20] ? 5'd2 : - (f3_sfd__h793198[19] ? + (f3_sfd__h793195[19] ? 5'd3 : - (f3_sfd__h793198[18] ? + (f3_sfd__h793195[18] ? 5'd4 : - (f3_sfd__h793198[17] ? + (f3_sfd__h793195[17] ? 5'd5 : - (f3_sfd__h793198[16] ? + (f3_sfd__h793195[16] ? 5'd6 : - (f3_sfd__h793198[15] ? + (f3_sfd__h793195[15] ? 5'd7 : - (f3_sfd__h793198[14] ? + (f3_sfd__h793195[14] ? 5'd8 : - (f3_sfd__h793198[13] ? + (f3_sfd__h793195[13] ? 5'd9 : - (f3_sfd__h793198[12] ? + (f3_sfd__h793195[12] ? 5'd10 : - (f3_sfd__h793198[11] ? + (f3_sfd__h793195[11] ? 5'd11 : - (f3_sfd__h793198[10] ? + (f3_sfd__h793195[10] ? 5'd12 : - (f3_sfd__h793198[9] ? + (f3_sfd__h793195[9] ? 5'd13 : - (f3_sfd__h793198[8] ? + (f3_sfd__h793195[8] ? 5'd14 : - (f3_sfd__h793198[7] ? + (f3_sfd__h793195[7] ? 5'd15 : - (f3_sfd__h793198[6] ? + (f3_sfd__h793195[6] ? 5'd16 : - (f3_sfd__h793198[5] ? + (f3_sfd__h793195[5] ? 5'd17 : - (f3_sfd__h793198[4] ? + (f3_sfd__h793195[4] ? 5'd18 : - (f3_sfd__h793198[3] ? + (f3_sfd__h793195[3] ? 5'd19 : - (f3_sfd__h793198[2] ? + (f3_sfd__h793195[2] ? 5'd20 : - (f3_sfd__h793198[1] ? + (f3_sfd__h793195[1] ? 5'd21 : - (f3_sfd__h793198[0] ? + (f3_sfd__h793195[0] ? 5'd22 : 5'd23)))))))))))))))))))))) } ; assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13391 = @@ -29760,51 +29755,51 @@ module mkCore(CLK, assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14160 = 12'd3970 - { 7'd0, - f2_sfd__h753894[22] ? + f2_sfd__h753891[22] ? 5'd0 : - (f2_sfd__h753894[21] ? + (f2_sfd__h753891[21] ? 5'd1 : - (f2_sfd__h753894[20] ? + (f2_sfd__h753891[20] ? 5'd2 : - (f2_sfd__h753894[19] ? + (f2_sfd__h753891[19] ? 5'd3 : - (f2_sfd__h753894[18] ? + (f2_sfd__h753891[18] ? 5'd4 : - (f2_sfd__h753894[17] ? + (f2_sfd__h753891[17] ? 5'd5 : - (f2_sfd__h753894[16] ? + (f2_sfd__h753891[16] ? 5'd6 : - (f2_sfd__h753894[15] ? + (f2_sfd__h753891[15] ? 5'd7 : - (f2_sfd__h753894[14] ? + (f2_sfd__h753891[14] ? 5'd8 : - (f2_sfd__h753894[13] ? + (f2_sfd__h753891[13] ? 5'd9 : - (f2_sfd__h753894[12] ? + (f2_sfd__h753891[12] ? 5'd10 : - (f2_sfd__h753894[11] ? + (f2_sfd__h753891[11] ? 5'd11 : - (f2_sfd__h753894[10] ? + (f2_sfd__h753891[10] ? 5'd12 : - (f2_sfd__h753894[9] ? + (f2_sfd__h753891[9] ? 5'd13 : - (f2_sfd__h753894[8] ? + (f2_sfd__h753891[8] ? 5'd14 : - (f2_sfd__h753894[7] ? + (f2_sfd__h753891[7] ? 5'd15 : - (f2_sfd__h753894[6] ? + (f2_sfd__h753891[6] ? 5'd16 : - (f2_sfd__h753894[5] ? + (f2_sfd__h753891[5] ? 5'd17 : - (f2_sfd__h753894[4] ? + (f2_sfd__h753891[4] ? 5'd18 : - (f2_sfd__h753894[3] ? + (f2_sfd__h753891[3] ? 5'd19 : - (f2_sfd__h753894[2] ? + (f2_sfd__h753891[2] ? 5'd20 : - (f2_sfd__h753894[1] ? + (f2_sfd__h753891[1] ? 5'd21 : - (f2_sfd__h753894[0] ? + (f2_sfd__h753891[0] ? 5'd22 : 5'd23)))))))))))))))))))))) } ; assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14161 = @@ -29845,7 +29840,7 @@ module mkCore(CLK, fetchStage$pipelines_1_first[238:237] != 2'd1 && fetchStage_pipelines_1_first__0265_BITS_268_TO_ETC___d22174 ; assign _dfoo16 = - k__h945030 == 1'd1 && fetchStage$pipelines_0_canDeq && + k__h945028 == 1'd1 && fetchStage$pipelines_0_canDeq && NOT_fetchStage_pipelines_0_first__0256_BITS_26_ETC___d22015 || (fetchStage_pipelines_0_canDeq__0254_AND_NOT_fe_ETC___d22100 || NOT_fetchStage_pipelines_0_canDeq__0254_0255_O_ETC___d22113) == @@ -29853,7 +29848,7 @@ module mkCore(CLK, NOT_fetchStage_pipelines_0_canDeq__0254_0255_O_ETC___d22118 && NOT_fetchStage_pipelines_1_first__0265_BITS_26_ETC___d22130 ; assign _dfoo18 = - k__h945030 == 1'd0 && fetchStage$pipelines_0_canDeq && + k__h945028 == 1'd0 && fetchStage$pipelines_0_canDeq && NOT_fetchStage_pipelines_0_first__0256_BITS_26_ETC___d22015 || (fetchStage_pipelines_0_canDeq__0254_AND_NOT_fe_ETC___d22100 || NOT_fetchStage_pipelines_0_canDeq__0254_0255_O_ETC___d22113) == @@ -29876,48 +29871,48 @@ module mkCore(CLK, commitStage_commitTrap_2268_BITS_44_TO_43_2461_ETC___d22613 ; assign _dfoo24 = rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd42 || rob$deqPort_0_deq_data[469:465] == 5'd24 || rob$deqPort_0_deq_data[469:465] == 5'd25 ; assign _dfoo26 = rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd27 || rob$deqPort_0_deq_data[469:465] == 5'd18 && - IF_rob_deqPort_0_deq_data__2261_BIT_294_3454_T_ETC___d23476 == + IF_rob_deqPort_0_deq_data__2261_BIT_294_3456_T_ETC___d23478 == 4'd9 ; assign _dfoo28 = rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd24 || rob$deqPort_0_deq_data[469:465] == 5'd18 && - IF_rob_deqPort_0_deq_data__2261_BIT_294_3454_T_ETC___d23476 == + IF_rob_deqPort_0_deq_data__2261_BIT_294_3456_T_ETC___d23478 == 4'd6 ; assign _dfoo30 = rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd19 || rob$deqPort_0_deq_data[469:465] == 5'd25 ; assign _dfoo36 = rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd13 || rob$deqPort_0_deq_data[469:465] == 5'd18 && - IF_rob_deqPort_0_deq_data__2261_BIT_294_3454_T_ETC___d23476 == + IF_rob_deqPort_0_deq_data__2261_BIT_294_3456_T_ETC___d23478 == 4'd5 ; assign _dfoo38 = rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd10 || rob$deqPort_0_deq_data[469:465] == 5'd18 && - IF_rob_deqPort_0_deq_data__2261_BIT_294_3454_T_ETC___d23476 == + IF_rob_deqPort_0_deq_data__2261_BIT_294_3456_T_ETC___d23478 == 4'd2 ; assign _dfoo40 = rob$deqPort_0_deq_data[469:465] == 5'd17 && - (IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + (IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd8 || - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd19) || rob$deqPort_0_deq_data[469:465] == 5'd24 ; assign _dfoo7 = @@ -29988,1415 +29983,1415 @@ module mkCore(CLK, assign _dor1sbCons$EN_setReady_1_put = WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F || WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; - assign _theResult_____2__h515368 = + assign _theResult_____2__h515366 = IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d7240 ? - next_deqP___1__h515613 : + next_deqP___1__h515611 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP ; - assign _theResult_____2__h526145 = + assign _theResult_____2__h526143 = IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d7334 ? - next_deqP___1__h526390 : + next_deqP___1__h526388 : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP ; - assign _theResult_____2__h533238 = + assign _theResult_____2__h533236 = IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d7493 ? - next_deqP___1__h533668 : + next_deqP___1__h533666 : coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP ; - assign _theResult_____2__h543873 = + assign _theResult_____2__h543871 = IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d7577 ? - next_deqP___1__h544303 : + next_deqP___1__h544301 : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP ; - assign _theResult_____2__h557706 = + assign _theResult_____2__h557704 = IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d7782 ? - next_deqP___1__h557951 : + next_deqP___1__h557949 : coreFix_memExe_memRespLdQ_deqP ; - assign _theResult_____2__h561485 = + assign _theResult_____2__h561483 = IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d7864 ? - next_deqP___1__h561730 : + next_deqP___1__h561728 : coreFix_memExe_forwardQ_deqP ; - assign _theResult____h576454 = - (value__h577076 == 54'd0) ? sfd__h568849 : 57'd1 ; - assign _theResult____h594093 = + assign _theResult____h576452 = + (value__h577074 == 54'd0) ? sfd__h568847 : 57'd1 ; + assign _theResult____h594091 = ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d8677 ^ 12'h800) < 12'd2105) ? - result__h594706 : - _theResult____h576454 ; - assign _theResult____h622205 = - (value__h622825 == 54'd0) ? sfd__h614603 : 57'd1 ; - assign _theResult____h639842 = + result__h594704 : + _theResult____h576452 ; + assign _theResult____h622203 = + (value__h622823 == 54'd0) ? sfd__h614601 : 57'd1 ; + assign _theResult____h639840 = ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d10074 ^ 12'h800) < 12'd2105) ? - result__h640455 : - _theResult____h622205 ; - assign _theResult____h667952 = - (value__h668572 == 54'd0) ? sfd__h660350 : 57'd1 ; - assign _theResult____h685589 = + result__h640453 : + _theResult____h622203 ; + assign _theResult____h667950 = + (value__h668570 == 54'd0) ? sfd__h660348 : 57'd1 ; + assign _theResult____h685587 = ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d11471 ^ 12'h800) < 12'd2105) ? - result__h686202 : - _theResult____h667952 ; - assign _theResult____h735628 = + result__h686200 : + _theResult____h667950 ; + assign _theResult____h735625 = ((_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d12800 ^ 12'h800) < 12'd2105) ? - result__h736241 : - ((value__h719844 == 25'd0) ? sfd__h715261 : 57'd1) ; - assign _theResult____h774481 = + result__h736238 : + ((value__h719841 == 25'd0) ? sfd__h715258 : 57'd1) ; + assign _theResult____h774478 = ((_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d14285 ^ 12'h800) < 12'd2105) ? - result__h775094 : - ((value__h758697 == 25'd0) ? sfd__h754255 : 57'd1) ; - assign _theResult____h813785 = + result__h775091 : + ((value__h758694 == 25'd0) ? sfd__h754252 : 57'd1) ; + assign _theResult____h813782 = ((_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d13515 ^ 12'h800) < 12'd2105) ? - result__h814398 : - ((value__h798001 == 25'd0) ? sfd__h793559 : 57'd1) ; - assign _theResult____h920232 = + result__h814395 : + ((value__h797998 == 25'd0) ? sfd__h793556 : 57'd1) ; + assign _theResult____h920230 = (csrf_prv_reg != 2'd3 || csrf_ie_vec_3) ? - enabled_ints___1__h920757 : + enabled_ints___1__h920755 : 16'd0 ; - assign _theResult___exp__h585081 = - sfd__h584657[24] ? - ((_theResult___fst_exp__h584565 == 8'd254) ? + assign _theResult___exp__h585079 = + sfd__h584655[24] ? + ((_theResult___fst_exp__h584563 == 8'd254) ? 8'd255 : - din_inc___2_exp__h611598) : - ((_theResult___fst_exp__h584565 == 8'd0 && - sfd__h584657[24:23] == 2'b01) ? + din_inc___2_exp__h611596) : + ((_theResult___fst_exp__h584563 == 8'd0 && + sfd__h584655[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h584565) ; - assign _theResult___exp__h593663 = - sfd__h593239[24] ? - ((_theResult___fst_exp__h593221 == 8'd254) ? + _theResult___fst_exp__h584563) ; + assign _theResult___exp__h593661 = + sfd__h593237[24] ? + ((_theResult___fst_exp__h593219 == 8'd254) ? 8'd255 : - din_inc___2_exp__h611622) : - ((_theResult___fst_exp__h593221 == 8'd0 && - sfd__h593239[24:23] == 2'b01) ? + din_inc___2_exp__h611620) : + ((_theResult___fst_exp__h593219 == 8'd0 && + sfd__h593237[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h593221) ; - assign _theResult___exp__h602847 = - sfd__h602423[24] ? - ((_theResult___fst_exp__h602331 == 8'd254) ? + _theResult___fst_exp__h593219) ; + assign _theResult___exp__h602845 = + sfd__h602421[24] ? + ((_theResult___fst_exp__h602329 == 8'd254) ? 8'd255 : - din_inc___2_exp__h611652) : - ((_theResult___fst_exp__h602331 == 8'd0 && - sfd__h602423[24:23] == 2'b01) ? + din_inc___2_exp__h611650) : + ((_theResult___fst_exp__h602329 == 8'd0 && + sfd__h602421[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h602331) ; - assign _theResult___exp__h611483 = - sfd__h611035[24] ? - ((_theResult___fst_exp__h611016 == 8'd254) ? + _theResult___fst_exp__h602329) ; + assign _theResult___exp__h611481 = + sfd__h611033[24] ? + ((_theResult___fst_exp__h611014 == 8'd254) ? 8'd255 : - din_inc___2_exp__h611676) : - ((_theResult___fst_exp__h611016 == 8'd0 && - sfd__h611035[24:23] == 2'b01) ? + din_inc___2_exp__h611674) : + ((_theResult___fst_exp__h611014 == 8'd0 && + sfd__h611033[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h611016) ; - assign _theResult___exp__h611585 = + _theResult___fst_exp__h611014) ; + assign _theResult___exp__h611583 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h611576 ; - assign _theResult___exp__h630830 = - sfd__h630406[24] ? - ((_theResult___fst_exp__h630314 == 8'd254) ? + _theResult___fst_exp__h611574 ; + assign _theResult___exp__h630828 = + sfd__h630404[24] ? + ((_theResult___fst_exp__h630312 == 8'd254) ? 8'd255 : - din_inc___2_exp__h657347) : - ((_theResult___fst_exp__h630314 == 8'd0 && - sfd__h630406[24:23] == 2'b01) ? + din_inc___2_exp__h657345) : + ((_theResult___fst_exp__h630312 == 8'd0 && + sfd__h630404[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h630314) ; - assign _theResult___exp__h639412 = - sfd__h638988[24] ? - ((_theResult___fst_exp__h638970 == 8'd254) ? + _theResult___fst_exp__h630312) ; + assign _theResult___exp__h639410 = + sfd__h638986[24] ? + ((_theResult___fst_exp__h638968 == 8'd254) ? 8'd255 : - din_inc___2_exp__h657371) : - ((_theResult___fst_exp__h638970 == 8'd0 && - sfd__h638988[24:23] == 2'b01) ? + din_inc___2_exp__h657369) : + ((_theResult___fst_exp__h638968 == 8'd0 && + sfd__h638986[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h638970) ; - assign _theResult___exp__h648596 = - sfd__h648172[24] ? - ((_theResult___fst_exp__h648080 == 8'd254) ? + _theResult___fst_exp__h638968) ; + assign _theResult___exp__h648594 = + sfd__h648170[24] ? + ((_theResult___fst_exp__h648078 == 8'd254) ? 8'd255 : - din_inc___2_exp__h657401) : - ((_theResult___fst_exp__h648080 == 8'd0 && - sfd__h648172[24:23] == 2'b01) ? + din_inc___2_exp__h657399) : + ((_theResult___fst_exp__h648078 == 8'd0 && + sfd__h648170[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h648080) ; - assign _theResult___exp__h657232 = - sfd__h656784[24] ? - ((_theResult___fst_exp__h656765 == 8'd254) ? + _theResult___fst_exp__h648078) ; + assign _theResult___exp__h657230 = + sfd__h656782[24] ? + ((_theResult___fst_exp__h656763 == 8'd254) ? 8'd255 : - din_inc___2_exp__h657425) : - ((_theResult___fst_exp__h656765 == 8'd0 && - sfd__h656784[24:23] == 2'b01) ? + din_inc___2_exp__h657423) : + ((_theResult___fst_exp__h656763 == 8'd0 && + sfd__h656782[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h656765) ; - assign _theResult___exp__h657334 = + _theResult___fst_exp__h656763) ; + assign _theResult___exp__h657332 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h657325 ; - assign _theResult___exp__h676577 = - sfd__h676153[24] ? - ((_theResult___fst_exp__h676061 == 8'd254) ? + _theResult___fst_exp__h657323 ; + assign _theResult___exp__h676575 = + sfd__h676151[24] ? + ((_theResult___fst_exp__h676059 == 8'd254) ? 8'd255 : - din_inc___2_exp__h703094) : - ((_theResult___fst_exp__h676061 == 8'd0 && - sfd__h676153[24:23] == 2'b01) ? + din_inc___2_exp__h703092) : + ((_theResult___fst_exp__h676059 == 8'd0 && + sfd__h676151[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h676061) ; - assign _theResult___exp__h685159 = - sfd__h684735[24] ? - ((_theResult___fst_exp__h684717 == 8'd254) ? + _theResult___fst_exp__h676059) ; + assign _theResult___exp__h685157 = + sfd__h684733[24] ? + ((_theResult___fst_exp__h684715 == 8'd254) ? 8'd255 : - din_inc___2_exp__h703118) : - ((_theResult___fst_exp__h684717 == 8'd0 && - sfd__h684735[24:23] == 2'b01) ? + din_inc___2_exp__h703116) : + ((_theResult___fst_exp__h684715 == 8'd0 && + sfd__h684733[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h684717) ; - assign _theResult___exp__h694343 = - sfd__h693919[24] ? - ((_theResult___fst_exp__h693827 == 8'd254) ? + _theResult___fst_exp__h684715) ; + assign _theResult___exp__h694341 = + sfd__h693917[24] ? + ((_theResult___fst_exp__h693825 == 8'd254) ? 8'd255 : - din_inc___2_exp__h703148) : - ((_theResult___fst_exp__h693827 == 8'd0 && - sfd__h693919[24:23] == 2'b01) ? + din_inc___2_exp__h703146) : + ((_theResult___fst_exp__h693825 == 8'd0 && + sfd__h693917[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h693827) ; - assign _theResult___exp__h702979 = - sfd__h702531[24] ? - ((_theResult___fst_exp__h702512 == 8'd254) ? + _theResult___fst_exp__h693825) ; + assign _theResult___exp__h702977 = + sfd__h702529[24] ? + ((_theResult___fst_exp__h702510 == 8'd254) ? 8'd255 : - din_inc___2_exp__h703172) : - ((_theResult___fst_exp__h702512 == 8'd0 && - sfd__h702531[24:23] == 2'b01) ? + din_inc___2_exp__h703170) : + ((_theResult___fst_exp__h702510 == 8'd0 && + sfd__h702529[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h702512) ; - assign _theResult___exp__h703081 = + _theResult___fst_exp__h702510) ; + assign _theResult___exp__h703079 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h703072 ; - assign _theResult___exp__h734942 = - sfd__h734305[53] ? - ((_theResult___fst_exp__h734287 == 11'd2046) ? + _theResult___fst_exp__h703070 ; + assign _theResult___exp__h734939 = + sfd__h734302[53] ? + ((_theResult___fst_exp__h734284 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h753537) : - ((_theResult___fst_exp__h734287 == 11'd0 && - sfd__h734305[53:52] == 2'b01) ? + din_inc___2_exp__h753534) : + ((_theResult___fst_exp__h734284 == 11'd0 && + sfd__h734302[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h734287) ; - assign _theResult___exp__h744593 = - sfd__h743956[53] ? - ((_theResult___fst_exp__h743864 == 11'd2046) ? + _theResult___fst_exp__h734284) ; + assign _theResult___exp__h744590 = + sfd__h743953[53] ? + ((_theResult___fst_exp__h743861 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h753572) : - ((_theResult___fst_exp__h743864 == 11'd0 && - sfd__h743956[53:52] == 2'b01) ? + din_inc___2_exp__h753569) : + ((_theResult___fst_exp__h743861 == 11'd0 && + sfd__h743953[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h743864) ; - assign _theResult___exp__h753377 = - sfd__h752716[53] ? - ((_theResult___fst_exp__h752697 == 11'd2046) ? + _theResult___fst_exp__h743861) ; + assign _theResult___exp__h753374 = + sfd__h752713[53] ? + ((_theResult___fst_exp__h752694 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h753598) : - ((_theResult___fst_exp__h752697 == 11'd0 && - sfd__h752716[53:52] == 2'b01) ? + din_inc___2_exp__h753595) : + ((_theResult___fst_exp__h752694 == 11'd0 && + sfd__h752713[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h752697) ; - assign _theResult___exp__h773795 = - sfd__h773158[53] ? - ((_theResult___fst_exp__h773140 == 11'd2046) ? + _theResult___fst_exp__h752694) ; + assign _theResult___exp__h773792 = + sfd__h773155[53] ? + ((_theResult___fst_exp__h773137 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h792390) : - ((_theResult___fst_exp__h773140 == 11'd0 && - sfd__h773158[53:52] == 2'b01) ? + din_inc___2_exp__h792387) : + ((_theResult___fst_exp__h773137 == 11'd0 && + sfd__h773155[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h773140) ; - assign _theResult___exp__h783446 = - sfd__h782809[53] ? - ((_theResult___fst_exp__h782717 == 11'd2046) ? + _theResult___fst_exp__h773137) ; + assign _theResult___exp__h783443 = + sfd__h782806[53] ? + ((_theResult___fst_exp__h782714 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h792425) : - ((_theResult___fst_exp__h782717 == 11'd0 && - sfd__h782809[53:52] == 2'b01) ? + din_inc___2_exp__h792422) : + ((_theResult___fst_exp__h782714 == 11'd0 && + sfd__h782806[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h782717) ; - assign _theResult___exp__h792230 = - sfd__h791569[53] ? - ((_theResult___fst_exp__h791550 == 11'd2046) ? + _theResult___fst_exp__h782714) ; + assign _theResult___exp__h792227 = + sfd__h791566[53] ? + ((_theResult___fst_exp__h791547 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h792451) : - ((_theResult___fst_exp__h791550 == 11'd0 && - sfd__h791569[53:52] == 2'b01) ? + din_inc___2_exp__h792448) : + ((_theResult___fst_exp__h791547 == 11'd0 && + sfd__h791566[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h791550) ; - assign _theResult___exp__h813099 = - sfd__h812462[53] ? - ((_theResult___fst_exp__h812444 == 11'd2046) ? + _theResult___fst_exp__h791547) ; + assign _theResult___exp__h813096 = + sfd__h812459[53] ? + ((_theResult___fst_exp__h812441 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h831694) : - ((_theResult___fst_exp__h812444 == 11'd0 && - sfd__h812462[53:52] == 2'b01) ? + din_inc___2_exp__h831691) : + ((_theResult___fst_exp__h812441 == 11'd0 && + sfd__h812459[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h812444) ; - assign _theResult___exp__h822750 = - sfd__h822113[53] ? - ((_theResult___fst_exp__h822021 == 11'd2046) ? + _theResult___fst_exp__h812441) ; + assign _theResult___exp__h822747 = + sfd__h822110[53] ? + ((_theResult___fst_exp__h822018 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h831729) : - ((_theResult___fst_exp__h822021 == 11'd0 && - sfd__h822113[53:52] == 2'b01) ? + din_inc___2_exp__h831726) : + ((_theResult___fst_exp__h822018 == 11'd0 && + sfd__h822110[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h822021) ; - assign _theResult___exp__h831534 = - sfd__h830873[53] ? - ((_theResult___fst_exp__h830854 == 11'd2046) ? + _theResult___fst_exp__h822018) ; + assign _theResult___exp__h831531 = + sfd__h830870[53] ? + ((_theResult___fst_exp__h830851 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h831755) : - ((_theResult___fst_exp__h830854 == 11'd0 && - sfd__h830873[53:52] == 2'b01) ? + din_inc___2_exp__h831752) : + ((_theResult___fst_exp__h830851 == 11'd0 && + sfd__h830870[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h830854) ; - assign _theResult___fst__h836129 = - a__h835707[63] ? a___1__h836134 : a__h835707 ; - assign _theResult___fst_exp__h584565 = - _theResult____h576454[56] ? + _theResult___fst_exp__h830851) ; + assign _theResult___fst__h836126 = + a__h835704[63] ? a___1__h836131 : a__h835704 ; + assign _theResult___fst_exp__h584563 = + _theResult____h576452[56] ? 8'd2 : - _theResult___fst_exp__h584639 ; - assign _theResult___fst_exp__h584630 = + _theResult___fst_exp__h584637 ; + assign _theResult___fst_exp__h584628 = 8'd0 - { 2'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d8370 } ; - assign _theResult___fst_exp__h584636 = - (!_theResult____h576454[56] && !_theResult____h576454[55] && - !_theResult____h576454[54] && - !_theResult____h576454[53] && - !_theResult____h576454[52] && - !_theResult____h576454[51] && - !_theResult____h576454[50] && - !_theResult____h576454[49] && - !_theResult____h576454[48] && - !_theResult____h576454[47] && - !_theResult____h576454[46] && - !_theResult____h576454[45] && - !_theResult____h576454[44] && - !_theResult____h576454[43] && - !_theResult____h576454[42] && - !_theResult____h576454[41] && - !_theResult____h576454[40] && - !_theResult____h576454[39] && - !_theResult____h576454[38] && - !_theResult____h576454[37] && - !_theResult____h576454[36] && - !_theResult____h576454[35] && - !_theResult____h576454[34] && - !_theResult____h576454[33] && - !_theResult____h576454[32] && - !_theResult____h576454[31] && - !_theResult____h576454[30] && - !_theResult____h576454[29] && - !_theResult____h576454[28] && - !_theResult____h576454[27] && - !_theResult____h576454[26] && - !_theResult____h576454[25] && - !_theResult____h576454[24] && - !_theResult____h576454[23] && - !_theResult____h576454[22] && - !_theResult____h576454[21] && - !_theResult____h576454[20] && - !_theResult____h576454[19] && - !_theResult____h576454[18] && - !_theResult____h576454[17] && - !_theResult____h576454[16] && - !_theResult____h576454[15] && - !_theResult____h576454[14] && - !_theResult____h576454[13] && - !_theResult____h576454[12] && - !_theResult____h576454[11] && - !_theResult____h576454[10] && - !_theResult____h576454[9] && - !_theResult____h576454[8] && - !_theResult____h576454[7] && - !_theResult____h576454[6] && - !_theResult____h576454[5] && - !_theResult____h576454[4] && - !_theResult____h576454[3] && - !_theResult____h576454[2] && - !_theResult____h576454[1] && - !_theResult____h576454[0] || + assign _theResult___fst_exp__h584634 = + (!_theResult____h576452[56] && !_theResult____h576452[55] && + !_theResult____h576452[54] && + !_theResult____h576452[53] && + !_theResult____h576452[52] && + !_theResult____h576452[51] && + !_theResult____h576452[50] && + !_theResult____h576452[49] && + !_theResult____h576452[48] && + !_theResult____h576452[47] && + !_theResult____h576452[46] && + !_theResult____h576452[45] && + !_theResult____h576452[44] && + !_theResult____h576452[43] && + !_theResult____h576452[42] && + !_theResult____h576452[41] && + !_theResult____h576452[40] && + !_theResult____h576452[39] && + !_theResult____h576452[38] && + !_theResult____h576452[37] && + !_theResult____h576452[36] && + !_theResult____h576452[35] && + !_theResult____h576452[34] && + !_theResult____h576452[33] && + !_theResult____h576452[32] && + !_theResult____h576452[31] && + !_theResult____h576452[30] && + !_theResult____h576452[29] && + !_theResult____h576452[28] && + !_theResult____h576452[27] && + !_theResult____h576452[26] && + !_theResult____h576452[25] && + !_theResult____h576452[24] && + !_theResult____h576452[23] && + !_theResult____h576452[22] && + !_theResult____h576452[21] && + !_theResult____h576452[20] && + !_theResult____h576452[19] && + !_theResult____h576452[18] && + !_theResult____h576452[17] && + !_theResult____h576452[16] && + !_theResult____h576452[15] && + !_theResult____h576452[14] && + !_theResult____h576452[13] && + !_theResult____h576452[12] && + !_theResult____h576452[11] && + !_theResult____h576452[10] && + !_theResult____h576452[9] && + !_theResult____h576452[8] && + !_theResult____h576452[7] && + !_theResult____h576452[6] && + !_theResult____h576452[5] && + !_theResult____h576452[4] && + !_theResult____h576452[3] && + !_theResult____h576452[2] && + !_theResult____h576452[1] && + !_theResult____h576452[0] || !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d8372) ? 8'd0 : - _theResult___fst_exp__h584630 ; - assign _theResult___fst_exp__h584639 = - (!_theResult____h576454[56] && _theResult____h576454[55]) ? + _theResult___fst_exp__h584628 ; + assign _theResult___fst_exp__h584637 = + (!_theResult____h576452[56] && _theResult____h576452[55]) ? 8'd1 : - _theResult___fst_exp__h584636 ; - assign _theResult___fst_exp__h585162 = - (_theResult___fst_exp__h584565 == 8'd255) ? - _theResult___fst_exp__h584565 : - _theResult___fst_exp__h585159 ; - assign _theResult___fst_exp__h593212 = + _theResult___fst_exp__h584634 ; + assign _theResult___fst_exp__h585160 = + (_theResult___fst_exp__h584563 == 8'd255) ? + _theResult___fst_exp__h584563 : + _theResult___fst_exp__h585157 ; + assign _theResult___fst_exp__h593210 = 8'd129 - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d8601 } ; - assign _theResult___fst_exp__h593218 = + assign _theResult___fst_exp__h593216 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d8546 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d8603) ? 8'd0 : - _theResult___fst_exp__h593212 ; - assign _theResult___fst_exp__h593221 = + _theResult___fst_exp__h593210 ; + assign _theResult___fst_exp__h593219 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h593218 : + _theResult___fst_exp__h593216 : 8'd129 ; - assign _theResult___fst_exp__h593744 = - (_theResult___fst_exp__h593221 == 8'd255) ? - _theResult___fst_exp__h593221 : - _theResult___fst_exp__h593741 ; - assign _theResult___fst_exp__h602331 = - _theResult____h594093[56] ? + assign _theResult___fst_exp__h593742 = + (_theResult___fst_exp__h593219 == 8'd255) ? + _theResult___fst_exp__h593219 : + _theResult___fst_exp__h593739 ; + assign _theResult___fst_exp__h602329 = + _theResult____h594091[56] ? 8'd2 : - _theResult___fst_exp__h602405 ; - assign _theResult___fst_exp__h602396 = + _theResult___fst_exp__h602403 ; + assign _theResult___fst_exp__h602394 = 8'd0 - { 2'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d8921 } ; - assign _theResult___fst_exp__h602402 = - (!_theResult____h594093[56] && !_theResult____h594093[55] && - !_theResult____h594093[54] && - !_theResult____h594093[53] && - !_theResult____h594093[52] && - !_theResult____h594093[51] && - !_theResult____h594093[50] && - !_theResult____h594093[49] && - !_theResult____h594093[48] && - !_theResult____h594093[47] && - !_theResult____h594093[46] && - !_theResult____h594093[45] && - !_theResult____h594093[44] && - !_theResult____h594093[43] && - !_theResult____h594093[42] && - !_theResult____h594093[41] && - !_theResult____h594093[40] && - !_theResult____h594093[39] && - !_theResult____h594093[38] && - !_theResult____h594093[37] && - !_theResult____h594093[36] && - !_theResult____h594093[35] && - !_theResult____h594093[34] && - !_theResult____h594093[33] && - !_theResult____h594093[32] && - !_theResult____h594093[31] && - !_theResult____h594093[30] && - !_theResult____h594093[29] && - !_theResult____h594093[28] && - !_theResult____h594093[27] && - !_theResult____h594093[26] && - !_theResult____h594093[25] && - !_theResult____h594093[24] && - !_theResult____h594093[23] && - !_theResult____h594093[22] && - !_theResult____h594093[21] && - !_theResult____h594093[20] && - !_theResult____h594093[19] && - !_theResult____h594093[18] && - !_theResult____h594093[17] && - !_theResult____h594093[16] && - !_theResult____h594093[15] && - !_theResult____h594093[14] && - !_theResult____h594093[13] && - !_theResult____h594093[12] && - !_theResult____h594093[11] && - !_theResult____h594093[10] && - !_theResult____h594093[9] && - !_theResult____h594093[8] && - !_theResult____h594093[7] && - !_theResult____h594093[6] && - !_theResult____h594093[5] && - !_theResult____h594093[4] && - !_theResult____h594093[3] && - !_theResult____h594093[2] && - !_theResult____h594093[1] && - !_theResult____h594093[0] || + assign _theResult___fst_exp__h602400 = + (!_theResult____h594091[56] && !_theResult____h594091[55] && + !_theResult____h594091[54] && + !_theResult____h594091[53] && + !_theResult____h594091[52] && + !_theResult____h594091[51] && + !_theResult____h594091[50] && + !_theResult____h594091[49] && + !_theResult____h594091[48] && + !_theResult____h594091[47] && + !_theResult____h594091[46] && + !_theResult____h594091[45] && + !_theResult____h594091[44] && + !_theResult____h594091[43] && + !_theResult____h594091[42] && + !_theResult____h594091[41] && + !_theResult____h594091[40] && + !_theResult____h594091[39] && + !_theResult____h594091[38] && + !_theResult____h594091[37] && + !_theResult____h594091[36] && + !_theResult____h594091[35] && + !_theResult____h594091[34] && + !_theResult____h594091[33] && + !_theResult____h594091[32] && + !_theResult____h594091[31] && + !_theResult____h594091[30] && + !_theResult____h594091[29] && + !_theResult____h594091[28] && + !_theResult____h594091[27] && + !_theResult____h594091[26] && + !_theResult____h594091[25] && + !_theResult____h594091[24] && + !_theResult____h594091[23] && + !_theResult____h594091[22] && + !_theResult____h594091[21] && + !_theResult____h594091[20] && + !_theResult____h594091[19] && + !_theResult____h594091[18] && + !_theResult____h594091[17] && + !_theResult____h594091[16] && + !_theResult____h594091[15] && + !_theResult____h594091[14] && + !_theResult____h594091[13] && + !_theResult____h594091[12] && + !_theResult____h594091[11] && + !_theResult____h594091[10] && + !_theResult____h594091[9] && + !_theResult____h594091[8] && + !_theResult____h594091[7] && + !_theResult____h594091[6] && + !_theResult____h594091[5] && + !_theResult____h594091[4] && + !_theResult____h594091[3] && + !_theResult____h594091[2] && + !_theResult____h594091[1] && + !_theResult____h594091[0] || !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d8923) ? 8'd0 : - _theResult___fst_exp__h602396 ; - assign _theResult___fst_exp__h602405 = - (!_theResult____h594093[56] && _theResult____h594093[55]) ? + _theResult___fst_exp__h602394 ; + assign _theResult___fst_exp__h602403 = + (!_theResult____h594091[56] && _theResult____h594091[55]) ? 8'd1 : - _theResult___fst_exp__h602402 ; - assign _theResult___fst_exp__h602928 = - (_theResult___fst_exp__h602331 == 8'd255) ? - _theResult___fst_exp__h602331 : - _theResult___fst_exp__h602925 ; - assign _theResult___fst_exp__h610968 = + _theResult___fst_exp__h602400 ; + assign _theResult___fst_exp__h602926 = + (_theResult___fst_exp__h602329 == 8'd255) ? + _theResult___fst_exp__h602329 : + _theResult___fst_exp__h602923 ; + assign _theResult___fst_exp__h610966 = (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q49[7:0] == 8'd0) ? 8'd1 : SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q49[7:0] ; - assign _theResult___fst_exp__h611007 = + assign _theResult___fst_exp__h611005 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q49[7:0] - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d8601 } ; - assign _theResult___fst_exp__h611013 = + assign _theResult___fst_exp__h611011 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d8546 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d8996) ? 8'd0 : - _theResult___fst_exp__h611007 ; - assign _theResult___fst_exp__h611016 = + _theResult___fst_exp__h611005 ; + assign _theResult___fst_exp__h611014 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h611013 : - _theResult___fst_exp__h610968 ; - assign _theResult___fst_exp__h611564 = - (_theResult___fst_exp__h611016 == 8'd255) ? - _theResult___fst_exp__h611016 : - _theResult___fst_exp__h611561 ; - assign _theResult___fst_exp__h611573 = + _theResult___fst_exp__h611011 : + _theResult___fst_exp__h610966 ; + assign _theResult___fst_exp__h611562 = + (_theResult___fst_exp__h611014 == 8'd255) ? + _theResult___fst_exp__h611014 : + _theResult___fst_exp__h611559 ; + assign _theResult___fst_exp__h611571 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8135 ? - _theResult___snd_fst_exp__h593747 : - _theResult___fst_exp__h576436) : + _theResult___snd_fst_exp__h593745 : + _theResult___fst_exp__h576434) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8675 ? - _theResult___snd_fst_exp__h611567 : - _theResult___fst_exp__h576436) ; - assign _theResult___fst_exp__h611576 = + _theResult___snd_fst_exp__h611565 : + _theResult___fst_exp__h576434) ; + assign _theResult___fst_exp__h611574 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == 52'd0) ? 8'd0 : - _theResult___fst_exp__h611573 ; - assign _theResult___fst_exp__h630314 = - _theResult____h622205[56] ? + _theResult___fst_exp__h611571 ; + assign _theResult___fst_exp__h630312 = + _theResult____h622203[56] ? 8'd2 : - _theResult___fst_exp__h630388 ; - assign _theResult___fst_exp__h630379 = + _theResult___fst_exp__h630386 ; + assign _theResult___fst_exp__h630377 = 8'd0 - { 2'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d9767 } ; - assign _theResult___fst_exp__h630385 = - (!_theResult____h622205[56] && !_theResult____h622205[55] && - !_theResult____h622205[54] && - !_theResult____h622205[53] && - !_theResult____h622205[52] && - !_theResult____h622205[51] && - !_theResult____h622205[50] && - !_theResult____h622205[49] && - !_theResult____h622205[48] && - !_theResult____h622205[47] && - !_theResult____h622205[46] && - !_theResult____h622205[45] && - !_theResult____h622205[44] && - !_theResult____h622205[43] && - !_theResult____h622205[42] && - !_theResult____h622205[41] && - !_theResult____h622205[40] && - !_theResult____h622205[39] && - !_theResult____h622205[38] && - !_theResult____h622205[37] && - !_theResult____h622205[36] && - !_theResult____h622205[35] && - !_theResult____h622205[34] && - !_theResult____h622205[33] && - !_theResult____h622205[32] && - !_theResult____h622205[31] && - !_theResult____h622205[30] && - !_theResult____h622205[29] && - !_theResult____h622205[28] && - !_theResult____h622205[27] && - !_theResult____h622205[26] && - !_theResult____h622205[25] && - !_theResult____h622205[24] && - !_theResult____h622205[23] && - !_theResult____h622205[22] && - !_theResult____h622205[21] && - !_theResult____h622205[20] && - !_theResult____h622205[19] && - !_theResult____h622205[18] && - !_theResult____h622205[17] && - !_theResult____h622205[16] && - !_theResult____h622205[15] && - !_theResult____h622205[14] && - !_theResult____h622205[13] && - !_theResult____h622205[12] && - !_theResult____h622205[11] && - !_theResult____h622205[10] && - !_theResult____h622205[9] && - !_theResult____h622205[8] && - !_theResult____h622205[7] && - !_theResult____h622205[6] && - !_theResult____h622205[5] && - !_theResult____h622205[4] && - !_theResult____h622205[3] && - !_theResult____h622205[2] && - !_theResult____h622205[1] && - !_theResult____h622205[0] || + assign _theResult___fst_exp__h630383 = + (!_theResult____h622203[56] && !_theResult____h622203[55] && + !_theResult____h622203[54] && + !_theResult____h622203[53] && + !_theResult____h622203[52] && + !_theResult____h622203[51] && + !_theResult____h622203[50] && + !_theResult____h622203[49] && + !_theResult____h622203[48] && + !_theResult____h622203[47] && + !_theResult____h622203[46] && + !_theResult____h622203[45] && + !_theResult____h622203[44] && + !_theResult____h622203[43] && + !_theResult____h622203[42] && + !_theResult____h622203[41] && + !_theResult____h622203[40] && + !_theResult____h622203[39] && + !_theResult____h622203[38] && + !_theResult____h622203[37] && + !_theResult____h622203[36] && + !_theResult____h622203[35] && + !_theResult____h622203[34] && + !_theResult____h622203[33] && + !_theResult____h622203[32] && + !_theResult____h622203[31] && + !_theResult____h622203[30] && + !_theResult____h622203[29] && + !_theResult____h622203[28] && + !_theResult____h622203[27] && + !_theResult____h622203[26] && + !_theResult____h622203[25] && + !_theResult____h622203[24] && + !_theResult____h622203[23] && + !_theResult____h622203[22] && + !_theResult____h622203[21] && + !_theResult____h622203[20] && + !_theResult____h622203[19] && + !_theResult____h622203[18] && + !_theResult____h622203[17] && + !_theResult____h622203[16] && + !_theResult____h622203[15] && + !_theResult____h622203[14] && + !_theResult____h622203[13] && + !_theResult____h622203[12] && + !_theResult____h622203[11] && + !_theResult____h622203[10] && + !_theResult____h622203[9] && + !_theResult____h622203[8] && + !_theResult____h622203[7] && + !_theResult____h622203[6] && + !_theResult____h622203[5] && + !_theResult____h622203[4] && + !_theResult____h622203[3] && + !_theResult____h622203[2] && + !_theResult____h622203[1] && + !_theResult____h622203[0] || !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d9769) ? 8'd0 : - _theResult___fst_exp__h630379 ; - assign _theResult___fst_exp__h630388 = - (!_theResult____h622205[56] && _theResult____h622205[55]) ? + _theResult___fst_exp__h630377 ; + assign _theResult___fst_exp__h630386 = + (!_theResult____h622203[56] && _theResult____h622203[55]) ? 8'd1 : - _theResult___fst_exp__h630385 ; - assign _theResult___fst_exp__h630911 = - (_theResult___fst_exp__h630314 == 8'd255) ? - _theResult___fst_exp__h630314 : - _theResult___fst_exp__h630908 ; - assign _theResult___fst_exp__h638961 = + _theResult___fst_exp__h630383 ; + assign _theResult___fst_exp__h630909 = + (_theResult___fst_exp__h630312 == 8'd255) ? + _theResult___fst_exp__h630312 : + _theResult___fst_exp__h630906 ; + assign _theResult___fst_exp__h638959 = 8'd129 - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d9998 } ; - assign _theResult___fst_exp__h638967 = + assign _theResult___fst_exp__h638965 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d9943 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d10000) ? 8'd0 : - _theResult___fst_exp__h638961 ; - assign _theResult___fst_exp__h638970 = + _theResult___fst_exp__h638959 ; + assign _theResult___fst_exp__h638968 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h638967 : + _theResult___fst_exp__h638965 : 8'd129 ; - assign _theResult___fst_exp__h639493 = - (_theResult___fst_exp__h638970 == 8'd255) ? - _theResult___fst_exp__h638970 : - _theResult___fst_exp__h639490 ; - assign _theResult___fst_exp__h648080 = - _theResult____h639842[56] ? + assign _theResult___fst_exp__h639491 = + (_theResult___fst_exp__h638968 == 8'd255) ? + _theResult___fst_exp__h638968 : + _theResult___fst_exp__h639488 ; + assign _theResult___fst_exp__h648078 = + _theResult____h639840[56] ? 8'd2 : - _theResult___fst_exp__h648154 ; - assign _theResult___fst_exp__h648145 = + _theResult___fst_exp__h648152 ; + assign _theResult___fst_exp__h648143 = 8'd0 - { 2'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d10318 } ; - assign _theResult___fst_exp__h648151 = - (!_theResult____h639842[56] && !_theResult____h639842[55] && - !_theResult____h639842[54] && - !_theResult____h639842[53] && - !_theResult____h639842[52] && - !_theResult____h639842[51] && - !_theResult____h639842[50] && - !_theResult____h639842[49] && - !_theResult____h639842[48] && - !_theResult____h639842[47] && - !_theResult____h639842[46] && - !_theResult____h639842[45] && - !_theResult____h639842[44] && - !_theResult____h639842[43] && - !_theResult____h639842[42] && - !_theResult____h639842[41] && - !_theResult____h639842[40] && - !_theResult____h639842[39] && - !_theResult____h639842[38] && - !_theResult____h639842[37] && - !_theResult____h639842[36] && - !_theResult____h639842[35] && - !_theResult____h639842[34] && - !_theResult____h639842[33] && - !_theResult____h639842[32] && - !_theResult____h639842[31] && - !_theResult____h639842[30] && - !_theResult____h639842[29] && - !_theResult____h639842[28] && - !_theResult____h639842[27] && - !_theResult____h639842[26] && - !_theResult____h639842[25] && - !_theResult____h639842[24] && - !_theResult____h639842[23] && - !_theResult____h639842[22] && - !_theResult____h639842[21] && - !_theResult____h639842[20] && - !_theResult____h639842[19] && - !_theResult____h639842[18] && - !_theResult____h639842[17] && - !_theResult____h639842[16] && - !_theResult____h639842[15] && - !_theResult____h639842[14] && - !_theResult____h639842[13] && - !_theResult____h639842[12] && - !_theResult____h639842[11] && - !_theResult____h639842[10] && - !_theResult____h639842[9] && - !_theResult____h639842[8] && - !_theResult____h639842[7] && - !_theResult____h639842[6] && - !_theResult____h639842[5] && - !_theResult____h639842[4] && - !_theResult____h639842[3] && - !_theResult____h639842[2] && - !_theResult____h639842[1] && - !_theResult____h639842[0] || + assign _theResult___fst_exp__h648149 = + (!_theResult____h639840[56] && !_theResult____h639840[55] && + !_theResult____h639840[54] && + !_theResult____h639840[53] && + !_theResult____h639840[52] && + !_theResult____h639840[51] && + !_theResult____h639840[50] && + !_theResult____h639840[49] && + !_theResult____h639840[48] && + !_theResult____h639840[47] && + !_theResult____h639840[46] && + !_theResult____h639840[45] && + !_theResult____h639840[44] && + !_theResult____h639840[43] && + !_theResult____h639840[42] && + !_theResult____h639840[41] && + !_theResult____h639840[40] && + !_theResult____h639840[39] && + !_theResult____h639840[38] && + !_theResult____h639840[37] && + !_theResult____h639840[36] && + !_theResult____h639840[35] && + !_theResult____h639840[34] && + !_theResult____h639840[33] && + !_theResult____h639840[32] && + !_theResult____h639840[31] && + !_theResult____h639840[30] && + !_theResult____h639840[29] && + !_theResult____h639840[28] && + !_theResult____h639840[27] && + !_theResult____h639840[26] && + !_theResult____h639840[25] && + !_theResult____h639840[24] && + !_theResult____h639840[23] && + !_theResult____h639840[22] && + !_theResult____h639840[21] && + !_theResult____h639840[20] && + !_theResult____h639840[19] && + !_theResult____h639840[18] && + !_theResult____h639840[17] && + !_theResult____h639840[16] && + !_theResult____h639840[15] && + !_theResult____h639840[14] && + !_theResult____h639840[13] && + !_theResult____h639840[12] && + !_theResult____h639840[11] && + !_theResult____h639840[10] && + !_theResult____h639840[9] && + !_theResult____h639840[8] && + !_theResult____h639840[7] && + !_theResult____h639840[6] && + !_theResult____h639840[5] && + !_theResult____h639840[4] && + !_theResult____h639840[3] && + !_theResult____h639840[2] && + !_theResult____h639840[1] && + !_theResult____h639840[0] || !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d10320) ? 8'd0 : - _theResult___fst_exp__h648145 ; - assign _theResult___fst_exp__h648154 = - (!_theResult____h639842[56] && _theResult____h639842[55]) ? + _theResult___fst_exp__h648143 ; + assign _theResult___fst_exp__h648152 = + (!_theResult____h639840[56] && _theResult____h639840[55]) ? 8'd1 : - _theResult___fst_exp__h648151 ; - assign _theResult___fst_exp__h648677 = - (_theResult___fst_exp__h648080 == 8'd255) ? - _theResult___fst_exp__h648080 : - _theResult___fst_exp__h648674 ; - assign _theResult___fst_exp__h656717 = + _theResult___fst_exp__h648149 ; + assign _theResult___fst_exp__h648675 = + (_theResult___fst_exp__h648078 == 8'd255) ? + _theResult___fst_exp__h648078 : + _theResult___fst_exp__h648672 ; + assign _theResult___fst_exp__h656715 = (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q84[7:0] == 8'd0) ? 8'd1 : SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q84[7:0] ; - assign _theResult___fst_exp__h656756 = + assign _theResult___fst_exp__h656754 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q84[7:0] - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d9998 } ; - assign _theResult___fst_exp__h656762 = + assign _theResult___fst_exp__h656760 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d9943 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d10393) ? 8'd0 : - _theResult___fst_exp__h656756 ; - assign _theResult___fst_exp__h656765 = + _theResult___fst_exp__h656754 ; + assign _theResult___fst_exp__h656763 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h656762 : - _theResult___fst_exp__h656717 ; - assign _theResult___fst_exp__h657313 = - (_theResult___fst_exp__h656765 == 8'd255) ? - _theResult___fst_exp__h656765 : - _theResult___fst_exp__h657310 ; - assign _theResult___fst_exp__h657322 = + _theResult___fst_exp__h656760 : + _theResult___fst_exp__h656715 ; + assign _theResult___fst_exp__h657311 = + (_theResult___fst_exp__h656763 == 8'd255) ? + _theResult___fst_exp__h656763 : + _theResult___fst_exp__h657308 ; + assign _theResult___fst_exp__h657320 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9532 ? - _theResult___snd_fst_exp__h639496 : - _theResult___fst_exp__h622187) : + _theResult___snd_fst_exp__h639494 : + _theResult___fst_exp__h622185) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10072 ? - _theResult___snd_fst_exp__h657316 : - _theResult___fst_exp__h622187) ; - assign _theResult___fst_exp__h657325 = + _theResult___snd_fst_exp__h657314 : + _theResult___fst_exp__h622185) ; + assign _theResult___fst_exp__h657323 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == 52'd0) ? 8'd0 : - _theResult___fst_exp__h657322 ; - assign _theResult___fst_exp__h676061 = - _theResult____h667952[56] ? + _theResult___fst_exp__h657320 ; + assign _theResult___fst_exp__h676059 = + _theResult____h667950[56] ? 8'd2 : - _theResult___fst_exp__h676135 ; - assign _theResult___fst_exp__h676126 = + _theResult___fst_exp__h676133 ; + assign _theResult___fst_exp__h676124 = 8'd0 - { 2'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d11164 } ; - assign _theResult___fst_exp__h676132 = - (!_theResult____h667952[56] && !_theResult____h667952[55] && - !_theResult____h667952[54] && - !_theResult____h667952[53] && - !_theResult____h667952[52] && - !_theResult____h667952[51] && - !_theResult____h667952[50] && - !_theResult____h667952[49] && - !_theResult____h667952[48] && - !_theResult____h667952[47] && - !_theResult____h667952[46] && - !_theResult____h667952[45] && - !_theResult____h667952[44] && - !_theResult____h667952[43] && - !_theResult____h667952[42] && - !_theResult____h667952[41] && - !_theResult____h667952[40] && - !_theResult____h667952[39] && - !_theResult____h667952[38] && - !_theResult____h667952[37] && - !_theResult____h667952[36] && - !_theResult____h667952[35] && - !_theResult____h667952[34] && - !_theResult____h667952[33] && - !_theResult____h667952[32] && - !_theResult____h667952[31] && - !_theResult____h667952[30] && - !_theResult____h667952[29] && - !_theResult____h667952[28] && - !_theResult____h667952[27] && - !_theResult____h667952[26] && - !_theResult____h667952[25] && - !_theResult____h667952[24] && - !_theResult____h667952[23] && - !_theResult____h667952[22] && - !_theResult____h667952[21] && - !_theResult____h667952[20] && - !_theResult____h667952[19] && - !_theResult____h667952[18] && - !_theResult____h667952[17] && - !_theResult____h667952[16] && - !_theResult____h667952[15] && - !_theResult____h667952[14] && - !_theResult____h667952[13] && - !_theResult____h667952[12] && - !_theResult____h667952[11] && - !_theResult____h667952[10] && - !_theResult____h667952[9] && - !_theResult____h667952[8] && - !_theResult____h667952[7] && - !_theResult____h667952[6] && - !_theResult____h667952[5] && - !_theResult____h667952[4] && - !_theResult____h667952[3] && - !_theResult____h667952[2] && - !_theResult____h667952[1] && - !_theResult____h667952[0] || + assign _theResult___fst_exp__h676130 = + (!_theResult____h667950[56] && !_theResult____h667950[55] && + !_theResult____h667950[54] && + !_theResult____h667950[53] && + !_theResult____h667950[52] && + !_theResult____h667950[51] && + !_theResult____h667950[50] && + !_theResult____h667950[49] && + !_theResult____h667950[48] && + !_theResult____h667950[47] && + !_theResult____h667950[46] && + !_theResult____h667950[45] && + !_theResult____h667950[44] && + !_theResult____h667950[43] && + !_theResult____h667950[42] && + !_theResult____h667950[41] && + !_theResult____h667950[40] && + !_theResult____h667950[39] && + !_theResult____h667950[38] && + !_theResult____h667950[37] && + !_theResult____h667950[36] && + !_theResult____h667950[35] && + !_theResult____h667950[34] && + !_theResult____h667950[33] && + !_theResult____h667950[32] && + !_theResult____h667950[31] && + !_theResult____h667950[30] && + !_theResult____h667950[29] && + !_theResult____h667950[28] && + !_theResult____h667950[27] && + !_theResult____h667950[26] && + !_theResult____h667950[25] && + !_theResult____h667950[24] && + !_theResult____h667950[23] && + !_theResult____h667950[22] && + !_theResult____h667950[21] && + !_theResult____h667950[20] && + !_theResult____h667950[19] && + !_theResult____h667950[18] && + !_theResult____h667950[17] && + !_theResult____h667950[16] && + !_theResult____h667950[15] && + !_theResult____h667950[14] && + !_theResult____h667950[13] && + !_theResult____h667950[12] && + !_theResult____h667950[11] && + !_theResult____h667950[10] && + !_theResult____h667950[9] && + !_theResult____h667950[8] && + !_theResult____h667950[7] && + !_theResult____h667950[6] && + !_theResult____h667950[5] && + !_theResult____h667950[4] && + !_theResult____h667950[3] && + !_theResult____h667950[2] && + !_theResult____h667950[1] && + !_theResult____h667950[0] || !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d11166) ? 8'd0 : - _theResult___fst_exp__h676126 ; - assign _theResult___fst_exp__h676135 = - (!_theResult____h667952[56] && _theResult____h667952[55]) ? + _theResult___fst_exp__h676124 ; + assign _theResult___fst_exp__h676133 = + (!_theResult____h667950[56] && _theResult____h667950[55]) ? 8'd1 : - _theResult___fst_exp__h676132 ; - assign _theResult___fst_exp__h676658 = - (_theResult___fst_exp__h676061 == 8'd255) ? - _theResult___fst_exp__h676061 : - _theResult___fst_exp__h676655 ; - assign _theResult___fst_exp__h684708 = + _theResult___fst_exp__h676130 ; + assign _theResult___fst_exp__h676656 = + (_theResult___fst_exp__h676059 == 8'd255) ? + _theResult___fst_exp__h676059 : + _theResult___fst_exp__h676653 ; + assign _theResult___fst_exp__h684706 = 8'd129 - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d11395 } ; - assign _theResult___fst_exp__h684714 = + assign _theResult___fst_exp__h684712 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d11340 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d11397) ? 8'd0 : - _theResult___fst_exp__h684708 ; - assign _theResult___fst_exp__h684717 = + _theResult___fst_exp__h684706 ; + assign _theResult___fst_exp__h684715 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h684714 : + _theResult___fst_exp__h684712 : 8'd129 ; - assign _theResult___fst_exp__h685240 = - (_theResult___fst_exp__h684717 == 8'd255) ? - _theResult___fst_exp__h684717 : - _theResult___fst_exp__h685237 ; - assign _theResult___fst_exp__h693827 = - _theResult____h685589[56] ? + assign _theResult___fst_exp__h685238 = + (_theResult___fst_exp__h684715 == 8'd255) ? + _theResult___fst_exp__h684715 : + _theResult___fst_exp__h685235 ; + assign _theResult___fst_exp__h693825 = + _theResult____h685587[56] ? 8'd2 : - _theResult___fst_exp__h693901 ; - assign _theResult___fst_exp__h693892 = + _theResult___fst_exp__h693899 ; + assign _theResult___fst_exp__h693890 = 8'd0 - { 2'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d11715 } ; - assign _theResult___fst_exp__h693898 = - (!_theResult____h685589[56] && !_theResult____h685589[55] && - !_theResult____h685589[54] && - !_theResult____h685589[53] && - !_theResult____h685589[52] && - !_theResult____h685589[51] && - !_theResult____h685589[50] && - !_theResult____h685589[49] && - !_theResult____h685589[48] && - !_theResult____h685589[47] && - !_theResult____h685589[46] && - !_theResult____h685589[45] && - !_theResult____h685589[44] && - !_theResult____h685589[43] && - !_theResult____h685589[42] && - !_theResult____h685589[41] && - !_theResult____h685589[40] && - !_theResult____h685589[39] && - !_theResult____h685589[38] && - !_theResult____h685589[37] && - !_theResult____h685589[36] && - !_theResult____h685589[35] && - !_theResult____h685589[34] && - !_theResult____h685589[33] && - !_theResult____h685589[32] && - !_theResult____h685589[31] && - !_theResult____h685589[30] && - !_theResult____h685589[29] && - !_theResult____h685589[28] && - !_theResult____h685589[27] && - !_theResult____h685589[26] && - !_theResult____h685589[25] && - !_theResult____h685589[24] && - !_theResult____h685589[23] && - !_theResult____h685589[22] && - !_theResult____h685589[21] && - !_theResult____h685589[20] && - !_theResult____h685589[19] && - !_theResult____h685589[18] && - !_theResult____h685589[17] && - !_theResult____h685589[16] && - !_theResult____h685589[15] && - !_theResult____h685589[14] && - !_theResult____h685589[13] && - !_theResult____h685589[12] && - !_theResult____h685589[11] && - !_theResult____h685589[10] && - !_theResult____h685589[9] && - !_theResult____h685589[8] && - !_theResult____h685589[7] && - !_theResult____h685589[6] && - !_theResult____h685589[5] && - !_theResult____h685589[4] && - !_theResult____h685589[3] && - !_theResult____h685589[2] && - !_theResult____h685589[1] && - !_theResult____h685589[0] || + assign _theResult___fst_exp__h693896 = + (!_theResult____h685587[56] && !_theResult____h685587[55] && + !_theResult____h685587[54] && + !_theResult____h685587[53] && + !_theResult____h685587[52] && + !_theResult____h685587[51] && + !_theResult____h685587[50] && + !_theResult____h685587[49] && + !_theResult____h685587[48] && + !_theResult____h685587[47] && + !_theResult____h685587[46] && + !_theResult____h685587[45] && + !_theResult____h685587[44] && + !_theResult____h685587[43] && + !_theResult____h685587[42] && + !_theResult____h685587[41] && + !_theResult____h685587[40] && + !_theResult____h685587[39] && + !_theResult____h685587[38] && + !_theResult____h685587[37] && + !_theResult____h685587[36] && + !_theResult____h685587[35] && + !_theResult____h685587[34] && + !_theResult____h685587[33] && + !_theResult____h685587[32] && + !_theResult____h685587[31] && + !_theResult____h685587[30] && + !_theResult____h685587[29] && + !_theResult____h685587[28] && + !_theResult____h685587[27] && + !_theResult____h685587[26] && + !_theResult____h685587[25] && + !_theResult____h685587[24] && + !_theResult____h685587[23] && + !_theResult____h685587[22] && + !_theResult____h685587[21] && + !_theResult____h685587[20] && + !_theResult____h685587[19] && + !_theResult____h685587[18] && + !_theResult____h685587[17] && + !_theResult____h685587[16] && + !_theResult____h685587[15] && + !_theResult____h685587[14] && + !_theResult____h685587[13] && + !_theResult____h685587[12] && + !_theResult____h685587[11] && + !_theResult____h685587[10] && + !_theResult____h685587[9] && + !_theResult____h685587[8] && + !_theResult____h685587[7] && + !_theResult____h685587[6] && + !_theResult____h685587[5] && + !_theResult____h685587[4] && + !_theResult____h685587[3] && + !_theResult____h685587[2] && + !_theResult____h685587[1] && + !_theResult____h685587[0] || !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d11717) ? 8'd0 : - _theResult___fst_exp__h693892 ; - assign _theResult___fst_exp__h693901 = - (!_theResult____h685589[56] && _theResult____h685589[55]) ? + _theResult___fst_exp__h693890 ; + assign _theResult___fst_exp__h693899 = + (!_theResult____h685587[56] && _theResult____h685587[55]) ? 8'd1 : - _theResult___fst_exp__h693898 ; - assign _theResult___fst_exp__h694424 = - (_theResult___fst_exp__h693827 == 8'd255) ? - _theResult___fst_exp__h693827 : - _theResult___fst_exp__h694421 ; - assign _theResult___fst_exp__h702464 = + _theResult___fst_exp__h693896 ; + assign _theResult___fst_exp__h694422 = + (_theResult___fst_exp__h693825 == 8'd255) ? + _theResult___fst_exp__h693825 : + _theResult___fst_exp__h694419 ; + assign _theResult___fst_exp__h702462 = (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q119[7:0] == 8'd0) ? 8'd1 : SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q119[7:0] ; - assign _theResult___fst_exp__h702503 = + assign _theResult___fst_exp__h702501 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q119[7:0] - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d11395 } ; - assign _theResult___fst_exp__h702509 = + assign _theResult___fst_exp__h702507 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d11340 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d11790) ? 8'd0 : - _theResult___fst_exp__h702503 ; - assign _theResult___fst_exp__h702512 = + _theResult___fst_exp__h702501 ; + assign _theResult___fst_exp__h702510 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h702509 : - _theResult___fst_exp__h702464 ; - assign _theResult___fst_exp__h703060 = - (_theResult___fst_exp__h702512 == 8'd255) ? - _theResult___fst_exp__h702512 : - _theResult___fst_exp__h703057 ; - assign _theResult___fst_exp__h703069 = + _theResult___fst_exp__h702507 : + _theResult___fst_exp__h702462 ; + assign _theResult___fst_exp__h703058 = + (_theResult___fst_exp__h702510 == 8'd255) ? + _theResult___fst_exp__h702510 : + _theResult___fst_exp__h703055 ; + assign _theResult___fst_exp__h703067 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10929 ? - _theResult___snd_fst_exp__h685243 : - _theResult___fst_exp__h667934) : + _theResult___snd_fst_exp__h685241 : + _theResult___fst_exp__h667932) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11469 ? - _theResult___snd_fst_exp__h703063 : - _theResult___fst_exp__h667934) ; - assign _theResult___fst_exp__h703072 = + _theResult___snd_fst_exp__h703061 : + _theResult___fst_exp__h667932) ; + assign _theResult___fst_exp__h703070 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == 52'd0) ? 8'd0 : - _theResult___fst_exp__h703069 ; - assign _theResult___fst_exp__h719214 = + _theResult___fst_exp__h703067 ; + assign _theResult___fst_exp__h719211 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q27 ; - assign _theResult___fst_exp__h734278 = + assign _theResult___fst_exp__h734275 = 11'd897 - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d12734 } ; - assign _theResult___fst_exp__h734284 = - (f1_exp__h714899 == 8'd0 && !f1_sfd__h714900[22] && + assign _theResult___fst_exp__h734281 = + (f1_exp__h714896 == 8'd0 && !f1_sfd__h714897[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d12707 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d12736) ? 11'd0 : - _theResult___fst_exp__h734278 ; - assign _theResult___fst_exp__h734287 = - (f1_exp__h714899 == 8'd0) ? - _theResult___fst_exp__h734284 : + _theResult___fst_exp__h734275 ; + assign _theResult___fst_exp__h734284 = + (f1_exp__h714896 == 8'd0) ? + _theResult___fst_exp__h734281 : 11'd897 ; - assign _theResult___fst_exp__h735042 = + assign _theResult___fst_exp__h735039 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard26326_0b0_theResult___fst_exp34287_0_ETC__q156 : + CASE_guard26323_0b0_theResult___fst_exp34284_0_ETC__q156 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13170 ; - assign _theResult___fst_exp__h735045 = - (_theResult___fst_exp__h734287 == 11'd2047) ? - _theResult___fst_exp__h734287 : - _theResult___fst_exp__h735042 ; - assign _theResult___fst_exp__h743864 = - _theResult____h735628[56] ? + assign _theResult___fst_exp__h735042 = + (_theResult___fst_exp__h734284 == 11'd2047) ? + _theResult___fst_exp__h734284 : + _theResult___fst_exp__h735039 ; + assign _theResult___fst_exp__h743861 = + _theResult____h735625[56] ? 11'd2 : - _theResult___fst_exp__h743938 ; - assign _theResult___fst_exp__h743929 = + _theResult___fst_exp__h743935 ; + assign _theResult___fst_exp__h743926 = 11'd0 - { 5'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d13046 } ; - assign _theResult___fst_exp__h743935 = - (!_theResult____h735628[56] && !_theResult____h735628[55] && - !_theResult____h735628[54] && - !_theResult____h735628[53] && - !_theResult____h735628[52] && - !_theResult____h735628[51] && - !_theResult____h735628[50] && - !_theResult____h735628[49] && - !_theResult____h735628[48] && - !_theResult____h735628[47] && - !_theResult____h735628[46] && - !_theResult____h735628[45] && - !_theResult____h735628[44] && - !_theResult____h735628[43] && - !_theResult____h735628[42] && - !_theResult____h735628[41] && - !_theResult____h735628[40] && - !_theResult____h735628[39] && - !_theResult____h735628[38] && - !_theResult____h735628[37] && - !_theResult____h735628[36] && - !_theResult____h735628[35] && - !_theResult____h735628[34] && - !_theResult____h735628[33] && - !_theResult____h735628[32] && - !_theResult____h735628[31] && - !_theResult____h735628[30] && - !_theResult____h735628[29] && - !_theResult____h735628[28] && - !_theResult____h735628[27] && - !_theResult____h735628[26] && - !_theResult____h735628[25] && - !_theResult____h735628[24] && - !_theResult____h735628[23] && - !_theResult____h735628[22] && - !_theResult____h735628[21] && - !_theResult____h735628[20] && - !_theResult____h735628[19] && - !_theResult____h735628[18] && - !_theResult____h735628[17] && - !_theResult____h735628[16] && - !_theResult____h735628[15] && - !_theResult____h735628[14] && - !_theResult____h735628[13] && - !_theResult____h735628[12] && - !_theResult____h735628[11] && - !_theResult____h735628[10] && - !_theResult____h735628[9] && - !_theResult____h735628[8] && - !_theResult____h735628[7] && - !_theResult____h735628[6] && - !_theResult____h735628[5] && - !_theResult____h735628[4] && - !_theResult____h735628[3] && - !_theResult____h735628[2] && - !_theResult____h735628[1] && - !_theResult____h735628[0] || + assign _theResult___fst_exp__h743932 = + (!_theResult____h735625[56] && !_theResult____h735625[55] && + !_theResult____h735625[54] && + !_theResult____h735625[53] && + !_theResult____h735625[52] && + !_theResult____h735625[51] && + !_theResult____h735625[50] && + !_theResult____h735625[49] && + !_theResult____h735625[48] && + !_theResult____h735625[47] && + !_theResult____h735625[46] && + !_theResult____h735625[45] && + !_theResult____h735625[44] && + !_theResult____h735625[43] && + !_theResult____h735625[42] && + !_theResult____h735625[41] && + !_theResult____h735625[40] && + !_theResult____h735625[39] && + !_theResult____h735625[38] && + !_theResult____h735625[37] && + !_theResult____h735625[36] && + !_theResult____h735625[35] && + !_theResult____h735625[34] && + !_theResult____h735625[33] && + !_theResult____h735625[32] && + !_theResult____h735625[31] && + !_theResult____h735625[30] && + !_theResult____h735625[29] && + !_theResult____h735625[28] && + !_theResult____h735625[27] && + !_theResult____h735625[26] && + !_theResult____h735625[25] && + !_theResult____h735625[24] && + !_theResult____h735625[23] && + !_theResult____h735625[22] && + !_theResult____h735625[21] && + !_theResult____h735625[20] && + !_theResult____h735625[19] && + !_theResult____h735625[18] && + !_theResult____h735625[17] && + !_theResult____h735625[16] && + !_theResult____h735625[15] && + !_theResult____h735625[14] && + !_theResult____h735625[13] && + !_theResult____h735625[12] && + !_theResult____h735625[11] && + !_theResult____h735625[10] && + !_theResult____h735625[9] && + !_theResult____h735625[8] && + !_theResult____h735625[7] && + !_theResult____h735625[6] && + !_theResult____h735625[5] && + !_theResult____h735625[4] && + !_theResult____h735625[3] && + !_theResult____h735625[2] && + !_theResult____h735625[1] && + !_theResult____h735625[0] || !_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d13048) ? 11'd0 : - _theResult___fst_exp__h743929 ; - assign _theResult___fst_exp__h743938 = - (!_theResult____h735628[56] && _theResult____h735628[55]) ? + _theResult___fst_exp__h743926 ; + assign _theResult___fst_exp__h743935 = + (!_theResult____h735625[56] && _theResult____h735625[55]) ? 11'd1 : - _theResult___fst_exp__h743935 ; - assign _theResult___fst_exp__h744693 = + _theResult___fst_exp__h743932 ; + assign _theResult___fst_exp__h744690 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard35638_0b0_theResult___fst_exp43864_0_ETC__q224 : + CASE_guard35635_0b0_theResult___fst_exp43861_0_ETC__q224 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13213 ; - assign _theResult___fst_exp__h744696 = - (_theResult___fst_exp__h743864 == 11'd2047) ? - _theResult___fst_exp__h743864 : - _theResult___fst_exp__h744693 ; - assign _theResult___fst_exp__h752649 = + assign _theResult___fst_exp__h744693 = + (_theResult___fst_exp__h743861 == 11'd2047) ? + _theResult___fst_exp__h743861 : + _theResult___fst_exp__h744690 ; + assign _theResult___fst_exp__h752646 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q149[10:0] == 11'd0) ? 11'd1 : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q149[10:0] ; - assign _theResult___fst_exp__h752688 = + assign _theResult___fst_exp__h752685 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q149[10:0] - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d12734 } ; - assign _theResult___fst_exp__h752694 = - (f1_exp__h714899 == 8'd0 && !f1_sfd__h714900[22] && + assign _theResult___fst_exp__h752691 = + (f1_exp__h714896 == 8'd0 && !f1_sfd__h714897[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d12707 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d13098) ? 11'd0 : - _theResult___fst_exp__h752688 ; - assign _theResult___fst_exp__h752697 = - (f1_exp__h714899 == 8'd0) ? - _theResult___fst_exp__h752694 : - _theResult___fst_exp__h752649 ; - assign _theResult___fst_exp__h753477 = + _theResult___fst_exp__h752685 ; + assign _theResult___fst_exp__h752694 = + (f1_exp__h714896 == 8'd0) ? + _theResult___fst_exp__h752691 : + _theResult___fst_exp__h752646 ; + assign _theResult___fst_exp__h753474 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard44707_0b0_theResult___fst_exp52697_0_ETC__q226 : + CASE_guard44704_0b0_theResult___fst_exp52694_0_ETC__q228 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13244 ; - assign _theResult___fst_exp__h753480 = - (_theResult___fst_exp__h752697 == 11'd2047) ? - _theResult___fst_exp__h752697 : - _theResult___fst_exp__h753477 ; - assign _theResult___fst_exp__h753489 = - (f1_exp__h714899 == 8'd0) ? + assign _theResult___fst_exp__h753477 = + (_theResult___fst_exp__h752694 == 11'd2047) ? + _theResult___fst_exp__h752694 : + _theResult___fst_exp__h753474 ; + assign _theResult___fst_exp__h753486 = + (f1_exp__h714896 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12661 ? - _theResult___snd_fst_exp__h735048 : - _theResult___fst_exp__h719214) : + _theResult___snd_fst_exp__h735045 : + _theResult___fst_exp__h719211) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12798 ? - _theResult___snd_fst_exp__h753483 : - _theResult___fst_exp__h719214) ; - assign _theResult___fst_exp__h753492 = - (f1_exp__h714899 == 8'd0 && f1_sfd__h714900 == 23'd0) ? + _theResult___snd_fst_exp__h753480 : + _theResult___fst_exp__h719211) ; + assign _theResult___fst_exp__h753489 = + (f1_exp__h714896 == 8'd0 && f1_sfd__h714897 == 23'd0) ? 11'd0 : - _theResult___fst_exp__h753489 ; - assign _theResult___fst_exp__h758067 = + _theResult___fst_exp__h753486 ; + assign _theResult___fst_exp__h758064 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q29 ; - assign _theResult___fst_exp__h773131 = + assign _theResult___fst_exp__h773128 = 11'd897 - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14234 } ; - assign _theResult___fst_exp__h773137 = - (f2_exp__h753893 == 8'd0 && !f2_sfd__h753894[22] && + assign _theResult___fst_exp__h773134 = + (f2_exp__h753890 == 8'd0 && !f2_sfd__h753891[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d14207 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14236) ? 11'd0 : - _theResult___fst_exp__h773131 ; - assign _theResult___fst_exp__h773140 = - (f2_exp__h753893 == 8'd0) ? - _theResult___fst_exp__h773137 : + _theResult___fst_exp__h773128 ; + assign _theResult___fst_exp__h773137 = + (f2_exp__h753890 == 8'd0) ? + _theResult___fst_exp__h773134 : 11'd897 ; - assign _theResult___fst_exp__h773895 = + assign _theResult___fst_exp__h773892 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard65179_0b0_theResult___fst_exp73140_0_ETC__q196 : + CASE_guard65176_0b0_theResult___fst_exp73137_0_ETC__q196 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14655 ; - assign _theResult___fst_exp__h773898 = - (_theResult___fst_exp__h773140 == 11'd2047) ? - _theResult___fst_exp__h773140 : - _theResult___fst_exp__h773895 ; - assign _theResult___fst_exp__h782717 = - _theResult____h774481[56] ? + assign _theResult___fst_exp__h773895 = + (_theResult___fst_exp__h773137 == 11'd2047) ? + _theResult___fst_exp__h773137 : + _theResult___fst_exp__h773892 ; + assign _theResult___fst_exp__h782714 = + _theResult____h774478[56] ? 11'd2 : - _theResult___fst_exp__h782791 ; - assign _theResult___fst_exp__h782782 = + _theResult___fst_exp__h782788 ; + assign _theResult___fst_exp__h782779 = 11'd0 - { 5'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d14531 } ; - assign _theResult___fst_exp__h782788 = - (!_theResult____h774481[56] && !_theResult____h774481[55] && - !_theResult____h774481[54] && - !_theResult____h774481[53] && - !_theResult____h774481[52] && - !_theResult____h774481[51] && - !_theResult____h774481[50] && - !_theResult____h774481[49] && - !_theResult____h774481[48] && - !_theResult____h774481[47] && - !_theResult____h774481[46] && - !_theResult____h774481[45] && - !_theResult____h774481[44] && - !_theResult____h774481[43] && - !_theResult____h774481[42] && - !_theResult____h774481[41] && - !_theResult____h774481[40] && - !_theResult____h774481[39] && - !_theResult____h774481[38] && - !_theResult____h774481[37] && - !_theResult____h774481[36] && - !_theResult____h774481[35] && - !_theResult____h774481[34] && - !_theResult____h774481[33] && - !_theResult____h774481[32] && - !_theResult____h774481[31] && - !_theResult____h774481[30] && - !_theResult____h774481[29] && - !_theResult____h774481[28] && - !_theResult____h774481[27] && - !_theResult____h774481[26] && - !_theResult____h774481[25] && - !_theResult____h774481[24] && - !_theResult____h774481[23] && - !_theResult____h774481[22] && - !_theResult____h774481[21] && - !_theResult____h774481[20] && - !_theResult____h774481[19] && - !_theResult____h774481[18] && - !_theResult____h774481[17] && - !_theResult____h774481[16] && - !_theResult____h774481[15] && - !_theResult____h774481[14] && - !_theResult____h774481[13] && - !_theResult____h774481[12] && - !_theResult____h774481[11] && - !_theResult____h774481[10] && - !_theResult____h774481[9] && - !_theResult____h774481[8] && - !_theResult____h774481[7] && - !_theResult____h774481[6] && - !_theResult____h774481[5] && - !_theResult____h774481[4] && - !_theResult____h774481[3] && - !_theResult____h774481[2] && - !_theResult____h774481[1] && - !_theResult____h774481[0] || + assign _theResult___fst_exp__h782785 = + (!_theResult____h774478[56] && !_theResult____h774478[55] && + !_theResult____h774478[54] && + !_theResult____h774478[53] && + !_theResult____h774478[52] && + !_theResult____h774478[51] && + !_theResult____h774478[50] && + !_theResult____h774478[49] && + !_theResult____h774478[48] && + !_theResult____h774478[47] && + !_theResult____h774478[46] && + !_theResult____h774478[45] && + !_theResult____h774478[44] && + !_theResult____h774478[43] && + !_theResult____h774478[42] && + !_theResult____h774478[41] && + !_theResult____h774478[40] && + !_theResult____h774478[39] && + !_theResult____h774478[38] && + !_theResult____h774478[37] && + !_theResult____h774478[36] && + !_theResult____h774478[35] && + !_theResult____h774478[34] && + !_theResult____h774478[33] && + !_theResult____h774478[32] && + !_theResult____h774478[31] && + !_theResult____h774478[30] && + !_theResult____h774478[29] && + !_theResult____h774478[28] && + !_theResult____h774478[27] && + !_theResult____h774478[26] && + !_theResult____h774478[25] && + !_theResult____h774478[24] && + !_theResult____h774478[23] && + !_theResult____h774478[22] && + !_theResult____h774478[21] && + !_theResult____h774478[20] && + !_theResult____h774478[19] && + !_theResult____h774478[18] && + !_theResult____h774478[17] && + !_theResult____h774478[16] && + !_theResult____h774478[15] && + !_theResult____h774478[14] && + !_theResult____h774478[13] && + !_theResult____h774478[12] && + !_theResult____h774478[11] && + !_theResult____h774478[10] && + !_theResult____h774478[9] && + !_theResult____h774478[8] && + !_theResult____h774478[7] && + !_theResult____h774478[6] && + !_theResult____h774478[5] && + !_theResult____h774478[4] && + !_theResult____h774478[3] && + !_theResult____h774478[2] && + !_theResult____h774478[1] && + !_theResult____h774478[0] || !_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14533) ? 11'd0 : - _theResult___fst_exp__h782782 ; - assign _theResult___fst_exp__h782791 = - (!_theResult____h774481[56] && _theResult____h774481[55]) ? + _theResult___fst_exp__h782779 ; + assign _theResult___fst_exp__h782788 = + (!_theResult____h774478[56] && _theResult____h774478[55]) ? 11'd1 : - _theResult___fst_exp__h782788 ; - assign _theResult___fst_exp__h783546 = + _theResult___fst_exp__h782785 ; + assign _theResult___fst_exp__h783543 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard74491_0b0_theResult___fst_exp82717_0_ETC__q200 : + CASE_guard74488_0b0_theResult___fst_exp82714_0_ETC__q198 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14693 ; - assign _theResult___fst_exp__h783549 = - (_theResult___fst_exp__h782717 == 11'd2047) ? - _theResult___fst_exp__h782717 : - _theResult___fst_exp__h783546 ; - assign _theResult___fst_exp__h791502 = + assign _theResult___fst_exp__h783546 = + (_theResult___fst_exp__h782714 == 11'd2047) ? + _theResult___fst_exp__h782714 : + _theResult___fst_exp__h783543 ; + assign _theResult___fst_exp__h791499 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q189[10:0] == 11'd0) ? 11'd1 : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q189[10:0] ; - assign _theResult___fst_exp__h791541 = + assign _theResult___fst_exp__h791538 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q189[10:0] - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14234 } ; - assign _theResult___fst_exp__h791547 = - (f2_exp__h753893 == 8'd0 && !f2_sfd__h753894[22] && + assign _theResult___fst_exp__h791544 = + (f2_exp__h753890 == 8'd0 && !f2_sfd__h753891[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d14207 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14583) ? 11'd0 : - _theResult___fst_exp__h791541 ; - assign _theResult___fst_exp__h791550 = - (f2_exp__h753893 == 8'd0) ? - _theResult___fst_exp__h791547 : - _theResult___fst_exp__h791502 ; - assign _theResult___fst_exp__h792330 = + _theResult___fst_exp__h791538 ; + assign _theResult___fst_exp__h791547 = + (f2_exp__h753890 == 8'd0) ? + _theResult___fst_exp__h791544 : + _theResult___fst_exp__h791499 ; + assign _theResult___fst_exp__h792327 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard83560_0b0_theResult___fst_exp91550_0_ETC__q198 : + CASE_guard83557_0b0_theResult___fst_exp91547_0_ETC__q200 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14724 ; - assign _theResult___fst_exp__h792333 = - (_theResult___fst_exp__h791550 == 11'd2047) ? - _theResult___fst_exp__h791550 : - _theResult___fst_exp__h792330 ; - assign _theResult___fst_exp__h792342 = - (f2_exp__h753893 == 8'd0) ? + assign _theResult___fst_exp__h792330 = + (_theResult___fst_exp__h791547 == 11'd2047) ? + _theResult___fst_exp__h791547 : + _theResult___fst_exp__h792327 ; + assign _theResult___fst_exp__h792339 = + (f2_exp__h753890 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14161 ? - _theResult___snd_fst_exp__h773901 : - _theResult___fst_exp__h758067) : + _theResult___snd_fst_exp__h773898 : + _theResult___fst_exp__h758064) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14283 ? - _theResult___snd_fst_exp__h792336 : - _theResult___fst_exp__h758067) ; - assign _theResult___fst_exp__h792345 = - (f2_exp__h753893 == 8'd0 && f2_sfd__h753894 == 23'd0) ? + _theResult___snd_fst_exp__h792333 : + _theResult___fst_exp__h758064) ; + assign _theResult___fst_exp__h792342 = + (f2_exp__h753890 == 8'd0 && f2_sfd__h753891 == 23'd0) ? 11'd0 : - _theResult___fst_exp__h792342 ; - assign _theResult___fst_exp__h797371 = + _theResult___fst_exp__h792339 ; + assign _theResult___fst_exp__h797368 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q31 ; - assign _theResult___fst_exp__h812435 = + assign _theResult___fst_exp__h812432 = 11'd897 - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13464 } ; - assign _theResult___fst_exp__h812441 = - (f3_exp__h793197 == 8'd0 && !f3_sfd__h793198[22] && + assign _theResult___fst_exp__h812438 = + (f3_exp__h793194 == 8'd0 && !f3_sfd__h793195[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d13437 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d13466) ? 11'd0 : - _theResult___fst_exp__h812435 ; - assign _theResult___fst_exp__h812444 = - (f3_exp__h793197 == 8'd0) ? - _theResult___fst_exp__h812441 : + _theResult___fst_exp__h812432 ; + assign _theResult___fst_exp__h812441 = + (f3_exp__h793194 == 8'd0) ? + _theResult___fst_exp__h812438 : 11'd897 ; - assign _theResult___fst_exp__h813199 = + assign _theResult___fst_exp__h813196 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard04483_0b0_theResult___fst_exp12444_0_ETC__q173 : + CASE_guard04480_0b0_theResult___fst_exp12441_0_ETC__q173 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13885 ; - assign _theResult___fst_exp__h813202 = - (_theResult___fst_exp__h812444 == 11'd2047) ? - _theResult___fst_exp__h812444 : - _theResult___fst_exp__h813199 ; - assign _theResult___fst_exp__h822021 = - _theResult____h813785[56] ? + assign _theResult___fst_exp__h813199 = + (_theResult___fst_exp__h812441 == 11'd2047) ? + _theResult___fst_exp__h812441 : + _theResult___fst_exp__h813196 ; + assign _theResult___fst_exp__h822018 = + _theResult____h813782[56] ? 11'd2 : - _theResult___fst_exp__h822095 ; - assign _theResult___fst_exp__h822086 = + _theResult___fst_exp__h822092 ; + assign _theResult___fst_exp__h822083 = 11'd0 - { 5'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d13761 } ; - assign _theResult___fst_exp__h822092 = - (!_theResult____h813785[56] && !_theResult____h813785[55] && - !_theResult____h813785[54] && - !_theResult____h813785[53] && - !_theResult____h813785[52] && - !_theResult____h813785[51] && - !_theResult____h813785[50] && - !_theResult____h813785[49] && - !_theResult____h813785[48] && - !_theResult____h813785[47] && - !_theResult____h813785[46] && - !_theResult____h813785[45] && - !_theResult____h813785[44] && - !_theResult____h813785[43] && - !_theResult____h813785[42] && - !_theResult____h813785[41] && - !_theResult____h813785[40] && - !_theResult____h813785[39] && - !_theResult____h813785[38] && - !_theResult____h813785[37] && - !_theResult____h813785[36] && - !_theResult____h813785[35] && - !_theResult____h813785[34] && - !_theResult____h813785[33] && - !_theResult____h813785[32] && - !_theResult____h813785[31] && - !_theResult____h813785[30] && - !_theResult____h813785[29] && - !_theResult____h813785[28] && - !_theResult____h813785[27] && - !_theResult____h813785[26] && - !_theResult____h813785[25] && - !_theResult____h813785[24] && - !_theResult____h813785[23] && - !_theResult____h813785[22] && - !_theResult____h813785[21] && - !_theResult____h813785[20] && - !_theResult____h813785[19] && - !_theResult____h813785[18] && - !_theResult____h813785[17] && - !_theResult____h813785[16] && - !_theResult____h813785[15] && - !_theResult____h813785[14] && - !_theResult____h813785[13] && - !_theResult____h813785[12] && - !_theResult____h813785[11] && - !_theResult____h813785[10] && - !_theResult____h813785[9] && - !_theResult____h813785[8] && - !_theResult____h813785[7] && - !_theResult____h813785[6] && - !_theResult____h813785[5] && - !_theResult____h813785[4] && - !_theResult____h813785[3] && - !_theResult____h813785[2] && - !_theResult____h813785[1] && - !_theResult____h813785[0] || + assign _theResult___fst_exp__h822089 = + (!_theResult____h813782[56] && !_theResult____h813782[55] && + !_theResult____h813782[54] && + !_theResult____h813782[53] && + !_theResult____h813782[52] && + !_theResult____h813782[51] && + !_theResult____h813782[50] && + !_theResult____h813782[49] && + !_theResult____h813782[48] && + !_theResult____h813782[47] && + !_theResult____h813782[46] && + !_theResult____h813782[45] && + !_theResult____h813782[44] && + !_theResult____h813782[43] && + !_theResult____h813782[42] && + !_theResult____h813782[41] && + !_theResult____h813782[40] && + !_theResult____h813782[39] && + !_theResult____h813782[38] && + !_theResult____h813782[37] && + !_theResult____h813782[36] && + !_theResult____h813782[35] && + !_theResult____h813782[34] && + !_theResult____h813782[33] && + !_theResult____h813782[32] && + !_theResult____h813782[31] && + !_theResult____h813782[30] && + !_theResult____h813782[29] && + !_theResult____h813782[28] && + !_theResult____h813782[27] && + !_theResult____h813782[26] && + !_theResult____h813782[25] && + !_theResult____h813782[24] && + !_theResult____h813782[23] && + !_theResult____h813782[22] && + !_theResult____h813782[21] && + !_theResult____h813782[20] && + !_theResult____h813782[19] && + !_theResult____h813782[18] && + !_theResult____h813782[17] && + !_theResult____h813782[16] && + !_theResult____h813782[15] && + !_theResult____h813782[14] && + !_theResult____h813782[13] && + !_theResult____h813782[12] && + !_theResult____h813782[11] && + !_theResult____h813782[10] && + !_theResult____h813782[9] && + !_theResult____h813782[8] && + !_theResult____h813782[7] && + !_theResult____h813782[6] && + !_theResult____h813782[5] && + !_theResult____h813782[4] && + !_theResult____h813782[3] && + !_theResult____h813782[2] && + !_theResult____h813782[1] && + !_theResult____h813782[0] || !_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d13763) ? 11'd0 : - _theResult___fst_exp__h822086 ; - assign _theResult___fst_exp__h822095 = - (!_theResult____h813785[56] && _theResult____h813785[55]) ? + _theResult___fst_exp__h822083 ; + assign _theResult___fst_exp__h822092 = + (!_theResult____h813782[56] && _theResult____h813782[55]) ? 11'd1 : - _theResult___fst_exp__h822092 ; - assign _theResult___fst_exp__h822850 = + _theResult___fst_exp__h822089 ; + assign _theResult___fst_exp__h822847 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard13795_0b0_theResult___fst_exp22021_0_ETC__q202 : + CASE_guard13792_0b0_theResult___fst_exp22018_0_ETC__q204 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13923 ; - assign _theResult___fst_exp__h822853 = - (_theResult___fst_exp__h822021 == 11'd2047) ? - _theResult___fst_exp__h822021 : - _theResult___fst_exp__h822850 ; - assign _theResult___fst_exp__h830806 = + assign _theResult___fst_exp__h822850 = + (_theResult___fst_exp__h822018 == 11'd2047) ? + _theResult___fst_exp__h822018 : + _theResult___fst_exp__h822847 ; + assign _theResult___fst_exp__h830803 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q166[10:0] == 11'd0) ? 11'd1 : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q166[10:0] ; - assign _theResult___fst_exp__h830845 = + assign _theResult___fst_exp__h830842 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q166[10:0] - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13464 } ; - assign _theResult___fst_exp__h830851 = - (f3_exp__h793197 == 8'd0 && !f3_sfd__h793198[22] && + assign _theResult___fst_exp__h830848 = + (f3_exp__h793194 == 8'd0 && !f3_sfd__h793195[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d13437 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d13813) ? 11'd0 : - _theResult___fst_exp__h830845 ; - assign _theResult___fst_exp__h830854 = - (f3_exp__h793197 == 8'd0) ? - _theResult___fst_exp__h830851 : - _theResult___fst_exp__h830806 ; - assign _theResult___fst_exp__h831634 = + _theResult___fst_exp__h830842 ; + assign _theResult___fst_exp__h830851 = + (f3_exp__h793194 == 8'd0) ? + _theResult___fst_exp__h830848 : + _theResult___fst_exp__h830803 ; + assign _theResult___fst_exp__h831631 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard22864_0b0_theResult___fst_exp30854_0_ETC__q204 : + CASE_guard22861_0b0_theResult___fst_exp30851_0_ETC__q202 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13954 ; - assign _theResult___fst_exp__h831637 = - (_theResult___fst_exp__h830854 == 11'd2047) ? - _theResult___fst_exp__h830854 : - _theResult___fst_exp__h831634 ; - assign _theResult___fst_exp__h831646 = - (f3_exp__h793197 == 8'd0) ? + assign _theResult___fst_exp__h831634 = + (_theResult___fst_exp__h830851 == 11'd2047) ? + _theResult___fst_exp__h830851 : + _theResult___fst_exp__h831631 ; + assign _theResult___fst_exp__h831643 = + (f3_exp__h793194 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13391 ? - _theResult___snd_fst_exp__h813205 : - _theResult___fst_exp__h797371) : + _theResult___snd_fst_exp__h813202 : + _theResult___fst_exp__h797368) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13513 ? - _theResult___snd_fst_exp__h831640 : - _theResult___fst_exp__h797371) ; - assign _theResult___fst_exp__h831649 = - (f3_exp__h793197 == 8'd0 && f3_sfd__h793198 == 23'd0) ? + _theResult___snd_fst_exp__h831637 : + _theResult___fst_exp__h797368) ; + assign _theResult___fst_exp__h831646 = + (f3_exp__h793194 == 8'd0 && f3_sfd__h793195 == 23'd0) ? 11'd0 : - _theResult___fst_exp__h831646 ; - assign _theResult___fst_sfd__h585163 = - (_theResult___fst_exp__h584565 == 8'd255) ? - sfdin__h584559[56:34] : - _theResult___fst_sfd__h585160 ; - assign _theResult___fst_sfd__h593745 = - (_theResult___fst_exp__h593221 == 8'd255) ? - _theResult___snd__h593172[56:34] : - _theResult___fst_sfd__h593742 ; - assign _theResult___fst_sfd__h602929 = - (_theResult___fst_exp__h602331 == 8'd255) ? - sfdin__h602325[56:34] : - _theResult___fst_sfd__h602926 ; - assign _theResult___fst_sfd__h611565 = - (_theResult___fst_exp__h611016 == 8'd255) ? - _theResult___snd__h610962[56:34] : - _theResult___fst_sfd__h611562 ; - assign _theResult___fst_sfd__h611574 = + _theResult___fst_exp__h831643 ; + assign _theResult___fst_sfd__h585161 = + (_theResult___fst_exp__h584563 == 8'd255) ? + sfdin__h584557[56:34] : + _theResult___fst_sfd__h585158 ; + assign _theResult___fst_sfd__h593743 = + (_theResult___fst_exp__h593219 == 8'd255) ? + _theResult___snd__h593170[56:34] : + _theResult___fst_sfd__h593740 ; + assign _theResult___fst_sfd__h602927 = + (_theResult___fst_exp__h602329 == 8'd255) ? + sfdin__h602323[56:34] : + _theResult___fst_sfd__h602924 ; + assign _theResult___fst_sfd__h611563 = + (_theResult___fst_exp__h611014 == 8'd255) ? + _theResult___snd__h610960[56:34] : + _theResult___fst_sfd__h611560 ; + assign _theResult___fst_sfd__h611572 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8135 ? - _theResult___snd_fst_sfd__h593748 : - _theResult___fst_sfd__h576437) : + _theResult___snd_fst_sfd__h593746 : + _theResult___fst_sfd__h576435) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8675 ? - _theResult___snd_fst_sfd__h611568 : - _theResult___fst_sfd__h576437) ; - assign _theResult___fst_sfd__h611580 = + _theResult___snd_fst_sfd__h611566 : + _theResult___fst_sfd__h576435) ; + assign _theResult___fst_sfd__h611578 = ((coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == @@ -31404,33 +31399,33 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == 52'd0) ? 23'd0 : - _theResult___fst_sfd__h611574 ; - assign _theResult___fst_sfd__h630912 = - (_theResult___fst_exp__h630314 == 8'd255) ? - sfdin__h630308[56:34] : - _theResult___fst_sfd__h630909 ; - assign _theResult___fst_sfd__h639494 = - (_theResult___fst_exp__h638970 == 8'd255) ? - _theResult___snd__h638921[56:34] : - _theResult___fst_sfd__h639491 ; - assign _theResult___fst_sfd__h648678 = - (_theResult___fst_exp__h648080 == 8'd255) ? - sfdin__h648074[56:34] : - _theResult___fst_sfd__h648675 ; - assign _theResult___fst_sfd__h657314 = - (_theResult___fst_exp__h656765 == 8'd255) ? - _theResult___snd__h656711[56:34] : - _theResult___fst_sfd__h657311 ; - assign _theResult___fst_sfd__h657323 = + _theResult___fst_sfd__h611572 ; + assign _theResult___fst_sfd__h630910 = + (_theResult___fst_exp__h630312 == 8'd255) ? + sfdin__h630306[56:34] : + _theResult___fst_sfd__h630907 ; + assign _theResult___fst_sfd__h639492 = + (_theResult___fst_exp__h638968 == 8'd255) ? + _theResult___snd__h638919[56:34] : + _theResult___fst_sfd__h639489 ; + assign _theResult___fst_sfd__h648676 = + (_theResult___fst_exp__h648078 == 8'd255) ? + sfdin__h648072[56:34] : + _theResult___fst_sfd__h648673 ; + assign _theResult___fst_sfd__h657312 = + (_theResult___fst_exp__h656763 == 8'd255) ? + _theResult___snd__h656709[56:34] : + _theResult___fst_sfd__h657309 ; + assign _theResult___fst_sfd__h657321 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9532 ? - _theResult___snd_fst_sfd__h639497 : - _theResult___fst_sfd__h622188) : + _theResult___snd_fst_sfd__h639495 : + _theResult___fst_sfd__h622186) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10072 ? - _theResult___snd_fst_sfd__h657317 : - _theResult___fst_sfd__h622188) ; - assign _theResult___fst_sfd__h657329 = + _theResult___snd_fst_sfd__h657315 : + _theResult___fst_sfd__h622186) ; + assign _theResult___fst_sfd__h657327 = ((coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == @@ -31438,33 +31433,33 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == 52'd0) ? 23'd0 : - _theResult___fst_sfd__h657323 ; - assign _theResult___fst_sfd__h676659 = - (_theResult___fst_exp__h676061 == 8'd255) ? - sfdin__h676055[56:34] : - _theResult___fst_sfd__h676656 ; - assign _theResult___fst_sfd__h685241 = - (_theResult___fst_exp__h684717 == 8'd255) ? - _theResult___snd__h684668[56:34] : - _theResult___fst_sfd__h685238 ; - assign _theResult___fst_sfd__h694425 = - (_theResult___fst_exp__h693827 == 8'd255) ? - sfdin__h693821[56:34] : - _theResult___fst_sfd__h694422 ; - assign _theResult___fst_sfd__h703061 = - (_theResult___fst_exp__h702512 == 8'd255) ? - _theResult___snd__h702458[56:34] : - _theResult___fst_sfd__h703058 ; - assign _theResult___fst_sfd__h703070 = + _theResult___fst_sfd__h657321 ; + assign _theResult___fst_sfd__h676657 = + (_theResult___fst_exp__h676059 == 8'd255) ? + sfdin__h676053[56:34] : + _theResult___fst_sfd__h676654 ; + assign _theResult___fst_sfd__h685239 = + (_theResult___fst_exp__h684715 == 8'd255) ? + _theResult___snd__h684666[56:34] : + _theResult___fst_sfd__h685236 ; + assign _theResult___fst_sfd__h694423 = + (_theResult___fst_exp__h693825 == 8'd255) ? + sfdin__h693819[56:34] : + _theResult___fst_sfd__h694420 ; + assign _theResult___fst_sfd__h703059 = + (_theResult___fst_exp__h702510 == 8'd255) ? + _theResult___snd__h702456[56:34] : + _theResult___fst_sfd__h703056 ; + assign _theResult___fst_sfd__h703068 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10929 ? - _theResult___snd_fst_sfd__h685244 : - _theResult___fst_sfd__h667935) : + _theResult___snd_fst_sfd__h685242 : + _theResult___fst_sfd__h667933) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11469 ? - _theResult___snd_fst_sfd__h703064 : - _theResult___fst_sfd__h667935) ; - assign _theResult___fst_sfd__h703076 = + _theResult___snd_fst_sfd__h703062 : + _theResult___fst_sfd__h667933) ; + assign _theResult___fst_sfd__h703074 = ((coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == @@ -31472,1441 +31467,1441 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == 52'd0) ? 23'd0 : - _theResult___fst_sfd__h703070 ; - assign _theResult___fst_sfd__h719215 = + _theResult___fst_sfd__h703068 ; + assign _theResult___fst_sfd__h719212 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q28 ; - assign _theResult___fst_sfd__h735043 = + assign _theResult___fst_sfd__h735040 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard26326_0b0_theResult___snd34238_BITS__ETC__q228 : + CASE_guard26323_0b0_theResult___snd34235_BITS__ETC__q226 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13270 ; - assign _theResult___fst_sfd__h735046 = - (_theResult___fst_exp__h734287 == 11'd2047) ? - _theResult___snd__h734238[56:5] : - _theResult___fst_sfd__h735043 ; - assign _theResult___fst_sfd__h744694 = + assign _theResult___fst_sfd__h735043 = + (_theResult___fst_exp__h734284 == 11'd2047) ? + _theResult___snd__h734235[56:5] : + _theResult___fst_sfd__h735040 ; + assign _theResult___fst_sfd__h744691 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard35638_0b0_sfdin43858_BITS_56_TO_5_0b_ETC__q230 : + CASE_guard35635_0b0_sfdin43855_BITS_56_TO_5_0b_ETC__q230 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13297 ; - assign _theResult___fst_sfd__h744697 = - (_theResult___fst_exp__h743864 == 11'd2047) ? - sfdin__h743858[56:5] : - _theResult___fst_sfd__h744694 ; - assign _theResult___fst_sfd__h753478 = + assign _theResult___fst_sfd__h744694 = + (_theResult___fst_exp__h743861 == 11'd2047) ? + sfdin__h743855[56:5] : + _theResult___fst_sfd__h744691 ; + assign _theResult___fst_sfd__h753475 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard44707_0b0_theResult___snd52643_BITS__ETC__q232 : + CASE_guard44704_0b0_theResult___snd52640_BITS__ETC__q232 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13316 ; - assign _theResult___fst_sfd__h753481 = - (_theResult___fst_exp__h752697 == 11'd2047) ? - _theResult___snd__h752643[56:5] : - _theResult___fst_sfd__h753478 ; - assign _theResult___fst_sfd__h753490 = - (f1_exp__h714899 == 8'd0) ? + assign _theResult___fst_sfd__h753478 = + (_theResult___fst_exp__h752694 == 11'd2047) ? + _theResult___snd__h752640[56:5] : + _theResult___fst_sfd__h753475 ; + assign _theResult___fst_sfd__h753487 = + (f1_exp__h714896 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12661 ? - _theResult___snd_fst_sfd__h735049 : - _theResult___fst_sfd__h719215) : + _theResult___snd_fst_sfd__h735046 : + _theResult___fst_sfd__h719212) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12798 ? - _theResult___snd_fst_sfd__h753484 : - _theResult___fst_sfd__h719215) ; - assign _theResult___fst_sfd__h753496 = - ((f1_exp__h714899 == 8'd255 || f1_exp__h714899 == 8'd0) && - f1_sfd__h714900 == 23'd0) ? + _theResult___snd_fst_sfd__h753481 : + _theResult___fst_sfd__h719212) ; + assign _theResult___fst_sfd__h753493 = + ((f1_exp__h714896 == 8'd255 || f1_exp__h714896 == 8'd0) && + f1_sfd__h714897 == 23'd0) ? 52'd0 : - _theResult___fst_sfd__h753490 ; - assign _theResult___fst_sfd__h758068 = + _theResult___fst_sfd__h753487 ; + assign _theResult___fst_sfd__h758065 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q30 ; - assign _theResult___fst_sfd__h773896 = + assign _theResult___fst_sfd__h773893 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard65179_0b0_theResult___snd73091_BITS__ETC__q218 : + CASE_guard65176_0b0_theResult___snd73088_BITS__ETC__q218 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14750 ; - assign _theResult___fst_sfd__h773899 = - (_theResult___fst_exp__h773140 == 11'd2047) ? - _theResult___snd__h773091[56:5] : - _theResult___fst_sfd__h773896 ; - assign _theResult___fst_sfd__h783547 = + assign _theResult___fst_sfd__h773896 = + (_theResult___fst_exp__h773137 == 11'd2047) ? + _theResult___snd__h773088[56:5] : + _theResult___fst_sfd__h773893 ; + assign _theResult___fst_sfd__h783544 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard74491_0b0_sfdin82711_BITS_56_TO_5_0b_ETC__q220 : + CASE_guard74488_0b0_sfdin82708_BITS_56_TO_5_0b_ETC__q220 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14776 ; - assign _theResult___fst_sfd__h783550 = - (_theResult___fst_exp__h782717 == 11'd2047) ? - sfdin__h782711[56:5] : - _theResult___fst_sfd__h783547 ; - assign _theResult___fst_sfd__h792331 = + assign _theResult___fst_sfd__h783547 = + (_theResult___fst_exp__h782714 == 11'd2047) ? + sfdin__h782708[56:5] : + _theResult___fst_sfd__h783544 ; + assign _theResult___fst_sfd__h792328 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard83560_0b0_theResult___snd91496_BITS__ETC__q222 : + CASE_guard83557_0b0_theResult___snd91493_BITS__ETC__q222 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14795 ; - assign _theResult___fst_sfd__h792334 = - (_theResult___fst_exp__h791550 == 11'd2047) ? - _theResult___snd__h791496[56:5] : - _theResult___fst_sfd__h792331 ; - assign _theResult___fst_sfd__h792343 = - (f2_exp__h753893 == 8'd0) ? + assign _theResult___fst_sfd__h792331 = + (_theResult___fst_exp__h791547 == 11'd2047) ? + _theResult___snd__h791493[56:5] : + _theResult___fst_sfd__h792328 ; + assign _theResult___fst_sfd__h792340 = + (f2_exp__h753890 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14161 ? - _theResult___snd_fst_sfd__h773902 : - _theResult___fst_sfd__h758068) : + _theResult___snd_fst_sfd__h773899 : + _theResult___fst_sfd__h758065) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14283 ? - _theResult___snd_fst_sfd__h792337 : - _theResult___fst_sfd__h758068) ; - assign _theResult___fst_sfd__h792349 = - ((f2_exp__h753893 == 8'd255 || f2_exp__h753893 == 8'd0) && - f2_sfd__h753894 == 23'd0) ? + _theResult___snd_fst_sfd__h792334 : + _theResult___fst_sfd__h758065) ; + assign _theResult___fst_sfd__h792346 = + ((f2_exp__h753890 == 8'd255 || f2_exp__h753890 == 8'd0) && + f2_sfd__h753891 == 23'd0) ? 52'd0 : - _theResult___fst_sfd__h792343 ; - assign _theResult___fst_sfd__h797372 = + _theResult___fst_sfd__h792340 ; + assign _theResult___fst_sfd__h797369 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q32 ; - assign _theResult___fst_sfd__h813200 = + assign _theResult___fst_sfd__h813197 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard04483_0b0_theResult___snd12395_BITS__ETC__q234 : + CASE_guard04480_0b0_theResult___snd12392_BITS__ETC__q234 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13980 ; - assign _theResult___fst_sfd__h813203 = - (_theResult___fst_exp__h812444 == 11'd2047) ? - _theResult___snd__h812395[56:5] : - _theResult___fst_sfd__h813200 ; - assign _theResult___fst_sfd__h822851 = + assign _theResult___fst_sfd__h813200 = + (_theResult___fst_exp__h812441 == 11'd2047) ? + _theResult___snd__h812392[56:5] : + _theResult___fst_sfd__h813197 ; + assign _theResult___fst_sfd__h822848 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard13795_0b0_sfdin22015_BITS_56_TO_5_0b_ETC__q236 : + CASE_guard13792_0b0_sfdin22012_BITS_56_TO_5_0b_ETC__q236 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14006 ; - assign _theResult___fst_sfd__h822854 = - (_theResult___fst_exp__h822021 == 11'd2047) ? - sfdin__h822015[56:5] : - _theResult___fst_sfd__h822851 ; - assign _theResult___fst_sfd__h831635 = + assign _theResult___fst_sfd__h822851 = + (_theResult___fst_exp__h822018 == 11'd2047) ? + sfdin__h822012[56:5] : + _theResult___fst_sfd__h822848 ; + assign _theResult___fst_sfd__h831632 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard22864_0b0_theResult___snd30800_BITS__ETC__q238 : + CASE_guard22861_0b0_theResult___snd30797_BITS__ETC__q238 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14025 ; - assign _theResult___fst_sfd__h831638 = - (_theResult___fst_exp__h830854 == 11'd2047) ? - _theResult___snd__h830800[56:5] : - _theResult___fst_sfd__h831635 ; - assign _theResult___fst_sfd__h831647 = - (f3_exp__h793197 == 8'd0) ? + assign _theResult___fst_sfd__h831635 = + (_theResult___fst_exp__h830851 == 11'd2047) ? + _theResult___snd__h830797[56:5] : + _theResult___fst_sfd__h831632 ; + assign _theResult___fst_sfd__h831644 = + (f3_exp__h793194 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13391 ? - _theResult___snd_fst_sfd__h813206 : - _theResult___fst_sfd__h797372) : + _theResult___snd_fst_sfd__h813203 : + _theResult___fst_sfd__h797369) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13513 ? - _theResult___snd_fst_sfd__h831641 : - _theResult___fst_sfd__h797372) ; - assign _theResult___fst_sfd__h831653 = - ((f3_exp__h793197 == 8'd255 || f3_exp__h793197 == 8'd0) && - f3_sfd__h793198 == 23'd0) ? + _theResult___snd_fst_sfd__h831638 : + _theResult___fst_sfd__h797369) ; + assign _theResult___fst_sfd__h831650 = + ((f3_exp__h793194 == 8'd255 || f3_exp__h793194 == 8'd0) && + f3_sfd__h793195 == 23'd0) ? 52'd0 : - _theResult___fst_sfd__h831647 ; - assign _theResult___sfd__h585082 = - sfd__h584657[24] ? - ((_theResult___fst_exp__h584565 == 8'd254) ? + _theResult___fst_sfd__h831644 ; + assign _theResult___sfd__h585080 = + sfd__h584655[24] ? + ((_theResult___fst_exp__h584563 == 8'd254) ? 23'd0 : - sfd__h584657[23:1]) : - sfd__h584657[22:0] ; - assign _theResult___sfd__h593664 = - sfd__h593239[24] ? - ((_theResult___fst_exp__h593221 == 8'd254) ? + sfd__h584655[23:1]) : + sfd__h584655[22:0] ; + assign _theResult___sfd__h593662 = + sfd__h593237[24] ? + ((_theResult___fst_exp__h593219 == 8'd254) ? 23'd0 : - sfd__h593239[23:1]) : - sfd__h593239[22:0] ; - assign _theResult___sfd__h602848 = - sfd__h602423[24] ? - ((_theResult___fst_exp__h602331 == 8'd254) ? + sfd__h593237[23:1]) : + sfd__h593237[22:0] ; + assign _theResult___sfd__h602846 = + sfd__h602421[24] ? + ((_theResult___fst_exp__h602329 == 8'd254) ? 23'd0 : - sfd__h602423[23:1]) : - sfd__h602423[22:0] ; - assign _theResult___sfd__h611484 = - sfd__h611035[24] ? - ((_theResult___fst_exp__h611016 == 8'd254) ? + sfd__h602421[23:1]) : + sfd__h602421[22:0] ; + assign _theResult___sfd__h611482 = + sfd__h611033[24] ? + ((_theResult___fst_exp__h611014 == 8'd254) ? 23'd0 : - sfd__h611035[23:1]) : - sfd__h611035[22:0] ; - assign _theResult___sfd__h611586 = + sfd__h611033[23:1]) : + sfd__h611033[22:0] ; + assign _theResult___sfd__h611584 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h568799 : - _theResult___fst_sfd__h611580 ; - assign _theResult___sfd__h630831 = - sfd__h630406[24] ? - ((_theResult___fst_exp__h630314 == 8'd254) ? + _theResult___snd_fst_sfd__h568797 : + _theResult___fst_sfd__h611578 ; + assign _theResult___sfd__h630829 = + sfd__h630404[24] ? + ((_theResult___fst_exp__h630312 == 8'd254) ? 23'd0 : - sfd__h630406[23:1]) : - sfd__h630406[22:0] ; - assign _theResult___sfd__h639413 = - sfd__h638988[24] ? - ((_theResult___fst_exp__h638970 == 8'd254) ? + sfd__h630404[23:1]) : + sfd__h630404[22:0] ; + assign _theResult___sfd__h639411 = + sfd__h638986[24] ? + ((_theResult___fst_exp__h638968 == 8'd254) ? 23'd0 : - sfd__h638988[23:1]) : - sfd__h638988[22:0] ; - assign _theResult___sfd__h648597 = - sfd__h648172[24] ? - ((_theResult___fst_exp__h648080 == 8'd254) ? + sfd__h638986[23:1]) : + sfd__h638986[22:0] ; + assign _theResult___sfd__h648595 = + sfd__h648170[24] ? + ((_theResult___fst_exp__h648078 == 8'd254) ? 23'd0 : - sfd__h648172[23:1]) : - sfd__h648172[22:0] ; - assign _theResult___sfd__h657233 = - sfd__h656784[24] ? - ((_theResult___fst_exp__h656765 == 8'd254) ? + sfd__h648170[23:1]) : + sfd__h648170[22:0] ; + assign _theResult___sfd__h657231 = + sfd__h656782[24] ? + ((_theResult___fst_exp__h656763 == 8'd254) ? 23'd0 : - sfd__h656784[23:1]) : - sfd__h656784[22:0] ; - assign _theResult___sfd__h657335 = + sfd__h656782[23:1]) : + sfd__h656782[22:0] ; + assign _theResult___sfd__h657333 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h614553 : - _theResult___fst_sfd__h657329 ; - assign _theResult___sfd__h676578 = - sfd__h676153[24] ? - ((_theResult___fst_exp__h676061 == 8'd254) ? + _theResult___snd_fst_sfd__h614551 : + _theResult___fst_sfd__h657327 ; + assign _theResult___sfd__h676576 = + sfd__h676151[24] ? + ((_theResult___fst_exp__h676059 == 8'd254) ? 23'd0 : - sfd__h676153[23:1]) : - sfd__h676153[22:0] ; - assign _theResult___sfd__h685160 = - sfd__h684735[24] ? - ((_theResult___fst_exp__h684717 == 8'd254) ? + sfd__h676151[23:1]) : + sfd__h676151[22:0] ; + assign _theResult___sfd__h685158 = + sfd__h684733[24] ? + ((_theResult___fst_exp__h684715 == 8'd254) ? 23'd0 : - sfd__h684735[23:1]) : - sfd__h684735[22:0] ; - assign _theResult___sfd__h694344 = - sfd__h693919[24] ? - ((_theResult___fst_exp__h693827 == 8'd254) ? + sfd__h684733[23:1]) : + sfd__h684733[22:0] ; + assign _theResult___sfd__h694342 = + sfd__h693917[24] ? + ((_theResult___fst_exp__h693825 == 8'd254) ? 23'd0 : - sfd__h693919[23:1]) : - sfd__h693919[22:0] ; - assign _theResult___sfd__h702980 = - sfd__h702531[24] ? - ((_theResult___fst_exp__h702512 == 8'd254) ? + sfd__h693917[23:1]) : + sfd__h693917[22:0] ; + assign _theResult___sfd__h702978 = + sfd__h702529[24] ? + ((_theResult___fst_exp__h702510 == 8'd254) ? 23'd0 : - sfd__h702531[23:1]) : - sfd__h702531[22:0] ; - assign _theResult___sfd__h703082 = + sfd__h702529[23:1]) : + sfd__h702529[22:0] ; + assign _theResult___sfd__h703080 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h660300 : - _theResult___fst_sfd__h703076 ; - assign _theResult___sfd__h734943 = - sfd__h734305[53] ? - ((_theResult___fst_exp__h734287 == 11'd2046) ? + _theResult___snd_fst_sfd__h660298 : + _theResult___fst_sfd__h703074 ; + assign _theResult___sfd__h734940 = + sfd__h734302[53] ? + ((_theResult___fst_exp__h734284 == 11'd2046) ? 52'd0 : - sfd__h734305[52:1]) : - sfd__h734305[51:0] ; - assign _theResult___sfd__h744594 = - sfd__h743956[53] ? - ((_theResult___fst_exp__h743864 == 11'd2046) ? + sfd__h734302[52:1]) : + sfd__h734302[51:0] ; + assign _theResult___sfd__h744591 = + sfd__h743953[53] ? + ((_theResult___fst_exp__h743861 == 11'd2046) ? 52'd0 : - sfd__h743956[52:1]) : - sfd__h743956[51:0] ; - assign _theResult___sfd__h753378 = - sfd__h752716[53] ? - ((_theResult___fst_exp__h752697 == 11'd2046) ? + sfd__h743953[52:1]) : + sfd__h743953[51:0] ; + assign _theResult___sfd__h753375 = + sfd__h752713[53] ? + ((_theResult___fst_exp__h752694 == 11'd2046) ? 52'd0 : - sfd__h752716[52:1]) : - sfd__h752716[51:0] ; - assign _theResult___sfd__h773796 = - sfd__h773158[53] ? - ((_theResult___fst_exp__h773140 == 11'd2046) ? + sfd__h752713[52:1]) : + sfd__h752713[51:0] ; + assign _theResult___sfd__h773793 = + sfd__h773155[53] ? + ((_theResult___fst_exp__h773137 == 11'd2046) ? 52'd0 : - sfd__h773158[52:1]) : - sfd__h773158[51:0] ; - assign _theResult___sfd__h783447 = - sfd__h782809[53] ? - ((_theResult___fst_exp__h782717 == 11'd2046) ? + sfd__h773155[52:1]) : + sfd__h773155[51:0] ; + assign _theResult___sfd__h783444 = + sfd__h782806[53] ? + ((_theResult___fst_exp__h782714 == 11'd2046) ? 52'd0 : - sfd__h782809[52:1]) : - sfd__h782809[51:0] ; - assign _theResult___sfd__h792231 = - sfd__h791569[53] ? - ((_theResult___fst_exp__h791550 == 11'd2046) ? + sfd__h782806[52:1]) : + sfd__h782806[51:0] ; + assign _theResult___sfd__h792228 = + sfd__h791566[53] ? + ((_theResult___fst_exp__h791547 == 11'd2046) ? 52'd0 : - sfd__h791569[52:1]) : - sfd__h791569[51:0] ; - assign _theResult___sfd__h813100 = - sfd__h812462[53] ? - ((_theResult___fst_exp__h812444 == 11'd2046) ? + sfd__h791566[52:1]) : + sfd__h791566[51:0] ; + assign _theResult___sfd__h813097 = + sfd__h812459[53] ? + ((_theResult___fst_exp__h812441 == 11'd2046) ? 52'd0 : - sfd__h812462[52:1]) : - sfd__h812462[51:0] ; - assign _theResult___sfd__h822751 = - sfd__h822113[53] ? - ((_theResult___fst_exp__h822021 == 11'd2046) ? + sfd__h812459[52:1]) : + sfd__h812459[51:0] ; + assign _theResult___sfd__h822748 = + sfd__h822110[53] ? + ((_theResult___fst_exp__h822018 == 11'd2046) ? 52'd0 : - sfd__h822113[52:1]) : - sfd__h822113[51:0] ; - assign _theResult___sfd__h831535 = - sfd__h830873[53] ? - ((_theResult___fst_exp__h830854 == 11'd2046) ? + sfd__h822110[52:1]) : + sfd__h822110[51:0] ; + assign _theResult___sfd__h831532 = + sfd__h830870[53] ? + ((_theResult___fst_exp__h830851 == 11'd2046) ? 52'd0 : - sfd__h830873[52:1]) : - sfd__h830873[51:0] ; - assign _theResult___snd__h584576 = { _theResult____h576454[55:0], 1'd0 } ; - assign _theResult___snd__h584587 = - (!_theResult____h576454[56] && _theResult____h576454[55]) ? - _theResult___snd__h584589 : - _theResult___snd__h584599 ; - assign _theResult___snd__h584589 = { _theResult____h576454[54:0], 2'd0 } ; - assign _theResult___snd__h584599 = - (!_theResult____h576454[56] && !_theResult____h576454[55] && - !_theResult____h576454[54] && - !_theResult____h576454[53] && - !_theResult____h576454[52] && - !_theResult____h576454[51] && - !_theResult____h576454[50] && - !_theResult____h576454[49] && - !_theResult____h576454[48] && - !_theResult____h576454[47] && - !_theResult____h576454[46] && - !_theResult____h576454[45] && - !_theResult____h576454[44] && - !_theResult____h576454[43] && - !_theResult____h576454[42] && - !_theResult____h576454[41] && - !_theResult____h576454[40] && - !_theResult____h576454[39] && - !_theResult____h576454[38] && - !_theResult____h576454[37] && - !_theResult____h576454[36] && - !_theResult____h576454[35] && - !_theResult____h576454[34] && - !_theResult____h576454[33] && - !_theResult____h576454[32] && - !_theResult____h576454[31] && - !_theResult____h576454[30] && - !_theResult____h576454[29] && - !_theResult____h576454[28] && - !_theResult____h576454[27] && - !_theResult____h576454[26] && - !_theResult____h576454[25] && - !_theResult____h576454[24] && - !_theResult____h576454[23] && - !_theResult____h576454[22] && - !_theResult____h576454[21] && - !_theResult____h576454[20] && - !_theResult____h576454[19] && - !_theResult____h576454[18] && - !_theResult____h576454[17] && - !_theResult____h576454[16] && - !_theResult____h576454[15] && - !_theResult____h576454[14] && - !_theResult____h576454[13] && - !_theResult____h576454[12] && - !_theResult____h576454[11] && - !_theResult____h576454[10] && - !_theResult____h576454[9] && - !_theResult____h576454[8] && - !_theResult____h576454[7] && - !_theResult____h576454[6] && - !_theResult____h576454[5] && - !_theResult____h576454[4] && - !_theResult____h576454[3] && - !_theResult____h576454[2] && - !_theResult____h576454[1] && - !_theResult____h576454[0]) ? - _theResult____h576454 : - _theResult___snd__h584605 ; - assign _theResult___snd__h584605 = + sfd__h830870[52:1]) : + sfd__h830870[51:0] ; + assign _theResult___snd__h584574 = { _theResult____h576452[55:0], 1'd0 } ; + assign _theResult___snd__h584585 = + (!_theResult____h576452[56] && _theResult____h576452[55]) ? + _theResult___snd__h584587 : + _theResult___snd__h584597 ; + assign _theResult___snd__h584587 = { _theResult____h576452[54:0], 2'd0 } ; + assign _theResult___snd__h584597 = + (!_theResult____h576452[56] && !_theResult____h576452[55] && + !_theResult____h576452[54] && + !_theResult____h576452[53] && + !_theResult____h576452[52] && + !_theResult____h576452[51] && + !_theResult____h576452[50] && + !_theResult____h576452[49] && + !_theResult____h576452[48] && + !_theResult____h576452[47] && + !_theResult____h576452[46] && + !_theResult____h576452[45] && + !_theResult____h576452[44] && + !_theResult____h576452[43] && + !_theResult____h576452[42] && + !_theResult____h576452[41] && + !_theResult____h576452[40] && + !_theResult____h576452[39] && + !_theResult____h576452[38] && + !_theResult____h576452[37] && + !_theResult____h576452[36] && + !_theResult____h576452[35] && + !_theResult____h576452[34] && + !_theResult____h576452[33] && + !_theResult____h576452[32] && + !_theResult____h576452[31] && + !_theResult____h576452[30] && + !_theResult____h576452[29] && + !_theResult____h576452[28] && + !_theResult____h576452[27] && + !_theResult____h576452[26] && + !_theResult____h576452[25] && + !_theResult____h576452[24] && + !_theResult____h576452[23] && + !_theResult____h576452[22] && + !_theResult____h576452[21] && + !_theResult____h576452[20] && + !_theResult____h576452[19] && + !_theResult____h576452[18] && + !_theResult____h576452[17] && + !_theResult____h576452[16] && + !_theResult____h576452[15] && + !_theResult____h576452[14] && + !_theResult____h576452[13] && + !_theResult____h576452[12] && + !_theResult____h576452[11] && + !_theResult____h576452[10] && + !_theResult____h576452[9] && + !_theResult____h576452[8] && + !_theResult____h576452[7] && + !_theResult____h576452[6] && + !_theResult____h576452[5] && + !_theResult____h576452[4] && + !_theResult____h576452[3] && + !_theResult____h576452[2] && + !_theResult____h576452[1] && + !_theResult____h576452[0]) ? + _theResult____h576452 : + _theResult___snd__h584603 ; + assign _theResult___snd__h584603 = { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q40[54:0], 2'd0 } ; - assign _theResult___snd__h584628 = - _theResult____h576454 << + assign _theResult___snd__h584626 = + _theResult____h576452 << IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d8370 ; - assign _theResult___snd__h593172 = + assign _theResult___snd__h593170 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___snd__h593181 : - _theResult___snd__h593174 ; - assign _theResult___snd__h593174 = + _theResult___snd__h593179 : + _theResult___snd__h593172 ; + assign _theResult___snd__h593172 = { coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5], 5'd0 } ; - assign _theResult___snd__h593181 = + assign _theResult___snd__h593179 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d8546) ? - sfd__h568849 : - _theResult___snd__h593187 ; - assign _theResult___snd__h593187 = + sfd__h568847 : + _theResult___snd__h593185 ; + assign _theResult___snd__h593185 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q42[54:0], 2'd0 } ; - assign _theResult___snd__h593210 = - sfd__h568849 << + assign _theResult___snd__h593208 = + sfd__h568847 << IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d8601 ; - assign _theResult___snd__h602342 = { _theResult____h594093[55:0], 1'd0 } ; - assign _theResult___snd__h602353 = - (!_theResult____h594093[56] && _theResult____h594093[55]) ? - _theResult___snd__h602355 : - _theResult___snd__h602365 ; - assign _theResult___snd__h602355 = { _theResult____h594093[54:0], 2'd0 } ; - assign _theResult___snd__h602365 = - (!_theResult____h594093[56] && !_theResult____h594093[55] && - !_theResult____h594093[54] && - !_theResult____h594093[53] && - !_theResult____h594093[52] && - !_theResult____h594093[51] && - !_theResult____h594093[50] && - !_theResult____h594093[49] && - !_theResult____h594093[48] && - !_theResult____h594093[47] && - !_theResult____h594093[46] && - !_theResult____h594093[45] && - !_theResult____h594093[44] && - !_theResult____h594093[43] && - !_theResult____h594093[42] && - !_theResult____h594093[41] && - !_theResult____h594093[40] && - !_theResult____h594093[39] && - !_theResult____h594093[38] && - !_theResult____h594093[37] && - !_theResult____h594093[36] && - !_theResult____h594093[35] && - !_theResult____h594093[34] && - !_theResult____h594093[33] && - !_theResult____h594093[32] && - !_theResult____h594093[31] && - !_theResult____h594093[30] && - !_theResult____h594093[29] && - !_theResult____h594093[28] && - !_theResult____h594093[27] && - !_theResult____h594093[26] && - !_theResult____h594093[25] && - !_theResult____h594093[24] && - !_theResult____h594093[23] && - !_theResult____h594093[22] && - !_theResult____h594093[21] && - !_theResult____h594093[20] && - !_theResult____h594093[19] && - !_theResult____h594093[18] && - !_theResult____h594093[17] && - !_theResult____h594093[16] && - !_theResult____h594093[15] && - !_theResult____h594093[14] && - !_theResult____h594093[13] && - !_theResult____h594093[12] && - !_theResult____h594093[11] && - !_theResult____h594093[10] && - !_theResult____h594093[9] && - !_theResult____h594093[8] && - !_theResult____h594093[7] && - !_theResult____h594093[6] && - !_theResult____h594093[5] && - !_theResult____h594093[4] && - !_theResult____h594093[3] && - !_theResult____h594093[2] && - !_theResult____h594093[1] && - !_theResult____h594093[0]) ? - _theResult____h594093 : - _theResult___snd__h602371 ; - assign _theResult___snd__h602371 = + assign _theResult___snd__h602340 = { _theResult____h594091[55:0], 1'd0 } ; + assign _theResult___snd__h602351 = + (!_theResult____h594091[56] && _theResult____h594091[55]) ? + _theResult___snd__h602353 : + _theResult___snd__h602363 ; + assign _theResult___snd__h602353 = { _theResult____h594091[54:0], 2'd0 } ; + assign _theResult___snd__h602363 = + (!_theResult____h594091[56] && !_theResult____h594091[55] && + !_theResult____h594091[54] && + !_theResult____h594091[53] && + !_theResult____h594091[52] && + !_theResult____h594091[51] && + !_theResult____h594091[50] && + !_theResult____h594091[49] && + !_theResult____h594091[48] && + !_theResult____h594091[47] && + !_theResult____h594091[46] && + !_theResult____h594091[45] && + !_theResult____h594091[44] && + !_theResult____h594091[43] && + !_theResult____h594091[42] && + !_theResult____h594091[41] && + !_theResult____h594091[40] && + !_theResult____h594091[39] && + !_theResult____h594091[38] && + !_theResult____h594091[37] && + !_theResult____h594091[36] && + !_theResult____h594091[35] && + !_theResult____h594091[34] && + !_theResult____h594091[33] && + !_theResult____h594091[32] && + !_theResult____h594091[31] && + !_theResult____h594091[30] && + !_theResult____h594091[29] && + !_theResult____h594091[28] && + !_theResult____h594091[27] && + !_theResult____h594091[26] && + !_theResult____h594091[25] && + !_theResult____h594091[24] && + !_theResult____h594091[23] && + !_theResult____h594091[22] && + !_theResult____h594091[21] && + !_theResult____h594091[20] && + !_theResult____h594091[19] && + !_theResult____h594091[18] && + !_theResult____h594091[17] && + !_theResult____h594091[16] && + !_theResult____h594091[15] && + !_theResult____h594091[14] && + !_theResult____h594091[13] && + !_theResult____h594091[12] && + !_theResult____h594091[11] && + !_theResult____h594091[10] && + !_theResult____h594091[9] && + !_theResult____h594091[8] && + !_theResult____h594091[7] && + !_theResult____h594091[6] && + !_theResult____h594091[5] && + !_theResult____h594091[4] && + !_theResult____h594091[3] && + !_theResult____h594091[2] && + !_theResult____h594091[1] && + !_theResult____h594091[0]) ? + _theResult____h594091 : + _theResult___snd__h602369 ; + assign _theResult___snd__h602369 = { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q50[54:0], 2'd0 } ; - assign _theResult___snd__h602394 = - _theResult____h594093 << + assign _theResult___snd__h602392 = + _theResult____h594091 << IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d8921 ; - assign _theResult___snd__h610962 = + assign _theResult___snd__h610960 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___snd__h610976 : - _theResult___snd__h593174 ; - assign _theResult___snd__h610976 = + _theResult___snd__h610974 : + _theResult___snd__h593172 ; + assign _theResult___snd__h610974 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d8546) ? - sfd__h568849 : - _theResult___snd__h610982 ; - assign _theResult___snd__h610982 = + sfd__h568847 : + _theResult___snd__h610980 ; + assign _theResult___snd__h610980 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q55[54:0], 2'd0 } ; - assign _theResult___snd__h611000 = - sfd__h568849 << + assign _theResult___snd__h610998 = + sfd__h568847 << (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8995[8] ? 9'h0AA : IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8995) ; - assign _theResult___snd__h630325 = { _theResult____h622205[55:0], 1'd0 } ; - assign _theResult___snd__h630336 = - (!_theResult____h622205[56] && _theResult____h622205[55]) ? - _theResult___snd__h630338 : - _theResult___snd__h630348 ; - assign _theResult___snd__h630338 = { _theResult____h622205[54:0], 2'd0 } ; - assign _theResult___snd__h630348 = - (!_theResult____h622205[56] && !_theResult____h622205[55] && - !_theResult____h622205[54] && - !_theResult____h622205[53] && - !_theResult____h622205[52] && - !_theResult____h622205[51] && - !_theResult____h622205[50] && - !_theResult____h622205[49] && - !_theResult____h622205[48] && - !_theResult____h622205[47] && - !_theResult____h622205[46] && - !_theResult____h622205[45] && - !_theResult____h622205[44] && - !_theResult____h622205[43] && - !_theResult____h622205[42] && - !_theResult____h622205[41] && - !_theResult____h622205[40] && - !_theResult____h622205[39] && - !_theResult____h622205[38] && - !_theResult____h622205[37] && - !_theResult____h622205[36] && - !_theResult____h622205[35] && - !_theResult____h622205[34] && - !_theResult____h622205[33] && - !_theResult____h622205[32] && - !_theResult____h622205[31] && - !_theResult____h622205[30] && - !_theResult____h622205[29] && - !_theResult____h622205[28] && - !_theResult____h622205[27] && - !_theResult____h622205[26] && - !_theResult____h622205[25] && - !_theResult____h622205[24] && - !_theResult____h622205[23] && - !_theResult____h622205[22] && - !_theResult____h622205[21] && - !_theResult____h622205[20] && - !_theResult____h622205[19] && - !_theResult____h622205[18] && - !_theResult____h622205[17] && - !_theResult____h622205[16] && - !_theResult____h622205[15] && - !_theResult____h622205[14] && - !_theResult____h622205[13] && - !_theResult____h622205[12] && - !_theResult____h622205[11] && - !_theResult____h622205[10] && - !_theResult____h622205[9] && - !_theResult____h622205[8] && - !_theResult____h622205[7] && - !_theResult____h622205[6] && - !_theResult____h622205[5] && - !_theResult____h622205[4] && - !_theResult____h622205[3] && - !_theResult____h622205[2] && - !_theResult____h622205[1] && - !_theResult____h622205[0]) ? - _theResult____h622205 : - _theResult___snd__h630354 ; - assign _theResult___snd__h630354 = + assign _theResult___snd__h630323 = { _theResult____h622203[55:0], 1'd0 } ; + assign _theResult___snd__h630334 = + (!_theResult____h622203[56] && _theResult____h622203[55]) ? + _theResult___snd__h630336 : + _theResult___snd__h630346 ; + assign _theResult___snd__h630336 = { _theResult____h622203[54:0], 2'd0 } ; + assign _theResult___snd__h630346 = + (!_theResult____h622203[56] && !_theResult____h622203[55] && + !_theResult____h622203[54] && + !_theResult____h622203[53] && + !_theResult____h622203[52] && + !_theResult____h622203[51] && + !_theResult____h622203[50] && + !_theResult____h622203[49] && + !_theResult____h622203[48] && + !_theResult____h622203[47] && + !_theResult____h622203[46] && + !_theResult____h622203[45] && + !_theResult____h622203[44] && + !_theResult____h622203[43] && + !_theResult____h622203[42] && + !_theResult____h622203[41] && + !_theResult____h622203[40] && + !_theResult____h622203[39] && + !_theResult____h622203[38] && + !_theResult____h622203[37] && + !_theResult____h622203[36] && + !_theResult____h622203[35] && + !_theResult____h622203[34] && + !_theResult____h622203[33] && + !_theResult____h622203[32] && + !_theResult____h622203[31] && + !_theResult____h622203[30] && + !_theResult____h622203[29] && + !_theResult____h622203[28] && + !_theResult____h622203[27] && + !_theResult____h622203[26] && + !_theResult____h622203[25] && + !_theResult____h622203[24] && + !_theResult____h622203[23] && + !_theResult____h622203[22] && + !_theResult____h622203[21] && + !_theResult____h622203[20] && + !_theResult____h622203[19] && + !_theResult____h622203[18] && + !_theResult____h622203[17] && + !_theResult____h622203[16] && + !_theResult____h622203[15] && + !_theResult____h622203[14] && + !_theResult____h622203[13] && + !_theResult____h622203[12] && + !_theResult____h622203[11] && + !_theResult____h622203[10] && + !_theResult____h622203[9] && + !_theResult____h622203[8] && + !_theResult____h622203[7] && + !_theResult____h622203[6] && + !_theResult____h622203[5] && + !_theResult____h622203[4] && + !_theResult____h622203[3] && + !_theResult____h622203[2] && + !_theResult____h622203[1] && + !_theResult____h622203[0]) ? + _theResult____h622203 : + _theResult___snd__h630352 ; + assign _theResult___snd__h630352 = { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q75[54:0], 2'd0 } ; - assign _theResult___snd__h630377 = - _theResult____h622205 << + assign _theResult___snd__h630375 = + _theResult____h622203 << IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d9767 ; - assign _theResult___snd__h638921 = + assign _theResult___snd__h638919 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___snd__h638930 : - _theResult___snd__h638923 ; - assign _theResult___snd__h638923 = + _theResult___snd__h638928 : + _theResult___snd__h638921 ; + assign _theResult___snd__h638921 = { coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5], 5'd0 } ; - assign _theResult___snd__h638930 = + assign _theResult___snd__h638928 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d9943) ? - sfd__h614603 : - _theResult___snd__h638936 ; - assign _theResult___snd__h638936 = + sfd__h614601 : + _theResult___snd__h638934 ; + assign _theResult___snd__h638934 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q77[54:0], 2'd0 } ; - assign _theResult___snd__h638959 = - sfd__h614603 << + assign _theResult___snd__h638957 = + sfd__h614601 << IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d9998 ; - assign _theResult___snd__h648091 = { _theResult____h639842[55:0], 1'd0 } ; - assign _theResult___snd__h648102 = - (!_theResult____h639842[56] && _theResult____h639842[55]) ? - _theResult___snd__h648104 : - _theResult___snd__h648114 ; - assign _theResult___snd__h648104 = { _theResult____h639842[54:0], 2'd0 } ; - assign _theResult___snd__h648114 = - (!_theResult____h639842[56] && !_theResult____h639842[55] && - !_theResult____h639842[54] && - !_theResult____h639842[53] && - !_theResult____h639842[52] && - !_theResult____h639842[51] && - !_theResult____h639842[50] && - !_theResult____h639842[49] && - !_theResult____h639842[48] && - !_theResult____h639842[47] && - !_theResult____h639842[46] && - !_theResult____h639842[45] && - !_theResult____h639842[44] && - !_theResult____h639842[43] && - !_theResult____h639842[42] && - !_theResult____h639842[41] && - !_theResult____h639842[40] && - !_theResult____h639842[39] && - !_theResult____h639842[38] && - !_theResult____h639842[37] && - !_theResult____h639842[36] && - !_theResult____h639842[35] && - !_theResult____h639842[34] && - !_theResult____h639842[33] && - !_theResult____h639842[32] && - !_theResult____h639842[31] && - !_theResult____h639842[30] && - !_theResult____h639842[29] && - !_theResult____h639842[28] && - !_theResult____h639842[27] && - !_theResult____h639842[26] && - !_theResult____h639842[25] && - !_theResult____h639842[24] && - !_theResult____h639842[23] && - !_theResult____h639842[22] && - !_theResult____h639842[21] && - !_theResult____h639842[20] && - !_theResult____h639842[19] && - !_theResult____h639842[18] && - !_theResult____h639842[17] && - !_theResult____h639842[16] && - !_theResult____h639842[15] && - !_theResult____h639842[14] && - !_theResult____h639842[13] && - !_theResult____h639842[12] && - !_theResult____h639842[11] && - !_theResult____h639842[10] && - !_theResult____h639842[9] && - !_theResult____h639842[8] && - !_theResult____h639842[7] && - !_theResult____h639842[6] && - !_theResult____h639842[5] && - !_theResult____h639842[4] && - !_theResult____h639842[3] && - !_theResult____h639842[2] && - !_theResult____h639842[1] && - !_theResult____h639842[0]) ? - _theResult____h639842 : - _theResult___snd__h648120 ; - assign _theResult___snd__h648120 = + assign _theResult___snd__h648089 = { _theResult____h639840[55:0], 1'd0 } ; + assign _theResult___snd__h648100 = + (!_theResult____h639840[56] && _theResult____h639840[55]) ? + _theResult___snd__h648102 : + _theResult___snd__h648112 ; + assign _theResult___snd__h648102 = { _theResult____h639840[54:0], 2'd0 } ; + assign _theResult___snd__h648112 = + (!_theResult____h639840[56] && !_theResult____h639840[55] && + !_theResult____h639840[54] && + !_theResult____h639840[53] && + !_theResult____h639840[52] && + !_theResult____h639840[51] && + !_theResult____h639840[50] && + !_theResult____h639840[49] && + !_theResult____h639840[48] && + !_theResult____h639840[47] && + !_theResult____h639840[46] && + !_theResult____h639840[45] && + !_theResult____h639840[44] && + !_theResult____h639840[43] && + !_theResult____h639840[42] && + !_theResult____h639840[41] && + !_theResult____h639840[40] && + !_theResult____h639840[39] && + !_theResult____h639840[38] && + !_theResult____h639840[37] && + !_theResult____h639840[36] && + !_theResult____h639840[35] && + !_theResult____h639840[34] && + !_theResult____h639840[33] && + !_theResult____h639840[32] && + !_theResult____h639840[31] && + !_theResult____h639840[30] && + !_theResult____h639840[29] && + !_theResult____h639840[28] && + !_theResult____h639840[27] && + !_theResult____h639840[26] && + !_theResult____h639840[25] && + !_theResult____h639840[24] && + !_theResult____h639840[23] && + !_theResult____h639840[22] && + !_theResult____h639840[21] && + !_theResult____h639840[20] && + !_theResult____h639840[19] && + !_theResult____h639840[18] && + !_theResult____h639840[17] && + !_theResult____h639840[16] && + !_theResult____h639840[15] && + !_theResult____h639840[14] && + !_theResult____h639840[13] && + !_theResult____h639840[12] && + !_theResult____h639840[11] && + !_theResult____h639840[10] && + !_theResult____h639840[9] && + !_theResult____h639840[8] && + !_theResult____h639840[7] && + !_theResult____h639840[6] && + !_theResult____h639840[5] && + !_theResult____h639840[4] && + !_theResult____h639840[3] && + !_theResult____h639840[2] && + !_theResult____h639840[1] && + !_theResult____h639840[0]) ? + _theResult____h639840 : + _theResult___snd__h648118 ; + assign _theResult___snd__h648118 = { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q85[54:0], 2'd0 } ; - assign _theResult___snd__h648143 = - _theResult____h639842 << + assign _theResult___snd__h648141 = + _theResult____h639840 << IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d10318 ; - assign _theResult___snd__h656711 = + assign _theResult___snd__h656709 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___snd__h656725 : - _theResult___snd__h638923 ; - assign _theResult___snd__h656725 = + _theResult___snd__h656723 : + _theResult___snd__h638921 ; + assign _theResult___snd__h656723 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d9943) ? - sfd__h614603 : - _theResult___snd__h656731 ; - assign _theResult___snd__h656731 = + sfd__h614601 : + _theResult___snd__h656729 ; + assign _theResult___snd__h656729 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q90[54:0], 2'd0 } ; - assign _theResult___snd__h656749 = - sfd__h614603 << + assign _theResult___snd__h656747 = + sfd__h614601 << (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d10392[8] ? 9'h0AA : IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d10392) ; - assign _theResult___snd__h676072 = { _theResult____h667952[55:0], 1'd0 } ; - assign _theResult___snd__h676083 = - (!_theResult____h667952[56] && _theResult____h667952[55]) ? - _theResult___snd__h676085 : - _theResult___snd__h676095 ; - assign _theResult___snd__h676085 = { _theResult____h667952[54:0], 2'd0 } ; - assign _theResult___snd__h676095 = - (!_theResult____h667952[56] && !_theResult____h667952[55] && - !_theResult____h667952[54] && - !_theResult____h667952[53] && - !_theResult____h667952[52] && - !_theResult____h667952[51] && - !_theResult____h667952[50] && - !_theResult____h667952[49] && - !_theResult____h667952[48] && - !_theResult____h667952[47] && - !_theResult____h667952[46] && - !_theResult____h667952[45] && - !_theResult____h667952[44] && - !_theResult____h667952[43] && - !_theResult____h667952[42] && - !_theResult____h667952[41] && - !_theResult____h667952[40] && - !_theResult____h667952[39] && - !_theResult____h667952[38] && - !_theResult____h667952[37] && - !_theResult____h667952[36] && - !_theResult____h667952[35] && - !_theResult____h667952[34] && - !_theResult____h667952[33] && - !_theResult____h667952[32] && - !_theResult____h667952[31] && - !_theResult____h667952[30] && - !_theResult____h667952[29] && - !_theResult____h667952[28] && - !_theResult____h667952[27] && - !_theResult____h667952[26] && - !_theResult____h667952[25] && - !_theResult____h667952[24] && - !_theResult____h667952[23] && - !_theResult____h667952[22] && - !_theResult____h667952[21] && - !_theResult____h667952[20] && - !_theResult____h667952[19] && - !_theResult____h667952[18] && - !_theResult____h667952[17] && - !_theResult____h667952[16] && - !_theResult____h667952[15] && - !_theResult____h667952[14] && - !_theResult____h667952[13] && - !_theResult____h667952[12] && - !_theResult____h667952[11] && - !_theResult____h667952[10] && - !_theResult____h667952[9] && - !_theResult____h667952[8] && - !_theResult____h667952[7] && - !_theResult____h667952[6] && - !_theResult____h667952[5] && - !_theResult____h667952[4] && - !_theResult____h667952[3] && - !_theResult____h667952[2] && - !_theResult____h667952[1] && - !_theResult____h667952[0]) ? - _theResult____h667952 : - _theResult___snd__h676101 ; - assign _theResult___snd__h676101 = + assign _theResult___snd__h676070 = { _theResult____h667950[55:0], 1'd0 } ; + assign _theResult___snd__h676081 = + (!_theResult____h667950[56] && _theResult____h667950[55]) ? + _theResult___snd__h676083 : + _theResult___snd__h676093 ; + assign _theResult___snd__h676083 = { _theResult____h667950[54:0], 2'd0 } ; + assign _theResult___snd__h676093 = + (!_theResult____h667950[56] && !_theResult____h667950[55] && + !_theResult____h667950[54] && + !_theResult____h667950[53] && + !_theResult____h667950[52] && + !_theResult____h667950[51] && + !_theResult____h667950[50] && + !_theResult____h667950[49] && + !_theResult____h667950[48] && + !_theResult____h667950[47] && + !_theResult____h667950[46] && + !_theResult____h667950[45] && + !_theResult____h667950[44] && + !_theResult____h667950[43] && + !_theResult____h667950[42] && + !_theResult____h667950[41] && + !_theResult____h667950[40] && + !_theResult____h667950[39] && + !_theResult____h667950[38] && + !_theResult____h667950[37] && + !_theResult____h667950[36] && + !_theResult____h667950[35] && + !_theResult____h667950[34] && + !_theResult____h667950[33] && + !_theResult____h667950[32] && + !_theResult____h667950[31] && + !_theResult____h667950[30] && + !_theResult____h667950[29] && + !_theResult____h667950[28] && + !_theResult____h667950[27] && + !_theResult____h667950[26] && + !_theResult____h667950[25] && + !_theResult____h667950[24] && + !_theResult____h667950[23] && + !_theResult____h667950[22] && + !_theResult____h667950[21] && + !_theResult____h667950[20] && + !_theResult____h667950[19] && + !_theResult____h667950[18] && + !_theResult____h667950[17] && + !_theResult____h667950[16] && + !_theResult____h667950[15] && + !_theResult____h667950[14] && + !_theResult____h667950[13] && + !_theResult____h667950[12] && + !_theResult____h667950[11] && + !_theResult____h667950[10] && + !_theResult____h667950[9] && + !_theResult____h667950[8] && + !_theResult____h667950[7] && + !_theResult____h667950[6] && + !_theResult____h667950[5] && + !_theResult____h667950[4] && + !_theResult____h667950[3] && + !_theResult____h667950[2] && + !_theResult____h667950[1] && + !_theResult____h667950[0]) ? + _theResult____h667950 : + _theResult___snd__h676099 ; + assign _theResult___snd__h676099 = { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q110[54:0], 2'd0 } ; - assign _theResult___snd__h676124 = - _theResult____h667952 << + assign _theResult___snd__h676122 = + _theResult____h667950 << IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d11164 ; - assign _theResult___snd__h684668 = + assign _theResult___snd__h684666 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___snd__h684677 : - _theResult___snd__h684670 ; - assign _theResult___snd__h684670 = + _theResult___snd__h684675 : + _theResult___snd__h684668 ; + assign _theResult___snd__h684668 = { coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5], 5'd0 } ; - assign _theResult___snd__h684677 = + assign _theResult___snd__h684675 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d11340) ? - sfd__h660350 : - _theResult___snd__h684683 ; - assign _theResult___snd__h684683 = + sfd__h660348 : + _theResult___snd__h684681 ; + assign _theResult___snd__h684681 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q112[54:0], 2'd0 } ; - assign _theResult___snd__h684706 = - sfd__h660350 << + assign _theResult___snd__h684704 = + sfd__h660348 << IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d11395 ; - assign _theResult___snd__h693838 = { _theResult____h685589[55:0], 1'd0 } ; - assign _theResult___snd__h693849 = - (!_theResult____h685589[56] && _theResult____h685589[55]) ? - _theResult___snd__h693851 : - _theResult___snd__h693861 ; - assign _theResult___snd__h693851 = { _theResult____h685589[54:0], 2'd0 } ; - assign _theResult___snd__h693861 = - (!_theResult____h685589[56] && !_theResult____h685589[55] && - !_theResult____h685589[54] && - !_theResult____h685589[53] && - !_theResult____h685589[52] && - !_theResult____h685589[51] && - !_theResult____h685589[50] && - !_theResult____h685589[49] && - !_theResult____h685589[48] && - !_theResult____h685589[47] && - !_theResult____h685589[46] && - !_theResult____h685589[45] && - !_theResult____h685589[44] && - !_theResult____h685589[43] && - !_theResult____h685589[42] && - !_theResult____h685589[41] && - !_theResult____h685589[40] && - !_theResult____h685589[39] && - !_theResult____h685589[38] && - !_theResult____h685589[37] && - !_theResult____h685589[36] && - !_theResult____h685589[35] && - !_theResult____h685589[34] && - !_theResult____h685589[33] && - !_theResult____h685589[32] && - !_theResult____h685589[31] && - !_theResult____h685589[30] && - !_theResult____h685589[29] && - !_theResult____h685589[28] && - !_theResult____h685589[27] && - !_theResult____h685589[26] && - !_theResult____h685589[25] && - !_theResult____h685589[24] && - !_theResult____h685589[23] && - !_theResult____h685589[22] && - !_theResult____h685589[21] && - !_theResult____h685589[20] && - !_theResult____h685589[19] && - !_theResult____h685589[18] && - !_theResult____h685589[17] && - !_theResult____h685589[16] && - !_theResult____h685589[15] && - !_theResult____h685589[14] && - !_theResult____h685589[13] && - !_theResult____h685589[12] && - !_theResult____h685589[11] && - !_theResult____h685589[10] && - !_theResult____h685589[9] && - !_theResult____h685589[8] && - !_theResult____h685589[7] && - !_theResult____h685589[6] && - !_theResult____h685589[5] && - !_theResult____h685589[4] && - !_theResult____h685589[3] && - !_theResult____h685589[2] && - !_theResult____h685589[1] && - !_theResult____h685589[0]) ? - _theResult____h685589 : - _theResult___snd__h693867 ; - assign _theResult___snd__h693867 = + assign _theResult___snd__h693836 = { _theResult____h685587[55:0], 1'd0 } ; + assign _theResult___snd__h693847 = + (!_theResult____h685587[56] && _theResult____h685587[55]) ? + _theResult___snd__h693849 : + _theResult___snd__h693859 ; + assign _theResult___snd__h693849 = { _theResult____h685587[54:0], 2'd0 } ; + assign _theResult___snd__h693859 = + (!_theResult____h685587[56] && !_theResult____h685587[55] && + !_theResult____h685587[54] && + !_theResult____h685587[53] && + !_theResult____h685587[52] && + !_theResult____h685587[51] && + !_theResult____h685587[50] && + !_theResult____h685587[49] && + !_theResult____h685587[48] && + !_theResult____h685587[47] && + !_theResult____h685587[46] && + !_theResult____h685587[45] && + !_theResult____h685587[44] && + !_theResult____h685587[43] && + !_theResult____h685587[42] && + !_theResult____h685587[41] && + !_theResult____h685587[40] && + !_theResult____h685587[39] && + !_theResult____h685587[38] && + !_theResult____h685587[37] && + !_theResult____h685587[36] && + !_theResult____h685587[35] && + !_theResult____h685587[34] && + !_theResult____h685587[33] && + !_theResult____h685587[32] && + !_theResult____h685587[31] && + !_theResult____h685587[30] && + !_theResult____h685587[29] && + !_theResult____h685587[28] && + !_theResult____h685587[27] && + !_theResult____h685587[26] && + !_theResult____h685587[25] && + !_theResult____h685587[24] && + !_theResult____h685587[23] && + !_theResult____h685587[22] && + !_theResult____h685587[21] && + !_theResult____h685587[20] && + !_theResult____h685587[19] && + !_theResult____h685587[18] && + !_theResult____h685587[17] && + !_theResult____h685587[16] && + !_theResult____h685587[15] && + !_theResult____h685587[14] && + !_theResult____h685587[13] && + !_theResult____h685587[12] && + !_theResult____h685587[11] && + !_theResult____h685587[10] && + !_theResult____h685587[9] && + !_theResult____h685587[8] && + !_theResult____h685587[7] && + !_theResult____h685587[6] && + !_theResult____h685587[5] && + !_theResult____h685587[4] && + !_theResult____h685587[3] && + !_theResult____h685587[2] && + !_theResult____h685587[1] && + !_theResult____h685587[0]) ? + _theResult____h685587 : + _theResult___snd__h693865 ; + assign _theResult___snd__h693865 = { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q120[54:0], 2'd0 } ; - assign _theResult___snd__h693890 = - _theResult____h685589 << + assign _theResult___snd__h693888 = + _theResult____h685587 << IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d11715 ; - assign _theResult___snd__h702458 = + assign _theResult___snd__h702456 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___snd__h702472 : - _theResult___snd__h684670 ; - assign _theResult___snd__h702472 = + _theResult___snd__h702470 : + _theResult___snd__h684668 ; + assign _theResult___snd__h702470 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d11340) ? - sfd__h660350 : - _theResult___snd__h702478 ; - assign _theResult___snd__h702478 = + sfd__h660348 : + _theResult___snd__h702476 ; + assign _theResult___snd__h702476 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q125[54:0], 2'd0 } ; - assign _theResult___snd__h702496 = - sfd__h660350 << + assign _theResult___snd__h702494 = + sfd__h660348 << (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d11789[8] ? 9'h0AA : IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d11789) ; - assign _theResult___snd__h734238 = - (f1_exp__h714899 == 8'd0) ? - _theResult___snd__h734247 : - _theResult___snd__h734240 ; - assign _theResult___snd__h734240 = { f1_sfd__h714900, 34'd0 } ; - assign _theResult___snd__h734247 = - (f1_exp__h714899 == 8'd0 && !f1_sfd__h714900[22] && + assign _theResult___snd__h734235 = + (f1_exp__h714896 == 8'd0) ? + _theResult___snd__h734244 : + _theResult___snd__h734237 ; + assign _theResult___snd__h734237 = { f1_sfd__h714897, 34'd0 } ; + assign _theResult___snd__h734244 = + (f1_exp__h714896 == 8'd0 && !f1_sfd__h714897[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d12707) ? - sfd__h715261 : - _theResult___snd__h734253 ; - assign _theResult___snd__h734253 = + sfd__h715258 : + _theResult___snd__h734250 ; + assign _theResult___snd__h734250 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q146[54:0], 2'd0 } ; - assign _theResult___snd__h734276 = - sfd__h715261 << + assign _theResult___snd__h734273 = + sfd__h715258 << IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d12734 ; - assign _theResult___snd__h743875 = { _theResult____h735628[55:0], 1'd0 } ; - assign _theResult___snd__h743886 = - (!_theResult____h735628[56] && _theResult____h735628[55]) ? - _theResult___snd__h743888 : - _theResult___snd__h743898 ; - assign _theResult___snd__h743888 = { _theResult____h735628[54:0], 2'd0 } ; - assign _theResult___snd__h743898 = - (!_theResult____h735628[56] && !_theResult____h735628[55] && - !_theResult____h735628[54] && - !_theResult____h735628[53] && - !_theResult____h735628[52] && - !_theResult____h735628[51] && - !_theResult____h735628[50] && - !_theResult____h735628[49] && - !_theResult____h735628[48] && - !_theResult____h735628[47] && - !_theResult____h735628[46] && - !_theResult____h735628[45] && - !_theResult____h735628[44] && - !_theResult____h735628[43] && - !_theResult____h735628[42] && - !_theResult____h735628[41] && - !_theResult____h735628[40] && - !_theResult____h735628[39] && - !_theResult____h735628[38] && - !_theResult____h735628[37] && - !_theResult____h735628[36] && - !_theResult____h735628[35] && - !_theResult____h735628[34] && - !_theResult____h735628[33] && - !_theResult____h735628[32] && - !_theResult____h735628[31] && - !_theResult____h735628[30] && - !_theResult____h735628[29] && - !_theResult____h735628[28] && - !_theResult____h735628[27] && - !_theResult____h735628[26] && - !_theResult____h735628[25] && - !_theResult____h735628[24] && - !_theResult____h735628[23] && - !_theResult____h735628[22] && - !_theResult____h735628[21] && - !_theResult____h735628[20] && - !_theResult____h735628[19] && - !_theResult____h735628[18] && - !_theResult____h735628[17] && - !_theResult____h735628[16] && - !_theResult____h735628[15] && - !_theResult____h735628[14] && - !_theResult____h735628[13] && - !_theResult____h735628[12] && - !_theResult____h735628[11] && - !_theResult____h735628[10] && - !_theResult____h735628[9] && - !_theResult____h735628[8] && - !_theResult____h735628[7] && - !_theResult____h735628[6] && - !_theResult____h735628[5] && - !_theResult____h735628[4] && - !_theResult____h735628[3] && - !_theResult____h735628[2] && - !_theResult____h735628[1] && - !_theResult____h735628[0]) ? - _theResult____h735628 : - _theResult___snd__h743904 ; - assign _theResult___snd__h743904 = + assign _theResult___snd__h743872 = { _theResult____h735625[55:0], 1'd0 } ; + assign _theResult___snd__h743883 = + (!_theResult____h735625[56] && _theResult____h735625[55]) ? + _theResult___snd__h743885 : + _theResult___snd__h743895 ; + assign _theResult___snd__h743885 = { _theResult____h735625[54:0], 2'd0 } ; + assign _theResult___snd__h743895 = + (!_theResult____h735625[56] && !_theResult____h735625[55] && + !_theResult____h735625[54] && + !_theResult____h735625[53] && + !_theResult____h735625[52] && + !_theResult____h735625[51] && + !_theResult____h735625[50] && + !_theResult____h735625[49] && + !_theResult____h735625[48] && + !_theResult____h735625[47] && + !_theResult____h735625[46] && + !_theResult____h735625[45] && + !_theResult____h735625[44] && + !_theResult____h735625[43] && + !_theResult____h735625[42] && + !_theResult____h735625[41] && + !_theResult____h735625[40] && + !_theResult____h735625[39] && + !_theResult____h735625[38] && + !_theResult____h735625[37] && + !_theResult____h735625[36] && + !_theResult____h735625[35] && + !_theResult____h735625[34] && + !_theResult____h735625[33] && + !_theResult____h735625[32] && + !_theResult____h735625[31] && + !_theResult____h735625[30] && + !_theResult____h735625[29] && + !_theResult____h735625[28] && + !_theResult____h735625[27] && + !_theResult____h735625[26] && + !_theResult____h735625[25] && + !_theResult____h735625[24] && + !_theResult____h735625[23] && + !_theResult____h735625[22] && + !_theResult____h735625[21] && + !_theResult____h735625[20] && + !_theResult____h735625[19] && + !_theResult____h735625[18] && + !_theResult____h735625[17] && + !_theResult____h735625[16] && + !_theResult____h735625[15] && + !_theResult____h735625[14] && + !_theResult____h735625[13] && + !_theResult____h735625[12] && + !_theResult____h735625[11] && + !_theResult____h735625[10] && + !_theResult____h735625[9] && + !_theResult____h735625[8] && + !_theResult____h735625[7] && + !_theResult____h735625[6] && + !_theResult____h735625[5] && + !_theResult____h735625[4] && + !_theResult____h735625[3] && + !_theResult____h735625[2] && + !_theResult____h735625[1] && + !_theResult____h735625[0]) ? + _theResult____h735625 : + _theResult___snd__h743901 ; + assign _theResult___snd__h743901 = { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q150[54:0], 2'd0 } ; - assign _theResult___snd__h743927 = - _theResult____h735628 << + assign _theResult___snd__h743924 = + _theResult____h735625 << IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d13046 ; - assign _theResult___snd__h752643 = - (f1_exp__h714899 == 8'd0) ? - _theResult___snd__h752657 : - _theResult___snd__h734240 ; - assign _theResult___snd__h752657 = - (f1_exp__h714899 == 8'd0 && !f1_sfd__h714900[22] && + assign _theResult___snd__h752640 = + (f1_exp__h714896 == 8'd0) ? + _theResult___snd__h752654 : + _theResult___snd__h734237 ; + assign _theResult___snd__h752654 = + (f1_exp__h714896 == 8'd0 && !f1_sfd__h714897[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d12707) ? - sfd__h715261 : - _theResult___snd__h752663 ; - assign _theResult___snd__h752663 = + sfd__h715258 : + _theResult___snd__h752660 ; + assign _theResult___snd__h752660 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q153[54:0], 2'd0 } ; - assign _theResult___snd__h752681 = - sfd__h715261 << + assign _theResult___snd__h752678 = + sfd__h715258 << IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d13097 ; - assign _theResult___snd__h773091 = - (f2_exp__h753893 == 8'd0) ? - _theResult___snd__h773100 : - _theResult___snd__h773093 ; - assign _theResult___snd__h773093 = { f2_sfd__h753894, 34'd0 } ; - assign _theResult___snd__h773100 = - (f2_exp__h753893 == 8'd0 && !f2_sfd__h753894[22] && + assign _theResult___snd__h773088 = + (f2_exp__h753890 == 8'd0) ? + _theResult___snd__h773097 : + _theResult___snd__h773090 ; + assign _theResult___snd__h773090 = { f2_sfd__h753891, 34'd0 } ; + assign _theResult___snd__h773097 = + (f2_exp__h753890 == 8'd0 && !f2_sfd__h753891[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d14207) ? - sfd__h754255 : - _theResult___snd__h773106 ; - assign _theResult___snd__h773106 = + sfd__h754252 : + _theResult___snd__h773103 ; + assign _theResult___snd__h773103 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q186[54:0], 2'd0 } ; - assign _theResult___snd__h773129 = - sfd__h754255 << + assign _theResult___snd__h773126 = + sfd__h754252 << IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14234 ; - assign _theResult___snd__h782728 = { _theResult____h774481[55:0], 1'd0 } ; - assign _theResult___snd__h782739 = - (!_theResult____h774481[56] && _theResult____h774481[55]) ? - _theResult___snd__h782741 : - _theResult___snd__h782751 ; - assign _theResult___snd__h782741 = { _theResult____h774481[54:0], 2'd0 } ; - assign _theResult___snd__h782751 = - (!_theResult____h774481[56] && !_theResult____h774481[55] && - !_theResult____h774481[54] && - !_theResult____h774481[53] && - !_theResult____h774481[52] && - !_theResult____h774481[51] && - !_theResult____h774481[50] && - !_theResult____h774481[49] && - !_theResult____h774481[48] && - !_theResult____h774481[47] && - !_theResult____h774481[46] && - !_theResult____h774481[45] && - !_theResult____h774481[44] && - !_theResult____h774481[43] && - !_theResult____h774481[42] && - !_theResult____h774481[41] && - !_theResult____h774481[40] && - !_theResult____h774481[39] && - !_theResult____h774481[38] && - !_theResult____h774481[37] && - !_theResult____h774481[36] && - !_theResult____h774481[35] && - !_theResult____h774481[34] && - !_theResult____h774481[33] && - !_theResult____h774481[32] && - !_theResult____h774481[31] && - !_theResult____h774481[30] && - !_theResult____h774481[29] && - !_theResult____h774481[28] && - !_theResult____h774481[27] && - !_theResult____h774481[26] && - !_theResult____h774481[25] && - !_theResult____h774481[24] && - !_theResult____h774481[23] && - !_theResult____h774481[22] && - !_theResult____h774481[21] && - !_theResult____h774481[20] && - !_theResult____h774481[19] && - !_theResult____h774481[18] && - !_theResult____h774481[17] && - !_theResult____h774481[16] && - !_theResult____h774481[15] && - !_theResult____h774481[14] && - !_theResult____h774481[13] && - !_theResult____h774481[12] && - !_theResult____h774481[11] && - !_theResult____h774481[10] && - !_theResult____h774481[9] && - !_theResult____h774481[8] && - !_theResult____h774481[7] && - !_theResult____h774481[6] && - !_theResult____h774481[5] && - !_theResult____h774481[4] && - !_theResult____h774481[3] && - !_theResult____h774481[2] && - !_theResult____h774481[1] && - !_theResult____h774481[0]) ? - _theResult____h774481 : - _theResult___snd__h782757 ; - assign _theResult___snd__h782757 = + assign _theResult___snd__h782725 = { _theResult____h774478[55:0], 1'd0 } ; + assign _theResult___snd__h782736 = + (!_theResult____h774478[56] && _theResult____h774478[55]) ? + _theResult___snd__h782738 : + _theResult___snd__h782748 ; + assign _theResult___snd__h782738 = { _theResult____h774478[54:0], 2'd0 } ; + assign _theResult___snd__h782748 = + (!_theResult____h774478[56] && !_theResult____h774478[55] && + !_theResult____h774478[54] && + !_theResult____h774478[53] && + !_theResult____h774478[52] && + !_theResult____h774478[51] && + !_theResult____h774478[50] && + !_theResult____h774478[49] && + !_theResult____h774478[48] && + !_theResult____h774478[47] && + !_theResult____h774478[46] && + !_theResult____h774478[45] && + !_theResult____h774478[44] && + !_theResult____h774478[43] && + !_theResult____h774478[42] && + !_theResult____h774478[41] && + !_theResult____h774478[40] && + !_theResult____h774478[39] && + !_theResult____h774478[38] && + !_theResult____h774478[37] && + !_theResult____h774478[36] && + !_theResult____h774478[35] && + !_theResult____h774478[34] && + !_theResult____h774478[33] && + !_theResult____h774478[32] && + !_theResult____h774478[31] && + !_theResult____h774478[30] && + !_theResult____h774478[29] && + !_theResult____h774478[28] && + !_theResult____h774478[27] && + !_theResult____h774478[26] && + !_theResult____h774478[25] && + !_theResult____h774478[24] && + !_theResult____h774478[23] && + !_theResult____h774478[22] && + !_theResult____h774478[21] && + !_theResult____h774478[20] && + !_theResult____h774478[19] && + !_theResult____h774478[18] && + !_theResult____h774478[17] && + !_theResult____h774478[16] && + !_theResult____h774478[15] && + !_theResult____h774478[14] && + !_theResult____h774478[13] && + !_theResult____h774478[12] && + !_theResult____h774478[11] && + !_theResult____h774478[10] && + !_theResult____h774478[9] && + !_theResult____h774478[8] && + !_theResult____h774478[7] && + !_theResult____h774478[6] && + !_theResult____h774478[5] && + !_theResult____h774478[4] && + !_theResult____h774478[3] && + !_theResult____h774478[2] && + !_theResult____h774478[1] && + !_theResult____h774478[0]) ? + _theResult____h774478 : + _theResult___snd__h782754 ; + assign _theResult___snd__h782754 = { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q190[54:0], 2'd0 } ; - assign _theResult___snd__h782780 = - _theResult____h774481 << + assign _theResult___snd__h782777 = + _theResult____h774478 << IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d14531 ; - assign _theResult___snd__h791496 = - (f2_exp__h753893 == 8'd0) ? - _theResult___snd__h791510 : - _theResult___snd__h773093 ; - assign _theResult___snd__h791510 = - (f2_exp__h753893 == 8'd0 && !f2_sfd__h753894[22] && + assign _theResult___snd__h791493 = + (f2_exp__h753890 == 8'd0) ? + _theResult___snd__h791507 : + _theResult___snd__h773090 ; + assign _theResult___snd__h791507 = + (f2_exp__h753890 == 8'd0 && !f2_sfd__h753891[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d14207) ? - sfd__h754255 : - _theResult___snd__h791516 ; - assign _theResult___snd__h791516 = + sfd__h754252 : + _theResult___snd__h791513 ; + assign _theResult___snd__h791513 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q193[54:0], 2'd0 } ; - assign _theResult___snd__h791534 = - sfd__h754255 << + assign _theResult___snd__h791531 = + sfd__h754252 << IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d14582 ; - assign _theResult___snd__h812395 = - (f3_exp__h793197 == 8'd0) ? - _theResult___snd__h812404 : - _theResult___snd__h812397 ; - assign _theResult___snd__h812397 = { f3_sfd__h793198, 34'd0 } ; - assign _theResult___snd__h812404 = - (f3_exp__h793197 == 8'd0 && !f3_sfd__h793198[22] && + assign _theResult___snd__h812392 = + (f3_exp__h793194 == 8'd0) ? + _theResult___snd__h812401 : + _theResult___snd__h812394 ; + assign _theResult___snd__h812394 = { f3_sfd__h793195, 34'd0 } ; + assign _theResult___snd__h812401 = + (f3_exp__h793194 == 8'd0 && !f3_sfd__h793195[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d13437) ? - sfd__h793559 : - _theResult___snd__h812410 ; - assign _theResult___snd__h812410 = + sfd__h793556 : + _theResult___snd__h812407 ; + assign _theResult___snd__h812407 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q163[54:0], 2'd0 } ; - assign _theResult___snd__h812433 = - sfd__h793559 << + assign _theResult___snd__h812430 = + sfd__h793556 << IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13464 ; - assign _theResult___snd__h822032 = { _theResult____h813785[55:0], 1'd0 } ; - assign _theResult___snd__h822043 = - (!_theResult____h813785[56] && _theResult____h813785[55]) ? - _theResult___snd__h822045 : - _theResult___snd__h822055 ; - assign _theResult___snd__h822045 = { _theResult____h813785[54:0], 2'd0 } ; - assign _theResult___snd__h822055 = - (!_theResult____h813785[56] && !_theResult____h813785[55] && - !_theResult____h813785[54] && - !_theResult____h813785[53] && - !_theResult____h813785[52] && - !_theResult____h813785[51] && - !_theResult____h813785[50] && - !_theResult____h813785[49] && - !_theResult____h813785[48] && - !_theResult____h813785[47] && - !_theResult____h813785[46] && - !_theResult____h813785[45] && - !_theResult____h813785[44] && - !_theResult____h813785[43] && - !_theResult____h813785[42] && - !_theResult____h813785[41] && - !_theResult____h813785[40] && - !_theResult____h813785[39] && - !_theResult____h813785[38] && - !_theResult____h813785[37] && - !_theResult____h813785[36] && - !_theResult____h813785[35] && - !_theResult____h813785[34] && - !_theResult____h813785[33] && - !_theResult____h813785[32] && - !_theResult____h813785[31] && - !_theResult____h813785[30] && - !_theResult____h813785[29] && - !_theResult____h813785[28] && - !_theResult____h813785[27] && - !_theResult____h813785[26] && - !_theResult____h813785[25] && - !_theResult____h813785[24] && - !_theResult____h813785[23] && - !_theResult____h813785[22] && - !_theResult____h813785[21] && - !_theResult____h813785[20] && - !_theResult____h813785[19] && - !_theResult____h813785[18] && - !_theResult____h813785[17] && - !_theResult____h813785[16] && - !_theResult____h813785[15] && - !_theResult____h813785[14] && - !_theResult____h813785[13] && - !_theResult____h813785[12] && - !_theResult____h813785[11] && - !_theResult____h813785[10] && - !_theResult____h813785[9] && - !_theResult____h813785[8] && - !_theResult____h813785[7] && - !_theResult____h813785[6] && - !_theResult____h813785[5] && - !_theResult____h813785[4] && - !_theResult____h813785[3] && - !_theResult____h813785[2] && - !_theResult____h813785[1] && - !_theResult____h813785[0]) ? - _theResult____h813785 : - _theResult___snd__h822061 ; - assign _theResult___snd__h822061 = + assign _theResult___snd__h822029 = { _theResult____h813782[55:0], 1'd0 } ; + assign _theResult___snd__h822040 = + (!_theResult____h813782[56] && _theResult____h813782[55]) ? + _theResult___snd__h822042 : + _theResult___snd__h822052 ; + assign _theResult___snd__h822042 = { _theResult____h813782[54:0], 2'd0 } ; + assign _theResult___snd__h822052 = + (!_theResult____h813782[56] && !_theResult____h813782[55] && + !_theResult____h813782[54] && + !_theResult____h813782[53] && + !_theResult____h813782[52] && + !_theResult____h813782[51] && + !_theResult____h813782[50] && + !_theResult____h813782[49] && + !_theResult____h813782[48] && + !_theResult____h813782[47] && + !_theResult____h813782[46] && + !_theResult____h813782[45] && + !_theResult____h813782[44] && + !_theResult____h813782[43] && + !_theResult____h813782[42] && + !_theResult____h813782[41] && + !_theResult____h813782[40] && + !_theResult____h813782[39] && + !_theResult____h813782[38] && + !_theResult____h813782[37] && + !_theResult____h813782[36] && + !_theResult____h813782[35] && + !_theResult____h813782[34] && + !_theResult____h813782[33] && + !_theResult____h813782[32] && + !_theResult____h813782[31] && + !_theResult____h813782[30] && + !_theResult____h813782[29] && + !_theResult____h813782[28] && + !_theResult____h813782[27] && + !_theResult____h813782[26] && + !_theResult____h813782[25] && + !_theResult____h813782[24] && + !_theResult____h813782[23] && + !_theResult____h813782[22] && + !_theResult____h813782[21] && + !_theResult____h813782[20] && + !_theResult____h813782[19] && + !_theResult____h813782[18] && + !_theResult____h813782[17] && + !_theResult____h813782[16] && + !_theResult____h813782[15] && + !_theResult____h813782[14] && + !_theResult____h813782[13] && + !_theResult____h813782[12] && + !_theResult____h813782[11] && + !_theResult____h813782[10] && + !_theResult____h813782[9] && + !_theResult____h813782[8] && + !_theResult____h813782[7] && + !_theResult____h813782[6] && + !_theResult____h813782[5] && + !_theResult____h813782[4] && + !_theResult____h813782[3] && + !_theResult____h813782[2] && + !_theResult____h813782[1] && + !_theResult____h813782[0]) ? + _theResult____h813782 : + _theResult___snd__h822058 ; + assign _theResult___snd__h822058 = { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q167[54:0], 2'd0 } ; - assign _theResult___snd__h822084 = - _theResult____h813785 << + assign _theResult___snd__h822081 = + _theResult____h813782 << IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d13761 ; - assign _theResult___snd__h830800 = - (f3_exp__h793197 == 8'd0) ? - _theResult___snd__h830814 : - _theResult___snd__h812397 ; - assign _theResult___snd__h830814 = - (f3_exp__h793197 == 8'd0 && !f3_sfd__h793198[22] && + assign _theResult___snd__h830797 = + (f3_exp__h793194 == 8'd0) ? + _theResult___snd__h830811 : + _theResult___snd__h812394 ; + assign _theResult___snd__h830811 = + (f3_exp__h793194 == 8'd0 && !f3_sfd__h793195[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d13437) ? - sfd__h793559 : - _theResult___snd__h830820 ; - assign _theResult___snd__h830820 = + sfd__h793556 : + _theResult___snd__h830817 ; + assign _theResult___snd__h830817 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q170[54:0], 2'd0 } ; - assign _theResult___snd__h830838 = - sfd__h793559 << + assign _theResult___snd__h830835 = + sfd__h793556 << IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d13812 ; - assign _theResult___snd__h836130 = - b__h835708[63] ? b___1__h836179 : b__h835708 ; - assign _theResult___snd_fst_exp__h593747 = + assign _theResult___snd__h836127 = + b__h835705[63] ? b___1__h836176 : b__h835705 ; + assign _theResult___snd_fst_exp__h593745 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8136 ? - _theResult___fst_exp__h585162 : - _theResult___fst_exp__h593744 ; - assign _theResult___snd_fst_exp__h611567 = + _theResult___fst_exp__h585160 : + _theResult___fst_exp__h593742 ; + assign _theResult___snd_fst_exp__h611565 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8676 ? - _theResult___fst_exp__h602928 : - _theResult___fst_exp__h611564 ; - assign _theResult___snd_fst_exp__h639496 = + _theResult___fst_exp__h602926 : + _theResult___fst_exp__h611562 ; + assign _theResult___snd_fst_exp__h639494 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9533 ? - _theResult___fst_exp__h630911 : - _theResult___fst_exp__h639493 ; - assign _theResult___snd_fst_exp__h657316 = + _theResult___fst_exp__h630909 : + _theResult___fst_exp__h639491 ; + assign _theResult___snd_fst_exp__h657314 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10073 ? - _theResult___fst_exp__h648677 : - _theResult___fst_exp__h657313 ; - assign _theResult___snd_fst_exp__h685243 = + _theResult___fst_exp__h648675 : + _theResult___fst_exp__h657311 ; + assign _theResult___snd_fst_exp__h685241 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10930 ? - _theResult___fst_exp__h676658 : - _theResult___fst_exp__h685240 ; - assign _theResult___snd_fst_exp__h703063 = + _theResult___fst_exp__h676656 : + _theResult___fst_exp__h685238 ; + assign _theResult___snd_fst_exp__h703061 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11470 ? - _theResult___fst_exp__h694424 : - _theResult___fst_exp__h703060 ; - assign _theResult___snd_fst_exp__h735048 = + _theResult___fst_exp__h694422 : + _theResult___fst_exp__h703058 ; + assign _theResult___snd_fst_exp__h735045 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12663 ? 11'd0 : - _theResult___fst_exp__h735045 ; - assign _theResult___snd_fst_exp__h753483 = + _theResult___fst_exp__h735042 ; + assign _theResult___snd_fst_exp__h753480 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12799 ? - _theResult___fst_exp__h744696 : - _theResult___fst_exp__h753480 ; - assign _theResult___snd_fst_exp__h773901 = + _theResult___fst_exp__h744693 : + _theResult___fst_exp__h753477 ; + assign _theResult___snd_fst_exp__h773898 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14163 ? 11'd0 : - _theResult___fst_exp__h773898 ; - assign _theResult___snd_fst_exp__h792336 = + _theResult___fst_exp__h773895 ; + assign _theResult___snd_fst_exp__h792333 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14284 ? - _theResult___fst_exp__h783549 : - _theResult___fst_exp__h792333 ; - assign _theResult___snd_fst_exp__h813205 = + _theResult___fst_exp__h783546 : + _theResult___fst_exp__h792330 ; + assign _theResult___snd_fst_exp__h813202 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13393 ? 11'd0 : - _theResult___fst_exp__h813202 ; - assign _theResult___snd_fst_exp__h831640 = + _theResult___fst_exp__h813199 ; + assign _theResult___snd_fst_exp__h831637 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13514 ? - _theResult___fst_exp__h822853 : - _theResult___fst_exp__h831637 ; - assign _theResult___snd_fst_sfd__h568799 = + _theResult___fst_exp__h822850 : + _theResult___fst_exp__h831634 ; + assign _theResult___snd_fst_sfd__h568797 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:34] == 23'd0) ? 23'd2097152 : coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:34] ; - assign _theResult___snd_fst_sfd__h593748 = + assign _theResult___snd_fst_sfd__h593746 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8136 ? - _theResult___fst_sfd__h585163 : - _theResult___fst_sfd__h593745 ; - assign _theResult___snd_fst_sfd__h611568 = + _theResult___fst_sfd__h585161 : + _theResult___fst_sfd__h593743 ; + assign _theResult___snd_fst_sfd__h611566 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8676 ? - _theResult___fst_sfd__h602929 : - _theResult___fst_sfd__h611565 ; - assign _theResult___snd_fst_sfd__h614553 = + _theResult___fst_sfd__h602927 : + _theResult___fst_sfd__h611563 ; + assign _theResult___snd_fst_sfd__h614551 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:34] == 23'd0) ? 23'd2097152 : coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:34] ; - assign _theResult___snd_fst_sfd__h639497 = + assign _theResult___snd_fst_sfd__h639495 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9533 ? - _theResult___fst_sfd__h630912 : - _theResult___fst_sfd__h639494 ; - assign _theResult___snd_fst_sfd__h657317 = + _theResult___fst_sfd__h630910 : + _theResult___fst_sfd__h639492 ; + assign _theResult___snd_fst_sfd__h657315 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10073 ? - _theResult___fst_sfd__h648678 : - _theResult___fst_sfd__h657314 ; - assign _theResult___snd_fst_sfd__h660300 = + _theResult___fst_sfd__h648676 : + _theResult___fst_sfd__h657312 ; + assign _theResult___snd_fst_sfd__h660298 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:34] == 23'd0) ? 23'd2097152 : coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:34] ; - assign _theResult___snd_fst_sfd__h685244 = + assign _theResult___snd_fst_sfd__h685242 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10930 ? - _theResult___fst_sfd__h676659 : - _theResult___fst_sfd__h685241 ; - assign _theResult___snd_fst_sfd__h703064 = + _theResult___fst_sfd__h676657 : + _theResult___fst_sfd__h685239 ; + assign _theResult___snd_fst_sfd__h703062 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11470 ? - _theResult___fst_sfd__h694425 : - _theResult___fst_sfd__h703061 ; - assign _theResult___snd_fst_sfd__h715215 = - (f1_sfd__h714900 == 23'd0) ? + _theResult___fst_sfd__h694423 : + _theResult___fst_sfd__h703059 ; + assign _theResult___snd_fst_sfd__h715212 = + (f1_sfd__h714897 == 23'd0) ? 52'h4000000000000 : - out___1_sfd__h714963 ; - assign _theResult___snd_fst_sfd__h735049 = + out___1_sfd__h714960 ; + assign _theResult___snd_fst_sfd__h735046 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12663 ? 52'd0 : - _theResult___fst_sfd__h735046 ; - assign _theResult___snd_fst_sfd__h753484 = + _theResult___fst_sfd__h735043 ; + assign _theResult___snd_fst_sfd__h753481 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12799 ? - _theResult___fst_sfd__h744697 : - _theResult___fst_sfd__h753481 ; - assign _theResult___snd_fst_sfd__h754209 = - (f2_sfd__h753894 == 23'd0) ? + _theResult___fst_sfd__h744694 : + _theResult___fst_sfd__h753478 ; + assign _theResult___snd_fst_sfd__h754206 = + (f2_sfd__h753891 == 23'd0) ? 52'h4000000000000 : - out___1_sfd__h753957 ; - assign _theResult___snd_fst_sfd__h773902 = + out___1_sfd__h753954 ; + assign _theResult___snd_fst_sfd__h773899 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14163 ? 52'd0 : - _theResult___fst_sfd__h773899 ; - assign _theResult___snd_fst_sfd__h792337 = + _theResult___fst_sfd__h773896 ; + assign _theResult___snd_fst_sfd__h792334 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14284 ? - _theResult___fst_sfd__h783550 : - _theResult___fst_sfd__h792334 ; - assign _theResult___snd_fst_sfd__h793513 = - (f3_sfd__h793198 == 23'd0) ? + _theResult___fst_sfd__h783547 : + _theResult___fst_sfd__h792331 ; + assign _theResult___snd_fst_sfd__h793510 = + (f3_sfd__h793195 == 23'd0) ? 52'h4000000000000 : - out___1_sfd__h793261 ; - assign _theResult___snd_fst_sfd__h813206 = + out___1_sfd__h793258 ; + assign _theResult___snd_fst_sfd__h813203 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13393 ? 52'd0 : - _theResult___fst_sfd__h813203 ; - assign _theResult___snd_fst_sfd__h831641 = + _theResult___fst_sfd__h813200 ; + assign _theResult___snd_fst_sfd__h831638 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13514 ? - _theResult___fst_sfd__h822854 : - _theResult___fst_sfd__h831638 ; - assign a___1__h835848 = + _theResult___fst_sfd__h822851 : + _theResult___fst_sfd__h831635 ; + assign a___1__h835845 = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd1) ? { 32'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[171:140] } : { {32{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q22[31]}}, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q22 } ; - assign a___1__h836134 = 64'd0 - a__h835707 ; - assign a__h835707 = + assign a___1__h836131 = 64'd0 - a__h835704 ; + assign a__h835704 = coreFix_fpuMulDivExe_0_regToExeQ$first[227] ? - a___1__h835848 : + a___1__h835845 : coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; - assign addBase__h1008585 = - { {48{base__h895975[15]}}, base__h895975 } << + assign addBase__h1008620 = + { {48{base__h895973[15]}}, base__h895973 } << csrf_stcc_reg[33:28] ; - assign addBase__h1008988 = - { {48{base__h854220[15]}}, base__h854220 } << + assign addBase__h1009023 = + { {48{base__h854219[15]}}, base__h854219 } << IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16100 ; - assign addBase__h1009405 = - { {48{base__h896259[15]}}, base__h896259 } << + assign addBase__h1009440 = + { {48{base__h896257[15]}}, base__h896257 } << csrf_mtcc_reg[33:28] ; - assign addBase__h1009808 = - { {48{base__h855213[15]}}, base__h855213 } << + assign addBase__h1009843 = + { {48{base__h855212[15]}}, base__h855212 } << IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16252 ; - assign addBase__h1010478 = - { {48{base__h896604[15]}}, base__h896604 } << + assign addBase__h1010513 = + { {48{base__h896602[15]}}, base__h896602 } << csrf_rg_dpc[33:28] ; - assign addBase__h239864 = - { {48{base__h239699[15]}}, base__h239699 } << + assign addBase__h239861 = + { {48{base__h239696[15]}}, base__h239696 } << coreFix_memExe_regToExeQ$first[265:260] ; - assign addBase__h241021 = - { {48{base__h240856[15]}}, base__h240856 } << + assign addBase__h241018 = + { {48{base__h240853[15]}}, base__h240853 } << coreFix_memExe_regToExeQ$first[102:97] ; - assign addBase__h254645 = - { {48{base__h254480[15]}}, base__h254480 } << + assign addBase__h254642 = + { {48{base__h254477[15]}}, base__h254477 } << coreFix_memExe_dTlb$procResp[334:329] ; - assign addTop__h239973 = - { {50{x__h240072[15]}}, x__h240072 } << + assign addTop__h239970 = + { {50{x__h240069[15]}}, x__h240069 } << coreFix_memExe_regToExeQ$first[265:260] ; - assign addTop__h241130 = - { {50{x__h241229[15]}}, x__h241229 } << + assign addTop__h241127 = + { {50{x__h241226[15]}}, x__h241226 } << coreFix_memExe_regToExeQ$first[102:97] ; - assign addTop__h254754 = - { {50{x__h254853[15]}}, x__h254853 } << + assign addTop__h254751 = + { {50{x__h254850[15]}}, x__h254850 } << coreFix_memExe_dTlb$procResp[334:329] ; - assign addr__h148439 = + assign addr__h148438 = coreFix_memExe_reqLdQ_data_0_lat_0$whas ? coreFix_memExe_reqLdQ_data_0_lat_0$wget[63:0] : coreFix_memExe_reqLdQ_data_0_rl[63:0] ; - assign addr__h152015 = + assign addr__h152014 = CAN_FIRE_RL_coreFix_memExe_doIssueSB ? coreFix_memExe_reqStQ_data_0_lat_0$wget[63:0] : coreFix_memExe_reqStQ_data_0_rl[63:0] ; - assign addr__h235317 = x__h235746[63:0] + csrf_ddc_reg[149:86] ; - assign addr__h989736 = + assign addr__h235314 = x__h235743[63:0] + csrf_ddc_reg[149:86] ; + assign addr__h989734 = (rob$deqPort_0_deq_data[273:272] == 2'd1 && (rob$deqPort_0_deq_data[265:261] == 5'd1 || rob$deqPort_0_deq_data[265:261] == 5'd12)) ? rob$deqPort_0_deq_data[260:197] : rob$deqPort_0_deq_data[191:128] ; - assign address__h1000151 = { 2'd0, address__h999478 } ; - assign address__h1000495 = { 2'd0, base__h999443 } ; - assign address__h1013682 = rob$deqPort_0_deq_data[565:502] + 64'd4 ; - assign address__h999428 = base__h999389 + { 57'd0, x__h999587 } ; - assign address__h999478 = base__h999443 + { 57'd0, x__h999587 } ; - assign address__h999494 = { 2'd0, address__h999428 } ; - assign address__h999838 = { 2'd0, base__h999389 } ; - assign b___1__h835849 = + assign address__h1000186 = { 2'd0, address__h999513 } ; + assign address__h1000530 = { 2'd0, base__h999478 } ; + assign address__h1013717 = rob$deqPort_0_deq_data[565:502] + 64'd4 ; + assign address__h999463 = base__h999424 + { 57'd0, x__h999622 } ; + assign address__h999513 = base__h999478 + { 57'd0, x__h999622 } ; + assign address__h999529 = { 2'd0, address__h999463 } ; + assign address__h999873 = { 2'd0, base__h999424 } ; + assign b___1__h835846 = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? { {32{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q23[31]}}, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q23 } : { 32'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[107:76] } ; - assign b___1__h836179 = 64'd0 - b__h835708 ; - assign b__h835708 = + assign b___1__h836176 = 64'd0 - b__h835705 ; + assign b__h835705 = coreFix_fpuMulDivExe_0_regToExeQ$first[227] ? - b___1__h835849 : + b___1__h835846 : coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; - assign b_base__h127528 = + assign b_base__h127527 = { coreFix_memExe_respLrScAmoQ_data_0[77:67], ~coreFix_memExe_respLrScAmoQ_data_0[66], coreFix_memExe_respLrScAmoQ_data_0[65:64] } ; - assign b_base__h140444 = + assign b_base__h140443 = { mmio_dataRespQ_data_0[77:67], ~mmio_dataRespQ_data_0[66], mmio_dataRespQ_data_0[65:64] } ; - assign b_base__h183706 = - { x__h183399[77:67], ~x__h183399[66], x__h183399[65:64] } ; - assign b_base__h202457 = - { x__h199251[77:67], ~x__h199251[66], x__h199251[65:64] } ; - assign b_base__h217023 = + assign b_base__h183704 = + { x__h183397[77:67], ~x__h183397[66], x__h183397[65:64] } ; + assign b_base__h202455 = + { x__h199249[77:67], ~x__h199249[66], x__h199249[65:64] } ; + assign b_base__h217021 = { coreFix_memExe_lsq$respLd[77:67], ~coreFix_memExe_lsq$respLd[66], coreFix_memExe_lsq$respLd[65:64] } ; - assign b_base__h867086 = + assign b_base__h867085 = { coreFix_aluExe_1_regToExeQ$first[255:245], ~coreFix_aluExe_1_regToExeQ$first[244], coreFix_aluExe_1_regToExeQ$first[243:242] } ; - assign b_base__h867634 = + assign b_base__h867633 = { coreFix_aluExe_1_regToExeQ$first[126:116], ~coreFix_aluExe_1_regToExeQ$first[115], coreFix_aluExe_1_regToExeQ$first[114:113] } ; - assign b_base__h906772 = + assign b_base__h906770 = { coreFix_aluExe_0_regToExeQ$first[255:245], ~coreFix_aluExe_0_regToExeQ$first[244], coreFix_aluExe_0_regToExeQ$first[243:242] } ; - assign b_base__h907320 = + assign b_base__h907318 = { coreFix_aluExe_0_regToExeQ$first[126:116], ~coreFix_aluExe_0_regToExeQ$first[115], coreFix_aluExe_0_regToExeQ$first[114:113] } ; - assign b_base__h995136 = + assign b_base__h995134 = { commitStage_commitTrap[186:176], ~commitStage_commitTrap[175], commitStage_commitTrap[174:173] } ; - assign b_top__h127527 = + assign b_top__h127526 = { coreFix_memExe_respLrScAmoQ_data_0[89:81], ~coreFix_memExe_respLrScAmoQ_data_0[80:79], coreFix_memExe_respLrScAmoQ_data_0[78] } ; - assign b_top__h140443 = + assign b_top__h140442 = { mmio_dataRespQ_data_0[89:81], ~mmio_dataRespQ_data_0[80:79], mmio_dataRespQ_data_0[78] } ; - assign b_top__h183705 = - { x__h183399[89:81], ~x__h183399[80:79], x__h183399[78] } ; - assign b_top__h202456 = - { x__h199251[89:81], ~x__h199251[80:79], x__h199251[78] } ; - assign b_top__h217022 = + assign b_top__h183703 = + { x__h183397[89:81], ~x__h183397[80:79], x__h183397[78] } ; + assign b_top__h202454 = + { x__h199249[89:81], ~x__h199249[80:79], x__h199249[78] } ; + assign b_top__h217020 = { coreFix_memExe_lsq$respLd[89:81], ~coreFix_memExe_lsq$respLd[80:79], coreFix_memExe_lsq$respLd[78] } ; - assign b_top__h867085 = + assign b_top__h867084 = { coreFix_aluExe_1_regToExeQ$first[267:259], ~coreFix_aluExe_1_regToExeQ$first[258:257], coreFix_aluExe_1_regToExeQ$first[256] } ; - assign b_top__h867633 = + assign b_top__h867632 = { coreFix_aluExe_1_regToExeQ$first[138:130], ~coreFix_aluExe_1_regToExeQ$first[129:128], coreFix_aluExe_1_regToExeQ$first[127] } ; - assign b_top__h906771 = + assign b_top__h906769 = { coreFix_aluExe_0_regToExeQ$first[267:259], ~coreFix_aluExe_0_regToExeQ$first[258:257], coreFix_aluExe_0_regToExeQ$first[256] } ; - assign b_top__h907319 = + assign b_top__h907317 = { coreFix_aluExe_0_regToExeQ$first[138:130], ~coreFix_aluExe_0_regToExeQ$first[129:128], coreFix_aluExe_0_regToExeQ$first[127] } ; - assign b_top__h995135 = + assign b_top__h995133 = { commitStage_commitTrap[198:190], ~commitStage_commitTrap[189:188], commitStage_commitTrap[187] } ; - assign base__h239699 = + assign base__h239696 = { coreFix_memExe_regToExeQ$first[223:222], coreFix_memExe_regToExeQ$first[245:232] } ; - assign base__h240856 = + assign base__h240853 = { coreFix_memExe_regToExeQ$first[60:59], coreFix_memExe_regToExeQ$first[82:69] } ; - assign base__h254480 = + assign base__h254477 = { coreFix_memExe_dTlb$procResp[292:291], coreFix_memExe_dTlb$procResp[314:301] } ; - assign base__h854220 = + assign base__h854219 = { (IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16087 == IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16089) ? 2'd0 : @@ -32915,7 +32910,7 @@ module mkCore(CLK, 2'd1 : 2'd3), IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16084 } ; - assign base__h855213 = + assign base__h855212 = { (IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16239 == IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16241) ? 2'd0 : @@ -32924,7 +32919,7 @@ module mkCore(CLK, 2'd1 : 2'd3), IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16236 } ; - assign base__h895975 = + assign base__h895973 = { (csrf_stcc_reg_read__6046_BITS_13_TO_11_6049_UL_ETC___d16051 == csrf_stcc_reg_read__6046_BITS_85_TO_83_6052_UL_ETC___d16053) ? 2'd0 : @@ -32933,7 +32928,7 @@ module mkCore(CLK, 2'd1 : 2'd3), csrf_stcc_reg[13:0] } ; - assign base__h896259 = + assign base__h896257 = { (csrf_mtcc_reg_read__6198_BITS_13_TO_11_6201_UL_ETC___d16203 == csrf_mtcc_reg_read__6198_BITS_85_TO_83_6204_UL_ETC___d16205) ? 2'd0 : @@ -32942,7 +32937,7 @@ module mkCore(CLK, 2'd1 : 2'd3), csrf_mtcc_reg[13:0] } ; - assign base__h896604 = + assign base__h896602 = { (csrf_rg_dpc_read__6343_BITS_13_TO_11_6346_ULT__ETC___d16348 == csrf_rg_dpc_read__6343_BITS_85_TO_83_6349_ULT__ETC___d16350) ? 2'd0 : @@ -32951,58 +32946,58 @@ module mkCore(CLK, 2'd1 : 2'd3), csrf_rg_dpc[13:0] } ; - assign base__h997574 = - { (IF_INV_commitStage_commitTrap_2268_BITS_217_TO_ETC___d22661 == - IF_INV_commitStage_commitTrap_2268_BITS_217_TO_ETC___d22663) ? + assign base__h997609 = + { (IF_INV_commitStage_commitTrap_2268_BITS_217_TO_ETC___d22662 == + IF_INV_commitStage_commitTrap_2268_BITS_217_TO_ETC___d22664) ? 2'd0 : - ((IF_INV_commitStage_commitTrap_2268_BITS_217_TO_ETC___d22661 && - !IF_INV_commitStage_commitTrap_2268_BITS_217_TO_ETC___d22663) ? + ((IF_INV_commitStage_commitTrap_2268_BITS_217_TO_ETC___d22662 && + !IF_INV_commitStage_commitTrap_2268_BITS_217_TO_ETC___d22664) ? 2'd1 : 2'd3), - x__h995129 } ; - assign base__h999389 = { csrf_stcc_reg[149:88], 2'b0 } ; - assign base__h999443 = { csrf_mtcc_reg[149:88], 2'b0 } ; - assign bot__h1008588 = - { csrf_stcc_reg[149:100] & highBitsfilter__h1008372, 14'd0 } + - addBase__h1008585 ; - assign bot__h1008991 = + x__h995127 } ; + assign base__h999424 = { csrf_stcc_reg[149:88], 2'b0 } ; + assign base__h999478 = { csrf_mtcc_reg[149:88], 2'b0 } ; + assign bot__h1008623 = + { csrf_stcc_reg[149:100] & highBitsfilter__h1008407, 14'd0 } + + addBase__h1008620 ; + assign bot__h1009026 = { IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16104[63:14] & - highBitsfilter__h1008775, + highBitsfilter__h1008810, 14'd0 } + - addBase__h1008988 ; - assign bot__h1009408 = - { csrf_mtcc_reg[149:100] & highBitsfilter__h1009192, 14'd0 } + - addBase__h1009405 ; - assign bot__h1009811 = + addBase__h1009023 ; + assign bot__h1009443 = + { csrf_mtcc_reg[149:100] & highBitsfilter__h1009227, 14'd0 } + + addBase__h1009440 ; + assign bot__h1009846 = { IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16256[63:14] & - highBitsfilter__h1009595, + highBitsfilter__h1009630, 14'd0 } + - addBase__h1009808 ; - assign bot__h1010481 = - { csrf_rg_dpc[149:100] & highBitsfilter__h1010264, 14'd0 } + - addBase__h1010478 ; - assign carry_out__h127432 = - (topBits__h127430 < x__h127521[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h140348 = - (topBits__h140346 < x__h140437[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h183610 = - (topBits__h183608 < x__h183699[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h202361 = - (topBits__h202359 < x__h202450[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h216927 = - (topBits__h216925 < x__h217016[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h866989 = - (topBits__h866987 < x__h867079[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h867537 = - (topBits__h867535 < x__h867627[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h906675 = - (topBits__h906673 < x__h906765[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h907223 = - (topBits__h907221 < x__h907313[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h995040 = - (topBits__h995038 < x__h995129[11:0]) ? 2'b01 : 2'b0 ; - assign cause_code__h996858 = { 1'd0, i__h995510 } ; - assign cause_interrupt__h995318 = + addBase__h1009843 ; + assign bot__h1010516 = + { csrf_rg_dpc[149:100] & highBitsfilter__h1010299, 14'd0 } + + addBase__h1010513 ; + assign carry_out__h127431 = + (topBits__h127429 < x__h127520[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h140347 = + (topBits__h140345 < x__h140436[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h183608 = + (topBits__h183606 < x__h183697[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h202359 = + (topBits__h202357 < x__h202448[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h216925 = + (topBits__h216923 < x__h217014[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h866988 = + (topBits__h866986 < x__h867078[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h867536 = + (topBits__h867534 < x__h867626[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h906673 = + (topBits__h906671 < x__h906763[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h907221 = + (topBits__h907219 < x__h907311[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h995038 = + (topBits__h995036 < x__h995127[11:0]) ? 2'b01 : 2'b0 ; + assign cause_code__h996893 = { 1'd0, i__h995534 } ; + assign cause_interrupt__h995316 = commitStage_commitTrap[44:43] != 2'd1 && commitStage_commitTrap[44:43] != 2'd0 ; assign commitStage_commitTrap_2268_BITS_44_TO_43_2461_ETC___d22501 = @@ -33067,7 +33062,7 @@ module mkCore(CLK, IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19204, IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19396, coreFix_aluExe_0_dispToRegQ$first[124] ? - repBound__h900631 : + repBound__h900629 : 3'd7, NOT_coreFix_aluExe_0_dispToRegQ_first__8383_BI_ETC___d19436 } ; assign coreFix_aluExe_0_dispToRegQ_first__8383_BIT_13_ETC___d18468 = @@ -33118,7 +33113,7 @@ module mkCore(CLK, IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d16826, IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d17262, coreFix_aluExe_1_dispToRegQ$first[124] ? - repBound__h860557 : + repBound__h860556 : 3'd7, NOT_coreFix_aluExe_1_dispToRegQ_first__5620_BI_ETC___d17320 } ; assign coreFix_aluExe_1_dispToRegQ_first__5620_BIT_13_ETC___d15705 = @@ -33223,9 +33218,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d14958 | - ((f3_exp__h793197 != 8'd255 || f3_sfd__h793198 == 23'd0) && - (f3_exp__h793197 != 8'd255 || f3_sfd__h793198 != 23'd0) && - (f3_exp__h793197 != 8'd0 || f3_sfd__h793198 != 23'd0) && + ((f3_exp__h793194 != 8'd255 || f3_sfd__h793195 == 23'd0) && + (f3_exp__h793194 != 8'd255 || f3_sfd__h793195 != 23'd0) && + (f3_exp__h793194 != 8'd0 || f3_sfd__h793195 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14998) ; assign coreFix_fpuMulDivExe_0_regToExeQ_first__2522_B_ETC___d15039 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || @@ -33233,9 +33228,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15027 | - ((f3_exp__h793197 != 8'd255 || f3_sfd__h793198 == 23'd0) && - (f3_exp__h793197 != 8'd255 || f3_sfd__h793198 != 23'd0) && - (f3_exp__h793197 != 8'd0 || f3_sfd__h793198 != 23'd0) && + ((f3_exp__h793194 != 8'd255 || f3_sfd__h793195 == 23'd0) && + (f3_exp__h793194 != 8'd255 || f3_sfd__h793195 != 23'd0) && + (f3_exp__h793194 != 8'd0 || f3_sfd__h793195 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15034) ; assign coreFix_fpuMulDivExe_0_regToExeQ_first__2522_B_ETC___d15087 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || @@ -33243,9 +33238,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15071 | - ((f3_exp__h793197 != 8'd255 || f3_sfd__h793198 == 23'd0) && - (f3_exp__h793197 != 8'd255 || f3_sfd__h793198 != 23'd0) && - (f3_exp__h793197 != 8'd0 || f3_sfd__h793198 != 23'd0) && + ((f3_exp__h793194 != 8'd255 || f3_sfd__h793195 == 23'd0) && + (f3_exp__h793194 != 8'd255 || f3_sfd__h793195 != 23'd0) && + (f3_exp__h793194 != 8'd0 || f3_sfd__h793195 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15082) ; assign coreFix_fpuMulDivExe_0_regToExeQ_first__2522_B_ETC___d15129 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || @@ -33253,9 +33248,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15115 | - ((f3_exp__h793197 != 8'd255 || f3_sfd__h793198 == 23'd0) && - (f3_exp__h793197 != 8'd255 || f3_sfd__h793198 != 23'd0) && - (f3_exp__h793197 != 8'd0 || f3_sfd__h793198 != 23'd0) && + ((f3_exp__h793194 != 8'd255 || f3_sfd__h793195 == 23'd0) && + (f3_exp__h793194 != 8'd255 || f3_sfd__h793195 != 23'd0) && + (f3_exp__h793194 != 8'd0 || f3_sfd__h793195 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15124) ; assign coreFix_fpuMulDivExe_0_regToExeQ_first__2522_B_ETC___d15171 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || @@ -33263,9 +33258,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15157 | - ((f3_exp__h793197 != 8'd255 || f3_sfd__h793198 == 23'd0) && - (f3_exp__h793197 != 8'd255 || f3_sfd__h793198 != 23'd0) && - (f3_exp__h793197 != 8'd0 || f3_sfd__h793198 != 23'd0) && + ((f3_exp__h793194 != 8'd255 || f3_sfd__h793195 == 23'd0) && + (f3_exp__h793194 != 8'd255 || f3_sfd__h793195 != 23'd0) && + (f3_exp__h793194 != 8'd0 || f3_sfd__h793195 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15166) ; assign coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q23 = coreFix_fpuMulDivExe_0_regToExeQ$first[107:76] ; @@ -33304,7 +33299,7 @@ module mkCore(CLK, !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5023 && coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58] && coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[57:0] == - y__h422565 ; + y__h422564 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_pi_ETC___d5632 = coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == 3'd3 && @@ -35484,12 +35479,12 @@ module mkCore(CLK, assign coreFix_memExe_dTlb_procResp__257_BITS_334_TO__ETC___d4420 = coreFix_memExe_dTlb$procResp[334:329] < 6'd51 && coreFix_memExe_dTlb_procResp__257_BITS_452_TO__ETC___d4407[64:63] - - { 1'd0, x__h254922 } > + { 1'd0, x__h254919 } > 2'd1 ; assign coreFix_memExe_dTlb_procResp__257_BITS_452_TO__ETC___d4407 = - { coreFix_memExe_dTlb$procResp[452:401] & mask__h254755, + { coreFix_memExe_dTlb$procResp[452:401] & mask__h254752, 14'd0 } + - addTop__h254754 ; + addTop__h254751 ; assign coreFix_memExe_dTlb_procResp__257_BITS_560_TO__ETC___d4557 = coreFix_memExe_dTlb$procResp[560:500] < 61'd402653184 ; assign coreFix_memExe_dTlb_procResp__257_BITS_560_TO__ETC___d4558 = @@ -35535,15 +35530,15 @@ module mkCore(CLK, 66'd0, IF_coreFix_memExe_dispToRegQ_first__686_BIT_10_ETC___d3580 } ; assign coreFix_memExe_lsq_getOrigBE_coreFix_memExe_re_ETC___d4250 = - { coreFix_memExe_lsq$getOrigBE << pointer__h242638[3:0], - (highOffsetBits__h242647 == 50'd0 && + { coreFix_memExe_lsq$getOrigBE << pointer__h242635[3:0], + (highOffsetBits__h242644 == 50'd0 && IF_SEXT_coreFix_memExe_regToExeQ_first__645_BI_ETC___d4095 || coreFix_memExe_regToExeQ$first[265:260] >= 6'd50) && coreFix_memExe_regToExeQ$first[384], - result_d_address__h242849, - x__h248120[13:0], + result_d_address__h242846, + x__h248117[13:0], coreFix_memExe_regToExeQ$first[303:232], - repBound__h248218, + repBound__h248215, coreFix_memExe_regToExeQ_first__645_BITS_259_T_ETC___d4110, coreFix_memExe_regToExeQ_first__645_BITS_245_T_ETC___d4111, coreFix_memExe_regToExeQ_first__645_BITS_383_T_ETC___d4123, @@ -35551,7 +35546,7 @@ module mkCore(CLK, assign coreFix_memExe_regToExeQ_first__645_BITS_102_T_ETC___d3779 = coreFix_memExe_regToExeQ$first[102:97] < 6'd51 && coreFix_memExe_regToExeQ_first__645_BITS_220_T_ETC___d3766[64:63] - - { 1'd0, x__h241298 } > + { 1'd0, x__h241295 } > 2'd1 ; assign coreFix_memExe_regToExeQ_first__645_BITS_140_T_ETC___d4070 = { coreFix_memExe_regToExeQ$first[140:125], @@ -35564,26 +35559,26 @@ module mkCore(CLK, ~IF_coreFix_memExe_regToExeQ_first__645_BIT_103_ETC___d4017[2], IF_coreFix_memExe_regToExeQ_first__645_BIT_103_ETC___d4017[1:0], coreFix_memExe_regToExeQ$first[218:155] } << - x__h244678 ; + x__h244675 ; assign coreFix_memExe_regToExeQ_first__645_BITS_220_T_ETC___d3766 = - { coreFix_memExe_regToExeQ$first[220:169] & mask__h241131, + { coreFix_memExe_regToExeQ$first[220:169] & mask__h241128, 14'd0 } + - addTop__h241130 ; + addTop__h241127 ; assign coreFix_memExe_regToExeQ_first__645_BITS_245_T_ETC___d4111 = - coreFix_memExe_regToExeQ$first[245:243] < repBound__h248218 ; + coreFix_memExe_regToExeQ$first[245:243] < repBound__h248215 ; assign coreFix_memExe_regToExeQ_first__645_BITS_259_T_ETC___d4110 = - coreFix_memExe_regToExeQ$first[259:257] < repBound__h248218 ; + coreFix_memExe_regToExeQ$first[259:257] < repBound__h248215 ; assign coreFix_memExe_regToExeQ_first__645_BITS_265_T_ETC___d3717 = coreFix_memExe_regToExeQ$first[265:260] < 6'd51 && coreFix_memExe_regToExeQ_first__645_BITS_383_T_ETC___d3704[64:63] - - { 1'd0, x__h240141 } > + { 1'd0, x__h240138 } > 2'd1 ; assign coreFix_memExe_regToExeQ_first__645_BITS_383_T_ETC___d3704 = - { coreFix_memExe_regToExeQ$first[383:332] & mask__h239974, + { coreFix_memExe_regToExeQ$first[383:332] & mask__h239971, 14'd0 } + - addTop__h239973 ; + addTop__h239970 ; assign coreFix_memExe_regToExeQ_first__645_BITS_383_T_ETC___d4113 = - x__h248120[13:11] < repBound__h248218 ; + x__h248117[13:11] < repBound__h248215 ; assign coreFix_memExe_regToExeQ_first__645_BITS_383_T_ETC___d4123 = { coreFix_memExe_regToExeQ_first__645_BITS_383_T_ETC___d4113, (coreFix_memExe_regToExeQ_first__645_BITS_259_T_ETC___d4110 == @@ -35612,56 +35607,56 @@ module mkCore(CLK, ({ {48{coreFix_memExe_regToExeQfirst_BITS_223_TO_222__q2[1]}}, coreFix_memExe_regToExeQfirst_BITS_223_TO_222__q2 } << coreFix_memExe_regToExeQ$first[265:260]) ; - assign coreFix_memExe_regToExeQfirst_BITS_434_TO_403__q17 = + assign coreFix_memExe_regToExeQfirst_BITS_434_TO_403__q15 = coreFix_memExe_regToExeQ$first[434:403] ; assign coreFix_memExe_regToExeQfirst_BITS_60_TO_59__q4 = coreFix_memExe_regToExeQ$first[60:59] ; - assign coreFix_memExe_stb_isEmpty__186_AND_coreFix_me_ETC___d23027 = + assign coreFix_memExe_stb_isEmpty__186_AND_coreFix_me_ETC___d23029 = coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty && - rob$RDY_deqPort_0_deq && - rob$RDY_deqPort_0_deq_data && regRenamingTable$RDY_commit_0_commit && + rob$RDY_deqPort_0_deq_data && + rob$RDY_deqPort_0_deq && fetchStage$iTlbIfc_noPendingReq && coreFix_memExe_dTlb$noPendingReq && - NOT_rob_deqPort_0_deq_data__2261_BITS_469_TO_4_ETC___d23022 ; - assign cr_addrBits__h866672 = + NOT_rob_deqPort_0_deq_data__2261_BITS_469_TO_4_ETC___d23024 ; + assign cr_addrBits__h866671 = INV_coreFix_aluExe_1_regToExeQfirst_BITS_286__ETC__q11[0] ? - x__h866848[13:0] : + x__h866847[13:0] : coreFix_aluExe_1_regToExeQ$first[191:178] ; - assign cr_addrBits__h867220 = + assign cr_addrBits__h867219 = INV_coreFix_aluExe_1_regToExeQfirst_BITS_157__ETC__q12[0] ? - x__h867396[13:0] : + x__h867395[13:0] : coreFix_aluExe_1_regToExeQ$first[62:49] ; - assign cr_addrBits__h906358 = + assign cr_addrBits__h906356 = INV_coreFix_aluExe_0_regToExeQfirst_BITS_286__ETC__q13[0] ? - x__h906534[13:0] : + x__h906532[13:0] : coreFix_aluExe_0_regToExeQ$first[191:178] ; - assign cr_addrBits__h906906 = + assign cr_addrBits__h906904 = INV_coreFix_aluExe_0_regToExeQfirst_BITS_157__ETC__q14[0] ? - x__h907082[13:0] : + x__h907080[13:0] : coreFix_aluExe_0_regToExeQ$first[62:49] ; - assign cr_address__h866671 = + assign cr_address__h866670 = { 2'd0, coreFix_aluExe_1_regToExeQ$first[241:178] } ; - assign cr_address__h867219 = + assign cr_address__h867218 = { 2'd0, coreFix_aluExe_1_regToExeQ$first[112:49] } ; - assign cr_address__h906357 = + assign cr_address__h906355 = { 2'd0, coreFix_aluExe_0_regToExeQ$first[241:178] } ; - assign cr_address__h906905 = + assign cr_address__h906903 = { 2'd0, coreFix_aluExe_0_regToExeQ$first[112:49] } ; - assign cr_flags__h866674 = coreFix_aluExe_1_regToExeQ$first[287] ; - assign cr_flags__h867222 = coreFix_aluExe_1_regToExeQ$first[158] ; - assign cr_flags__h906360 = coreFix_aluExe_0_regToExeQ$first[287] ; - assign cr_flags__h906908 = coreFix_aluExe_0_regToExeQ$first[158] ; - assign cr_reserved__h866675 = coreFix_aluExe_1_regToExeQ$first[289:288] ; - assign cr_reserved__h867223 = coreFix_aluExe_1_regToExeQ$first[160:159] ; - assign cr_reserved__h906361 = coreFix_aluExe_0_regToExeQ$first[289:288] ; - assign cr_reserved__h906909 = coreFix_aluExe_0_regToExeQ$first[160:159] ; + assign cr_flags__h866673 = coreFix_aluExe_1_regToExeQ$first[287] ; + assign cr_flags__h867221 = coreFix_aluExe_1_regToExeQ$first[158] ; + assign cr_flags__h906358 = coreFix_aluExe_0_regToExeQ$first[287] ; + assign cr_flags__h906906 = coreFix_aluExe_0_regToExeQ$first[158] ; + assign cr_reserved__h866674 = coreFix_aluExe_1_regToExeQ$first[289:288] ; + assign cr_reserved__h867222 = coreFix_aluExe_1_regToExeQ$first[160:159] ; + assign cr_reserved__h906359 = coreFix_aluExe_0_regToExeQ$first[289:288] ; + assign cr_reserved__h906907 = coreFix_aluExe_0_regToExeQ$first[160:159] ; assign csrf_ddc_reg_read__051_BITS_13_TO_11_140_ULT_c_ETC___d4144 = - csrf_ddc_reg[13:11] < repBound__h248743 ; + csrf_ddc_reg[13:11] < repBound__h248740 ; assign csrf_ddc_reg_read__051_BITS_27_TO_25_142_ULT_c_ETC___d4143 = - csrf_ddc_reg[27:25] < repBound__h248743 ; + csrf_ddc_reg[27:25] < repBound__h248740 ; assign csrf_ddc_reg_read__051_BITS_85_TO_83_145_ULT_c_ETC___d4146 = - csrf_ddc_reg[85:83] < repBound__h248743 ; + csrf_ddc_reg[85:83] < repBound__h248740 ; assign csrf_ddc_reg_read__051_BITS_85_TO_83_145_ULT_c_ETC___d4156 = { csrf_ddc_reg_read__051_BITS_85_TO_83_145_ULT_c_ETC___d4146, (csrf_ddc_reg_read__051_BITS_27_TO_25_142_ULT_c_ETC___d4143 == @@ -35718,73 +35713,70 @@ module mkCore(CLK, csrf_tw_reg && csrf_prv_reg != 2'd3 ; assign csrf_mtcc_reg_read__6198_BITS_13_TO_11_6201_UL_ETC___d16203 = - csrf_mtcc_reg[13:11] < repBound__h855069 ; - assign csrf_mtcc_reg_read__6198_BITS_149_TO_86_2811_A_ETC___d22814 = - csrf_mtcc_reg[149:86] & mask__h1000157 ; - assign csrf_mtcc_reg_read__6198_BITS_149_TO_86_2811_A_ETC___d22821 = - newAddrDiff__h1000158 == mask__h1000157 ; - assign csrf_mtcc_reg_read__6198_BITS_149_TO_86_2811_A_ETC___d22849 = - newAddrDiff__h1000502 == mask__h1000157 ; + csrf_mtcc_reg[13:11] < repBound__h855068 ; + assign csrf_mtcc_reg_read__6198_BITS_149_TO_86_2813_A_ETC___d22816 = + csrf_mtcc_reg[149:86] & mask__h1000192 ; + assign csrf_mtcc_reg_read__6198_BITS_149_TO_86_2813_A_ETC___d22823 = + newAddrDiff__h1000193 == mask__h1000192 ; + assign csrf_mtcc_reg_read__6198_BITS_149_TO_86_2813_A_ETC___d22851 = + newAddrDiff__h1000537 == mask__h1000192 ; assign csrf_mtcc_reg_read__6198_BITS_85_TO_83_6204_UL_ETC___d16205 = - csrf_mtcc_reg[85:83] < repBound__h855069 ; - assign csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22647 = + csrf_mtcc_reg[85:83] < repBound__h855068 ; + assign csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22648 = csrf_prv_reg_read__0286_ULE_1___d22614 && - ((commitStage_commitTrap[44:43] == 2'd1) ? - _0b0_CONCAT_csrf_medeleg_28_26_reg_read__6161_6_ETC___d22642 : - commitStage_commitTrap[44:43] != 2'd0 && - _0b0_CONCAT_csrf_mideleg_11_reg_read__6172_6173_ETC___d22644) ; + CASE_commitStage_commitTrap_BITS_44_TO_43_0_cs_ETC__q276 ; assign csrf_prv_reg_read__0286_ULE_1___d22614 = csrf_prv_reg <= 2'd1 ; assign csrf_rg_dpc_read__6343_BITS_13_TO_11_6346_ULT__ETC___d16348 = - csrf_rg_dpc[13:11] < repBound__h855899 ; + csrf_rg_dpc[13:11] < repBound__h855898 ; assign csrf_rg_dpc_read__6343_BITS_85_TO_83_6349_ULT__ETC___d16350 = - csrf_rg_dpc[85:83] < repBound__h855899 ; + csrf_rg_dpc[85:83] < repBound__h855898 ; assign csrf_stcc_reg_read__6046_BITS_13_TO_11_6049_UL_ETC___d16051 = - csrf_stcc_reg[13:11] < repBound__h854076 ; - assign csrf_stcc_reg_read__6046_BITS_149_TO_86_2740_A_ETC___d22743 = - csrf_stcc_reg[149:86] & mask__h999500 ; - assign csrf_stcc_reg_read__6046_BITS_149_TO_86_2740_A_ETC___d22752 = - newAddrDiff__h999501 == mask__h999500 ; - assign csrf_stcc_reg_read__6046_BITS_149_TO_86_2740_A_ETC___d22780 = - newAddrDiff__h999845 == mask__h999500 ; + csrf_stcc_reg[13:11] < repBound__h854075 ; + assign csrf_stcc_reg_read__6046_BITS_149_TO_86_2742_A_ETC___d22745 = + csrf_stcc_reg[149:86] & mask__h999535 ; + assign csrf_stcc_reg_read__6046_BITS_149_TO_86_2742_A_ETC___d22754 = + newAddrDiff__h999536 == mask__h999535 ; + assign csrf_stcc_reg_read__6046_BITS_149_TO_86_2742_A_ETC___d22782 = + newAddrDiff__h999880 == mask__h999535 ; assign csrf_stcc_reg_read__6046_BITS_85_TO_83_6052_UL_ETC___d16053 = - csrf_stcc_reg[85:83] < repBound__h854076 ; - assign data05833_BITS_31_TO_0__q26 = data__h705833[31:0] ; - assign data___1__h705533 = + csrf_stcc_reg[85:83] < repBound__h854075 ; + assign data05831_BITS_31_TO_0__q26 = data__h705831[31:0] ; + assign data___1__h705531 = { {32{IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q145[31]}}, IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q145 } ; - assign data___1__h706393 = - { {32{data05833_BITS_31_TO_0__q26[31]}}, - data05833_BITS_31_TO_0__q26 } ; - assign data__h567680 = + assign data___1__h706391 = + { {32{data05831_BITS_31_TO_0__q26[31]}}, + data05831_BITS_31_TO_0__q26 } ; + assign data__h567678 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[39] ? - res_data__h568243 : - res_data__h568238 ; - assign data__h613440 = + res_data__h568241 : + res_data__h568236 ; + assign data__h613438 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[39] ? - res_data__h613997 : - res_data__h613992 ; - assign data__h659187 = + res_data__h613995 : + res_data__h613990 ; + assign data__h659185 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[39] ? - res_data__h659744 : - res_data__h659739 ; - assign data__h705001 = + res_data__h659742 : + res_data__h659737 ; + assign data__h704999 = coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[33] ? - data___1__h705533 : + data___1__h705531 : IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC___d12208 ; - assign data__h705833 = + assign data__h705831 = (coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[35:34] == 2'd2) ? - x_quotient__h705747 : - x_remainder__h705748 ; - assign data__h705864 = + x_quotient__h705745 : + x_remainder__h705746 ; + assign data__h705862 = coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[33] ? - data___1__h706393 : - data__h705833 ; - assign data_addrBits__h1018718 = { 2'd0, f_gpr_reqs$D_OUT[63:52] } ; - assign data_addrBits__h1019572 = { 2'b0, f_fpr_reqs$D_OUT[63:52] } ; - assign data_address__h1018717 = { 2'd0, f_gpr_reqs$D_OUT[63:0] } ; - assign data_address__h1019571 = { 2'd0, f_fpr_reqs$D_OUT[63:0] } ; - assign dcsr_cause__h994364 = + data___1__h706391 : + data__h705831 ; + assign data_addrBits__h1018752 = { 2'd0, f_gpr_reqs$D_OUT[63:52] } ; + assign data_addrBits__h1019606 = { 2'b0, f_fpr_reqs$D_OUT[63:52] } ; + assign data_address__h1018751 = { 2'd0, f_gpr_reqs$D_OUT[63:0] } ; + assign data_address__h1019605 = { 2'd0, f_fpr_reqs$D_OUT[63:0] } ; + assign dcsr_cause__h994362 = (commitStage_commitTrap[44:43] != 2'd0 && commitStage_commitTrap[44:43] != 2'd1 && commitStage_commitTrap[35:32] == 4'd14) ? @@ -35803,94 +35795,94 @@ module mkCore(CLK, commitStage_commitTrap[35:32] != 4'd14) ? 3'd4 : 3'd1) ; - assign din_inc___2_exp__h611598 = _theResult___fst_exp__h584565 + 8'd1 ; - assign din_inc___2_exp__h611622 = _theResult___fst_exp__h593221 + 8'd1 ; - assign din_inc___2_exp__h611652 = _theResult___fst_exp__h602331 + 8'd1 ; - assign din_inc___2_exp__h611676 = _theResult___fst_exp__h611016 + 8'd1 ; - assign din_inc___2_exp__h657347 = _theResult___fst_exp__h630314 + 8'd1 ; - assign din_inc___2_exp__h657371 = _theResult___fst_exp__h638970 + 8'd1 ; - assign din_inc___2_exp__h657401 = _theResult___fst_exp__h648080 + 8'd1 ; - assign din_inc___2_exp__h657425 = _theResult___fst_exp__h656765 + 8'd1 ; - assign din_inc___2_exp__h703094 = _theResult___fst_exp__h676061 + 8'd1 ; - assign din_inc___2_exp__h703118 = _theResult___fst_exp__h684717 + 8'd1 ; - assign din_inc___2_exp__h703148 = _theResult___fst_exp__h693827 + 8'd1 ; - assign din_inc___2_exp__h703172 = _theResult___fst_exp__h702512 + 8'd1 ; - assign din_inc___2_exp__h753537 = _theResult___fst_exp__h734287 + 11'd1 ; - assign din_inc___2_exp__h753572 = _theResult___fst_exp__h743864 + 11'd1 ; - assign din_inc___2_exp__h753598 = _theResult___fst_exp__h752697 + 11'd1 ; - assign din_inc___2_exp__h792390 = _theResult___fst_exp__h773140 + 11'd1 ; - assign din_inc___2_exp__h792425 = _theResult___fst_exp__h782717 + 11'd1 ; - assign din_inc___2_exp__h792451 = _theResult___fst_exp__h791550 + 11'd1 ; - assign din_inc___2_exp__h831694 = _theResult___fst_exp__h812444 + 11'd1 ; - assign din_inc___2_exp__h831729 = _theResult___fst_exp__h822021 + 11'd1 ; - assign din_inc___2_exp__h831755 = _theResult___fst_exp__h830854 + 11'd1 ; - assign enabled_ints___1__h920757 = pend_ints__h920230 & y__h920769 ; - assign enabled_ints__h920803 = - pend_ints__h920230 & - { r1__read_BITS_13_TO_0___h920779, csrf_mideleg_1_0_reg } ; - assign f1_exp14899_MINUS_127__q148 = f1_exp__h714899 - 8'd127 ; - assign f1_exp__h714899 = + assign din_inc___2_exp__h611596 = _theResult___fst_exp__h584563 + 8'd1 ; + assign din_inc___2_exp__h611620 = _theResult___fst_exp__h593219 + 8'd1 ; + assign din_inc___2_exp__h611650 = _theResult___fst_exp__h602329 + 8'd1 ; + assign din_inc___2_exp__h611674 = _theResult___fst_exp__h611014 + 8'd1 ; + assign din_inc___2_exp__h657345 = _theResult___fst_exp__h630312 + 8'd1 ; + assign din_inc___2_exp__h657369 = _theResult___fst_exp__h638968 + 8'd1 ; + assign din_inc___2_exp__h657399 = _theResult___fst_exp__h648078 + 8'd1 ; + assign din_inc___2_exp__h657423 = _theResult___fst_exp__h656763 + 8'd1 ; + assign din_inc___2_exp__h703092 = _theResult___fst_exp__h676059 + 8'd1 ; + assign din_inc___2_exp__h703116 = _theResult___fst_exp__h684715 + 8'd1 ; + assign din_inc___2_exp__h703146 = _theResult___fst_exp__h693825 + 8'd1 ; + assign din_inc___2_exp__h703170 = _theResult___fst_exp__h702510 + 8'd1 ; + assign din_inc___2_exp__h753534 = _theResult___fst_exp__h734284 + 11'd1 ; + assign din_inc___2_exp__h753569 = _theResult___fst_exp__h743861 + 11'd1 ; + assign din_inc___2_exp__h753595 = _theResult___fst_exp__h752694 + 11'd1 ; + assign din_inc___2_exp__h792387 = _theResult___fst_exp__h773137 + 11'd1 ; + assign din_inc___2_exp__h792422 = _theResult___fst_exp__h782714 + 11'd1 ; + assign din_inc___2_exp__h792448 = _theResult___fst_exp__h791547 + 11'd1 ; + assign din_inc___2_exp__h831691 = _theResult___fst_exp__h812441 + 11'd1 ; + assign din_inc___2_exp__h831726 = _theResult___fst_exp__h822018 + 11'd1 ; + assign din_inc___2_exp__h831752 = _theResult___fst_exp__h830851 + 11'd1 ; + assign enabled_ints___1__h920755 = pend_ints__h920228 & y__h920767 ; + assign enabled_ints__h920801 = + pend_ints__h920228 & + { r1__read_BITS_13_TO_0___h920777, csrf_mideleg_1_0_reg } ; + assign f1_exp14896_MINUS_127__q148 = f1_exp__h714896 - 8'd127 ; + assign f1_exp__h714896 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] : 8'd255 ; - assign f1_sfd__h714900 = + assign f1_sfd__h714897 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] : 23'd4194304 ; - assign f2_exp53893_MINUS_127__q188 = f2_exp__h753893 - 8'd127 ; - assign f2_exp__h753893 = + assign f2_exp53890_MINUS_127__q188 = f2_exp__h753890 - 8'd127 ; + assign f2_exp__h753890 = (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] : 8'd255 ; - assign f2_sfd__h753894 = + assign f2_sfd__h753891 = (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] : 23'd4194304 ; - assign f3_exp93197_MINUS_127__q165 = f3_exp__h793197 - 8'd127 ; - assign f3_exp__h793197 = + assign f3_exp93194_MINUS_127__q165 = f3_exp__h793194 - 8'd127 ; + assign f3_exp__h793194 = (coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] : 8'd255 ; - assign f3_sfd__h793198 = + assign f3_sfd__h793195 = (coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] : 23'd4194304 ; - assign f_csr_reqs_first__3969_BITS_63_TO_14_4122_XOR__ETC___d24136 = - (highOffsetBits__h1031424 == 50'd0 && - IF_f_csr_reqs_first__3969_BIT_63_4123_THEN_NOT_ETC___d24133 || - NOT_csrf_stcc_reg_read__6046_BITS_33_TO_28_606_ETC___d22739) && + assign f_csr_reqs_first__3971_BITS_63_TO_14_4124_XOR__ETC___d24138 = + (highOffsetBits__h1031458 == 50'd0 && + IF_f_csr_reqs_first__3971_BIT_63_4125_THEN_NOT_ETC___d24135 || + NOT_csrf_stcc_reg_read__6046_BITS_33_TO_28_606_ETC___d22741) && csrf_stcc_reg[152] ; - assign f_csr_reqs_first__3969_BITS_63_TO_14_4122_XOR__ETC___d24158 = - (highOffsetBits__h1031827 == 50'd0 && - IF_f_csr_reqs_first__3969_BIT_63_4123_THEN_NOT_ETC___d24155 || - NOT_IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN__ETC___d23177) && + assign f_csr_reqs_first__3971_BITS_63_TO_14_4124_XOR__ETC___d24160 = + (highOffsetBits__h1031861 == 50'd0 && + IF_f_csr_reqs_first__3971_BIT_63_4125_THEN_NOT_ETC___d24157 || + NOT_IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN__ETC___d23179) && IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16810 ; - assign f_csr_reqs_first__3969_BITS_63_TO_14_4122_XOR__ETC___d24216 = - (highOffsetBits__h1032244 == 50'd0 && - IF_f_csr_reqs_first__3969_BIT_63_4123_THEN_NOT_ETC___d24213 || - NOT_csrf_mtcc_reg_read__6198_BITS_33_TO_28_621_ETC___d22810) && + assign f_csr_reqs_first__3971_BITS_63_TO_14_4124_XOR__ETC___d24218 = + (highOffsetBits__h1032278 == 50'd0 && + IF_f_csr_reqs_first__3971_BIT_63_4125_THEN_NOT_ETC___d24215 || + NOT_csrf_mtcc_reg_read__6198_BITS_33_TO_28_621_ETC___d22812) && csrf_mtcc_reg[152] ; - assign f_csr_reqs_first__3969_BITS_63_TO_14_4122_XOR__ETC___d24236 = - (highOffsetBits__h1032647 == 50'd0 && - IF_f_csr_reqs_first__3969_BIT_63_4123_THEN_NOT_ETC___d24233 || - NOT_IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN__ETC___d23314) && + assign f_csr_reqs_first__3971_BITS_63_TO_14_4124_XOR__ETC___d24238 = + (highOffsetBits__h1032681 == 50'd0 && + IF_f_csr_reqs_first__3971_BIT_63_4125_THEN_NOT_ETC___d24235 || + NOT_IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN__ETC___d23316) && IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16818 ; - assign f_csr_reqs_first__3969_BITS_63_TO_14_4122_XOR__ETC___d24307 = - (highOffsetBits__h1033314 == 50'd0 && - IF_f_csr_reqs_first__3969_BIT_63_4123_THEN_NOT_ETC___d24304 || - NOT_csrf_rg_dpc_read__6343_BITS_33_TO_28_6360__ETC___d23427) && + assign f_csr_reqs_first__3971_BITS_63_TO_14_4124_XOR__ETC___d24309 = + (highOffsetBits__h1033348 == 50'd0 && + IF_f_csr_reqs_first__3971_BIT_63_4125_THEN_NOT_ETC___d24306 || + NOT_csrf_rg_dpc_read__6343_BITS_33_TO_28_6360__ETC___d23429) && csrf_rg_dpc[152] ; - assign f_csr_rsps_i_notFull__3967_AND_f_csr_reqs_firs_ETC___d24072 = + assign f_csr_rsps_i_notFull__3969_AND_f_csr_reqs_firs_ETC___d24074 = f_csr_rsps$FULL_N && (f_csr_reqs$D_OUT[75:64] != 12'd2049 || csrf_stats_module_writeQ$FULL_N) && (f_csr_reqs$D_OUT[75:64] != 12'd2048 || csrf_terminate_module_terminateQ$FULL_N) ; - assign fcsr_csr__read__h849219 = { 56'd0, x__h853092 } ; + assign fcsr_csr__read__h849218 = { 56'd0, x__h853091 } ; assign fetchStage_RDY_pipelines_0_first__0253_AND_fet_ETC___d21254 = fetchStage$RDY_pipelines_0_first && fetchStage$pipelines_1_first[268:266] == 3'd1 && @@ -36164,104 +36156,104 @@ module mkCore(CLK, assign fetchStage_pipelines_1_first__0265_BIT_180_145_ETC___d21553 = { fetchStage$pipelines_1_first[180], CASE_fetchStagepipelines_1_first_BITS_179_TO__ETC__q259 } ; - assign fflags__h1016316 = - NOT_rob_deqPort_0_canDeq__3598_3599_OR_rob_deq_ETC___d23818 ? - y_avValue_snd_fst__h1016376 : - IF_rob_deqPort_0_canDeq__3598_THEN_IF_NOT_rob__ETC___d23825 ; - assign fflags_csr__read__h849194 = { 59'd0, csrf_fflags_reg } ; - assign frm_csr__read__h849205 = { 61'd0, csrf_frm_reg } ; - assign guard__h576464 = - { IF_sfdin84559_BIT_33_THEN_2_ELSE_0__q41[1], - { sfdin__h584559[32:0], 23'd0 } != 56'd0 } ; - assign guard__h585173 = - { IF_theResult___snd93172_BIT_33_THEN_2_ELSE_0__q43[1], - { _theResult___snd__h593172[32:0], 23'd0 } != 56'd0 } ; - assign guard__h594103 = - { IF_sfdin02325_BIT_33_THEN_2_ELSE_0__q51[1], - { sfdin__h602325[32:0], 23'd0 } != 56'd0 } ; - assign guard__h594701 = x__h594803 != 57'd0 ; - assign guard__h602939 = - { IF_theResult___snd10962_BIT_33_THEN_2_ELSE_0__q56[1], - { _theResult___snd__h610962[32:0], 23'd0 } != 56'd0 } ; - assign guard__h622215 = - { IF_sfdin30308_BIT_33_THEN_2_ELSE_0__q76[1], - { sfdin__h630308[32:0], 23'd0 } != 56'd0 } ; - assign guard__h630922 = - { IF_theResult___snd38921_BIT_33_THEN_2_ELSE_0__q78[1], - { _theResult___snd__h638921[32:0], 23'd0 } != 56'd0 } ; - assign guard__h639852 = - { IF_sfdin48074_BIT_33_THEN_2_ELSE_0__q86[1], - { sfdin__h648074[32:0], 23'd0 } != 56'd0 } ; - assign guard__h640450 = x__h640552 != 57'd0 ; - assign guard__h648688 = - { IF_theResult___snd56711_BIT_33_THEN_2_ELSE_0__q91[1], - { _theResult___snd__h656711[32:0], 23'd0 } != 56'd0 } ; - assign guard__h667962 = - { IF_sfdin76055_BIT_33_THEN_2_ELSE_0__q111[1], - { sfdin__h676055[32:0], 23'd0 } != 56'd0 } ; - assign guard__h676669 = - { IF_theResult___snd84668_BIT_33_THEN_2_ELSE_0__q113[1], - { _theResult___snd__h684668[32:0], 23'd0 } != 56'd0 } ; - assign guard__h685599 = - { IF_sfdin93821_BIT_33_THEN_2_ELSE_0__q121[1], - { sfdin__h693821[32:0], 23'd0 } != 56'd0 } ; - assign guard__h686197 = x__h686299 != 57'd0 ; - assign guard__h694435 = - { IF_theResult___snd02458_BIT_33_THEN_2_ELSE_0__q126[1], - { _theResult___snd__h702458[32:0], 23'd0 } != 56'd0 } ; - assign guard__h726326 = - { IF_theResult___snd34238_BIT_4_THEN_2_ELSE_0__q147[1], - { _theResult___snd__h734238[3:0], 52'd0 } != 56'd0 } ; - assign guard__h735638 = - { IF_sfdin43858_BIT_4_THEN_2_ELSE_0__q151[1], - { sfdin__h743858[3:0], 52'd0 } != 56'd0 } ; - assign guard__h736236 = x__h736336 != 57'd0 ; - assign guard__h744707 = - { IF_theResult___snd52643_BIT_4_THEN_2_ELSE_0__q154[1], - { _theResult___snd__h752643[3:0], 52'd0 } != 56'd0 } ; - assign guard__h765179 = - { IF_theResult___snd73091_BIT_4_THEN_2_ELSE_0__q187[1], - { _theResult___snd__h773091[3:0], 52'd0 } != 56'd0 } ; - assign guard__h774491 = - { IF_sfdin82711_BIT_4_THEN_2_ELSE_0__q191[1], - { sfdin__h782711[3:0], 52'd0 } != 56'd0 } ; - assign guard__h775089 = x__h775189 != 57'd0 ; - assign guard__h783560 = - { IF_theResult___snd91496_BIT_4_THEN_2_ELSE_0__q194[1], - { _theResult___snd__h791496[3:0], 52'd0 } != 56'd0 } ; - assign guard__h804483 = - { IF_theResult___snd12395_BIT_4_THEN_2_ELSE_0__q164[1], - { _theResult___snd__h812395[3:0], 52'd0 } != 56'd0 } ; - assign guard__h813795 = - { IF_sfdin22015_BIT_4_THEN_2_ELSE_0__q168[1], - { sfdin__h822015[3:0], 52'd0 } != 56'd0 } ; - assign guard__h814393 = x__h814493 != 57'd0 ; - assign guard__h822864 = - { IF_theResult___snd30800_BIT_4_THEN_2_ELSE_0__q171[1], - { _theResult___snd__h830800[3:0], 52'd0 } != 56'd0 } ; - assign highBitsfilter__h1008372 = + assign fflags__h1016351 = + NOT_rob_deqPort_0_canDeq__3600_3601_OR_rob_deq_ETC___d23820 ? + y_avValue_snd_fst__h1016411 : + IF_rob_deqPort_0_canDeq__3600_THEN_IF_NOT_rob__ETC___d23827 ; + assign fflags_csr__read__h849193 = { 59'd0, csrf_fflags_reg } ; + assign frm_csr__read__h849204 = { 61'd0, csrf_frm_reg } ; + assign guard__h576462 = + { IF_sfdin84557_BIT_33_THEN_2_ELSE_0__q41[1], + { sfdin__h584557[32:0], 23'd0 } != 56'd0 } ; + assign guard__h585171 = + { IF_theResult___snd93170_BIT_33_THEN_2_ELSE_0__q43[1], + { _theResult___snd__h593170[32:0], 23'd0 } != 56'd0 } ; + assign guard__h594101 = + { IF_sfdin02323_BIT_33_THEN_2_ELSE_0__q51[1], + { sfdin__h602323[32:0], 23'd0 } != 56'd0 } ; + assign guard__h594699 = x__h594801 != 57'd0 ; + assign guard__h602937 = + { IF_theResult___snd10960_BIT_33_THEN_2_ELSE_0__q56[1], + { _theResult___snd__h610960[32:0], 23'd0 } != 56'd0 } ; + assign guard__h622213 = + { IF_sfdin30306_BIT_33_THEN_2_ELSE_0__q76[1], + { sfdin__h630306[32:0], 23'd0 } != 56'd0 } ; + assign guard__h630920 = + { IF_theResult___snd38919_BIT_33_THEN_2_ELSE_0__q78[1], + { _theResult___snd__h638919[32:0], 23'd0 } != 56'd0 } ; + assign guard__h639850 = + { IF_sfdin48072_BIT_33_THEN_2_ELSE_0__q86[1], + { sfdin__h648072[32:0], 23'd0 } != 56'd0 } ; + assign guard__h640448 = x__h640550 != 57'd0 ; + assign guard__h648686 = + { IF_theResult___snd56709_BIT_33_THEN_2_ELSE_0__q91[1], + { _theResult___snd__h656709[32:0], 23'd0 } != 56'd0 } ; + assign guard__h667960 = + { IF_sfdin76053_BIT_33_THEN_2_ELSE_0__q111[1], + { sfdin__h676053[32:0], 23'd0 } != 56'd0 } ; + assign guard__h676667 = + { IF_theResult___snd84666_BIT_33_THEN_2_ELSE_0__q113[1], + { _theResult___snd__h684666[32:0], 23'd0 } != 56'd0 } ; + assign guard__h685597 = + { IF_sfdin93819_BIT_33_THEN_2_ELSE_0__q121[1], + { sfdin__h693819[32:0], 23'd0 } != 56'd0 } ; + assign guard__h686195 = x__h686297 != 57'd0 ; + assign guard__h694433 = + { IF_theResult___snd02456_BIT_33_THEN_2_ELSE_0__q126[1], + { _theResult___snd__h702456[32:0], 23'd0 } != 56'd0 } ; + assign guard__h726323 = + { IF_theResult___snd34235_BIT_4_THEN_2_ELSE_0__q147[1], + { _theResult___snd__h734235[3:0], 52'd0 } != 56'd0 } ; + assign guard__h735635 = + { IF_sfdin43855_BIT_4_THEN_2_ELSE_0__q151[1], + { sfdin__h743855[3:0], 52'd0 } != 56'd0 } ; + assign guard__h736233 = x__h736333 != 57'd0 ; + assign guard__h744704 = + { IF_theResult___snd52640_BIT_4_THEN_2_ELSE_0__q154[1], + { _theResult___snd__h752640[3:0], 52'd0 } != 56'd0 } ; + assign guard__h765176 = + { IF_theResult___snd73088_BIT_4_THEN_2_ELSE_0__q187[1], + { _theResult___snd__h773088[3:0], 52'd0 } != 56'd0 } ; + assign guard__h774488 = + { IF_sfdin82708_BIT_4_THEN_2_ELSE_0__q191[1], + { sfdin__h782708[3:0], 52'd0 } != 56'd0 } ; + assign guard__h775086 = x__h775186 != 57'd0 ; + assign guard__h783557 = + { IF_theResult___snd91493_BIT_4_THEN_2_ELSE_0__q194[1], + { _theResult___snd__h791493[3:0], 52'd0 } != 56'd0 } ; + assign guard__h804480 = + { IF_theResult___snd12392_BIT_4_THEN_2_ELSE_0__q164[1], + { _theResult___snd__h812392[3:0], 52'd0 } != 56'd0 } ; + assign guard__h813792 = + { IF_sfdin22012_BIT_4_THEN_2_ELSE_0__q168[1], + { sfdin__h822012[3:0], 52'd0 } != 56'd0 } ; + assign guard__h814390 = x__h814490 != 57'd0 ; + assign guard__h822861 = + { IF_theResult___snd30797_BIT_4_THEN_2_ELSE_0__q171[1], + { _theResult___snd__h830797[3:0], 52'd0 } != 56'd0 } ; + assign highBitsfilter__h1008407 = 50'h3FFFFFFFFFFFF << csrf_stcc_reg[33:28] ; - assign highBitsfilter__h1008775 = + assign highBitsfilter__h1008810 = 50'h3FFFFFFFFFFFF << IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16100 ; - assign highBitsfilter__h1009192 = + assign highBitsfilter__h1009227 = 50'h3FFFFFFFFFFFF << csrf_mtcc_reg[33:28] ; - assign highBitsfilter__h1009595 = + assign highBitsfilter__h1009630 = 50'h3FFFFFFFFFFFF << IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16252 ; - assign highBitsfilter__h1010264 = 50'h3FFFFFFFFFFFF << csrf_rg_dpc[33:28] ; - assign highOffsetBits__h1008373 = x__h1008400 & highBitsfilter__h1008372 ; - assign highOffsetBits__h1008776 = x__h1008400 & highBitsfilter__h1008775 ; - assign highOffsetBits__h1009193 = x__h1008400 & highBitsfilter__h1009192 ; - assign highOffsetBits__h1009596 = x__h1008400 & highBitsfilter__h1009595 ; - assign highOffsetBits__h1010265 = x__h1008400 & highBitsfilter__h1010264 ; - assign highOffsetBits__h1031424 = x__h1031451 & highBitsfilter__h1008372 ; - assign highOffsetBits__h1031827 = x__h1031451 & highBitsfilter__h1008775 ; - assign highOffsetBits__h1032244 = x__h1031451 & highBitsfilter__h1009192 ; - assign highOffsetBits__h1032647 = x__h1031451 & highBitsfilter__h1009595 ; - assign highOffsetBits__h1033314 = x__h1031451 & highBitsfilter__h1010264 ; - assign highOffsetBits__h242647 = x__h242674 & mask__h239865 ; - assign idx__h968880 = + assign highBitsfilter__h1010299 = 50'h3FFFFFFFFFFFF << csrf_rg_dpc[33:28] ; + assign highOffsetBits__h1008408 = x__h1008435 & highBitsfilter__h1008407 ; + assign highOffsetBits__h1008811 = x__h1008435 & highBitsfilter__h1008810 ; + assign highOffsetBits__h1009228 = x__h1008435 & highBitsfilter__h1009227 ; + assign highOffsetBits__h1009631 = x__h1008435 & highBitsfilter__h1009630 ; + assign highOffsetBits__h1010300 = x__h1008435 & highBitsfilter__h1010299 ; + assign highOffsetBits__h1031458 = x__h1031485 & highBitsfilter__h1008407 ; + assign highOffsetBits__h1031861 = x__h1031485 & highBitsfilter__h1008810 ; + assign highOffsetBits__h1032278 = x__h1031485 & highBitsfilter__h1009227 ; + assign highOffsetBits__h1032681 = x__h1031485 & highBitsfilter__h1009630 ; + assign highOffsetBits__h1033348 = x__h1031485 & highBitsfilter__h1010299 ; + assign highOffsetBits__h242644 = x__h242671 & mask__h239862 ; + assign idx__h968878 = fetchStage$pipelines_0_canDeq && NOT_fetchStage_pipelines_0_first__0256_BITS_26_ETC___d21652 || !coreFix_aluExe_0_rsAlu$canEnq || @@ -36269,91 +36261,91 @@ module mkCore(CLK, fetchStage_pipelines_0_first__0256_BITS_268_TO_ETC___d21675) && coreFix_aluExe_1_rsAlu$canEnq && !coreFix_aluExe_0_rsAlu_approximateCount__1196__ETC___d21198 ; - assign impliedTopBits__h127434 = x__h127518 + len_correction__h127433 ; - assign impliedTopBits__h140350 = x__h140434 + len_correction__h140349 ; - assign impliedTopBits__h183612 = x__h183696 + len_correction__h183611 ; - assign impliedTopBits__h202363 = x__h202447 + len_correction__h202362 ; - assign impliedTopBits__h216929 = x__h217013 + len_correction__h216928 ; - assign impliedTopBits__h866991 = x__h867076 + len_correction__h866990 ; - assign impliedTopBits__h867539 = x__h867624 + len_correction__h867538 ; - assign impliedTopBits__h906677 = x__h906762 + len_correction__h906676 ; - assign impliedTopBits__h907225 = x__h907310 + len_correction__h907224 ; - assign impliedTopBits__h995042 = x__h995126 + len_correction__h995041 ; - assign in__h239804 = coreFix_memExe_regToExeQ$first[383:318] & y__h239821 ; - assign in__h240961 = coreFix_memExe_regToExeQ$first[220:155] & y__h240978 ; - assign in__h254585 = coreFix_memExe_dTlb$procResp[452:387] & y__h254602 ; - assign in__h854154 = csrf_stcc_reg[151:86] & y__h854171 ; - assign in__h854459 = + assign impliedTopBits__h127433 = x__h127517 + len_correction__h127432 ; + assign impliedTopBits__h140349 = x__h140433 + len_correction__h140348 ; + assign impliedTopBits__h183610 = x__h183694 + len_correction__h183609 ; + assign impliedTopBits__h202361 = x__h202445 + len_correction__h202360 ; + assign impliedTopBits__h216927 = x__h217011 + len_correction__h216926 ; + assign impliedTopBits__h866990 = x__h867075 + len_correction__h866989 ; + assign impliedTopBits__h867538 = x__h867623 + len_correction__h867537 ; + assign impliedTopBits__h906675 = x__h906760 + len_correction__h906674 ; + assign impliedTopBits__h907223 = x__h907308 + len_correction__h907222 ; + assign impliedTopBits__h995040 = x__h995124 + len_correction__h995039 ; + assign in__h239801 = coreFix_memExe_regToExeQ$first[383:318] & y__h239818 ; + assign in__h240958 = coreFix_memExe_regToExeQ$first[220:155] & y__h240975 ; + assign in__h254582 = coreFix_memExe_dTlb$procResp[452:387] & y__h254599 ; + assign in__h854153 = csrf_stcc_reg[151:86] & y__h854170 ; + assign in__h854458 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16104 & - y__h854476 ; - assign in__h855147 = csrf_mtcc_reg[151:86] & y__h855164 ; - assign in__h855451 = + y__h854475 ; + assign in__h855146 = csrf_mtcc_reg[151:86] & y__h855163 ; + assign in__h855450 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16256 & - y__h855468 ; - assign in__h855977 = csrf_rg_dpc[151:86] & y__h855994 ; - assign in__h997656 = pc_address__h994739 & y__h997673 ; - assign k__h945030 = + y__h855467 ; + assign in__h855976 = csrf_rg_dpc[151:86] & y__h855993 ; + assign in__h997691 = pc_address__h994737 & y__h997708 ; + assign k__h945028 = !coreFix_aluExe_0_rsAlu$canEnq || coreFix_aluExe_1_rsAlu$canEnq && !coreFix_aluExe_0_rsAlu_approximateCount__1196__ETC___d21198 ; - assign len_correction__h127433 = + assign len_correction__h127432 = INV_coreFix_memExe_respLrScAmoQ_data_0_BITS_10_ETC__q8[0] ? 2'b01 : 2'b0 ; - assign len_correction__h140349 = + assign len_correction__h140348 = INV_mmio_dataRespQ_data_0_BITS_108_TO_90__q9[0] ? 2'b01 : 2'b0 ; - assign len_correction__h183611 = - INV_x83399_BITS_108_TO_90__q34[0] ? 2'b01 : 2'b0 ; - assign len_correction__h202362 = - INV_x99251_BITS_108_TO_90__q36[0] ? 2'b01 : 2'b0 ; - assign len_correction__h216928 = + assign len_correction__h183609 = + INV_x83397_BITS_108_TO_90__q34[0] ? 2'b01 : 2'b0 ; + assign len_correction__h202360 = + INV_x99249_BITS_108_TO_90__q36[0] ? 2'b01 : 2'b0 ; + assign len_correction__h216926 = INV_coreFix_memExe_lsqrespLd_BITS_108_TO_90__q10[0] ? 2'b01 : 2'b0 ; - assign len_correction__h866990 = + assign len_correction__h866989 = INV_coreFix_aluExe_1_regToExeQfirst_BITS_286__ETC__q11[0] ? 2'b01 : 2'b0 ; - assign len_correction__h867538 = + assign len_correction__h867537 = INV_coreFix_aluExe_1_regToExeQfirst_BITS_157__ETC__q12[0] ? 2'b01 : 2'b0 ; - assign len_correction__h906676 = + assign len_correction__h906674 = INV_coreFix_aluExe_0_regToExeQfirst_BITS_286__ETC__q13[0] ? 2'b01 : 2'b0 ; - assign len_correction__h907224 = + assign len_correction__h907222 = INV_coreFix_aluExe_0_regToExeQfirst_BITS_157__ETC__q14[0] ? 2'b01 : 2'b0 ; - assign len_correction__h995041 = - INV_commitStage_commitTrap_BITS_217_TO_199__q15[0] ? + assign len_correction__h995039 = + INV_commitStage_commitTrap_BITS_217_TO_199__q16[0] ? 2'b01 : 2'b0 ; - assign mask__h1000157 = 64'hFFFFFFFFFFFFFFFF << x__h1000218 ; - assign mask__h239865 = + assign mask__h1000192 = 64'hFFFFFFFFFFFFFFFF << x__h1000253 ; + assign mask__h239862 = 50'h3FFFFFFFFFFFF << coreFix_memExe_regToExeQ$first[265:260] ; - assign mask__h239974 = + assign mask__h239971 = 52'hFFFFFFFFFFFFF << coreFix_memExe_regToExeQ$first[265:260] ; - assign mask__h241022 = + assign mask__h241019 = 50'h3FFFFFFFFFFFF << coreFix_memExe_regToExeQ$first[102:97] ; - assign mask__h241131 = + assign mask__h241128 = 52'hFFFFFFFFFFFFF << coreFix_memExe_regToExeQ$first[102:97] ; - assign mask__h254646 = + assign mask__h254643 = 50'h3FFFFFFFFFFFF << coreFix_memExe_dTlb$procResp[334:329] ; - assign mask__h254755 = + assign mask__h254752 = 52'hFFFFFFFFFFFFF << coreFix_memExe_dTlb$procResp[334:329] ; - assign mask__h999500 = 64'hFFFFFFFFFFFFFFFF << x__h999561 ; - assign mcause_csr__read__h850886 = - { r1__read__h855501, csrf_mcause_code_reg } ; - assign mcounteren_csr__read__h850620 = - { r1__read__h855197, csrf_mcounteren_cy_reg } ; - assign medeleg_csr__read__h850223 = - { r1__read__h854874, csrf_medeleg_9_0_reg } ; - assign mideleg_csr__read__h850321 = - { r1__read__h854897, csrf_mideleg_1_0_reg } ; - assign mie_csr__read__h850448 = { r1__read__h854921, 1'b0 } ; - assign mip_csr__read__h851125 = { r1__read__h855508, 1'b0 } ; + assign mask__h999535 = 64'hFFFFFFFFFFFFFFFF << x__h999596 ; + assign mcause_csr__read__h850885 = + { r1__read__h855500, csrf_mcause_code_reg } ; + assign mcounteren_csr__read__h850619 = + { r1__read__h855196, csrf_mcounteren_cy_reg } ; + assign medeleg_csr__read__h850222 = + { r1__read__h854873, csrf_medeleg_9_0_reg } ; + assign mideleg_csr__read__h850320 = + { r1__read__h854896, csrf_mideleg_1_0_reg } ; + assign mie_csr__read__h850447 = { r1__read__h854920, 1'b0 } ; + assign mip_csr__read__h851124 = { r1__read__h855507, 1'b0 } ; assign mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d20679 = mmio_pRqQ_empty && epochManager$checkEpoch_0_check && (renameStage_rg_m_halt_req[4] || @@ -36395,56 +36387,56 @@ module mkCore(CLK, fetchStage$pipelines_0_first[273:269] != 5'd24 && fetchStage$pipelines_0_first[273:269] != 5'd25 && rg_core_run_state == 2'd2 ; - assign mstatus_csr__read__h850062 = { r1__read__h854749, csrf_ie_vec_0 } ; - assign n__read__h1014112 = + assign mstatus_csr__read__h850061 = { r1__read__h854748, csrf_ie_vec_0 } ; + assign n__read__h1014147 = csrf_minstret_ehr_data_lat_0$whas ? - upd__h1014188 : + upd__h1014223 : csrf_minstret_ehr_data_rl ; assign n__read__h7908 = csrf_mcycle_ehr_data_lat_0$whas ? upd__h7977 : csrf_mcycle_ehr_data_rl ; - assign newAddrBits__h1008555 = - { 2'd0, csrf_stcc_reg[13:0] } + { 2'd0, x__h1008496[13:0] } ; - assign newAddrBits__h1008958 = + assign newAddrBits__h1008590 = + { 2'd0, csrf_stcc_reg[13:0] } + { 2'd0, x__h1008531[13:0] } ; + assign newAddrBits__h1008993 = { 2'd0, IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16084 } + - { 2'd0, x__h1008899[13:0] } ; - assign newAddrBits__h1009375 = - { 2'd0, csrf_mtcc_reg[13:0] } + { 2'd0, x__h1009316[13:0] } ; - assign newAddrBits__h1009778 = + { 2'd0, x__h1008934[13:0] } ; + assign newAddrBits__h1009410 = + { 2'd0, csrf_mtcc_reg[13:0] } + { 2'd0, x__h1009351[13:0] } ; + assign newAddrBits__h1009813 = { 2'd0, IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16236 } + - { 2'd0, x__h1009719[13:0] } ; - assign newAddrBits__h1010447 = - { 2'd0, csrf_rg_dpc[13:0] } + { 2'd0, x__h1010388[13:0] } ; - assign newAddrBits__h1031606 = - { 2'd0, csrf_stcc_reg[13:0] } + { 2'd0, x__h1031547[13:0] } ; - assign newAddrBits__h1032009 = + { 2'd0, x__h1009754[13:0] } ; + assign newAddrBits__h1010482 = + { 2'd0, csrf_rg_dpc[13:0] } + { 2'd0, x__h1010423[13:0] } ; + assign newAddrBits__h1031640 = + { 2'd0, csrf_stcc_reg[13:0] } + { 2'd0, x__h1031581[13:0] } ; + assign newAddrBits__h1032043 = { 2'd0, IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16084 } + - { 2'd0, x__h1031950[13:0] } ; - assign newAddrBits__h1032426 = - { 2'd0, csrf_mtcc_reg[13:0] } + { 2'd0, x__h1032367[13:0] } ; - assign newAddrBits__h1032829 = + { 2'd0, x__h1031984[13:0] } ; + assign newAddrBits__h1032460 = + { 2'd0, csrf_mtcc_reg[13:0] } + { 2'd0, x__h1032401[13:0] } ; + assign newAddrBits__h1032863 = { 2'd0, IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16236 } + - { 2'd0, x__h1032770[13:0] } ; - assign newAddrBits__h1033496 = - { 2'd0, csrf_rg_dpc[13:0] } + { 2'd0, x__h1033437[13:0] } ; - assign newAddrDiff__h1000158 = - csrf_mtcc_reg_read__6198_BITS_149_TO_86_2811_A_ETC___d22814 - - (address__h999478 & mask__h1000157) ; - assign newAddrDiff__h1000502 = - csrf_mtcc_reg_read__6198_BITS_149_TO_86_2811_A_ETC___d22814 - - (base__h999443 & mask__h1000157) ; - assign newAddrDiff__h999501 = - csrf_stcc_reg_read__6046_BITS_149_TO_86_2740_A_ETC___d22743 - - (address__h999428 & mask__h999500) ; - assign newAddrDiff__h999845 = - csrf_stcc_reg_read__6046_BITS_149_TO_86_2740_A_ETC___d22743 - - (base__h999389 & mask__h999500) ; - assign new_pc__h872925 = + { 2'd0, x__h1032804[13:0] } ; + assign newAddrBits__h1033530 = + { 2'd0, csrf_rg_dpc[13:0] } + { 2'd0, x__h1033471[13:0] } ; + assign newAddrDiff__h1000193 = + csrf_mtcc_reg_read__6198_BITS_149_TO_86_2813_A_ETC___d22816 - + (address__h999513 & mask__h1000192) ; + assign newAddrDiff__h1000537 = + csrf_mtcc_reg_read__6198_BITS_149_TO_86_2813_A_ETC___d22816 - + (base__h999478 & mask__h1000192) ; + assign newAddrDiff__h999536 = + csrf_stcc_reg_read__6046_BITS_149_TO_86_2742_A_ETC___d22745 - + (address__h999463 & mask__h999535) ; + assign newAddrDiff__h999880 = + csrf_stcc_reg_read__6046_BITS_149_TO_86_2742_A_ETC___d22745 - + (base__h999424 & mask__h999535) ; + assign new_pc__h872924 = { coreFix_aluExe_1_exeToFinQ$first[460], coreFix_aluExe_1_exeToFinQ$first[379:364], coreFix_aluExe_1_exeToFinQ$first[362:361], @@ -36456,7 +36448,7 @@ module mkCore(CLK, ~IF_coreFix_aluExe_1_exeToFinQ_first__7830_BIT__ETC___d17996[2], IF_coreFix_aluExe_1_exeToFinQ_first__7830_BIT__ETC___d17996[1:0], coreFix_aluExe_1_exeToFinQ$first[457:394] } ; - assign new_pc__h912073 = + assign new_pc__h912071 = { coreFix_aluExe_0_exeToFinQ$first[460], coreFix_aluExe_0_exeToFinQ$first[379:364], coreFix_aluExe_0_exeToFinQ$first[362:361], @@ -36468,275 +36460,275 @@ module mkCore(CLK, ~IF_coreFix_aluExe_0_exeToFinQ_first__9946_BIT__ETC___d20111[2], IF_coreFix_aluExe_0_exeToFinQ_first__9946_BIT__ETC___d20111[1:0], coreFix_aluExe_0_exeToFinQ$first[457:394] } ; - assign next_deqP___1__h515613 = + assign next_deqP___1__h515611 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP == 3'd7) ? 3'd0 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP + 3'd1 ; - assign next_deqP___1__h526390 = + assign next_deqP___1__h526388 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP + 1'd1 ; - assign next_deqP___1__h533668 = + assign next_deqP___1__h533666 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP + 1'd1 ; - assign next_deqP___1__h544303 = + assign next_deqP___1__h544301 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP + 1'd1 ; - assign next_deqP___1__h557951 = coreFix_memExe_memRespLdQ_deqP + 1'd1 ; - assign next_deqP___1__h561730 = coreFix_memExe_forwardQ_deqP + 1'd1 ; - assign next_pc__h1012222 = + assign next_deqP___1__h557949 = coreFix_memExe_memRespLdQ_deqP + 1'd1 ; + assign next_deqP___1__h561728 = coreFix_memExe_forwardQ_deqP + 1'd1 ; + assign next_pc__h1012257 = (rob$deqPort_0_deq_data[196:195] == 2'd0) ? rob$deqPort_0_deq_data[160:32] : - { rob$deqPort_0_deq_data[630:566], address__h1013682 } ; - assign offset__h239700 = + { rob$deqPort_0_deq_data[630:566], address__h1013717 } ; + assign offset__h239697 = { 2'd0, coreFix_memExe_regToExeQ$first[317:304] } - - base__h239699 ; - assign offset__h240857 = + base__h239696 ; + assign offset__h240854 = { 2'd0, coreFix_memExe_regToExeQ$first[154:141] } - - base__h240856 ; - assign offset__h242628 = - { {32{coreFix_memExe_regToExeQfirst_BITS_434_TO_403__q17[31]}}, - coreFix_memExe_regToExeQfirst_BITS_434_TO_403__q17 } ; - assign offset__h254481 = - { 2'd0, coreFix_memExe_dTlb$procResp[386:373] } - base__h254480 ; - assign offset__h854221 = + base__h240853 ; + assign offset__h242625 = + { {32{coreFix_memExe_regToExeQfirst_BITS_434_TO_403__q15[31]}}, + coreFix_memExe_regToExeQfirst_BITS_434_TO_403__q15 } ; + assign offset__h254478 = + { 2'd0, coreFix_memExe_dTlb$procResp[386:373] } - base__h254477 ; + assign offset__h854220 = { 2'd0, IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16080 } - - base__h854220 ; - assign offset__h855214 = + base__h854219 ; + assign offset__h855213 = { 2'd0, IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16232 } - - base__h855213 ; - assign offset__h895976 = { 2'd0, csrf_stcc_reg[85:72] } - base__h895975 ; - assign offset__h896260 = { 2'd0, csrf_mtcc_reg[85:72] } - base__h896259 ; - assign offset__h896605 = { 2'd0, csrf_rg_dpc[85:72] } - base__h896604 ; - assign offset__h997575 = { 2'd0, pc_addrBits__h994740 } - base__h997574 ; - assign out___1_sfd__h714963 = { f1_sfd__h714900, 29'd0 } ; - assign out___1_sfd__h753957 = { f2_sfd__h753894, 29'd0 } ; - assign out___1_sfd__h793261 = { f3_sfd__h793198, 29'd0 } ; - assign out_exp__h585084 = - sfdin__h584559[34] ? - _theResult___exp__h585081 : - _theResult___fst_exp__h584565 ; - assign out_exp__h593666 = - _theResult___snd__h593172[34] ? - _theResult___exp__h593663 : - _theResult___fst_exp__h593221 ; - assign out_exp__h602850 = - sfdin__h602325[34] ? - _theResult___exp__h602847 : - _theResult___fst_exp__h602331 ; - assign out_exp__h611486 = - _theResult___snd__h610962[34] ? - _theResult___exp__h611483 : - _theResult___fst_exp__h611016 ; - assign out_exp__h630833 = - sfdin__h630308[34] ? - _theResult___exp__h630830 : - _theResult___fst_exp__h630314 ; - assign out_exp__h639415 = - _theResult___snd__h638921[34] ? - _theResult___exp__h639412 : - _theResult___fst_exp__h638970 ; - assign out_exp__h648599 = - sfdin__h648074[34] ? - _theResult___exp__h648596 : - _theResult___fst_exp__h648080 ; - assign out_exp__h657235 = - _theResult___snd__h656711[34] ? - _theResult___exp__h657232 : - _theResult___fst_exp__h656765 ; - assign out_exp__h676580 = - sfdin__h676055[34] ? - _theResult___exp__h676577 : - _theResult___fst_exp__h676061 ; - assign out_exp__h685162 = - _theResult___snd__h684668[34] ? - _theResult___exp__h685159 : - _theResult___fst_exp__h684717 ; - assign out_exp__h694346 = - sfdin__h693821[34] ? - _theResult___exp__h694343 : - _theResult___fst_exp__h693827 ; - assign out_exp__h702982 = - _theResult___snd__h702458[34] ? - _theResult___exp__h702979 : - _theResult___fst_exp__h702512 ; - assign out_exp__h734945 = - _theResult___snd__h734238[5] ? - _theResult___exp__h734942 : - _theResult___fst_exp__h734287 ; - assign out_exp__h744596 = - sfdin__h743858[5] ? - _theResult___exp__h744593 : - _theResult___fst_exp__h743864 ; - assign out_exp__h753380 = - _theResult___snd__h752643[5] ? - _theResult___exp__h753377 : - _theResult___fst_exp__h752697 ; - assign out_exp__h773798 = - _theResult___snd__h773091[5] ? - _theResult___exp__h773795 : - _theResult___fst_exp__h773140 ; - assign out_exp__h783449 = - sfdin__h782711[5] ? - _theResult___exp__h783446 : - _theResult___fst_exp__h782717 ; - assign out_exp__h792233 = - _theResult___snd__h791496[5] ? - _theResult___exp__h792230 : - _theResult___fst_exp__h791550 ; - assign out_exp__h813102 = - _theResult___snd__h812395[5] ? - _theResult___exp__h813099 : - _theResult___fst_exp__h812444 ; - assign out_exp__h822753 = - sfdin__h822015[5] ? - _theResult___exp__h822750 : - _theResult___fst_exp__h822021 ; - assign out_exp__h831537 = - _theResult___snd__h830800[5] ? - _theResult___exp__h831534 : - _theResult___fst_exp__h830854 ; - assign out_f_exp__h611862 = - (_theResult___exp__h611585 == 8'd255 && - _theResult___sfd__h611586 != 23'd0 || + base__h855212 ; + assign offset__h895974 = { 2'd0, csrf_stcc_reg[85:72] } - base__h895973 ; + assign offset__h896258 = { 2'd0, csrf_mtcc_reg[85:72] } - base__h896257 ; + assign offset__h896603 = { 2'd0, csrf_rg_dpc[85:72] } - base__h896602 ; + assign offset__h997610 = { 2'd0, pc_addrBits__h994738 } - base__h997609 ; + assign out___1_sfd__h714960 = { f1_sfd__h714897, 29'd0 } ; + assign out___1_sfd__h753954 = { f2_sfd__h753891, 29'd0 } ; + assign out___1_sfd__h793258 = { f3_sfd__h793195, 29'd0 } ; + assign out_exp__h585082 = + sfdin__h584557[34] ? + _theResult___exp__h585079 : + _theResult___fst_exp__h584563 ; + assign out_exp__h593664 = + _theResult___snd__h593170[34] ? + _theResult___exp__h593661 : + _theResult___fst_exp__h593219 ; + assign out_exp__h602848 = + sfdin__h602323[34] ? + _theResult___exp__h602845 : + _theResult___fst_exp__h602329 ; + assign out_exp__h611484 = + _theResult___snd__h610960[34] ? + _theResult___exp__h611481 : + _theResult___fst_exp__h611014 ; + assign out_exp__h630831 = + sfdin__h630306[34] ? + _theResult___exp__h630828 : + _theResult___fst_exp__h630312 ; + assign out_exp__h639413 = + _theResult___snd__h638919[34] ? + _theResult___exp__h639410 : + _theResult___fst_exp__h638968 ; + assign out_exp__h648597 = + sfdin__h648072[34] ? + _theResult___exp__h648594 : + _theResult___fst_exp__h648078 ; + assign out_exp__h657233 = + _theResult___snd__h656709[34] ? + _theResult___exp__h657230 : + _theResult___fst_exp__h656763 ; + assign out_exp__h676578 = + sfdin__h676053[34] ? + _theResult___exp__h676575 : + _theResult___fst_exp__h676059 ; + assign out_exp__h685160 = + _theResult___snd__h684666[34] ? + _theResult___exp__h685157 : + _theResult___fst_exp__h684715 ; + assign out_exp__h694344 = + sfdin__h693819[34] ? + _theResult___exp__h694341 : + _theResult___fst_exp__h693825 ; + assign out_exp__h702980 = + _theResult___snd__h702456[34] ? + _theResult___exp__h702977 : + _theResult___fst_exp__h702510 ; + assign out_exp__h734942 = + _theResult___snd__h734235[5] ? + _theResult___exp__h734939 : + _theResult___fst_exp__h734284 ; + assign out_exp__h744593 = + sfdin__h743855[5] ? + _theResult___exp__h744590 : + _theResult___fst_exp__h743861 ; + assign out_exp__h753377 = + _theResult___snd__h752640[5] ? + _theResult___exp__h753374 : + _theResult___fst_exp__h752694 ; + assign out_exp__h773795 = + _theResult___snd__h773088[5] ? + _theResult___exp__h773792 : + _theResult___fst_exp__h773137 ; + assign out_exp__h783446 = + sfdin__h782708[5] ? + _theResult___exp__h783443 : + _theResult___fst_exp__h782714 ; + assign out_exp__h792230 = + _theResult___snd__h791493[5] ? + _theResult___exp__h792227 : + _theResult___fst_exp__h791547 ; + assign out_exp__h813099 = + _theResult___snd__h812392[5] ? + _theResult___exp__h813096 : + _theResult___fst_exp__h812441 ; + assign out_exp__h822750 = + sfdin__h822012[5] ? + _theResult___exp__h822747 : + _theResult___fst_exp__h822018 ; + assign out_exp__h831534 = + _theResult___snd__h830797[5] ? + _theResult___exp__h831531 : + _theResult___fst_exp__h830851 ; + assign out_f_exp__h611860 = + (_theResult___exp__h611583 == 8'd255 && + _theResult___sfd__h611584 != 23'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h611576 ; - assign out_f_exp__h657611 = - (_theResult___exp__h657334 == 8'd255 && - _theResult___sfd__h657335 != 23'd0 || + _theResult___fst_exp__h611574 ; + assign out_f_exp__h657609 = + (_theResult___exp__h657332 == 8'd255 && + _theResult___sfd__h657333 != 23'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h657325 ; - assign out_f_exp__h703358 = - (_theResult___exp__h703081 == 8'd255 && - _theResult___sfd__h703082 != 23'd0 || + _theResult___fst_exp__h657323 ; + assign out_f_exp__h703356 = + (_theResult___exp__h703079 == 8'd255 && + _theResult___sfd__h703080 != 23'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h703072 ; - assign out_f_sfd__h611863 = - (_theResult___exp__h611585 == 8'd255 && - _theResult___sfd__h611586 != 23'd0) ? + _theResult___fst_exp__h703070 ; + assign out_f_sfd__h611861 = + (_theResult___exp__h611583 == 8'd255 && + _theResult___sfd__h611584 != 23'd0) ? 23'd4194304 : - _theResult___sfd__h611586 ; - assign out_f_sfd__h657612 = - (_theResult___exp__h657334 == 8'd255 && - _theResult___sfd__h657335 != 23'd0) ? + _theResult___sfd__h611584 ; + assign out_f_sfd__h657610 = + (_theResult___exp__h657332 == 8'd255 && + _theResult___sfd__h657333 != 23'd0) ? 23'd4194304 : - _theResult___sfd__h657335 ; - assign out_f_sfd__h703359 = - (_theResult___exp__h703081 == 8'd255 && - _theResult___sfd__h703082 != 23'd0) ? + _theResult___sfd__h657333 ; + assign out_f_sfd__h703357 = + (_theResult___exp__h703079 == 8'd255 && + _theResult___sfd__h703080 != 23'd0) ? 23'd4194304 : - _theResult___sfd__h703082 ; - assign out_sfd__h585085 = - sfdin__h584559[34] ? - _theResult___sfd__h585082 : - sfdin__h584559[56:34] ; - assign out_sfd__h593667 = - _theResult___snd__h593172[34] ? - _theResult___sfd__h593664 : - _theResult___snd__h593172[56:34] ; - assign out_sfd__h602851 = - sfdin__h602325[34] ? - _theResult___sfd__h602848 : - sfdin__h602325[56:34] ; - assign out_sfd__h611487 = - _theResult___snd__h610962[34] ? - _theResult___sfd__h611484 : - _theResult___snd__h610962[56:34] ; - assign out_sfd__h630834 = - sfdin__h630308[34] ? - _theResult___sfd__h630831 : - sfdin__h630308[56:34] ; - assign out_sfd__h639416 = - _theResult___snd__h638921[34] ? - _theResult___sfd__h639413 : - _theResult___snd__h638921[56:34] ; - assign out_sfd__h648600 = - sfdin__h648074[34] ? - _theResult___sfd__h648597 : - sfdin__h648074[56:34] ; - assign out_sfd__h657236 = - _theResult___snd__h656711[34] ? - _theResult___sfd__h657233 : - _theResult___snd__h656711[56:34] ; - assign out_sfd__h676581 = - sfdin__h676055[34] ? - _theResult___sfd__h676578 : - sfdin__h676055[56:34] ; - assign out_sfd__h685163 = - _theResult___snd__h684668[34] ? - _theResult___sfd__h685160 : - _theResult___snd__h684668[56:34] ; - assign out_sfd__h694347 = - sfdin__h693821[34] ? - _theResult___sfd__h694344 : - sfdin__h693821[56:34] ; - assign out_sfd__h702983 = - _theResult___snd__h702458[34] ? - _theResult___sfd__h702980 : - _theResult___snd__h702458[56:34] ; - assign out_sfd__h734946 = - _theResult___snd__h734238[5] ? - _theResult___sfd__h734943 : - _theResult___snd__h734238[56:5] ; - assign out_sfd__h744597 = - sfdin__h743858[5] ? - _theResult___sfd__h744594 : - sfdin__h743858[56:5] ; - assign out_sfd__h753381 = - _theResult___snd__h752643[5] ? - _theResult___sfd__h753378 : - _theResult___snd__h752643[56:5] ; - assign out_sfd__h773799 = - _theResult___snd__h773091[5] ? - _theResult___sfd__h773796 : - _theResult___snd__h773091[56:5] ; - assign out_sfd__h783450 = - sfdin__h782711[5] ? - _theResult___sfd__h783447 : - sfdin__h782711[56:5] ; - assign out_sfd__h792234 = - _theResult___snd__h791496[5] ? - _theResult___sfd__h792231 : - _theResult___snd__h791496[56:5] ; - assign out_sfd__h813103 = - _theResult___snd__h812395[5] ? - _theResult___sfd__h813100 : - _theResult___snd__h812395[56:5] ; - assign out_sfd__h822754 = - sfdin__h822015[5] ? - _theResult___sfd__h822751 : - sfdin__h822015[56:5] ; - assign out_sfd__h831538 = - _theResult___snd__h830800[5] ? - _theResult___sfd__h831535 : - _theResult___snd__h830800[56:5] ; - assign pc__h963242 = fetchStage$pipelines_1_first[591:463] ; - assign pc_addrBits__h994740 = - INV_commitStage_commitTrap_BITS_217_TO_199__q15[0] ? - x__h994911[13:0] : + _theResult___sfd__h703080 ; + assign out_sfd__h585083 = + sfdin__h584557[34] ? + _theResult___sfd__h585080 : + sfdin__h584557[56:34] ; + assign out_sfd__h593665 = + _theResult___snd__h593170[34] ? + _theResult___sfd__h593662 : + _theResult___snd__h593170[56:34] ; + assign out_sfd__h602849 = + sfdin__h602323[34] ? + _theResult___sfd__h602846 : + sfdin__h602323[56:34] ; + assign out_sfd__h611485 = + _theResult___snd__h610960[34] ? + _theResult___sfd__h611482 : + _theResult___snd__h610960[56:34] ; + assign out_sfd__h630832 = + sfdin__h630306[34] ? + _theResult___sfd__h630829 : + sfdin__h630306[56:34] ; + assign out_sfd__h639414 = + _theResult___snd__h638919[34] ? + _theResult___sfd__h639411 : + _theResult___snd__h638919[56:34] ; + assign out_sfd__h648598 = + sfdin__h648072[34] ? + _theResult___sfd__h648595 : + sfdin__h648072[56:34] ; + assign out_sfd__h657234 = + _theResult___snd__h656709[34] ? + _theResult___sfd__h657231 : + _theResult___snd__h656709[56:34] ; + assign out_sfd__h676579 = + sfdin__h676053[34] ? + _theResult___sfd__h676576 : + sfdin__h676053[56:34] ; + assign out_sfd__h685161 = + _theResult___snd__h684666[34] ? + _theResult___sfd__h685158 : + _theResult___snd__h684666[56:34] ; + assign out_sfd__h694345 = + sfdin__h693819[34] ? + _theResult___sfd__h694342 : + sfdin__h693819[56:34] ; + assign out_sfd__h702981 = + _theResult___snd__h702456[34] ? + _theResult___sfd__h702978 : + _theResult___snd__h702456[56:34] ; + assign out_sfd__h734943 = + _theResult___snd__h734235[5] ? + _theResult___sfd__h734940 : + _theResult___snd__h734235[56:5] ; + assign out_sfd__h744594 = + sfdin__h743855[5] ? + _theResult___sfd__h744591 : + sfdin__h743855[56:5] ; + assign out_sfd__h753378 = + _theResult___snd__h752640[5] ? + _theResult___sfd__h753375 : + _theResult___snd__h752640[56:5] ; + assign out_sfd__h773796 = + _theResult___snd__h773088[5] ? + _theResult___sfd__h773793 : + _theResult___snd__h773088[56:5] ; + assign out_sfd__h783447 = + sfdin__h782708[5] ? + _theResult___sfd__h783444 : + sfdin__h782708[56:5] ; + assign out_sfd__h792231 = + _theResult___snd__h791493[5] ? + _theResult___sfd__h792228 : + _theResult___snd__h791493[56:5] ; + assign out_sfd__h813100 = + _theResult___snd__h812392[5] ? + _theResult___sfd__h813097 : + _theResult___snd__h812392[56:5] ; + assign out_sfd__h822751 = + sfdin__h822012[5] ? + _theResult___sfd__h822748 : + sfdin__h822012[56:5] ; + assign out_sfd__h831535 = + _theResult___snd__h830797[5] ? + _theResult___sfd__h831532 : + _theResult___snd__h830797[56:5] ; + assign pc__h963240 = fetchStage$pipelines_1_first[591:463] ; + assign pc_addrBits__h994738 = + INV_commitStage_commitTrap_BITS_217_TO_199__q16[0] ? + x__h994909[13:0] : commitStage_commitTrap[122:109] ; - assign pc_address__h994739 = { 2'd0, commitStage_commitTrap[172:109] } ; - assign pend_ints__h920230 = + assign pc_address__h994737 = { 2'd0, commitStage_commitTrap[172:109] } ; + assign pend_ints__h920228 = { _0_CONCAT_csrf_external_int_en_vec_3_read__6183_ETC___d20297, csrf_software_int_en_vec_3 & csrf_software_int_pend_vec_3, 1'd0, csrf_software_int_en_vec_1 & csrf_software_int_pend_vec_1, 1'd0 } ; - assign pointer__h242638 = + assign pointer__h242635 = coreFix_memExe_regToExeQ$first[383:318] + - { 2'd0, offset__h242628 } ; - assign prv__h1017409 = csrf_prv_reg ; - assign prv__h1017453 = csrf_mprv_reg ? csrf_mpp_reg : csrf_prv_reg ; - assign q___1__h706458 = + { 2'd0, offset__h242625 } ; + assign prv__h1017444 = csrf_prv_reg ; + assign prv__h1017488 = csrf_mprv_reg ? csrf_mpp_reg : csrf_prv_reg ; + assign q___1__h706456 = 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[127:64] ; - assign r1__read_BITS_13_TO_0___h920779 = + assign r1__read_BITS_13_TO_0___h920777 = { 4'd0, csrf_mideleg_11_reg, 1'b0, @@ -36744,129 +36736,129 @@ module mkCore(CLK, 1'b0, csrf_mideleg_5_3_reg, 1'b0 } ; - assign r1__read_BITS_13_TO_12___h926454 = csrf_fs_reg ; - assign r1__read_BIT_20___h926960 = csrf_tw_reg ; - assign r1__read__h853107 = { r1__read__h853109, csrf_ie_vec_1 } ; - assign r1__read__h853109 = { r1__read__h853111, 2'b0 } ; - assign r1__read__h853111 = { r1__read__h853113, csrf_prev_ie_vec_0 } ; - assign r1__read__h853113 = { r1__read__h853115, csrf_prev_ie_vec_1 } ; - assign r1__read__h853115 = { r1__read__h853117, 2'b0 } ; - assign r1__read__h853117 = { r1__read__h853119, csrf_spp_reg } ; - assign r1__read__h853119 = { r1__read__h853121, 4'b0 } ; - assign r1__read__h853121 = { r1__read__h853123, csrf_fs_reg } ; - assign r1__read__h853123 = { r1__read__h853125, 2'd0 } ; - assign r1__read__h853125 = { r1__read__h853127, 1'b0 } ; - assign r1__read__h853127 = { r1__read__h853129, csrf_sum_reg } ; - assign r1__read__h853129 = { r1__read__h853131, csrf_mxr_reg } ; - assign r1__read__h853131 = { r1__read__h853133, 12'b0 } ; - assign r1__read__h853133 = { r1__read__h853135, 2'b10 } ; - assign r1__read__h853135 = { r__h853139, 29'b0 } ; - assign r1__read__h853511 = - { r1__read__h853513, csrf_software_int_en_vec_1 } ; - assign r1__read__h853513 = { r1__read__h853515, 2'b0 } ; - assign r1__read__h853515 = { r1__read__h853517, 1'b0 } ; - assign r1__read__h853517 = { r1__read__h853519, csrf_timer_int_en_vec_1 } ; - assign r1__read__h853519 = { r1__read__h853521, 2'b0 } ; - assign r1__read__h853521 = { r1__read__h853523, 1'b0 } ; - assign r1__read__h853523 = { 54'b0, csrf_external_int_en_vec_1 } ; - assign r1__read__h854204 = { r1__read__h854206, csrf_scounteren_tm_reg } ; - assign r1__read__h854206 = { 61'd0, csrf_scounteren_ir_reg } ; - assign r1__read__h854509 = { csrf_scause_interrupt_reg, 58'b0 } ; - assign r1__read__h854516 = - { r1__read__h854518, csrf_software_int_pend_vec_1 } ; - assign r1__read__h854518 = { r1__read__h854520, 2'b0 } ; - assign r1__read__h854520 = { r1__read__h854522, 1'b0 } ; - assign r1__read__h854522 = - { r1__read__h854524, csrf_timer_int_pend_vec_1 } ; - assign r1__read__h854524 = { r1__read__h854526, 2'b0 } ; - assign r1__read__h854526 = { r1__read__h854528, 1'b0 } ; - assign r1__read__h854528 = { 54'b0, csrf_external_int_pend_vec_1 } ; - assign r1__read__h854726 = { vm_mode_reg__read__h854732, 16'd0 } ; - assign r1__read__h854749 = { r1__read__h854751, csrf_ie_vec_1 } ; - assign r1__read__h854751 = { r1__read__h854753, 1'b0 } ; - assign r1__read__h854753 = { r1__read__h854755, csrf_ie_vec_3 } ; - assign r1__read__h854755 = { r1__read__h854757, csrf_prev_ie_vec_0 } ; - assign r1__read__h854757 = { r1__read__h854759, csrf_prev_ie_vec_1 } ; - assign r1__read__h854759 = { r1__read__h854761, 1'b0 } ; - assign r1__read__h854761 = { r1__read__h854763, csrf_prev_ie_vec_3 } ; - assign r1__read__h854763 = { r1__read__h854765, csrf_spp_reg } ; - assign r1__read__h854765 = { r1__read__h854767, 2'b0 } ; - assign r1__read__h854767 = { r1__read__h854769, csrf_mpp_reg } ; - assign r1__read__h854769 = { r1__read__h854771, csrf_fs_reg } ; - assign r1__read__h854771 = { r1__read__h854773, 2'd0 } ; - assign r1__read__h854773 = { r1__read__h854775, csrf_mprv_reg } ; - assign r1__read__h854775 = { r1__read__h854777, csrf_sum_reg } ; - assign r1__read__h854777 = { r1__read__h854779, csrf_mxr_reg } ; - assign r1__read__h854779 = { r1__read__h854781, csrf_tvm_reg } ; - assign r1__read__h854781 = { r1__read__h854783, csrf_tw_reg } ; - assign r1__read__h854783 = { r1__read__h854785, csrf_tsr_reg } ; - assign r1__read__h854785 = { r1__read__h854787, 9'b0 } ; - assign r1__read__h854787 = { r1__read__h854789, 2'b10 } ; - assign r1__read__h854789 = { r1__read__h854791, 2'b10 } ; - assign r1__read__h854791 = { r__h853139, 27'b0 } ; - assign r1__read__h854874 = { r1__read__h854876, 1'b0 } ; - assign r1__read__h854876 = { r1__read__h854878, csrf_medeleg_13_11_reg } ; - assign r1__read__h854878 = { r1__read__h854880, 1'b0 } ; - assign r1__read__h854880 = { r1__read__h854882, csrf_medeleg_15_reg } ; - assign r1__read__h854882 = { r1__read__h854884, 10'b0 } ; - assign r1__read__h854884 = { 35'b0, csrf_medeleg_28_26_reg } ; - assign r1__read__h854897 = { r1__read__h854899, 1'b0 } ; - assign r1__read__h854899 = { r1__read__h854901, csrf_mideleg_5_3_reg } ; - assign r1__read__h854901 = { r1__read__h854903, 1'b0 } ; - assign r1__read__h854903 = { r1__read__h854905, csrf_mideleg_9_7_reg } ; - assign r1__read__h854905 = { r1__read__h854907, 1'b0 } ; - assign r1__read__h854907 = { 52'b0, csrf_mideleg_11_reg } ; - assign r1__read__h854921 = - { r1__read__h854923, csrf_software_int_en_vec_1 } ; - assign r1__read__h854923 = { r1__read__h854925, 1'b0 } ; - assign r1__read__h854925 = - { r1__read__h854927, csrf_software_int_en_vec_3 } ; - assign r1__read__h854927 = { r1__read__h854929, 1'b0 } ; - assign r1__read__h854929 = { r1__read__h854931, csrf_timer_int_en_vec_1 } ; - assign r1__read__h854931 = { r1__read__h854933, 1'b0 } ; - assign r1__read__h854933 = { r1__read__h854935, csrf_timer_int_en_vec_3 } ; - assign r1__read__h854935 = { r1__read__h854937, 1'b0 } ; - assign r1__read__h854937 = - { r1__read__h854939, csrf_external_int_en_vec_1 } ; - assign r1__read__h854939 = { r1__read__h854941, 1'b0 } ; - assign r1__read__h854941 = { 52'b0, csrf_external_int_en_vec_3 } ; - assign r1__read__h855197 = { r1__read__h855199, csrf_mcounteren_tm_reg } ; - assign r1__read__h855199 = { 61'd0, csrf_mcounteren_ir_reg } ; - assign r1__read__h855501 = { csrf_mcause_interrupt_reg, 58'd0 } ; - assign r1__read__h855508 = - { r1__read__h855510, csrf_software_int_pend_vec_1 } ; - assign r1__read__h855510 = { r1__read__h855512, 1'b0 } ; - assign r1__read__h855512 = - { r1__read__h855514, csrf_software_int_pend_vec_3 } ; - assign r1__read__h855514 = { r1__read__h855516, 1'b0 } ; - assign r1__read__h855516 = - { r1__read__h855518, csrf_timer_int_pend_vec_1 } ; - assign r1__read__h855518 = { r1__read__h855520, 1'b0 } ; - assign r1__read__h855520 = - { r1__read__h855522, csrf_timer_int_pend_vec_3 } ; - assign r1__read__h855522 = { r1__read__h855524, 1'b0 } ; - assign r1__read__h855524 = - { r1__read__h855526, csrf_external_int_pend_vec_1 } ; - assign r1__read__h855526 = { r1__read__h855528, 1'b0 } ; - assign r1__read__h855528 = { 52'b0, csrf_external_int_pend_vec_3 } ; - assign r1__read__h855837 = { 4'd0, csrf_rg_tdata1_dmode } ; - assign rVal1__h714520 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; - assign rVal2__h714521 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; - assign r___1__h706484 = + assign r1__read_BITS_13_TO_12___h926452 = csrf_fs_reg ; + assign r1__read_BIT_20___h926958 = csrf_tw_reg ; + assign r1__read__h853106 = { r1__read__h853108, csrf_ie_vec_1 } ; + assign r1__read__h853108 = { r1__read__h853110, 2'b0 } ; + assign r1__read__h853110 = { r1__read__h853112, csrf_prev_ie_vec_0 } ; + assign r1__read__h853112 = { r1__read__h853114, csrf_prev_ie_vec_1 } ; + assign r1__read__h853114 = { r1__read__h853116, 2'b0 } ; + assign r1__read__h853116 = { r1__read__h853118, csrf_spp_reg } ; + assign r1__read__h853118 = { r1__read__h853120, 4'b0 } ; + assign r1__read__h853120 = { r1__read__h853122, csrf_fs_reg } ; + assign r1__read__h853122 = { r1__read__h853124, 2'd0 } ; + assign r1__read__h853124 = { r1__read__h853126, 1'b0 } ; + assign r1__read__h853126 = { r1__read__h853128, csrf_sum_reg } ; + assign r1__read__h853128 = { r1__read__h853130, csrf_mxr_reg } ; + assign r1__read__h853130 = { r1__read__h853132, 12'b0 } ; + assign r1__read__h853132 = { r1__read__h853134, 2'b10 } ; + assign r1__read__h853134 = { r__h853138, 29'b0 } ; + assign r1__read__h853510 = + { r1__read__h853512, csrf_software_int_en_vec_1 } ; + assign r1__read__h853512 = { r1__read__h853514, 2'b0 } ; + assign r1__read__h853514 = { r1__read__h853516, 1'b0 } ; + assign r1__read__h853516 = { r1__read__h853518, csrf_timer_int_en_vec_1 } ; + assign r1__read__h853518 = { r1__read__h853520, 2'b0 } ; + assign r1__read__h853520 = { r1__read__h853522, 1'b0 } ; + assign r1__read__h853522 = { 54'b0, csrf_external_int_en_vec_1 } ; + assign r1__read__h854203 = { r1__read__h854205, csrf_scounteren_tm_reg } ; + assign r1__read__h854205 = { 61'd0, csrf_scounteren_ir_reg } ; + assign r1__read__h854508 = { csrf_scause_interrupt_reg, 58'b0 } ; + assign r1__read__h854515 = + { r1__read__h854517, csrf_software_int_pend_vec_1 } ; + assign r1__read__h854517 = { r1__read__h854519, 2'b0 } ; + assign r1__read__h854519 = { r1__read__h854521, 1'b0 } ; + assign r1__read__h854521 = + { r1__read__h854523, csrf_timer_int_pend_vec_1 } ; + assign r1__read__h854523 = { r1__read__h854525, 2'b0 } ; + assign r1__read__h854525 = { r1__read__h854527, 1'b0 } ; + assign r1__read__h854527 = { 54'b0, csrf_external_int_pend_vec_1 } ; + assign r1__read__h854725 = { vm_mode_reg__read__h854731, 16'd0 } ; + assign r1__read__h854748 = { r1__read__h854750, csrf_ie_vec_1 } ; + assign r1__read__h854750 = { r1__read__h854752, 1'b0 } ; + assign r1__read__h854752 = { r1__read__h854754, csrf_ie_vec_3 } ; + assign r1__read__h854754 = { r1__read__h854756, csrf_prev_ie_vec_0 } ; + assign r1__read__h854756 = { r1__read__h854758, csrf_prev_ie_vec_1 } ; + assign r1__read__h854758 = { r1__read__h854760, 1'b0 } ; + assign r1__read__h854760 = { r1__read__h854762, csrf_prev_ie_vec_3 } ; + assign r1__read__h854762 = { r1__read__h854764, csrf_spp_reg } ; + assign r1__read__h854764 = { r1__read__h854766, 2'b0 } ; + assign r1__read__h854766 = { r1__read__h854768, csrf_mpp_reg } ; + assign r1__read__h854768 = { r1__read__h854770, csrf_fs_reg } ; + assign r1__read__h854770 = { r1__read__h854772, 2'd0 } ; + assign r1__read__h854772 = { r1__read__h854774, csrf_mprv_reg } ; + assign r1__read__h854774 = { r1__read__h854776, csrf_sum_reg } ; + assign r1__read__h854776 = { r1__read__h854778, csrf_mxr_reg } ; + assign r1__read__h854778 = { r1__read__h854780, csrf_tvm_reg } ; + assign r1__read__h854780 = { r1__read__h854782, csrf_tw_reg } ; + assign r1__read__h854782 = { r1__read__h854784, csrf_tsr_reg } ; + assign r1__read__h854784 = { r1__read__h854786, 9'b0 } ; + assign r1__read__h854786 = { r1__read__h854788, 2'b10 } ; + assign r1__read__h854788 = { r1__read__h854790, 2'b10 } ; + assign r1__read__h854790 = { r__h853138, 27'b0 } ; + assign r1__read__h854873 = { r1__read__h854875, 1'b0 } ; + assign r1__read__h854875 = { r1__read__h854877, csrf_medeleg_13_11_reg } ; + assign r1__read__h854877 = { r1__read__h854879, 1'b0 } ; + assign r1__read__h854879 = { r1__read__h854881, csrf_medeleg_15_reg } ; + assign r1__read__h854881 = { r1__read__h854883, 10'b0 } ; + assign r1__read__h854883 = { 35'b0, csrf_medeleg_28_26_reg } ; + assign r1__read__h854896 = { r1__read__h854898, 1'b0 } ; + assign r1__read__h854898 = { r1__read__h854900, csrf_mideleg_5_3_reg } ; + assign r1__read__h854900 = { r1__read__h854902, 1'b0 } ; + assign r1__read__h854902 = { r1__read__h854904, csrf_mideleg_9_7_reg } ; + assign r1__read__h854904 = { r1__read__h854906, 1'b0 } ; + assign r1__read__h854906 = { 52'b0, csrf_mideleg_11_reg } ; + assign r1__read__h854920 = + { r1__read__h854922, csrf_software_int_en_vec_1 } ; + assign r1__read__h854922 = { r1__read__h854924, 1'b0 } ; + assign r1__read__h854924 = + { r1__read__h854926, csrf_software_int_en_vec_3 } ; + assign r1__read__h854926 = { r1__read__h854928, 1'b0 } ; + assign r1__read__h854928 = { r1__read__h854930, csrf_timer_int_en_vec_1 } ; + assign r1__read__h854930 = { r1__read__h854932, 1'b0 } ; + assign r1__read__h854932 = { r1__read__h854934, csrf_timer_int_en_vec_3 } ; + assign r1__read__h854934 = { r1__read__h854936, 1'b0 } ; + assign r1__read__h854936 = + { r1__read__h854938, csrf_external_int_en_vec_1 } ; + assign r1__read__h854938 = { r1__read__h854940, 1'b0 } ; + assign r1__read__h854940 = { 52'b0, csrf_external_int_en_vec_3 } ; + assign r1__read__h855196 = { r1__read__h855198, csrf_mcounteren_tm_reg } ; + assign r1__read__h855198 = { 61'd0, csrf_mcounteren_ir_reg } ; + assign r1__read__h855500 = { csrf_mcause_interrupt_reg, 58'd0 } ; + assign r1__read__h855507 = + { r1__read__h855509, csrf_software_int_pend_vec_1 } ; + assign r1__read__h855509 = { r1__read__h855511, 1'b0 } ; + assign r1__read__h855511 = + { r1__read__h855513, csrf_software_int_pend_vec_3 } ; + assign r1__read__h855513 = { r1__read__h855515, 1'b0 } ; + assign r1__read__h855515 = + { r1__read__h855517, csrf_timer_int_pend_vec_1 } ; + assign r1__read__h855517 = { r1__read__h855519, 1'b0 } ; + assign r1__read__h855519 = + { r1__read__h855521, csrf_timer_int_pend_vec_3 } ; + assign r1__read__h855521 = { r1__read__h855523, 1'b0 } ; + assign r1__read__h855523 = + { r1__read__h855525, csrf_external_int_pend_vec_1 } ; + assign r1__read__h855525 = { r1__read__h855527, 1'b0 } ; + assign r1__read__h855527 = { 52'b0, csrf_external_int_pend_vec_3 } ; + assign r1__read__h855836 = { 4'd0, csrf_rg_tdata1_dmode } ; + assign rVal1__h714517 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; + assign rVal2__h714518 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; + assign r___1__h706482 = 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[63:0] ; - assign r__h853139 = csrf_fs_reg == 2'b11 ; - assign r__h855583 = csrf_software_int_pend_vec_3 ; - assign regRenamingTable_RDY_rename_0_claimRename__102_ETC___d21039 = - regRenamingTable$RDY_rename_0_claimRename && - fetchStage$RDY_pipelines_0_deq && + assign r__h853138 = csrf_fs_reg == 2'b11 ; + assign r__h855582 = csrf_software_int_pend_vec_3 ; + assign regRenamingTable_RDY_rename_0_getRename__1028__ETC___d21039 = + regRenamingTable$RDY_rename_0_getRename && + rob$RDY_enqPort_0_enq && fetchStage$RDY_pipelines_0_first && - epochManager$RDY_incrementEpoch && + fetchStage$RDY_pipelines_0_deq && (fetchStage$pipelines_0_first[268:266] != 3'd0 && fetchStage$pipelines_0_first[238:237] != 2'd1 && fetchStage$pipelines_0_first[238:237] != 2'd0 || coreFix_aluExe_0_rsAlu$RDY_enq) ; - assign regRenamingTable_RDY_rename_0_getRename__1027__ETC___d21854 = + assign regRenamingTable_RDY_rename_0_getRename__1028__ETC___d21854 = regRenamingTable$RDY_rename_0_getRename && CASE_fetchStagepipelines_0_first_BITS_265_TO__ETC__q269 && (fetchStage$pipelines_0_first[273:269] == 5'd19 || @@ -37059,85 +37051,85 @@ module mkCore(CLK, fetchStage$pipelines_0_first[69] || checkForException___d20654[13] || !rob$enqPort_0_canEnq ; - assign renaming_spec_bits__h968741 = + assign renaming_spec_bits__h968739 = fetchStage$pipelines_0_canDeq ? - y_avValue_snd_fst__h963385 : + y_avValue_snd_fst__h963383 : specTagManager$currentSpecBits ; - assign repBoundBits__h242653 = + assign repBoundBits__h242650 = { coreFix_memExe_regToExeQ$first[231:229], 11'd0 } ; - assign repBound__h237318 = rf$read_3_rd1[13:11] - 3'b001 ; - assign repBound__h239003 = rf$read_3_rd2[13:11] - 3'b001 ; - assign repBound__h248218 = + assign repBound__h237315 = rf$read_3_rd1[13:11] - 3'b001 ; + assign repBound__h239000 = rf$read_3_rd2[13:11] - 3'b001 ; + assign repBound__h248215 = coreFix_memExe_regToExeQ$first[245:243] - 3'b001 ; - assign repBound__h248743 = csrf_ddc_reg[13:11] - 3'b001 ; - assign repBound__h854076 = csrf_stcc_reg[13:11] - 3'b001 ; - assign repBound__h854398 = + assign repBound__h248740 = csrf_ddc_reg[13:11] - 3'b001 ; + assign repBound__h854075 = csrf_stcc_reg[13:11] - 3'b001 ; + assign repBound__h854397 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16084[13:11] - 3'b001 ; - assign repBound__h855069 = csrf_mtcc_reg[13:11] - 3'b001 ; - assign repBound__h855390 = + assign repBound__h855068 = csrf_mtcc_reg[13:11] - 3'b001 ; + assign repBound__h855389 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16236[13:11] - 3'b001 ; - assign repBound__h855899 = csrf_rg_dpc[13:11] - 3'b001 ; - assign repBound__h857577 = rf$read_1_rd1[13:11] - 3'b001 ; - assign repBound__h860539 = rf$read_1_rd2[13:11] - 3'b001 ; - assign repBound__h860557 = thin_bounds_baseBits__h860422[13:11] - 3'b001 ; - assign repBound__h867140 = x__h867079[13:11] - 3'b001 ; - assign repBound__h867688 = x__h867627[13:11] - 3'b001 ; - assign repBound__h898286 = rf$read_0_rd1[13:11] - 3'b001 ; - assign repBound__h900613 = rf$read_0_rd2[13:11] - 3'b001 ; - assign repBound__h900631 = thin_bounds_baseBits__h900516[13:11] - 3'b001 ; - assign repBound__h906826 = x__h906765[13:11] - 3'b001 ; - assign repBound__h907374 = x__h907313[13:11] - 3'b001 ; - assign repBound__h997599 = x__h995129[13:11] - 3'b001 ; - assign res_addrBits__h126823 = + assign repBound__h855898 = csrf_rg_dpc[13:11] - 3'b001 ; + assign repBound__h857576 = rf$read_1_rd1[13:11] - 3'b001 ; + assign repBound__h860538 = rf$read_1_rd2[13:11] - 3'b001 ; + assign repBound__h860556 = thin_bounds_baseBits__h860421[13:11] - 3'b001 ; + assign repBound__h867139 = x__h867078[13:11] - 3'b001 ; + assign repBound__h867687 = x__h867626[13:11] - 3'b001 ; + assign repBound__h898284 = rf$read_0_rd1[13:11] - 3'b001 ; + assign repBound__h900611 = rf$read_0_rd2[13:11] - 3'b001 ; + assign repBound__h900629 = thin_bounds_baseBits__h900514[13:11] - 3'b001 ; + assign repBound__h906824 = x__h906763[13:11] - 3'b001 ; + assign repBound__h907372 = x__h907311[13:11] - 3'b001 ; + assign repBound__h997634 = x__h995127[13:11] - 3'b001 ; + assign res_addrBits__h126822 = INV_coreFix_memExe_respLrScAmoQ_data_0_BITS_10_ETC__q8[0] ? - x__h127303[13:0] : + x__h127302[13:0] : coreFix_memExe_respLrScAmoQ_data_0[13:0] ; - assign res_addrBits__h139735 = + assign res_addrBits__h139734 = INV_mmio_dataRespQ_data_0_BITS_108_TO_90__q9[0] ? - x__h140219[13:0] : + x__h140218[13:0] : mmio_dataRespQ_data_0[13:0] ; - assign res_addrBits__h178899 = - INV_x83399_BITS_108_TO_90__q34[0] ? - x__h183481[13:0] : - x__h183399[13:0] ; - assign res_addrBits__h197664 = - INV_x99251_BITS_108_TO_90__q36[0] ? - x__h202232[13:0] : - x__h199251[13:0] ; - assign res_addrBits__h216423 = + assign res_addrBits__h178897 = + INV_x83397_BITS_108_TO_90__q34[0] ? + x__h183479[13:0] : + x__h183397[13:0] ; + assign res_addrBits__h197662 = + INV_x99249_BITS_108_TO_90__q36[0] ? + x__h202230[13:0] : + x__h199249[13:0] ; + assign res_addrBits__h216421 = INV_coreFix_memExe_lsqrespLd_BITS_108_TO_90__q10[0] ? - x__h216798[13:0] : + x__h216796[13:0] : coreFix_memExe_lsq$respLd[13:0] ; - assign res_addrBits__h235324 = { 2'b0, addr__h235317[63:52] } ; - assign res_addrBits__h567347 = + assign res_addrBits__h235321 = { 2'b0, addr__h235314[63:52] } ; + assign res_addrBits__h567344 = { 2'b0, coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[101:90] } ; - assign res_addrBits__h568199 = { 2'b0, data__h567680[63:52] } ; - assign res_addrBits__h613956 = { 2'b0, data__h613440[63:52] } ; - assign res_addrBits__h659703 = { 2'b0, data__h659187[63:52] } ; - assign res_addrBits__h705512 = { 2'b0, data__h705001[63:52] } ; - assign res_addrBits__h706372 = { 2'b0, data__h705864[63:52] } ; - assign res_addrBits__h848645 = { 2'b0, addr__h843950[63:52] } ; - assign res_addrBits__h892146 = { 2'b0, addr__h887459[63:52] } ; - assign res_address__h126822 = + assign res_addrBits__h568197 = { 2'b0, data__h567678[63:52] } ; + assign res_addrBits__h613954 = { 2'b0, data__h613438[63:52] } ; + assign res_addrBits__h659701 = { 2'b0, data__h659185[63:52] } ; + assign res_addrBits__h705510 = { 2'b0, data__h704999[63:52] } ; + assign res_addrBits__h706370 = { 2'b0, data__h705862[63:52] } ; + assign res_addrBits__h848643 = { 2'b0, addr__h843948[63:52] } ; + assign res_addrBits__h892145 = { 2'b0, addr__h887458[63:52] } ; + assign res_address__h126821 = { 2'd0, coreFix_memExe_respLrScAmoQ_data_0[63:0] } ; - assign res_address__h139734 = { 2'd0, mmio_dataRespQ_data_0[63:0] } ; - assign res_address__h178898 = { 2'd0, x__h183399[63:0] } ; - assign res_address__h197663 = { 2'd0, x__h199251[63:0] } ; - assign res_address__h216422 = { 2'd0, coreFix_memExe_lsq$respLd[63:0] } ; - assign res_address__h235323 = { 2'd0, addr__h235317 } ; - assign res_address__h567346 = + assign res_address__h139733 = { 2'd0, mmio_dataRespQ_data_0[63:0] } ; + assign res_address__h178896 = { 2'd0, x__h183397[63:0] } ; + assign res_address__h197661 = { 2'd0, x__h199249[63:0] } ; + assign res_address__h216420 = { 2'd0, coreFix_memExe_lsq$respLd[63:0] } ; + assign res_address__h235320 = { 2'd0, addr__h235314 } ; + assign res_address__h567343 = { 2'd0, coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[101:38] } ; - assign res_address__h568198 = { 2'd0, data__h567680 } ; - assign res_address__h613955 = { 2'd0, data__h613440 } ; - assign res_address__h659702 = { 2'd0, data__h659187 } ; - assign res_address__h705511 = { 2'd0, data__h705001 } ; - assign res_address__h706371 = { 2'd0, data__h705864 } ; - assign res_address__h848644 = { 2'd0, addr__h843950 } ; - assign res_address__h892145 = { 2'd0, addr__h887459 } ; - assign res_data__h568238 = { 32'hFFFFFFFF, x__h568253 } ; - assign res_data__h568243 = + assign res_address__h568196 = { 2'd0, data__h567678 } ; + assign res_address__h613953 = { 2'd0, data__h613438 } ; + assign res_address__h659700 = { 2'd0, data__h659185 } ; + assign res_address__h705509 = { 2'd0, data__h704999 } ; + assign res_address__h706369 = { 2'd0, data__h705862 } ; + assign res_address__h848642 = { 2'd0, addr__h843948 } ; + assign res_address__h892144 = { 2'd0, addr__h887458 } ; + assign res_data__h568236 = { 32'hFFFFFFFF, x__h568251 } ; + assign res_data__h568241 = { (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == @@ -37150,8 +37142,8 @@ module mkCore(CLK, 52'd0) ? 63'h7FF8000000000000 : coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:5] } ; - assign res_data__h613992 = { 32'hFFFFFFFF, x__h614007 } ; - assign res_data__h613997 = + assign res_data__h613990 = { 32'hFFFFFFFF, x__h614005 } ; + assign res_data__h613995 = { (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == @@ -37164,8 +37156,8 @@ module mkCore(CLK, 52'd0) ? 63'h7FF8000000000000 : coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:5] } ; - assign res_data__h659739 = { 32'hFFFFFFFF, x__h659754 } ; - assign res_data__h659744 = + assign res_data__h659737 = { 32'hFFFFFFFF, x__h659752 } ; + assign res_data__h659742 = { (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == @@ -37178,7 +37170,7 @@ module mkCore(CLK, 52'd0) ? 63'h7FF8000000000000 : coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:5] } ; - assign res_fflags__h568239 = + assign res_fflags__h568237 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[38:34] | coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[4:0] | { (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != @@ -37246,7 +37238,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d9383 } ; - assign res_fflags__h613993 = + assign res_fflags__h613991 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[38:34] | coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[4:0] | { (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != @@ -37314,7 +37306,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d10780 } ; - assign res_fflags__h659740 = + assign res_fflags__h659738 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[38:34] | coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[4:0] | { (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != @@ -37325,8 +37317,7 @@ module mkCore(CLK, 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && - (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != - 11'd0 || + (value_BIT_52___h677325 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d12124, @@ -37338,8 +37329,7 @@ module mkCore(CLK, 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && - (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != - 11'd0 || + (value_BIT_52___h677325 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d12135, @@ -37351,8 +37341,7 @@ module mkCore(CLK, 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && - (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != - 11'd0 || + (value_BIT_52___h677325 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d12151, @@ -37364,8 +37353,7 @@ module mkCore(CLK, 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && - (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != - 11'd0 || + (value_BIT_52___h677325 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d12164, @@ -37377,143 +37365,142 @@ module mkCore(CLK, 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && - (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != - 11'd0 || + (value_BIT_52___h677325 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d12177 } ; - assign resp_addr__h509111 = + assign resp_addr__h509110 = { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot[53:1], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getRq[168:158] } ; - assign result__h240600 = + assign result__h240597 = { 1'd0, ~coreFix_memExe_regToExeQ_first__645_BITS_383_T_ETC___d3704[64], coreFix_memExe_regToExeQ_first__645_BITS_383_T_ETC___d3704[63:0] } ; - assign result__h241757 = + assign result__h241754 = { 1'd0, ~coreFix_memExe_regToExeQ_first__645_BITS_220_T_ETC___d3766[64], coreFix_memExe_regToExeQ_first__645_BITS_220_T_ETC___d3766[63:0] } ; - assign result__h255381 = + assign result__h255378 = { 1'd0, ~coreFix_memExe_dTlb_procResp__257_BITS_452_TO__ETC___d4407[64], coreFix_memExe_dTlb_procResp__257_BITS_452_TO__ETC___d4407[63:0] } ; - assign result__h594706 = + assign result__h594704 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d8681[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d8681[0] | - guard__h594701 } ; - assign result__h640455 = + guard__h594699 } ; + assign result__h640453 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d10078[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d10078[0] | - guard__h640450 } ; - assign result__h686202 = + guard__h640448 } ; + assign result__h686200 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d11475[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d11475[0] | - guard__h686197 } ; - assign result__h736241 = + guard__h686195 } ; + assign result__h736238 = { _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d12804[56:1], _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d12804[0] | - guard__h736236 } ; - assign result__h775094 = + guard__h736233 } ; + assign result__h775091 = { _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d14289[56:1], _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d14289[0] | - guard__h775089 } ; - assign result__h814398 = + guard__h775086 } ; + assign result__h814395 = { _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d13519[56:1], _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d13519[0] | - guard__h814393 } ; - assign result__h915810 = w__h915805 & y__h915839 ; - assign result__h915861 = ~x__h915860 ; - assign result_d_addrBits__h1008567 = + guard__h814390 } ; + assign result__h915808 = w__h915803 & y__h915837 ; + assign result__h915859 = ~x__h915858 ; + assign result_d_addrBits__h1008602 = (csrf_stcc_reg[33:28] == 6'd52) ? - { 1'b0, newAddrBits__h1008555[12:0] } : - newAddrBits__h1008555[13:0] ; - assign result_d_addrBits__h1008970 = + { 1'b0, newAddrBits__h1008590[12:0] } : + newAddrBits__h1008590[13:0] ; + assign result_d_addrBits__h1009005 = (IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16100 == 6'd52) ? - { 1'b0, newAddrBits__h1008958[12:0] } : - newAddrBits__h1008958[13:0] ; - assign result_d_addrBits__h1009387 = + { 1'b0, newAddrBits__h1008993[12:0] } : + newAddrBits__h1008993[13:0] ; + assign result_d_addrBits__h1009422 = (csrf_mtcc_reg[33:28] == 6'd52) ? - { 1'b0, newAddrBits__h1009375[12:0] } : - newAddrBits__h1009375[13:0] ; - assign result_d_addrBits__h1009790 = + { 1'b0, newAddrBits__h1009410[12:0] } : + newAddrBits__h1009410[13:0] ; + assign result_d_addrBits__h1009825 = (IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16252 == 6'd52) ? - { 1'b0, newAddrBits__h1009778[12:0] } : - newAddrBits__h1009778[13:0] ; - assign result_d_addrBits__h1010459 = + { 1'b0, newAddrBits__h1009813[12:0] } : + newAddrBits__h1009813[13:0] ; + assign result_d_addrBits__h1010494 = (csrf_rg_dpc[33:28] == 6'd52) ? - { 1'b0, newAddrBits__h1010447[12:0] } : - newAddrBits__h1010447[13:0] ; - assign result_d_addrBits__h1031618 = + { 1'b0, newAddrBits__h1010482[12:0] } : + newAddrBits__h1010482[13:0] ; + assign result_d_addrBits__h1031652 = (csrf_stcc_reg[33:28] == 6'd52) ? - { 1'b0, newAddrBits__h1031606[12:0] } : - newAddrBits__h1031606[13:0] ; - assign result_d_addrBits__h1032021 = + { 1'b0, newAddrBits__h1031640[12:0] } : + newAddrBits__h1031640[13:0] ; + assign result_d_addrBits__h1032055 = (IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16100 == 6'd52) ? - { 1'b0, newAddrBits__h1032009[12:0] } : - newAddrBits__h1032009[13:0] ; - assign result_d_addrBits__h1032438 = + { 1'b0, newAddrBits__h1032043[12:0] } : + newAddrBits__h1032043[13:0] ; + assign result_d_addrBits__h1032472 = (csrf_mtcc_reg[33:28] == 6'd52) ? - { 1'b0, newAddrBits__h1032426[12:0] } : - newAddrBits__h1032426[13:0] ; - assign result_d_addrBits__h1032841 = + { 1'b0, newAddrBits__h1032460[12:0] } : + newAddrBits__h1032460[13:0] ; + assign result_d_addrBits__h1032875 = (IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16252 == 6'd52) ? - { 1'b0, newAddrBits__h1032829[12:0] } : - newAddrBits__h1032829[13:0] ; - assign result_d_addrBits__h1033508 = + { 1'b0, newAddrBits__h1032863[12:0] } : + newAddrBits__h1032863[13:0] ; + assign result_d_addrBits__h1033542 = (csrf_rg_dpc[33:28] == 6'd52) ? - { 1'b0, newAddrBits__h1033496[12:0] } : - newAddrBits__h1033496[13:0] ; - assign result_d_address__h1008566 = - { 2'd0, bot__h1008588 } + + { 1'b0, newAddrBits__h1033530[12:0] } : + newAddrBits__h1033530[13:0] ; + assign result_d_address__h1008601 = + { 2'd0, bot__h1008623 } + { 2'd0, rob$deqPort_0_deq_data[95:32] } ; - assign result_d_address__h1008969 = - { 2'd0, bot__h1008991 } + + assign result_d_address__h1009004 = + { 2'd0, bot__h1009026 } + { 2'd0, rob$deqPort_0_deq_data[95:32] } ; - assign result_d_address__h1009386 = - { 2'd0, bot__h1009408 } + + assign result_d_address__h1009421 = + { 2'd0, bot__h1009443 } + { 2'd0, rob$deqPort_0_deq_data[95:32] } ; - assign result_d_address__h1009789 = - { 2'd0, bot__h1009811 } + + assign result_d_address__h1009824 = + { 2'd0, bot__h1009846 } + { 2'd0, rob$deqPort_0_deq_data[95:32] } ; - assign result_d_address__h1010458 = - { 2'd0, bot__h1010481 } + + assign result_d_address__h1010493 = + { 2'd0, bot__h1010516 } + { 2'd0, rob$deqPort_0_deq_data[95:32] } ; - assign result_d_address__h1031617 = - { 2'd0, bot__h1008588 } + { 2'd0, f_csr_reqs$D_OUT[63:0] } ; - assign result_d_address__h1032020 = - { 2'd0, bot__h1008991 } + { 2'd0, f_csr_reqs$D_OUT[63:0] } ; - assign result_d_address__h1032437 = - { 2'd0, bot__h1009408 } + { 2'd0, f_csr_reqs$D_OUT[63:0] } ; - assign result_d_address__h1032840 = - { 2'd0, bot__h1009811 } + { 2'd0, f_csr_reqs$D_OUT[63:0] } ; - assign result_d_address__h1033507 = - { 2'd0, bot__h1010481 } + { 2'd0, f_csr_reqs$D_OUT[63:0] } ; - assign result_d_address__h242849 = { 2'd0, pointer__h242638[63:0] } ; - assign ret__h239977 = + assign result_d_address__h1031651 = + { 2'd0, bot__h1008623 } + { 2'd0, f_csr_reqs$D_OUT[63:0] } ; + assign result_d_address__h1032054 = + { 2'd0, bot__h1009026 } + { 2'd0, f_csr_reqs$D_OUT[63:0] } ; + assign result_d_address__h1032471 = + { 2'd0, bot__h1009443 } + { 2'd0, f_csr_reqs$D_OUT[63:0] } ; + assign result_d_address__h1032874 = + { 2'd0, bot__h1009846 } + { 2'd0, f_csr_reqs$D_OUT[63:0] } ; + assign result_d_address__h1033541 = + { 2'd0, bot__h1010516 } + { 2'd0, f_csr_reqs$D_OUT[63:0] } ; + assign result_d_address__h242846 = { 2'd0, pointer__h242635[63:0] } ; + assign ret__h239974 = { 1'd0, coreFix_memExe_regToExeQ_first__645_BITS_383_T_ETC___d3704[64:0] } ; - assign ret__h241134 = + assign ret__h241131 = { 1'd0, coreFix_memExe_regToExeQ_first__645_BITS_220_T_ETC___d3766[64:0] } ; - assign ret__h254758 = + assign ret__h254755 = { 1'd0, coreFix_memExe_dTlb_procResp__257_BITS_452_TO__ETC___d4407[64:0] } ; assign rf_read_0_rd1_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19097 = - rf$read_0_rd1[27:25] < repBound__h898286 ; + rf$read_0_rd1[27:25] < repBound__h898284 ; assign rf_read_0_rd1_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19110 = - rf$read_0_rd1[13:11] < repBound__h898286 ; + rf$read_0_rd1[13:11] < repBound__h898284 ; assign rf_read_0_rd1_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19124 = - rf$read_0_rd1[85:83] < repBound__h898286 ; + rf$read_0_rd1[85:83] < repBound__h898284 ; assign rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19168 = - rf$read_0_rd2[27:25] < repBound__h900613 ; + rf$read_0_rd2[27:25] < repBound__h900611 ; assign rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19169 = - rf$read_0_rd2[13:11] < repBound__h900613 ; + rf$read_0_rd2[13:11] < repBound__h900611 ; assign rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19171 = - rf$read_0_rd2[85:83] < repBound__h900613 ; + rf$read_0_rd2[85:83] < repBound__h900611 ; assign rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19181 = { rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19171, (rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19168 == @@ -37531,17 +37518,17 @@ module mkCore(CLK, 2'd1 : 2'd3) } ; assign rf_read_1_rd1_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16702 = - rf$read_1_rd1[27:25] < repBound__h857577 ; + rf$read_1_rd1[27:25] < repBound__h857576 ; assign rf_read_1_rd1_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16715 = - rf$read_1_rd1[13:11] < repBound__h857577 ; + rf$read_1_rd1[13:11] < repBound__h857576 ; assign rf_read_1_rd1_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16729 = - rf$read_1_rd1[85:83] < repBound__h857577 ; + rf$read_1_rd1[85:83] < repBound__h857576 ; assign rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16773 = - rf$read_1_rd2[27:25] < repBound__h860539 ; + rf$read_1_rd2[27:25] < repBound__h860538 ; assign rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16774 = - rf$read_1_rd2[13:11] < repBound__h860539 ; + rf$read_1_rd2[13:11] < repBound__h860538 ; assign rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16776 = - rf$read_1_rd2[85:83] < repBound__h860539 ; + rf$read_1_rd2[85:83] < repBound__h860538 ; assign rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16786 = { rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16776, (rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16773 == @@ -37559,25 +37546,25 @@ module mkCore(CLK, 2'd1 : 2'd3) } ; assign rf_read_3_rd1_coreFix_memExe_dispToRegQ_first__ETC___d3331 = - rf$read_3_rd1[27:25] < repBound__h237318 ; + rf$read_3_rd1[27:25] < repBound__h237315 ; assign rf_read_3_rd1_coreFix_memExe_dispToRegQ_first__ETC___d3344 = - rf$read_3_rd1[13:11] < repBound__h237318 ; + rf$read_3_rd1[13:11] < repBound__h237315 ; assign rf_read_3_rd1_coreFix_memExe_dispToRegQ_first__ETC___d3358 = - rf$read_3_rd1[85:83] < repBound__h237318 ; + rf$read_3_rd1[85:83] < repBound__h237315 ; assign rf_read_3_rd2_coreFix_memExe_dispToRegQ_first__ETC___d3592 = - rf$read_3_rd2[27:25] < repBound__h239003 ; + rf$read_3_rd2[27:25] < repBound__h239000 ; assign rf_read_3_rd2_coreFix_memExe_dispToRegQ_first__ETC___d3600 = - rf$read_3_rd2[13:11] < repBound__h239003 ; + rf$read_3_rd2[13:11] < repBound__h239000 ; assign rf_read_3_rd2_coreFix_memExe_dispToRegQ_first__ETC___d3609 = - rf$read_3_rd2[85:83] < repBound__h239003 ; - assign rg_core_run_state_read__0682_EQ_2_0683_AND_NOT_ETC___d23893 = + rf$read_3_rd2[85:83] < repBound__h239000 ; + assign rg_core_run_state_read__0682_EQ_2_0683_AND_NOT_ETC___d23895 = rg_core_run_state == 2'd2 && !flush_reservation && !flush_tlbs && !update_vm_info && fetchStage$iTlbIfc_flush_done && coreFix_memExe_dTlb$flush_done && !flush_caches ; - assign rg_tdata1__read__h852226 = - { r1__read__h855837, csrf_rg_tdata1_data } ; + assign rg_tdata1__read__h852225 = + { r1__read__h855836, csrf_rg_tdata1_data } ; assign rob_enqPort_1_canEnq__1634_AND_epochManager_ch_ETC___d21639 = rob$enqPort_1_canEnq && epochManager$checkEpoch_1_check && (!fetchStage$pipelines_0_canDeq || @@ -37585,9 +37572,9 @@ module mkCore(CLK, specTagManager$canClaim) && regRenamingTable_rename_0_canRename__1151_AND__ETC___d21245 && IF_IF_fetchStage_pipelines_0_first__0256_BITS__ETC___d21231) ; - assign robdeqPort_0_deq_data_BITS_95_TO_32__q16 = + assign robdeqPort_0_deq_data_BITS_95_TO_32__q17 = rob$deqPort_0_deq_data[95:32] ; - assign satp_csr__read__h849916 = { r1__read__h854726, csrf_ppn_reg } ; + assign satp_csr__read__h849915 = { r1__read__h854725, csrf_ppn_reg } ; assign sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d12442 = (sbCons$lazyLookup_2_get[2] || IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d12398 && @@ -37607,295 +37594,295 @@ module mkCore(CLK, (sbCons$lazyLookup_3_get[2] || IF_coreFix_memExe_dispToRegQ_RDY_first__685_AN_ETC___d2748 && IF_NOT_coreFix_memExe_bypassWire_0_whas__704_7_ETC___d2765) ; - assign sbIdx__h152016 = + assign sbIdx__h152015 = CAN_FIRE_RL_coreFix_memExe_doIssueSB ? coreFix_memExe_reqStQ_data_0_lat_0$wget[65:64] : coreFix_memExe_reqStQ_data_0_rl[65:64] ; - assign scause_csr__read__h849713 = - { r1__read__h854509, csrf_scause_code_reg } ; - assign scounteren_csr__read__h849573 = - { r1__read__h854204, csrf_scounteren_cy_reg } ; - assign sfd__h568849 = { value__h577076, 3'd0 } ; - assign sfd__h584657 = + assign scause_csr__read__h849712 = + { r1__read__h854508, csrf_scause_code_reg } ; + assign scounteren_csr__read__h849572 = + { r1__read__h854203, csrf_scounteren_cy_reg } ; + assign sfd__h568847 = { value__h577074, 3'd0 } ; + assign sfd__h584655 = { 1'b0, - _theResult___fst_exp__h584565 != 8'd0, - sfdin__h584559[56:34] } + + _theResult___fst_exp__h584563 != 8'd0, + sfdin__h584557[56:34] } + 25'd1 ; - assign sfd__h593239 = + assign sfd__h593237 = { 1'b0, - _theResult___fst_exp__h593221 != 8'd0, - _theResult___snd__h593172[56:34] } + + _theResult___fst_exp__h593219 != 8'd0, + _theResult___snd__h593170[56:34] } + 25'd1 ; - assign sfd__h602423 = + assign sfd__h602421 = { 1'b0, - _theResult___fst_exp__h602331 != 8'd0, - sfdin__h602325[56:34] } + + _theResult___fst_exp__h602329 != 8'd0, + sfdin__h602323[56:34] } + 25'd1 ; - assign sfd__h611035 = + assign sfd__h611033 = { 1'b0, - _theResult___fst_exp__h611016 != 8'd0, - _theResult___snd__h610962[56:34] } + + _theResult___fst_exp__h611014 != 8'd0, + _theResult___snd__h610960[56:34] } + 25'd1 ; - assign sfd__h614603 = { value__h622825, 3'd0 } ; - assign sfd__h630406 = + assign sfd__h614601 = { value__h622823, 3'd0 } ; + assign sfd__h630404 = { 1'b0, - _theResult___fst_exp__h630314 != 8'd0, - sfdin__h630308[56:34] } + + _theResult___fst_exp__h630312 != 8'd0, + sfdin__h630306[56:34] } + 25'd1 ; - assign sfd__h638988 = + assign sfd__h638986 = { 1'b0, - _theResult___fst_exp__h638970 != 8'd0, - _theResult___snd__h638921[56:34] } + + _theResult___fst_exp__h638968 != 8'd0, + _theResult___snd__h638919[56:34] } + 25'd1 ; - assign sfd__h648172 = + assign sfd__h648170 = { 1'b0, - _theResult___fst_exp__h648080 != 8'd0, - sfdin__h648074[56:34] } + + _theResult___fst_exp__h648078 != 8'd0, + sfdin__h648072[56:34] } + 25'd1 ; - assign sfd__h656784 = + assign sfd__h656782 = { 1'b0, - _theResult___fst_exp__h656765 != 8'd0, - _theResult___snd__h656711[56:34] } + + _theResult___fst_exp__h656763 != 8'd0, + _theResult___snd__h656709[56:34] } + 25'd1 ; - assign sfd__h660350 = { value__h668572, 3'd0 } ; - assign sfd__h676153 = + assign sfd__h660348 = { value__h668570, 3'd0 } ; + assign sfd__h676151 = { 1'b0, - _theResult___fst_exp__h676061 != 8'd0, - sfdin__h676055[56:34] } + + _theResult___fst_exp__h676059 != 8'd0, + sfdin__h676053[56:34] } + 25'd1 ; - assign sfd__h684735 = + assign sfd__h684733 = { 1'b0, - _theResult___fst_exp__h684717 != 8'd0, - _theResult___snd__h684668[56:34] } + + _theResult___fst_exp__h684715 != 8'd0, + _theResult___snd__h684666[56:34] } + 25'd1 ; - assign sfd__h693919 = + assign sfd__h693917 = { 1'b0, - _theResult___fst_exp__h693827 != 8'd0, - sfdin__h693821[56:34] } + + _theResult___fst_exp__h693825 != 8'd0, + sfdin__h693819[56:34] } + 25'd1 ; - assign sfd__h702531 = + assign sfd__h702529 = { 1'b0, - _theResult___fst_exp__h702512 != 8'd0, - _theResult___snd__h702458[56:34] } + + _theResult___fst_exp__h702510 != 8'd0, + _theResult___snd__h702456[56:34] } + 25'd1 ; - assign sfd__h715261 = { value__h719844, 32'd0 } ; - assign sfd__h734305 = + assign sfd__h715258 = { value__h719841, 32'd0 } ; + assign sfd__h734302 = { 1'b0, - _theResult___fst_exp__h734287 != 11'd0, - _theResult___snd__h734238[56:5] } + + _theResult___fst_exp__h734284 != 11'd0, + _theResult___snd__h734235[56:5] } + 54'd1 ; - assign sfd__h743956 = + assign sfd__h743953 = { 1'b0, - _theResult___fst_exp__h743864 != 11'd0, - sfdin__h743858[56:5] } + + _theResult___fst_exp__h743861 != 11'd0, + sfdin__h743855[56:5] } + 54'd1 ; - assign sfd__h752716 = + assign sfd__h752713 = { 1'b0, - _theResult___fst_exp__h752697 != 11'd0, - _theResult___snd__h752643[56:5] } + + _theResult___fst_exp__h752694 != 11'd0, + _theResult___snd__h752640[56:5] } + 54'd1 ; - assign sfd__h754255 = { value__h758697, 32'd0 } ; - assign sfd__h773158 = + assign sfd__h754252 = { value__h758694, 32'd0 } ; + assign sfd__h773155 = { 1'b0, - _theResult___fst_exp__h773140 != 11'd0, - _theResult___snd__h773091[56:5] } + + _theResult___fst_exp__h773137 != 11'd0, + _theResult___snd__h773088[56:5] } + 54'd1 ; - assign sfd__h782809 = + assign sfd__h782806 = { 1'b0, - _theResult___fst_exp__h782717 != 11'd0, - sfdin__h782711[56:5] } + + _theResult___fst_exp__h782714 != 11'd0, + sfdin__h782708[56:5] } + 54'd1 ; - assign sfd__h791569 = + assign sfd__h791566 = { 1'b0, - _theResult___fst_exp__h791550 != 11'd0, - _theResult___snd__h791496[56:5] } + + _theResult___fst_exp__h791547 != 11'd0, + _theResult___snd__h791493[56:5] } + 54'd1 ; - assign sfd__h793559 = { value__h798001, 32'd0 } ; - assign sfd__h812462 = + assign sfd__h793556 = { value__h797998, 32'd0 } ; + assign sfd__h812459 = { 1'b0, - _theResult___fst_exp__h812444 != 11'd0, - _theResult___snd__h812395[56:5] } + + _theResult___fst_exp__h812441 != 11'd0, + _theResult___snd__h812392[56:5] } + 54'd1 ; - assign sfd__h822113 = + assign sfd__h822110 = { 1'b0, - _theResult___fst_exp__h822021 != 11'd0, - sfdin__h822015[56:5] } + + _theResult___fst_exp__h822018 != 11'd0, + sfdin__h822012[56:5] } + 54'd1 ; - assign sfd__h830873 = + assign sfd__h830870 = { 1'b0, - _theResult___fst_exp__h830854 != 11'd0, - _theResult___snd__h830800[56:5] } + + _theResult___fst_exp__h830851 != 11'd0, + _theResult___snd__h830797[56:5] } + 54'd1 ; - assign sfdin__h584559 = - _theResult____h576454[56] ? - _theResult___snd__h584576 : - _theResult___snd__h584587 ; - assign sfdin__h602325 = - _theResult____h594093[56] ? - _theResult___snd__h602342 : - _theResult___snd__h602353 ; - assign sfdin__h630308 = - _theResult____h622205[56] ? - _theResult___snd__h630325 : - _theResult___snd__h630336 ; - assign sfdin__h648074 = - _theResult____h639842[56] ? - _theResult___snd__h648091 : - _theResult___snd__h648102 ; - assign sfdin__h676055 = - _theResult____h667952[56] ? - _theResult___snd__h676072 : - _theResult___snd__h676083 ; - assign sfdin__h693821 = - _theResult____h685589[56] ? - _theResult___snd__h693838 : - _theResult___snd__h693849 ; - assign sfdin__h743858 = - _theResult____h735628[56] ? - _theResult___snd__h743875 : - _theResult___snd__h743886 ; - assign sfdin__h782711 = - _theResult____h774481[56] ? - _theResult___snd__h782728 : - _theResult___snd__h782739 ; - assign sfdin__h822015 = - _theResult____h813785[56] ? - _theResult___snd__h822032 : - _theResult___snd__h822043 ; - assign sie_csr__read__h849485 = { r1__read__h853511, 1'b0 } ; - assign signBits__h1008370 = - {50{robdeqPort_0_deq_data_BITS_95_TO_32__q16[63]}} ; - assign signBits__h1031421 = {50{f_csr_reqs$D_OUT[63]}} ; - assign signBits__h242644 = {50{offset__h242628[63]}} ; - assign sip_csr__read__h849853 = { r1__read__h854516, 1'b0 } ; - assign spec_bits__h973792 = specTagManager$currentSpecBits | y__h973805 ; - assign sstatus_csr__read__h849415 = { r1__read__h853107, csrf_ie_vec_0 } ; - assign tb__h867137 = { impliedTopBits__h866991, topBits__h866987[11] } ; - assign tb__h867685 = { impliedTopBits__h867539, topBits__h867535[11] } ; - assign tb__h906823 = { impliedTopBits__h906677, topBits__h906673[11] } ; - assign tb__h907371 = { impliedTopBits__h907225, topBits__h907221[11] } ; - assign thin_address__h999382 = - csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22647 ? - IF_csrf_stcc_reg_read__6046_BIT_86_2736_AND_NO_ETC___d22904 : - IF_csrf_mtcc_reg_read__6198_BIT_86_2807_AND_NO_ETC___d22905 ; - assign tmpAddr__h242837 = pointer__h242638[63:0] ; - assign tmp_expBotHalf__h127296 = + assign sfdin__h584557 = + _theResult____h576452[56] ? + _theResult___snd__h584574 : + _theResult___snd__h584585 ; + assign sfdin__h602323 = + _theResult____h594091[56] ? + _theResult___snd__h602340 : + _theResult___snd__h602351 ; + assign sfdin__h630306 = + _theResult____h622203[56] ? + _theResult___snd__h630323 : + _theResult___snd__h630334 ; + assign sfdin__h648072 = + _theResult____h639840[56] ? + _theResult___snd__h648089 : + _theResult___snd__h648100 ; + assign sfdin__h676053 = + _theResult____h667950[56] ? + _theResult___snd__h676070 : + _theResult___snd__h676081 ; + assign sfdin__h693819 = + _theResult____h685587[56] ? + _theResult___snd__h693836 : + _theResult___snd__h693847 ; + assign sfdin__h743855 = + _theResult____h735625[56] ? + _theResult___snd__h743872 : + _theResult___snd__h743883 ; + assign sfdin__h782708 = + _theResult____h774478[56] ? + _theResult___snd__h782725 : + _theResult___snd__h782736 ; + assign sfdin__h822012 = + _theResult____h813782[56] ? + _theResult___snd__h822029 : + _theResult___snd__h822040 ; + assign sie_csr__read__h849484 = { r1__read__h853510, 1'b0 } ; + assign signBits__h1008405 = + {50{robdeqPort_0_deq_data_BITS_95_TO_32__q17[63]}} ; + assign signBits__h1031455 = {50{f_csr_reqs$D_OUT[63]}} ; + assign signBits__h242641 = {50{offset__h242625[63]}} ; + assign sip_csr__read__h849852 = { r1__read__h854515, 1'b0 } ; + assign spec_bits__h973790 = specTagManager$currentSpecBits | y__h973803 ; + assign sstatus_csr__read__h849414 = { r1__read__h853106, csrf_ie_vec_0 } ; + assign tb__h867136 = { impliedTopBits__h866990, topBits__h866986[11] } ; + assign tb__h867684 = { impliedTopBits__h867538, topBits__h867534[11] } ; + assign tb__h906821 = { impliedTopBits__h906675, topBits__h906671[11] } ; + assign tb__h907369 = { impliedTopBits__h907223, topBits__h907219[11] } ; + assign thin_address__h999417 = + csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22648 ? + IF_csrf_stcc_reg_read__6046_BIT_86_2738_AND_NO_ETC___d22906 : + IF_csrf_mtcc_reg_read__6198_BIT_86_2809_AND_NO_ETC___d22907 ; + assign tmpAddr__h242834 = pointer__h242635[63:0] ; + assign tmp_expBotHalf__h127295 = { ~coreFix_memExe_respLrScAmoQ_data_0[66], coreFix_memExe_respLrScAmoQ_data_0[65:64] } ; - assign tmp_expBotHalf__h140212 = + assign tmp_expBotHalf__h140211 = { ~mmio_dataRespQ_data_0[66], mmio_dataRespQ_data_0[65:64] } ; - assign tmp_expBotHalf__h183474 = { ~x__h183399[66], x__h183399[65:64] } ; - assign tmp_expBotHalf__h202225 = { ~x__h199251[66], x__h199251[65:64] } ; - assign tmp_expBotHalf__h216791 = + assign tmp_expBotHalf__h183472 = { ~x__h183397[66], x__h183397[65:64] } ; + assign tmp_expBotHalf__h202223 = { ~x__h199249[66], x__h199249[65:64] } ; + assign tmp_expBotHalf__h216789 = { ~coreFix_memExe_lsq$respLd[66], coreFix_memExe_lsq$respLd[65:64] } ; - assign tmp_expBotHalf__h866840 = + assign tmp_expBotHalf__h866839 = { ~coreFix_aluExe_1_regToExeQ$first[244], coreFix_aluExe_1_regToExeQ$first[243:242] } ; - assign tmp_expBotHalf__h867388 = + assign tmp_expBotHalf__h867387 = { ~coreFix_aluExe_1_regToExeQ$first[115], coreFix_aluExe_1_regToExeQ$first[114:113] } ; - assign tmp_expBotHalf__h906526 = + assign tmp_expBotHalf__h906524 = { ~coreFix_aluExe_0_regToExeQ$first[244], coreFix_aluExe_0_regToExeQ$first[243:242] } ; - assign tmp_expBotHalf__h907074 = + assign tmp_expBotHalf__h907072 = { ~coreFix_aluExe_0_regToExeQ$first[115], coreFix_aluExe_0_regToExeQ$first[114:113] } ; - assign tmp_expBotHalf__h994904 = + assign tmp_expBotHalf__h994902 = { ~commitStage_commitTrap[175], commitStage_commitTrap[174:173] } ; - assign tmp_expTopHalf__h127294 = + assign tmp_expTopHalf__h127293 = { ~coreFix_memExe_respLrScAmoQ_data_0[80:79], coreFix_memExe_respLrScAmoQ_data_0[78] } ; - assign tmp_expTopHalf__h140210 = + assign tmp_expTopHalf__h140209 = { ~mmio_dataRespQ_data_0[80:79], mmio_dataRespQ_data_0[78] } ; - assign tmp_expTopHalf__h183472 = { ~x__h183399[80:79], x__h183399[78] } ; - assign tmp_expTopHalf__h202223 = { ~x__h199251[80:79], x__h199251[78] } ; - assign tmp_expTopHalf__h216789 = + assign tmp_expTopHalf__h183470 = { ~x__h183397[80:79], x__h183397[78] } ; + assign tmp_expTopHalf__h202221 = { ~x__h199249[80:79], x__h199249[78] } ; + assign tmp_expTopHalf__h216787 = { ~coreFix_memExe_lsq$respLd[80:79], coreFix_memExe_lsq$respLd[78] } ; - assign tmp_expTopHalf__h866838 = + assign tmp_expTopHalf__h866837 = { ~coreFix_aluExe_1_regToExeQ$first[258:257], coreFix_aluExe_1_regToExeQ$first[256] } ; - assign tmp_expTopHalf__h867386 = + assign tmp_expTopHalf__h867385 = { ~coreFix_aluExe_1_regToExeQ$first[129:128], coreFix_aluExe_1_regToExeQ$first[127] } ; - assign tmp_expTopHalf__h906524 = + assign tmp_expTopHalf__h906522 = { ~coreFix_aluExe_0_regToExeQ$first[258:257], coreFix_aluExe_0_regToExeQ$first[256] } ; - assign tmp_expTopHalf__h907072 = + assign tmp_expTopHalf__h907070 = { ~coreFix_aluExe_0_regToExeQ$first[129:128], coreFix_aluExe_0_regToExeQ$first[127] } ; - assign tmp_expTopHalf__h994902 = + assign tmp_expTopHalf__h994900 = { ~commitStage_commitTrap[189:188], commitStage_commitTrap[187] } ; - assign toBoundsM1__h1008383 = { 3'b110, ~csrf_stcc_reg[10:0] } ; - assign toBoundsM1__h1008786 = + assign toBoundsM1__h1008418 = { 3'b110, ~csrf_stcc_reg[10:0] } ; + assign toBoundsM1__h1008821 = { 3'b110, ~IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16084[10:0] } ; - assign toBoundsM1__h1009203 = { 3'b110, ~csrf_mtcc_reg[10:0] } ; - assign toBoundsM1__h1009606 = + assign toBoundsM1__h1009238 = { 3'b110, ~csrf_mtcc_reg[10:0] } ; + assign toBoundsM1__h1009641 = { 3'b110, ~IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16236[10:0] } ; - assign toBoundsM1__h1010275 = { 3'b110, ~csrf_rg_dpc[10:0] } ; - assign toBoundsM1__h242657 = - repBoundBits__h242653 + + assign toBoundsM1__h1010310 = { 3'b110, ~csrf_rg_dpc[10:0] } ; + assign toBoundsM1__h242654 = + repBoundBits__h242650 + ~coreFix_memExe_regToExeQ$first[317:304] ; - assign toBounds__h1008382 = 14'd14336 - { 3'b0, csrf_stcc_reg[10:0] } ; - assign toBounds__h1008785 = + assign toBounds__h1008417 = 14'd14336 - { 3'b0, csrf_stcc_reg[10:0] } ; + assign toBounds__h1008820 = 14'd14336 - { 3'b0, IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16084[10:0] } ; - assign toBounds__h1009202 = 14'd14336 - { 3'b0, csrf_mtcc_reg[10:0] } ; - assign toBounds__h1009605 = + assign toBounds__h1009237 = 14'd14336 - { 3'b0, csrf_mtcc_reg[10:0] } ; + assign toBounds__h1009640 = 14'd14336 - { 3'b0, IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16236[10:0] } ; - assign toBounds__h1010274 = 14'd14336 - { 3'b0, csrf_rg_dpc[10:0] } ; - assign toBounds__h242656 = - repBoundBits__h242653 - coreFix_memExe_regToExeQ$first[317:304] ; - assign topBits__h127430 = + assign toBounds__h1010309 = 14'd14336 - { 3'b0, csrf_rg_dpc[10:0] } ; + assign toBounds__h242653 = + repBoundBits__h242650 - coreFix_memExe_regToExeQ$first[317:304] ; + assign topBits__h127429 = INV_coreFix_memExe_respLrScAmoQ_data_0_BITS_10_ETC__q8[0] ? { coreFix_memExe_respLrScAmoQ_data_0[89:81], 3'd0 } : - b_top__h127527 ; - assign topBits__h140346 = + b_top__h127526 ; + assign topBits__h140345 = INV_mmio_dataRespQ_data_0_BITS_108_TO_90__q9[0] ? { mmio_dataRespQ_data_0[89:81], 3'd0 } : - b_top__h140443 ; - assign topBits__h183608 = - INV_x83399_BITS_108_TO_90__q34[0] ? - { x__h183399[89:81], 3'd0 } : - b_top__h183705 ; - assign topBits__h202359 = - INV_x99251_BITS_108_TO_90__q36[0] ? - { x__h199251[89:81], 3'd0 } : - b_top__h202456 ; - assign topBits__h216925 = + b_top__h140442 ; + assign topBits__h183606 = + INV_x83397_BITS_108_TO_90__q34[0] ? + { x__h183397[89:81], 3'd0 } : + b_top__h183703 ; + assign topBits__h202357 = + INV_x99249_BITS_108_TO_90__q36[0] ? + { x__h199249[89:81], 3'd0 } : + b_top__h202454 ; + assign topBits__h216923 = INV_coreFix_memExe_lsqrespLd_BITS_108_TO_90__q10[0] ? { coreFix_memExe_lsq$respLd[89:81], 3'd0 } : - b_top__h217022 ; - assign topBits__h866987 = + b_top__h217020 ; + assign topBits__h866986 = INV_coreFix_aluExe_1_regToExeQfirst_BITS_286__ETC__q11[0] ? { coreFix_aluExe_1_regToExeQ$first[267:259], 3'd0 } : - b_top__h867085 ; - assign topBits__h867535 = + b_top__h867084 ; + assign topBits__h867534 = INV_coreFix_aluExe_1_regToExeQfirst_BITS_157__ETC__q12[0] ? { coreFix_aluExe_1_regToExeQ$first[138:130], 3'd0 } : - b_top__h867633 ; - assign topBits__h906673 = + b_top__h867632 ; + assign topBits__h906671 = INV_coreFix_aluExe_0_regToExeQfirst_BITS_286__ETC__q13[0] ? { coreFix_aluExe_0_regToExeQ$first[267:259], 3'd0 } : - b_top__h906771 ; - assign topBits__h907221 = + b_top__h906769 ; + assign topBits__h907219 = INV_coreFix_aluExe_0_regToExeQfirst_BITS_157__ETC__q14[0] ? { coreFix_aluExe_0_regToExeQ$first[138:130], 3'd0 } : - b_top__h907319 ; - assign topBits__h995038 = - INV_commitStage_commitTrap_BITS_217_TO_199__q15[0] ? + b_top__h907317 ; + assign topBits__h995036 = + INV_commitStage_commitTrap_BITS_217_TO_199__q16[0] ? { commitStage_commitTrap[198:190], 3'd0 } : - b_top__h995135 ; - assign trap_val__h997040 = { 53'd0, x__h998861 } ; - assign upd__h1014188 = + b_top__h995133 ; + assign trap_val__h997075 = { 53'd0, x__h998896 } ; + assign upd__h1014223 = MUX_csrf_minstret_ehr_data_lat_0$wset_1__SEL_1 ? f_csr_reqs$D_OUT[63:0] : rob$deqPort_0_deq_data[95:32] ; @@ -37908,382 +37895,385 @@ module mkCore(CLK, MUX_csrf_mcycle_ehr_data_lat_0$wset_1__SEL_1 ? f_csr_reqs$D_OUT[63:0] : rob$deqPort_0_deq_data[95:32] ; - assign v__h1012261 = + assign v__h1012296 = { csrf_sepcc_reg_data_rl[152], csrf_sepcc_reg_data_rl[71:56], csrf_sepcc_reg_data_rl[54:53], csrf_sepcc_reg_data_rl[55], - CASE_csrf_sepcc_reg_data_rl_BITS_52_TO_35_2621_ETC__q276, + CASE_csrf_sepcc_reg_data_rl_BITS_52_TO_35_2621_ETC__q278, ~csrf_sepcc_reg_data_rl[34], - IF_csrf_sepcc_reg_read_wget__3506_BIT_34_3518__ETC___d23528[25:17], - ~IF_csrf_sepcc_reg_read_wget__3506_BIT_34_3518__ETC___d23528[16:15], - IF_csrf_sepcc_reg_read_wget__3506_BIT_34_3518__ETC___d23528[14:3], - ~IF_csrf_sepcc_reg_read_wget__3506_BIT_34_3518__ETC___d23528[2], - IF_csrf_sepcc_reg_read_wget__3506_BIT_34_3518__ETC___d23528[1:0], + IF_csrf_sepcc_reg_read_wget__3508_BIT_34_3520__ETC___d23530[25:17], + ~IF_csrf_sepcc_reg_read_wget__3508_BIT_34_3520__ETC___d23530[16:15], + IF_csrf_sepcc_reg_read_wget__3508_BIT_34_3520__ETC___d23530[14:3], + ~IF_csrf_sepcc_reg_read_wget__3508_BIT_34_3520__ETC___d23530[2], + IF_csrf_sepcc_reg_read_wget__3508_BIT_34_3520__ETC___d23530[1:0], csrf_sepcc_reg_data_rl[149:86] } ; - assign v__h1012970 = + assign v__h1013005 = { csrf_mepcc_reg_data_rl[152], csrf_mepcc_reg_data_rl[71:56], csrf_mepcc_reg_data_rl[54:53], csrf_mepcc_reg_data_rl[55], - CASE_csrf_mepcc_reg_data_rl_BITS_52_TO_35_2621_ETC__q277, + CASE_csrf_mepcc_reg_data_rl_BITS_52_TO_35_2621_ETC__q279, ~csrf_mepcc_reg_data_rl[34], - IF_csrf_mepcc_reg_read_wget__3540_BIT_34_3552__ETC___d23562[25:17], - ~IF_csrf_mepcc_reg_read_wget__3540_BIT_34_3552__ETC___d23562[16:15], - IF_csrf_mepcc_reg_read_wget__3540_BIT_34_3552__ETC___d23562[14:3], - ~IF_csrf_mepcc_reg_read_wget__3540_BIT_34_3552__ETC___d23562[2], - IF_csrf_mepcc_reg_read_wget__3540_BIT_34_3552__ETC___d23562[1:0], + IF_csrf_mepcc_reg_read_wget__3542_BIT_34_3554__ETC___d23564[25:17], + ~IF_csrf_mepcc_reg_read_wget__3542_BIT_34_3554__ETC___d23564[16:15], + IF_csrf_mepcc_reg_read_wget__3542_BIT_34_3554__ETC___d23564[14:3], + ~IF_csrf_mepcc_reg_read_wget__3542_BIT_34_3554__ETC___d23564[2], + IF_csrf_mepcc_reg_read_wget__3542_BIT_34_3554__ETC___d23564[1:0], csrf_mepcc_reg_data_rl[149:86] } ; - assign v__h514824 = + assign v__h514822 = IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d7227 ? - v__h515019 : + v__h515017 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ; - assign v__h515019 = + assign v__h515017 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd7) ? 3'd0 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP + 3'd1 ; - assign v__h516844 = + assign v__h516842 = IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d7321 ? - v__h517224 : + v__h517222 : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP ; - assign v__h517224 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP + 1'd1 ; - assign v__h532563 = + assign v__h517222 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP + 1'd1 ; + assign v__h532561 = IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d7480 ? - v__h532758 : + v__h532756 : coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP ; - assign v__h532758 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP + 1'd1 ; - assign v__h535012 = + assign v__h532756 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP + 1'd1 ; + assign v__h535010 = IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d7564 ? - v__h535207 : + v__h535205 : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP ; - assign v__h535207 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP + 1'd1 ; - assign v__h556032 = + assign v__h535205 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP + 1'd1 ; + assign v__h556030 = IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d7769 ? - v__h556227 : + v__h556225 : coreFix_memExe_memRespLdQ_enqP ; - assign v__h556227 = coreFix_memExe_memRespLdQ_enqP + 1'd1 ; - assign v__h559811 = + assign v__h556225 = coreFix_memExe_memRespLdQ_enqP + 1'd1 ; + assign v__h559809 = IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d7851 ? - v__h560006 : + v__h560004 : coreFix_memExe_forwardQ_enqP ; - assign v__h560006 = coreFix_memExe_forwardQ_enqP + 1'd1 ; - assign v__h836642 = + assign v__h560004 = coreFix_memExe_forwardQ_enqP + 1'd1 ; + assign v__h836639 = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_deqEn$whas ? - v__h836652 : + v__h836649 : coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit ; - assign v__h836652 = + assign v__h836649 = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit + 2'd1 ; - assign v__h837287 = v__h836642 - 2'd1 ; - assign value__h239694 = x__h239712 | in__h239804[63:0] ; - assign value__h239858 = - { coreFix_memExe_regToExeQ$first[381:332] & mask__h239865, + assign v__h837284 = v__h836639 - 2'd1 ; + assign value_BIT_52___h677325 = + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != + 11'd0 ; + assign value__h239691 = x__h239709 | in__h239801[63:0] ; + assign value__h239855 = + { coreFix_memExe_regToExeQ$first[381:332] & mask__h239862, 14'd0 } + - addBase__h239864 ; - assign value__h240851 = x__h240869 | in__h240961[63:0] ; - assign value__h241015 = - { coreFix_memExe_regToExeQ$first[218:169] & mask__h241022, + addBase__h239861 ; + assign value__h240848 = x__h240866 | in__h240958[63:0] ; + assign value__h241012 = + { coreFix_memExe_regToExeQ$first[218:169] & mask__h241019, 14'd0 } + - addBase__h241021 ; - assign value__h254475 = x__h254493 | in__h254585[63:0] ; - assign value__h254639 = - { coreFix_memExe_dTlb$procResp[450:401] & mask__h254646, + addBase__h241018 ; + assign value__h254472 = x__h254490 | in__h254582[63:0] ; + assign value__h254636 = + { coreFix_memExe_dTlb$procResp[450:401] & mask__h254643, 14'd0 } + - addBase__h254645 ; - assign value__h577076 = + addBase__h254642 ; + assign value__h577074 = { 1'b0, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != 11'd0, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] } ; - assign value__h622825 = + assign value__h622823 = { 1'b0, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != 11'd0, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] } ; - assign value__h668572 = + assign value__h668570 = { 1'b0, - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != - 11'd0, + value_BIT_52___h677325, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] } ; - assign value__h719844 = { 1'b0, f1_exp__h714899 != 8'd0, f1_sfd__h714900 } ; - assign value__h758697 = { 1'b0, f2_exp__h753893 != 8'd0, f2_sfd__h753894 } ; - assign value__h798001 = { 1'b0, f3_exp__h793197 != 8'd0, f3_sfd__h793198 } ; - assign vm_mode_reg__read__h854732 = { csrf_vm_mode_sv39_reg, 3'b0 } ; - assign w__h915805 = + assign value__h719841 = { 1'b0, f1_exp__h714896 != 8'd0, f1_sfd__h714897 } ; + assign value__h758694 = { 1'b0, f2_exp__h753890 != 8'd0, f2_sfd__h753891 } ; + assign value__h797998 = { 1'b0, f3_exp__h793194 != 8'd0, f3_sfd__h793195 } ; + assign vm_mode_reg__read__h854731 = { csrf_vm_mode_sv39_reg, 3'b0 } ; + assign w__h915803 = coreFix_globalSpecUpdate_correctSpecTag_0$whas ? - result__h915861 : + result__h915859 : 12'd4095 ; - assign wordIdx__h263233 = + assign wordIdx__h263231 = coreFix_memExe_dMem_cache_m_banks_0_processAmo[165:164] ; - assign x1_avValue_new_pcc_capFat_bounds_baseBits__h1000887 = - csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22647 ? + assign x1_avValue_new_pcc_capFat_bounds_baseBits__h1000922 = + csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22648 ? csrf_stcc_reg[13:0] : csrf_mtcc_reg[13:0] ; - assign x__h1000218 = csrf_mtcc_reg[33:28] + 6'd14 ; - assign x__h1000345 = address__h1000151 >> csrf_mtcc_reg[33:28] ; - assign x__h1000649 = address__h1000495 >> csrf_mtcc_reg[33:28] ; - assign x__h1000884 = - csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22647 ? + assign x__h1000027 = address__h999873 >> csrf_stcc_reg[33:28] ; + assign x__h1000253 = csrf_mtcc_reg[33:28] + 6'd14 ; + assign x__h1000380 = address__h1000186 >> csrf_mtcc_reg[33:28] ; + assign x__h1000684 = address__h1000530 >> csrf_mtcc_reg[33:28] ; + assign x__h1000919 = + csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22648 ? csrf_stcc_reg[27:14] : csrf_mtcc_reg[27:14] ; - assign x__h1000905 = - csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22647 ? + assign x__h1000940 = + csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22648 ? csrf_stcc_reg[33:28] : csrf_mtcc_reg[33:28] ; - assign x__h1008400 = - robdeqPort_0_deq_data_BITS_95_TO_32__q16[63:14] ^ - signBits__h1008370 ; - assign x__h1008496 = rob$deqPort_0_deq_data[95:32] >> csrf_stcc_reg[33:28] ; - assign x__h1008899 = + assign x__h1008435 = + robdeqPort_0_deq_data_BITS_95_TO_32__q17[63:14] ^ + signBits__h1008405 ; + assign x__h1008531 = rob$deqPort_0_deq_data[95:32] >> csrf_stcc_reg[33:28] ; + assign x__h1008934 = rob$deqPort_0_deq_data[95:32] >> IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16100 ; - assign x__h1009316 = rob$deqPort_0_deq_data[95:32] >> csrf_mtcc_reg[33:28] ; - assign x__h1009719 = + assign x__h1009351 = rob$deqPort_0_deq_data[95:32] >> csrf_mtcc_reg[33:28] ; + assign x__h1009754 = rob$deqPort_0_deq_data[95:32] >> IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16252 ; - assign x__h1010388 = rob$deqPort_0_deq_data[95:32] >> csrf_rg_dpc[33:28] ; - assign x__h1012282 = { 1'b0, csrf_spp_reg } ; - assign x__h1016564 = - NOT_rob_deqPort_0_canDeq__3598_3599_OR_rob_deq_ETC___d23818 ? - y_avValue_snd_snd_snd_fst__h1016386 : - IF_rob_deqPort_0_canDeq__3598_THEN_IF_NOT_rob__ETC___d23847 ; - assign x__h1031451 = f_csr_reqs$D_OUT[63:14] ^ signBits__h1031421 ; - assign x__h1031547 = f_csr_reqs$D_OUT[63:0] >> csrf_stcc_reg[33:28] ; - assign x__h1031950 = + assign x__h1010423 = rob$deqPort_0_deq_data[95:32] >> csrf_rg_dpc[33:28] ; + assign x__h1012317 = { 1'b0, csrf_spp_reg } ; + assign x__h1016599 = + NOT_rob_deqPort_0_canDeq__3600_3601_OR_rob_deq_ETC___d23820 ? + y_avValue_snd_snd_snd_fst__h1016421 : + IF_rob_deqPort_0_canDeq__3600_THEN_IF_NOT_rob__ETC___d23849 ; + assign x__h1031485 = f_csr_reqs$D_OUT[63:14] ^ signBits__h1031455 ; + assign x__h1031581 = f_csr_reqs$D_OUT[63:0] >> csrf_stcc_reg[33:28] ; + assign x__h1031984 = f_csr_reqs$D_OUT[63:0] >> IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16100 ; - assign x__h1032367 = f_csr_reqs$D_OUT[63:0] >> csrf_mtcc_reg[33:28] ; - assign x__h1032770 = + assign x__h1032401 = f_csr_reqs$D_OUT[63:0] >> csrf_mtcc_reg[33:28] ; + assign x__h1032804 = f_csr_reqs$D_OUT[63:0] >> IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16252 ; - assign x__h1033437 = f_csr_reqs$D_OUT[63:0] >> csrf_rg_dpc[33:28] ; - assign x__h127303 = coreFix_memExe_respLrScAmoQ_data_0[63:0] >> x__h127341 ; - assign x__h127341 = { tmp_expTopHalf__h127294, tmp_expBotHalf__h127296 } ; - assign x__h127501 = { impliedTopBits__h127434, topBits__h127430 } ; - assign x__h127518 = x__h127521[13:12] + carry_out__h127432 ; - assign x__h127521 = + assign x__h1033471 = f_csr_reqs$D_OUT[63:0] >> csrf_rg_dpc[33:28] ; + assign x__h127302 = coreFix_memExe_respLrScAmoQ_data_0[63:0] >> x__h127340 ; + assign x__h127340 = { tmp_expTopHalf__h127293, tmp_expBotHalf__h127295 } ; + assign x__h127500 = { impliedTopBits__h127433, topBits__h127429 } ; + assign x__h127517 = x__h127520[13:12] + carry_out__h127431 ; + assign x__h127520 = INV_coreFix_memExe_respLrScAmoQ_data_0_BITS_10_ETC__q8[0] ? { coreFix_memExe_respLrScAmoQ_data_0[77:67], 3'd0 } : - b_base__h127528 ; - assign x__h140219 = mmio_dataRespQ_data_0[63:0] >> x__h140257 ; - assign x__h140257 = { tmp_expTopHalf__h140210, tmp_expBotHalf__h140212 } ; - assign x__h140417 = { impliedTopBits__h140350, topBits__h140346 } ; - assign x__h140434 = x__h140437[13:12] + carry_out__h140348 ; - assign x__h140437 = + b_base__h127527 ; + assign x__h140218 = mmio_dataRespQ_data_0[63:0] >> x__h140256 ; + assign x__h140256 = { tmp_expTopHalf__h140209, tmp_expBotHalf__h140211 } ; + assign x__h140416 = { impliedTopBits__h140349, topBits__h140345 } ; + assign x__h140433 = x__h140436[13:12] + carry_out__h140347 ; + assign x__h140436 = INV_mmio_dataRespQ_data_0_BITS_108_TO_90__q9[0] ? { mmio_dataRespQ_data_0[77:67], 3'd0 } : - b_base__h140444 ; - assign x__h148991 = + b_base__h140443 ; + assign x__h148990 = coreFix_memExe_reqLdQ_data_0_lat_0$whas ? coreFix_memExe_reqLdQ_data_0_lat_0$wget[68:64] : coreFix_memExe_reqLdQ_data_0_rl[68:64] ; - assign x__h152125 = { 3'd0, sbIdx__h152016 } ; - assign x__h183399 = + assign x__h152124 = { 3'd0, sbIdx__h152015 } ; + assign x__h183397 = (coreFix_memExe_lsq$firstLd[125:110] == 16'd65535) ? coreFix_memExe_respLrScAmoQ_data_0[127:0] : { 64'd0, IF_coreFix_memExe_lsq_firstLd__498_BIT_117_521_ETC___d1913 } ; - assign x__h183481 = x__h183399[63:0] >> x__h183519 ; - assign x__h183519 = { tmp_expTopHalf__h183472, tmp_expBotHalf__h183474 } ; - assign x__h183679 = { impliedTopBits__h183612, topBits__h183608 } ; - assign x__h183696 = x__h183699[13:12] + carry_out__h183610 ; - assign x__h183699 = - INV_x83399_BITS_108_TO_90__q34[0] ? - { x__h183399[77:67], 3'd0 } : - b_base__h183706 ; - assign x__h199251 = + assign x__h183479 = x__h183397[63:0] >> x__h183517 ; + assign x__h183517 = { tmp_expTopHalf__h183470, tmp_expBotHalf__h183472 } ; + assign x__h183677 = { impliedTopBits__h183610, topBits__h183606 } ; + assign x__h183694 = x__h183697[13:12] + carry_out__h183608 ; + assign x__h183697 = + INV_x83397_BITS_108_TO_90__q34[0] ? + { x__h183397[77:67], 3'd0 } : + b_base__h183704 ; + assign x__h199249 = (coreFix_memExe_lsq$firstLd[125:110] == 16'd65535) ? mmio_dataRespQ_data_0[127:0] : { 64'd0, IF_coreFix_memExe_lsq_firstLd__498_BIT_117_521_ETC___d2079 } ; - assign x__h202232 = x__h199251[63:0] >> x__h202270 ; - assign x__h202270 = { tmp_expTopHalf__h202223, tmp_expBotHalf__h202225 } ; - assign x__h202430 = { impliedTopBits__h202363, topBits__h202359 } ; - assign x__h202447 = x__h202450[13:12] + carry_out__h202361 ; - assign x__h202450 = - INV_x99251_BITS_108_TO_90__q36[0] ? - { x__h199251[77:67], 3'd0 } : - b_base__h202457 ; - assign x__h216798 = coreFix_memExe_lsq$respLd[63:0] >> x__h216836 ; - assign x__h216836 = { tmp_expTopHalf__h216789, tmp_expBotHalf__h216791 } ; - assign x__h216996 = { impliedTopBits__h216929, topBits__h216925 } ; - assign x__h217013 = x__h217016[13:12] + carry_out__h216927 ; - assign x__h217016 = + assign x__h202230 = x__h199249[63:0] >> x__h202268 ; + assign x__h202268 = { tmp_expTopHalf__h202221, tmp_expBotHalf__h202223 } ; + assign x__h202428 = { impliedTopBits__h202361, topBits__h202357 } ; + assign x__h202445 = x__h202448[13:12] + carry_out__h202359 ; + assign x__h202448 = + INV_x99249_BITS_108_TO_90__q36[0] ? + { x__h199249[77:67], 3'd0 } : + b_base__h202455 ; + assign x__h216796 = coreFix_memExe_lsq$respLd[63:0] >> x__h216834 ; + assign x__h216834 = { tmp_expTopHalf__h216787, tmp_expBotHalf__h216789 } ; + assign x__h216994 = { impliedTopBits__h216927, topBits__h216923 } ; + assign x__h217011 = x__h217014[13:12] + carry_out__h216925 ; + assign x__h217014 = INV_coreFix_memExe_lsqrespLd_BITS_108_TO_90__q10[0] ? { coreFix_memExe_lsq$respLd[77:67], 3'd0 } : - b_base__h217023 ; - assign x__h235746 = + b_base__h217021 ; + assign x__h235743 = (coreFix_memExe_dispToRegQ$first[110] && coreFix_memExe_dispToRegQ$first[109:103] != 7'd0) ? IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3048 : 66'd0 ; - assign x__h239712 = x__h239714 << coreFix_memExe_regToExeQ$first[265:260] ; - assign x__h239714 = { {48{offset__h239700[15]}}, offset__h239700 } ; - assign x__h239822 = + assign x__h239709 = x__h239711 << coreFix_memExe_regToExeQ$first[265:260] ; + assign x__h239711 = { {48{offset__h239697[15]}}, offset__h239697 } ; + assign x__h239819 = 66'h3FFFFFFFFFFFFFFFF << coreFix_memExe_regToExeQ$first[265:260] ; - assign x__h239970 = + assign x__h239967 = coreFix_memExe_regToExeQ_first__645_BITS_265_T_ETC___d3717 ? - result__h240600 : - ret__h239977 ; - assign x__h240072 = + result__h240597 : + ret__h239974 ; + assign x__h240069 = { coreFix_memExe_regToExeQ$first[225:224], coreFix_memExe_regToExeQ$first[259:246] } ; - assign x__h240141 = + assign x__h240138 = (coreFix_memExe_regToExeQ$first[265:260] == 6'd50) ? coreFix_memExe_regToExeQ$first[245] : coreFix_memExe_regToExeQfirst_BITS_381_TO_332_ETC__q3[49] ; - assign x__h240869 = x__h240871 << coreFix_memExe_regToExeQ$first[102:97] ; - assign x__h240871 = { {48{offset__h240857[15]}}, offset__h240857 } ; - assign x__h240979 = + assign x__h240866 = x__h240868 << coreFix_memExe_regToExeQ$first[102:97] ; + assign x__h240868 = { {48{offset__h240854[15]}}, offset__h240854 } ; + assign x__h240976 = 66'h3FFFFFFFFFFFFFFFF << coreFix_memExe_regToExeQ$first[102:97] ; - assign x__h241127 = + assign x__h241124 = coreFix_memExe_regToExeQ_first__645_BITS_102_T_ETC___d3779 ? - result__h241757 : - ret__h241134 ; - assign x__h241229 = + result__h241754 : + ret__h241131 ; + assign x__h241226 = { coreFix_memExe_regToExeQ$first[62:61], coreFix_memExe_regToExeQ$first[96:83] } ; - assign x__h241298 = + assign x__h241295 = (coreFix_memExe_regToExeQ$first[102:97] == 6'd50) ? coreFix_memExe_regToExeQ$first[82] : coreFix_memExe_regToExeQfirst_BITS_218_TO_169_ETC__q5[49] ; - assign x__h242674 = offset__h242628[63:14] ^ signBits__h242644 ; - assign x__h242777 = - offset__h242628 >> coreFix_memExe_regToExeQ$first[265:260] ; - assign x__h244678 = { pointer__h242638[3:0], 3'b0 } ; - assign x__h248120 = - pointer__h242638 >> coreFix_memExe_regToExeQ$first[265:260] ; - assign x__h249478 = x__h249490 + y__h249491 ; - assign x__h249490 = x__h249502 + y__h249503 ; - assign x__h249502 = x__h249514 + y__h249515 ; - assign x__h249514 = x__h249526 + y__h249527 ; - assign x__h249526 = x__h249538 + y__h249539 ; - assign x__h249538 = x__h249550 + y__h249551 ; - assign x__h249550 = x__h249562 + y__h249563 ; - assign x__h249562 = x__h249574 + y__h249575 ; - assign x__h249574 = x__h249586 + y__h249587 ; - assign x__h249586 = x__h249598 + y__h249599 ; - assign x__h249598 = x__h249610 + y__h249611 ; - assign x__h249610 = x__h249622 + y__h249623 ; - assign x__h249622 = x__h249634 + y__h249635 ; - assign x__h249634 = x__h249646 + y__h249647 ; - assign x__h249646 = { 4'd0, coreFix_memExe_lsq$getOrigBE[15] } ; - assign x__h254493 = x__h254495 << coreFix_memExe_dTlb$procResp[334:329] ; - assign x__h254495 = { {48{offset__h254481[15]}}, offset__h254481 } ; - assign x__h254603 = + assign x__h242671 = offset__h242625[63:14] ^ signBits__h242641 ; + assign x__h242774 = + offset__h242625 >> coreFix_memExe_regToExeQ$first[265:260] ; + assign x__h244675 = { pointer__h242635[3:0], 3'b0 } ; + assign x__h248117 = + pointer__h242635 >> coreFix_memExe_regToExeQ$first[265:260] ; + assign x__h249475 = x__h249487 + y__h249488 ; + assign x__h249487 = x__h249499 + y__h249500 ; + assign x__h249499 = x__h249511 + y__h249512 ; + assign x__h249511 = x__h249523 + y__h249524 ; + assign x__h249523 = x__h249535 + y__h249536 ; + assign x__h249535 = x__h249547 + y__h249548 ; + assign x__h249547 = x__h249559 + y__h249560 ; + assign x__h249559 = x__h249571 + y__h249572 ; + assign x__h249571 = x__h249583 + y__h249584 ; + assign x__h249583 = x__h249595 + y__h249596 ; + assign x__h249595 = x__h249607 + y__h249608 ; + assign x__h249607 = x__h249619 + y__h249620 ; + assign x__h249619 = x__h249631 + y__h249632 ; + assign x__h249631 = x__h249643 + y__h249644 ; + assign x__h249643 = { 4'd0, coreFix_memExe_lsq$getOrigBE[15] } ; + assign x__h254490 = x__h254492 << coreFix_memExe_dTlb$procResp[334:329] ; + assign x__h254492 = { {48{offset__h254478[15]}}, offset__h254478 } ; + assign x__h254600 = 66'h3FFFFFFFFFFFFFFFF << coreFix_memExe_dTlb$procResp[334:329] ; - assign x__h254751 = + assign x__h254748 = coreFix_memExe_dTlb_procResp__257_BITS_334_TO__ETC___d4420 ? - result__h255381 : - ret__h254758 ; - assign x__h254853 = + result__h255378 : + ret__h254755 ; + assign x__h254850 = { coreFix_memExe_dTlb$procResp[294:293], coreFix_memExe_dTlb$procResp[328:315] } ; - assign x__h254922 = + assign x__h254919 = (coreFix_memExe_dTlb$procResp[334:329] == 6'd50) ? coreFix_memExe_dTlb$procResp[314] : coreFix_memExe_dTlbprocResp_BITS_450_TO_401_P_ETC__q7[49] ; - assign x__h521675 = + assign x__h521673 = EN_dCacheToParent_fromP_enq ? coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[2:0] : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[2:0] ; - assign x__h568253 = - { (_theResult___exp__h611585 != 8'd255 || - _theResult___sfd__h611586 == 23'd0) && + assign x__h568251 = + { (_theResult___exp__h611583 != 8'd255 || + _theResult___sfd__h611584 == 23'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9263, - out_f_exp__h611862, - out_f_sfd__h611863 } ; - assign x__h594803 = - sfd__h568849 << (x__h594836[11] ? 12'hAAA : x__h594836) ; - assign x__h594836 = + out_f_exp__h611860, + out_f_sfd__h611861 } ; + assign x__h594801 = + sfd__h568847 << (x__h594834[11] ? 12'hAAA : x__h594834) ; + assign x__h594834 = 12'd57 - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d8677 ; - assign x__h614007 = - { (_theResult___exp__h657334 != 8'd255 || - _theResult___sfd__h657335 == 23'd0) && + assign x__h614005 = + { (_theResult___exp__h657332 != 8'd255 || + _theResult___sfd__h657333 == 23'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10660, - out_f_exp__h657611, - out_f_sfd__h657612 } ; - assign x__h640552 = - sfd__h614603 << (x__h640585[11] ? 12'hAAA : x__h640585) ; - assign x__h640585 = + out_f_exp__h657609, + out_f_sfd__h657610 } ; + assign x__h640550 = + sfd__h614601 << (x__h640583[11] ? 12'hAAA : x__h640583) ; + assign x__h640583 = 12'd57 - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d10074 ; assign x__h65639 = mmio_pRqQ_data_0[31:0] ; - assign x__h659754 = - { (_theResult___exp__h703081 != 8'd255 || - _theResult___sfd__h703082 == 23'd0) && + assign x__h659752 = + { (_theResult___exp__h703079 != 8'd255 || + _theResult___sfd__h703080 == 23'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12057, - out_f_exp__h703358, - out_f_sfd__h703359 } ; - assign x__h686299 = - sfd__h660350 << (x__h686332[11] ? 12'hAAA : x__h686332) ; - assign x__h686332 = + out_f_exp__h703356, + out_f_sfd__h703357 } ; + assign x__h686297 = + sfd__h660348 << (x__h686330[11] ? 12'hAAA : x__h686330) ; + assign x__h686330 = 12'd57 - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d11471 ; - assign x__h714429 = + assign x__h714426 = sbCons$lazyLookup_2_get[3] ? rf$read_2_rd1[149:86] : - y_avValue__h710475 ; - assign x__h714430 = + y_avValue__h710472 ; + assign x__h714427 = sbCons$lazyLookup_2_get[2] ? rf$read_2_rd2[149:86] : - y_avValue__h711108 ; - assign x__h714431 = + y_avValue__h711105 ; + assign x__h714428 = sbCons$lazyLookup_2_get[1] ? rf$read_2_rd3[149:86] : - y_avValue__h711735 ; - assign x__h736336 = sfd__h715261 << x__h736369 ; - assign x__h736369 = + y_avValue__h711732 ; + assign x__h736333 = sfd__h715258 << x__h736366 ; + assign x__h736366 = 12'd57 - _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d12800 ; - assign x__h775189 = sfd__h754255 << x__h775222 ; - assign x__h775222 = + assign x__h775186 = sfd__h754252 << x__h775219 ; + assign x__h775219 = 12'd57 - _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d14285 ; - assign x__h814493 = sfd__h793559 << x__h814526 ; - assign x__h814526 = + assign x__h814490 = sfd__h793556 << x__h814523 ; + assign x__h814523 = 12'd57 - _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d13515 ; - assign x__h836143 = a__h835707[63] ^ b__h835708[63] ; - assign x__h853092 = { csrf_frm_reg, csrf_fflags_reg } ; - assign x__h854172 = 66'h3FFFFFFFFFFFFFFFF << csrf_stcc_reg[33:28] ; - assign x__h854233 = - x__h854235 << + assign x__h836140 = a__h835704[63] ^ b__h835705[63] ; + assign x__h853091 = { csrf_frm_reg, csrf_fflags_reg } ; + assign x__h854171 = 66'h3FFFFFFFFFFFFFFFF << csrf_stcc_reg[33:28] ; + assign x__h854232 = + x__h854234 << IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16100 ; - assign x__h854235 = { {48{offset__h854221[15]}}, offset__h854221 } ; - assign x__h854477 = + assign x__h854234 = { {48{offset__h854220[15]}}, offset__h854220 } ; + assign x__h854476 = 66'h3FFFFFFFFFFFFFFFF << IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16100 ; - assign x__h855165 = 66'h3FFFFFFFFFFFFFFFF << csrf_mtcc_reg[33:28] ; - assign x__h855226 = - x__h855228 << + assign x__h855164 = 66'h3FFFFFFFFFFFFFFFF << csrf_mtcc_reg[33:28] ; + assign x__h855225 = + x__h855227 << IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16252 ; - assign x__h855228 = { {48{offset__h855214[15]}}, offset__h855214 } ; - assign x__h855469 = + assign x__h855227 = { {48{offset__h855213[15]}}, offset__h855213 } ; + assign x__h855468 = 66'h3FFFFFFFFFFFFFFFF << IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16252 ; - assign x__h855995 = 66'h3FFFFFFFFFFFFFFFF << csrf_rg_dpc[33:28] ; - assign x__h866848 = - coreFix_aluExe_1_regToExeQ$first[241:178] >> x__h866886 ; - assign x__h866886 = { tmp_expTopHalf__h866838, tmp_expBotHalf__h866840 } ; - assign x__h867059 = { impliedTopBits__h866991, topBits__h866987 } ; - assign x__h867076 = x__h867079[13:12] + carry_out__h866989 ; - assign x__h867079 = + assign x__h855994 = 66'h3FFFFFFFFFFFFFFFF << csrf_rg_dpc[33:28] ; + assign x__h866847 = + coreFix_aluExe_1_regToExeQ$first[241:178] >> x__h866885 ; + assign x__h866885 = { tmp_expTopHalf__h866837, tmp_expBotHalf__h866839 } ; + assign x__h867058 = { impliedTopBits__h866990, topBits__h866986 } ; + assign x__h867075 = x__h867078[13:12] + carry_out__h866988 ; + assign x__h867078 = INV_coreFix_aluExe_1_regToExeQfirst_BITS_286__ETC__q11[0] ? { coreFix_aluExe_1_regToExeQ$first[255:245], 3'd0 } : - b_base__h867086 ; - assign x__h867396 = coreFix_aluExe_1_regToExeQ$first[112:49] >> x__h867434 ; - assign x__h867434 = { tmp_expTopHalf__h867386, tmp_expBotHalf__h867388 } ; - assign x__h867607 = { impliedTopBits__h867539, topBits__h867535 } ; - assign x__h867624 = x__h867627[13:12] + carry_out__h867537 ; - assign x__h867627 = + b_base__h867085 ; + assign x__h867395 = coreFix_aluExe_1_regToExeQ$first[112:49] >> x__h867433 ; + assign x__h867433 = { tmp_expTopHalf__h867385, tmp_expBotHalf__h867387 } ; + assign x__h867606 = { impliedTopBits__h867538, topBits__h867534 } ; + assign x__h867623 = x__h867626[13:12] + carry_out__h867536 ; + assign x__h867626 = INV_coreFix_aluExe_1_regToExeQfirst_BITS_157__ETC__q12[0] ? { coreFix_aluExe_1_regToExeQ$first[126:116], 3'd0 } : - b_base__h867634 ; - assign x__h879903 = + b_base__h867633 ; + assign x__h879902 = { coreFix_aluExe_1_exeToFinQ$first[623], coreFix_aluExe_1_exeToFinQ$first[542:527], coreFix_aluExe_1_exeToFinQ$first[525:524], @@ -38295,34 +38285,34 @@ module mkCore(CLK, ~IF_coreFix_aluExe_1_exeToFinQ_first__7830_BIT__ETC___d18027[2], IF_coreFix_aluExe_1_exeToFinQ_first__7830_BIT__ETC___d18027[1:0], coreFix_aluExe_1_exeToFinQ$first[620:557] } ; - assign x__h895988 = x__h895990 << csrf_stcc_reg[33:28] ; - assign x__h895990 = { {48{offset__h895976[15]}}, offset__h895976 } ; - assign x__h896272 = x__h896274 << csrf_mtcc_reg[33:28] ; - assign x__h896274 = { {48{offset__h896260[15]}}, offset__h896260 } ; - assign x__h896542 = + assign x__h895986 = x__h895988 << csrf_stcc_reg[33:28] ; + assign x__h895988 = { {48{offset__h895974[15]}}, offset__h895974 } ; + assign x__h896270 = x__h896272 << csrf_mtcc_reg[33:28] ; + assign x__h896272 = { {48{offset__h896258[15]}}, offset__h896258 } ; + assign x__h896540 = { csrf_mccsr_reg[10:5], CASE_csrf_mccsr_reg_BITS_4_TO_0_0_csrf_mccsr_r_ETC__q24, 5'd3 } ; - assign x__h896617 = x__h896619 << csrf_rg_dpc[33:28] ; - assign x__h896619 = { {48{offset__h896605[15]}}, offset__h896605 } ; - assign x__h906534 = - coreFix_aluExe_0_regToExeQ$first[241:178] >> x__h906572 ; - assign x__h906572 = { tmp_expTopHalf__h906524, tmp_expBotHalf__h906526 } ; - assign x__h906745 = { impliedTopBits__h906677, topBits__h906673 } ; - assign x__h906762 = x__h906765[13:12] + carry_out__h906675 ; - assign x__h906765 = + assign x__h896615 = x__h896617 << csrf_rg_dpc[33:28] ; + assign x__h896617 = { {48{offset__h896603[15]}}, offset__h896603 } ; + assign x__h906532 = + coreFix_aluExe_0_regToExeQ$first[241:178] >> x__h906570 ; + assign x__h906570 = { tmp_expTopHalf__h906522, tmp_expBotHalf__h906524 } ; + assign x__h906743 = { impliedTopBits__h906675, topBits__h906671 } ; + assign x__h906760 = x__h906763[13:12] + carry_out__h906673 ; + assign x__h906763 = INV_coreFix_aluExe_0_regToExeQfirst_BITS_286__ETC__q13[0] ? { coreFix_aluExe_0_regToExeQ$first[255:245], 3'd0 } : - b_base__h906772 ; - assign x__h907082 = coreFix_aluExe_0_regToExeQ$first[112:49] >> x__h907120 ; - assign x__h907120 = { tmp_expTopHalf__h907072, tmp_expBotHalf__h907074 } ; - assign x__h907293 = { impliedTopBits__h907225, topBits__h907221 } ; - assign x__h907310 = x__h907313[13:12] + carry_out__h907223 ; - assign x__h907313 = + b_base__h906770 ; + assign x__h907080 = coreFix_aluExe_0_regToExeQ$first[112:49] >> x__h907118 ; + assign x__h907118 = { tmp_expTopHalf__h907070, tmp_expBotHalf__h907072 } ; + assign x__h907291 = { impliedTopBits__h907223, topBits__h907219 } ; + assign x__h907308 = x__h907311[13:12] + carry_out__h907221 ; + assign x__h907311 = INV_coreFix_aluExe_0_regToExeQfirst_BITS_157__ETC__q14[0] ? { coreFix_aluExe_0_regToExeQ$first[126:116], 3'd0 } : - b_base__h907320 ; - assign x__h914620 = + b_base__h907318 ; + assign x__h914618 = { coreFix_aluExe_0_exeToFinQ$first[623], coreFix_aluExe_0_exeToFinQ$first[542:527], coreFix_aluExe_0_exeToFinQ$first[525:524], @@ -38334,30 +38324,29 @@ module mkCore(CLK, ~IF_coreFix_aluExe_0_exeToFinQ_first__9946_BIT__ETC___d20142[2], IF_coreFix_aluExe_0_exeToFinQ_first__9946_BIT__ETC___d20142[1:0], coreFix_aluExe_0_exeToFinQ$first[620:557] } ; - assign x__h915809 = 12'd1 << coreFix_aluExe_1_exeToFinQ$first[15:12] ; - assign x__h915860 = 12'd1 << coreFix_aluExe_0_exeToFinQ$first[15:12] ; - assign x__h994911 = commitStage_commitTrap[172:109] >> x__h994949 ; - assign x__h994949 = { tmp_expTopHalf__h994902, tmp_expBotHalf__h994904 } ; - assign x__h995109 = { impliedTopBits__h995042, topBits__h995038 } ; - assign x__h995126 = x__h995129[13:12] + carry_out__h995040 ; - assign x__h995129 = - INV_commitStage_commitTrap_BITS_217_TO_199__q15[0] ? + assign x__h915807 = 12'd1 << coreFix_aluExe_1_exeToFinQ$first[15:12] ; + assign x__h915858 = 12'd1 << coreFix_aluExe_0_exeToFinQ$first[15:12] ; + assign x__h994909 = commitStage_commitTrap[172:109] >> x__h994947 ; + assign x__h994947 = { tmp_expTopHalf__h994900, tmp_expBotHalf__h994902 } ; + assign x__h995107 = { impliedTopBits__h995040, topBits__h995036 } ; + assign x__h995124 = x__h995127[13:12] + carry_out__h995038 ; + assign x__h995127 = + INV_commitStage_commitTrap_BITS_217_TO_199__q16[0] ? { commitStage_commitTrap[186:176], 3'd0 } : - b_base__h995136 ; - assign x__h997587 = - x__h997589 << + b_base__h995134 ; + assign x__h997622 = + x__h997624 << IF_INV_commitStage_commitTrap_2268_BITS_217_TO_ETC___d22580 ; - assign x__h997589 = { {48{offset__h997575[15]}}, offset__h997575 } ; - assign x__h997674 = + assign x__h997624 = { {48{offset__h997610[15]}}, offset__h997610 } ; + assign x__h997709 = 66'h3FFFFFFFFFFFFFFFF << IF_INV_commitStage_commitTrap_2268_BITS_217_TO_ETC___d22580 ; - assign x__h998861 = + assign x__h998896 = { commitStage_commitTrap[42:37], CASE_commitStage_commitTrap_BITS_36_TO_32_0_co_ETC__q25 } ; - assign x__h999561 = csrf_stcc_reg[33:28] + 6'd14 ; - assign x__h999587 = { cause_code__h995320, 2'b0 } ; - assign x__h999688 = address__h999494 >> csrf_stcc_reg[33:28] ; - assign x__h999992 = address__h999838 >> csrf_stcc_reg[33:28] ; + assign x__h999596 = csrf_stcc_reg[33:28] + 6'd14 ; + assign x__h999622 = { cause_code__h995318, 2'b0 } ; + assign x__h999723 = address__h999529 >> csrf_stcc_reg[33:28] ; assign x_addr__h19883 = mmio_dataReqQ_enqReq_lat_0$whas ? mmio_dataReqQ_enqReq_lat_0$wget[214:151] : @@ -38366,7 +38355,7 @@ module mkCore(CLK, mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[214:151] : mmio_cRqQ_enqReq_rl[214:151] ; - assign x_addr__h535374 = + assign x_addr__h535372 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[582:519] : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[582:519] ; @@ -38374,55 +38363,55 @@ module mkCore(CLK, EN_mmioToPlatform_pRq_enq ? mmio_pRqQ_enqReq_lat_0$wget[31:0] : mmio_pRqQ_enqReq_rl[31:0] ; - assign x_decodeInfo_frm__h926248 = csrf_frm_reg ; - assign x_quotient__h705747 = + assign x_decodeInfo_frm__h926246 = csrf_frm_reg ; + assign x_quotient__h705745 = coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[75] ? 64'hFFFFFFFFFFFFFFFF : ((coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[10] && coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[9]) ? - q___1__h706458 : + q___1__h706456 : coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[127:64]) ; - assign x_reg_ifc__read__h849324 = { 63'd0, csrf_stats_module_doStats } ; - assign x_remainder__h705748 = + assign x_reg_ifc__read__h849323 = { 63'd0, csrf_stats_module_doStats } ; + assign x_remainder__h705746 = coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[75] ? coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[74:11] : ((coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[10] && coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[8]) ? - r___1__h706484 : + r___1__h706482 : coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[63:0]) ; - assign y__h1000274 = { mask__h1000157[62:0], 1'd0 } ; - assign y__h1016339 = - NOT_rob_deqPort_0_canDeq__3598_3599_OR_rob_deq_ETC___d23818 ? - y_avValue_snd_snd_snd_snd_snd__h1016392 : - IF_rob_deqPort_0_canDeq__3598_THEN_IF_NOT_rob__ETC___d23719 ; - assign y__h239821 = ~x__h239822 ; - assign y__h240978 = ~x__h240979 ; - assign y__h249479 = { 4'd0, coreFix_memExe_lsq$getOrigBE[0] } ; - assign y__h249491 = { 4'd0, coreFix_memExe_lsq$getOrigBE[1] } ; - assign y__h249503 = { 4'd0, coreFix_memExe_lsq$getOrigBE[2] } ; - assign y__h249515 = { 4'd0, coreFix_memExe_lsq$getOrigBE[3] } ; - assign y__h249527 = { 4'd0, coreFix_memExe_lsq$getOrigBE[4] } ; - assign y__h249539 = { 4'd0, coreFix_memExe_lsq$getOrigBE[5] } ; - assign y__h249551 = { 4'd0, coreFix_memExe_lsq$getOrigBE[6] } ; - assign y__h249563 = { 4'd0, coreFix_memExe_lsq$getOrigBE[7] } ; - assign y__h249575 = { 4'd0, coreFix_memExe_lsq$getOrigBE[8] } ; - assign y__h249587 = { 4'd0, coreFix_memExe_lsq$getOrigBE[9] } ; - assign y__h249599 = { 4'd0, coreFix_memExe_lsq$getOrigBE[10] } ; - assign y__h249611 = { 4'd0, coreFix_memExe_lsq$getOrigBE[11] } ; - assign y__h249623 = { 4'd0, coreFix_memExe_lsq$getOrigBE[12] } ; - assign y__h249635 = { 4'd0, coreFix_memExe_lsq$getOrigBE[13] } ; - assign y__h249647 = { 4'd0, coreFix_memExe_lsq$getOrigBE[14] } ; - assign y__h254602 = ~x__h254603 ; - assign y__h422565 = + assign y__h1000309 = { mask__h1000192[62:0], 1'd0 } ; + assign y__h1016374 = + NOT_rob_deqPort_0_canDeq__3600_3601_OR_rob_deq_ETC___d23820 ? + y_avValue_snd_snd_snd_snd_snd__h1016427 : + IF_rob_deqPort_0_canDeq__3600_THEN_IF_NOT_rob__ETC___d23721 ; + assign y__h239818 = ~x__h239819 ; + assign y__h240975 = ~x__h240976 ; + assign y__h249476 = { 4'd0, coreFix_memExe_lsq$getOrigBE[0] } ; + assign y__h249488 = { 4'd0, coreFix_memExe_lsq$getOrigBE[1] } ; + assign y__h249500 = { 4'd0, coreFix_memExe_lsq$getOrigBE[2] } ; + assign y__h249512 = { 4'd0, coreFix_memExe_lsq$getOrigBE[3] } ; + assign y__h249524 = { 4'd0, coreFix_memExe_lsq$getOrigBE[4] } ; + assign y__h249536 = { 4'd0, coreFix_memExe_lsq$getOrigBE[5] } ; + assign y__h249548 = { 4'd0, coreFix_memExe_lsq$getOrigBE[6] } ; + assign y__h249560 = { 4'd0, coreFix_memExe_lsq$getOrigBE[7] } ; + assign y__h249572 = { 4'd0, coreFix_memExe_lsq$getOrigBE[8] } ; + assign y__h249584 = { 4'd0, coreFix_memExe_lsq$getOrigBE[9] } ; + assign y__h249596 = { 4'd0, coreFix_memExe_lsq$getOrigBE[10] } ; + assign y__h249608 = { 4'd0, coreFix_memExe_lsq$getOrigBE[11] } ; + assign y__h249620 = { 4'd0, coreFix_memExe_lsq$getOrigBE[12] } ; + assign y__h249632 = { 4'd0, coreFix_memExe_lsq$getOrigBE[13] } ; + assign y__h249644 = { 4'd0, coreFix_memExe_lsq$getOrigBE[14] } ; + assign y__h254599 = ~x__h254600 ; + assign y__h422564 = { coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[574:522], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[168:164] } ; - assign y__h854171 = ~x__h854172 ; - assign y__h854476 = ~x__h854477 ; - assign y__h855164 = ~x__h855165 ; - assign y__h855468 = ~x__h855469 ; - assign y__h855994 = ~x__h855995 ; - assign y__h915839 = ~x__h915809 ; - assign y__h920769 = + assign y__h854170 = ~x__h854171 ; + assign y__h854475 = ~x__h854476 ; + assign y__h855163 = ~x__h855164 ; + assign y__h855467 = ~x__h855468 ; + assign y__h855993 = ~x__h855994 ; + assign y__h915837 = ~x__h915807 ; + assign y__h920767 = { 4'd15, ~csrf_mideleg_11_reg, 1'd1, @@ -38431,22 +38420,22 @@ module mkCore(CLK, ~csrf_mideleg_5_3_reg, 1'd1, ~csrf_mideleg_1_0_reg } ; - assign y__h973805 = 12'd1 << specTagManager$nextSpecTag ; - assign y__h997673 = ~x__h997674 ; - assign y__h999617 = { mask__h999500[62:0], 1'd0 } ; - assign y_avValue__h710475 = + assign y__h973803 = 12'd1 << specTagManager$nextSpecTag ; + assign y__h997708 = ~x__h997709 ; + assign y__h999652 = { mask__h999535[62:0], 1'd0 } ; + assign y_avValue__h710472 = NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d12381 ? coreFix_fpuMulDivExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12486 ; - assign y_avValue__h711108 = + assign y_avValue__h711105 = NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d12408 ? coreFix_fpuMulDivExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12498 ; - assign y_avValue__h711735 = + assign y_avValue__h711732 = NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d12432 ? coreFix_fpuMulDivExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12510 ; - assign y_avValue_snd_fst__h1015794 = + assign y_avValue_snd_fst__h1015829 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[274] || rob$deqPort_0_deq_data[469:465] == 5'd0 || @@ -38461,7 +38450,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[469:465] == 5'd25) ? 5'd0 : rob$deqPort_0_deq_data[31:27] ; - assign y_avValue_snd_fst__h1016376 = + assign y_avValue_snd_fst__h1016411 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[274] || rob$deqPort_1_deq_data[469:465] == 5'd0 || @@ -38474,26 +38463,26 @@ module mkCore(CLK, rob$deqPort_1_deq_data[469:465] == 5'd20 || rob$deqPort_1_deq_data[469:465] == 5'd24 || rob$deqPort_1_deq_data[469:465] == 5'd25) ? - IF_rob_deqPort_0_canDeq__3598_THEN_IF_NOT_rob__ETC___d23825 : - y_avValue_snd_fst__h1016405 ; - assign y_avValue_snd_fst__h1016405 = - IF_rob_deqPort_0_canDeq__3598_THEN_IF_NOT_rob__ETC___d23825 | + IF_rob_deqPort_0_canDeq__3600_THEN_IF_NOT_rob__ETC___d23827 : + y_avValue_snd_fst__h1016440 ; + assign y_avValue_snd_fst__h1016440 = + IF_rob_deqPort_0_canDeq__3600_THEN_IF_NOT_rob__ETC___d23827 | rob$deqPort_1_deq_data[31:27] ; - assign y_avValue_snd_fst__h963385 = + assign y_avValue_snd_fst__h963383 = ((fetchStage$pipelines_0_first[268:266] != 3'd1 || specTagManager$canClaim) && regRenamingTable_rename_0_canRename__1151_AND__ETC___d21180) ? - y_avValue_snd_fst__h963427 : + y_avValue_snd_fst__h963425 : specTagManager$currentSpecBits ; - assign y_avValue_snd_fst__h963427 = + assign y_avValue_snd_fst__h963425 = IF_fetchStage_pipelines_0_first__0256_BITS_268_ETC___d21222 ? - y_avValue_snd_fst__h963469 : + y_avValue_snd_fst__h963467 : specTagManager$currentSpecBits ; - assign y_avValue_snd_fst__h963469 = + assign y_avValue_snd_fst__h963467 = (fetchStage$pipelines_0_first[268:266] == 3'd1) ? - spec_bits__h973792 : + spec_bits__h973790 : specTagManager$currentSpecBits ; - assign y_avValue_snd_snd_snd_fst__h1015804 = + assign y_avValue_snd_snd_snd_fst__h1015839 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[274] || rob$deqPort_0_deq_data[469:465] == 5'd0 || @@ -38508,7 +38497,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[469:465] == 5'd25) ? 2'd0 : 2'd1 ; - assign y_avValue_snd_snd_snd_fst__h1016386 = + assign y_avValue_snd_snd_snd_fst__h1016421 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[274] || rob$deqPort_1_deq_data[469:465] == 5'd0 || @@ -38521,12 +38510,12 @@ module mkCore(CLK, rob$deqPort_1_deq_data[469:465] == 5'd20 || rob$deqPort_1_deq_data[469:465] == 5'd24 || rob$deqPort_1_deq_data[469:465] == 5'd25) ? - IF_rob_deqPort_0_canDeq__3598_THEN_IF_NOT_rob__ETC___d23847 : - y_avValue_snd_snd_snd_fst__h1016415 ; - assign y_avValue_snd_snd_snd_fst__h1016415 = - IF_rob_deqPort_0_canDeq__3598_THEN_IF_NOT_rob__ETC___d23847 + + IF_rob_deqPort_0_canDeq__3600_THEN_IF_NOT_rob__ETC___d23849 : + y_avValue_snd_snd_snd_fst__h1016450 ; + assign y_avValue_snd_snd_snd_fst__h1016450 = + IF_rob_deqPort_0_canDeq__3600_THEN_IF_NOT_rob__ETC___d23849 + 2'd1 ; - assign y_avValue_snd_snd_snd_snd_snd__h1015810 = + assign y_avValue_snd_snd_snd_snd_snd__h1015845 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[274] || rob$deqPort_0_deq_data[469:465] == 5'd0 || @@ -38541,7 +38530,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[469:465] == 5'd25) ? 64'd0 : 64'd1 ; - assign y_avValue_snd_snd_snd_snd_snd__h1016392 = + assign y_avValue_snd_snd_snd_snd_snd__h1016427 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[274] || rob$deqPort_1_deq_data[469:465] == 5'd0 || @@ -38554,10 +38543,10 @@ module mkCore(CLK, rob$deqPort_1_deq_data[469:465] == 5'd20 || rob$deqPort_1_deq_data[469:465] == 5'd24 || rob$deqPort_1_deq_data[469:465] == 5'd25) ? - IF_rob_deqPort_0_canDeq__3598_THEN_IF_NOT_rob__ETC___d23719 : - y_avValue_snd_snd_snd_snd_snd__h1016421 ; - assign y_avValue_snd_snd_snd_snd_snd__h1016421 = - IF_rob_deqPort_0_canDeq__3598_THEN_IF_NOT_rob__ETC___d23719 + + IF_rob_deqPort_0_canDeq__3600_THEN_IF_NOT_rob__ETC___d23721 : + y_avValue_snd_snd_snd_snd_snd__h1016456 ; + assign y_avValue_snd_snd_snd_snd_snd__h1016456 = + IF_rob_deqPort_0_canDeq__3600_THEN_IF_NOT_rob__ETC___d23721 + 64'd1 ; always@(mmio_cRqQ_data_0) begin @@ -38582,28 +38571,28 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP) 3'd0: - x__h501097 = + x__h501096 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0; 3'd1: - x__h501097 = + x__h501096 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1; 3'd2: - x__h501097 = + x__h501096 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2; 3'd3: - x__h501097 = + x__h501096 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3; 3'd4: - x__h501097 = + x__h501096 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4; 3'd5: - x__h501097 = + x__h501096 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5; 3'd6: - x__h501097 = + x__h501096 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6; 3'd7: - x__h501097 = + x__h501096 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7; endcase end @@ -38613,10 +38602,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - addr__h505615 = + addr__h505614 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[585:522]; 1'd1: - addr__h505615 = + addr__h505614 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[585:522]; endcase end @@ -38625,16 +38614,16 @@ module mkCore(CLK, coreFix_memExe_memRespLdQ_data_1) begin case (coreFix_memExe_memRespLdQ_deqP) - 1'd0: t__h212841 = coreFix_memExe_memRespLdQ_data_0[133:129]; - 1'd1: t__h212841 = coreFix_memExe_memRespLdQ_data_1[133:129]; + 1'd0: t__h212839 = coreFix_memExe_memRespLdQ_data_0[133:129]; + 1'd1: t__h212839 = coreFix_memExe_memRespLdQ_data_1[133:129]; endcase end always@(coreFix_memExe_forwardQ_deqP or coreFix_memExe_forwardQ_data_0 or coreFix_memExe_forwardQ_data_1) begin case (coreFix_memExe_forwardQ_deqP) - 1'd0: t__h215127 = coreFix_memExe_forwardQ_data_0[133:129]; - 1'd1: t__h215127 = coreFix_memExe_forwardQ_data_1[133:129]; + 1'd0: t__h215125 = coreFix_memExe_forwardQ_data_0[133:129]; + 1'd1: t__h215125 = coreFix_memExe_forwardQ_data_1[133:129]; endcase end always@(coreFix_memExe_dMem_cache_m_banks_0_processAmo or @@ -38693,16 +38682,16 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_processAmo[167:166]) 2'd0: - x__h264732 = + x__h264730 = CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q18; 2'd1: - x__h264732 = + x__h264730 = CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q19; 2'd2: - x__h264732 = + x__h264730 = CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q20; 2'd3: - x__h264732 = + x__h264730 = CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q21; endcase end @@ -38710,8 +38699,8 @@ module mkCore(CLK, begin case (commitStage_commitTrap[35:32]) 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: - i__h995510 = commitStage_commitTrap[35:32]; - default: i__h995510 = 4'd15; + i__h995534 = commitStage_commitTrap[35:32]; + default: i__h995534 = 4'd15; endcase end always@(csrf_mccsr_reg) @@ -38784,123 +38773,123 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - x__h508765 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[2:0]; + x__h508764 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[2:0]; 1'd1: - x__h508765 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[2:0]; + x__h508764 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[2:0]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h576436 = 8'd255; + 3'd0, 3'd1: _theResult___fst_exp__h576434 = 8'd255; 3'd2: - _theResult___fst_exp__h576436 = + _theResult___fst_exp__h576434 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 8'd254 : 8'd255; 3'd3: - _theResult___fst_exp__h576436 = + _theResult___fst_exp__h576434 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 8'd255 : 8'd254; - 3'd4: _theResult___fst_exp__h576436 = 8'd254; - default: _theResult___fst_exp__h576436 = 8'd0; + 3'd4: _theResult___fst_exp__h576434 = 8'd254; + default: _theResult___fst_exp__h576434 = 8'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_sfd__h576437 = 23'd0; + 3'd0, 3'd1: _theResult___fst_sfd__h576435 = 23'd0; 3'd2: - _theResult___fst_sfd__h576437 = + _theResult___fst_sfd__h576435 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 23'd8388607 : 23'd0; 3'd3: - _theResult___fst_sfd__h576437 = + _theResult___fst_sfd__h576435 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 23'd0 : 23'd8388607; - 3'd4: _theResult___fst_sfd__h576437 = 23'd8388607; - default: _theResult___fst_sfd__h576437 = 23'd0; + 3'd4: _theResult___fst_sfd__h576435 = 23'd8388607; + default: _theResult___fst_sfd__h576435 = 23'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h622187 = 8'd255; + 3'd0, 3'd1: _theResult___fst_exp__h622185 = 8'd255; 3'd2: - _theResult___fst_exp__h622187 = + _theResult___fst_exp__h622185 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 8'd254 : 8'd255; 3'd3: - _theResult___fst_exp__h622187 = + _theResult___fst_exp__h622185 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 8'd255 : 8'd254; - 3'd4: _theResult___fst_exp__h622187 = 8'd254; - default: _theResult___fst_exp__h622187 = 8'd0; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h667934 = 8'd255; - 3'd2: - _theResult___fst_exp__h667934 = - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - 8'd254 : - 8'd255; - 3'd3: - _theResult___fst_exp__h667934 = - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - 8'd255 : - 8'd254; - 3'd4: _theResult___fst_exp__h667934 = 8'd254; - default: _theResult___fst_exp__h667934 = 8'd0; + 3'd4: _theResult___fst_exp__h622185 = 8'd254; + default: _theResult___fst_exp__h622185 = 8'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_sfd__h622188 = 23'd0; + 3'd0, 3'd1: _theResult___fst_sfd__h622186 = 23'd0; 3'd2: - _theResult___fst_sfd__h622188 = + _theResult___fst_sfd__h622186 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 23'd8388607 : 23'd0; 3'd3: - _theResult___fst_sfd__h622188 = + _theResult___fst_sfd__h622186 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 23'd0 : 23'd8388607; - 3'd4: _theResult___fst_sfd__h622188 = 23'd8388607; - default: _theResult___fst_sfd__h622188 = 23'd0; + 3'd4: _theResult___fst_sfd__h622186 = 23'd8388607; + default: _theResult___fst_sfd__h622186 = 23'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_sfd__h667935 = 23'd0; + 3'd0, 3'd1: _theResult___fst_exp__h667932 = 8'd255; 3'd2: - _theResult___fst_sfd__h667935 = + _theResult___fst_exp__h667932 = + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? + 8'd254 : + 8'd255; + 3'd3: + _theResult___fst_exp__h667932 = + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? + 8'd255 : + 8'd254; + 3'd4: _theResult___fst_exp__h667932 = 8'd254; + default: _theResult___fst_exp__h667932 = 8'd0; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) + 3'd0, 3'd1: _theResult___fst_sfd__h667933 = 23'd0; + 3'd2: + _theResult___fst_sfd__h667933 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 23'd8388607 : 23'd0; 3'd3: - _theResult___fst_sfd__h667935 = + _theResult___fst_sfd__h667933 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 23'd0 : 23'd8388607; - 3'd4: _theResult___fst_sfd__h667935 = 23'd8388607; - default: _theResult___fst_sfd__h667935 = 23'd0; + 3'd4: _theResult___fst_sfd__h667933 = 23'd8388607; + default: _theResult___fst_sfd__h667933 = 23'd0; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) @@ -39052,16 +39041,62 @@ module mkCore(CLK, 5'd12, 5'd13, 5'd15: - i__h995336 = commitStage_commitTrap[36:32]; - default: i__h995336 = 5'd28; + i__h995334 = commitStage_commitTrap[36:32]; + default: i__h995334 = 5'd28; endcase end - always@(commitStage_commitTrap or cause_code__h996858 or i__h995336) + always@(commitStage_commitTrap or cause_code__h996893 or i__h995334) begin case (commitStage_commitTrap[44:43]) - 2'd0: cause_code__h995320 = 5'd28; - 2'd1: cause_code__h995320 = i__h995336; - default: cause_code__h995320 = cause_code__h996858; + 2'd0: cause_code__h995318 = 5'd28; + 2'd1: cause_code__h995318 = i__h995334; + default: cause_code__h995318 = cause_code__h996893; + endcase + end + always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) + begin + case (coreFix_memExe_lsq$firstLd[37:35]) + 3'd0: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1885 = + coreFix_memExe_respLrScAmoQ_data_0[15:0]; + 3'd1: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1885 = + coreFix_memExe_respLrScAmoQ_data_0[31:16]; + 3'd2: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1885 = + coreFix_memExe_respLrScAmoQ_data_0[47:32]; + 3'd3: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1885 = + coreFix_memExe_respLrScAmoQ_data_0[63:48]; + 3'd4: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1885 = + coreFix_memExe_respLrScAmoQ_data_0[79:64]; + 3'd5: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1885 = + coreFix_memExe_respLrScAmoQ_data_0[95:80]; + 3'd6: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1885 = + coreFix_memExe_respLrScAmoQ_data_0[111:96]; + 3'd7: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1885 = + coreFix_memExe_respLrScAmoQ_data_0[127:112]; + endcase + end + always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) + begin + case (coreFix_memExe_lsq$firstLd[37:36]) + 2'd0: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1872 = + coreFix_memExe_respLrScAmoQ_data_0[31:0]; + 2'd1: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1872 = + coreFix_memExe_respLrScAmoQ_data_0[63:32]; + 2'd2: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1872 = + coreFix_memExe_respLrScAmoQ_data_0[95:64]; + 2'd3: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1872 = + coreFix_memExe_respLrScAmoQ_data_0[127:96]; endcase end always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) @@ -39118,52 +39153,6 @@ module mkCore(CLK, endcase end always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) - begin - case (coreFix_memExe_lsq$firstLd[37:35]) - 3'd0: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1885 = - coreFix_memExe_respLrScAmoQ_data_0[15:0]; - 3'd1: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1885 = - coreFix_memExe_respLrScAmoQ_data_0[31:16]; - 3'd2: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1885 = - coreFix_memExe_respLrScAmoQ_data_0[47:32]; - 3'd3: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1885 = - coreFix_memExe_respLrScAmoQ_data_0[63:48]; - 3'd4: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1885 = - coreFix_memExe_respLrScAmoQ_data_0[79:64]; - 3'd5: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1885 = - coreFix_memExe_respLrScAmoQ_data_0[95:80]; - 3'd6: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1885 = - coreFix_memExe_respLrScAmoQ_data_0[111:96]; - 3'd7: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1885 = - coreFix_memExe_respLrScAmoQ_data_0[127:112]; - endcase - end - always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) - begin - case (coreFix_memExe_lsq$firstLd[37:36]) - 2'd0: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1872 = - coreFix_memExe_respLrScAmoQ_data_0[31:0]; - 2'd1: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1872 = - coreFix_memExe_respLrScAmoQ_data_0[63:32]; - 2'd2: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1872 = - coreFix_memExe_respLrScAmoQ_data_0[95:64]; - 2'd3: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1872 = - coreFix_memExe_respLrScAmoQ_data_0[127:96]; - endcase - end - always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) begin case (coreFix_memExe_lsq$firstLd[37]) 1'd0: @@ -39309,24 +39298,6 @@ module mkCore(CLK, !coreFix_memExe_forwardQ_data_1[128]; endcase end - always@(coreFix_memExe_dMem_cache_m_banks_0_processAmo or - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first) - begin - case (coreFix_memExe_dMem_cache_m_banks_0_processAmo[167:166]) - 2'd0: - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4867 = - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0]; - 2'd1: - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4867 = - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128]; - 2'd2: - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4867 = - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256]; - 2'd3: - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4867 = - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384]; - endcase - end always@(coreFix_memExe_dMem_cache_m_banks_0_processAmo or coreFix_memExe_dMem_cache_m_banks_0_pipeline$first) begin @@ -39345,22 +39316,40 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448]; endcase end + always@(coreFix_memExe_dMem_cache_m_banks_0_processAmo or + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first) + begin + case (coreFix_memExe_dMem_cache_m_banks_0_processAmo[167:166]) + 2'd0: + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4867 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0]; + 2'd1: + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4867 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128]; + 2'd2: + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4867 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256]; + 2'd3: + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4867 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384]; + endcase + end always@(coreFix_memExe_dMem_cache_m_banks_0_processAmo or SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4867 or SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4861) begin case (coreFix_memExe_dMem_cache_m_banks_0_processAmo[165:164]) 2'd0: - x__h264887 = + x__h264885 = SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4867[31:0]; 2'd1: - x__h264887 = + x__h264885 = SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4867[63:32]; 2'd2: - x__h264887 = + x__h264885 = SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4861[31:0]; 2'd3: - x__h264887 = + x__h264885 = SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4861[63:32]; endcase end @@ -39524,394 +39513,446 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[516]; endcase end - always@(guard__h585173 or - _theResult___fst_exp__h593221 or - out_exp__h593666 or _theResult___exp__h593663) + always@(guard__h585171 or + _theResult___fst_exp__h593219 or + out_exp__h593664 or _theResult___exp__h593661) begin - case (guard__h585173) + case (guard__h585171) 2'b0, 2'b01: - CASE_guard85173_0b0_theResult___fst_exp93221_0_ETC__q44 = - _theResult___fst_exp__h593221; + CASE_guard85171_0b0_theResult___fst_exp93219_0_ETC__q44 = + _theResult___fst_exp__h593219; 2'b10: - CASE_guard85173_0b0_theResult___fst_exp93221_0_ETC__q44 = - out_exp__h593666; + CASE_guard85171_0b0_theResult___fst_exp93219_0_ETC__q44 = + out_exp__h593664; 2'b11: - CASE_guard85173_0b0_theResult___fst_exp93221_0_ETC__q44 = - _theResult___exp__h593663; + CASE_guard85171_0b0_theResult___fst_exp93219_0_ETC__q44 = + _theResult___exp__h593661; endcase end - always@(guard__h585173 or - _theResult___fst_exp__h593221 or _theResult___exp__h593663) + always@(guard__h585171 or + _theResult___fst_exp__h593219 or _theResult___exp__h593661) begin - case (guard__h585173) + case (guard__h585171) 2'b0: - CASE_guard85173_0b0_theResult___fst_exp93221_0_ETC__q45 = - _theResult___fst_exp__h593221; + CASE_guard85171_0b0_theResult___fst_exp93219_0_ETC__q45 = + _theResult___fst_exp__h593219; 2'b01, 2'b10, 2'b11: - CASE_guard85173_0b0_theResult___fst_exp93221_0_ETC__q45 = - _theResult___exp__h593663; + CASE_guard85171_0b0_theResult___fst_exp93219_0_ETC__q45 = + _theResult___exp__h593661; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard85173_0b0_theResult___fst_exp93221_0_ETC__q44 or - CASE_guard85173_0b0_theResult___fst_exp93221_0_ETC__q45 or + CASE_guard85171_0b0_theResult___fst_exp93219_0_ETC__q44 or + CASE_guard85171_0b0_theResult___fst_exp93219_0_ETC__q45 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d8655 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d8657 or - _theResult___fst_exp__h593221) + _theResult___fst_exp__h593219) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h593741 = - CASE_guard85173_0b0_theResult___fst_exp93221_0_ETC__q44; + _theResult___fst_exp__h593739 = + CASE_guard85171_0b0_theResult___fst_exp93219_0_ETC__q44; 3'd1: - _theResult___fst_exp__h593741 = - CASE_guard85173_0b0_theResult___fst_exp93221_0_ETC__q45; + _theResult___fst_exp__h593739 = + CASE_guard85171_0b0_theResult___fst_exp93219_0_ETC__q45; 3'd2: - _theResult___fst_exp__h593741 = + _theResult___fst_exp__h593739 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d8655; 3'd3: - _theResult___fst_exp__h593741 = + _theResult___fst_exp__h593739 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d8657; - 3'd4: _theResult___fst_exp__h593741 = _theResult___fst_exp__h593221; - default: _theResult___fst_exp__h593741 = 8'd0; + 3'd4: _theResult___fst_exp__h593739 = _theResult___fst_exp__h593219; + default: _theResult___fst_exp__h593739 = 8'd0; endcase end - always@(guard__h576464 or - _theResult___fst_exp__h584565 or - out_exp__h585084 or _theResult___exp__h585081) + always@(guard__h576462 or + _theResult___fst_exp__h584563 or + out_exp__h585082 or _theResult___exp__h585079) begin - case (guard__h576464) + case (guard__h576462) 2'b0, 2'b01: - CASE_guard76464_0b0_theResult___fst_exp84565_0_ETC__q46 = - _theResult___fst_exp__h584565; + CASE_guard76462_0b0_theResult___fst_exp84563_0_ETC__q46 = + _theResult___fst_exp__h584563; 2'b10: - CASE_guard76464_0b0_theResult___fst_exp84565_0_ETC__q46 = - out_exp__h585084; + CASE_guard76462_0b0_theResult___fst_exp84563_0_ETC__q46 = + out_exp__h585082; 2'b11: - CASE_guard76464_0b0_theResult___fst_exp84565_0_ETC__q46 = - _theResult___exp__h585081; + CASE_guard76462_0b0_theResult___fst_exp84563_0_ETC__q46 = + _theResult___exp__h585079; endcase end - always@(guard__h576464 or - _theResult___fst_exp__h584565 or _theResult___exp__h585081) + always@(guard__h576462 or + _theResult___fst_exp__h584563 or _theResult___exp__h585079) begin - case (guard__h576464) + case (guard__h576462) 2'b0: - CASE_guard76464_0b0_theResult___fst_exp84565_0_ETC__q47 = - _theResult___fst_exp__h584565; + CASE_guard76462_0b0_theResult___fst_exp84563_0_ETC__q47 = + _theResult___fst_exp__h584563; 2'b01, 2'b10, 2'b11: - CASE_guard76464_0b0_theResult___fst_exp84565_0_ETC__q47 = - _theResult___exp__h585081; + CASE_guard76462_0b0_theResult___fst_exp84563_0_ETC__q47 = + _theResult___exp__h585079; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard76464_0b0_theResult___fst_exp84565_0_ETC__q46 or - CASE_guard76464_0b0_theResult___fst_exp84565_0_ETC__q47 or + CASE_guard76462_0b0_theResult___fst_exp84563_0_ETC__q46 or + CASE_guard76462_0b0_theResult___fst_exp84563_0_ETC__q47 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d8433 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d8436 or - _theResult___fst_exp__h584565) + _theResult___fst_exp__h584563) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h585159 = - CASE_guard76464_0b0_theResult___fst_exp84565_0_ETC__q46; + _theResult___fst_exp__h585157 = + CASE_guard76462_0b0_theResult___fst_exp84563_0_ETC__q46; 3'd1: - _theResult___fst_exp__h585159 = - CASE_guard76464_0b0_theResult___fst_exp84565_0_ETC__q47; + _theResult___fst_exp__h585157 = + CASE_guard76462_0b0_theResult___fst_exp84563_0_ETC__q47; 3'd2: - _theResult___fst_exp__h585159 = + _theResult___fst_exp__h585157 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d8433; 3'd3: - _theResult___fst_exp__h585159 = + _theResult___fst_exp__h585157 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d8436; - 3'd4: _theResult___fst_exp__h585159 = _theResult___fst_exp__h584565; - default: _theResult___fst_exp__h585159 = 8'd0; + 3'd4: _theResult___fst_exp__h585157 = _theResult___fst_exp__h584563; + default: _theResult___fst_exp__h585157 = 8'd0; endcase end - always@(guard__h594103 or - _theResult___fst_exp__h602331 or - out_exp__h602850 or _theResult___exp__h602847) + always@(guard__h594101 or + _theResult___fst_exp__h602329 or + out_exp__h602848 or _theResult___exp__h602845) begin - case (guard__h594103) + case (guard__h594101) 2'b0, 2'b01: - CASE_guard94103_0b0_theResult___fst_exp02331_0_ETC__q52 = - _theResult___fst_exp__h602331; + CASE_guard94101_0b0_theResult___fst_exp02329_0_ETC__q52 = + _theResult___fst_exp__h602329; 2'b10: - CASE_guard94103_0b0_theResult___fst_exp02331_0_ETC__q52 = - out_exp__h602850; + CASE_guard94101_0b0_theResult___fst_exp02329_0_ETC__q52 = + out_exp__h602848; 2'b11: - CASE_guard94103_0b0_theResult___fst_exp02331_0_ETC__q52 = - _theResult___exp__h602847; + CASE_guard94101_0b0_theResult___fst_exp02329_0_ETC__q52 = + _theResult___exp__h602845; endcase end - always@(guard__h594103 or - _theResult___fst_exp__h602331 or _theResult___exp__h602847) + always@(guard__h594101 or + _theResult___fst_exp__h602329 or _theResult___exp__h602845) begin - case (guard__h594103) + case (guard__h594101) 2'b0: - CASE_guard94103_0b0_theResult___fst_exp02331_0_ETC__q53 = - _theResult___fst_exp__h602331; + CASE_guard94101_0b0_theResult___fst_exp02329_0_ETC__q53 = + _theResult___fst_exp__h602329; 2'b01, 2'b10, 2'b11: - CASE_guard94103_0b0_theResult___fst_exp02331_0_ETC__q53 = - _theResult___exp__h602847; + CASE_guard94101_0b0_theResult___fst_exp02329_0_ETC__q53 = + _theResult___exp__h602845; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard94103_0b0_theResult___fst_exp02331_0_ETC__q52 or - CASE_guard94103_0b0_theResult___fst_exp02331_0_ETC__q53 or + CASE_guard94101_0b0_theResult___fst_exp02329_0_ETC__q52 or + CASE_guard94101_0b0_theResult___fst_exp02329_0_ETC__q53 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d8980 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d8982 or - _theResult___fst_exp__h602331) + _theResult___fst_exp__h602329) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h602925 = - CASE_guard94103_0b0_theResult___fst_exp02331_0_ETC__q52; + _theResult___fst_exp__h602923 = + CASE_guard94101_0b0_theResult___fst_exp02329_0_ETC__q52; 3'd1: - _theResult___fst_exp__h602925 = - CASE_guard94103_0b0_theResult___fst_exp02331_0_ETC__q53; + _theResult___fst_exp__h602923 = + CASE_guard94101_0b0_theResult___fst_exp02329_0_ETC__q53; 3'd2: - _theResult___fst_exp__h602925 = + _theResult___fst_exp__h602923 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d8980; 3'd3: - _theResult___fst_exp__h602925 = + _theResult___fst_exp__h602923 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d8982; - 3'd4: _theResult___fst_exp__h602925 = _theResult___fst_exp__h602331; - default: _theResult___fst_exp__h602925 = 8'd0; + 3'd4: _theResult___fst_exp__h602923 = _theResult___fst_exp__h602329; + default: _theResult___fst_exp__h602923 = 8'd0; endcase end - always@(guard__h602939 or - _theResult___fst_exp__h611016 or - out_exp__h611486 or _theResult___exp__h611483) + always@(guard__h602937 or + _theResult___fst_exp__h611014 or + out_exp__h611484 or _theResult___exp__h611481) begin - case (guard__h602939) + case (guard__h602937) 2'b0, 2'b01: - CASE_guard02939_0b0_theResult___fst_exp11016_0_ETC__q57 = - _theResult___fst_exp__h611016; + CASE_guard02937_0b0_theResult___fst_exp11014_0_ETC__q57 = + _theResult___fst_exp__h611014; 2'b10: - CASE_guard02939_0b0_theResult___fst_exp11016_0_ETC__q57 = - out_exp__h611486; + CASE_guard02937_0b0_theResult___fst_exp11014_0_ETC__q57 = + out_exp__h611484; 2'b11: - CASE_guard02939_0b0_theResult___fst_exp11016_0_ETC__q57 = - _theResult___exp__h611483; + CASE_guard02937_0b0_theResult___fst_exp11014_0_ETC__q57 = + _theResult___exp__h611481; endcase end - always@(guard__h602939 or - _theResult___fst_exp__h611016 or _theResult___exp__h611483) + always@(guard__h602937 or + _theResult___fst_exp__h611014 or _theResult___exp__h611481) begin - case (guard__h602939) + case (guard__h602937) 2'b0: - CASE_guard02939_0b0_theResult___fst_exp11016_0_ETC__q58 = - _theResult___fst_exp__h611016; + CASE_guard02937_0b0_theResult___fst_exp11014_0_ETC__q58 = + _theResult___fst_exp__h611014; 2'b01, 2'b10, 2'b11: - CASE_guard02939_0b0_theResult___fst_exp11016_0_ETC__q58 = - _theResult___exp__h611483; + CASE_guard02937_0b0_theResult___fst_exp11014_0_ETC__q58 = + _theResult___exp__h611481; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard02939_0b0_theResult___fst_exp11016_0_ETC__q57 or - CASE_guard02939_0b0_theResult___fst_exp11016_0_ETC__q58 or + CASE_guard02937_0b0_theResult___fst_exp11014_0_ETC__q57 or + CASE_guard02937_0b0_theResult___fst_exp11014_0_ETC__q58 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9049 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9051 or - _theResult___fst_exp__h611016) + _theResult___fst_exp__h611014) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h611561 = - CASE_guard02939_0b0_theResult___fst_exp11016_0_ETC__q57; + _theResult___fst_exp__h611559 = + CASE_guard02937_0b0_theResult___fst_exp11014_0_ETC__q57; 3'd1: - _theResult___fst_exp__h611561 = - CASE_guard02939_0b0_theResult___fst_exp11016_0_ETC__q58; + _theResult___fst_exp__h611559 = + CASE_guard02937_0b0_theResult___fst_exp11014_0_ETC__q58; 3'd2: - _theResult___fst_exp__h611561 = + _theResult___fst_exp__h611559 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9049; 3'd3: - _theResult___fst_exp__h611561 = + _theResult___fst_exp__h611559 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9051; - 3'd4: _theResult___fst_exp__h611561 = _theResult___fst_exp__h611016; - default: _theResult___fst_exp__h611561 = 8'd0; + 3'd4: _theResult___fst_exp__h611559 = _theResult___fst_exp__h611014; + default: _theResult___fst_exp__h611559 = 8'd0; endcase end - always@(guard__h585173 or - _theResult___snd__h593172 or - out_sfd__h593667 or _theResult___sfd__h593664) + always@(guard__h585171 or + _theResult___snd__h593170 or + out_sfd__h593665 or _theResult___sfd__h593662) begin - case (guard__h585173) + case (guard__h585171) 2'b0, 2'b01: - CASE_guard85173_0b0_theResult___snd93172_BITS__ETC__q59 = - _theResult___snd__h593172[56:34]; + CASE_guard85171_0b0_theResult___snd93170_BITS__ETC__q59 = + _theResult___snd__h593170[56:34]; 2'b10: - CASE_guard85173_0b0_theResult___snd93172_BITS__ETC__q59 = - out_sfd__h593667; + CASE_guard85171_0b0_theResult___snd93170_BITS__ETC__q59 = + out_sfd__h593665; 2'b11: - CASE_guard85173_0b0_theResult___snd93172_BITS__ETC__q59 = - _theResult___sfd__h593664; + CASE_guard85171_0b0_theResult___snd93170_BITS__ETC__q59 = + _theResult___sfd__h593662; endcase end - always@(guard__h585173 or - _theResult___snd__h593172 or _theResult___sfd__h593664) + always@(guard__h585171 or + _theResult___snd__h593170 or _theResult___sfd__h593662) begin - case (guard__h585173) + case (guard__h585171) 2'b0: - CASE_guard85173_0b0_theResult___snd93172_BITS__ETC__q60 = - _theResult___snd__h593172[56:34]; + CASE_guard85171_0b0_theResult___snd93170_BITS__ETC__q60 = + _theResult___snd__h593170[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard85173_0b0_theResult___snd93172_BITS__ETC__q60 = - _theResult___sfd__h593664; + CASE_guard85171_0b0_theResult___snd93170_BITS__ETC__q60 = + _theResult___sfd__h593662; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard85173_0b0_theResult___snd93172_BITS__ETC__q59 or - CASE_guard85173_0b0_theResult___snd93172_BITS__ETC__q60 or + CASE_guard85171_0b0_theResult___snd93170_BITS__ETC__q59 or + CASE_guard85171_0b0_theResult___snd93170_BITS__ETC__q60 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9099 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9101 or - _theResult___snd__h593172) + _theResult___snd__h593170) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h593742 = - CASE_guard85173_0b0_theResult___snd93172_BITS__ETC__q59; + _theResult___fst_sfd__h593740 = + CASE_guard85171_0b0_theResult___snd93170_BITS__ETC__q59; 3'd1: - _theResult___fst_sfd__h593742 = - CASE_guard85173_0b0_theResult___snd93172_BITS__ETC__q60; + _theResult___fst_sfd__h593740 = + CASE_guard85171_0b0_theResult___snd93170_BITS__ETC__q60; 3'd2: - _theResult___fst_sfd__h593742 = + _theResult___fst_sfd__h593740 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9099; 3'd3: - _theResult___fst_sfd__h593742 = + _theResult___fst_sfd__h593740 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9101; - 3'd4: _theResult___fst_sfd__h593742 = _theResult___snd__h593172[56:34]; - default: _theResult___fst_sfd__h593742 = 23'd0; + 3'd4: _theResult___fst_sfd__h593740 = _theResult___snd__h593170[56:34]; + default: _theResult___fst_sfd__h593740 = 23'd0; endcase end - always@(guard__h576464 or - sfdin__h584559 or out_sfd__h585085 or _theResult___sfd__h585082) + always@(guard__h576462 or + sfdin__h584557 or out_sfd__h585083 or _theResult___sfd__h585080) begin - case (guard__h576464) + case (guard__h576462) 2'b0, 2'b01: - CASE_guard76464_0b0_sfdin84559_BITS_56_TO_34_0_ETC__q61 = - sfdin__h584559[56:34]; + CASE_guard76462_0b0_sfdin84557_BITS_56_TO_34_0_ETC__q61 = + sfdin__h584557[56:34]; 2'b10: - CASE_guard76464_0b0_sfdin84559_BITS_56_TO_34_0_ETC__q61 = - out_sfd__h585085; + CASE_guard76462_0b0_sfdin84557_BITS_56_TO_34_0_ETC__q61 = + out_sfd__h585083; 2'b11: - CASE_guard76464_0b0_sfdin84559_BITS_56_TO_34_0_ETC__q61 = - _theResult___sfd__h585082; + CASE_guard76462_0b0_sfdin84557_BITS_56_TO_34_0_ETC__q61 = + _theResult___sfd__h585080; endcase end - always@(guard__h576464 or sfdin__h584559 or _theResult___sfd__h585082) + always@(guard__h576462 or sfdin__h584557 or _theResult___sfd__h585080) begin - case (guard__h576464) + case (guard__h576462) 2'b0: - CASE_guard76464_0b0_sfdin84559_BITS_56_TO_34_0_ETC__q62 = - sfdin__h584559[56:34]; + CASE_guard76462_0b0_sfdin84557_BITS_56_TO_34_0_ETC__q62 = + sfdin__h584557[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard76464_0b0_sfdin84559_BITS_56_TO_34_0_ETC__q62 = - _theResult___sfd__h585082; + CASE_guard76462_0b0_sfdin84557_BITS_56_TO_34_0_ETC__q62 = + _theResult___sfd__h585080; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard76464_0b0_sfdin84559_BITS_56_TO_34_0_ETC__q61 or - CASE_guard76464_0b0_sfdin84559_BITS_56_TO_34_0_ETC__q62 or + CASE_guard76462_0b0_sfdin84557_BITS_56_TO_34_0_ETC__q61 or + CASE_guard76462_0b0_sfdin84557_BITS_56_TO_34_0_ETC__q62 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9080 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9082 or - sfdin__h584559) + sfdin__h584557) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h585160 = - CASE_guard76464_0b0_sfdin84559_BITS_56_TO_34_0_ETC__q61; + _theResult___fst_sfd__h585158 = + CASE_guard76462_0b0_sfdin84557_BITS_56_TO_34_0_ETC__q61; 3'd1: - _theResult___fst_sfd__h585160 = - CASE_guard76464_0b0_sfdin84559_BITS_56_TO_34_0_ETC__q62; + _theResult___fst_sfd__h585158 = + CASE_guard76462_0b0_sfdin84557_BITS_56_TO_34_0_ETC__q62; 3'd2: - _theResult___fst_sfd__h585160 = + _theResult___fst_sfd__h585158 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9080; 3'd3: - _theResult___fst_sfd__h585160 = + _theResult___fst_sfd__h585158 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9082; - 3'd4: _theResult___fst_sfd__h585160 = sfdin__h584559[56:34]; - default: _theResult___fst_sfd__h585160 = 23'd0; + 3'd4: _theResult___fst_sfd__h585158 = sfdin__h584557[56:34]; + default: _theResult___fst_sfd__h585158 = 23'd0; endcase end - always@(guard__h594103 or - sfdin__h602325 or out_sfd__h602851 or _theResult___sfd__h602848) + always@(guard__h594101 or + sfdin__h602323 or out_sfd__h602849 or _theResult___sfd__h602846) begin - case (guard__h594103) + case (guard__h594101) 2'b0, 2'b01: - CASE_guard94103_0b0_sfdin02325_BITS_56_TO_34_0_ETC__q63 = - sfdin__h602325[56:34]; + CASE_guard94101_0b0_sfdin02323_BITS_56_TO_34_0_ETC__q63 = + sfdin__h602323[56:34]; 2'b10: - CASE_guard94103_0b0_sfdin02325_BITS_56_TO_34_0_ETC__q63 = - out_sfd__h602851; + CASE_guard94101_0b0_sfdin02323_BITS_56_TO_34_0_ETC__q63 = + out_sfd__h602849; 2'b11: - CASE_guard94103_0b0_sfdin02325_BITS_56_TO_34_0_ETC__q63 = - _theResult___sfd__h602848; + CASE_guard94101_0b0_sfdin02323_BITS_56_TO_34_0_ETC__q63 = + _theResult___sfd__h602846; endcase end - always@(guard__h594103 or sfdin__h602325 or _theResult___sfd__h602848) + always@(guard__h594101 or sfdin__h602323 or _theResult___sfd__h602846) begin - case (guard__h594103) + case (guard__h594101) 2'b0: - CASE_guard94103_0b0_sfdin02325_BITS_56_TO_34_0_ETC__q64 = - sfdin__h602325[56:34]; + CASE_guard94101_0b0_sfdin02323_BITS_56_TO_34_0_ETC__q64 = + sfdin__h602323[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard94103_0b0_sfdin02325_BITS_56_TO_34_0_ETC__q64 = - _theResult___sfd__h602848; + CASE_guard94101_0b0_sfdin02323_BITS_56_TO_34_0_ETC__q64 = + _theResult___sfd__h602846; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard94103_0b0_sfdin02325_BITS_56_TO_34_0_ETC__q63 or - CASE_guard94103_0b0_sfdin02325_BITS_56_TO_34_0_ETC__q64 or + CASE_guard94101_0b0_sfdin02323_BITS_56_TO_34_0_ETC__q63 or + CASE_guard94101_0b0_sfdin02323_BITS_56_TO_34_0_ETC__q64 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9126 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9128 or - sfdin__h602325) + sfdin__h602323) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h602926 = - CASE_guard94103_0b0_sfdin02325_BITS_56_TO_34_0_ETC__q63; + _theResult___fst_sfd__h602924 = + CASE_guard94101_0b0_sfdin02323_BITS_56_TO_34_0_ETC__q63; 3'd1: - _theResult___fst_sfd__h602926 = - CASE_guard94103_0b0_sfdin02325_BITS_56_TO_34_0_ETC__q64; + _theResult___fst_sfd__h602924 = + CASE_guard94101_0b0_sfdin02323_BITS_56_TO_34_0_ETC__q64; 3'd2: - _theResult___fst_sfd__h602926 = + _theResult___fst_sfd__h602924 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9126; 3'd3: - _theResult___fst_sfd__h602926 = + _theResult___fst_sfd__h602924 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9128; - 3'd4: _theResult___fst_sfd__h602926 = sfdin__h602325[56:34]; - default: _theResult___fst_sfd__h602926 = 23'd0; + 3'd4: _theResult___fst_sfd__h602924 = sfdin__h602323[56:34]; + default: _theResult___fst_sfd__h602924 = 23'd0; endcase end - always@(guard__h576464 or + always@(guard__h602937 or + _theResult___snd__h610960 or + out_sfd__h611485 or _theResult___sfd__h611482) + begin + case (guard__h602937) + 2'b0, 2'b01: + CASE_guard02937_0b0_theResult___snd10960_BITS__ETC__q65 = + _theResult___snd__h610960[56:34]; + 2'b10: + CASE_guard02937_0b0_theResult___snd10960_BITS__ETC__q65 = + out_sfd__h611485; + 2'b11: + CASE_guard02937_0b0_theResult___snd10960_BITS__ETC__q65 = + _theResult___sfd__h611482; + endcase + end + always@(guard__h602937 or + _theResult___snd__h610960 or _theResult___sfd__h611482) + begin + case (guard__h602937) + 2'b0: + CASE_guard02937_0b0_theResult___snd10960_BITS__ETC__q66 = + _theResult___snd__h610960[56:34]; + 2'b01, 2'b10, 2'b11: + CASE_guard02937_0b0_theResult___snd10960_BITS__ETC__q66 = + _theResult___sfd__h611482; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or + CASE_guard02937_0b0_theResult___snd10960_BITS__ETC__q65 or + CASE_guard02937_0b0_theResult___snd10960_BITS__ETC__q66 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9145 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9147 or + _theResult___snd__h610960) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) + 3'd0: + _theResult___fst_sfd__h611560 = + CASE_guard02937_0b0_theResult___snd10960_BITS__ETC__q65; + 3'd1: + _theResult___fst_sfd__h611560 = + CASE_guard02937_0b0_theResult___snd10960_BITS__ETC__q66; + 3'd2: + _theResult___fst_sfd__h611560 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9145; + 3'd3: + _theResult___fst_sfd__h611560 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9147; + 3'd4: _theResult___fst_sfd__h611560 = _theResult___snd__h610960[56:34]; + default: _theResult___fst_sfd__h611560 = 23'd0; + endcase + end + always@(guard__h576462 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h576464) + case (guard__h576462) 2'b0, 2'b01, 2'b10: - CASE_guard76464_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q65 = + CASE_guard76462_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q67 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard76464_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q65 = - guard__h576464 == 2'b11 && + CASE_guard76462_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q67 = + guard__h576462 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard76464_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q65 or - guard__h576464) + CASE_guard76462_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q67 or + guard__h576462) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9233 = - CASE_guard76464_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q65; + CASE_guard76462_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q67; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9233 = - (guard__h576464 == 2'b0) ? + (guard__h576462 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h576464 == 2'b01 || guard__h576464 == 2'b10 || - guard__h576464 == 2'b11) && + (guard__h576462 == 2'b01 || guard__h576462 == 2'b10 || + guard__h576462 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9233 = @@ -39922,86 +39963,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h602939 or - _theResult___snd__h610962 or - out_sfd__h611487 or _theResult___sfd__h611484) - begin - case (guard__h602939) - 2'b0, 2'b01: - CASE_guard02939_0b0_theResult___snd10962_BITS__ETC__q66 = - _theResult___snd__h610962[56:34]; - 2'b10: - CASE_guard02939_0b0_theResult___snd10962_BITS__ETC__q66 = - out_sfd__h611487; - 2'b11: - CASE_guard02939_0b0_theResult___snd10962_BITS__ETC__q66 = - _theResult___sfd__h611484; - endcase - end - always@(guard__h602939 or - _theResult___snd__h610962 or _theResult___sfd__h611484) - begin - case (guard__h602939) - 2'b0: - CASE_guard02939_0b0_theResult___snd10962_BITS__ETC__q67 = - _theResult___snd__h610962[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard02939_0b0_theResult___snd10962_BITS__ETC__q67 = - _theResult___sfd__h611484; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard02939_0b0_theResult___snd10962_BITS__ETC__q66 or - CASE_guard02939_0b0_theResult___snd10962_BITS__ETC__q67 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9145 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9147 or - _theResult___snd__h610962) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0: - _theResult___fst_sfd__h611562 = - CASE_guard02939_0b0_theResult___snd10962_BITS__ETC__q66; - 3'd1: - _theResult___fst_sfd__h611562 = - CASE_guard02939_0b0_theResult___snd10962_BITS__ETC__q67; - 3'd2: - _theResult___fst_sfd__h611562 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9145; - 3'd3: - _theResult___fst_sfd__h611562 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9147; - 3'd4: _theResult___fst_sfd__h611562 = _theResult___snd__h610962[56:34]; - default: _theResult___fst_sfd__h611562 = 23'd0; - endcase - end - always@(guard__h576464 or + always@(guard__h576462 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h576464) + case (guard__h576462) 2'b0, 2'b01, 2'b10: - CASE_guard76464_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q68 = + CASE_guard76462_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q68 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard76464_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q68 = - guard__h576464 != 2'b11 || + CASE_guard76462_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q68 = + guard__h576462 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard76464_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q68 or - guard__h576464) + CASE_guard76462_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q68 or + guard__h576462) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9177 = - CASE_guard76464_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q68; + CASE_guard76462_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q68; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9177 = - (guard__h576464 == 2'b0) ? + (guard__h576462 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h576464 != 2'b01 && guard__h576464 != 2'b10 && - guard__h576464 != 2'b11 || + guard__h576462 != 2'b01 && guard__h576462 != 2'b10 && + guard__h576462 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9177 = @@ -40012,34 +40001,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h585173 or + always@(guard__h585171 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h585173) + case (guard__h585171) 2'b0, 2'b01, 2'b10: - CASE_guard85173_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q69 = + CASE_guard85171_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q69 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard85173_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q69 = - guard__h585173 == 2'b11 && + CASE_guard85171_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q69 = + guard__h585171 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard85173_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q69 or - guard__h585173) + CASE_guard85171_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q69 or + guard__h585171) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9240 = - CASE_guard85173_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q69; + CASE_guard85171_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q69; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9240 = - (guard__h585173 == 2'b0) ? + (guard__h585171 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h585173 == 2'b01 || guard__h585173 == 2'b10 || - guard__h585173 == 2'b11) && + (guard__h585171 == 2'b01 || guard__h585171 == 2'b10 || + guard__h585171 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9240 = @@ -40050,34 +40039,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h585173 or + always@(guard__h585171 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h585173) + case (guard__h585171) 2'b0, 2'b01, 2'b10: - CASE_guard85173_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q70 = + CASE_guard85171_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q70 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard85173_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q70 = - guard__h585173 != 2'b11 || + CASE_guard85171_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q70 = + guard__h585171 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard85173_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q70 or - guard__h585173) + CASE_guard85171_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q70 or + guard__h585171) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9190 = - CASE_guard85173_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q70; + CASE_guard85171_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q70; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9190 = - (guard__h585173 == 2'b0) ? + (guard__h585171 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h585173 != 2'b01 && guard__h585173 != 2'b10 && - guard__h585173 != 2'b11 || + guard__h585171 != 2'b01 && guard__h585171 != 2'b10 && + guard__h585171 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9190 = @@ -40088,34 +40077,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h594103 or + always@(guard__h594101 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h594103) + case (guard__h594101) 2'b0, 2'b01, 2'b10: - CASE_guard94103_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q71 = + CASE_guard94101_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q71 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard94103_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q71 = - guard__h594103 == 2'b11 && + CASE_guard94101_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q71 = + guard__h594101 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard94103_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q71 or - guard__h594103) + CASE_guard94101_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q71 or + guard__h594101) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9250 = - CASE_guard94103_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q71; + CASE_guard94101_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q71; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9250 = - (guard__h594103 == 2'b0) ? + (guard__h594101 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h594103 == 2'b01 || guard__h594103 == 2'b10 || - guard__h594103 == 2'b11) && + (guard__h594101 == 2'b01 || guard__h594101 == 2'b10 || + guard__h594101 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9250 = @@ -40126,34 +40115,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h594103 or + always@(guard__h594101 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h594103) + case (guard__h594101) 2'b0, 2'b01, 2'b10: - CASE_guard94103_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q72 = + CASE_guard94101_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q72 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard94103_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q72 = - guard__h594103 != 2'b11 || + CASE_guard94101_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q72 = + guard__h594101 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard94103_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q72 or - guard__h594103) + CASE_guard94101_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q72 or + guard__h594101) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9207 = - CASE_guard94103_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q72; + CASE_guard94101_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q72; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9207 = - (guard__h594103 == 2'b0) ? + (guard__h594101 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h594103 != 2'b01 && guard__h594103 != 2'b10 && - guard__h594103 != 2'b11 || + guard__h594101 != 2'b01 && guard__h594101 != 2'b10 && + guard__h594101 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9207 = @@ -40164,34 +40153,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h602939 or + always@(guard__h602937 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h602939) + case (guard__h602937) 2'b0, 2'b01, 2'b10: - CASE_guard02939_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q73 = + CASE_guard02937_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q73 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard02939_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q73 = - guard__h602939 == 2'b11 && + CASE_guard02937_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q73 = + guard__h602937 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard02939_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q73 or - guard__h602939) + CASE_guard02937_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q73 or + guard__h602937) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9257 = - CASE_guard02939_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q73; + CASE_guard02937_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q73; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9257 = - (guard__h602939 == 2'b0) ? + (guard__h602937 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h602939 == 2'b01 || guard__h602939 == 2'b10 || - guard__h602939 == 2'b11) && + (guard__h602937 == 2'b01 || guard__h602937 == 2'b10 || + guard__h602937 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9257 = @@ -40202,34 +40191,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h602939 or + always@(guard__h602937 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h602939) + case (guard__h602937) 2'b0, 2'b01, 2'b10: - CASE_guard02939_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q74 = + CASE_guard02937_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q74 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard02939_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q74 = - guard__h602939 != 2'b11 || + CASE_guard02937_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q74 = + guard__h602937 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard02939_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q74 or - guard__h602939) + CASE_guard02937_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q74 or + guard__h602937) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9220 = - CASE_guard02939_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q74; + CASE_guard02937_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q74; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9220 = - (guard__h602939 == 2'b0) ? + (guard__h602937 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h602939 != 2'b01 && guard__h602939 != 2'b10 && - guard__h602939 != 2'b11 || + guard__h602937 != 2'b01 && guard__h602937 != 2'b10 && + guard__h602937 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9220 = @@ -40266,446 +40255,394 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h630922 or - _theResult___fst_exp__h638970 or - out_exp__h639415 or _theResult___exp__h639412) + always@(guard__h630920 or + _theResult___fst_exp__h638968 or + out_exp__h639413 or _theResult___exp__h639410) begin - case (guard__h630922) + case (guard__h630920) 2'b0, 2'b01: - CASE_guard30922_0b0_theResult___fst_exp38970_0_ETC__q79 = - _theResult___fst_exp__h638970; + CASE_guard30920_0b0_theResult___fst_exp38968_0_ETC__q79 = + _theResult___fst_exp__h638968; 2'b10: - CASE_guard30922_0b0_theResult___fst_exp38970_0_ETC__q79 = - out_exp__h639415; + CASE_guard30920_0b0_theResult___fst_exp38968_0_ETC__q79 = + out_exp__h639413; 2'b11: - CASE_guard30922_0b0_theResult___fst_exp38970_0_ETC__q79 = - _theResult___exp__h639412; + CASE_guard30920_0b0_theResult___fst_exp38968_0_ETC__q79 = + _theResult___exp__h639410; endcase end - always@(guard__h630922 or - _theResult___fst_exp__h638970 or _theResult___exp__h639412) + always@(guard__h630920 or + _theResult___fst_exp__h638968 or _theResult___exp__h639410) begin - case (guard__h630922) + case (guard__h630920) 2'b0: - CASE_guard30922_0b0_theResult___fst_exp38970_0_ETC__q80 = - _theResult___fst_exp__h638970; + CASE_guard30920_0b0_theResult___fst_exp38968_0_ETC__q80 = + _theResult___fst_exp__h638968; 2'b01, 2'b10, 2'b11: - CASE_guard30922_0b0_theResult___fst_exp38970_0_ETC__q80 = - _theResult___exp__h639412; + CASE_guard30920_0b0_theResult___fst_exp38968_0_ETC__q80 = + _theResult___exp__h639410; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard30922_0b0_theResult___fst_exp38970_0_ETC__q79 or - CASE_guard30922_0b0_theResult___fst_exp38970_0_ETC__q80 or + CASE_guard30920_0b0_theResult___fst_exp38968_0_ETC__q79 or + CASE_guard30920_0b0_theResult___fst_exp38968_0_ETC__q80 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10052 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10054 or - _theResult___fst_exp__h638970) + _theResult___fst_exp__h638968) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h639490 = - CASE_guard30922_0b0_theResult___fst_exp38970_0_ETC__q79; + _theResult___fst_exp__h639488 = + CASE_guard30920_0b0_theResult___fst_exp38968_0_ETC__q79; 3'd1: - _theResult___fst_exp__h639490 = - CASE_guard30922_0b0_theResult___fst_exp38970_0_ETC__q80; + _theResult___fst_exp__h639488 = + CASE_guard30920_0b0_theResult___fst_exp38968_0_ETC__q80; 3'd2: - _theResult___fst_exp__h639490 = + _theResult___fst_exp__h639488 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10052; 3'd3: - _theResult___fst_exp__h639490 = + _theResult___fst_exp__h639488 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10054; - 3'd4: _theResult___fst_exp__h639490 = _theResult___fst_exp__h638970; - default: _theResult___fst_exp__h639490 = 8'd0; + 3'd4: _theResult___fst_exp__h639488 = _theResult___fst_exp__h638968; + default: _theResult___fst_exp__h639488 = 8'd0; endcase end - always@(guard__h622215 or - _theResult___fst_exp__h630314 or - out_exp__h630833 or _theResult___exp__h630830) + always@(guard__h622213 or + _theResult___fst_exp__h630312 or + out_exp__h630831 or _theResult___exp__h630828) begin - case (guard__h622215) + case (guard__h622213) 2'b0, 2'b01: - CASE_guard22215_0b0_theResult___fst_exp30314_0_ETC__q81 = - _theResult___fst_exp__h630314; + CASE_guard22213_0b0_theResult___fst_exp30312_0_ETC__q81 = + _theResult___fst_exp__h630312; 2'b10: - CASE_guard22215_0b0_theResult___fst_exp30314_0_ETC__q81 = - out_exp__h630833; + CASE_guard22213_0b0_theResult___fst_exp30312_0_ETC__q81 = + out_exp__h630831; 2'b11: - CASE_guard22215_0b0_theResult___fst_exp30314_0_ETC__q81 = - _theResult___exp__h630830; + CASE_guard22213_0b0_theResult___fst_exp30312_0_ETC__q81 = + _theResult___exp__h630828; endcase end - always@(guard__h622215 or - _theResult___fst_exp__h630314 or _theResult___exp__h630830) + always@(guard__h622213 or + _theResult___fst_exp__h630312 or _theResult___exp__h630828) begin - case (guard__h622215) + case (guard__h622213) 2'b0: - CASE_guard22215_0b0_theResult___fst_exp30314_0_ETC__q82 = - _theResult___fst_exp__h630314; + CASE_guard22213_0b0_theResult___fst_exp30312_0_ETC__q82 = + _theResult___fst_exp__h630312; 2'b01, 2'b10, 2'b11: - CASE_guard22215_0b0_theResult___fst_exp30314_0_ETC__q82 = - _theResult___exp__h630830; + CASE_guard22213_0b0_theResult___fst_exp30312_0_ETC__q82 = + _theResult___exp__h630828; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard22215_0b0_theResult___fst_exp30314_0_ETC__q81 or - CASE_guard22215_0b0_theResult___fst_exp30314_0_ETC__q82 or + CASE_guard22213_0b0_theResult___fst_exp30312_0_ETC__q81 or + CASE_guard22213_0b0_theResult___fst_exp30312_0_ETC__q82 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9830 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9833 or - _theResult___fst_exp__h630314) + _theResult___fst_exp__h630312) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h630908 = - CASE_guard22215_0b0_theResult___fst_exp30314_0_ETC__q81; + _theResult___fst_exp__h630906 = + CASE_guard22213_0b0_theResult___fst_exp30312_0_ETC__q81; 3'd1: - _theResult___fst_exp__h630908 = - CASE_guard22215_0b0_theResult___fst_exp30314_0_ETC__q82; + _theResult___fst_exp__h630906 = + CASE_guard22213_0b0_theResult___fst_exp30312_0_ETC__q82; 3'd2: - _theResult___fst_exp__h630908 = + _theResult___fst_exp__h630906 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9830; 3'd3: - _theResult___fst_exp__h630908 = + _theResult___fst_exp__h630906 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9833; - 3'd4: _theResult___fst_exp__h630908 = _theResult___fst_exp__h630314; - default: _theResult___fst_exp__h630908 = 8'd0; + 3'd4: _theResult___fst_exp__h630906 = _theResult___fst_exp__h630312; + default: _theResult___fst_exp__h630906 = 8'd0; endcase end - always@(guard__h639852 or - _theResult___fst_exp__h648080 or - out_exp__h648599 or _theResult___exp__h648596) + always@(guard__h639850 or + _theResult___fst_exp__h648078 or + out_exp__h648597 or _theResult___exp__h648594) begin - case (guard__h639852) + case (guard__h639850) 2'b0, 2'b01: - CASE_guard39852_0b0_theResult___fst_exp48080_0_ETC__q87 = - _theResult___fst_exp__h648080; + CASE_guard39850_0b0_theResult___fst_exp48078_0_ETC__q87 = + _theResult___fst_exp__h648078; 2'b10: - CASE_guard39852_0b0_theResult___fst_exp48080_0_ETC__q87 = - out_exp__h648599; + CASE_guard39850_0b0_theResult___fst_exp48078_0_ETC__q87 = + out_exp__h648597; 2'b11: - CASE_guard39852_0b0_theResult___fst_exp48080_0_ETC__q87 = - _theResult___exp__h648596; + CASE_guard39850_0b0_theResult___fst_exp48078_0_ETC__q87 = + _theResult___exp__h648594; endcase end - always@(guard__h639852 or - _theResult___fst_exp__h648080 or _theResult___exp__h648596) + always@(guard__h639850 or + _theResult___fst_exp__h648078 or _theResult___exp__h648594) begin - case (guard__h639852) + case (guard__h639850) 2'b0: - CASE_guard39852_0b0_theResult___fst_exp48080_0_ETC__q88 = - _theResult___fst_exp__h648080; + CASE_guard39850_0b0_theResult___fst_exp48078_0_ETC__q88 = + _theResult___fst_exp__h648078; 2'b01, 2'b10, 2'b11: - CASE_guard39852_0b0_theResult___fst_exp48080_0_ETC__q88 = - _theResult___exp__h648596; + CASE_guard39850_0b0_theResult___fst_exp48078_0_ETC__q88 = + _theResult___exp__h648594; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard39852_0b0_theResult___fst_exp48080_0_ETC__q87 or - CASE_guard39852_0b0_theResult___fst_exp48080_0_ETC__q88 or + CASE_guard39850_0b0_theResult___fst_exp48078_0_ETC__q87 or + CASE_guard39850_0b0_theResult___fst_exp48078_0_ETC__q88 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10377 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10379 or - _theResult___fst_exp__h648080) + _theResult___fst_exp__h648078) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h648674 = - CASE_guard39852_0b0_theResult___fst_exp48080_0_ETC__q87; + _theResult___fst_exp__h648672 = + CASE_guard39850_0b0_theResult___fst_exp48078_0_ETC__q87; 3'd1: - _theResult___fst_exp__h648674 = - CASE_guard39852_0b0_theResult___fst_exp48080_0_ETC__q88; + _theResult___fst_exp__h648672 = + CASE_guard39850_0b0_theResult___fst_exp48078_0_ETC__q88; 3'd2: - _theResult___fst_exp__h648674 = + _theResult___fst_exp__h648672 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10377; 3'd3: - _theResult___fst_exp__h648674 = + _theResult___fst_exp__h648672 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10379; - 3'd4: _theResult___fst_exp__h648674 = _theResult___fst_exp__h648080; - default: _theResult___fst_exp__h648674 = 8'd0; + 3'd4: _theResult___fst_exp__h648672 = _theResult___fst_exp__h648078; + default: _theResult___fst_exp__h648672 = 8'd0; endcase end - always@(guard__h648688 or - _theResult___fst_exp__h656765 or - out_exp__h657235 or _theResult___exp__h657232) + always@(guard__h648686 or + _theResult___fst_exp__h656763 or + out_exp__h657233 or _theResult___exp__h657230) begin - case (guard__h648688) + case (guard__h648686) 2'b0, 2'b01: - CASE_guard48688_0b0_theResult___fst_exp56765_0_ETC__q92 = - _theResult___fst_exp__h656765; + CASE_guard48686_0b0_theResult___fst_exp56763_0_ETC__q92 = + _theResult___fst_exp__h656763; 2'b10: - CASE_guard48688_0b0_theResult___fst_exp56765_0_ETC__q92 = - out_exp__h657235; + CASE_guard48686_0b0_theResult___fst_exp56763_0_ETC__q92 = + out_exp__h657233; 2'b11: - CASE_guard48688_0b0_theResult___fst_exp56765_0_ETC__q92 = - _theResult___exp__h657232; + CASE_guard48686_0b0_theResult___fst_exp56763_0_ETC__q92 = + _theResult___exp__h657230; endcase end - always@(guard__h648688 or - _theResult___fst_exp__h656765 or _theResult___exp__h657232) + always@(guard__h648686 or + _theResult___fst_exp__h656763 or _theResult___exp__h657230) begin - case (guard__h648688) + case (guard__h648686) 2'b0: - CASE_guard48688_0b0_theResult___fst_exp56765_0_ETC__q93 = - _theResult___fst_exp__h656765; + CASE_guard48686_0b0_theResult___fst_exp56763_0_ETC__q93 = + _theResult___fst_exp__h656763; 2'b01, 2'b10, 2'b11: - CASE_guard48688_0b0_theResult___fst_exp56765_0_ETC__q93 = - _theResult___exp__h657232; + CASE_guard48686_0b0_theResult___fst_exp56763_0_ETC__q93 = + _theResult___exp__h657230; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard48688_0b0_theResult___fst_exp56765_0_ETC__q92 or - CASE_guard48688_0b0_theResult___fst_exp56765_0_ETC__q93 or + CASE_guard48686_0b0_theResult___fst_exp56763_0_ETC__q92 or + CASE_guard48686_0b0_theResult___fst_exp56763_0_ETC__q93 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10446 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10448 or - _theResult___fst_exp__h656765) + _theResult___fst_exp__h656763) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h657310 = - CASE_guard48688_0b0_theResult___fst_exp56765_0_ETC__q92; + _theResult___fst_exp__h657308 = + CASE_guard48686_0b0_theResult___fst_exp56763_0_ETC__q92; 3'd1: - _theResult___fst_exp__h657310 = - CASE_guard48688_0b0_theResult___fst_exp56765_0_ETC__q93; + _theResult___fst_exp__h657308 = + CASE_guard48686_0b0_theResult___fst_exp56763_0_ETC__q93; 3'd2: - _theResult___fst_exp__h657310 = + _theResult___fst_exp__h657308 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10446; 3'd3: - _theResult___fst_exp__h657310 = + _theResult___fst_exp__h657308 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10448; - 3'd4: _theResult___fst_exp__h657310 = _theResult___fst_exp__h656765; - default: _theResult___fst_exp__h657310 = 8'd0; + 3'd4: _theResult___fst_exp__h657308 = _theResult___fst_exp__h656763; + default: _theResult___fst_exp__h657308 = 8'd0; endcase end - always@(guard__h630922 or - _theResult___snd__h638921 or - out_sfd__h639416 or _theResult___sfd__h639413) + always@(guard__h630920 or + _theResult___snd__h638919 or + out_sfd__h639414 or _theResult___sfd__h639411) begin - case (guard__h630922) + case (guard__h630920) 2'b0, 2'b01: - CASE_guard30922_0b0_theResult___snd38921_BITS__ETC__q94 = - _theResult___snd__h638921[56:34]; + CASE_guard30920_0b0_theResult___snd38919_BITS__ETC__q94 = + _theResult___snd__h638919[56:34]; 2'b10: - CASE_guard30922_0b0_theResult___snd38921_BITS__ETC__q94 = - out_sfd__h639416; + CASE_guard30920_0b0_theResult___snd38919_BITS__ETC__q94 = + out_sfd__h639414; 2'b11: - CASE_guard30922_0b0_theResult___snd38921_BITS__ETC__q94 = - _theResult___sfd__h639413; + CASE_guard30920_0b0_theResult___snd38919_BITS__ETC__q94 = + _theResult___sfd__h639411; endcase end - always@(guard__h630922 or - _theResult___snd__h638921 or _theResult___sfd__h639413) + always@(guard__h630920 or + _theResult___snd__h638919 or _theResult___sfd__h639411) begin - case (guard__h630922) + case (guard__h630920) 2'b0: - CASE_guard30922_0b0_theResult___snd38921_BITS__ETC__q95 = - _theResult___snd__h638921[56:34]; + CASE_guard30920_0b0_theResult___snd38919_BITS__ETC__q95 = + _theResult___snd__h638919[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard30922_0b0_theResult___snd38921_BITS__ETC__q95 = - _theResult___sfd__h639413; + CASE_guard30920_0b0_theResult___snd38919_BITS__ETC__q95 = + _theResult___sfd__h639411; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard30922_0b0_theResult___snd38921_BITS__ETC__q94 or - CASE_guard30922_0b0_theResult___snd38921_BITS__ETC__q95 or + CASE_guard30920_0b0_theResult___snd38919_BITS__ETC__q94 or + CASE_guard30920_0b0_theResult___snd38919_BITS__ETC__q95 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10496 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10498 or - _theResult___snd__h638921) + _theResult___snd__h638919) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h639491 = - CASE_guard30922_0b0_theResult___snd38921_BITS__ETC__q94; + _theResult___fst_sfd__h639489 = + CASE_guard30920_0b0_theResult___snd38919_BITS__ETC__q94; 3'd1: - _theResult___fst_sfd__h639491 = - CASE_guard30922_0b0_theResult___snd38921_BITS__ETC__q95; + _theResult___fst_sfd__h639489 = + CASE_guard30920_0b0_theResult___snd38919_BITS__ETC__q95; 3'd2: - _theResult___fst_sfd__h639491 = + _theResult___fst_sfd__h639489 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10496; 3'd3: - _theResult___fst_sfd__h639491 = + _theResult___fst_sfd__h639489 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10498; - 3'd4: _theResult___fst_sfd__h639491 = _theResult___snd__h638921[56:34]; - default: _theResult___fst_sfd__h639491 = 23'd0; + 3'd4: _theResult___fst_sfd__h639489 = _theResult___snd__h638919[56:34]; + default: _theResult___fst_sfd__h639489 = 23'd0; endcase end - always@(guard__h622215 or - sfdin__h630308 or out_sfd__h630834 or _theResult___sfd__h630831) + always@(guard__h622213 or + sfdin__h630306 or out_sfd__h630832 or _theResult___sfd__h630829) begin - case (guard__h622215) + case (guard__h622213) 2'b0, 2'b01: - CASE_guard22215_0b0_sfdin30308_BITS_56_TO_34_0_ETC__q96 = - sfdin__h630308[56:34]; + CASE_guard22213_0b0_sfdin30306_BITS_56_TO_34_0_ETC__q96 = + sfdin__h630306[56:34]; 2'b10: - CASE_guard22215_0b0_sfdin30308_BITS_56_TO_34_0_ETC__q96 = - out_sfd__h630834; + CASE_guard22213_0b0_sfdin30306_BITS_56_TO_34_0_ETC__q96 = + out_sfd__h630832; 2'b11: - CASE_guard22215_0b0_sfdin30308_BITS_56_TO_34_0_ETC__q96 = - _theResult___sfd__h630831; + CASE_guard22213_0b0_sfdin30306_BITS_56_TO_34_0_ETC__q96 = + _theResult___sfd__h630829; endcase end - always@(guard__h622215 or sfdin__h630308 or _theResult___sfd__h630831) + always@(guard__h622213 or sfdin__h630306 or _theResult___sfd__h630829) begin - case (guard__h622215) + case (guard__h622213) 2'b0: - CASE_guard22215_0b0_sfdin30308_BITS_56_TO_34_0_ETC__q97 = - sfdin__h630308[56:34]; + CASE_guard22213_0b0_sfdin30306_BITS_56_TO_34_0_ETC__q97 = + sfdin__h630306[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard22215_0b0_sfdin30308_BITS_56_TO_34_0_ETC__q97 = - _theResult___sfd__h630831; + CASE_guard22213_0b0_sfdin30306_BITS_56_TO_34_0_ETC__q97 = + _theResult___sfd__h630829; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard22215_0b0_sfdin30308_BITS_56_TO_34_0_ETC__q96 or - CASE_guard22215_0b0_sfdin30308_BITS_56_TO_34_0_ETC__q97 or + CASE_guard22213_0b0_sfdin30306_BITS_56_TO_34_0_ETC__q96 or + CASE_guard22213_0b0_sfdin30306_BITS_56_TO_34_0_ETC__q97 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d10477 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d10479 or - sfdin__h630308) + sfdin__h630306) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h630909 = - CASE_guard22215_0b0_sfdin30308_BITS_56_TO_34_0_ETC__q96; + _theResult___fst_sfd__h630907 = + CASE_guard22213_0b0_sfdin30306_BITS_56_TO_34_0_ETC__q96; 3'd1: - _theResult___fst_sfd__h630909 = - CASE_guard22215_0b0_sfdin30308_BITS_56_TO_34_0_ETC__q97; + _theResult___fst_sfd__h630907 = + CASE_guard22213_0b0_sfdin30306_BITS_56_TO_34_0_ETC__q97; 3'd2: - _theResult___fst_sfd__h630909 = + _theResult___fst_sfd__h630907 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d10477; 3'd3: - _theResult___fst_sfd__h630909 = + _theResult___fst_sfd__h630907 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d10479; - 3'd4: _theResult___fst_sfd__h630909 = sfdin__h630308[56:34]; - default: _theResult___fst_sfd__h630909 = 23'd0; + 3'd4: _theResult___fst_sfd__h630907 = sfdin__h630306[56:34]; + default: _theResult___fst_sfd__h630907 = 23'd0; endcase end - always@(guard__h639852 or - sfdin__h648074 or out_sfd__h648600 or _theResult___sfd__h648597) + always@(guard__h639850 or + sfdin__h648072 or out_sfd__h648598 or _theResult___sfd__h648595) begin - case (guard__h639852) + case (guard__h639850) 2'b0, 2'b01: - CASE_guard39852_0b0_sfdin48074_BITS_56_TO_34_0_ETC__q98 = - sfdin__h648074[56:34]; + CASE_guard39850_0b0_sfdin48072_BITS_56_TO_34_0_ETC__q98 = + sfdin__h648072[56:34]; 2'b10: - CASE_guard39852_0b0_sfdin48074_BITS_56_TO_34_0_ETC__q98 = - out_sfd__h648600; + CASE_guard39850_0b0_sfdin48072_BITS_56_TO_34_0_ETC__q98 = + out_sfd__h648598; 2'b11: - CASE_guard39852_0b0_sfdin48074_BITS_56_TO_34_0_ETC__q98 = - _theResult___sfd__h648597; + CASE_guard39850_0b0_sfdin48072_BITS_56_TO_34_0_ETC__q98 = + _theResult___sfd__h648595; endcase end - always@(guard__h639852 or sfdin__h648074 or _theResult___sfd__h648597) + always@(guard__h639850 or sfdin__h648072 or _theResult___sfd__h648595) begin - case (guard__h639852) + case (guard__h639850) 2'b0: - CASE_guard39852_0b0_sfdin48074_BITS_56_TO_34_0_ETC__q99 = - sfdin__h648074[56:34]; + CASE_guard39850_0b0_sfdin48072_BITS_56_TO_34_0_ETC__q99 = + sfdin__h648072[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard39852_0b0_sfdin48074_BITS_56_TO_34_0_ETC__q99 = - _theResult___sfd__h648597; + CASE_guard39850_0b0_sfdin48072_BITS_56_TO_34_0_ETC__q99 = + _theResult___sfd__h648595; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard39852_0b0_sfdin48074_BITS_56_TO_34_0_ETC__q98 or - CASE_guard39852_0b0_sfdin48074_BITS_56_TO_34_0_ETC__q99 or + CASE_guard39850_0b0_sfdin48072_BITS_56_TO_34_0_ETC__q98 or + CASE_guard39850_0b0_sfdin48072_BITS_56_TO_34_0_ETC__q99 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10523 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10525 or - sfdin__h648074) + sfdin__h648072) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h648675 = - CASE_guard39852_0b0_sfdin48074_BITS_56_TO_34_0_ETC__q98; + _theResult___fst_sfd__h648673 = + CASE_guard39850_0b0_sfdin48072_BITS_56_TO_34_0_ETC__q98; 3'd1: - _theResult___fst_sfd__h648675 = - CASE_guard39852_0b0_sfdin48074_BITS_56_TO_34_0_ETC__q99; + _theResult___fst_sfd__h648673 = + CASE_guard39850_0b0_sfdin48072_BITS_56_TO_34_0_ETC__q99; 3'd2: - _theResult___fst_sfd__h648675 = + _theResult___fst_sfd__h648673 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10523; 3'd3: - _theResult___fst_sfd__h648675 = + _theResult___fst_sfd__h648673 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10525; - 3'd4: _theResult___fst_sfd__h648675 = sfdin__h648074[56:34]; - default: _theResult___fst_sfd__h648675 = 23'd0; + 3'd4: _theResult___fst_sfd__h648673 = sfdin__h648072[56:34]; + default: _theResult___fst_sfd__h648673 = 23'd0; endcase end - always@(guard__h648688 or - _theResult___snd__h656711 or - out_sfd__h657236 or _theResult___sfd__h657233) - begin - case (guard__h648688) - 2'b0, 2'b01: - CASE_guard48688_0b0_theResult___snd56711_BITS__ETC__q100 = - _theResult___snd__h656711[56:34]; - 2'b10: - CASE_guard48688_0b0_theResult___snd56711_BITS__ETC__q100 = - out_sfd__h657236; - 2'b11: - CASE_guard48688_0b0_theResult___snd56711_BITS__ETC__q100 = - _theResult___sfd__h657233; - endcase - end - always@(guard__h648688 or - _theResult___snd__h656711 or _theResult___sfd__h657233) - begin - case (guard__h648688) - 2'b0: - CASE_guard48688_0b0_theResult___snd56711_BITS__ETC__q101 = - _theResult___snd__h656711[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard48688_0b0_theResult___snd56711_BITS__ETC__q101 = - _theResult___sfd__h657233; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard48688_0b0_theResult___snd56711_BITS__ETC__q100 or - CASE_guard48688_0b0_theResult___snd56711_BITS__ETC__q101 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10542 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10544 or - _theResult___snd__h656711) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0: - _theResult___fst_sfd__h657311 = - CASE_guard48688_0b0_theResult___snd56711_BITS__ETC__q100; - 3'd1: - _theResult___fst_sfd__h657311 = - CASE_guard48688_0b0_theResult___snd56711_BITS__ETC__q101; - 3'd2: - _theResult___fst_sfd__h657311 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10542; - 3'd3: - _theResult___fst_sfd__h657311 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10544; - 3'd4: _theResult___fst_sfd__h657311 = _theResult___snd__h656711[56:34]; - default: _theResult___fst_sfd__h657311 = 23'd0; - endcase - end - always@(guard__h622215 or + always@(guard__h622213 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h622215) + case (guard__h622213) 2'b0, 2'b01, 2'b10: - CASE_guard22215_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q102 = + CASE_guard22213_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q100 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard22215_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q102 = - guard__h622215 == 2'b11 && + CASE_guard22213_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q100 = + guard__h622213 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard22215_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q102 or - guard__h622215) + CASE_guard22213_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q100 or + guard__h622213) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10630 = - CASE_guard22215_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q102; + CASE_guard22213_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q100; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10630 = - (guard__h622215 == 2'b0) ? + (guard__h622213 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h622215 == 2'b01 || guard__h622215 == 2'b10 || - guard__h622215 == 2'b11) && + (guard__h622213 == 2'b01 || guard__h622213 == 2'b10 || + guard__h622213 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10630 = @@ -40716,34 +40653,86 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h622215 or + always@(guard__h648686 or + _theResult___snd__h656709 or + out_sfd__h657234 or _theResult___sfd__h657231) + begin + case (guard__h648686) + 2'b0, 2'b01: + CASE_guard48686_0b0_theResult___snd56709_BITS__ETC__q101 = + _theResult___snd__h656709[56:34]; + 2'b10: + CASE_guard48686_0b0_theResult___snd56709_BITS__ETC__q101 = + out_sfd__h657234; + 2'b11: + CASE_guard48686_0b0_theResult___snd56709_BITS__ETC__q101 = + _theResult___sfd__h657231; + endcase + end + always@(guard__h648686 or + _theResult___snd__h656709 or _theResult___sfd__h657231) + begin + case (guard__h648686) + 2'b0: + CASE_guard48686_0b0_theResult___snd56709_BITS__ETC__q102 = + _theResult___snd__h656709[56:34]; + 2'b01, 2'b10, 2'b11: + CASE_guard48686_0b0_theResult___snd56709_BITS__ETC__q102 = + _theResult___sfd__h657231; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or + CASE_guard48686_0b0_theResult___snd56709_BITS__ETC__q101 or + CASE_guard48686_0b0_theResult___snd56709_BITS__ETC__q102 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10542 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10544 or + _theResult___snd__h656709) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) + 3'd0: + _theResult___fst_sfd__h657309 = + CASE_guard48686_0b0_theResult___snd56709_BITS__ETC__q101; + 3'd1: + _theResult___fst_sfd__h657309 = + CASE_guard48686_0b0_theResult___snd56709_BITS__ETC__q102; + 3'd2: + _theResult___fst_sfd__h657309 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10542; + 3'd3: + _theResult___fst_sfd__h657309 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10544; + 3'd4: _theResult___fst_sfd__h657309 = _theResult___snd__h656709[56:34]; + default: _theResult___fst_sfd__h657309 = 23'd0; + endcase + end + always@(guard__h622213 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h622215) + case (guard__h622213) 2'b0, 2'b01, 2'b10: - CASE_guard22215_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q103 = + CASE_guard22213_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q103 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard22215_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q103 = - guard__h622215 != 2'b11 || + CASE_guard22213_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q103 = + guard__h622213 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard22215_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q103 or - guard__h622215) + CASE_guard22213_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q103 or + guard__h622213) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10574 = - CASE_guard22215_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q103; + CASE_guard22213_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q103; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10574 = - (guard__h622215 == 2'b0) ? + (guard__h622213 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h622215 != 2'b01 && guard__h622215 != 2'b10 && - guard__h622215 != 2'b11 || + guard__h622213 != 2'b01 && guard__h622213 != 2'b10 && + guard__h622213 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10574 = @@ -40754,34 +40743,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h630922 or + always@(guard__h630920 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h630922) + case (guard__h630920) 2'b0, 2'b01, 2'b10: - CASE_guard30922_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q104 = + CASE_guard30920_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q104 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard30922_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q104 = - guard__h630922 == 2'b11 && + CASE_guard30920_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q104 = + guard__h630920 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard30922_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q104 or - guard__h630922) + CASE_guard30920_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q104 or + guard__h630920) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10637 = - CASE_guard30922_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q104; + CASE_guard30920_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q104; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10637 = - (guard__h630922 == 2'b0) ? + (guard__h630920 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h630922 == 2'b01 || guard__h630922 == 2'b10 || - guard__h630922 == 2'b11) && + (guard__h630920 == 2'b01 || guard__h630920 == 2'b10 || + guard__h630920 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10637 = @@ -40792,34 +40781,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h630922 or + always@(guard__h630920 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h630922) + case (guard__h630920) 2'b0, 2'b01, 2'b10: - CASE_guard30922_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q105 = + CASE_guard30920_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q105 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard30922_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q105 = - guard__h630922 != 2'b11 || + CASE_guard30920_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q105 = + guard__h630920 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard30922_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q105 or - guard__h630922) + CASE_guard30920_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q105 or + guard__h630920) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10587 = - CASE_guard30922_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q105; + CASE_guard30920_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q105; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10587 = - (guard__h630922 == 2'b0) ? + (guard__h630920 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h630922 != 2'b01 && guard__h630922 != 2'b10 && - guard__h630922 != 2'b11 || + guard__h630920 != 2'b01 && guard__h630920 != 2'b10 && + guard__h630920 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10587 = @@ -40830,34 +40819,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h639852 or + always@(guard__h639850 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h639852) + case (guard__h639850) 2'b0, 2'b01, 2'b10: - CASE_guard39852_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q106 = + CASE_guard39850_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q106 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard39852_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q106 = - guard__h639852 == 2'b11 && + CASE_guard39850_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q106 = + guard__h639850 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard39852_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q106 or - guard__h639852) + CASE_guard39850_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q106 or + guard__h639850) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10647 = - CASE_guard39852_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q106; + CASE_guard39850_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q106; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10647 = - (guard__h639852 == 2'b0) ? + (guard__h639850 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h639852 == 2'b01 || guard__h639852 == 2'b10 || - guard__h639852 == 2'b11) && + (guard__h639850 == 2'b01 || guard__h639850 == 2'b10 || + guard__h639850 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10647 = @@ -40868,34 +40857,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h639852 or + always@(guard__h639850 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h639852) + case (guard__h639850) 2'b0, 2'b01, 2'b10: - CASE_guard39852_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q107 = + CASE_guard39850_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q107 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard39852_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q107 = - guard__h639852 != 2'b11 || + CASE_guard39850_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q107 = + guard__h639850 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard39852_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q107 or - guard__h639852) + CASE_guard39850_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q107 or + guard__h639850) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10604 = - CASE_guard39852_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q107; + CASE_guard39850_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q107; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10604 = - (guard__h639852 == 2'b0) ? + (guard__h639850 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h639852 != 2'b01 && guard__h639852 != 2'b10 && - guard__h639852 != 2'b11 || + guard__h639850 != 2'b01 && guard__h639850 != 2'b10 && + guard__h639850 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10604 = @@ -40906,34 +40895,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h648688 or + always@(guard__h648686 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h648688) + case (guard__h648686) 2'b0, 2'b01, 2'b10: - CASE_guard48688_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q108 = + CASE_guard48686_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q108 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard48688_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q108 = - guard__h648688 == 2'b11 && + CASE_guard48686_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q108 = + guard__h648686 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard48688_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q108 or - guard__h648688) + CASE_guard48686_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q108 or + guard__h648686) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10654 = - CASE_guard48688_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q108; + CASE_guard48686_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q108; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10654 = - (guard__h648688 == 2'b0) ? + (guard__h648686 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h648688 == 2'b01 || guard__h648688 == 2'b10 || - guard__h648688 == 2'b11) && + (guard__h648686 == 2'b01 || guard__h648686 == 2'b10 || + guard__h648686 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10654 = @@ -40944,34 +40933,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h648688 or + always@(guard__h648686 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h648688) + case (guard__h648686) 2'b0, 2'b01, 2'b10: - CASE_guard48688_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q109 = + CASE_guard48686_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q109 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard48688_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q109 = - guard__h648688 != 2'b11 || + CASE_guard48686_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q109 = + guard__h648686 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard48688_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q109 or - guard__h648688) + CASE_guard48686_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q109 or + guard__h648686) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10617 = - CASE_guard48688_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q109; + CASE_guard48686_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q109; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10617 = - (guard__h648688 == 2'b0) ? + (guard__h648686 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h648688 != 2'b01 && guard__h648688 != 2'b10 && - guard__h648688 != 2'b11 || + guard__h648686 != 2'b01 && guard__h648686 != 2'b10 && + guard__h648686 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10617 = @@ -41008,446 +40997,446 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h676669 or - _theResult___fst_exp__h684717 or - out_exp__h685162 or _theResult___exp__h685159) + always@(guard__h676667 or + _theResult___fst_exp__h684715 or + out_exp__h685160 or _theResult___exp__h685157) begin - case (guard__h676669) + case (guard__h676667) 2'b0, 2'b01: - CASE_guard76669_0b0_theResult___fst_exp84717_0_ETC__q114 = - _theResult___fst_exp__h684717; + CASE_guard76667_0b0_theResult___fst_exp84715_0_ETC__q114 = + _theResult___fst_exp__h684715; 2'b10: - CASE_guard76669_0b0_theResult___fst_exp84717_0_ETC__q114 = - out_exp__h685162; + CASE_guard76667_0b0_theResult___fst_exp84715_0_ETC__q114 = + out_exp__h685160; 2'b11: - CASE_guard76669_0b0_theResult___fst_exp84717_0_ETC__q114 = - _theResult___exp__h685159; + CASE_guard76667_0b0_theResult___fst_exp84715_0_ETC__q114 = + _theResult___exp__h685157; endcase end - always@(guard__h676669 or - _theResult___fst_exp__h684717 or _theResult___exp__h685159) + always@(guard__h676667 or + _theResult___fst_exp__h684715 or _theResult___exp__h685157) begin - case (guard__h676669) + case (guard__h676667) 2'b0: - CASE_guard76669_0b0_theResult___fst_exp84717_0_ETC__q115 = - _theResult___fst_exp__h684717; + CASE_guard76667_0b0_theResult___fst_exp84715_0_ETC__q115 = + _theResult___fst_exp__h684715; 2'b01, 2'b10, 2'b11: - CASE_guard76669_0b0_theResult___fst_exp84717_0_ETC__q115 = - _theResult___exp__h685159; + CASE_guard76667_0b0_theResult___fst_exp84715_0_ETC__q115 = + _theResult___exp__h685157; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard76669_0b0_theResult___fst_exp84717_0_ETC__q114 or - CASE_guard76669_0b0_theResult___fst_exp84717_0_ETC__q115 or + CASE_guard76667_0b0_theResult___fst_exp84715_0_ETC__q114 or + CASE_guard76667_0b0_theResult___fst_exp84715_0_ETC__q115 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11449 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11451 or - _theResult___fst_exp__h684717) + _theResult___fst_exp__h684715) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h685237 = - CASE_guard76669_0b0_theResult___fst_exp84717_0_ETC__q114; + _theResult___fst_exp__h685235 = + CASE_guard76667_0b0_theResult___fst_exp84715_0_ETC__q114; 3'd1: - _theResult___fst_exp__h685237 = - CASE_guard76669_0b0_theResult___fst_exp84717_0_ETC__q115; + _theResult___fst_exp__h685235 = + CASE_guard76667_0b0_theResult___fst_exp84715_0_ETC__q115; 3'd2: - _theResult___fst_exp__h685237 = + _theResult___fst_exp__h685235 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11449; 3'd3: - _theResult___fst_exp__h685237 = + _theResult___fst_exp__h685235 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11451; - 3'd4: _theResult___fst_exp__h685237 = _theResult___fst_exp__h684717; - default: _theResult___fst_exp__h685237 = 8'd0; + 3'd4: _theResult___fst_exp__h685235 = _theResult___fst_exp__h684715; + default: _theResult___fst_exp__h685235 = 8'd0; endcase end - always@(guard__h667962 or - _theResult___fst_exp__h676061 or - out_exp__h676580 or _theResult___exp__h676577) + always@(guard__h667960 or + _theResult___fst_exp__h676059 or + out_exp__h676578 or _theResult___exp__h676575) begin - case (guard__h667962) + case (guard__h667960) 2'b0, 2'b01: - CASE_guard67962_0b0_theResult___fst_exp76061_0_ETC__q116 = - _theResult___fst_exp__h676061; + CASE_guard67960_0b0_theResult___fst_exp76059_0_ETC__q116 = + _theResult___fst_exp__h676059; 2'b10: - CASE_guard67962_0b0_theResult___fst_exp76061_0_ETC__q116 = - out_exp__h676580; + CASE_guard67960_0b0_theResult___fst_exp76059_0_ETC__q116 = + out_exp__h676578; 2'b11: - CASE_guard67962_0b0_theResult___fst_exp76061_0_ETC__q116 = - _theResult___exp__h676577; + CASE_guard67960_0b0_theResult___fst_exp76059_0_ETC__q116 = + _theResult___exp__h676575; endcase end - always@(guard__h667962 or - _theResult___fst_exp__h676061 or _theResult___exp__h676577) + always@(guard__h667960 or + _theResult___fst_exp__h676059 or _theResult___exp__h676575) begin - case (guard__h667962) + case (guard__h667960) 2'b0: - CASE_guard67962_0b0_theResult___fst_exp76061_0_ETC__q117 = - _theResult___fst_exp__h676061; + CASE_guard67960_0b0_theResult___fst_exp76059_0_ETC__q117 = + _theResult___fst_exp__h676059; 2'b01, 2'b10, 2'b11: - CASE_guard67962_0b0_theResult___fst_exp76061_0_ETC__q117 = - _theResult___exp__h676577; + CASE_guard67960_0b0_theResult___fst_exp76059_0_ETC__q117 = + _theResult___exp__h676575; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard67962_0b0_theResult___fst_exp76061_0_ETC__q116 or - CASE_guard67962_0b0_theResult___fst_exp76061_0_ETC__q117 or + CASE_guard67960_0b0_theResult___fst_exp76059_0_ETC__q116 or + CASE_guard67960_0b0_theResult___fst_exp76059_0_ETC__q117 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11227 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11230 or - _theResult___fst_exp__h676061) + _theResult___fst_exp__h676059) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h676655 = - CASE_guard67962_0b0_theResult___fst_exp76061_0_ETC__q116; + _theResult___fst_exp__h676653 = + CASE_guard67960_0b0_theResult___fst_exp76059_0_ETC__q116; 3'd1: - _theResult___fst_exp__h676655 = - CASE_guard67962_0b0_theResult___fst_exp76061_0_ETC__q117; + _theResult___fst_exp__h676653 = + CASE_guard67960_0b0_theResult___fst_exp76059_0_ETC__q117; 3'd2: - _theResult___fst_exp__h676655 = + _theResult___fst_exp__h676653 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11227; 3'd3: - _theResult___fst_exp__h676655 = + _theResult___fst_exp__h676653 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11230; - 3'd4: _theResult___fst_exp__h676655 = _theResult___fst_exp__h676061; - default: _theResult___fst_exp__h676655 = 8'd0; + 3'd4: _theResult___fst_exp__h676653 = _theResult___fst_exp__h676059; + default: _theResult___fst_exp__h676653 = 8'd0; endcase end - always@(guard__h685599 or - _theResult___fst_exp__h693827 or - out_exp__h694346 or _theResult___exp__h694343) + always@(guard__h685597 or + _theResult___fst_exp__h693825 or + out_exp__h694344 or _theResult___exp__h694341) begin - case (guard__h685599) + case (guard__h685597) 2'b0, 2'b01: - CASE_guard85599_0b0_theResult___fst_exp93827_0_ETC__q122 = - _theResult___fst_exp__h693827; + CASE_guard85597_0b0_theResult___fst_exp93825_0_ETC__q122 = + _theResult___fst_exp__h693825; 2'b10: - CASE_guard85599_0b0_theResult___fst_exp93827_0_ETC__q122 = - out_exp__h694346; + CASE_guard85597_0b0_theResult___fst_exp93825_0_ETC__q122 = + out_exp__h694344; 2'b11: - CASE_guard85599_0b0_theResult___fst_exp93827_0_ETC__q122 = - _theResult___exp__h694343; + CASE_guard85597_0b0_theResult___fst_exp93825_0_ETC__q122 = + _theResult___exp__h694341; endcase end - always@(guard__h685599 or - _theResult___fst_exp__h693827 or _theResult___exp__h694343) + always@(guard__h685597 or + _theResult___fst_exp__h693825 or _theResult___exp__h694341) begin - case (guard__h685599) + case (guard__h685597) 2'b0: - CASE_guard85599_0b0_theResult___fst_exp93827_0_ETC__q123 = - _theResult___fst_exp__h693827; + CASE_guard85597_0b0_theResult___fst_exp93825_0_ETC__q123 = + _theResult___fst_exp__h693825; 2'b01, 2'b10, 2'b11: - CASE_guard85599_0b0_theResult___fst_exp93827_0_ETC__q123 = - _theResult___exp__h694343; + CASE_guard85597_0b0_theResult___fst_exp93825_0_ETC__q123 = + _theResult___exp__h694341; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard85599_0b0_theResult___fst_exp93827_0_ETC__q122 or - CASE_guard85599_0b0_theResult___fst_exp93827_0_ETC__q123 or + CASE_guard85597_0b0_theResult___fst_exp93825_0_ETC__q122 or + CASE_guard85597_0b0_theResult___fst_exp93825_0_ETC__q123 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11774 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11776 or - _theResult___fst_exp__h693827) + _theResult___fst_exp__h693825) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h694421 = - CASE_guard85599_0b0_theResult___fst_exp93827_0_ETC__q122; + _theResult___fst_exp__h694419 = + CASE_guard85597_0b0_theResult___fst_exp93825_0_ETC__q122; 3'd1: - _theResult___fst_exp__h694421 = - CASE_guard85599_0b0_theResult___fst_exp93827_0_ETC__q123; + _theResult___fst_exp__h694419 = + CASE_guard85597_0b0_theResult___fst_exp93825_0_ETC__q123; 3'd2: - _theResult___fst_exp__h694421 = + _theResult___fst_exp__h694419 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11774; 3'd3: - _theResult___fst_exp__h694421 = + _theResult___fst_exp__h694419 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11776; - 3'd4: _theResult___fst_exp__h694421 = _theResult___fst_exp__h693827; - default: _theResult___fst_exp__h694421 = 8'd0; + 3'd4: _theResult___fst_exp__h694419 = _theResult___fst_exp__h693825; + default: _theResult___fst_exp__h694419 = 8'd0; endcase end - always@(guard__h694435 or - _theResult___fst_exp__h702512 or - out_exp__h702982 or _theResult___exp__h702979) + always@(guard__h694433 or + _theResult___fst_exp__h702510 or + out_exp__h702980 or _theResult___exp__h702977) begin - case (guard__h694435) + case (guard__h694433) 2'b0, 2'b01: - CASE_guard94435_0b0_theResult___fst_exp02512_0_ETC__q127 = - _theResult___fst_exp__h702512; + CASE_guard94433_0b0_theResult___fst_exp02510_0_ETC__q127 = + _theResult___fst_exp__h702510; 2'b10: - CASE_guard94435_0b0_theResult___fst_exp02512_0_ETC__q127 = - out_exp__h702982; + CASE_guard94433_0b0_theResult___fst_exp02510_0_ETC__q127 = + out_exp__h702980; 2'b11: - CASE_guard94435_0b0_theResult___fst_exp02512_0_ETC__q127 = - _theResult___exp__h702979; + CASE_guard94433_0b0_theResult___fst_exp02510_0_ETC__q127 = + _theResult___exp__h702977; endcase end - always@(guard__h694435 or - _theResult___fst_exp__h702512 or _theResult___exp__h702979) + always@(guard__h694433 or + _theResult___fst_exp__h702510 or _theResult___exp__h702977) begin - case (guard__h694435) + case (guard__h694433) 2'b0: - CASE_guard94435_0b0_theResult___fst_exp02512_0_ETC__q128 = - _theResult___fst_exp__h702512; + CASE_guard94433_0b0_theResult___fst_exp02510_0_ETC__q128 = + _theResult___fst_exp__h702510; 2'b01, 2'b10, 2'b11: - CASE_guard94435_0b0_theResult___fst_exp02512_0_ETC__q128 = - _theResult___exp__h702979; + CASE_guard94433_0b0_theResult___fst_exp02510_0_ETC__q128 = + _theResult___exp__h702977; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard94435_0b0_theResult___fst_exp02512_0_ETC__q127 or - CASE_guard94435_0b0_theResult___fst_exp02512_0_ETC__q128 or + CASE_guard94433_0b0_theResult___fst_exp02510_0_ETC__q127 or + CASE_guard94433_0b0_theResult___fst_exp02510_0_ETC__q128 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11843 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11845 or - _theResult___fst_exp__h702512) + _theResult___fst_exp__h702510) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h703057 = - CASE_guard94435_0b0_theResult___fst_exp02512_0_ETC__q127; + _theResult___fst_exp__h703055 = + CASE_guard94433_0b0_theResult___fst_exp02510_0_ETC__q127; 3'd1: - _theResult___fst_exp__h703057 = - CASE_guard94435_0b0_theResult___fst_exp02512_0_ETC__q128; + _theResult___fst_exp__h703055 = + CASE_guard94433_0b0_theResult___fst_exp02510_0_ETC__q128; 3'd2: - _theResult___fst_exp__h703057 = + _theResult___fst_exp__h703055 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11843; 3'd3: - _theResult___fst_exp__h703057 = + _theResult___fst_exp__h703055 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11845; - 3'd4: _theResult___fst_exp__h703057 = _theResult___fst_exp__h702512; - default: _theResult___fst_exp__h703057 = 8'd0; + 3'd4: _theResult___fst_exp__h703055 = _theResult___fst_exp__h702510; + default: _theResult___fst_exp__h703055 = 8'd0; endcase end - always@(guard__h667962 or - sfdin__h676055 or out_sfd__h676581 or _theResult___sfd__h676578) + always@(guard__h676667 or + _theResult___snd__h684666 or + out_sfd__h685161 or _theResult___sfd__h685158) begin - case (guard__h667962) + case (guard__h676667) 2'b0, 2'b01: - CASE_guard67962_0b0_sfdin76055_BITS_56_TO_34_0_ETC__q129 = - sfdin__h676055[56:34]; + CASE_guard76667_0b0_theResult___snd84666_BITS__ETC__q129 = + _theResult___snd__h684666[56:34]; 2'b10: - CASE_guard67962_0b0_sfdin76055_BITS_56_TO_34_0_ETC__q129 = - out_sfd__h676581; + CASE_guard76667_0b0_theResult___snd84666_BITS__ETC__q129 = + out_sfd__h685161; 2'b11: - CASE_guard67962_0b0_sfdin76055_BITS_56_TO_34_0_ETC__q129 = - _theResult___sfd__h676578; + CASE_guard76667_0b0_theResult___snd84666_BITS__ETC__q129 = + _theResult___sfd__h685158; endcase end - always@(guard__h667962 or sfdin__h676055 or _theResult___sfd__h676578) + always@(guard__h676667 or + _theResult___snd__h684666 or _theResult___sfd__h685158) begin - case (guard__h667962) + case (guard__h676667) 2'b0: - CASE_guard67962_0b0_sfdin76055_BITS_56_TO_34_0_ETC__q130 = - sfdin__h676055[56:34]; + CASE_guard76667_0b0_theResult___snd84666_BITS__ETC__q130 = + _theResult___snd__h684666[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard67962_0b0_sfdin76055_BITS_56_TO_34_0_ETC__q130 = - _theResult___sfd__h676578; + CASE_guard76667_0b0_theResult___snd84666_BITS__ETC__q130 = + _theResult___sfd__h685158; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard67962_0b0_sfdin76055_BITS_56_TO_34_0_ETC__q129 or - CASE_guard67962_0b0_sfdin76055_BITS_56_TO_34_0_ETC__q130 or - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11874 or - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11876 or - sfdin__h676055) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0: - _theResult___fst_sfd__h676656 = - CASE_guard67962_0b0_sfdin76055_BITS_56_TO_34_0_ETC__q129; - 3'd1: - _theResult___fst_sfd__h676656 = - CASE_guard67962_0b0_sfdin76055_BITS_56_TO_34_0_ETC__q130; - 3'd2: - _theResult___fst_sfd__h676656 = - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11874; - 3'd3: - _theResult___fst_sfd__h676656 = - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11876; - 3'd4: _theResult___fst_sfd__h676656 = sfdin__h676055[56:34]; - default: _theResult___fst_sfd__h676656 = 23'd0; - endcase - end - always@(guard__h676669 or - _theResult___snd__h684668 or - out_sfd__h685163 or _theResult___sfd__h685160) - begin - case (guard__h676669) - 2'b0, 2'b01: - CASE_guard76669_0b0_theResult___snd84668_BITS__ETC__q131 = - _theResult___snd__h684668[56:34]; - 2'b10: - CASE_guard76669_0b0_theResult___snd84668_BITS__ETC__q131 = - out_sfd__h685163; - 2'b11: - CASE_guard76669_0b0_theResult___snd84668_BITS__ETC__q131 = - _theResult___sfd__h685160; - endcase - end - always@(guard__h676669 or - _theResult___snd__h684668 or _theResult___sfd__h685160) - begin - case (guard__h676669) - 2'b0: - CASE_guard76669_0b0_theResult___snd84668_BITS__ETC__q132 = - _theResult___snd__h684668[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard76669_0b0_theResult___snd84668_BITS__ETC__q132 = - _theResult___sfd__h685160; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard76669_0b0_theResult___snd84668_BITS__ETC__q131 or - CASE_guard76669_0b0_theResult___snd84668_BITS__ETC__q132 or + CASE_guard76667_0b0_theResult___snd84666_BITS__ETC__q129 or + CASE_guard76667_0b0_theResult___snd84666_BITS__ETC__q130 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11893 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11895 or - _theResult___snd__h684668) + _theResult___snd__h684666) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h685238 = - CASE_guard76669_0b0_theResult___snd84668_BITS__ETC__q131; + _theResult___fst_sfd__h685236 = + CASE_guard76667_0b0_theResult___snd84666_BITS__ETC__q129; 3'd1: - _theResult___fst_sfd__h685238 = - CASE_guard76669_0b0_theResult___snd84668_BITS__ETC__q132; + _theResult___fst_sfd__h685236 = + CASE_guard76667_0b0_theResult___snd84666_BITS__ETC__q130; 3'd2: - _theResult___fst_sfd__h685238 = + _theResult___fst_sfd__h685236 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11893; 3'd3: - _theResult___fst_sfd__h685238 = + _theResult___fst_sfd__h685236 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11895; - 3'd4: _theResult___fst_sfd__h685238 = _theResult___snd__h684668[56:34]; - default: _theResult___fst_sfd__h685238 = 23'd0; + 3'd4: _theResult___fst_sfd__h685236 = _theResult___snd__h684666[56:34]; + default: _theResult___fst_sfd__h685236 = 23'd0; endcase end - always@(guard__h685599 or - sfdin__h693821 or out_sfd__h694347 or _theResult___sfd__h694344) + always@(guard__h667960 or + sfdin__h676053 or out_sfd__h676579 or _theResult___sfd__h676576) begin - case (guard__h685599) + case (guard__h667960) 2'b0, 2'b01: - CASE_guard85599_0b0_sfdin93821_BITS_56_TO_34_0_ETC__q133 = - sfdin__h693821[56:34]; + CASE_guard67960_0b0_sfdin76053_BITS_56_TO_34_0_ETC__q131 = + sfdin__h676053[56:34]; 2'b10: - CASE_guard85599_0b0_sfdin93821_BITS_56_TO_34_0_ETC__q133 = - out_sfd__h694347; + CASE_guard67960_0b0_sfdin76053_BITS_56_TO_34_0_ETC__q131 = + out_sfd__h676579; 2'b11: - CASE_guard85599_0b0_sfdin93821_BITS_56_TO_34_0_ETC__q133 = - _theResult___sfd__h694344; + CASE_guard67960_0b0_sfdin76053_BITS_56_TO_34_0_ETC__q131 = + _theResult___sfd__h676576; endcase end - always@(guard__h685599 or sfdin__h693821 or _theResult___sfd__h694344) + always@(guard__h667960 or sfdin__h676053 or _theResult___sfd__h676576) begin - case (guard__h685599) + case (guard__h667960) 2'b0: - CASE_guard85599_0b0_sfdin93821_BITS_56_TO_34_0_ETC__q134 = - sfdin__h693821[56:34]; + CASE_guard67960_0b0_sfdin76053_BITS_56_TO_34_0_ETC__q132 = + sfdin__h676053[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard85599_0b0_sfdin93821_BITS_56_TO_34_0_ETC__q134 = - _theResult___sfd__h694344; + CASE_guard67960_0b0_sfdin76053_BITS_56_TO_34_0_ETC__q132 = + _theResult___sfd__h676576; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard85599_0b0_sfdin93821_BITS_56_TO_34_0_ETC__q133 or - CASE_guard85599_0b0_sfdin93821_BITS_56_TO_34_0_ETC__q134 or + CASE_guard67960_0b0_sfdin76053_BITS_56_TO_34_0_ETC__q131 or + CASE_guard67960_0b0_sfdin76053_BITS_56_TO_34_0_ETC__q132 or + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11874 or + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11876 or + sfdin__h676053) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) + 3'd0: + _theResult___fst_sfd__h676654 = + CASE_guard67960_0b0_sfdin76053_BITS_56_TO_34_0_ETC__q131; + 3'd1: + _theResult___fst_sfd__h676654 = + CASE_guard67960_0b0_sfdin76053_BITS_56_TO_34_0_ETC__q132; + 3'd2: + _theResult___fst_sfd__h676654 = + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11874; + 3'd3: + _theResult___fst_sfd__h676654 = + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11876; + 3'd4: _theResult___fst_sfd__h676654 = sfdin__h676053[56:34]; + default: _theResult___fst_sfd__h676654 = 23'd0; + endcase + end + always@(guard__h685597 or + sfdin__h693819 or out_sfd__h694345 or _theResult___sfd__h694342) + begin + case (guard__h685597) + 2'b0, 2'b01: + CASE_guard85597_0b0_sfdin93819_BITS_56_TO_34_0_ETC__q133 = + sfdin__h693819[56:34]; + 2'b10: + CASE_guard85597_0b0_sfdin93819_BITS_56_TO_34_0_ETC__q133 = + out_sfd__h694345; + 2'b11: + CASE_guard85597_0b0_sfdin93819_BITS_56_TO_34_0_ETC__q133 = + _theResult___sfd__h694342; + endcase + end + always@(guard__h685597 or sfdin__h693819 or _theResult___sfd__h694342) + begin + case (guard__h685597) + 2'b0: + CASE_guard85597_0b0_sfdin93819_BITS_56_TO_34_0_ETC__q134 = + sfdin__h693819[56:34]; + 2'b01, 2'b10, 2'b11: + CASE_guard85597_0b0_sfdin93819_BITS_56_TO_34_0_ETC__q134 = + _theResult___sfd__h694342; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or + CASE_guard85597_0b0_sfdin93819_BITS_56_TO_34_0_ETC__q133 or + CASE_guard85597_0b0_sfdin93819_BITS_56_TO_34_0_ETC__q134 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11920 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11922 or - sfdin__h693821) + sfdin__h693819) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h694422 = - CASE_guard85599_0b0_sfdin93821_BITS_56_TO_34_0_ETC__q133; + _theResult___fst_sfd__h694420 = + CASE_guard85597_0b0_sfdin93819_BITS_56_TO_34_0_ETC__q133; 3'd1: - _theResult___fst_sfd__h694422 = - CASE_guard85599_0b0_sfdin93821_BITS_56_TO_34_0_ETC__q134; + _theResult___fst_sfd__h694420 = + CASE_guard85597_0b0_sfdin93819_BITS_56_TO_34_0_ETC__q134; 3'd2: - _theResult___fst_sfd__h694422 = + _theResult___fst_sfd__h694420 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11920; 3'd3: - _theResult___fst_sfd__h694422 = + _theResult___fst_sfd__h694420 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11922; - 3'd4: _theResult___fst_sfd__h694422 = sfdin__h693821[56:34]; - default: _theResult___fst_sfd__h694422 = 23'd0; + 3'd4: _theResult___fst_sfd__h694420 = sfdin__h693819[56:34]; + default: _theResult___fst_sfd__h694420 = 23'd0; endcase end - always@(guard__h694435 or - _theResult___snd__h702458 or - out_sfd__h702983 or _theResult___sfd__h702980) + always@(guard__h694433 or + _theResult___snd__h702456 or + out_sfd__h702981 or _theResult___sfd__h702978) begin - case (guard__h694435) + case (guard__h694433) 2'b0, 2'b01: - CASE_guard94435_0b0_theResult___snd02458_BITS__ETC__q135 = - _theResult___snd__h702458[56:34]; + CASE_guard94433_0b0_theResult___snd02456_BITS__ETC__q135 = + _theResult___snd__h702456[56:34]; 2'b10: - CASE_guard94435_0b0_theResult___snd02458_BITS__ETC__q135 = - out_sfd__h702983; + CASE_guard94433_0b0_theResult___snd02456_BITS__ETC__q135 = + out_sfd__h702981; 2'b11: - CASE_guard94435_0b0_theResult___snd02458_BITS__ETC__q135 = - _theResult___sfd__h702980; + CASE_guard94433_0b0_theResult___snd02456_BITS__ETC__q135 = + _theResult___sfd__h702978; endcase end - always@(guard__h694435 or - _theResult___snd__h702458 or _theResult___sfd__h702980) + always@(guard__h694433 or + _theResult___snd__h702456 or _theResult___sfd__h702978) begin - case (guard__h694435) + case (guard__h694433) 2'b0: - CASE_guard94435_0b0_theResult___snd02458_BITS__ETC__q136 = - _theResult___snd__h702458[56:34]; + CASE_guard94433_0b0_theResult___snd02456_BITS__ETC__q136 = + _theResult___snd__h702456[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard94435_0b0_theResult___snd02458_BITS__ETC__q136 = - _theResult___sfd__h702980; + CASE_guard94433_0b0_theResult___snd02456_BITS__ETC__q136 = + _theResult___sfd__h702978; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard94435_0b0_theResult___snd02458_BITS__ETC__q135 or - CASE_guard94435_0b0_theResult___snd02458_BITS__ETC__q136 or + CASE_guard94433_0b0_theResult___snd02456_BITS__ETC__q135 or + CASE_guard94433_0b0_theResult___snd02456_BITS__ETC__q136 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11939 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11941 or - _theResult___snd__h702458) + _theResult___snd__h702456) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h703058 = - CASE_guard94435_0b0_theResult___snd02458_BITS__ETC__q135; + _theResult___fst_sfd__h703056 = + CASE_guard94433_0b0_theResult___snd02456_BITS__ETC__q135; 3'd1: - _theResult___fst_sfd__h703058 = - CASE_guard94435_0b0_theResult___snd02458_BITS__ETC__q136; + _theResult___fst_sfd__h703056 = + CASE_guard94433_0b0_theResult___snd02456_BITS__ETC__q136; 3'd2: - _theResult___fst_sfd__h703058 = + _theResult___fst_sfd__h703056 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11939; 3'd3: - _theResult___fst_sfd__h703058 = + _theResult___fst_sfd__h703056 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11941; - 3'd4: _theResult___fst_sfd__h703058 = _theResult___snd__h702458[56:34]; - default: _theResult___fst_sfd__h703058 = 23'd0; + 3'd4: _theResult___fst_sfd__h703056 = _theResult___snd__h702456[56:34]; + default: _theResult___fst_sfd__h703056 = 23'd0; endcase end - always@(guard__h667962 or + always@(guard__h667960 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h667962) + case (guard__h667960) 2'b0, 2'b01, 2'b10: - CASE_guard67962_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q137 = + CASE_guard67960_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q137 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard67962_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q137 = - guard__h667962 == 2'b11 && + CASE_guard67960_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q137 = + guard__h667960 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard67962_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q137 or - guard__h667962) + CASE_guard67960_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q137 or + guard__h667960) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12027 = - CASE_guard67962_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q137; + CASE_guard67960_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q137; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12027 = - (guard__h667962 == 2'b0) ? + (guard__h667960 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h667962 == 2'b01 || guard__h667962 == 2'b10 || - guard__h667962 == 2'b11) && + (guard__h667960 == 2'b01 || guard__h667960 == 2'b10 || + guard__h667960 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12027 = @@ -41458,72 +41447,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h676669 or + always@(guard__h667960 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h676669) + case (guard__h667960) 2'b0, 2'b01, 2'b10: - CASE_guard76669_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q138 = - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - 2'd3: - CASE_guard76669_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q138 = - guard__h676669 == 2'b11 && - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard76669_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q138 or - guard__h676669) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12034 = - CASE_guard76669_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q138; - 3'd1: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12034 = - (guard__h676669 == 2'b0) ? - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h676669 == 2'b01 || guard__h676669 == 2'b10 || - guard__h676669 == 2'b11) && - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12034 = - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12034 = - coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] == - 3'd4 && - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - endcase - end - always@(guard__h667962 or - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) - begin - case (guard__h667962) - 2'b0, 2'b01, 2'b10: - CASE_guard67962_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q139 = + CASE_guard67960_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q138 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard67962_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q139 = - guard__h667962 != 2'b11 || + CASE_guard67960_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q138 = + guard__h667960 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard67962_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q139 or - guard__h667962) + CASE_guard67960_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q138 or + guard__h667960) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11971 = - CASE_guard67962_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q139; + CASE_guard67960_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q138; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11971 = - (guard__h667962 == 2'b0) ? + (guard__h667960 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h667962 != 2'b01 && guard__h667962 != 2'b10 && - guard__h667962 != 2'b11 || + guard__h667960 != 2'b01 && guard__h667960 != 2'b10 && + guard__h667960 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11971 = @@ -41534,34 +41485,72 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h676669 or + always@(guard__h676667 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h676669) + case (guard__h676667) 2'b0, 2'b01, 2'b10: - CASE_guard76669_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q140 = + CASE_guard76667_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q139 = + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + 2'd3: + CASE_guard76667_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q139 = + guard__h676667 == 2'b11 && + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or + CASE_guard76667_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q139 or + guard__h676667) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) + 3'd0: + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12034 = + CASE_guard76667_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q139; + 3'd1: + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12034 = + (guard__h676667 == 2'b0) ? + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : + (guard__h676667 == 2'b01 || guard__h676667 == 2'b10 || + guard__h676667 == 2'b11) && + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + 3'd2, 3'd3: + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12034 = + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12034 = + coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] == + 3'd4 && + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + endcase + end + always@(guard__h676667 or + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) + begin + case (guard__h676667) + 2'b0, 2'b01, 2'b10: + CASE_guard76667_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q140 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard76669_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q140 = - guard__h676669 != 2'b11 || + CASE_guard76667_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q140 = + guard__h676667 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard76669_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q140 or - guard__h676669) + CASE_guard76667_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q140 or + guard__h676667) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11984 = - CASE_guard76669_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q140; + CASE_guard76667_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q140; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11984 = - (guard__h676669 == 2'b0) ? + (guard__h676667 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h676669 != 2'b01 && guard__h676669 != 2'b10 && - guard__h676669 != 2'b11 || + guard__h676667 != 2'b01 && guard__h676667 != 2'b10 && + guard__h676667 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11984 = @@ -41572,34 +41561,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h685599 or + always@(guard__h685597 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h685599) + case (guard__h685597) 2'b0, 2'b01, 2'b10: - CASE_guard85599_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q141 = + CASE_guard85597_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q141 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard85599_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q141 = - guard__h685599 == 2'b11 && + CASE_guard85597_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q141 = + guard__h685597 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard85599_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q141 or - guard__h685599) + CASE_guard85597_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q141 or + guard__h685597) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12044 = - CASE_guard85599_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q141; + CASE_guard85597_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q141; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12044 = - (guard__h685599 == 2'b0) ? + (guard__h685597 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h685599 == 2'b01 || guard__h685599 == 2'b10 || - guard__h685599 == 2'b11) && + (guard__h685597 == 2'b01 || guard__h685597 == 2'b10 || + guard__h685597 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12044 = @@ -41610,34 +41599,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h685599 or + always@(guard__h685597 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h685599) + case (guard__h685597) 2'b0, 2'b01, 2'b10: - CASE_guard85599_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q142 = + CASE_guard85597_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q142 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard85599_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q142 = - guard__h685599 != 2'b11 || + CASE_guard85597_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q142 = + guard__h685597 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard85599_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q142 or - guard__h685599) + CASE_guard85597_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q142 or + guard__h685597) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12001 = - CASE_guard85599_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q142; + CASE_guard85597_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q142; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12001 = - (guard__h685599 == 2'b0) ? + (guard__h685597 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h685599 != 2'b01 && guard__h685599 != 2'b10 && - guard__h685599 != 2'b11 || + guard__h685597 != 2'b01 && guard__h685597 != 2'b10 && + guard__h685597 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12001 = @@ -41648,34 +41637,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h694435 or + always@(guard__h694433 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h694435) + case (guard__h694433) 2'b0, 2'b01, 2'b10: - CASE_guard94435_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q143 = + CASE_guard94433_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q143 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard94435_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q143 = - guard__h694435 == 2'b11 && + CASE_guard94433_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q143 = + guard__h694433 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard94435_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q143 or - guard__h694435) + CASE_guard94433_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q143 or + guard__h694433) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12051 = - CASE_guard94435_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q143; + CASE_guard94433_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q143; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12051 = - (guard__h694435 == 2'b0) ? + (guard__h694433 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h694435 == 2'b01 || guard__h694435 == 2'b10 || - guard__h694435 == 2'b11) && + (guard__h694433 == 2'b01 || guard__h694433 == 2'b10 || + guard__h694433 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12051 = @@ -41686,34 +41675,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h694435 or + always@(guard__h694433 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h694435) + case (guard__h694433) 2'b0, 2'b01, 2'b10: - CASE_guard94435_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q144 = + CASE_guard94433_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q144 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard94435_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q144 = - guard__h694435 != 2'b11 || + CASE_guard94433_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q144 = + guard__h694433 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard94435_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q144 or - guard__h694435) + CASE_guard94433_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q144 or + guard__h694433) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12014 = - CASE_guard94435_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q144; + CASE_guard94433_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q144; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12014 = - (guard__h694435 == 2'b0) ? + (guard__h694433 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h694435 != 2'b01 && guard__h694435 != 2'b10 && - guard__h694435 != 2'b11 || + guard__h694433 != 2'b01 && guard__h694433 != 2'b10 && + guard__h694433 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12014 = @@ -41770,28 +41759,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_request_put; endcase end - always@(guard__h726326 or - _theResult___fst_exp__h734287 or _theResult___exp__h734942) + always@(guard__h726323 or + _theResult___fst_exp__h734284 or _theResult___exp__h734939) begin - case (guard__h726326) + case (guard__h726323) 2'b0: - CASE_guard26326_0b0_theResult___fst_exp34287_0_ETC__q155 = - _theResult___fst_exp__h734287; + CASE_guard26323_0b0_theResult___fst_exp34284_0_ETC__q155 = + _theResult___fst_exp__h734284; 2'b01, 2'b10, 2'b11: - CASE_guard26326_0b0_theResult___fst_exp34287_0_ETC__q155 = - _theResult___exp__h734942; + CASE_guard26323_0b0_theResult___fst_exp34284_0_ETC__q155 = + _theResult___exp__h734939; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h734287 or + _theResult___fst_exp__h734284 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13166 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13164 or - CASE_guard26326_0b0_theResult___fst_exp34287_0_ETC__q155) + CASE_guard26323_0b0_theResult___fst_exp34284_0_ETC__q155) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13170 = - _theResult___fst_exp__h734287; + _theResult___fst_exp__h734284; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13170 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13166; @@ -41800,44 +41789,44 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13164; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13170 = - CASE_guard26326_0b0_theResult___fst_exp34287_0_ETC__q155; + CASE_guard26323_0b0_theResult___fst_exp34284_0_ETC__q155; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13170 = 11'd0; endcase end - always@(guard__h726326 or - _theResult___fst_exp__h734287 or - out_exp__h734945 or _theResult___exp__h734942) + always@(guard__h726323 or + _theResult___fst_exp__h734284 or + out_exp__h734942 or _theResult___exp__h734939) begin - case (guard__h726326) + case (guard__h726323) 2'b0, 2'b01: - CASE_guard26326_0b0_theResult___fst_exp34287_0_ETC__q156 = - _theResult___fst_exp__h734287; + CASE_guard26323_0b0_theResult___fst_exp34284_0_ETC__q156 = + _theResult___fst_exp__h734284; 2'b10: - CASE_guard26326_0b0_theResult___fst_exp34287_0_ETC__q156 = - out_exp__h734945; + CASE_guard26323_0b0_theResult___fst_exp34284_0_ETC__q156 = + out_exp__h734942; 2'b11: - CASE_guard26326_0b0_theResult___fst_exp34287_0_ETC__q156 = - _theResult___exp__h734942; + CASE_guard26323_0b0_theResult___fst_exp34284_0_ETC__q156 = + _theResult___exp__h734939; endcase end - always@(guard__h726326 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h726323 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h726326) + case (guard__h726323) 2'b0, 2'b01, 2'b10: - CASE_guard26326_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q157 = + CASE_guard26323_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q157 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard26326_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q157 = - guard__h726326 == 2'b11 && + CASE_guard26323_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q157 = + guard__h726323 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h726326) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h726323) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -41847,12 +41836,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q158 = - (guard__h726326 == 2'b0) ? + (guard__h726323 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h726326 == 2'b01 || guard__h726326 == 2'b10 || - guard__h726326 == 2'b11) && + (guard__h726323 == 2'b01 || guard__h726323 == 2'b10 || + guard__h726323 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; @@ -41863,23 +41852,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(guard__h735638 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h735635 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h735638) + case (guard__h735635) 2'b0, 2'b01, 2'b10: - CASE_guard35638_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q159 = + CASE_guard35635_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q159 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard35638_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q159 = - guard__h735638 == 2'b11 && + CASE_guard35635_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q159 = + guard__h735635 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h735638) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h735635) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -41889,12 +41878,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q160 = - (guard__h735638 == 2'b0) ? + (guard__h735635 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h735638 == 2'b01 || guard__h735638 == 2'b10 || - guard__h735638 == 2'b11) && + (guard__h735635 == 2'b01 || guard__h735635 == 2'b10 || + guard__h735635 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; @@ -41905,23 +41894,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(guard__h744707 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h744704 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h744707) + case (guard__h744704) 2'b0, 2'b01, 2'b10: - CASE_guard44707_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q161 = + CASE_guard44704_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q161 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard44707_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q161 = - guard__h744707 == 2'b11 && + CASE_guard44704_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q161 = + guard__h744704 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h744707) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h744704) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -41931,12 +41920,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q162 = - (guard__h744707 == 2'b0) ? + (guard__h744704 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h744707 == 2'b01 || guard__h744707 == 2'b10 || - guard__h744707 == 2'b11) && + (guard__h744704 == 2'b01 || guard__h744704 == 2'b10 || + guard__h744704 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; @@ -41947,28 +41936,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(guard__h804483 or - _theResult___fst_exp__h812444 or _theResult___exp__h813099) + always@(guard__h804480 or + _theResult___fst_exp__h812441 or _theResult___exp__h813096) begin - case (guard__h804483) + case (guard__h804480) 2'b0: - CASE_guard04483_0b0_theResult___fst_exp12444_0_ETC__q172 = - _theResult___fst_exp__h812444; + CASE_guard04480_0b0_theResult___fst_exp12441_0_ETC__q172 = + _theResult___fst_exp__h812441; 2'b01, 2'b10, 2'b11: - CASE_guard04483_0b0_theResult___fst_exp12444_0_ETC__q172 = - _theResult___exp__h813099; + CASE_guard04480_0b0_theResult___fst_exp12441_0_ETC__q172 = + _theResult___exp__h813096; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h812444 or + _theResult___fst_exp__h812441 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13881 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13879 or - CASE_guard04483_0b0_theResult___fst_exp12444_0_ETC__q172) + CASE_guard04480_0b0_theResult___fst_exp12441_0_ETC__q172) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13885 = - _theResult___fst_exp__h812444; + _theResult___fst_exp__h812441; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13885 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13881; @@ -41977,42 +41966,42 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13879; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13885 = - CASE_guard04483_0b0_theResult___fst_exp12444_0_ETC__q172; + CASE_guard04480_0b0_theResult___fst_exp12441_0_ETC__q172; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13885 = 11'd0; endcase end - always@(guard__h804483 or - _theResult___fst_exp__h812444 or - out_exp__h813102 or _theResult___exp__h813099) + always@(guard__h804480 or + _theResult___fst_exp__h812441 or + out_exp__h813099 or _theResult___exp__h813096) begin - case (guard__h804483) + case (guard__h804480) 2'b0, 2'b01: - CASE_guard04483_0b0_theResult___fst_exp12444_0_ETC__q173 = - _theResult___fst_exp__h812444; + CASE_guard04480_0b0_theResult___fst_exp12441_0_ETC__q173 = + _theResult___fst_exp__h812441; 2'b10: - CASE_guard04483_0b0_theResult___fst_exp12444_0_ETC__q173 = - out_exp__h813102; + CASE_guard04480_0b0_theResult___fst_exp12441_0_ETC__q173 = + out_exp__h813099; 2'b11: - CASE_guard04483_0b0_theResult___fst_exp12444_0_ETC__q173 = - _theResult___exp__h813099; + CASE_guard04480_0b0_theResult___fst_exp12441_0_ETC__q173 = + _theResult___exp__h813096; endcase end - always@(guard__h804483 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h813792 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h804483) + case (guard__h813792) 2'b0, 2'b01, 2'b10: - CASE_guard04483_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q174 = + CASE_guard13792_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q174 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard04483_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q174 = - guard__h804483 == 2'b11 && + CASE_guard13792_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q174 = + guard__h813792 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h804483) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h813792) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -42021,12 +42010,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q175 = - (guard__h804483 == 2'b0) ? + (guard__h813792 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h804483 == 2'b01 || guard__h804483 == 2'b10 || - guard__h804483 == 2'b11) && + (guard__h813792 == 2'b01 || guard__h813792 == 2'b10 || + guard__h813792 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -42037,21 +42026,21 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h813795 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h804480 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h813795) + case (guard__h804480) 2'b0, 2'b01, 2'b10: - CASE_guard13795_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q176 = + CASE_guard04480_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q176 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard13795_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q176 = - guard__h813795 == 2'b11 && + CASE_guard04480_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q176 = + guard__h804480 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h813795) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h804480) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -42060,12 +42049,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q177 = - (guard__h813795 == 2'b0) ? + (guard__h804480 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h813795 == 2'b01 || guard__h813795 == 2'b10 || - guard__h813795 == 2'b11) && + (guard__h804480 == 2'b01 || guard__h804480 == 2'b10 || + guard__h804480 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -42076,21 +42065,21 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h822864 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h822861 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h822864) + case (guard__h822861) 2'b0, 2'b01, 2'b10: - CASE_guard22864_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q178 = + CASE_guard22861_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q178 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard22864_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q178 = - guard__h822864 == 2'b11 && + CASE_guard22861_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q178 = + guard__h822861 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h822864) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h822861) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -42099,12 +42088,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q179 = - (guard__h822864 == 2'b0) ? + (guard__h822861 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h822864 == 2'b01 || guard__h822864 == 2'b10 || - guard__h822864 == 2'b11) && + (guard__h822861 == 2'b01 || guard__h822861 == 2'b10 || + guard__h822861 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -42115,21 +42104,21 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h813795 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h813792 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h813795) + case (guard__h813792) 2'b0, 2'b01, 2'b10: - CASE_guard13795_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q180 = + CASE_guard13792_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q180 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard13795_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q180 = - guard__h813795 != 2'b11 || + CASE_guard13792_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q180 = + guard__h813792 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h813795) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h813792) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -42138,12 +42127,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q181 = - (guard__h813795 == 2'b0) ? + (guard__h813792 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h813795 != 2'b01 && guard__h813795 != 2'b10 && - guard__h813795 != 2'b11 || + guard__h813792 != 2'b01 && guard__h813792 != 2'b10 && + guard__h813792 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -42154,21 +42143,21 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h822864 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h822861 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h822864) + case (guard__h822861) 2'b0, 2'b01, 2'b10: - CASE_guard22864_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q182 = + CASE_guard22861_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q182 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard22864_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q182 = - guard__h822864 != 2'b11 || + CASE_guard22861_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q182 = + guard__h822861 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h822864) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h822861) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -42177,12 +42166,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q183 = - (guard__h822864 == 2'b0) ? + (guard__h822861 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h822864 != 2'b01 && guard__h822864 != 2'b10 && - guard__h822864 != 2'b11 || + guard__h822861 != 2'b01 && guard__h822861 != 2'b10 && + guard__h822861 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -42193,21 +42182,21 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h804483 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h804480 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h804483) + case (guard__h804480) 2'b0, 2'b01, 2'b10: - CASE_guard04483_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q184 = + CASE_guard04480_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q184 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard04483_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q184 = - guard__h804483 != 2'b11 || + CASE_guard04480_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q184 = + guard__h804480 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h804483) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h804480) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -42216,12 +42205,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q185 = - (guard__h804483 == 2'b0) ? + (guard__h804480 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h804483 != 2'b01 && guard__h804483 != 2'b10 && - guard__h804483 != 2'b11 || + guard__h804480 != 2'b01 && guard__h804480 != 2'b10 && + guard__h804480 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -42232,28 +42221,28 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h765179 or - _theResult___fst_exp__h773140 or _theResult___exp__h773795) + always@(guard__h765176 or + _theResult___fst_exp__h773137 or _theResult___exp__h773792) begin - case (guard__h765179) + case (guard__h765176) 2'b0: - CASE_guard65179_0b0_theResult___fst_exp73140_0_ETC__q195 = - _theResult___fst_exp__h773140; + CASE_guard65176_0b0_theResult___fst_exp73137_0_ETC__q195 = + _theResult___fst_exp__h773137; 2'b01, 2'b10, 2'b11: - CASE_guard65179_0b0_theResult___fst_exp73140_0_ETC__q195 = - _theResult___exp__h773795; + CASE_guard65176_0b0_theResult___fst_exp73137_0_ETC__q195 = + _theResult___exp__h773792; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h773140 or + _theResult___fst_exp__h773137 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14651 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14649 or - CASE_guard65179_0b0_theResult___fst_exp73140_0_ETC__q195) + CASE_guard65176_0b0_theResult___fst_exp73137_0_ETC__q195) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14655 = - _theResult___fst_exp__h773140; + _theResult___fst_exp__h773137; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14655 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14651; @@ -42262,100 +42251,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14649; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14655 = - CASE_guard65179_0b0_theResult___fst_exp73140_0_ETC__q195; + CASE_guard65176_0b0_theResult___fst_exp73137_0_ETC__q195; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14655 = 11'd0; endcase end - always@(guard__h765179 or - _theResult___fst_exp__h773140 or - out_exp__h773798 or _theResult___exp__h773795) + always@(guard__h765176 or + _theResult___fst_exp__h773137 or + out_exp__h773795 or _theResult___exp__h773792) begin - case (guard__h765179) + case (guard__h765176) 2'b0, 2'b01: - CASE_guard65179_0b0_theResult___fst_exp73140_0_ETC__q196 = - _theResult___fst_exp__h773140; + CASE_guard65176_0b0_theResult___fst_exp73137_0_ETC__q196 = + _theResult___fst_exp__h773137; 2'b10: - CASE_guard65179_0b0_theResult___fst_exp73140_0_ETC__q196 = - out_exp__h773798; + CASE_guard65176_0b0_theResult___fst_exp73137_0_ETC__q196 = + out_exp__h773795; 2'b11: - CASE_guard65179_0b0_theResult___fst_exp73140_0_ETC__q196 = - _theResult___exp__h773795; + CASE_guard65176_0b0_theResult___fst_exp73137_0_ETC__q196 = + _theResult___exp__h773792; endcase end - always@(guard__h783560 or - _theResult___fst_exp__h791550 or _theResult___exp__h792230) + always@(guard__h774488 or + _theResult___fst_exp__h782714 or _theResult___exp__h783443) begin - case (guard__h783560) + case (guard__h774488) 2'b0: - CASE_guard83560_0b0_theResult___fst_exp91550_0_ETC__q197 = - _theResult___fst_exp__h791550; + CASE_guard74488_0b0_theResult___fst_exp82714_0_ETC__q197 = + _theResult___fst_exp__h782714; 2'b01, 2'b10, 2'b11: - CASE_guard83560_0b0_theResult___fst_exp91550_0_ETC__q197 = - _theResult___exp__h792230; + CASE_guard74488_0b0_theResult___fst_exp82714_0_ETC__q197 = + _theResult___exp__h783443; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h791550 or - IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14720 or - IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14718 or - CASE_guard83560_0b0_theResult___fst_exp91550_0_ETC__q197) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd1: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14724 = - _theResult___fst_exp__h791550; - 3'd2: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14724 = - IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14720; - 3'd3: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14724 = - IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14718; - 3'd4: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14724 = - CASE_guard83560_0b0_theResult___fst_exp91550_0_ETC__q197; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14724 = - 11'd0; - endcase - end - always@(guard__h783560 or - _theResult___fst_exp__h791550 or - out_exp__h792233 or _theResult___exp__h792230) - begin - case (guard__h783560) - 2'b0, 2'b01: - CASE_guard83560_0b0_theResult___fst_exp91550_0_ETC__q198 = - _theResult___fst_exp__h791550; - 2'b10: - CASE_guard83560_0b0_theResult___fst_exp91550_0_ETC__q198 = - out_exp__h792233; - 2'b11: - CASE_guard83560_0b0_theResult___fst_exp91550_0_ETC__q198 = - _theResult___exp__h792230; - endcase - end - always@(guard__h774491 or - _theResult___fst_exp__h782717 or _theResult___exp__h783446) - begin - case (guard__h774491) - 2'b0: - CASE_guard74491_0b0_theResult___fst_exp82717_0_ETC__q199 = - _theResult___fst_exp__h782717; - 2'b01, 2'b10, 2'b11: - CASE_guard74491_0b0_theResult___fst_exp82717_0_ETC__q199 = - _theResult___exp__h783446; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h782717 or + _theResult___fst_exp__h782714 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14689 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14687 or - CASE_guard74491_0b0_theResult___fst_exp82717_0_ETC__q199) + CASE_guard74488_0b0_theResult___fst_exp82714_0_ETC__q197) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14693 = - _theResult___fst_exp__h782717; + _theResult___fst_exp__h782714; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14693 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14689; @@ -42364,100 +42302,100 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14687; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14693 = - CASE_guard74491_0b0_theResult___fst_exp82717_0_ETC__q199; + CASE_guard74488_0b0_theResult___fst_exp82714_0_ETC__q197; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14693 = 11'd0; endcase end - always@(guard__h774491 or - _theResult___fst_exp__h782717 or - out_exp__h783449 or _theResult___exp__h783446) + always@(guard__h774488 or + _theResult___fst_exp__h782714 or + out_exp__h783446 or _theResult___exp__h783443) begin - case (guard__h774491) + case (guard__h774488) 2'b0, 2'b01: - CASE_guard74491_0b0_theResult___fst_exp82717_0_ETC__q200 = - _theResult___fst_exp__h782717; + CASE_guard74488_0b0_theResult___fst_exp82714_0_ETC__q198 = + _theResult___fst_exp__h782714; 2'b10: - CASE_guard74491_0b0_theResult___fst_exp82717_0_ETC__q200 = - out_exp__h783449; + CASE_guard74488_0b0_theResult___fst_exp82714_0_ETC__q198 = + out_exp__h783446; 2'b11: - CASE_guard74491_0b0_theResult___fst_exp82717_0_ETC__q200 = - _theResult___exp__h783446; + CASE_guard74488_0b0_theResult___fst_exp82714_0_ETC__q198 = + _theResult___exp__h783443; endcase end - always@(guard__h813795 or - _theResult___fst_exp__h822021 or _theResult___exp__h822750) + always@(guard__h783557 or + _theResult___fst_exp__h791547 or _theResult___exp__h792227) begin - case (guard__h813795) + case (guard__h783557) 2'b0: - CASE_guard13795_0b0_theResult___fst_exp22021_0_ETC__q201 = - _theResult___fst_exp__h822021; + CASE_guard83557_0b0_theResult___fst_exp91547_0_ETC__q199 = + _theResult___fst_exp__h791547; 2'b01, 2'b10, 2'b11: - CASE_guard13795_0b0_theResult___fst_exp22021_0_ETC__q201 = - _theResult___exp__h822750; + CASE_guard83557_0b0_theResult___fst_exp91547_0_ETC__q199 = + _theResult___exp__h792227; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h822021 or - IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13919 or - IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13917 or - CASE_guard13795_0b0_theResult___fst_exp22021_0_ETC__q201) + _theResult___fst_exp__h791547 or + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14720 or + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14718 or + CASE_guard83557_0b0_theResult___fst_exp91547_0_ETC__q199) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13923 = - _theResult___fst_exp__h822021; + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14724 = + _theResult___fst_exp__h791547; 3'd2: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13923 = - IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13919; + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14724 = + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14720; 3'd3: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13923 = - IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13917; + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14724 = + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14718; 3'd4: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13923 = - CASE_guard13795_0b0_theResult___fst_exp22021_0_ETC__q201; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13923 = + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14724 = + CASE_guard83557_0b0_theResult___fst_exp91547_0_ETC__q199; + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14724 = 11'd0; endcase end - always@(guard__h813795 or - _theResult___fst_exp__h822021 or - out_exp__h822753 or _theResult___exp__h822750) + always@(guard__h783557 or + _theResult___fst_exp__h791547 or + out_exp__h792230 or _theResult___exp__h792227) begin - case (guard__h813795) + case (guard__h783557) 2'b0, 2'b01: - CASE_guard13795_0b0_theResult___fst_exp22021_0_ETC__q202 = - _theResult___fst_exp__h822021; + CASE_guard83557_0b0_theResult___fst_exp91547_0_ETC__q200 = + _theResult___fst_exp__h791547; 2'b10: - CASE_guard13795_0b0_theResult___fst_exp22021_0_ETC__q202 = - out_exp__h822753; + CASE_guard83557_0b0_theResult___fst_exp91547_0_ETC__q200 = + out_exp__h792230; 2'b11: - CASE_guard13795_0b0_theResult___fst_exp22021_0_ETC__q202 = - _theResult___exp__h822750; + CASE_guard83557_0b0_theResult___fst_exp91547_0_ETC__q200 = + _theResult___exp__h792227; endcase end - always@(guard__h822864 or - _theResult___fst_exp__h830854 or _theResult___exp__h831534) + always@(guard__h822861 or + _theResult___fst_exp__h830851 or _theResult___exp__h831531) begin - case (guard__h822864) + case (guard__h822861) 2'b0: - CASE_guard22864_0b0_theResult___fst_exp30854_0_ETC__q203 = - _theResult___fst_exp__h830854; + CASE_guard22861_0b0_theResult___fst_exp30851_0_ETC__q201 = + _theResult___fst_exp__h830851; 2'b01, 2'b10, 2'b11: - CASE_guard22864_0b0_theResult___fst_exp30854_0_ETC__q203 = - _theResult___exp__h831534; + CASE_guard22861_0b0_theResult___fst_exp30851_0_ETC__q201 = + _theResult___exp__h831531; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h830854 or + _theResult___fst_exp__h830851 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13950 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13948 or - CASE_guard22864_0b0_theResult___fst_exp30854_0_ETC__q203) + CASE_guard22861_0b0_theResult___fst_exp30851_0_ETC__q201) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13954 = - _theResult___fst_exp__h830854; + _theResult___fst_exp__h830851; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13954 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13950; @@ -42466,44 +42404,95 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13948; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13954 = - CASE_guard22864_0b0_theResult___fst_exp30854_0_ETC__q203; + CASE_guard22861_0b0_theResult___fst_exp30851_0_ETC__q201; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13954 = 11'd0; endcase end - always@(guard__h822864 or - _theResult___fst_exp__h830854 or - out_exp__h831537 or _theResult___exp__h831534) + always@(guard__h822861 or + _theResult___fst_exp__h830851 or + out_exp__h831534 or _theResult___exp__h831531) begin - case (guard__h822864) + case (guard__h822861) 2'b0, 2'b01: - CASE_guard22864_0b0_theResult___fst_exp30854_0_ETC__q204 = - _theResult___fst_exp__h830854; + CASE_guard22861_0b0_theResult___fst_exp30851_0_ETC__q202 = + _theResult___fst_exp__h830851; 2'b10: - CASE_guard22864_0b0_theResult___fst_exp30854_0_ETC__q204 = - out_exp__h831537; + CASE_guard22861_0b0_theResult___fst_exp30851_0_ETC__q202 = + out_exp__h831534; 2'b11: - CASE_guard22864_0b0_theResult___fst_exp30854_0_ETC__q204 = - _theResult___exp__h831534; + CASE_guard22861_0b0_theResult___fst_exp30851_0_ETC__q202 = + _theResult___exp__h831531; endcase end - always@(guard__h765179 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h813792 or + _theResult___fst_exp__h822018 or _theResult___exp__h822747) begin - case (guard__h765179) + case (guard__h813792) + 2'b0: + CASE_guard13792_0b0_theResult___fst_exp22018_0_ETC__q203 = + _theResult___fst_exp__h822018; + 2'b01, 2'b10, 2'b11: + CASE_guard13792_0b0_theResult___fst_exp22018_0_ETC__q203 = + _theResult___exp__h822747; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or + _theResult___fst_exp__h822018 or + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13919 or + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13917 or + CASE_guard13792_0b0_theResult___fst_exp22018_0_ETC__q203) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd1: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13923 = + _theResult___fst_exp__h822018; + 3'd2: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13923 = + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13919; + 3'd3: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13923 = + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13917; + 3'd4: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13923 = + CASE_guard13792_0b0_theResult___fst_exp22018_0_ETC__q203; + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13923 = + 11'd0; + endcase + end + always@(guard__h813792 or + _theResult___fst_exp__h822018 or + out_exp__h822750 or _theResult___exp__h822747) + begin + case (guard__h813792) + 2'b0, 2'b01: + CASE_guard13792_0b0_theResult___fst_exp22018_0_ETC__q204 = + _theResult___fst_exp__h822018; + 2'b10: + CASE_guard13792_0b0_theResult___fst_exp22018_0_ETC__q204 = + out_exp__h822750; + 2'b11: + CASE_guard13792_0b0_theResult___fst_exp22018_0_ETC__q204 = + _theResult___exp__h822747; + endcase + end + always@(guard__h765176 or coreFix_fpuMulDivExe_0_regToExeQ$first) + begin + case (guard__h765176) 2'b0, 2'b01, 2'b10: - CASE_guard65179_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q205 = + CASE_guard65176_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q205 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard65179_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q205 = - guard__h765179 == 2'b11 && + CASE_guard65176_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q205 = + guard__h765176 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h765179) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h765176) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -42513,12 +42502,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q206 = - (guard__h765179 == 2'b0) ? + (guard__h765176 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h765179 == 2'b01 || guard__h765179 == 2'b10 || - guard__h765179 == 2'b11) && + (guard__h765176 == 2'b01 || guard__h765176 == 2'b10 || + guard__h765176 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -42529,23 +42518,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h774491 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h774488 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h774491) + case (guard__h774488) 2'b0, 2'b01, 2'b10: - CASE_guard74491_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q207 = + CASE_guard74488_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q207 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard74491_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q207 = - guard__h774491 == 2'b11 && + CASE_guard74488_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q207 = + guard__h774488 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h774491) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h774488) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -42555,12 +42544,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q208 = - (guard__h774491 == 2'b0) ? + (guard__h774488 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h774491 == 2'b01 || guard__h774491 == 2'b10 || - guard__h774491 == 2'b11) && + (guard__h774488 == 2'b01 || guard__h774488 == 2'b10 || + guard__h774488 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -42571,23 +42560,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h783560 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h783557 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h783560) + case (guard__h783557) 2'b0, 2'b01, 2'b10: - CASE_guard83560_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q209 = + CASE_guard83557_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q209 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard83560_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q209 = - guard__h783560 == 2'b11 && + CASE_guard83557_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q209 = + guard__h783557 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h783560) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h783557) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -42597,12 +42586,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q210 = - (guard__h783560 == 2'b0) ? + (guard__h783557 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h783560 == 2'b01 || guard__h783560 == 2'b10 || - guard__h783560 == 2'b11) && + (guard__h783557 == 2'b01 || guard__h783557 == 2'b10 || + guard__h783557 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -42613,23 +42602,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h774491 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h774488 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h774491) + case (guard__h774488) 2'b0, 2'b01, 2'b10: - CASE_guard74491_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q211 = + CASE_guard74488_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q211 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard74491_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q211 = - guard__h774491 != 2'b11 || + CASE_guard74488_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q211 = + guard__h774488 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h774491) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h774488) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -42639,12 +42628,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q212 = - (guard__h774491 == 2'b0) ? + (guard__h774488 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h774491 != 2'b01 && guard__h774491 != 2'b10 && - guard__h774491 != 2'b11 || + guard__h774488 != 2'b01 && guard__h774488 != 2'b10 && + guard__h774488 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -42655,23 +42644,23 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h783560 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h783557 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h783560) + case (guard__h783557) 2'b0, 2'b01, 2'b10: - CASE_guard83560_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q213 = + CASE_guard83557_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q213 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard83560_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q213 = - guard__h783560 != 2'b11 || + CASE_guard83557_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q213 = + guard__h783557 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h783560) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h783557) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -42681,12 +42670,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q214 = - (guard__h783560 == 2'b0) ? + (guard__h783557 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h783560 != 2'b01 && guard__h783560 != 2'b10 && - guard__h783560 != 2'b11 || + guard__h783557 != 2'b01 && guard__h783557 != 2'b10 && + guard__h783557 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -42697,23 +42686,23 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h765179 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h765176 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h765179) + case (guard__h765176) 2'b0, 2'b01, 2'b10: - CASE_guard65179_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q215 = + CASE_guard65176_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q215 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard65179_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q215 = - guard__h765179 != 2'b11 || + CASE_guard65176_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q215 = + guard__h765176 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h765179) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h765176) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -42723,12 +42712,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q216 = - (guard__h765179 == 2'b0) ? + (guard__h765176 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h765179 != 2'b01 && guard__h765179 != 2'b10 && - guard__h765179 != 2'b11 || + guard__h765176 != 2'b01 && guard__h765176 != 2'b10 && + guard__h765176 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -42739,28 +42728,28 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h765179 or - _theResult___snd__h773091 or _theResult___sfd__h773796) + always@(guard__h765176 or + _theResult___snd__h773088 or _theResult___sfd__h773793) begin - case (guard__h765179) + case (guard__h765176) 2'b0: - CASE_guard65179_0b0_theResult___snd73091_BITS__ETC__q217 = - _theResult___snd__h773091[56:5]; + CASE_guard65176_0b0_theResult___snd73088_BITS__ETC__q217 = + _theResult___snd__h773088[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard65179_0b0_theResult___snd73091_BITS__ETC__q217 = - _theResult___sfd__h773796; + CASE_guard65176_0b0_theResult___snd73088_BITS__ETC__q217 = + _theResult___sfd__h773793; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h773091 or + _theResult___snd__h773088 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14746 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14744 or - CASE_guard65179_0b0_theResult___snd73091_BITS__ETC__q217) + CASE_guard65176_0b0_theResult___snd73088_BITS__ETC__q217) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14750 = - _theResult___snd__h773091[56:5]; + _theResult___snd__h773088[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14750 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14746; @@ -42769,48 +42758,48 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14744; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14750 = - CASE_guard65179_0b0_theResult___snd73091_BITS__ETC__q217; + CASE_guard65176_0b0_theResult___snd73088_BITS__ETC__q217; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14750 = 52'd0; endcase end - always@(guard__h765179 or - _theResult___snd__h773091 or - out_sfd__h773799 or _theResult___sfd__h773796) + always@(guard__h765176 or + _theResult___snd__h773088 or + out_sfd__h773796 or _theResult___sfd__h773793) begin - case (guard__h765179) + case (guard__h765176) 2'b0, 2'b01: - CASE_guard65179_0b0_theResult___snd73091_BITS__ETC__q218 = - _theResult___snd__h773091[56:5]; + CASE_guard65176_0b0_theResult___snd73088_BITS__ETC__q218 = + _theResult___snd__h773088[56:5]; 2'b10: - CASE_guard65179_0b0_theResult___snd73091_BITS__ETC__q218 = - out_sfd__h773799; + CASE_guard65176_0b0_theResult___snd73088_BITS__ETC__q218 = + out_sfd__h773796; 2'b11: - CASE_guard65179_0b0_theResult___snd73091_BITS__ETC__q218 = - _theResult___sfd__h773796; + CASE_guard65176_0b0_theResult___snd73088_BITS__ETC__q218 = + _theResult___sfd__h773793; endcase end - always@(guard__h774491 or sfdin__h782711 or _theResult___sfd__h783447) + always@(guard__h774488 or sfdin__h782708 or _theResult___sfd__h783444) begin - case (guard__h774491) + case (guard__h774488) 2'b0: - CASE_guard74491_0b0_sfdin82711_BITS_56_TO_5_0b_ETC__q219 = - sfdin__h782711[56:5]; + CASE_guard74488_0b0_sfdin82708_BITS_56_TO_5_0b_ETC__q219 = + sfdin__h782708[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard74491_0b0_sfdin82711_BITS_56_TO_5_0b_ETC__q219 = - _theResult___sfd__h783447; + CASE_guard74488_0b0_sfdin82708_BITS_56_TO_5_0b_ETC__q219 = + _theResult___sfd__h783444; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h782711 or + sfdin__h782708 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14772 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14770 or - CASE_guard74491_0b0_sfdin82711_BITS_56_TO_5_0b_ETC__q219) + CASE_guard74488_0b0_sfdin82708_BITS_56_TO_5_0b_ETC__q219) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14776 = - sfdin__h782711[56:5]; + sfdin__h782708[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14776 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14772; @@ -42819,48 +42808,48 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14770; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14776 = - CASE_guard74491_0b0_sfdin82711_BITS_56_TO_5_0b_ETC__q219; + CASE_guard74488_0b0_sfdin82708_BITS_56_TO_5_0b_ETC__q219; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14776 = 52'd0; endcase end - always@(guard__h774491 or - sfdin__h782711 or out_sfd__h783450 or _theResult___sfd__h783447) + always@(guard__h774488 or + sfdin__h782708 or out_sfd__h783447 or _theResult___sfd__h783444) begin - case (guard__h774491) + case (guard__h774488) 2'b0, 2'b01: - CASE_guard74491_0b0_sfdin82711_BITS_56_TO_5_0b_ETC__q220 = - sfdin__h782711[56:5]; + CASE_guard74488_0b0_sfdin82708_BITS_56_TO_5_0b_ETC__q220 = + sfdin__h782708[56:5]; 2'b10: - CASE_guard74491_0b0_sfdin82711_BITS_56_TO_5_0b_ETC__q220 = - out_sfd__h783450; + CASE_guard74488_0b0_sfdin82708_BITS_56_TO_5_0b_ETC__q220 = + out_sfd__h783447; 2'b11: - CASE_guard74491_0b0_sfdin82711_BITS_56_TO_5_0b_ETC__q220 = - _theResult___sfd__h783447; + CASE_guard74488_0b0_sfdin82708_BITS_56_TO_5_0b_ETC__q220 = + _theResult___sfd__h783444; endcase end - always@(guard__h783560 or - _theResult___snd__h791496 or _theResult___sfd__h792231) + always@(guard__h783557 or + _theResult___snd__h791493 or _theResult___sfd__h792228) begin - case (guard__h783560) + case (guard__h783557) 2'b0: - CASE_guard83560_0b0_theResult___snd91496_BITS__ETC__q221 = - _theResult___snd__h791496[56:5]; + CASE_guard83557_0b0_theResult___snd91493_BITS__ETC__q221 = + _theResult___snd__h791493[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard83560_0b0_theResult___snd91496_BITS__ETC__q221 = - _theResult___sfd__h792231; + CASE_guard83557_0b0_theResult___snd91493_BITS__ETC__q221 = + _theResult___sfd__h792228; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h791496 or + _theResult___snd__h791493 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14791 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14789 or - CASE_guard83560_0b0_theResult___snd91496_BITS__ETC__q221) + CASE_guard83557_0b0_theResult___snd91493_BITS__ETC__q221) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14795 = - _theResult___snd__h791496[56:5]; + _theResult___snd__h791493[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14795 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14791; @@ -42869,49 +42858,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14789; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14795 = - CASE_guard83560_0b0_theResult___snd91496_BITS__ETC__q221; + CASE_guard83557_0b0_theResult___snd91493_BITS__ETC__q221; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14795 = 52'd0; endcase end - always@(guard__h783560 or - _theResult___snd__h791496 or - out_sfd__h792234 or _theResult___sfd__h792231) + always@(guard__h783557 or + _theResult___snd__h791493 or + out_sfd__h792231 or _theResult___sfd__h792228) begin - case (guard__h783560) + case (guard__h783557) 2'b0, 2'b01: - CASE_guard83560_0b0_theResult___snd91496_BITS__ETC__q222 = - _theResult___snd__h791496[56:5]; + CASE_guard83557_0b0_theResult___snd91493_BITS__ETC__q222 = + _theResult___snd__h791493[56:5]; 2'b10: - CASE_guard83560_0b0_theResult___snd91496_BITS__ETC__q222 = - out_sfd__h792234; + CASE_guard83557_0b0_theResult___snd91493_BITS__ETC__q222 = + out_sfd__h792231; 2'b11: - CASE_guard83560_0b0_theResult___snd91496_BITS__ETC__q222 = - _theResult___sfd__h792231; + CASE_guard83557_0b0_theResult___snd91493_BITS__ETC__q222 = + _theResult___sfd__h792228; endcase end - always@(guard__h735638 or - _theResult___fst_exp__h743864 or _theResult___exp__h744593) + always@(guard__h735635 or + _theResult___fst_exp__h743861 or _theResult___exp__h744590) begin - case (guard__h735638) + case (guard__h735635) 2'b0: - CASE_guard35638_0b0_theResult___fst_exp43864_0_ETC__q223 = - _theResult___fst_exp__h743864; + CASE_guard35635_0b0_theResult___fst_exp43861_0_ETC__q223 = + _theResult___fst_exp__h743861; 2'b01, 2'b10, 2'b11: - CASE_guard35638_0b0_theResult___fst_exp43864_0_ETC__q223 = - _theResult___exp__h744593; + CASE_guard35635_0b0_theResult___fst_exp43861_0_ETC__q223 = + _theResult___exp__h744590; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h743864 or + _theResult___fst_exp__h743861 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13209 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13207 or - CASE_guard35638_0b0_theResult___fst_exp43864_0_ETC__q223) + CASE_guard35635_0b0_theResult___fst_exp43861_0_ETC__q223) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13213 = - _theResult___fst_exp__h743864; + _theResult___fst_exp__h743861; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13213 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13209; @@ -42920,100 +42909,49 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13207; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13213 = - CASE_guard35638_0b0_theResult___fst_exp43864_0_ETC__q223; + CASE_guard35635_0b0_theResult___fst_exp43861_0_ETC__q223; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13213 = 11'd0; endcase end - always@(guard__h735638 or - _theResult___fst_exp__h743864 or - out_exp__h744596 or _theResult___exp__h744593) + always@(guard__h735635 or + _theResult___fst_exp__h743861 or + out_exp__h744593 or _theResult___exp__h744590) begin - case (guard__h735638) + case (guard__h735635) 2'b0, 2'b01: - CASE_guard35638_0b0_theResult___fst_exp43864_0_ETC__q224 = - _theResult___fst_exp__h743864; + CASE_guard35635_0b0_theResult___fst_exp43861_0_ETC__q224 = + _theResult___fst_exp__h743861; 2'b10: - CASE_guard35638_0b0_theResult___fst_exp43864_0_ETC__q224 = - out_exp__h744596; + CASE_guard35635_0b0_theResult___fst_exp43861_0_ETC__q224 = + out_exp__h744593; 2'b11: - CASE_guard35638_0b0_theResult___fst_exp43864_0_ETC__q224 = - _theResult___exp__h744593; + CASE_guard35635_0b0_theResult___fst_exp43861_0_ETC__q224 = + _theResult___exp__h744590; endcase end - always@(guard__h744707 or - _theResult___fst_exp__h752697 or _theResult___exp__h753377) + always@(guard__h726323 or + _theResult___snd__h734235 or _theResult___sfd__h734940) begin - case (guard__h744707) + case (guard__h726323) 2'b0: - CASE_guard44707_0b0_theResult___fst_exp52697_0_ETC__q225 = - _theResult___fst_exp__h752697; + CASE_guard26323_0b0_theResult___snd34235_BITS__ETC__q225 = + _theResult___snd__h734235[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard44707_0b0_theResult___fst_exp52697_0_ETC__q225 = - _theResult___exp__h753377; + CASE_guard26323_0b0_theResult___snd34235_BITS__ETC__q225 = + _theResult___sfd__h734940; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h752697 or - IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13240 or - IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13238 or - CASE_guard44707_0b0_theResult___fst_exp52697_0_ETC__q225) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd1: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13244 = - _theResult___fst_exp__h752697; - 3'd2: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13244 = - IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13240; - 3'd3: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13244 = - IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13238; - 3'd4: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13244 = - CASE_guard44707_0b0_theResult___fst_exp52697_0_ETC__q225; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13244 = - 11'd0; - endcase - end - always@(guard__h744707 or - _theResult___fst_exp__h752697 or - out_exp__h753380 or _theResult___exp__h753377) - begin - case (guard__h744707) - 2'b0, 2'b01: - CASE_guard44707_0b0_theResult___fst_exp52697_0_ETC__q226 = - _theResult___fst_exp__h752697; - 2'b10: - CASE_guard44707_0b0_theResult___fst_exp52697_0_ETC__q226 = - out_exp__h753380; - 2'b11: - CASE_guard44707_0b0_theResult___fst_exp52697_0_ETC__q226 = - _theResult___exp__h753377; - endcase - end - always@(guard__h726326 or - _theResult___snd__h734238 or _theResult___sfd__h734943) - begin - case (guard__h726326) - 2'b0: - CASE_guard26326_0b0_theResult___snd34238_BITS__ETC__q227 = - _theResult___snd__h734238[56:5]; - 2'b01, 2'b10, 2'b11: - CASE_guard26326_0b0_theResult___snd34238_BITS__ETC__q227 = - _theResult___sfd__h734943; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h734238 or + _theResult___snd__h734235 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13266 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13264 or - CASE_guard26326_0b0_theResult___snd34238_BITS__ETC__q227) + CASE_guard26323_0b0_theResult___snd34235_BITS__ETC__q225) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13270 = - _theResult___snd__h734238[56:5]; + _theResult___snd__h734235[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13270 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13266; @@ -43022,48 +42960,99 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13264; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13270 = - CASE_guard26326_0b0_theResult___snd34238_BITS__ETC__q227; + CASE_guard26323_0b0_theResult___snd34235_BITS__ETC__q225; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13270 = 52'd0; endcase end - always@(guard__h726326 or - _theResult___snd__h734238 or - out_sfd__h734946 or _theResult___sfd__h734943) + always@(guard__h726323 or + _theResult___snd__h734235 or + out_sfd__h734943 or _theResult___sfd__h734940) begin - case (guard__h726326) + case (guard__h726323) 2'b0, 2'b01: - CASE_guard26326_0b0_theResult___snd34238_BITS__ETC__q228 = - _theResult___snd__h734238[56:5]; + CASE_guard26323_0b0_theResult___snd34235_BITS__ETC__q226 = + _theResult___snd__h734235[56:5]; 2'b10: - CASE_guard26326_0b0_theResult___snd34238_BITS__ETC__q228 = - out_sfd__h734946; + CASE_guard26323_0b0_theResult___snd34235_BITS__ETC__q226 = + out_sfd__h734943; 2'b11: - CASE_guard26326_0b0_theResult___snd34238_BITS__ETC__q228 = - _theResult___sfd__h734943; + CASE_guard26323_0b0_theResult___snd34235_BITS__ETC__q226 = + _theResult___sfd__h734940; endcase end - always@(guard__h735638 or sfdin__h743858 or _theResult___sfd__h744594) + always@(guard__h744704 or + _theResult___fst_exp__h752694 or _theResult___exp__h753374) begin - case (guard__h735638) + case (guard__h744704) 2'b0: - CASE_guard35638_0b0_sfdin43858_BITS_56_TO_5_0b_ETC__q229 = - sfdin__h743858[56:5]; + CASE_guard44704_0b0_theResult___fst_exp52694_0_ETC__q227 = + _theResult___fst_exp__h752694; 2'b01, 2'b10, 2'b11: - CASE_guard35638_0b0_sfdin43858_BITS_56_TO_5_0b_ETC__q229 = - _theResult___sfd__h744594; + CASE_guard44704_0b0_theResult___fst_exp52694_0_ETC__q227 = + _theResult___exp__h753374; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h743858 or + _theResult___fst_exp__h752694 or + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13240 or + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13238 or + CASE_guard44704_0b0_theResult___fst_exp52694_0_ETC__q227) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd1: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13244 = + _theResult___fst_exp__h752694; + 3'd2: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13244 = + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13240; + 3'd3: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13244 = + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13238; + 3'd4: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13244 = + CASE_guard44704_0b0_theResult___fst_exp52694_0_ETC__q227; + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13244 = + 11'd0; + endcase + end + always@(guard__h744704 or + _theResult___fst_exp__h752694 or + out_exp__h753377 or _theResult___exp__h753374) + begin + case (guard__h744704) + 2'b0, 2'b01: + CASE_guard44704_0b0_theResult___fst_exp52694_0_ETC__q228 = + _theResult___fst_exp__h752694; + 2'b10: + CASE_guard44704_0b0_theResult___fst_exp52694_0_ETC__q228 = + out_exp__h753377; + 2'b11: + CASE_guard44704_0b0_theResult___fst_exp52694_0_ETC__q228 = + _theResult___exp__h753374; + endcase + end + always@(guard__h735635 or sfdin__h743855 or _theResult___sfd__h744591) + begin + case (guard__h735635) + 2'b0: + CASE_guard35635_0b0_sfdin43855_BITS_56_TO_5_0b_ETC__q229 = + sfdin__h743855[56:5]; + 2'b01, 2'b10, 2'b11: + CASE_guard35635_0b0_sfdin43855_BITS_56_TO_5_0b_ETC__q229 = + _theResult___sfd__h744591; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or + sfdin__h743855 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13293 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13291 or - CASE_guard35638_0b0_sfdin43858_BITS_56_TO_5_0b_ETC__q229) + CASE_guard35635_0b0_sfdin43855_BITS_56_TO_5_0b_ETC__q229) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13297 = - sfdin__h743858[56:5]; + sfdin__h743855[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13297 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13293; @@ -43072,48 +43061,48 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13291; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13297 = - CASE_guard35638_0b0_sfdin43858_BITS_56_TO_5_0b_ETC__q229; + CASE_guard35635_0b0_sfdin43855_BITS_56_TO_5_0b_ETC__q229; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13297 = 52'd0; endcase end - always@(guard__h735638 or - sfdin__h743858 or out_sfd__h744597 or _theResult___sfd__h744594) + always@(guard__h735635 or + sfdin__h743855 or out_sfd__h744594 or _theResult___sfd__h744591) begin - case (guard__h735638) + case (guard__h735635) 2'b0, 2'b01: - CASE_guard35638_0b0_sfdin43858_BITS_56_TO_5_0b_ETC__q230 = - sfdin__h743858[56:5]; + CASE_guard35635_0b0_sfdin43855_BITS_56_TO_5_0b_ETC__q230 = + sfdin__h743855[56:5]; 2'b10: - CASE_guard35638_0b0_sfdin43858_BITS_56_TO_5_0b_ETC__q230 = - out_sfd__h744597; + CASE_guard35635_0b0_sfdin43855_BITS_56_TO_5_0b_ETC__q230 = + out_sfd__h744594; 2'b11: - CASE_guard35638_0b0_sfdin43858_BITS_56_TO_5_0b_ETC__q230 = - _theResult___sfd__h744594; + CASE_guard35635_0b0_sfdin43855_BITS_56_TO_5_0b_ETC__q230 = + _theResult___sfd__h744591; endcase end - always@(guard__h744707 or - _theResult___snd__h752643 or _theResult___sfd__h753378) + always@(guard__h744704 or + _theResult___snd__h752640 or _theResult___sfd__h753375) begin - case (guard__h744707) + case (guard__h744704) 2'b0: - CASE_guard44707_0b0_theResult___snd52643_BITS__ETC__q231 = - _theResult___snd__h752643[56:5]; + CASE_guard44704_0b0_theResult___snd52640_BITS__ETC__q231 = + _theResult___snd__h752640[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard44707_0b0_theResult___snd52643_BITS__ETC__q231 = - _theResult___sfd__h753378; + CASE_guard44704_0b0_theResult___snd52640_BITS__ETC__q231 = + _theResult___sfd__h753375; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h752643 or + _theResult___snd__h752640 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13312 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13310 or - CASE_guard44707_0b0_theResult___snd52643_BITS__ETC__q231) + CASE_guard44704_0b0_theResult___snd52640_BITS__ETC__q231) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13316 = - _theResult___snd__h752643[56:5]; + _theResult___snd__h752640[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13316 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13312; @@ -43122,49 +43111,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13310; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13316 = - CASE_guard44707_0b0_theResult___snd52643_BITS__ETC__q231; + CASE_guard44704_0b0_theResult___snd52640_BITS__ETC__q231; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13316 = 52'd0; endcase end - always@(guard__h744707 or - _theResult___snd__h752643 or - out_sfd__h753381 or _theResult___sfd__h753378) + always@(guard__h744704 or + _theResult___snd__h752640 or + out_sfd__h753378 or _theResult___sfd__h753375) begin - case (guard__h744707) + case (guard__h744704) 2'b0, 2'b01: - CASE_guard44707_0b0_theResult___snd52643_BITS__ETC__q232 = - _theResult___snd__h752643[56:5]; + CASE_guard44704_0b0_theResult___snd52640_BITS__ETC__q232 = + _theResult___snd__h752640[56:5]; 2'b10: - CASE_guard44707_0b0_theResult___snd52643_BITS__ETC__q232 = - out_sfd__h753381; + CASE_guard44704_0b0_theResult___snd52640_BITS__ETC__q232 = + out_sfd__h753378; 2'b11: - CASE_guard44707_0b0_theResult___snd52643_BITS__ETC__q232 = - _theResult___sfd__h753378; + CASE_guard44704_0b0_theResult___snd52640_BITS__ETC__q232 = + _theResult___sfd__h753375; endcase end - always@(guard__h804483 or - _theResult___snd__h812395 or _theResult___sfd__h813100) + always@(guard__h804480 or + _theResult___snd__h812392 or _theResult___sfd__h813097) begin - case (guard__h804483) + case (guard__h804480) 2'b0: - CASE_guard04483_0b0_theResult___snd12395_BITS__ETC__q233 = - _theResult___snd__h812395[56:5]; + CASE_guard04480_0b0_theResult___snd12392_BITS__ETC__q233 = + _theResult___snd__h812392[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard04483_0b0_theResult___snd12395_BITS__ETC__q233 = - _theResult___sfd__h813100; + CASE_guard04480_0b0_theResult___snd12392_BITS__ETC__q233 = + _theResult___sfd__h813097; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h812395 or + _theResult___snd__h812392 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13976 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13974 or - CASE_guard04483_0b0_theResult___snd12395_BITS__ETC__q233) + CASE_guard04480_0b0_theResult___snd12392_BITS__ETC__q233) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13980 = - _theResult___snd__h812395[56:5]; + _theResult___snd__h812392[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13980 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13976; @@ -43173,48 +43162,48 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13974; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13980 = - CASE_guard04483_0b0_theResult___snd12395_BITS__ETC__q233; + CASE_guard04480_0b0_theResult___snd12392_BITS__ETC__q233; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13980 = 52'd0; endcase end - always@(guard__h804483 or - _theResult___snd__h812395 or - out_sfd__h813103 or _theResult___sfd__h813100) + always@(guard__h804480 or + _theResult___snd__h812392 or + out_sfd__h813100 or _theResult___sfd__h813097) begin - case (guard__h804483) + case (guard__h804480) 2'b0, 2'b01: - CASE_guard04483_0b0_theResult___snd12395_BITS__ETC__q234 = - _theResult___snd__h812395[56:5]; + CASE_guard04480_0b0_theResult___snd12392_BITS__ETC__q234 = + _theResult___snd__h812392[56:5]; 2'b10: - CASE_guard04483_0b0_theResult___snd12395_BITS__ETC__q234 = - out_sfd__h813103; + CASE_guard04480_0b0_theResult___snd12392_BITS__ETC__q234 = + out_sfd__h813100; 2'b11: - CASE_guard04483_0b0_theResult___snd12395_BITS__ETC__q234 = - _theResult___sfd__h813100; + CASE_guard04480_0b0_theResult___snd12392_BITS__ETC__q234 = + _theResult___sfd__h813097; endcase end - always@(guard__h813795 or sfdin__h822015 or _theResult___sfd__h822751) + always@(guard__h813792 or sfdin__h822012 or _theResult___sfd__h822748) begin - case (guard__h813795) + case (guard__h813792) 2'b0: - CASE_guard13795_0b0_sfdin22015_BITS_56_TO_5_0b_ETC__q235 = - sfdin__h822015[56:5]; + CASE_guard13792_0b0_sfdin22012_BITS_56_TO_5_0b_ETC__q235 = + sfdin__h822012[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard13795_0b0_sfdin22015_BITS_56_TO_5_0b_ETC__q235 = - _theResult___sfd__h822751; + CASE_guard13792_0b0_sfdin22012_BITS_56_TO_5_0b_ETC__q235 = + _theResult___sfd__h822748; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h822015 or + sfdin__h822012 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14002 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14000 or - CASE_guard13795_0b0_sfdin22015_BITS_56_TO_5_0b_ETC__q235) + CASE_guard13792_0b0_sfdin22012_BITS_56_TO_5_0b_ETC__q235) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14006 = - sfdin__h822015[56:5]; + sfdin__h822012[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14006 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14002; @@ -43223,24 +43212,24 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14000; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14006 = - CASE_guard13795_0b0_sfdin22015_BITS_56_TO_5_0b_ETC__q235; + CASE_guard13792_0b0_sfdin22012_BITS_56_TO_5_0b_ETC__q235; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14006 = 52'd0; endcase end - always@(guard__h813795 or - sfdin__h822015 or out_sfd__h822754 or _theResult___sfd__h822751) + always@(guard__h813792 or + sfdin__h822012 or out_sfd__h822751 or _theResult___sfd__h822748) begin - case (guard__h813795) + case (guard__h813792) 2'b0, 2'b01: - CASE_guard13795_0b0_sfdin22015_BITS_56_TO_5_0b_ETC__q236 = - sfdin__h822015[56:5]; + CASE_guard13792_0b0_sfdin22012_BITS_56_TO_5_0b_ETC__q236 = + sfdin__h822012[56:5]; 2'b10: - CASE_guard13795_0b0_sfdin22015_BITS_56_TO_5_0b_ETC__q236 = - out_sfd__h822754; + CASE_guard13792_0b0_sfdin22012_BITS_56_TO_5_0b_ETC__q236 = + out_sfd__h822751; 2'b11: - CASE_guard13795_0b0_sfdin22015_BITS_56_TO_5_0b_ETC__q236 = - _theResult___sfd__h822751; + CASE_guard13792_0b0_sfdin22012_BITS_56_TO_5_0b_ETC__q236 = + _theResult___sfd__h822748; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or @@ -43275,28 +43264,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ_first__2522_B_ETC___d15003; endcase end - always@(guard__h822864 or - _theResult___snd__h830800 or _theResult___sfd__h831535) + always@(guard__h822861 or + _theResult___snd__h830797 or _theResult___sfd__h831532) begin - case (guard__h822864) + case (guard__h822861) 2'b0: - CASE_guard22864_0b0_theResult___snd30800_BITS__ETC__q237 = - _theResult___snd__h830800[56:5]; + CASE_guard22861_0b0_theResult___snd30797_BITS__ETC__q237 = + _theResult___snd__h830797[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard22864_0b0_theResult___snd30800_BITS__ETC__q237 = - _theResult___sfd__h831535; + CASE_guard22861_0b0_theResult___snd30797_BITS__ETC__q237 = + _theResult___sfd__h831532; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h830800 or + _theResult___snd__h830797 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14021 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14019 or - CASE_guard22864_0b0_theResult___snd30800_BITS__ETC__q237) + CASE_guard22861_0b0_theResult___snd30797_BITS__ETC__q237) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14025 = - _theResult___snd__h830800[56:5]; + _theResult___snd__h830797[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14025 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14021; @@ -43305,25 +43294,25 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14019; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14025 = - CASE_guard22864_0b0_theResult___snd30800_BITS__ETC__q237; + CASE_guard22861_0b0_theResult___snd30797_BITS__ETC__q237; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14025 = 52'd0; endcase end - always@(guard__h822864 or - _theResult___snd__h830800 or - out_sfd__h831538 or _theResult___sfd__h831535) + always@(guard__h822861 or + _theResult___snd__h830797 or + out_sfd__h831535 or _theResult___sfd__h831532) begin - case (guard__h822864) + case (guard__h822861) 2'b0, 2'b01: - CASE_guard22864_0b0_theResult___snd30800_BITS__ETC__q238 = - _theResult___snd__h830800[56:5]; + CASE_guard22861_0b0_theResult___snd30797_BITS__ETC__q238 = + _theResult___snd__h830797[56:5]; 2'b10: - CASE_guard22864_0b0_theResult___snd30800_BITS__ETC__q238 = - out_sfd__h831538; + CASE_guard22861_0b0_theResult___snd30797_BITS__ETC__q238 = + out_sfd__h831535; 2'b11: - CASE_guard22864_0b0_theResult___snd30800_BITS__ETC__q238 = - _theResult___sfd__h831535; + CASE_guard22861_0b0_theResult___snd30797_BITS__ETC__q238 = + _theResult___sfd__h831532; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or @@ -43495,16 +43484,6 @@ module mkCore(CLK, endcase end always@(coreFix_aluExe_0_rsAlu$dispatchData) - begin - case (coreFix_aluExe_0_rsAlu$dispatchData[197:194]) - 4'd7, 4'd8, 4'd9, 4'd10, 4'd11: - IF_coreFix_aluExe_0_rsAlu_dispatchData__8084_B_ETC___d18143 = - coreFix_aluExe_0_rsAlu$dispatchData[197:194]; - default: IF_coreFix_aluExe_0_rsAlu_dispatchData__8084_B_ETC___d18143 = - 4'd12; - endcase - end - always@(coreFix_aluExe_0_rsAlu$dispatchData) begin case (coreFix_aluExe_0_rsAlu$dispatchData[193:191]) 3'd2, 3'd3: @@ -43514,6 +43493,16 @@ module mkCore(CLK, 3'd4; endcase end + always@(coreFix_aluExe_0_rsAlu$dispatchData) + begin + case (coreFix_aluExe_0_rsAlu$dispatchData[197:194]) + 4'd7, 4'd8, 4'd9, 4'd10, 4'd11: + IF_coreFix_aluExe_0_rsAlu_dispatchData__8084_B_ETC___d18143 = + coreFix_aluExe_0_rsAlu$dispatchData[197:194]; + default: IF_coreFix_aluExe_0_rsAlu_dispatchData__8084_B_ETC___d18143 = + 4'd12; + endcase + end always@(IF_coreFix_aluExe_0_rsAlu_dispatchData__8084_B_ETC___d18175) begin case (IF_coreFix_aluExe_0_rsAlu_dispatchData__8084_B_ETC___d18175) @@ -43875,10 +43864,10 @@ module mkCore(CLK, 4'd14; endcase end - always@(k__h945030 or + always@(k__h945028 or coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq) begin - case (k__h945030) + case (k__h945028) 1'd0: SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__119_ETC___d21202 = !coreFix_aluExe_0_rsAlu$canEnq; @@ -43898,10 +43887,10 @@ module mkCore(CLK, coreFix_memExe_lsq$enqStTag[6]; endcase end - always@(k__h945030 or + always@(k__h945028 or coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq) begin - case (k__h945030) + case (k__h945028) 1'd0: SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__1191_co_ETC___d21225 = coreFix_aluExe_0_rsAlu$canEnq; @@ -44118,7 +44107,7 @@ module mkCore(CLK, 11'd1194; endcase end - always@(idx__h968880 or + always@(idx__h968878 or fetchStage$pipelines_0_canDeq or NOT_fetchStage_pipelines_0_first__0256_BITS_26_ETC___d21652 or coreFix_aluExe_0_rsAlu$canEnq or @@ -44128,7 +44117,7 @@ module mkCore(CLK, fetchStage_pipelines_0_first__0256_BITS_268_TO_ETC___d21657 or coreFix_aluExe_1_rsAlu$canEnq) begin - case (idx__h968880) + case (idx__h968878) 1'd0: SEL_ARR_fetchStage_pipelines_0_canDeq__0254_AN_ETC___d21680 = fetchStage$pipelines_0_canDeq && @@ -44232,15 +44221,15 @@ module mkCore(CLK, regRenamingTable_rename_1_canRename__1286_AND__ETC___d21642; endcase end - always@(k__h945030 or + always@(k__h945028 or coreFix_aluExe_0_rsAlu$RDY_enq or coreFix_aluExe_1_rsAlu$RDY_enq) begin - case (k__h945030) + case (k__h945028) 1'd0: - CASE_k45030_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q268 = + CASE_k45028_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q268 = coreFix_aluExe_0_rsAlu$RDY_enq; 1'd1: - CASE_k45030_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q268 = + CASE_k45028_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q268 = coreFix_aluExe_1_rsAlu$RDY_enq; endcase end @@ -44258,7 +44247,7 @@ module mkCore(CLK, always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or IF_fetchStage_pipelines_0_first__0256_BITS_265_ETC___d21275 or - regRenamingTable_RDY_rename_0_getRename__1027__ETC___d21854 or + regRenamingTable_RDY_rename_0_getRename__1028__ETC___d21854 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq or coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_enq or regRenamingTable$RDY_rename_0_getRename) @@ -44273,10 +44262,10 @@ module mkCore(CLK, fetchStage$pipelines_0_first[268:266] != 3'd2 || !coreFix_memExe_rsMem$canEnq || IF_fetchStage_pipelines_0_first__0256_BITS_265_ETC___d21275 || - regRenamingTable_RDY_rename_0_getRename__1027__ETC___d21854; + regRenamingTable_RDY_rename_0_getRename__1028__ETC___d21854; endcase end - always@(idx__h968880 or + always@(idx__h968878 or fetchStage$pipelines_0_canDeq or fetchStage$pipelines_0_first or specTagManager$canClaim or @@ -44286,7 +44275,7 @@ module mkCore(CLK, NOT_fetchStage_pipelines_0_first__0256_BITS_26_ETC___d21911 or coreFix_aluExe_1_rsAlu$canEnq) begin - case (idx__h968880) + case (idx__h968878) 1'd0: SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__025_ETC___d21916 = (!fetchStage$pipelines_0_canDeq || @@ -44493,102 +44482,134 @@ module mkCore(CLK, csrf_rg_dcsr[12]; endcase end + always@(commitStage_commitTrap or + _0b0_CONCAT_csrf_mideleg_11_reg_read__6172_6173_ETC___d22645 or + csrf_medeleg_28_26_reg or + _0b0_CONCAT_csrf_medeleg_28_26_reg_read__6161_6_ETC___d22642) + begin + case (commitStage_commitTrap[44:43]) + 2'd0: + CASE_commitStage_commitTrap_BITS_44_TO_43_0_cs_ETC__q276 = + csrf_medeleg_28_26_reg[2]; + 2'd1: + CASE_commitStage_commitTrap_BITS_44_TO_43_0_cs_ETC__q276 = + _0b0_CONCAT_csrf_medeleg_28_26_reg_read__6161_6_ETC___d22642; + default: CASE_commitStage_commitTrap_BITS_44_TO_43_0_cs_ETC__q276 = + _0b0_CONCAT_csrf_mideleg_11_reg_read__6172_6173_ETC___d22645; + endcase + end + always@(commitStage_commitTrap or + _0b0_CONCAT_csrf_mideleg_11_reg_read__6172_6173_ETC___d22645 or + csrf_medeleg_28_26_reg or + _0b0_CONCAT_csrf_medeleg_28_26_reg_read__6161_6_ETC___d22642) + begin + case (commitStage_commitTrap[44:43]) + 2'd0: + CASE_commitStage_commitTrap_BITS_44_TO_43_0_NO_ETC__q277 = + !csrf_medeleg_28_26_reg[2]; + 2'd1: + CASE_commitStage_commitTrap_BITS_44_TO_43_0_NO_ETC__q277 = + !_0b0_CONCAT_csrf_medeleg_28_26_reg_read__6161_6_ETC___d22642; + default: CASE_commitStage_commitTrap_BITS_44_TO_43_0_NO_ETC__q277 = + !_0b0_CONCAT_csrf_mideleg_11_reg_read__6172_6173_ETC___d22645; + endcase + end always@(rob$deqPort_0_deq_data) begin case (rob$deqPort_0_deq_data[287:276]) 12'd1: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd0; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd0; 12'd2: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd1; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd1; 12'd3: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd2; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd2; 12'd256: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd8; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd8; 12'd260: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd9; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd9; 12'd261: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd10; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd10; 12'd262: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd11; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd11; 12'd320: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd12; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd12; 12'd321: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd13; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd13; 12'd322: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd14; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd14; 12'd323: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd15; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd15; 12'd324: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd16; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd16; 12'd384: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd17; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd17; 12'd768: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd19; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd19; 12'd769: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd20; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd20; 12'd770: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd21; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd21; 12'd771: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd22; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd22; 12'd772: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd23; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd23; 12'd773: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd24; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd24; 12'd774: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd25; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd25; 12'd832: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd26; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd26; 12'd833: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd27; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd27; 12'd834: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd28; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd28; 12'd835: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd29; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd29; 12'd836: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd30; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd30; 12'd1952: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd38; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd38; 12'd1953: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd39; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd39; 12'd1954: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd40; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd40; 12'd1955: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd41; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd41; 12'd1968: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd42; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd42; 12'd1969: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd43; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd43; 12'd1970: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd44; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd44; 12'd1971: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd45; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd45; 12'd2048: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd6; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd6; 12'd2049: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd7; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd7; 12'd2496: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd18; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd18; 12'd2816: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd31; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd31; 12'd2818: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd32; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd32; 12'd3008: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd37; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd37; 12'd3072: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd3; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd3; 12'd3073: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd4; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd4; 12'd3074: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd5; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd5; 12'd3857: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd33; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd33; 12'd3858: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd34; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd34; 12'd3859: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd35; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd35; 12'd3860: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd36; - default: IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd36; + default: IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd46; endcase end @@ -44596,26 +44617,26 @@ module mkCore(CLK, begin case (rob$deqPort_0_deq_data[293:289]) 5'd0: - IF_rob_deqPort_0_deq_data__2261_BIT_294_3454_T_ETC___d23476 = 4'd0; + IF_rob_deqPort_0_deq_data__2261_BIT_294_3456_T_ETC___d23478 = 4'd0; 5'd1: - IF_rob_deqPort_0_deq_data__2261_BIT_294_3454_T_ETC___d23476 = 4'd1; + IF_rob_deqPort_0_deq_data__2261_BIT_294_3456_T_ETC___d23478 = 4'd1; 5'd12: - IF_rob_deqPort_0_deq_data__2261_BIT_294_3454_T_ETC___d23476 = 4'd2; + IF_rob_deqPort_0_deq_data__2261_BIT_294_3456_T_ETC___d23478 = 4'd2; 5'd13: - IF_rob_deqPort_0_deq_data__2261_BIT_294_3454_T_ETC___d23476 = 4'd3; + IF_rob_deqPort_0_deq_data__2261_BIT_294_3456_T_ETC___d23478 = 4'd3; 5'd14: - IF_rob_deqPort_0_deq_data__2261_BIT_294_3454_T_ETC___d23476 = 4'd4; + IF_rob_deqPort_0_deq_data__2261_BIT_294_3456_T_ETC___d23478 = 4'd4; 5'd15: - IF_rob_deqPort_0_deq_data__2261_BIT_294_3454_T_ETC___d23476 = 4'd5; + IF_rob_deqPort_0_deq_data__2261_BIT_294_3456_T_ETC___d23478 = 4'd5; 5'd28: - IF_rob_deqPort_0_deq_data__2261_BIT_294_3454_T_ETC___d23476 = 4'd6; + IF_rob_deqPort_0_deq_data__2261_BIT_294_3456_T_ETC___d23478 = 4'd6; 5'd29: - IF_rob_deqPort_0_deq_data__2261_BIT_294_3454_T_ETC___d23476 = 4'd7; + IF_rob_deqPort_0_deq_data__2261_BIT_294_3456_T_ETC___d23478 = 4'd7; 5'd30: - IF_rob_deqPort_0_deq_data__2261_BIT_294_3454_T_ETC___d23476 = 4'd8; + IF_rob_deqPort_0_deq_data__2261_BIT_294_3456_T_ETC___d23478 = 4'd8; 5'd31: - IF_rob_deqPort_0_deq_data__2261_BIT_294_3454_T_ETC___d23476 = 4'd9; - default: IF_rob_deqPort_0_deq_data__2261_BIT_294_3454_T_ETC___d23476 = + IF_rob_deqPort_0_deq_data__2261_BIT_294_3456_T_ETC___d23478 = 4'd9; + default: IF_rob_deqPort_0_deq_data__2261_BIT_294_3456_T_ETC___d23478 = 4'd10; endcase end @@ -44623,8 +44644,8 @@ module mkCore(CLK, begin case (csrf_sepcc_reg_data_rl[52:35]) 18'd262142, 18'd262143: - CASE_csrf_sepcc_reg_data_rl_BITS_52_TO_35_2621_ETC__q276 = 18'd0; - default: CASE_csrf_sepcc_reg_data_rl_BITS_52_TO_35_2621_ETC__q276 = + CASE_csrf_sepcc_reg_data_rl_BITS_52_TO_35_2621_ETC__q278 = 18'd0; + default: CASE_csrf_sepcc_reg_data_rl_BITS_52_TO_35_2621_ETC__q278 = ~csrf_sepcc_reg_data_rl[52:35]; endcase end @@ -44632,8 +44653,8 @@ module mkCore(CLK, begin case (csrf_mepcc_reg_data_rl[52:35]) 18'd262142, 18'd262143: - CASE_csrf_mepcc_reg_data_rl_BITS_52_TO_35_2621_ETC__q277 = 18'd0; - default: CASE_csrf_mepcc_reg_data_rl_BITS_52_TO_35_2621_ETC__q277 = + CASE_csrf_mepcc_reg_data_rl_BITS_52_TO_35_2621_ETC__q279 = 18'd0; + default: CASE_csrf_mepcc_reg_data_rl_BITS_52_TO_35_2621_ETC__q279 = ~csrf_mepcc_reg_data_rl[52:35]; endcase end @@ -44643,10 +44664,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q278 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q280 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[515]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q278 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q280 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[515]; endcase end @@ -44656,10 +44677,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q279 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q281 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[514]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q279 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q281 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[514]; endcase end @@ -44669,10 +44690,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q280 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q282 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[513]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q280 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q282 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[513]; endcase end @@ -44726,19 +44747,6 @@ module mkCore(CLK, coreFix_memExe_forwardQ_data_1[63:0]; endcase end - always@(commitStage_commitTrap or - SEXT__0_CONCAT_IF_INV_commitStage_commitTrap_2_ETC___d22677) - begin - case (commitStage_commitTrap[36:32]) - 5'd0, 5'd3: - trap_val__h996887 = - SEXT__0_CONCAT_IF_INV_commitStage_commitTrap_2_ETC___d22677; - 5'd1, 5'd4, 5'd5, 5'd6, 5'd7, 5'd12, 5'd13, 5'd15: - trap_val__h996887 = commitStage_commitTrap[108:45]; - 5'd2: trap_val__h996887 = { 32'd0, commitStage_commitTrap[31:0] }; - default: trap_val__h996887 = 64'd0; - endcase - end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) @@ -44757,6 +44765,19 @@ module mkCore(CLK, 3'd0; endcase end + always@(commitStage_commitTrap or + SEXT__0_CONCAT_IF_INV_commitStage_commitTrap_2_ETC___d22678) + begin + case (commitStage_commitTrap[36:32]) + 5'd0, 5'd3: + trap_val__h996922 = + SEXT__0_CONCAT_IF_INV_commitStage_commitTrap_2_ETC___d22678; + 5'd1, 5'd4, 5'd5, 5'd6, 5'd7, 5'd12, 5'd13, 5'd15: + trap_val__h996922 = commitStage_commitTrap[108:45]; + 5'd2: trap_val__h996922 = { 32'd0, commitStage_commitTrap[31:0] }; + default: trap_val__h996922 = 64'd0; + endcase + end always@(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq or coreFix_memExe_dMem_cache_m_banks_0_pipeline$first or coreFix_memExe_stb$deq or @@ -44987,35 +45008,35 @@ module mkCore(CLK, begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd4, 3'd3, 3'd2, 3'd1, 3'd0: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q281 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q283 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q281 = 3'd7; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q283 = 3'd7; endcase end always@(coreFix_aluExe_1_regToExeQ$first) begin case (coreFix_aluExe_1_regToExeQ$first[791:789]) 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_791_ETC__q282 = + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_791_ETC__q284 = coreFix_aluExe_1_regToExeQ$first[791:789]; - default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_791_ETC__q282 = 3'd7; + default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_791_ETC__q284 = 3'd7; endcase end always@(coreFix_aluExe_1_regToExeQ$first or - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_791_ETC__q282) + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_791_ETC__q284) begin case (coreFix_aluExe_1_regToExeQ$first[817:815]) 3'd0, 3'd1, 3'd2, 3'd3: - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_817_ETC__q283 = + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_817_ETC__q285 = coreFix_aluExe_1_regToExeQ$first[817:788]; 3'd4: - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_817_ETC__q283 = + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_817_ETC__q285 = { coreFix_aluExe_1_regToExeQ$first[817:815], 18'h2AAAA, coreFix_aluExe_1_regToExeQ$first[796:792], - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_791_ETC__q282, + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_791_ETC__q284, coreFix_aluExe_1_regToExeQ$first[788] }; - default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_817_ETC__q283 = + default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_817_ETC__q285 = 30'd715827882; endcase end @@ -45024,13 +45045,13 @@ module mkCore(CLK, begin case (coreFix_aluExe_1_regToExeQ$first[787:786]) 2'd0: - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_787_ETC__q284 = + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_787_ETC__q286 = coreFix_aluExe_1_regToExeQ$first[787:777]; 2'd1: - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_787_ETC__q284 = + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_787_ETC__q286 = { coreFix_aluExe_1_regToExeQ$first[787:786], IF_coreFix_aluExe_1_regToExeQ_first__7341_BITS_ETC___d17481 }; - default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_787_ETC__q284 = + default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_787_ETC__q286 = 11'd1194; endcase end @@ -45083,9 +45104,9 @@ module mkCore(CLK, 12'd3858, 12'd3859, 12'd3860: - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_728_ETC__q285 = + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_728_ETC__q287 = coreFix_aluExe_1_regToExeQ$first[728:717]; - default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_728_ETC__q285 = + default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_728_ETC__q287 = 12'd2303; endcase end @@ -45093,9 +45114,9 @@ module mkCore(CLK, begin case (coreFix_aluExe_1_regToExeQ$first[715:711]) 5'd0, 5'd1, 5'd12, 5'd13, 5'd14, 5'd15, 5'd28, 5'd29, 5'd30, 5'd31: - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_715_ETC__q286 = + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_715_ETC__q288 = coreFix_aluExe_1_regToExeQ$first[715:711]; - default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_715_ETC__q286 = + default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_715_ETC__q288 = 5'd10; endcase end @@ -45103,26 +45124,26 @@ module mkCore(CLK, begin case (coreFix_aluExe_0_regToExeQ$first[791:789]) 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_791_ETC__q287 = + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_791_ETC__q289 = coreFix_aluExe_0_regToExeQ$first[791:789]; - default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_791_ETC__q287 = 3'd7; + default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_791_ETC__q289 = 3'd7; endcase end always@(coreFix_aluExe_0_regToExeQ$first or - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_791_ETC__q287) + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_791_ETC__q289) begin case (coreFix_aluExe_0_regToExeQ$first[817:815]) 3'd0, 3'd1, 3'd2, 3'd3: - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_817_ETC__q288 = + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_817_ETC__q290 = coreFix_aluExe_0_regToExeQ$first[817:788]; 3'd4: - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_817_ETC__q288 = + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_817_ETC__q290 = { coreFix_aluExe_0_regToExeQ$first[817:815], 18'h2AAAA, coreFix_aluExe_0_regToExeQ$first[796:792], - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_791_ETC__q287, + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_791_ETC__q289, coreFix_aluExe_0_regToExeQ$first[788] }; - default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_817_ETC__q288 = + default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_817_ETC__q290 = 30'd715827882; endcase end @@ -45131,13 +45152,13 @@ module mkCore(CLK, begin case (coreFix_aluExe_0_regToExeQ$first[787:786]) 2'd0: - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_787_ETC__q289 = + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_787_ETC__q291 = coreFix_aluExe_0_regToExeQ$first[787:777]; 2'd1: - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_787_ETC__q289 = + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_787_ETC__q291 = { coreFix_aluExe_0_regToExeQ$first[787:786], IF_coreFix_aluExe_0_regToExeQ_first__9457_BITS_ETC___d19597 }; - default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_787_ETC__q289 = + default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_787_ETC__q291 = 11'd1194; endcase end @@ -45190,9 +45211,9 @@ module mkCore(CLK, 12'd3858, 12'd3859, 12'd3860: - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_728_ETC__q290 = + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_728_ETC__q292 = coreFix_aluExe_0_regToExeQ$first[728:717]; - default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_728_ETC__q290 = + default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_728_ETC__q292 = 12'd2303; endcase end @@ -45200,9 +45221,9 @@ module mkCore(CLK, begin case (coreFix_aluExe_0_regToExeQ$first[715:711]) 5'd0, 5'd1, 5'd12, 5'd13, 5'd14, 5'd15, 5'd28, 5'd29, 5'd30, 5'd31: - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_715_ETC__q291 = + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_715_ETC__q293 = coreFix_aluExe_0_regToExeQ$first[715:711]; - default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_715_ETC__q291 = + default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_715_ETC__q293 = 5'd10; endcase end @@ -45269,9 +45290,9 @@ module mkCore(CLK, 5'd24, 5'd25, 5'd26: - CASE_capChecks_160_BITS_4_TO_0_0_capChecks_160_ETC__q292 = + CASE_capChecks_160_BITS_4_TO_0_0_capChecks_160_ETC__q294 = capChecks___d4160[4:0]; - default: CASE_capChecks_160_BITS_4_TO_0_0_capChecks_160_ETC__q292 = + default: CASE_capChecks_160_BITS_4_TO_0_0_capChecks_160_ETC__q294 = 5'd27; endcase end @@ -45281,10 +45302,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q293 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q295 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[514:451]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q293 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q295 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[514:451]; endcase end @@ -45294,10 +45315,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q294 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q296 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[450:387]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q294 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q296 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[450:387]; endcase end @@ -45307,10 +45328,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q295 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q297 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[386:323]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q295 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q297 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[386:323]; endcase end @@ -45320,10 +45341,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q296 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q298 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[322:259]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q296 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q298 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[322:259]; endcase end @@ -45333,10 +45354,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q297 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q299 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[258:195]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q297 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q299 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[258:195]; endcase end @@ -45346,10 +45367,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q298 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q300 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[194:131]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q298 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q300 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[194:131]; endcase end @@ -45359,10 +45380,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q299 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q301 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[511:448]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q299 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q301 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[511:448]; endcase end @@ -45372,10 +45393,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q300 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q302 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[447:384]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q300 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q302 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[447:384]; endcase end @@ -45385,10 +45406,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q301 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q303 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[383:320]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q301 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q303 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[383:320]; endcase end @@ -45398,10 +45419,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q302 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q304 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[319:256]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q302 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q304 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[319:256]; endcase end @@ -45411,10 +45432,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q303 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q305 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[255:192]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q303 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q305 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[255:192]; endcase end @@ -45424,10 +45445,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q304 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q306 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[191:128]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q304 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q306 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[191:128]; endcase end @@ -45437,10 +45458,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q305 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q307 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[515]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q305 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q307 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[515]; endcase end @@ -45450,10 +45471,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q306 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q308 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[130:67]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q306 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q308 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[130:67]; endcase end @@ -45463,10 +45484,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q307 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q309 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[66:3]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q307 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q309 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[66:3]; endcase end @@ -45476,10 +45497,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q308 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q310 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[512]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q308 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q310 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[512]; endcase end @@ -45489,10 +45510,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q309 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q311 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[127:64]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q309 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q311 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[127:64]; endcase end @@ -45502,10 +45523,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q310 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q312 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[63:0]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q310 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q312 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[63:0]; endcase end @@ -45515,10 +45536,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q311 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q313 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[582:519]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q311 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q313 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[582:519]; endcase end @@ -45528,10 +45549,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q312 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q314 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[518:517]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q312 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q314 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[518:517]; endcase end @@ -45541,10 +45562,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q313 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q315 = !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[516]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q313 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q315 = !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[516]; endcase end @@ -45554,10 +45575,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q314 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q316 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[521:520]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q314 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q316 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[521:520]; endcase end @@ -45567,10 +45588,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q315 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q317 = !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[519]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q315 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q317 = !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[519]; endcase end @@ -45622,10 +45643,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q316 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q318 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[5:4]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q316 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q318 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[5:4]; endcase end @@ -45635,10 +45656,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q317 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q319 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[3]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q317 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q319 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[3]; endcase end @@ -45648,10 +45669,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q318 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q320 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[2:0]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q318 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q320 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[2:0]; endcase end @@ -45661,10 +45682,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q319 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q321 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[71:8]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q319 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q321 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[71:8]; endcase end @@ -45674,10 +45695,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q320 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q322 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[7:6]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q320 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q322 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[7:6]; endcase end @@ -45687,10 +45708,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q321 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q323 = !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[586]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q321 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q323 = !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[586]; endcase end @@ -45700,10 +45721,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q322 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q324 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[586]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q322 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q324 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[586]; endcase end @@ -45711,9 +45732,9 @@ module mkCore(CLK, begin case (rob$deqPort_0_deq_data[264:261]) 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: - CASE_robdeqPort_0_deq_data_BITS_264_TO_261_0__ETC__q323 = + CASE_robdeqPort_0_deq_data_BITS_264_TO_261_0__ETC__q325 = rob$deqPort_0_deq_data[264:261]; - default: CASE_robdeqPort_0_deq_data_BITS_264_TO_261_0__ETC__q323 = + default: CASE_robdeqPort_0_deq_data_BITS_264_TO_261_0__ETC__q325 = 4'd15; endcase end @@ -45743,9 +45764,9 @@ module mkCore(CLK, 5'd24, 5'd25, 5'd26: - CASE_robdeqPort_0_deq_data_BITS_265_TO_261_0__ETC__q324 = + CASE_robdeqPort_0_deq_data_BITS_265_TO_261_0__ETC__q326 = rob$deqPort_0_deq_data[265:261]; - default: CASE_robdeqPort_0_deq_data_BITS_265_TO_261_0__ETC__q324 = + default: CASE_robdeqPort_0_deq_data_BITS_265_TO_261_0__ETC__q326 = 5'd27; endcase end @@ -45766,31 +45787,43 @@ module mkCore(CLK, 5'd12, 5'd13, 5'd15: - CASE_robdeqPort_0_deq_data_BITS_265_TO_261_0__ETC__q325 = + CASE_robdeqPort_0_deq_data_BITS_265_TO_261_0__ETC__q327 = rob$deqPort_0_deq_data[265:261]; - default: CASE_robdeqPort_0_deq_data_BITS_265_TO_261_0__ETC__q325 = + default: CASE_robdeqPort_0_deq_data_BITS_265_TO_261_0__ETC__q327 = 5'd28; endcase end always@(rob$deqPort_0_deq_data or - CASE_robdeqPort_0_deq_data_BITS_264_TO_261_0__ETC__q323 or - CASE_robdeqPort_0_deq_data_BITS_265_TO_261_0__ETC__q324 or - CASE_robdeqPort_0_deq_data_BITS_265_TO_261_0__ETC__q325) + CASE_robdeqPort_0_deq_data_BITS_264_TO_261_0__ETC__q325 or + CASE_robdeqPort_0_deq_data_BITS_265_TO_261_0__ETC__q326 or + CASE_robdeqPort_0_deq_data_BITS_265_TO_261_0__ETC__q327) begin case (rob$deqPort_0_deq_data[273:272]) 2'd0: - CASE_robdeqPort_0_deq_data_BITS_273_TO_272_0__ETC__q326 = + CASE_robdeqPort_0_deq_data_BITS_273_TO_272_0__ETC__q328 = { 2'd0, rob$deqPort_0_deq_data[271:266], - CASE_robdeqPort_0_deq_data_BITS_265_TO_261_0__ETC__q324 }; + CASE_robdeqPort_0_deq_data_BITS_265_TO_261_0__ETC__q326 }; 2'd1: - CASE_robdeqPort_0_deq_data_BITS_273_TO_272_0__ETC__q326 = + CASE_robdeqPort_0_deq_data_BITS_273_TO_272_0__ETC__q328 = { rob$deqPort_0_deq_data[273:272], 6'h2A, - CASE_robdeqPort_0_deq_data_BITS_265_TO_261_0__ETC__q325 }; - default: CASE_robdeqPort_0_deq_data_BITS_273_TO_272_0__ETC__q326 = + CASE_robdeqPort_0_deq_data_BITS_265_TO_261_0__ETC__q327 }; + default: CASE_robdeqPort_0_deq_data_BITS_273_TO_272_0__ETC__q328 = { 9'd298, - CASE_robdeqPort_0_deq_data_BITS_264_TO_261_0__ETC__q323 }; + CASE_robdeqPort_0_deq_data_BITS_264_TO_261_0__ETC__q325 }; + endcase + end + always@(coreFix_memExe_forwardQ_deqP or + coreFix_memExe_forwardQ_data_0 or coreFix_memExe_forwardQ_data_1) + begin + case (coreFix_memExe_forwardQ_deqP) + 1'd0: + CASE_coreFix_memExe_forwardQ_deqP_0_coreFix_me_ETC__q329 = + coreFix_memExe_forwardQ_data_0[128]; + 1'd1: + CASE_coreFix_memExe_forwardQ_deqP_0_coreFix_me_ETC__q329 = + coreFix_memExe_forwardQ_data_1[128]; endcase end always@(coreFix_memExe_memRespLdQ_deqP or @@ -45799,25 +45832,13 @@ module mkCore(CLK, begin case (coreFix_memExe_memRespLdQ_deqP) 1'd0: - CASE_coreFix_memExe_memRespLdQ_deqP_0_coreFix__ETC__q327 = + CASE_coreFix_memExe_memRespLdQ_deqP_0_coreFix__ETC__q330 = coreFix_memExe_memRespLdQ_data_0[128]; 1'd1: - CASE_coreFix_memExe_memRespLdQ_deqP_0_coreFix__ETC__q327 = + CASE_coreFix_memExe_memRespLdQ_deqP_0_coreFix__ETC__q330 = coreFix_memExe_memRespLdQ_data_1[128]; endcase end - always@(coreFix_memExe_forwardQ_deqP or - coreFix_memExe_forwardQ_data_0 or coreFix_memExe_forwardQ_data_1) - begin - case (coreFix_memExe_forwardQ_deqP) - 1'd0: - CASE_coreFix_memExe_forwardQ_deqP_0_coreFix_me_ETC__q328 = - coreFix_memExe_forwardQ_data_0[128]; - 1'd1: - CASE_coreFix_memExe_forwardQ_deqP_0_coreFix_me_ETC__q328 = - coreFix_memExe_forwardQ_data_1[128]; - endcase - end always@(f_csr_reqs$D_OUT) begin case (f_csr_reqs$D_OUT[9:5]) @@ -45844,15 +45865,15 @@ module mkCore(CLK, 5'd24, 5'd25, 5'd26: - CASE_f_csr_reqsD_OUT_BITS_9_TO_5_0_f_csr_reqs_ETC__q329 = + CASE_f_csr_reqsD_OUT_BITS_9_TO_5_0_f_csr_reqs_ETC__q331 = f_csr_reqs$D_OUT[9:5]; - default: CASE_f_csr_reqsD_OUT_BITS_9_TO_5_0_f_csr_reqs_ETC__q329 = + default: CASE_f_csr_reqsD_OUT_BITS_9_TO_5_0_f_csr_reqs_ETC__q331 = 5'd27; endcase end - always@(robdeqPort_0_deq_data_BITS_95_TO_32__q16) + always@(robdeqPort_0_deq_data_BITS_95_TO_32__q17) begin - case (robdeqPort_0_deq_data_BITS_95_TO_32__q16[9:5]) + case (robdeqPort_0_deq_data_BITS_95_TO_32__q17[9:5]) 5'd0, 5'd1, 5'd2, @@ -45876,9 +45897,9 @@ module mkCore(CLK, 5'd24, 5'd25, 5'd26: - CASE_robdeqPort_0_deq_data_BITS_95_TO_326_BITS_ETC__q330 = - robdeqPort_0_deq_data_BITS_95_TO_32__q16[9:5]; - default: CASE_robdeqPort_0_deq_data_BITS_95_TO_326_BITS_ETC__q330 = + CASE_robdeqPort_0_deq_data_BITS_95_TO_327_BITS_ETC__q332 = + robdeqPort_0_deq_data_BITS_95_TO_32__q17[9:5]; + default: CASE_robdeqPort_0_deq_data_BITS_95_TO_327_BITS_ETC__q332 = 5'd27; endcase end @@ -45892,17 +45913,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[123:119]) - 5'd1: thin_addrBits__h858474 = csrf_ddc_reg[85:72]; - 5'd12: thin_addrBits__h858474 = csrf_stcc_reg[85:72]; - 5'd13: thin_addrBits__h858474 = csrf_stdc_reg[85:72]; - 5'd14: thin_addrBits__h858474 = csrf_sScratchC_reg[85:72]; + 5'd1: thin_addrBits__h858473 = csrf_ddc_reg[85:72]; + 5'd12: thin_addrBits__h858473 = csrf_stcc_reg[85:72]; + 5'd13: thin_addrBits__h858473 = csrf_stdc_reg[85:72]; + 5'd14: thin_addrBits__h858473 = csrf_sScratchC_reg[85:72]; 5'd15: - thin_addrBits__h858474 = + thin_addrBits__h858473 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16080; - 5'd28: thin_addrBits__h858474 = csrf_mtcc_reg[85:72]; - 5'd29: thin_addrBits__h858474 = csrf_mtdc_reg[85:72]; - 5'd30: thin_addrBits__h858474 = csrf_mScratchC_reg[85:72]; - default: thin_addrBits__h858474 = + 5'd28: thin_addrBits__h858473 = csrf_mtcc_reg[85:72]; + 5'd29: thin_addrBits__h858473 = csrf_mtdc_reg[85:72]; + 5'd30: thin_addrBits__h858473 = csrf_mScratchC_reg[85:72]; + default: thin_addrBits__h858473 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16232; endcase end @@ -45916,17 +45937,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[123:119]) - 5'd1: thin_addrBits__h899110 = csrf_ddc_reg[85:72]; - 5'd12: thin_addrBits__h899110 = csrf_stcc_reg[85:72]; - 5'd13: thin_addrBits__h899110 = csrf_stdc_reg[85:72]; - 5'd14: thin_addrBits__h899110 = csrf_sScratchC_reg[85:72]; + 5'd1: thin_addrBits__h899108 = csrf_ddc_reg[85:72]; + 5'd12: thin_addrBits__h899108 = csrf_stcc_reg[85:72]; + 5'd13: thin_addrBits__h899108 = csrf_stdc_reg[85:72]; + 5'd14: thin_addrBits__h899108 = csrf_sScratchC_reg[85:72]; 5'd15: - thin_addrBits__h899110 = + thin_addrBits__h899108 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16080; - 5'd28: thin_addrBits__h899110 = csrf_mtcc_reg[85:72]; - 5'd29: thin_addrBits__h899110 = csrf_mtdc_reg[85:72]; - 5'd30: thin_addrBits__h899110 = csrf_mScratchC_reg[85:72]; - default: thin_addrBits__h899110 = + 5'd28: thin_addrBits__h899108 = csrf_mtcc_reg[85:72]; + 5'd29: thin_addrBits__h899108 = csrf_mtdc_reg[85:72]; + 5'd30: thin_addrBits__h899108 = csrf_mScratchC_reg[85:72]; + default: thin_addrBits__h899108 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16232; endcase end @@ -45940,17 +45961,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[123:119]) - 5'd1: thin_bounds_baseBits__h860422 = csrf_ddc_reg[13:0]; - 5'd12: thin_bounds_baseBits__h860422 = csrf_stcc_reg[13:0]; - 5'd13: thin_bounds_baseBits__h860422 = csrf_stdc_reg[13:0]; - 5'd14: thin_bounds_baseBits__h860422 = csrf_sScratchC_reg[13:0]; + 5'd1: thin_bounds_baseBits__h860421 = csrf_ddc_reg[13:0]; + 5'd12: thin_bounds_baseBits__h860421 = csrf_stcc_reg[13:0]; + 5'd13: thin_bounds_baseBits__h860421 = csrf_stdc_reg[13:0]; + 5'd14: thin_bounds_baseBits__h860421 = csrf_sScratchC_reg[13:0]; 5'd15: - thin_bounds_baseBits__h860422 = + thin_bounds_baseBits__h860421 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16084; - 5'd28: thin_bounds_baseBits__h860422 = csrf_mtcc_reg[13:0]; - 5'd29: thin_bounds_baseBits__h860422 = csrf_mtdc_reg[13:0]; - 5'd30: thin_bounds_baseBits__h860422 = csrf_mScratchC_reg[13:0]; - default: thin_bounds_baseBits__h860422 = + 5'd28: thin_bounds_baseBits__h860421 = csrf_mtcc_reg[13:0]; + 5'd29: thin_bounds_baseBits__h860421 = csrf_mtdc_reg[13:0]; + 5'd30: thin_bounds_baseBits__h860421 = csrf_mScratchC_reg[13:0]; + default: thin_bounds_baseBits__h860421 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16236; endcase end @@ -45964,17 +45985,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[123:119]) - 5'd1: thin_bounds_baseBits__h900516 = csrf_ddc_reg[13:0]; - 5'd12: thin_bounds_baseBits__h900516 = csrf_stcc_reg[13:0]; - 5'd13: thin_bounds_baseBits__h900516 = csrf_stdc_reg[13:0]; - 5'd14: thin_bounds_baseBits__h900516 = csrf_sScratchC_reg[13:0]; + 5'd1: thin_bounds_baseBits__h900514 = csrf_ddc_reg[13:0]; + 5'd12: thin_bounds_baseBits__h900514 = csrf_stcc_reg[13:0]; + 5'd13: thin_bounds_baseBits__h900514 = csrf_stdc_reg[13:0]; + 5'd14: thin_bounds_baseBits__h900514 = csrf_sScratchC_reg[13:0]; 5'd15: - thin_bounds_baseBits__h900516 = + thin_bounds_baseBits__h900514 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16084; - 5'd28: thin_bounds_baseBits__h900516 = csrf_mtcc_reg[13:0]; - 5'd29: thin_bounds_baseBits__h900516 = csrf_mtdc_reg[13:0]; - 5'd30: thin_bounds_baseBits__h900516 = csrf_mScratchC_reg[13:0]; - default: thin_bounds_baseBits__h900516 = + 5'd28: thin_bounds_baseBits__h900514 = csrf_mtcc_reg[13:0]; + 5'd29: thin_bounds_baseBits__h900514 = csrf_mtdc_reg[13:0]; + 5'd30: thin_bounds_baseBits__h900514 = csrf_mScratchC_reg[13:0]; + default: thin_bounds_baseBits__h900514 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16236; endcase end @@ -45988,17 +46009,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[123:119]) - 5'd1: thin_address__h858473 = csrf_ddc_reg[151:86]; - 5'd12: thin_address__h858473 = csrf_stcc_reg[151:86]; - 5'd13: thin_address__h858473 = csrf_stdc_reg[151:86]; - 5'd14: thin_address__h858473 = csrf_sScratchC_reg[151:86]; + 5'd1: thin_address__h858472 = csrf_ddc_reg[151:86]; + 5'd12: thin_address__h858472 = csrf_stcc_reg[151:86]; + 5'd13: thin_address__h858472 = csrf_stdc_reg[151:86]; + 5'd14: thin_address__h858472 = csrf_sScratchC_reg[151:86]; 5'd15: - thin_address__h858473 = + thin_address__h858472 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16104; - 5'd28: thin_address__h858473 = csrf_mtcc_reg[151:86]; - 5'd29: thin_address__h858473 = csrf_mtdc_reg[151:86]; - 5'd30: thin_address__h858473 = csrf_mScratchC_reg[151:86]; - default: thin_address__h858473 = + 5'd28: thin_address__h858472 = csrf_mtcc_reg[151:86]; + 5'd29: thin_address__h858472 = csrf_mtdc_reg[151:86]; + 5'd30: thin_address__h858472 = csrf_mScratchC_reg[151:86]; + default: thin_address__h858472 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16256; endcase end @@ -46012,289 +46033,289 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[123:119]) - 5'd1: thin_address__h899109 = csrf_ddc_reg[151:86]; - 5'd12: thin_address__h899109 = csrf_stcc_reg[151:86]; - 5'd13: thin_address__h899109 = csrf_stdc_reg[151:86]; - 5'd14: thin_address__h899109 = csrf_sScratchC_reg[151:86]; + 5'd1: thin_address__h899107 = csrf_ddc_reg[151:86]; + 5'd12: thin_address__h899107 = csrf_stcc_reg[151:86]; + 5'd13: thin_address__h899107 = csrf_stdc_reg[151:86]; + 5'd14: thin_address__h899107 = csrf_sScratchC_reg[151:86]; 5'd15: - thin_address__h899109 = + thin_address__h899107 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16104; - 5'd28: thin_address__h899109 = csrf_mtcc_reg[151:86]; - 5'd29: thin_address__h899109 = csrf_mtdc_reg[151:86]; - 5'd30: thin_address__h899109 = csrf_mScratchC_reg[151:86]; - default: thin_address__h899109 = + 5'd28: thin_address__h899107 = csrf_mtcc_reg[151:86]; + 5'd29: thin_address__h899107 = csrf_mtdc_reg[151:86]; + 5'd30: thin_address__h899107 = csrf_mScratchC_reg[151:86]; + default: thin_address__h899107 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16256; endcase end always@(f_csr_reqs$D_OUT or - fflags_csr__read__h849194 or - frm_csr__read__h849205 or - fcsr_csr__read__h849219 or - sstatus_csr__read__h849415 or - sie_csr__read__h849485 or + fflags_csr__read__h849193 or + frm_csr__read__h849204 or + fcsr_csr__read__h849218 or + sstatus_csr__read__h849414 or + sie_csr__read__h849484 or SEXT__0_CONCAT_csrf_stcc_reg_read__6046_BITS_8_ETC___d16070 or - scounteren_csr__read__h849573 or + scounteren_csr__read__h849572 or csrf_sscratch_csr or SEXT__0_CONCAT_IF_csrf_sepcc_reg_data_lat_0_wh_ETC___d16109 or - scause_csr__read__h849713 or + scause_csr__read__h849712 or csrf_stval_csr or - sip_csr__read__h849853 or - satp_csr__read__h849916 or - mstatus_csr__read__h850062 or - medeleg_csr__read__h850223 or - mideleg_csr__read__h850321 or - mie_csr__read__h850448 or + sip_csr__read__h849852 or + satp_csr__read__h849915 or + mstatus_csr__read__h850061 or + medeleg_csr__read__h850222 or + mideleg_csr__read__h850320 or + mie_csr__read__h850447 or SEXT__0_CONCAT_csrf_mtcc_reg_read__6198_BITS_8_ETC___d16222 or - mcounteren_csr__read__h850620 or + mcounteren_csr__read__h850619 or csrf_mscratch_csr or SEXT__0_CONCAT_IF_csrf_mepcc_reg_data_lat_0_wh_ETC___d16261 or - mcause_csr__read__h850886 or + mcause_csr__read__h850885 or csrf_mtval_csr or - mip_csr__read__h851125 or + mip_csr__read__h851124 or csrf_rg_tselect or - rg_tdata1__read__h852226 or + rg_tdata1__read__h852225 or csrf_rg_tdata2 or csrf_rg_tdata3 or csrf_rg_dcsr or SEXT__0_CONCAT_csrf_rg_dpc_read__6343_BITS_85__ETC___d16367 or csrf_rg_dscratch0 or csrf_rg_dscratch1 or - x_reg_ifc__read__h849324 or + x_reg_ifc__read__h849323 or csrf_mcycle_ehr_data_rl or - csrf_minstret_ehr_data_rl or x__h896542 or csrf_time_reg) + csrf_minstret_ehr_data_rl or x__h896540 or csrf_time_reg) begin case (f_csr_reqs$D_OUT[75:64]) - 12'd1: data_out__h1019990 = fflags_csr__read__h849194; - 12'd2: data_out__h1019990 = frm_csr__read__h849205; - 12'd3: data_out__h1019990 = fcsr_csr__read__h849219; - 12'd256: data_out__h1019990 = sstatus_csr__read__h849415; - 12'd260: data_out__h1019990 = sie_csr__read__h849485; + 12'd1: data_out__h1020024 = fflags_csr__read__h849193; + 12'd2: data_out__h1020024 = frm_csr__read__h849204; + 12'd3: data_out__h1020024 = fcsr_csr__read__h849218; + 12'd256: data_out__h1020024 = sstatus_csr__read__h849414; + 12'd260: data_out__h1020024 = sie_csr__read__h849484; 12'd261: - data_out__h1019990 = + data_out__h1020024 = SEXT__0_CONCAT_csrf_stcc_reg_read__6046_BITS_8_ETC___d16070; - 12'd262: data_out__h1019990 = scounteren_csr__read__h849573; - 12'd320: data_out__h1019990 = csrf_sscratch_csr; + 12'd262: data_out__h1020024 = scounteren_csr__read__h849572; + 12'd320: data_out__h1020024 = csrf_sscratch_csr; 12'd321: - data_out__h1019990 = + data_out__h1020024 = SEXT__0_CONCAT_IF_csrf_sepcc_reg_data_lat_0_wh_ETC___d16109; - 12'd322: data_out__h1019990 = scause_csr__read__h849713; - 12'd323: data_out__h1019990 = csrf_stval_csr; - 12'd324: data_out__h1019990 = sip_csr__read__h849853; - 12'd384: data_out__h1019990 = satp_csr__read__h849916; - 12'd768: data_out__h1019990 = mstatus_csr__read__h850062; - 12'd769: data_out__h1019990 = 64'h800000000014112D; - 12'd770: data_out__h1019990 = medeleg_csr__read__h850223; - 12'd771: data_out__h1019990 = mideleg_csr__read__h850321; - 12'd772: data_out__h1019990 = mie_csr__read__h850448; + 12'd322: data_out__h1020024 = scause_csr__read__h849712; + 12'd323: data_out__h1020024 = csrf_stval_csr; + 12'd324: data_out__h1020024 = sip_csr__read__h849852; + 12'd384: data_out__h1020024 = satp_csr__read__h849915; + 12'd768: data_out__h1020024 = mstatus_csr__read__h850061; + 12'd769: data_out__h1020024 = 64'h800000000014112D; + 12'd770: data_out__h1020024 = medeleg_csr__read__h850222; + 12'd771: data_out__h1020024 = mideleg_csr__read__h850320; + 12'd772: data_out__h1020024 = mie_csr__read__h850447; 12'd773: - data_out__h1019990 = + data_out__h1020024 = SEXT__0_CONCAT_csrf_mtcc_reg_read__6198_BITS_8_ETC___d16222; - 12'd774: data_out__h1019990 = mcounteren_csr__read__h850620; - 12'd832: data_out__h1019990 = csrf_mscratch_csr; + 12'd774: data_out__h1020024 = mcounteren_csr__read__h850619; + 12'd832: data_out__h1020024 = csrf_mscratch_csr; 12'd833: - data_out__h1019990 = + data_out__h1020024 = SEXT__0_CONCAT_IF_csrf_mepcc_reg_data_lat_0_wh_ETC___d16261; - 12'd834: data_out__h1019990 = mcause_csr__read__h850886; - 12'd835: data_out__h1019990 = csrf_mtval_csr; - 12'd836: data_out__h1019990 = mip_csr__read__h851125; - 12'd1952: data_out__h1019990 = csrf_rg_tselect; - 12'd1953: data_out__h1019990 = rg_tdata1__read__h852226; - 12'd1954: data_out__h1019990 = csrf_rg_tdata2; - 12'd1955: data_out__h1019990 = csrf_rg_tdata3; - 12'd1968: data_out__h1019990 = csrf_rg_dcsr; + 12'd834: data_out__h1020024 = mcause_csr__read__h850885; + 12'd835: data_out__h1020024 = csrf_mtval_csr; + 12'd836: data_out__h1020024 = mip_csr__read__h851124; + 12'd1952: data_out__h1020024 = csrf_rg_tselect; + 12'd1953: data_out__h1020024 = rg_tdata1__read__h852225; + 12'd1954: data_out__h1020024 = csrf_rg_tdata2; + 12'd1955: data_out__h1020024 = csrf_rg_tdata3; + 12'd1968: data_out__h1020024 = csrf_rg_dcsr; 12'd1969: - data_out__h1019990 = + data_out__h1020024 = SEXT__0_CONCAT_csrf_rg_dpc_read__6343_BITS_85__ETC___d16367; - 12'd1970: data_out__h1019990 = csrf_rg_dscratch0; - 12'd1971: data_out__h1019990 = csrf_rg_dscratch1; + 12'd1970: data_out__h1020024 = csrf_rg_dscratch0; + 12'd1971: data_out__h1020024 = csrf_rg_dscratch1; 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: - data_out__h1019990 = 64'd0; - 12'd2049: data_out__h1019990 = x_reg_ifc__read__h849324; - 12'd2816, 12'd3072: data_out__h1019990 = csrf_mcycle_ehr_data_rl; - 12'd2818, 12'd3074: data_out__h1019990 = csrf_minstret_ehr_data_rl; - 12'd3008: data_out__h1019990 = { 48'd0, x__h896542 }; - 12'd3073: data_out__h1019990 = csrf_time_reg; - default: data_out__h1019990 = 64'b0; + data_out__h1020024 = 64'd0; + 12'd2049: data_out__h1020024 = x_reg_ifc__read__h849323; + 12'd2816, 12'd3072: data_out__h1020024 = csrf_mcycle_ehr_data_rl; + 12'd2818, 12'd3074: data_out__h1020024 = csrf_minstret_ehr_data_rl; + 12'd3008: data_out__h1020024 = { 48'd0, x__h896540 }; + 12'd3073: data_out__h1020024 = csrf_time_reg; + default: data_out__h1020024 = 64'b0; endcase end always@(coreFix_aluExe_1_dispToRegQ$first or - fflags_csr__read__h849194 or - frm_csr__read__h849205 or - fcsr_csr__read__h849219 or - sstatus_csr__read__h849415 or - sie_csr__read__h849485 or + fflags_csr__read__h849193 or + frm_csr__read__h849204 or + fcsr_csr__read__h849218 or + sstatus_csr__read__h849414 or + sie_csr__read__h849484 or SEXT__0_CONCAT_csrf_stcc_reg_read__6046_BITS_8_ETC___d16070 or - scounteren_csr__read__h849573 or + scounteren_csr__read__h849572 or csrf_sscratch_csr or SEXT__0_CONCAT_IF_csrf_sepcc_reg_data_lat_0_wh_ETC___d16109 or - scause_csr__read__h849713 or + scause_csr__read__h849712 or csrf_stval_csr or - sip_csr__read__h849853 or - satp_csr__read__h849916 or - mstatus_csr__read__h850062 or - medeleg_csr__read__h850223 or - mideleg_csr__read__h850321 or - mie_csr__read__h850448 or + sip_csr__read__h849852 or + satp_csr__read__h849915 or + mstatus_csr__read__h850061 or + medeleg_csr__read__h850222 or + mideleg_csr__read__h850320 or + mie_csr__read__h850447 or SEXT__0_CONCAT_csrf_mtcc_reg_read__6198_BITS_8_ETC___d16222 or - mcounteren_csr__read__h850620 or + mcounteren_csr__read__h850619 or csrf_mscratch_csr or SEXT__0_CONCAT_IF_csrf_mepcc_reg_data_lat_0_wh_ETC___d16261 or - mcause_csr__read__h850886 or + mcause_csr__read__h850885 or csrf_mtval_csr or - mip_csr__read__h851125 or + mip_csr__read__h851124 or csrf_rg_tselect or - rg_tdata1__read__h852226 or + rg_tdata1__read__h852225 or csrf_rg_tdata2 or csrf_rg_tdata3 or csrf_rg_dcsr or SEXT__0_CONCAT_csrf_rg_dpc_read__6343_BITS_85__ETC___d16367 or csrf_rg_dscratch0 or csrf_rg_dscratch1 or - x_reg_ifc__read__h849324 or + x_reg_ifc__read__h849323 or csrf_mcycle_ehr_data_rl or - csrf_minstret_ehr_data_rl or x__h896542 or csrf_time_reg) + csrf_minstret_ehr_data_rl or x__h896540 or csrf_time_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[136:125]) - 12'd1: addr__h843950 = fflags_csr__read__h849194; - 12'd2: addr__h843950 = frm_csr__read__h849205; - 12'd3: addr__h843950 = fcsr_csr__read__h849219; - 12'd256: addr__h843950 = sstatus_csr__read__h849415; - 12'd260: addr__h843950 = sie_csr__read__h849485; + 12'd1: addr__h843948 = fflags_csr__read__h849193; + 12'd2: addr__h843948 = frm_csr__read__h849204; + 12'd3: addr__h843948 = fcsr_csr__read__h849218; + 12'd256: addr__h843948 = sstatus_csr__read__h849414; + 12'd260: addr__h843948 = sie_csr__read__h849484; 12'd261: - addr__h843950 = + addr__h843948 = SEXT__0_CONCAT_csrf_stcc_reg_read__6046_BITS_8_ETC___d16070; - 12'd262: addr__h843950 = scounteren_csr__read__h849573; - 12'd320: addr__h843950 = csrf_sscratch_csr; + 12'd262: addr__h843948 = scounteren_csr__read__h849572; + 12'd320: addr__h843948 = csrf_sscratch_csr; 12'd321: - addr__h843950 = + addr__h843948 = SEXT__0_CONCAT_IF_csrf_sepcc_reg_data_lat_0_wh_ETC___d16109; - 12'd322: addr__h843950 = scause_csr__read__h849713; - 12'd323: addr__h843950 = csrf_stval_csr; - 12'd324: addr__h843950 = sip_csr__read__h849853; - 12'd384: addr__h843950 = satp_csr__read__h849916; - 12'd768: addr__h843950 = mstatus_csr__read__h850062; - 12'd769: addr__h843950 = 64'h800000000014112D; - 12'd770: addr__h843950 = medeleg_csr__read__h850223; - 12'd771: addr__h843950 = mideleg_csr__read__h850321; - 12'd772: addr__h843950 = mie_csr__read__h850448; + 12'd322: addr__h843948 = scause_csr__read__h849712; + 12'd323: addr__h843948 = csrf_stval_csr; + 12'd324: addr__h843948 = sip_csr__read__h849852; + 12'd384: addr__h843948 = satp_csr__read__h849915; + 12'd768: addr__h843948 = mstatus_csr__read__h850061; + 12'd769: addr__h843948 = 64'h800000000014112D; + 12'd770: addr__h843948 = medeleg_csr__read__h850222; + 12'd771: addr__h843948 = mideleg_csr__read__h850320; + 12'd772: addr__h843948 = mie_csr__read__h850447; 12'd773: - addr__h843950 = + addr__h843948 = SEXT__0_CONCAT_csrf_mtcc_reg_read__6198_BITS_8_ETC___d16222; - 12'd774: addr__h843950 = mcounteren_csr__read__h850620; - 12'd832: addr__h843950 = csrf_mscratch_csr; + 12'd774: addr__h843948 = mcounteren_csr__read__h850619; + 12'd832: addr__h843948 = csrf_mscratch_csr; 12'd833: - addr__h843950 = + addr__h843948 = SEXT__0_CONCAT_IF_csrf_mepcc_reg_data_lat_0_wh_ETC___d16261; - 12'd834: addr__h843950 = mcause_csr__read__h850886; - 12'd835: addr__h843950 = csrf_mtval_csr; - 12'd836: addr__h843950 = mip_csr__read__h851125; - 12'd1952: addr__h843950 = csrf_rg_tselect; - 12'd1953: addr__h843950 = rg_tdata1__read__h852226; - 12'd1954: addr__h843950 = csrf_rg_tdata2; - 12'd1955: addr__h843950 = csrf_rg_tdata3; - 12'd1968: addr__h843950 = csrf_rg_dcsr; + 12'd834: addr__h843948 = mcause_csr__read__h850885; + 12'd835: addr__h843948 = csrf_mtval_csr; + 12'd836: addr__h843948 = mip_csr__read__h851124; + 12'd1952: addr__h843948 = csrf_rg_tselect; + 12'd1953: addr__h843948 = rg_tdata1__read__h852225; + 12'd1954: addr__h843948 = csrf_rg_tdata2; + 12'd1955: addr__h843948 = csrf_rg_tdata3; + 12'd1968: addr__h843948 = csrf_rg_dcsr; 12'd1969: - addr__h843950 = + addr__h843948 = SEXT__0_CONCAT_csrf_rg_dpc_read__6343_BITS_85__ETC___d16367; - 12'd1970: addr__h843950 = csrf_rg_dscratch0; - 12'd1971: addr__h843950 = csrf_rg_dscratch1; - 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: addr__h843950 = 64'd0; - 12'd2049: addr__h843950 = x_reg_ifc__read__h849324; - 12'd2816, 12'd3072: addr__h843950 = csrf_mcycle_ehr_data_rl; - 12'd2818, 12'd3074: addr__h843950 = csrf_minstret_ehr_data_rl; - 12'd3008: addr__h843950 = { 48'd0, x__h896542 }; - 12'd3073: addr__h843950 = csrf_time_reg; - default: addr__h843950 = 64'b0; + 12'd1970: addr__h843948 = csrf_rg_dscratch0; + 12'd1971: addr__h843948 = csrf_rg_dscratch1; + 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: addr__h843948 = 64'd0; + 12'd2049: addr__h843948 = x_reg_ifc__read__h849323; + 12'd2816, 12'd3072: addr__h843948 = csrf_mcycle_ehr_data_rl; + 12'd2818, 12'd3074: addr__h843948 = csrf_minstret_ehr_data_rl; + 12'd3008: addr__h843948 = { 48'd0, x__h896540 }; + 12'd3073: addr__h843948 = csrf_time_reg; + default: addr__h843948 = 64'b0; endcase end always@(coreFix_aluExe_0_dispToRegQ$first or - fflags_csr__read__h849194 or - frm_csr__read__h849205 or - fcsr_csr__read__h849219 or - sstatus_csr__read__h849415 or - sie_csr__read__h849485 or + fflags_csr__read__h849193 or + frm_csr__read__h849204 or + fcsr_csr__read__h849218 or + sstatus_csr__read__h849414 or + sie_csr__read__h849484 or SEXT__0_CONCAT_csrf_stcc_reg_read__6046_BITS_8_ETC___d16070 or - scounteren_csr__read__h849573 or + scounteren_csr__read__h849572 or csrf_sscratch_csr or SEXT__0_CONCAT_IF_csrf_sepcc_reg_data_lat_0_wh_ETC___d16109 or - scause_csr__read__h849713 or + scause_csr__read__h849712 or csrf_stval_csr or - sip_csr__read__h849853 or - satp_csr__read__h849916 or - mstatus_csr__read__h850062 or - medeleg_csr__read__h850223 or - mideleg_csr__read__h850321 or - mie_csr__read__h850448 or + sip_csr__read__h849852 or + satp_csr__read__h849915 or + mstatus_csr__read__h850061 or + medeleg_csr__read__h850222 or + mideleg_csr__read__h850320 or + mie_csr__read__h850447 or SEXT__0_CONCAT_csrf_mtcc_reg_read__6198_BITS_8_ETC___d16222 or - mcounteren_csr__read__h850620 or + mcounteren_csr__read__h850619 or csrf_mscratch_csr or SEXT__0_CONCAT_IF_csrf_mepcc_reg_data_lat_0_wh_ETC___d16261 or - mcause_csr__read__h850886 or + mcause_csr__read__h850885 or csrf_mtval_csr or - mip_csr__read__h851125 or + mip_csr__read__h851124 or csrf_rg_tselect or - rg_tdata1__read__h852226 or + rg_tdata1__read__h852225 or csrf_rg_tdata2 or csrf_rg_tdata3 or csrf_rg_dcsr or SEXT__0_CONCAT_csrf_rg_dpc_read__6343_BITS_85__ETC___d16367 or csrf_rg_dscratch0 or csrf_rg_dscratch1 or - x_reg_ifc__read__h849324 or + x_reg_ifc__read__h849323 or csrf_mcycle_ehr_data_rl or - csrf_minstret_ehr_data_rl or x__h896542 or csrf_time_reg) + csrf_minstret_ehr_data_rl or x__h896540 or csrf_time_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[136:125]) - 12'd1: addr__h887459 = fflags_csr__read__h849194; - 12'd2: addr__h887459 = frm_csr__read__h849205; - 12'd3: addr__h887459 = fcsr_csr__read__h849219; - 12'd256: addr__h887459 = sstatus_csr__read__h849415; - 12'd260: addr__h887459 = sie_csr__read__h849485; + 12'd1: addr__h887458 = fflags_csr__read__h849193; + 12'd2: addr__h887458 = frm_csr__read__h849204; + 12'd3: addr__h887458 = fcsr_csr__read__h849218; + 12'd256: addr__h887458 = sstatus_csr__read__h849414; + 12'd260: addr__h887458 = sie_csr__read__h849484; 12'd261: - addr__h887459 = + addr__h887458 = SEXT__0_CONCAT_csrf_stcc_reg_read__6046_BITS_8_ETC___d16070; - 12'd262: addr__h887459 = scounteren_csr__read__h849573; - 12'd320: addr__h887459 = csrf_sscratch_csr; + 12'd262: addr__h887458 = scounteren_csr__read__h849572; + 12'd320: addr__h887458 = csrf_sscratch_csr; 12'd321: - addr__h887459 = + addr__h887458 = SEXT__0_CONCAT_IF_csrf_sepcc_reg_data_lat_0_wh_ETC___d16109; - 12'd322: addr__h887459 = scause_csr__read__h849713; - 12'd323: addr__h887459 = csrf_stval_csr; - 12'd324: addr__h887459 = sip_csr__read__h849853; - 12'd384: addr__h887459 = satp_csr__read__h849916; - 12'd768: addr__h887459 = mstatus_csr__read__h850062; - 12'd769: addr__h887459 = 64'h800000000014112D; - 12'd770: addr__h887459 = medeleg_csr__read__h850223; - 12'd771: addr__h887459 = mideleg_csr__read__h850321; - 12'd772: addr__h887459 = mie_csr__read__h850448; + 12'd322: addr__h887458 = scause_csr__read__h849712; + 12'd323: addr__h887458 = csrf_stval_csr; + 12'd324: addr__h887458 = sip_csr__read__h849852; + 12'd384: addr__h887458 = satp_csr__read__h849915; + 12'd768: addr__h887458 = mstatus_csr__read__h850061; + 12'd769: addr__h887458 = 64'h800000000014112D; + 12'd770: addr__h887458 = medeleg_csr__read__h850222; + 12'd771: addr__h887458 = mideleg_csr__read__h850320; + 12'd772: addr__h887458 = mie_csr__read__h850447; 12'd773: - addr__h887459 = + addr__h887458 = SEXT__0_CONCAT_csrf_mtcc_reg_read__6198_BITS_8_ETC___d16222; - 12'd774: addr__h887459 = mcounteren_csr__read__h850620; - 12'd832: addr__h887459 = csrf_mscratch_csr; + 12'd774: addr__h887458 = mcounteren_csr__read__h850619; + 12'd832: addr__h887458 = csrf_mscratch_csr; 12'd833: - addr__h887459 = + addr__h887458 = SEXT__0_CONCAT_IF_csrf_mepcc_reg_data_lat_0_wh_ETC___d16261; - 12'd834: addr__h887459 = mcause_csr__read__h850886; - 12'd835: addr__h887459 = csrf_mtval_csr; - 12'd836: addr__h887459 = mip_csr__read__h851125; - 12'd1952: addr__h887459 = csrf_rg_tselect; - 12'd1953: addr__h887459 = rg_tdata1__read__h852226; - 12'd1954: addr__h887459 = csrf_rg_tdata2; - 12'd1955: addr__h887459 = csrf_rg_tdata3; - 12'd1968: addr__h887459 = csrf_rg_dcsr; + 12'd834: addr__h887458 = mcause_csr__read__h850885; + 12'd835: addr__h887458 = csrf_mtval_csr; + 12'd836: addr__h887458 = mip_csr__read__h851124; + 12'd1952: addr__h887458 = csrf_rg_tselect; + 12'd1953: addr__h887458 = rg_tdata1__read__h852225; + 12'd1954: addr__h887458 = csrf_rg_tdata2; + 12'd1955: addr__h887458 = csrf_rg_tdata3; + 12'd1968: addr__h887458 = csrf_rg_dcsr; 12'd1969: - addr__h887459 = + addr__h887458 = SEXT__0_CONCAT_csrf_rg_dpc_read__6343_BITS_85__ETC___d16367; - 12'd1970: addr__h887459 = csrf_rg_dscratch0; - 12'd1971: addr__h887459 = csrf_rg_dscratch1; - 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: addr__h887459 = 64'd0; - 12'd2049: addr__h887459 = x_reg_ifc__read__h849324; - 12'd2816, 12'd3072: addr__h887459 = csrf_mcycle_ehr_data_rl; - 12'd2818, 12'd3074: addr__h887459 = csrf_minstret_ehr_data_rl; - 12'd3008: addr__h887459 = { 48'd0, x__h896542 }; - 12'd3073: addr__h887459 = csrf_time_reg; - default: addr__h887459 = 64'b0; + 12'd1970: addr__h887458 = csrf_rg_dscratch0; + 12'd1971: addr__h887458 = csrf_rg_dscratch1; + 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: addr__h887458 = 64'd0; + 12'd2049: addr__h887458 = x_reg_ifc__read__h849323; + 12'd2816, 12'd3072: addr__h887458 = csrf_mcycle_ehr_data_rl; + 12'd2818, 12'd3074: addr__h887458 = csrf_minstret_ehr_data_rl; + 12'd3008: addr__h887458 = { 48'd0, x__h896540 }; + 12'd3073: addr__h887458 = csrf_time_reg; + default: addr__h887458 = 64'b0; endcase end always@(coreFix_aluExe_1_dispToRegQ$first or @@ -46877,17 +46898,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[123:119]) - 5'd1: thin_reserved__h858477 = csrf_ddc_reg[54:53]; - 5'd12: thin_reserved__h858477 = csrf_stcc_reg[54:53]; - 5'd13: thin_reserved__h858477 = csrf_stdc_reg[54:53]; - 5'd14: thin_reserved__h858477 = csrf_sScratchC_reg[54:53]; + 5'd1: thin_reserved__h858476 = csrf_ddc_reg[54:53]; + 5'd12: thin_reserved__h858476 = csrf_stcc_reg[54:53]; + 5'd13: thin_reserved__h858476 = csrf_stdc_reg[54:53]; + 5'd14: thin_reserved__h858476 = csrf_sScratchC_reg[54:53]; 5'd15: - thin_reserved__h858477 = + thin_reserved__h858476 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17176; - 5'd28: thin_reserved__h858477 = csrf_mtcc_reg[54:53]; - 5'd29: thin_reserved__h858477 = csrf_mtdc_reg[54:53]; - 5'd30: thin_reserved__h858477 = csrf_mScratchC_reg[54:53]; - default: thin_reserved__h858477 = + 5'd28: thin_reserved__h858476 = csrf_mtcc_reg[54:53]; + 5'd29: thin_reserved__h858476 = csrf_mtdc_reg[54:53]; + 5'd30: thin_reserved__h858476 = csrf_mScratchC_reg[54:53]; + default: thin_reserved__h858476 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17182; endcase end @@ -46901,17 +46922,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[123:119]) - 5'd1: thin_reserved__h899113 = csrf_ddc_reg[54:53]; - 5'd12: thin_reserved__h899113 = csrf_stcc_reg[54:53]; - 5'd13: thin_reserved__h899113 = csrf_stdc_reg[54:53]; - 5'd14: thin_reserved__h899113 = csrf_sScratchC_reg[54:53]; + 5'd1: thin_reserved__h899111 = csrf_ddc_reg[54:53]; + 5'd12: thin_reserved__h899111 = csrf_stcc_reg[54:53]; + 5'd13: thin_reserved__h899111 = csrf_stdc_reg[54:53]; + 5'd14: thin_reserved__h899111 = csrf_sScratchC_reg[54:53]; 5'd15: - thin_reserved__h899113 = + thin_reserved__h899111 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17176; - 5'd28: thin_reserved__h899113 = csrf_mtcc_reg[54:53]; - 5'd29: thin_reserved__h899113 = csrf_mtdc_reg[54:53]; - 5'd30: thin_reserved__h899113 = csrf_mScratchC_reg[54:53]; - default: thin_reserved__h899113 = + 5'd28: thin_reserved__h899111 = csrf_mtcc_reg[54:53]; + 5'd29: thin_reserved__h899111 = csrf_mtdc_reg[54:53]; + 5'd30: thin_reserved__h899111 = csrf_mScratchC_reg[54:53]; + default: thin_reserved__h899111 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17182; endcase end @@ -46925,17 +46946,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[123:119]) - 5'd1: thin_perms_soft__h858713 = csrf_ddc_reg[71:68]; - 5'd12: thin_perms_soft__h858713 = csrf_stcc_reg[71:68]; - 5'd13: thin_perms_soft__h858713 = csrf_stdc_reg[71:68]; - 5'd14: thin_perms_soft__h858713 = csrf_sScratchC_reg[71:68]; + 5'd1: thin_perms_soft__h858712 = csrf_ddc_reg[71:68]; + 5'd12: thin_perms_soft__h858712 = csrf_stcc_reg[71:68]; + 5'd13: thin_perms_soft__h858712 = csrf_stdc_reg[71:68]; + 5'd14: thin_perms_soft__h858712 = csrf_sScratchC_reg[71:68]; 5'd15: - thin_perms_soft__h858713 = + thin_perms_soft__h858712 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16862; - 5'd28: thin_perms_soft__h858713 = csrf_mtcc_reg[71:68]; - 5'd29: thin_perms_soft__h858713 = csrf_mtdc_reg[71:68]; - 5'd30: thin_perms_soft__h858713 = csrf_mScratchC_reg[71:68]; - default: thin_perms_soft__h858713 = + 5'd28: thin_perms_soft__h858712 = csrf_mtcc_reg[71:68]; + 5'd29: thin_perms_soft__h858712 = csrf_mtdc_reg[71:68]; + 5'd30: thin_perms_soft__h858712 = csrf_mScratchC_reg[71:68]; + default: thin_perms_soft__h858712 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16868; endcase end @@ -46949,17 +46970,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[123:119]) - 5'd1: thin_perms_soft__h899289 = csrf_ddc_reg[71:68]; - 5'd12: thin_perms_soft__h899289 = csrf_stcc_reg[71:68]; - 5'd13: thin_perms_soft__h899289 = csrf_stdc_reg[71:68]; - 5'd14: thin_perms_soft__h899289 = csrf_sScratchC_reg[71:68]; + 5'd1: thin_perms_soft__h899287 = csrf_ddc_reg[71:68]; + 5'd12: thin_perms_soft__h899287 = csrf_stcc_reg[71:68]; + 5'd13: thin_perms_soft__h899287 = csrf_stdc_reg[71:68]; + 5'd14: thin_perms_soft__h899287 = csrf_sScratchC_reg[71:68]; 5'd15: - thin_perms_soft__h899289 = + thin_perms_soft__h899287 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16862; - 5'd28: thin_perms_soft__h899289 = csrf_mtcc_reg[71:68]; - 5'd29: thin_perms_soft__h899289 = csrf_mtdc_reg[71:68]; - 5'd30: thin_perms_soft__h899289 = csrf_mScratchC_reg[71:68]; - default: thin_perms_soft__h899289 = + 5'd28: thin_perms_soft__h899287 = csrf_mtcc_reg[71:68]; + 5'd29: thin_perms_soft__h899287 = csrf_mtdc_reg[71:68]; + 5'd30: thin_perms_soft__h899287 = csrf_mScratchC_reg[71:68]; + default: thin_perms_soft__h899287 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16868; endcase end @@ -46973,17 +46994,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[123:119]) - 5'd1: thin_bounds_topBits__h860421 = csrf_ddc_reg[27:14]; - 5'd12: thin_bounds_topBits__h860421 = csrf_stcc_reg[27:14]; - 5'd13: thin_bounds_topBits__h860421 = csrf_stdc_reg[27:14]; - 5'd14: thin_bounds_topBits__h860421 = csrf_sScratchC_reg[27:14]; + 5'd1: thin_bounds_topBits__h860420 = csrf_ddc_reg[27:14]; + 5'd12: thin_bounds_topBits__h860420 = csrf_stcc_reg[27:14]; + 5'd13: thin_bounds_topBits__h860420 = csrf_stdc_reg[27:14]; + 5'd14: thin_bounds_topBits__h860420 = csrf_sScratchC_reg[27:14]; 5'd15: - thin_bounds_topBits__h860421 = + thin_bounds_topBits__h860420 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17285; - 5'd28: thin_bounds_topBits__h860421 = csrf_mtcc_reg[27:14]; - 5'd29: thin_bounds_topBits__h860421 = csrf_mtdc_reg[27:14]; - 5'd30: thin_bounds_topBits__h860421 = csrf_mScratchC_reg[27:14]; - default: thin_bounds_topBits__h860421 = + 5'd28: thin_bounds_topBits__h860420 = csrf_mtcc_reg[27:14]; + 5'd29: thin_bounds_topBits__h860420 = csrf_mtdc_reg[27:14]; + 5'd30: thin_bounds_topBits__h860420 = csrf_mScratchC_reg[27:14]; + default: thin_bounds_topBits__h860420 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17291; endcase end @@ -46997,17 +47018,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[123:119]) - 5'd1: thin_bounds_topBits__h900515 = csrf_ddc_reg[27:14]; - 5'd12: thin_bounds_topBits__h900515 = csrf_stcc_reg[27:14]; - 5'd13: thin_bounds_topBits__h900515 = csrf_stdc_reg[27:14]; - 5'd14: thin_bounds_topBits__h900515 = csrf_sScratchC_reg[27:14]; + 5'd1: thin_bounds_topBits__h900513 = csrf_ddc_reg[27:14]; + 5'd12: thin_bounds_topBits__h900513 = csrf_stcc_reg[27:14]; + 5'd13: thin_bounds_topBits__h900513 = csrf_stdc_reg[27:14]; + 5'd14: thin_bounds_topBits__h900513 = csrf_sScratchC_reg[27:14]; 5'd15: - thin_bounds_topBits__h900515 = + thin_bounds_topBits__h900513 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17285; - 5'd28: thin_bounds_topBits__h900515 = csrf_mtcc_reg[27:14]; - 5'd29: thin_bounds_topBits__h900515 = csrf_mtdc_reg[27:14]; - 5'd30: thin_bounds_topBits__h900515 = csrf_mScratchC_reg[27:14]; - default: thin_bounds_topBits__h900515 = + 5'd28: thin_bounds_topBits__h900513 = csrf_mtcc_reg[27:14]; + 5'd29: thin_bounds_topBits__h900513 = csrf_mtdc_reg[27:14]; + 5'd30: thin_bounds_topBits__h900513 = csrf_mScratchC_reg[27:14]; + default: thin_bounds_topBits__h900513 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17291; endcase end @@ -47163,44 +47184,6 @@ module mkCore(CLK, IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16934; endcase end - always@(coreFix_aluExe_0_dispToRegQ$first or - IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16956 or - csrf_ddc_reg or - csrf_stcc_reg or - csrf_stdc_reg or - csrf_sScratchC_reg or - IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16950 or - csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) - begin - case (coreFix_aluExe_0_dispToRegQ$first[123:119]) - 5'd1: - IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19267 = - csrf_ddc_reg[64]; - 5'd12: - IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19267 = - csrf_stcc_reg[64]; - 5'd13: - IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19267 = - csrf_stdc_reg[64]; - 5'd14: - IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19267 = - csrf_sScratchC_reg[64]; - 5'd15: - IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19267 = - IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16950; - 5'd28: - IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19267 = - csrf_mtcc_reg[64]; - 5'd29: - IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19267 = - csrf_mtdc_reg[64]; - 5'd30: - IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19267 = - csrf_mScratchC_reg[64]; - default: IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19267 = - IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16956; - endcase - end always@(coreFix_aluExe_0_dispToRegQ$first or IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16978 or csrf_ddc_reg or @@ -47239,6 +47222,44 @@ module mkCore(CLK, IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16978; endcase end + always@(coreFix_aluExe_0_dispToRegQ$first or + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16956 or + csrf_ddc_reg or + csrf_stcc_reg or + csrf_stdc_reg or + csrf_sScratchC_reg or + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16950 or + csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) + begin + case (coreFix_aluExe_0_dispToRegQ$first[123:119]) + 5'd1: + IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19267 = + csrf_ddc_reg[64]; + 5'd12: + IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19267 = + csrf_stcc_reg[64]; + 5'd13: + IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19267 = + csrf_stdc_reg[64]; + 5'd14: + IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19267 = + csrf_sScratchC_reg[64]; + 5'd15: + IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19267 = + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16950; + 5'd28: + IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19267 = + csrf_mtcc_reg[64]; + 5'd29: + IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19267 = + csrf_mtdc_reg[64]; + 5'd30: + IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19267 = + csrf_mScratchC_reg[64]; + default: IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19267 = + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16956; + endcase + end always@(coreFix_aluExe_0_dispToRegQ$first or IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17000 or csrf_ddc_reg or @@ -47353,44 +47374,6 @@ module mkCore(CLK, IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17044; endcase end - always@(coreFix_aluExe_0_dispToRegQ$first or - IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17088 or - csrf_ddc_reg or - csrf_stcc_reg or - csrf_stdc_reg or - csrf_sScratchC_reg or - IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17082 or - csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) - begin - case (coreFix_aluExe_0_dispToRegQ$first[123:119]) - 5'd1: - IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19321 = - csrf_ddc_reg[58]; - 5'd12: - IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19321 = - csrf_stcc_reg[58]; - 5'd13: - IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19321 = - csrf_stdc_reg[58]; - 5'd14: - IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19321 = - csrf_sScratchC_reg[58]; - 5'd15: - IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19321 = - IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17082; - 5'd28: - IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19321 = - csrf_mtcc_reg[58]; - 5'd29: - IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19321 = - csrf_mtdc_reg[58]; - 5'd30: - IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19321 = - csrf_mScratchC_reg[58]; - default: IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19321 = - IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17088; - endcase - end always@(coreFix_aluExe_0_dispToRegQ$first or IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17066 or csrf_ddc_reg or @@ -47430,41 +47413,41 @@ module mkCore(CLK, endcase end always@(coreFix_aluExe_0_dispToRegQ$first or - IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17110 or + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17088 or csrf_ddc_reg or csrf_stcc_reg or csrf_stdc_reg or csrf_sScratchC_reg or - IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17104 or + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17082 or csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[123:119]) 5'd1: - IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19330 = - csrf_ddc_reg[57]; + IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19321 = + csrf_ddc_reg[58]; 5'd12: - IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19330 = - csrf_stcc_reg[57]; + IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19321 = + csrf_stcc_reg[58]; 5'd13: - IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19330 = - csrf_stdc_reg[57]; + IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19321 = + csrf_stdc_reg[58]; 5'd14: - IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19330 = - csrf_sScratchC_reg[57]; + IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19321 = + csrf_sScratchC_reg[58]; 5'd15: - IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19330 = - IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17104; + IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19321 = + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17082; 5'd28: - IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19330 = - csrf_mtcc_reg[57]; + IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19321 = + csrf_mtcc_reg[58]; 5'd29: - IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19330 = - csrf_mtdc_reg[57]; + IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19321 = + csrf_mtdc_reg[58]; 5'd30: - IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19330 = - csrf_mScratchC_reg[57]; - default: IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19330 = - IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17110; + IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19321 = + csrf_mScratchC_reg[58]; + default: IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19321 = + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17088; endcase end always@(coreFix_aluExe_0_dispToRegQ$first or @@ -47505,6 +47488,44 @@ module mkCore(CLK, IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17132; endcase end + always@(coreFix_aluExe_0_dispToRegQ$first or + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17110 or + csrf_ddc_reg or + csrf_stcc_reg or + csrf_stdc_reg or + csrf_sScratchC_reg or + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17104 or + csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) + begin + case (coreFix_aluExe_0_dispToRegQ$first[123:119]) + 5'd1: + IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19330 = + csrf_ddc_reg[57]; + 5'd12: + IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19330 = + csrf_stcc_reg[57]; + 5'd13: + IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19330 = + csrf_stdc_reg[57]; + 5'd14: + IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19330 = + csrf_sScratchC_reg[57]; + 5'd15: + IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19330 = + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17104; + 5'd28: + IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19330 = + csrf_mtcc_reg[57]; + 5'd29: + IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19330 = + csrf_mtdc_reg[57]; + 5'd30: + IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19330 = + csrf_mScratchC_reg[57]; + default: IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19330 = + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17110; + endcase + end always@(coreFix_aluExe_0_dispToRegQ$first or IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17160 or csrf_ddc_reg or @@ -47591,17 +47612,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[123:119]) - 5'd1: thin_otype__h858478 = csrf_ddc_reg[52:35]; - 5'd12: thin_otype__h858478 = csrf_stcc_reg[52:35]; - 5'd13: thin_otype__h858478 = csrf_stdc_reg[52:35]; - 5'd14: thin_otype__h858478 = csrf_sScratchC_reg[52:35]; + 5'd1: thin_otype__h858477 = csrf_ddc_reg[52:35]; + 5'd12: thin_otype__h858477 = csrf_stcc_reg[52:35]; + 5'd13: thin_otype__h858477 = csrf_stdc_reg[52:35]; + 5'd14: thin_otype__h858477 = csrf_sScratchC_reg[52:35]; 5'd15: - thin_otype__h858478 = + thin_otype__h858477 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17198; - 5'd28: thin_otype__h858478 = csrf_mtcc_reg[52:35]; - 5'd29: thin_otype__h858478 = csrf_mtdc_reg[52:35]; - 5'd30: thin_otype__h858478 = csrf_mScratchC_reg[52:35]; - default: thin_otype__h858478 = + 5'd28: thin_otype__h858477 = csrf_mtcc_reg[52:35]; + 5'd29: thin_otype__h858477 = csrf_mtdc_reg[52:35]; + 5'd30: thin_otype__h858477 = csrf_mScratchC_reg[52:35]; + default: thin_otype__h858477 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17204; endcase end @@ -47615,17 +47636,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[123:119]) - 5'd1: thin_otype__h899114 = csrf_ddc_reg[52:35]; - 5'd12: thin_otype__h899114 = csrf_stcc_reg[52:35]; - 5'd13: thin_otype__h899114 = csrf_stdc_reg[52:35]; - 5'd14: thin_otype__h899114 = csrf_sScratchC_reg[52:35]; + 5'd1: thin_otype__h899112 = csrf_ddc_reg[52:35]; + 5'd12: thin_otype__h899112 = csrf_stcc_reg[52:35]; + 5'd13: thin_otype__h899112 = csrf_stdc_reg[52:35]; + 5'd14: thin_otype__h899112 = csrf_sScratchC_reg[52:35]; 5'd15: - thin_otype__h899114 = + thin_otype__h899112 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17198; - 5'd28: thin_otype__h899114 = csrf_mtcc_reg[52:35]; - 5'd29: thin_otype__h899114 = csrf_mtdc_reg[52:35]; - 5'd30: thin_otype__h899114 = csrf_mScratchC_reg[52:35]; - default: thin_otype__h899114 = + 5'd28: thin_otype__h899112 = csrf_mtcc_reg[52:35]; + 5'd29: thin_otype__h899112 = csrf_mtdc_reg[52:35]; + 5'd30: thin_otype__h899112 = csrf_mScratchC_reg[52:35]; + default: thin_otype__h899112 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17204; endcase end @@ -47709,10 +47730,10 @@ module mkCore(CLK, begin case (mmio_dataReqQ_data_0[150:149]) 2'd0, 2'd1, 2'd2: - CASE_mmio_dataReqQ_data_0_BITS_150_TO_149_0_mm_ETC__q331 = + CASE_mmio_dataReqQ_data_0_BITS_150_TO_149_0_mm_ETC__q333 = mmio_dataReqQ_data_0[150:145]; 2'd3: - CASE_mmio_dataReqQ_data_0_BITS_150_TO_149_0_mm_ETC__q331 = + CASE_mmio_dataReqQ_data_0_BITS_150_TO_149_0_mm_ETC__q333 = { 2'd3, mmio_dataReqQ_data_0[148:145] }; endcase end @@ -47720,9 +47741,9 @@ module mkCore(CLK, begin case (coreFix_memExe_lsq$firstSt[3:0]) 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: - CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q332 = + CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q334 = coreFix_memExe_lsq$firstSt[3:0]; - default: CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q332 = + default: CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q334 = 4'd15; endcase end @@ -47752,9 +47773,9 @@ module mkCore(CLK, 5'd24, 5'd25, 5'd26: - CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q333 = + CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q335 = coreFix_memExe_lsq$firstSt[4:0]; - default: CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q333 = + default: CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q335 = 5'd27; endcase end @@ -47775,40 +47796,40 @@ module mkCore(CLK, 5'd12, 5'd13, 5'd15: - CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q334 = + CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q336 = coreFix_memExe_lsq$firstSt[4:0]; - default: CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q334 = + default: CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q336 = 5'd28; endcase end always@(coreFix_memExe_lsq$firstSt or - CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q332 or - CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q333 or - CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q334) + CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q334 or + CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q335 or + CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q336) begin case (coreFix_memExe_lsq$firstSt[12:11]) 2'd0: - CASE_coreFix_memExe_lsqfirstSt_BITS_12_TO_11__ETC__q335 = + CASE_coreFix_memExe_lsqfirstSt_BITS_12_TO_11__ETC__q337 = { 2'd0, coreFix_memExe_lsq$firstSt[10:5], - CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q333 }; + CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q335 }; 2'd1: - CASE_coreFix_memExe_lsqfirstSt_BITS_12_TO_11__ETC__q335 = + CASE_coreFix_memExe_lsqfirstSt_BITS_12_TO_11__ETC__q337 = { coreFix_memExe_lsq$firstSt[12:11], 6'h2A, - CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q334 }; - default: CASE_coreFix_memExe_lsqfirstSt_BITS_12_TO_11__ETC__q335 = + CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q336 }; + default: CASE_coreFix_memExe_lsqfirstSt_BITS_12_TO_11__ETC__q337 = { 9'd298, - CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q332 }; + CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q334 }; endcase end always@(coreFix_memExe_lsq$firstLd) begin case (coreFix_memExe_lsq$firstLd[6:3]) 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: - CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q336 = + CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q338 = coreFix_memExe_lsq$firstLd[6:3]; - default: CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q336 = + default: CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q338 = 4'd15; endcase end @@ -47838,9 +47859,9 @@ module mkCore(CLK, 5'd24, 5'd25, 5'd26: - CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q337 = + CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q339 = coreFix_memExe_lsq$firstLd[7:3]; - default: CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q337 = + default: CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q339 = 5'd27; endcase end @@ -47861,41 +47882,41 @@ module mkCore(CLK, 5'd12, 5'd13, 5'd15: - CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q338 = + CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q340 = coreFix_memExe_lsq$firstLd[7:3]; - default: CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q338 = + default: CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q340 = 5'd28; endcase end always@(coreFix_memExe_lsq$firstLd or - CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q336 or - CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q337 or - CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q338) + CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q338 or + CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q339 or + CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q340) begin case (coreFix_memExe_lsq$firstLd[15:14]) 2'd0: - CASE_coreFix_memExe_lsqfirstLd_BITS_15_TO_14__ETC__q339 = + CASE_coreFix_memExe_lsqfirstLd_BITS_15_TO_14__ETC__q341 = { 2'd0, coreFix_memExe_lsq$firstLd[13:8], - CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q337 }; + CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q339 }; 2'd1: - CASE_coreFix_memExe_lsqfirstLd_BITS_15_TO_14__ETC__q339 = + CASE_coreFix_memExe_lsqfirstLd_BITS_15_TO_14__ETC__q341 = { coreFix_memExe_lsq$firstLd[15:14], 6'h2A, - CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q338 }; - default: CASE_coreFix_memExe_lsqfirstLd_BITS_15_TO_14__ETC__q339 = + CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q340 }; + default: CASE_coreFix_memExe_lsqfirstLd_BITS_15_TO_14__ETC__q341 = { 9'd298, - CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q336 }; + CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q338 }; endcase end always@(mmioToPlatform_pRq_enq_x) begin case (mmioToPlatform_pRq_enq_x[37:36]) 2'd0, 2'd1, 2'd2: - CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q340 = + CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q342 = mmioToPlatform_pRq_enq_x[37:32]; 2'd3: - CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q340 = + CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q342 = { 2'd3, mmioToPlatform_pRq_enq_x[35:32] }; endcase end @@ -47903,26 +47924,26 @@ module mkCore(CLK, begin case (coreFix_aluExe_0_rsAlu$dispatchData[203:201]) 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q341 = + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q343 = coreFix_aluExe_0_rsAlu$dispatchData[203:201]; - default: CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q341 = 3'd7; + default: CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q343 = 3'd7; endcase end always@(coreFix_aluExe_0_rsAlu$dispatchData or - CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q341) + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q343) begin case (coreFix_aluExe_0_rsAlu$dispatchData[229:227]) 3'd0, 3'd1, 3'd2, 3'd3: - CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q342 = + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q344 = coreFix_aluExe_0_rsAlu$dispatchData[229:200]; 3'd4: - CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q342 = + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q344 = { coreFix_aluExe_0_rsAlu$dispatchData[229:227], 18'h2AAAA, coreFix_aluExe_0_rsAlu$dispatchData[208:204], - CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q341, + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q343, coreFix_aluExe_0_rsAlu$dispatchData[200] }; - default: CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q342 = + default: CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q344 = 30'd715827882; endcase end @@ -47931,13 +47952,13 @@ module mkCore(CLK, begin case (coreFix_aluExe_0_rsAlu$dispatchData[199:198]) 2'd0: - CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q343 = + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q345 = coreFix_aluExe_0_rsAlu$dispatchData[199:189]; 2'd1: - CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q343 = + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q345 = { coreFix_aluExe_0_rsAlu$dispatchData[199:198], IF_coreFix_aluExe_0_rsAlu_dispatchData__8084_B_ETC___d18225 }; - default: CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q343 = + default: CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q345 = 11'd1194; endcase end @@ -47990,9 +48011,9 @@ module mkCore(CLK, 12'd3858, 12'd3859, 12'd3860: - CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q344 = + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q346 = coreFix_aluExe_0_rsAlu$dispatchData[140:129]; - default: CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q344 = + default: CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q346 = 12'd2303; endcase end @@ -48000,9 +48021,9 @@ module mkCore(CLK, begin case (coreFix_aluExe_0_rsAlu$dispatchData[127:123]) 5'd0, 5'd1, 5'd12, 5'd13, 5'd14, 5'd15, 5'd28, 5'd29, 5'd30, 5'd31: - CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q345 = + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q347 = coreFix_aluExe_0_rsAlu$dispatchData[127:123]; - default: CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q345 = + default: CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q347 = 5'd10; endcase end @@ -48032,9 +48053,9 @@ module mkCore(CLK, 5'd24, 5'd25, 5'd26: - CASE_basicExec_9859_BITS_270_TO_266_0_basicExe_ETC__q346 = + CASE_basicExec_9859_BITS_270_TO_266_0_basicExe_ETC__q348 = basicExec___d19859[270:266]; - default: CASE_basicExec_9859_BITS_270_TO_266_0_basicExe_ETC__q346 = + default: CASE_basicExec_9859_BITS_270_TO_266_0_basicExe_ETC__q348 = 5'd27; endcase end @@ -48042,26 +48063,26 @@ module mkCore(CLK, begin case (coreFix_aluExe_0_dispToRegQ$first[199:197]) 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_19_ETC__q347 = + CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_19_ETC__q349 = coreFix_aluExe_0_dispToRegQ$first[199:197]; - default: CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_19_ETC__q347 = 3'd7; + default: CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_19_ETC__q349 = 3'd7; endcase end always@(coreFix_aluExe_0_dispToRegQ$first or - CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_19_ETC__q347) + CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_19_ETC__q349) begin case (coreFix_aluExe_0_dispToRegQ$first[225:223]) 3'd0, 3'd1, 3'd2, 3'd3: - CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_22_ETC__q348 = + CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_22_ETC__q350 = coreFix_aluExe_0_dispToRegQ$first[225:196]; 3'd4: - CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_22_ETC__q348 = + CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_22_ETC__q350 = { coreFix_aluExe_0_dispToRegQ$first[225:223], 18'h2AAAA, coreFix_aluExe_0_dispToRegQ$first[204:200], - CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_19_ETC__q347, + CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_19_ETC__q349, coreFix_aluExe_0_dispToRegQ$first[196] }; - default: CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_22_ETC__q348 = + default: CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_22_ETC__q350 = 30'd715827882; endcase end @@ -48070,13 +48091,13 @@ module mkCore(CLK, begin case (coreFix_aluExe_0_dispToRegQ$first[195:194]) 2'd0: - CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_19_ETC__q349 = + CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_19_ETC__q351 = coreFix_aluExe_0_dispToRegQ$first[195:185]; 2'd1: - CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_19_ETC__q349 = + CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_19_ETC__q351 = { coreFix_aluExe_0_dispToRegQ$first[195:194], IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d18609 }; - default: CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_19_ETC__q349 = + default: CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_19_ETC__q351 = 11'd1194; endcase end @@ -48129,9 +48150,9 @@ module mkCore(CLK, 12'd3858, 12'd3859, 12'd3860: - CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q350 = + CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q352 = coreFix_aluExe_0_dispToRegQ$first[136:125]; - default: CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q350 = + default: CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q352 = 12'd2303; endcase end @@ -48139,9 +48160,9 @@ module mkCore(CLK, begin case (coreFix_aluExe_0_dispToRegQ$first[123:119]) 5'd0, 5'd1, 5'd12, 5'd13, 5'd14, 5'd15, 5'd28, 5'd29, 5'd30, 5'd31: - CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_12_ETC__q351 = + CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_12_ETC__q353 = coreFix_aluExe_0_dispToRegQ$first[123:119]; - default: CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_12_ETC__q351 = + default: CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_12_ETC__q353 = 5'd10; endcase end @@ -48149,26 +48170,26 @@ module mkCore(CLK, begin case (coreFix_aluExe_1_rsAlu$dispatchData[203:201]) 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q352 = + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q354 = coreFix_aluExe_1_rsAlu$dispatchData[203:201]; - default: CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q352 = 3'd7; + default: CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q354 = 3'd7; endcase end always@(coreFix_aluExe_1_rsAlu$dispatchData or - CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q352) + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q354) begin case (coreFix_aluExe_1_rsAlu$dispatchData[229:227]) 3'd0, 3'd1, 3'd2, 3'd3: - CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q353 = + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q355 = coreFix_aluExe_1_rsAlu$dispatchData[229:200]; 3'd4: - CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q353 = + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q355 = { coreFix_aluExe_1_rsAlu$dispatchData[229:227], 18'h2AAAA, coreFix_aluExe_1_rsAlu$dispatchData[208:204], - CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q352, + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q354, coreFix_aluExe_1_rsAlu$dispatchData[200] }; - default: CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q353 = + default: CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q355 = 30'd715827882; endcase end @@ -48177,13 +48198,13 @@ module mkCore(CLK, begin case (coreFix_aluExe_1_rsAlu$dispatchData[199:198]) 2'd0: - CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q354 = + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q356 = coreFix_aluExe_1_rsAlu$dispatchData[199:189]; 2'd1: - CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q354 = + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q356 = { coreFix_aluExe_1_rsAlu$dispatchData[199:198], IF_coreFix_aluExe_1_rsAlu_dispatchData__5318_B_ETC___d15461 }; - default: CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q354 = + default: CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q356 = 11'd1194; endcase end @@ -48236,9 +48257,9 @@ module mkCore(CLK, 12'd3858, 12'd3859, 12'd3860: - CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q355 = + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q357 = coreFix_aluExe_1_rsAlu$dispatchData[140:129]; - default: CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q355 = + default: CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q357 = 12'd2303; endcase end @@ -48246,9 +48267,9 @@ module mkCore(CLK, begin case (coreFix_aluExe_1_rsAlu$dispatchData[127:123]) 5'd0, 5'd1, 5'd12, 5'd13, 5'd14, 5'd15, 5'd28, 5'd29, 5'd30, 5'd31: - CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q356 = + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q358 = coreFix_aluExe_1_rsAlu$dispatchData[127:123]; - default: CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q356 = + default: CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q358 = 5'd10; endcase end @@ -48278,9 +48299,9 @@ module mkCore(CLK, 5'd24, 5'd25, 5'd26: - CASE_basicExec_7743_BITS_270_TO_266_0_basicExe_ETC__q357 = + CASE_basicExec_7743_BITS_270_TO_266_0_basicExe_ETC__q359 = basicExec___d17743[270:266]; - default: CASE_basicExec_7743_BITS_270_TO_266_0_basicExe_ETC__q357 = + default: CASE_basicExec_7743_BITS_270_TO_266_0_basicExe_ETC__q359 = 5'd27; endcase end @@ -48288,26 +48309,26 @@ module mkCore(CLK, begin case (coreFix_aluExe_1_dispToRegQ$first[199:197]) 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_19_ETC__q358 = + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_19_ETC__q360 = coreFix_aluExe_1_dispToRegQ$first[199:197]; - default: CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_19_ETC__q358 = 3'd7; + default: CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_19_ETC__q360 = 3'd7; endcase end always@(coreFix_aluExe_1_dispToRegQ$first or - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_19_ETC__q358) + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_19_ETC__q360) begin case (coreFix_aluExe_1_dispToRegQ$first[225:223]) 3'd0, 3'd1, 3'd2, 3'd3: - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_22_ETC__q359 = + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_22_ETC__q361 = coreFix_aluExe_1_dispToRegQ$first[225:196]; 3'd4: - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_22_ETC__q359 = + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_22_ETC__q361 = { coreFix_aluExe_1_dispToRegQ$first[225:223], 18'h2AAAA, coreFix_aluExe_1_dispToRegQ$first[204:200], - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_19_ETC__q358, + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_19_ETC__q360, coreFix_aluExe_1_dispToRegQ$first[196] }; - default: CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_22_ETC__q359 = + default: CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_22_ETC__q361 = 30'd715827882; endcase end @@ -48316,13 +48337,13 @@ module mkCore(CLK, begin case (coreFix_aluExe_1_dispToRegQ$first[195:194]) 2'd0: - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_19_ETC__q360 = + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_19_ETC__q362 = coreFix_aluExe_1_dispToRegQ$first[195:185]; 2'd1: - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_19_ETC__q360 = + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_19_ETC__q362 = { coreFix_aluExe_1_dispToRegQ$first[195:194], IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d15846 }; - default: CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_19_ETC__q360 = + default: CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_19_ETC__q362 = 11'd1194; endcase end @@ -48375,9 +48396,9 @@ module mkCore(CLK, 12'd3858, 12'd3859, 12'd3860: - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q361 = + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q363 = coreFix_aluExe_1_dispToRegQ$first[136:125]; - default: CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q361 = + default: CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q363 = 12'd2303; endcase end @@ -48385,9 +48406,9 @@ module mkCore(CLK, begin case (coreFix_aluExe_1_dispToRegQ$first[123:119]) 5'd0, 5'd1, 5'd12, 5'd13, 5'd14, 5'd15, 5'd28, 5'd29, 5'd30, 5'd31: - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_12_ETC__q362 = + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_12_ETC__q364 = coreFix_aluExe_1_dispToRegQ$first[123:119]; - default: CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_12_ETC__q362 = + default: CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_12_ETC__q364 = 5'd10; endcase end @@ -48395,26 +48416,26 @@ module mkCore(CLK, begin case (coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[69:67]) 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q363 = + CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q365 = coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[69:67]; - default: CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q363 = 3'd7; + default: CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q365 = 3'd7; endcase end always@(coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData or - CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q363) + CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q365) begin case (coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[95:93]) 3'd0, 3'd1, 3'd2, 3'd3: - CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q364 = + CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q366 = coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[95:66]; 3'd4: - CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q364 = + CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q366 = { coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[95:93], 18'h2AAAA, coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[74:70], - CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q363, + CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q365, coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[66] }; - default: CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q364 = + default: CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q366 = 30'd715827882; endcase end @@ -48426,16 +48447,16 @@ module mkCore(CLK, begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229]) 5'd0: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q365 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q367 = IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14805; 5'd1: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q365 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q367 = coreFix_fpuMulDivExe_0_regToExeQ$first[225] ? { !coreFix_fpuMulDivExe_0_regToExeQ$first[139], coreFix_fpuMulDivExe_0_regToExeQ$first[138:76] } : { IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14858, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14803 }; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q365 = + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q367 = IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13325; endcase end @@ -48444,9 +48465,9 @@ module mkCore(CLK, begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229]) 5'd0, 5'd1: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q366 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q368 = 64'h3FF0000000000000; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q366 = + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q368 = IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14805; endcase end @@ -48454,26 +48475,26 @@ module mkCore(CLK, begin case (coreFix_fpuMulDivExe_0_dispToRegQ$first[60:58]) 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q367 = + CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q369 = coreFix_fpuMulDivExe_0_dispToRegQ$first[60:58]; - default: CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q367 = 3'd7; + default: CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q369 = 3'd7; endcase end always@(coreFix_fpuMulDivExe_0_dispToRegQ$first or - CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q367) + CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q369) begin case (coreFix_fpuMulDivExe_0_dispToRegQ$first[86:84]) 3'd0, 3'd1, 3'd2, 3'd3: - CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q368 = + CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q370 = coreFix_fpuMulDivExe_0_dispToRegQ$first[86:57]; 3'd4: - CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q368 = + CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q370 = { coreFix_fpuMulDivExe_0_dispToRegQ$first[86:84], 18'h2AAAA, coreFix_fpuMulDivExe_0_dispToRegQ$first[65:61], - CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q367, + CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q369, coreFix_fpuMulDivExe_0_dispToRegQ$first[57] }; - default: CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q368 = + default: CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q370 = 30'd715827882; endcase end @@ -48483,10 +48504,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q369 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q371 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[1:0]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q369 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q371 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[1:0]; endcase end @@ -48497,12 +48518,12 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_processAmo[7:6]) 2'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q370 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q372 = SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4867; 2'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q370 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q372 = SEXT_SEL_ARR_SEL_ARR_coreFix_memExe_dMem_cache_ETC___d4881[63:0]; - default: CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q370 = + default: CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q372 = SEXT_SEL_ARR_SEL_ARR_coreFix_memExe_dMem_cache_ETC___d4889[63:0]; endcase end @@ -48513,12 +48534,12 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_processAmo[7:6]) 2'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q371 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q373 = SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4861; 2'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q371 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q373 = SEXT_SEL_ARR_SEL_ARR_coreFix_memExe_dMem_cache_ETC___d4881[127:64]; - default: CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q371 = + default: CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q373 = SEXT_SEL_ARR_SEL_ARR_coreFix_memExe_dMem_cache_ETC___d4889[127:64]; endcase end @@ -53572,12 +53593,12 @@ module mkCore(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo) $write("'h%h", - CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q370, + CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q372, " "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo) $write("'h%h", - CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q371, + CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q373, " "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo) @@ -53886,7 +53907,7 @@ module mkCore(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == 6'd6) + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd6) $display("[Terminate CSR] being written (val = %x), ", "send terminate signal to host", rob$deqPort_0_deq_data[95:32]); @@ -54024,7 +54045,7 @@ module mkCore(CLK, rob$deqPort_1_deq_data[469:465] != 5'd25) $write("instret:%0d PC:0x%0h instr:0x%08h", commitStage_rg_serial_num + - IF_rob_deqPort_0_canDeq__3598_THEN_IF_NOT_rob__ETC___d23719, + IF_rob_deqPort_0_canDeq__3600_THEN_IF_NOT_rob__ETC___d23721, rob$deqPort_1_deq_data[630:502], rob$deqPort_1_deq_data[501:470], " iType:"); @@ -56715,17 +56736,17 @@ module mkCore(CLK, if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) $write(" o: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) - $write("'h%h", value__h254475); + $write("'h%h", value__h254472); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) $write(" b: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) - $write("'h%h", value__h254639); + $write("'h%h", value__h254636); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) $write(" t: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) - $write("'h%h", x__h254751[64:0]); + $write("'h%h", x__h254748[64:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) $write(" sp: "); if (RST_N != `BSV_RESET_VALUE) @@ -58519,14 +58540,14 @@ module mkCore(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem) begin - v__h213413 = $time; + v__h213411 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem) - $write("%t : ", v__h213413, "[doRespLdMem]", " "); + $write("%t : ", v__h213411, "[doRespLdMem]", " "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem) $write("'h%h", t__h212841); + if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem) $write("'h%h", t__h212839); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem) $write("; "); if (RST_N != `BSV_RESET_VALUE) @@ -58665,15 +58686,15 @@ module mkCore(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward) begin - v__h215682 = $time; + v__h215680 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward) - $write("%t : ", v__h215682, "[doRespLdForward]", " "); + $write("%t : ", v__h215680, "[doRespLdForward]", " "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward) - $write("'h%h", t__h215127); + $write("'h%h", t__h215125); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward) $write("; "); if (RST_N != `BSV_RESET_VALUE) @@ -58898,17 +58919,17 @@ module mkCore(CLK, if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" o: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) - $write("'h%h", value__h239694); + $write("'h%h", value__h239691); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" b: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) - $write("'h%h", value__h239858); + $write("'h%h", value__h239855); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" t: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) - $write("'h%h", x__h239970[64:0]); + $write("'h%h", x__h239967[64:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" sp: "); if (RST_N != `BSV_RESET_VALUE) @@ -58948,17 +58969,17 @@ module mkCore(CLK, if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" o: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) - $write("'h%h", value__h240851); + $write("'h%h", value__h240848); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" b: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) - $write("'h%h", value__h241015); + $write("'h%h", value__h241012); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" t: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) - $write("'h%h", x__h241127[64:0]); + $write("'h%h", x__h241124[64:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" sp: "); if (RST_N != `BSV_RESET_VALUE) @@ -67191,14 +67212,14 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5591) begin - v__h271939 = $time; + v__h271938 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5591) - $write("%t : [Ld resp] ", v__h271939); + $write("%t : [Ld resp] ", v__h271938); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && @@ -68838,13 +68859,13 @@ module mkCore(CLK, if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5595) begin - v__h347457 = $time; + v__h347456 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5595) - $write("%t : [Ld resp] ", v__h347457); + $write("%t : [Ld resp] ", v__h347456); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5595) @@ -70718,7 +70739,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == 3'd0) begin - v__h423783 = $time; + v__h423782 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) @@ -70726,7 +70747,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == 3'd0) - $write("%t : [Ld resp] ", v__h423783); + $write("%t : [Ld resp] ", v__h423782); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && @@ -73130,7 +73151,7 @@ module mkCore(CLK, $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas && - v__h836642 == 2'd0) + v__h836639 == 2'd0) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); end // synopsys translate_on diff --git a/src_SSITH_P3/Verilog_RTL/mkCoreW.v b/src_SSITH_P3/Verilog_RTL/mkCoreW.v index b86c663..2cee937 100644 --- a/src_SSITH_P3/Verilog_RTL/mkCoreW.v +++ b/src_SSITH_P3/Verilog_RTL/mkCoreW.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jul 1 17:07:45 BST 2020 +// On Thu Jul 2 02:59:17 BST 2020 // // // Ports: @@ -783,7 +783,7 @@ module mkCoreW(RST_N_dm_power_on_reset, ifcs_1_1_noRoute_currentReq$port1__read, ifcs_1_noRoute_inner_currentReq$port1__read, msNoSynth_1_arNoSynth_buffer_enqw$wget, - msNoSynth_1_awNoSynth_snk_putWire$wget; + msNoSynth_1_awNoSynth_buffer_enqw$wget; wire [74 : 0] tagController_tmp_shimSlave_wff_rv$port0__write_1, tagController_tmp_shimSlave_wff_rv$port1__read, tagController_tmp_shimSlave_wff_rv$port2__read, @@ -3313,12 +3313,12 @@ module mkCoreW(RST_N_dm_power_on_reset, MUX_flitToSink_2$wset_1__SEL_1, MUX_flitToSink_2$wset_1__SEL_3, MUX_ifcs_0_1_state_1$write_1__SEL_1, - MUX_ifcs_0_state$write_1__PSEL_3, + MUX_ifcs_0_state$write_1__PSEL_1, MUX_ifcs_0_state$write_1__SEL_1, MUX_ifcs_0_state$write_1__SEL_2, MUX_ifcs_0_state$write_1__SEL_3, MUX_ifcs_1_1_state_1$write_1__SEL_1, - MUX_ifcs_1_state$write_1__PSEL_3, + MUX_ifcs_1_state$write_1__PSEL_1, MUX_ifcs_1_state$write_1__SEL_1, MUX_ifcs_1_state$write_1__SEL_2, MUX_ifcs_1_state$write_1__SEL_3, @@ -5303,22 +5303,22 @@ module mkCoreW(RST_N_dm_power_on_reset, // rule RL_rl_dm_hart0_reset_wait assign CAN_FIRE_RL_rl_dm_hart0_reset_wait = (rg_hart0_reset_delay != 8'd1 || - proc$RDY_start && - debug_module$RDY_hart0_reset_client_response_put) && + debug_module$RDY_hart0_reset_client_response_put && + proc$RDY_start) && rg_hart0_reset_delay != 8'd0 ; assign WILL_FIRE_RL_rl_dm_hart0_reset_wait = CAN_FIRE_RL_rl_dm_hart0_reset_wait && !EN_start ; // rule RL_ClientServerRequest assign CAN_FIRE_RL_ClientServerRequest = - proc$RDY_hart0_run_halt_server_request_put && - debug_module$RDY_hart0_client_run_halt_request_get ; + debug_module$RDY_hart0_client_run_halt_request_get && + proc$RDY_hart0_run_halt_server_request_put ; assign WILL_FIRE_RL_ClientServerRequest = CAN_FIRE_RL_ClientServerRequest ; // rule RL_ClientServerResponse assign CAN_FIRE_RL_ClientServerResponse = - proc$RDY_hart0_run_halt_server_response_get && - debug_module$RDY_hart0_client_run_halt_response_put ; + debug_module$RDY_hart0_client_run_halt_response_put && + proc$RDY_hart0_run_halt_server_response_get ; assign WILL_FIRE_RL_ClientServerResponse = CAN_FIRE_RL_ClientServerResponse ; @@ -5330,15 +5330,15 @@ module mkCoreW(RST_N_dm_power_on_reset, // rule RL_ClientServerResponse_1 assign CAN_FIRE_RL_ClientServerResponse_1 = - proc$RDY_hart0_gpr_mem_server_response_get && - debug_module$RDY_hart0_gpr_mem_client_response_put ; + debug_module$RDY_hart0_gpr_mem_client_response_put && + proc$RDY_hart0_gpr_mem_server_response_get ; assign WILL_FIRE_RL_ClientServerResponse_1 = CAN_FIRE_RL_ClientServerResponse_1 ; // rule RL_ClientServerResponse_2 assign CAN_FIRE_RL_ClientServerResponse_2 = - proc$RDY_hart0_csr_mem_server_response_get && - debug_module$RDY_hart0_csr_mem_client_response_put ; + debug_module$RDY_hart0_csr_mem_client_response_put && + proc$RDY_hart0_csr_mem_server_response_get ; assign WILL_FIRE_RL_ClientServerResponse_2 = CAN_FIRE_RL_ClientServerResponse_2 ; @@ -7758,15 +7758,15 @@ module mkCoreW(RST_N_dm_power_on_reset, // rule RL_ClientServerRequest_1 assign CAN_FIRE_RL_ClientServerRequest_1 = - proc$RDY_hart0_gpr_mem_server_request_put && - debug_module$RDY_hart0_gpr_mem_client_request_get ; + debug_module$RDY_hart0_gpr_mem_client_request_get && + proc$RDY_hart0_gpr_mem_server_request_put ; assign WILL_FIRE_RL_ClientServerRequest_1 = CAN_FIRE_RL_ClientServerRequest_1 ; // rule RL_ClientServerRequest_2 assign CAN_FIRE_RL_ClientServerRequest_2 = - proc$RDY_hart0_csr_mem_server_request_put && - debug_module$RDY_hart0_csr_mem_client_request_get ; + debug_module$RDY_hart0_csr_mem_client_request_get && + proc$RDY_hart0_csr_mem_server_request_put ; assign WILL_FIRE_RL_ClientServerRequest_2 = CAN_FIRE_RL_ClientServerRequest_2 ; @@ -8623,33 +8623,33 @@ module mkCoreW(RST_N_dm_power_on_reset, assign MUX_ifcs_0_1_state_1$write_1__SEL_1 = WILL_FIRE_RL_ifcs_0_1_followFlits_1 && ssNoSynth_0_rNoSynth_buffer_ff$D_OUT[1] ; - assign MUX_ifcs_0_state$write_1__SEL_1 = - WILL_FIRE_RL_ifcs_0_firstFlit && - IF_merged_0_outflit_whas__501_THEN_NOT_merged__ETC___d1556 ; - assign MUX_ifcs_0_state$write_1__SEL_2 = - WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp && - IF_merged_0_outflit_whas__501_THEN_NOT_merged__ETC___d1556 ; - assign MUX_ifcs_0_state$write_1__PSEL_3 = + assign MUX_ifcs_0_state$write_1__PSEL_1 = WILL_FIRE_RL_ifcs_0_drainFlits || WILL_FIRE_RL_ifcs_0_followFlits ; - assign MUX_ifcs_0_state$write_1__SEL_3 = - MUX_ifcs_0_state$write_1__PSEL_3 && + assign MUX_ifcs_0_state$write_1__SEL_1 = + MUX_ifcs_0_state$write_1__PSEL_1 && IF_merged_0_outflit_whas__501_THEN_merged_0_ou_ETC___d1561 ; + assign MUX_ifcs_0_state$write_1__SEL_2 = + WILL_FIRE_RL_ifcs_0_firstFlit && + IF_merged_0_outflit_whas__501_THEN_NOT_merged__ETC___d1556 ; + assign MUX_ifcs_0_state$write_1__SEL_3 = + WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp && + IF_merged_0_outflit_whas__501_THEN_NOT_merged__ETC___d1556 ; assign MUX_ifcs_1_1_state_1$write_1__SEL_1 = WILL_FIRE_RL_ifcs_1_1_followFlits_1 && ssNoSynth_1_rNoSynth_buffer_ff$D_OUT[1] ; - assign MUX_ifcs_1_state$write_1__SEL_1 = - WILL_FIRE_RL_ifcs_1_firstFlit && - IF_merged_1_outflit_whas__601_THEN_NOT_merged__ETC___d1650 ; - assign MUX_ifcs_1_state$write_1__SEL_2 = - WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp && - IF_merged_1_outflit_whas__601_THEN_NOT_merged__ETC___d1650 ; - assign MUX_ifcs_1_state$write_1__PSEL_3 = + assign MUX_ifcs_1_state$write_1__PSEL_1 = WILL_FIRE_RL_ifcs_1_drainFlits || WILL_FIRE_RL_ifcs_1_followFlits ; - assign MUX_ifcs_1_state$write_1__SEL_3 = - MUX_ifcs_1_state$write_1__PSEL_3 && + assign MUX_ifcs_1_state$write_1__SEL_1 = + MUX_ifcs_1_state$write_1__PSEL_1 && IF_merged_1_outflit_whas__601_THEN_merged_1_ou_ETC___d1655 ; + assign MUX_ifcs_1_state$write_1__SEL_2 = + WILL_FIRE_RL_ifcs_1_firstFlit && + IF_merged_1_outflit_whas__601_THEN_NOT_merged__ETC___d1650 ; + assign MUX_ifcs_1_state$write_1__SEL_3 = + WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp && + IF_merged_1_outflit_whas__601_THEN_NOT_merged__ETC___d1650 ; assign MUX_ifcs_2_1_state$write_1__SEL_1 = WILL_FIRE_RL_ifcs_2_1_followFlits && ssNoSynth_2_rNoSynth_buffer_ff$D_OUT[1] ; @@ -8917,7 +8917,7 @@ module mkCoreW(RST_N_dm_power_on_reset, WILL_FIRE_RL_sinks_1_1_0_doPut ? MUX_ifcs_0_1_snk_putWire$wset_1__VAL_1 : ifcs_0_1_noRouteRsp$D_OUT ; - assign msNoSynth_1_awNoSynth_snk_putWire$wget = + assign msNoSynth_1_awNoSynth_buffer_enqw$wget = { debug_module$master_awid, debug_module$master_awaddr, debug_module$master_awlen, @@ -9706,20 +9706,20 @@ module mkCoreW(RST_N_dm_power_on_reset, MUX_ifcs_0_state$write_1__SEL_2 or MUX_ifcs_0_state$write_1__SEL_3) begin case (1'b1) // synopsys parallel_case - MUX_ifcs_0_state$write_1__SEL_1: ifcs_0_state$D_IN = 2'd1; - MUX_ifcs_0_state$write_1__SEL_2: ifcs_0_state$D_IN = 2'd2; - MUX_ifcs_0_state$write_1__SEL_3: ifcs_0_state$D_IN = 2'd0; + MUX_ifcs_0_state$write_1__SEL_1: ifcs_0_state$D_IN = 2'd0; + MUX_ifcs_0_state$write_1__SEL_2: ifcs_0_state$D_IN = 2'd1; + MUX_ifcs_0_state$write_1__SEL_3: ifcs_0_state$D_IN = 2'd2; default: ifcs_0_state$D_IN = 2'b10 /* unspecified value */ ; endcase end assign ifcs_0_state$EN = + (WILL_FIRE_RL_ifcs_0_drainFlits || + WILL_FIRE_RL_ifcs_0_followFlits) && + IF_merged_0_outflit_whas__501_THEN_merged_0_ou_ETC___d1561 || WILL_FIRE_RL_ifcs_0_firstFlit && IF_merged_0_outflit_whas__501_THEN_NOT_merged__ETC___d1556 || WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp && - IF_merged_0_outflit_whas__501_THEN_NOT_merged__ETC___d1556 || - (WILL_FIRE_RL_ifcs_0_drainFlits || - WILL_FIRE_RL_ifcs_0_followFlits) && - IF_merged_0_outflit_whas__501_THEN_merged_0_ou_ETC___d1561 ; + IF_merged_0_outflit_whas__501_THEN_NOT_merged__ETC___d1556 ; // register ifcs_0_state_1 assign ifcs_0_state_1$D_IN = 1'd0 ; @@ -9764,20 +9764,20 @@ module mkCoreW(RST_N_dm_power_on_reset, MUX_ifcs_1_state$write_1__SEL_2 or MUX_ifcs_1_state$write_1__SEL_3) begin case (1'b1) // synopsys parallel_case - MUX_ifcs_1_state$write_1__SEL_1: ifcs_1_state$D_IN = 2'd1; - MUX_ifcs_1_state$write_1__SEL_2: ifcs_1_state$D_IN = 2'd2; - MUX_ifcs_1_state$write_1__SEL_3: ifcs_1_state$D_IN = 2'd0; + MUX_ifcs_1_state$write_1__SEL_1: ifcs_1_state$D_IN = 2'd0; + MUX_ifcs_1_state$write_1__SEL_2: ifcs_1_state$D_IN = 2'd1; + MUX_ifcs_1_state$write_1__SEL_3: ifcs_1_state$D_IN = 2'd2; default: ifcs_1_state$D_IN = 2'b10 /* unspecified value */ ; endcase end assign ifcs_1_state$EN = + (WILL_FIRE_RL_ifcs_1_drainFlits || + WILL_FIRE_RL_ifcs_1_followFlits) && + IF_merged_1_outflit_whas__601_THEN_merged_1_ou_ETC___d1655 || WILL_FIRE_RL_ifcs_1_firstFlit && IF_merged_1_outflit_whas__601_THEN_NOT_merged__ETC___d1650 || WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp && - IF_merged_1_outflit_whas__601_THEN_NOT_merged__ETC___d1650 || - (WILL_FIRE_RL_ifcs_1_drainFlits || - WILL_FIRE_RL_ifcs_1_followFlits) && - IF_merged_1_outflit_whas__601_THEN_merged_1_ou_ETC___d1655 ; + IF_merged_1_outflit_whas__601_THEN_NOT_merged__ETC___d1650 ; // register ifcs_1_state_1 assign ifcs_1_state_1$D_IN = 1'd0 ; @@ -10332,7 +10332,7 @@ module mkCoreW(RST_N_dm_power_on_reset, assign merged_1_awff$D_IN = msNoSynth_1_awNoSynth_buffer_ff$EMPTY_N ? msNoSynth_1_awNoSynth_buffer_ff$D_OUT : - msNoSynth_1_awNoSynth_snk_putWire$wget ; + msNoSynth_1_awNoSynth_buffer_enqw$wget ; assign merged_1_awff$ENQ = CAN_FIRE_RL_merged_1_awFlit ; assign merged_1_awff$DEQ = CAN_FIRE_RL_merged_1_genFirst ; assign merged_1_awff$CLR = 1'b0 ; @@ -10432,7 +10432,7 @@ module mkCoreW(RST_N_dm_power_on_reset, // submodule msNoSynth_1_awNoSynth_buffer_ff assign msNoSynth_1_awNoSynth_buffer_ff$D_IN = - msNoSynth_1_awNoSynth_snk_putWire$wget ; + msNoSynth_1_awNoSynth_buffer_enqw$wget ; assign msNoSynth_1_awNoSynth_buffer_ff$ENQ = CAN_FIRE_RL_msNoSynth_1_awNoSynth_buffer_enqueue ; assign msNoSynth_1_awNoSynth_buffer_ff$DEQ = diff --git a/src_SSITH_P3/Verilog_RTL/mkDCRqMshrWrapper.v b/src_SSITH_P3/Verilog_RTL/mkDCRqMshrWrapper.v index d8f0756..8863dc3 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDCRqMshrWrapper.v +++ b/src_SSITH_P3/Verilog_RTL/mkDCRqMshrWrapper.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:52:01 BST 2020 +// On Thu Jul 2 02:53:53 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkDM_Abstract_Commands.v b/src_SSITH_P3/Verilog_RTL/mkDM_Abstract_Commands.v index a5ea406..8a66c6a 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDM_Abstract_Commands.v +++ b/src_SSITH_P3/Verilog_RTL/mkDM_Abstract_Commands.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 24 20:23:59 BST 2020 +// On Thu Jul 2 02:46:44 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkDM_Run_Control.v b/src_SSITH_P3/Verilog_RTL/mkDM_Run_Control.v index 52cd854..2cdae8a 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDM_Run_Control.v +++ b/src_SSITH_P3/Verilog_RTL/mkDM_Run_Control.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 24 20:23:58 BST 2020 +// On Thu Jul 2 02:46:43 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkDM_System_Bus.v b/src_SSITH_P3/Verilog_RTL/mkDM_System_Bus.v index 87ed61e..45cb1e9 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDM_System_Bus.v +++ b/src_SSITH_P3/Verilog_RTL/mkDM_System_Bus.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:45:18 BST 2020 +// On Thu Jul 2 02:46:59 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkDPRqMshrWrapper.v b/src_SSITH_P3/Verilog_RTL/mkDPRqMshrWrapper.v index 3a1285e..091e4a5 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDPRqMshrWrapper.v +++ b/src_SSITH_P3/Verilog_RTL/mkDPRqMshrWrapper.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:52:02 BST 2020 +// On Thu Jul 2 02:53:54 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkDPipeline.v b/src_SSITH_P3/Verilog_RTL/mkDPipeline.v index 02b27ea..52b9305 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDPipeline.v +++ b/src_SSITH_P3/Verilog_RTL/mkDPipeline.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:52:05 BST 2020 +// On Thu Jul 2 02:53:57 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkDTlbSynth.v b/src_SSITH_P3/Verilog_RTL/mkDTlbSynth.v index d47a114..3b4ce0f 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDTlbSynth.v +++ b/src_SSITH_P3/Verilog_RTL/mkDTlbSynth.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:52:32 BST 2020 +// On Thu Jul 2 02:54:27 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkDebug_Module.v b/src_SSITH_P3/Verilog_RTL/mkDebug_Module.v index 63c5137..11e425d 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDebug_Module.v +++ b/src_SSITH_P3/Verilog_RTL/mkDebug_Module.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:45:19 BST 2020 +// On Thu Jul 2 02:47:00 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkDirPredictor.v b/src_SSITH_P3/Verilog_RTL/mkDirPredictor.v index ea4c12d..2b0072b 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDirPredictor.v +++ b/src_SSITH_P3/Verilog_RTL/mkDirPredictor.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:53:56 BST 2020 +// On Thu Jul 2 02:56:45 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkDivExecQ.v b/src_SSITH_P3/Verilog_RTL/mkDivExecQ.v index 26bed02..aa37e9d 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDivExecQ.v +++ b/src_SSITH_P3/Verilog_RTL/mkDivExecQ.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:53:50 BST 2020 +// On Thu Jul 2 02:55:48 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkDoubleDiv.v b/src_SSITH_P3/Verilog_RTL/mkDoubleDiv.v index a9fc74d..67af9a1 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDoubleDiv.v +++ b/src_SSITH_P3/Verilog_RTL/mkDoubleDiv.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:53:30 BST 2020 +// On Thu Jul 2 02:55:27 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkDoubleFMA.v b/src_SSITH_P3/Verilog_RTL/mkDoubleFMA.v index 22e646b..b276d98 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDoubleFMA.v +++ b/src_SSITH_P3/Verilog_RTL/mkDoubleFMA.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:53:36 BST 2020 +// On Thu Jul 2 02:55:33 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkDoubleSqrt.v b/src_SSITH_P3/Verilog_RTL/mkDoubleSqrt.v index a38d838..39ac50d 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDoubleSqrt.v +++ b/src_SSITH_P3/Verilog_RTL/mkDoubleSqrt.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:53:33 BST 2020 +// On Thu Jul 2 02:55:30 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkDummyStoreBuffer.v b/src_SSITH_P3/Verilog_RTL/mkDummyStoreBuffer.v index 4674119..8a46fff 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDummyStoreBuffer.v +++ b/src_SSITH_P3/Verilog_RTL/mkDummyStoreBuffer.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:46:05 BST 2020 +// On Thu Jul 2 02:47:51 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkEpochManager.v b/src_SSITH_P3/Verilog_RTL/mkEpochManager.v index 5eff025..409e367 100644 --- a/src_SSITH_P3/Verilog_RTL/mkEpochManager.v +++ b/src_SSITH_P3/Verilog_RTL/mkEpochManager.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:45:54 BST 2020 +// On Thu Jul 2 02:47:40 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkFetchStage.v b/src_SSITH_P3/Verilog_RTL/mkFetchStage.v index 93dfe52..d32e3f0 100644 --- a/src_SSITH_P3/Verilog_RTL/mkFetchStage.v +++ b/src_SSITH_P3/Verilog_RTL/mkFetchStage.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:54:10 BST 2020 +// On Thu Jul 2 02:56:59 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkFmaExecQ.v b/src_SSITH_P3/Verilog_RTL/mkFmaExecQ.v index 30f6e60..8a2f5d7 100644 --- a/src_SSITH_P3/Verilog_RTL/mkFmaExecQ.v +++ b/src_SSITH_P3/Verilog_RTL/mkFmaExecQ.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:53:38 BST 2020 +// On Thu Jul 2 02:55:35 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkFpuMulDivDispToRegFifo.v b/src_SSITH_P3/Verilog_RTL/mkFpuMulDivDispToRegFifo.v index 4283b86..a6aee6c 100644 --- a/src_SSITH_P3/Verilog_RTL/mkFpuMulDivDispToRegFifo.v +++ b/src_SSITH_P3/Verilog_RTL/mkFpuMulDivDispToRegFifo.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:53:51 BST 2020 +// On Thu Jul 2 02:55:49 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkFpuMulDivRegToExeFifo.v b/src_SSITH_P3/Verilog_RTL/mkFpuMulDivRegToExeFifo.v index 1d123cf..21640fd 100644 --- a/src_SSITH_P3/Verilog_RTL/mkFpuMulDivRegToExeFifo.v +++ b/src_SSITH_P3/Verilog_RTL/mkFpuMulDivRegToExeFifo.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:53:52 BST 2020 +// On Thu Jul 2 02:55:49 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkGSelectGHistReg.v b/src_SSITH_P3/Verilog_RTL/mkGSelectGHistReg.v index 52b5d00..49613ec 100644 --- a/src_SSITH_P3/Verilog_RTL/mkGSelectGHistReg.v +++ b/src_SSITH_P3/Verilog_RTL/mkGSelectGHistReg.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:53:52 BST 2020 +// On Thu Jul 2 02:56:42 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkGSelectPred.v b/src_SSITH_P3/Verilog_RTL/mkGSelectPred.v index f8bdbef..158aded 100644 --- a/src_SSITH_P3/Verilog_RTL/mkGSelectPred.v +++ b/src_SSITH_P3/Verilog_RTL/mkGSelectPred.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:53:53 BST 2020 +// On Thu Jul 2 02:56:42 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkGShareGHistReg.v b/src_SSITH_P3/Verilog_RTL/mkGShareGHistReg.v index b294278..a5c42dc 100644 --- a/src_SSITH_P3/Verilog_RTL/mkGShareGHistReg.v +++ b/src_SSITH_P3/Verilog_RTL/mkGShareGHistReg.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:53:53 BST 2020 +// On Thu Jul 2 02:56:43 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkGSharePred.v b/src_SSITH_P3/Verilog_RTL/mkGSharePred.v index 15c3761..3a02e80 100644 --- a/src_SSITH_P3/Verilog_RTL/mkGSharePred.v +++ b/src_SSITH_P3/Verilog_RTL/mkGSharePred.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:53:53 BST 2020 +// On Thu Jul 2 02:56:43 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkIBankWrapper.v b/src_SSITH_P3/Verilog_RTL/mkIBankWrapper.v index 578f452..a4dcf1d 100644 --- a/src_SSITH_P3/Verilog_RTL/mkIBankWrapper.v +++ b/src_SSITH_P3/Verilog_RTL/mkIBankWrapper.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:52:11 BST 2020 +// On Thu Jul 2 02:54:04 BST 2020 // // // Ports: @@ -585,7 +585,7 @@ module mkIBankWrapper(CLK, SEL_ARR_m_fromPQ_data_0_13_BITS_65_TO_2_22_m_f_ETC___d425, addr__h42425; reg [31 : 0] CASE_m_cRqMshrpipelineResp_getRq_BITS_5_TO_2__ETC__q37, - CASE_sel1069_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36; + CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36; reg [2 : 0] CASE_m_rqToPQ_deqP_0_m_rqToPQ_data_0_BITS_2_TO_ETC__q31, x__h45568; reg [1 : 0] CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_1_TO_ETC__q38, @@ -616,7 +616,7 @@ module mkIBankWrapper(CLK, IF_m_pipeline_first__47_BITS_518_TO_516_52_EQ__ETC___d595; wire [5 : 0] IF_m_pipeline_first__47_BITS_521_TO_520_58_EQ__ETC___d600, SEL_ARR_m_rqToPQ_data_0_84_BITS_5_TO_4_94_m_rq_ETC___d806; - wire [3 : 0] sel__h51069; + wire [3 : 0] sel__h51068; wire [2 : 0] IF_m_cRqMshr_pipelineResp_searchEndOfChain_m_c_ETC___d615, SEL_ARR_m_fromPQ_data_0_13_BIT_518_49_m_fromPQ_ETC___d461, SEL_ARR_m_rsToPQ_data_0_10_BIT_515_27_m_rsToPQ_ETC___d739, @@ -1055,7 +1055,7 @@ module mkIBankWrapper(CLK, WILL_FIRE_RL_m_pipelineResp_pRq && !m_pipeline$first[575] ; assign MUX_m_cRqMshr$pipelineResp_setResult_2__VAL_1 = { 4'd15 - m_cRqMshr$pipelineResp_getRq[5:2] != 4'd0, - CASE_sel1069_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36, + CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36, 1'd1, CASE_m_cRqMshrpipelineResp_getRq_BITS_5_TO_2__ETC__q37 } ; assign MUX_m_cRqMshr$pipelineResp_setStateSlot_2__VAL_2 = @@ -1714,7 +1714,7 @@ module mkIBankWrapper(CLK, assign resp_addr__h45726 = { m_cRqMshr$sendRsToP_cRq_getSlot[53:1], m_cRqMshr$sendRsToP_cRq_getRq[10:0] } ; - assign sel__h51069 = m_cRqMshr$pipelineResp_getRq[5:2] + 4'd1 ; + assign sel__h51068 = m_cRqMshr$pipelineResp_getRq[5:2] + 4'd1 ; assign v__h10212 = IF_m_rsToPQ_enqReq_lat_1_whas__1_THEN_m_rsToPQ_ETC___d40 ? v__h10363 : @@ -2150,56 +2150,56 @@ module mkIBankWrapper(CLK, m_fromPQ_data_1[586]; endcase end - always@(sel__h51069 or m_pipeline$first) + always@(sel__h51068 or m_pipeline$first) begin - case (sel__h51069) + case (sel__h51068) 4'd0: - CASE_sel1069_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[31:0]; 4'd1: - CASE_sel1069_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[63:32]; 4'd2: - CASE_sel1069_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[95:64]; 4'd3: - CASE_sel1069_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[127:96]; 4'd4: - CASE_sel1069_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[159:128]; 4'd5: - CASE_sel1069_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[191:160]; 4'd6: - CASE_sel1069_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[223:192]; 4'd7: - CASE_sel1069_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[255:224]; 4'd8: - CASE_sel1069_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[287:256]; 4'd9: - CASE_sel1069_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[319:288]; 4'd10: - CASE_sel1069_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[351:320]; 4'd11: - CASE_sel1069_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[383:352]; 4'd12: - CASE_sel1069_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[415:384]; 4'd13: - CASE_sel1069_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[447:416]; 4'd14: - CASE_sel1069_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[479:448]; 4'd15: - CASE_sel1069_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[511:480]; endcase end diff --git a/src_SSITH_P3/Verilog_RTL/mkICRqMshrWrapper.v b/src_SSITH_P3/Verilog_RTL/mkICRqMshrWrapper.v index 2222c94..c39a248 100644 --- a/src_SSITH_P3/Verilog_RTL/mkICRqMshrWrapper.v +++ b/src_SSITH_P3/Verilog_RTL/mkICRqMshrWrapper.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:52:06 BST 2020 +// On Thu Jul 2 02:53:58 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkICoCache.v b/src_SSITH_P3/Verilog_RTL/mkICoCache.v index e422da8..959f31b 100644 --- a/src_SSITH_P3/Verilog_RTL/mkICoCache.v +++ b/src_SSITH_P3/Verilog_RTL/mkICoCache.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:52:12 BST 2020 +// On Thu Jul 2 02:54:04 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkIPRqMshrWrapper.v b/src_SSITH_P3/Verilog_RTL/mkIPRqMshrWrapper.v index ac14188..7ead3ba 100644 --- a/src_SSITH_P3/Verilog_RTL/mkIPRqMshrWrapper.v +++ b/src_SSITH_P3/Verilog_RTL/mkIPRqMshrWrapper.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:52:07 BST 2020 +// On Thu Jul 2 02:53:59 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkIPipeline.v b/src_SSITH_P3/Verilog_RTL/mkIPipeline.v index 10408d7..dc3c7c5 100644 --- a/src_SSITH_P3/Verilog_RTL/mkIPipeline.v +++ b/src_SSITH_P3/Verilog_RTL/mkIPipeline.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:52:09 BST 2020 +// On Thu Jul 2 02:54:02 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkITlb.v b/src_SSITH_P3/Verilog_RTL/mkITlb.v index 3710d77..d0227f6 100644 --- a/src_SSITH_P3/Verilog_RTL/mkITlb.v +++ b/src_SSITH_P3/Verilog_RTL/mkITlb.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:45:53 BST 2020 +// On Thu Jul 2 02:47:39 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkJtagTap.v b/src_SSITH_P3/Verilog_RTL/mkJtagTap.v index 45ffba2..322715f 100644 --- a/src_SSITH_P3/Verilog_RTL/mkJtagTap.v +++ b/src_SSITH_P3/Verilog_RTL/mkJtagTap.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 24 20:23:27 BST 2020 +// On Thu Jul 2 02:46:12 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkL2Tlb.v b/src_SSITH_P3/Verilog_RTL/mkL2Tlb.v index 3233cfd..ca3cbd1 100644 --- a/src_SSITH_P3/Verilog_RTL/mkL2Tlb.v +++ b/src_SSITH_P3/Verilog_RTL/mkL2Tlb.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:51:44 BST 2020 +// On Thu Jul 2 02:53:30 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkLLCache.v b/src_SSITH_P3/Verilog_RTL/mkLLCache.v index 5507f55..b288a89 100644 --- a/src_SSITH_P3/Verilog_RTL/mkLLCache.v +++ b/src_SSITH_P3/Verilog_RTL/mkLLCache.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:53:24 BST 2020 +// On Thu Jul 2 02:55:19 BST 2020 // // // Ports: @@ -1617,7 +1617,7 @@ module mkLLCache(CLK, cache_cRqMshrpipelineResp_getData_BITS_447_TO_ETC__q119, cache_cRqMshrpipelineResp_getData_BITS_511_TO_ETC__q120, cache_cRqMshrpipelineResp_getData_BITS_63_TO_0__q126, - rqAddr__h296735, + rqAddr__h296734, x_addr__h12321, x_addr__h74358; wire [62 : 0] IF_IF_SEL_ARR_cache_pipeline_first__466_BITS_5_ETC___d3416, @@ -2902,7 +2902,7 @@ module mkLLCache(CLK, cache_cRqMshr$sendRsToDmaC_getRq[2:0] } ; assign MUX_cache_toCQ_enqReq_lat_0$wset_1__VAL_2 = { 522'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, - rqAddr__h296735, + rqAddr__h296734, IF_SEL_ARR_cache_cRqMshr_sendRqToC_getSlot_IF__ETC___d2438, child__h296070 } ; assign MUX_cache_toMInfoQ$enq_1__VAL_1 = @@ -6125,7 +6125,7 @@ module mkLLCache(CLK, cache_rsToCIndexQ_deqP + 4'd1 ; assign next_deqP___1__h38335 = cache_toCQ_deqP + 1'd1 ; assign next_deqP___1__h4227 = cache_rqFromCQ_deqP + 1'd1 ; - assign rqAddr__h296735 = + assign rqAddr__h296734 = (cache_cRqMshr$sendRqToC_getState == 3'd3) ? cache_cRqMshr$sendRqToC_getRq[139:76] : { cache_cRqMshr$sendRqToC_getSlot[58:9], diff --git a/src_SSITH_P3/Verilog_RTL/mkLLPipeline.v b/src_SSITH_P3/Verilog_RTL/mkLLPipeline.v index 83ecca8..6c7184a 100644 --- a/src_SSITH_P3/Verilog_RTL/mkLLPipeline.v +++ b/src_SSITH_P3/Verilog_RTL/mkLLPipeline.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:53:12 BST 2020 +// On Thu Jul 2 02:55:08 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkLSQIssueLdQ.v b/src_SSITH_P3/Verilog_RTL/mkLSQIssueLdQ.v index db276a1..8fc44de 100644 --- a/src_SSITH_P3/Verilog_RTL/mkLSQIssueLdQ.v +++ b/src_SSITH_P3/Verilog_RTL/mkLSQIssueLdQ.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:50:07 BST 2020 +// On Thu Jul 2 02:51:56 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkLastLvCRqMshr.v b/src_SSITH_P3/Verilog_RTL/mkLastLvCRqMshr.v index f45df3f..eb4b242 100644 --- a/src_SSITH_P3/Verilog_RTL/mkLastLvCRqMshr.v +++ b/src_SSITH_P3/Verilog_RTL/mkLastLvCRqMshr.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:53:04 BST 2020 +// On Thu Jul 2 02:55:00 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkMMIOInst.v b/src_SSITH_P3/Verilog_RTL/mkMMIOInst.v index 06e42bf..104987e 100644 --- a/src_SSITH_P3/Verilog_RTL/mkMMIOInst.v +++ b/src_SSITH_P3/Verilog_RTL/mkMMIOInst.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:45:43 BST 2020 +// On Thu Jul 2 02:47:28 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkMemDispToRegFifo.v b/src_SSITH_P3/Verilog_RTL/mkMemDispToRegFifo.v index e24d405..8a70870 100644 --- a/src_SSITH_P3/Verilog_RTL/mkMemDispToRegFifo.v +++ b/src_SSITH_P3/Verilog_RTL/mkMemDispToRegFifo.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:52:24 BST 2020 +// On Thu Jul 2 02:54:18 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkMemLoader.v b/src_SSITH_P3/Verilog_RTL/mkMemLoader.v index 29a9fce..ef6f348 100644 --- a/src_SSITH_P3/Verilog_RTL/mkMemLoader.v +++ b/src_SSITH_P3/Verilog_RTL/mkMemLoader.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:52:39 BST 2020 +// On Thu Jul 2 02:54:36 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkMemRegToExeFifo.v b/src_SSITH_P3/Verilog_RTL/mkMemRegToExeFifo.v index 1eddd77..592ff26 100644 --- a/src_SSITH_P3/Verilog_RTL/mkMemRegToExeFifo.v +++ b/src_SSITH_P3/Verilog_RTL/mkMemRegToExeFifo.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:52:24 BST 2020 +// On Thu Jul 2 02:54:18 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkMinimumExecQ.v b/src_SSITH_P3/Verilog_RTL/mkMinimumExecQ.v index 73c279c..77e09f9 100644 --- a/src_SSITH_P3/Verilog_RTL/mkMinimumExecQ.v +++ b/src_SSITH_P3/Verilog_RTL/mkMinimumExecQ.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:53:38 BST 2020 +// On Thu Jul 2 02:55:35 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkMulExecQ.v b/src_SSITH_P3/Verilog_RTL/mkMulExecQ.v index 083fbf2..1a460bb 100644 --- a/src_SSITH_P3/Verilog_RTL/mkMulExecQ.v +++ b/src_SSITH_P3/Verilog_RTL/mkMulExecQ.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:53:50 BST 2020 +// On Thu Jul 2 02:55:47 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkNullTransCache.v b/src_SSITH_P3/Verilog_RTL/mkNullTransCache.v index a4f6259..8625c0c 100644 --- a/src_SSITH_P3/Verilog_RTL/mkNullTransCache.v +++ b/src_SSITH_P3/Verilog_RTL/mkNullTransCache.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:45:40 BST 2020 +// On Thu Jul 2 02:47:23 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkP3_Core.v b/src_SSITH_P3/Verilog_RTL/mkP3_Core.v index ba7fb28..757a589 100644 --- a/src_SSITH_P3/Verilog_RTL/mkP3_Core.v +++ b/src_SSITH_P3/Verilog_RTL/mkP3_Core.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jul 1 17:07:56 BST 2020 +// On Thu Jul 2 02:59:27 BST 2020 // // // Ports: @@ -1350,7 +1350,7 @@ module mkP3_Core(CLK, // rule RL_rl_ndm_reset_wait assign CAN_FIRE_RL_rl_ndm_reset_wait = (rg_ndm_reset_delay != 8'd1 || - corew$RDY_start && corew$RDY_ndm_reset_client_response_put) && + corew$RDY_ndm_reset_client_response_put && corew$RDY_start) && rg_ndm_reset_delay != 8'd0 ; assign WILL_FIRE_RL_rl_ndm_reset_wait = CAN_FIRE_RL_rl_ndm_reset_wait ; diff --git a/src_SSITH_P3/Verilog_RTL/mkPLIC_16_2_7.v b/src_SSITH_P3/Verilog_RTL/mkPLIC_16_2_7.v index 6551d17..627cd77 100644 --- a/src_SSITH_P3/Verilog_RTL/mkPLIC_16_2_7.v +++ b/src_SSITH_P3/Verilog_RTL/mkPLIC_16_2_7.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:45:12 BST 2020 +// On Thu Jul 2 02:46:53 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkPowerOnReset.v b/src_SSITH_P3/Verilog_RTL/mkPowerOnReset.v index 1b21cdd..6dbfc0e 100644 --- a/src_SSITH_P3/Verilog_RTL/mkPowerOnReset.v +++ b/src_SSITH_P3/Verilog_RTL/mkPowerOnReset.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 24 20:23:22 BST 2020 +// On Thu Jul 2 02:46:08 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkProc.v b/src_SSITH_P3/Verilog_RTL/mkProc.v index 8129743..4eb9c68 100644 --- a/src_SSITH_P3/Verilog_RTL/mkProc.v +++ b/src_SSITH_P3/Verilog_RTL/mkProc.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jul 1 17:07:33 BST 2020 +// On Thu Jul 2 02:59:06 BST 2020 // // // Ports: @@ -2005,7 +2005,7 @@ module mkProc(CLK, CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q24, CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q25, CASE_x22858_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q29, - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1970, + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1971, dword__h150359, ld_data__h188181, v_wdata__h215359, @@ -2034,9 +2034,9 @@ module mkProc(CLK, wire [519 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__561_THE_ETC___d1830; wire [517 : 0] IF_enqDst_1_0_lat_1_whas__634_THEN_enqDst_1_0__ETC___d1680; wire [515 : 0] IF_enqDst_1_0_lat_0_whas__637_THEN_enqDst_1_0__ETC___d1672, - IF_llc_axi4_adapter_rg_rd_rsp_beat_243_BIT_0_2_ETC___d2285, + IF_llc_axi4_adapter_rg_rd_rsp_beat_245_BIT_0_2_ETC___d2287, SEL_ARR_IF_propDstData_1_0_lat_0_whas__561_THE_ETC___d1825; - wire [383 : 0] IF_llc_mem_server_axi4_slave_xactor_shim_awff__ETC___d2018, + wire [383 : 0] IF_llc_mem_server_axi4_slave_xactor_shim_awff__ETC___d2019, SEL_ARR_IF_propDstData_1_0_lat_0_whas__561_THE_ETC___d1807; wire [129 : 0] IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_ETC___d1111, IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_ETC___d1164; @@ -2056,7 +2056,7 @@ module mkProc(CLK, wire [66 : 0] IF_NOT_core_0_mmioToPlatform_cRq_first__21_BIT_ETC___d546, IF_core_0_mmioToPlatform_cRq_first__21_BITS_21_ETC___d544; wire [65 : 0] mmio_axi4_adapter_f_rsps_to_core_first__291_BI_ETC___d1392; - wire [64 : 0] IF_llc_mem_server_propDstData_0_lat_0_whas__10_ETC___d2107; + wire [64 : 0] IF_llc_mem_server_propDstData_0_lat_0_whas__10_ETC___d2108; wire [63 : 0] IF_enqDst_1_0_lat_0_whas__637_THEN_enqDst_1_0__ETC___d1652, IF_mmioPlatform_fromHostQ_empty_80_OR_mmioPlat_ETC___d1159, IF_mmioPlatform_fromHostQ_empty_80_THEN_0_ELSE_ETC___d1157, @@ -2096,10 +2096,10 @@ module mkProc(CLK, IF_mmioPlatform_fetchingWay_363_THEN_mmioPlatf_ETC___d1389, amo_req_data__h39114, lower_data__h44520, - mmioPlatform_mtime_BITS_31_TO_0__q6, - mmioPlatform_mtime_BITS_63_TO_32__q5, - mmioPlatform_mtimecmp_0_BITS_31_TO_0__q8, - mmioPlatform_mtimecmp_0_BITS_63_TO_32__q7, + mmioPlatform_mtime_BITS_31_TO_0__q8, + mmioPlatform_mtime_BITS_63_TO_32__q7, + mmioPlatform_mtimecmp_0_BITS_31_TO_0__q6, + mmioPlatform_mtimecmp_0_BITS_63_TO_32__q5, upper_data__h44521, v__h44376, v__h44413, @@ -2153,8 +2153,8 @@ module mkProc(CLK, IF_enqDst_1_0_lat_0_whas__637_THEN_enqDst_1_0__ETC___d1642, IF_enqDst_1_0_lat_0_whas__637_THEN_enqDst_1_0__ETC___d1662, IF_enqDst_1_0_lat_0_whas__637_THEN_enqDst_1_0__ETC___d1678, - IF_llc_mem_server_enqDst_0_lat_0_whas__112_THE_ETC___d2117, - IF_llc_mem_server_propDstIdx_0_lat_0_whas__097_ETC___d2100, + IF_llc_mem_server_enqDst_0_lat_0_whas__113_THE_ETC___d2118, + IF_llc_mem_server_propDstIdx_0_lat_0_whas__098_ETC___d2101, IF_mmioPlatform_mtimecmp_0_99_ULE_IF_NOT_mmioP_ETC___d1038, IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_ETC___d819, IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_2_ETC___d1100, @@ -2174,9 +2174,9 @@ module mkProc(CLK, IF_propDstIdx_1_lat_0_whas__420_THEN_propDstId_ETC___d1423, NOT_enqDst_0_rl_445_BIT_73_446_451_AND_SEL_ARR_ETC___d1539, NOT_enqDst_1_0_rl_640_BIT_584_641_646_AND_SEL__ETC___d1836, - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239, - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2318, - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2321, + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241, + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2320, + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2323, NOT_mmioPlatform_curReq_97_BITS_66_TO_64_98_EQ_ETC___d1194, NOT_mmioPlatform_curReq_97_BITS_66_TO_64_98_EQ_ETC___d1289, NOT_mmioPlatform_curReq_97_BITS_66_TO_64_98_EQ_ETC___d1300, @@ -2191,6 +2191,7 @@ module mkProc(CLK, NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d993, SEL_ARR_IF_propDstIdx_0_lat_0_whas__413_THEN_p_ETC___d1481, SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__546_THEN_ETC___d1714, + _dand1mmio_axi4_adapter_f_reqs_from_core$EN_deq, _theResult____h13492, core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d523, core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d525, @@ -2203,9 +2204,9 @@ module mkProc(CLK, core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d781, core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d788, core_0_mmioToPlatform_cRq_notEmpty__07_AND_cor_ETC___d764, - llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2250, - llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2036, - llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1935, + llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2252, + llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2037, + llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1936, mmioPlatform_amoWaitWriteResp_304_OR_core_0_RD_ETC___d1307, mmioPlatform_cycle_90_ULT_99___d491, mmioPlatform_fetchingWay_363_ULT_mmioPlatform__ETC___d1372, @@ -2230,6 +2231,7 @@ module mkProc(CLK, mmio_axi4_adapter_f_reqs_from_core_i_notEmpty__ETC___d8, mmio_axi4_adapter_read_req_addr_79_BIT_3_80_PL_ETC___d181, mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ax_ETC___d217, + whichHalf___1__h15055, x__h100756, x__h10399, x__h116294, @@ -3001,36 +3003,32 @@ module mkProc(CLK, // rule RL_sendPRq assign CAN_FIRE_RL_sendPRq = + llc$RDY_to_child_toC_first && llc$RDY_to_child_toC_deq && core_0$RDY_dCacheToParent_fromP_enq && - llc$RDY_to_child_toC_deq && - llc$RDY_to_child_toC_first && !llc$to_child_toC_first[587] && !llc$to_child_toC_first[0] ; assign WILL_FIRE_RL_sendPRq = CAN_FIRE_RL_sendPRq ; // rule RL_sendPRs assign CAN_FIRE_RL_sendPRs = + llc$RDY_to_child_toC_first && llc$RDY_to_child_toC_deq && core_0$RDY_dCacheToParent_fromP_enq && - llc$RDY_to_child_toC_deq && - llc$RDY_to_child_toC_first && llc$to_child_toC_first[587] && !llc$to_child_toC_first[520] ; assign WILL_FIRE_RL_sendPRs = CAN_FIRE_RL_sendPRs ; // rule RL_sendPRq_1 assign CAN_FIRE_RL_sendPRq_1 = + llc$RDY_to_child_toC_first && llc$RDY_to_child_toC_deq && core_0$RDY_iCacheToParent_fromP_enq && - llc$RDY_to_child_toC_deq && - llc$RDY_to_child_toC_first && !llc$to_child_toC_first[587] && llc$to_child_toC_first[0] ; assign WILL_FIRE_RL_sendPRq_1 = CAN_FIRE_RL_sendPRq_1 ; // rule RL_sendPRs_1 assign CAN_FIRE_RL_sendPRs_1 = + llc$RDY_to_child_toC_first && llc$RDY_to_child_toC_deq && core_0$RDY_iCacheToParent_fromP_enq && - llc$RDY_to_child_toC_deq && - llc$RDY_to_child_toC_first && llc$to_child_toC_first[587] && llc$to_child_toC_first[520] ; assign WILL_FIRE_RL_sendPRs_1 = CAN_FIRE_RL_sendPRs_1 ; @@ -3370,7 +3368,7 @@ module mkProc(CLK, // rule RL_llc_mem_server_rl_cacheline_cache_writeback_finish assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish = - llc$RDY_dma_respSt_deq && llc$RDY_dma_respSt_first && + llc$RDY_dma_respSt_first && llc$RDY_dma_respSt_deq && !llc$dma_respSt_first[4] && llc_mem_server_rg_cacheline_cache_state == 3'd1 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish = @@ -3378,7 +3376,7 @@ module mkProc(CLK, // rule RL_llc_mem_server_rl_cacheline_cache_reload_finish assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish = - llc$RDY_dma_respLd_deq && llc$RDY_dma_respLd_first && + llc$RDY_dma_respLd_first && llc$RDY_dma_respLd_deq && !llc$dma_respLd_first[4] && llc_mem_server_rg_cacheline_cache_state == 3'd2 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish = @@ -3399,21 +3397,21 @@ module mkProc(CLK, // rule RL_llc_mem_server_doEnq assign CAN_FIRE_RL_llc_mem_server_doEnq = llc_mem_server_tlbQ$FULL_N && - IF_llc_mem_server_enqDst_0_lat_0_whas__112_THE_ETC___d2117 ; + IF_llc_mem_server_enqDst_0_lat_0_whas__113_THE_ETC___d2118 ; assign WILL_FIRE_RL_llc_mem_server_doEnq = CAN_FIRE_RL_llc_mem_server_doEnq ; // rule RL_llc_mem_server_sendLdRespToTlb assign CAN_FIRE_RL_llc_mem_server_sendLdRespToTlb = - core_0$RDY_tlbToMem_respLd_enq && llc$RDY_dma_respLd_deq && - llc$RDY_dma_respLd_first && + llc$RDY_dma_respLd_first && llc$RDY_dma_respLd_deq && + core_0$RDY_tlbToMem_respLd_enq && llc$dma_respLd_first[4] ; assign WILL_FIRE_RL_llc_mem_server_sendLdRespToTlb = CAN_FIRE_RL_llc_mem_server_sendLdRespToTlb ; // rule RL_llc_mem_server_sendStRespToTlb assign CAN_FIRE_RL_llc_mem_server_sendStRespToTlb = - llc$RDY_dma_respSt_deq && llc$RDY_dma_respSt_first && + llc$RDY_dma_respSt_first && llc$RDY_dma_respSt_deq && llc$dma_respSt_first[4] ; assign WILL_FIRE_RL_llc_mem_server_sendStRespToTlb = CAN_FIRE_RL_llc_mem_server_sendStRespToTlb ; @@ -3467,7 +3465,7 @@ module mkProc(CLK, !llc_mem_server_axi4_slave_xactor_shim_rff_rv[73] && (llc_mem_server_rg_cacheline_cache_state == 3'd3 || llc_mem_server_rg_cacheline_cache_state == 3'd4) && - llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2036 ; + llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2037 ; assign WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req = CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req ; @@ -3479,7 +3477,7 @@ module mkProc(CLK, !llc_mem_server_axi4_slave_xactor_shim_bff_rv[7] && (llc_mem_server_rg_cacheline_cache_state == 3'd3 || llc_mem_server_rg_cacheline_cache_state == 3'd4) && - llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1935 ; + llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1936 ; assign WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req = CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req && !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged ; @@ -3498,7 +3496,7 @@ module mkProc(CLK, !llc_mem_server_axi4_slave_xactor_clearing && llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[98] && llc_mem_server_rg_cacheline_cache_state == 3'd4 && - !llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1935 ; + !llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1936 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss && !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged ; @@ -3509,7 +3507,7 @@ module mkProc(CLK, !llc_mem_server_axi4_slave_xactor_clearing && llc_mem_server_axi4_slave_xactor_shim_arff_rv$port1__read[98] && llc_mem_server_rg_cacheline_cache_state == 3'd4 && - !llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2036 ; + !llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2037 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss && !WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req && @@ -3522,7 +3520,7 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[98] && llc$RDY_dma_memReq_enq && llc_mem_server_rg_cacheline_cache_state == 3'd3 && - !llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1935 ; + !llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1936 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ; @@ -3532,7 +3530,7 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_shim_arff_rv$port1__read[98] && llc$RDY_dma_memReq_enq && llc_mem_server_rg_cacheline_cache_state == 3'd3 && - !llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2036 ; + !llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2037 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld && !WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req && @@ -3623,8 +3621,8 @@ module mkProc(CLK, // rule RL_llc_axi4_adapter_rl_handle_read_req assign CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req = !llc_axi4_adapter_master_xactor_clearing && - llc$RDY_to_mem_toM_deq && llc$RDY_to_mem_toM_first && + llc$RDY_to_mem_toM_deq && !llc_axi4_adapter_master_xactor_shim_arff_rv[98] && llc_axi4_adapter_f_pending_reads$FULL_N && !llc$to_mem_toM_first[644] && @@ -3731,7 +3729,7 @@ module mkProc(CLK, // rule RL_llc_axi4_adapter_rl_handle_read_rsps assign CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps = !llc_axi4_adapter_master_xactor_clearing && - llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2250 ; + llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2252 ; assign WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps ; @@ -3925,7 +3923,7 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:33] != 2'd0 && llc_mem_server_rg_cacheline_cache_data[512], - IF_llc_mem_server_axi4_slave_xactor_shim_awff__ETC___d2018, + IF_llc_mem_server_axi4_slave_xactor_shim_awff__ETC___d2019, (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32] == 3'd1) ? data__h140632 : @@ -4128,10 +4126,10 @@ module mkProc(CLK, !llc_mem_server_axi4_slave_xactor_shim_arff_rv[98] ; assign llc_mem_server_propDstIdx_0_lat_1$whas = !llc_mem_server_enqDst_0_rl[65] && - IF_llc_mem_server_propDstIdx_0_lat_0_whas__097_ETC___d2100 ; + IF_llc_mem_server_propDstIdx_0_lat_0_whas__098_ETC___d2101 ; assign llc_mem_server_enqDst_0_lat_0$wget = { 1'd1, - IF_llc_mem_server_propDstData_0_lat_0_whas__10_ETC___d2107 } ; + IF_llc_mem_server_propDstData_0_lat_0_whas__10_ETC___d2108 } ; assign llc_axi4_adapter_master_xactor_master_bSynth_snk_putWire$wget = { master0_bid, master0_bresp } ; assign llc_axi4_adapter_master_xactor_master_bSynth_snk_putWire$whas = @@ -4346,7 +4344,7 @@ module mkProc(CLK, EN_hart0_put_other_req_put ? hart0_put_other_req_put : set_verbosity_verbosity ; - assign cfg_verbosity$EN = EN_hart0_put_other_req_put || EN_set_verbosity ; + assign cfg_verbosity$EN = EN_set_verbosity || EN_hart0_put_other_req_put ; // register enqDst_0_rl assign enqDst_0_rl$D_IN = @@ -4407,7 +4405,7 @@ module mkProc(CLK, // register llc_axi4_adapter_rg_cline assign llc_axi4_adapter_rg_cline$D_IN = - IF_llc_axi4_adapter_rg_rd_rsp_beat_243_BIT_0_2_ETC___d2285 ; + IF_llc_axi4_adapter_rg_rd_rsp_beat_245_BIT_0_2_ETC___d2287 ; assign llc_axi4_adapter_rg_cline$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps ; @@ -4456,7 +4454,7 @@ module mkProc(CLK, // register llc_mem_server_enqDst_0_rl assign llc_mem_server_enqDst_0_rl$D_IN = { !CAN_FIRE_RL_llc_mem_server_doEnq && - IF_llc_mem_server_enqDst_0_lat_0_whas__112_THE_ETC___d2117, + IF_llc_mem_server_enqDst_0_lat_0_whas__113_THE_ETC___d2118, CAN_FIRE_RL_llc_mem_server_doEnq ? 65'h0AAAAAAAAAAAAAAAA : (llc_mem_server_propDstIdx_0_lat_1$whas ? @@ -4466,13 +4464,13 @@ module mkProc(CLK, // register llc_mem_server_propDstData_0_rl assign llc_mem_server_propDstData_0_rl$D_IN = - IF_llc_mem_server_propDstData_0_lat_0_whas__10_ETC___d2107 ; + IF_llc_mem_server_propDstData_0_lat_0_whas__10_ETC___d2108 ; assign llc_mem_server_propDstData_0_rl$EN = 1'd1 ; // register llc_mem_server_propDstIdx_0_rl assign llc_mem_server_propDstIdx_0_rl$D_IN = !llc_mem_server_propDstIdx_0_lat_1$whas && - IF_llc_mem_server_propDstIdx_0_lat_0_whas__097_ETC___d2100 ; + IF_llc_mem_server_propDstIdx_0_lat_0_whas__098_ETC___d2101 ; assign llc_mem_server_propDstIdx_0_rl$EN = 1'd1 ; // register llc_mem_server_rg_cacheline_cache_addr @@ -4859,7 +4857,7 @@ module mkProc(CLK, // register mmio_axi4_adapter_rg_wr_req_beat assign mmio_axi4_adapter_rg_wr_req_beat$D_IN = - mmio_axi4_adapter_f_reqs_from_core$D_OUT[136:129] != 8'd0 && + !whichHalf___1__h15055 && mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] != 8'd0 && !mmio_axi4_adapter_rg_wr_req_beat && x__h17610 ; @@ -5190,7 +5188,7 @@ module mkProc(CLK, IF_enqDst_1_0_lat_0_whas__637_THEN_enqDst_1_0__ETC___d1672, IF_enqDst_1_0_lat_0_whas__637_THEN_enqDst_1_0__ETC___d1678 } ; assign llc$to_mem_rsFromM_enq_x = - { IF_llc_axi4_adapter_rg_rd_rsp_beat_243_BIT_0_2_ETC___d2285, + { IF_llc_axi4_adapter_rg_rd_rsp_beat_245_BIT_0_2_ETC___d2287, llc_axi4_adapter_f_pending_reads$D_OUT[4:0] } ; assign llc$EN_to_child_rsFromC_enq = CAN_FIRE_RL_doEnq_1 ; assign llc$EN_to_child_rqFromC_enq = CAN_FIRE_RL_doEnq ; @@ -5283,11 +5281,7 @@ module mkProc(CLK, WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req || WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req ; assign mmio_axi4_adapter_f_reqs_from_core$DEQ = - WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && - (mmio_axi4_adapter_f_reqs_from_core$D_OUT[136:129] == 8'd0 || - mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] == 8'd0 || - mmio_axi4_adapter_rg_wr_req_beat || - !mmio_axi4_adapter_soc_map$m_is_IO_addr) || + _dand1mmio_axi4_adapter_f_reqs_from_core$EN_deq || WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St || WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req ; assign mmio_axi4_adapter_f_reqs_from_core$CLR = 1'b0 ; @@ -5370,7 +5364,7 @@ module mkProc(CLK, assign mmio_axi4_adapter_master_shim_wff$D_IN = { wflit_wdata__h17678, wflit_wstrb__h17679, - mmio_axi4_adapter_f_reqs_from_core$D_OUT[136:129] == 8'd0 || + whichHalf___1__h15055 || mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] == 8'd0 || mmio_axi4_adapter_rg_wr_req_beat, 1'd0 } ; @@ -5611,14 +5605,14 @@ module mkProc(CLK, 2'b10 : IF_enqDst_1_0_lat_0_whas__637_THEN_enqDst_1_0__ETC___d1657, IF_enqDst_1_0_lat_1_whas__634_THEN_enqDst_1_0__ETC___d1680 } ; - assign IF_llc_axi4_adapter_rg_rd_rsp_beat_243_BIT_0_2_ETC___d2285 = + assign IF_llc_axi4_adapter_rg_rd_rsp_beat_245_BIT_0_2_ETC___d2287 = { llc_axi4_adapter_rg_rd_rsp_beat[0] ? llc_axi4_adapter_rg_cline[515:512] : { llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[0], llc_axi4_adapter_rg_cline[515:513] }, llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[67:4], llc_axi4_adapter_rg_cline[511:64] } ; - assign IF_llc_mem_server_axi4_slave_xactor_shim_awff__ETC___d2018 = + assign IF_llc_mem_server_axi4_slave_xactor_shim_awff__ETC___d2019 = { (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32] == 3'd7) ? data__h140632 : @@ -5643,15 +5637,15 @@ module mkProc(CLK, 3'd2) ? data__h140632 : llc_mem_server_rg_cacheline_cache_data[191:128] } ; - assign IF_llc_mem_server_enqDst_0_lat_0_whas__112_THE_ETC___d2117 = + assign IF_llc_mem_server_enqDst_0_lat_0_whas__113_THE_ETC___d2118 = llc_mem_server_propDstIdx_0_lat_1$whas ? llc_mem_server_enqDst_0_lat_0$wget[65] : llc_mem_server_enqDst_0_rl[65] ; - assign IF_llc_mem_server_propDstData_0_lat_0_whas__10_ETC___d2107 = + assign IF_llc_mem_server_propDstData_0_lat_0_whas__10_ETC___d2108 = CAN_FIRE_RL_llc_mem_server_srcPropose ? core_0$tlbToMem_memReq_first : llc_mem_server_propDstData_0_rl ; - assign IF_llc_mem_server_propDstIdx_0_lat_0_whas__097_ETC___d2100 = + assign IF_llc_mem_server_propDstIdx_0_lat_0_whas__098_ETC___d2101 = CAN_FIRE_RL_llc_mem_server_srcPropose || llc_mem_server_propDstIdx_0_rl ; assign IF_mmioPlatform_fetchingWay_363_THEN_mmioPlatf_ETC___d1389 = @@ -5696,16 +5690,16 @@ module mkProc(CLK, mmioPlatform_reqData[63:0]) ; assign IF_mmioPlatform_reqBE_05_BIT_4_06_THEN_SEXT_mm_ETC___d1054 = mmioPlatform_reqBE[4] ? - { {32{mmioPlatform_mtime_BITS_63_TO_32__q5[31]}}, - mmioPlatform_mtime_BITS_63_TO_32__q5 } : - { {32{mmioPlatform_mtime_BITS_31_TO_0__q6[31]}}, - mmioPlatform_mtime_BITS_31_TO_0__q6 } ; + { {32{mmioPlatform_mtime_BITS_63_TO_32__q7[31]}}, + mmioPlatform_mtime_BITS_63_TO_32__q7 } : + { {32{mmioPlatform_mtime_BITS_31_TO_0__q8[31]}}, + mmioPlatform_mtime_BITS_31_TO_0__q8 } ; assign IF_mmioPlatform_reqBE_05_BIT_4_06_THEN_SEXT_mm_ETC___d981 = mmioPlatform_reqBE[4] ? - { {32{mmioPlatform_mtimecmp_0_BITS_63_TO_32__q7[31]}}, - mmioPlatform_mtimecmp_0_BITS_63_TO_32__q7 } : - { {32{mmioPlatform_mtimecmp_0_BITS_31_TO_0__q8[31]}}, - mmioPlatform_mtimecmp_0_BITS_31_TO_0__q8 } ; + { {32{mmioPlatform_mtimecmp_0_BITS_63_TO_32__q5[31]}}, + mmioPlatform_mtimecmp_0_BITS_63_TO_32__q5 } : + { {32{mmioPlatform_mtimecmp_0_BITS_31_TO_0__q6[31]}}, + mmioPlatform_mtimecmp_0_BITS_31_TO_0__q6 } ; assign IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_ETC___d1111 = (mmioPlatform_reqFunc[5:4] == 2'd0) ? 130'h2AAAAAAAAAAAAAAA955555554AAAAAAAA : @@ -5782,7 +5776,7 @@ module mkProc(CLK, assign IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d206 = mmio_axi4_adapter_soc_map$m_is_IO_addr ? mmio_axi4_adapter_master_shim_wff$FULL_N && - (mmio_axi4_adapter_f_reqs_from_core$D_OUT[136:129] != 8'd0 && + (!whichHalf___1__h15055 && mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] != 8'd0 && mmio_axi4_adapter_rg_wr_req_beat || mmio_axi4_adapter_master_shim_awff$FULL_N) : @@ -5835,15 +5829,15 @@ module mkProc(CLK, (SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__546_THEN_ETC___d1710 ? !srcRR_1_0 : IF_propDstIdx_1_0_lat_0_whas__546_THEN_propDst_ETC___d1549) ; - assign NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239 = + assign NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241 = llc_axi4_adapter_cfg_verbosity > 4'd1 ; - assign NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2318 = - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239 && + assign NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2320 = + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241 && (llc_axi4_adapter_rg_rd_rsp_beat[0] ? !llc_axi4_adapter_rg_cline[515] : !llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[0]) ; - assign NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2321 = - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239 && + assign NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2323 = + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241 && (llc_axi4_adapter_rg_rd_rsp_beat[0] ? llc_axi4_adapter_rg_cline[515] : llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[0]) ; @@ -5997,12 +5991,18 @@ module mkProc(CLK, (IF_propDstIdx_1_0_lat_0_whas__546_THEN_NOT_pro_ETC___d1712 ? IF_propDstIdx_1_1_lat_0_whas__553_THEN_propDst_ETC___d1556 : IF_propDstIdx_1_0_lat_0_whas__546_THEN_propDst_ETC___d1549) ; + assign _dand1mmio_axi4_adapter_f_reqs_from_core$EN_deq = + WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + (whichHalf___1__h15055 || + mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] == 8'd0 || + mmio_axi4_adapter_rg_wr_req_beat || + !mmio_axi4_adapter_soc_map$m_is_IO_addr) ; assign _theResult_____1_awsize_val__h17116 = (x__h15143 + y__h15144 <= 5'd4) ? 3'b010 : 3'b011 ; assign _theResult____h13492 = - (mmio_axi4_adapter_f_reqs_from_core$D_OUT[136:129] == 8'd0 || + (whichHalf___1__h15055 || mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] == 8'd0) ? - mmio_axi4_adapter_f_reqs_from_core$D_OUT[136:129] == 8'd0 : + whichHalf___1__h15055 : mmio_axi4_adapter_rg_wr_req_beat ; assign addr1__h90533 = { mmioPlatform_curReq[63:3], 3'b0 } ; assign amo_req_data__h39114 = @@ -6077,28 +6077,28 @@ module mkProc(CLK, assign data__h140632 = { llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[9] ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[73:66] : - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1970[63:56], + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1971[63:56], llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[8] ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[65:58] : - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1970[55:48], + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1971[55:48], llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[7] ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[57:50] : - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1970[47:40], + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1971[47:40], llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[6] ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[49:42] : - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1970[39:32], + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1971[39:32], llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[5] ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[41:34] : - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1970[31:24], + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1971[31:24], llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[4] ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[33:26] : - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1970[23:16], + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1971[23:16], llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[3] ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[25:18] : - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1970[15:8], + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1971[15:8], llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[2] ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[17:10] : - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1970[7:0] } ; + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1971[7:0] } ; assign failed_testnum__h223734 = { 1'd0, mmioPlatform_toHostQ_data_0[63:1] } ; assign line_addr__h140065 = @@ -6112,16 +6112,16 @@ module mkProc(CLK, llc_axi4_adapter_master_xactor_shim_arff_rv$port1__read[97:0] ; assign llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q32 = llc_axi4_adapter_master_xactor_shim_awff_rv$port1__read[97:0] ; - assign llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2250 = + assign llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2252 = llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[73] && (llc_axi4_adapter_rg_rd_rsp_beat != 3'd7 || llc$RDY_to_mem_rsFromM_enq && llc_axi4_adapter_f_pending_reads$EMPTY_N) ; assign llc_axi4_adapter_master_xactor_shim_wff_rvpor_ETC__q33 = llc_axi4_adapter_master_xactor_shim_wff_rv$port1__read[73:0] ; - assign llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2036 = + assign llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2037 = line_addr__h150176 == llc_mem_server_rg_cacheline_cache_addr ; - assign llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1935 = + assign llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1936 = line_addr__h140065 == llc_mem_server_rg_cacheline_cache_addr ; assign llc_mem_server_axi4_slave_xactor_shim_bff_rvp_ETC__q30 = llc_mem_server_axi4_slave_xactor_shim_bff_rv$port1__read[6:0] ; @@ -6130,7 +6130,7 @@ module mkProc(CLK, assign lower_data__h44520 = mmioPlatform_waitLowerMSIPCRs ? v__h44413 : 32'd0 ; assign mem_req_rd_addr_arlen__h5411 = - (mmio_axi4_adapter_f_reqs_from_core$D_OUT[136:129] != 8'd0 && + (!whichHalf___1__h15055 && mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] != 8'd0) ? 8'd1 : 8'd0 ; @@ -6142,16 +6142,16 @@ module mkProc(CLK, assign mmioPlatform_cycle_90_ULT_99___d491 = mmioPlatform_cycle < 7'd99 ; assign mmioPlatform_fetchingWay_363_ULT_mmioPlatform__ETC___d1372 = mmioPlatform_fetchingWay < mmioPlatform_reqFunc[0] ; - assign mmioPlatform_mtime_BITS_31_TO_0__q6 = mmioPlatform_mtime[31:0] ; - assign mmioPlatform_mtime_BITS_63_TO_32__q5 = mmioPlatform_mtime[63:32] ; + assign mmioPlatform_mtime_BITS_31_TO_0__q8 = mmioPlatform_mtime[31:0] ; + assign mmioPlatform_mtime_BITS_63_TO_32__q7 = mmioPlatform_mtime[63:32] ; assign mmioPlatform_mtime__h59831 = mmioPlatform_mtime ; assign mmioPlatform_mtimecmp_0_99_ULE_IF_NOT_mmioPlat_ETC___d1029 = mmioPlatform_mtimecmp_0 <= newData__h53320 ; assign mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500 = mmioPlatform_mtimecmp_0 <= mmioPlatform_mtime ; - assign mmioPlatform_mtimecmp_0_BITS_31_TO_0__q8 = + assign mmioPlatform_mtimecmp_0_BITS_31_TO_0__q6 = mmioPlatform_mtimecmp_0[31:0] ; - assign mmioPlatform_mtimecmp_0_BITS_63_TO_32__q7 = + assign mmioPlatform_mtimecmp_0_BITS_63_TO_32__q5 = mmioPlatform_mtimecmp_0[63:32] ; assign mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d584 = (mmioPlatform_mtip_0 || @@ -6275,12 +6275,12 @@ module mkProc(CLK, (IF_NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03__ETC___d957 || !mmioPlatform_mtip_0) ; assign mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253 = - (mmio_axi4_adapter_f_reqs_from_core$D_OUT[136:129] == 8'd0 || + (whichHalf___1__h15055 || mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] == 8'd0 || !mmio_axi4_adapter_rg_wr_req_beat) && mmio_axi4_adapter_cfg_verbosity != 4'd0 ; assign mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d259 = - (mmio_axi4_adapter_f_reqs_from_core$D_OUT[136:129] == 8'd0 || + (whichHalf___1__h15055 || mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] == 8'd0 || !mmio_axi4_adapter_rg_wr_req_beat) && mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15 ; @@ -6310,7 +6310,7 @@ module mkProc(CLK, mmio_axi4_adapter_master_shim_rff$D_OUT[67:4] } } ; assign mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ax_ETC___d217 = mmio_axi4_adapter_soc_map$m_is_IO_addr && - (mmio_axi4_adapter_f_reqs_from_core$D_OUT[136:129] == 8'd0 || + (whichHalf___1__h15055 || mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] == 8'd0 || !mmio_axi4_adapter_rg_wr_req_beat) ; assign newData__h45219 = @@ -6331,6 +6331,8 @@ module mkProc(CLK, assign v__h44413 = { 31'd0, core_0$mmioToPlatform_cRs_first } ; assign v_awaddr__h214948 = { llc$to_mem_toM_first[643:586], 6'h0 } ; assign value__h61538 = mmioPlatform_mtimecmp_0 ; + assign whichHalf___1__h15055 = + mmio_axi4_adapter_f_reqs_from_core$D_OUT[136:129] == 8'd0 ; assign x__h100756 = SEL_ARR_IF_propDstIdx_0_lat_0_whas__413_THEN_p_ETC___d1477 ? srcRR_0 : @@ -7061,28 +7063,28 @@ module mkProc(CLK, begin case (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32]) 3'd0: - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1970 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1971 = llc_mem_server_rg_cacheline_cache_data[63:0]; 3'd1: - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1970 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1971 = llc_mem_server_rg_cacheline_cache_data[127:64]; 3'd2: - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1970 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1971 = llc_mem_server_rg_cacheline_cache_data[191:128]; 3'd3: - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1970 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1971 = llc_mem_server_rg_cacheline_cache_data[255:192]; 3'd4: - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1970 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1971 = llc_mem_server_rg_cacheline_cache_data[319:256]; 3'd5: - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1970 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1971 = llc_mem_server_rg_cacheline_cache_data[383:320]; 3'd6: - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1970 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1971 = llc_mem_server_rg_cacheline_cache_data[447:384]; 3'd7: - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1970 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1971 = llc_mem_server_rg_cacheline_cache_data[511:448]; endcase end @@ -8348,7 +8350,7 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_f_reqs_from_core$D_OUT[136:129] != 8'd0 && + !whichHalf___1__h15055 && mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] != 8'd0 && !mmio_axi4_adapter_rg_wr_req_beat) $write("False"); @@ -8356,7 +8358,7 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0 && - (mmio_axi4_adapter_f_reqs_from_core$D_OUT[136:129] == 8'd0 || + (whichHalf___1__h15055 || mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] == 8'd0 || mmio_axi4_adapter_rg_wr_req_beat)) $write("True"); @@ -8375,10 +8377,10 @@ module mkProc(CLK, mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) $write("first: %d, last: %d, whichHalf: %d", - mmio_axi4_adapter_f_reqs_from_core$D_OUT[136:129] == 8'd0 || + whichHalf___1__h15055 || mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] == 8'd0 || !mmio_axi4_adapter_rg_wr_req_beat, - mmio_axi4_adapter_f_reqs_from_core$D_OUT[136:129] == 8'd0 || + whichHalf___1__h15055 || mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] == 8'd0 || mmio_axi4_adapter_rg_wr_req_beat, _theResult____h13492, @@ -13393,103 +13395,103 @@ module mkProc(CLK, $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write("AXI4_ARFlit { ", "arid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write("'h%h", 5'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write(", ", "araddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write("'h%h", line_addr__h193455); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write(", ", "arlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write("'h%h", 8'd7); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write(", ", "arsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write("AXI4_Size { ", "val: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write("'h%h", 3'b011, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write(", ", "arburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write("INCR"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write(", ", "arlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write("NORMAL"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write(", ", "arcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write("'h%h", 4'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write(", ", "arprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write("'h%h", 3'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write(", ", "arqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write(", ", "arregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write(", ", "aruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_awSynth_src_warnDoDrop) @@ -13570,7 +13572,7 @@ module mkProc(CLK, $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) begin v__h193908 = $stime; #0; @@ -13578,54 +13580,54 @@ module mkProc(CLK, v__h193902 = v__h193908 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsps: beat %0d ", v__h193902, llc_axi4_adapter_rg_rd_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write("AXI4_RFlit { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write("'h%h", llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[72:68]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write("'h%h", llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[67:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239 && + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241 && llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] == 2'd0) $write("OKAY"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239 && + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241 && llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] == 2'd1) $write("EXOKAY"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239 && + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241 && llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] == 2'd2) $write("SLVERR"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239 && + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241 && llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != 2'd0 && llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != @@ -13634,31 +13636,31 @@ module mkProc(CLK, $write("DECERR"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239 && + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241 && llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239 && + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241 && !llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write("'h%h", llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[0], " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && @@ -13752,27 +13754,27 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write(" Response to LLC: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write("MemRsMsg { ", "data: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write("CLine { ", "tag: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write(", ", "data: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write(" >"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write(" }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write(", ", "child: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write(", ", "id: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write("LdMemRqId { ", "refill: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239 && + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241 && llc_axi4_adapter_f_pending_reads$D_OUT[4]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239 && + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241 && !llc_axi4_adapter_f_pending_reads$D_OUT[4]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write(", ", "mshrIdx: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write("'h%h", llc_axi4_adapter_f_pending_reads$D_OUT[3:0], " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write(" }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write("\n"); end // synopsys translate_on diff --git a/src_SSITH_P3/Verilog_RTL/mkRFileSynth.v b/src_SSITH_P3/Verilog_RTL/mkRFileSynth.v index 1a008f5..14f529a 100644 --- a/src_SSITH_P3/Verilog_RTL/mkRFileSynth.v +++ b/src_SSITH_P3/Verilog_RTL/mkRFileSynth.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:48:58 BST 2020 +// On Thu Jul 2 02:50:45 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkRas.v b/src_SSITH_P3/Verilog_RTL/mkRas.v index b6d433b..b82bda2 100644 --- a/src_SSITH_P3/Verilog_RTL/mkRas.v +++ b/src_SSITH_P3/Verilog_RTL/mkRas.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:50:02 BST 2020 +// On Thu Jul 2 02:51:50 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkRegRenamingTable.v b/src_SSITH_P3/Verilog_RTL/mkRegRenamingTable.v index eff8e9c..28f6fa9 100644 --- a/src_SSITH_P3/Verilog_RTL/mkRegRenamingTable.v +++ b/src_SSITH_P3/Verilog_RTL/mkRegRenamingTable.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:46:31 BST 2020 +// On Thu Jul 2 02:48:17 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkReorderBufferSynth.v b/src_SSITH_P3/Verilog_RTL/mkReorderBufferSynth.v index c74409b..985acb0 100644 --- a/src_SSITH_P3/Verilog_RTL/mkReorderBufferSynth.v +++ b/src_SSITH_P3/Verilog_RTL/mkReorderBufferSynth.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:49:39 BST 2020 +// On Thu Jul 2 02:51:26 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkReservationStationAlu.v b/src_SSITH_P3/Verilog_RTL/mkReservationStationAlu.v index a13a7e4..b7407ae 100644 --- a/src_SSITH_P3/Verilog_RTL/mkReservationStationAlu.v +++ b/src_SSITH_P3/Verilog_RTL/mkReservationStationAlu.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:54:23 BST 2020 +// On Thu Jul 2 02:57:11 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkReservationStationFpuMulDiv.v b/src_SSITH_P3/Verilog_RTL/mkReservationStationFpuMulDiv.v index 80c922e..83272b2 100644 --- a/src_SSITH_P3/Verilog_RTL/mkReservationStationFpuMulDiv.v +++ b/src_SSITH_P3/Verilog_RTL/mkReservationStationFpuMulDiv.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:49:52 BST 2020 +// On Thu Jul 2 02:51:40 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkReservationStationMem.v b/src_SSITH_P3/Verilog_RTL/mkReservationStationMem.v index f9b935e..633751c 100644 --- a/src_SSITH_P3/Verilog_RTL/mkReservationStationMem.v +++ b/src_SSITH_P3/Verilog_RTL/mkReservationStationMem.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:49:47 BST 2020 +// On Thu Jul 2 02:51:35 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkRobRowSynth.v b/src_SSITH_P3/Verilog_RTL/mkRobRowSynth.v index b94cd19..a72426d 100644 --- a/src_SSITH_P3/Verilog_RTL/mkRobRowSynth.v +++ b/src_SSITH_P3/Verilog_RTL/mkRobRowSynth.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:49:08 BST 2020 +// On Thu Jul 2 02:50:55 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkScoreboardAggr.v b/src_SSITH_P3/Verilog_RTL/mkScoreboardAggr.v index f3160ac..c357f95 100644 --- a/src_SSITH_P3/Verilog_RTL/mkScoreboardAggr.v +++ b/src_SSITH_P3/Verilog_RTL/mkScoreboardAggr.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jul 1 17:05:30 BST 2020 +// On Thu Jul 2 02:53:09 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkScoreboardCons.v b/src_SSITH_P3/Verilog_RTL/mkScoreboardCons.v index 0161f17..9ad03e7 100644 --- a/src_SSITH_P3/Verilog_RTL/mkScoreboardCons.v +++ b/src_SSITH_P3/Verilog_RTL/mkScoreboardCons.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jul 1 17:05:23 BST 2020 +// On Thu Jul 2 02:53:02 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkSimpleRespQ.v b/src_SSITH_P3/Verilog_RTL/mkSimpleRespQ.v index 731cdc5..b36ae0d 100644 --- a/src_SSITH_P3/Verilog_RTL/mkSimpleRespQ.v +++ b/src_SSITH_P3/Verilog_RTL/mkSimpleRespQ.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:53:38 BST 2020 +// On Thu Jul 2 02:55:35 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkSoC_Map.v b/src_SSITH_P3/Verilog_RTL/mkSoC_Map.v index aff3d1b..cbc1583 100644 --- a/src_SSITH_P3/Verilog_RTL/mkSoC_Map.v +++ b/src_SSITH_P3/Verilog_RTL/mkSoC_Map.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:45:07 BST 2020 +// On Thu Jul 2 02:46:48 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkSpecTagManager.v b/src_SSITH_P3/Verilog_RTL/mkSpecTagManager.v index 2118078..36346da 100644 --- a/src_SSITH_P3/Verilog_RTL/mkSpecTagManager.v +++ b/src_SSITH_P3/Verilog_RTL/mkSpecTagManager.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:48:49 BST 2020 +// On Thu Jul 2 02:50:35 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkSplitLSQ.v b/src_SSITH_P3/Verilog_RTL/mkSplitLSQ.v index e135a28..bdfba73 100644 --- a/src_SSITH_P3/Verilog_RTL/mkSplitLSQ.v +++ b/src_SSITH_P3/Verilog_RTL/mkSplitLSQ.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:50:45 BST 2020 +// On Thu Jul 2 02:52:33 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkSplitTransCache.v b/src_SSITH_P3/Verilog_RTL/mkSplitTransCache.v index 077739d..e5190dc 100644 --- a/src_SSITH_P3/Verilog_RTL/mkSplitTransCache.v +++ b/src_SSITH_P3/Verilog_RTL/mkSplitTransCache.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:45:39 BST 2020 +// On Thu Jul 2 02:47:22 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkStoreBufferEhr.v b/src_SSITH_P3/Verilog_RTL/mkStoreBufferEhr.v index da5e7b0..fa7c126 100644 --- a/src_SSITH_P3/Verilog_RTL/mkStoreBufferEhr.v +++ b/src_SSITH_P3/Verilog_RTL/mkStoreBufferEhr.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:46:04 BST 2020 +// On Thu Jul 2 02:47:50 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkSyncBramFifo_w36_d512.v b/src_SSITH_P3/Verilog_RTL/mkSyncBramFifo_w36_d512.v index 3570f20..89d0978 100644 --- a/src_SSITH_P3/Verilog_RTL/mkSyncBramFifo_w36_d512.v +++ b/src_SSITH_P3/Verilog_RTL/mkSyncBramFifo_w36_d512.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 24 20:31:55 BST 2020 +// On Thu Jul 2 02:54:30 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkSyncFifo_w32_d16.v b/src_SSITH_P3/Verilog_RTL/mkSyncFifo_w32_d16.v index 1a41439..903e663 100644 --- a/src_SSITH_P3/Verilog_RTL/mkSyncFifo_w32_d16.v +++ b/src_SSITH_P3/Verilog_RTL/mkSyncFifo_w32_d16.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 24 20:31:55 BST 2020 +// On Thu Jul 2 02:54:30 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkTagController.v b/src_SSITH_P3/Verilog_RTL/mkTagController.v index 8ec3206..6db409c 100644 --- a/src_SSITH_P3/Verilog_RTL/mkTagController.v +++ b/src_SSITH_P3/Verilog_RTL/mkTagController.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 24 20:34:04 BST 2020 +// On Thu Jul 2 02:56:37 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkTourGHistReg.v b/src_SSITH_P3/Verilog_RTL/mkTourGHistReg.v index c9315a3..77d6b46 100644 --- a/src_SSITH_P3/Verilog_RTL/mkTourGHistReg.v +++ b/src_SSITH_P3/Verilog_RTL/mkTourGHistReg.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:53:54 BST 2020 +// On Thu Jul 2 02:56:43 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkTourPred.v b/src_SSITH_P3/Verilog_RTL/mkTourPred.v index fa6b54e..edd6088 100644 --- a/src_SSITH_P3/Verilog_RTL/mkTourPred.v +++ b/src_SSITH_P3/Verilog_RTL/mkTourPred.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:53:54 BST 2020 +// On Thu Jul 2 02:56:44 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkTourPredSecure.v b/src_SSITH_P3/Verilog_RTL/mkTourPredSecure.v index 52c8769..1b82c22 100644 --- a/src_SSITH_P3/Verilog_RTL/mkTourPredSecure.v +++ b/src_SSITH_P3/Verilog_RTL/mkTourPredSecure.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:53:55 BST 2020 +// On Thu Jul 2 02:56:44 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkXilinxFpDiv.v b/src_SSITH_P3/Verilog_RTL/mkXilinxFpDiv.v index 6ccee51..ce2bbdf 100644 --- a/src_SSITH_P3/Verilog_RTL/mkXilinxFpDiv.v +++ b/src_SSITH_P3/Verilog_RTL/mkXilinxFpDiv.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 24 20:32:50 BST 2020 +// On Thu Jul 2 02:55:23 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkXilinxFpDivIP.v b/src_SSITH_P3/Verilog_RTL/mkXilinxFpDivIP.v index cae3995..81f24da 100644 --- a/src_SSITH_P3/Verilog_RTL/mkXilinxFpDivIP.v +++ b/src_SSITH_P3/Verilog_RTL/mkXilinxFpDivIP.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 24 20:32:50 BST 2020 +// On Thu Jul 2 02:55:23 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkXilinxFpDivSim.v b/src_SSITH_P3/Verilog_RTL/mkXilinxFpDivSim.v index bdc6945..a51d531 100644 --- a/src_SSITH_P3/Verilog_RTL/mkXilinxFpDivSim.v +++ b/src_SSITH_P3/Verilog_RTL/mkXilinxFpDivSim.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 24 20:32:50 BST 2020 +// On Thu Jul 2 02:55:23 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkXilinxFpFma.v b/src_SSITH_P3/Verilog_RTL/mkXilinxFpFma.v index c118fe7..e0abe15 100644 --- a/src_SSITH_P3/Verilog_RTL/mkXilinxFpFma.v +++ b/src_SSITH_P3/Verilog_RTL/mkXilinxFpFma.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 24 20:32:50 BST 2020 +// On Thu Jul 2 02:55:23 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkXilinxFpFmaIP.v b/src_SSITH_P3/Verilog_RTL/mkXilinxFpFmaIP.v index b2c85cf..71c0bd2 100644 --- a/src_SSITH_P3/Verilog_RTL/mkXilinxFpFmaIP.v +++ b/src_SSITH_P3/Verilog_RTL/mkXilinxFpFmaIP.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 24 20:32:50 BST 2020 +// On Thu Jul 2 02:55:23 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkXilinxFpFmaSim.v b/src_SSITH_P3/Verilog_RTL/mkXilinxFpFmaSim.v index 3b0d41f..86a3886 100644 --- a/src_SSITH_P3/Verilog_RTL/mkXilinxFpFmaSim.v +++ b/src_SSITH_P3/Verilog_RTL/mkXilinxFpFmaSim.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 24 20:32:50 BST 2020 +// On Thu Jul 2 02:55:23 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkXilinxFpSqrt.v b/src_SSITH_P3/Verilog_RTL/mkXilinxFpSqrt.v index c8f3301..23e5d8a 100644 --- a/src_SSITH_P3/Verilog_RTL/mkXilinxFpSqrt.v +++ b/src_SSITH_P3/Verilog_RTL/mkXilinxFpSqrt.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 24 20:32:50 BST 2020 +// On Thu Jul 2 02:55:23 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkXilinxFpSqrtIP.v b/src_SSITH_P3/Verilog_RTL/mkXilinxFpSqrtIP.v index 2c53437..72fa192 100644 --- a/src_SSITH_P3/Verilog_RTL/mkXilinxFpSqrtIP.v +++ b/src_SSITH_P3/Verilog_RTL/mkXilinxFpSqrtIP.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 24 20:32:50 BST 2020 +// On Thu Jul 2 02:55:23 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkXilinxFpSqrtSim.v b/src_SSITH_P3/Verilog_RTL/mkXilinxFpSqrtSim.v index 89c5e28..37fdff6 100644 --- a/src_SSITH_P3/Verilog_RTL/mkXilinxFpSqrtSim.v +++ b/src_SSITH_P3/Verilog_RTL/mkXilinxFpSqrtSim.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 24 20:32:50 BST 2020 +// On Thu Jul 2 02:55:23 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/module_alu.v b/src_SSITH_P3/Verilog_RTL/module_alu.v index a9f9800..69b174e 100644 --- a/src_SSITH_P3/Verilog_RTL/module_alu.v +++ b/src_SSITH_P3/Verilog_RTL/module_alu.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:45:25 BST 2020 +// On Thu Jul 2 02:47:07 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/module_aluBr.v b/src_SSITH_P3/Verilog_RTL/module_aluBr.v index c8bd44b..518a50c 100644 --- a/src_SSITH_P3/Verilog_RTL/module_aluBr.v +++ b/src_SSITH_P3/Verilog_RTL/module_aluBr.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:45:27 BST 2020 +// On Thu Jul 2 02:47:09 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/module_amoExec.v b/src_SSITH_P3/Verilog_RTL/module_amoExec.v index f0e0b02..24cc5e3 100644 --- a/src_SSITH_P3/Verilog_RTL/module_amoExec.v +++ b/src_SSITH_P3/Verilog_RTL/module_amoExec.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:45:06 BST 2020 +// On Thu Jul 2 02:46:45 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/module_basicExec.v b/src_SSITH_P3/Verilog_RTL/module_basicExec.v index 756ad26..b31032f 100644 --- a/src_SSITH_P3/Verilog_RTL/module_basicExec.v +++ b/src_SSITH_P3/Verilog_RTL/module_basicExec.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:45:28 BST 2020 +// On Thu Jul 2 02:47:10 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/module_brAddrCalc.v b/src_SSITH_P3/Verilog_RTL/module_brAddrCalc.v index 20fa1f2..b6aa6b5 100644 --- a/src_SSITH_P3/Verilog_RTL/module_brAddrCalc.v +++ b/src_SSITH_P3/Verilog_RTL/module_brAddrCalc.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:45:27 BST 2020 +// On Thu Jul 2 02:47:09 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/module_capChecks.v b/src_SSITH_P3/Verilog_RTL/module_capChecks.v index 7e7e1b1..4ce00f1 100644 --- a/src_SSITH_P3/Verilog_RTL/module_capChecks.v +++ b/src_SSITH_P3/Verilog_RTL/module_capChecks.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:45:24 BST 2020 +// On Thu Jul 2 02:47:06 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/module_capInspect.v b/src_SSITH_P3/Verilog_RTL/module_capInspect.v index d6e32bc..887e628 100644 --- a/src_SSITH_P3/Verilog_RTL/module_capInspect.v +++ b/src_SSITH_P3/Verilog_RTL/module_capInspect.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:45:27 BST 2020 +// On Thu Jul 2 02:47:09 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/module_capModify.v b/src_SSITH_P3/Verilog_RTL/module_capModify.v index 21db3a4..39de667 100644 --- a/src_SSITH_P3/Verilog_RTL/module_capModify.v +++ b/src_SSITH_P3/Verilog_RTL/module_capModify.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:45:27 BST 2020 +// On Thu Jul 2 02:47:09 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/module_checkForException.v b/src_SSITH_P3/Verilog_RTL/module_checkForException.v index 5f3e268..88d46e5 100644 --- a/src_SSITH_P3/Verilog_RTL/module_checkForException.v +++ b/src_SSITH_P3/Verilog_RTL/module_checkForException.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:45:29 BST 2020 +// On Thu Jul 2 02:47:11 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/module_decode.v b/src_SSITH_P3/Verilog_RTL/module_decode.v index f4a5472..aef0a68 100644 --- a/src_SSITH_P3/Verilog_RTL/module_decode.v +++ b/src_SSITH_P3/Verilog_RTL/module_decode.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:49:58 BST 2020 +// On Thu Jul 2 02:51:46 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/module_decodeBrPred.v b/src_SSITH_P3/Verilog_RTL/module_decodeBrPred.v index 51876d2..c692635 100644 --- a/src_SSITH_P3/Verilog_RTL/module_decodeBrPred.v +++ b/src_SSITH_P3/Verilog_RTL/module_decodeBrPred.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:49:54 BST 2020 +// On Thu Jul 2 02:51:43 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/module_execFpuSimple.v b/src_SSITH_P3/Verilog_RTL/module_execFpuSimple.v index 59badfc..395bb44 100644 --- a/src_SSITH_P3/Verilog_RTL/module_execFpuSimple.v +++ b/src_SSITH_P3/Verilog_RTL/module_execFpuSimple.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:53:45 BST 2020 +// On Thu Jul 2 02:55:42 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/module_prepareBoundsCheck.v b/src_SSITH_P3/Verilog_RTL/module_prepareBoundsCheck.v index 1100df8..e5808b1 100644 --- a/src_SSITH_P3/Verilog_RTL/module_prepareBoundsCheck.v +++ b/src_SSITH_P3/Verilog_RTL/module_prepareBoundsCheck.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:45:25 BST 2020 +// On Thu Jul 2 02:47:07 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/module_setBoundsALU.v b/src_SSITH_P3/Verilog_RTL/module_setBoundsALU.v index 907c720..753ab1d 100644 --- a/src_SSITH_P3/Verilog_RTL/module_setBoundsALU.v +++ b/src_SSITH_P3/Verilog_RTL/module_setBoundsALU.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:45:25 BST 2020 +// On Thu Jul 2 02:47:07 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/module_specialRWALU.v b/src_SSITH_P3/Verilog_RTL/module_specialRWALU.v index 0397d99..aa771f7 100644 --- a/src_SSITH_P3/Verilog_RTL/module_specialRWALU.v +++ b/src_SSITH_P3/Verilog_RTL/module_specialRWALU.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:45:27 BST 2020 +// On Thu Jul 2 02:47:09 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkAluDispToRegFifo.v b/src_SSITH_P3/Verilog_RTL_sim/mkAluDispToRegFifo.v index e2a1928..725820f 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkAluDispToRegFifo.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkAluDispToRegFifo.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:42:40 BST 2020 +// On Thu Jul 2 02:57:33 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkAluExeToFinFifo.v b/src_SSITH_P3/Verilog_RTL_sim/mkAluExeToFinFifo.v index de83815..c2258ea 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkAluExeToFinFifo.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkAluExeToFinFifo.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:42:41 BST 2020 +// On Thu Jul 2 02:57:34 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkAluRegToExeFifo.v b/src_SSITH_P3/Verilog_RTL_sim/mkAluRegToExeFifo.v index 90fdac5..68659bc 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkAluRegToExeFifo.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkAluRegToExeFifo.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:42:41 BST 2020 +// On Thu Jul 2 02:57:34 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkBht.v b/src_SSITH_P3/Verilog_RTL_sim/mkBht.v index d35659f..d05ac07 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkBht.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkBht.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:41:33 BST 2020 +// On Thu Jul 2 02:55:33 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkCore.v b/src_SSITH_P3/Verilog_RTL_sim/mkCore.v index 527f887..b018668 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkCore.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkCore.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jul 1 17:03:59 BST 2020 +// On Thu Jul 2 02:58:36 BST 2020 // // // Ports: @@ -3585,7 +3585,7 @@ module mkCore(CLK, MUX_fetchStage$redirect_1__VAL_1, MUX_fetchStage$redirect_1__VAL_6; wire [64 : 0] MUX_f_csr_rsps$enq_1__VAL_3, MUX_f_fpr_rsps$enq_1__VAL_3; - wire [63 : 0] MUX_commitStage_rg_serial_num$write_1__VAL_1, + wire [63 : 0] MUX_commitStage_rg_serial_num$write_1__VAL_2, MUX_commitStage_rg_serial_num$write_1__VAL_3, MUX_csrf_minstret_ehr_data_lat_0$wset_1__VAL_2, MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1, @@ -3593,7 +3593,7 @@ module mkCore(CLK, MUX_csrf_mtval_csr$write_1__VAL_1, MUX_csrf_rg_dcsr$write_1__VAL_1, MUX_csrf_rg_dcsr$write_1__VAL_3, - MUX_csrf_rg_tdata3$write_1__VAL_2, + MUX_csrf_rg_tselect$write_1__VAL_2, MUX_csrf_stval_csr$write_1__VAL_1; wire [58 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_3__VAL_1, MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_3__VAL_2, @@ -3740,7 +3740,7 @@ module mkCore(CLK, MUX_epochManager$updatePrevEpoch_0_update_1__SEL_2, MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2, MUX_f_run_halt_rsps$enq_1__SEL_1, - MUX_flush_reservation$write_1__SEL_1, + MUX_flush_reservation$write_1__SEL_2, MUX_flush_tlbs$write_1__SEL_1, MUX_regRenamingTable$rename_0_getRename_1__SEL_1, MUX_regRenamingTable$rename_0_getRename_1__SEL_2, @@ -3762,47 +3762,48 @@ module mkCore(CLK, MUX_sbAggr$setReady_4_put_1__SEL_2, MUX_sbCons$setReady_3_put_1__SEL_1, MUX_sbCons$setReady_3_put_1__SEL_2, - MUX_sbCons$setReady_3_put_1__SEL_3; + MUX_sbCons$setReady_3_put_1__SEL_3, + MUX_started$write_1__SEL_1; // declarations used by system tasks // synopsys translate_off - reg [63 : 0] v__h215838; - reg [63 : 0] v__h218174; - reg [63 : 0] v__h275405; - reg [63 : 0] v__h351164; - reg [63 : 0] v__h427780; + reg [63 : 0] v__h215836; + reg [63 : 0] v__h218172; + reg [63 : 0] v__h275404; + reg [63 : 0] v__h351162; + reg [63 : 0] v__h427778; // synopsys translate_on // remaining internal signals reg [515 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5511; reg [127 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d4911; - reg [65 : 0] thin_address__h864888, thin_address__h906786; - reg [63 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q366, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q367, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q293, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q294, + reg [65 : 0] thin_address__h864886, thin_address__h906783; + reg [63 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q368, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q369, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q295, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q296, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q297, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q298, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q306, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q307, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q299, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q300, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q308, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q309, CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q18, CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q19, CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q20, CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q21, - CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q371, - CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q372, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q320, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q299, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q300, + CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q373, + CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q374, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q322, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q301, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q302, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q303, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q304, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q309, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q310, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q305, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q306, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q311, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q312, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q313, CASE_coreFix_memExe_lsqfirstLd_BIT_37_0_coreF_ETC__q34, CASE_coreFix_memExe_lsqfirstLd_BIT_37_0_mmio__ETC__q36, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14201, @@ -3815,33 +3816,33 @@ module mkCore(CLK, SEL_ARR_coreFix_memExe_forwardQ_data_0_224_BIT_ETC___d2242, SEL_ARR_coreFix_memExe_memRespLdQ_data_0_140_B_ETC___d2154, SEL_ARR_coreFix_memExe_memRespLdQ_data_0_140_B_ETC___d2158, - addr__h509973, - addr__h850291, - addr__h895062, - data_out__h1031472, - trap_val__h1007620, - x__h267669; + addr__h509971, + addr__h850288, + addr__h895060, + data_out__h1031505, + trap_val__h1007654, + x__h267667; reg [51 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q29, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q31, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q33, - CASE_guard09416_0b0_theResult___snd17328_BITS__ETC__q233, - CASE_guard09416_0b0_theResult___snd17328_BITS__ETC__q234, - CASE_guard18728_0b0_sfdin26948_BITS_56_TO_5_0b_ETC__q235, - CASE_guard18728_0b0_sfdin26948_BITS_56_TO_5_0b_ETC__q236, - CASE_guard27797_0b0_theResult___snd35733_BITS__ETC__q237, - CASE_guard27797_0b0_theResult___snd35733_BITS__ETC__q238, - CASE_guard31259_0b0_theResult___snd39171_BITS__ETC__q229, - CASE_guard31259_0b0_theResult___snd39171_BITS__ETC__q230, - CASE_guard40571_0b0_sfdin48791_BITS_56_TO_5_0b_ETC__q227, - CASE_guard40571_0b0_sfdin48791_BITS_56_TO_5_0b_ETC__q228, - CASE_guard49640_0b0_theResult___snd57576_BITS__ETC__q231, - CASE_guard49640_0b0_theResult___snd57576_BITS__ETC__q232, - CASE_guard70112_0b0_theResult___snd78024_BITS__ETC__q217, - CASE_guard70112_0b0_theResult___snd78024_BITS__ETC__q218, - CASE_guard79424_0b0_sfdin87644_BITS_56_TO_5_0b_ETC__q221, - CASE_guard79424_0b0_sfdin87644_BITS_56_TO_5_0b_ETC__q222, - CASE_guard88493_0b0_theResult___snd96429_BITS__ETC__q219, - CASE_guard88493_0b0_theResult___snd96429_BITS__ETC__q220, + CASE_guard09412_0b0_theResult___snd17324_BITS__ETC__q233, + CASE_guard09412_0b0_theResult___snd17324_BITS__ETC__q234, + CASE_guard18724_0b0_sfdin26944_BITS_56_TO_5_0b_ETC__q235, + CASE_guard18724_0b0_sfdin26944_BITS_56_TO_5_0b_ETC__q236, + CASE_guard27793_0b0_theResult___snd35729_BITS__ETC__q237, + CASE_guard27793_0b0_theResult___snd35729_BITS__ETC__q238, + CASE_guard31255_0b0_theResult___snd39167_BITS__ETC__q227, + CASE_guard31255_0b0_theResult___snd39167_BITS__ETC__q228, + CASE_guard40567_0b0_sfdin48787_BITS_56_TO_5_0b_ETC__q229, + CASE_guard40567_0b0_sfdin48787_BITS_56_TO_5_0b_ETC__q230, + CASE_guard49636_0b0_theResult___snd57572_BITS__ETC__q231, + CASE_guard49636_0b0_theResult___snd57572_BITS__ETC__q232, + CASE_guard70108_0b0_theResult___snd78020_BITS__ETC__q217, + CASE_guard70108_0b0_theResult___snd78020_BITS__ETC__q218, + CASE_guard79420_0b0_sfdin87640_BITS_56_TO_5_0b_ETC__q219, + CASE_guard79420_0b0_sfdin87640_BITS_56_TO_5_0b_ETC__q220, + CASE_guard88489_0b0_theResult___snd96425_BITS__ETC__q221, + CASE_guard88489_0b0_theResult___snd96425_BITS__ETC__q222, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d13376, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d13403, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d13422, @@ -3855,108 +3856,108 @@ module mkCore(CLK, IF_coreFix_aluExe_1_dispToRegQ_first__5790_BIT_ETC___d17440; reg [31 : 0] SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_235_ETC___d1876, SEL_ARR_mmio_dataRespQ_data_0_393_BITS_31_TO_0_ETC___d2046, - x__h267824; - reg [29 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_22_ETC__q349, - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_817_ETC__q288, - CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q343, - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_22_ETC__q360, - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_817_ETC__q283, - CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q354, - CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q369, - CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q365, + x__h267822; + reg [29 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_22_ETC__q351, + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_817_ETC__q290, + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q345, + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_22_ETC__q362, + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_817_ETC__q285, + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q356, + CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q371, + CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q367, IF_fetchStage_pipelines_0_first__0544_BITS_268_ETC___d20670, IF_fetchStage_pipelines_1_first__0553_BITS_268_ETC___d21642; - reg [22 : 0] CASE_guard07364_0b0_theResult___snd15387_BITS__ETC__q66, - CASE_guard07364_0b0_theResult___snd15387_BITS__ETC__q67, - CASE_guard26640_0b0_sfdin34733_BITS_56_TO_34_0_ETC__q97, - CASE_guard26640_0b0_sfdin34733_BITS_56_TO_34_0_ETC__q98, - CASE_guard35347_0b0_theResult___snd43346_BITS__ETC__q95, - CASE_guard35347_0b0_theResult___snd43346_BITS__ETC__q96, - CASE_guard44277_0b0_sfdin52499_BITS_56_TO_34_0_ETC__q100, - CASE_guard44277_0b0_sfdin52499_BITS_56_TO_34_0_ETC__q99, - CASE_guard53113_0b0_theResult___snd61136_BITS__ETC__q101, - CASE_guard53113_0b0_theResult___snd61136_BITS__ETC__q102, - CASE_guard72387_0b0_sfdin80480_BITS_56_TO_34_0_ETC__q132, - CASE_guard72387_0b0_sfdin80480_BITS_56_TO_34_0_ETC__q133, - CASE_guard80889_0b0_sfdin88984_BITS_56_TO_34_0_ETC__q60, - CASE_guard80889_0b0_sfdin88984_BITS_56_TO_34_0_ETC__q61, - CASE_guard81094_0b0_theResult___snd89093_BITS__ETC__q130, - CASE_guard81094_0b0_theResult___snd89093_BITS__ETC__q131, - CASE_guard89598_0b0_theResult___snd97597_BITS__ETC__q62, - CASE_guard89598_0b0_theResult___snd97597_BITS__ETC__q63, - CASE_guard90024_0b0_sfdin98246_BITS_56_TO_34_0_ETC__q134, - CASE_guard90024_0b0_sfdin98246_BITS_56_TO_34_0_ETC__q135, - CASE_guard98528_0b0_sfdin06750_BITS_56_TO_34_0_ETC__q64, - CASE_guard98528_0b0_sfdin06750_BITS_56_TO_34_0_ETC__q65, - CASE_guard98860_0b0_theResult___snd06883_BITS__ETC__q136, - CASE_guard98860_0b0_theResult___snd06883_BITS__ETC__q137, - _theResult___fst_sfd__h580862, - _theResult___fst_sfd__h589585, - _theResult___fst_sfd__h598167, - _theResult___fst_sfd__h607351, - _theResult___fst_sfd__h615987, - _theResult___fst_sfd__h626613, - _theResult___fst_sfd__h635334, - _theResult___fst_sfd__h643916, - _theResult___fst_sfd__h653100, - _theResult___fst_sfd__h661736, - _theResult___fst_sfd__h672360, - _theResult___fst_sfd__h681081, - _theResult___fst_sfd__h689663, - _theResult___fst_sfd__h698847, - _theResult___fst_sfd__h707483; - reg [17 : 0] CASE_csrf_mepcc_reg_data_rl_BITS_52_TO_35_2621_ETC__q277, - CASE_csrf_sepcc_reg_data_rl_BITS_52_TO_35_2621_ETC__q276, - thin_otype__h864893, - thin_otype__h906791; + reg [22 : 0] CASE_guard07361_0b0_theResult___snd15384_BITS__ETC__q66, + CASE_guard07361_0b0_theResult___snd15384_BITS__ETC__q67, + CASE_guard26637_0b0_sfdin34730_BITS_56_TO_34_0_ETC__q95, + CASE_guard26637_0b0_sfdin34730_BITS_56_TO_34_0_ETC__q96, + CASE_guard35344_0b0_theResult___snd43343_BITS__ETC__q97, + CASE_guard35344_0b0_theResult___snd43343_BITS__ETC__q98, + CASE_guard44274_0b0_sfdin52496_BITS_56_TO_34_0_ETC__q100, + CASE_guard44274_0b0_sfdin52496_BITS_56_TO_34_0_ETC__q99, + CASE_guard53110_0b0_theResult___snd61133_BITS__ETC__q101, + CASE_guard53110_0b0_theResult___snd61133_BITS__ETC__q102, + CASE_guard72384_0b0_sfdin80477_BITS_56_TO_34_0_ETC__q132, + CASE_guard72384_0b0_sfdin80477_BITS_56_TO_34_0_ETC__q133, + CASE_guard80886_0b0_sfdin88981_BITS_56_TO_34_0_ETC__q62, + CASE_guard80886_0b0_sfdin88981_BITS_56_TO_34_0_ETC__q63, + CASE_guard81091_0b0_theResult___snd89090_BITS__ETC__q130, + CASE_guard81091_0b0_theResult___snd89090_BITS__ETC__q131, + CASE_guard89595_0b0_theResult___snd97594_BITS__ETC__q60, + CASE_guard89595_0b0_theResult___snd97594_BITS__ETC__q61, + CASE_guard90021_0b0_sfdin98243_BITS_56_TO_34_0_ETC__q134, + CASE_guard90021_0b0_sfdin98243_BITS_56_TO_34_0_ETC__q135, + CASE_guard98525_0b0_sfdin06747_BITS_56_TO_34_0_ETC__q64, + CASE_guard98525_0b0_sfdin06747_BITS_56_TO_34_0_ETC__q65, + CASE_guard98857_0b0_theResult___snd06880_BITS__ETC__q137, + CASE_guard98857_0b0_theResult___snd06880_BITS__ETC__q138, + _theResult___fst_sfd__h580859, + _theResult___fst_sfd__h589582, + _theResult___fst_sfd__h598164, + _theResult___fst_sfd__h607348, + _theResult___fst_sfd__h615984, + _theResult___fst_sfd__h626610, + _theResult___fst_sfd__h635331, + _theResult___fst_sfd__h643913, + _theResult___fst_sfd__h653097, + _theResult___fst_sfd__h661733, + _theResult___fst_sfd__h672357, + _theResult___fst_sfd__h681078, + _theResult___fst_sfd__h689660, + _theResult___fst_sfd__h698844, + _theResult___fst_sfd__h707480; + reg [17 : 0] CASE_csrf_mepcc_reg_data_rl_BITS_52_TO_35_2621_ETC__q279, + CASE_csrf_sepcc_reg_data_rl_BITS_52_TO_35_2621_ETC__q278, + thin_otype__h864891, + thin_otype__h906788; reg [15 : 0] SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_235_ETC___d1889, SEL_ARR_mmio_dataRespQ_data_0_393_BITS_15_TO_0_ETC___d2058; - reg [13 : 0] thin_addrBits__h864889, - thin_addrBits__h906787, - thin_bounds_baseBits__h866837, - thin_bounds_baseBits__h908193, - thin_bounds_topBits__h866836, - thin_bounds_topBits__h908192; - reg [12 : 0] CASE_coreFix_memExe_lsqfirstLd_BITS_15_TO_14__ETC__q340, - CASE_coreFix_memExe_lsqfirstSt_BITS_12_TO_11__ETC__q336, - CASE_robdeqPort_0_deq_data_BITS_273_TO_272_0__ETC__q327; - reg [11 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q351, - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_728_ETC__q290, - CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q345, - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q362, - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_728_ETC__q285, - CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q356, + reg [13 : 0] thin_addrBits__h864887, + thin_addrBits__h906784, + thin_bounds_baseBits__h866835, + thin_bounds_baseBits__h908190, + thin_bounds_topBits__h866834, + thin_bounds_topBits__h908189; + reg [12 : 0] CASE_coreFix_memExe_lsqfirstLd_BITS_15_TO_14__ETC__q342, + CASE_coreFix_memExe_lsqfirstSt_BITS_12_TO_11__ETC__q338, + CASE_robdeqPort_0_deq_data_BITS_273_TO_272_0__ETC__q329; + reg [11 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q353, + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_728_ETC__q292, + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q347, + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q364, + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_728_ETC__q287, + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q358, CASE_fetchStagepipelines_0_first_BITS_179_TO__ETC__q254, CASE_fetchStagepipelines_1_first_BITS_179_TO__ETC__q259; - reg [10 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_19_ETC__q350, - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_787_ETC__q289, - CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q344, - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_19_ETC__q361, - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_787_ETC__q284, - CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q355, + reg [10 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_19_ETC__q352, + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_787_ETC__q291, + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q346, + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_19_ETC__q363, + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_787_ETC__q286, + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q357, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q28, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q30, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q32, CASE_fetchStagepipelines_0_first_BITS_238_TO__ETC__q256, CASE_fetchStagepipelines_1_first_BITS_238_TO__ETC__q264, - CASE_guard09416_0b0_theResult___fst_exp17377_0_ETC__q172, - CASE_guard09416_0b0_theResult___fst_exp17377_0_ETC__q173, - CASE_guard18728_0b0_theResult___fst_exp26954_0_ETC__q201, - CASE_guard18728_0b0_theResult___fst_exp26954_0_ETC__q202, - CASE_guard27797_0b0_theResult___fst_exp35787_0_ETC__q203, - CASE_guard27797_0b0_theResult___fst_exp35787_0_ETC__q204, - CASE_guard31259_0b0_theResult___fst_exp39220_0_ETC__q155, - CASE_guard31259_0b0_theResult___fst_exp39220_0_ETC__q156, - CASE_guard40571_0b0_theResult___fst_exp48797_0_ETC__q223, - CASE_guard40571_0b0_theResult___fst_exp48797_0_ETC__q224, - CASE_guard49640_0b0_theResult___fst_exp57630_0_ETC__q225, - CASE_guard49640_0b0_theResult___fst_exp57630_0_ETC__q226, - CASE_guard70112_0b0_theResult___fst_exp78073_0_ETC__q195, - CASE_guard70112_0b0_theResult___fst_exp78073_0_ETC__q196, - CASE_guard79424_0b0_theResult___fst_exp87650_0_ETC__q197, - CASE_guard79424_0b0_theResult___fst_exp87650_0_ETC__q198, - CASE_guard88493_0b0_theResult___fst_exp96483_0_ETC__q199, - CASE_guard88493_0b0_theResult___fst_exp96483_0_ETC__q200, + CASE_guard09412_0b0_theResult___fst_exp17373_0_ETC__q172, + CASE_guard09412_0b0_theResult___fst_exp17373_0_ETC__q173, + CASE_guard18724_0b0_theResult___fst_exp26950_0_ETC__q201, + CASE_guard18724_0b0_theResult___fst_exp26950_0_ETC__q202, + CASE_guard27793_0b0_theResult___fst_exp35783_0_ETC__q203, + CASE_guard27793_0b0_theResult___fst_exp35783_0_ETC__q204, + CASE_guard31255_0b0_theResult___fst_exp39216_0_ETC__q155, + CASE_guard31255_0b0_theResult___fst_exp39216_0_ETC__q156, + CASE_guard40567_0b0_theResult___fst_exp48793_0_ETC__q223, + CASE_guard40567_0b0_theResult___fst_exp48793_0_ETC__q224, + CASE_guard49636_0b0_theResult___fst_exp57626_0_ETC__q225, + CASE_guard49636_0b0_theResult___fst_exp57626_0_ETC__q226, + CASE_guard70108_0b0_theResult___fst_exp78069_0_ETC__q195, + CASE_guard70108_0b0_theResult___fst_exp78069_0_ETC__q196, + CASE_guard79420_0b0_theResult___fst_exp87646_0_ETC__q199, + CASE_guard79420_0b0_theResult___fst_exp87646_0_ETC__q200, + CASE_guard88489_0b0_theResult___fst_exp96479_0_ETC__q197, + CASE_guard88489_0b0_theResult___fst_exp96479_0_ETC__q198, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d13276, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d13319, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d13350, @@ -3966,79 +3967,79 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14761, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14799, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14830; - reg [7 : 0] CASE_guard07364_0b0_theResult___fst_exp15441_0_ETC__q58, - CASE_guard07364_0b0_theResult___fst_exp15441_0_ETC__q59, - CASE_guard26640_0b0_theResult___fst_exp34739_0_ETC__q82, - CASE_guard26640_0b0_theResult___fst_exp34739_0_ETC__q83, - CASE_guard35347_0b0_theResult___fst_exp43395_0_ETC__q80, - CASE_guard35347_0b0_theResult___fst_exp43395_0_ETC__q81, - CASE_guard44277_0b0_theResult___fst_exp52505_0_ETC__q88, - CASE_guard44277_0b0_theResult___fst_exp52505_0_ETC__q89, - CASE_guard53113_0b0_theResult___fst_exp61190_0_ETC__q93, - CASE_guard53113_0b0_theResult___fst_exp61190_0_ETC__q94, - CASE_guard72387_0b0_theResult___fst_exp80486_0_ETC__q117, - CASE_guard72387_0b0_theResult___fst_exp80486_0_ETC__q118, - CASE_guard80889_0b0_theResult___fst_exp88990_0_ETC__q49, - CASE_guard80889_0b0_theResult___fst_exp88990_0_ETC__q50, - CASE_guard81094_0b0_theResult___fst_exp89142_0_ETC__q115, - CASE_guard81094_0b0_theResult___fst_exp89142_0_ETC__q116, - CASE_guard89598_0b0_theResult___fst_exp97646_0_ETC__q47, - CASE_guard89598_0b0_theResult___fst_exp97646_0_ETC__q48, - CASE_guard90024_0b0_theResult___fst_exp98252_0_ETC__q123, - CASE_guard90024_0b0_theResult___fst_exp98252_0_ETC__q124, - CASE_guard98528_0b0_theResult___fst_exp06756_0_ETC__q53, - CASE_guard98528_0b0_theResult___fst_exp06756_0_ETC__q54, - CASE_guard98860_0b0_theResult___fst_exp06937_0_ETC__q128, - CASE_guard98860_0b0_theResult___fst_exp06937_0_ETC__q129, + reg [7 : 0] CASE_guard07361_0b0_theResult___fst_exp15438_0_ETC__q58, + CASE_guard07361_0b0_theResult___fst_exp15438_0_ETC__q59, + CASE_guard26637_0b0_theResult___fst_exp34736_0_ETC__q82, + CASE_guard26637_0b0_theResult___fst_exp34736_0_ETC__q83, + CASE_guard35344_0b0_theResult___fst_exp43392_0_ETC__q80, + CASE_guard35344_0b0_theResult___fst_exp43392_0_ETC__q81, + CASE_guard44274_0b0_theResult___fst_exp52502_0_ETC__q88, + CASE_guard44274_0b0_theResult___fst_exp52502_0_ETC__q89, + CASE_guard53110_0b0_theResult___fst_exp61187_0_ETC__q93, + CASE_guard53110_0b0_theResult___fst_exp61187_0_ETC__q94, + CASE_guard72384_0b0_theResult___fst_exp80483_0_ETC__q117, + CASE_guard72384_0b0_theResult___fst_exp80483_0_ETC__q118, + CASE_guard80886_0b0_theResult___fst_exp88987_0_ETC__q47, + CASE_guard80886_0b0_theResult___fst_exp88987_0_ETC__q48, + CASE_guard81091_0b0_theResult___fst_exp89139_0_ETC__q115, + CASE_guard81091_0b0_theResult___fst_exp89139_0_ETC__q116, + CASE_guard89595_0b0_theResult___fst_exp97643_0_ETC__q45, + CASE_guard89595_0b0_theResult___fst_exp97643_0_ETC__q46, + CASE_guard90021_0b0_theResult___fst_exp98249_0_ETC__q123, + CASE_guard90021_0b0_theResult___fst_exp98249_0_ETC__q124, + CASE_guard98525_0b0_theResult___fst_exp06753_0_ETC__q53, + CASE_guard98525_0b0_theResult___fst_exp06753_0_ETC__q54, + CASE_guard98857_0b0_theResult___fst_exp06934_0_ETC__q128, + CASE_guard98857_0b0_theResult___fst_exp06934_0_ETC__q129, SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_235_ETC___d1911, SEL_ARR_mmio_dataRespQ_data_0_393_BITS_7_TO_0__ETC___d2079, - _theResult___fst_exp__h580861, - _theResult___fst_exp__h589584, - _theResult___fst_exp__h598166, - _theResult___fst_exp__h607350, - _theResult___fst_exp__h615986, - _theResult___fst_exp__h626612, - _theResult___fst_exp__h635333, - _theResult___fst_exp__h643915, - _theResult___fst_exp__h653099, - _theResult___fst_exp__h661735, - _theResult___fst_exp__h672359, - _theResult___fst_exp__h681080, - _theResult___fst_exp__h689662, - _theResult___fst_exp__h698846, - _theResult___fst_exp__h707482; - reg [5 : 0] CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q341, + _theResult___fst_exp__h580858, + _theResult___fst_exp__h589581, + _theResult___fst_exp__h598163, + _theResult___fst_exp__h607347, + _theResult___fst_exp__h615983, + _theResult___fst_exp__h626609, + _theResult___fst_exp__h635330, + _theResult___fst_exp__h643912, + _theResult___fst_exp__h653096, + _theResult___fst_exp__h661732, + _theResult___fst_exp__h672356, + _theResult___fst_exp__h681077, + _theResult___fst_exp__h689659, + _theResult___fst_exp__h698843, + _theResult___fst_exp__h707479; + reg [5 : 0] CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q343, CASE_mmio_cRqQ_data_0_BITS_150_TO_149_0_mmio_c_ETC__q1, - CASE_mmio_dataReqQ_data_0_BITS_150_TO_149_0_mm_ETC__q332, - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388; - reg [4 : 0] CASE_basicExec_0102_BITS_270_TO_266_0_basicExe_ETC__q347, - CASE_basicExec_7927_BITS_270_TO_266_0_basicExe_ETC__q358, - CASE_capChecks_179_BITS_4_TO_0_0_capChecks_179_ETC__q292, + CASE_mmio_dataReqQ_data_0_BITS_150_TO_149_0_mm_ETC__q334, + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390; + reg [4 : 0] CASE_basicExec_0102_BITS_270_TO_266_0_basicExe_ETC__q349, + CASE_basicExec_7927_BITS_270_TO_266_0_basicExe_ETC__q360, + CASE_capChecks_179_BITS_4_TO_0_0_capChecks_179_ETC__q294, CASE_checkForException_0942_BITS_4_TO_0_0_chec_ETC__q257, CASE_commitStage_commitTrap_BITS_36_TO_32_0_co_ETC__q26, - CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_12_ETC__q352, - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_715_ETC__q291, - CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q346, - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_12_ETC__q363, - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_715_ETC__q286, - CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q357, - CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q338, - CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q339, - CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q334, - CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q335, + CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_12_ETC__q354, + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_715_ETC__q293, + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q348, + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_12_ETC__q365, + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_715_ETC__q288, + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q359, + CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q340, + CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q341, + CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q336, + CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q337, CASE_csrf_mccsr_reg_BITS_4_TO_0_0_csrf_mccsr_r_ETC__q25, - CASE_f_csr_reqsD_OUT_BITS_9_TO_5_0_f_csr_reqs_ETC__q330, + CASE_f_csr_reqsD_OUT_BITS_9_TO_5_0_f_csr_reqs_ETC__q332, CASE_fetchStagepipelines_0_first_BITS_166_TO__ETC__q253, CASE_fetchStagepipelines_1_first_BITS_166_TO__ETC__q263, - CASE_robdeqPort_0_deq_data_BITS_265_TO_261_0__ETC__q325, - CASE_robdeqPort_0_deq_data_BITS_265_TO_261_0__ETC__q326, - CASE_robdeqPort_0_deq_data_BITS_95_TO_326_BITS_ETC__q331, + CASE_robdeqPort_0_deq_data_BITS_265_TO_261_0__ETC__q327, + CASE_robdeqPort_0_deq_data_BITS_265_TO_261_0__ETC__q328, + CASE_robdeqPort_0_deq_data_BITS_95_TO_326_BITS_ETC__q333, IF_fetchStage_pipelines_0_first__0544_BITS_265_ETC___d22363, IF_fetchStage_pipelines_1_first__0553_BITS_265_ETC___d22544, - cause_code__h1006053, - i__h1006069, - t__h215266, - t__h217619; + cause_code__h1006050, + i__h1006066, + t__h215264, + t__h217617; reg [3 : 0] CASE_IF_coreFix_aluExe_0_dispToRegQ_first__861_ETC__q248, CASE_IF_coreFix_aluExe_0_regToExeQ_first__9699_ETC__q250, CASE_IF_coreFix_aluExe_0_rsAlu_dispatchData__8_ETC__q246, @@ -4048,9 +4049,9 @@ module mkCore(CLK, CASE_IF_fetchStage_pipelines_0_first__0544_BIT_ETC__q252, CASE_IF_fetchStage_pipelines_1_first__0553_BIT_ETC__q261, CASE_checkForException_0942_BITS_4_TO_0_0_0_1__ETC__q258, - CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q337, - CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q333, - CASE_robdeqPort_0_deq_data_BITS_264_TO_261_0__ETC__q324, + CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q339, + CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q335, + CASE_robdeqPort_0_deq_data_BITS_264_TO_261_0__ETC__q326, IF_checkForException_0942_BITS_3_TO_0_1195_EQ__ETC___d21215, IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d18785, IF_coreFix_aluExe_0_regToExeQ_first__9699_BITS_ETC___d19759, @@ -4063,10 +4064,10 @@ module mkCore(CLK, IF_fetchStage_pipelines_0_first__0544_BIT_69_0_ETC___d21100, IF_fetchStage_pipelines_1_first__0553_BITS_236_ETC___d21670, IF_fetchStage_pipelines_1_first__0553_BITS_265_ETC___d22545, - IF_rob_deqPort_0_deq_data__2632_BIT_294_3835_T_ETC___d23857, - i__h1006243, - thin_perms_soft__h865128, - thin_perms_soft__h906966; + IF_rob_deqPort_0_deq_data__2632_BIT_294_3837_T_ETC___d23859, + i__h1006266, + thin_perms_soft__h865126, + thin_perms_soft__h906963; reg [2 : 0] CASE_IF_coreFix_aluExe_0_dispToRegQ_first__861_ETC__q247, CASE_IF_coreFix_aluExe_0_regToExeQ_first__9699_ETC__q249, CASE_IF_coreFix_aluExe_0_rsAlu_dispatchData__8_ETC__q245, @@ -4075,16 +4076,16 @@ module mkCore(CLK, CASE_IF_coreFix_aluExe_1_rsAlu_dispatchData__5_ETC__q241, CASE_IF_fetchStage_pipelines_0_first__0544_BIT_ETC__q251, CASE_IF_fetchStage_pipelines_1_first__0553_BIT_ETC__q260, - CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_19_ETC__q348, - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_791_ETC__q287, - CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q342, - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_19_ETC__q359, - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_791_ETC__q282, - CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q353, - CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q368, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q281, - CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q364, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q319, + CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_19_ETC__q350, + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_791_ETC__q289, + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q344, + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_19_ETC__q361, + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_791_ETC__q284, + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q355, + CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q370, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q283, + CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q366, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q321, CASE_fetchStagepipelines_0_first_BITS_242_TO__ETC__q255, CASE_fetchStagepipelines_1_first_BITS_242_TO__ETC__q262, IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d18817, @@ -4096,16 +4097,18 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14974, IF_fetchStage_pipelines_0_first__0544_BITS_232_ETC___d20730, IF_fetchStage_pipelines_1_first__0553_BITS_232_ETC___d21702, - x__h505455, - x__h513123; - reg [1 : 0] CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q314, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q370, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q317, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q321, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q312, - thin_reserved__h864892, - thin_reserved__h906790; - reg CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q158, + x__h505453, + x__h513121; + reg [1 : 0] CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q316, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q372, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q319, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q323, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q314, + thin_reserved__h864890, + thin_reserved__h906787; + reg CASE_commitStage_commitTrap_BITS_44_TO_43_0_NO_ETC__q277, + CASE_commitStage_commitTrap_BITS_44_TO_43_0_cs_ETC__q276, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q158, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q160, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q162, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q175, @@ -4120,22 +4123,22 @@ module mkCore(CLK, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q212, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q214, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q216, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q316, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q305, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q315, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q322, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q323, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q318, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q307, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q317, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q324, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q325, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q38, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q39, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q40, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q318, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q278, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q279, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q320, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q280, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q308, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q313, - CASE_coreFix_memExe_forwardQ_deqP_0_coreFix_me_ETC__q329, - CASE_coreFix_memExe_memRespLdQ_deqP_0_coreFix__ETC__q328, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q281, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q282, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q310, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q315, + CASE_coreFix_memExe_forwardQ_deqP_0_coreFix_me_ETC__q331, + CASE_coreFix_memExe_memRespLdQ_deqP_0_coreFix__ETC__q330, CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q274, CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q275, CASE_fetchStage_pipelines_0_canDeq__0542_AND_N_ETC__q270, @@ -4146,46 +4149,46 @@ module mkCore(CLK, CASE_fetchStagepipelines_1_first_BITS_265_TO__ETC__q267, CASE_fetchStagepipelines_1_first_BITS_265_TO__ETC__q271, CASE_fetchStagepipelines_1_first_BITS_268_TO__ETC__q273, - CASE_guard07364_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q75, - CASE_guard07364_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q74, - CASE_guard09416_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q184, - CASE_guard09416_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q176, - CASE_guard18728_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q180, - CASE_guard18728_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q174, - CASE_guard26640_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q104, - CASE_guard26640_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q103, - CASE_guard27797_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q182, - CASE_guard27797_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q178, - CASE_guard31259_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q157, - CASE_guard35347_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q106, - CASE_guard35347_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q105, - CASE_guard40571_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q159, - CASE_guard44277_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q108, - CASE_guard44277_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q107, - CASE_guard49640_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q161, - CASE_guard53113_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q110, - CASE_guard53113_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q109, - CASE_guard70112_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q213, - CASE_guard70112_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q205, - CASE_guard72387_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q139, - CASE_guard72387_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q138, - CASE_guard79424_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q211, - CASE_guard79424_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q207, - CASE_guard80889_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q69, - CASE_guard80889_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q68, - CASE_guard81094_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q141, - CASE_guard81094_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q140, - CASE_guard88493_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q215, - CASE_guard88493_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q209, - CASE_guard89598_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q71, - CASE_guard89598_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q70, - CASE_guard90024_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q143, - CASE_guard90024_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q142, - CASE_guard98528_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q73, - CASE_guard98528_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q72, - CASE_guard98860_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q145, - CASE_guard98860_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q144, - CASE_k54121_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q268, + CASE_guard07361_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q75, + CASE_guard07361_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q74, + CASE_guard09412_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q184, + CASE_guard09412_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q174, + CASE_guard18724_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q180, + CASE_guard18724_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q176, + CASE_guard26637_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q105, + CASE_guard26637_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q103, + CASE_guard27793_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q182, + CASE_guard27793_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q178, + CASE_guard31255_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q157, + CASE_guard35344_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q106, + CASE_guard35344_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q104, + CASE_guard40567_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q159, + CASE_guard44274_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q108, + CASE_guard44274_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q107, + CASE_guard49636_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q161, + CASE_guard53110_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q110, + CASE_guard53110_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q109, + CASE_guard70108_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q215, + CASE_guard70108_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q205, + CASE_guard72384_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q139, + CASE_guard72384_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q136, + CASE_guard79420_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q211, + CASE_guard79420_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q207, + CASE_guard80886_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q69, + CASE_guard80886_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q68, + CASE_guard81091_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q141, + CASE_guard81091_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q140, + CASE_guard88489_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q213, + CASE_guard88489_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q209, + CASE_guard89595_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q71, + CASE_guard89595_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q70, + CASE_guard90021_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q143, + CASE_guard90021_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q142, + CASE_guard98525_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q73, + CASE_guard98525_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q72, + CASE_guard98857_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q145, + CASE_guard98857_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q144, + CASE_k54118_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q268, IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19446, IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19482, IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19491, @@ -4289,12 +4292,12 @@ module mkCore(CLK, wire [515 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5194, IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d5195, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d7225, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d24838; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d24840; wire [511 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d4963; wire [457 : 0] coreFix_memExe_lsq_getOrigBE_coreFix_memExe_re_ETC___d4269; wire [383 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5192, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d7215, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d24828; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d24830; wire [294 : 0] fetchStage_pipelines_0_first__0544_BIT_167_088_ETC___d21450; wire [278 : 0] IF_coreFix_memExe_lsq_getOrigBE_coreFix_memExe_ETC___d4268; wire [265 : 0] prepareBoundsCheck___d4263; @@ -4318,38 +4321,38 @@ module mkCore(CLK, IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d5583; wire [128 : 0] amoExec___d4942, amoExec___d775, - fallthrough_pc__h948608, - fallthrough_pc__h973095, - new_pc__h880399, - new_pc__h920773, - next_pc__h1023233, - pc__h973086, - v__h1023555, - v__h1024264, - x__h873780, - x__h887434, - x__h914821, - x__h923377, - y__h874034, - y__h915075; + fallthrough_pc__h948605, + fallthrough_pc__h973092, + new_pc__h880397, + new_pc__h920770, + next_pc__h1023267, + pc__h973083, + v__h1023589, + v__h1024298, + x__h873778, + x__h887432, + x__h914818, + x__h923374, + y__h874032, + y__h915072; wire [127 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5188, SEXT_SEL_ARR_SEL_ARR_coreFix_memExe_dMem_cache_ETC___d4901, SEXT_SEL_ARR_SEL_ARR_coreFix_memExe_dMem_cache_ETC___d4909, - b__h840826, - b__h840902, - b__h841003, - b__h841015, + b__h840822, + b__h840898, + b__h840999, + b__h841011, coreFix_memExe_regToExeQ_first__664_BITS_140_T_ETC___d4089, - x__h185174, - x__h201338, - x__h841827; + x__h185172, + x__h201336, + x__h841823; wire [109 : 0] IF_fetchStage_pipelines_0_first__0544_BITS_238_ETC___d20910, IF_fetchStage_pipelines_1_first__0553_BITS_238_ETC___d21882; wire [85 : 0] IF_coreFix_memExe_dispToRegQ_first__695_BIT_10_ETC___d3599; wire [71 : 0] IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19637, IF_coreFix_aluExe_1_dispToRegQ_first__5790_BIT_ETC___d17444, - IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d23712, - IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d23575; + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d23714, + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d23577; wire [68 : 0] execFpuSimple___d15313; wire [66 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d7124; wire [65 : 0] IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__863_ETC___d19063, @@ -4368,91 +4371,91 @@ module mkCore(CLK, IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16614, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3075, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3437, - addTop__h242866, - addTop__h244023, - addTop__h257644, - address__h1010227, - address__h1010571, - address__h1010884, - address__h1011228, + addTop__h242863, + addTop__h244020, + addTop__h257641, + address__h1010261, + address__h1010605, + address__h1010918, + address__h1011262, coreFix_memExe_dTlb_procResp__276_BITS_452_TO__ETC___d4426, coreFix_memExe_regToExeQ_first__664_BITS_220_T_ETC___d3785, coreFix_memExe_regToExeQ_first__664_BITS_383_T_ETC___d3723, - cr_address__h872617, - cr_address__h873165, - cr_address__h913658, - cr_address__h914206, - data_address__h1030199, - data_address__h1031053, - in__h1008389, - in__h242697, - in__h243854, - in__h257475, - in__h860569, - in__h860874, - in__h861562, - in__h861866, - in__h862392, - pc_address__h1005472, - pointer__h245528, - res_address__h127849, - res_address__h140989, - res_address__h180673, - res_address__h199750, - res_address__h218914, - res_address__h238214, - res_address__h571771, - res_address__h572623, - res_address__h618380, - res_address__h664127, - res_address__h710013, - res_address__h710959, - res_address__h855059, - res_address__h899822, - result__h243493, - result__h244650, - result__h258271, - result_d_address__h1019531, - result_d_address__h1019934, - result_d_address__h1020351, - result_d_address__h1020754, - result_d_address__h1021423, - result_d_address__h1043099, - result_d_address__h1043502, - result_d_address__h1043919, - result_d_address__h1044322, - result_d_address__h1044989, - result_d_address__h245739, - ret__h242870, - ret__h244027, - ret__h257648, - x__h1008407, - x__h1010421, - x__h1010725, - x__h1011078, - x__h1011382, - x__h238637, - x__h242715, - x__h242863, - x__h243872, - x__h244020, - x__h251010, - x__h257493, - x__h257641, - x__h860587, - x__h860892, - x__h861580, - x__h861884, - x__h862410, - y__h1008406, - y__h242714, - y__h243871, - y__h257492, - y__h860586, - y__h860891, - y__h861579, - y__h861883, - y__h862409; + cr_address__h872615, + cr_address__h873163, + cr_address__h913655, + cr_address__h914203, + data_address__h1030232, + data_address__h1031086, + in__h1008423, + in__h242694, + in__h243851, + in__h257472, + in__h860567, + in__h860872, + in__h861560, + in__h861864, + in__h862390, + pc_address__h1005469, + pointer__h245525, + res_address__h127848, + res_address__h140988, + res_address__h180671, + res_address__h199748, + res_address__h218912, + res_address__h238211, + res_address__h571767, + res_address__h572620, + res_address__h618377, + res_address__h664124, + res_address__h710010, + res_address__h710956, + res_address__h855056, + res_address__h899820, + result__h243490, + result__h244647, + result__h258268, + result_d_address__h1019565, + result_d_address__h1019968, + result_d_address__h1020385, + result_d_address__h1020788, + result_d_address__h1021457, + result_d_address__h1043132, + result_d_address__h1043535, + result_d_address__h1043952, + result_d_address__h1044355, + result_d_address__h1045022, + result_d_address__h245736, + ret__h242867, + ret__h244024, + ret__h257645, + x__h1008441, + x__h1010455, + x__h1010759, + x__h1011112, + x__h1011416, + x__h238634, + x__h242712, + x__h242860, + x__h243869, + x__h244017, + x__h251007, + x__h257490, + x__h257638, + x__h860585, + x__h860890, + x__h861578, + x__h861882, + x__h862408, + y__h1008440, + y__h242711, + y__h243868, + y__h257489, + y__h860584, + y__h860889, + y__h861577, + y__h861881, + y__h862407; wire [63 : 0] IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13430, IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12597, IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12598, @@ -4472,224 +4475,224 @@ module mkCore(CLK, IF_coreFix_memExe_lsq_firstLd__502_BIT_113_517_ETC___d2084, IF_coreFix_memExe_lsq_firstLd__502_BIT_117_525_ETC___d1917, IF_coreFix_memExe_lsq_firstLd__502_BIT_117_525_ETC___d2085, - IF_csrf_mtcc_reg_read__6389_BIT_86_3183_AND_NO_ETC___d23281, - IF_csrf_stcc_reg_read__6237_BIT_86_3112_AND_NO_ETC___d23280, - IF_rob_deqPort_0_canDeq__3983_THEN_IF_NOT_rob__ETC___d24105, - SEXT__0_CONCAT_IF_INV_commitStage_commitTrap_2_ETC___d23053, + IF_csrf_mtcc_reg_read__6389_BIT_86_3185_AND_NO_ETC___d23283, + IF_csrf_stcc_reg_read__6237_BIT_86_3114_AND_NO_ETC___d23282, + IF_rob_deqPort_0_canDeq__3985_THEN_IF_NOT_rob__ETC___d24107, + SEXT__0_CONCAT_IF_INV_commitStage_commitTrap_2_ETC___d23054, SEXT__0_CONCAT_IF_csrf_mepcc_reg_data_lat_0_wh_ETC___d16452, SEXT__0_CONCAT_IF_csrf_sepcc_reg_data_lat_0_wh_ETC___d16300, SEXT__0_CONCAT_csrf_mtcc_reg_read__6389_BITS_8_ETC___d16413, SEXT__0_CONCAT_csrf_rg_dpc_read__6534_BITS_85__ETC___d16558, SEXT__0_CONCAT_csrf_stcc_reg_read__6237_BITS_8_ETC___d16261, - _18446744073709551615_SL_csrf_mtcc_reg_read__63_ETC___d23200, - _18446744073709551615_SL_csrf_stcc_reg_read__62_ETC___d23131, - _theResult___fst__h841226, - _theResult___snd__h841227, - a___1__h840840, - a___1__h841231, - a__h840678, - addBase__h1019550, - addBase__h1019953, - addBase__h1020370, - addBase__h1020773, - addBase__h1021443, - addBase__h242757, - addBase__h243914, - addBase__h257535, - addr__h1000333, - addr__h149996, - addr__h153572, - addr__h238208, - address__h1010161, - address__h1010211, - address__h1023286, - address__h874073, - address__h915078, - address__h965683, - address__h990659, - b___1__h840841, - b___1__h841292, - b__h840679, - base__h1010122, - base__h1010176, - bot__h1019553, - bot__h1019956, - bot__h1020373, - bot__h1020776, - bot__h1021446, + _18446744073709551615_SL_csrf_mtcc_reg_read__63_ETC___d23202, + _18446744073709551615_SL_csrf_stcc_reg_read__62_ETC___d23133, + _theResult___fst__h841222, + _theResult___snd__h841223, + a___1__h840836, + a___1__h841227, + a__h840674, + addBase__h1019584, + addBase__h1019987, + addBase__h1020404, + addBase__h1020807, + addBase__h1021477, + addBase__h242754, + addBase__h243911, + addBase__h257532, + addr__h1000330, + addr__h149995, + addr__h153571, + addr__h238205, + address__h1010195, + address__h1010245, + address__h1023320, + address__h874071, + address__h915075, + address__h965680, + address__h990656, + b___1__h840837, + b___1__h841288, + b__h840675, + base__h1010156, + base__h1010210, + bot__h1019587, + bot__h1019990, + bot__h1020407, + bot__h1020810, + bot__h1021480, coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d15402, coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d15403, - csrf_mtcc_reg_read__6389_BITS_149_TO_86_3187_A_ETC___d23190, - csrf_stcc_reg_read__6237_BITS_149_TO_86_3116_A_ETC___d23119, - data___1__h710035, - data___1__h710981, - data__h572105, - data__h617865, - data__h663612, - data__h709497, - data__h709528, - data__h710443, - data__h710474, - fcsr_csr__read__h855634, - fflags_csr__read__h855609, - frm_csr__read__h855620, - mask__h1010233, - mask__h1010890, - mcause_csr__read__h857301, - mcounteren_csr__read__h857035, - medeleg_csr__read__h856638, - mideleg_csr__read__h856736, - mie_csr__read__h856863, - mip_csr__read__h857540, - mstatus_csr__read__h856477, - n__read__h1025204, + csrf_mtcc_reg_read__6389_BITS_149_TO_86_3189_A_ETC___d23192, + csrf_stcc_reg_read__6237_BITS_149_TO_86_3118_A_ETC___d23121, + data___1__h710032, + data___1__h710978, + data__h572102, + data__h617862, + data__h663609, + data__h709494, + data__h709525, + data__h710440, + data__h710471, + fcsr_csr__read__h855632, + fflags_csr__read__h855607, + frm_csr__read__h855618, + mask__h1010267, + mask__h1010924, + mcause_csr__read__h857299, + mcounteren_csr__read__h857033, + medeleg_csr__read__h856636, + mideleg_csr__read__h856734, + mie_csr__read__h856861, + mip_csr__read__h857538, + mstatus_csr__read__h856475, + n__read__h1025238, n__read__h7908, - newAddrDiff__h1010234, - newAddrDiff__h1010578, - newAddrDiff__h1010891, - newAddrDiff__h1011235, - offset__h245518, - q___1__h711056, - rVal1__h719448, - rVal2__h719449, - r___1__h711083, - res_data__h572663, - res_data__h572668, - res_data__h618417, - res_data__h618422, - res_data__h664164, - res_data__h664169, - resp_addr__h513542, - rg_tdata1__read__h858641, + newAddrDiff__h1010268, + newAddrDiff__h1010612, + newAddrDiff__h1010925, + newAddrDiff__h1011269, + offset__h245515, + q___1__h711053, + rVal1__h719444, + rVal2__h719445, + r___1__h711080, + res_data__h572660, + res_data__h572665, + res_data__h618414, + res_data__h618419, + res_data__h664161, + res_data__h664166, + resp_addr__h513540, + rg_tdata1__read__h858639, robdeqPort_0_deq_data_BITS_95_TO_32__q16, - satp_csr__read__h856331, - scause_csr__read__h856128, - scounteren_csr__read__h855988, - sie_csr__read__h855900, - sip_csr__read__h856268, - sstatus_csr__read__h855830, - thin_address__h1010115, - tmpAddr__h245727, - trap_val__h1007773, - upd__h1025280, + satp_csr__read__h856329, + scause_csr__read__h856126, + scounteren_csr__read__h855986, + sie_csr__read__h855898, + sip_csr__read__h856266, + sstatus_csr__read__h855828, + thin_address__h1010149, + tmpAddr__h245724, + trap_val__h1007807, + upd__h1025314, upd__h3066, upd__h3676, upd__h7977, - value__h242587, - value__h242751, - value__h243744, - value__h243908, - value__h257365, - value__h257529, - x__h1005644, - x__h1008320, - x__h1008322, - x__h1019461, - x__h1019864, - x__h1020281, - x__h1020684, - x__h1021353, - x__h1043029, - x__h1043432, - x__h1043849, - x__h1044252, - x__h1044919, - x__h128330, - x__h141474, - x__h185256, - x__h204319, - x__h219290, - x__h242605, - x__h242607, - x__h243762, - x__h243764, - x__h245667, - x__h257383, - x__h257385, - x__h719354, - x__h719355, - x__h719356, - x__h841215, + value__h242584, + value__h242748, + value__h243741, + value__h243905, + value__h257362, + value__h257526, + x__h1005641, + x__h1008354, + x__h1008356, + x__h1019495, + x__h1019898, + x__h1020315, + x__h1020718, + x__h1021387, + x__h1043062, + x__h1043465, + x__h1043882, + x__h1044285, + x__h1044952, + x__h128329, + x__h141473, + x__h185254, + x__h204317, + x__h219288, + x__h242602, + x__h242604, + x__h243759, + x__h243761, + x__h245664, + x__h257380, + x__h257382, + x__h719350, + x__h719351, + x__h719352, + x__h841211, + x__h860646, x__h860648, - x__h860650, + x__h861639, x__h861641, - x__h861643, - x__h872794, - x__h873342, - x__h903665, - x__h903667, - x__h903949, - x__h903951, - x__h904294, - x__h904296, - x__h913835, - x__h914383, + x__h872792, + x__h873340, + x__h903662, + x__h903664, + x__h903946, + x__h903948, + x__h904291, + x__h904293, + x__h913832, + x__h914380, x_addr__h19883, x_addr__h44252, - x_addr__h539799, - x_quotient__h710245, - x_reg_ifc__read__h855739, - x_remainder__h710246, - y__h1010350, - y__h1011007, - y__h1027821, - y_avValue__h715403, - y_avValue__h716111, - y_avValue__h716813, - y_avValue_snd_snd_snd_snd_snd__h1027231, - y_avValue_snd_snd_snd_snd_snd__h1027874, - y_avValue_snd_snd_snd_snd_snd__h1027903; + x_addr__h539796, + x_quotient__h710242, + x_reg_ifc__read__h855737, + x_remainder__h710243, + y__h1010384, + y__h1011041, + y__h1027855, + y_avValue__h715399, + y_avValue__h716107, + y_avValue__h716809, + y_avValue_snd_snd_snd_snd_snd__h1027265, + y_avValue_snd_snd_snd_snd_snd__h1027908, + y_avValue_snd_snd_snd_snd_snd__h1027937; wire [62 : 0] IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14139, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14909, - r1__read__h859522, + r1__read__h859520, + r1__read__h859924, + r1__read__h860617, + r1__read__h860929, + r1__read__h861162, + r1__read__h861334, + r1__read__h861610, + r1__read__h861921; + wire [61 : 0] r1__read__h859522, r1__read__h859926, r1__read__h860619, r1__read__h860931, r1__read__h861164, + r1__read__h861310, r1__read__h861336, r1__read__h861612, r1__read__h861923; - wire [61 : 0] r1__read__h859524, - r1__read__h859928, - r1__read__h860621, - r1__read__h860933, - r1__read__h861166, + wire [60 : 0] r1__read__h861166, r1__read__h861312, r1__read__h861338, - r1__read__h861614, r1__read__h861925; - wire [60 : 0] r1__read__h861168, - r1__read__h861314, + wire [59 : 0] r1__read__h859524, + r1__read__h859928, + r1__read__h860933, + r1__read__h861168, r1__read__h861340, r1__read__h861927; - wire [59 : 0] r1__read__h859526, - r1__read__h859930, - r1__read__h860935, - r1__read__h861170, - r1__read__h861342, - r1__read__h861929; wire [58 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5519, IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5561, IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d7043, + r1__read__h859526, + r1__read__h859930, + r1__read__h860922, + r1__read__h860935, + r1__read__h861170, + r1__read__h861342, + r1__read__h861914, + r1__read__h861929; + wire [57 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d7302, r1__read__h859528, r1__read__h859932, - r1__read__h860924, r1__read__h860937, r1__read__h861172, + r1__read__h861314, r1__read__h861344, - r1__read__h861916, - r1__read__h861931; - wire [57 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d7302, - r1__read__h859530, - r1__read__h859934, - r1__read__h860939, - r1__read__h861174, - r1__read__h861316, - r1__read__h861346, - r1__read__h861933, - y__h426316; + r1__read__h861931, + y__h426314; wire [56 : 0] IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q111, - IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q43, + IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q41, IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q76, IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q150, IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q167, @@ -4705,7 +4708,7 @@ module mkCore(CLK, IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q193, IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q113, IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q126, - IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q45, + IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q43, IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q56, IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q78, IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q91, @@ -4715,195 +4718,195 @@ module mkCore(CLK, _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d10169, _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d11566, _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d8772, - _theResult____h580879, - _theResult____h598518, - _theResult____h626630, - _theResult____h644267, - _theResult____h672377, - _theResult____h690014, - _theResult____h740561, - _theResult____h779414, - _theResult____h818718, - _theResult___snd__h589001, - _theResult___snd__h589012, - _theResult___snd__h589014, - _theResult___snd__h589024, - _theResult___snd__h589030, - _theResult___snd__h589053, - _theResult___snd__h597597, - _theResult___snd__h597599, - _theResult___snd__h597606, - _theResult___snd__h597612, - _theResult___snd__h597635, - _theResult___snd__h606767, - _theResult___snd__h606778, - _theResult___snd__h606780, - _theResult___snd__h606790, - _theResult___snd__h606796, - _theResult___snd__h606819, - _theResult___snd__h615387, - _theResult___snd__h615401, - _theResult___snd__h615407, - _theResult___snd__h615425, - _theResult___snd__h634750, - _theResult___snd__h634761, - _theResult___snd__h634763, - _theResult___snd__h634773, - _theResult___snd__h634779, - _theResult___snd__h634802, - _theResult___snd__h643346, - _theResult___snd__h643348, - _theResult___snd__h643355, - _theResult___snd__h643361, - _theResult___snd__h643384, - _theResult___snd__h652516, - _theResult___snd__h652527, - _theResult___snd__h652529, - _theResult___snd__h652539, - _theResult___snd__h652545, - _theResult___snd__h652568, - _theResult___snd__h661136, - _theResult___snd__h661150, - _theResult___snd__h661156, - _theResult___snd__h661174, - _theResult___snd__h680497, - _theResult___snd__h680508, - _theResult___snd__h680510, - _theResult___snd__h680520, - _theResult___snd__h680526, - _theResult___snd__h680549, - _theResult___snd__h689093, - _theResult___snd__h689095, - _theResult___snd__h689102, - _theResult___snd__h689108, - _theResult___snd__h689131, - _theResult___snd__h698263, - _theResult___snd__h698274, - _theResult___snd__h698276, - _theResult___snd__h698286, - _theResult___snd__h698292, - _theResult___snd__h698315, - _theResult___snd__h706883, - _theResult___snd__h706897, - _theResult___snd__h706903, - _theResult___snd__h706921, - _theResult___snd__h739171, - _theResult___snd__h739173, - _theResult___snd__h739180, - _theResult___snd__h739186, - _theResult___snd__h739209, - _theResult___snd__h748808, - _theResult___snd__h748819, - _theResult___snd__h748821, - _theResult___snd__h748831, - _theResult___snd__h748837, - _theResult___snd__h748860, - _theResult___snd__h757576, - _theResult___snd__h757590, - _theResult___snd__h757596, - _theResult___snd__h757614, - _theResult___snd__h778024, - _theResult___snd__h778026, - _theResult___snd__h778033, - _theResult___snd__h778039, - _theResult___snd__h778062, - _theResult___snd__h787661, - _theResult___snd__h787672, - _theResult___snd__h787674, - _theResult___snd__h787684, - _theResult___snd__h787690, - _theResult___snd__h787713, - _theResult___snd__h796429, - _theResult___snd__h796443, - _theResult___snd__h796449, - _theResult___snd__h796467, - _theResult___snd__h817328, - _theResult___snd__h817330, - _theResult___snd__h817337, - _theResult___snd__h817343, - _theResult___snd__h817366, - _theResult___snd__h826965, - _theResult___snd__h826976, - _theResult___snd__h826978, - _theResult___snd__h826988, - _theResult___snd__h826994, - _theResult___snd__h827017, - _theResult___snd__h835733, - _theResult___snd__h835747, - _theResult___snd__h835753, - _theResult___snd__h835771, - r1__read__h861176, - r1__read__h861318, - r1__read__h861348, - r1__read__h861935, - result__h599131, - result__h644880, - result__h690627, - result__h741174, - result__h780027, - result__h819331, - sfd__h573274, - sfd__h619028, - sfd__h664775, - sfd__h720194, - sfd__h759188, - sfd__h798492, - sfdin__h588984, - sfdin__h606750, - sfdin__h634733, - sfdin__h652499, - sfdin__h680480, - sfdin__h698246, - sfdin__h748791, - sfdin__h787644, - sfdin__h826948, - x__h599228, - x__h644977, - x__h690724, - x__h741269, - x__h780122, - x__h819426; + _theResult____h580876, + _theResult____h598515, + _theResult____h626627, + _theResult____h644264, + _theResult____h672374, + _theResult____h690011, + _theResult____h740557, + _theResult____h779410, + _theResult____h818714, + _theResult___snd__h588998, + _theResult___snd__h589009, + _theResult___snd__h589011, + _theResult___snd__h589021, + _theResult___snd__h589027, + _theResult___snd__h589050, + _theResult___snd__h597594, + _theResult___snd__h597596, + _theResult___snd__h597603, + _theResult___snd__h597609, + _theResult___snd__h597632, + _theResult___snd__h606764, + _theResult___snd__h606775, + _theResult___snd__h606777, + _theResult___snd__h606787, + _theResult___snd__h606793, + _theResult___snd__h606816, + _theResult___snd__h615384, + _theResult___snd__h615398, + _theResult___snd__h615404, + _theResult___snd__h615422, + _theResult___snd__h634747, + _theResult___snd__h634758, + _theResult___snd__h634760, + _theResult___snd__h634770, + _theResult___snd__h634776, + _theResult___snd__h634799, + _theResult___snd__h643343, + _theResult___snd__h643345, + _theResult___snd__h643352, + _theResult___snd__h643358, + _theResult___snd__h643381, + _theResult___snd__h652513, + _theResult___snd__h652524, + _theResult___snd__h652526, + _theResult___snd__h652536, + _theResult___snd__h652542, + _theResult___snd__h652565, + _theResult___snd__h661133, + _theResult___snd__h661147, + _theResult___snd__h661153, + _theResult___snd__h661171, + _theResult___snd__h680494, + _theResult___snd__h680505, + _theResult___snd__h680507, + _theResult___snd__h680517, + _theResult___snd__h680523, + _theResult___snd__h680546, + _theResult___snd__h689090, + _theResult___snd__h689092, + _theResult___snd__h689099, + _theResult___snd__h689105, + _theResult___snd__h689128, + _theResult___snd__h698260, + _theResult___snd__h698271, + _theResult___snd__h698273, + _theResult___snd__h698283, + _theResult___snd__h698289, + _theResult___snd__h698312, + _theResult___snd__h706880, + _theResult___snd__h706894, + _theResult___snd__h706900, + _theResult___snd__h706918, + _theResult___snd__h739167, + _theResult___snd__h739169, + _theResult___snd__h739176, + _theResult___snd__h739182, + _theResult___snd__h739205, + _theResult___snd__h748804, + _theResult___snd__h748815, + _theResult___snd__h748817, + _theResult___snd__h748827, + _theResult___snd__h748833, + _theResult___snd__h748856, + _theResult___snd__h757572, + _theResult___snd__h757586, + _theResult___snd__h757592, + _theResult___snd__h757610, + _theResult___snd__h778020, + _theResult___snd__h778022, + _theResult___snd__h778029, + _theResult___snd__h778035, + _theResult___snd__h778058, + _theResult___snd__h787657, + _theResult___snd__h787668, + _theResult___snd__h787670, + _theResult___snd__h787680, + _theResult___snd__h787686, + _theResult___snd__h787709, + _theResult___snd__h796425, + _theResult___snd__h796439, + _theResult___snd__h796445, + _theResult___snd__h796463, + _theResult___snd__h817324, + _theResult___snd__h817326, + _theResult___snd__h817333, + _theResult___snd__h817339, + _theResult___snd__h817362, + _theResult___snd__h826961, + _theResult___snd__h826972, + _theResult___snd__h826974, + _theResult___snd__h826984, + _theResult___snd__h826990, + _theResult___snd__h827013, + _theResult___snd__h835729, + _theResult___snd__h835743, + _theResult___snd__h835749, + _theResult___snd__h835767, + r1__read__h861174, + r1__read__h861316, + r1__read__h861346, + r1__read__h861933, + result__h599128, + result__h644877, + result__h690624, + result__h741170, + result__h780023, + result__h819327, + sfd__h573271, + sfd__h619025, + sfd__h664772, + sfd__h720190, + sfd__h759184, + sfd__h798488, + sfdin__h588981, + sfdin__h606747, + sfdin__h634730, + sfdin__h652496, + sfdin__h680477, + sfdin__h698243, + sfdin__h748787, + sfdin__h787640, + sfdin__h826944, + x__h599225, + x__h644974, + x__h690721, + x__h741265, + x__h780118, + x__h819422; wire [55 : 0] coreFix_memExe_dispToRegQ_first__695_BIT_102_7_ETC___d3598, + r1__read__h859530, + r1__read__h859934, + r1__read__h860939, + r1__read__h861176, + r1__read__h861348, + r1__read__h861935; + wire [54 : 0] IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19636, + IF_coreFix_aluExe_1_dispToRegQ_first__5790_BIT_ETC___d17443, r1__read__h859532, r1__read__h859936, r1__read__h860941, r1__read__h861178, r1__read__h861350, r1__read__h861937; - wire [54 : 0] IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19636, - IF_coreFix_aluExe_1_dispToRegQ_first__5790_BIT_ETC___d17443, - r1__read__h859534, - r1__read__h859938, - r1__read__h860943, - r1__read__h861180, + wire [53 : 0] r1__read__h861287, + r1__read__h861318, r1__read__h861352, - r1__read__h861939; - wire [53 : 0] r1__read__h861289, - r1__read__h861320, - r1__read__h861354, - r1__read__h861941, - sfd__h739238, - sfd__h748889, - sfd__h757649, - sfd__h778091, - sfd__h787742, - sfd__h796502, - sfd__h817395, - sfd__h827046, - sfd__h835806, - value__h581501, - value__h627250, - value__h672997; + r1__read__h861939, + sfd__h739234, + sfd__h748885, + sfd__h757645, + sfd__h778087, + sfd__h787738, + sfd__h796498, + sfd__h817391, + sfd__h827042, + sfd__h835802, + value__h581498, + value__h627247, + value__h672994; wire [52 : 0] IF_coreFix_memExe_dispToRegQ_first__695_BIT_10_ETC___d3597, INV_coreFix_aluExe_0_regToExeQ_first__9699_BIT_ETC___d20014, INV_coreFix_aluExe_0_regToExeQ_first__9699_BIT_ETC___d20078, INV_coreFix_aluExe_1_regToExeQ_first__7524_BIT_ETC___d17839, INV_coreFix_aluExe_1_regToExeQ_first__7524_BIT_ETC___d17903, - r1__read__h861182, - r1__read__h861291, - r1__read__h861322, - r1__read__h861356, - r1__read__h861943; + r1__read__h861180, + r1__read__h861289, + r1__read__h861320, + r1__read__h861354, + r1__read__h861941; wire [51 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13397, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13399, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14106, @@ -4925,107 +4928,107 @@ module mkCore(CLK, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13429, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14138, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14908, - _theResult___fst_sfd__h724148, - _theResult___fst_sfd__h739976, - _theResult___fst_sfd__h739979, - _theResult___fst_sfd__h749627, - _theResult___fst_sfd__h749630, - _theResult___fst_sfd__h758411, - _theResult___fst_sfd__h758414, - _theResult___fst_sfd__h758423, - _theResult___fst_sfd__h758429, - _theResult___fst_sfd__h763001, - _theResult___fst_sfd__h778829, - _theResult___fst_sfd__h778832, - _theResult___fst_sfd__h788480, - _theResult___fst_sfd__h788483, - _theResult___fst_sfd__h797264, - _theResult___fst_sfd__h797267, - _theResult___fst_sfd__h797276, - _theResult___fst_sfd__h797282, - _theResult___fst_sfd__h802305, - _theResult___fst_sfd__h818133, - _theResult___fst_sfd__h818136, - _theResult___fst_sfd__h827784, - _theResult___fst_sfd__h827787, - _theResult___fst_sfd__h836568, - _theResult___fst_sfd__h836571, - _theResult___fst_sfd__h836580, - _theResult___fst_sfd__h836586, - _theResult___sfd__h739876, - _theResult___sfd__h749527, - _theResult___sfd__h758311, - _theResult___sfd__h778729, - _theResult___sfd__h788380, - _theResult___sfd__h797164, - _theResult___sfd__h818033, - _theResult___sfd__h827684, - _theResult___sfd__h836468, - _theResult___snd_fst_sfd__h720148, - _theResult___snd_fst_sfd__h739982, - _theResult___snd_fst_sfd__h758417, - _theResult___snd_fst_sfd__h759142, - _theResult___snd_fst_sfd__h778835, - _theResult___snd_fst_sfd__h797270, - _theResult___snd_fst_sfd__h798446, - _theResult___snd_fst_sfd__h818139, - _theResult___snd_fst_sfd__h836574, - mask__h242867, - mask__h244024, - mask__h257645, - out___1_sfd__h719896, - out___1_sfd__h758890, - out___1_sfd__h798194, - out_sfd__h739879, - out_sfd__h749530, - out_sfd__h758314, - out_sfd__h778732, - out_sfd__h788383, - out_sfd__h797167, - out_sfd__h818036, - out_sfd__h827687, - out_sfd__h836471; - wire [50 : 0] r1__read__h859536, r1__read__h861184; + _theResult___fst_sfd__h724144, + _theResult___fst_sfd__h739972, + _theResult___fst_sfd__h739975, + _theResult___fst_sfd__h749623, + _theResult___fst_sfd__h749626, + _theResult___fst_sfd__h758407, + _theResult___fst_sfd__h758410, + _theResult___fst_sfd__h758419, + _theResult___fst_sfd__h758425, + _theResult___fst_sfd__h762997, + _theResult___fst_sfd__h778825, + _theResult___fst_sfd__h778828, + _theResult___fst_sfd__h788476, + _theResult___fst_sfd__h788479, + _theResult___fst_sfd__h797260, + _theResult___fst_sfd__h797263, + _theResult___fst_sfd__h797272, + _theResult___fst_sfd__h797278, + _theResult___fst_sfd__h802301, + _theResult___fst_sfd__h818129, + _theResult___fst_sfd__h818132, + _theResult___fst_sfd__h827780, + _theResult___fst_sfd__h827783, + _theResult___fst_sfd__h836564, + _theResult___fst_sfd__h836567, + _theResult___fst_sfd__h836576, + _theResult___fst_sfd__h836582, + _theResult___sfd__h739872, + _theResult___sfd__h749523, + _theResult___sfd__h758307, + _theResult___sfd__h778725, + _theResult___sfd__h788376, + _theResult___sfd__h797160, + _theResult___sfd__h818029, + _theResult___sfd__h827680, + _theResult___sfd__h836464, + _theResult___snd_fst_sfd__h720144, + _theResult___snd_fst_sfd__h739978, + _theResult___snd_fst_sfd__h758413, + _theResult___snd_fst_sfd__h759138, + _theResult___snd_fst_sfd__h778831, + _theResult___snd_fst_sfd__h797266, + _theResult___snd_fst_sfd__h798442, + _theResult___snd_fst_sfd__h818135, + _theResult___snd_fst_sfd__h836570, + mask__h242864, + mask__h244021, + mask__h257642, + out___1_sfd__h719892, + out___1_sfd__h758886, + out___1_sfd__h798190, + out_sfd__h739875, + out_sfd__h749526, + out_sfd__h758310, + out_sfd__h778728, + out_sfd__h788379, + out_sfd__h797163, + out_sfd__h818032, + out_sfd__h827683, + out_sfd__h836467; + wire [50 : 0] r1__read__h859534, r1__read__h861182; wire [49 : 0] coreFix_memExe_dTlbprocResp_BITS_450_TO_401_P_ETC__q7, coreFix_memExe_regToExeQfirst_BITS_218_TO_169_ETC__q5, coreFix_memExe_regToExeQfirst_BITS_381_TO_332_ETC__q3, - highBitsfilter__h1019337, - highBitsfilter__h1019740, - highBitsfilter__h1020157, - highBitsfilter__h1020560, - highBitsfilter__h1021229, - highOffsetBits__h1019338, - highOffsetBits__h1019741, - highOffsetBits__h1020158, - highOffsetBits__h1020561, - highOffsetBits__h1021230, - highOffsetBits__h1042906, - highOffsetBits__h1043309, - highOffsetBits__h1043726, - highOffsetBits__h1044129, - highOffsetBits__h1044796, - highOffsetBits__h245537, - mask__h242758, - mask__h243915, - mask__h257536, - r1__read__h861293, - signBits__h1019335, - signBits__h1042903, - signBits__h245534, - x__h1019365, - x__h1042933, - x__h245564; - wire [48 : 0] r1__read__h859538, r1__read__h861186, r1__read__h861295; - wire [47 : 0] r1__read__h861297; - wire [46 : 0] r1__read__h859540, r1__read__h861188; - wire [45 : 0] r1__read__h859542, r1__read__h861190; - wire [44 : 0] r1__read__h859544, r1__read__h861192; - wire [43 : 0] r1__read__h859546, r1__read__h861194; - wire [42 : 0] r1__read__h861196; - wire [41 : 0] r1__read__h861198; - wire [40 : 0] r1__read__h861200; - wire [38 : 0] IF_csrf_prv_reg_read__0574_ULE_1_2990_AND_IF_c_ETC___d23252; - wire [37 : 0] r1__read__h861299; + highBitsfilter__h1019371, + highBitsfilter__h1019774, + highBitsfilter__h1020191, + highBitsfilter__h1020594, + highBitsfilter__h1021263, + highOffsetBits__h1019372, + highOffsetBits__h1019775, + highOffsetBits__h1020192, + highOffsetBits__h1020595, + highOffsetBits__h1021264, + highOffsetBits__h1042939, + highOffsetBits__h1043342, + highOffsetBits__h1043759, + highOffsetBits__h1044162, + highOffsetBits__h1044829, + highOffsetBits__h245534, + mask__h242755, + mask__h243912, + mask__h257533, + r1__read__h861291, + signBits__h1019369, + signBits__h1042936, + signBits__h245531, + x__h1019399, + x__h1042966, + x__h245561; + wire [48 : 0] r1__read__h859536, r1__read__h861184, r1__read__h861293; + wire [47 : 0] r1__read__h861295; + wire [46 : 0] r1__read__h859538, r1__read__h861186; + wire [45 : 0] r1__read__h859540, r1__read__h861188; + wire [44 : 0] r1__read__h859542, r1__read__h861190; + wire [43 : 0] r1__read__h859544, r1__read__h861192; + wire [42 : 0] r1__read__h861194; + wire [41 : 0] r1__read__h861196; + wire [40 : 0] r1__read__h861198; + wire [38 : 0] IF_csrf_prv_reg_read__0574_ULE_1_2990_AND_IF_c_ETC___d23254; + wire [37 : 0] r1__read__h861297; wire [33 : 0] IF_INV_IF_coreFix_memExe_lsq_firstLd__502_BITS_ETC___d1958, IF_INV_IF_coreFix_memExe_lsq_firstLd__502_BITS_ETC___d2126, IF_INV_coreFix_memExe_lsq_respLd_166_BITS_108__ETC___d2217, @@ -5048,18 +5051,18 @@ module mkCore(CLK, wire [31 : 0] coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q24, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q23, coreFix_memExe_regToExeQfirst_BITS_434_TO_403__q17, - data09497_BITS_31_TO_0__q22, - data10443_BITS_31_TO_0__q27, - r1__read__h859548, - r1__read__h861202, - x__h572678, - x__h618432, + data09494_BITS_31_TO_0__q22, + data10440_BITS_31_TO_0__q27, + r1__read__h859546, + r1__read__h861200, + x__h572675, + x__h618429, x__h65639, - x__h664179, + x__h664176, x_data__h60140; - wire [29 : 0] r1__read__h859550, r1__read__h861204; - wire [27 : 0] r1__read__h861206; - wire [25 : 0] IF_IF_csrf_prv_reg_read__0574_ULE_1_2990_AND_I_ETC___d23270, + wire [29 : 0] r1__read__h859548, r1__read__h861202; + wire [27 : 0] r1__read__h861204; + wire [25 : 0] IF_IF_csrf_prv_reg_read__0574_ULE_1_2990_AND_I_ETC___d23272, IF_basicExec_0102_BIT_325_0113_THEN_basicExec__ETC___d20121, IF_basicExec_7927_BIT_325_7938_THEN_basicExec__ETC___d17946, IF_coreFix_aluExe_0_exeToFinQ_first__0233_BIT__ETC___d20400, @@ -5067,24 +5070,24 @@ module mkCore(CLK, IF_coreFix_aluExe_1_exeToFinQ_first__8058_BIT__ETC___d18226, IF_coreFix_aluExe_1_exeToFinQ_first__8058_BIT__ETC___d18268, IF_coreFix_memExe_regToExeQ_first__664_BIT_103_ETC___d4036, - IF_csrf_mepcc_reg_read_wget__3928_BIT_34_3940__ETC___d23950, - IF_csrf_rg_dpc_read__6534_BIT_34_4739_THEN_csr_ETC___d24747, - IF_csrf_sepcc_reg_read_wget__3894_BIT_34_3906__ETC___d23916; - wire [24 : 0] sfd__h589082, - sfd__h597664, - sfd__h606848, - sfd__h615460, - sfd__h634831, - sfd__h643413, - sfd__h652597, - sfd__h661209, - sfd__h680578, - sfd__h689160, - sfd__h698344, - sfd__h706956, - value__h724777, - value__h763630, - value__h802934; + IF_csrf_mepcc_reg_read_wget__3930_BIT_34_3942__ETC___d23952, + IF_csrf_rg_dpc_read__6534_BIT_34_4741_THEN_csr_ETC___d24749, + IF_csrf_sepcc_reg_read_wget__3896_BIT_34_3908__ETC___d23918; + wire [24 : 0] sfd__h589079, + sfd__h597661, + sfd__h606845, + sfd__h615457, + sfd__h634828, + sfd__h643410, + sfd__h652594, + sfd__h661206, + sfd__h680575, + sfd__h689157, + sfd__h698341, + sfd__h706953, + value__h724773, + value__h763626, + value__h802930; wire [22 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d10568, IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d10570, IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11965, @@ -5109,67 +5112,67 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9192, IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9236, IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9238, - _theResult___fst_sfd__h589588, - _theResult___fst_sfd__h598170, - _theResult___fst_sfd__h607354, - _theResult___fst_sfd__h615990, - _theResult___fst_sfd__h615999, - _theResult___fst_sfd__h616005, - _theResult___fst_sfd__h635337, - _theResult___fst_sfd__h643919, - _theResult___fst_sfd__h653103, - _theResult___fst_sfd__h661739, - _theResult___fst_sfd__h661748, - _theResult___fst_sfd__h661754, - _theResult___fst_sfd__h681084, - _theResult___fst_sfd__h689666, - _theResult___fst_sfd__h698850, - _theResult___fst_sfd__h707486, - _theResult___fst_sfd__h707495, - _theResult___fst_sfd__h707501, - _theResult___sfd__h589507, - _theResult___sfd__h598089, - _theResult___sfd__h607273, - _theResult___sfd__h615909, - _theResult___sfd__h616011, - _theResult___sfd__h635256, - _theResult___sfd__h643838, - _theResult___sfd__h653022, - _theResult___sfd__h661658, - _theResult___sfd__h661760, - _theResult___sfd__h681003, - _theResult___sfd__h689585, - _theResult___sfd__h698769, - _theResult___sfd__h707405, - _theResult___sfd__h707507, - _theResult___snd_fst_sfd__h573224, - _theResult___snd_fst_sfd__h598173, - _theResult___snd_fst_sfd__h615993, - _theResult___snd_fst_sfd__h618978, - _theResult___snd_fst_sfd__h643922, - _theResult___snd_fst_sfd__h661742, - _theResult___snd_fst_sfd__h664725, - _theResult___snd_fst_sfd__h689669, - _theResult___snd_fst_sfd__h707489, - f1_sfd__h719833, - f2_sfd__h758827, - f3_sfd__h798131, - out_f_sfd__h616288, - out_f_sfd__h662037, - out_f_sfd__h707784, - out_sfd__h589510, - out_sfd__h598092, - out_sfd__h607276, - out_sfd__h615912, - out_sfd__h635259, - out_sfd__h643841, - out_sfd__h653025, - out_sfd__h661661, - out_sfd__h681006, - out_sfd__h689588, - out_sfd__h698772, - out_sfd__h707408; - wire [19 : 0] r1__read__h861141; + _theResult___fst_sfd__h589585, + _theResult___fst_sfd__h598167, + _theResult___fst_sfd__h607351, + _theResult___fst_sfd__h615987, + _theResult___fst_sfd__h615996, + _theResult___fst_sfd__h616002, + _theResult___fst_sfd__h635334, + _theResult___fst_sfd__h643916, + _theResult___fst_sfd__h653100, + _theResult___fst_sfd__h661736, + _theResult___fst_sfd__h661745, + _theResult___fst_sfd__h661751, + _theResult___fst_sfd__h681081, + _theResult___fst_sfd__h689663, + _theResult___fst_sfd__h698847, + _theResult___fst_sfd__h707483, + _theResult___fst_sfd__h707492, + _theResult___fst_sfd__h707498, + _theResult___sfd__h589504, + _theResult___sfd__h598086, + _theResult___sfd__h607270, + _theResult___sfd__h615906, + _theResult___sfd__h616008, + _theResult___sfd__h635253, + _theResult___sfd__h643835, + _theResult___sfd__h653019, + _theResult___sfd__h661655, + _theResult___sfd__h661757, + _theResult___sfd__h681000, + _theResult___sfd__h689582, + _theResult___sfd__h698766, + _theResult___sfd__h707402, + _theResult___sfd__h707504, + _theResult___snd_fst_sfd__h573221, + _theResult___snd_fst_sfd__h598170, + _theResult___snd_fst_sfd__h615990, + _theResult___snd_fst_sfd__h618975, + _theResult___snd_fst_sfd__h643919, + _theResult___snd_fst_sfd__h661739, + _theResult___snd_fst_sfd__h664722, + _theResult___snd_fst_sfd__h689666, + _theResult___snd_fst_sfd__h707486, + f1_sfd__h719829, + f2_sfd__h758823, + f3_sfd__h798127, + out_f_sfd__h616285, + out_f_sfd__h662034, + out_f_sfd__h707781, + out_sfd__h589507, + out_sfd__h598089, + out_sfd__h607273, + out_sfd__h615909, + out_sfd__h635256, + out_sfd__h643838, + out_sfd__h653022, + out_sfd__h661658, + out_sfd__h681003, + out_sfd__h689585, + out_sfd__h698769, + out_sfd__h707405; + wire [19 : 0] r1__read__h861139; wire [18 : 0] INV_commitStage_commitTrap_BITS_217_TO_199__q15, INV_coreFix_aluExe_0_regToExeQfirst_BITS_157__ETC__q14, INV_coreFix_aluExe_0_regToExeQfirst_BITS_286__ETC__q13, @@ -5178,8 +5181,8 @@ module mkCore(CLK, INV_coreFix_memExe_lsqrespLd_BITS_108_TO_90__q10, INV_coreFix_memExe_respLrScAmoQ_data_0_BITS_10_ETC__q8, INV_mmio_dataRespQ_data_0_BITS_108_TO_90__q9, - INV_x01338_BITS_108_TO_90__q37, - INV_x85174_BITS_108_TO_90__q35; + INV_x01336_BITS_108_TO_90__q37, + INV_x85172_BITS_108_TO_90__q35; wire [17 : 0] IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__863_ETC___d19292, IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__863_ETC___d19293, IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__581_ETC___d16838, @@ -5196,43 +5199,43 @@ module mkCore(CLK, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3579; wire [15 : 0] IF_IF_NOT_csrf_prv_reg_read__0574_EQ_3_0575_05_ETC___d20611, IF_coreFix_memExe_dispToRegQ_first__695_BIT_10_ETC___d3556, - _theResult____h928986, - base__h1008307, - base__h242592, - base__h243749, - base__h257370, - base__h860635, - base__h861628, - base__h903652, - base__h903936, - base__h904281, - enabled_ints___1__h929511, - enabled_ints__h929557, - newAddrBits__h1019520, - newAddrBits__h1019923, - newAddrBits__h1020340, - newAddrBits__h1020743, - newAddrBits__h1021412, - newAddrBits__h1043088, - newAddrBits__h1043491, - newAddrBits__h1043908, - newAddrBits__h1044311, - newAddrBits__h1044978, - offset__h1008308, - offset__h242593, - offset__h243750, - offset__h257371, - offset__h860636, - offset__h861629, - offset__h903653, - offset__h903937, - offset__h904282, - pend_ints__h928984, - x__h242965, - x__h244122, - x__h257743, - x__h904219, - y__h929523; + _theResult____h928983, + base__h1008341, + base__h242589, + base__h243746, + base__h257367, + base__h860633, + base__h861626, + base__h903649, + base__h903933, + base__h904278, + enabled_ints___1__h929508, + enabled_ints__h929554, + newAddrBits__h1019554, + newAddrBits__h1019957, + newAddrBits__h1020374, + newAddrBits__h1020777, + newAddrBits__h1021446, + newAddrBits__h1043121, + newAddrBits__h1043524, + newAddrBits__h1043941, + newAddrBits__h1044344, + newAddrBits__h1045011, + offset__h1008342, + offset__h242590, + offset__h243747, + offset__h257368, + offset__h860634, + offset__h861627, + offset__h903650, + offset__h903934, + offset__h904279, + pend_ints__h928981, + x__h242962, + x__h244119, + x__h257740, + x__h904216, + y__h929520; wire [13 : 0] IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__863_ETC___d19078, IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__863_ETC___d19079, IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__581_ETC___d16624, @@ -5254,85 +5257,85 @@ module mkCore(CLK, IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16629, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3095, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3445, - b_base__h1005869, - b_base__h128555, - b_base__h141699, - b_base__h185481, - b_base__h204544, - b_base__h219515, - b_base__h873032, - b_base__h873580, - b_base__h914073, - b_base__h914621, + b_base__h1005866, + b_base__h128554, + b_base__h141698, + b_base__h185479, + b_base__h204542, + b_base__h219513, + b_base__h873030, + b_base__h873578, + b_base__h914070, + b_base__h914618, checkForException___d20942, checkForException___d21903, - cr_addrBits__h872618, - cr_addrBits__h873166, - cr_addrBits__h913659, - cr_addrBits__h914207, - data_addrBits__h1030200, - data_addrBits__h1031054, - pc_addrBits__h1005473, - r1__read_BITS_13_TO_0___h929533, - repBoundBits__h245543, - res_addrBits__h127850, - res_addrBits__h140990, - res_addrBits__h180674, - res_addrBits__h199751, - res_addrBits__h218915, - res_addrBits__h238215, - res_addrBits__h571772, - res_addrBits__h572624, - res_addrBits__h618381, - res_addrBits__h664128, - res_addrBits__h710014, - res_addrBits__h710960, - res_addrBits__h855060, - res_addrBits__h899823, - result_d_addrBits__h1019532, - result_d_addrBits__h1019935, - result_d_addrBits__h1020352, - result_d_addrBits__h1020755, - result_d_addrBits__h1021424, - result_d_addrBits__h1043100, - result_d_addrBits__h1043503, - result_d_addrBits__h1043920, - result_d_addrBits__h1044323, - result_d_addrBits__h1044990, - toBoundsM1__h1019348, - toBoundsM1__h1019751, - toBoundsM1__h1020168, - toBoundsM1__h1020571, - toBoundsM1__h1021240, - toBoundsM1__h245547, - toBounds__h1019347, - toBounds__h1019750, - toBounds__h1020167, - toBounds__h1020570, - toBounds__h1021239, - toBounds__h245546, - x1_avValue_new_pcc_capFat_bounds_baseBits__h1011620, - x__h1005842, - x__h1005862, - x__h1011617, - x__h128528, - x__h128548, - x__h141672, - x__h141692, - x__h185454, - x__h185474, - x__h204517, - x__h204537, - x__h219488, - x__h219508, - x__h873005, - x__h873025, - x__h873553, - x__h873573, - x__h914046, - x__h914066, - x__h914594, - x__h914614; + cr_addrBits__h872616, + cr_addrBits__h873164, + cr_addrBits__h913656, + cr_addrBits__h914204, + data_addrBits__h1030233, + data_addrBits__h1031087, + pc_addrBits__h1005470, + r1__read_BITS_13_TO_0___h929530, + repBoundBits__h245540, + res_addrBits__h127849, + res_addrBits__h140989, + res_addrBits__h180672, + res_addrBits__h199749, + res_addrBits__h218913, + res_addrBits__h238212, + res_addrBits__h571768, + res_addrBits__h572621, + res_addrBits__h618378, + res_addrBits__h664125, + res_addrBits__h710011, + res_addrBits__h710957, + res_addrBits__h855057, + res_addrBits__h899821, + result_d_addrBits__h1019566, + result_d_addrBits__h1019969, + result_d_addrBits__h1020386, + result_d_addrBits__h1020789, + result_d_addrBits__h1021458, + result_d_addrBits__h1043133, + result_d_addrBits__h1043536, + result_d_addrBits__h1043953, + result_d_addrBits__h1044356, + result_d_addrBits__h1045023, + toBoundsM1__h1019382, + toBoundsM1__h1019785, + toBoundsM1__h1020202, + toBoundsM1__h1020605, + toBoundsM1__h1021274, + toBoundsM1__h245544, + toBounds__h1019381, + toBounds__h1019784, + toBounds__h1020201, + toBounds__h1020604, + toBounds__h1021273, + toBounds__h245543, + x1_avValue_new_pcc_capFat_bounds_baseBits__h1011654, + x__h1005839, + x__h1005859, + x__h1011651, + x__h128527, + x__h128547, + x__h141671, + x__h141691, + x__h185452, + x__h185472, + x__h204515, + x__h204535, + x__h219486, + x__h219506, + x__h873003, + x__h873023, + x__h873551, + x__h873571, + x__h914043, + x__h914063, + x__h914591, + x__h914611; wire [12 : 0] IF_IF_coreFix_memExe_dTlb_procResp__276_BIT_27_ETC___d4776, IF_NOT_renameStage_rg_m_halt_req_0571_BIT_4_05_ETC___d21275, IF_NOT_renameStage_rg_m_halt_req_0571_BIT_4_05_ETC___d21276, @@ -5352,7 +5355,7 @@ module mkCore(CLK, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10162, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q85, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8765, - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q42, + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q50, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11559, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q120, _0_CONCAT_csrf_external_int_en_vec_3_read__6374_ETC___d20585, @@ -5368,47 +5371,47 @@ module mkCore(CLK, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d10165, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d11562, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d8768, - b_top__h1005868, - b_top__h128554, - b_top__h141698, - b_top__h185480, - b_top__h204543, - b_top__h219514, - b_top__h873031, - b_top__h873579, - b_top__h914072, - b_top__h914620, + b_top__h1005865, + b_top__h128553, + b_top__h141697, + b_top__h185478, + b_top__h204541, + b_top__h219512, + b_top__h873029, + b_top__h873577, + b_top__h914069, + b_top__h914617, capChecks___d4179, - inc__h965682, - inc__h990658, - renaming_spec_bits__h978585, - result__h924564, - result__h924615, - spec_bits__h983636, - topBits__h1005771, - topBits__h128457, - topBits__h141601, - topBits__h185383, - topBits__h204446, - topBits__h219417, - topBits__h872933, - topBits__h873481, - topBits__h913974, - topBits__h914522, - w__h924559, - x__h599261, - x__h645010, - x__h690757, - x__h741302, - x__h780155, - x__h819459, - x__h924563, - x__h924614, - y__h924593, - y__h983649, - y_avValue_snd_fst__h973229, - y_avValue_snd_fst__h973271, - y_avValue_snd_fst__h973313; + inc__h965679, + inc__h990655, + renaming_spec_bits__h978582, + result__h924561, + result__h924612, + spec_bits__h983633, + topBits__h1005768, + topBits__h128456, + topBits__h141600, + topBits__h185381, + topBits__h204444, + topBits__h219415, + topBits__h872931, + topBits__h873479, + topBits__h913971, + topBits__h914519, + w__h924556, + x__h599258, + x__h645007, + x__h690754, + x__h741298, + x__h780151, + x__h819455, + x__h924560, + x__h924611, + y__h924590, + y__h983646, + y_avValue_snd_fst__h973226, + y_avValue_snd_fst__h973268, + y_avValue_snd_fst__h973310; wire [10 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13313, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13315, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14023, @@ -5432,103 +5435,103 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q152, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q169, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q192, - _theResult___exp__h739875, - _theResult___exp__h749526, - _theResult___exp__h758310, - _theResult___exp__h778728, - _theResult___exp__h788379, - _theResult___exp__h797163, - _theResult___exp__h818032, - _theResult___exp__h827683, - _theResult___exp__h836467, - _theResult___fst_exp__h724147, - _theResult___fst_exp__h739211, - _theResult___fst_exp__h739217, - _theResult___fst_exp__h739220, - _theResult___fst_exp__h739975, - _theResult___fst_exp__h739978, - _theResult___fst_exp__h748797, - _theResult___fst_exp__h748862, - _theResult___fst_exp__h748868, - _theResult___fst_exp__h748871, - _theResult___fst_exp__h749626, - _theResult___fst_exp__h749629, - _theResult___fst_exp__h757582, - _theResult___fst_exp__h757621, - _theResult___fst_exp__h757627, - _theResult___fst_exp__h757630, - _theResult___fst_exp__h758410, - _theResult___fst_exp__h758413, - _theResult___fst_exp__h758422, - _theResult___fst_exp__h758425, - _theResult___fst_exp__h763000, - _theResult___fst_exp__h778064, - _theResult___fst_exp__h778070, - _theResult___fst_exp__h778073, - _theResult___fst_exp__h778828, - _theResult___fst_exp__h778831, - _theResult___fst_exp__h787650, - _theResult___fst_exp__h787715, - _theResult___fst_exp__h787721, - _theResult___fst_exp__h787724, - _theResult___fst_exp__h788479, - _theResult___fst_exp__h788482, - _theResult___fst_exp__h796435, - _theResult___fst_exp__h796474, - _theResult___fst_exp__h796480, - _theResult___fst_exp__h796483, - _theResult___fst_exp__h797263, - _theResult___fst_exp__h797266, - _theResult___fst_exp__h797275, - _theResult___fst_exp__h797278, - _theResult___fst_exp__h802304, - _theResult___fst_exp__h817368, - _theResult___fst_exp__h817374, - _theResult___fst_exp__h817377, - _theResult___fst_exp__h818132, - _theResult___fst_exp__h818135, - _theResult___fst_exp__h826954, - _theResult___fst_exp__h827019, - _theResult___fst_exp__h827025, - _theResult___fst_exp__h827028, - _theResult___fst_exp__h827783, - _theResult___fst_exp__h827786, - _theResult___fst_exp__h835739, - _theResult___fst_exp__h835778, - _theResult___fst_exp__h835784, - _theResult___fst_exp__h835787, - _theResult___fst_exp__h836567, - _theResult___fst_exp__h836570, - _theResult___fst_exp__h836579, - _theResult___fst_exp__h836582, - _theResult___snd_fst_exp__h739981, - _theResult___snd_fst_exp__h758416, - _theResult___snd_fst_exp__h778834, - _theResult___snd_fst_exp__h797269, - _theResult___snd_fst_exp__h818138, - _theResult___snd_fst_exp__h836573, + _theResult___exp__h739871, + _theResult___exp__h749522, + _theResult___exp__h758306, + _theResult___exp__h778724, + _theResult___exp__h788375, + _theResult___exp__h797159, + _theResult___exp__h818028, + _theResult___exp__h827679, + _theResult___exp__h836463, + _theResult___fst_exp__h724143, + _theResult___fst_exp__h739207, + _theResult___fst_exp__h739213, + _theResult___fst_exp__h739216, + _theResult___fst_exp__h739971, + _theResult___fst_exp__h739974, + _theResult___fst_exp__h748793, + _theResult___fst_exp__h748858, + _theResult___fst_exp__h748864, + _theResult___fst_exp__h748867, + _theResult___fst_exp__h749622, + _theResult___fst_exp__h749625, + _theResult___fst_exp__h757578, + _theResult___fst_exp__h757617, + _theResult___fst_exp__h757623, + _theResult___fst_exp__h757626, + _theResult___fst_exp__h758406, + _theResult___fst_exp__h758409, + _theResult___fst_exp__h758418, + _theResult___fst_exp__h758421, + _theResult___fst_exp__h762996, + _theResult___fst_exp__h778060, + _theResult___fst_exp__h778066, + _theResult___fst_exp__h778069, + _theResult___fst_exp__h778824, + _theResult___fst_exp__h778827, + _theResult___fst_exp__h787646, + _theResult___fst_exp__h787711, + _theResult___fst_exp__h787717, + _theResult___fst_exp__h787720, + _theResult___fst_exp__h788475, + _theResult___fst_exp__h788478, + _theResult___fst_exp__h796431, + _theResult___fst_exp__h796470, + _theResult___fst_exp__h796476, + _theResult___fst_exp__h796479, + _theResult___fst_exp__h797259, + _theResult___fst_exp__h797262, + _theResult___fst_exp__h797271, + _theResult___fst_exp__h797274, + _theResult___fst_exp__h802300, + _theResult___fst_exp__h817364, + _theResult___fst_exp__h817370, + _theResult___fst_exp__h817373, + _theResult___fst_exp__h818128, + _theResult___fst_exp__h818131, + _theResult___fst_exp__h826950, + _theResult___fst_exp__h827015, + _theResult___fst_exp__h827021, + _theResult___fst_exp__h827024, + _theResult___fst_exp__h827779, + _theResult___fst_exp__h827782, + _theResult___fst_exp__h835735, + _theResult___fst_exp__h835774, + _theResult___fst_exp__h835780, + _theResult___fst_exp__h835783, + _theResult___fst_exp__h836563, + _theResult___fst_exp__h836566, + _theResult___fst_exp__h836575, + _theResult___fst_exp__h836578, + _theResult___snd_fst_exp__h739977, + _theResult___snd_fst_exp__h758412, + _theResult___snd_fst_exp__h778830, + _theResult___snd_fst_exp__h797265, + _theResult___snd_fst_exp__h818134, + _theResult___snd_fst_exp__h836569, coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q84, - coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q41, + coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q49, coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q119, - din_inc___2_exp__h758470, - din_inc___2_exp__h758505, - din_inc___2_exp__h758531, - din_inc___2_exp__h797323, - din_inc___2_exp__h797358, - din_inc___2_exp__h797384, - din_inc___2_exp__h836627, - din_inc___2_exp__h836662, - din_inc___2_exp__h836688, - out_exp__h739878, - out_exp__h749529, - out_exp__h758313, - out_exp__h778731, - out_exp__h788382, - out_exp__h797166, - out_exp__h818035, - out_exp__h827686, - out_exp__h836470, - x__h1009594; + din_inc___2_exp__h758466, + din_inc___2_exp__h758501, + din_inc___2_exp__h758527, + din_inc___2_exp__h797319, + din_inc___2_exp__h797354, + din_inc___2_exp__h797380, + din_inc___2_exp__h836623, + din_inc___2_exp__h836658, + din_inc___2_exp__h836684, + out_exp__h739874, + out_exp__h749525, + out_exp__h758309, + out_exp__h778727, + out_exp__h788378, + out_exp__h797162, + out_exp__h818031, + out_exp__h827682, + out_exp__h836466, + x__h1009628; wire [9 : 0] IF_coreFix_memExe_dispToRegQ_first__695_BIT_10_ETC___d3654; wire [8 : 0] IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d10483, IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d11880, @@ -5584,128 +5587,128 @@ module mkCore(CLK, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q90, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q55, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q125, - _theResult___exp__h589506, - _theResult___exp__h598088, - _theResult___exp__h607272, - _theResult___exp__h615908, - _theResult___exp__h616010, - _theResult___exp__h635255, - _theResult___exp__h643837, - _theResult___exp__h653021, - _theResult___exp__h661657, - _theResult___exp__h661759, - _theResult___exp__h681002, - _theResult___exp__h689584, - _theResult___exp__h698768, - _theResult___exp__h707404, - _theResult___exp__h707506, - _theResult___fst_exp__h588990, - _theResult___fst_exp__h589055, + _theResult___exp__h589503, + _theResult___exp__h598085, + _theResult___exp__h607269, + _theResult___exp__h615905, + _theResult___exp__h616007, + _theResult___exp__h635252, + _theResult___exp__h643834, + _theResult___exp__h653018, + _theResult___exp__h661654, + _theResult___exp__h661756, + _theResult___exp__h680999, + _theResult___exp__h689581, + _theResult___exp__h698765, + _theResult___exp__h707401, + _theResult___exp__h707503, + _theResult___fst_exp__h588987, + _theResult___fst_exp__h589052, + _theResult___fst_exp__h589058, _theResult___fst_exp__h589061, - _theResult___fst_exp__h589064, - _theResult___fst_exp__h589587, - _theResult___fst_exp__h597637, + _theResult___fst_exp__h589584, + _theResult___fst_exp__h597634, + _theResult___fst_exp__h597640, _theResult___fst_exp__h597643, - _theResult___fst_exp__h597646, - _theResult___fst_exp__h598169, - _theResult___fst_exp__h606756, - _theResult___fst_exp__h606821, + _theResult___fst_exp__h598166, + _theResult___fst_exp__h606753, + _theResult___fst_exp__h606818, + _theResult___fst_exp__h606824, _theResult___fst_exp__h606827, - _theResult___fst_exp__h606830, - _theResult___fst_exp__h607353, - _theResult___fst_exp__h615393, - _theResult___fst_exp__h615432, + _theResult___fst_exp__h607350, + _theResult___fst_exp__h615390, + _theResult___fst_exp__h615429, + _theResult___fst_exp__h615435, _theResult___fst_exp__h615438, - _theResult___fst_exp__h615441, - _theResult___fst_exp__h615989, + _theResult___fst_exp__h615986, + _theResult___fst_exp__h615995, _theResult___fst_exp__h615998, - _theResult___fst_exp__h616001, - _theResult___fst_exp__h634739, - _theResult___fst_exp__h634804, + _theResult___fst_exp__h634736, + _theResult___fst_exp__h634801, + _theResult___fst_exp__h634807, _theResult___fst_exp__h634810, - _theResult___fst_exp__h634813, - _theResult___fst_exp__h635336, - _theResult___fst_exp__h643386, + _theResult___fst_exp__h635333, + _theResult___fst_exp__h643383, + _theResult___fst_exp__h643389, _theResult___fst_exp__h643392, - _theResult___fst_exp__h643395, - _theResult___fst_exp__h643918, - _theResult___fst_exp__h652505, - _theResult___fst_exp__h652570, + _theResult___fst_exp__h643915, + _theResult___fst_exp__h652502, + _theResult___fst_exp__h652567, + _theResult___fst_exp__h652573, _theResult___fst_exp__h652576, - _theResult___fst_exp__h652579, - _theResult___fst_exp__h653102, - _theResult___fst_exp__h661142, - _theResult___fst_exp__h661181, + _theResult___fst_exp__h653099, + _theResult___fst_exp__h661139, + _theResult___fst_exp__h661178, + _theResult___fst_exp__h661184, _theResult___fst_exp__h661187, - _theResult___fst_exp__h661190, - _theResult___fst_exp__h661738, + _theResult___fst_exp__h661735, + _theResult___fst_exp__h661744, _theResult___fst_exp__h661747, - _theResult___fst_exp__h661750, - _theResult___fst_exp__h680486, - _theResult___fst_exp__h680551, + _theResult___fst_exp__h680483, + _theResult___fst_exp__h680548, + _theResult___fst_exp__h680554, _theResult___fst_exp__h680557, - _theResult___fst_exp__h680560, - _theResult___fst_exp__h681083, - _theResult___fst_exp__h689133, + _theResult___fst_exp__h681080, + _theResult___fst_exp__h689130, + _theResult___fst_exp__h689136, _theResult___fst_exp__h689139, - _theResult___fst_exp__h689142, - _theResult___fst_exp__h689665, - _theResult___fst_exp__h698252, - _theResult___fst_exp__h698317, + _theResult___fst_exp__h689662, + _theResult___fst_exp__h698249, + _theResult___fst_exp__h698314, + _theResult___fst_exp__h698320, _theResult___fst_exp__h698323, - _theResult___fst_exp__h698326, - _theResult___fst_exp__h698849, - _theResult___fst_exp__h706889, - _theResult___fst_exp__h706928, + _theResult___fst_exp__h698846, + _theResult___fst_exp__h706886, + _theResult___fst_exp__h706925, + _theResult___fst_exp__h706931, _theResult___fst_exp__h706934, - _theResult___fst_exp__h706937, - _theResult___fst_exp__h707485, + _theResult___fst_exp__h707482, + _theResult___fst_exp__h707491, _theResult___fst_exp__h707494, - _theResult___fst_exp__h707497, - _theResult___snd_fst_exp__h598172, - _theResult___snd_fst_exp__h615992, - _theResult___snd_fst_exp__h643921, - _theResult___snd_fst_exp__h661741, - _theResult___snd_fst_exp__h689668, - _theResult___snd_fst_exp__h707488, - din_inc___2_exp__h616023, - din_inc___2_exp__h616047, - din_inc___2_exp__h616077, - din_inc___2_exp__h616101, - din_inc___2_exp__h661772, - din_inc___2_exp__h661796, - din_inc___2_exp__h661826, - din_inc___2_exp__h661850, - din_inc___2_exp__h707519, - din_inc___2_exp__h707543, - din_inc___2_exp__h707573, - din_inc___2_exp__h707597, - f1_exp19832_MINUS_127__q148, - f1_exp__h719832, - f2_exp58826_MINUS_127__q188, - f2_exp__h758826, - f3_exp98130_MINUS_127__q165, - f3_exp__h798130, - out_exp__h589509, - out_exp__h598091, - out_exp__h607275, - out_exp__h615911, - out_exp__h635258, - out_exp__h643840, - out_exp__h653024, - out_exp__h661660, - out_exp__h681005, - out_exp__h689587, - out_exp__h698771, - out_exp__h707407, - out_f_exp__h616287, - out_f_exp__h662036, - out_f_exp__h707783, - x__h859507; + _theResult___snd_fst_exp__h598169, + _theResult___snd_fst_exp__h615989, + _theResult___snd_fst_exp__h643918, + _theResult___snd_fst_exp__h661738, + _theResult___snd_fst_exp__h689665, + _theResult___snd_fst_exp__h707485, + din_inc___2_exp__h616020, + din_inc___2_exp__h616044, + din_inc___2_exp__h616074, + din_inc___2_exp__h616098, + din_inc___2_exp__h661769, + din_inc___2_exp__h661793, + din_inc___2_exp__h661823, + din_inc___2_exp__h661847, + din_inc___2_exp__h707516, + din_inc___2_exp__h707540, + din_inc___2_exp__h707570, + din_inc___2_exp__h707594, + f1_exp19828_MINUS_127__q148, + f1_exp__h719828, + f2_exp58822_MINUS_127__q188, + f2_exp__h758822, + f3_exp98126_MINUS_127__q165, + f3_exp__h798126, + out_exp__h589506, + out_exp__h598088, + out_exp__h607272, + out_exp__h615908, + out_exp__h635255, + out_exp__h643837, + out_exp__h653021, + out_exp__h661657, + out_exp__h681002, + out_exp__h689584, + out_exp__h698768, + out_exp__h707404, + out_f_exp__h616284, + out_f_exp__h662033, + out_f_exp__h707780, + x__h859505; wire [6 : 0] NOT_coreFix_aluExe_0_dispToRegQ_first__8612_BI_ETC___d19678, NOT_coreFix_aluExe_1_dispToRegQ_first__5790_BI_ETC___d17503, - x__h1010320, - x__h247568; + x__h1010354, + x__h247565; wire [5 : 0] IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d11255, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d8461, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d9858, @@ -5731,22 +5734,22 @@ module mkCore(CLK, IF_fetchStage_pipelines_0_first__0544_BITS_265_ETC___d22369, IF_fetchStage_pipelines_1_first__0553_BITS_265_ETC___d22548, NOT_coreFix_memExe_dispToRegQ_first__695_BIT_1_ETC___d3653, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d24864, + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d24866, fetchStage_pipelines_0_first__0544_BIT_167_088_ETC___d20904, fetchStage_pipelines_1_first__0553_BIT_167_185_ETC___d21876, - x__h1005682, - x__h1010294, - x__h1010951, - x__h1011638, - x__h128368, - x__h141512, - x__h185294, - x__h204357, - x__h219328, - x__h872832, - x__h873380, - x__h913873, - x__h914421; + x__h1005679, + x__h1010328, + x__h1010985, + x__h1011672, + x__h128367, + x__h141511, + x__h185292, + x__h204355, + x__h219326, + x__h872830, + x__h873378, + x__h913870, + x__h914418; wire [4 : 0] IF_IF_coreFix_aluExe_0_exeToFinQ_first__0233_B_ETC___d20377, IF_IF_coreFix_aluExe_0_exeToFinQ_first__0233_B_ETC___d20378, IF_IF_coreFix_aluExe_1_exeToFinQ_first__8058_B_ETC___d18203, @@ -5773,7 +5776,7 @@ module mkCore(CLK, IF_INV_coreFix_aluExe_1_regToExeQ_first__7524__ETC___d17923, IF_NOT_fetchStage_pipelines_0_first__0544_BITS_ETC___d22423, IF_NOT_fetchStage_pipelines_1_first__0553_BITS_ETC___d22613, - IF_rob_deqPort_0_canDeq__3983_THEN_IF_NOT_rob__ETC___d24215, + IF_rob_deqPort_0_canDeq__3985_THEN_IF_NOT_rob__ETC___d24217, _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d10785, _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d12182, _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d9388, @@ -5789,51 +5792,51 @@ module mkCore(CLK, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d10797, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d12194, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d9400, - cause_code__h1007591, + cause_code__h1007625, coreFix_memExe_regToExeQ_first__664_BITS_383_T_ETC___d4142, csrf_ddc_reg_read__078_BITS_85_TO_83_164_ULT_c_ETC___d4175, - fflags__h1027798, - r1__read__h862252, - res_fflags__h572664, - res_fflags__h618418, - res_fflags__h664165, + fflags__h1027832, + r1__read__h862250, + res_fflags__h572661, + res_fflags__h618415, + res_fflags__h664162, rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19426, rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16972, - x__h150548, - x__h153682, - x__h252368, - x__h252380, - x__h252392, - x__h252404, - x__h252416, - x__h252428, - x__h252440, - x__h252452, - x__h252464, - x__h252476, - x__h252488, - x__h252500, - x__h252512, - x__h252524, - x__h252536, - y__h252369, - y__h252381, - y__h252393, - y__h252405, - y__h252417, - y__h252429, - y__h252441, - y__h252453, - y__h252465, - y__h252477, - y__h252489, - y__h252501, - y__h252513, - y__h252525, - y__h252537, - y_avValue_snd_fst__h1027215, - y_avValue_snd_fst__h1027858, - y_avValue_snd_fst__h1027887; + x__h150547, + x__h153681, + x__h252365, + x__h252377, + x__h252389, + x__h252401, + x__h252413, + x__h252425, + x__h252437, + x__h252449, + x__h252461, + x__h252473, + x__h252485, + x__h252497, + x__h252509, + x__h252521, + x__h252533, + y__h252366, + y__h252378, + y__h252390, + y__h252402, + y__h252414, + y__h252426, + y__h252438, + y__h252450, + y__h252462, + y__h252474, + y__h252486, + y__h252498, + y__h252510, + y__h252522, + y__h252534, + y_avValue_snd_fst__h1027249, + y_avValue_snd_fst__h1027892, + y_avValue_snd_fst__h1027921; wire [3 : 0] IF_IF_coreFix_aluExe_0_dispToRegQ_first__8612__ETC___d19675, IF_IF_coreFix_aluExe_1_dispToRegQ_first__5790__ETC___d17500, IF_IF_renameStage_rg_m_halt_req_0571_BIT_4_057_ETC___d21265, @@ -5878,7 +5881,7 @@ module mkCore(CLK, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3416, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3453, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3651, - vm_mode_reg__read__h861147; + vm_mode_reg__read__h861145; wire [2 : 0] IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__863_ETC___d19336, IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__863_ETC___d19337, IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__581_ETC___d16882, @@ -5894,58 +5897,58 @@ module mkCore(CLK, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3353, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3608, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d7184, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d24797, - _theResult_____2__h519793, - dcsr_cause__h1005097, - next_deqP___1__h520038, - repBound__h1008332, - repBound__h240209, - repBound__h241894, - repBound__h251108, - repBound__h251633, - repBound__h860491, - repBound__h860813, - repBound__h861484, - repBound__h861805, - repBound__h862314, - repBound__h863992, - repBound__h866954, - repBound__h866972, - repBound__h873086, - repBound__h873634, - repBound__h905963, - repBound__h908290, - repBound__h908308, - repBound__h914127, - repBound__h914675, - tb__h873083, - tb__h873631, - tb__h914124, - tb__h914672, - tmp_expBotHalf__h1005637, - tmp_expBotHalf__h128323, - tmp_expBotHalf__h141467, - tmp_expBotHalf__h185249, - tmp_expBotHalf__h204312, - tmp_expBotHalf__h219283, - tmp_expBotHalf__h872786, - tmp_expBotHalf__h873334, - tmp_expBotHalf__h913827, - tmp_expBotHalf__h914375, - tmp_expTopHalf__h1005635, - tmp_expTopHalf__h128321, - tmp_expTopHalf__h141465, - tmp_expTopHalf__h185247, - tmp_expTopHalf__h204310, - tmp_expTopHalf__h219281, - tmp_expTopHalf__h872784, - tmp_expTopHalf__h873332, - tmp_expTopHalf__h913825, - tmp_expTopHalf__h914373, - v__h519249, - v__h519444, - x__h526100, - x_decodeInfo_frm__h935002; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d24799, + _theResult_____2__h519790, + dcsr_cause__h1005094, + next_deqP___1__h520035, + repBound__h1008366, + repBound__h240206, + repBound__h241891, + repBound__h251105, + repBound__h251630, + repBound__h860489, + repBound__h860811, + repBound__h861482, + repBound__h861803, + repBound__h862312, + repBound__h863990, + repBound__h866952, + repBound__h866970, + repBound__h873084, + repBound__h873632, + repBound__h905960, + repBound__h908287, + repBound__h908305, + repBound__h914124, + repBound__h914672, + tb__h873081, + tb__h873629, + tb__h914121, + tb__h914669, + tmp_expBotHalf__h1005634, + tmp_expBotHalf__h128322, + tmp_expBotHalf__h141466, + tmp_expBotHalf__h185247, + tmp_expBotHalf__h204310, + tmp_expBotHalf__h219281, + tmp_expBotHalf__h872784, + tmp_expBotHalf__h873332, + tmp_expBotHalf__h913824, + tmp_expBotHalf__h914372, + tmp_expTopHalf__h1005632, + tmp_expTopHalf__h128320, + tmp_expTopHalf__h141464, + tmp_expTopHalf__h185245, + tmp_expTopHalf__h204308, + tmp_expTopHalf__h219279, + tmp_expTopHalf__h872782, + tmp_expTopHalf__h873330, + tmp_expTopHalf__h913822, + tmp_expTopHalf__h914370, + v__h519246, + v__h519441, + x__h526097, + x_decodeInfo_frm__h934999; wire [1 : 0] IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__863_ETC___d19279, IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__863_ETC___d19280, IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__581_ETC___d16825, @@ -5956,111 +5959,111 @@ module mkCore(CLK, IF_NOT_coreFix_memExe_bypassWire_0_whas__716_7_ETC___d3567, IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17365, IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17359, - IF_rob_deqPort_0_canDeq__3983_THEN_IF_NOT_rob__ETC___d24237, + IF_rob_deqPort_0_canDeq__3985_THEN_IF_NOT_rob__ETC___d24239, IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d19284, IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16830, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3296, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3571, - IF_sfdin06750_BIT_33_THEN_2_ELSE_0__q52, - IF_sfdin26948_BIT_4_THEN_2_ELSE_0__q168, - IF_sfdin34733_BIT_33_THEN_2_ELSE_0__q77, - IF_sfdin48791_BIT_4_THEN_2_ELSE_0__q151, - IF_sfdin52499_BIT_33_THEN_2_ELSE_0__q87, - IF_sfdin80480_BIT_33_THEN_2_ELSE_0__q112, - IF_sfdin87644_BIT_4_THEN_2_ELSE_0__q191, - IF_sfdin88984_BIT_33_THEN_2_ELSE_0__q44, - IF_sfdin98246_BIT_33_THEN_2_ELSE_0__q122, - IF_theResult___snd06883_BIT_33_THEN_2_ELSE_0__q127, - IF_theResult___snd15387_BIT_33_THEN_2_ELSE_0__q57, - IF_theResult___snd17328_BIT_4_THEN_2_ELSE_0__q164, - IF_theResult___snd35733_BIT_4_THEN_2_ELSE_0__q171, - IF_theResult___snd39171_BIT_4_THEN_2_ELSE_0__q147, - IF_theResult___snd43346_BIT_33_THEN_2_ELSE_0__q79, - IF_theResult___snd57576_BIT_4_THEN_2_ELSE_0__q154, - IF_theResult___snd61136_BIT_33_THEN_2_ELSE_0__q92, - IF_theResult___snd78024_BIT_4_THEN_2_ELSE_0__q187, - IF_theResult___snd89093_BIT_33_THEN_2_ELSE_0__q114, - IF_theResult___snd96429_BIT_4_THEN_2_ELSE_0__q194, - IF_theResult___snd97597_BIT_33_THEN_2_ELSE_0__q46, - carry_out__h1005773, - carry_out__h128459, - carry_out__h141603, - carry_out__h185385, - carry_out__h204448, - carry_out__h219419, - carry_out__h872935, - carry_out__h873483, - carry_out__h913976, - carry_out__h914524, + IF_sfdin06747_BIT_33_THEN_2_ELSE_0__q52, + IF_sfdin26944_BIT_4_THEN_2_ELSE_0__q168, + IF_sfdin34730_BIT_33_THEN_2_ELSE_0__q77, + IF_sfdin48787_BIT_4_THEN_2_ELSE_0__q151, + IF_sfdin52496_BIT_33_THEN_2_ELSE_0__q87, + IF_sfdin80477_BIT_33_THEN_2_ELSE_0__q112, + IF_sfdin87640_BIT_4_THEN_2_ELSE_0__q191, + IF_sfdin88981_BIT_33_THEN_2_ELSE_0__q42, + IF_sfdin98243_BIT_33_THEN_2_ELSE_0__q122, + IF_theResult___snd06880_BIT_33_THEN_2_ELSE_0__q127, + IF_theResult___snd15384_BIT_33_THEN_2_ELSE_0__q57, + IF_theResult___snd17324_BIT_4_THEN_2_ELSE_0__q164, + IF_theResult___snd35729_BIT_4_THEN_2_ELSE_0__q171, + IF_theResult___snd39167_BIT_4_THEN_2_ELSE_0__q147, + IF_theResult___snd43343_BIT_33_THEN_2_ELSE_0__q79, + IF_theResult___snd57572_BIT_4_THEN_2_ELSE_0__q154, + IF_theResult___snd61133_BIT_33_THEN_2_ELSE_0__q92, + IF_theResult___snd78020_BIT_4_THEN_2_ELSE_0__q187, + IF_theResult___snd89090_BIT_33_THEN_2_ELSE_0__q114, + IF_theResult___snd96425_BIT_4_THEN_2_ELSE_0__q194, + IF_theResult___snd97594_BIT_33_THEN_2_ELSE_0__q44, + carry_out__h1005770, + carry_out__h128458, + carry_out__h141602, + carry_out__h185383, + carry_out__h204446, + carry_out__h219417, + carry_out__h872933, + carry_out__h873481, + carry_out__h913973, + carry_out__h914521, coreFix_memExe_dTlbprocResp_BITS_292_TO_291__q6, coreFix_memExe_regToExeQfirst_BITS_223_TO_222__q2, coreFix_memExe_regToExeQfirst_BITS_60_TO_59__q4, - cr_reserved__h873169, - cr_reserved__h914210, - guard__h580889, - guard__h589598, - guard__h598528, - guard__h607364, - guard__h626640, - guard__h635347, - guard__h644277, - guard__h653113, - guard__h672387, - guard__h681094, - guard__h690024, - guard__h698860, - guard__h731259, - guard__h740571, - guard__h749640, - guard__h770112, - guard__h779424, - guard__h788493, - guard__h809416, - guard__h818728, - guard__h827797, - impliedTopBits__h1005775, - impliedTopBits__h128461, - impliedTopBits__h141605, - impliedTopBits__h185387, - impliedTopBits__h204450, - impliedTopBits__h219421, - impliedTopBits__h872937, - impliedTopBits__h873485, - impliedTopBits__h913978, - impliedTopBits__h914526, - len_correction__h1005774, - len_correction__h128460, - len_correction__h141604, - len_correction__h185386, - len_correction__h204449, - len_correction__h219420, - len_correction__h872936, - len_correction__h873484, - len_correction__h913977, - len_correction__h914525, - prv__h1028891, - prv__h1028935, - r1__read_BITS_13_TO_12___h935208, - sbIdx__h153573, - v__h841897, - v__h841907, - v__h842938, - wordIdx__h266170, - x__h1005859, - x__h1023576, - x__h1028046, - x__h128545, - x__h141689, - x__h185471, - x__h204534, - x__h219505, - x__h873022, - x__h873570, - x__h914063, - x__h914611, - y_avValue_snd_snd_snd_fst__h1027225, - y_avValue_snd_snd_snd_fst__h1027868, - y_avValue_snd_snd_snd_fst__h1027897; + cr_reserved__h873167, + cr_reserved__h914207, + guard__h580886, + guard__h589595, + guard__h598525, + guard__h607361, + guard__h626637, + guard__h635344, + guard__h644274, + guard__h653110, + guard__h672384, + guard__h681091, + guard__h690021, + guard__h698857, + guard__h731255, + guard__h740567, + guard__h749636, + guard__h770108, + guard__h779420, + guard__h788489, + guard__h809412, + guard__h818724, + guard__h827793, + impliedTopBits__h1005772, + impliedTopBits__h128460, + impliedTopBits__h141604, + impliedTopBits__h185385, + impliedTopBits__h204448, + impliedTopBits__h219419, + impliedTopBits__h872935, + impliedTopBits__h873483, + impliedTopBits__h913975, + impliedTopBits__h914523, + len_correction__h1005771, + len_correction__h128459, + len_correction__h141603, + len_correction__h185384, + len_correction__h204447, + len_correction__h219418, + len_correction__h872934, + len_correction__h873482, + len_correction__h913974, + len_correction__h914522, + prv__h1028925, + prv__h1028969, + r1__read_BITS_13_TO_12___h935205, + sbIdx__h153572, + v__h841893, + v__h841903, + v__h842934, + wordIdx__h266168, + x__h1005856, + x__h1023610, + x__h1028080, + x__h128544, + x__h141688, + x__h185469, + x__h204532, + x__h219503, + x__h873020, + x__h873568, + x__h914060, + x__h914608, + y_avValue_snd_snd_snd_fst__h1027259, + y_avValue_snd_snd_snd_fst__h1027902, + y_avValue_snd_snd_snd_fst__h1027931; wire IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d10680, IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d10730, IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d12077, @@ -6132,13 +6135,13 @@ module mkCore(CLK, IF_IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_w_ETC___d7897, IF_IF_fetchStage_pipelines_0_first__0544_BITS__ETC___d21530, IF_IF_fetchStage_pipelines_0_first__0544_BITS__ETC___d22175, - IF_IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_ETC___d23507, - IF_IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_ETC___d23551, - IF_IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_ETC___d23646, - IF_IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_ETC___d23688, - IF_IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_ETC___d23801, - IF_INV_commitStage_commitTrap_2639_BITS_217_TO_ETC___d23037, - IF_INV_commitStage_commitTrap_2639_BITS_217_TO_ETC___d23039, + IF_IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_ETC___d23509, + IF_IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_ETC___d23553, + IF_IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_ETC___d23648, + IF_IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_ETC___d23690, + IF_IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_ETC___d23803, + IF_INV_commitStage_commitTrap_2639_BITS_217_TO_ETC___d23038, + IF_INV_commitStage_commitTrap_2639_BITS_217_TO_ETC___d23040, IF_INV_coreFix_aluExe_0_regToExeQ_first__9699__ETC___d20021, IF_INV_coreFix_aluExe_0_regToExeQ_first__9699__ETC___d20022, IF_INV_coreFix_aluExe_0_regToExeQ_first__9699__ETC___d20024, @@ -6331,7 +6334,7 @@ module mkCore(CLK, IF_NOT_fetchStage_pipelines_0_canDeq__0542_054_ETC___d22128, IF_NOT_fetchStage_pipelines_1_first__0553_BITS_ETC___d22040, IF_NOT_fetchStage_pipelines_1_first__0553_BITS_ETC___d22127, - IF_NOT_rob_deqPort_1_deq_data__3990_BIT_25_399_ETC___d24228, + IF_NOT_rob_deqPort_1_deq_data__3992_BIT_25_399_ETC___d24230, IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d13244, IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d13959, IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d14193, @@ -6450,11 +6453,11 @@ module mkCore(CLK, IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17315, IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17343, IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17410, - IF_csrf_mtcc_reg_read__6389_BITS_149_TO_86_318_ETC___d23216, - IF_csrf_mtcc_reg_read__6389_BITS_149_TO_86_318_ETC___d23219, - IF_csrf_mtcc_reg_read__6389_BITS_149_TO_86_318_ETC___d23241, - IF_csrf_mtcc_reg_read__6389_BITS_149_TO_86_318_ETC___d23244, - IF_csrf_mtcc_reg_read__6389_BIT_86_3183_AND_NO_ETC___d23247, + IF_csrf_mtcc_reg_read__6389_BITS_149_TO_86_318_ETC___d23218, + IF_csrf_mtcc_reg_read__6389_BITS_149_TO_86_318_ETC___d23221, + IF_csrf_mtcc_reg_read__6389_BITS_149_TO_86_318_ETC___d23243, + IF_csrf_mtcc_reg_read__6389_BITS_149_TO_86_318_ETC___d23246, + IF_csrf_mtcc_reg_read__6389_BIT_86_3185_AND_NO_ETC___d23249, IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16278, IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16280, IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16993, @@ -6472,16 +6475,16 @@ module mkCore(CLK, IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17309, IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17337, IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17404, - IF_csrf_stcc_reg_read__6237_BITS_149_TO_86_311_ETC___d23147, - IF_csrf_stcc_reg_read__6237_BITS_149_TO_86_311_ETC___d23150, - IF_csrf_stcc_reg_read__6237_BITS_149_TO_86_311_ETC___d23172, - IF_csrf_stcc_reg_read__6237_BITS_149_TO_86_311_ETC___d23175, - IF_csrf_stcc_reg_read__6237_BIT_86_3112_AND_NO_ETC___d23178, - IF_f_csr_reqs_first__4359_BIT_63_4513_THEN_NOT_ETC___d24523, - IF_f_csr_reqs_first__4359_BIT_63_4513_THEN_NOT_ETC___d24545, - IF_f_csr_reqs_first__4359_BIT_63_4513_THEN_NOT_ETC___d24603, - IF_f_csr_reqs_first__4359_BIT_63_4513_THEN_NOT_ETC___d24623, - IF_f_csr_reqs_first__4359_BIT_63_4513_THEN_NOT_ETC___d24694, + IF_csrf_stcc_reg_read__6237_BITS_149_TO_86_311_ETC___d23149, + IF_csrf_stcc_reg_read__6237_BITS_149_TO_86_311_ETC___d23152, + IF_csrf_stcc_reg_read__6237_BITS_149_TO_86_311_ETC___d23174, + IF_csrf_stcc_reg_read__6237_BITS_149_TO_86_311_ETC___d23177, + IF_csrf_stcc_reg_read__6237_BIT_86_3114_AND_NO_ETC___d23180, + IF_f_csr_reqs_first__4361_BIT_63_4515_THEN_NOT_ETC___d24525, + IF_f_csr_reqs_first__4361_BIT_63_4515_THEN_NOT_ETC___d24547, + IF_f_csr_reqs_first__4361_BIT_63_4515_THEN_NOT_ETC___d24605, + IF_f_csr_reqs_first__4361_BIT_63_4515_THEN_NOT_ETC___d24625, + IF_f_csr_reqs_first__4361_BIT_63_4515_THEN_NOT_ETC___d24696, IF_fetchStage_RDY_pipelines_0_first__0541_AND__ETC___d21486, IF_fetchStage_RDY_pipelines_1_first__0552_AND__ETC___d22042, IF_fetchStage_RDY_pipelines_1_first__0552_AND__ETC___d22117, @@ -6508,12 +6511,12 @@ module mkCore(CLK, IF_mmio_dataRespQ_enqReq_lat_1_whas__73_THEN_m_ETC___d182, IF_mmio_pRqQ_enqReq_lat_1_whas__56_THEN_mmio_p_ETC___d565, IF_mmio_pRsQ_enqReq_lat_1_whas__15_THEN_mmio_p_ETC___d424, - IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_19_ETC___d23510, - IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_19_ETC___d23556, - IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_19_ETC___d23649, - IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_19_ETC___d23693, - IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_19_ETC___d23807, - IF_rob_deqPort_1_canDeq__3987_THEN_IF_NOT_rob__ETC___d24229, + IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_19_ETC___d23512, + IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_19_ETC___d23558, + IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_19_ETC___d23651, + IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_19_ETC___d23695, + IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_19_ETC___d23809, + IF_rob_deqPort_1_canDeq__3989_THEN_IF_NOT_rob__ETC___d24231, IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d19009, IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d19109, IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d19122, @@ -6595,25 +6598,30 @@ module mkCore(CLK, NOT_IF_IF_NOT_csrf_prv_reg_read__0574_EQ_3_057_ETC___d21356, NOT_IF_IF_NOT_csrf_prv_reg_read__0574_EQ_3_057_ETC___d21473, NOT_IF_IF_NOT_csrf_prv_reg_read__0574_EQ_3_057_ETC___d21930, - NOT_IF_NOT_rob_deqPort_0_canDeq__3983_3984_OR__ETC___d24234, + NOT_IF_NOT_rob_deqPort_0_canDeq__3985_3986_OR__ETC___d24236, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d12813, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d13543, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d14313, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15022, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15064, + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15108, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15122, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15133, + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15144, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15162, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15177, + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15192, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15208, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15221, + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15234, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15250, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15263, - NOT_IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN__ETC___d23691, - NOT_IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN__ETC___d23554, + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15276, + NOT_IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN__ETC___d23693, + NOT_IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN__ETC___d23556, NOT_commitStage_commitTrap_2639_BITS_44_TO_43__ETC___d22910, NOT_commitStage_commitTrap_2639_BITS_44_TO_43__ETC___d22911, - NOT_commitStage_rg_run_state_2637_2638_AND_NOT_ETC___d23408, + NOT_commitStage_rg_run_state_2637_2638_AND_NOT_ETC___d23410, NOT_coreFix_aluExe_0_bypassWire_0_whas__8635_8_ETC___d18662, NOT_coreFix_aluExe_0_bypassWire_0_whas__8635_8_ETC___d18694, NOT_coreFix_aluExe_0_dispToRegQ_first__8612_BI_ETC___d18720, @@ -6667,10 +6675,10 @@ module mkCore(CLK, NOT_csrf_fs_reg_read__6201_EQ_0_0928_0929_OR_N_ETC___d21354, NOT_csrf_fs_reg_read__6201_EQ_0_0928_0929_OR_N_ETC___d21471, NOT_csrf_fs_reg_read__6201_EQ_0_0928_0929_OR_N_ETC___d21928, - NOT_csrf_mtcc_reg_read__6389_BITS_33_TO_28_640_ETC___d23186, - NOT_csrf_prv_reg_read__0574_ULE_1_2990_3105_OR_ETC___d23110, - NOT_csrf_rg_dpc_read__6534_BITS_33_TO_28_6551__ETC___d23804, - NOT_csrf_stcc_reg_read__6237_BITS_33_TO_28_625_ETC___d23115, + NOT_csrf_mtcc_reg_read__6389_BITS_33_TO_28_640_ETC___d23188, + NOT_csrf_prv_reg_read__0574_ULE_1_2990_3106_OR_ETC___d23112, + NOT_csrf_rg_dpc_read__6534_BITS_33_TO_28_6551__ETC___d23806, + NOT_csrf_stcc_reg_read__6237_BITS_33_TO_28_625_ETC___d23117, NOT_fetchStage_pipelines_0_canDeq__0542_0543_O_ETC___d21582, NOT_fetchStage_pipelines_0_canDeq__0542_0543_O_ETC___d22022, NOT_fetchStage_pipelines_0_canDeq__0542_0543_O_ETC___d22091, @@ -6712,10 +6720,10 @@ module mkCore(CLK, NOT_renameStage_rg_m_halt_req_0571_BIT_4_0572__ETC___d21478, NOT_renameStage_rg_m_halt_req_0571_BIT_4_0572__ETC___d22088, NOT_renameStage_rg_m_halt_req_0571_BIT_4_0572__ETC___d22108, - NOT_rob_deqPort_0_canDeq__3983_3984_OR_rob_RDY_ETC___d24024, - NOT_rob_deqPort_0_canDeq__3983_3984_OR_rob_deq_ETC___d24208, - NOT_rob_deqPort_0_deq_data__2632_BITS_469_TO_4_ETC___d23398, - NOT_rob_deqPort_1_deq_data__3990_BIT_25_3991_3_ETC___d24021, + NOT_rob_deqPort_0_canDeq__3985_3986_OR_regRena_ETC___d24026, + NOT_rob_deqPort_0_canDeq__3985_3986_OR_rob_deq_ETC___d24210, + NOT_rob_deqPort_0_deq_data__2632_BITS_469_TO_4_ETC___d23400, + NOT_rob_deqPort_1_deq_data__3992_BIT_25_3993_3_ETC___d24023, NOT_specTagManager_canClaim__1454_1547_OR_NOT__ETC___d22220, NOT_specTagManager_canClaim__1454_1547_OR_NOT__ETC___d22289, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12904, @@ -6751,15 +6759,15 @@ module mkCore(CLK, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d11881, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d8694, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d9087, - _0_CONCAT_csrf_mtcc_reg_read__6389_BITS_149_TO__ETC___d23208, - _0_CONCAT_csrf_mtcc_reg_read__6389_BITS_149_TO__ETC___d23233, - _0_CONCAT_csrf_stcc_reg_read__6237_BITS_149_TO__ETC___d23139, - _0_CONCAT_csrf_stcc_reg_read__6237_BITS_149_TO__ETC___d23164, + _0_CONCAT_csrf_mtcc_reg_read__6389_BITS_149_TO__ETC___d23210, + _0_CONCAT_csrf_mtcc_reg_read__6389_BITS_149_TO__ETC___d23235, + _0_CONCAT_csrf_stcc_reg_read__6237_BITS_149_TO__ETC___d23141, + _0_CONCAT_csrf_stcc_reg_read__6237_BITS_149_TO__ETC___d23166, _0_OR_NOT_fetchStage_pipelines_0_first__0544_BI_ETC___d22140, _0_OR_NOT_fetchStage_pipelines_1_first__0553_BI_ETC___d22038, _0_OR_NOT_fetchStage_pipelines_1_first__0553_BI_ETC___d22233, _0b0_CONCAT_csrf_medeleg_28_26_reg_read__6352_6_ETC___d23018, - _0b0_CONCAT_csrf_mideleg_11_reg_read__6363_6364_ETC___d23020, + _0b0_CONCAT_csrf_mideleg_11_reg_read__6363_6364_ETC___d23021, _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10800, _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10825, _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10852, @@ -6785,7 +6793,7 @@ module mkCore(CLK, _dfoo16, _dfoo18, _dfoo2, - _dfoo22, + _dfoo20, _dfoo24, _dfoo26, _dfoo28, @@ -6813,12 +6821,12 @@ module mkCore(CLK, _dor1sbAggr$EN_setReady_3_put, _dor1sbCons$EN_setReady_0_put, _dor1sbCons$EN_setReady_1_put, - _theResult_____2__h530570, - _theResult_____2__h537663, - _theResult_____2__h548298, - _theResult_____2__h562131, - _theResult_____2__h565910, - cause_interrupt__h1006051, + _theResult_____2__h530567, + _theResult_____2__h537660, + _theResult_____2__h548295, + _theResult_____2__h562128, + _theResult_____2__h565907, + cause_interrupt__h1006048, commitStage_commitTrap_2639_BITS_44_TO_43_2837_ETC___d22877, commitStage_commitTrap_2639_BITS_44_TO_43_2837_ETC___d22884, commitStage_commitTrap_2639_BITS_44_TO_43_2837_ETC___d22989, @@ -6867,11 +6875,6 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_RDY_first_ETC___d10888, coreFix_fpuMulDivExe_0_mulDivExec_divQ_RDY_enq_ETC___d12684, coreFix_fpuMulDivExe_0_mulDivExec_mulQ_RDY_fir_ETC___d12285, - coreFix_fpuMulDivExe_0_regToExeQ_first__2628_B_ETC___d15109, - coreFix_fpuMulDivExe_0_regToExeQ_first__2628_B_ETC___d15145, - coreFix_fpuMulDivExe_0_regToExeQ_first__2628_B_ETC___d15193, - coreFix_fpuMulDivExe_0_regToExeQ_first__2628_B_ETC___d15235, - coreFix_fpuMulDivExe_0_regToExeQ_first__2628_B_ETC___d15277, coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__21_ETC___d22240, coreFix_memExe_bypassWire_0_wget__717_BITS_169_ETC___d2719, coreFix_memExe_bypassWire_0_wget__717_BITS_169_ETC___d2761, @@ -7216,9 +7219,9 @@ module mkCore(CLK, coreFix_memExe_regToExeQ_first__664_BITS_259_T_ETC___d4129, coreFix_memExe_regToExeQ_first__664_BITS_265_T_ETC___d3736, coreFix_memExe_regToExeQ_first__664_BITS_383_T_ETC___d4132, - coreFix_memExe_stb_isEmpty__188_AND_coreFix_me_ETC___d23403, - cr_flags__h873168, - cr_flags__h914209, + coreFix_memExe_stb_isEmpty__188_AND_coreFix_me_ETC___d23405, + cr_flags__h873166, + cr_flags__h914206, csrf_ddc_reg_read__078_BITS_13_TO_11_159_ULT_c_ETC___d4163, csrf_ddc_reg_read__078_BITS_27_TO_25_161_ULT_c_ETC___d4162, csrf_ddc_reg_read__078_BITS_85_TO_83_164_ULT_c_ETC___d4165, @@ -7226,23 +7229,23 @@ module mkCore(CLK, csrf_fs_reg_read__6201_EQ_0_0928_AND_fetchStag_ETC___d21557, csrf_fs_reg_read__6201_EQ_0_0928_AND_fetchStag_ETC___d21999, csrf_mtcc_reg_read__6389_BITS_13_TO_11_6392_UL_ETC___d16394, - csrf_mtcc_reg_read__6389_BITS_149_TO_86_3187_A_ETC___d23197, - csrf_mtcc_reg_read__6389_BITS_149_TO_86_3187_A_ETC___d23225, + csrf_mtcc_reg_read__6389_BITS_149_TO_86_3189_A_ETC___d23199, + csrf_mtcc_reg_read__6389_BITS_149_TO_86_3189_A_ETC___d23227, csrf_mtcc_reg_read__6389_BITS_85_TO_83_6395_UL_ETC___d16396, - csrf_prv_reg_read__0574_ULE_1_2990_AND_IF_comm_ETC___d23023, + csrf_prv_reg_read__0574_ULE_1_2990_AND_IF_comm_ETC___d23024, csrf_prv_reg_read__0574_ULE_1___d22990, csrf_rg_dpc_read__6534_BITS_13_TO_11_6537_ULT__ETC___d16539, csrf_rg_dpc_read__6534_BITS_85_TO_83_6540_ULT__ETC___d16541, csrf_stcc_reg_read__6237_BITS_13_TO_11_6240_UL_ETC___d16242, - csrf_stcc_reg_read__6237_BITS_149_TO_86_3116_A_ETC___d23128, - csrf_stcc_reg_read__6237_BITS_149_TO_86_3116_A_ETC___d23156, + csrf_stcc_reg_read__6237_BITS_149_TO_86_3118_A_ETC___d23130, + csrf_stcc_reg_read__6237_BITS_149_TO_86_3118_A_ETC___d23158, csrf_stcc_reg_read__6237_BITS_85_TO_83_6243_UL_ETC___d16244, - f_csr_reqs_first__4359_BITS_63_TO_14_4512_XOR__ETC___d24526, - f_csr_reqs_first__4359_BITS_63_TO_14_4512_XOR__ETC___d24548, - f_csr_reqs_first__4359_BITS_63_TO_14_4512_XOR__ETC___d24606, - f_csr_reqs_first__4359_BITS_63_TO_14_4512_XOR__ETC___d24626, - f_csr_reqs_first__4359_BITS_63_TO_14_4512_XOR__ETC___d24697, - f_csr_rsps_i_notFull__4357_AND_f_csr_reqs_firs_ETC___d24462, + f_csr_reqs_first__4361_BITS_63_TO_14_4514_XOR__ETC___d24528, + f_csr_reqs_first__4361_BITS_63_TO_14_4514_XOR__ETC___d24550, + f_csr_reqs_first__4361_BITS_63_TO_14_4514_XOR__ETC___d24608, + f_csr_reqs_first__4361_BITS_63_TO_14_4514_XOR__ETC___d24628, + f_csr_reqs_first__4361_BITS_63_TO_14_4514_XOR__ETC___d24699, + f_csr_rsps_i_notFull__4359_AND_f_csr_reqs_firs_ETC___d24464, fetchStage_RDY_pipelines_0_first__0541_AND_fet_ETC___d21553, fetchStage_RDY_pipelines_1_deq__0556_AND_NOT_f_ETC___d22293, fetchStage_pipelines_0_canDeq__0542_AND_NOT_fe_ETC___d22231, @@ -7269,29 +7272,29 @@ module mkCore(CLK, fetchStage_pipelines_0_first__0544_BIT_69_0573_ETC___d22044, fetchStage_pipelines_1_first__0553_BITS_268_TO_ETC___d22187, fetchStage_pipelines_1_first__0553_BITS_273_TO_ETC___d22198, - guard__h599126, - guard__h644875, - guard__h690622, - guard__h741169, - guard__h780022, - guard__h819326, - idx__h978724, - k__h954121, + guard__h599123, + guard__h644872, + guard__h690619, + guard__h741165, + guard__h780018, + guard__h819322, + idx__h978721, + k__h954118, mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d20967, mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d21359, mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d21379, mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d22307, mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d22309, - next_deqP___1__h530815, - next_deqP___1__h538093, - next_deqP___1__h548728, - next_deqP___1__h562376, - next_deqP___1__h566155, - r1__read_BIT_20___h935714, - r__h859554, - r__h861998, - regRenamingTable_RDY_rename_0_claimRename__131_ETC___d21327, - regRenamingTable_RDY_rename_0_getRename__1315__ETC___d22153, + next_deqP___1__h530812, + next_deqP___1__h538090, + next_deqP___1__h548725, + next_deqP___1__h562373, + next_deqP___1__h566152, + r1__read_BIT_20___h935711, + r__h859552, + r__h861996, + regRenamingTable_RDY_rename_0_getRename__1316__ETC___d21327, + regRenamingTable_RDY_rename_0_getRename__1316__ETC___d22153, regRenamingTable_rename_0_canRename__1456_AND__ETC___d21480, regRenamingTable_rename_0_canRename__1456_AND__ETC___d21544, regRenamingTable_rename_0_canRename__1456_AND__ETC___d21548, @@ -7336,22 +7339,23 @@ module mkCore(CLK, rf_read_3_rd2_coreFix_memExe_dispToRegQ_first__ETC___d3611, rf_read_3_rd2_coreFix_memExe_dispToRegQ_first__ETC___d3619, rf_read_3_rd2_coreFix_memExe_dispToRegQ_first__ETC___d3628, - rg_core_run_state_read__0970_EQ_2_0971_AND_NOT_ETC___d24283, + rg_core_run_state_read__0970_EQ_2_0971_AND_NOT_ETC___d24285, rob_enqPort_1_canEnq__1933_AND_epochManager_ch_ETC___d21938, - v__h521269, - v__h521649, - v__h536988, - v__h537183, - v__h539437, - v__h539632, - v__h560457, - v__h560652, - v__h564236, - v__h564431, - x__h243034, - x__h244191, - x__h257812, - x__h841241; + v__h521266, + v__h521646, + v__h536985, + v__h537180, + v__h539434, + v__h539629, + v__h560454, + v__h560649, + v__h564233, + v__h564428, + value_BIT_23___h810070, + x__h243031, + x__h244188, + x__h257809, + x__h841237; // action method coreReq_start assign RDY_coreReq_start = !renameStage_rg_m_halt_req[4] ; @@ -7389,10 +7393,10 @@ module mkCore(CLK, // value method dCacheToParent_rsToP_first assign dCacheToParent_rsToP_first = - { CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q311, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q312, - !CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q313, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d24838 } ; + { CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q313, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q314, + !CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q315, + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d24840 } ; assign RDY_dCacheToParent_rsToP_first = !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty ; @@ -7410,9 +7414,9 @@ module mkCore(CLK, // value method dCacheToParent_rqToP_first assign dCacheToParent_rqToP_first = - { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q320, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q321, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d24864 } ; + { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q322, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q323, + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d24866 } ; assign RDY_dCacheToParent_rqToP_first = !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty ; @@ -9274,32 +9278,32 @@ module mkCore(CLK, // rule RL_sendDTlbReq assign CAN_FIRE_RL_sendDTlbReq = - coreFix_memExe_dTlb$RDY_toParent_rqToP_deq && coreFix_memExe_dTlb$RDY_toParent_rqToP_first && + coreFix_memExe_dTlb$RDY_toParent_rqToP_deq && l2Tlb$RDY_toChildren_rqFromC_put ; assign WILL_FIRE_RL_sendDTlbReq = CAN_FIRE_RL_sendDTlbReq ; // rule RL_sendITlbReq assign CAN_FIRE_RL_sendITlbReq = - fetchStage$RDY_iTlbIfc_toParent_rqToP_deq && + l2Tlb$RDY_toChildren_rqFromC_put && fetchStage$RDY_iTlbIfc_toParent_rqToP_first && - l2Tlb$RDY_toChildren_rqFromC_put ; + fetchStage$RDY_iTlbIfc_toParent_rqToP_deq ; assign WILL_FIRE_RL_sendITlbReq = CAN_FIRE_RL_sendITlbReq && !WILL_FIRE_RL_sendDTlbReq ; // rule RL_sendRsToDTlb assign CAN_FIRE_RL_sendRsToDTlb = - l2Tlb$RDY_toChildren_rsToC_deq && l2Tlb$RDY_toChildren_rsToC_first && + l2Tlb$RDY_toChildren_rsToC_deq && coreFix_memExe_dTlb$RDY_toParent_ldTransRsFromP_enq && l2Tlb$toChildren_rsToC_first[83] ; assign WILL_FIRE_RL_sendRsToDTlb = CAN_FIRE_RL_sendRsToDTlb ; // rule RL_sendRsToITlb assign CAN_FIRE_RL_sendRsToITlb = - fetchStage$RDY_iTlbIfc_toParent_rsFromP_enq && - l2Tlb$RDY_toChildren_rsToC_deq && l2Tlb$RDY_toChildren_rsToC_first && + l2Tlb$RDY_toChildren_rsToC_deq && + fetchStage$RDY_iTlbIfc_toParent_rsFromP_enq && !l2Tlb$toChildren_rsToC_first[83] ; assign WILL_FIRE_RL_sendRsToITlb = CAN_FIRE_RL_sendRsToITlb ; @@ -9311,16 +9315,16 @@ module mkCore(CLK, // rule RL_mkConnectionGetPut_1 assign CAN_FIRE_RL_mkConnectionGetPut_1 = - fetchStage$RDY_iTlbIfc_toParent_flush_request_get && - l2Tlb$RDY_toChildren_iTlbReqFlush_put ; + l2Tlb$RDY_toChildren_iTlbReqFlush_put && + fetchStage$RDY_iTlbIfc_toParent_flush_request_get ; assign WILL_FIRE_RL_mkConnectionGetPut_1 = CAN_FIRE_RL_mkConnectionGetPut_1 ; // rule RL_sendFlushDone assign CAN_FIRE_RL_sendFlushDone = - fetchStage$RDY_iTlbIfc_toParent_flush_response_put && coreFix_memExe_dTlb$RDY_toParent_flush_response_put && - l2Tlb$RDY_toChildren_flushDone_get ; + l2Tlb$RDY_toChildren_flushDone_get && + fetchStage$RDY_iTlbIfc_toParent_flush_response_put ; assign WILL_FIRE_RL_sendFlushDone = CAN_FIRE_RL_sendFlushDone ; // rule RL_sendRobEnqTime @@ -9341,7 +9345,7 @@ module mkCore(CLK, // rule RL_readyToFetch assign CAN_FIRE_RL_readyToFetch = fetchStage$RDY_done_flushing && - rg_core_run_state_read__0970_EQ_2_0971_AND_NOT_ETC___d24283 && + rg_core_run_state_read__0970_EQ_2_0971_AND_NOT_ETC___d24285 && !flush_brpred && fetchStage$iMemIfc_flush_done && fetchStage$flush_predictors_done ; @@ -9470,9 +9474,9 @@ module mkCore(CLK, // rule RL_mmio_sendInstReq assign CAN_FIRE_RL_mmio_sendInstReq = - !mmio_cRqQ_full && fetchStage$RDY_mmioIfc_instReq_deq && + !mmio_cRqQ_full && fetchStage$RDY_mmioIfc_instReq_first_snd && fetchStage$RDY_mmioIfc_instReq_first_fst && - fetchStage$RDY_mmioIfc_instReq_first_snd ; + fetchStage$RDY_mmioIfc_instReq_deq ; assign WILL_FIRE_RL_mmio_sendInstReq = CAN_FIRE_RL_mmio_sendInstReq && !WILL_FIRE_RL_mmio_sendDataReq ; @@ -9553,16 +9557,16 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doDeqLdQ_fault assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_fault = - rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_firstLd && - coreFix_memExe_lsq$RDY_deqLd && + rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_deqLd && + coreFix_memExe_lsq$RDY_firstLd && coreFix_memExe_lsq$firstLd[16] ; assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault = CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ; // rule RL_coreFix_memExe_doDeqLdQ_Ld_Mem assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem = - rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_firstLd && - coreFix_memExe_lsq$RDY_deqLd && + rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_deqLd && + coreFix_memExe_lsq$RDY_firstLd && !coreFix_memExe_lsq$firstLd[16] && !coreFix_memExe_lsq$firstLd[126] && !coreFix_memExe_lsq$firstLd[33] ; @@ -9802,7 +9806,7 @@ module mkCore(CLK, // rule RL_commitStage_doCommitTrap_flush assign CAN_FIRE_RL_commitStage_doCommitTrap_flush = - rob$RDY_deqPort_0_deq && rob$RDY_deqPort_0_deq_data && + rob$RDY_deqPort_0_deq_data && rob$RDY_deqPort_0_deq && (rob$deqPort_0_deq_data[12] || epochManager$RDY_incrementEpoch) && !commitStage_rg_run_state && @@ -9855,15 +9859,15 @@ module mkCore(CLK, // rule RL_rl_debug_csr_write assign CAN_FIRE_RL_rl_debug_csr_write = f_csr_reqs$EMPTY_N && - f_csr_rsps_i_notFull__4357_AND_f_csr_reqs_firs_ETC___d24462 && + f_csr_rsps_i_notFull__4359_AND_f_csr_reqs_firs_ETC___d24464 && rg_core_run_state == 2'd1 && f_csr_reqs$D_OUT[76] ; assign WILL_FIRE_RL_rl_debug_csr_write = CAN_FIRE_RL_rl_debug_csr_write ; // rule RL_commitStage_doCommitKilledLd assign CAN_FIRE_RL_commitStage_doCommitKilledLd = - rob$RDY_deqPort_0_deq && rob$RDY_deqPort_0_deq_data && - epochManager$RDY_incrementEpoch && + epochManager$RDY_incrementEpoch && rob$RDY_deqPort_0_deq_data && + rob$RDY_deqPort_0_deq && !commitStage_rg_run_state && !commitStage_commitTrap[238] && !rob$deqPort_0_deq_data[274] && @@ -9893,8 +9897,8 @@ module mkCore(CLK, // rule RL_commitStage_doCommitSystemInst assign CAN_FIRE_RL_commitStage_doCommitSystemInst = - coreFix_memExe_stb_isEmpty__188_AND_coreFix_me_ETC___d23403 && - NOT_commitStage_rg_run_state_2637_2638_AND_NOT_ETC___d23408 && + coreFix_memExe_stb_isEmpty__188_AND_coreFix_me_ETC___d23405 && + NOT_commitStage_rg_run_state_2637_2638_AND_NOT_ETC___d23410 && (rob$deqPort_0_deq_data[469:465] == 5'd0 || rob$deqPort_0_deq_data[469:465] == 5'd26 || rob$deqPort_0_deq_data[469:465] == 5'd22 || @@ -9937,8 +9941,8 @@ module mkCore(CLK, // rule RL_commitStage_doCommitNormalInst assign CAN_FIRE_RL_commitStage_doCommitNormalInst = rob$RDY_deqPort_0_deq_data && - NOT_rob_deqPort_0_canDeq__3983_3984_OR_rob_RDY_ETC___d24024 && - NOT_commitStage_rg_run_state_2637_2638_AND_NOT_ETC___d23408 && + NOT_rob_deqPort_0_canDeq__3985_3986_OR_regRena_ETC___d24026 && + NOT_commitStage_rg_run_state_2637_2638_AND_NOT_ETC___d23410 && rob$deqPort_0_deq_data[469:465] != 5'd0 && rob$deqPort_0_deq_data[469:465] != 5'd26 && rob$deqPort_0_deq_data[469:465] != 5'd22 && @@ -10096,8 +10100,8 @@ module mkCore(CLK, // rule RL_coreFix_aluExe_0_doDispatchAlu assign CAN_FIRE_RL_coreFix_aluExe_0_doDispatchAlu = coreFix_aluExe_0_dispToRegQ$RDY_enq && - coreFix_aluExe_0_rsAlu$RDY_dispatchData && - coreFix_aluExe_0_rsAlu$RDY_doDispatch ; + coreFix_aluExe_0_rsAlu$RDY_doDispatch && + coreFix_aluExe_0_rsAlu$RDY_dispatchData ; assign WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu = CAN_FIRE_RL_coreFix_aluExe_0_doDispatchAlu && !WILL_FIRE_RL_commitStage_doCommitKilledLd && @@ -10108,8 +10112,8 @@ module mkCore(CLK, // rule RL_coreFix_aluExe_1_doDispatchAlu assign CAN_FIRE_RL_coreFix_aluExe_1_doDispatchAlu = coreFix_aluExe_1_dispToRegQ$RDY_enq && - coreFix_aluExe_1_rsAlu$RDY_dispatchData && - coreFix_aluExe_1_rsAlu$RDY_doDispatch ; + coreFix_aluExe_1_rsAlu$RDY_doDispatch && + coreFix_aluExe_1_rsAlu$RDY_dispatchData ; assign WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu = CAN_FIRE_RL_coreFix_aluExe_1_doDispatchAlu && !WILL_FIRE_RL_commitStage_doCommitKilledLd && @@ -10121,8 +10125,8 @@ module mkCore(CLK, assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq = !coreFix_memExe_respLrScAmoQ_empty && rob$RDY_setExecuted_deqLSQ && - coreFix_memExe_lsq$RDY_firstLd && coreFix_memExe_lsq$RDY_deqLd && + coreFix_memExe_lsq$RDY_firstLd && coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd1 ; assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq = CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && @@ -10146,8 +10150,8 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doFinishMem assign CAN_FIRE_RL_coreFix_memExe_doFinishMem = rob$RDY_setExecuted_doFinishMem && - coreFix_memExe_dTlb$RDY_procResp && - coreFix_memExe_dTlb$RDY_deqProcResp ; + coreFix_memExe_dTlb$RDY_deqProcResp && + coreFix_memExe_dTlb$RDY_procResp ; assign WILL_FIRE_RL_coreFix_memExe_doFinishMem = CAN_FIRE_RL_coreFix_memExe_doFinishMem ; @@ -10340,8 +10344,8 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doDeqStQ_fault assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_fault = - rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_firstSt && - coreFix_memExe_lsq$RDY_deqSt && + rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_deqSt && + coreFix_memExe_lsq$RDY_firstSt && coreFix_memExe_lsq$firstSt[13] ; assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault = CAN_FIRE_RL_coreFix_memExe_doDeqStQ_fault && @@ -10363,8 +10367,8 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doDeqStQ_Fence assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_Fence = - rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_firstSt && - coreFix_memExe_lsq$RDY_deqSt && + rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_deqSt && + coreFix_memExe_lsq$RDY_firstSt && !coreFix_memExe_lsq$firstSt[13] && coreFix_memExe_lsq$firstSt[240:239] == 2'd3 && (!coreFix_memExe_lsq$firstSt[233] || @@ -10391,8 +10395,8 @@ module mkCore(CLK, assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq = !coreFix_memExe_respLrScAmoQ_empty && rob$RDY_setExecuted_deqLSQ && - coreFix_memExe_lsq$RDY_firstSt && coreFix_memExe_lsq$RDY_deqSt && + coreFix_memExe_lsq$RDY_firstSt && coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd2 ; assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq = CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && @@ -10567,8 +10571,8 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doDeqStQ_St_Mem assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem = - coreFix_memExe_stb$RDY_enq && coreFix_memExe_lsq$RDY_firstSt && - coreFix_memExe_lsq$RDY_deqSt && + coreFix_memExe_stb$RDY_enq && coreFix_memExe_lsq$RDY_deqSt && + coreFix_memExe_lsq$RDY_firstSt && !coreFix_memExe_lsq$firstSt[13] && coreFix_memExe_lsq$firstSt[240:239] == 2'd0 && !coreFix_memExe_lsq$firstSt[159] && @@ -10594,16 +10598,16 @@ module mkCore(CLK, // rule RL_prepareCachesAndTlbs assign CAN_FIRE_RL_prepareCachesAndTlbs = (!flush_tlbs || - fetchStage$RDY_iTlbIfc_flush && - coreFix_memExe_dTlb$RDY_flush) && + coreFix_memExe_dTlb$RDY_flush && + fetchStage$RDY_iTlbIfc_flush) && (flush_reservation || flush_tlbs || update_vm_info) ; assign WILL_FIRE_RL_prepareCachesAndTlbs = CAN_FIRE_RL_prepareCachesAndTlbs ; // rule RL_rl_debug_resume assign CAN_FIRE_RL_rl_debug_resume = - commitStage_rg_run_state && fetchStage$RDY_iTlbIfc_flush && - coreFix_memExe_dTlb$RDY_flush && + commitStage_rg_run_state && coreFix_memExe_dTlb$RDY_flush && + fetchStage$RDY_iTlbIfc_flush && f_run_halt_reqs$EMPTY_N && f_run_halt_rsps$FULL_N && rg_core_run_state == 2'd1 && @@ -10611,9 +10615,7 @@ module mkCore(CLK, !f_gpr_reqs$EMPTY_N && !f_fpr_reqs$EMPTY_N && !f_csr_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_debug_resume = - CAN_FIRE_RL_rl_debug_resume && - !WILL_FIRE_RL_prepareCachesAndTlbs ; + assign WILL_FIRE_RL_rl_debug_resume = MUX_started$write_1__SEL_1 ; // rule RL_coreFix_memExe_doRegReadMem assign CAN_FIRE_RL_coreFix_memExe_doRegReadMem = @@ -10629,8 +10631,8 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doDispatchMem assign CAN_FIRE_RL_coreFix_memExe_doDispatchMem = coreFix_memExe_dispToRegQ$RDY_enq && - coreFix_memExe_rsMem$RDY_dispatchData && - coreFix_memExe_rsMem$RDY_doDispatch ; + coreFix_memExe_rsMem$RDY_doDispatch && + coreFix_memExe_rsMem$RDY_dispatchData ; assign WILL_FIRE_RL_coreFix_memExe_doDispatchMem = CAN_FIRE_RL_coreFix_memExe_doDispatchMem && !WILL_FIRE_RL_commitStage_doCommitKilledLd && @@ -10643,7 +10645,7 @@ module mkCore(CLK, !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty && coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_send && coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_getEmptyEntryInit && - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q322 ; + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q324 ; assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer = CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer ; @@ -10672,7 +10674,7 @@ module mkCore(CLK, assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer = !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty && coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_send && - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q323 ; + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q325 ; assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer = CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer ; @@ -10847,8 +10849,8 @@ module mkCore(CLK, // rule RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv = coreFix_fpuMulDivExe_0_dispToRegQ$RDY_enq && - coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_dispatchData && - coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_doDispatch ; + coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_doDispatch && + coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_dispatchData ; assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv = CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv && !WILL_FIRE_RL_commitStage_doCommitKilledLd && @@ -10892,9 +10894,9 @@ module mkCore(CLK, // rule RL_renameStage_doRenaming_Trap assign CAN_FIRE_RL_renameStage_doRenaming_Trap = - rob$RDY_enqPort_0_enq && fetchStage$RDY_pipelines_0_deq && + epochManager$RDY_incrementEpoch && rob$RDY_enqPort_0_enq && fetchStage$RDY_pipelines_0_first && - epochManager$RDY_incrementEpoch && + fetchStage$RDY_pipelines_0_deq && mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d20967 && rob$isEmpty && rg_core_run_state == 2'd2 ; @@ -10907,9 +10909,9 @@ module mkCore(CLK, // rule RL_renameStage_doRenaming_SystemInst assign CAN_FIRE_RL_renameStage_doRenaming_SystemInst = - rob$RDY_enqPort_0_enq && - regRenamingTable$RDY_rename_0_getRename && - regRenamingTable_RDY_rename_0_claimRename__131_ETC___d21327 && + epochManager$RDY_incrementEpoch && + regRenamingTable$RDY_rename_0_claimRename && + regRenamingTable_RDY_rename_0_getRename__1316__ETC___d21327 && mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d21379 && rg_core_run_state == 2'd2 ; assign WILL_FIRE_RL_renameStage_doRenaming_SystemInst = @@ -11010,10 +11012,7 @@ module mkCore(CLK, WILL_FIRE_RL_commitStage_doCommitKilledLd || WILL_FIRE_RL_commitStage_doCommitTrap_flush ; assign MUX_coreFix_aluExe_0_rsAlu$enq_1__SEL_1 = - WILL_FIRE_RL_renameStage_doRenaming_SystemInst && - (fetchStage$pipelines_0_first[268:266] == 3'd0 || - fetchStage$pipelines_0_first[238:237] == 2'd1 || - fetchStage$pipelines_0_first[238:237] == 2'd0) ; + WILL_FIRE_RL_renameStage_doRenaming && _dfoo18 ; assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple && coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] ; @@ -11178,9 +11177,9 @@ module mkCore(CLK, assign MUX_csrf_external_int_en_vec_1$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - (IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + (IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd9 || - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd23) ; assign MUX_csrf_external_int_en_vec_3$write_1__SEL_1 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11188,9 +11187,9 @@ module mkCore(CLK, assign MUX_csrf_external_int_pend_vec_1$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - (IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + (IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd16 || - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd30) ; assign MUX_csrf_external_int_pend_vec_1$write_1__SEL_2 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11198,13 +11197,13 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd836) ; assign MUX_csrf_fflags_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitNormalInst && - NOT_IF_NOT_rob_deqPort_0_canDeq__3983_3984_OR__ETC___d24234 ; + NOT_IF_NOT_rob_deqPort_0_canDeq__3985_3986_OR__ETC___d24236 ; assign MUX_csrf_fflags_reg$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - (IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + (IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd0 || - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd2) ; assign MUX_csrf_fflags_reg$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11213,22 +11212,22 @@ module mkCore(CLK, assign MUX_csrf_frm_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - (IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + (IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd1 || - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd2) ; assign MUX_csrf_fs_reg$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - (IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + (IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd0 || - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd1 || - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd2 || - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd8 || - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd19) ; assign MUX_csrf_fs_reg$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11240,9 +11239,9 @@ module mkCore(CLK, assign MUX_csrf_ie_vec_0$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - (IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + (IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd8 || - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd19) ; assign MUX_csrf_ie_vec_0$write_1__SEL_2 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11253,7 +11252,7 @@ module mkCore(CLK, assign MUX_csrf_ie_vec_1$write_1__SEL_3 = WILL_FIRE_RL_commitStage_doCommitTrap_handle && commitStage_commitTrap_2639_BITS_44_TO_43_2837_ETC___d22989 && - csrf_prv_reg_read__0574_ULE_1_2990_AND_IF_comm_ETC___d23023 ; + csrf_prv_reg_read__0574_ULE_1_2990_AND_IF_comm_ETC___d23024 ; assign MUX_csrf_ie_vec_3$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo30 ; assign MUX_csrf_ie_vec_3$write_1__SEL_2 = @@ -11262,11 +11261,11 @@ module mkCore(CLK, assign MUX_csrf_ie_vec_3$write_1__SEL_3 = WILL_FIRE_RL_commitStage_doCommitTrap_handle && commitStage_commitTrap_2639_BITS_44_TO_43_2837_ETC___d22989 && - NOT_csrf_prv_reg_read__0574_ULE_1_2990_3105_OR_ETC___d23110 ; + NOT_csrf_prv_reg_read__0574_ULE_1_2990_3106_OR_ETC___d23112 ; assign MUX_csrf_mcause_code_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd28 ; assign MUX_csrf_mcause_code_reg$write_1__SEL_2 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11284,8 +11283,7 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd770 ; assign MUX_csrf_mepcc_reg_data_lat_1$wset_1__SEL_1 = - WILL_FIRE_RL_rl_debug_csr_write && - f_csr_reqs$D_OUT[75:64] == 12'd833 ; + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; assign MUX_csrf_mideleg_11_reg$write_1__SEL_1 = WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd771 ; @@ -11298,12 +11296,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd832 ; assign MUX_csrf_mtcc_reg$write_1__SEL_1 = - WILL_FIRE_RL_rl_debug_csr_write && - f_csr_reqs$D_OUT[75:64] == 12'd773 ; + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 ; assign MUX_csrf_mtval_csr$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd29 ; assign MUX_csrf_mtval_csr$write_1__SEL_2 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11323,12 +11320,12 @@ module mkCore(CLK, assign MUX_csrf_rg_dcsr$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd42 ; assign MUX_csrf_rg_dpc$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd43 ; assign MUX_csrf_rg_dpc$write_1__SEL_2 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11354,7 +11351,7 @@ module mkCore(CLK, assign MUX_csrf_scause_code_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd14 ; assign MUX_csrf_scause_code_reg$write_1__SEL_2 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11363,8 +11360,7 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd262 ; assign MUX_csrf_sepcc_reg_data_lat_1$wset_1__SEL_1 = - WILL_FIRE_RL_rl_debug_csr_write && - f_csr_reqs$D_OUT[75:64] == 12'd321 ; + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo36 ; assign MUX_csrf_spp_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo40 ; assign MUX_csrf_sscratch_csr$write_1__SEL_1 = @@ -11374,12 +11370,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd2049 ; assign MUX_csrf_stcc_reg$write_1__SEL_1 = - WILL_FIRE_RL_rl_debug_csr_write && - f_csr_reqs$D_OUT[75:64] == 12'd261 ; + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo38 ; assign MUX_csrf_stval_csr$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd15 ; assign MUX_csrf_stval_csr$write_1__SEL_2 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11397,7 +11392,7 @@ module mkCore(CLK, assign MUX_f_run_halt_rsps$enq_1__SEL_1 = WILL_FIRE_RL_rl_debug_halted || WILL_FIRE_RL_rl_debug_halt_req_already_halted ; - assign MUX_flush_reservation$write_1__SEL_1 = + assign MUX_flush_reservation$write_1__SEL_2 = WILL_FIRE_RL_prepareCachesAndTlbs && flush_reservation ; assign MUX_flush_tlbs$write_1__SEL_1 = WILL_FIRE_RL_prepareCachesAndTlbs && flush_tlbs ; @@ -11450,6 +11445,9 @@ module mkCore(CLK, coreFix_memExe_lsq$firstLd[106] ; assign MUX_sbCons$setReady_3_put_1__SEL_3 = MUX_rf$write_3_wr_1__PSEL_5 && coreFix_memExe_lsq$respLd[137] ; + assign MUX_started$write_1__SEL_1 = + CAN_FIRE_RL_rl_debug_resume && + !WILL_FIRE_RL_prepareCachesAndTlbs ; assign MUX_regRenamingTable$rename_0_getRename_1__VAL_2 = { 2'd2, f_gpr_reqs$D_OUT[68:64], 20'd345386 } ; assign MUX_regRenamingTable$rename_0_getRename_1__VAL_3 = @@ -11457,25 +11455,15 @@ module mkCore(CLK, assign MUX_commitStage_commitTrap$write_1__VAL_2 = { 1'd1, rob$deqPort_0_deq_data[630:502], - addr__h1000333, - CASE_robdeqPort_0_deq_data_BITS_273_TO_272_0__ETC__q327, + addr__h1000330, + CASE_robdeqPort_0_deq_data_BITS_273_TO_272_0__ETC__q329, rob$deqPort_0_deq_data[501:470] } ; - assign MUX_commitStage_rg_serial_num$write_1__VAL_1 = + assign MUX_commitStage_rg_serial_num$write_1__VAL_2 = commitStage_rg_serial_num + 64'd1 ; assign MUX_commitStage_rg_serial_num$write_1__VAL_3 = - commitStage_rg_serial_num + y__h1027821 ; + commitStage_rg_serial_num + y__h1027855 ; assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_1 = - { fetchStage$pipelines_0_first[273:269], - IF_fetchStage_pipelines_0_first__0544_BITS_268_ETC___d20670, - IF_fetchStage_pipelines_0_first__0544_BITS_238_ETC___d20910, - fetchStage$pipelines_0_first[329:306], - regRenamingTable$rename_0_getRename, - rob$enqPort_0_getEnqInstTag, - specTagManager$currentSpecBits, - 5'd10, - sbAggr$eagerLookup_0_get } ; - assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_2 = - (k__h954121 == 1'd0 && fetchStage$pipelines_0_canDeq && + (k__h954118 == 1'd0 && fetchStage$pipelines_0_canDeq && NOT_fetchStage_pipelines_0_first__0544_BITS_26_ETC___d22314) ? { fetchStage$pipelines_0_first[273:269], IF_fetchStage_pipelines_0_first__0544_BITS_268_ETC___d20670, @@ -11493,10 +11481,20 @@ module mkCore(CLK, fetchStage$pipelines_1_first[329:306], regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h978585, + renaming_spec_bits__h978582, fetchStage$pipelines_1_first[268:266] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; + assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_2 = + { fetchStage$pipelines_0_first[273:269], + IF_fetchStage_pipelines_0_first__0544_BITS_268_ETC___d20670, + IF_fetchStage_pipelines_0_first__0544_BITS_238_ETC___d20910, + fetchStage$pipelines_0_first[329:306], + regRenamingTable$rename_0_getRename, + rob$enqPort_0_getEnqInstTag, + specTagManager$currentSpecBits, + 5'd10, + sbAggr$eagerLookup_0_get } ; assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1 = { 1'd1, coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[31:25] } ; assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2 = @@ -11591,7 +11589,7 @@ module mkCore(CLK, assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_1 = { 521'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq[221:158], - x__h505455 } ; + x__h505453 } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_2 = { 521'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d7124 } ; @@ -11601,7 +11599,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_4 = { 2'd2, - addr__h509973, + addr__h509971, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d7232 } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_1 = { 1'd1, @@ -11618,12 +11616,12 @@ module mkCore(CLK, coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget : coreFix_memExe_reqLrScAmoQ_data_0_rl ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_2 = - { x__h150548, - addr__h149996, + { x__h150547, + addr__h149995, 158'h20AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_3 = - { x__h153682, - addr__h153572, + { x__h153681, + addr__h153571, 158'h32AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_1 = { 1'd1, @@ -11633,7 +11631,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[581:579] } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_1 = { 1'd1, - resp_addr__h513542, + resp_addr__h513540, 2'd0, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getData } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_2 = @@ -11641,8 +11639,8 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getRq, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getData } ; assign MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1 = - { prv__h1028935, - prv__h1028935 != 2'd3 && csrf_vm_mode_sv39_reg, + { prv__h1028969, + prv__h1028969 != 2'd3 && csrf_vm_mode_sv39_reg, csrf_mxr_reg, csrf_sum_reg, csrf_ppn_reg } ; @@ -11667,11 +11665,11 @@ module mkCore(CLK, coreFix_memExe_stb$search[128:0] : 129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; assign MUX_coreFix_memExe_lsq$respLd_2__VAL_1 = - { CASE_coreFix_memExe_memRespLdQ_deqP_0_coreFix__ETC__q328, + { CASE_coreFix_memExe_memRespLdQ_deqP_0_coreFix__ETC__q330, SEL_ARR_coreFix_memExe_memRespLdQ_data_0_140_B_ETC___d2154, SEL_ARR_coreFix_memExe_memRespLdQ_data_0_140_B_ETC___d2158 } ; assign MUX_coreFix_memExe_lsq$respLd_2__VAL_2 = - { CASE_coreFix_memExe_forwardQ_deqP_0_coreFix_me_ETC__q329, + { CASE_coreFix_memExe_forwardQ_deqP_0_coreFix_me_ETC__q331, SEL_ARR_coreFix_memExe_forwardQ_data_0_224_BIT_ETC___d2238, SEL_ARR_coreFix_memExe_forwardQ_data_0_224_BIT_ETC___d2242 } ; assign MUX_coreFix_memExe_memRespLdQ_enqReq_lat_0$wset_1__VAL_1 = @@ -11711,41 +11709,41 @@ module mkCore(CLK, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4874, IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d4911 } ; assign MUX_coreFix_trainBPQ_0$enq_1__VAL_1 = - { x__h923377, - new_pc__h920773, + { x__h923374, + new_pc__h920770, coreFix_aluExe_0_exeToFinQ$first[1066:1062], coreFix_aluExe_0_exeToFinQ$first[297], coreFix_aluExe_0_exeToFinQ$first[1040:1017], 1'd0, coreFix_aluExe_0_exeToFinQ$first[1016] } ; assign MUX_coreFix_trainBPQ_0$enq_1__VAL_2 = - { x__h923377, - new_pc__h920773, + { x__h923374, + new_pc__h920770, coreFix_aluExe_0_exeToFinQ$first[1066:1062], coreFix_aluExe_0_exeToFinQ$first[297], coreFix_aluExe_0_exeToFinQ$first[1040:1017], 1'd1, coreFix_aluExe_0_exeToFinQ$first[1016] } ; assign MUX_coreFix_trainBPQ_1$enq_1__VAL_1 = - { x__h887434, - new_pc__h880399, + { x__h887432, + new_pc__h880397, coreFix_aluExe_1_exeToFinQ$first[1066:1062], coreFix_aluExe_1_exeToFinQ$first[297], coreFix_aluExe_1_exeToFinQ$first[1040:1017], 1'd0, coreFix_aluExe_1_exeToFinQ$first[1016] } ; assign MUX_coreFix_trainBPQ_1$enq_1__VAL_2 = - { x__h887434, - new_pc__h880399, + { x__h887432, + new_pc__h880397, coreFix_aluExe_1_exeToFinQ$first[1066:1062], coreFix_aluExe_1_exeToFinQ$first[297], coreFix_aluExe_1_exeToFinQ$first[1040:1017], 1'd1, coreFix_aluExe_1_exeToFinQ$first[1016] } ; assign MUX_csrf_fflags_reg$write_1__VAL_1 = - csrf_fflags_reg | fflags__h1027798 ; + csrf_fflags_reg | fflags__h1027832 ; assign MUX_csrf_frm_reg$write_1__VAL_1 = - (IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + (IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd1) ? robdeqPort_0_deq_data_BITS_95_TO_32__q16[2:0] : robdeqPort_0_deq_data_BITS_95_TO_32__q16[7:5] ; @@ -11753,10 +11751,10 @@ module mkCore(CLK, (f_csr_reqs$D_OUT[75:64] == 12'd2) ? f_csr_reqs$D_OUT[2:0] : f_csr_reqs$D_OUT[7:5] ; - always@(IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 or + always@(IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 or robdeqPort_0_deq_data_BITS_95_TO_32__q16) begin - case (IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388) + case (IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390) 6'd0, 6'd1, 6'd2: MUX_csrf_fs_reg$write_1__VAL_2 = 2'b11; default: MUX_csrf_fs_reg$write_1__VAL_2 = robdeqPort_0_deq_data_BITS_95_TO_32__q16[14:13]; @@ -11771,163 +11769,163 @@ module mkCore(CLK, end assign MUX_csrf_ie_vec_1$write_1__VAL_1 = (rob$deqPort_0_deq_data[469:465] == 5'd17 && - (IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + (IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd8 || - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd19)) ? robdeqPort_0_deq_data_BITS_95_TO_32__q16[1] : csrf_prev_ie_vec_1 ; assign MUX_csrf_ie_vec_3$write_1__VAL_1 = (rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd19) ? robdeqPort_0_deq_data_BITS_95_TO_32__q16[3] : csrf_prev_ie_vec_3 ; assign MUX_csrf_mccsr_reg$write_1__VAL_1 = { f_csr_reqs$D_OUT[15:10], - CASE_f_csr_reqsD_OUT_BITS_9_TO_5_0_f_csr_reqs_ETC__q330 } ; + CASE_f_csr_reqsD_OUT_BITS_9_TO_5_0_f_csr_reqs_ETC__q332 } ; assign MUX_csrf_mccsr_reg$write_1__VAL_2 = { robdeqPort_0_deq_data_BITS_95_TO_32__q16[15:10], - CASE_robdeqPort_0_deq_data_BITS_95_TO_326_BITS_ETC__q331 } ; + CASE_robdeqPort_0_deq_data_BITS_95_TO_326_BITS_ETC__q333 } ; assign MUX_csrf_mepcc_reg_data_lat_1$wset_1__VAL_1 = - { f_csr_reqs_first__4359_BITS_63_TO_14_4512_XOR__ETC___d24626, - result_d_address__h1044322, - result_d_addrBits__h1044323, - IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d23712 } ; - assign MUX_csrf_mepcc_reg_data_lat_1$wset_1__VAL_2 = (rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd27) ? - { IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_19_ETC___d23693, - result_d_address__h1020754, - result_d_addrBits__h1020755, - IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d23712 } : + { IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_19_ETC___d23695, + result_d_address__h1020788, + result_d_addrBits__h1020789, + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d23714 } : rob$deqPort_0_deq_data[194:42] ; + assign MUX_csrf_mepcc_reg_data_lat_1$wset_1__VAL_2 = + { f_csr_reqs_first__4361_BITS_63_TO_14_4514_XOR__ETC___d24628, + result_d_address__h1044355, + result_d_addrBits__h1044356, + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d23714 } ; assign MUX_csrf_minstret_ehr_data_lat_0$wset_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ; assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1 = - n__read__h1025204 + 64'd1 ; + n__read__h1025238 + 64'd1 ; assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2 = - n__read__h1025204 + { 62'd0, x__h1028046 } ; + n__read__h1025238 + { 62'd0, x__h1028080 } ; assign MUX_csrf_mpp_reg$write_1__VAL_1 = (rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd19) ? MUX_csrf_minstret_ehr_data_lat_0$wset_1__VAL_2[12:11] : 2'd0 ; assign MUX_csrf_mtcc_reg$write_1__VAL_1 = - { f_csr_reqs_first__4359_BITS_63_TO_14_4512_XOR__ETC___d24606, - result_d_address__h1043919, - result_d_addrBits__h1043920, - csrf_mtcc_reg[71:0] } ; - assign MUX_csrf_mtcc_reg$write_1__VAL_2 = (rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd24) ? - { IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_19_ETC___d23649, - result_d_address__h1020351, - result_d_addrBits__h1020352, + { IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_19_ETC___d23651, + result_d_address__h1020385, + result_d_addrBits__h1020386, csrf_mtcc_reg[71:0] } : rob$deqPort_0_deq_data[194:42] ; + assign MUX_csrf_mtcc_reg$write_1__VAL_2 = + { f_csr_reqs_first__4361_BITS_63_TO_14_4514_XOR__ETC___d24608, + result_d_address__h1043952, + result_d_addrBits__h1043953, + csrf_mtcc_reg[71:0] } ; assign MUX_csrf_mtval_csr$write_1__VAL_1 = rob$deqPort_0_deq_data[95:32] ; - always@(commitStage_commitTrap or trap_val__h1007773 or trap_val__h1007620) + always@(commitStage_commitTrap or trap_val__h1007807 or trap_val__h1007654) begin case (commitStage_commitTrap[44:43]) - 2'd0: MUX_csrf_mtval_csr$write_1__VAL_3 = trap_val__h1007773; - 2'd1: MUX_csrf_mtval_csr$write_1__VAL_3 = trap_val__h1007620; + 2'd0: MUX_csrf_mtval_csr$write_1__VAL_3 = trap_val__h1007807; + 2'd1: MUX_csrf_mtval_csr$write_1__VAL_3 = trap_val__h1007654; default: MUX_csrf_mtval_csr$write_1__VAL_3 = 64'd0; endcase end assign MUX_csrf_prev_ie_vec_1$write_1__VAL_1 = rob$deqPort_0_deq_data[469:465] != 5'd17 || - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 != + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 != 6'd8 && - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 != + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 != 6'd19 || MUX_csrf_mtval_csr$write_1__VAL_1[5] ; assign MUX_csrf_prev_ie_vec_3$write_1__VAL_1 = rob$deqPort_0_deq_data[469:465] != 5'd17 || - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 != + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 != 6'd19 || MUX_csrf_mtval_csr$write_1__VAL_1[7] ; assign MUX_csrf_prv_reg$write_1__VAL_1 = (rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd42) ? MUX_csrf_mtval_csr$write_1__VAL_1[1:0] : ((rob$deqPort_0_deq_data[469:465] == 5'd24) ? - x__h1023576 : + x__h1023610 : csrf_mpp_reg) ; assign MUX_csrf_prv_reg$write_1__VAL_3 = - csrf_prv_reg_read__0574_ULE_1_2990_AND_IF_comm_ETC___d23023 ? + csrf_prv_reg_read__0574_ULE_1_2990_AND_IF_comm_ETC___d23024 ? 2'd1 : 2'd3 ; assign MUX_csrf_rg_dcsr$write_1__VAL_1 = rob$deqPort_0_deq_data[95:32] ; assign MUX_csrf_rg_dcsr$write_1__VAL_3 = { 32'b0, csrf_rg_dcsr[31:9], - dcsr_cause__h1005097, + dcsr_cause__h1005094, csrf_rg_dcsr[5:2], csrf_prv_reg } ; assign MUX_csrf_rg_dpc$write_1__VAL_1 = - { IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_19_ETC___d23807, - result_d_address__h1021423, - result_d_addrBits__h1021424, + { IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_19_ETC___d23809, + result_d_address__h1021457, + result_d_addrBits__h1021458, csrf_rg_dpc[71:0] } ; assign MUX_csrf_rg_dpc$write_1__VAL_2 = - { f_csr_reqs_first__4359_BITS_63_TO_14_4512_XOR__ETC___d24697, - result_d_address__h1044989, - result_d_addrBits__h1044990, + { f_csr_reqs_first__4361_BITS_63_TO_14_4514_XOR__ETC___d24699, + result_d_address__h1045022, + result_d_addrBits__h1045023, csrf_rg_dpc[71:0] } ; assign MUX_csrf_rg_dpc$write_1__VAL_3 = { commitStage_commitTrap[237], - pc_address__h1005472, - pc_addrBits__h1005473, + pc_address__h1005469, + pc_addrBits__h1005470, commitStage_commitTrap[236:221], commitStage_commitTrap[218], commitStage_commitTrap[220:219], ~commitStage_commitTrap[217:199], IF_INV_commitStage_commitTrap_2639_BITS_217_TO_ETC___d22956, - x__h1005842, - x__h1005862 } ; - assign MUX_csrf_rg_tdata3$write_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ; + x__h1005839, + x__h1005859 } ; + assign MUX_csrf_rg_tselect$write_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ; assign MUX_csrf_sepcc_reg_data_lat_1$wset_1__VAL_1 = - { f_csr_reqs_first__4359_BITS_63_TO_14_4512_XOR__ETC___d24548, - result_d_address__h1043502, - result_d_addrBits__h1043503, - IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d23575 } ; - assign MUX_csrf_sepcc_reg_data_lat_1$wset_1__VAL_2 = (rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd13) ? - { IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_19_ETC___d23556, - result_d_address__h1019934, - result_d_addrBits__h1019935, - IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d23575 } : + { IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_19_ETC___d23558, + result_d_address__h1019968, + result_d_addrBits__h1019969, + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d23577 } : rob$deqPort_0_deq_data[194:42] ; + assign MUX_csrf_sepcc_reg_data_lat_1$wset_1__VAL_2 = + { f_csr_reqs_first__4361_BITS_63_TO_14_4514_XOR__ETC___d24550, + result_d_address__h1043535, + result_d_addrBits__h1043536, + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d23577 } ; assign MUX_csrf_spp_reg$write_1__VAL_1 = rob$deqPort_0_deq_data[469:465] == 5'd17 && - (IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + (IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd8 || - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd19) && - MUX_csrf_rg_tdata3$write_1__VAL_2[8] ; + MUX_csrf_rg_tselect$write_1__VAL_2[8] ; assign MUX_csrf_stcc_reg$write_1__VAL_1 = - { f_csr_reqs_first__4359_BITS_63_TO_14_4512_XOR__ETC___d24526, - result_d_address__h1043099, - result_d_addrBits__h1043100, - csrf_stcc_reg[71:0] } ; - assign MUX_csrf_stcc_reg$write_1__VAL_2 = (rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd10) ? - { IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_19_ETC___d23510, - result_d_address__h1019531, - result_d_addrBits__h1019532, + { IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_19_ETC___d23512, + result_d_address__h1019565, + result_d_addrBits__h1019566, csrf_stcc_reg[71:0] } : rob$deqPort_0_deq_data[194:42] ; + assign MUX_csrf_stcc_reg$write_1__VAL_2 = + { f_csr_reqs_first__4361_BITS_63_TO_14_4514_XOR__ETC___d24528, + result_d_address__h1043132, + result_d_addrBits__h1043133, + csrf_stcc_reg[71:0] } ; assign MUX_csrf_stval_csr$write_1__VAL_1 = rob$deqPort_0_deq_data[95:32] ; - assign MUX_f_csr_rsps$enq_1__VAL_3 = { 1'd1, data_out__h1031472 } ; + assign MUX_f_csr_rsps$enq_1__VAL_3 = { 1'd1, data_out__h1031505 } ; assign MUX_f_fpr_rsps$enq_1__VAL_3 = { 1'd1, rf$read_4_rd1[149:86] } ; assign MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 = { csrf_prv_reg, @@ -11936,21 +11934,21 @@ module mkCore(CLK, csrf_sum_reg, csrf_ppn_reg } ; assign MUX_fetchStage$redirect_1__VAL_1 = - { IF_csrf_prv_reg_read__0574_ULE_1_2990_AND_IF_c_ETC___d23252[38:19], - ~IF_csrf_prv_reg_read__0574_ULE_1_2990_AND_IF_c_ETC___d23252[18:0], - IF_IF_csrf_prv_reg_read__0574_ULE_1_2990_AND_I_ETC___d23270[25:17], - ~IF_IF_csrf_prv_reg_read__0574_ULE_1_2990_AND_I_ETC___d23270[16:15], - IF_IF_csrf_prv_reg_read__0574_ULE_1_2990_AND_I_ETC___d23270[14:3], - ~IF_IF_csrf_prv_reg_read__0574_ULE_1_2990_AND_I_ETC___d23270[2], - IF_IF_csrf_prv_reg_read__0574_ULE_1_2990_AND_I_ETC___d23270[1:0], - thin_address__h1010115 } ; + { IF_csrf_prv_reg_read__0574_ULE_1_2990_AND_IF_c_ETC___d23254[38:19], + ~IF_csrf_prv_reg_read__0574_ULE_1_2990_AND_IF_c_ETC___d23254[18:0], + IF_IF_csrf_prv_reg_read__0574_ULE_1_2990_AND_I_ETC___d23272[25:17], + ~IF_IF_csrf_prv_reg_read__0574_ULE_1_2990_AND_I_ETC___d23272[16:15], + IF_IF_csrf_prv_reg_read__0574_ULE_1_2990_AND_I_ETC___d23272[14:3], + ~IF_IF_csrf_prv_reg_read__0574_ULE_1_2990_AND_I_ETC___d23272[2], + IF_IF_csrf_prv_reg_read__0574_ULE_1_2990_AND_I_ETC___d23272[1:0], + thin_address__h1010149 } ; always@(rob$deqPort_0_deq_data or - next_pc__h1023233 or v__h1023555 or v__h1024264) + next_pc__h1023267 or v__h1023589 or v__h1024298) begin case (rob$deqPort_0_deq_data[469:465]) - 5'd24: MUX_fetchStage$redirect_1__VAL_5 = v__h1023555; - 5'd25: MUX_fetchStage$redirect_1__VAL_5 = v__h1024264; - default: MUX_fetchStage$redirect_1__VAL_5 = next_pc__h1023233; + 5'd24: MUX_fetchStage$redirect_1__VAL_5 = v__h1023589; + 5'd25: MUX_fetchStage$redirect_1__VAL_5 = v__h1024298; + default: MUX_fetchStage$redirect_1__VAL_5 = next_pc__h1023267; endcase end assign MUX_fetchStage$redirect_1__VAL_6 = @@ -11959,11 +11957,11 @@ module mkCore(CLK, csrf_rg_dpc[54:53], csrf_rg_dpc[55], ~csrf_rg_dpc[52:34], - IF_csrf_rg_dpc_read__6534_BIT_34_4739_THEN_csr_ETC___d24747[25:17], - ~IF_csrf_rg_dpc_read__6534_BIT_34_4739_THEN_csr_ETC___d24747[16:15], - IF_csrf_rg_dpc_read__6534_BIT_34_4739_THEN_csr_ETC___d24747[14:3], - ~IF_csrf_rg_dpc_read__6534_BIT_34_4739_THEN_csr_ETC___d24747[2], - IF_csrf_rg_dpc_read__6534_BIT_34_4739_THEN_csr_ETC___d24747[1:0], + IF_csrf_rg_dpc_read__6534_BIT_34_4741_THEN_csr_ETC___d24749[25:17], + ~IF_csrf_rg_dpc_read__6534_BIT_34_4741_THEN_csr_ETC___d24749[16:15], + IF_csrf_rg_dpc_read__6534_BIT_34_4741_THEN_csr_ETC___d24749[14:3], + ~IF_csrf_rg_dpc_read__6534_BIT_34_4741_THEN_csr_ETC___d24749[2], + IF_csrf_rg_dpc_read__6534_BIT_34_4741_THEN_csr_ETC___d24749[1:0], csrf_rg_dpc[149:86] } ; assign MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_1 = { 1'd1, @@ -11974,7 +11972,7 @@ module mkCore(CLK, assign MUX_mmio_cRqQ_enqReq_lat_0$wset_1__VAL_1 = { 1'd1, mmio_dataReqQ_data_0[214:151], - CASE_mmio_dataReqQ_data_0_BITS_150_TO_149_0_mm_ETC__q332, + CASE_mmio_dataReqQ_data_0_BITS_150_TO_149_0_mm_ETC__q334, mmio_dataReqQ_data_0[144:0] } ; assign MUX_mmio_cRqQ_enqReq_lat_0$wset_1__VAL_2 = { 1'd1, @@ -11997,38 +11995,38 @@ module mkCore(CLK, 112'hAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; assign MUX_rf$write_2_wr_2__VAL_1 = { 1'd0, - res_address__h571771, - res_addrBits__h571772, + res_address__h571767, + res_addrBits__h571768, 72'h00001FFFFF44000000 } ; assign MUX_rf$write_2_wr_2__VAL_2 = { 1'd0, - res_address__h572623, - res_addrBits__h572624, + res_address__h572620, + res_addrBits__h572621, 72'h00001FFFFF44000000 } ; assign MUX_rf$write_2_wr_2__VAL_3 = { 1'd0, - res_address__h618380, - res_addrBits__h618381, + res_address__h618377, + res_addrBits__h618378, 72'h00001FFFFF44000000 } ; assign MUX_rf$write_2_wr_2__VAL_4 = { 1'd0, - res_address__h664127, - res_addrBits__h664128, + res_address__h664124, + res_addrBits__h664125, 72'h00001FFFFF44000000 } ; assign MUX_rf$write_2_wr_2__VAL_5 = { 1'd0, - res_address__h710013, - res_addrBits__h710014, + res_address__h710010, + res_addrBits__h710011, 72'h00001FFFFF44000000 } ; assign MUX_rf$write_2_wr_2__VAL_6 = { 1'd0, - res_address__h710959, - res_addrBits__h710960, + res_address__h710956, + res_addrBits__h710957, 72'h00001FFFFF44000000 } ; assign MUX_rf$write_3_wr_2__VAL_1 = { coreFix_memExe_respLrScAmoQ_data_0[128], - res_address__h127849, - res_addrBits__h127850, + res_address__h127848, + res_addrBits__h127849, coreFix_memExe_respLrScAmoQ_data_0[127:112], coreFix_memExe_respLrScAmoQ_data_0[109], coreFix_memExe_respLrScAmoQ_data_0[111:110], @@ -12036,8 +12034,8 @@ module mkCore(CLK, IF_INV_coreFix_memExe_respLrScAmoQ_data_0_235__ETC___d1275 } ; assign MUX_rf$write_3_wr_2__VAL_2 = { mmio_dataRespQ_data_0[128], - res_address__h140989, - res_addrBits__h140990, + res_address__h140988, + res_addrBits__h140989, mmio_dataRespQ_data_0[127:112], mmio_dataRespQ_data_0[109], mmio_dataRespQ_data_0[111:110], @@ -12046,27 +12044,27 @@ module mkCore(CLK, assign MUX_rf$write_3_wr_2__VAL_3 = { coreFix_memExe_lsq$firstLd[125:110] == 16'd65535 && coreFix_memExe_respLrScAmoQ_data_0[128], - res_address__h180673, - res_addrBits__h180674, - x__h185174[127:112], - x__h185174[109], - x__h185174[111:110], - ~x__h185174[108:90], + res_address__h180671, + res_addrBits__h180672, + x__h185172[127:112], + x__h185172[109], + x__h185172[111:110], + ~x__h185172[108:90], IF_INV_IF_coreFix_memExe_lsq_firstLd__502_BITS_ETC___d1958 } ; assign MUX_rf$write_3_wr_2__VAL_4 = { coreFix_memExe_lsq$firstLd[125:110] == 16'd65535 && mmio_dataRespQ_data_0[128], - res_address__h199750, - res_addrBits__h199751, - x__h201338[127:112], - x__h201338[109], - x__h201338[111:110], - ~x__h201338[108:90], + res_address__h199748, + res_addrBits__h199749, + x__h201336[127:112], + x__h201336[109], + x__h201336[111:110], + ~x__h201336[108:90], IF_INV_IF_coreFix_memExe_lsq_firstLd__502_BITS_ETC___d2126 } ; assign MUX_rf$write_3_wr_2__VAL_5 = { coreFix_memExe_lsq$respLd[128], - res_address__h218914, - res_addrBits__h218915, + res_address__h218912, + res_addrBits__h218913, coreFix_memExe_lsq$respLd[127:112], coreFix_memExe_lsq$respLd[109], coreFix_memExe_lsq$respLd[111:110], @@ -12074,13 +12072,13 @@ module mkCore(CLK, IF_INV_coreFix_memExe_lsq_respLd_166_BITS_108__ETC___d2217 } ; assign MUX_rf$write_4_wr_2__VAL_1 = { 1'd1, - data_address__h1030199, - data_addrBits__h1030200, + data_address__h1030232, + data_addrBits__h1030233, 72'hFFFF1FFFFF44000000 } ; assign MUX_rf$write_4_wr_2__VAL_2 = { 1'd0, - data_address__h1031053, - data_addrBits__h1031054, + data_address__h1031086, + data_addrBits__h1031087, 72'h00001FFFFF44000000 } ; assign MUX_rob$enqPort_0_enq_1__VAL_1 = { fetchStage$pipelines_0_first[591:463], @@ -12135,22 +12133,22 @@ module mkCore(CLK, fetchStage_pipelines_0_first__0544_BIT_167_088_ETC___d21450 } ; assign MUX_rob$setExecuted_deqLSQ_2__VAL_2 = { 1'd1, - CASE_coreFix_memExe_lsqfirstSt_BITS_12_TO_11__ETC__q336 } ; + CASE_coreFix_memExe_lsqfirstSt_BITS_12_TO_11__ETC__q338 } ; assign MUX_rob$setExecuted_deqLSQ_2__VAL_6 = { 1'd1, - CASE_coreFix_memExe_lsqfirstLd_BITS_15_TO_14__ETC__q340 } ; + CASE_coreFix_memExe_lsqfirstLd_BITS_15_TO_14__ETC__q342 } ; assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_2 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[4:0] : - res_fflags__h572664 ; + res_fflags__h572661 ; assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_3 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[4:0] : - res_fflags__h618418 ; + res_fflags__h618415 ; assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_4 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[4:0] : - res_fflags__h664165 ; + res_fflags__h664162 ; // inlined wires assign csrf_minstret_ehr_data_lat_0$whas = @@ -12158,7 +12156,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd2818 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd32 ; assign csrf_minstret_ehr_data_lat_1$whas = WILL_FIRE_RL_commitStage_doCommitSystemInst || @@ -12168,24 +12166,24 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd2816 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd31 ; assign csrf_sepcc_reg_data_lat_1$wget = MUX_csrf_sepcc_reg_data_lat_1$wset_1__SEL_1 ? MUX_csrf_sepcc_reg_data_lat_1$wset_1__VAL_1 : MUX_csrf_sepcc_reg_data_lat_1$wset_1__VAL_2 ; assign csrf_sepcc_reg_data_lat_1$whas = + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo36 || WILL_FIRE_RL_rl_debug_csr_write && - f_csr_reqs$D_OUT[75:64] == 12'd321 || - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo36 ; + f_csr_reqs$D_OUT[75:64] == 12'd321 ; assign csrf_mepcc_reg_data_lat_1$wget = MUX_csrf_mepcc_reg_data_lat_1$wset_1__SEL_1 ? MUX_csrf_mepcc_reg_data_lat_1$wset_1__VAL_1 : MUX_csrf_mepcc_reg_data_lat_1$wset_1__VAL_2 ; assign csrf_mepcc_reg_data_lat_1$whas = + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 || WILL_FIRE_RL_rl_debug_csr_write && - f_csr_reqs$D_OUT[75:64] == 12'd833 || - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; + f_csr_reqs$D_OUT[75:64] == 12'd833 ; assign csrInstOrInterruptInflight_lat_0$whas = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 || @@ -12233,7 +12231,7 @@ module mkCore(CLK, assign mmio_pRqQ_enqReq_lat_0$wget = { 1'd1, mmioToPlatform_pRq_enq_x[38], - CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q341, + CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q343, mmioToPlatform_pRq_enq_x[31:0] } ; assign mmio_cRsQ_enqReq_lat_0$wget = { 1'd1, csrf_software_int_pend_vec_3 } ; @@ -12536,7 +12534,7 @@ module mkCore(CLK, // register commitStage_rg_serial_num always@(MUX_commitStage_rg_serial_num$write_1__SEL_1 or - MUX_commitStage_rg_serial_num$write_1__VAL_1 or + MUX_commitStage_rg_serial_num$write_1__VAL_2 or WILL_FIRE_RL_commitStage_doCommitSystemInst or WILL_FIRE_RL_commitStage_doCommitNormalInst or MUX_commitStage_rg_serial_num$write_1__VAL_3) @@ -12544,10 +12542,10 @@ module mkCore(CLK, case (1'b1) // synopsys parallel_case MUX_commitStage_rg_serial_num$write_1__SEL_1: commitStage_rg_serial_num$D_IN = - MUX_commitStage_rg_serial_num$write_1__VAL_1; + MUX_commitStage_rg_serial_num$write_1__VAL_2; WILL_FIRE_RL_commitStage_doCommitSystemInst: commitStage_rg_serial_num$D_IN = - MUX_commitStage_rg_serial_num$write_1__VAL_1; + MUX_commitStage_rg_serial_num$write_1__VAL_2; WILL_FIRE_RL_commitStage_doCommitNormalInst: commitStage_rg_serial_num$D_IN = MUX_commitStage_rg_serial_num$write_1__VAL_3; @@ -12584,8 +12582,8 @@ module mkCore(CLK, // register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$D_IN = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas ? - v__h842938 : - v__h841897 ; + v__h842934 : + v__h841893 ; assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$EN = 1'd1 ; // register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_0 @@ -12722,7 +12720,7 @@ module mkCore(CLK, assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$D_IN = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl ? 3'd0 : - _theResult_____2__h519793 ; + _theResult_____2__h519790 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl @@ -12741,7 +12739,7 @@ module mkCore(CLK, assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$D_IN = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl ? 3'd0 : - v__h519249 ; + v__h519246 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl @@ -12783,7 +12781,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$D_IN = !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl && - _theResult_____2__h530570 ; + _theResult_____2__h530567 ; assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl @@ -12802,7 +12800,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$D_IN = !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl && - v__h521269 ; + v__h521266 ; assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl @@ -12899,7 +12897,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$D_IN = !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl && - _theResult_____2__h537663 ; + _theResult_____2__h537660 ; assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl @@ -12915,7 +12913,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$D_IN = !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl && - v__h536988 ; + v__h536985 ; assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl @@ -12935,7 +12933,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$D_IN = - { x_addr__h539799, + { x_addr__h539796, coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[518:517] : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[518:517], @@ -12962,7 +12960,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$D_IN = !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl && - _theResult_____2__h548298 ; + _theResult_____2__h548295 ; assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl @@ -12981,7 +12979,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$D_IN = !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl && - v__h539437 ; + v__h539434 ; assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl @@ -13057,7 +13055,7 @@ module mkCore(CLK, // register coreFix_memExe_forwardQ_deqP assign coreFix_memExe_forwardQ_deqP$D_IN = !coreFix_memExe_forwardQ_clearReq_rl && - _theResult_____2__h565910 ; + _theResult_____2__h565907 ; assign coreFix_memExe_forwardQ_deqP$EN = 1'd1 ; // register coreFix_memExe_forwardQ_deqReq_rl @@ -13072,7 +13070,7 @@ module mkCore(CLK, // register coreFix_memExe_forwardQ_enqP assign coreFix_memExe_forwardQ_enqP$D_IN = - !coreFix_memExe_forwardQ_clearReq_rl && v__h564236 ; + !coreFix_memExe_forwardQ_clearReq_rl && v__h564233 ; assign coreFix_memExe_forwardQ_enqP$EN = 1'd1 ; // register coreFix_memExe_forwardQ_enqReq_rl @@ -13113,7 +13111,7 @@ module mkCore(CLK, // register coreFix_memExe_memRespLdQ_deqP assign coreFix_memExe_memRespLdQ_deqP$D_IN = !coreFix_memExe_memRespLdQ_clearReq_rl && - _theResult_____2__h562131 ; + _theResult_____2__h562128 ; assign coreFix_memExe_memRespLdQ_deqP$EN = 1'd1 ; // register coreFix_memExe_memRespLdQ_deqReq_rl @@ -13128,7 +13126,7 @@ module mkCore(CLK, // register coreFix_memExe_memRespLdQ_enqP assign coreFix_memExe_memRespLdQ_enqP$D_IN = - !coreFix_memExe_memRespLdQ_clearReq_rl && v__h560457 ; + !coreFix_memExe_memRespLdQ_clearReq_rl && v__h560454 ; assign coreFix_memExe_memRespLdQ_enqP$EN = 1'd1 ; // register coreFix_memExe_memRespLdQ_enqReq_rl @@ -13293,7 +13291,7 @@ module mkCore(CLK, assign csrf_ddc_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd18 && - IF_rob_deqPort_0_deq_data__2632_BIT_294_3835_T_ETC___d23857 == + IF_rob_deqPort_0_deq_data__2632_BIT_294_3837_T_ETC___d23859 == 4'd1 ; // register csrf_external_int_en_vec_0 @@ -13321,7 +13319,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd772 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd23 ; // register csrf_external_int_pend_vec_0 @@ -13372,12 +13370,12 @@ module mkCore(CLK, assign csrf_fflags_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - (IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + (IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd0 || - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd2) || WILL_FIRE_RL_commitStage_doCommitNormalInst && - NOT_IF_NOT_rob_deqPort_0_canDeq__3983_3984_OR__ETC___d24234 || + NOT_IF_NOT_rob_deqPort_0_canDeq__3985_3986_OR__ETC___d24236 || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd1 || f_csr_reqs$D_OUT[75:64] == 12'd3) ; @@ -13390,9 +13388,9 @@ module mkCore(CLK, assign csrf_frm_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - (IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + (IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd1 || - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd2) || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd2 || @@ -13414,7 +13412,7 @@ module mkCore(CLK, assign csrf_fs_reg$EN = MUX_csrf_fs_reg$write_1__SEL_2 || WILL_FIRE_RL_commitStage_doCommitNormalInst && - NOT_IF_NOT_rob_deqPort_0_canDeq__3983_3984_OR__ETC___d24234 || + NOT_IF_NOT_rob_deqPort_0_canDeq__3985_3986_OR__ETC___d24236 || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd1 || f_csr_reqs$D_OUT[75:64] == 12'd2 || @@ -13447,13 +13445,13 @@ module mkCore(CLK, default: csrf_ie_vec_1$D_IN = 1'b0 /* unspecified value */ ; endcase assign csrf_ie_vec_1$EN = + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo40 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && commitStage_commitTrap_2639_BITS_44_TO_43_2837_ETC___d22989 && - csrf_prv_reg_read__0574_ULE_1_2990_AND_IF_comm_ETC___d23023 || + csrf_prv_reg_read__0574_ULE_1_2990_AND_IF_comm_ETC___d23024 || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd256 || - f_csr_reqs$D_OUT[75:64] == 12'd768) || - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo40 ; + f_csr_reqs$D_OUT[75:64] == 12'd768) ; // register csrf_ie_vec_3 always@(MUX_csrf_ie_vec_3$write_1__SEL_1 or @@ -13469,19 +13467,19 @@ module mkCore(CLK, default: csrf_ie_vec_3$D_IN = 1'b0 /* unspecified value */ ; endcase assign csrf_ie_vec_3$EN = + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo30 || WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && commitStage_commitTrap_2639_BITS_44_TO_43_2837_ETC___d22989 && - NOT_csrf_prv_reg_read__0574_ULE_1_2990_3105_OR_ETC___d23110 || - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo30 ; + NOT_csrf_prv_reg_read__0574_ULE_1_2990_3106_OR_ETC___d23112 ; // register csrf_mScratchC_reg assign csrf_mScratchC_reg$D_IN = rob$deqPort_0_deq_data[194:42] ; assign csrf_mScratchC_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd18 && - IF_rob_deqPort_0_deq_data__2632_BIT_294_3835_T_ETC___d23857 == + IF_rob_deqPort_0_deq_data__2632_BIT_294_3837_T_ETC___d23859 == 4'd8 ; // register csrf_mcause_code_reg @@ -13489,14 +13487,14 @@ module mkCore(CLK, MUX_csrf_stval_csr$write_1__VAL_1 or MUX_csrf_mcause_code_reg$write_1__SEL_2 or f_csr_reqs$D_OUT or - MUX_csrf_ie_vec_3$write_1__SEL_3 or cause_code__h1006053) + MUX_csrf_ie_vec_3$write_1__SEL_3 or cause_code__h1006050) case (1'b1) MUX_csrf_mcause_code_reg$write_1__SEL_1: csrf_mcause_code_reg$D_IN = MUX_csrf_stval_csr$write_1__VAL_1[4:0]; MUX_csrf_mcause_code_reg$write_1__SEL_2: csrf_mcause_code_reg$D_IN = f_csr_reqs$D_OUT[4:0]; MUX_csrf_ie_vec_3$write_1__SEL_3: - csrf_mcause_code_reg$D_IN = cause_code__h1006053; + csrf_mcause_code_reg$D_IN = cause_code__h1006050; default: csrf_mcause_code_reg$D_IN = 5'b01010 /* unspecified value */ ; endcase assign csrf_mcause_code_reg$EN = @@ -13504,10 +13502,10 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd834 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && commitStage_commitTrap_2639_BITS_44_TO_43_2837_ETC___d22989 && - NOT_csrf_prv_reg_read__0574_ULE_1_2990_3105_OR_ETC___d23110 || + NOT_csrf_prv_reg_read__0574_ULE_1_2990_3106_OR_ETC___d23112 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd28 ; // register csrf_mcause_interrupt_reg @@ -13515,7 +13513,7 @@ module mkCore(CLK, MUX_csrf_stval_csr$write_1__VAL_1 or MUX_csrf_mcause_code_reg$write_1__SEL_2 or f_csr_reqs$D_OUT or - MUX_csrf_ie_vec_3$write_1__SEL_3 or cause_interrupt__h1006051) + MUX_csrf_ie_vec_3$write_1__SEL_3 or cause_interrupt__h1006048) case (1'b1) MUX_csrf_mcause_code_reg$write_1__SEL_1: csrf_mcause_interrupt_reg$D_IN = @@ -13523,7 +13521,7 @@ module mkCore(CLK, MUX_csrf_mcause_code_reg$write_1__SEL_2: csrf_mcause_interrupt_reg$D_IN = f_csr_reqs$D_OUT[63]; MUX_csrf_ie_vec_3$write_1__SEL_3: - csrf_mcause_interrupt_reg$D_IN = cause_interrupt__h1006051; + csrf_mcause_interrupt_reg$D_IN = cause_interrupt__h1006048; default: csrf_mcause_interrupt_reg$D_IN = 1'b0 /* unspecified value */ ; endcase assign csrf_mcause_interrupt_reg$EN = @@ -13531,10 +13529,10 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd834 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && commitStage_commitTrap_2639_BITS_44_TO_43_2837_ETC___d22989 && - NOT_csrf_prv_reg_read__0574_ULE_1_2990_3105_OR_ETC___d23110 || + NOT_csrf_prv_reg_read__0574_ULE_1_2990_3106_OR_ETC___d23112 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd28 ; // register csrf_mccsr_reg @@ -13547,7 +13545,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd3008 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd37 ; // register csrf_mcounteren_cy_reg @@ -13560,7 +13558,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd774 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd25 ; // register csrf_mcounteren_ir_reg @@ -13573,7 +13571,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd774 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd25 ; // register csrf_mcounteren_tm_reg @@ -13586,7 +13584,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd774 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd25 ; // register csrf_mcycle_ehr_data_rl @@ -13603,7 +13601,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd770 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd21 ; // register csrf_medeleg_15_reg @@ -13616,7 +13614,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd770 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd21 ; // register csrf_medeleg_28_26_reg @@ -13629,7 +13627,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd770 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd21 ; // register csrf_medeleg_9_0_reg @@ -13642,7 +13640,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd770 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd21 ; // register csrf_mepcc_reg_data_rl @@ -13664,7 +13662,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd771 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd22 ; // register csrf_mideleg_1_0_reg @@ -13677,7 +13675,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd771 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd22 ; // register csrf_mideleg_5_3_reg @@ -13690,7 +13688,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd771 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd22 ; // register csrf_mideleg_9_7_reg @@ -13703,14 +13701,14 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd771 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd22 ; // register csrf_minstret_ehr_data_rl assign csrf_minstret_ehr_data_rl$D_IN = csrf_minstret_ehr_data_lat_1$whas ? upd__h3066 : - n__read__h1025204 ; + n__read__h1025238 ; assign csrf_minstret_ehr_data_rl$EN = 1'd1 ; // register csrf_mpp_reg @@ -13728,12 +13726,12 @@ module mkCore(CLK, default: csrf_mpp_reg$D_IN = 2'b10 /* unspecified value */ ; endcase assign csrf_mpp_reg$EN = + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo30 || WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && commitStage_commitTrap_2639_BITS_44_TO_43_2837_ETC___d22989 && - NOT_csrf_prv_reg_read__0574_ULE_1_2990_3105_OR_ETC___d23110 || - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo30 ; + NOT_csrf_prv_reg_read__0574_ULE_1_2990_3106_OR_ETC___d23112 ; // register csrf_mprv_reg assign csrf_mprv_reg$D_IN = @@ -13745,7 +13743,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd19 ; // register csrf_mscratch_csr @@ -13758,7 +13756,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd832 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd26 ; // register csrf_mtcc_reg @@ -13767,16 +13765,16 @@ module mkCore(CLK, MUX_csrf_mtcc_reg$write_1__VAL_1 : MUX_csrf_mtcc_reg$write_1__VAL_2 ; assign csrf_mtcc_reg$EN = + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 || WILL_FIRE_RL_rl_debug_csr_write && - f_csr_reqs$D_OUT[75:64] == 12'd773 || - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 ; + f_csr_reqs$D_OUT[75:64] == 12'd773 ; // register csrf_mtdc_reg assign csrf_mtdc_reg$D_IN = rob$deqPort_0_deq_data[194:42] ; assign csrf_mtdc_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd18 && - IF_rob_deqPort_0_deq_data__2632_BIT_294_3835_T_ETC___d23857 == + IF_rob_deqPort_0_deq_data__2632_BIT_294_3837_T_ETC___d23859 == 4'd7 ; // register csrf_mtval_csr @@ -13801,10 +13799,10 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd835 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && commitStage_commitTrap_2639_BITS_44_TO_43_2837_ETC___d22989 && - NOT_csrf_prv_reg_read__0574_ULE_1_2990_3105_OR_ETC___d23110 || + NOT_csrf_prv_reg_read__0574_ULE_1_2990_3106_OR_ETC___d23112 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd29 ; // register csrf_mxr_reg @@ -13828,7 +13826,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd384 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd17 ; // register csrf_prev_ie_vec_0 @@ -13857,13 +13855,13 @@ module mkCore(CLK, default: csrf_prev_ie_vec_1$D_IN = 1'b0 /* unspecified value */ ; endcase assign csrf_prev_ie_vec_1$EN = + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo40 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && commitStage_commitTrap_2639_BITS_44_TO_43_2837_ETC___d22989 && - csrf_prv_reg_read__0574_ULE_1_2990_AND_IF_comm_ETC___d23023 || + csrf_prv_reg_read__0574_ULE_1_2990_AND_IF_comm_ETC___d23024 || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd256 || - f_csr_reqs$D_OUT[75:64] == 12'd768) || - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo40 ; + f_csr_reqs$D_OUT[75:64] == 12'd768) ; // register csrf_prev_ie_vec_3 always@(MUX_csrf_prev_ie_vec_3$write_1__SEL_1 or @@ -13880,12 +13878,12 @@ module mkCore(CLK, default: csrf_prev_ie_vec_3$D_IN = 1'b0 /* unspecified value */ ; endcase assign csrf_prev_ie_vec_3$EN = + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo30 || WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && commitStage_commitTrap_2639_BITS_44_TO_43_2837_ETC___d22989 && - NOT_csrf_prv_reg_read__0574_ULE_1_2990_3105_OR_ETC___d23110 || - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo30 ; + NOT_csrf_prv_reg_read__0574_ULE_1_2990_3106_OR_ETC___d23112 ; // register csrf_prv_reg always@(MUX_csrf_prv_reg$write_1__SEL_1 or @@ -13904,11 +13902,11 @@ module mkCore(CLK, default: csrf_prv_reg$D_IN = 2'b10 /* unspecified value */ ; endcase assign csrf_prv_reg$EN = + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo24 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && commitStage_commitTrap_2639_BITS_44_TO_43_2837_ETC___d22989 || WILL_FIRE_RL_rl_debug_csr_write && - f_csr_reqs$D_OUT[75:64] == 12'd1968 || - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo24 ; + f_csr_reqs$D_OUT[75:64] == 12'd1968 ; // register csrf_rg_dcsr always@(MUX_csrf_rg_dcsr$write_1__SEL_1 or @@ -13934,7 +13932,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1968 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd42 ; // register csrf_rg_dpc @@ -13961,7 +13959,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1969 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd43 ; // register csrf_rg_dscratch0 @@ -13974,7 +13972,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1970 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd44 ; // register csrf_rg_dscratch1 @@ -13987,7 +13985,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1971 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd45 ; // register csrf_rg_tdata1_data @@ -14000,7 +13998,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1953 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd39 ; // register csrf_rg_tdata1_dmode @@ -14013,7 +14011,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1953 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd39 ; // register csrf_rg_tdata2 @@ -14026,7 +14024,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1954 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd40 ; // register csrf_rg_tdata3 @@ -14039,7 +14037,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1955 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd41 ; // register csrf_rg_tselect @@ -14052,7 +14050,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1952 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd38 ; // register csrf_sScratchC_reg @@ -14060,7 +14058,7 @@ module mkCore(CLK, assign csrf_sScratchC_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd18 && - IF_rob_deqPort_0_deq_data__2632_BIT_294_3835_T_ETC___d23857 == + IF_rob_deqPort_0_deq_data__2632_BIT_294_3837_T_ETC___d23859 == 4'd4 ; // register csrf_scause_code_reg @@ -14068,14 +14066,14 @@ module mkCore(CLK, MUX_csrf_stval_csr$write_1__VAL_1 or MUX_csrf_scause_code_reg$write_1__SEL_2 or f_csr_reqs$D_OUT or - MUX_csrf_ie_vec_1$write_1__SEL_3 or cause_code__h1006053) + MUX_csrf_ie_vec_1$write_1__SEL_3 or cause_code__h1006050) case (1'b1) MUX_csrf_scause_code_reg$write_1__SEL_1: csrf_scause_code_reg$D_IN = MUX_csrf_stval_csr$write_1__VAL_1[4:0]; MUX_csrf_scause_code_reg$write_1__SEL_2: csrf_scause_code_reg$D_IN = f_csr_reqs$D_OUT[4:0]; MUX_csrf_ie_vec_1$write_1__SEL_3: - csrf_scause_code_reg$D_IN = cause_code__h1006053; + csrf_scause_code_reg$D_IN = cause_code__h1006050; default: csrf_scause_code_reg$D_IN = 5'b01010 /* unspecified value */ ; endcase assign csrf_scause_code_reg$EN = @@ -14083,10 +14081,10 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd322 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && commitStage_commitTrap_2639_BITS_44_TO_43_2837_ETC___d22989 && - csrf_prv_reg_read__0574_ULE_1_2990_AND_IF_comm_ETC___d23023 || + csrf_prv_reg_read__0574_ULE_1_2990_AND_IF_comm_ETC___d23024 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd14 ; // register csrf_scause_interrupt_reg @@ -14094,7 +14092,7 @@ module mkCore(CLK, MUX_csrf_stval_csr$write_1__VAL_1 or MUX_csrf_scause_code_reg$write_1__SEL_2 or f_csr_reqs$D_OUT or - MUX_csrf_ie_vec_1$write_1__SEL_3 or cause_interrupt__h1006051) + MUX_csrf_ie_vec_1$write_1__SEL_3 or cause_interrupt__h1006048) case (1'b1) MUX_csrf_scause_code_reg$write_1__SEL_1: csrf_scause_interrupt_reg$D_IN = @@ -14102,7 +14100,7 @@ module mkCore(CLK, MUX_csrf_scause_code_reg$write_1__SEL_2: csrf_scause_interrupt_reg$D_IN = f_csr_reqs$D_OUT[63]; MUX_csrf_ie_vec_1$write_1__SEL_3: - csrf_scause_interrupt_reg$D_IN = cause_interrupt__h1006051; + csrf_scause_interrupt_reg$D_IN = cause_interrupt__h1006048; default: csrf_scause_interrupt_reg$D_IN = 1'b0 /* unspecified value */ ; endcase assign csrf_scause_interrupt_reg$EN = @@ -14110,10 +14108,10 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd322 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && commitStage_commitTrap_2639_BITS_44_TO_43_2837_ETC___d22989 && - csrf_prv_reg_read__0574_ULE_1_2990_AND_IF_comm_ETC___d23023 || + csrf_prv_reg_read__0574_ULE_1_2990_AND_IF_comm_ETC___d23024 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd14 ; // register csrf_scounteren_cy_reg @@ -14126,7 +14124,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd262 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd11 ; // register csrf_scounteren_ir_reg @@ -14139,7 +14137,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd262 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd11 ; // register csrf_scounteren_tm_reg @@ -14152,7 +14150,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd262 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd11 ; // register csrf_sepcc_reg_data_rl @@ -14189,7 +14187,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd772 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd23 ; // register csrf_software_int_pend_vec_0 @@ -14231,13 +14229,13 @@ module mkCore(CLK, default: csrf_spp_reg$D_IN = 1'b0 /* unspecified value */ ; endcase assign csrf_spp_reg$EN = + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo40 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && commitStage_commitTrap_2639_BITS_44_TO_43_2837_ETC___d22989 && - csrf_prv_reg_read__0574_ULE_1_2990_AND_IF_comm_ETC___d23023 || + csrf_prv_reg_read__0574_ULE_1_2990_AND_IF_comm_ETC___d23024 || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd256 || - f_csr_reqs$D_OUT[75:64] == 12'd768) || - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo40 ; + f_csr_reqs$D_OUT[75:64] == 12'd768) ; // register csrf_sscratch_csr assign csrf_sscratch_csr$D_IN = @@ -14249,7 +14247,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd320 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd12 ; // register csrf_stats_module_doStats @@ -14262,16 +14260,16 @@ module mkCore(CLK, MUX_csrf_stcc_reg$write_1__VAL_1 : MUX_csrf_stcc_reg$write_1__VAL_2 ; assign csrf_stcc_reg$EN = + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo38 || WILL_FIRE_RL_rl_debug_csr_write && - f_csr_reqs$D_OUT[75:64] == 12'd261 || - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo38 ; + f_csr_reqs$D_OUT[75:64] == 12'd261 ; // register csrf_stdc_reg assign csrf_stdc_reg$D_IN = rob$deqPort_0_deq_data[194:42] ; assign csrf_stdc_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd18 && - IF_rob_deqPort_0_deq_data__2632_BIT_294_3835_T_ETC___d23857 == + IF_rob_deqPort_0_deq_data__2632_BIT_294_3837_T_ETC___d23859 == 4'd3 ; // register csrf_stval_csr @@ -14296,10 +14294,10 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd323 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && commitStage_commitTrap_2639_BITS_44_TO_43_2837_ETC___d22989 && - csrf_prv_reg_read__0574_ULE_1_2990_AND_IF_comm_ETC___d23023 || + csrf_prv_reg_read__0574_ULE_1_2990_AND_IF_comm_ETC___d23024 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd15 ; // register csrf_sum_reg @@ -14342,7 +14340,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd772 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd23 ; // register csrf_timer_int_pend_vec_0 @@ -14376,7 +14374,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd19 ; // register csrf_tvm_reg @@ -14389,7 +14387,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd19 ; // register csrf_tw_reg @@ -14402,7 +14400,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd19 ; // register csrf_vm_mode_sv39_reg @@ -14415,7 +14413,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd384 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd17 ; // register flush_brpred @@ -14433,10 +14431,10 @@ module mkCore(CLK, WILL_FIRE_RL_flushCaches ; // register flush_reservation - assign flush_reservation$D_IN = !MUX_flush_reservation$write_1__SEL_1 ; + assign flush_reservation$D_IN = !MUX_flush_reservation$write_1__SEL_2 ; assign flush_reservation$EN = + WILL_FIRE_RL_commitStage_doCommitTrap_handle && _dfoo20 || WILL_FIRE_RL_prepareCachesAndTlbs && flush_reservation || - WILL_FIRE_RL_commitStage_doCommitTrap_handle && _dfoo22 || WILL_FIRE_RL_commitStage_doCommitSystemInst ; // register flush_tlbs @@ -14448,7 +14446,7 @@ module mkCore(CLK, WILL_FIRE_RL_commitStage_doCommitSystemInst && (rob$deqPort_0_deq_data[469:465] == 5'd21 || rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd17) ; // register mmio_cRqQ_clearReq_rl @@ -14815,19 +14813,19 @@ module mkCore(CLK, assign update_vm_info$D_IN = !MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1 ; assign update_vm_info$EN = + WILL_FIRE_RL_commitStage_doCommitTrap_handle && _dfoo20 || WILL_FIRE_RL_prepareCachesAndTlbs && update_vm_info || - WILL_FIRE_RL_commitStage_doCommitTrap_handle && _dfoo22 || WILL_FIRE_RL_commitStage_doCommitSystemInst ; // submodule coreFix_aluExe_0_dispToRegQ assign coreFix_aluExe_0_dispToRegQ$enq_x = { coreFix_aluExe_0_rsAlu$dispatchData[234:230], - CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q343, - CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q344, - coreFix_aluExe_0_rsAlu$dispatchData[188:141], CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q345, - coreFix_aluExe_0_rsAlu$dispatchData[128], CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q346, + coreFix_aluExe_0_rsAlu$dispatchData[188:141], + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q347, + coreFix_aluExe_0_rsAlu$dispatchData[128], + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q348, coreFix_aluExe_0_rsAlu$dispatchData[122:90], coreFix_aluExe_0_rsAlu$dispatchData[65:21], coreFix_aluExe_0_rsAlu$dispatchData[89:66], @@ -14881,7 +14879,7 @@ module mkCore(CLK, coreFix_aluExe_0_regToExeQ$first[822:818] == 5'd18, basicExec___d20102[932:770], basicExec___d20102[606:271], - CASE_basicExec_0102_BITS_270_TO_266_0_basicExe_ETC__q347, + CASE_basicExec_0102_BITS_270_TO_266_0_basicExe_ETC__q349, basicExec___d20102[265:0], coreFix_aluExe_0_regToExeQ$first[16:0] } ; assign coreFix_aluExe_0_exeToFinQ$specUpdate_correctSpeculation_mask = @@ -14923,12 +14921,12 @@ module mkCore(CLK, // submodule coreFix_aluExe_0_regToExeQ assign coreFix_aluExe_0_regToExeQ$enq_x = { coreFix_aluExe_0_dispToRegQ$first[230:226], - CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_22_ETC__q349, - CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_19_ETC__q350, + CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_22_ETC__q351, + CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_19_ETC__q352, coreFix_aluExe_0_dispToRegQ$first[184:137], - CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q351, + CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q353, coreFix_aluExe_0_dispToRegQ$first[124], - CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_12_ETC__q352, + CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_12_ETC__q354, coreFix_aluExe_0_dispToRegQ$first[118:86], coreFix_aluExe_0_dispToRegQ$first[61:17], NOT_coreFix_aluExe_0_dispToRegQ_first__8612_BI_ETC___d19690, @@ -15066,11 +15064,11 @@ module mkCore(CLK, endcase end assign coreFix_aluExe_0_rsAlu$EN_enq = + WILL_FIRE_RL_renameStage_doRenaming && _dfoo18 || WILL_FIRE_RL_renameStage_doRenaming_SystemInst && (fetchStage$pipelines_0_first[268:266] == 3'd0 || fetchStage$pipelines_0_first[238:237] == 2'd1 || - fetchStage$pipelines_0_first[238:237] == 2'd0) || - WILL_FIRE_RL_renameStage_doRenaming && _dfoo18 ; + fetchStage$pipelines_0_first[238:237] == 2'd0) ; assign coreFix_aluExe_0_rsAlu$EN_setRobEnqTime = 1'd1 ; assign coreFix_aluExe_0_rsAlu$EN_doDispatch = WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu ; @@ -15123,12 +15121,12 @@ module mkCore(CLK, // submodule coreFix_aluExe_1_dispToRegQ assign coreFix_aluExe_1_dispToRegQ$enq_x = { coreFix_aluExe_1_rsAlu$dispatchData[234:230], - CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q354, - CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q355, - coreFix_aluExe_1_rsAlu$dispatchData[188:141], CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q356, - coreFix_aluExe_1_rsAlu$dispatchData[128], CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q357, + coreFix_aluExe_1_rsAlu$dispatchData[188:141], + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q358, + coreFix_aluExe_1_rsAlu$dispatchData[128], + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q359, coreFix_aluExe_1_rsAlu$dispatchData[122:90], coreFix_aluExe_1_rsAlu$dispatchData[65:21], coreFix_aluExe_1_rsAlu$dispatchData[89:66], @@ -15181,7 +15179,7 @@ module mkCore(CLK, coreFix_aluExe_1_regToExeQ$first[822:818] == 5'd18, basicExec___d17927[932:770], basicExec___d17927[606:271], - CASE_basicExec_7927_BITS_270_TO_266_0_basicExe_ETC__q358, + CASE_basicExec_7927_BITS_270_TO_266_0_basicExe_ETC__q360, basicExec___d17927[265:0], coreFix_aluExe_1_regToExeQ$first[16:0] } ; assign coreFix_aluExe_1_exeToFinQ$specUpdate_correctSpeculation_mask = @@ -15223,12 +15221,12 @@ module mkCore(CLK, // submodule coreFix_aluExe_1_regToExeQ assign coreFix_aluExe_1_regToExeQ$enq_x = { coreFix_aluExe_1_dispToRegQ$first[230:226], - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_22_ETC__q360, - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_19_ETC__q361, + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_22_ETC__q362, + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_19_ETC__q363, coreFix_aluExe_1_dispToRegQ$first[184:137], - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q362, + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q364, coreFix_aluExe_1_dispToRegQ$first[124], - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_12_ETC__q363, + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_12_ETC__q365, coreFix_aluExe_1_dispToRegQ$first[118:86], coreFix_aluExe_1_dispToRegQ$first[61:17], NOT_coreFix_aluExe_1_dispToRegQ_first__5790_BI_ETC___d17515, @@ -15270,7 +15268,7 @@ module mkCore(CLK, // submodule coreFix_aluExe_1_rsAlu assign coreFix_aluExe_1_rsAlu$enq_x = - (k__h954121 == 1'd1 && fetchStage$pipelines_0_canDeq && + (k__h954118 == 1'd1 && fetchStage$pipelines_0_canDeq && NOT_fetchStage_pipelines_0_first__0544_BITS_26_ETC___d22314) ? { fetchStage$pipelines_0_first[273:269], IF_fetchStage_pipelines_0_first__0544_BITS_268_ETC___d20670, @@ -15288,7 +15286,7 @@ module mkCore(CLK, fetchStage$pipelines_1_first[329:306], regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h978585, + renaming_spec_bits__h978582, fetchStage$pipelines_1_first[268:266] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -15437,7 +15435,7 @@ module mkCore(CLK, // submodule coreFix_fpuMulDivExe_0_dispToRegQ assign coreFix_fpuMulDivExe_0_dispToRegQ$enq_x = - { CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q365, + { CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q367, coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[65:9] } ; assign coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_correctSpeculation_mask = IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d20485 ; @@ -15549,8 +15547,8 @@ module mkCore(CLK, assign coreFix_fpuMulDivExe_0_fpuExec_double_fma$request_put = { coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd2, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14201, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q366, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q367, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q368, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q369, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14974 } ; assign coreFix_fpuMulDivExe_0_fpuExec_double_fma$EN_request_put = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && @@ -15766,12 +15764,12 @@ module mkCore(CLK, // submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$D_IN = - { x__h841215, - b__h840679 == 64'd0, - a__h840678, + { x__h841211, + b__h840675 == 64'd0, + a__h840674, coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0, - x__h841241, - a__h840678[63], + x__h841237, + a__h840674[63], 8'd0 } ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$ENQ = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && @@ -15786,8 +15784,8 @@ module mkCore(CLK, // submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$D_IN = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? - _theResult___snd__h841227 : - b__h840679 ; + _theResult___snd__h841223 : + b__h840675 ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$ENQ = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && coreFix_fpuMulDivExe_0_regToExeQ$first[254:252] == 3'd3 && @@ -15800,7 +15798,7 @@ module mkCore(CLK, // submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_IN = - { x__h841827, + { x__h841823, coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$D_OUT[75:0] } ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$ENQ = CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_compute ; @@ -15879,11 +15877,11 @@ module mkCore(CLK, // submodule coreFix_fpuMulDivExe_0_regToExeQ assign coreFix_fpuMulDivExe_0_regToExeQ$enq_x = - { CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q369, + { CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q371, coreFix_fpuMulDivExe_0_dispToRegQ$first[32:12], - x__h719354, - x__h719355, - x__h719356, + x__h719350, + x__h719351, + x__h719352, coreFix_fpuMulDivExe_0_dispToRegQ$first[11:0] } ; assign coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_correctSpeculation_mask = IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d20485 ; @@ -15935,7 +15933,7 @@ module mkCore(CLK, { IF_fetchStage_pipelines_1_first__0553_BITS_268_ETC___d21642, regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h978585, + renaming_spec_bits__h978582, fetchStage$pipelines_1_first[268:266] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -16093,7 +16091,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget : coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq_n = - x__h505455 ; + x__h505453 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n = (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[583:582] == 2'd0) ? @@ -16203,7 +16201,7 @@ module mkCore(CLK, // submodule coreFix_memExe_dMem_cache_m_banks_0_pRqMshr assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit_r = { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d7144, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q370 } ; + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q372 } ; assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq_n = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[580:579] ; assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getState_n = @@ -16525,7 +16523,7 @@ module mkCore(CLK, (fetchStage$pipelines_0_canDeq && regRenamingTable_rename_0_canRename__1456_AND__ETC___d22394) ? specTagManager$currentSpecBits : - renaming_spec_bits__h978585 ; + renaming_spec_bits__h978582 ; assign coreFix_memExe_lsq$enqSt_dst = (fetchStage$pipelines_0_canDeq && regRenamingTable_rename_0_canRename__1456_AND__ETC___d22403) ? @@ -16545,7 +16543,7 @@ module mkCore(CLK, (fetchStage$pipelines_0_canDeq && regRenamingTable_rename_0_canRename__1456_AND__ETC___d22403) ? specTagManager$currentSpecBits : - renaming_spec_bits__h978585 ; + renaming_spec_bits__h978582 ; assign coreFix_memExe_lsq$getHit_t = MUX_coreFix_memExe_lsq$getHit_1__SEL_1 ? MUX_coreFix_memExe_lsq$getHit_1__VAL_1 : @@ -16574,8 +16572,8 @@ module mkCore(CLK, MUX_coreFix_memExe_lsq$respLd_2__VAL_2 ; assign coreFix_memExe_lsq$respLd_t = WILL_FIRE_RL_coreFix_memExe_doRespLdMem ? - t__h215266 : - t__h217619 ; + t__h215264 : + t__h217617 ; assign coreFix_memExe_lsq$setAtCommit_0_put = rob$deqPort_0_deq_data[24:19] ; assign coreFix_memExe_lsq$setAtCommit_1_put = @@ -16628,7 +16626,7 @@ module mkCore(CLK, ~IF_coreFix_memExe_regToExeQ_first__664_BIT_103_ETC___d4036[2], IF_coreFix_memExe_regToExeQ_first__664_BIT_103_ETC___d4036[1:0], coreFix_memExe_regToExeQ$first[218:155] } : - { pointer__h245528[3:0] == 4'd0 && + { pointer__h245525[3:0] == 4'd0 && coreFix_memExe_lsq$getOrigBE[0] && coreFix_memExe_lsq$getOrigBE[1] && coreFix_memExe_lsq$getOrigBE[2] && @@ -16798,7 +16796,7 @@ module mkCore(CLK, !fetchStage$pipelines_1_first[239], regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h978585, + renaming_spec_bits__h978582, fetchStage$pipelines_1_first[268:266] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -17020,7 +17018,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd2049 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd7 ; assign csrf_stats_module_writeQ$DEQ = EN_sendDoStats ; assign csrf_stats_module_writeQ$CLR = 1'b0 ; @@ -17031,7 +17029,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd2048 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd6 ; assign csrf_terminate_module_terminateQ$DEQ = EN_coreIndInv_terminate ; assign csrf_terminate_module_terminateQ$CLR = 1'b0 ; @@ -17211,9 +17209,9 @@ module mkCore(CLK, always@(MUX_commitStage_rg_serial_num$write_1__SEL_1 or MUX_fetchStage$redirect_1__VAL_1 or WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or - new_pc__h880399 or + new_pc__h880397 or WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or - new_pc__h920773 or + new_pc__h920770 or WILL_FIRE_RL_commitStage_doCommitKilledLd or rob$deqPort_0_deq_data or WILL_FIRE_RL_commitStage_doCommitSystemInst or @@ -17224,9 +17222,9 @@ module mkCore(CLK, MUX_commitStage_rg_serial_num$write_1__SEL_1: fetchStage$redirect_pc = MUX_fetchStage$redirect_1__VAL_1; WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T: - fetchStage$redirect_pc = new_pc__h880399; + fetchStage$redirect_pc = new_pc__h880397; WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T: - fetchStage$redirect_pc = new_pc__h920773; + fetchStage$redirect_pc = new_pc__h920770; WILL_FIRE_RL_commitStage_doCommitKilledLd: fetchStage$redirect_pc = rob$deqPort_0_deq_data[630:502]; WILL_FIRE_RL_commitStage_doCommitSystemInst: @@ -17416,7 +17414,7 @@ module mkCore(CLK, assign regRenamingTable$rename_1_claimRename_r = fetchStage$pipelines_1_first[96:70] ; assign regRenamingTable$rename_1_claimRename_sb = - renaming_spec_bits__h978585 ; + renaming_spec_bits__h978582 ; assign regRenamingTable$rename_1_getRename_r = fetchStage$pipelines_1_first[96:70] ; assign regRenamingTable$specUpdate_correctSpeculation_mask = @@ -17693,7 +17691,7 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__0553_BITS_265_ETC___d22542, IF_NOT_fetchStage_pipelines_1_first__0553_BITS_ETC___d22613, 7'd32, - renaming_spec_bits__h978585 } ; + renaming_spec_bits__h978582 } ; assign rob$getOrigPC_0_get_x = coreFix_aluExe_0_dispToRegQ$first[52:41] ; assign rob$getOrigPC_1_get_x = coreFix_aluExe_1_dispToRegQ$first[52:41] ; assign rob$getOrigPC_2_get_x = 12'h0 ; @@ -17777,29 +17775,29 @@ module mkCore(CLK, always@(WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple or coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first or WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma or - data__h572105 or + data__h572102 or WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv or - data__h617865 or + data__h617862 or WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt or - data__h663612 or + data__h663609 or WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul or - data__h709528 or - WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv or data__h710474) + data__h709525 or + WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv or data__h710471) begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple: rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[101:38]; WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma: - rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = data__h572105; + rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = data__h572102; WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv: - rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = data__h617865; + rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = data__h617862; WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt: - rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = data__h663612; + rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = data__h663609; WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul: - rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = data__h709528; + rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = data__h709525; WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv: - rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = data__h710474; + rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = data__h710471; default: rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase @@ -18256,11 +18254,11 @@ module mkCore(CLK, module_amoExec instance_amoExec_5(.amoExec_amo_inst({ mmio_pRqQ_data_0[35:32], 4'd8 }), .amoExec_wordIdx(2'd0), - .amoExec_current({ 128'd0, r__h861998 }), + .amoExec_current({ 128'd0, r__h861996 }), .amoExec_inpt({ 97'd0, x__h65639 }), .amoExec(amoExec___d775)); module_amoExec instance_amoExec_4(.amoExec_amo_inst(coreFix_memExe_dMem_cache_m_banks_0_processAmo[11:4]), - .amoExec_wordIdx(wordIdx__h266170), + .amoExec_wordIdx(wordIdx__h266168), .amoExec_current({ SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4874, { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4881, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4887 } }), @@ -18277,12 +18275,12 @@ module mkCore(CLK, fetchStage$pipelines_0_first[81:77], { fetchStage$pipelines_0_first[76], fetchStage$pipelines_0_first[75:70] } } }), - .checkForException_csrState({ x_decodeInfo_frm__h935002, - r1__read_BITS_13_TO_12___h935208 != + .checkForException_csrState({ x_decodeInfo_frm__h934999, + r1__read_BITS_13_TO_12___h935205 != 2'd0, - { prv__h1028891, + { prv__h1028925, csrf_tvm_reg, - { r1__read_BIT_20___h935714, + { r1__read_BIT_20___h935711, csrf_tsr_reg, { csrf_mcounteren_cy_reg, csrf_mcounteren_cy_reg && @@ -18308,12 +18306,12 @@ module mkCore(CLK, fetchStage$pipelines_1_first[81:77], { fetchStage$pipelines_1_first[76], fetchStage$pipelines_1_first[75:70] } } }), - .checkForException_csrState({ x_decodeInfo_frm__h935002, - r1__read_BITS_13_TO_12___h935208 != + .checkForException_csrState({ x_decodeInfo_frm__h934999, + r1__read_BITS_13_TO_12___h935205 != 2'd0, - { prv__h1028891, + { prv__h1028925, csrf_tvm_reg, - { r1__read_BIT_20___h935714, + { r1__read_BIT_20___h935711, csrf_tsr_reg, { csrf_mcounteren_cy_reg, csrf_mcounteren_cy_reg && @@ -18324,14 +18322,14 @@ module mkCore(CLK, { csrf_mcounteren_tm_reg, csrf_mcounteren_tm_reg && csrf_scounteren_tm_reg } } } } } }), - .checkForException_pcc(pc__h973086), + .checkForException_pcc(pc__h973083), .checkForException_fourByteInst(fetchStage$pipelines_1_first[98:97] == 2'b11), .checkForException(checkForException___d21903)); module_capChecks instance_capChecks_0(.capChecks_a(coreFix_memExe_regToExeQ$first[384:222]), .capChecks_b(coreFix_memExe_regToExeQ$first[221:59]), .capChecks_ddc({ csrf_ddc_reg, - repBound__h251633, + repBound__h251630, { csrf_ddc_reg_read__078_BITS_27_TO_25_161_ULT_c_ETC___d4162, csrf_ddc_reg_read__078_BITS_13_TO_11_159_ULT_c_ETC___d4163, csrf_ddc_reg_read__078_BITS_85_TO_83_164_ULT_c_ETC___d4175 } }), @@ -18342,84 +18340,84 @@ module mkCore(CLK, .prepareBoundsCheck_b(coreFix_memExe_regToExeQ$first[221:59]), .prepareBoundsCheck_pcc(163'h400000000000000000003FFFC7FFFFD10000003F0), .prepareBoundsCheck_ddc({ csrf_ddc_reg, - repBound__h251633, + repBound__h251630, { csrf_ddc_reg_read__078_BITS_27_TO_25_161_ULT_c_ETC___d4162, csrf_ddc_reg_read__078_BITS_13_TO_11_159_ULT_c_ETC___d4163, csrf_ddc_reg_read__078_BITS_85_TO_83_164_ULT_c_ETC___d4175 } }), - .prepareBoundsCheck_vaddr(tmpAddr__h245727), - .prepareBoundsCheck_size(x__h252368 + - y__h252369), + .prepareBoundsCheck_vaddr(tmpAddr__h245724), + .prepareBoundsCheck_size(x__h252365 + + y__h252366), .prepareBoundsCheck_toCheck(coreFix_memExe_regToExeQ$first[58:12]), .prepareBoundsCheck(prepareBoundsCheck___d4263)); module_execFpuSimple instance_execFpuSimple_3(.execFpuSimple_fpu_inst({ coreFix_fpuMulDivExe_0_regToExeQ$first[233:229], - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q281, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q283, coreFix_fpuMulDivExe_0_regToExeQ$first[225] }), - .execFpuSimple_rVal1(rVal1__h719448), - .execFpuSimple_rVal2(rVal2__h719449), + .execFpuSimple_rVal1(rVal1__h719444), + .execFpuSimple_rVal2(rVal2__h719445), .execFpuSimple(execFpuSimple___d15313)); module_basicExec instance_basicExec_8(.basicExec_dInst({ coreFix_aluExe_1_regToExeQ$first[822:818], - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_817_ETC__q283, - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_787_ETC__q284, + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_817_ETC__q285, + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_787_ETC__q286, coreFix_aluExe_1_regToExeQ$first[776:729], - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_728_ETC__q285, + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_728_ETC__q287, coreFix_aluExe_1_regToExeQ$first[716], - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_715_ETC__q286, + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_715_ETC__q288, coreFix_aluExe_1_regToExeQ$first[710:678] }), .basicExec_rVal1(coreFix_aluExe_1_regToExeQ$first[632:470]), .basicExec_rVal2(coreFix_aluExe_1_regToExeQ$first[469:307]), .basicExec_pcc({ coreFix_aluExe_1_regToExeQ$first[306], - { cr_address__h872617, - cr_addrBits__h872618, + { cr_address__h872615, + cr_addrBits__h872616, { coreFix_aluExe_1_regToExeQ$first[305:290], { coreFix_aluExe_1_regToExeQ$first[287], coreFix_aluExe_1_regToExeQ$first[289:288] }, INV_coreFix_aluExe_1_regToExeQ_first__7524_BIT_ETC___d17839 } }, - repBound__h873086, + repBound__h873084, { IF_INV_coreFix_aluExe_1_regToExeQ_first__7524__ETC___d17846, IF_INV_coreFix_aluExe_1_regToExeQ_first__7524__ETC___d17847, IF_INV_coreFix_aluExe_1_regToExeQ_first__7524__ETC___d17859 } }), .basicExec_ppc({ coreFix_aluExe_1_regToExeQ$first[177], - { cr_address__h873165, - cr_addrBits__h873166, + { cr_address__h873163, + cr_addrBits__h873164, { coreFix_aluExe_1_regToExeQ$first[176:161], - { cr_flags__h873168, - cr_reserved__h873169 }, + { cr_flags__h873166, + cr_reserved__h873167 }, INV_coreFix_aluExe_1_regToExeQ_first__7524_BIT_ETC___d17903 } }, - repBound__h873634, + repBound__h873632, { IF_INV_coreFix_aluExe_1_regToExeQ_first__7524__ETC___d17910, IF_INV_coreFix_aluExe_1_regToExeQ_first__7524__ETC___d17911, IF_INV_coreFix_aluExe_1_regToExeQ_first__7524__ETC___d17923 } }), .basicExec_orig_inst(coreFix_aluExe_1_regToExeQ$first[48:17]), .basicExec(basicExec___d17927)); module_basicExec instance_basicExec_7(.basicExec_dInst({ coreFix_aluExe_0_regToExeQ$first[822:818], - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_817_ETC__q288, - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_787_ETC__q289, + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_817_ETC__q290, + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_787_ETC__q291, coreFix_aluExe_0_regToExeQ$first[776:729], - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_728_ETC__q290, + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_728_ETC__q292, coreFix_aluExe_0_regToExeQ$first[716], - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_715_ETC__q291, + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_715_ETC__q293, coreFix_aluExe_0_regToExeQ$first[710:678] }), .basicExec_rVal1(coreFix_aluExe_0_regToExeQ$first[632:470]), .basicExec_rVal2(coreFix_aluExe_0_regToExeQ$first[469:307]), .basicExec_pcc({ coreFix_aluExe_0_regToExeQ$first[306], - { cr_address__h913658, - cr_addrBits__h913659, + { cr_address__h913655, + cr_addrBits__h913656, { coreFix_aluExe_0_regToExeQ$first[305:290], { coreFix_aluExe_0_regToExeQ$first[287], coreFix_aluExe_0_regToExeQ$first[289:288] }, INV_coreFix_aluExe_0_regToExeQ_first__9699_BIT_ETC___d20014 } }, - repBound__h914127, + repBound__h914124, { IF_INV_coreFix_aluExe_0_regToExeQ_first__9699__ETC___d20021, IF_INV_coreFix_aluExe_0_regToExeQ_first__9699__ETC___d20022, IF_INV_coreFix_aluExe_0_regToExeQ_first__9699__ETC___d20034 } }), .basicExec_ppc({ coreFix_aluExe_0_regToExeQ$first[177], - { cr_address__h914206, - cr_addrBits__h914207, + { cr_address__h914203, + cr_addrBits__h914204, { coreFix_aluExe_0_regToExeQ$first[176:161], - { cr_flags__h914209, - cr_reserved__h914210 }, + { cr_flags__h914206, + cr_reserved__h914207 }, INV_coreFix_aluExe_0_regToExeQ_first__9699_BIT_ETC___d20078 } }, - repBound__h914675, + repBound__h914672, { IF_INV_coreFix_aluExe_0_regToExeQ_first__9699__ETC___d20085, IF_INV_coreFix_aluExe_0_regToExeQ_first__9699__ETC___d20086, IF_INV_coreFix_aluExe_0_regToExeQ_first__9699__ETC___d20098 } }), @@ -18427,1191 +18425,1191 @@ module mkCore(CLK, .basicExec(basicExec___d20102)); assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q111 = _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d11257 ? - _theResult___snd__h680549 : - _theResult____h672377 ; - assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q43 = + _theResult___snd__h680546 : + _theResult____h672374 ; + assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q41 = _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d8463 ? - _theResult___snd__h589053 : - _theResult____h580879 ; + _theResult___snd__h589050 : + _theResult____h580876 ; assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q76 = _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d9860 ? - _theResult___snd__h634802 : - _theResult____h626630 ; + _theResult___snd__h634799 : + _theResult____h626627 ; assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q150 = _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d13154 ? - _theResult___snd__h748860 : - _theResult____h740561 ; + _theResult___snd__h748856 : + _theResult____h740557 ; assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q167 = _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d13869 ? - _theResult___snd__h827017 : - _theResult____h818718 ; + _theResult___snd__h827013 : + _theResult____h818714 ; assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q190 = _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14639 ? - _theResult___snd__h787713 : - _theResult____h779414 ; + _theResult___snd__h787709 : + _theResult____h779410 ; assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q121 = _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d11808 ? - _theResult___snd__h698315 : - _theResult____h690014 ; + _theResult___snd__h698312 : + _theResult____h690011 ; assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q51 = _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d9014 ? - _theResult___snd__h606819 : - _theResult____h598518 ; + _theResult___snd__h606816 : + _theResult____h598515 ; assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q86 = _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d10411 ? - _theResult___snd__h652568 : - _theResult____h644267 ; + _theResult___snd__h652565 : + _theResult____h644264 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q146 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d12842 ? - _theResult___snd__h739209 : + _theResult___snd__h739205 : 57'd0 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q153 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d13204 ? - _theResult___snd__h739209 : - _theResult___snd__h757614 ; + _theResult___snd__h739205 : + _theResult___snd__h757610 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q163 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d13572 ? - _theResult___snd__h817366 : + _theResult___snd__h817362 : 57'd0 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q170 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d13919 ? - _theResult___snd__h817366 : - _theResult___snd__h835771 ; + _theResult___snd__h817362 : + _theResult___snd__h835767 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q186 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14342 ? - _theResult___snd__h778062 : + _theResult___snd__h778058 : 57'd0 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q193 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14689 ? - _theResult___snd__h778062 : - _theResult___snd__h796467 ; + _theResult___snd__h778058 : + _theResult___snd__h796463 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q113 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d11488 ? - _theResult___snd__h689131 : + _theResult___snd__h689128 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q126 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d11881 ? - _theResult___snd__h689131 : - _theResult___snd__h706921 ; - assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q45 = + _theResult___snd__h689128 : + _theResult___snd__h706918 ; + assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q43 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d8694 ? - _theResult___snd__h597635 : + _theResult___snd__h597632 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q56 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d9087 ? - _theResult___snd__h597635 : - _theResult___snd__h615425 ; + _theResult___snd__h597632 : + _theResult___snd__h615422 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q78 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d10091 ? - _theResult___snd__h643384 : + _theResult___snd__h643381 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q91 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d10484 ? - _theResult___snd__h643384 : - _theResult___snd__h661174 ; + _theResult___snd__h643381 : + _theResult___snd__h661171 ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d10680 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9624 ? - ((_theResult___fst_exp__h634739 == 8'd255) ? + ((_theResult___fst_exp__h634736 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10665) : - ((_theResult___fst_exp__h643395 == 8'd255) ? + ((_theResult___fst_exp__h643392 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10678) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d10730 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9624 ? - ((_theResult___fst_exp__h634739 == 8'd255) ? + ((_theResult___fst_exp__h634736 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10721) : - ((_theResult___fst_exp__h643395 == 8'd255) ? + ((_theResult___fst_exp__h643392 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10728) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d12077 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d11021 ? - ((_theResult___fst_exp__h680486 == 8'd255) ? + ((_theResult___fst_exp__h680483 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12062) : - ((_theResult___fst_exp__h689142 == 8'd255) ? + ((_theResult___fst_exp__h689139 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12075) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d12127 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d11021 ? - ((_theResult___fst_exp__h680486 == 8'd255) ? + ((_theResult___fst_exp__h680483 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12118) : - ((_theResult___fst_exp__h689142 == 8'd255) ? + ((_theResult___fst_exp__h689139 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12125) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d9283 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8227 ? - ((_theResult___fst_exp__h588990 == 8'd255) ? + ((_theResult___fst_exp__h588987 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9268) : - ((_theResult___fst_exp__h597646 == 8'd255) ? + ((_theResult___fst_exp__h597643 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9281) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d9333 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8227 ? - ((_theResult___fst_exp__h588990 == 8'd255) ? + ((_theResult___fst_exp__h588987 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9324) : - ((_theResult___fst_exp__h597646 == 8'd255) ? + ((_theResult___fst_exp__h597643 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9331) ; assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d11255 = - (_theResult____h672377[56] ? + (_theResult____h672374[56] ? 6'd0 : - (_theResult____h672377[55] ? + (_theResult____h672374[55] ? 6'd1 : - (_theResult____h672377[54] ? + (_theResult____h672374[54] ? 6'd2 : - (_theResult____h672377[53] ? + (_theResult____h672374[53] ? 6'd3 : - (_theResult____h672377[52] ? + (_theResult____h672374[52] ? 6'd4 : - (_theResult____h672377[51] ? + (_theResult____h672374[51] ? 6'd5 : - (_theResult____h672377[50] ? + (_theResult____h672374[50] ? 6'd6 : - (_theResult____h672377[49] ? + (_theResult____h672374[49] ? 6'd7 : - (_theResult____h672377[48] ? + (_theResult____h672374[48] ? 6'd8 : - (_theResult____h672377[47] ? + (_theResult____h672374[47] ? 6'd9 : - (_theResult____h672377[46] ? + (_theResult____h672374[46] ? 6'd10 : - (_theResult____h672377[45] ? + (_theResult____h672374[45] ? 6'd11 : - (_theResult____h672377[44] ? + (_theResult____h672374[44] ? 6'd12 : - (_theResult____h672377[43] ? + (_theResult____h672374[43] ? 6'd13 : - (_theResult____h672377[42] ? + (_theResult____h672374[42] ? 6'd14 : - (_theResult____h672377[41] ? + (_theResult____h672374[41] ? 6'd15 : - (_theResult____h672377[40] ? + (_theResult____h672374[40] ? 6'd16 : - (_theResult____h672377[39] ? + (_theResult____h672374[39] ? 6'd17 : - (_theResult____h672377[38] ? + (_theResult____h672374[38] ? 6'd18 : - (_theResult____h672377[37] ? + (_theResult____h672374[37] ? 6'd19 : - (_theResult____h672377[36] ? + (_theResult____h672374[36] ? 6'd20 : - (_theResult____h672377[35] ? + (_theResult____h672374[35] ? 6'd21 : - (_theResult____h672377[34] ? + (_theResult____h672374[34] ? 6'd22 : - (_theResult____h672377[33] ? + (_theResult____h672374[33] ? 6'd23 : - (_theResult____h672377[32] ? + (_theResult____h672374[32] ? 6'd24 : - (_theResult____h672377[31] ? + (_theResult____h672374[31] ? 6'd25 : - (_theResult____h672377[30] ? + (_theResult____h672374[30] ? 6'd26 : - (_theResult____h672377[29] ? + (_theResult____h672374[29] ? 6'd27 : - (_theResult____h672377[28] ? + (_theResult____h672374[28] ? 6'd28 : - (_theResult____h672377[27] ? + (_theResult____h672374[27] ? 6'd29 : - (_theResult____h672377[26] ? + (_theResult____h672374[26] ? 6'd30 : - (_theResult____h672377[25] ? + (_theResult____h672374[25] ? 6'd31 : - (_theResult____h672377[24] ? + (_theResult____h672374[24] ? 6'd32 : - (_theResult____h672377[23] ? + (_theResult____h672374[23] ? 6'd33 : - (_theResult____h672377[22] ? + (_theResult____h672374[22] ? 6'd34 : - (_theResult____h672377[21] ? + (_theResult____h672374[21] ? 6'd35 : - (_theResult____h672377[20] ? + (_theResult____h672374[20] ? 6'd36 : - (_theResult____h672377[19] ? + (_theResult____h672374[19] ? 6'd37 : - (_theResult____h672377[18] ? + (_theResult____h672374[18] ? 6'd38 : - (_theResult____h672377[17] ? + (_theResult____h672374[17] ? 6'd39 : - (_theResult____h672377[16] ? + (_theResult____h672374[16] ? 6'd40 : - (_theResult____h672377[15] ? + (_theResult____h672374[15] ? 6'd41 : - (_theResult____h672377[14] ? + (_theResult____h672374[14] ? 6'd42 : - (_theResult____h672377[13] ? + (_theResult____h672374[13] ? 6'd43 : - (_theResult____h672377[12] ? + (_theResult____h672374[12] ? 6'd44 : - (_theResult____h672377[11] ? + (_theResult____h672374[11] ? 6'd45 : - (_theResult____h672377[10] ? + (_theResult____h672374[10] ? 6'd46 : - (_theResult____h672377[9] ? + (_theResult____h672374[9] ? 6'd47 : - (_theResult____h672377[8] ? + (_theResult____h672374[8] ? 6'd48 : - (_theResult____h672377[7] ? + (_theResult____h672374[7] ? 6'd49 : - (_theResult____h672377[6] ? + (_theResult____h672374[6] ? 6'd50 : - (_theResult____h672377[5] ? + (_theResult____h672374[5] ? 6'd51 : - (_theResult____h672377[4] ? + (_theResult____h672374[4] ? 6'd52 : - (_theResult____h672377[3] ? + (_theResult____h672374[3] ? 6'd53 : - (_theResult____h672377[2] ? + (_theResult____h672374[2] ? 6'd54 : - (_theResult____h672377[1] ? + (_theResult____h672374[1] ? 6'd55 : - (_theResult____h672377[0] ? + (_theResult____h672374[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d8461 = - (_theResult____h580879[56] ? + (_theResult____h580876[56] ? 6'd0 : - (_theResult____h580879[55] ? + (_theResult____h580876[55] ? 6'd1 : - (_theResult____h580879[54] ? + (_theResult____h580876[54] ? 6'd2 : - (_theResult____h580879[53] ? + (_theResult____h580876[53] ? 6'd3 : - (_theResult____h580879[52] ? + (_theResult____h580876[52] ? 6'd4 : - (_theResult____h580879[51] ? + (_theResult____h580876[51] ? 6'd5 : - (_theResult____h580879[50] ? + (_theResult____h580876[50] ? 6'd6 : - (_theResult____h580879[49] ? + (_theResult____h580876[49] ? 6'd7 : - (_theResult____h580879[48] ? + (_theResult____h580876[48] ? 6'd8 : - (_theResult____h580879[47] ? + (_theResult____h580876[47] ? 6'd9 : - (_theResult____h580879[46] ? + (_theResult____h580876[46] ? 6'd10 : - (_theResult____h580879[45] ? + (_theResult____h580876[45] ? 6'd11 : - (_theResult____h580879[44] ? + (_theResult____h580876[44] ? 6'd12 : - (_theResult____h580879[43] ? + (_theResult____h580876[43] ? 6'd13 : - (_theResult____h580879[42] ? + (_theResult____h580876[42] ? 6'd14 : - (_theResult____h580879[41] ? + (_theResult____h580876[41] ? 6'd15 : - (_theResult____h580879[40] ? + (_theResult____h580876[40] ? 6'd16 : - (_theResult____h580879[39] ? + (_theResult____h580876[39] ? 6'd17 : - (_theResult____h580879[38] ? + (_theResult____h580876[38] ? 6'd18 : - (_theResult____h580879[37] ? + (_theResult____h580876[37] ? 6'd19 : - (_theResult____h580879[36] ? + (_theResult____h580876[36] ? 6'd20 : - (_theResult____h580879[35] ? + (_theResult____h580876[35] ? 6'd21 : - (_theResult____h580879[34] ? + (_theResult____h580876[34] ? 6'd22 : - (_theResult____h580879[33] ? + (_theResult____h580876[33] ? 6'd23 : - (_theResult____h580879[32] ? + (_theResult____h580876[32] ? 6'd24 : - (_theResult____h580879[31] ? + (_theResult____h580876[31] ? 6'd25 : - (_theResult____h580879[30] ? + (_theResult____h580876[30] ? 6'd26 : - (_theResult____h580879[29] ? + (_theResult____h580876[29] ? 6'd27 : - (_theResult____h580879[28] ? + (_theResult____h580876[28] ? 6'd28 : - (_theResult____h580879[27] ? + (_theResult____h580876[27] ? 6'd29 : - (_theResult____h580879[26] ? + (_theResult____h580876[26] ? 6'd30 : - (_theResult____h580879[25] ? + (_theResult____h580876[25] ? 6'd31 : - (_theResult____h580879[24] ? + (_theResult____h580876[24] ? 6'd32 : - (_theResult____h580879[23] ? + (_theResult____h580876[23] ? 6'd33 : - (_theResult____h580879[22] ? + (_theResult____h580876[22] ? 6'd34 : - (_theResult____h580879[21] ? + (_theResult____h580876[21] ? 6'd35 : - (_theResult____h580879[20] ? + (_theResult____h580876[20] ? 6'd36 : - (_theResult____h580879[19] ? + (_theResult____h580876[19] ? 6'd37 : - (_theResult____h580879[18] ? + (_theResult____h580876[18] ? 6'd38 : - (_theResult____h580879[17] ? + (_theResult____h580876[17] ? 6'd39 : - (_theResult____h580879[16] ? + (_theResult____h580876[16] ? 6'd40 : - (_theResult____h580879[15] ? + (_theResult____h580876[15] ? 6'd41 : - (_theResult____h580879[14] ? + (_theResult____h580876[14] ? 6'd42 : - (_theResult____h580879[13] ? + (_theResult____h580876[13] ? 6'd43 : - (_theResult____h580879[12] ? + (_theResult____h580876[12] ? 6'd44 : - (_theResult____h580879[11] ? + (_theResult____h580876[11] ? 6'd45 : - (_theResult____h580879[10] ? + (_theResult____h580876[10] ? 6'd46 : - (_theResult____h580879[9] ? + (_theResult____h580876[9] ? 6'd47 : - (_theResult____h580879[8] ? + (_theResult____h580876[8] ? 6'd48 : - (_theResult____h580879[7] ? + (_theResult____h580876[7] ? 6'd49 : - (_theResult____h580879[6] ? + (_theResult____h580876[6] ? 6'd50 : - (_theResult____h580879[5] ? + (_theResult____h580876[5] ? 6'd51 : - (_theResult____h580879[4] ? + (_theResult____h580876[4] ? 6'd52 : - (_theResult____h580879[3] ? + (_theResult____h580876[3] ? 6'd53 : - (_theResult____h580879[2] ? + (_theResult____h580876[2] ? 6'd54 : - (_theResult____h580879[1] ? + (_theResult____h580876[1] ? 6'd55 : - (_theResult____h580879[0] ? + (_theResult____h580876[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d9858 = - (_theResult____h626630[56] ? + (_theResult____h626627[56] ? 6'd0 : - (_theResult____h626630[55] ? + (_theResult____h626627[55] ? 6'd1 : - (_theResult____h626630[54] ? + (_theResult____h626627[54] ? 6'd2 : - (_theResult____h626630[53] ? + (_theResult____h626627[53] ? 6'd3 : - (_theResult____h626630[52] ? + (_theResult____h626627[52] ? 6'd4 : - (_theResult____h626630[51] ? + (_theResult____h626627[51] ? 6'd5 : - (_theResult____h626630[50] ? + (_theResult____h626627[50] ? 6'd6 : - (_theResult____h626630[49] ? + (_theResult____h626627[49] ? 6'd7 : - (_theResult____h626630[48] ? + (_theResult____h626627[48] ? 6'd8 : - (_theResult____h626630[47] ? + (_theResult____h626627[47] ? 6'd9 : - (_theResult____h626630[46] ? + (_theResult____h626627[46] ? 6'd10 : - (_theResult____h626630[45] ? + (_theResult____h626627[45] ? 6'd11 : - (_theResult____h626630[44] ? + (_theResult____h626627[44] ? 6'd12 : - (_theResult____h626630[43] ? + (_theResult____h626627[43] ? 6'd13 : - (_theResult____h626630[42] ? + (_theResult____h626627[42] ? 6'd14 : - (_theResult____h626630[41] ? + (_theResult____h626627[41] ? 6'd15 : - (_theResult____h626630[40] ? + (_theResult____h626627[40] ? 6'd16 : - (_theResult____h626630[39] ? + (_theResult____h626627[39] ? 6'd17 : - (_theResult____h626630[38] ? + (_theResult____h626627[38] ? 6'd18 : - (_theResult____h626630[37] ? + (_theResult____h626627[37] ? 6'd19 : - (_theResult____h626630[36] ? + (_theResult____h626627[36] ? 6'd20 : - (_theResult____h626630[35] ? + (_theResult____h626627[35] ? 6'd21 : - (_theResult____h626630[34] ? + (_theResult____h626627[34] ? 6'd22 : - (_theResult____h626630[33] ? + (_theResult____h626627[33] ? 6'd23 : - (_theResult____h626630[32] ? + (_theResult____h626627[32] ? 6'd24 : - (_theResult____h626630[31] ? + (_theResult____h626627[31] ? 6'd25 : - (_theResult____h626630[30] ? + (_theResult____h626627[30] ? 6'd26 : - (_theResult____h626630[29] ? + (_theResult____h626627[29] ? 6'd27 : - (_theResult____h626630[28] ? + (_theResult____h626627[28] ? 6'd28 : - (_theResult____h626630[27] ? + (_theResult____h626627[27] ? 6'd29 : - (_theResult____h626630[26] ? + (_theResult____h626627[26] ? 6'd30 : - (_theResult____h626630[25] ? + (_theResult____h626627[25] ? 6'd31 : - (_theResult____h626630[24] ? + (_theResult____h626627[24] ? 6'd32 : - (_theResult____h626630[23] ? + (_theResult____h626627[23] ? 6'd33 : - (_theResult____h626630[22] ? + (_theResult____h626627[22] ? 6'd34 : - (_theResult____h626630[21] ? + (_theResult____h626627[21] ? 6'd35 : - (_theResult____h626630[20] ? + (_theResult____h626627[20] ? 6'd36 : - (_theResult____h626630[19] ? + (_theResult____h626627[19] ? 6'd37 : - (_theResult____h626630[18] ? + (_theResult____h626627[18] ? 6'd38 : - (_theResult____h626630[17] ? + (_theResult____h626627[17] ? 6'd39 : - (_theResult____h626630[16] ? + (_theResult____h626627[16] ? 6'd40 : - (_theResult____h626630[15] ? + (_theResult____h626627[15] ? 6'd41 : - (_theResult____h626630[14] ? + (_theResult____h626627[14] ? 6'd42 : - (_theResult____h626630[13] ? + (_theResult____h626627[13] ? 6'd43 : - (_theResult____h626630[12] ? + (_theResult____h626627[12] ? 6'd44 : - (_theResult____h626630[11] ? + (_theResult____h626627[11] ? 6'd45 : - (_theResult____h626630[10] ? + (_theResult____h626627[10] ? 6'd46 : - (_theResult____h626630[9] ? + (_theResult____h626627[9] ? 6'd47 : - (_theResult____h626630[8] ? + (_theResult____h626627[8] ? 6'd48 : - (_theResult____h626630[7] ? + (_theResult____h626627[7] ? 6'd49 : - (_theResult____h626630[6] ? + (_theResult____h626627[6] ? 6'd50 : - (_theResult____h626630[5] ? + (_theResult____h626627[5] ? 6'd51 : - (_theResult____h626630[4] ? + (_theResult____h626627[4] ? 6'd52 : - (_theResult____h626630[3] ? + (_theResult____h626627[3] ? 6'd53 : - (_theResult____h626630[2] ? + (_theResult____h626627[2] ? 6'd54 : - (_theResult____h626630[1] ? + (_theResult____h626627[1] ? 6'd55 : - (_theResult____h626630[0] ? + (_theResult____h626627[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d13152 = - (_theResult____h740561[56] ? + (_theResult____h740557[56] ? 6'd0 : - (_theResult____h740561[55] ? + (_theResult____h740557[55] ? 6'd1 : - (_theResult____h740561[54] ? + (_theResult____h740557[54] ? 6'd2 : - (_theResult____h740561[53] ? + (_theResult____h740557[53] ? 6'd3 : - (_theResult____h740561[52] ? + (_theResult____h740557[52] ? 6'd4 : - (_theResult____h740561[51] ? + (_theResult____h740557[51] ? 6'd5 : - (_theResult____h740561[50] ? + (_theResult____h740557[50] ? 6'd6 : - (_theResult____h740561[49] ? + (_theResult____h740557[49] ? 6'd7 : - (_theResult____h740561[48] ? + (_theResult____h740557[48] ? 6'd8 : - (_theResult____h740561[47] ? + (_theResult____h740557[47] ? 6'd9 : - (_theResult____h740561[46] ? + (_theResult____h740557[46] ? 6'd10 : - (_theResult____h740561[45] ? + (_theResult____h740557[45] ? 6'd11 : - (_theResult____h740561[44] ? + (_theResult____h740557[44] ? 6'd12 : - (_theResult____h740561[43] ? + (_theResult____h740557[43] ? 6'd13 : - (_theResult____h740561[42] ? + (_theResult____h740557[42] ? 6'd14 : - (_theResult____h740561[41] ? + (_theResult____h740557[41] ? 6'd15 : - (_theResult____h740561[40] ? + (_theResult____h740557[40] ? 6'd16 : - (_theResult____h740561[39] ? + (_theResult____h740557[39] ? 6'd17 : - (_theResult____h740561[38] ? + (_theResult____h740557[38] ? 6'd18 : - (_theResult____h740561[37] ? + (_theResult____h740557[37] ? 6'd19 : - (_theResult____h740561[36] ? + (_theResult____h740557[36] ? 6'd20 : - (_theResult____h740561[35] ? + (_theResult____h740557[35] ? 6'd21 : - (_theResult____h740561[34] ? + (_theResult____h740557[34] ? 6'd22 : - (_theResult____h740561[33] ? + (_theResult____h740557[33] ? 6'd23 : - (_theResult____h740561[32] ? + (_theResult____h740557[32] ? 6'd24 : - (_theResult____h740561[31] ? + (_theResult____h740557[31] ? 6'd25 : - (_theResult____h740561[30] ? + (_theResult____h740557[30] ? 6'd26 : - (_theResult____h740561[29] ? + (_theResult____h740557[29] ? 6'd27 : - (_theResult____h740561[28] ? + (_theResult____h740557[28] ? 6'd28 : - (_theResult____h740561[27] ? + (_theResult____h740557[27] ? 6'd29 : - (_theResult____h740561[26] ? + (_theResult____h740557[26] ? 6'd30 : - (_theResult____h740561[25] ? + (_theResult____h740557[25] ? 6'd31 : - (_theResult____h740561[24] ? + (_theResult____h740557[24] ? 6'd32 : - (_theResult____h740561[23] ? + (_theResult____h740557[23] ? 6'd33 : - (_theResult____h740561[22] ? + (_theResult____h740557[22] ? 6'd34 : - (_theResult____h740561[21] ? + (_theResult____h740557[21] ? 6'd35 : - (_theResult____h740561[20] ? + (_theResult____h740557[20] ? 6'd36 : - (_theResult____h740561[19] ? + (_theResult____h740557[19] ? 6'd37 : - (_theResult____h740561[18] ? + (_theResult____h740557[18] ? 6'd38 : - (_theResult____h740561[17] ? + (_theResult____h740557[17] ? 6'd39 : - (_theResult____h740561[16] ? + (_theResult____h740557[16] ? 6'd40 : - (_theResult____h740561[15] ? + (_theResult____h740557[15] ? 6'd41 : - (_theResult____h740561[14] ? + (_theResult____h740557[14] ? 6'd42 : - (_theResult____h740561[13] ? + (_theResult____h740557[13] ? 6'd43 : - (_theResult____h740561[12] ? + (_theResult____h740557[12] ? 6'd44 : - (_theResult____h740561[11] ? + (_theResult____h740557[11] ? 6'd45 : - (_theResult____h740561[10] ? + (_theResult____h740557[10] ? 6'd46 : - (_theResult____h740561[9] ? + (_theResult____h740557[9] ? 6'd47 : - (_theResult____h740561[8] ? + (_theResult____h740557[8] ? 6'd48 : - (_theResult____h740561[7] ? + (_theResult____h740557[7] ? 6'd49 : - (_theResult____h740561[6] ? + (_theResult____h740557[6] ? 6'd50 : - (_theResult____h740561[5] ? + (_theResult____h740557[5] ? 6'd51 : - (_theResult____h740561[4] ? + (_theResult____h740557[4] ? 6'd52 : - (_theResult____h740561[3] ? + (_theResult____h740557[3] ? 6'd53 : - (_theResult____h740561[2] ? + (_theResult____h740557[2] ? 6'd54 : - (_theResult____h740561[1] ? + (_theResult____h740557[1] ? 6'd55 : - (_theResult____h740561[0] ? + (_theResult____h740557[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d13867 = - (_theResult____h818718[56] ? + (_theResult____h818714[56] ? 6'd0 : - (_theResult____h818718[55] ? + (_theResult____h818714[55] ? 6'd1 : - (_theResult____h818718[54] ? + (_theResult____h818714[54] ? 6'd2 : - (_theResult____h818718[53] ? + (_theResult____h818714[53] ? 6'd3 : - (_theResult____h818718[52] ? + (_theResult____h818714[52] ? 6'd4 : - (_theResult____h818718[51] ? + (_theResult____h818714[51] ? 6'd5 : - (_theResult____h818718[50] ? + (_theResult____h818714[50] ? 6'd6 : - (_theResult____h818718[49] ? + (_theResult____h818714[49] ? 6'd7 : - (_theResult____h818718[48] ? + (_theResult____h818714[48] ? 6'd8 : - (_theResult____h818718[47] ? + (_theResult____h818714[47] ? 6'd9 : - (_theResult____h818718[46] ? + (_theResult____h818714[46] ? 6'd10 : - (_theResult____h818718[45] ? + (_theResult____h818714[45] ? 6'd11 : - (_theResult____h818718[44] ? + (_theResult____h818714[44] ? 6'd12 : - (_theResult____h818718[43] ? + (_theResult____h818714[43] ? 6'd13 : - (_theResult____h818718[42] ? + (_theResult____h818714[42] ? 6'd14 : - (_theResult____h818718[41] ? + (_theResult____h818714[41] ? 6'd15 : - (_theResult____h818718[40] ? + (_theResult____h818714[40] ? 6'd16 : - (_theResult____h818718[39] ? + (_theResult____h818714[39] ? 6'd17 : - (_theResult____h818718[38] ? + (_theResult____h818714[38] ? 6'd18 : - (_theResult____h818718[37] ? + (_theResult____h818714[37] ? 6'd19 : - (_theResult____h818718[36] ? + (_theResult____h818714[36] ? 6'd20 : - (_theResult____h818718[35] ? + (_theResult____h818714[35] ? 6'd21 : - (_theResult____h818718[34] ? + (_theResult____h818714[34] ? 6'd22 : - (_theResult____h818718[33] ? + (_theResult____h818714[33] ? 6'd23 : - (_theResult____h818718[32] ? + (_theResult____h818714[32] ? 6'd24 : - (_theResult____h818718[31] ? + (_theResult____h818714[31] ? 6'd25 : - (_theResult____h818718[30] ? + (_theResult____h818714[30] ? 6'd26 : - (_theResult____h818718[29] ? + (_theResult____h818714[29] ? 6'd27 : - (_theResult____h818718[28] ? + (_theResult____h818714[28] ? 6'd28 : - (_theResult____h818718[27] ? + (_theResult____h818714[27] ? 6'd29 : - (_theResult____h818718[26] ? + (_theResult____h818714[26] ? 6'd30 : - (_theResult____h818718[25] ? + (_theResult____h818714[25] ? 6'd31 : - (_theResult____h818718[24] ? + (_theResult____h818714[24] ? 6'd32 : - (_theResult____h818718[23] ? + (_theResult____h818714[23] ? 6'd33 : - (_theResult____h818718[22] ? + (_theResult____h818714[22] ? 6'd34 : - (_theResult____h818718[21] ? + (_theResult____h818714[21] ? 6'd35 : - (_theResult____h818718[20] ? + (_theResult____h818714[20] ? 6'd36 : - (_theResult____h818718[19] ? + (_theResult____h818714[19] ? 6'd37 : - (_theResult____h818718[18] ? + (_theResult____h818714[18] ? 6'd38 : - (_theResult____h818718[17] ? + (_theResult____h818714[17] ? 6'd39 : - (_theResult____h818718[16] ? + (_theResult____h818714[16] ? 6'd40 : - (_theResult____h818718[15] ? + (_theResult____h818714[15] ? 6'd41 : - (_theResult____h818718[14] ? + (_theResult____h818714[14] ? 6'd42 : - (_theResult____h818718[13] ? + (_theResult____h818714[13] ? 6'd43 : - (_theResult____h818718[12] ? + (_theResult____h818714[12] ? 6'd44 : - (_theResult____h818718[11] ? + (_theResult____h818714[11] ? 6'd45 : - (_theResult____h818718[10] ? + (_theResult____h818714[10] ? 6'd46 : - (_theResult____h818718[9] ? + (_theResult____h818714[9] ? 6'd47 : - (_theResult____h818718[8] ? + (_theResult____h818714[8] ? 6'd48 : - (_theResult____h818718[7] ? + (_theResult____h818714[7] ? 6'd49 : - (_theResult____h818718[6] ? + (_theResult____h818714[6] ? 6'd50 : - (_theResult____h818718[5] ? + (_theResult____h818714[5] ? 6'd51 : - (_theResult____h818718[4] ? + (_theResult____h818714[4] ? 6'd52 : - (_theResult____h818718[3] ? + (_theResult____h818714[3] ? 6'd53 : - (_theResult____h818718[2] ? + (_theResult____h818714[2] ? 6'd54 : - (_theResult____h818718[1] ? + (_theResult____h818714[1] ? 6'd55 : - (_theResult____h818718[0] ? + (_theResult____h818714[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d14637 = - (_theResult____h779414[56] ? + (_theResult____h779410[56] ? 6'd0 : - (_theResult____h779414[55] ? + (_theResult____h779410[55] ? 6'd1 : - (_theResult____h779414[54] ? + (_theResult____h779410[54] ? 6'd2 : - (_theResult____h779414[53] ? + (_theResult____h779410[53] ? 6'd3 : - (_theResult____h779414[52] ? + (_theResult____h779410[52] ? 6'd4 : - (_theResult____h779414[51] ? + (_theResult____h779410[51] ? 6'd5 : - (_theResult____h779414[50] ? + (_theResult____h779410[50] ? 6'd6 : - (_theResult____h779414[49] ? + (_theResult____h779410[49] ? 6'd7 : - (_theResult____h779414[48] ? + (_theResult____h779410[48] ? 6'd8 : - (_theResult____h779414[47] ? + (_theResult____h779410[47] ? 6'd9 : - (_theResult____h779414[46] ? + (_theResult____h779410[46] ? 6'd10 : - (_theResult____h779414[45] ? + (_theResult____h779410[45] ? 6'd11 : - (_theResult____h779414[44] ? + (_theResult____h779410[44] ? 6'd12 : - (_theResult____h779414[43] ? + (_theResult____h779410[43] ? 6'd13 : - (_theResult____h779414[42] ? + (_theResult____h779410[42] ? 6'd14 : - (_theResult____h779414[41] ? + (_theResult____h779410[41] ? 6'd15 : - (_theResult____h779414[40] ? + (_theResult____h779410[40] ? 6'd16 : - (_theResult____h779414[39] ? + (_theResult____h779410[39] ? 6'd17 : - (_theResult____h779414[38] ? + (_theResult____h779410[38] ? 6'd18 : - (_theResult____h779414[37] ? + (_theResult____h779410[37] ? 6'd19 : - (_theResult____h779414[36] ? + (_theResult____h779410[36] ? 6'd20 : - (_theResult____h779414[35] ? + (_theResult____h779410[35] ? 6'd21 : - (_theResult____h779414[34] ? + (_theResult____h779410[34] ? 6'd22 : - (_theResult____h779414[33] ? + (_theResult____h779410[33] ? 6'd23 : - (_theResult____h779414[32] ? + (_theResult____h779410[32] ? 6'd24 : - (_theResult____h779414[31] ? + (_theResult____h779410[31] ? 6'd25 : - (_theResult____h779414[30] ? + (_theResult____h779410[30] ? 6'd26 : - (_theResult____h779414[29] ? + (_theResult____h779410[29] ? 6'd27 : - (_theResult____h779414[28] ? + (_theResult____h779410[28] ? 6'd28 : - (_theResult____h779414[27] ? + (_theResult____h779410[27] ? 6'd29 : - (_theResult____h779414[26] ? + (_theResult____h779410[26] ? 6'd30 : - (_theResult____h779414[25] ? + (_theResult____h779410[25] ? 6'd31 : - (_theResult____h779414[24] ? + (_theResult____h779410[24] ? 6'd32 : - (_theResult____h779414[23] ? + (_theResult____h779410[23] ? 6'd33 : - (_theResult____h779414[22] ? + (_theResult____h779410[22] ? 6'd34 : - (_theResult____h779414[21] ? + (_theResult____h779410[21] ? 6'd35 : - (_theResult____h779414[20] ? + (_theResult____h779410[20] ? 6'd36 : - (_theResult____h779414[19] ? + (_theResult____h779410[19] ? 6'd37 : - (_theResult____h779414[18] ? + (_theResult____h779410[18] ? 6'd38 : - (_theResult____h779414[17] ? + (_theResult____h779410[17] ? 6'd39 : - (_theResult____h779414[16] ? + (_theResult____h779410[16] ? 6'd40 : - (_theResult____h779414[15] ? + (_theResult____h779410[15] ? 6'd41 : - (_theResult____h779414[14] ? + (_theResult____h779410[14] ? 6'd42 : - (_theResult____h779414[13] ? + (_theResult____h779410[13] ? 6'd43 : - (_theResult____h779414[12] ? + (_theResult____h779410[12] ? 6'd44 : - (_theResult____h779414[11] ? + (_theResult____h779410[11] ? 6'd45 : - (_theResult____h779414[10] ? + (_theResult____h779410[10] ? 6'd46 : - (_theResult____h779414[9] ? + (_theResult____h779410[9] ? 6'd47 : - (_theResult____h779414[8] ? + (_theResult____h779410[8] ? 6'd48 : - (_theResult____h779414[7] ? + (_theResult____h779410[7] ? 6'd49 : - (_theResult____h779414[6] ? + (_theResult____h779410[6] ? 6'd50 : - (_theResult____h779414[5] ? + (_theResult____h779410[5] ? 6'd51 : - (_theResult____h779414[4] ? + (_theResult____h779410[4] ? 6'd52 : - (_theResult____h779414[3] ? + (_theResult____h779410[3] ? 6'd53 : - (_theResult____h779414[2] ? + (_theResult____h779410[2] ? 6'd54 : - (_theResult____h779414[1] ? + (_theResult____h779410[1] ? 6'd55 : - (_theResult____h779414[0] ? + (_theResult____h779410[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d10409 = - (_theResult____h644267[56] ? + (_theResult____h644264[56] ? 6'd0 : - (_theResult____h644267[55] ? + (_theResult____h644264[55] ? 6'd1 : - (_theResult____h644267[54] ? + (_theResult____h644264[54] ? 6'd2 : - (_theResult____h644267[53] ? + (_theResult____h644264[53] ? 6'd3 : - (_theResult____h644267[52] ? + (_theResult____h644264[52] ? 6'd4 : - (_theResult____h644267[51] ? + (_theResult____h644264[51] ? 6'd5 : - (_theResult____h644267[50] ? + (_theResult____h644264[50] ? 6'd6 : - (_theResult____h644267[49] ? + (_theResult____h644264[49] ? 6'd7 : - (_theResult____h644267[48] ? + (_theResult____h644264[48] ? 6'd8 : - (_theResult____h644267[47] ? + (_theResult____h644264[47] ? 6'd9 : - (_theResult____h644267[46] ? + (_theResult____h644264[46] ? 6'd10 : - (_theResult____h644267[45] ? + (_theResult____h644264[45] ? 6'd11 : - (_theResult____h644267[44] ? + (_theResult____h644264[44] ? 6'd12 : - (_theResult____h644267[43] ? + (_theResult____h644264[43] ? 6'd13 : - (_theResult____h644267[42] ? + (_theResult____h644264[42] ? 6'd14 : - (_theResult____h644267[41] ? + (_theResult____h644264[41] ? 6'd15 : - (_theResult____h644267[40] ? + (_theResult____h644264[40] ? 6'd16 : - (_theResult____h644267[39] ? + (_theResult____h644264[39] ? 6'd17 : - (_theResult____h644267[38] ? + (_theResult____h644264[38] ? 6'd18 : - (_theResult____h644267[37] ? + (_theResult____h644264[37] ? 6'd19 : - (_theResult____h644267[36] ? + (_theResult____h644264[36] ? 6'd20 : - (_theResult____h644267[35] ? + (_theResult____h644264[35] ? 6'd21 : - (_theResult____h644267[34] ? + (_theResult____h644264[34] ? 6'd22 : - (_theResult____h644267[33] ? + (_theResult____h644264[33] ? 6'd23 : - (_theResult____h644267[32] ? + (_theResult____h644264[32] ? 6'd24 : - (_theResult____h644267[31] ? + (_theResult____h644264[31] ? 6'd25 : - (_theResult____h644267[30] ? + (_theResult____h644264[30] ? 6'd26 : - (_theResult____h644267[29] ? + (_theResult____h644264[29] ? 6'd27 : - (_theResult____h644267[28] ? + (_theResult____h644264[28] ? 6'd28 : - (_theResult____h644267[27] ? + (_theResult____h644264[27] ? 6'd29 : - (_theResult____h644267[26] ? + (_theResult____h644264[26] ? 6'd30 : - (_theResult____h644267[25] ? + (_theResult____h644264[25] ? 6'd31 : - (_theResult____h644267[24] ? + (_theResult____h644264[24] ? 6'd32 : - (_theResult____h644267[23] ? + (_theResult____h644264[23] ? 6'd33 : - (_theResult____h644267[22] ? + (_theResult____h644264[22] ? 6'd34 : - (_theResult____h644267[21] ? + (_theResult____h644264[21] ? 6'd35 : - (_theResult____h644267[20] ? + (_theResult____h644264[20] ? 6'd36 : - (_theResult____h644267[19] ? + (_theResult____h644264[19] ? 6'd37 : - (_theResult____h644267[18] ? + (_theResult____h644264[18] ? 6'd38 : - (_theResult____h644267[17] ? + (_theResult____h644264[17] ? 6'd39 : - (_theResult____h644267[16] ? + (_theResult____h644264[16] ? 6'd40 : - (_theResult____h644267[15] ? + (_theResult____h644264[15] ? 6'd41 : - (_theResult____h644267[14] ? + (_theResult____h644264[14] ? 6'd42 : - (_theResult____h644267[13] ? + (_theResult____h644264[13] ? 6'd43 : - (_theResult____h644267[12] ? + (_theResult____h644264[12] ? 6'd44 : - (_theResult____h644267[11] ? + (_theResult____h644264[11] ? 6'd45 : - (_theResult____h644267[10] ? + (_theResult____h644264[10] ? 6'd46 : - (_theResult____h644267[9] ? + (_theResult____h644264[9] ? 6'd47 : - (_theResult____h644267[8] ? + (_theResult____h644264[8] ? 6'd48 : - (_theResult____h644267[7] ? + (_theResult____h644264[7] ? 6'd49 : - (_theResult____h644267[6] ? + (_theResult____h644264[6] ? 6'd50 : - (_theResult____h644267[5] ? + (_theResult____h644264[5] ? 6'd51 : - (_theResult____h644267[4] ? + (_theResult____h644264[4] ? 6'd52 : - (_theResult____h644267[3] ? + (_theResult____h644264[3] ? 6'd53 : - (_theResult____h644267[2] ? + (_theResult____h644264[2] ? 6'd54 : - (_theResult____h644267[1] ? + (_theResult____h644264[1] ? 6'd55 : - (_theResult____h644267[0] ? + (_theResult____h644264[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d11806 = - (_theResult____h690014[56] ? + (_theResult____h690011[56] ? 6'd0 : - (_theResult____h690014[55] ? + (_theResult____h690011[55] ? 6'd1 : - (_theResult____h690014[54] ? + (_theResult____h690011[54] ? 6'd2 : - (_theResult____h690014[53] ? + (_theResult____h690011[53] ? 6'd3 : - (_theResult____h690014[52] ? + (_theResult____h690011[52] ? 6'd4 : - (_theResult____h690014[51] ? + (_theResult____h690011[51] ? 6'd5 : - (_theResult____h690014[50] ? + (_theResult____h690011[50] ? 6'd6 : - (_theResult____h690014[49] ? + (_theResult____h690011[49] ? 6'd7 : - (_theResult____h690014[48] ? + (_theResult____h690011[48] ? 6'd8 : - (_theResult____h690014[47] ? + (_theResult____h690011[47] ? 6'd9 : - (_theResult____h690014[46] ? + (_theResult____h690011[46] ? 6'd10 : - (_theResult____h690014[45] ? + (_theResult____h690011[45] ? 6'd11 : - (_theResult____h690014[44] ? + (_theResult____h690011[44] ? 6'd12 : - (_theResult____h690014[43] ? + (_theResult____h690011[43] ? 6'd13 : - (_theResult____h690014[42] ? + (_theResult____h690011[42] ? 6'd14 : - (_theResult____h690014[41] ? + (_theResult____h690011[41] ? 6'd15 : - (_theResult____h690014[40] ? + (_theResult____h690011[40] ? 6'd16 : - (_theResult____h690014[39] ? + (_theResult____h690011[39] ? 6'd17 : - (_theResult____h690014[38] ? + (_theResult____h690011[38] ? 6'd18 : - (_theResult____h690014[37] ? + (_theResult____h690011[37] ? 6'd19 : - (_theResult____h690014[36] ? + (_theResult____h690011[36] ? 6'd20 : - (_theResult____h690014[35] ? + (_theResult____h690011[35] ? 6'd21 : - (_theResult____h690014[34] ? + (_theResult____h690011[34] ? 6'd22 : - (_theResult____h690014[33] ? + (_theResult____h690011[33] ? 6'd23 : - (_theResult____h690014[32] ? + (_theResult____h690011[32] ? 6'd24 : - (_theResult____h690014[31] ? + (_theResult____h690011[31] ? 6'd25 : - (_theResult____h690014[30] ? + (_theResult____h690011[30] ? 6'd26 : - (_theResult____h690014[29] ? + (_theResult____h690011[29] ? 6'd27 : - (_theResult____h690014[28] ? + (_theResult____h690011[28] ? 6'd28 : - (_theResult____h690014[27] ? + (_theResult____h690011[27] ? 6'd29 : - (_theResult____h690014[26] ? + (_theResult____h690011[26] ? 6'd30 : - (_theResult____h690014[25] ? + (_theResult____h690011[25] ? 6'd31 : - (_theResult____h690014[24] ? + (_theResult____h690011[24] ? 6'd32 : - (_theResult____h690014[23] ? + (_theResult____h690011[23] ? 6'd33 : - (_theResult____h690014[22] ? + (_theResult____h690011[22] ? 6'd34 : - (_theResult____h690014[21] ? + (_theResult____h690011[21] ? 6'd35 : - (_theResult____h690014[20] ? + (_theResult____h690011[20] ? 6'd36 : - (_theResult____h690014[19] ? + (_theResult____h690011[19] ? 6'd37 : - (_theResult____h690014[18] ? + (_theResult____h690011[18] ? 6'd38 : - (_theResult____h690014[17] ? + (_theResult____h690011[17] ? 6'd39 : - (_theResult____h690014[16] ? + (_theResult____h690011[16] ? 6'd40 : - (_theResult____h690014[15] ? + (_theResult____h690011[15] ? 6'd41 : - (_theResult____h690014[14] ? + (_theResult____h690011[14] ? 6'd42 : - (_theResult____h690014[13] ? + (_theResult____h690011[13] ? 6'd43 : - (_theResult____h690014[12] ? + (_theResult____h690011[12] ? 6'd44 : - (_theResult____h690014[11] ? + (_theResult____h690011[11] ? 6'd45 : - (_theResult____h690014[10] ? + (_theResult____h690011[10] ? 6'd46 : - (_theResult____h690014[9] ? + (_theResult____h690011[9] ? 6'd47 : - (_theResult____h690014[8] ? + (_theResult____h690011[8] ? 6'd48 : - (_theResult____h690014[7] ? + (_theResult____h690011[7] ? 6'd49 : - (_theResult____h690014[6] ? + (_theResult____h690011[6] ? 6'd50 : - (_theResult____h690014[5] ? + (_theResult____h690011[5] ? 6'd51 : - (_theResult____h690014[4] ? + (_theResult____h690011[4] ? 6'd52 : - (_theResult____h690014[3] ? + (_theResult____h690011[3] ? 6'd53 : - (_theResult____h690014[2] ? + (_theResult____h690011[2] ? 6'd54 : - (_theResult____h690014[1] ? + (_theResult____h690011[1] ? 6'd55 : - (_theResult____h690014[0] ? + (_theResult____h690011[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d9012 = - (_theResult____h598518[56] ? + (_theResult____h598515[56] ? 6'd0 : - (_theResult____h598518[55] ? + (_theResult____h598515[55] ? 6'd1 : - (_theResult____h598518[54] ? + (_theResult____h598515[54] ? 6'd2 : - (_theResult____h598518[53] ? + (_theResult____h598515[53] ? 6'd3 : - (_theResult____h598518[52] ? + (_theResult____h598515[52] ? 6'd4 : - (_theResult____h598518[51] ? + (_theResult____h598515[51] ? 6'd5 : - (_theResult____h598518[50] ? + (_theResult____h598515[50] ? 6'd6 : - (_theResult____h598518[49] ? + (_theResult____h598515[49] ? 6'd7 : - (_theResult____h598518[48] ? + (_theResult____h598515[48] ? 6'd8 : - (_theResult____h598518[47] ? + (_theResult____h598515[47] ? 6'd9 : - (_theResult____h598518[46] ? + (_theResult____h598515[46] ? 6'd10 : - (_theResult____h598518[45] ? + (_theResult____h598515[45] ? 6'd11 : - (_theResult____h598518[44] ? + (_theResult____h598515[44] ? 6'd12 : - (_theResult____h598518[43] ? + (_theResult____h598515[43] ? 6'd13 : - (_theResult____h598518[42] ? + (_theResult____h598515[42] ? 6'd14 : - (_theResult____h598518[41] ? + (_theResult____h598515[41] ? 6'd15 : - (_theResult____h598518[40] ? + (_theResult____h598515[40] ? 6'd16 : - (_theResult____h598518[39] ? + (_theResult____h598515[39] ? 6'd17 : - (_theResult____h598518[38] ? + (_theResult____h598515[38] ? 6'd18 : - (_theResult____h598518[37] ? + (_theResult____h598515[37] ? 6'd19 : - (_theResult____h598518[36] ? + (_theResult____h598515[36] ? 6'd20 : - (_theResult____h598518[35] ? + (_theResult____h598515[35] ? 6'd21 : - (_theResult____h598518[34] ? + (_theResult____h598515[34] ? 6'd22 : - (_theResult____h598518[33] ? + (_theResult____h598515[33] ? 6'd23 : - (_theResult____h598518[32] ? + (_theResult____h598515[32] ? 6'd24 : - (_theResult____h598518[31] ? + (_theResult____h598515[31] ? 6'd25 : - (_theResult____h598518[30] ? + (_theResult____h598515[30] ? 6'd26 : - (_theResult____h598518[29] ? + (_theResult____h598515[29] ? 6'd27 : - (_theResult____h598518[28] ? + (_theResult____h598515[28] ? 6'd28 : - (_theResult____h598518[27] ? + (_theResult____h598515[27] ? 6'd29 : - (_theResult____h598518[26] ? + (_theResult____h598515[26] ? 6'd30 : - (_theResult____h598518[25] ? + (_theResult____h598515[25] ? 6'd31 : - (_theResult____h598518[24] ? + (_theResult____h598515[24] ? 6'd32 : - (_theResult____h598518[23] ? + (_theResult____h598515[23] ? 6'd33 : - (_theResult____h598518[22] ? + (_theResult____h598515[22] ? 6'd34 : - (_theResult____h598518[21] ? + (_theResult____h598515[21] ? 6'd35 : - (_theResult____h598518[20] ? + (_theResult____h598515[20] ? 6'd36 : - (_theResult____h598518[19] ? + (_theResult____h598515[19] ? 6'd37 : - (_theResult____h598518[18] ? + (_theResult____h598515[18] ? 6'd38 : - (_theResult____h598518[17] ? + (_theResult____h598515[17] ? 6'd39 : - (_theResult____h598518[16] ? + (_theResult____h598515[16] ? 6'd40 : - (_theResult____h598518[15] ? + (_theResult____h598515[15] ? 6'd41 : - (_theResult____h598518[14] ? + (_theResult____h598515[14] ? 6'd42 : - (_theResult____h598518[13] ? + (_theResult____h598515[13] ? 6'd43 : - (_theResult____h598518[12] ? + (_theResult____h598515[12] ? 6'd44 : - (_theResult____h598518[11] ? + (_theResult____h598515[11] ? 6'd45 : - (_theResult____h598518[10] ? + (_theResult____h598515[10] ? 6'd46 : - (_theResult____h598518[9] ? + (_theResult____h598515[9] ? 6'd47 : - (_theResult____h598518[8] ? + (_theResult____h598515[8] ? 6'd48 : - (_theResult____h598518[7] ? + (_theResult____h598515[7] ? 6'd49 : - (_theResult____h598518[6] ? + (_theResult____h598515[6] ? 6'd50 : - (_theResult____h598518[5] ? + (_theResult____h598515[5] ? 6'd51 : - (_theResult____h598518[4] ? + (_theResult____h598515[4] ? 6'd52 : - (_theResult____h598518[3] ? + (_theResult____h598515[3] ? 6'd53 : - (_theResult____h598518[2] ? + (_theResult____h598515[2] ? 6'd54 : - (_theResult____h598518[1] ? + (_theResult____h598515[1] ? 6'd55 : - (_theResult____h598518[0] ? + (_theResult____h598515[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d13196 = - (_theResult___fst_exp__h748797 == 11'd2047) ? + (_theResult___fst_exp__h748793 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : @@ -19619,10 +19617,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard40571_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q159 : + CASE_guard40567_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q159 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q160) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d13911 = - (_theResult___fst_exp__h826954 == 11'd2047) ? + (_theResult___fst_exp__h826950 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -19630,10 +19628,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard18728_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q174 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q175) ; + CASE_guard18724_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q176 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q177) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d14179 = - (_theResult___fst_exp__h826954 == 11'd2047) ? + (_theResult___fst_exp__h826950 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -19641,10 +19639,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard18728_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q180 : + CASE_guard18724_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q180 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q181) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d14681 = - (_theResult___fst_exp__h787650 == 11'd2047) ? + (_theResult___fst_exp__h787646 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -19652,10 +19650,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard79424_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q207 : + CASE_guard79420_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q207 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q208) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d14948 = - (_theResult___fst_exp__h787650 == 11'd2047) ? + (_theResult___fst_exp__h787646 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -19663,404 +19661,404 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard79424_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q211 : + CASE_guard79420_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q211 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q212) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d10568 = - (guard__h626640 == 2'b0 || + (guard__h626637 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - sfdin__h634733[56:34] : - _theResult___sfd__h635256 ; + sfdin__h634730[56:34] : + _theResult___sfd__h635253 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d10570 = - (guard__h626640 == 2'b0) ? - sfdin__h634733[56:34] : + (guard__h626637 == 2'b0) ? + sfdin__h634730[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h635256 : - sfdin__h634733[56:34]) ; + _theResult___sfd__h635253 : + sfdin__h634730[56:34]) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11318 = - (guard__h672387 == 2'b0 || + (guard__h672384 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h680486 : - _theResult___exp__h681002 ; + _theResult___fst_exp__h680483 : + _theResult___exp__h680999 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11321 = - (guard__h672387 == 2'b0) ? - _theResult___fst_exp__h680486 : + (guard__h672384 == 2'b0) ? + _theResult___fst_exp__h680483 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h681002 : - _theResult___fst_exp__h680486) ; + _theResult___exp__h680999 : + _theResult___fst_exp__h680483) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11965 = - (guard__h672387 == 2'b0 || + (guard__h672384 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - sfdin__h680480[56:34] : - _theResult___sfd__h681003 ; + sfdin__h680477[56:34] : + _theResult___sfd__h681000 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11967 = - (guard__h672387 == 2'b0) ? - sfdin__h680480[56:34] : + (guard__h672384 == 2'b0) ? + sfdin__h680477[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h681003 : - sfdin__h680480[56:34]) ; + _theResult___sfd__h681000 : + sfdin__h680477[56:34]) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d8524 = - (guard__h580889 == 2'b0 || + (guard__h580886 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h588990 : - _theResult___exp__h589506 ; + _theResult___fst_exp__h588987 : + _theResult___exp__h589503 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d8527 = - (guard__h580889 == 2'b0) ? - _theResult___fst_exp__h588990 : + (guard__h580886 == 2'b0) ? + _theResult___fst_exp__h588987 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h589506 : - _theResult___fst_exp__h588990) ; + _theResult___exp__h589503 : + _theResult___fst_exp__h588987) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9171 = - (guard__h580889 == 2'b0 || + (guard__h580886 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - sfdin__h588984[56:34] : - _theResult___sfd__h589507 ; + sfdin__h588981[56:34] : + _theResult___sfd__h589504 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9173 = - (guard__h580889 == 2'b0) ? - sfdin__h588984[56:34] : + (guard__h580886 == 2'b0) ? + sfdin__h588981[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h589507 : - sfdin__h588984[56:34]) ; + _theResult___sfd__h589504 : + sfdin__h588981[56:34]) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9921 = - (guard__h626640 == 2'b0 || + (guard__h626637 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h634739 : - _theResult___exp__h635255 ; + _theResult___fst_exp__h634736 : + _theResult___exp__h635252 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9924 = - (guard__h626640 == 2'b0) ? - _theResult___fst_exp__h634739 : + (guard__h626637 == 2'b0) ? + _theResult___fst_exp__h634736 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h635255 : - _theResult___fst_exp__h634739) ; + _theResult___exp__h635252 : + _theResult___fst_exp__h634736) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13313 = - (guard__h740571 == 2'b0 || + (guard__h740567 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___fst_exp__h748797 : - _theResult___exp__h749526 ; + _theResult___fst_exp__h748793 : + _theResult___exp__h749522 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13315 = - (guard__h740571 == 2'b0) ? - _theResult___fst_exp__h748797 : + (guard__h740567 == 2'b0) ? + _theResult___fst_exp__h748793 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___exp__h749526 : - _theResult___fst_exp__h748797) ; + _theResult___exp__h749522 : + _theResult___fst_exp__h748793) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13397 = - (guard__h740571 == 2'b0 || + (guard__h740567 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - sfdin__h748791[56:5] : - _theResult___sfd__h749527 ; + sfdin__h748787[56:5] : + _theResult___sfd__h749523 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13399 = - (guard__h740571 == 2'b0) ? - sfdin__h748791[56:5] : + (guard__h740567 == 2'b0) ? + sfdin__h748787[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___sfd__h749527 : - sfdin__h748791[56:5]) ; + _theResult___sfd__h749523 : + sfdin__h748787[56:5]) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14023 = - (guard__h818728 == 2'b0 || + (guard__h818724 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___fst_exp__h826954 : - _theResult___exp__h827683 ; + _theResult___fst_exp__h826950 : + _theResult___exp__h827679 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14025 = - (guard__h818728 == 2'b0) ? - _theResult___fst_exp__h826954 : + (guard__h818724 == 2'b0) ? + _theResult___fst_exp__h826950 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___exp__h827683 : - _theResult___fst_exp__h826954) ; + _theResult___exp__h827679 : + _theResult___fst_exp__h826950) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14106 = - (guard__h818728 == 2'b0 || + (guard__h818724 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - sfdin__h826948[56:5] : - _theResult___sfd__h827684 ; + sfdin__h826944[56:5] : + _theResult___sfd__h827680 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14108 = - (guard__h818728 == 2'b0) ? - sfdin__h826948[56:5] : + (guard__h818724 == 2'b0) ? + sfdin__h826944[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___sfd__h827684 : - sfdin__h826948[56:5]) ; + _theResult___sfd__h827680 : + sfdin__h826944[56:5]) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14793 = - (guard__h779424 == 2'b0 || + (guard__h779420 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___fst_exp__h787650 : - _theResult___exp__h788379 ; + _theResult___fst_exp__h787646 : + _theResult___exp__h788375 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14795 = - (guard__h779424 == 2'b0) ? - _theResult___fst_exp__h787650 : + (guard__h779420 == 2'b0) ? + _theResult___fst_exp__h787646 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___exp__h788379 : - _theResult___fst_exp__h787650) ; + _theResult___exp__h788375 : + _theResult___fst_exp__h787646) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14876 = - (guard__h779424 == 2'b0 || + (guard__h779420 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - sfdin__h787644[56:5] : - _theResult___sfd__h788380 ; + sfdin__h787640[56:5] : + _theResult___sfd__h788376 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14878 = - (guard__h779424 == 2'b0) ? - sfdin__h787644[56:5] : + (guard__h779420 == 2'b0) ? + sfdin__h787640[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___sfd__h788380 : - sfdin__h787644[56:5]) ; + _theResult___sfd__h788376 : + sfdin__h787640[56:5]) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10468 = - (guard__h644277 == 2'b0 || + (guard__h644274 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h652505 : - _theResult___exp__h653021 ; + _theResult___fst_exp__h652502 : + _theResult___exp__h653018 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10470 = - (guard__h644277 == 2'b0) ? - _theResult___fst_exp__h652505 : + (guard__h644274 == 2'b0) ? + _theResult___fst_exp__h652502 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h653021 : - _theResult___fst_exp__h652505) ; + _theResult___exp__h653018 : + _theResult___fst_exp__h652502) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10614 = - (guard__h644277 == 2'b0 || + (guard__h644274 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - sfdin__h652499[56:34] : - _theResult___sfd__h653022 ; + sfdin__h652496[56:34] : + _theResult___sfd__h653019 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10616 = - (guard__h644277 == 2'b0) ? - sfdin__h652499[56:34] : + (guard__h644274 == 2'b0) ? + sfdin__h652496[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h653022 : - sfdin__h652499[56:34]) ; + _theResult___sfd__h653019 : + sfdin__h652496[56:34]) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11865 = - (guard__h690024 == 2'b0 || + (guard__h690021 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h698252 : - _theResult___exp__h698768 ; + _theResult___fst_exp__h698249 : + _theResult___exp__h698765 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11867 = - (guard__h690024 == 2'b0) ? - _theResult___fst_exp__h698252 : + (guard__h690021 == 2'b0) ? + _theResult___fst_exp__h698249 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h698768 : - _theResult___fst_exp__h698252) ; + _theResult___exp__h698765 : + _theResult___fst_exp__h698249) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d12011 = - (guard__h690024 == 2'b0 || + (guard__h690021 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - sfdin__h698246[56:34] : - _theResult___sfd__h698769 ; + sfdin__h698243[56:34] : + _theResult___sfd__h698766 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d12013 = - (guard__h690024 == 2'b0) ? - sfdin__h698246[56:34] : + (guard__h690021 == 2'b0) ? + sfdin__h698243[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h698769 : - sfdin__h698246[56:34]) ; + _theResult___sfd__h698766 : + sfdin__h698243[56:34]) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9071 = - (guard__h598528 == 2'b0 || + (guard__h598525 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h606756 : - _theResult___exp__h607272 ; + _theResult___fst_exp__h606753 : + _theResult___exp__h607269 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9073 = - (guard__h598528 == 2'b0) ? - _theResult___fst_exp__h606756 : + (guard__h598525 == 2'b0) ? + _theResult___fst_exp__h606753 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h607272 : - _theResult___fst_exp__h606756) ; + _theResult___exp__h607269 : + _theResult___fst_exp__h606753) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9217 = - (guard__h598528 == 2'b0 || + (guard__h598525 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - sfdin__h606750[56:34] : - _theResult___sfd__h607273 ; + sfdin__h606747[56:34] : + _theResult___sfd__h607270 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9219 = - (guard__h598528 == 2'b0) ? - sfdin__h606750[56:34] : + (guard__h598525 == 2'b0) ? + sfdin__h606747[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h607273 : - sfdin__h606750[56:34]) ; + _theResult___sfd__h607270 : + sfdin__h606747[56:34]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13270 = - (guard__h731259 == 2'b0 || + (guard__h731255 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___fst_exp__h739220 : - _theResult___exp__h739875 ; + _theResult___fst_exp__h739216 : + _theResult___exp__h739871 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13272 = - (guard__h731259 == 2'b0) ? - _theResult___fst_exp__h739220 : + (guard__h731255 == 2'b0) ? + _theResult___fst_exp__h739216 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___exp__h739875 : - _theResult___fst_exp__h739220) ; + _theResult___exp__h739871 : + _theResult___fst_exp__h739216) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13344 = - (guard__h749640 == 2'b0 || + (guard__h749636 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___fst_exp__h757630 : - _theResult___exp__h758310 ; + _theResult___fst_exp__h757626 : + _theResult___exp__h758306 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13346 = - (guard__h749640 == 2'b0) ? - _theResult___fst_exp__h757630 : + (guard__h749636 == 2'b0) ? + _theResult___fst_exp__h757626 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___exp__h758310 : - _theResult___fst_exp__h757630) ; + _theResult___exp__h758306 : + _theResult___fst_exp__h757626) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13370 = - (guard__h731259 == 2'b0 || + (guard__h731255 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___snd__h739171[56:5] : - _theResult___sfd__h739876 ; + _theResult___snd__h739167[56:5] : + _theResult___sfd__h739872 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13372 = - (guard__h731259 == 2'b0) ? - _theResult___snd__h739171[56:5] : + (guard__h731255 == 2'b0) ? + _theResult___snd__h739167[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___sfd__h739876 : - _theResult___snd__h739171[56:5]) ; + _theResult___sfd__h739872 : + _theResult___snd__h739167[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13416 = - (guard__h749640 == 2'b0 || + (guard__h749636 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___snd__h757576[56:5] : - _theResult___sfd__h758311 ; + _theResult___snd__h757572[56:5] : + _theResult___sfd__h758307 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13418 = - (guard__h749640 == 2'b0) ? - _theResult___snd__h757576[56:5] : + (guard__h749636 == 2'b0) ? + _theResult___snd__h757572[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___sfd__h758311 : - _theResult___snd__h757576[56:5]) ; + _theResult___sfd__h758307 : + _theResult___snd__h757572[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13985 = - (guard__h809416 == 2'b0 || + (guard__h809412 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___fst_exp__h817377 : - _theResult___exp__h818032 ; + _theResult___fst_exp__h817373 : + _theResult___exp__h818028 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13987 = - (guard__h809416 == 2'b0) ? - _theResult___fst_exp__h817377 : + (guard__h809412 == 2'b0) ? + _theResult___fst_exp__h817373 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___exp__h818032 : - _theResult___fst_exp__h817377) ; + _theResult___exp__h818028 : + _theResult___fst_exp__h817373) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14054 = - (guard__h827797 == 2'b0 || + (guard__h827793 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___fst_exp__h835787 : - _theResult___exp__h836467 ; + _theResult___fst_exp__h835783 : + _theResult___exp__h836463 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14056 = - (guard__h827797 == 2'b0) ? - _theResult___fst_exp__h835787 : + (guard__h827793 == 2'b0) ? + _theResult___fst_exp__h835783 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___exp__h836467 : - _theResult___fst_exp__h835787) ; + _theResult___exp__h836463 : + _theResult___fst_exp__h835783) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14080 = - (guard__h809416 == 2'b0 || + (guard__h809412 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___snd__h817328[56:5] : - _theResult___sfd__h818033 ; + _theResult___snd__h817324[56:5] : + _theResult___sfd__h818029 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14082 = - (guard__h809416 == 2'b0) ? - _theResult___snd__h817328[56:5] : + (guard__h809412 == 2'b0) ? + _theResult___snd__h817324[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___sfd__h818033 : - _theResult___snd__h817328[56:5]) ; + _theResult___sfd__h818029 : + _theResult___snd__h817324[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14125 = - (guard__h827797 == 2'b0 || + (guard__h827793 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___snd__h835733[56:5] : - _theResult___sfd__h836468 ; + _theResult___snd__h835729[56:5] : + _theResult___sfd__h836464 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14127 = - (guard__h827797 == 2'b0) ? - _theResult___snd__h835733[56:5] : + (guard__h827793 == 2'b0) ? + _theResult___snd__h835729[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___sfd__h836468 : - _theResult___snd__h835733[56:5]) ; + _theResult___sfd__h836464 : + _theResult___snd__h835729[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14755 = - (guard__h770112 == 2'b0 || + (guard__h770108 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___fst_exp__h778073 : - _theResult___exp__h778728 ; + _theResult___fst_exp__h778069 : + _theResult___exp__h778724 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14757 = - (guard__h770112 == 2'b0) ? - _theResult___fst_exp__h778073 : + (guard__h770108 == 2'b0) ? + _theResult___fst_exp__h778069 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___exp__h778728 : - _theResult___fst_exp__h778073) ; + _theResult___exp__h778724 : + _theResult___fst_exp__h778069) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14824 = - (guard__h788493 == 2'b0 || + (guard__h788489 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___fst_exp__h796483 : - _theResult___exp__h797163 ; + _theResult___fst_exp__h796479 : + _theResult___exp__h797159 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14826 = - (guard__h788493 == 2'b0) ? - _theResult___fst_exp__h796483 : + (guard__h788489 == 2'b0) ? + _theResult___fst_exp__h796479 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___exp__h797163 : - _theResult___fst_exp__h796483) ; + _theResult___exp__h797159 : + _theResult___fst_exp__h796479) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14850 = - (guard__h770112 == 2'b0 || + (guard__h770108 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___snd__h778024[56:5] : - _theResult___sfd__h778729 ; + _theResult___snd__h778020[56:5] : + _theResult___sfd__h778725 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14852 = - (guard__h770112 == 2'b0) ? - _theResult___snd__h778024[56:5] : + (guard__h770108 == 2'b0) ? + _theResult___snd__h778020[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___sfd__h778729 : - _theResult___snd__h778024[56:5]) ; + _theResult___sfd__h778725 : + _theResult___snd__h778020[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14895 = - (guard__h788493 == 2'b0 || + (guard__h788489 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___snd__h796429[56:5] : - _theResult___sfd__h797164 ; + _theResult___snd__h796425[56:5] : + _theResult___sfd__h797160 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14897 = - (guard__h788493 == 2'b0) ? - _theResult___snd__h796429[56:5] : + (guard__h788489 == 2'b0) ? + _theResult___snd__h796425[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___sfd__h797164 : - _theResult___snd__h796429[56:5]) ; + _theResult___sfd__h797160 : + _theResult___snd__h796425[56:5]) ; assign IF_IF_IF_NOT_csrf_prv_reg_read__0574_EQ_3_0575_ETC___d21217 = (IF_IF_NOT_csrf_prv_reg_read__0574_EQ_3_0575_05_ETC___d20611[0] || IF_IF_NOT_csrf_prv_reg_read__0574_EQ_3_0575_05_ETC___d20611[1] || @@ -20272,139 +20270,139 @@ module mkCore(CLK, IF_checkForException_0942_BITS_3_TO_0_1195_EQ__ETC___d21215 == 4'd9 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10143 = - (guard__h635347 == 2'b0 || + (guard__h635344 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h643395 : - _theResult___exp__h643837 ; + _theResult___fst_exp__h643392 : + _theResult___exp__h643834 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10145 = - (guard__h635347 == 2'b0) ? - _theResult___fst_exp__h643395 : + (guard__h635344 == 2'b0) ? + _theResult___fst_exp__h643392 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h643837 : - _theResult___fst_exp__h643395) ; + _theResult___exp__h643834 : + _theResult___fst_exp__h643392) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10537 = - (guard__h653113 == 2'b0 || + (guard__h653110 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h661190 : - _theResult___exp__h661657 ; + _theResult___fst_exp__h661187 : + _theResult___exp__h661654 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10539 = - (guard__h653113 == 2'b0) ? - _theResult___fst_exp__h661190 : + (guard__h653110 == 2'b0) ? + _theResult___fst_exp__h661187 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h661657 : - _theResult___fst_exp__h661190) ; + _theResult___exp__h661654 : + _theResult___fst_exp__h661187) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10587 = - (guard__h635347 == 2'b0 || + (guard__h635344 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___snd__h643346[56:34] : - _theResult___sfd__h643838 ; + _theResult___snd__h643343[56:34] : + _theResult___sfd__h643835 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10589 = - (guard__h635347 == 2'b0) ? - _theResult___snd__h643346[56:34] : + (guard__h635344 == 2'b0) ? + _theResult___snd__h643343[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h643838 : - _theResult___snd__h643346[56:34]) ; + _theResult___sfd__h643835 : + _theResult___snd__h643343[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10633 = - (guard__h653113 == 2'b0 || + (guard__h653110 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___snd__h661136[56:34] : - _theResult___sfd__h661658 ; + _theResult___snd__h661133[56:34] : + _theResult___sfd__h661655 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10635 = - (guard__h653113 == 2'b0) ? - _theResult___snd__h661136[56:34] : + (guard__h653110 == 2'b0) ? + _theResult___snd__h661133[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h661658 : - _theResult___snd__h661136[56:34]) ; + _theResult___sfd__h661655 : + _theResult___snd__h661133[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11540 = - (guard__h681094 == 2'b0 || + (guard__h681091 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h689142 : - _theResult___exp__h689584 ; + _theResult___fst_exp__h689139 : + _theResult___exp__h689581 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11542 = - (guard__h681094 == 2'b0) ? - _theResult___fst_exp__h689142 : + (guard__h681091 == 2'b0) ? + _theResult___fst_exp__h689139 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h689584 : - _theResult___fst_exp__h689142) ; + _theResult___exp__h689581 : + _theResult___fst_exp__h689139) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11934 = - (guard__h698860 == 2'b0 || + (guard__h698857 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h706937 : - _theResult___exp__h707404 ; + _theResult___fst_exp__h706934 : + _theResult___exp__h707401 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11936 = - (guard__h698860 == 2'b0) ? - _theResult___fst_exp__h706937 : + (guard__h698857 == 2'b0) ? + _theResult___fst_exp__h706934 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h707404 : - _theResult___fst_exp__h706937) ; + _theResult___exp__h707401 : + _theResult___fst_exp__h706934) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11984 = - (guard__h681094 == 2'b0 || + (guard__h681091 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___snd__h689093[56:34] : - _theResult___sfd__h689585 ; + _theResult___snd__h689090[56:34] : + _theResult___sfd__h689582 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11986 = - (guard__h681094 == 2'b0) ? - _theResult___snd__h689093[56:34] : + (guard__h681091 == 2'b0) ? + _theResult___snd__h689090[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h689585 : - _theResult___snd__h689093[56:34]) ; + _theResult___sfd__h689582 : + _theResult___snd__h689090[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d12030 = - (guard__h698860 == 2'b0 || + (guard__h698857 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___snd__h706883[56:34] : - _theResult___sfd__h707405 ; + _theResult___snd__h706880[56:34] : + _theResult___sfd__h707402 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d12032 = - (guard__h698860 == 2'b0) ? - _theResult___snd__h706883[56:34] : + (guard__h698857 == 2'b0) ? + _theResult___snd__h706880[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h707405 : - _theResult___snd__h706883[56:34]) ; + _theResult___sfd__h707402 : + _theResult___snd__h706880[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d8746 = - (guard__h589598 == 2'b0 || + (guard__h589595 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h597646 : - _theResult___exp__h598088 ; + _theResult___fst_exp__h597643 : + _theResult___exp__h598085 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d8748 = - (guard__h589598 == 2'b0) ? - _theResult___fst_exp__h597646 : + (guard__h589595 == 2'b0) ? + _theResult___fst_exp__h597643 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h598088 : - _theResult___fst_exp__h597646) ; + _theResult___exp__h598085 : + _theResult___fst_exp__h597643) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9140 = - (guard__h607364 == 2'b0 || + (guard__h607361 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h615441 : - _theResult___exp__h615908 ; + _theResult___fst_exp__h615438 : + _theResult___exp__h615905 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9142 = - (guard__h607364 == 2'b0) ? - _theResult___fst_exp__h615441 : + (guard__h607361 == 2'b0) ? + _theResult___fst_exp__h615438 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h615908 : - _theResult___fst_exp__h615441) ; + _theResult___exp__h615905 : + _theResult___fst_exp__h615438) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9190 = - (guard__h589598 == 2'b0 || + (guard__h589595 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___snd__h597597[56:34] : - _theResult___sfd__h598089 ; + _theResult___snd__h597594[56:34] : + _theResult___sfd__h598086 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9192 = - (guard__h589598 == 2'b0) ? - _theResult___snd__h597597[56:34] : + (guard__h589595 == 2'b0) ? + _theResult___snd__h597594[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h598089 : - _theResult___snd__h597597[56:34]) ; + _theResult___sfd__h598086 : + _theResult___snd__h597594[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9236 = - (guard__h607364 == 2'b0 || + (guard__h607361 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___snd__h615387[56:34] : - _theResult___sfd__h615909 ; + _theResult___snd__h615384[56:34] : + _theResult___sfd__h615906 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9238 = - (guard__h607364 == 2'b0) ? - _theResult___snd__h615387[56:34] : + (guard__h607361 == 2'b0) ? + _theResult___snd__h615384[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h615909 : - _theResult___snd__h615387[56:34]) ; + _theResult___sfd__h615906 : + _theResult___snd__h615384[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d13242 = - (_theResult___fst_exp__h757630 == 11'd2047) ? + (_theResult___fst_exp__h757626 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : @@ -20412,10 +20410,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard49640_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q161 : + CASE_guard49636_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q161 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q162) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d13957 = - (_theResult___fst_exp__h835787 == 11'd2047) ? + (_theResult___fst_exp__h835783 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -20423,10 +20421,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard27797_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q178 : + CASE_guard27793_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q178 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q179) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d14164 = - (_theResult___fst_exp__h817377 == 11'd2047) ? + (_theResult___fst_exp__h817373 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -20434,10 +20432,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard09416_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q184 : + CASE_guard09412_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q184 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q185) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d14191 = - (_theResult___fst_exp__h835787 == 11'd2047) ? + (_theResult___fst_exp__h835783 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -20445,10 +20443,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard27797_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q182 : + CASE_guard27793_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q182 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q183) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d14727 = - (_theResult___fst_exp__h796483 == 11'd2047) ? + (_theResult___fst_exp__h796479 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -20456,10 +20454,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard88493_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q209 : + CASE_guard88489_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q209 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q210) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d14933 = - (_theResult___fst_exp__h778073 == 11'd2047) ? + (_theResult___fst_exp__h778069 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -20467,25 +20465,25 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard70112_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q213 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q214) ; - assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d14960 = - (_theResult___fst_exp__h796483 == 11'd2047) ? - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != - 32'hFFFFFFFF || - !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard88493_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q215 : + CASE_guard70108_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q215 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q216) ; + assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d14960 = + (_theResult___fst_exp__h796479 == 11'd2047) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : + ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? + CASE_guard88489_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q213 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q214) ; assign IF_IF_NOT_csrf_prv_reg_read__0574_EQ_3_0575_05_ETC___d20611 = - (_theResult____h928986 == 16'd0 && + (_theResult____h928983 == 16'd0 && (csrf_prv_reg == 2'd0 || csrf_prv_reg == 2'd1 && csrf_ie_vec_1)) ? - enabled_ints__h929557 : - _theResult____h928986 ; + enabled_ints__h929554 : + _theResult____h928983 ; assign IF_IF_NOT_csrf_prv_reg_read__0574_EQ_3_0575_05_ETC___d20964 = IF_IF_NOT_csrf_prv_reg_read__0574_EQ_3_0575_05_ETC___d20611[0] || IF_IF_NOT_csrf_prv_reg_read__0574_EQ_3_0575_05_ETC___d20611[1] || @@ -20930,148 +20928,148 @@ module mkCore(CLK, 5'd0 : IF_IF_coreFix_aluExe_1_exeToFinQ_first__8058_B_ETC___d18203 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d12840 = - ((f1_exp__h719832 == 8'd0) ? - (f1_sfd__h719833[22] ? + ((f1_exp__h719828 == 8'd0) ? + (f1_sfd__h719829[22] ? 6'd2 : - (f1_sfd__h719833[21] ? + (f1_sfd__h719829[21] ? 6'd3 : - (f1_sfd__h719833[20] ? + (f1_sfd__h719829[20] ? 6'd4 : - (f1_sfd__h719833[19] ? + (f1_sfd__h719829[19] ? 6'd5 : - (f1_sfd__h719833[18] ? + (f1_sfd__h719829[18] ? 6'd6 : - (f1_sfd__h719833[17] ? + (f1_sfd__h719829[17] ? 6'd7 : - (f1_sfd__h719833[16] ? + (f1_sfd__h719829[16] ? 6'd8 : - (f1_sfd__h719833[15] ? + (f1_sfd__h719829[15] ? 6'd9 : - (f1_sfd__h719833[14] ? + (f1_sfd__h719829[14] ? 6'd10 : - (f1_sfd__h719833[13] ? + (f1_sfd__h719829[13] ? 6'd11 : - (f1_sfd__h719833[12] ? + (f1_sfd__h719829[12] ? 6'd12 : - (f1_sfd__h719833[11] ? + (f1_sfd__h719829[11] ? 6'd13 : - (f1_sfd__h719833[10] ? + (f1_sfd__h719829[10] ? 6'd14 : - (f1_sfd__h719833[9] ? + (f1_sfd__h719829[9] ? 6'd15 : - (f1_sfd__h719833[8] ? + (f1_sfd__h719829[8] ? 6'd16 : - (f1_sfd__h719833[7] ? + (f1_sfd__h719829[7] ? 6'd17 : - (f1_sfd__h719833[6] ? + (f1_sfd__h719829[6] ? 6'd18 : - (f1_sfd__h719833[5] ? + (f1_sfd__h719829[5] ? 6'd19 : - (f1_sfd__h719833[4] ? + (f1_sfd__h719829[4] ? 6'd20 : - (f1_sfd__h719833[3] ? + (f1_sfd__h719829[3] ? 6'd21 : - (f1_sfd__h719833[2] ? + (f1_sfd__h719829[2] ? 6'd22 : - (f1_sfd__h719833[1] ? + (f1_sfd__h719829[1] ? 6'd23 : - (f1_sfd__h719833[0] ? + (f1_sfd__h719829[0] ? 6'd24 : 6'd57))))))))))))))))))))))) : 6'd1) - 6'd1 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13246 = - (f1_exp__h719832 == 8'd255 && f1_sfd__h719833 != 23'd0 || - (f1_exp__h719832 == 8'd255 || f1_exp__h719832 == 8'd0) && - f1_sfd__h719833 == 23'd0) ? + (f1_exp__h719828 == 8'd255 && f1_sfd__h719829 != 23'd0 || + (f1_exp__h719828 == 8'd255 || f1_exp__h719828 == 8'd0) && + f1_sfd__h719829 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - ((f1_exp__h719832 == 8'd0) ? + ((f1_exp__h719828 == 8'd0) ? IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d12901 : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d13244) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13429 = - (f1_exp__h719832 == 8'd255 && f1_sfd__h719833 != 23'd0) ? - _theResult___snd_fst_sfd__h720148 : - _theResult___fst_sfd__h758429 ; + (f1_exp__h719828 == 8'd255 && f1_sfd__h719829 != 23'd0) ? + _theResult___snd_fst_sfd__h720144 : + _theResult___fst_sfd__h758425 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13430 = { IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13246, - (f1_exp__h719832 == 8'd255) ? + (f1_exp__h719828 == 8'd255) ? 11'd2047 : - _theResult___fst_exp__h758425, + _theResult___fst_exp__h758421, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13429 } ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13570 = - ((f3_exp__h798130 == 8'd0) ? - (f3_sfd__h798131[22] ? + ((f3_exp__h798126 == 8'd0) ? + (f3_sfd__h798127[22] ? 6'd2 : - (f3_sfd__h798131[21] ? + (f3_sfd__h798127[21] ? 6'd3 : - (f3_sfd__h798131[20] ? + (f3_sfd__h798127[20] ? 6'd4 : - (f3_sfd__h798131[19] ? + (f3_sfd__h798127[19] ? 6'd5 : - (f3_sfd__h798131[18] ? + (f3_sfd__h798127[18] ? 6'd6 : - (f3_sfd__h798131[17] ? + (f3_sfd__h798127[17] ? 6'd7 : - (f3_sfd__h798131[16] ? + (f3_sfd__h798127[16] ? 6'd8 : - (f3_sfd__h798131[15] ? + (f3_sfd__h798127[15] ? 6'd9 : - (f3_sfd__h798131[14] ? + (f3_sfd__h798127[14] ? 6'd10 : - (f3_sfd__h798131[13] ? + (f3_sfd__h798127[13] ? 6'd11 : - (f3_sfd__h798131[12] ? + (f3_sfd__h798127[12] ? 6'd12 : - (f3_sfd__h798131[11] ? + (f3_sfd__h798127[11] ? 6'd13 : - (f3_sfd__h798131[10] ? + (f3_sfd__h798127[10] ? 6'd14 : - (f3_sfd__h798131[9] ? + (f3_sfd__h798127[9] ? 6'd15 : - (f3_sfd__h798131[8] ? + (f3_sfd__h798127[8] ? 6'd16 : - (f3_sfd__h798131[7] ? + (f3_sfd__h798127[7] ? 6'd17 : - (f3_sfd__h798131[6] ? + (f3_sfd__h798127[6] ? 6'd18 : - (f3_sfd__h798131[5] ? + (f3_sfd__h798127[5] ? 6'd19 : - (f3_sfd__h798131[4] ? + (f3_sfd__h798127[4] ? 6'd20 : - (f3_sfd__h798131[3] ? + (f3_sfd__h798127[3] ? 6'd21 : - (f3_sfd__h798131[2] ? + (f3_sfd__h798127[2] ? 6'd22 : - (f3_sfd__h798131[1] ? + (f3_sfd__h798127[1] ? 6'd23 : - (f3_sfd__h798131[0] ? + (f3_sfd__h798127[0] ? 6'd24 : 6'd57))))))))))))))))))))))) : 6'd1) - 6'd1 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13961 = - (f3_exp__h798130 == 8'd255 && f3_sfd__h798131 != 23'd0 || - (f3_exp__h798130 == 8'd255 || f3_exp__h798130 == 8'd0) && - f3_sfd__h798131 == 23'd0) ? + (f3_exp__h798126 == 8'd255 && f3_sfd__h798127 != 23'd0 || + (f3_exp__h798126 == 8'd255 || f3_exp__h798126 == 8'd0) && + f3_sfd__h798127 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - ((f3_exp__h798130 == 8'd0) ? + ((f3_exp__h798126 == 8'd0) ? IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d13616 : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d13959) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14138 = - (f3_exp__h798130 == 8'd255 && f3_sfd__h798131 != 23'd0) ? - _theResult___snd_fst_sfd__h798446 : - _theResult___fst_sfd__h836586 ; + (f3_exp__h798126 == 8'd255 && f3_sfd__h798127 != 23'd0) ? + _theResult___snd_fst_sfd__h798442 : + _theResult___fst_sfd__h836582 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14139 = - { (f3_exp__h798130 == 8'd255) ? + { (f3_exp__h798126 == 8'd255) ? 11'd2047 : - _theResult___fst_exp__h836582, + _theResult___fst_exp__h836578, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14138 } ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14194 = - (f3_exp__h798130 == 8'd0) ? + (f3_exp__h798126 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13497 ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13499 ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != @@ -21081,85 +21079,85 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14166) : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d14193 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14195 = - (f3_exp__h798130 == 8'd255 && f3_sfd__h798131 != 23'd0 || - (f3_exp__h798130 == 8'd255 || f3_exp__h798130 == 8'd0) && - f3_sfd__h798131 == 23'd0) ? + (f3_exp__h798126 == 8'd255 && f3_sfd__h798127 != 23'd0 || + (f3_exp__h798126 == 8'd255 || f3_exp__h798126 == 8'd0) && + f3_sfd__h798127 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14194 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14340 = - ((f2_exp__h758826 == 8'd0) ? - (f2_sfd__h758827[22] ? + ((f2_exp__h758822 == 8'd0) ? + (f2_sfd__h758823[22] ? 6'd2 : - (f2_sfd__h758827[21] ? + (f2_sfd__h758823[21] ? 6'd3 : - (f2_sfd__h758827[20] ? + (f2_sfd__h758823[20] ? 6'd4 : - (f2_sfd__h758827[19] ? + (f2_sfd__h758823[19] ? 6'd5 : - (f2_sfd__h758827[18] ? + (f2_sfd__h758823[18] ? 6'd6 : - (f2_sfd__h758827[17] ? + (f2_sfd__h758823[17] ? 6'd7 : - (f2_sfd__h758827[16] ? + (f2_sfd__h758823[16] ? 6'd8 : - (f2_sfd__h758827[15] ? + (f2_sfd__h758823[15] ? 6'd9 : - (f2_sfd__h758827[14] ? + (f2_sfd__h758823[14] ? 6'd10 : - (f2_sfd__h758827[13] ? + (f2_sfd__h758823[13] ? 6'd11 : - (f2_sfd__h758827[12] ? + (f2_sfd__h758823[12] ? 6'd12 : - (f2_sfd__h758827[11] ? + (f2_sfd__h758823[11] ? 6'd13 : - (f2_sfd__h758827[10] ? + (f2_sfd__h758823[10] ? 6'd14 : - (f2_sfd__h758827[9] ? + (f2_sfd__h758823[9] ? 6'd15 : - (f2_sfd__h758827[8] ? + (f2_sfd__h758823[8] ? 6'd16 : - (f2_sfd__h758827[7] ? + (f2_sfd__h758823[7] ? 6'd17 : - (f2_sfd__h758827[6] ? + (f2_sfd__h758823[6] ? 6'd18 : - (f2_sfd__h758827[5] ? + (f2_sfd__h758823[5] ? 6'd19 : - (f2_sfd__h758827[4] ? + (f2_sfd__h758823[4] ? 6'd20 : - (f2_sfd__h758827[3] ? + (f2_sfd__h758823[3] ? 6'd21 : - (f2_sfd__h758827[2] ? + (f2_sfd__h758823[2] ? 6'd22 : - (f2_sfd__h758827[1] ? + (f2_sfd__h758823[1] ? 6'd23 : - (f2_sfd__h758827[0] ? + (f2_sfd__h758823[0] ? 6'd24 : 6'd57))))))))))))))))))))))) : 6'd1) - 6'd1 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14731 = - (f2_exp__h758826 == 8'd255 && f2_sfd__h758827 != 23'd0 || - (f2_exp__h758826 == 8'd255 || f2_exp__h758826 == 8'd0) && - f2_sfd__h758827 == 23'd0) ? + (f2_exp__h758822 == 8'd255 && f2_sfd__h758823 != 23'd0 || + (f2_exp__h758822 == 8'd255 || f2_exp__h758822 == 8'd0) && + f2_sfd__h758823 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - ((f2_exp__h758826 == 8'd0) ? + ((f2_exp__h758822 == 8'd0) ? IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d14386 : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d14729) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14908 = - (f2_exp__h758826 == 8'd255 && f2_sfd__h758827 != 23'd0) ? - _theResult___snd_fst_sfd__h759142 : - _theResult___fst_sfd__h797282 ; + (f2_exp__h758822 == 8'd255 && f2_sfd__h758823 != 23'd0) ? + _theResult___snd_fst_sfd__h759138 : + _theResult___fst_sfd__h797278 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14909 = - { (f2_exp__h758826 == 8'd255) ? + { (f2_exp__h758822 == 8'd255) ? 11'd2047 : - _theResult___fst_exp__h797278, + _theResult___fst_exp__h797274, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14908 } ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14963 = - (f2_exp__h758826 == 8'd0) ? + (f2_exp__h758822 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14267 ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14269 ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != @@ -21169,15 +21167,15 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14935) : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d14962 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14964 = - (f2_exp__h758826 == 8'd255 && f2_sfd__h758827 != 23'd0 || - (f2_exp__h758826 == 8'd255 || f2_exp__h758826 == 8'd0) && - f2_sfd__h758827 == 23'd0) ? + (f2_exp__h758822 == 8'd255 && f2_sfd__h758823 != 23'd0 || + (f2_exp__h758822 == 8'd255 || f2_exp__h758822 == 8'd0) && + f2_sfd__h758823 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14963 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15019 = - (f1_exp__h719832 == 8'd0) ? + (f1_exp__h719828 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12767 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12769 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14998[4] : @@ -21185,7 +21183,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12905 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d15015[4] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15060 = - (f2_exp__h758826 == 8'd0) ? + (f2_exp__h758822 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14267 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14269 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d15039[4] : @@ -21193,7 +21191,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14390 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d15056[4] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15104 = - (f3_exp__h798130 == 8'd0) ? + (f3_exp__h798126 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13497 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13499 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d15083[4] : @@ -21201,7 +21199,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13620 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d15100[4] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15119 = - (f1_exp__h719832 == 8'd0) ? + (f1_exp__h719828 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12767 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12769 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14998[3] : @@ -21209,7 +21207,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12905 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d15015[3] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15129 = - (f2_exp__h758826 == 8'd0) ? + (f2_exp__h758822 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14267 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14269 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d15039[3] : @@ -21217,7 +21215,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14390 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d15056[3] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15140 = - (f3_exp__h798130 == 8'd0) ? + (f3_exp__h798126 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13497 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13499 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d15083[3] : @@ -21225,70 +21223,70 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13620 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d15100[3] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15159 = - (f1_exp__h719832 == 8'd0) ? + (f1_exp__h719828 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12767 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12769 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14998[2] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12904 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15157 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15173 = - (f2_exp__h758826 == 8'd0) ? + (f2_exp__h758822 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14267 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14269 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d15039[2] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14389 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15171 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15188 = - (f3_exp__h798130 == 8'd0) ? + (f3_exp__h798126 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13497 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13499 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d15083[2] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13619 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15186 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15205 = - (f1_exp__h719832 == 8'd0) ? + (f1_exp__h719828 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12767 && (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12769 || _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14998[1]) : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12904 && IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15203 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15217 = - (f2_exp__h758826 == 8'd0) ? + (f2_exp__h758822 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14267 && (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14269 || _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d15039[1]) : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14389 && IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15215 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15230 = - (f3_exp__h798130 == 8'd0) ? + (f3_exp__h798126 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13497 && (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13499 || _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d15083[1]) : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13619 && IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15228 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15247 = - (f1_exp__h719832 == 8'd0) ? + (f1_exp__h719828 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12767 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12769 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14998[0] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12904 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15245 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15259 = - (f2_exp__h758826 == 8'd0) ? + (f2_exp__h758822 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14267 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14269 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d15039[0] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14389 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15257 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15272 = - (f3_exp__h798130 == 8'd0) ? + (f3_exp__h798126 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13497 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13499 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d15083[0] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13619 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15270 ; assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_cRqR_ETC___d7340 = - _theResult_____2__h519793 == v__h519249 ; + _theResult_____2__h519790 == v__h519246 ; assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_cRqR_ETC___d7348 = IF_IF_coreFix_memExe_dMem_cache_m_banks_0_cRqR_ETC___d7340 && (IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d7318 || @@ -21303,7 +21301,7 @@ module mkCore(CLK, (IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d7331 || coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty) ; assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_from_ETC___d7431 = - _theResult_____2__h530570 == v__h521269 ; + _theResult_____2__h530567 == v__h521266 ; assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_from_ETC___d7440 = IF_IF_coreFix_memExe_dMem_cache_m_banks_0_from_ETC___d7431 && (IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d7412 || @@ -21332,9 +21330,9 @@ module mkCore(CLK, EN_dCacheToParent_fromP_enq ? coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[518:3] : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[518:3], - x__h526100 } ; + x__h526097 } ; assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_rqTo_ETC___d7591 = - _theResult_____2__h537663 == v__h536988 ; + _theResult_____2__h537660 == v__h536985 ; assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_rqTo_ETC___d7599 = IF_IF_coreFix_memExe_dMem_cache_m_banks_0_rqTo_ETC___d7591 && (IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d7571 || @@ -21349,7 +21347,7 @@ module mkCore(CLK, (IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d7584 || coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty) ; assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_rsTo_ETC___d7675 = - _theResult_____2__h548298 == v__h539437 ; + _theResult_____2__h548295 == v__h539434 ; assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_rsTo_ETC___d7683 = IF_IF_coreFix_memExe_dMem_cache_m_banks_0_rsTo_ETC___d7675 && (IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d7655 || @@ -21746,7 +21744,7 @@ module mkCore(CLK, 5'd15 : 5'd28))))))))))))) } ; assign IF_IF_coreFix_memExe_forwardQ_deqReq_lat_1_wha_ETC___d7961 = - _theResult_____2__h565910 == v__h564236 ; + _theResult_____2__h565907 == v__h564233 ; assign IF_IF_coreFix_memExe_forwardQ_deqReq_lat_1_wha_ETC___d7969 = IF_IF_coreFix_memExe_forwardQ_deqReq_lat_1_wha_ETC___d7961 && (IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d7942 || @@ -21761,7 +21759,7 @@ module mkCore(CLK, (IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d7955 || coreFix_memExe_forwardQ_empty) ; assign IF_IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_w_ETC___d7879 = - _theResult_____2__h562131 == v__h560457 ; + _theResult_____2__h562128 == v__h560454 ; assign IF_IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_w_ETC___d7887 = IF_IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_w_ETC___d7879 && (IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d7860 || @@ -21775,16 +21773,16 @@ module mkCore(CLK, !coreFix_memExe_memRespLdQ_enqReq_rl[134]) && (IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d7873 || coreFix_memExe_memRespLdQ_empty) ; - assign IF_IF_csrf_prv_reg_read__0574_ULE_1_2990_AND_I_ETC___d23270 = - (csrf_prv_reg_read__0574_ULE_1_2990_AND_IF_comm_ETC___d23023 ? + assign IF_IF_csrf_prv_reg_read__0574_ULE_1_2990_AND_I_ETC___d23272 = + (csrf_prv_reg_read__0574_ULE_1_2990_AND_IF_comm_ETC___d23024 ? !csrf_stcc_reg[34] : !csrf_mtcc_reg[34]) ? - { x__h1011617[11:0], - x1_avValue_new_pcc_capFat_bounds_baseBits__h1011620 } : - { x__h1011617[11:3], - x__h1011638[5:3], - x1_avValue_new_pcc_capFat_bounds_baseBits__h1011620[13:3], - x__h1011638[2:0] } ; + { x__h1011651[11:0], + x1_avValue_new_pcc_capFat_bounds_baseBits__h1011654 } : + { x__h1011651[11:3], + x__h1011672[5:3], + x1_avValue_new_pcc_capFat_bounds_baseBits__h1011654[13:3], + x__h1011672[2:0] } ; assign IF_IF_fetchStage_pipelines_0_first__0544_BITS__ETC___d21530 = IF_fetchStage_pipelines_0_first__0544_BITS_268_ETC___d21521 ? !csrf_rg_dcsr[2] && @@ -22024,48 +22022,48 @@ module mkCore(CLK, IF_IF_IF_NOT_csrf_prv_reg_read__0574_EQ_3_0575_ETC___d21217) ? 4'd0 : IF_IF_renameStage_rg_m_halt_req_0571_BIT_4_057_ETC___d21272 ; - assign IF_IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_ETC___d23507 = + assign IF_IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_ETC___d23509 = robdeqPort_0_deq_data_BITS_95_TO_32__q16[63] ? - x__h1019461[13:0] >= toBounds__h1019347 : - x__h1019461[13:0] <= toBoundsM1__h1019348 ; - assign IF_IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_ETC___d23551 = + x__h1019495[13:0] >= toBounds__h1019381 : + x__h1019495[13:0] <= toBoundsM1__h1019382 ; + assign IF_IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_ETC___d23553 = MUX_csrf_rg_dcsr$write_1__VAL_1[63] ? - x__h1019864[13:0] >= toBounds__h1019750 : - x__h1019864[13:0] <= toBoundsM1__h1019751 ; - assign IF_IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_ETC___d23646 = + x__h1019898[13:0] >= toBounds__h1019784 : + x__h1019898[13:0] <= toBoundsM1__h1019785 ; + assign IF_IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_ETC___d23648 = robdeqPort_0_deq_data_BITS_95_TO_32__q16[63] ? - x__h1020281[13:0] >= toBounds__h1020167 : - x__h1020281[13:0] <= toBoundsM1__h1020168 ; - assign IF_IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_ETC___d23688 = + x__h1020315[13:0] >= toBounds__h1020201 : + x__h1020315[13:0] <= toBoundsM1__h1020202 ; + assign IF_IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_ETC___d23690 = MUX_csrf_rg_dcsr$write_1__VAL_1[63] ? - x__h1020684[13:0] >= toBounds__h1020570 : - x__h1020684[13:0] <= toBoundsM1__h1020571 ; - assign IF_IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_ETC___d23801 = + x__h1020718[13:0] >= toBounds__h1020604 : + x__h1020718[13:0] <= toBoundsM1__h1020605 ; + assign IF_IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_ETC___d23803 = robdeqPort_0_deq_data_BITS_95_TO_32__q16[63] ? - x__h1021353[13:0] >= toBounds__h1021239 : - x__h1021353[13:0] <= toBoundsM1__h1021240 ; + x__h1021387[13:0] >= toBounds__h1021273 : + x__h1021387[13:0] <= toBoundsM1__h1021274 ; assign IF_INV_IF_coreFix_memExe_lsq_firstLd__502_BITS_ETC___d1958 = - { INV_x85174_BITS_108_TO_90__q35[0] ? x__h185294 : 6'd0, - x__h185454, - x__h185474 } ; + { INV_x85172_BITS_108_TO_90__q35[0] ? x__h185292 : 6'd0, + x__h185452, + x__h185472 } ; assign IF_INV_IF_coreFix_memExe_lsq_firstLd__502_BITS_ETC___d2126 = - { INV_x01338_BITS_108_TO_90__q37[0] ? x__h204357 : 6'd0, - x__h204517, - x__h204537 } ; + { INV_x01336_BITS_108_TO_90__q37[0] ? x__h204355 : 6'd0, + x__h204515, + x__h204535 } ; assign IF_INV_commitStage_commitTrap_2639_BITS_217_TO_ETC___d22956 = INV_commitStage_commitTrap_BITS_217_TO_199__q15[0] ? - x__h1005682 : + x__h1005679 : 6'd0 ; - assign IF_INV_commitStage_commitTrap_2639_BITS_217_TO_ETC___d23037 = - x__h1005862[13:11] < repBound__h1008332 ; - assign IF_INV_commitStage_commitTrap_2639_BITS_217_TO_ETC___d23039 = - pc_addrBits__h1005473[13:11] < repBound__h1008332 ; + assign IF_INV_commitStage_commitTrap_2639_BITS_217_TO_ETC___d23038 = + x__h1005859[13:11] < repBound__h1008366 ; + assign IF_INV_commitStage_commitTrap_2639_BITS_217_TO_ETC___d23040 = + pc_addrBits__h1005470[13:11] < repBound__h1008366 ; assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9699__ETC___d20021 = - tb__h914124 < repBound__h914127 ; + tb__h914121 < repBound__h914124 ; assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9699__ETC___d20022 = - x__h914066[13:11] < repBound__h914127 ; + x__h914063[13:11] < repBound__h914124 ; assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9699__ETC___d20024 = - cr_addrBits__h913659[13:11] < repBound__h914127 ; + cr_addrBits__h913656[13:11] < repBound__h914124 ; assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9699__ETC___d20034 = { IF_INV_coreFix_aluExe_0_regToExeQ_first__9699__ETC___d20024, (IF_INV_coreFix_aluExe_0_regToExeQ_first__9699__ETC___d20021 == @@ -22083,11 +22081,11 @@ module mkCore(CLK, 2'd1 : 2'd3) } ; assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9699__ETC___d20085 = - tb__h914672 < repBound__h914675 ; + tb__h914669 < repBound__h914672 ; assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9699__ETC___d20086 = - x__h914614[13:11] < repBound__h914675 ; + x__h914611[13:11] < repBound__h914672 ; assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9699__ETC___d20088 = - cr_addrBits__h914207[13:11] < repBound__h914675 ; + cr_addrBits__h914204[13:11] < repBound__h914672 ; assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9699__ETC___d20098 = { IF_INV_coreFix_aluExe_0_regToExeQ_first__9699__ETC___d20088, (IF_INV_coreFix_aluExe_0_regToExeQ_first__9699__ETC___d20085 == @@ -22105,11 +22103,11 @@ module mkCore(CLK, 2'd1 : 2'd3) } ; assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7524__ETC___d17846 = - tb__h873083 < repBound__h873086 ; + tb__h873081 < repBound__h873084 ; assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7524__ETC___d17847 = - x__h873025[13:11] < repBound__h873086 ; + x__h873023[13:11] < repBound__h873084 ; assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7524__ETC___d17849 = - cr_addrBits__h872618[13:11] < repBound__h873086 ; + cr_addrBits__h872616[13:11] < repBound__h873084 ; assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7524__ETC___d17859 = { IF_INV_coreFix_aluExe_1_regToExeQ_first__7524__ETC___d17849, (IF_INV_coreFix_aluExe_1_regToExeQ_first__7524__ETC___d17846 == @@ -22127,11 +22125,11 @@ module mkCore(CLK, 2'd1 : 2'd3) } ; assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7524__ETC___d17910 = - tb__h873631 < repBound__h873634 ; + tb__h873629 < repBound__h873632 ; assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7524__ETC___d17911 = - x__h873573[13:11] < repBound__h873634 ; + x__h873571[13:11] < repBound__h873632 ; assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7524__ETC___d17913 = - cr_addrBits__h873166[13:11] < repBound__h873634 ; + cr_addrBits__h873164[13:11] < repBound__h873632 ; assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7524__ETC___d17923 = { IF_INV_coreFix_aluExe_1_regToExeQ_first__7524__ETC___d17913, (IF_INV_coreFix_aluExe_1_regToExeQ_first__7524__ETC___d17910 == @@ -22150,26 +22148,26 @@ module mkCore(CLK, 2'd3) } ; assign IF_INV_coreFix_memExe_lsq_respLd_166_BITS_108__ETC___d2217 = { INV_coreFix_memExe_lsqrespLd_BITS_108_TO_90__q10[0] ? - x__h219328 : + x__h219326 : 6'd0, - x__h219488, - x__h219508 } ; + x__h219486, + x__h219506 } ; assign IF_INV_coreFix_memExe_respLrScAmoQ_data_0_235__ETC___d1275 = { INV_coreFix_memExe_respLrScAmoQ_data_0_BITS_10_ETC__q8[0] ? - x__h128368 : + x__h128367 : 6'd0, - x__h128528, - x__h128548 } ; + x__h128527, + x__h128547 } ; assign IF_INV_mmio_dataRespQ_data_0_393_BITS_108_TO_9_ETC___d1437 = { INV_mmio_dataRespQ_data_0_BITS_108_TO_90__q9[0] ? - x__h141512 : + x__h141511 : 6'd0, - x__h141672, - x__h141692 } ; + x__h141671, + x__h141691 } ; assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d12901 = (!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12767 || _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12769 || - _theResult___fst_exp__h739220 == 11'd2047) ? + _theResult___fst_exp__h739216 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : @@ -22177,12 +22175,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard31259_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q157 : + CASE_guard31255_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q157 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q158) ; assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d13616 = (!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13497 || _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13499 || - _theResult___fst_exp__h817377 == 11'd2047) ? + _theResult___fst_exp__h817373 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -22190,12 +22188,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard09416_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q176 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q177) ; + CASE_guard09412_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q174 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q175) ; assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d14386 = (!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14267 || _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14269 || - _theResult___fst_exp__h778073 == 11'd2047) ? + _theResult___fst_exp__h778069 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -22203,7 +22201,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard70112_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q205 : + CASE_guard70108_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q205 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q206) ; assign IF_NOT_IF_IF_NOT_csrf_prv_reg_read__0574_EQ_3__ETC___d21193 = IF_IF_NOT_csrf_prv_reg_read__0574_EQ_3_0575_05_ETC___d20611[0] ? @@ -23842,7 +23840,7 @@ module mkCore(CLK, checkForException___d20942[10:5], CASE_checkForException_0942_BITS_4_TO_0_0_chec_ETC__q257 } : IF_NOT_renameStage_rg_m_halt_req_0571_BIT_4_05_ETC___d21275 ; - assign IF_NOT_rob_deqPort_1_deq_data__3990_BIT_25_399_ETC___d24228 = + assign IF_NOT_rob_deqPort_1_deq_data__3992_BIT_25_399_ETC___d24230 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[274] || rob$deqPort_1_deq_data[469:465] == 5'd0 || @@ -23918,48 +23916,48 @@ module mkCore(CLK, assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15157 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12905 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d15015[2] : - _theResult___fst_exp__h758413 == 11'd2047 && - _theResult___fst_sfd__h758414 == 52'd0 ; + _theResult___fst_exp__h758409 == 11'd2047 && + _theResult___fst_sfd__h758410 == 52'd0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15171 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14390 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d15056[2] : - _theResult___fst_exp__h797266 == 11'd2047 && - _theResult___fst_sfd__h797267 == 52'd0 ; + _theResult___fst_exp__h797262 == 11'd2047 && + _theResult___fst_sfd__h797263 == 52'd0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15186 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13620 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d15100[2] : - _theResult___fst_exp__h836570 == 11'd2047 && - _theResult___fst_sfd__h836571 == 52'd0 ; + _theResult___fst_exp__h836566 == 11'd2047 && + _theResult___fst_sfd__h836567 == 52'd0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15203 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12905 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d15015[1] : - _theResult___fst_exp__h757630 == 11'd0 && - guard__h749640 != 2'b0 ; + _theResult___fst_exp__h757626 == 11'd0 && + guard__h749636 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15215 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14390 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d15056[1] : - _theResult___fst_exp__h796483 == 11'd0 && - guard__h788493 != 2'b0 ; + _theResult___fst_exp__h796479 == 11'd0 && + guard__h788489 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15228 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13620 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d15100[1] : - _theResult___fst_exp__h835787 == 11'd0 && - guard__h827797 != 2'b0 ; + _theResult___fst_exp__h835783 == 11'd0 && + guard__h827793 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15245 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12905 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d15015[0] : - _theResult___fst_exp__h757630 != 11'd2047 && - guard__h749640 != 2'b0 ; + _theResult___fst_exp__h757626 != 11'd2047 && + guard__h749636 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15257 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14390 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d15056[0] : - _theResult___fst_exp__h796483 != 11'd2047 && - guard__h788493 != 2'b0 ; + _theResult___fst_exp__h796479 != 11'd2047 && + guard__h788489 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15270 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13620 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d15100[0] : - _theResult___fst_exp__h835787 != 11'd2047 && - guard__h827797 != 2'b0 ; + _theResult___fst_exp__h835783 != 11'd2047 && + guard__h827793 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d10483 = ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q85[7:0] == 8'd0) ? @@ -23969,35 +23967,35 @@ module mkCore(CLK, 9'd386 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d10710 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10164 ? - ((_theResult___fst_exp__h652505 == 8'd255) ? + ((_theResult___fst_exp__h652502 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10695) : - ((_theResult___fst_exp__h661190 == 8'd255) ? + ((_theResult___fst_exp__h661187 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10708) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d10747 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10164 ? - ((_theResult___fst_exp__h652505 == 8'd255) ? + ((_theResult___fst_exp__h652502 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10738) : - ((_theResult___fst_exp__h661190 == 8'd255) ? + ((_theResult___fst_exp__h661187 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10745) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d10843 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10164 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d10814[2] : - _theResult___fst_exp__h661738 == 8'd255 && - _theResult___fst_sfd__h661739 == 23'd0 ; + _theResult___fst_exp__h661735 == 8'd255 && + _theResult___fst_sfd__h661736 == 23'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d10856 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10164 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d10814[1] : - _theResult___fst_exp__h661190 == 8'd0 && - guard__h653113 != 2'b0 ; + _theResult___fst_exp__h661187 == 8'd0 && + guard__h653110 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d10869 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10164 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d10814[0] : - _theResult___fst_exp__h661190 != 8'd255 && - guard__h653113 != 2'b0 ; + _theResult___fst_exp__h661187 != 8'd255 && + guard__h653110 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d11880 = ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q120[7:0] == 8'd0) ? @@ -24007,37 +24005,37 @@ module mkCore(CLK, 9'd386 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d12107 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11561 ? - ((_theResult___fst_exp__h698252 == 8'd255) ? + ((_theResult___fst_exp__h698249 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12092) : - ((_theResult___fst_exp__h706937 == 8'd255) ? + ((_theResult___fst_exp__h706934 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12105) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d12144 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11561 ? - ((_theResult___fst_exp__h698252 == 8'd255) ? + ((_theResult___fst_exp__h698249 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12135) : - ((_theResult___fst_exp__h706937 == 8'd255) ? + ((_theResult___fst_exp__h706934 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12142) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d12240 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11561 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d12211[2] : - _theResult___fst_exp__h707485 == 8'd255 && - _theResult___fst_sfd__h707486 == 23'd0 ; + _theResult___fst_exp__h707482 == 8'd255 && + _theResult___fst_sfd__h707483 == 23'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d12253 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11561 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d12211[1] : - _theResult___fst_exp__h706937 == 8'd0 && - guard__h698860 != 2'b0 ; + _theResult___fst_exp__h706934 == 8'd0 && + guard__h698857 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d12266 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11561 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d12211[0] : - _theResult___fst_exp__h706937 != 8'd255 && - guard__h698860 != 2'b0 ; + _theResult___fst_exp__h706934 != 8'd255 && + guard__h698857 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d9086 = - ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q42[7:0] == + ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q50[7:0] == 8'd0) ? 9'd386 : { SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q55[7], @@ -24045,41 +24043,41 @@ module mkCore(CLK, 9'd386 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d9313 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8767 ? - ((_theResult___fst_exp__h606756 == 8'd255) ? + ((_theResult___fst_exp__h606753 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9298) : - ((_theResult___fst_exp__h615441 == 8'd255) ? + ((_theResult___fst_exp__h615438 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9311) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d9350 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8767 ? - ((_theResult___fst_exp__h606756 == 8'd255) ? + ((_theResult___fst_exp__h606753 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9341) : - ((_theResult___fst_exp__h615441 == 8'd255) ? + ((_theResult___fst_exp__h615438 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9348) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d9446 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8767 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d9417[2] : - _theResult___fst_exp__h615989 == 8'd255 && - _theResult___fst_sfd__h615990 == 23'd0 ; + _theResult___fst_exp__h615986 == 8'd255 && + _theResult___fst_sfd__h615987 == 23'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d9459 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8767 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d9417[1] : - _theResult___fst_exp__h615441 == 8'd0 && - guard__h607364 != 2'b0 ; + _theResult___fst_exp__h615438 == 8'd0 && + guard__h607361 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d9472 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8767 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d9417[0] : - _theResult___fst_exp__h615441 != 8'd255 && - guard__h607364 != 2'b0 ; + _theResult___fst_exp__h615438 != 8'd255 && + guard__h607361 != 2'b0 ; assign IF_SEXT_coreFix_memExe_regToExeQ_first__664_BI_ETC___d4114 = - offset__h245518[63] ? - x__h245667[13:0] >= toBounds__h245546 && - repBoundBits__h245543 != + offset__h245515[63] ? + x__h245664[13:0] >= toBounds__h245543 && + repBoundBits__h245540 != coreFix_memExe_regToExeQ$first[317:304] : - x__h245667[13:0] < toBoundsM1__h245547 ; + x__h245664[13:0] < toBoundsM1__h245544 ; assign IF_basicExec_0102_BIT_325_0113_THEN_basicExec__ETC___d20121 = basicExec___d20102[325] ? { basicExec___d20102[316:308], @@ -24181,24 +24179,24 @@ module mkCore(CLK, IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d18866 ; assign IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19070 = coreFix_aluExe_0_dispToRegQ$first[137] ? - res_address__h899822 : + res_address__h899820 : ((coreFix_aluExe_0_dispToRegQ$first[85] && coreFix_aluExe_0_dispToRegQ$first[84:78] != 7'd0) ? IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d19068 : 66'd0) ; assign IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19085 = coreFix_aluExe_0_dispToRegQ$first[137] ? - res_addrBits__h899823 : + res_addrBits__h899821 : ((coreFix_aluExe_0_dispToRegQ$first[85] && coreFix_aluExe_0_dispToRegQ$first[84:78] != 7'd0) ? IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d19083 : 14'd0) ; assign IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19636 = { coreFix_aluExe_0_dispToRegQ$first[124] ? - thin_reserved__h906790 : + thin_reserved__h906787 : 2'd0, coreFix_aluExe_0_dispToRegQ$first[124] ? - thin_otype__h906791 : + thin_otype__h906788 : 18'd262143, !coreFix_aluExe_0_dispToRegQ$first[124] || IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19624, @@ -24207,7 +24205,7 @@ module mkCore(CLK, 34'h344000000 } ; assign IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19637 = { coreFix_aluExe_0_dispToRegQ$first[124] ? - thin_perms_soft__h906966 : + thin_perms_soft__h906963 : 4'd0, coreFix_aluExe_0_dispToRegQ$first[124] && IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19482, @@ -24238,18 +24236,18 @@ module mkCore(CLK, IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19636 } ; assign IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19638 = { coreFix_aluExe_0_dispToRegQ$first[124] ? - thin_address__h906786 : + thin_address__h906783 : 66'd0, coreFix_aluExe_0_dispToRegQ$first[124] ? - thin_addrBits__h906787 : + thin_addrBits__h906784 : 14'd0, IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19637 } ; assign IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19659 = - thin_bounds_topBits__h908192[13:11] < repBound__h908308 ; + thin_bounds_topBits__h908189[13:11] < repBound__h908305 ; assign IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19661 = - thin_bounds_baseBits__h908193[13:11] < repBound__h908308 ; + thin_bounds_baseBits__h908190[13:11] < repBound__h908305 ; assign IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19664 = - thin_addrBits__h906787[13:11] < repBound__h908308 ; + thin_addrBits__h906784[13:11] < repBound__h908305 ; assign IF_coreFix_aluExe_0_exeToFinQ_first__0233_BIT__ETC___d20379 = { (coreFix_aluExe_0_exeToFinQ$first[282] && !coreFix_aluExe_0_exeToFinQ$first[294]) ? @@ -24496,24 +24494,24 @@ module mkCore(CLK, IF_coreFix_aluExe_1_dispToRegQ_first__5790_BIT_ETC___d16044 ; assign IF_coreFix_aluExe_1_dispToRegQ_first__5790_BIT_ETC___d16616 = coreFix_aluExe_1_dispToRegQ$first[137] ? - res_address__h855059 : + res_address__h855056 : ((coreFix_aluExe_1_dispToRegQ$first[85] && coreFix_aluExe_1_dispToRegQ$first[84:78] != 7'd0) ? IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16614 : 66'd0) ; assign IF_coreFix_aluExe_1_dispToRegQ_first__5790_BIT_ETC___d16631 = coreFix_aluExe_1_dispToRegQ$first[137] ? - res_addrBits__h855060 : + res_addrBits__h855057 : ((coreFix_aluExe_1_dispToRegQ$first[85] && coreFix_aluExe_1_dispToRegQ$first[84:78] != 7'd0) ? IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16629 : 14'd0) ; assign IF_coreFix_aluExe_1_dispToRegQ_first__5790_BIT_ETC___d17443 = { coreFix_aluExe_1_dispToRegQ$first[124] ? - thin_reserved__h864892 : + thin_reserved__h864890 : 2'd0, coreFix_aluExe_1_dispToRegQ$first[124] ? - thin_otype__h864893 : + thin_otype__h864891 : 18'd262143, !coreFix_aluExe_1_dispToRegQ$first[124] || IF_coreFix_aluExe_1_dispToRegQ_first__5790_BIT_ETC___d17418, @@ -24522,7 +24520,7 @@ module mkCore(CLK, 34'h344000000 } ; assign IF_coreFix_aluExe_1_dispToRegQ_first__5790_BIT_ETC___d17444 = { coreFix_aluExe_1_dispToRegQ$first[124] ? - thin_perms_soft__h865128 : + thin_perms_soft__h865126 : 4'd0, coreFix_aluExe_1_dispToRegQ$first[124] && IF_coreFix_aluExe_1_dispToRegQ_first__5790_BIT_ETC___d17081, @@ -24553,18 +24551,18 @@ module mkCore(CLK, IF_coreFix_aluExe_1_dispToRegQ_first__5790_BIT_ETC___d17443 } ; assign IF_coreFix_aluExe_1_dispToRegQ_first__5790_BIT_ETC___d17445 = { coreFix_aluExe_1_dispToRegQ$first[124] ? - thin_address__h864888 : + thin_address__h864886 : 66'd0, coreFix_aluExe_1_dispToRegQ$first[124] ? - thin_addrBits__h864889 : + thin_addrBits__h864887 : 14'd0, IF_coreFix_aluExe_1_dispToRegQ_first__5790_BIT_ETC___d17444 } ; assign IF_coreFix_aluExe_1_dispToRegQ_first__5790_BIT_ETC___d17484 = - thin_bounds_topBits__h866836[13:11] < repBound__h866972 ; + thin_bounds_topBits__h866834[13:11] < repBound__h866970 ; assign IF_coreFix_aluExe_1_dispToRegQ_first__5790_BIT_ETC___d17486 = - thin_bounds_baseBits__h866837[13:11] < repBound__h866972 ; + thin_bounds_baseBits__h866835[13:11] < repBound__h866970 ; assign IF_coreFix_aluExe_1_dispToRegQ_first__5790_BIT_ETC___d17489 = - thin_addrBits__h864889[13:11] < repBound__h866972 ; + thin_addrBits__h864887[13:11] < repBound__h866970 ; assign IF_coreFix_aluExe_1_exeToFinQ_first__8058_BIT__ETC___d18205 = { (coreFix_aluExe_1_exeToFinQ$first[282] && !coreFix_aluExe_1_exeToFinQ$first[294]) ? @@ -25345,8 +25343,8 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107] ; assign IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d20485 = coreFix_globalSpecUpdate_correctSpecTag_1$whas ? - result__h924564 : - w__h924559 ; + result__h924561 : + w__h924556 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5034 = (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == 3'd3 && @@ -25558,12 +25556,12 @@ module mkCore(CLK, 64'd0 : 64'd1 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d7294 = - !MUX_flush_reservation$write_1__SEL_1 && + !MUX_flush_reservation$write_1__SEL_2 && (coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget[58] : coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58]) ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d7302 = - MUX_flush_reservation$write_1__SEL_1 ? + MUX_flush_reservation$write_1__SEL_2 ? 58'h2AAAAAAAAAAAAAA : (coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget[57:0] : @@ -25820,15 +25818,15 @@ module mkCore(CLK, NOT_coreFix_memExe_dispToRegQ_first__695_BIT_1_ETC___d3653 } ; assign IF_coreFix_memExe_dispToRegQ_first__695_BIT_12_ETC___d3097 = coreFix_memExe_dispToRegQ$first[12] ? - res_addrBits__h238215 : + res_addrBits__h238212 : ((coreFix_memExe_dispToRegQ$first[110] && coreFix_memExe_dispToRegQ$first[109:103] != 7'd0) ? IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3095 : 14'd0) ; assign IF_coreFix_memExe_dispToRegQ_first__695_BIT_12_ETC___d3341 = { coreFix_memExe_dispToRegQ$first[12] ? - res_address__h238214 : - x__h238637, + res_address__h238211 : + x__h238634, IF_coreFix_memExe_dispToRegQ_first__695_BIT_12_ETC___d3097, coreFix_memExe_dispToRegQ$first[12] ? 4'd0 : @@ -25967,15 +25965,15 @@ module mkCore(CLK, IF_coreFix_memExe_lsq_firstLd__502_BIT_113_517_ETC___d2084 ; assign IF_coreFix_memExe_lsq_getOrigBE_coreFix_memExe_ETC___d4268 = { coreFix_memExe_lsq$getOrigBE[15] ? - pointer__h245528[3:0] != 4'd0 : + pointer__h245525[3:0] != 4'd0 : (coreFix_memExe_lsq$getOrigBE[7] ? - pointer__h245528[2:0] != 3'd0 : + pointer__h245525[2:0] != 3'd0 : (coreFix_memExe_lsq$getOrigBE[3] ? - pointer__h245528[1:0] != 2'd0 : + pointer__h245525[1:0] != 2'd0 : coreFix_memExe_lsq$getOrigBE[1] && - pointer__h245528[0])), + pointer__h245525[0])), capChecks___d4179[11:5], - CASE_capChecks_179_BITS_4_TO_0_0_capChecks_179_ETC__q292, + CASE_capChecks_179_BITS_4_TO_0_0_capChecks_179_ETC__q294, prepareBoundsCheck___d4263 } ; assign IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d7873 = WILL_FIRE_RL_coreFix_memExe_doRespLdMem || @@ -26005,10 +26003,10 @@ module mkCore(CLK, csrf_mepcc_reg_data_rl[13:0] ; assign IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16430 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16427[13:11] < - repBound__h861805 ; + repBound__h861803 ; assign IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16432 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16423[13:11] < - repBound__h861805 ; + repBound__h861803 ; assign IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16443 = MUX_csrf_ie_vec_3$write_1__SEL_3 ? MUX_csrf_rg_dpc$write_1__VAL_3[33:28] : @@ -26097,86 +26095,86 @@ module mkCore(CLK, MUX_csrf_ie_vec_3$write_1__SEL_3 ? MUX_csrf_rg_dpc$write_1__VAL_3[27:14] : csrf_mepcc_reg_data_rl[27:14] ; - assign IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d23712 = + assign IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d23714 = MUX_csrf_ie_vec_3$write_1__SEL_3 ? MUX_csrf_rg_dpc$write_1__VAL_3[71:0] : csrf_mepcc_reg_data_rl[71:0] ; - assign IF_csrf_mepcc_reg_read_wget__3928_BIT_34_3940__ETC___d23950 = + assign IF_csrf_mepcc_reg_read_wget__3930_BIT_34_3942__ETC___d23952 = csrf_mepcc_reg_data_rl[34] ? { csrf_mepcc_reg_data_rl[25:17], csrf_mepcc_reg_data_rl[33:31], csrf_mepcc_reg_data_rl[13:3], csrf_mepcc_reg_data_rl[30:28] } : csrf_mepcc_reg_data_rl[25:0] ; - assign IF_csrf_mtcc_reg_read__6389_BITS_149_TO_86_318_ETC___d23216 = - ((newAddrDiff__h1010891 == 64'd0) ? + assign IF_csrf_mtcc_reg_read__6389_BITS_149_TO_86_318_ETC___d23218 = + ((newAddrDiff__h1010925 == 64'd0) ? 2'd0 : - (csrf_mtcc_reg_read__6389_BITS_149_TO_86_3187_A_ETC___d23197 ? + (csrf_mtcc_reg_read__6389_BITS_149_TO_86_3189_A_ETC___d23199 ? 2'd3 : 2'd1)) == ((csrf_mtcc_reg_read__6389_BITS_85_TO_83_6395_UL_ETC___d16396 && - _0_CONCAT_csrf_mtcc_reg_read__6389_BITS_149_TO__ETC___d23208) ? + _0_CONCAT_csrf_mtcc_reg_read__6389_BITS_149_TO__ETC___d23210) ? 2'd0 : ((csrf_mtcc_reg_read__6389_BITS_85_TO_83_6395_UL_ETC___d16396 && - !_0_CONCAT_csrf_mtcc_reg_read__6389_BITS_149_TO__ETC___d23208) ? + !_0_CONCAT_csrf_mtcc_reg_read__6389_BITS_149_TO__ETC___d23210) ? 2'd1 : ((!csrf_mtcc_reg_read__6389_BITS_85_TO_83_6395_UL_ETC___d16396 && - _0_CONCAT_csrf_mtcc_reg_read__6389_BITS_149_TO__ETC___d23208) ? + _0_CONCAT_csrf_mtcc_reg_read__6389_BITS_149_TO__ETC___d23210) ? 2'd3 : 2'd0))) ; - assign IF_csrf_mtcc_reg_read__6389_BITS_149_TO_86_318_ETC___d23219 = - IF_csrf_mtcc_reg_read__6389_BITS_149_TO_86_318_ETC___d23216 && - (newAddrDiff__h1010891 == 64'd0 || - csrf_mtcc_reg_read__6389_BITS_149_TO_86_3187_A_ETC___d23197 || - newAddrDiff__h1010891 == - _18446744073709551615_SL_csrf_mtcc_reg_read__63_ETC___d23200) ; - assign IF_csrf_mtcc_reg_read__6389_BITS_149_TO_86_318_ETC___d23241 = - ((newAddrDiff__h1011235 == 64'd0) ? + assign IF_csrf_mtcc_reg_read__6389_BITS_149_TO_86_318_ETC___d23221 = + IF_csrf_mtcc_reg_read__6389_BITS_149_TO_86_318_ETC___d23218 && + (newAddrDiff__h1010925 == 64'd0 || + csrf_mtcc_reg_read__6389_BITS_149_TO_86_3189_A_ETC___d23199 || + newAddrDiff__h1010925 == + _18446744073709551615_SL_csrf_mtcc_reg_read__63_ETC___d23202) ; + assign IF_csrf_mtcc_reg_read__6389_BITS_149_TO_86_318_ETC___d23243 = + ((newAddrDiff__h1011269 == 64'd0) ? 2'd0 : - (csrf_mtcc_reg_read__6389_BITS_149_TO_86_3187_A_ETC___d23225 ? + (csrf_mtcc_reg_read__6389_BITS_149_TO_86_3189_A_ETC___d23227 ? 2'd3 : 2'd1)) == ((csrf_mtcc_reg_read__6389_BITS_85_TO_83_6395_UL_ETC___d16396 && - _0_CONCAT_csrf_mtcc_reg_read__6389_BITS_149_TO__ETC___d23233) ? + _0_CONCAT_csrf_mtcc_reg_read__6389_BITS_149_TO__ETC___d23235) ? 2'd0 : ((csrf_mtcc_reg_read__6389_BITS_85_TO_83_6395_UL_ETC___d16396 && - !_0_CONCAT_csrf_mtcc_reg_read__6389_BITS_149_TO__ETC___d23233) ? + !_0_CONCAT_csrf_mtcc_reg_read__6389_BITS_149_TO__ETC___d23235) ? 2'd1 : ((!csrf_mtcc_reg_read__6389_BITS_85_TO_83_6395_UL_ETC___d16396 && - _0_CONCAT_csrf_mtcc_reg_read__6389_BITS_149_TO__ETC___d23233) ? + _0_CONCAT_csrf_mtcc_reg_read__6389_BITS_149_TO__ETC___d23235) ? 2'd3 : 2'd0))) ; - assign IF_csrf_mtcc_reg_read__6389_BITS_149_TO_86_318_ETC___d23244 = - IF_csrf_mtcc_reg_read__6389_BITS_149_TO_86_318_ETC___d23241 && - (newAddrDiff__h1011235 == 64'd0 || - csrf_mtcc_reg_read__6389_BITS_149_TO_86_3187_A_ETC___d23225 || - newAddrDiff__h1011235 == - _18446744073709551615_SL_csrf_mtcc_reg_read__63_ETC___d23200) ; - assign IF_csrf_mtcc_reg_read__6389_BIT_86_3183_AND_NO_ETC___d23247 = - (csrf_mtcc_reg[86] && cause_interrupt__h1006051) ? - (NOT_csrf_mtcc_reg_read__6389_BITS_33_TO_28_640_ETC___d23186 || - IF_csrf_mtcc_reg_read__6389_BITS_149_TO_86_318_ETC___d23219) && + assign IF_csrf_mtcc_reg_read__6389_BITS_149_TO_86_318_ETC___d23246 = + IF_csrf_mtcc_reg_read__6389_BITS_149_TO_86_318_ETC___d23243 && + (newAddrDiff__h1011269 == 64'd0 || + csrf_mtcc_reg_read__6389_BITS_149_TO_86_3189_A_ETC___d23227 || + newAddrDiff__h1011269 == + _18446744073709551615_SL_csrf_mtcc_reg_read__63_ETC___d23202) ; + assign IF_csrf_mtcc_reg_read__6389_BIT_86_3185_AND_NO_ETC___d23249 = + (csrf_mtcc_reg[86] && cause_interrupt__h1006048) ? + (NOT_csrf_mtcc_reg_read__6389_BITS_33_TO_28_640_ETC___d23188 || + IF_csrf_mtcc_reg_read__6389_BITS_149_TO_86_318_ETC___d23221) && csrf_mtcc_reg[152] : - (NOT_csrf_mtcc_reg_read__6389_BITS_33_TO_28_640_ETC___d23186 || - IF_csrf_mtcc_reg_read__6389_BITS_149_TO_86_318_ETC___d23244) && + (NOT_csrf_mtcc_reg_read__6389_BITS_33_TO_28_640_ETC___d23188 || + IF_csrf_mtcc_reg_read__6389_BITS_149_TO_86_318_ETC___d23246) && csrf_mtcc_reg[152] ; - assign IF_csrf_mtcc_reg_read__6389_BIT_86_3183_AND_NO_ETC___d23281 = - (csrf_mtcc_reg[86] && cause_interrupt__h1006051) ? - address__h1010211 : - base__h1010176 ; - assign IF_csrf_prv_reg_read__0574_ULE_1_2990_AND_IF_c_ETC___d23252 = - csrf_prv_reg_read__0574_ULE_1_2990_AND_IF_comm_ETC___d23023 ? - { IF_csrf_stcc_reg_read__6237_BIT_86_3112_AND_NO_ETC___d23178, + assign IF_csrf_mtcc_reg_read__6389_BIT_86_3185_AND_NO_ETC___d23283 = + (csrf_mtcc_reg[86] && cause_interrupt__h1006048) ? + address__h1010245 : + base__h1010210 ; + assign IF_csrf_prv_reg_read__0574_ULE_1_2990_AND_IF_c_ETC___d23254 = + csrf_prv_reg_read__0574_ULE_1_2990_AND_IF_comm_ETC___d23024 ? + { IF_csrf_stcc_reg_read__6237_BIT_86_3114_AND_NO_ETC___d23180, csrf_stcc_reg[71:56], csrf_stcc_reg[54:53], csrf_stcc_reg[55], csrf_stcc_reg[52:34] } : - { IF_csrf_mtcc_reg_read__6389_BIT_86_3183_AND_NO_ETC___d23247, + { IF_csrf_mtcc_reg_read__6389_BIT_86_3185_AND_NO_ETC___d23249, csrf_mtcc_reg[71:56], csrf_mtcc_reg[54:53], csrf_mtcc_reg[55], csrf_mtcc_reg[52:34] } ; - assign IF_csrf_rg_dpc_read__6534_BIT_34_4739_THEN_csr_ETC___d24747 = + assign IF_csrf_rg_dpc_read__6534_BIT_34_4741_THEN_csr_ETC___d24749 = csrf_rg_dpc[34] ? { csrf_rg_dpc[25:17], csrf_rg_dpc[33:31], @@ -26193,10 +26191,10 @@ module mkCore(CLK, csrf_sepcc_reg_data_rl[13:0] ; assign IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16278 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16275[13:11] < - repBound__h860813 ; + repBound__h860811 ; assign IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16280 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16271[13:11] < - repBound__h860813 ; + repBound__h860811 ; assign IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16291 = MUX_csrf_ie_vec_1$write_1__SEL_3 ? MUX_csrf_rg_dpc$write_1__VAL_3[33:28] : @@ -26285,93 +26283,93 @@ module mkCore(CLK, MUX_csrf_ie_vec_1$write_1__SEL_3 ? MUX_csrf_rg_dpc$write_1__VAL_3[27:14] : csrf_sepcc_reg_data_rl[27:14] ; - assign IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d23575 = + assign IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d23577 = MUX_csrf_ie_vec_1$write_1__SEL_3 ? MUX_csrf_rg_dpc$write_1__VAL_3[71:0] : csrf_sepcc_reg_data_rl[71:0] ; - assign IF_csrf_sepcc_reg_read_wget__3894_BIT_34_3906__ETC___d23916 = + assign IF_csrf_sepcc_reg_read_wget__3896_BIT_34_3908__ETC___d23918 = csrf_sepcc_reg_data_rl[34] ? { csrf_sepcc_reg_data_rl[25:17], csrf_sepcc_reg_data_rl[33:31], csrf_sepcc_reg_data_rl[13:3], csrf_sepcc_reg_data_rl[30:28] } : csrf_sepcc_reg_data_rl[25:0] ; - assign IF_csrf_stcc_reg_read__6237_BITS_149_TO_86_311_ETC___d23147 = - ((newAddrDiff__h1010234 == 64'd0) ? + assign IF_csrf_stcc_reg_read__6237_BITS_149_TO_86_311_ETC___d23149 = + ((newAddrDiff__h1010268 == 64'd0) ? 2'd0 : - (csrf_stcc_reg_read__6237_BITS_149_TO_86_3116_A_ETC___d23128 ? + (csrf_stcc_reg_read__6237_BITS_149_TO_86_3118_A_ETC___d23130 ? 2'd3 : 2'd1)) == ((csrf_stcc_reg_read__6237_BITS_85_TO_83_6243_UL_ETC___d16244 && - _0_CONCAT_csrf_stcc_reg_read__6237_BITS_149_TO__ETC___d23139) ? + _0_CONCAT_csrf_stcc_reg_read__6237_BITS_149_TO__ETC___d23141) ? 2'd0 : ((csrf_stcc_reg_read__6237_BITS_85_TO_83_6243_UL_ETC___d16244 && - !_0_CONCAT_csrf_stcc_reg_read__6237_BITS_149_TO__ETC___d23139) ? + !_0_CONCAT_csrf_stcc_reg_read__6237_BITS_149_TO__ETC___d23141) ? 2'd1 : ((!csrf_stcc_reg_read__6237_BITS_85_TO_83_6243_UL_ETC___d16244 && - _0_CONCAT_csrf_stcc_reg_read__6237_BITS_149_TO__ETC___d23139) ? + _0_CONCAT_csrf_stcc_reg_read__6237_BITS_149_TO__ETC___d23141) ? 2'd3 : 2'd0))) ; - assign IF_csrf_stcc_reg_read__6237_BITS_149_TO_86_311_ETC___d23150 = - IF_csrf_stcc_reg_read__6237_BITS_149_TO_86_311_ETC___d23147 && - (newAddrDiff__h1010234 == 64'd0 || - csrf_stcc_reg_read__6237_BITS_149_TO_86_3116_A_ETC___d23128 || - newAddrDiff__h1010234 == - _18446744073709551615_SL_csrf_stcc_reg_read__62_ETC___d23131) ; - assign IF_csrf_stcc_reg_read__6237_BITS_149_TO_86_311_ETC___d23172 = - ((newAddrDiff__h1010578 == 64'd0) ? + assign IF_csrf_stcc_reg_read__6237_BITS_149_TO_86_311_ETC___d23152 = + IF_csrf_stcc_reg_read__6237_BITS_149_TO_86_311_ETC___d23149 && + (newAddrDiff__h1010268 == 64'd0 || + csrf_stcc_reg_read__6237_BITS_149_TO_86_3118_A_ETC___d23130 || + newAddrDiff__h1010268 == + _18446744073709551615_SL_csrf_stcc_reg_read__62_ETC___d23133) ; + assign IF_csrf_stcc_reg_read__6237_BITS_149_TO_86_311_ETC___d23174 = + ((newAddrDiff__h1010612 == 64'd0) ? 2'd0 : - (csrf_stcc_reg_read__6237_BITS_149_TO_86_3116_A_ETC___d23156 ? + (csrf_stcc_reg_read__6237_BITS_149_TO_86_3118_A_ETC___d23158 ? 2'd3 : 2'd1)) == ((csrf_stcc_reg_read__6237_BITS_85_TO_83_6243_UL_ETC___d16244 && - _0_CONCAT_csrf_stcc_reg_read__6237_BITS_149_TO__ETC___d23164) ? + _0_CONCAT_csrf_stcc_reg_read__6237_BITS_149_TO__ETC___d23166) ? 2'd0 : ((csrf_stcc_reg_read__6237_BITS_85_TO_83_6243_UL_ETC___d16244 && - !_0_CONCAT_csrf_stcc_reg_read__6237_BITS_149_TO__ETC___d23164) ? + !_0_CONCAT_csrf_stcc_reg_read__6237_BITS_149_TO__ETC___d23166) ? 2'd1 : ((!csrf_stcc_reg_read__6237_BITS_85_TO_83_6243_UL_ETC___d16244 && - _0_CONCAT_csrf_stcc_reg_read__6237_BITS_149_TO__ETC___d23164) ? + _0_CONCAT_csrf_stcc_reg_read__6237_BITS_149_TO__ETC___d23166) ? 2'd3 : 2'd0))) ; - assign IF_csrf_stcc_reg_read__6237_BITS_149_TO_86_311_ETC___d23175 = - IF_csrf_stcc_reg_read__6237_BITS_149_TO_86_311_ETC___d23172 && - (newAddrDiff__h1010578 == 64'd0 || - csrf_stcc_reg_read__6237_BITS_149_TO_86_3116_A_ETC___d23156 || - newAddrDiff__h1010578 == - _18446744073709551615_SL_csrf_stcc_reg_read__62_ETC___d23131) ; - assign IF_csrf_stcc_reg_read__6237_BIT_86_3112_AND_NO_ETC___d23178 = - (csrf_stcc_reg[86] && cause_interrupt__h1006051) ? - (NOT_csrf_stcc_reg_read__6237_BITS_33_TO_28_625_ETC___d23115 || - IF_csrf_stcc_reg_read__6237_BITS_149_TO_86_311_ETC___d23150) && + assign IF_csrf_stcc_reg_read__6237_BITS_149_TO_86_311_ETC___d23177 = + IF_csrf_stcc_reg_read__6237_BITS_149_TO_86_311_ETC___d23174 && + (newAddrDiff__h1010612 == 64'd0 || + csrf_stcc_reg_read__6237_BITS_149_TO_86_3118_A_ETC___d23158 || + newAddrDiff__h1010612 == + _18446744073709551615_SL_csrf_stcc_reg_read__62_ETC___d23133) ; + assign IF_csrf_stcc_reg_read__6237_BIT_86_3114_AND_NO_ETC___d23180 = + (csrf_stcc_reg[86] && cause_interrupt__h1006048) ? + (NOT_csrf_stcc_reg_read__6237_BITS_33_TO_28_625_ETC___d23117 || + IF_csrf_stcc_reg_read__6237_BITS_149_TO_86_311_ETC___d23152) && csrf_stcc_reg[152] : - (NOT_csrf_stcc_reg_read__6237_BITS_33_TO_28_625_ETC___d23115 || - IF_csrf_stcc_reg_read__6237_BITS_149_TO_86_311_ETC___d23175) && + (NOT_csrf_stcc_reg_read__6237_BITS_33_TO_28_625_ETC___d23117 || + IF_csrf_stcc_reg_read__6237_BITS_149_TO_86_311_ETC___d23177) && csrf_stcc_reg[152] ; - assign IF_csrf_stcc_reg_read__6237_BIT_86_3112_AND_NO_ETC___d23280 = - (csrf_stcc_reg[86] && cause_interrupt__h1006051) ? - address__h1010161 : - base__h1010122 ; - assign IF_f_csr_reqs_first__4359_BIT_63_4513_THEN_NOT_ETC___d24523 = + assign IF_csrf_stcc_reg_read__6237_BIT_86_3114_AND_NO_ETC___d23282 = + (csrf_stcc_reg[86] && cause_interrupt__h1006048) ? + address__h1010195 : + base__h1010156 ; + assign IF_f_csr_reqs_first__4361_BIT_63_4515_THEN_NOT_ETC___d24525 = f_csr_reqs$D_OUT[63] ? - x__h1043029[13:0] >= toBounds__h1019347 : - x__h1043029[13:0] <= toBoundsM1__h1019348 ; - assign IF_f_csr_reqs_first__4359_BIT_63_4513_THEN_NOT_ETC___d24545 = + x__h1043062[13:0] >= toBounds__h1019381 : + x__h1043062[13:0] <= toBoundsM1__h1019382 ; + assign IF_f_csr_reqs_first__4361_BIT_63_4515_THEN_NOT_ETC___d24547 = f_csr_reqs$D_OUT[63] ? - x__h1043432[13:0] >= toBounds__h1019750 : - x__h1043432[13:0] <= toBoundsM1__h1019751 ; - assign IF_f_csr_reqs_first__4359_BIT_63_4513_THEN_NOT_ETC___d24603 = + x__h1043465[13:0] >= toBounds__h1019784 : + x__h1043465[13:0] <= toBoundsM1__h1019785 ; + assign IF_f_csr_reqs_first__4361_BIT_63_4515_THEN_NOT_ETC___d24605 = f_csr_reqs$D_OUT[63] ? - x__h1043849[13:0] >= toBounds__h1020167 : - x__h1043849[13:0] <= toBoundsM1__h1020168 ; - assign IF_f_csr_reqs_first__4359_BIT_63_4513_THEN_NOT_ETC___d24623 = + x__h1043882[13:0] >= toBounds__h1020201 : + x__h1043882[13:0] <= toBoundsM1__h1020202 ; + assign IF_f_csr_reqs_first__4361_BIT_63_4515_THEN_NOT_ETC___d24625 = f_csr_reqs$D_OUT[63] ? - x__h1044252[13:0] >= toBounds__h1020570 : - x__h1044252[13:0] <= toBoundsM1__h1020571 ; - assign IF_f_csr_reqs_first__4359_BIT_63_4513_THEN_NOT_ETC___d24694 = + x__h1044285[13:0] >= toBounds__h1020604 : + x__h1044285[13:0] <= toBoundsM1__h1020605 ; + assign IF_f_csr_reqs_first__4361_BIT_63_4515_THEN_NOT_ETC___d24696 = f_csr_reqs$D_OUT[63] ? - x__h1044919[13:0] >= toBounds__h1021239 : - x__h1044919[13:0] <= toBoundsM1__h1021240 ; + x__h1044952[13:0] >= toBounds__h1021273 : + x__h1044952[13:0] <= toBoundsM1__h1021274 ; assign IF_fetchStage_RDY_pipelines_0_first__0541_AND__ETC___d21486 = (fetchStage$RDY_pipelines_0_first && (fetchStage$pipelines_0_first[268:266] != 3'd1 || @@ -26554,9 +26552,9 @@ module mkCore(CLK, IF_fetchStage_pipelines_0_first__0544_BITS_268_ETC___d21578 ; assign IF_fetchStage_pipelines_0_first__0544_BITS_268_ETC___d22166 = IF_fetchStage_pipelines_0_first__0544_BITS_268_ETC___d22159 || - rob$RDY_enqPort_0_enq && - regRenamingTable$RDY_rename_0_getRename && regRenamingTable$RDY_rename_0_claimRename && + regRenamingTable$RDY_rename_0_getRename && + rob$RDY_enqPort_0_enq && fetchStage$RDY_pipelines_0_deq && (fetchStage$pipelines_0_first[268:266] != 3'd1 || specTagManager$RDY_claimSpecTag) ; @@ -26707,9 +26705,9 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__0553_BITS_268_ETC___d22254 && IF_fetchStage_RDY_pipelines_1_first__0552_AND__ETC___d22042 && (IF_fetchStage_pipelines_1_first__0553_BITS_268_ETC___d22283 || - rob$RDY_enqPort_1_enq && - regRenamingTable$RDY_rename_1_getRename && regRenamingTable$RDY_rename_1_claimRename && + regRenamingTable$RDY_rename_1_getRename && + rob$RDY_enqPort_1_enq && fetchStage_RDY_pipelines_1_deq__0556_AND_NOT_f_ETC___d22293) ; assign IF_mmio_cRqQ_enqReq_lat_1_whas__87_THEN_mmio_c_ETC___d296 = mmio_cRqQ_enqReq_lat_0$whas ? @@ -26795,44 +26793,44 @@ module mkCore(CLK, !rf_read_3_rd2_coreFix_memExe_dispToRegQ_first__ETC___d3628) ? 2'd1 : 2'd3) } ; - assign IF_rob_deqPort_0_canDeq__3983_THEN_IF_NOT_rob__ETC___d24105 = + assign IF_rob_deqPort_0_canDeq__3985_THEN_IF_NOT_rob__ETC___d24107 = rob$deqPort_0_canDeq ? - y_avValue_snd_snd_snd_snd_snd__h1027231 : + y_avValue_snd_snd_snd_snd_snd__h1027265 : 64'd0 ; - assign IF_rob_deqPort_0_canDeq__3983_THEN_IF_NOT_rob__ETC___d24215 = - rob$deqPort_0_canDeq ? y_avValue_snd_fst__h1027215 : 5'd0 ; - assign IF_rob_deqPort_0_canDeq__3983_THEN_IF_NOT_rob__ETC___d24237 = + assign IF_rob_deqPort_0_canDeq__3985_THEN_IF_NOT_rob__ETC___d24217 = + rob$deqPort_0_canDeq ? y_avValue_snd_fst__h1027249 : 5'd0 ; + assign IF_rob_deqPort_0_canDeq__3985_THEN_IF_NOT_rob__ETC___d24239 = rob$deqPort_0_canDeq ? - y_avValue_snd_snd_snd_fst__h1027225 : + y_avValue_snd_snd_snd_fst__h1027259 : 2'd0 ; - assign IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_19_ETC___d23510 = - (highOffsetBits__h1019338 == 50'd0 && - IF_IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_ETC___d23507 || - NOT_csrf_stcc_reg_read__6237_BITS_33_TO_28_625_ETC___d23115) && + assign IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_19_ETC___d23512 = + (highOffsetBits__h1019372 == 50'd0 && + IF_IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_ETC___d23509 || + NOT_csrf_stcc_reg_read__6237_BITS_33_TO_28_625_ETC___d23117) && csrf_stcc_reg[152] ; - assign IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_19_ETC___d23556 = - (highOffsetBits__h1019741 == 50'd0 && - IF_IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_ETC___d23551 || - NOT_IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN__ETC___d23554) && + assign IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_19_ETC___d23558 = + (highOffsetBits__h1019775 == 50'd0 && + IF_IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_ETC___d23553 || + NOT_IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN__ETC___d23556) && IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16993 ; - assign IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_19_ETC___d23649 = - (highOffsetBits__h1020158 == 50'd0 && - IF_IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_ETC___d23646 || - NOT_csrf_mtcc_reg_read__6389_BITS_33_TO_28_640_ETC___d23186) && + assign IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_19_ETC___d23651 = + (highOffsetBits__h1020192 == 50'd0 && + IF_IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_ETC___d23648 || + NOT_csrf_mtcc_reg_read__6389_BITS_33_TO_28_640_ETC___d23188) && csrf_mtcc_reg[152] ; - assign IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_19_ETC___d23693 = - (highOffsetBits__h1020561 == 50'd0 && - IF_IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_ETC___d23688 || - NOT_IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN__ETC___d23691) && + assign IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_19_ETC___d23695 = + (highOffsetBits__h1020595 == 50'd0 && + IF_IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_ETC___d23690 || + NOT_IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN__ETC___d23693) && IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17001 ; - assign IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_19_ETC___d23807 = - (highOffsetBits__h1021230 == 50'd0 && - IF_IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_ETC___d23801 || - NOT_csrf_rg_dpc_read__6534_BITS_33_TO_28_6551__ETC___d23804) && + assign IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_19_ETC___d23809 = + (highOffsetBits__h1021264 == 50'd0 && + IF_IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_ETC___d23803 || + NOT_csrf_rg_dpc_read__6534_BITS_33_TO_28_6551__ETC___d23806) && csrf_rg_dpc[152] ; - assign IF_rob_deqPort_1_canDeq__3987_THEN_IF_NOT_rob__ETC___d24229 = + assign IF_rob_deqPort_1_canDeq__3989_THEN_IF_NOT_rob__ETC___d24231 = rob$deqPort_1_canDeq ? - IF_NOT_rob_deqPort_1_deq_data__3990_BIT_25_399_ETC___d24228 : + IF_NOT_rob_deqPort_1_deq_data__3992_BIT_25_399_ETC___d24230 : rob$deqPort_0_canDeq && rob$deqPort_0_deq_data[26] ; assign IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d19009 = sbCons$lazyLookup_0_get[3] ? @@ -26962,7 +26960,7 @@ module mkCore(CLK, IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__863_ETC___d19319) ; assign IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d19341 = sbCons$lazyLookup_0_get[3] ? - repBound__h905963 : + repBound__h905960 : (NOT_coreFix_aluExe_0_bypassWire_0_whas__8635_8_ETC___d18662 ? coreFix_aluExe_0_bypassWire_3$wget[9:7] : IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__863_ETC___d19337) ; @@ -26993,7 +26991,7 @@ module mkCore(CLK, assign IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d19438 = sbCons$lazyLookup_0_get[2] ? { rf$read_0_rd2, - repBound__h908290, + repBound__h908287, rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19413, rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19414, rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19426 } : @@ -27128,7 +27126,7 @@ module mkCore(CLK, IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__581_ETC___d16865) ; assign IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16887 = sbCons$lazyLookup_1_get[3] ? - repBound__h863992 : + repBound__h863990 : (NOT_coreFix_aluExe_1_bypassWire_0_whas__5813_5_ETC___d15840 ? coreFix_aluExe_0_bypassWire_3$wget[9:7] : IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__581_ETC___d16883) ; @@ -27159,7 +27157,7 @@ module mkCore(CLK, assign IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16984 = sbCons$lazyLookup_1_get[2] ? { rf$read_1_rd2, - repBound__h866954, + repBound__h866952, rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16959, rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16960, rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16972 } : @@ -27294,7 +27292,7 @@ module mkCore(CLK, IF_NOT_coreFix_memExe_bypassWire_0_whas__716_7_ETC___d3331) ; assign IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3353 = sbCons$lazyLookup_3_get[3] ? - repBound__h240209 : + repBound__h240206 : (NOT_coreFix_memExe_bypassWire_0_whas__716_722__ETC___d2743 ? coreFix_aluExe_0_bypassWire_3$wget[9:7] : IF_NOT_coreFix_memExe_bypassWire_0_whas__716_7_ETC___d3349) ; @@ -27450,7 +27448,7 @@ module mkCore(CLK, IF_NOT_coreFix_memExe_bypassWire_0_whas__716_7_ETC___d3591) ; assign IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3608 = sbCons$lazyLookup_3_get[2] ? - repBound__h241894 : + repBound__h241891 : (NOT_coreFix_memExe_bypassWire_0_whas__716_722__ETC___d2774 ? coreFix_aluExe_0_bypassWire_3$wget[9:7] : IF_NOT_coreFix_memExe_bypassWire_0_whas__716_7_ETC___d3604) ; @@ -27478,64 +27476,64 @@ module mkCore(CLK, (NOT_coreFix_memExe_bypassWire_0_whas__716_722__ETC___d2774 ? coreFix_aluExe_0_bypassWire_3$wget[3:0] : IF_NOT_coreFix_memExe_bypassWire_0_whas__716_7_ETC___d3647) ; - assign IF_sfdin06750_BIT_33_THEN_2_ELSE_0__q52 = - sfdin__h606750[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin26948_BIT_4_THEN_2_ELSE_0__q168 = - sfdin__h826948[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin34733_BIT_33_THEN_2_ELSE_0__q77 = - sfdin__h634733[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin48791_BIT_4_THEN_2_ELSE_0__q151 = - sfdin__h748791[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin52499_BIT_33_THEN_2_ELSE_0__q87 = - sfdin__h652499[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin80480_BIT_33_THEN_2_ELSE_0__q112 = - sfdin__h680480[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin87644_BIT_4_THEN_2_ELSE_0__q191 = - sfdin__h787644[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin88984_BIT_33_THEN_2_ELSE_0__q44 = - sfdin__h588984[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin98246_BIT_33_THEN_2_ELSE_0__q122 = - sfdin__h698246[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd06883_BIT_33_THEN_2_ELSE_0__q127 = - _theResult___snd__h706883[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd15387_BIT_33_THEN_2_ELSE_0__q57 = - _theResult___snd__h615387[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd17328_BIT_4_THEN_2_ELSE_0__q164 = - _theResult___snd__h817328[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd35733_BIT_4_THEN_2_ELSE_0__q171 = - _theResult___snd__h835733[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd39171_BIT_4_THEN_2_ELSE_0__q147 = - _theResult___snd__h739171[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd43346_BIT_33_THEN_2_ELSE_0__q79 = - _theResult___snd__h643346[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd57576_BIT_4_THEN_2_ELSE_0__q154 = - _theResult___snd__h757576[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd61136_BIT_33_THEN_2_ELSE_0__q92 = - _theResult___snd__h661136[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd78024_BIT_4_THEN_2_ELSE_0__q187 = - _theResult___snd__h778024[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd89093_BIT_33_THEN_2_ELSE_0__q114 = - _theResult___snd__h689093[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd96429_BIT_4_THEN_2_ELSE_0__q194 = - _theResult___snd__h796429[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd97597_BIT_33_THEN_2_ELSE_0__q46 = - _theResult___snd__h597597[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin06747_BIT_33_THEN_2_ELSE_0__q52 = + sfdin__h606747[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin26944_BIT_4_THEN_2_ELSE_0__q168 = + sfdin__h826944[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin34730_BIT_33_THEN_2_ELSE_0__q77 = + sfdin__h634730[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin48787_BIT_4_THEN_2_ELSE_0__q151 = + sfdin__h748787[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin52496_BIT_33_THEN_2_ELSE_0__q87 = + sfdin__h652496[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin80477_BIT_33_THEN_2_ELSE_0__q112 = + sfdin__h680477[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin87640_BIT_4_THEN_2_ELSE_0__q191 = + sfdin__h787640[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin88981_BIT_33_THEN_2_ELSE_0__q42 = + sfdin__h588981[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin98243_BIT_33_THEN_2_ELSE_0__q122 = + sfdin__h698243[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd06880_BIT_33_THEN_2_ELSE_0__q127 = + _theResult___snd__h706880[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd15384_BIT_33_THEN_2_ELSE_0__q57 = + _theResult___snd__h615384[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd17324_BIT_4_THEN_2_ELSE_0__q164 = + _theResult___snd__h817324[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd35729_BIT_4_THEN_2_ELSE_0__q171 = + _theResult___snd__h835729[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd39167_BIT_4_THEN_2_ELSE_0__q147 = + _theResult___snd__h739167[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd43343_BIT_33_THEN_2_ELSE_0__q79 = + _theResult___snd__h643343[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd57572_BIT_4_THEN_2_ELSE_0__q154 = + _theResult___snd__h757572[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd61133_BIT_33_THEN_2_ELSE_0__q92 = + _theResult___snd__h661133[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd78020_BIT_4_THEN_2_ELSE_0__q187 = + _theResult___snd__h778020[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd89090_BIT_33_THEN_2_ELSE_0__q114 = + _theResult___snd__h689090[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd96425_BIT_4_THEN_2_ELSE_0__q194 = + _theResult___snd__h796425[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd97594_BIT_33_THEN_2_ELSE_0__q44 = + _theResult___snd__h597594[33] ? 2'd2 : 2'd0 ; assign INV_commitStage_commitTrap_BITS_217_TO_199__q15 = ~commitStage_commitTrap[217:199] ; assign INV_coreFix_aluExe_0_regToExeQ_first__9699_BIT_ETC___d20014 = { ~coreFix_aluExe_0_regToExeQ$first[286:268], INV_coreFix_aluExe_0_regToExeQfirst_BITS_286__ETC__q13[0] ? - x__h913873 : + x__h913870 : 6'd0, - x__h914046, - x__h914066 } ; + x__h914043, + x__h914063 } ; assign INV_coreFix_aluExe_0_regToExeQ_first__9699_BIT_ETC___d20078 = { ~coreFix_aluExe_0_regToExeQ$first[157:139], INV_coreFix_aluExe_0_regToExeQfirst_BITS_157__ETC__q14[0] ? - x__h914421 : + x__h914418 : 6'd0, - x__h914594, - x__h914614 } ; + x__h914591, + x__h914611 } ; assign INV_coreFix_aluExe_0_regToExeQfirst_BITS_157__ETC__q14 = ~coreFix_aluExe_0_regToExeQ$first[157:139] ; assign INV_coreFix_aluExe_0_regToExeQfirst_BITS_286__ETC__q13 = @@ -27543,17 +27541,17 @@ module mkCore(CLK, assign INV_coreFix_aluExe_1_regToExeQ_first__7524_BIT_ETC___d17839 = { ~coreFix_aluExe_1_regToExeQ$first[286:268], INV_coreFix_aluExe_1_regToExeQfirst_BITS_286__ETC__q11[0] ? - x__h872832 : + x__h872830 : 6'd0, - x__h873005, - x__h873025 } ; + x__h873003, + x__h873023 } ; assign INV_coreFix_aluExe_1_regToExeQ_first__7524_BIT_ETC___d17903 = { ~coreFix_aluExe_1_regToExeQ$first[157:139], INV_coreFix_aluExe_1_regToExeQfirst_BITS_157__ETC__q12[0] ? - x__h873380 : + x__h873378 : 6'd0, - x__h873553, - x__h873573 } ; + x__h873551, + x__h873571 } ; assign INV_coreFix_aluExe_1_regToExeQfirst_BITS_157__ETC__q12 = ~coreFix_aluExe_1_regToExeQ$first[157:139] ; assign INV_coreFix_aluExe_1_regToExeQfirst_BITS_286__ETC__q11 = @@ -27564,8 +27562,8 @@ module mkCore(CLK, ~coreFix_memExe_respLrScAmoQ_data_0[108:90] ; assign INV_mmio_dataRespQ_data_0_BITS_108_TO_90__q9 = ~mmio_dataRespQ_data_0[108:90] ; - assign INV_x01338_BITS_108_TO_90__q37 = ~x__h201338[108:90] ; - assign INV_x85174_BITS_108_TO_90__q35 = ~x__h185174[108:90] ; + assign INV_x01336_BITS_108_TO_90__q37 = ~x__h201336[108:90] ; + assign INV_x85172_BITS_108_TO_90__q35 = ~x__h185172[108:90] ; assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d10837 = !_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9623 || (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9624 ? @@ -27653,136 +27651,166 @@ module mkCore(CLK, !IF_IF_NOT_csrf_prv_reg_read__0574_EQ_3_0575_05_ETC___d20611[15] && !checkForException___d21903[13] && NOT_csrf_fs_reg_read__6201_EQ_0_0928_0929_OR_N_ETC___d21928 ; - assign NOT_IF_NOT_rob_deqPort_0_canDeq__3983_3984_OR__ETC___d24234 = - (fflags__h1027798 & csrf_fflags_reg) != fflags__h1027798 || - !r__h859554 && - (IF_rob_deqPort_1_canDeq__3987_THEN_IF_NOT_rob__ETC___d24229 || - fflags__h1027798 != 5'd0) ; + assign NOT_IF_NOT_rob_deqPort_0_canDeq__3985_3986_OR__ETC___d24236 = + (fflags__h1027832 & csrf_fflags_reg) != fflags__h1027832 || + !r__h859552 && + (IF_rob_deqPort_1_canDeq__3989_THEN_IF_NOT_rob__ETC___d24231 || + fflags__h1027832 != 5'd0) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d12813 = - !f1_sfd__h719833[21] && !f1_sfd__h719833[20] && - !f1_sfd__h719833[19] && - !f1_sfd__h719833[18] && - !f1_sfd__h719833[17] && - !f1_sfd__h719833[16] && - !f1_sfd__h719833[15] && - !f1_sfd__h719833[14] && - !f1_sfd__h719833[13] && - !f1_sfd__h719833[12] && - !f1_sfd__h719833[11] && - !f1_sfd__h719833[10] && - !f1_sfd__h719833[9] && - !f1_sfd__h719833[8] && - !f1_sfd__h719833[7] && - !f1_sfd__h719833[6] && - !f1_sfd__h719833[5] && - !f1_sfd__h719833[4] && - !f1_sfd__h719833[3] && - !f1_sfd__h719833[2] && - !f1_sfd__h719833[1] && - !f1_sfd__h719833[0] ; + !f1_sfd__h719829[21] && !f1_sfd__h719829[20] && + !f1_sfd__h719829[19] && + !f1_sfd__h719829[18] && + !f1_sfd__h719829[17] && + !f1_sfd__h719829[16] && + !f1_sfd__h719829[15] && + !f1_sfd__h719829[14] && + !f1_sfd__h719829[13] && + !f1_sfd__h719829[12] && + !f1_sfd__h719829[11] && + !f1_sfd__h719829[10] && + !f1_sfd__h719829[9] && + !f1_sfd__h719829[8] && + !f1_sfd__h719829[7] && + !f1_sfd__h719829[6] && + !f1_sfd__h719829[5] && + !f1_sfd__h719829[4] && + !f1_sfd__h719829[3] && + !f1_sfd__h719829[2] && + !f1_sfd__h719829[1] && + !f1_sfd__h719829[0] ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d13543 = - !f3_sfd__h798131[21] && !f3_sfd__h798131[20] && - !f3_sfd__h798131[19] && - !f3_sfd__h798131[18] && - !f3_sfd__h798131[17] && - !f3_sfd__h798131[16] && - !f3_sfd__h798131[15] && - !f3_sfd__h798131[14] && - !f3_sfd__h798131[13] && - !f3_sfd__h798131[12] && - !f3_sfd__h798131[11] && - !f3_sfd__h798131[10] && - !f3_sfd__h798131[9] && - !f3_sfd__h798131[8] && - !f3_sfd__h798131[7] && - !f3_sfd__h798131[6] && - !f3_sfd__h798131[5] && - !f3_sfd__h798131[4] && - !f3_sfd__h798131[3] && - !f3_sfd__h798131[2] && - !f3_sfd__h798131[1] && - !f3_sfd__h798131[0] ; + !f3_sfd__h798127[21] && !f3_sfd__h798127[20] && + !f3_sfd__h798127[19] && + !f3_sfd__h798127[18] && + !f3_sfd__h798127[17] && + !f3_sfd__h798127[16] && + !f3_sfd__h798127[15] && + !f3_sfd__h798127[14] && + !f3_sfd__h798127[13] && + !f3_sfd__h798127[12] && + !f3_sfd__h798127[11] && + !f3_sfd__h798127[10] && + !f3_sfd__h798127[9] && + !f3_sfd__h798127[8] && + !f3_sfd__h798127[7] && + !f3_sfd__h798127[6] && + !f3_sfd__h798127[5] && + !f3_sfd__h798127[4] && + !f3_sfd__h798127[3] && + !f3_sfd__h798127[2] && + !f3_sfd__h798127[1] && + !f3_sfd__h798127[0] ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d14313 = - !f2_sfd__h758827[21] && !f2_sfd__h758827[20] && - !f2_sfd__h758827[19] && - !f2_sfd__h758827[18] && - !f2_sfd__h758827[17] && - !f2_sfd__h758827[16] && - !f2_sfd__h758827[15] && - !f2_sfd__h758827[14] && - !f2_sfd__h758827[13] && - !f2_sfd__h758827[12] && - !f2_sfd__h758827[11] && - !f2_sfd__h758827[10] && - !f2_sfd__h758827[9] && - !f2_sfd__h758827[8] && - !f2_sfd__h758827[7] && - !f2_sfd__h758827[6] && - !f2_sfd__h758827[5] && - !f2_sfd__h758827[4] && - !f2_sfd__h758827[3] && - !f2_sfd__h758827[2] && - !f2_sfd__h758827[1] && - !f2_sfd__h758827[0] ; + !f2_sfd__h758823[21] && !f2_sfd__h758823[20] && + !f2_sfd__h758823[19] && + !f2_sfd__h758823[18] && + !f2_sfd__h758823[17] && + !f2_sfd__h758823[16] && + !f2_sfd__h758823[15] && + !f2_sfd__h758823[14] && + !f2_sfd__h758823[13] && + !f2_sfd__h758823[12] && + !f2_sfd__h758823[11] && + !f2_sfd__h758823[10] && + !f2_sfd__h758823[9] && + !f2_sfd__h758823[8] && + !f2_sfd__h758823[7] && + !f2_sfd__h758823[6] && + !f2_sfd__h758823[5] && + !f2_sfd__h758823[4] && + !f2_sfd__h758823[3] && + !f2_sfd__h758823[2] && + !f2_sfd__h758823[1] && + !f2_sfd__h758823[0] ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15022 = - (f1_exp__h719832 != 8'd255 || f1_sfd__h719833 == 23'd0) && - (f1_exp__h719832 != 8'd255 || f1_sfd__h719833 != 23'd0) && - (f1_exp__h719832 != 8'd0 || f1_sfd__h719833 != 23'd0) && + (f1_exp__h719828 != 8'd255 || f1_sfd__h719829 == 23'd0) && + (f1_exp__h719828 != 8'd255 || f1_sfd__h719829 != 23'd0) && + (f1_exp__h719828 != 8'd0 || f1_sfd__h719829 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15019 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15064 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15022 | - ((f2_exp__h758826 != 8'd255 || f2_sfd__h758827 == 23'd0) && - (f2_exp__h758826 != 8'd255 || f2_sfd__h758827 != 23'd0) && - (f2_exp__h758826 != 8'd0 || f2_sfd__h758827 != 23'd0) && + ((f2_exp__h758822 != 8'd255 || f2_sfd__h758823 == 23'd0) && + (f2_exp__h758822 != 8'd255 || f2_sfd__h758823 != 23'd0) && + (f2_exp__h758822 != 8'd0 || f2_sfd__h758823 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15060) ; + assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15108 = + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15064 | + ((f3_exp__h798126 != 8'd255 || f3_sfd__h798127 == 23'd0) && + (f3_exp__h798126 != 8'd255 || f3_sfd__h798127 != 23'd0) && + (value_BIT_23___h810070 || f3_sfd__h798127 != 23'd0) && + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15104) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15122 = - (f1_exp__h719832 != 8'd255 || f1_sfd__h719833 == 23'd0) && - (f1_exp__h719832 != 8'd255 || f1_sfd__h719833 != 23'd0) && - (f1_exp__h719832 != 8'd0 || f1_sfd__h719833 != 23'd0) && + (f1_exp__h719828 != 8'd255 || f1_sfd__h719829 == 23'd0) && + (f1_exp__h719828 != 8'd255 || f1_sfd__h719829 != 23'd0) && + (f1_exp__h719828 != 8'd0 || f1_sfd__h719829 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15119 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15133 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15122 | - ((f2_exp__h758826 != 8'd255 || f2_sfd__h758827 == 23'd0) && - (f2_exp__h758826 != 8'd255 || f2_sfd__h758827 != 23'd0) && - (f2_exp__h758826 != 8'd0 || f2_sfd__h758827 != 23'd0) && + ((f2_exp__h758822 != 8'd255 || f2_sfd__h758823 == 23'd0) && + (f2_exp__h758822 != 8'd255 || f2_sfd__h758823 != 23'd0) && + (f2_exp__h758822 != 8'd0 || f2_sfd__h758823 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15129) ; + assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15144 = + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15133 | + ((f3_exp__h798126 != 8'd255 || f3_sfd__h798127 == 23'd0) && + (f3_exp__h798126 != 8'd255 || f3_sfd__h798127 != 23'd0) && + (value_BIT_23___h810070 || f3_sfd__h798127 != 23'd0) && + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15140) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15162 = - (f1_exp__h719832 != 8'd255 || f1_sfd__h719833 == 23'd0) && - (f1_exp__h719832 != 8'd255 || f1_sfd__h719833 != 23'd0) && - (f1_exp__h719832 != 8'd0 || f1_sfd__h719833 != 23'd0) && + (f1_exp__h719828 != 8'd255 || f1_sfd__h719829 == 23'd0) && + (f1_exp__h719828 != 8'd255 || f1_sfd__h719829 != 23'd0) && + (f1_exp__h719828 != 8'd0 || f1_sfd__h719829 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15159 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15177 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15162 | - ((f2_exp__h758826 != 8'd255 || f2_sfd__h758827 == 23'd0) && - (f2_exp__h758826 != 8'd255 || f2_sfd__h758827 != 23'd0) && - (f2_exp__h758826 != 8'd0 || f2_sfd__h758827 != 23'd0) && + ((f2_exp__h758822 != 8'd255 || f2_sfd__h758823 == 23'd0) && + (f2_exp__h758822 != 8'd255 || f2_sfd__h758823 != 23'd0) && + (f2_exp__h758822 != 8'd0 || f2_sfd__h758823 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15173) ; + assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15192 = + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15177 | + ((f3_exp__h798126 != 8'd255 || f3_sfd__h798127 == 23'd0) && + (f3_exp__h798126 != 8'd255 || f3_sfd__h798127 != 23'd0) && + (value_BIT_23___h810070 || f3_sfd__h798127 != 23'd0) && + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15188) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15208 = - (f1_exp__h719832 != 8'd255 || f1_sfd__h719833 == 23'd0) && - (f1_exp__h719832 != 8'd255 || f1_sfd__h719833 != 23'd0) && - (f1_exp__h719832 != 8'd0 || f1_sfd__h719833 != 23'd0) && + (f1_exp__h719828 != 8'd255 || f1_sfd__h719829 == 23'd0) && + (f1_exp__h719828 != 8'd255 || f1_sfd__h719829 != 23'd0) && + (f1_exp__h719828 != 8'd0 || f1_sfd__h719829 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15205 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15221 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15208 | - ((f2_exp__h758826 != 8'd255 || f2_sfd__h758827 == 23'd0) && - (f2_exp__h758826 != 8'd255 || f2_sfd__h758827 != 23'd0) && - (f2_exp__h758826 != 8'd0 || f2_sfd__h758827 != 23'd0) && + ((f2_exp__h758822 != 8'd255 || f2_sfd__h758823 == 23'd0) && + (f2_exp__h758822 != 8'd255 || f2_sfd__h758823 != 23'd0) && + (f2_exp__h758822 != 8'd0 || f2_sfd__h758823 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15217) ; + assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15234 = + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15221 | + ((f3_exp__h798126 != 8'd255 || f3_sfd__h798127 == 23'd0) && + (f3_exp__h798126 != 8'd255 || f3_sfd__h798127 != 23'd0) && + (value_BIT_23___h810070 || f3_sfd__h798127 != 23'd0) && + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15230) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15250 = - (f1_exp__h719832 != 8'd255 || f1_sfd__h719833 == 23'd0) && - (f1_exp__h719832 != 8'd255 || f1_sfd__h719833 != 23'd0) && - (f1_exp__h719832 != 8'd0 || f1_sfd__h719833 != 23'd0) && + (f1_exp__h719828 != 8'd255 || f1_sfd__h719829 == 23'd0) && + (f1_exp__h719828 != 8'd255 || f1_sfd__h719829 != 23'd0) && + (f1_exp__h719828 != 8'd0 || f1_sfd__h719829 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15247 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15263 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15250 | - ((f2_exp__h758826 != 8'd255 || f2_sfd__h758827 == 23'd0) && - (f2_exp__h758826 != 8'd255 || f2_sfd__h758827 != 23'd0) && - (f2_exp__h758826 != 8'd0 || f2_sfd__h758827 != 23'd0) && + ((f2_exp__h758822 != 8'd255 || f2_sfd__h758823 == 23'd0) && + (f2_exp__h758822 != 8'd255 || f2_sfd__h758823 != 23'd0) && + (f2_exp__h758822 != 8'd0 || f2_sfd__h758823 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15259) ; - assign NOT_IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN__ETC___d23691 = + assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15276 = + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15263 | + ((f3_exp__h798126 != 8'd255 || f3_sfd__h798127 == 23'd0) && + (f3_exp__h798126 != 8'd255 || f3_sfd__h798127 != 23'd0) && + (value_BIT_23___h810070 || f3_sfd__h798127 != 23'd0) && + IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15272) ; + assign NOT_IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN__ETC___d23693 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16443 >= 6'd50 ; - assign NOT_IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN__ETC___d23554 = + assign NOT_IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN__ETC___d23556 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16291 >= 6'd50 ; assign NOT_commitStage_commitTrap_2639_BITS_44_TO_43__ETC___d22910 = @@ -27805,7 +27833,7 @@ module mkCore(CLK, coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty && fetchStage$iTlbIfc_noPendingReq && coreFix_memExe_dTlb$noPendingReq ; - assign NOT_commitStage_rg_run_state_2637_2638_AND_NOT_ETC___d23408 = + assign NOT_commitStage_rg_run_state_2637_2638_AND_NOT_ETC___d23410 = !commitStage_rg_run_state && !commitStage_commitTrap[238] && !rob$deqPort_0_deq_data[274] && !rob$deqPort_0_deq_data[18] && @@ -28306,7 +28334,7 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[5] ; assign NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__26_ETC___d12686 = coreFix_fpuMulDivExe_0_regToExeQ$first[254:252] != 3'd3 || - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q316 ; + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q318 ; assign NOT_coreFix_memExe_bypassWire_0_whas__716_722__ETC___d2743 = (!coreFix_aluExe_0_bypassWire_0$whas || !coreFix_memExe_bypassWire_0_wget__717_BITS_169_ETC___d2719) && @@ -28616,17 +28644,14 @@ module mkCore(CLK, (fetchStage$pipelines_1_first[305:274] != 32'h10500073 || !csrf_tw_reg || csrf_prv_reg == 2'd3) ; - assign NOT_csrf_mtcc_reg_read__6389_BITS_33_TO_28_640_ETC___d23186 = + assign NOT_csrf_mtcc_reg_read__6389_BITS_33_TO_28_640_ETC___d23188 = csrf_mtcc_reg[33:28] >= 6'd50 ; - assign NOT_csrf_prv_reg_read__0574_ULE_1_2990_3105_OR_ETC___d23110 = + assign NOT_csrf_prv_reg_read__0574_ULE_1_2990_3106_OR_ETC___d23112 = !csrf_prv_reg_read__0574_ULE_1___d22990 || - ((commitStage_commitTrap[44:43] == 2'd1) ? - !_0b0_CONCAT_csrf_medeleg_28_26_reg_read__6352_6_ETC___d23018 : - commitStage_commitTrap[44:43] == 2'd0 || - !_0b0_CONCAT_csrf_mideleg_11_reg_read__6363_6364_ETC___d23020) ; - assign NOT_csrf_rg_dpc_read__6534_BITS_33_TO_28_6551__ETC___d23804 = + CASE_commitStage_commitTrap_BITS_44_TO_43_0_NO_ETC__q277 ; + assign NOT_csrf_rg_dpc_read__6534_BITS_33_TO_28_6551__ETC___d23806 = csrf_rg_dpc[33:28] >= 6'd50 ; - assign NOT_csrf_stcc_reg_read__6237_BITS_33_TO_28_625_ETC___d23115 = + assign NOT_csrf_stcc_reg_read__6237_BITS_33_TO_28_625_ETC___d23117 = csrf_stcc_reg[33:28] >= 6'd50 ; assign NOT_fetchStage_pipelines_0_canDeq__0542_0543_O_ETC___d21582 = !fetchStage$pipelines_0_canDeq || @@ -28769,7 +28794,7 @@ module mkCore(CLK, SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__1491_co_ETC___d21524 ; assign NOT_fetchStage_pipelines_0_first__0544_BITS_46_ETC___d22338 = fetchStage$pipelines_0_first[462:334] != - fallthrough_pc__h948608 ; + fallthrough_pc__h948605 ; assign NOT_fetchStage_pipelines_0_first__0544_BIT_69__ETC___d21014 = !fetchStage$pipelines_0_first[69] && !IF_IF_NOT_csrf_prv_reg_read__0574_EQ_3_0575_05_ETC___d20611[0] && @@ -28849,7 +28874,7 @@ module mkCore(CLK, SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__054_ETC___d22215 ; assign NOT_fetchStage_pipelines_1_first__0553_BITS_46_ETC___d22522 = fetchStage$pipelines_1_first[462:334] != - fallthrough_pc__h973095 ; + fallthrough_pc__h973092 ; assign NOT_fetchStage_pipelines_1_first__0553_BIT_69__ETC___d22460 = !fetchStage$pipelines_1_first[69] && !checkForException___d21903[13] && @@ -28858,12 +28883,12 @@ module mkCore(CLK, epochManager$checkEpoch_1_check ; assign NOT_mmio_dataPendQ_empty_80_382_AND_rob_RDY_se_ETC___d1383 = !mmio_dataPendQ_empty && rob$RDY_setExecuted_deqLSQ && - coreFix_memExe_lsq$RDY_firstSt && - coreFix_memExe_lsq$RDY_deqSt ; + coreFix_memExe_lsq$RDY_deqSt && + coreFix_memExe_lsq$RDY_firstSt ; assign NOT_mmio_dataPendQ_empty_80_382_AND_rob_RDY_se_ETC___d2032 = !mmio_dataPendQ_empty && rob$RDY_setExecuted_deqLSQ && - coreFix_memExe_lsq$RDY_firstLd && - coreFix_memExe_lsq$RDY_deqLd ; + coreFix_memExe_lsq$RDY_deqLd && + coreFix_memExe_lsq$RDY_firstLd ; assign NOT_regRenamingTable_rename_0_canRename__1456__ETC___d21966 = !regRenamingTable$rename_0_canRename || fetchStage$pipelines_0_first[273:269] == 5'd0 || @@ -28938,14 +28963,14 @@ module mkCore(CLK, epochManager$checkEpoch_1_check && (!fetchStage$pipelines_0_canDeq || NOT_fetchStage_pipelines_0_first__0544_BITS_26_ETC___d22104) ; - assign NOT_rob_deqPort_0_canDeq__3983_3984_OR_rob_RDY_ETC___d24024 = + assign NOT_rob_deqPort_0_canDeq__3985_3986_OR_regRena_ETC___d24026 = (!rob$deqPort_0_canDeq || - rob$RDY_deqPort_0_deq && - regRenamingTable$RDY_commit_0_commit) && + regRenamingTable$RDY_commit_0_commit && + rob$RDY_deqPort_0_deq) && (!rob$deqPort_1_canDeq || rob$RDY_deqPort_1_deq_data && - NOT_rob_deqPort_1_deq_data__3990_BIT_25_3991_3_ETC___d24021) ; - assign NOT_rob_deqPort_0_canDeq__3983_3984_OR_rob_deq_ETC___d24208 = + NOT_rob_deqPort_1_deq_data__3992_BIT_25_3993_3_ETC___d24023) ; + assign NOT_rob_deqPort_0_canDeq__3985_3986_OR_rob_deq_ETC___d24210 = (!rob$deqPort_0_canDeq || rob$deqPort_0_deq_data[25] && !rob$deqPort_0_deq_data[18] && !rob$deqPort_0_deq_data[274] && @@ -28960,15 +28985,15 @@ module mkCore(CLK, rob$deqPort_0_deq_data[469:465] != 5'd24 && rob$deqPort_0_deq_data[469:465] != 5'd25) && rob$deqPort_1_canDeq ; - assign NOT_rob_deqPort_0_deq_data__2632_BITS_469_TO_4_ETC___d23398 = + assign NOT_rob_deqPort_0_deq_data__2632_BITS_469_TO_4_ETC___d23400 = rob$deqPort_0_deq_data[469:465] != 5'd17 || - (IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 != + (IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 != 6'd7 || csrf_stats_module_writeQ$FULL_N) && - (IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 != + (IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 != 6'd6 || csrf_terminate_module_terminateQ$FULL_N) ; - assign NOT_rob_deqPort_1_deq_data__3990_BIT_25_3991_3_ETC___d24021 = + assign NOT_rob_deqPort_1_deq_data__3992_BIT_25_3993_3_ETC___d24023 = !rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[274] || rob$deqPort_1_deq_data[469:465] == 5'd0 || @@ -28981,7 +29006,7 @@ module mkCore(CLK, rob$deqPort_1_deq_data[469:465] == 5'd20 || rob$deqPort_1_deq_data[469:465] == 5'd24 || rob$deqPort_1_deq_data[469:465] == 5'd25 || - rob$RDY_deqPort_1_deq && regRenamingTable$RDY_commit_1_commit ; + regRenamingTable$RDY_commit_1_commit && rob$RDY_deqPort_1_deq ; assign NOT_specTagManager_canClaim__1454_1547_OR_NOT__ETC___d22220 = !specTagManager$canClaim || !regRenamingTable$rename_0_canRename || @@ -29001,47 +29026,47 @@ module mkCore(CLK, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q39, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q40 } ; assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d7215 = - { CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q293, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q294, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q295, + { CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q295, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q296, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q297, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q298 } ; + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q298, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q299, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q300 } ; assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d7225 = { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d7184, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q305, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q307, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d7215, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q306, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q307 } ; + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q308, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q309 } ; assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d7232 = - { CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q314, - !CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q315, + { CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q316, + !CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q317, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d7225, - x__h513123 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d24864 = - { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q317, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q318, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q319 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d24797 = - { CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q278, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q279, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q280 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d24828 = - { CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q299, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q300, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q301, + x__h513121 } ; + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d24866 = + { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q319, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q320, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q321 } ; + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d24799 = + { CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q280, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q281, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q282 } ; + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d24830 = + { CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q301, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q302, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q303, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q304 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d24838 = - { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d24797, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q308, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d24828, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q309, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q310 } ; + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q304, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q305, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q306 } ; + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d24840 = + { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d24799, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q310, + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d24830, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q311, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q312 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12903 = - { {4{f1_exp19832_MINUS_127__q148[7]}}, - f1_exp19832_MINUS_127__q148 } ; + { {4{f1_exp19828_MINUS_127__q148[7]}}, + f1_exp19828_MINUS_127__q148 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12904 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12903 ^ 12'h800) <= @@ -29051,8 +29076,8 @@ module mkCore(CLK, 12'h800) < 12'd1026 ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13618 = - { {4{f3_exp98130_MINUS_127__q165[7]}}, - f3_exp98130_MINUS_127__q165 } ; + { {4{f3_exp98126_MINUS_127__q165[7]}}, + f3_exp98126_MINUS_127__q165 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13619 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13618 ^ 12'h800) <= @@ -29062,8 +29087,8 @@ module mkCore(CLK, 12'h800) < 12'd1026 ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14388 = - { {4{f2_exp58826_MINUS_127__q188[7]}}, - f2_exp58826_MINUS_127__q188 } ; + { {4{f2_exp58822_MINUS_127__q188[7]}}, + f2_exp58822_MINUS_127__q188 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14389 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14388 ^ 12'h800) <= @@ -29073,9 +29098,9 @@ module mkCore(CLK, 12'h800) < 12'd1026 ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d15333 = - b__h840826 * b__h840902 ; + b__h840822 * b__h840898 ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d15346 = - b__h840826 * b__h841015 ; + b__h840822 * b__h841011 ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q149 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12903 + 12'd1023 ; @@ -29095,21 +29120,21 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q189[10:0] - 11'd1023 ; assign SEXT_SEL_ARR_SEL_ARR_coreFix_memExe_dMem_cache_ETC___d4901 = - { {64{x__h267669[63]}}, x__h267669 } ; + { {64{x__h267667[63]}}, x__h267667 } ; assign SEXT_SEL_ARR_SEL_ARR_coreFix_memExe_dMem_cache_ETC___d4909 = - { {96{x__h267824[31]}}, x__h267824 } ; - assign SEXT__0_CONCAT_IF_INV_commitStage_commitTrap_2_ETC___d23053 = - x__h1008320 | in__h1008389[63:0] ; + { {96{x__h267822[31]}}, x__h267822 } ; + assign SEXT__0_CONCAT_IF_INV_commitStage_commitTrap_2_ETC___d23054 = + x__h1008354 | in__h1008423[63:0] ; assign SEXT__0_CONCAT_IF_csrf_mepcc_reg_data_lat_0_wh_ETC___d16452 = - x__h861641 | in__h861866[63:0] ; + x__h861639 | in__h861864[63:0] ; assign SEXT__0_CONCAT_IF_csrf_sepcc_reg_data_lat_0_wh_ETC___d16300 = - x__h860648 | in__h860874[63:0] ; + x__h860646 | in__h860872[63:0] ; assign SEXT__0_CONCAT_csrf_mtcc_reg_read__6389_BITS_8_ETC___d16413 = - x__h903949 | in__h861562[63:0] ; + x__h903946 | in__h861560[63:0] ; assign SEXT__0_CONCAT_csrf_rg_dpc_read__6534_BITS_85__ETC___d16558 = - x__h904294 | in__h862392[63:0] ; + x__h904291 | in__h862390[63:0] ; assign SEXT__0_CONCAT_csrf_stcc_reg_read__6237_BITS_8_ETC___d16261 = - x__h903665 | in__h860569[63:0] ; + x__h903662 | in__h860567[63:0] ; assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10162 = { coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q84[10], coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q84 } ; @@ -29128,8 +29153,8 @@ module mkCore(CLK, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q85[7:0] - 8'd127 ; assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8765 = - { coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q41[10], - coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q41 } ; + { coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q49[10], + coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q49 } ; assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8766 = (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8765 ^ 12'h800) <= @@ -29138,11 +29163,11 @@ module mkCore(CLK, (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8765 ^ 12'h800) < 12'd1922 ; - assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q42 = + assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q50 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8765 + 12'd127 ; assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q55 = - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q42[7:0] - + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q50[7:0] - 8'd127 ; assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11559 = { coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q119[10], @@ -29163,15 +29188,15 @@ module mkCore(CLK, 8'd127 ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d10785 = { 3'd0, - _theResult___fst_exp__h634739 == 8'd0 && - (sfdin__h634733[56:34] == 23'd0 || guard__h626640 != 2'b0), + _theResult___fst_exp__h634736 == 8'd0 && + (sfdin__h634730[56:34] == 23'd0 || guard__h626637 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h635336 == 8'd255 && - _theResult___fst_sfd__h635337 == 23'd0, + _theResult___fst_exp__h635333 == 8'd255 && + _theResult___fst_sfd__h635334 == 23'd0, 1'd0, - _theResult___fst_exp__h634739 != 8'd255 && - guard__h626640 != 2'b0 } ; + _theResult___fst_exp__h634736 != 8'd255 && + guard__h626637 != 2'b0 } ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d11257 = ({ 3'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d11255 } ^ @@ -29179,15 +29204,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d12182 = { 3'd0, - _theResult___fst_exp__h680486 == 8'd0 && - (sfdin__h680480[56:34] == 23'd0 || guard__h672387 != 2'b0), + _theResult___fst_exp__h680483 == 8'd0 && + (sfdin__h680477[56:34] == 23'd0 || guard__h672384 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h681083 == 8'd255 && - _theResult___fst_sfd__h681084 == 23'd0, + _theResult___fst_exp__h681080 == 8'd255 && + _theResult___fst_sfd__h681081 == 23'd0, 1'd0, - _theResult___fst_exp__h680486 != 8'd255 && - guard__h672387 != 2'b0 } ; + _theResult___fst_exp__h680483 != 8'd255 && + guard__h672384 != 2'b0 } ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d8463 = ({ 3'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d8461 } ^ @@ -29195,15 +29220,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d9388 = { 3'd0, - _theResult___fst_exp__h588990 == 8'd0 && - (sfdin__h588984[56:34] == 23'd0 || guard__h580889 != 2'b0), + _theResult___fst_exp__h588987 == 8'd0 && + (sfdin__h588981[56:34] == 23'd0 || guard__h580886 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h589587 == 8'd255 && - _theResult___fst_sfd__h589588 == 23'd0, + _theResult___fst_exp__h589584 == 8'd255 && + _theResult___fst_sfd__h589585 == 23'd0, 1'd0, - _theResult___fst_exp__h588990 != 8'd255 && - guard__h580889 != 2'b0 } ; + _theResult___fst_exp__h588987 != 8'd255 && + guard__h580886 != 2'b0 } ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d9860 = ({ 3'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d9858 } ^ @@ -29226,37 +29251,37 @@ module mkCore(CLK, 12'd2048 ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d15015 = { 3'd0, - _theResult___fst_exp__h748797 == 11'd0 && - (sfdin__h748791[56:5] == 52'd0 || guard__h740571 != 2'b0), + _theResult___fst_exp__h748793 == 11'd0 && + (sfdin__h748787[56:5] == 52'd0 || guard__h740567 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h749629 == 11'd2047 && - _theResult___fst_sfd__h749630 == 52'd0, + _theResult___fst_exp__h749625 == 11'd2047 && + _theResult___fst_sfd__h749626 == 52'd0, 1'd0, - _theResult___fst_exp__h748797 != 11'd2047 && - guard__h740571 != 2'b0 } ; + _theResult___fst_exp__h748793 != 11'd2047 && + guard__h740567 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d15056 = { 3'd0, - _theResult___fst_exp__h787650 == 11'd0 && - (sfdin__h787644[56:5] == 52'd0 || guard__h779424 != 2'b0), + _theResult___fst_exp__h787646 == 11'd0 && + (sfdin__h787640[56:5] == 52'd0 || guard__h779420 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h788482 == 11'd2047 && - _theResult___fst_sfd__h788483 == 52'd0, + _theResult___fst_exp__h788478 == 11'd2047 && + _theResult___fst_sfd__h788479 == 52'd0, 1'd0, - _theResult___fst_exp__h787650 != 11'd2047 && - guard__h779424 != 2'b0 } ; + _theResult___fst_exp__h787646 != 11'd2047 && + guard__h779420 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d15100 = { 3'd0, - _theResult___fst_exp__h826954 == 11'd0 && - (sfdin__h826948[56:5] == 52'd0 || guard__h818728 != 2'b0), + _theResult___fst_exp__h826950 == 11'd0 && + (sfdin__h826944[56:5] == 52'd0 || guard__h818724 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h827786 == 11'd2047 && - _theResult___fst_sfd__h827787 == 52'd0, + _theResult___fst_exp__h827782 == 11'd2047 && + _theResult___fst_sfd__h827783 == 52'd0, 1'd0, - _theResult___fst_exp__h826954 != 11'd2047 && - guard__h818728 != 2'b0 } ; + _theResult___fst_exp__h826950 != 11'd2047 && + guard__h818724 != 2'b0 } ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d10411 = ({ 3'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d10409 } ^ @@ -29264,15 +29289,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d10814 = { 3'd0, - _theResult___fst_exp__h652505 == 8'd0 && - (sfdin__h652499[56:34] == 23'd0 || guard__h644277 != 2'b0), + _theResult___fst_exp__h652502 == 8'd0 && + (sfdin__h652496[56:34] == 23'd0 || guard__h644274 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h653102 == 8'd255 && - _theResult___fst_sfd__h653103 == 23'd0, + _theResult___fst_exp__h653099 == 8'd255 && + _theResult___fst_sfd__h653100 == 23'd0, 1'd0, - _theResult___fst_exp__h652505 != 8'd255 && - guard__h644277 != 2'b0 } ; + _theResult___fst_exp__h652502 != 8'd255 && + guard__h644274 != 2'b0 } ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d11808 = ({ 3'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d11806 } ^ @@ -29280,15 +29305,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d12211 = { 3'd0, - _theResult___fst_exp__h698252 == 8'd0 && - (sfdin__h698246[56:34] == 23'd0 || guard__h690024 != 2'b0), + _theResult___fst_exp__h698249 == 8'd0 && + (sfdin__h698243[56:34] == 23'd0 || guard__h690021 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h698849 == 8'd255 && - _theResult___fst_sfd__h698850 == 23'd0, + _theResult___fst_exp__h698846 == 8'd255 && + _theResult___fst_sfd__h698847 == 23'd0, 1'd0, - _theResult___fst_exp__h698252 != 8'd255 && - guard__h690024 != 2'b0 } ; + _theResult___fst_exp__h698249 != 8'd255 && + guard__h690021 != 2'b0 } ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d9014 = ({ 3'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d9012 } ^ @@ -29296,15 +29321,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d9417 = { 3'd0, - _theResult___fst_exp__h606756 == 8'd0 && - (sfdin__h606750[56:34] == 23'd0 || guard__h598528 != 2'b0), + _theResult___fst_exp__h606753 == 8'd0 && + (sfdin__h606747[56:34] == 23'd0 || guard__h598525 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h607353 == 8'd255 && - _theResult___fst_sfd__h607354 == 23'd0, + _theResult___fst_exp__h607350 == 8'd255 && + _theResult___fst_sfd__h607351 == 23'd0, 1'd0, - _theResult___fst_exp__h606756 != 8'd255 && - guard__h598528 != 2'b0 } ; + _theResult___fst_exp__h606753 != 8'd255 && + guard__h598525 != 2'b0 } ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d12842 = ({ 6'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d12840 } ^ @@ -29340,37 +29365,37 @@ module mkCore(CLK, 12'h800) ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14998 = { 3'd0, - _theResult___fst_exp__h739220 == 11'd0 && - guard__h731259 != 2'b0, + _theResult___fst_exp__h739216 == 11'd0 && + guard__h731255 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h739978 == 11'd2047 && - _theResult___fst_sfd__h739979 == 52'd0, + _theResult___fst_exp__h739974 == 11'd2047 && + _theResult___fst_sfd__h739975 == 52'd0, 1'd0, - _theResult___fst_exp__h739220 != 11'd2047 && - guard__h731259 != 2'b0 } ; + _theResult___fst_exp__h739216 != 11'd2047 && + guard__h731255 != 2'b0 } ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d15039 = { 3'd0, - _theResult___fst_exp__h778073 == 11'd0 && - guard__h770112 != 2'b0, + _theResult___fst_exp__h778069 == 11'd0 && + guard__h770108 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h778831 == 11'd2047 && - _theResult___fst_sfd__h778832 == 52'd0, + _theResult___fst_exp__h778827 == 11'd2047 && + _theResult___fst_sfd__h778828 == 52'd0, 1'd0, - _theResult___fst_exp__h778073 != 11'd2047 && - guard__h770112 != 2'b0 } ; + _theResult___fst_exp__h778069 != 11'd2047 && + guard__h770108 != 2'b0 } ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d15083 = { 3'd0, - _theResult___fst_exp__h817377 == 11'd0 && - guard__h809416 != 2'b0, + _theResult___fst_exp__h817373 == 11'd0 && + guard__h809412 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h818135 == 11'd2047 && - _theResult___fst_sfd__h818136 == 52'd0, + _theResult___fst_exp__h818131 == 11'd2047 && + _theResult___fst_sfd__h818132 == 52'd0, 1'd0, - _theResult___fst_exp__h817377 != 11'd2047 && - guard__h809416 != 2'b0 } ; + _theResult___fst_exp__h817373 != 11'd2047 && + guard__h809412 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d10091 = ({ 3'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d10089 } ^ @@ -29384,15 +29409,15 @@ module mkCore(CLK, 9'h100) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d10797 = { 3'd0, - _theResult___fst_exp__h643395 == 8'd0 && - guard__h635347 != 2'b0, + _theResult___fst_exp__h643392 == 8'd0 && + guard__h635344 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h643918 == 8'd255 && - _theResult___fst_sfd__h643919 == 23'd0, + _theResult___fst_exp__h643915 == 8'd255 && + _theResult___fst_sfd__h643916 == 23'd0, 1'd0, - _theResult___fst_exp__h643395 != 8'd255 && - guard__h635347 != 2'b0 } ; + _theResult___fst_exp__h643392 != 8'd255 && + guard__h635344 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d11488 = ({ 3'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d11486 } ^ @@ -29406,15 +29431,15 @@ module mkCore(CLK, 9'h100) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d12194 = { 3'd0, - _theResult___fst_exp__h689142 == 8'd0 && - guard__h681094 != 2'b0, + _theResult___fst_exp__h689139 == 8'd0 && + guard__h681091 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h689665 == 8'd255 && - _theResult___fst_sfd__h689666 == 23'd0, + _theResult___fst_exp__h689662 == 8'd255 && + _theResult___fst_sfd__h689663 == 23'd0, 1'd0, - _theResult___fst_exp__h689142 != 8'd255 && - guard__h681094 != 2'b0 } ; + _theResult___fst_exp__h689139 != 8'd255 && + guard__h681091 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d8694 = ({ 3'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d8692 } ^ @@ -29428,17 +29453,17 @@ module mkCore(CLK, 9'h100) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d9400 = { 3'd0, - _theResult___fst_exp__h597646 == 8'd0 && - guard__h589598 != 2'b0, + _theResult___fst_exp__h597643 == 8'd0 && + guard__h589595 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h598169 == 8'd255 && - _theResult___fst_sfd__h598170 == 23'd0, + _theResult___fst_exp__h598166 == 8'd255 && + _theResult___fst_sfd__h598167 == 23'd0, 1'd0, - _theResult___fst_exp__h597646 != 8'd255 && - guard__h589598 != 2'b0 } ; + _theResult___fst_exp__h597643 != 8'd255 && + guard__h589595 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d15339 = - b__h841003 * b__h841015 ; + b__h840999 * b__h841011 ; assign _0_CONCAT_IF_coreFix_memExe_dTlb_procResp__276__ETC___d4687 = { 2'd0, (coreFix_memExe_dTlb$procResp[277] && @@ -29458,18 +29483,18 @@ module mkCore(CLK, 1'd0, csrf_timer_int_en_vec_1 & csrf_timer_int_pend_vec_1, 1'd0 } ; - assign _0_CONCAT_csrf_mtcc_reg_read__6389_BITS_149_TO__ETC___d23208 = - x__h1011078[13:11] < repBound__h861484 ; - assign _0_CONCAT_csrf_mtcc_reg_read__6389_BITS_149_TO__ETC___d23233 = - x__h1011382[13:11] < repBound__h861484 ; - assign _0_CONCAT_csrf_stcc_reg_read__6237_BITS_149_TO__ETC___d23139 = - x__h1010421[13:11] < repBound__h860491 ; - assign _0_CONCAT_csrf_stcc_reg_read__6237_BITS_149_TO__ETC___d23164 = - x__h1010725[13:11] < repBound__h860491 ; + assign _0_CONCAT_csrf_mtcc_reg_read__6389_BITS_149_TO__ETC___d23210 = + x__h1011112[13:11] < repBound__h861482 ; + assign _0_CONCAT_csrf_mtcc_reg_read__6389_BITS_149_TO__ETC___d23235 = + x__h1011416[13:11] < repBound__h861482 ; + assign _0_CONCAT_csrf_stcc_reg_read__6237_BITS_149_TO__ETC___d23141 = + x__h1010455[13:11] < repBound__h860489 ; + assign _0_CONCAT_csrf_stcc_reg_read__6237_BITS_149_TO__ETC___d23166 = + x__h1010759[13:11] < repBound__h860489 ; assign _0_OR_NOT_fetchStage_pipelines_0_first__0544_BI_ETC___d22140 = (fetchStage$pipelines_0_first[268:266] != 3'd1 || specTagManager$RDY_nextSpecTag) && - CASE_k54121_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q268 ; + CASE_k54118_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q268 ; assign _0_OR_NOT_fetchStage_pipelines_1_first__0553_BI_ETC___d22038 = (fetchStage$pipelines_1_first[268:266] != 3'd1 || !fetchStage$pipelines_0_canDeq || @@ -29483,37 +29508,37 @@ module mkCore(CLK, specTagManager$RDY_nextSpecTag) && CASE_fetchStage_pipelines_0_canDeq__0542_AND_N_ETC__q270 ; assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d12910 = - sfd__h720194 >> + sfd__h720190 >> _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d12906 ; assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d13625 = - sfd__h798492 >> + sfd__h798488 >> _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d13621 ; assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d14395 = - sfd__h759188 >> + sfd__h759184 >> _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d14391 ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d10169 = - sfd__h619028 >> + sfd__h619025 >> (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d10165[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d10165) ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d11566 = - sfd__h664775 >> + sfd__h664772 >> (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d11562[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d11562) ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d8772 = - sfd__h573274 >> + sfd__h573271 >> (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d8768[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d8768) ; assign _0b0_CONCAT_csrf_medeleg_28_26_reg_read__6352_6_ETC___d23018 = - medeleg_csr__read__h856638[i__h1006069] ; - assign _0b0_CONCAT_csrf_mideleg_11_reg_read__6363_6364_ETC___d23020 = - mideleg_csr__read__h856736[i__h1006243] ; - assign _18446744073709551615_SL_csrf_mtcc_reg_read__63_ETC___d23200 = - mask__h1010890 ^ y__h1011007 ; - assign _18446744073709551615_SL_csrf_stcc_reg_read__62_ETC___d23131 = - mask__h1010233 ^ y__h1010350 ; + medeleg_csr__read__h856636[i__h1006066] ; + assign _0b0_CONCAT_csrf_mideleg_11_reg_read__6363_6364_ETC___d23021 = + mideleg_csr__read__h856734[i__h1006266] ; + assign _18446744073709551615_SL_csrf_mtcc_reg_read__63_ETC___d23202 = + mask__h1010924 ^ y__h1011041 ; + assign _18446744073709551615_SL_csrf_stcc_reg_read__62_ETC___d23133 = + mask__h1010267 ^ y__h1010384 ; assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10800 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9623 && (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9624 ? @@ -29919,51 +29944,51 @@ module mkCore(CLK, assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12766 = 12'd3970 - { 7'd0, - f1_sfd__h719833[22] ? + f1_sfd__h719829[22] ? 5'd0 : - (f1_sfd__h719833[21] ? + (f1_sfd__h719829[21] ? 5'd1 : - (f1_sfd__h719833[20] ? + (f1_sfd__h719829[20] ? 5'd2 : - (f1_sfd__h719833[19] ? + (f1_sfd__h719829[19] ? 5'd3 : - (f1_sfd__h719833[18] ? + (f1_sfd__h719829[18] ? 5'd4 : - (f1_sfd__h719833[17] ? + (f1_sfd__h719829[17] ? 5'd5 : - (f1_sfd__h719833[16] ? + (f1_sfd__h719829[16] ? 5'd6 : - (f1_sfd__h719833[15] ? + (f1_sfd__h719829[15] ? 5'd7 : - (f1_sfd__h719833[14] ? + (f1_sfd__h719829[14] ? 5'd8 : - (f1_sfd__h719833[13] ? + (f1_sfd__h719829[13] ? 5'd9 : - (f1_sfd__h719833[12] ? + (f1_sfd__h719829[12] ? 5'd10 : - (f1_sfd__h719833[11] ? + (f1_sfd__h719829[11] ? 5'd11 : - (f1_sfd__h719833[10] ? + (f1_sfd__h719829[10] ? 5'd12 : - (f1_sfd__h719833[9] ? + (f1_sfd__h719829[9] ? 5'd13 : - (f1_sfd__h719833[8] ? + (f1_sfd__h719829[8] ? 5'd14 : - (f1_sfd__h719833[7] ? + (f1_sfd__h719829[7] ? 5'd15 : - (f1_sfd__h719833[6] ? + (f1_sfd__h719829[6] ? 5'd16 : - (f1_sfd__h719833[5] ? + (f1_sfd__h719829[5] ? 5'd17 : - (f1_sfd__h719833[4] ? + (f1_sfd__h719829[4] ? 5'd18 : - (f1_sfd__h719833[3] ? + (f1_sfd__h719829[3] ? 5'd19 : - (f1_sfd__h719833[2] ? + (f1_sfd__h719829[2] ? 5'd20 : - (f1_sfd__h719833[1] ? + (f1_sfd__h719829[1] ? 5'd21 : - (f1_sfd__h719833[0] ? + (f1_sfd__h719829[0] ? 5'd22 : 5'd23)))))))))))))))))))))) } ; assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12767 = @@ -29977,51 +30002,51 @@ module mkCore(CLK, assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13496 = 12'd3970 - { 7'd0, - f3_sfd__h798131[22] ? + f3_sfd__h798127[22] ? 5'd0 : - (f3_sfd__h798131[21] ? + (f3_sfd__h798127[21] ? 5'd1 : - (f3_sfd__h798131[20] ? + (f3_sfd__h798127[20] ? 5'd2 : - (f3_sfd__h798131[19] ? + (f3_sfd__h798127[19] ? 5'd3 : - (f3_sfd__h798131[18] ? + (f3_sfd__h798127[18] ? 5'd4 : - (f3_sfd__h798131[17] ? + (f3_sfd__h798127[17] ? 5'd5 : - (f3_sfd__h798131[16] ? + (f3_sfd__h798127[16] ? 5'd6 : - (f3_sfd__h798131[15] ? + (f3_sfd__h798127[15] ? 5'd7 : - (f3_sfd__h798131[14] ? + (f3_sfd__h798127[14] ? 5'd8 : - (f3_sfd__h798131[13] ? + (f3_sfd__h798127[13] ? 5'd9 : - (f3_sfd__h798131[12] ? + (f3_sfd__h798127[12] ? 5'd10 : - (f3_sfd__h798131[11] ? + (f3_sfd__h798127[11] ? 5'd11 : - (f3_sfd__h798131[10] ? + (f3_sfd__h798127[10] ? 5'd12 : - (f3_sfd__h798131[9] ? + (f3_sfd__h798127[9] ? 5'd13 : - (f3_sfd__h798131[8] ? + (f3_sfd__h798127[8] ? 5'd14 : - (f3_sfd__h798131[7] ? + (f3_sfd__h798127[7] ? 5'd15 : - (f3_sfd__h798131[6] ? + (f3_sfd__h798127[6] ? 5'd16 : - (f3_sfd__h798131[5] ? + (f3_sfd__h798127[5] ? 5'd17 : - (f3_sfd__h798131[4] ? + (f3_sfd__h798127[4] ? 5'd18 : - (f3_sfd__h798131[3] ? + (f3_sfd__h798127[3] ? 5'd19 : - (f3_sfd__h798131[2] ? + (f3_sfd__h798127[2] ? 5'd20 : - (f3_sfd__h798131[1] ? + (f3_sfd__h798127[1] ? 5'd21 : - (f3_sfd__h798131[0] ? + (f3_sfd__h798127[0] ? 5'd22 : 5'd23)))))))))))))))))))))) } ; assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13497 = @@ -30035,51 +30060,51 @@ module mkCore(CLK, assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14266 = 12'd3970 - { 7'd0, - f2_sfd__h758827[22] ? + f2_sfd__h758823[22] ? 5'd0 : - (f2_sfd__h758827[21] ? + (f2_sfd__h758823[21] ? 5'd1 : - (f2_sfd__h758827[20] ? + (f2_sfd__h758823[20] ? 5'd2 : - (f2_sfd__h758827[19] ? + (f2_sfd__h758823[19] ? 5'd3 : - (f2_sfd__h758827[18] ? + (f2_sfd__h758823[18] ? 5'd4 : - (f2_sfd__h758827[17] ? + (f2_sfd__h758823[17] ? 5'd5 : - (f2_sfd__h758827[16] ? + (f2_sfd__h758823[16] ? 5'd6 : - (f2_sfd__h758827[15] ? + (f2_sfd__h758823[15] ? 5'd7 : - (f2_sfd__h758827[14] ? + (f2_sfd__h758823[14] ? 5'd8 : - (f2_sfd__h758827[13] ? + (f2_sfd__h758823[13] ? 5'd9 : - (f2_sfd__h758827[12] ? + (f2_sfd__h758823[12] ? 5'd10 : - (f2_sfd__h758827[11] ? + (f2_sfd__h758823[11] ? 5'd11 : - (f2_sfd__h758827[10] ? + (f2_sfd__h758823[10] ? 5'd12 : - (f2_sfd__h758827[9] ? + (f2_sfd__h758823[9] ? 5'd13 : - (f2_sfd__h758827[8] ? + (f2_sfd__h758823[8] ? 5'd14 : - (f2_sfd__h758827[7] ? + (f2_sfd__h758823[7] ? 5'd15 : - (f2_sfd__h758827[6] ? + (f2_sfd__h758823[6] ? 5'd16 : - (f2_sfd__h758827[5] ? + (f2_sfd__h758823[5] ? 5'd17 : - (f2_sfd__h758827[4] ? + (f2_sfd__h758823[4] ? 5'd18 : - (f2_sfd__h758827[3] ? + (f2_sfd__h758823[3] ? 5'd19 : - (f2_sfd__h758827[2] ? + (f2_sfd__h758823[2] ? 5'd20 : - (f2_sfd__h758827[1] ? + (f2_sfd__h758823[1] ? 5'd21 : - (f2_sfd__h758827[0] ? + (f2_sfd__h758823[0] ? 5'd22 : 5'd23)))))))))))))))))))))) } ; assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14267 = @@ -30110,7 +30135,7 @@ module mkCore(CLK, NOT_fetchStage_pipelines_0_canDeq__0542_0543_O_ETC___d22535 && fetchStage$pipelines_1_first[273:269] != 5'd19 ; assign _dfoo16 = - k__h954121 == 1'd1 && fetchStage$pipelines_0_canDeq && + k__h954118 == 1'd1 && fetchStage$pipelines_0_canDeq && NOT_fetchStage_pipelines_0_first__0544_BITS_26_ETC___d22314 || (fetchStage_pipelines_0_canDeq__0542_AND_NOT_fe_ETC___d22435 || NOT_fetchStage_pipelines_0_canDeq__0542_0543_O_ETC___d22448) == @@ -30118,7 +30143,7 @@ module mkCore(CLK, NOT_fetchStage_pipelines_0_canDeq__0542_0543_O_ETC___d22453 && NOT_fetchStage_pipelines_1_first__0553_BITS_26_ETC___d22465 ; assign _dfoo18 = - k__h954121 == 1'd0 && fetchStage$pipelines_0_canDeq && + k__h954118 == 1'd0 && fetchStage$pipelines_0_canDeq && NOT_fetchStage_pipelines_0_first__0544_BITS_26_ETC___d22314 || (fetchStage_pipelines_0_canDeq__0542_AND_NOT_fe_ETC___d22435 || NOT_fetchStage_pipelines_0_canDeq__0542_0543_O_ETC___d22448) == @@ -30136,53 +30161,53 @@ module mkCore(CLK, NOT_fetchStage_pipelines_0_canDeq__0542_0543_O_ETC___d22535 && fetchStage$pipelines_1_first[265:263] != 3'd0 && fetchStage$pipelines_1_first[265:263] != 3'd2 ; - assign _dfoo22 = + assign _dfoo20 = NOT_commitStage_commitTrap_2639_BITS_44_TO_43__ETC___d22910 || commitStage_commitTrap_2639_BITS_44_TO_43_2837_ETC___d22989 ; assign _dfoo24 = rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd42 || rob$deqPort_0_deq_data[469:465] == 5'd24 || rob$deqPort_0_deq_data[469:465] == 5'd25 ; assign _dfoo26 = rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd27 || rob$deqPort_0_deq_data[469:465] == 5'd18 && - IF_rob_deqPort_0_deq_data__2632_BIT_294_3835_T_ETC___d23857 == + IF_rob_deqPort_0_deq_data__2632_BIT_294_3837_T_ETC___d23859 == 4'd9 ; assign _dfoo28 = rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd24 || rob$deqPort_0_deq_data[469:465] == 5'd18 && - IF_rob_deqPort_0_deq_data__2632_BIT_294_3835_T_ETC___d23857 == + IF_rob_deqPort_0_deq_data__2632_BIT_294_3837_T_ETC___d23859 == 4'd6 ; assign _dfoo30 = rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd19 || rob$deqPort_0_deq_data[469:465] == 5'd25 ; assign _dfoo36 = rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd13 || rob$deqPort_0_deq_data[469:465] == 5'd18 && - IF_rob_deqPort_0_deq_data__2632_BIT_294_3835_T_ETC___d23857 == + IF_rob_deqPort_0_deq_data__2632_BIT_294_3837_T_ETC___d23859 == 4'd5 ; assign _dfoo38 = rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd10 || rob$deqPort_0_deq_data[469:465] == 5'd18 && - IF_rob_deqPort_0_deq_data__2632_BIT_294_3835_T_ETC___d23857 == + IF_rob_deqPort_0_deq_data__2632_BIT_294_3837_T_ETC___d23859 == 4'd2 ; assign _dfoo40 = rob$deqPort_0_deq_data[469:465] == 5'd17 && - (IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + (IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd8 || - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd19) || rob$deqPort_0_deq_data[469:465] == 5'd24 ; assign _dfoo7 = @@ -30253,1415 +30278,1415 @@ module mkCore(CLK, assign _dor1sbCons$EN_setReady_1_put = WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F || WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; - assign _theResult_____2__h519793 = + assign _theResult_____2__h519790 = IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d7331 ? - next_deqP___1__h520038 : + next_deqP___1__h520035 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP ; - assign _theResult_____2__h530570 = + assign _theResult_____2__h530567 = IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d7425 ? - next_deqP___1__h530815 : + next_deqP___1__h530812 : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP ; - assign _theResult_____2__h537663 = + assign _theResult_____2__h537660 = IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d7584 ? - next_deqP___1__h538093 : + next_deqP___1__h538090 : coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP ; - assign _theResult_____2__h548298 = + assign _theResult_____2__h548295 = IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d7668 ? - next_deqP___1__h548728 : + next_deqP___1__h548725 : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP ; - assign _theResult_____2__h562131 = + assign _theResult_____2__h562128 = IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d7873 ? - next_deqP___1__h562376 : + next_deqP___1__h562373 : coreFix_memExe_memRespLdQ_deqP ; - assign _theResult_____2__h565910 = + assign _theResult_____2__h565907 = IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d7955 ? - next_deqP___1__h566155 : + next_deqP___1__h566152 : coreFix_memExe_forwardQ_deqP ; - assign _theResult____h580879 = - (value__h581501 == 54'd0) ? sfd__h573274 : 57'd1 ; - assign _theResult____h598518 = + assign _theResult____h580876 = + (value__h581498 == 54'd0) ? sfd__h573271 : 57'd1 ; + assign _theResult____h598515 = ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d8768 ^ 12'h800) < 12'd2105) ? - result__h599131 : - _theResult____h580879 ; - assign _theResult____h626630 = - (value__h627250 == 54'd0) ? sfd__h619028 : 57'd1 ; - assign _theResult____h644267 = + result__h599128 : + _theResult____h580876 ; + assign _theResult____h626627 = + (value__h627247 == 54'd0) ? sfd__h619025 : 57'd1 ; + assign _theResult____h644264 = ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d10165 ^ 12'h800) < 12'd2105) ? - result__h644880 : - _theResult____h626630 ; - assign _theResult____h672377 = - (value__h672997 == 54'd0) ? sfd__h664775 : 57'd1 ; - assign _theResult____h690014 = + result__h644877 : + _theResult____h626627 ; + assign _theResult____h672374 = + (value__h672994 == 54'd0) ? sfd__h664772 : 57'd1 ; + assign _theResult____h690011 = ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d11562 ^ 12'h800) < 12'd2105) ? - result__h690627 : - _theResult____h672377 ; - assign _theResult____h740561 = + result__h690624 : + _theResult____h672374 ; + assign _theResult____h740557 = ((_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d12906 ^ 12'h800) < 12'd2105) ? - result__h741174 : - ((value__h724777 == 25'd0) ? sfd__h720194 : 57'd1) ; - assign _theResult____h779414 = + result__h741170 : + ((value__h724773 == 25'd0) ? sfd__h720190 : 57'd1) ; + assign _theResult____h779410 = ((_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d14391 ^ 12'h800) < 12'd2105) ? - result__h780027 : - ((value__h763630 == 25'd0) ? sfd__h759188 : 57'd1) ; - assign _theResult____h818718 = + result__h780023 : + ((value__h763626 == 25'd0) ? sfd__h759184 : 57'd1) ; + assign _theResult____h818714 = ((_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d13621 ^ 12'h800) < 12'd2105) ? - result__h819331 : - ((value__h802934 == 25'd0) ? sfd__h798492 : 57'd1) ; - assign _theResult____h928986 = + result__h819327 : + ((value__h802930 == 25'd0) ? sfd__h798488 : 57'd1) ; + assign _theResult____h928983 = (csrf_prv_reg != 2'd3 || csrf_ie_vec_3) ? - enabled_ints___1__h929511 : + enabled_ints___1__h929508 : 16'd0 ; - assign _theResult___exp__h589506 = - sfd__h589082[24] ? - ((_theResult___fst_exp__h588990 == 8'd254) ? + assign _theResult___exp__h589503 = + sfd__h589079[24] ? + ((_theResult___fst_exp__h588987 == 8'd254) ? 8'd255 : - din_inc___2_exp__h616023) : - ((_theResult___fst_exp__h588990 == 8'd0 && - sfd__h589082[24:23] == 2'b01) ? + din_inc___2_exp__h616020) : + ((_theResult___fst_exp__h588987 == 8'd0 && + sfd__h589079[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h588990) ; - assign _theResult___exp__h598088 = - sfd__h597664[24] ? - ((_theResult___fst_exp__h597646 == 8'd254) ? + _theResult___fst_exp__h588987) ; + assign _theResult___exp__h598085 = + sfd__h597661[24] ? + ((_theResult___fst_exp__h597643 == 8'd254) ? 8'd255 : - din_inc___2_exp__h616047) : - ((_theResult___fst_exp__h597646 == 8'd0 && - sfd__h597664[24:23] == 2'b01) ? + din_inc___2_exp__h616044) : + ((_theResult___fst_exp__h597643 == 8'd0 && + sfd__h597661[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h597646) ; - assign _theResult___exp__h607272 = - sfd__h606848[24] ? - ((_theResult___fst_exp__h606756 == 8'd254) ? + _theResult___fst_exp__h597643) ; + assign _theResult___exp__h607269 = + sfd__h606845[24] ? + ((_theResult___fst_exp__h606753 == 8'd254) ? 8'd255 : - din_inc___2_exp__h616077) : - ((_theResult___fst_exp__h606756 == 8'd0 && - sfd__h606848[24:23] == 2'b01) ? + din_inc___2_exp__h616074) : + ((_theResult___fst_exp__h606753 == 8'd0 && + sfd__h606845[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h606756) ; - assign _theResult___exp__h615908 = - sfd__h615460[24] ? - ((_theResult___fst_exp__h615441 == 8'd254) ? + _theResult___fst_exp__h606753) ; + assign _theResult___exp__h615905 = + sfd__h615457[24] ? + ((_theResult___fst_exp__h615438 == 8'd254) ? 8'd255 : - din_inc___2_exp__h616101) : - ((_theResult___fst_exp__h615441 == 8'd0 && - sfd__h615460[24:23] == 2'b01) ? + din_inc___2_exp__h616098) : + ((_theResult___fst_exp__h615438 == 8'd0 && + sfd__h615457[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h615441) ; - assign _theResult___exp__h616010 = + _theResult___fst_exp__h615438) ; + assign _theResult___exp__h616007 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h616001 ; - assign _theResult___exp__h635255 = - sfd__h634831[24] ? - ((_theResult___fst_exp__h634739 == 8'd254) ? + _theResult___fst_exp__h615998 ; + assign _theResult___exp__h635252 = + sfd__h634828[24] ? + ((_theResult___fst_exp__h634736 == 8'd254) ? 8'd255 : - din_inc___2_exp__h661772) : - ((_theResult___fst_exp__h634739 == 8'd0 && - sfd__h634831[24:23] == 2'b01) ? + din_inc___2_exp__h661769) : + ((_theResult___fst_exp__h634736 == 8'd0 && + sfd__h634828[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h634739) ; - assign _theResult___exp__h643837 = - sfd__h643413[24] ? - ((_theResult___fst_exp__h643395 == 8'd254) ? + _theResult___fst_exp__h634736) ; + assign _theResult___exp__h643834 = + sfd__h643410[24] ? + ((_theResult___fst_exp__h643392 == 8'd254) ? 8'd255 : - din_inc___2_exp__h661796) : - ((_theResult___fst_exp__h643395 == 8'd0 && - sfd__h643413[24:23] == 2'b01) ? + din_inc___2_exp__h661793) : + ((_theResult___fst_exp__h643392 == 8'd0 && + sfd__h643410[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h643395) ; - assign _theResult___exp__h653021 = - sfd__h652597[24] ? - ((_theResult___fst_exp__h652505 == 8'd254) ? + _theResult___fst_exp__h643392) ; + assign _theResult___exp__h653018 = + sfd__h652594[24] ? + ((_theResult___fst_exp__h652502 == 8'd254) ? 8'd255 : - din_inc___2_exp__h661826) : - ((_theResult___fst_exp__h652505 == 8'd0 && - sfd__h652597[24:23] == 2'b01) ? + din_inc___2_exp__h661823) : + ((_theResult___fst_exp__h652502 == 8'd0 && + sfd__h652594[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h652505) ; - assign _theResult___exp__h661657 = - sfd__h661209[24] ? - ((_theResult___fst_exp__h661190 == 8'd254) ? + _theResult___fst_exp__h652502) ; + assign _theResult___exp__h661654 = + sfd__h661206[24] ? + ((_theResult___fst_exp__h661187 == 8'd254) ? 8'd255 : - din_inc___2_exp__h661850) : - ((_theResult___fst_exp__h661190 == 8'd0 && - sfd__h661209[24:23] == 2'b01) ? + din_inc___2_exp__h661847) : + ((_theResult___fst_exp__h661187 == 8'd0 && + sfd__h661206[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h661190) ; - assign _theResult___exp__h661759 = + _theResult___fst_exp__h661187) ; + assign _theResult___exp__h661756 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h661750 ; - assign _theResult___exp__h681002 = - sfd__h680578[24] ? - ((_theResult___fst_exp__h680486 == 8'd254) ? + _theResult___fst_exp__h661747 ; + assign _theResult___exp__h680999 = + sfd__h680575[24] ? + ((_theResult___fst_exp__h680483 == 8'd254) ? 8'd255 : - din_inc___2_exp__h707519) : - ((_theResult___fst_exp__h680486 == 8'd0 && - sfd__h680578[24:23] == 2'b01) ? + din_inc___2_exp__h707516) : + ((_theResult___fst_exp__h680483 == 8'd0 && + sfd__h680575[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h680486) ; - assign _theResult___exp__h689584 = - sfd__h689160[24] ? - ((_theResult___fst_exp__h689142 == 8'd254) ? + _theResult___fst_exp__h680483) ; + assign _theResult___exp__h689581 = + sfd__h689157[24] ? + ((_theResult___fst_exp__h689139 == 8'd254) ? 8'd255 : - din_inc___2_exp__h707543) : - ((_theResult___fst_exp__h689142 == 8'd0 && - sfd__h689160[24:23] == 2'b01) ? + din_inc___2_exp__h707540) : + ((_theResult___fst_exp__h689139 == 8'd0 && + sfd__h689157[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h689142) ; - assign _theResult___exp__h698768 = - sfd__h698344[24] ? - ((_theResult___fst_exp__h698252 == 8'd254) ? + _theResult___fst_exp__h689139) ; + assign _theResult___exp__h698765 = + sfd__h698341[24] ? + ((_theResult___fst_exp__h698249 == 8'd254) ? 8'd255 : - din_inc___2_exp__h707573) : - ((_theResult___fst_exp__h698252 == 8'd0 && - sfd__h698344[24:23] == 2'b01) ? + din_inc___2_exp__h707570) : + ((_theResult___fst_exp__h698249 == 8'd0 && + sfd__h698341[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h698252) ; - assign _theResult___exp__h707404 = - sfd__h706956[24] ? - ((_theResult___fst_exp__h706937 == 8'd254) ? + _theResult___fst_exp__h698249) ; + assign _theResult___exp__h707401 = + sfd__h706953[24] ? + ((_theResult___fst_exp__h706934 == 8'd254) ? 8'd255 : - din_inc___2_exp__h707597) : - ((_theResult___fst_exp__h706937 == 8'd0 && - sfd__h706956[24:23] == 2'b01) ? + din_inc___2_exp__h707594) : + ((_theResult___fst_exp__h706934 == 8'd0 && + sfd__h706953[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h706937) ; - assign _theResult___exp__h707506 = + _theResult___fst_exp__h706934) ; + assign _theResult___exp__h707503 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h707497 ; - assign _theResult___exp__h739875 = - sfd__h739238[53] ? - ((_theResult___fst_exp__h739220 == 11'd2046) ? + _theResult___fst_exp__h707494 ; + assign _theResult___exp__h739871 = + sfd__h739234[53] ? + ((_theResult___fst_exp__h739216 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h758470) : - ((_theResult___fst_exp__h739220 == 11'd0 && - sfd__h739238[53:52] == 2'b01) ? + din_inc___2_exp__h758466) : + ((_theResult___fst_exp__h739216 == 11'd0 && + sfd__h739234[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h739220) ; - assign _theResult___exp__h749526 = - sfd__h748889[53] ? - ((_theResult___fst_exp__h748797 == 11'd2046) ? + _theResult___fst_exp__h739216) ; + assign _theResult___exp__h749522 = + sfd__h748885[53] ? + ((_theResult___fst_exp__h748793 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h758505) : - ((_theResult___fst_exp__h748797 == 11'd0 && - sfd__h748889[53:52] == 2'b01) ? + din_inc___2_exp__h758501) : + ((_theResult___fst_exp__h748793 == 11'd0 && + sfd__h748885[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h748797) ; - assign _theResult___exp__h758310 = - sfd__h757649[53] ? - ((_theResult___fst_exp__h757630 == 11'd2046) ? + _theResult___fst_exp__h748793) ; + assign _theResult___exp__h758306 = + sfd__h757645[53] ? + ((_theResult___fst_exp__h757626 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h758531) : - ((_theResult___fst_exp__h757630 == 11'd0 && - sfd__h757649[53:52] == 2'b01) ? + din_inc___2_exp__h758527) : + ((_theResult___fst_exp__h757626 == 11'd0 && + sfd__h757645[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h757630) ; - assign _theResult___exp__h778728 = - sfd__h778091[53] ? - ((_theResult___fst_exp__h778073 == 11'd2046) ? + _theResult___fst_exp__h757626) ; + assign _theResult___exp__h778724 = + sfd__h778087[53] ? + ((_theResult___fst_exp__h778069 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h797323) : - ((_theResult___fst_exp__h778073 == 11'd0 && - sfd__h778091[53:52] == 2'b01) ? + din_inc___2_exp__h797319) : + ((_theResult___fst_exp__h778069 == 11'd0 && + sfd__h778087[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h778073) ; - assign _theResult___exp__h788379 = - sfd__h787742[53] ? - ((_theResult___fst_exp__h787650 == 11'd2046) ? + _theResult___fst_exp__h778069) ; + assign _theResult___exp__h788375 = + sfd__h787738[53] ? + ((_theResult___fst_exp__h787646 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h797358) : - ((_theResult___fst_exp__h787650 == 11'd0 && - sfd__h787742[53:52] == 2'b01) ? + din_inc___2_exp__h797354) : + ((_theResult___fst_exp__h787646 == 11'd0 && + sfd__h787738[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h787650) ; - assign _theResult___exp__h797163 = - sfd__h796502[53] ? - ((_theResult___fst_exp__h796483 == 11'd2046) ? + _theResult___fst_exp__h787646) ; + assign _theResult___exp__h797159 = + sfd__h796498[53] ? + ((_theResult___fst_exp__h796479 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h797384) : - ((_theResult___fst_exp__h796483 == 11'd0 && - sfd__h796502[53:52] == 2'b01) ? + din_inc___2_exp__h797380) : + ((_theResult___fst_exp__h796479 == 11'd0 && + sfd__h796498[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h796483) ; - assign _theResult___exp__h818032 = - sfd__h817395[53] ? - ((_theResult___fst_exp__h817377 == 11'd2046) ? + _theResult___fst_exp__h796479) ; + assign _theResult___exp__h818028 = + sfd__h817391[53] ? + ((_theResult___fst_exp__h817373 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h836627) : - ((_theResult___fst_exp__h817377 == 11'd0 && - sfd__h817395[53:52] == 2'b01) ? + din_inc___2_exp__h836623) : + ((_theResult___fst_exp__h817373 == 11'd0 && + sfd__h817391[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h817377) ; - assign _theResult___exp__h827683 = - sfd__h827046[53] ? - ((_theResult___fst_exp__h826954 == 11'd2046) ? + _theResult___fst_exp__h817373) ; + assign _theResult___exp__h827679 = + sfd__h827042[53] ? + ((_theResult___fst_exp__h826950 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h836662) : - ((_theResult___fst_exp__h826954 == 11'd0 && - sfd__h827046[53:52] == 2'b01) ? + din_inc___2_exp__h836658) : + ((_theResult___fst_exp__h826950 == 11'd0 && + sfd__h827042[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h826954) ; - assign _theResult___exp__h836467 = - sfd__h835806[53] ? - ((_theResult___fst_exp__h835787 == 11'd2046) ? + _theResult___fst_exp__h826950) ; + assign _theResult___exp__h836463 = + sfd__h835802[53] ? + ((_theResult___fst_exp__h835783 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h836688) : - ((_theResult___fst_exp__h835787 == 11'd0 && - sfd__h835806[53:52] == 2'b01) ? + din_inc___2_exp__h836684) : + ((_theResult___fst_exp__h835783 == 11'd0 && + sfd__h835802[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h835787) ; - assign _theResult___fst__h841226 = - a__h840678[63] ? a___1__h841231 : a__h840678 ; - assign _theResult___fst_exp__h588990 = - _theResult____h580879[56] ? + _theResult___fst_exp__h835783) ; + assign _theResult___fst__h841222 = + a__h840674[63] ? a___1__h841227 : a__h840674 ; + assign _theResult___fst_exp__h588987 = + _theResult____h580876[56] ? 8'd2 : - _theResult___fst_exp__h589064 ; - assign _theResult___fst_exp__h589055 = + _theResult___fst_exp__h589061 ; + assign _theResult___fst_exp__h589052 = 8'd0 - { 2'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d8461 } ; - assign _theResult___fst_exp__h589061 = - (!_theResult____h580879[56] && !_theResult____h580879[55] && - !_theResult____h580879[54] && - !_theResult____h580879[53] && - !_theResult____h580879[52] && - !_theResult____h580879[51] && - !_theResult____h580879[50] && - !_theResult____h580879[49] && - !_theResult____h580879[48] && - !_theResult____h580879[47] && - !_theResult____h580879[46] && - !_theResult____h580879[45] && - !_theResult____h580879[44] && - !_theResult____h580879[43] && - !_theResult____h580879[42] && - !_theResult____h580879[41] && - !_theResult____h580879[40] && - !_theResult____h580879[39] && - !_theResult____h580879[38] && - !_theResult____h580879[37] && - !_theResult____h580879[36] && - !_theResult____h580879[35] && - !_theResult____h580879[34] && - !_theResult____h580879[33] && - !_theResult____h580879[32] && - !_theResult____h580879[31] && - !_theResult____h580879[30] && - !_theResult____h580879[29] && - !_theResult____h580879[28] && - !_theResult____h580879[27] && - !_theResult____h580879[26] && - !_theResult____h580879[25] && - !_theResult____h580879[24] && - !_theResult____h580879[23] && - !_theResult____h580879[22] && - !_theResult____h580879[21] && - !_theResult____h580879[20] && - !_theResult____h580879[19] && - !_theResult____h580879[18] && - !_theResult____h580879[17] && - !_theResult____h580879[16] && - !_theResult____h580879[15] && - !_theResult____h580879[14] && - !_theResult____h580879[13] && - !_theResult____h580879[12] && - !_theResult____h580879[11] && - !_theResult____h580879[10] && - !_theResult____h580879[9] && - !_theResult____h580879[8] && - !_theResult____h580879[7] && - !_theResult____h580879[6] && - !_theResult____h580879[5] && - !_theResult____h580879[4] && - !_theResult____h580879[3] && - !_theResult____h580879[2] && - !_theResult____h580879[1] && - !_theResult____h580879[0] || + assign _theResult___fst_exp__h589058 = + (!_theResult____h580876[56] && !_theResult____h580876[55] && + !_theResult____h580876[54] && + !_theResult____h580876[53] && + !_theResult____h580876[52] && + !_theResult____h580876[51] && + !_theResult____h580876[50] && + !_theResult____h580876[49] && + !_theResult____h580876[48] && + !_theResult____h580876[47] && + !_theResult____h580876[46] && + !_theResult____h580876[45] && + !_theResult____h580876[44] && + !_theResult____h580876[43] && + !_theResult____h580876[42] && + !_theResult____h580876[41] && + !_theResult____h580876[40] && + !_theResult____h580876[39] && + !_theResult____h580876[38] && + !_theResult____h580876[37] && + !_theResult____h580876[36] && + !_theResult____h580876[35] && + !_theResult____h580876[34] && + !_theResult____h580876[33] && + !_theResult____h580876[32] && + !_theResult____h580876[31] && + !_theResult____h580876[30] && + !_theResult____h580876[29] && + !_theResult____h580876[28] && + !_theResult____h580876[27] && + !_theResult____h580876[26] && + !_theResult____h580876[25] && + !_theResult____h580876[24] && + !_theResult____h580876[23] && + !_theResult____h580876[22] && + !_theResult____h580876[21] && + !_theResult____h580876[20] && + !_theResult____h580876[19] && + !_theResult____h580876[18] && + !_theResult____h580876[17] && + !_theResult____h580876[16] && + !_theResult____h580876[15] && + !_theResult____h580876[14] && + !_theResult____h580876[13] && + !_theResult____h580876[12] && + !_theResult____h580876[11] && + !_theResult____h580876[10] && + !_theResult____h580876[9] && + !_theResult____h580876[8] && + !_theResult____h580876[7] && + !_theResult____h580876[6] && + !_theResult____h580876[5] && + !_theResult____h580876[4] && + !_theResult____h580876[3] && + !_theResult____h580876[2] && + !_theResult____h580876[1] && + !_theResult____h580876[0] || !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d8463) ? 8'd0 : - _theResult___fst_exp__h589055 ; - assign _theResult___fst_exp__h589064 = - (!_theResult____h580879[56] && _theResult____h580879[55]) ? + _theResult___fst_exp__h589052 ; + assign _theResult___fst_exp__h589061 = + (!_theResult____h580876[56] && _theResult____h580876[55]) ? 8'd1 : - _theResult___fst_exp__h589061 ; - assign _theResult___fst_exp__h589587 = - (_theResult___fst_exp__h588990 == 8'd255) ? - _theResult___fst_exp__h588990 : - _theResult___fst_exp__h589584 ; - assign _theResult___fst_exp__h597637 = + _theResult___fst_exp__h589058 ; + assign _theResult___fst_exp__h589584 = + (_theResult___fst_exp__h588987 == 8'd255) ? + _theResult___fst_exp__h588987 : + _theResult___fst_exp__h589581 ; + assign _theResult___fst_exp__h597634 = 8'd129 - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d8692 } ; - assign _theResult___fst_exp__h597643 = + assign _theResult___fst_exp__h597640 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d8637 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d8694) ? 8'd0 : - _theResult___fst_exp__h597637 ; - assign _theResult___fst_exp__h597646 = + _theResult___fst_exp__h597634 ; + assign _theResult___fst_exp__h597643 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h597643 : + _theResult___fst_exp__h597640 : 8'd129 ; - assign _theResult___fst_exp__h598169 = - (_theResult___fst_exp__h597646 == 8'd255) ? - _theResult___fst_exp__h597646 : - _theResult___fst_exp__h598166 ; - assign _theResult___fst_exp__h606756 = - _theResult____h598518[56] ? + assign _theResult___fst_exp__h598166 = + (_theResult___fst_exp__h597643 == 8'd255) ? + _theResult___fst_exp__h597643 : + _theResult___fst_exp__h598163 ; + assign _theResult___fst_exp__h606753 = + _theResult____h598515[56] ? 8'd2 : - _theResult___fst_exp__h606830 ; - assign _theResult___fst_exp__h606821 = + _theResult___fst_exp__h606827 ; + assign _theResult___fst_exp__h606818 = 8'd0 - { 2'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d9012 } ; - assign _theResult___fst_exp__h606827 = - (!_theResult____h598518[56] && !_theResult____h598518[55] && - !_theResult____h598518[54] && - !_theResult____h598518[53] && - !_theResult____h598518[52] && - !_theResult____h598518[51] && - !_theResult____h598518[50] && - !_theResult____h598518[49] && - !_theResult____h598518[48] && - !_theResult____h598518[47] && - !_theResult____h598518[46] && - !_theResult____h598518[45] && - !_theResult____h598518[44] && - !_theResult____h598518[43] && - !_theResult____h598518[42] && - !_theResult____h598518[41] && - !_theResult____h598518[40] && - !_theResult____h598518[39] && - !_theResult____h598518[38] && - !_theResult____h598518[37] && - !_theResult____h598518[36] && - !_theResult____h598518[35] && - !_theResult____h598518[34] && - !_theResult____h598518[33] && - !_theResult____h598518[32] && - !_theResult____h598518[31] && - !_theResult____h598518[30] && - !_theResult____h598518[29] && - !_theResult____h598518[28] && - !_theResult____h598518[27] && - !_theResult____h598518[26] && - !_theResult____h598518[25] && - !_theResult____h598518[24] && - !_theResult____h598518[23] && - !_theResult____h598518[22] && - !_theResult____h598518[21] && - !_theResult____h598518[20] && - !_theResult____h598518[19] && - !_theResult____h598518[18] && - !_theResult____h598518[17] && - !_theResult____h598518[16] && - !_theResult____h598518[15] && - !_theResult____h598518[14] && - !_theResult____h598518[13] && - !_theResult____h598518[12] && - !_theResult____h598518[11] && - !_theResult____h598518[10] && - !_theResult____h598518[9] && - !_theResult____h598518[8] && - !_theResult____h598518[7] && - !_theResult____h598518[6] && - !_theResult____h598518[5] && - !_theResult____h598518[4] && - !_theResult____h598518[3] && - !_theResult____h598518[2] && - !_theResult____h598518[1] && - !_theResult____h598518[0] || + assign _theResult___fst_exp__h606824 = + (!_theResult____h598515[56] && !_theResult____h598515[55] && + !_theResult____h598515[54] && + !_theResult____h598515[53] && + !_theResult____h598515[52] && + !_theResult____h598515[51] && + !_theResult____h598515[50] && + !_theResult____h598515[49] && + !_theResult____h598515[48] && + !_theResult____h598515[47] && + !_theResult____h598515[46] && + !_theResult____h598515[45] && + !_theResult____h598515[44] && + !_theResult____h598515[43] && + !_theResult____h598515[42] && + !_theResult____h598515[41] && + !_theResult____h598515[40] && + !_theResult____h598515[39] && + !_theResult____h598515[38] && + !_theResult____h598515[37] && + !_theResult____h598515[36] && + !_theResult____h598515[35] && + !_theResult____h598515[34] && + !_theResult____h598515[33] && + !_theResult____h598515[32] && + !_theResult____h598515[31] && + !_theResult____h598515[30] && + !_theResult____h598515[29] && + !_theResult____h598515[28] && + !_theResult____h598515[27] && + !_theResult____h598515[26] && + !_theResult____h598515[25] && + !_theResult____h598515[24] && + !_theResult____h598515[23] && + !_theResult____h598515[22] && + !_theResult____h598515[21] && + !_theResult____h598515[20] && + !_theResult____h598515[19] && + !_theResult____h598515[18] && + !_theResult____h598515[17] && + !_theResult____h598515[16] && + !_theResult____h598515[15] && + !_theResult____h598515[14] && + !_theResult____h598515[13] && + !_theResult____h598515[12] && + !_theResult____h598515[11] && + !_theResult____h598515[10] && + !_theResult____h598515[9] && + !_theResult____h598515[8] && + !_theResult____h598515[7] && + !_theResult____h598515[6] && + !_theResult____h598515[5] && + !_theResult____h598515[4] && + !_theResult____h598515[3] && + !_theResult____h598515[2] && + !_theResult____h598515[1] && + !_theResult____h598515[0] || !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d9014) ? 8'd0 : - _theResult___fst_exp__h606821 ; - assign _theResult___fst_exp__h606830 = - (!_theResult____h598518[56] && _theResult____h598518[55]) ? + _theResult___fst_exp__h606818 ; + assign _theResult___fst_exp__h606827 = + (!_theResult____h598515[56] && _theResult____h598515[55]) ? 8'd1 : - _theResult___fst_exp__h606827 ; - assign _theResult___fst_exp__h607353 = - (_theResult___fst_exp__h606756 == 8'd255) ? - _theResult___fst_exp__h606756 : - _theResult___fst_exp__h607350 ; - assign _theResult___fst_exp__h615393 = - (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q42[7:0] == + _theResult___fst_exp__h606824 ; + assign _theResult___fst_exp__h607350 = + (_theResult___fst_exp__h606753 == 8'd255) ? + _theResult___fst_exp__h606753 : + _theResult___fst_exp__h607347 ; + assign _theResult___fst_exp__h615390 = + (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q50[7:0] == 8'd0) ? 8'd1 : - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q42[7:0] ; - assign _theResult___fst_exp__h615432 = - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q42[7:0] - + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q50[7:0] ; + assign _theResult___fst_exp__h615429 = + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q50[7:0] - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d8692 } ; - assign _theResult___fst_exp__h615438 = + assign _theResult___fst_exp__h615435 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d8637 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d9087) ? 8'd0 : - _theResult___fst_exp__h615432 ; - assign _theResult___fst_exp__h615441 = + _theResult___fst_exp__h615429 ; + assign _theResult___fst_exp__h615438 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? + _theResult___fst_exp__h615435 : + _theResult___fst_exp__h615390 ; + assign _theResult___fst_exp__h615986 = + (_theResult___fst_exp__h615438 == 8'd255) ? _theResult___fst_exp__h615438 : - _theResult___fst_exp__h615393 ; - assign _theResult___fst_exp__h615989 = - (_theResult___fst_exp__h615441 == 8'd255) ? - _theResult___fst_exp__h615441 : - _theResult___fst_exp__h615986 ; - assign _theResult___fst_exp__h615998 = + _theResult___fst_exp__h615983 ; + assign _theResult___fst_exp__h615995 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8226 ? - _theResult___snd_fst_exp__h598172 : - _theResult___fst_exp__h580861) : + _theResult___snd_fst_exp__h598169 : + _theResult___fst_exp__h580858) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8766 ? - _theResult___snd_fst_exp__h615992 : - _theResult___fst_exp__h580861) ; - assign _theResult___fst_exp__h616001 = + _theResult___snd_fst_exp__h615989 : + _theResult___fst_exp__h580858) ; + assign _theResult___fst_exp__h615998 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == 52'd0) ? 8'd0 : - _theResult___fst_exp__h615998 ; - assign _theResult___fst_exp__h634739 = - _theResult____h626630[56] ? + _theResult___fst_exp__h615995 ; + assign _theResult___fst_exp__h634736 = + _theResult____h626627[56] ? 8'd2 : - _theResult___fst_exp__h634813 ; - assign _theResult___fst_exp__h634804 = + _theResult___fst_exp__h634810 ; + assign _theResult___fst_exp__h634801 = 8'd0 - { 2'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d9858 } ; - assign _theResult___fst_exp__h634810 = - (!_theResult____h626630[56] && !_theResult____h626630[55] && - !_theResult____h626630[54] && - !_theResult____h626630[53] && - !_theResult____h626630[52] && - !_theResult____h626630[51] && - !_theResult____h626630[50] && - !_theResult____h626630[49] && - !_theResult____h626630[48] && - !_theResult____h626630[47] && - !_theResult____h626630[46] && - !_theResult____h626630[45] && - !_theResult____h626630[44] && - !_theResult____h626630[43] && - !_theResult____h626630[42] && - !_theResult____h626630[41] && - !_theResult____h626630[40] && - !_theResult____h626630[39] && - !_theResult____h626630[38] && - !_theResult____h626630[37] && - !_theResult____h626630[36] && - !_theResult____h626630[35] && - !_theResult____h626630[34] && - !_theResult____h626630[33] && - !_theResult____h626630[32] && - !_theResult____h626630[31] && - !_theResult____h626630[30] && - !_theResult____h626630[29] && - !_theResult____h626630[28] && - !_theResult____h626630[27] && - !_theResult____h626630[26] && - !_theResult____h626630[25] && - !_theResult____h626630[24] && - !_theResult____h626630[23] && - !_theResult____h626630[22] && - !_theResult____h626630[21] && - !_theResult____h626630[20] && - !_theResult____h626630[19] && - !_theResult____h626630[18] && - !_theResult____h626630[17] && - !_theResult____h626630[16] && - !_theResult____h626630[15] && - !_theResult____h626630[14] && - !_theResult____h626630[13] && - !_theResult____h626630[12] && - !_theResult____h626630[11] && - !_theResult____h626630[10] && - !_theResult____h626630[9] && - !_theResult____h626630[8] && - !_theResult____h626630[7] && - !_theResult____h626630[6] && - !_theResult____h626630[5] && - !_theResult____h626630[4] && - !_theResult____h626630[3] && - !_theResult____h626630[2] && - !_theResult____h626630[1] && - !_theResult____h626630[0] || + assign _theResult___fst_exp__h634807 = + (!_theResult____h626627[56] && !_theResult____h626627[55] && + !_theResult____h626627[54] && + !_theResult____h626627[53] && + !_theResult____h626627[52] && + !_theResult____h626627[51] && + !_theResult____h626627[50] && + !_theResult____h626627[49] && + !_theResult____h626627[48] && + !_theResult____h626627[47] && + !_theResult____h626627[46] && + !_theResult____h626627[45] && + !_theResult____h626627[44] && + !_theResult____h626627[43] && + !_theResult____h626627[42] && + !_theResult____h626627[41] && + !_theResult____h626627[40] && + !_theResult____h626627[39] && + !_theResult____h626627[38] && + !_theResult____h626627[37] && + !_theResult____h626627[36] && + !_theResult____h626627[35] && + !_theResult____h626627[34] && + !_theResult____h626627[33] && + !_theResult____h626627[32] && + !_theResult____h626627[31] && + !_theResult____h626627[30] && + !_theResult____h626627[29] && + !_theResult____h626627[28] && + !_theResult____h626627[27] && + !_theResult____h626627[26] && + !_theResult____h626627[25] && + !_theResult____h626627[24] && + !_theResult____h626627[23] && + !_theResult____h626627[22] && + !_theResult____h626627[21] && + !_theResult____h626627[20] && + !_theResult____h626627[19] && + !_theResult____h626627[18] && + !_theResult____h626627[17] && + !_theResult____h626627[16] && + !_theResult____h626627[15] && + !_theResult____h626627[14] && + !_theResult____h626627[13] && + !_theResult____h626627[12] && + !_theResult____h626627[11] && + !_theResult____h626627[10] && + !_theResult____h626627[9] && + !_theResult____h626627[8] && + !_theResult____h626627[7] && + !_theResult____h626627[6] && + !_theResult____h626627[5] && + !_theResult____h626627[4] && + !_theResult____h626627[3] && + !_theResult____h626627[2] && + !_theResult____h626627[1] && + !_theResult____h626627[0] || !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d9860) ? 8'd0 : - _theResult___fst_exp__h634804 ; - assign _theResult___fst_exp__h634813 = - (!_theResult____h626630[56] && _theResult____h626630[55]) ? + _theResult___fst_exp__h634801 ; + assign _theResult___fst_exp__h634810 = + (!_theResult____h626627[56] && _theResult____h626627[55]) ? 8'd1 : - _theResult___fst_exp__h634810 ; - assign _theResult___fst_exp__h635336 = - (_theResult___fst_exp__h634739 == 8'd255) ? - _theResult___fst_exp__h634739 : - _theResult___fst_exp__h635333 ; - assign _theResult___fst_exp__h643386 = + _theResult___fst_exp__h634807 ; + assign _theResult___fst_exp__h635333 = + (_theResult___fst_exp__h634736 == 8'd255) ? + _theResult___fst_exp__h634736 : + _theResult___fst_exp__h635330 ; + assign _theResult___fst_exp__h643383 = 8'd129 - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d10089 } ; - assign _theResult___fst_exp__h643392 = + assign _theResult___fst_exp__h643389 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d10034 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d10091) ? 8'd0 : - _theResult___fst_exp__h643386 ; - assign _theResult___fst_exp__h643395 = + _theResult___fst_exp__h643383 ; + assign _theResult___fst_exp__h643392 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h643392 : + _theResult___fst_exp__h643389 : 8'd129 ; - assign _theResult___fst_exp__h643918 = - (_theResult___fst_exp__h643395 == 8'd255) ? - _theResult___fst_exp__h643395 : - _theResult___fst_exp__h643915 ; - assign _theResult___fst_exp__h652505 = - _theResult____h644267[56] ? + assign _theResult___fst_exp__h643915 = + (_theResult___fst_exp__h643392 == 8'd255) ? + _theResult___fst_exp__h643392 : + _theResult___fst_exp__h643912 ; + assign _theResult___fst_exp__h652502 = + _theResult____h644264[56] ? 8'd2 : - _theResult___fst_exp__h652579 ; - assign _theResult___fst_exp__h652570 = + _theResult___fst_exp__h652576 ; + assign _theResult___fst_exp__h652567 = 8'd0 - { 2'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d10409 } ; - assign _theResult___fst_exp__h652576 = - (!_theResult____h644267[56] && !_theResult____h644267[55] && - !_theResult____h644267[54] && - !_theResult____h644267[53] && - !_theResult____h644267[52] && - !_theResult____h644267[51] && - !_theResult____h644267[50] && - !_theResult____h644267[49] && - !_theResult____h644267[48] && - !_theResult____h644267[47] && - !_theResult____h644267[46] && - !_theResult____h644267[45] && - !_theResult____h644267[44] && - !_theResult____h644267[43] && - !_theResult____h644267[42] && - !_theResult____h644267[41] && - !_theResult____h644267[40] && - !_theResult____h644267[39] && - !_theResult____h644267[38] && - !_theResult____h644267[37] && - !_theResult____h644267[36] && - !_theResult____h644267[35] && - !_theResult____h644267[34] && - !_theResult____h644267[33] && - !_theResult____h644267[32] && - !_theResult____h644267[31] && - !_theResult____h644267[30] && - !_theResult____h644267[29] && - !_theResult____h644267[28] && - !_theResult____h644267[27] && - !_theResult____h644267[26] && - !_theResult____h644267[25] && - !_theResult____h644267[24] && - !_theResult____h644267[23] && - !_theResult____h644267[22] && - !_theResult____h644267[21] && - !_theResult____h644267[20] && - !_theResult____h644267[19] && - !_theResult____h644267[18] && - !_theResult____h644267[17] && - !_theResult____h644267[16] && - !_theResult____h644267[15] && - !_theResult____h644267[14] && - !_theResult____h644267[13] && - !_theResult____h644267[12] && - !_theResult____h644267[11] && - !_theResult____h644267[10] && - !_theResult____h644267[9] && - !_theResult____h644267[8] && - !_theResult____h644267[7] && - !_theResult____h644267[6] && - !_theResult____h644267[5] && - !_theResult____h644267[4] && - !_theResult____h644267[3] && - !_theResult____h644267[2] && - !_theResult____h644267[1] && - !_theResult____h644267[0] || + assign _theResult___fst_exp__h652573 = + (!_theResult____h644264[56] && !_theResult____h644264[55] && + !_theResult____h644264[54] && + !_theResult____h644264[53] && + !_theResult____h644264[52] && + !_theResult____h644264[51] && + !_theResult____h644264[50] && + !_theResult____h644264[49] && + !_theResult____h644264[48] && + !_theResult____h644264[47] && + !_theResult____h644264[46] && + !_theResult____h644264[45] && + !_theResult____h644264[44] && + !_theResult____h644264[43] && + !_theResult____h644264[42] && + !_theResult____h644264[41] && + !_theResult____h644264[40] && + !_theResult____h644264[39] && + !_theResult____h644264[38] && + !_theResult____h644264[37] && + !_theResult____h644264[36] && + !_theResult____h644264[35] && + !_theResult____h644264[34] && + !_theResult____h644264[33] && + !_theResult____h644264[32] && + !_theResult____h644264[31] && + !_theResult____h644264[30] && + !_theResult____h644264[29] && + !_theResult____h644264[28] && + !_theResult____h644264[27] && + !_theResult____h644264[26] && + !_theResult____h644264[25] && + !_theResult____h644264[24] && + !_theResult____h644264[23] && + !_theResult____h644264[22] && + !_theResult____h644264[21] && + !_theResult____h644264[20] && + !_theResult____h644264[19] && + !_theResult____h644264[18] && + !_theResult____h644264[17] && + !_theResult____h644264[16] && + !_theResult____h644264[15] && + !_theResult____h644264[14] && + !_theResult____h644264[13] && + !_theResult____h644264[12] && + !_theResult____h644264[11] && + !_theResult____h644264[10] && + !_theResult____h644264[9] && + !_theResult____h644264[8] && + !_theResult____h644264[7] && + !_theResult____h644264[6] && + !_theResult____h644264[5] && + !_theResult____h644264[4] && + !_theResult____h644264[3] && + !_theResult____h644264[2] && + !_theResult____h644264[1] && + !_theResult____h644264[0] || !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d10411) ? 8'd0 : - _theResult___fst_exp__h652570 ; - assign _theResult___fst_exp__h652579 = - (!_theResult____h644267[56] && _theResult____h644267[55]) ? + _theResult___fst_exp__h652567 ; + assign _theResult___fst_exp__h652576 = + (!_theResult____h644264[56] && _theResult____h644264[55]) ? 8'd1 : - _theResult___fst_exp__h652576 ; - assign _theResult___fst_exp__h653102 = - (_theResult___fst_exp__h652505 == 8'd255) ? - _theResult___fst_exp__h652505 : - _theResult___fst_exp__h653099 ; - assign _theResult___fst_exp__h661142 = + _theResult___fst_exp__h652573 ; + assign _theResult___fst_exp__h653099 = + (_theResult___fst_exp__h652502 == 8'd255) ? + _theResult___fst_exp__h652502 : + _theResult___fst_exp__h653096 ; + assign _theResult___fst_exp__h661139 = (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q85[7:0] == 8'd0) ? 8'd1 : SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q85[7:0] ; - assign _theResult___fst_exp__h661181 = + assign _theResult___fst_exp__h661178 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q85[7:0] - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d10089 } ; - assign _theResult___fst_exp__h661187 = + assign _theResult___fst_exp__h661184 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d10034 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d10484) ? 8'd0 : - _theResult___fst_exp__h661181 ; - assign _theResult___fst_exp__h661190 = + _theResult___fst_exp__h661178 ; + assign _theResult___fst_exp__h661187 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? + _theResult___fst_exp__h661184 : + _theResult___fst_exp__h661139 ; + assign _theResult___fst_exp__h661735 = + (_theResult___fst_exp__h661187 == 8'd255) ? _theResult___fst_exp__h661187 : - _theResult___fst_exp__h661142 ; - assign _theResult___fst_exp__h661738 = - (_theResult___fst_exp__h661190 == 8'd255) ? - _theResult___fst_exp__h661190 : - _theResult___fst_exp__h661735 ; - assign _theResult___fst_exp__h661747 = + _theResult___fst_exp__h661732 ; + assign _theResult___fst_exp__h661744 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9623 ? - _theResult___snd_fst_exp__h643921 : - _theResult___fst_exp__h626612) : + _theResult___snd_fst_exp__h643918 : + _theResult___fst_exp__h626609) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10163 ? - _theResult___snd_fst_exp__h661741 : - _theResult___fst_exp__h626612) ; - assign _theResult___fst_exp__h661750 = + _theResult___snd_fst_exp__h661738 : + _theResult___fst_exp__h626609) ; + assign _theResult___fst_exp__h661747 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == 52'd0) ? 8'd0 : - _theResult___fst_exp__h661747 ; - assign _theResult___fst_exp__h680486 = - _theResult____h672377[56] ? + _theResult___fst_exp__h661744 ; + assign _theResult___fst_exp__h680483 = + _theResult____h672374[56] ? 8'd2 : - _theResult___fst_exp__h680560 ; - assign _theResult___fst_exp__h680551 = + _theResult___fst_exp__h680557 ; + assign _theResult___fst_exp__h680548 = 8'd0 - { 2'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d11255 } ; - assign _theResult___fst_exp__h680557 = - (!_theResult____h672377[56] && !_theResult____h672377[55] && - !_theResult____h672377[54] && - !_theResult____h672377[53] && - !_theResult____h672377[52] && - !_theResult____h672377[51] && - !_theResult____h672377[50] && - !_theResult____h672377[49] && - !_theResult____h672377[48] && - !_theResult____h672377[47] && - !_theResult____h672377[46] && - !_theResult____h672377[45] && - !_theResult____h672377[44] && - !_theResult____h672377[43] && - !_theResult____h672377[42] && - !_theResult____h672377[41] && - !_theResult____h672377[40] && - !_theResult____h672377[39] && - !_theResult____h672377[38] && - !_theResult____h672377[37] && - !_theResult____h672377[36] && - !_theResult____h672377[35] && - !_theResult____h672377[34] && - !_theResult____h672377[33] && - !_theResult____h672377[32] && - !_theResult____h672377[31] && - !_theResult____h672377[30] && - !_theResult____h672377[29] && - !_theResult____h672377[28] && - !_theResult____h672377[27] && - !_theResult____h672377[26] && - !_theResult____h672377[25] && - !_theResult____h672377[24] && - !_theResult____h672377[23] && - !_theResult____h672377[22] && - !_theResult____h672377[21] && - !_theResult____h672377[20] && - !_theResult____h672377[19] && - !_theResult____h672377[18] && - !_theResult____h672377[17] && - !_theResult____h672377[16] && - !_theResult____h672377[15] && - !_theResult____h672377[14] && - !_theResult____h672377[13] && - !_theResult____h672377[12] && - !_theResult____h672377[11] && - !_theResult____h672377[10] && - !_theResult____h672377[9] && - !_theResult____h672377[8] && - !_theResult____h672377[7] && - !_theResult____h672377[6] && - !_theResult____h672377[5] && - !_theResult____h672377[4] && - !_theResult____h672377[3] && - !_theResult____h672377[2] && - !_theResult____h672377[1] && - !_theResult____h672377[0] || + assign _theResult___fst_exp__h680554 = + (!_theResult____h672374[56] && !_theResult____h672374[55] && + !_theResult____h672374[54] && + !_theResult____h672374[53] && + !_theResult____h672374[52] && + !_theResult____h672374[51] && + !_theResult____h672374[50] && + !_theResult____h672374[49] && + !_theResult____h672374[48] && + !_theResult____h672374[47] && + !_theResult____h672374[46] && + !_theResult____h672374[45] && + !_theResult____h672374[44] && + !_theResult____h672374[43] && + !_theResult____h672374[42] && + !_theResult____h672374[41] && + !_theResult____h672374[40] && + !_theResult____h672374[39] && + !_theResult____h672374[38] && + !_theResult____h672374[37] && + !_theResult____h672374[36] && + !_theResult____h672374[35] && + !_theResult____h672374[34] && + !_theResult____h672374[33] && + !_theResult____h672374[32] && + !_theResult____h672374[31] && + !_theResult____h672374[30] && + !_theResult____h672374[29] && + !_theResult____h672374[28] && + !_theResult____h672374[27] && + !_theResult____h672374[26] && + !_theResult____h672374[25] && + !_theResult____h672374[24] && + !_theResult____h672374[23] && + !_theResult____h672374[22] && + !_theResult____h672374[21] && + !_theResult____h672374[20] && + !_theResult____h672374[19] && + !_theResult____h672374[18] && + !_theResult____h672374[17] && + !_theResult____h672374[16] && + !_theResult____h672374[15] && + !_theResult____h672374[14] && + !_theResult____h672374[13] && + !_theResult____h672374[12] && + !_theResult____h672374[11] && + !_theResult____h672374[10] && + !_theResult____h672374[9] && + !_theResult____h672374[8] && + !_theResult____h672374[7] && + !_theResult____h672374[6] && + !_theResult____h672374[5] && + !_theResult____h672374[4] && + !_theResult____h672374[3] && + !_theResult____h672374[2] && + !_theResult____h672374[1] && + !_theResult____h672374[0] || !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d11257) ? 8'd0 : - _theResult___fst_exp__h680551 ; - assign _theResult___fst_exp__h680560 = - (!_theResult____h672377[56] && _theResult____h672377[55]) ? + _theResult___fst_exp__h680548 ; + assign _theResult___fst_exp__h680557 = + (!_theResult____h672374[56] && _theResult____h672374[55]) ? 8'd1 : - _theResult___fst_exp__h680557 ; - assign _theResult___fst_exp__h681083 = - (_theResult___fst_exp__h680486 == 8'd255) ? - _theResult___fst_exp__h680486 : - _theResult___fst_exp__h681080 ; - assign _theResult___fst_exp__h689133 = + _theResult___fst_exp__h680554 ; + assign _theResult___fst_exp__h681080 = + (_theResult___fst_exp__h680483 == 8'd255) ? + _theResult___fst_exp__h680483 : + _theResult___fst_exp__h681077 ; + assign _theResult___fst_exp__h689130 = 8'd129 - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d11486 } ; - assign _theResult___fst_exp__h689139 = + assign _theResult___fst_exp__h689136 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d11431 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d11488) ? 8'd0 : - _theResult___fst_exp__h689133 ; - assign _theResult___fst_exp__h689142 = + _theResult___fst_exp__h689130 ; + assign _theResult___fst_exp__h689139 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h689139 : + _theResult___fst_exp__h689136 : 8'd129 ; - assign _theResult___fst_exp__h689665 = - (_theResult___fst_exp__h689142 == 8'd255) ? - _theResult___fst_exp__h689142 : - _theResult___fst_exp__h689662 ; - assign _theResult___fst_exp__h698252 = - _theResult____h690014[56] ? + assign _theResult___fst_exp__h689662 = + (_theResult___fst_exp__h689139 == 8'd255) ? + _theResult___fst_exp__h689139 : + _theResult___fst_exp__h689659 ; + assign _theResult___fst_exp__h698249 = + _theResult____h690011[56] ? 8'd2 : - _theResult___fst_exp__h698326 ; - assign _theResult___fst_exp__h698317 = + _theResult___fst_exp__h698323 ; + assign _theResult___fst_exp__h698314 = 8'd0 - { 2'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d11806 } ; - assign _theResult___fst_exp__h698323 = - (!_theResult____h690014[56] && !_theResult____h690014[55] && - !_theResult____h690014[54] && - !_theResult____h690014[53] && - !_theResult____h690014[52] && - !_theResult____h690014[51] && - !_theResult____h690014[50] && - !_theResult____h690014[49] && - !_theResult____h690014[48] && - !_theResult____h690014[47] && - !_theResult____h690014[46] && - !_theResult____h690014[45] && - !_theResult____h690014[44] && - !_theResult____h690014[43] && - !_theResult____h690014[42] && - !_theResult____h690014[41] && - !_theResult____h690014[40] && - !_theResult____h690014[39] && - !_theResult____h690014[38] && - !_theResult____h690014[37] && - !_theResult____h690014[36] && - !_theResult____h690014[35] && - !_theResult____h690014[34] && - !_theResult____h690014[33] && - !_theResult____h690014[32] && - !_theResult____h690014[31] && - !_theResult____h690014[30] && - !_theResult____h690014[29] && - !_theResult____h690014[28] && - !_theResult____h690014[27] && - !_theResult____h690014[26] && - !_theResult____h690014[25] && - !_theResult____h690014[24] && - !_theResult____h690014[23] && - !_theResult____h690014[22] && - !_theResult____h690014[21] && - !_theResult____h690014[20] && - !_theResult____h690014[19] && - !_theResult____h690014[18] && - !_theResult____h690014[17] && - !_theResult____h690014[16] && - !_theResult____h690014[15] && - !_theResult____h690014[14] && - !_theResult____h690014[13] && - !_theResult____h690014[12] && - !_theResult____h690014[11] && - !_theResult____h690014[10] && - !_theResult____h690014[9] && - !_theResult____h690014[8] && - !_theResult____h690014[7] && - !_theResult____h690014[6] && - !_theResult____h690014[5] && - !_theResult____h690014[4] && - !_theResult____h690014[3] && - !_theResult____h690014[2] && - !_theResult____h690014[1] && - !_theResult____h690014[0] || + assign _theResult___fst_exp__h698320 = + (!_theResult____h690011[56] && !_theResult____h690011[55] && + !_theResult____h690011[54] && + !_theResult____h690011[53] && + !_theResult____h690011[52] && + !_theResult____h690011[51] && + !_theResult____h690011[50] && + !_theResult____h690011[49] && + !_theResult____h690011[48] && + !_theResult____h690011[47] && + !_theResult____h690011[46] && + !_theResult____h690011[45] && + !_theResult____h690011[44] && + !_theResult____h690011[43] && + !_theResult____h690011[42] && + !_theResult____h690011[41] && + !_theResult____h690011[40] && + !_theResult____h690011[39] && + !_theResult____h690011[38] && + !_theResult____h690011[37] && + !_theResult____h690011[36] && + !_theResult____h690011[35] && + !_theResult____h690011[34] && + !_theResult____h690011[33] && + !_theResult____h690011[32] && + !_theResult____h690011[31] && + !_theResult____h690011[30] && + !_theResult____h690011[29] && + !_theResult____h690011[28] && + !_theResult____h690011[27] && + !_theResult____h690011[26] && + !_theResult____h690011[25] && + !_theResult____h690011[24] && + !_theResult____h690011[23] && + !_theResult____h690011[22] && + !_theResult____h690011[21] && + !_theResult____h690011[20] && + !_theResult____h690011[19] && + !_theResult____h690011[18] && + !_theResult____h690011[17] && + !_theResult____h690011[16] && + !_theResult____h690011[15] && + !_theResult____h690011[14] && + !_theResult____h690011[13] && + !_theResult____h690011[12] && + !_theResult____h690011[11] && + !_theResult____h690011[10] && + !_theResult____h690011[9] && + !_theResult____h690011[8] && + !_theResult____h690011[7] && + !_theResult____h690011[6] && + !_theResult____h690011[5] && + !_theResult____h690011[4] && + !_theResult____h690011[3] && + !_theResult____h690011[2] && + !_theResult____h690011[1] && + !_theResult____h690011[0] || !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d11808) ? 8'd0 : - _theResult___fst_exp__h698317 ; - assign _theResult___fst_exp__h698326 = - (!_theResult____h690014[56] && _theResult____h690014[55]) ? + _theResult___fst_exp__h698314 ; + assign _theResult___fst_exp__h698323 = + (!_theResult____h690011[56] && _theResult____h690011[55]) ? 8'd1 : - _theResult___fst_exp__h698323 ; - assign _theResult___fst_exp__h698849 = - (_theResult___fst_exp__h698252 == 8'd255) ? - _theResult___fst_exp__h698252 : - _theResult___fst_exp__h698846 ; - assign _theResult___fst_exp__h706889 = + _theResult___fst_exp__h698320 ; + assign _theResult___fst_exp__h698846 = + (_theResult___fst_exp__h698249 == 8'd255) ? + _theResult___fst_exp__h698249 : + _theResult___fst_exp__h698843 ; + assign _theResult___fst_exp__h706886 = (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q120[7:0] == 8'd0) ? 8'd1 : SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q120[7:0] ; - assign _theResult___fst_exp__h706928 = + assign _theResult___fst_exp__h706925 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q120[7:0] - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d11486 } ; - assign _theResult___fst_exp__h706934 = + assign _theResult___fst_exp__h706931 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d11431 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d11881) ? 8'd0 : - _theResult___fst_exp__h706928 ; - assign _theResult___fst_exp__h706937 = + _theResult___fst_exp__h706925 ; + assign _theResult___fst_exp__h706934 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? + _theResult___fst_exp__h706931 : + _theResult___fst_exp__h706886 ; + assign _theResult___fst_exp__h707482 = + (_theResult___fst_exp__h706934 == 8'd255) ? _theResult___fst_exp__h706934 : - _theResult___fst_exp__h706889 ; - assign _theResult___fst_exp__h707485 = - (_theResult___fst_exp__h706937 == 8'd255) ? - _theResult___fst_exp__h706937 : - _theResult___fst_exp__h707482 ; - assign _theResult___fst_exp__h707494 = + _theResult___fst_exp__h707479 ; + assign _theResult___fst_exp__h707491 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d11020 ? - _theResult___snd_fst_exp__h689668 : - _theResult___fst_exp__h672359) : + _theResult___snd_fst_exp__h689665 : + _theResult___fst_exp__h672356) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11560 ? - _theResult___snd_fst_exp__h707488 : - _theResult___fst_exp__h672359) ; - assign _theResult___fst_exp__h707497 = + _theResult___snd_fst_exp__h707485 : + _theResult___fst_exp__h672356) ; + assign _theResult___fst_exp__h707494 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == 52'd0) ? 8'd0 : - _theResult___fst_exp__h707494 ; - assign _theResult___fst_exp__h724147 = + _theResult___fst_exp__h707491 ; + assign _theResult___fst_exp__h724143 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q28 ; - assign _theResult___fst_exp__h739211 = + assign _theResult___fst_exp__h739207 = 11'd897 - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d12840 } ; - assign _theResult___fst_exp__h739217 = - (f1_exp__h719832 == 8'd0 && !f1_sfd__h719833[22] && + assign _theResult___fst_exp__h739213 = + (f1_exp__h719828 == 8'd0 && !f1_sfd__h719829[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d12813 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d12842) ? 11'd0 : - _theResult___fst_exp__h739211 ; - assign _theResult___fst_exp__h739220 = - (f1_exp__h719832 == 8'd0) ? - _theResult___fst_exp__h739217 : + _theResult___fst_exp__h739207 ; + assign _theResult___fst_exp__h739216 = + (f1_exp__h719828 == 8'd0) ? + _theResult___fst_exp__h739213 : 11'd897 ; - assign _theResult___fst_exp__h739975 = + assign _theResult___fst_exp__h739971 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard31259_0b0_theResult___fst_exp39220_0_ETC__q156 : + CASE_guard31255_0b0_theResult___fst_exp39216_0_ETC__q156 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d13276 ; - assign _theResult___fst_exp__h739978 = - (_theResult___fst_exp__h739220 == 11'd2047) ? - _theResult___fst_exp__h739220 : - _theResult___fst_exp__h739975 ; - assign _theResult___fst_exp__h748797 = - _theResult____h740561[56] ? + assign _theResult___fst_exp__h739974 = + (_theResult___fst_exp__h739216 == 11'd2047) ? + _theResult___fst_exp__h739216 : + _theResult___fst_exp__h739971 ; + assign _theResult___fst_exp__h748793 = + _theResult____h740557[56] ? 11'd2 : - _theResult___fst_exp__h748871 ; - assign _theResult___fst_exp__h748862 = + _theResult___fst_exp__h748867 ; + assign _theResult___fst_exp__h748858 = 11'd0 - { 5'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d13152 } ; - assign _theResult___fst_exp__h748868 = - (!_theResult____h740561[56] && !_theResult____h740561[55] && - !_theResult____h740561[54] && - !_theResult____h740561[53] && - !_theResult____h740561[52] && - !_theResult____h740561[51] && - !_theResult____h740561[50] && - !_theResult____h740561[49] && - !_theResult____h740561[48] && - !_theResult____h740561[47] && - !_theResult____h740561[46] && - !_theResult____h740561[45] && - !_theResult____h740561[44] && - !_theResult____h740561[43] && - !_theResult____h740561[42] && - !_theResult____h740561[41] && - !_theResult____h740561[40] && - !_theResult____h740561[39] && - !_theResult____h740561[38] && - !_theResult____h740561[37] && - !_theResult____h740561[36] && - !_theResult____h740561[35] && - !_theResult____h740561[34] && - !_theResult____h740561[33] && - !_theResult____h740561[32] && - !_theResult____h740561[31] && - !_theResult____h740561[30] && - !_theResult____h740561[29] && - !_theResult____h740561[28] && - !_theResult____h740561[27] && - !_theResult____h740561[26] && - !_theResult____h740561[25] && - !_theResult____h740561[24] && - !_theResult____h740561[23] && - !_theResult____h740561[22] && - !_theResult____h740561[21] && - !_theResult____h740561[20] && - !_theResult____h740561[19] && - !_theResult____h740561[18] && - !_theResult____h740561[17] && - !_theResult____h740561[16] && - !_theResult____h740561[15] && - !_theResult____h740561[14] && - !_theResult____h740561[13] && - !_theResult____h740561[12] && - !_theResult____h740561[11] && - !_theResult____h740561[10] && - !_theResult____h740561[9] && - !_theResult____h740561[8] && - !_theResult____h740561[7] && - !_theResult____h740561[6] && - !_theResult____h740561[5] && - !_theResult____h740561[4] && - !_theResult____h740561[3] && - !_theResult____h740561[2] && - !_theResult____h740561[1] && - !_theResult____h740561[0] || + assign _theResult___fst_exp__h748864 = + (!_theResult____h740557[56] && !_theResult____h740557[55] && + !_theResult____h740557[54] && + !_theResult____h740557[53] && + !_theResult____h740557[52] && + !_theResult____h740557[51] && + !_theResult____h740557[50] && + !_theResult____h740557[49] && + !_theResult____h740557[48] && + !_theResult____h740557[47] && + !_theResult____h740557[46] && + !_theResult____h740557[45] && + !_theResult____h740557[44] && + !_theResult____h740557[43] && + !_theResult____h740557[42] && + !_theResult____h740557[41] && + !_theResult____h740557[40] && + !_theResult____h740557[39] && + !_theResult____h740557[38] && + !_theResult____h740557[37] && + !_theResult____h740557[36] && + !_theResult____h740557[35] && + !_theResult____h740557[34] && + !_theResult____h740557[33] && + !_theResult____h740557[32] && + !_theResult____h740557[31] && + !_theResult____h740557[30] && + !_theResult____h740557[29] && + !_theResult____h740557[28] && + !_theResult____h740557[27] && + !_theResult____h740557[26] && + !_theResult____h740557[25] && + !_theResult____h740557[24] && + !_theResult____h740557[23] && + !_theResult____h740557[22] && + !_theResult____h740557[21] && + !_theResult____h740557[20] && + !_theResult____h740557[19] && + !_theResult____h740557[18] && + !_theResult____h740557[17] && + !_theResult____h740557[16] && + !_theResult____h740557[15] && + !_theResult____h740557[14] && + !_theResult____h740557[13] && + !_theResult____h740557[12] && + !_theResult____h740557[11] && + !_theResult____h740557[10] && + !_theResult____h740557[9] && + !_theResult____h740557[8] && + !_theResult____h740557[7] && + !_theResult____h740557[6] && + !_theResult____h740557[5] && + !_theResult____h740557[4] && + !_theResult____h740557[3] && + !_theResult____h740557[2] && + !_theResult____h740557[1] && + !_theResult____h740557[0] || !_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d13154) ? 11'd0 : - _theResult___fst_exp__h748862 ; - assign _theResult___fst_exp__h748871 = - (!_theResult____h740561[56] && _theResult____h740561[55]) ? + _theResult___fst_exp__h748858 ; + assign _theResult___fst_exp__h748867 = + (!_theResult____h740557[56] && _theResult____h740557[55]) ? 11'd1 : - _theResult___fst_exp__h748868 ; - assign _theResult___fst_exp__h749626 = + _theResult___fst_exp__h748864 ; + assign _theResult___fst_exp__h749622 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard40571_0b0_theResult___fst_exp48797_0_ETC__q224 : + CASE_guard40567_0b0_theResult___fst_exp48793_0_ETC__q224 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d13319 ; - assign _theResult___fst_exp__h749629 = - (_theResult___fst_exp__h748797 == 11'd2047) ? - _theResult___fst_exp__h748797 : - _theResult___fst_exp__h749626 ; - assign _theResult___fst_exp__h757582 = + assign _theResult___fst_exp__h749625 = + (_theResult___fst_exp__h748793 == 11'd2047) ? + _theResult___fst_exp__h748793 : + _theResult___fst_exp__h749622 ; + assign _theResult___fst_exp__h757578 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q149[10:0] == 11'd0) ? 11'd1 : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q149[10:0] ; - assign _theResult___fst_exp__h757621 = + assign _theResult___fst_exp__h757617 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q149[10:0] - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d12840 } ; - assign _theResult___fst_exp__h757627 = - (f1_exp__h719832 == 8'd0 && !f1_sfd__h719833[22] && + assign _theResult___fst_exp__h757623 = + (f1_exp__h719828 == 8'd0 && !f1_sfd__h719829[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d12813 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d13204) ? 11'd0 : - _theResult___fst_exp__h757621 ; - assign _theResult___fst_exp__h757630 = - (f1_exp__h719832 == 8'd0) ? - _theResult___fst_exp__h757627 : - _theResult___fst_exp__h757582 ; - assign _theResult___fst_exp__h758410 = + _theResult___fst_exp__h757617 ; + assign _theResult___fst_exp__h757626 = + (f1_exp__h719828 == 8'd0) ? + _theResult___fst_exp__h757623 : + _theResult___fst_exp__h757578 ; + assign _theResult___fst_exp__h758406 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard49640_0b0_theResult___fst_exp57630_0_ETC__q226 : + CASE_guard49636_0b0_theResult___fst_exp57626_0_ETC__q226 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d13350 ; - assign _theResult___fst_exp__h758413 = - (_theResult___fst_exp__h757630 == 11'd2047) ? - _theResult___fst_exp__h757630 : - _theResult___fst_exp__h758410 ; - assign _theResult___fst_exp__h758422 = - (f1_exp__h719832 == 8'd0) ? + assign _theResult___fst_exp__h758409 = + (_theResult___fst_exp__h757626 == 11'd2047) ? + _theResult___fst_exp__h757626 : + _theResult___fst_exp__h758406 ; + assign _theResult___fst_exp__h758418 = + (f1_exp__h719828 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12767 ? - _theResult___snd_fst_exp__h739981 : - _theResult___fst_exp__h724147) : + _theResult___snd_fst_exp__h739977 : + _theResult___fst_exp__h724143) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12904 ? - _theResult___snd_fst_exp__h758416 : - _theResult___fst_exp__h724147) ; - assign _theResult___fst_exp__h758425 = - (f1_exp__h719832 == 8'd0 && f1_sfd__h719833 == 23'd0) ? + _theResult___snd_fst_exp__h758412 : + _theResult___fst_exp__h724143) ; + assign _theResult___fst_exp__h758421 = + (f1_exp__h719828 == 8'd0 && f1_sfd__h719829 == 23'd0) ? 11'd0 : - _theResult___fst_exp__h758422 ; - assign _theResult___fst_exp__h763000 = + _theResult___fst_exp__h758418 ; + assign _theResult___fst_exp__h762996 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q30 ; - assign _theResult___fst_exp__h778064 = + assign _theResult___fst_exp__h778060 = 11'd897 - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14340 } ; - assign _theResult___fst_exp__h778070 = - (f2_exp__h758826 == 8'd0 && !f2_sfd__h758827[22] && + assign _theResult___fst_exp__h778066 = + (f2_exp__h758822 == 8'd0 && !f2_sfd__h758823[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d14313 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14342) ? 11'd0 : - _theResult___fst_exp__h778064 ; - assign _theResult___fst_exp__h778073 = - (f2_exp__h758826 == 8'd0) ? - _theResult___fst_exp__h778070 : + _theResult___fst_exp__h778060 ; + assign _theResult___fst_exp__h778069 = + (f2_exp__h758822 == 8'd0) ? + _theResult___fst_exp__h778066 : 11'd897 ; - assign _theResult___fst_exp__h778828 = + assign _theResult___fst_exp__h778824 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard70112_0b0_theResult___fst_exp78073_0_ETC__q196 : + CASE_guard70108_0b0_theResult___fst_exp78069_0_ETC__q196 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14761 ; - assign _theResult___fst_exp__h778831 = - (_theResult___fst_exp__h778073 == 11'd2047) ? - _theResult___fst_exp__h778073 : - _theResult___fst_exp__h778828 ; - assign _theResult___fst_exp__h787650 = - _theResult____h779414[56] ? + assign _theResult___fst_exp__h778827 = + (_theResult___fst_exp__h778069 == 11'd2047) ? + _theResult___fst_exp__h778069 : + _theResult___fst_exp__h778824 ; + assign _theResult___fst_exp__h787646 = + _theResult____h779410[56] ? 11'd2 : - _theResult___fst_exp__h787724 ; - assign _theResult___fst_exp__h787715 = + _theResult___fst_exp__h787720 ; + assign _theResult___fst_exp__h787711 = 11'd0 - { 5'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d14637 } ; - assign _theResult___fst_exp__h787721 = - (!_theResult____h779414[56] && !_theResult____h779414[55] && - !_theResult____h779414[54] && - !_theResult____h779414[53] && - !_theResult____h779414[52] && - !_theResult____h779414[51] && - !_theResult____h779414[50] && - !_theResult____h779414[49] && - !_theResult____h779414[48] && - !_theResult____h779414[47] && - !_theResult____h779414[46] && - !_theResult____h779414[45] && - !_theResult____h779414[44] && - !_theResult____h779414[43] && - !_theResult____h779414[42] && - !_theResult____h779414[41] && - !_theResult____h779414[40] && - !_theResult____h779414[39] && - !_theResult____h779414[38] && - !_theResult____h779414[37] && - !_theResult____h779414[36] && - !_theResult____h779414[35] && - !_theResult____h779414[34] && - !_theResult____h779414[33] && - !_theResult____h779414[32] && - !_theResult____h779414[31] && - !_theResult____h779414[30] && - !_theResult____h779414[29] && - !_theResult____h779414[28] && - !_theResult____h779414[27] && - !_theResult____h779414[26] && - !_theResult____h779414[25] && - !_theResult____h779414[24] && - !_theResult____h779414[23] && - !_theResult____h779414[22] && - !_theResult____h779414[21] && - !_theResult____h779414[20] && - !_theResult____h779414[19] && - !_theResult____h779414[18] && - !_theResult____h779414[17] && - !_theResult____h779414[16] && - !_theResult____h779414[15] && - !_theResult____h779414[14] && - !_theResult____h779414[13] && - !_theResult____h779414[12] && - !_theResult____h779414[11] && - !_theResult____h779414[10] && - !_theResult____h779414[9] && - !_theResult____h779414[8] && - !_theResult____h779414[7] && - !_theResult____h779414[6] && - !_theResult____h779414[5] && - !_theResult____h779414[4] && - !_theResult____h779414[3] && - !_theResult____h779414[2] && - !_theResult____h779414[1] && - !_theResult____h779414[0] || + assign _theResult___fst_exp__h787717 = + (!_theResult____h779410[56] && !_theResult____h779410[55] && + !_theResult____h779410[54] && + !_theResult____h779410[53] && + !_theResult____h779410[52] && + !_theResult____h779410[51] && + !_theResult____h779410[50] && + !_theResult____h779410[49] && + !_theResult____h779410[48] && + !_theResult____h779410[47] && + !_theResult____h779410[46] && + !_theResult____h779410[45] && + !_theResult____h779410[44] && + !_theResult____h779410[43] && + !_theResult____h779410[42] && + !_theResult____h779410[41] && + !_theResult____h779410[40] && + !_theResult____h779410[39] && + !_theResult____h779410[38] && + !_theResult____h779410[37] && + !_theResult____h779410[36] && + !_theResult____h779410[35] && + !_theResult____h779410[34] && + !_theResult____h779410[33] && + !_theResult____h779410[32] && + !_theResult____h779410[31] && + !_theResult____h779410[30] && + !_theResult____h779410[29] && + !_theResult____h779410[28] && + !_theResult____h779410[27] && + !_theResult____h779410[26] && + !_theResult____h779410[25] && + !_theResult____h779410[24] && + !_theResult____h779410[23] && + !_theResult____h779410[22] && + !_theResult____h779410[21] && + !_theResult____h779410[20] && + !_theResult____h779410[19] && + !_theResult____h779410[18] && + !_theResult____h779410[17] && + !_theResult____h779410[16] && + !_theResult____h779410[15] && + !_theResult____h779410[14] && + !_theResult____h779410[13] && + !_theResult____h779410[12] && + !_theResult____h779410[11] && + !_theResult____h779410[10] && + !_theResult____h779410[9] && + !_theResult____h779410[8] && + !_theResult____h779410[7] && + !_theResult____h779410[6] && + !_theResult____h779410[5] && + !_theResult____h779410[4] && + !_theResult____h779410[3] && + !_theResult____h779410[2] && + !_theResult____h779410[1] && + !_theResult____h779410[0] || !_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14639) ? 11'd0 : - _theResult___fst_exp__h787715 ; - assign _theResult___fst_exp__h787724 = - (!_theResult____h779414[56] && _theResult____h779414[55]) ? + _theResult___fst_exp__h787711 ; + assign _theResult___fst_exp__h787720 = + (!_theResult____h779410[56] && _theResult____h779410[55]) ? 11'd1 : - _theResult___fst_exp__h787721 ; - assign _theResult___fst_exp__h788479 = + _theResult___fst_exp__h787717 ; + assign _theResult___fst_exp__h788475 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard79424_0b0_theResult___fst_exp87650_0_ETC__q198 : + CASE_guard79420_0b0_theResult___fst_exp87646_0_ETC__q200 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14799 ; - assign _theResult___fst_exp__h788482 = - (_theResult___fst_exp__h787650 == 11'd2047) ? - _theResult___fst_exp__h787650 : - _theResult___fst_exp__h788479 ; - assign _theResult___fst_exp__h796435 = + assign _theResult___fst_exp__h788478 = + (_theResult___fst_exp__h787646 == 11'd2047) ? + _theResult___fst_exp__h787646 : + _theResult___fst_exp__h788475 ; + assign _theResult___fst_exp__h796431 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q189[10:0] == 11'd0) ? 11'd1 : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q189[10:0] ; - assign _theResult___fst_exp__h796474 = + assign _theResult___fst_exp__h796470 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q189[10:0] - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14340 } ; - assign _theResult___fst_exp__h796480 = - (f2_exp__h758826 == 8'd0 && !f2_sfd__h758827[22] && + assign _theResult___fst_exp__h796476 = + (f2_exp__h758822 == 8'd0 && !f2_sfd__h758823[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d14313 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14689) ? 11'd0 : - _theResult___fst_exp__h796474 ; - assign _theResult___fst_exp__h796483 = - (f2_exp__h758826 == 8'd0) ? - _theResult___fst_exp__h796480 : - _theResult___fst_exp__h796435 ; - assign _theResult___fst_exp__h797263 = + _theResult___fst_exp__h796470 ; + assign _theResult___fst_exp__h796479 = + (f2_exp__h758822 == 8'd0) ? + _theResult___fst_exp__h796476 : + _theResult___fst_exp__h796431 ; + assign _theResult___fst_exp__h797259 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard88493_0b0_theResult___fst_exp96483_0_ETC__q200 : + CASE_guard88489_0b0_theResult___fst_exp96479_0_ETC__q198 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14830 ; - assign _theResult___fst_exp__h797266 = - (_theResult___fst_exp__h796483 == 11'd2047) ? - _theResult___fst_exp__h796483 : - _theResult___fst_exp__h797263 ; - assign _theResult___fst_exp__h797275 = - (f2_exp__h758826 == 8'd0) ? + assign _theResult___fst_exp__h797262 = + (_theResult___fst_exp__h796479 == 11'd2047) ? + _theResult___fst_exp__h796479 : + _theResult___fst_exp__h797259 ; + assign _theResult___fst_exp__h797271 = + (f2_exp__h758822 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14267 ? - _theResult___snd_fst_exp__h778834 : - _theResult___fst_exp__h763000) : + _theResult___snd_fst_exp__h778830 : + _theResult___fst_exp__h762996) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14389 ? - _theResult___snd_fst_exp__h797269 : - _theResult___fst_exp__h763000) ; - assign _theResult___fst_exp__h797278 = - (f2_exp__h758826 == 8'd0 && f2_sfd__h758827 == 23'd0) ? + _theResult___snd_fst_exp__h797265 : + _theResult___fst_exp__h762996) ; + assign _theResult___fst_exp__h797274 = + (f2_exp__h758822 == 8'd0 && f2_sfd__h758823 == 23'd0) ? 11'd0 : - _theResult___fst_exp__h797275 ; - assign _theResult___fst_exp__h802304 = + _theResult___fst_exp__h797271 ; + assign _theResult___fst_exp__h802300 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q32 ; - assign _theResult___fst_exp__h817368 = + assign _theResult___fst_exp__h817364 = 11'd897 - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13570 } ; - assign _theResult___fst_exp__h817374 = - (f3_exp__h798130 == 8'd0 && !f3_sfd__h798131[22] && + assign _theResult___fst_exp__h817370 = + (f3_exp__h798126 == 8'd0 && !f3_sfd__h798127[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d13543 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d13572) ? 11'd0 : - _theResult___fst_exp__h817368 ; - assign _theResult___fst_exp__h817377 = - (f3_exp__h798130 == 8'd0) ? - _theResult___fst_exp__h817374 : + _theResult___fst_exp__h817364 ; + assign _theResult___fst_exp__h817373 = + (f3_exp__h798126 == 8'd0) ? + _theResult___fst_exp__h817370 : 11'd897 ; - assign _theResult___fst_exp__h818132 = + assign _theResult___fst_exp__h818128 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard09416_0b0_theResult___fst_exp17377_0_ETC__q173 : + CASE_guard09412_0b0_theResult___fst_exp17373_0_ETC__q173 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d13991 ; - assign _theResult___fst_exp__h818135 = - (_theResult___fst_exp__h817377 == 11'd2047) ? - _theResult___fst_exp__h817377 : - _theResult___fst_exp__h818132 ; - assign _theResult___fst_exp__h826954 = - _theResult____h818718[56] ? + assign _theResult___fst_exp__h818131 = + (_theResult___fst_exp__h817373 == 11'd2047) ? + _theResult___fst_exp__h817373 : + _theResult___fst_exp__h818128 ; + assign _theResult___fst_exp__h826950 = + _theResult____h818714[56] ? 11'd2 : - _theResult___fst_exp__h827028 ; - assign _theResult___fst_exp__h827019 = + _theResult___fst_exp__h827024 ; + assign _theResult___fst_exp__h827015 = 11'd0 - { 5'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d13867 } ; - assign _theResult___fst_exp__h827025 = - (!_theResult____h818718[56] && !_theResult____h818718[55] && - !_theResult____h818718[54] && - !_theResult____h818718[53] && - !_theResult____h818718[52] && - !_theResult____h818718[51] && - !_theResult____h818718[50] && - !_theResult____h818718[49] && - !_theResult____h818718[48] && - !_theResult____h818718[47] && - !_theResult____h818718[46] && - !_theResult____h818718[45] && - !_theResult____h818718[44] && - !_theResult____h818718[43] && - !_theResult____h818718[42] && - !_theResult____h818718[41] && - !_theResult____h818718[40] && - !_theResult____h818718[39] && - !_theResult____h818718[38] && - !_theResult____h818718[37] && - !_theResult____h818718[36] && - !_theResult____h818718[35] && - !_theResult____h818718[34] && - !_theResult____h818718[33] && - !_theResult____h818718[32] && - !_theResult____h818718[31] && - !_theResult____h818718[30] && - !_theResult____h818718[29] && - !_theResult____h818718[28] && - !_theResult____h818718[27] && - !_theResult____h818718[26] && - !_theResult____h818718[25] && - !_theResult____h818718[24] && - !_theResult____h818718[23] && - !_theResult____h818718[22] && - !_theResult____h818718[21] && - !_theResult____h818718[20] && - !_theResult____h818718[19] && - !_theResult____h818718[18] && - !_theResult____h818718[17] && - !_theResult____h818718[16] && - !_theResult____h818718[15] && - !_theResult____h818718[14] && - !_theResult____h818718[13] && - !_theResult____h818718[12] && - !_theResult____h818718[11] && - !_theResult____h818718[10] && - !_theResult____h818718[9] && - !_theResult____h818718[8] && - !_theResult____h818718[7] && - !_theResult____h818718[6] && - !_theResult____h818718[5] && - !_theResult____h818718[4] && - !_theResult____h818718[3] && - !_theResult____h818718[2] && - !_theResult____h818718[1] && - !_theResult____h818718[0] || + assign _theResult___fst_exp__h827021 = + (!_theResult____h818714[56] && !_theResult____h818714[55] && + !_theResult____h818714[54] && + !_theResult____h818714[53] && + !_theResult____h818714[52] && + !_theResult____h818714[51] && + !_theResult____h818714[50] && + !_theResult____h818714[49] && + !_theResult____h818714[48] && + !_theResult____h818714[47] && + !_theResult____h818714[46] && + !_theResult____h818714[45] && + !_theResult____h818714[44] && + !_theResult____h818714[43] && + !_theResult____h818714[42] && + !_theResult____h818714[41] && + !_theResult____h818714[40] && + !_theResult____h818714[39] && + !_theResult____h818714[38] && + !_theResult____h818714[37] && + !_theResult____h818714[36] && + !_theResult____h818714[35] && + !_theResult____h818714[34] && + !_theResult____h818714[33] && + !_theResult____h818714[32] && + !_theResult____h818714[31] && + !_theResult____h818714[30] && + !_theResult____h818714[29] && + !_theResult____h818714[28] && + !_theResult____h818714[27] && + !_theResult____h818714[26] && + !_theResult____h818714[25] && + !_theResult____h818714[24] && + !_theResult____h818714[23] && + !_theResult____h818714[22] && + !_theResult____h818714[21] && + !_theResult____h818714[20] && + !_theResult____h818714[19] && + !_theResult____h818714[18] && + !_theResult____h818714[17] && + !_theResult____h818714[16] && + !_theResult____h818714[15] && + !_theResult____h818714[14] && + !_theResult____h818714[13] && + !_theResult____h818714[12] && + !_theResult____h818714[11] && + !_theResult____h818714[10] && + !_theResult____h818714[9] && + !_theResult____h818714[8] && + !_theResult____h818714[7] && + !_theResult____h818714[6] && + !_theResult____h818714[5] && + !_theResult____h818714[4] && + !_theResult____h818714[3] && + !_theResult____h818714[2] && + !_theResult____h818714[1] && + !_theResult____h818714[0] || !_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d13869) ? 11'd0 : - _theResult___fst_exp__h827019 ; - assign _theResult___fst_exp__h827028 = - (!_theResult____h818718[56] && _theResult____h818718[55]) ? + _theResult___fst_exp__h827015 ; + assign _theResult___fst_exp__h827024 = + (!_theResult____h818714[56] && _theResult____h818714[55]) ? 11'd1 : - _theResult___fst_exp__h827025 ; - assign _theResult___fst_exp__h827783 = + _theResult___fst_exp__h827021 ; + assign _theResult___fst_exp__h827779 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard18728_0b0_theResult___fst_exp26954_0_ETC__q202 : + CASE_guard18724_0b0_theResult___fst_exp26950_0_ETC__q202 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14029 ; - assign _theResult___fst_exp__h827786 = - (_theResult___fst_exp__h826954 == 11'd2047) ? - _theResult___fst_exp__h826954 : - _theResult___fst_exp__h827783 ; - assign _theResult___fst_exp__h835739 = + assign _theResult___fst_exp__h827782 = + (_theResult___fst_exp__h826950 == 11'd2047) ? + _theResult___fst_exp__h826950 : + _theResult___fst_exp__h827779 ; + assign _theResult___fst_exp__h835735 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q166[10:0] == 11'd0) ? 11'd1 : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q166[10:0] ; - assign _theResult___fst_exp__h835778 = + assign _theResult___fst_exp__h835774 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q166[10:0] - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13570 } ; - assign _theResult___fst_exp__h835784 = - (f3_exp__h798130 == 8'd0 && !f3_sfd__h798131[22] && + assign _theResult___fst_exp__h835780 = + (f3_exp__h798126 == 8'd0 && !f3_sfd__h798127[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d13543 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d13919) ? 11'd0 : - _theResult___fst_exp__h835778 ; - assign _theResult___fst_exp__h835787 = - (f3_exp__h798130 == 8'd0) ? - _theResult___fst_exp__h835784 : - _theResult___fst_exp__h835739 ; - assign _theResult___fst_exp__h836567 = + _theResult___fst_exp__h835774 ; + assign _theResult___fst_exp__h835783 = + (f3_exp__h798126 == 8'd0) ? + _theResult___fst_exp__h835780 : + _theResult___fst_exp__h835735 ; + assign _theResult___fst_exp__h836563 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard27797_0b0_theResult___fst_exp35787_0_ETC__q204 : + CASE_guard27793_0b0_theResult___fst_exp35783_0_ETC__q204 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14060 ; - assign _theResult___fst_exp__h836570 = - (_theResult___fst_exp__h835787 == 11'd2047) ? - _theResult___fst_exp__h835787 : - _theResult___fst_exp__h836567 ; - assign _theResult___fst_exp__h836579 = - (f3_exp__h798130 == 8'd0) ? + assign _theResult___fst_exp__h836566 = + (_theResult___fst_exp__h835783 == 11'd2047) ? + _theResult___fst_exp__h835783 : + _theResult___fst_exp__h836563 ; + assign _theResult___fst_exp__h836575 = + (f3_exp__h798126 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13497 ? - _theResult___snd_fst_exp__h818138 : - _theResult___fst_exp__h802304) : + _theResult___snd_fst_exp__h818134 : + _theResult___fst_exp__h802300) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13619 ? - _theResult___snd_fst_exp__h836573 : - _theResult___fst_exp__h802304) ; - assign _theResult___fst_exp__h836582 = - (f3_exp__h798130 == 8'd0 && f3_sfd__h798131 == 23'd0) ? + _theResult___snd_fst_exp__h836569 : + _theResult___fst_exp__h802300) ; + assign _theResult___fst_exp__h836578 = + (f3_exp__h798126 == 8'd0 && f3_sfd__h798127 == 23'd0) ? 11'd0 : - _theResult___fst_exp__h836579 ; - assign _theResult___fst_sfd__h589588 = - (_theResult___fst_exp__h588990 == 8'd255) ? - sfdin__h588984[56:34] : - _theResult___fst_sfd__h589585 ; - assign _theResult___fst_sfd__h598170 = - (_theResult___fst_exp__h597646 == 8'd255) ? - _theResult___snd__h597597[56:34] : - _theResult___fst_sfd__h598167 ; - assign _theResult___fst_sfd__h607354 = - (_theResult___fst_exp__h606756 == 8'd255) ? - sfdin__h606750[56:34] : - _theResult___fst_sfd__h607351 ; - assign _theResult___fst_sfd__h615990 = - (_theResult___fst_exp__h615441 == 8'd255) ? - _theResult___snd__h615387[56:34] : - _theResult___fst_sfd__h615987 ; - assign _theResult___fst_sfd__h615999 = + _theResult___fst_exp__h836575 ; + assign _theResult___fst_sfd__h589585 = + (_theResult___fst_exp__h588987 == 8'd255) ? + sfdin__h588981[56:34] : + _theResult___fst_sfd__h589582 ; + assign _theResult___fst_sfd__h598167 = + (_theResult___fst_exp__h597643 == 8'd255) ? + _theResult___snd__h597594[56:34] : + _theResult___fst_sfd__h598164 ; + assign _theResult___fst_sfd__h607351 = + (_theResult___fst_exp__h606753 == 8'd255) ? + sfdin__h606747[56:34] : + _theResult___fst_sfd__h607348 ; + assign _theResult___fst_sfd__h615987 = + (_theResult___fst_exp__h615438 == 8'd255) ? + _theResult___snd__h615384[56:34] : + _theResult___fst_sfd__h615984 ; + assign _theResult___fst_sfd__h615996 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8226 ? - _theResult___snd_fst_sfd__h598173 : - _theResult___fst_sfd__h580862) : + _theResult___snd_fst_sfd__h598170 : + _theResult___fst_sfd__h580859) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8766 ? - _theResult___snd_fst_sfd__h615993 : - _theResult___fst_sfd__h580862) ; - assign _theResult___fst_sfd__h616005 = + _theResult___snd_fst_sfd__h615990 : + _theResult___fst_sfd__h580859) ; + assign _theResult___fst_sfd__h616002 = ((coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == @@ -31669,33 +31694,33 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == 52'd0) ? 23'd0 : - _theResult___fst_sfd__h615999 ; - assign _theResult___fst_sfd__h635337 = - (_theResult___fst_exp__h634739 == 8'd255) ? - sfdin__h634733[56:34] : - _theResult___fst_sfd__h635334 ; - assign _theResult___fst_sfd__h643919 = - (_theResult___fst_exp__h643395 == 8'd255) ? - _theResult___snd__h643346[56:34] : - _theResult___fst_sfd__h643916 ; - assign _theResult___fst_sfd__h653103 = - (_theResult___fst_exp__h652505 == 8'd255) ? - sfdin__h652499[56:34] : - _theResult___fst_sfd__h653100 ; - assign _theResult___fst_sfd__h661739 = - (_theResult___fst_exp__h661190 == 8'd255) ? - _theResult___snd__h661136[56:34] : - _theResult___fst_sfd__h661736 ; - assign _theResult___fst_sfd__h661748 = + _theResult___fst_sfd__h615996 ; + assign _theResult___fst_sfd__h635334 = + (_theResult___fst_exp__h634736 == 8'd255) ? + sfdin__h634730[56:34] : + _theResult___fst_sfd__h635331 ; + assign _theResult___fst_sfd__h643916 = + (_theResult___fst_exp__h643392 == 8'd255) ? + _theResult___snd__h643343[56:34] : + _theResult___fst_sfd__h643913 ; + assign _theResult___fst_sfd__h653100 = + (_theResult___fst_exp__h652502 == 8'd255) ? + sfdin__h652496[56:34] : + _theResult___fst_sfd__h653097 ; + assign _theResult___fst_sfd__h661736 = + (_theResult___fst_exp__h661187 == 8'd255) ? + _theResult___snd__h661133[56:34] : + _theResult___fst_sfd__h661733 ; + assign _theResult___fst_sfd__h661745 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9623 ? - _theResult___snd_fst_sfd__h643922 : - _theResult___fst_sfd__h626613) : + _theResult___snd_fst_sfd__h643919 : + _theResult___fst_sfd__h626610) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10163 ? - _theResult___snd_fst_sfd__h661742 : - _theResult___fst_sfd__h626613) ; - assign _theResult___fst_sfd__h661754 = + _theResult___snd_fst_sfd__h661739 : + _theResult___fst_sfd__h626610) ; + assign _theResult___fst_sfd__h661751 = ((coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == @@ -31703,33 +31728,33 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == 52'd0) ? 23'd0 : - _theResult___fst_sfd__h661748 ; - assign _theResult___fst_sfd__h681084 = - (_theResult___fst_exp__h680486 == 8'd255) ? - sfdin__h680480[56:34] : - _theResult___fst_sfd__h681081 ; - assign _theResult___fst_sfd__h689666 = - (_theResult___fst_exp__h689142 == 8'd255) ? - _theResult___snd__h689093[56:34] : - _theResult___fst_sfd__h689663 ; - assign _theResult___fst_sfd__h698850 = - (_theResult___fst_exp__h698252 == 8'd255) ? - sfdin__h698246[56:34] : - _theResult___fst_sfd__h698847 ; - assign _theResult___fst_sfd__h707486 = - (_theResult___fst_exp__h706937 == 8'd255) ? - _theResult___snd__h706883[56:34] : - _theResult___fst_sfd__h707483 ; - assign _theResult___fst_sfd__h707495 = + _theResult___fst_sfd__h661745 ; + assign _theResult___fst_sfd__h681081 = + (_theResult___fst_exp__h680483 == 8'd255) ? + sfdin__h680477[56:34] : + _theResult___fst_sfd__h681078 ; + assign _theResult___fst_sfd__h689663 = + (_theResult___fst_exp__h689139 == 8'd255) ? + _theResult___snd__h689090[56:34] : + _theResult___fst_sfd__h689660 ; + assign _theResult___fst_sfd__h698847 = + (_theResult___fst_exp__h698249 == 8'd255) ? + sfdin__h698243[56:34] : + _theResult___fst_sfd__h698844 ; + assign _theResult___fst_sfd__h707483 = + (_theResult___fst_exp__h706934 == 8'd255) ? + _theResult___snd__h706880[56:34] : + _theResult___fst_sfd__h707480 ; + assign _theResult___fst_sfd__h707492 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d11020 ? - _theResult___snd_fst_sfd__h689669 : - _theResult___fst_sfd__h672360) : + _theResult___snd_fst_sfd__h689666 : + _theResult___fst_sfd__h672357) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11560 ? - _theResult___snd_fst_sfd__h707489 : - _theResult___fst_sfd__h672360) ; - assign _theResult___fst_sfd__h707501 = + _theResult___snd_fst_sfd__h707486 : + _theResult___fst_sfd__h672357) ; + assign _theResult___fst_sfd__h707498 = ((coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == @@ -31737,1466 +31762,1466 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == 52'd0) ? 23'd0 : - _theResult___fst_sfd__h707495 ; - assign _theResult___fst_sfd__h724148 = + _theResult___fst_sfd__h707492 ; + assign _theResult___fst_sfd__h724144 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q29 ; - assign _theResult___fst_sfd__h739976 = + assign _theResult___fst_sfd__h739972 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard31259_0b0_theResult___snd39171_BITS__ETC__q230 : + CASE_guard31255_0b0_theResult___snd39167_BITS__ETC__q228 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d13376 ; - assign _theResult___fst_sfd__h739979 = - (_theResult___fst_exp__h739220 == 11'd2047) ? - _theResult___snd__h739171[56:5] : - _theResult___fst_sfd__h739976 ; - assign _theResult___fst_sfd__h749627 = + assign _theResult___fst_sfd__h739975 = + (_theResult___fst_exp__h739216 == 11'd2047) ? + _theResult___snd__h739167[56:5] : + _theResult___fst_sfd__h739972 ; + assign _theResult___fst_sfd__h749623 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard40571_0b0_sfdin48791_BITS_56_TO_5_0b_ETC__q228 : + CASE_guard40567_0b0_sfdin48787_BITS_56_TO_5_0b_ETC__q230 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d13403 ; - assign _theResult___fst_sfd__h749630 = - (_theResult___fst_exp__h748797 == 11'd2047) ? - sfdin__h748791[56:5] : - _theResult___fst_sfd__h749627 ; - assign _theResult___fst_sfd__h758411 = + assign _theResult___fst_sfd__h749626 = + (_theResult___fst_exp__h748793 == 11'd2047) ? + sfdin__h748787[56:5] : + _theResult___fst_sfd__h749623 ; + assign _theResult___fst_sfd__h758407 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard49640_0b0_theResult___snd57576_BITS__ETC__q232 : + CASE_guard49636_0b0_theResult___snd57572_BITS__ETC__q232 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d13422 ; - assign _theResult___fst_sfd__h758414 = - (_theResult___fst_exp__h757630 == 11'd2047) ? - _theResult___snd__h757576[56:5] : - _theResult___fst_sfd__h758411 ; - assign _theResult___fst_sfd__h758423 = - (f1_exp__h719832 == 8'd0) ? + assign _theResult___fst_sfd__h758410 = + (_theResult___fst_exp__h757626 == 11'd2047) ? + _theResult___snd__h757572[56:5] : + _theResult___fst_sfd__h758407 ; + assign _theResult___fst_sfd__h758419 = + (f1_exp__h719828 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12767 ? - _theResult___snd_fst_sfd__h739982 : - _theResult___fst_sfd__h724148) : + _theResult___snd_fst_sfd__h739978 : + _theResult___fst_sfd__h724144) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12904 ? - _theResult___snd_fst_sfd__h758417 : - _theResult___fst_sfd__h724148) ; - assign _theResult___fst_sfd__h758429 = - ((f1_exp__h719832 == 8'd255 || f1_exp__h719832 == 8'd0) && - f1_sfd__h719833 == 23'd0) ? + _theResult___snd_fst_sfd__h758413 : + _theResult___fst_sfd__h724144) ; + assign _theResult___fst_sfd__h758425 = + ((f1_exp__h719828 == 8'd255 || f1_exp__h719828 == 8'd0) && + f1_sfd__h719829 == 23'd0) ? 52'd0 : - _theResult___fst_sfd__h758423 ; - assign _theResult___fst_sfd__h763001 = + _theResult___fst_sfd__h758419 ; + assign _theResult___fst_sfd__h762997 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q31 ; - assign _theResult___fst_sfd__h778829 = + assign _theResult___fst_sfd__h778825 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard70112_0b0_theResult___snd78024_BITS__ETC__q218 : + CASE_guard70108_0b0_theResult___snd78020_BITS__ETC__q218 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14856 ; - assign _theResult___fst_sfd__h778832 = - (_theResult___fst_exp__h778073 == 11'd2047) ? - _theResult___snd__h778024[56:5] : - _theResult___fst_sfd__h778829 ; - assign _theResult___fst_sfd__h788480 = + assign _theResult___fst_sfd__h778828 = + (_theResult___fst_exp__h778069 == 11'd2047) ? + _theResult___snd__h778020[56:5] : + _theResult___fst_sfd__h778825 ; + assign _theResult___fst_sfd__h788476 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard79424_0b0_sfdin87644_BITS_56_TO_5_0b_ETC__q222 : + CASE_guard79420_0b0_sfdin87640_BITS_56_TO_5_0b_ETC__q220 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14882 ; - assign _theResult___fst_sfd__h788483 = - (_theResult___fst_exp__h787650 == 11'd2047) ? - sfdin__h787644[56:5] : - _theResult___fst_sfd__h788480 ; - assign _theResult___fst_sfd__h797264 = + assign _theResult___fst_sfd__h788479 = + (_theResult___fst_exp__h787646 == 11'd2047) ? + sfdin__h787640[56:5] : + _theResult___fst_sfd__h788476 ; + assign _theResult___fst_sfd__h797260 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard88493_0b0_theResult___snd96429_BITS__ETC__q220 : + CASE_guard88489_0b0_theResult___snd96425_BITS__ETC__q222 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14901 ; - assign _theResult___fst_sfd__h797267 = - (_theResult___fst_exp__h796483 == 11'd2047) ? - _theResult___snd__h796429[56:5] : - _theResult___fst_sfd__h797264 ; - assign _theResult___fst_sfd__h797276 = - (f2_exp__h758826 == 8'd0) ? + assign _theResult___fst_sfd__h797263 = + (_theResult___fst_exp__h796479 == 11'd2047) ? + _theResult___snd__h796425[56:5] : + _theResult___fst_sfd__h797260 ; + assign _theResult___fst_sfd__h797272 = + (f2_exp__h758822 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14267 ? - _theResult___snd_fst_sfd__h778835 : - _theResult___fst_sfd__h763001) : + _theResult___snd_fst_sfd__h778831 : + _theResult___fst_sfd__h762997) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14389 ? - _theResult___snd_fst_sfd__h797270 : - _theResult___fst_sfd__h763001) ; - assign _theResult___fst_sfd__h797282 = - ((f2_exp__h758826 == 8'd255 || f2_exp__h758826 == 8'd0) && - f2_sfd__h758827 == 23'd0) ? + _theResult___snd_fst_sfd__h797266 : + _theResult___fst_sfd__h762997) ; + assign _theResult___fst_sfd__h797278 = + ((f2_exp__h758822 == 8'd255 || f2_exp__h758822 == 8'd0) && + f2_sfd__h758823 == 23'd0) ? 52'd0 : - _theResult___fst_sfd__h797276 ; - assign _theResult___fst_sfd__h802305 = + _theResult___fst_sfd__h797272 ; + assign _theResult___fst_sfd__h802301 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q33 ; - assign _theResult___fst_sfd__h818133 = + assign _theResult___fst_sfd__h818129 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard09416_0b0_theResult___snd17328_BITS__ETC__q234 : + CASE_guard09412_0b0_theResult___snd17324_BITS__ETC__q234 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14086 ; - assign _theResult___fst_sfd__h818136 = - (_theResult___fst_exp__h817377 == 11'd2047) ? - _theResult___snd__h817328[56:5] : - _theResult___fst_sfd__h818133 ; - assign _theResult___fst_sfd__h827784 = + assign _theResult___fst_sfd__h818132 = + (_theResult___fst_exp__h817373 == 11'd2047) ? + _theResult___snd__h817324[56:5] : + _theResult___fst_sfd__h818129 ; + assign _theResult___fst_sfd__h827780 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard18728_0b0_sfdin26948_BITS_56_TO_5_0b_ETC__q236 : + CASE_guard18724_0b0_sfdin26944_BITS_56_TO_5_0b_ETC__q236 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14112 ; - assign _theResult___fst_sfd__h827787 = - (_theResult___fst_exp__h826954 == 11'd2047) ? - sfdin__h826948[56:5] : - _theResult___fst_sfd__h827784 ; - assign _theResult___fst_sfd__h836568 = + assign _theResult___fst_sfd__h827783 = + (_theResult___fst_exp__h826950 == 11'd2047) ? + sfdin__h826944[56:5] : + _theResult___fst_sfd__h827780 ; + assign _theResult___fst_sfd__h836564 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard27797_0b0_theResult___snd35733_BITS__ETC__q238 : + CASE_guard27793_0b0_theResult___snd35729_BITS__ETC__q238 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14131 ; - assign _theResult___fst_sfd__h836571 = - (_theResult___fst_exp__h835787 == 11'd2047) ? - _theResult___snd__h835733[56:5] : - _theResult___fst_sfd__h836568 ; - assign _theResult___fst_sfd__h836580 = - (f3_exp__h798130 == 8'd0) ? + assign _theResult___fst_sfd__h836567 = + (_theResult___fst_exp__h835783 == 11'd2047) ? + _theResult___snd__h835729[56:5] : + _theResult___fst_sfd__h836564 ; + assign _theResult___fst_sfd__h836576 = + (f3_exp__h798126 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13497 ? - _theResult___snd_fst_sfd__h818139 : - _theResult___fst_sfd__h802305) : + _theResult___snd_fst_sfd__h818135 : + _theResult___fst_sfd__h802301) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13619 ? - _theResult___snd_fst_sfd__h836574 : - _theResult___fst_sfd__h802305) ; - assign _theResult___fst_sfd__h836586 = - ((f3_exp__h798130 == 8'd255 || f3_exp__h798130 == 8'd0) && - f3_sfd__h798131 == 23'd0) ? + _theResult___snd_fst_sfd__h836570 : + _theResult___fst_sfd__h802301) ; + assign _theResult___fst_sfd__h836582 = + ((f3_exp__h798126 == 8'd255 || f3_exp__h798126 == 8'd0) && + f3_sfd__h798127 == 23'd0) ? 52'd0 : - _theResult___fst_sfd__h836580 ; - assign _theResult___sfd__h589507 = - sfd__h589082[24] ? - ((_theResult___fst_exp__h588990 == 8'd254) ? + _theResult___fst_sfd__h836576 ; + assign _theResult___sfd__h589504 = + sfd__h589079[24] ? + ((_theResult___fst_exp__h588987 == 8'd254) ? 23'd0 : - sfd__h589082[23:1]) : - sfd__h589082[22:0] ; - assign _theResult___sfd__h598089 = - sfd__h597664[24] ? - ((_theResult___fst_exp__h597646 == 8'd254) ? + sfd__h589079[23:1]) : + sfd__h589079[22:0] ; + assign _theResult___sfd__h598086 = + sfd__h597661[24] ? + ((_theResult___fst_exp__h597643 == 8'd254) ? 23'd0 : - sfd__h597664[23:1]) : - sfd__h597664[22:0] ; - assign _theResult___sfd__h607273 = - sfd__h606848[24] ? - ((_theResult___fst_exp__h606756 == 8'd254) ? + sfd__h597661[23:1]) : + sfd__h597661[22:0] ; + assign _theResult___sfd__h607270 = + sfd__h606845[24] ? + ((_theResult___fst_exp__h606753 == 8'd254) ? 23'd0 : - sfd__h606848[23:1]) : - sfd__h606848[22:0] ; - assign _theResult___sfd__h615909 = - sfd__h615460[24] ? - ((_theResult___fst_exp__h615441 == 8'd254) ? + sfd__h606845[23:1]) : + sfd__h606845[22:0] ; + assign _theResult___sfd__h615906 = + sfd__h615457[24] ? + ((_theResult___fst_exp__h615438 == 8'd254) ? 23'd0 : - sfd__h615460[23:1]) : - sfd__h615460[22:0] ; - assign _theResult___sfd__h616011 = + sfd__h615457[23:1]) : + sfd__h615457[22:0] ; + assign _theResult___sfd__h616008 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h573224 : - _theResult___fst_sfd__h616005 ; - assign _theResult___sfd__h635256 = - sfd__h634831[24] ? - ((_theResult___fst_exp__h634739 == 8'd254) ? + _theResult___snd_fst_sfd__h573221 : + _theResult___fst_sfd__h616002 ; + assign _theResult___sfd__h635253 = + sfd__h634828[24] ? + ((_theResult___fst_exp__h634736 == 8'd254) ? 23'd0 : - sfd__h634831[23:1]) : - sfd__h634831[22:0] ; - assign _theResult___sfd__h643838 = - sfd__h643413[24] ? - ((_theResult___fst_exp__h643395 == 8'd254) ? + sfd__h634828[23:1]) : + sfd__h634828[22:0] ; + assign _theResult___sfd__h643835 = + sfd__h643410[24] ? + ((_theResult___fst_exp__h643392 == 8'd254) ? 23'd0 : - sfd__h643413[23:1]) : - sfd__h643413[22:0] ; - assign _theResult___sfd__h653022 = - sfd__h652597[24] ? - ((_theResult___fst_exp__h652505 == 8'd254) ? + sfd__h643410[23:1]) : + sfd__h643410[22:0] ; + assign _theResult___sfd__h653019 = + sfd__h652594[24] ? + ((_theResult___fst_exp__h652502 == 8'd254) ? 23'd0 : - sfd__h652597[23:1]) : - sfd__h652597[22:0] ; - assign _theResult___sfd__h661658 = - sfd__h661209[24] ? - ((_theResult___fst_exp__h661190 == 8'd254) ? + sfd__h652594[23:1]) : + sfd__h652594[22:0] ; + assign _theResult___sfd__h661655 = + sfd__h661206[24] ? + ((_theResult___fst_exp__h661187 == 8'd254) ? 23'd0 : - sfd__h661209[23:1]) : - sfd__h661209[22:0] ; - assign _theResult___sfd__h661760 = + sfd__h661206[23:1]) : + sfd__h661206[22:0] ; + assign _theResult___sfd__h661757 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h618978 : - _theResult___fst_sfd__h661754 ; - assign _theResult___sfd__h681003 = - sfd__h680578[24] ? - ((_theResult___fst_exp__h680486 == 8'd254) ? + _theResult___snd_fst_sfd__h618975 : + _theResult___fst_sfd__h661751 ; + assign _theResult___sfd__h681000 = + sfd__h680575[24] ? + ((_theResult___fst_exp__h680483 == 8'd254) ? 23'd0 : - sfd__h680578[23:1]) : - sfd__h680578[22:0] ; - assign _theResult___sfd__h689585 = - sfd__h689160[24] ? - ((_theResult___fst_exp__h689142 == 8'd254) ? + sfd__h680575[23:1]) : + sfd__h680575[22:0] ; + assign _theResult___sfd__h689582 = + sfd__h689157[24] ? + ((_theResult___fst_exp__h689139 == 8'd254) ? 23'd0 : - sfd__h689160[23:1]) : - sfd__h689160[22:0] ; - assign _theResult___sfd__h698769 = - sfd__h698344[24] ? - ((_theResult___fst_exp__h698252 == 8'd254) ? + sfd__h689157[23:1]) : + sfd__h689157[22:0] ; + assign _theResult___sfd__h698766 = + sfd__h698341[24] ? + ((_theResult___fst_exp__h698249 == 8'd254) ? 23'd0 : - sfd__h698344[23:1]) : - sfd__h698344[22:0] ; - assign _theResult___sfd__h707405 = - sfd__h706956[24] ? - ((_theResult___fst_exp__h706937 == 8'd254) ? + sfd__h698341[23:1]) : + sfd__h698341[22:0] ; + assign _theResult___sfd__h707402 = + sfd__h706953[24] ? + ((_theResult___fst_exp__h706934 == 8'd254) ? 23'd0 : - sfd__h706956[23:1]) : - sfd__h706956[22:0] ; - assign _theResult___sfd__h707507 = + sfd__h706953[23:1]) : + sfd__h706953[22:0] ; + assign _theResult___sfd__h707504 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h664725 : - _theResult___fst_sfd__h707501 ; - assign _theResult___sfd__h739876 = - sfd__h739238[53] ? - ((_theResult___fst_exp__h739220 == 11'd2046) ? + _theResult___snd_fst_sfd__h664722 : + _theResult___fst_sfd__h707498 ; + assign _theResult___sfd__h739872 = + sfd__h739234[53] ? + ((_theResult___fst_exp__h739216 == 11'd2046) ? 52'd0 : - sfd__h739238[52:1]) : - sfd__h739238[51:0] ; - assign _theResult___sfd__h749527 = - sfd__h748889[53] ? - ((_theResult___fst_exp__h748797 == 11'd2046) ? + sfd__h739234[52:1]) : + sfd__h739234[51:0] ; + assign _theResult___sfd__h749523 = + sfd__h748885[53] ? + ((_theResult___fst_exp__h748793 == 11'd2046) ? 52'd0 : - sfd__h748889[52:1]) : - sfd__h748889[51:0] ; - assign _theResult___sfd__h758311 = - sfd__h757649[53] ? - ((_theResult___fst_exp__h757630 == 11'd2046) ? + sfd__h748885[52:1]) : + sfd__h748885[51:0] ; + assign _theResult___sfd__h758307 = + sfd__h757645[53] ? + ((_theResult___fst_exp__h757626 == 11'd2046) ? 52'd0 : - sfd__h757649[52:1]) : - sfd__h757649[51:0] ; - assign _theResult___sfd__h778729 = - sfd__h778091[53] ? - ((_theResult___fst_exp__h778073 == 11'd2046) ? + sfd__h757645[52:1]) : + sfd__h757645[51:0] ; + assign _theResult___sfd__h778725 = + sfd__h778087[53] ? + ((_theResult___fst_exp__h778069 == 11'd2046) ? 52'd0 : - sfd__h778091[52:1]) : - sfd__h778091[51:0] ; - assign _theResult___sfd__h788380 = - sfd__h787742[53] ? - ((_theResult___fst_exp__h787650 == 11'd2046) ? + sfd__h778087[52:1]) : + sfd__h778087[51:0] ; + assign _theResult___sfd__h788376 = + sfd__h787738[53] ? + ((_theResult___fst_exp__h787646 == 11'd2046) ? 52'd0 : - sfd__h787742[52:1]) : - sfd__h787742[51:0] ; - assign _theResult___sfd__h797164 = - sfd__h796502[53] ? - ((_theResult___fst_exp__h796483 == 11'd2046) ? + sfd__h787738[52:1]) : + sfd__h787738[51:0] ; + assign _theResult___sfd__h797160 = + sfd__h796498[53] ? + ((_theResult___fst_exp__h796479 == 11'd2046) ? 52'd0 : - sfd__h796502[52:1]) : - sfd__h796502[51:0] ; - assign _theResult___sfd__h818033 = - sfd__h817395[53] ? - ((_theResult___fst_exp__h817377 == 11'd2046) ? + sfd__h796498[52:1]) : + sfd__h796498[51:0] ; + assign _theResult___sfd__h818029 = + sfd__h817391[53] ? + ((_theResult___fst_exp__h817373 == 11'd2046) ? 52'd0 : - sfd__h817395[52:1]) : - sfd__h817395[51:0] ; - assign _theResult___sfd__h827684 = - sfd__h827046[53] ? - ((_theResult___fst_exp__h826954 == 11'd2046) ? + sfd__h817391[52:1]) : + sfd__h817391[51:0] ; + assign _theResult___sfd__h827680 = + sfd__h827042[53] ? + ((_theResult___fst_exp__h826950 == 11'd2046) ? 52'd0 : - sfd__h827046[52:1]) : - sfd__h827046[51:0] ; - assign _theResult___sfd__h836468 = - sfd__h835806[53] ? - ((_theResult___fst_exp__h835787 == 11'd2046) ? + sfd__h827042[52:1]) : + sfd__h827042[51:0] ; + assign _theResult___sfd__h836464 = + sfd__h835802[53] ? + ((_theResult___fst_exp__h835783 == 11'd2046) ? 52'd0 : - sfd__h835806[52:1]) : - sfd__h835806[51:0] ; - assign _theResult___snd__h589001 = { _theResult____h580879[55:0], 1'd0 } ; - assign _theResult___snd__h589012 = - (!_theResult____h580879[56] && _theResult____h580879[55]) ? - _theResult___snd__h589014 : - _theResult___snd__h589024 ; - assign _theResult___snd__h589014 = { _theResult____h580879[54:0], 2'd0 } ; - assign _theResult___snd__h589024 = - (!_theResult____h580879[56] && !_theResult____h580879[55] && - !_theResult____h580879[54] && - !_theResult____h580879[53] && - !_theResult____h580879[52] && - !_theResult____h580879[51] && - !_theResult____h580879[50] && - !_theResult____h580879[49] && - !_theResult____h580879[48] && - !_theResult____h580879[47] && - !_theResult____h580879[46] && - !_theResult____h580879[45] && - !_theResult____h580879[44] && - !_theResult____h580879[43] && - !_theResult____h580879[42] && - !_theResult____h580879[41] && - !_theResult____h580879[40] && - !_theResult____h580879[39] && - !_theResult____h580879[38] && - !_theResult____h580879[37] && - !_theResult____h580879[36] && - !_theResult____h580879[35] && - !_theResult____h580879[34] && - !_theResult____h580879[33] && - !_theResult____h580879[32] && - !_theResult____h580879[31] && - !_theResult____h580879[30] && - !_theResult____h580879[29] && - !_theResult____h580879[28] && - !_theResult____h580879[27] && - !_theResult____h580879[26] && - !_theResult____h580879[25] && - !_theResult____h580879[24] && - !_theResult____h580879[23] && - !_theResult____h580879[22] && - !_theResult____h580879[21] && - !_theResult____h580879[20] && - !_theResult____h580879[19] && - !_theResult____h580879[18] && - !_theResult____h580879[17] && - !_theResult____h580879[16] && - !_theResult____h580879[15] && - !_theResult____h580879[14] && - !_theResult____h580879[13] && - !_theResult____h580879[12] && - !_theResult____h580879[11] && - !_theResult____h580879[10] && - !_theResult____h580879[9] && - !_theResult____h580879[8] && - !_theResult____h580879[7] && - !_theResult____h580879[6] && - !_theResult____h580879[5] && - !_theResult____h580879[4] && - !_theResult____h580879[3] && - !_theResult____h580879[2] && - !_theResult____h580879[1] && - !_theResult____h580879[0]) ? - _theResult____h580879 : - _theResult___snd__h589030 ; - assign _theResult___snd__h589030 = - { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q43[54:0], + sfd__h835802[52:1]) : + sfd__h835802[51:0] ; + assign _theResult___snd__h588998 = { _theResult____h580876[55:0], 1'd0 } ; + assign _theResult___snd__h589009 = + (!_theResult____h580876[56] && _theResult____h580876[55]) ? + _theResult___snd__h589011 : + _theResult___snd__h589021 ; + assign _theResult___snd__h589011 = { _theResult____h580876[54:0], 2'd0 } ; + assign _theResult___snd__h589021 = + (!_theResult____h580876[56] && !_theResult____h580876[55] && + !_theResult____h580876[54] && + !_theResult____h580876[53] && + !_theResult____h580876[52] && + !_theResult____h580876[51] && + !_theResult____h580876[50] && + !_theResult____h580876[49] && + !_theResult____h580876[48] && + !_theResult____h580876[47] && + !_theResult____h580876[46] && + !_theResult____h580876[45] && + !_theResult____h580876[44] && + !_theResult____h580876[43] && + !_theResult____h580876[42] && + !_theResult____h580876[41] && + !_theResult____h580876[40] && + !_theResult____h580876[39] && + !_theResult____h580876[38] && + !_theResult____h580876[37] && + !_theResult____h580876[36] && + !_theResult____h580876[35] && + !_theResult____h580876[34] && + !_theResult____h580876[33] && + !_theResult____h580876[32] && + !_theResult____h580876[31] && + !_theResult____h580876[30] && + !_theResult____h580876[29] && + !_theResult____h580876[28] && + !_theResult____h580876[27] && + !_theResult____h580876[26] && + !_theResult____h580876[25] && + !_theResult____h580876[24] && + !_theResult____h580876[23] && + !_theResult____h580876[22] && + !_theResult____h580876[21] && + !_theResult____h580876[20] && + !_theResult____h580876[19] && + !_theResult____h580876[18] && + !_theResult____h580876[17] && + !_theResult____h580876[16] && + !_theResult____h580876[15] && + !_theResult____h580876[14] && + !_theResult____h580876[13] && + !_theResult____h580876[12] && + !_theResult____h580876[11] && + !_theResult____h580876[10] && + !_theResult____h580876[9] && + !_theResult____h580876[8] && + !_theResult____h580876[7] && + !_theResult____h580876[6] && + !_theResult____h580876[5] && + !_theResult____h580876[4] && + !_theResult____h580876[3] && + !_theResult____h580876[2] && + !_theResult____h580876[1] && + !_theResult____h580876[0]) ? + _theResult____h580876 : + _theResult___snd__h589027 ; + assign _theResult___snd__h589027 = + { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q41[54:0], 2'd0 } ; - assign _theResult___snd__h589053 = - _theResult____h580879 << + assign _theResult___snd__h589050 = + _theResult____h580876 << IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d8461 ; - assign _theResult___snd__h597597 = + assign _theResult___snd__h597594 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___snd__h597606 : - _theResult___snd__h597599 ; - assign _theResult___snd__h597599 = + _theResult___snd__h597603 : + _theResult___snd__h597596 ; + assign _theResult___snd__h597596 = { coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5], 5'd0 } ; - assign _theResult___snd__h597606 = + assign _theResult___snd__h597603 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d8637) ? - sfd__h573274 : - _theResult___snd__h597612 ; - assign _theResult___snd__h597612 = - { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q45[54:0], + sfd__h573271 : + _theResult___snd__h597609 ; + assign _theResult___snd__h597609 = + { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q43[54:0], 2'd0 } ; - assign _theResult___snd__h597635 = - sfd__h573274 << + assign _theResult___snd__h597632 = + sfd__h573271 << IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d8692 ; - assign _theResult___snd__h606767 = { _theResult____h598518[55:0], 1'd0 } ; - assign _theResult___snd__h606778 = - (!_theResult____h598518[56] && _theResult____h598518[55]) ? - _theResult___snd__h606780 : - _theResult___snd__h606790 ; - assign _theResult___snd__h606780 = { _theResult____h598518[54:0], 2'd0 } ; - assign _theResult___snd__h606790 = - (!_theResult____h598518[56] && !_theResult____h598518[55] && - !_theResult____h598518[54] && - !_theResult____h598518[53] && - !_theResult____h598518[52] && - !_theResult____h598518[51] && - !_theResult____h598518[50] && - !_theResult____h598518[49] && - !_theResult____h598518[48] && - !_theResult____h598518[47] && - !_theResult____h598518[46] && - !_theResult____h598518[45] && - !_theResult____h598518[44] && - !_theResult____h598518[43] && - !_theResult____h598518[42] && - !_theResult____h598518[41] && - !_theResult____h598518[40] && - !_theResult____h598518[39] && - !_theResult____h598518[38] && - !_theResult____h598518[37] && - !_theResult____h598518[36] && - !_theResult____h598518[35] && - !_theResult____h598518[34] && - !_theResult____h598518[33] && - !_theResult____h598518[32] && - !_theResult____h598518[31] && - !_theResult____h598518[30] && - !_theResult____h598518[29] && - !_theResult____h598518[28] && - !_theResult____h598518[27] && - !_theResult____h598518[26] && - !_theResult____h598518[25] && - !_theResult____h598518[24] && - !_theResult____h598518[23] && - !_theResult____h598518[22] && - !_theResult____h598518[21] && - !_theResult____h598518[20] && - !_theResult____h598518[19] && - !_theResult____h598518[18] && - !_theResult____h598518[17] && - !_theResult____h598518[16] && - !_theResult____h598518[15] && - !_theResult____h598518[14] && - !_theResult____h598518[13] && - !_theResult____h598518[12] && - !_theResult____h598518[11] && - !_theResult____h598518[10] && - !_theResult____h598518[9] && - !_theResult____h598518[8] && - !_theResult____h598518[7] && - !_theResult____h598518[6] && - !_theResult____h598518[5] && - !_theResult____h598518[4] && - !_theResult____h598518[3] && - !_theResult____h598518[2] && - !_theResult____h598518[1] && - !_theResult____h598518[0]) ? - _theResult____h598518 : - _theResult___snd__h606796 ; - assign _theResult___snd__h606796 = + assign _theResult___snd__h606764 = { _theResult____h598515[55:0], 1'd0 } ; + assign _theResult___snd__h606775 = + (!_theResult____h598515[56] && _theResult____h598515[55]) ? + _theResult___snd__h606777 : + _theResult___snd__h606787 ; + assign _theResult___snd__h606777 = { _theResult____h598515[54:0], 2'd0 } ; + assign _theResult___snd__h606787 = + (!_theResult____h598515[56] && !_theResult____h598515[55] && + !_theResult____h598515[54] && + !_theResult____h598515[53] && + !_theResult____h598515[52] && + !_theResult____h598515[51] && + !_theResult____h598515[50] && + !_theResult____h598515[49] && + !_theResult____h598515[48] && + !_theResult____h598515[47] && + !_theResult____h598515[46] && + !_theResult____h598515[45] && + !_theResult____h598515[44] && + !_theResult____h598515[43] && + !_theResult____h598515[42] && + !_theResult____h598515[41] && + !_theResult____h598515[40] && + !_theResult____h598515[39] && + !_theResult____h598515[38] && + !_theResult____h598515[37] && + !_theResult____h598515[36] && + !_theResult____h598515[35] && + !_theResult____h598515[34] && + !_theResult____h598515[33] && + !_theResult____h598515[32] && + !_theResult____h598515[31] && + !_theResult____h598515[30] && + !_theResult____h598515[29] && + !_theResult____h598515[28] && + !_theResult____h598515[27] && + !_theResult____h598515[26] && + !_theResult____h598515[25] && + !_theResult____h598515[24] && + !_theResult____h598515[23] && + !_theResult____h598515[22] && + !_theResult____h598515[21] && + !_theResult____h598515[20] && + !_theResult____h598515[19] && + !_theResult____h598515[18] && + !_theResult____h598515[17] && + !_theResult____h598515[16] && + !_theResult____h598515[15] && + !_theResult____h598515[14] && + !_theResult____h598515[13] && + !_theResult____h598515[12] && + !_theResult____h598515[11] && + !_theResult____h598515[10] && + !_theResult____h598515[9] && + !_theResult____h598515[8] && + !_theResult____h598515[7] && + !_theResult____h598515[6] && + !_theResult____h598515[5] && + !_theResult____h598515[4] && + !_theResult____h598515[3] && + !_theResult____h598515[2] && + !_theResult____h598515[1] && + !_theResult____h598515[0]) ? + _theResult____h598515 : + _theResult___snd__h606793 ; + assign _theResult___snd__h606793 = { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q51[54:0], 2'd0 } ; - assign _theResult___snd__h606819 = - _theResult____h598518 << + assign _theResult___snd__h606816 = + _theResult____h598515 << IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d9012 ; - assign _theResult___snd__h615387 = + assign _theResult___snd__h615384 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___snd__h615401 : - _theResult___snd__h597599 ; - assign _theResult___snd__h615401 = + _theResult___snd__h615398 : + _theResult___snd__h597596 ; + assign _theResult___snd__h615398 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d8637) ? - sfd__h573274 : - _theResult___snd__h615407 ; - assign _theResult___snd__h615407 = + sfd__h573271 : + _theResult___snd__h615404 ; + assign _theResult___snd__h615404 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q56[54:0], 2'd0 } ; - assign _theResult___snd__h615425 = - sfd__h573274 << + assign _theResult___snd__h615422 = + sfd__h573271 << (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d9086[8] ? 9'h0AA : IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d9086) ; - assign _theResult___snd__h634750 = { _theResult____h626630[55:0], 1'd0 } ; - assign _theResult___snd__h634761 = - (!_theResult____h626630[56] && _theResult____h626630[55]) ? - _theResult___snd__h634763 : - _theResult___snd__h634773 ; - assign _theResult___snd__h634763 = { _theResult____h626630[54:0], 2'd0 } ; - assign _theResult___snd__h634773 = - (!_theResult____h626630[56] && !_theResult____h626630[55] && - !_theResult____h626630[54] && - !_theResult____h626630[53] && - !_theResult____h626630[52] && - !_theResult____h626630[51] && - !_theResult____h626630[50] && - !_theResult____h626630[49] && - !_theResult____h626630[48] && - !_theResult____h626630[47] && - !_theResult____h626630[46] && - !_theResult____h626630[45] && - !_theResult____h626630[44] && - !_theResult____h626630[43] && - !_theResult____h626630[42] && - !_theResult____h626630[41] && - !_theResult____h626630[40] && - !_theResult____h626630[39] && - !_theResult____h626630[38] && - !_theResult____h626630[37] && - !_theResult____h626630[36] && - !_theResult____h626630[35] && - !_theResult____h626630[34] && - !_theResult____h626630[33] && - !_theResult____h626630[32] && - !_theResult____h626630[31] && - !_theResult____h626630[30] && - !_theResult____h626630[29] && - !_theResult____h626630[28] && - !_theResult____h626630[27] && - !_theResult____h626630[26] && - !_theResult____h626630[25] && - !_theResult____h626630[24] && - !_theResult____h626630[23] && - !_theResult____h626630[22] && - !_theResult____h626630[21] && - !_theResult____h626630[20] && - !_theResult____h626630[19] && - !_theResult____h626630[18] && - !_theResult____h626630[17] && - !_theResult____h626630[16] && - !_theResult____h626630[15] && - !_theResult____h626630[14] && - !_theResult____h626630[13] && - !_theResult____h626630[12] && - !_theResult____h626630[11] && - !_theResult____h626630[10] && - !_theResult____h626630[9] && - !_theResult____h626630[8] && - !_theResult____h626630[7] && - !_theResult____h626630[6] && - !_theResult____h626630[5] && - !_theResult____h626630[4] && - !_theResult____h626630[3] && - !_theResult____h626630[2] && - !_theResult____h626630[1] && - !_theResult____h626630[0]) ? - _theResult____h626630 : - _theResult___snd__h634779 ; - assign _theResult___snd__h634779 = + assign _theResult___snd__h634747 = { _theResult____h626627[55:0], 1'd0 } ; + assign _theResult___snd__h634758 = + (!_theResult____h626627[56] && _theResult____h626627[55]) ? + _theResult___snd__h634760 : + _theResult___snd__h634770 ; + assign _theResult___snd__h634760 = { _theResult____h626627[54:0], 2'd0 } ; + assign _theResult___snd__h634770 = + (!_theResult____h626627[56] && !_theResult____h626627[55] && + !_theResult____h626627[54] && + !_theResult____h626627[53] && + !_theResult____h626627[52] && + !_theResult____h626627[51] && + !_theResult____h626627[50] && + !_theResult____h626627[49] && + !_theResult____h626627[48] && + !_theResult____h626627[47] && + !_theResult____h626627[46] && + !_theResult____h626627[45] && + !_theResult____h626627[44] && + !_theResult____h626627[43] && + !_theResult____h626627[42] && + !_theResult____h626627[41] && + !_theResult____h626627[40] && + !_theResult____h626627[39] && + !_theResult____h626627[38] && + !_theResult____h626627[37] && + !_theResult____h626627[36] && + !_theResult____h626627[35] && + !_theResult____h626627[34] && + !_theResult____h626627[33] && + !_theResult____h626627[32] && + !_theResult____h626627[31] && + !_theResult____h626627[30] && + !_theResult____h626627[29] && + !_theResult____h626627[28] && + !_theResult____h626627[27] && + !_theResult____h626627[26] && + !_theResult____h626627[25] && + !_theResult____h626627[24] && + !_theResult____h626627[23] && + !_theResult____h626627[22] && + !_theResult____h626627[21] && + !_theResult____h626627[20] && + !_theResult____h626627[19] && + !_theResult____h626627[18] && + !_theResult____h626627[17] && + !_theResult____h626627[16] && + !_theResult____h626627[15] && + !_theResult____h626627[14] && + !_theResult____h626627[13] && + !_theResult____h626627[12] && + !_theResult____h626627[11] && + !_theResult____h626627[10] && + !_theResult____h626627[9] && + !_theResult____h626627[8] && + !_theResult____h626627[7] && + !_theResult____h626627[6] && + !_theResult____h626627[5] && + !_theResult____h626627[4] && + !_theResult____h626627[3] && + !_theResult____h626627[2] && + !_theResult____h626627[1] && + !_theResult____h626627[0]) ? + _theResult____h626627 : + _theResult___snd__h634776 ; + assign _theResult___snd__h634776 = { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q76[54:0], 2'd0 } ; - assign _theResult___snd__h634802 = - _theResult____h626630 << + assign _theResult___snd__h634799 = + _theResult____h626627 << IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d9858 ; - assign _theResult___snd__h643346 = + assign _theResult___snd__h643343 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___snd__h643355 : - _theResult___snd__h643348 ; - assign _theResult___snd__h643348 = + _theResult___snd__h643352 : + _theResult___snd__h643345 ; + assign _theResult___snd__h643345 = { coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5], 5'd0 } ; - assign _theResult___snd__h643355 = + assign _theResult___snd__h643352 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d10034) ? - sfd__h619028 : - _theResult___snd__h643361 ; - assign _theResult___snd__h643361 = + sfd__h619025 : + _theResult___snd__h643358 ; + assign _theResult___snd__h643358 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q78[54:0], 2'd0 } ; - assign _theResult___snd__h643384 = - sfd__h619028 << + assign _theResult___snd__h643381 = + sfd__h619025 << IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d10089 ; - assign _theResult___snd__h652516 = { _theResult____h644267[55:0], 1'd0 } ; - assign _theResult___snd__h652527 = - (!_theResult____h644267[56] && _theResult____h644267[55]) ? - _theResult___snd__h652529 : - _theResult___snd__h652539 ; - assign _theResult___snd__h652529 = { _theResult____h644267[54:0], 2'd0 } ; - assign _theResult___snd__h652539 = - (!_theResult____h644267[56] && !_theResult____h644267[55] && - !_theResult____h644267[54] && - !_theResult____h644267[53] && - !_theResult____h644267[52] && - !_theResult____h644267[51] && - !_theResult____h644267[50] && - !_theResult____h644267[49] && - !_theResult____h644267[48] && - !_theResult____h644267[47] && - !_theResult____h644267[46] && - !_theResult____h644267[45] && - !_theResult____h644267[44] && - !_theResult____h644267[43] && - !_theResult____h644267[42] && - !_theResult____h644267[41] && - !_theResult____h644267[40] && - !_theResult____h644267[39] && - !_theResult____h644267[38] && - !_theResult____h644267[37] && - !_theResult____h644267[36] && - !_theResult____h644267[35] && - !_theResult____h644267[34] && - !_theResult____h644267[33] && - !_theResult____h644267[32] && - !_theResult____h644267[31] && - !_theResult____h644267[30] && - !_theResult____h644267[29] && - !_theResult____h644267[28] && - !_theResult____h644267[27] && - !_theResult____h644267[26] && - !_theResult____h644267[25] && - !_theResult____h644267[24] && - !_theResult____h644267[23] && - !_theResult____h644267[22] && - !_theResult____h644267[21] && - !_theResult____h644267[20] && - !_theResult____h644267[19] && - !_theResult____h644267[18] && - !_theResult____h644267[17] && - !_theResult____h644267[16] && - !_theResult____h644267[15] && - !_theResult____h644267[14] && - !_theResult____h644267[13] && - !_theResult____h644267[12] && - !_theResult____h644267[11] && - !_theResult____h644267[10] && - !_theResult____h644267[9] && - !_theResult____h644267[8] && - !_theResult____h644267[7] && - !_theResult____h644267[6] && - !_theResult____h644267[5] && - !_theResult____h644267[4] && - !_theResult____h644267[3] && - !_theResult____h644267[2] && - !_theResult____h644267[1] && - !_theResult____h644267[0]) ? - _theResult____h644267 : - _theResult___snd__h652545 ; - assign _theResult___snd__h652545 = + assign _theResult___snd__h652513 = { _theResult____h644264[55:0], 1'd0 } ; + assign _theResult___snd__h652524 = + (!_theResult____h644264[56] && _theResult____h644264[55]) ? + _theResult___snd__h652526 : + _theResult___snd__h652536 ; + assign _theResult___snd__h652526 = { _theResult____h644264[54:0], 2'd0 } ; + assign _theResult___snd__h652536 = + (!_theResult____h644264[56] && !_theResult____h644264[55] && + !_theResult____h644264[54] && + !_theResult____h644264[53] && + !_theResult____h644264[52] && + !_theResult____h644264[51] && + !_theResult____h644264[50] && + !_theResult____h644264[49] && + !_theResult____h644264[48] && + !_theResult____h644264[47] && + !_theResult____h644264[46] && + !_theResult____h644264[45] && + !_theResult____h644264[44] && + !_theResult____h644264[43] && + !_theResult____h644264[42] && + !_theResult____h644264[41] && + !_theResult____h644264[40] && + !_theResult____h644264[39] && + !_theResult____h644264[38] && + !_theResult____h644264[37] && + !_theResult____h644264[36] && + !_theResult____h644264[35] && + !_theResult____h644264[34] && + !_theResult____h644264[33] && + !_theResult____h644264[32] && + !_theResult____h644264[31] && + !_theResult____h644264[30] && + !_theResult____h644264[29] && + !_theResult____h644264[28] && + !_theResult____h644264[27] && + !_theResult____h644264[26] && + !_theResult____h644264[25] && + !_theResult____h644264[24] && + !_theResult____h644264[23] && + !_theResult____h644264[22] && + !_theResult____h644264[21] && + !_theResult____h644264[20] && + !_theResult____h644264[19] && + !_theResult____h644264[18] && + !_theResult____h644264[17] && + !_theResult____h644264[16] && + !_theResult____h644264[15] && + !_theResult____h644264[14] && + !_theResult____h644264[13] && + !_theResult____h644264[12] && + !_theResult____h644264[11] && + !_theResult____h644264[10] && + !_theResult____h644264[9] && + !_theResult____h644264[8] && + !_theResult____h644264[7] && + !_theResult____h644264[6] && + !_theResult____h644264[5] && + !_theResult____h644264[4] && + !_theResult____h644264[3] && + !_theResult____h644264[2] && + !_theResult____h644264[1] && + !_theResult____h644264[0]) ? + _theResult____h644264 : + _theResult___snd__h652542 ; + assign _theResult___snd__h652542 = { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q86[54:0], 2'd0 } ; - assign _theResult___snd__h652568 = - _theResult____h644267 << + assign _theResult___snd__h652565 = + _theResult____h644264 << IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d10409 ; - assign _theResult___snd__h661136 = + assign _theResult___snd__h661133 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___snd__h661150 : - _theResult___snd__h643348 ; - assign _theResult___snd__h661150 = + _theResult___snd__h661147 : + _theResult___snd__h643345 ; + assign _theResult___snd__h661147 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d10034) ? - sfd__h619028 : - _theResult___snd__h661156 ; - assign _theResult___snd__h661156 = + sfd__h619025 : + _theResult___snd__h661153 ; + assign _theResult___snd__h661153 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q91[54:0], 2'd0 } ; - assign _theResult___snd__h661174 = - sfd__h619028 << + assign _theResult___snd__h661171 = + sfd__h619025 << (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d10483[8] ? 9'h0AA : IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d10483) ; - assign _theResult___snd__h680497 = { _theResult____h672377[55:0], 1'd0 } ; - assign _theResult___snd__h680508 = - (!_theResult____h672377[56] && _theResult____h672377[55]) ? - _theResult___snd__h680510 : - _theResult___snd__h680520 ; - assign _theResult___snd__h680510 = { _theResult____h672377[54:0], 2'd0 } ; - assign _theResult___snd__h680520 = - (!_theResult____h672377[56] && !_theResult____h672377[55] && - !_theResult____h672377[54] && - !_theResult____h672377[53] && - !_theResult____h672377[52] && - !_theResult____h672377[51] && - !_theResult____h672377[50] && - !_theResult____h672377[49] && - !_theResult____h672377[48] && - !_theResult____h672377[47] && - !_theResult____h672377[46] && - !_theResult____h672377[45] && - !_theResult____h672377[44] && - !_theResult____h672377[43] && - !_theResult____h672377[42] && - !_theResult____h672377[41] && - !_theResult____h672377[40] && - !_theResult____h672377[39] && - !_theResult____h672377[38] && - !_theResult____h672377[37] && - !_theResult____h672377[36] && - !_theResult____h672377[35] && - !_theResult____h672377[34] && - !_theResult____h672377[33] && - !_theResult____h672377[32] && - !_theResult____h672377[31] && - !_theResult____h672377[30] && - !_theResult____h672377[29] && - !_theResult____h672377[28] && - !_theResult____h672377[27] && - !_theResult____h672377[26] && - !_theResult____h672377[25] && - !_theResult____h672377[24] && - !_theResult____h672377[23] && - !_theResult____h672377[22] && - !_theResult____h672377[21] && - !_theResult____h672377[20] && - !_theResult____h672377[19] && - !_theResult____h672377[18] && - !_theResult____h672377[17] && - !_theResult____h672377[16] && - !_theResult____h672377[15] && - !_theResult____h672377[14] && - !_theResult____h672377[13] && - !_theResult____h672377[12] && - !_theResult____h672377[11] && - !_theResult____h672377[10] && - !_theResult____h672377[9] && - !_theResult____h672377[8] && - !_theResult____h672377[7] && - !_theResult____h672377[6] && - !_theResult____h672377[5] && - !_theResult____h672377[4] && - !_theResult____h672377[3] && - !_theResult____h672377[2] && - !_theResult____h672377[1] && - !_theResult____h672377[0]) ? - _theResult____h672377 : - _theResult___snd__h680526 ; - assign _theResult___snd__h680526 = + assign _theResult___snd__h680494 = { _theResult____h672374[55:0], 1'd0 } ; + assign _theResult___snd__h680505 = + (!_theResult____h672374[56] && _theResult____h672374[55]) ? + _theResult___snd__h680507 : + _theResult___snd__h680517 ; + assign _theResult___snd__h680507 = { _theResult____h672374[54:0], 2'd0 } ; + assign _theResult___snd__h680517 = + (!_theResult____h672374[56] && !_theResult____h672374[55] && + !_theResult____h672374[54] && + !_theResult____h672374[53] && + !_theResult____h672374[52] && + !_theResult____h672374[51] && + !_theResult____h672374[50] && + !_theResult____h672374[49] && + !_theResult____h672374[48] && + !_theResult____h672374[47] && + !_theResult____h672374[46] && + !_theResult____h672374[45] && + !_theResult____h672374[44] && + !_theResult____h672374[43] && + !_theResult____h672374[42] && + !_theResult____h672374[41] && + !_theResult____h672374[40] && + !_theResult____h672374[39] && + !_theResult____h672374[38] && + !_theResult____h672374[37] && + !_theResult____h672374[36] && + !_theResult____h672374[35] && + !_theResult____h672374[34] && + !_theResult____h672374[33] && + !_theResult____h672374[32] && + !_theResult____h672374[31] && + !_theResult____h672374[30] && + !_theResult____h672374[29] && + !_theResult____h672374[28] && + !_theResult____h672374[27] && + !_theResult____h672374[26] && + !_theResult____h672374[25] && + !_theResult____h672374[24] && + !_theResult____h672374[23] && + !_theResult____h672374[22] && + !_theResult____h672374[21] && + !_theResult____h672374[20] && + !_theResult____h672374[19] && + !_theResult____h672374[18] && + !_theResult____h672374[17] && + !_theResult____h672374[16] && + !_theResult____h672374[15] && + !_theResult____h672374[14] && + !_theResult____h672374[13] && + !_theResult____h672374[12] && + !_theResult____h672374[11] && + !_theResult____h672374[10] && + !_theResult____h672374[9] && + !_theResult____h672374[8] && + !_theResult____h672374[7] && + !_theResult____h672374[6] && + !_theResult____h672374[5] && + !_theResult____h672374[4] && + !_theResult____h672374[3] && + !_theResult____h672374[2] && + !_theResult____h672374[1] && + !_theResult____h672374[0]) ? + _theResult____h672374 : + _theResult___snd__h680523 ; + assign _theResult___snd__h680523 = { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q111[54:0], 2'd0 } ; - assign _theResult___snd__h680549 = - _theResult____h672377 << + assign _theResult___snd__h680546 = + _theResult____h672374 << IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d11255 ; - assign _theResult___snd__h689093 = + assign _theResult___snd__h689090 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___snd__h689102 : - _theResult___snd__h689095 ; - assign _theResult___snd__h689095 = + _theResult___snd__h689099 : + _theResult___snd__h689092 ; + assign _theResult___snd__h689092 = { coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5], 5'd0 } ; - assign _theResult___snd__h689102 = + assign _theResult___snd__h689099 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d11431) ? - sfd__h664775 : - _theResult___snd__h689108 ; - assign _theResult___snd__h689108 = + sfd__h664772 : + _theResult___snd__h689105 ; + assign _theResult___snd__h689105 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q113[54:0], 2'd0 } ; - assign _theResult___snd__h689131 = - sfd__h664775 << + assign _theResult___snd__h689128 = + sfd__h664772 << IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d11486 ; - assign _theResult___snd__h698263 = { _theResult____h690014[55:0], 1'd0 } ; - assign _theResult___snd__h698274 = - (!_theResult____h690014[56] && _theResult____h690014[55]) ? - _theResult___snd__h698276 : - _theResult___snd__h698286 ; - assign _theResult___snd__h698276 = { _theResult____h690014[54:0], 2'd0 } ; - assign _theResult___snd__h698286 = - (!_theResult____h690014[56] && !_theResult____h690014[55] && - !_theResult____h690014[54] && - !_theResult____h690014[53] && - !_theResult____h690014[52] && - !_theResult____h690014[51] && - !_theResult____h690014[50] && - !_theResult____h690014[49] && - !_theResult____h690014[48] && - !_theResult____h690014[47] && - !_theResult____h690014[46] && - !_theResult____h690014[45] && - !_theResult____h690014[44] && - !_theResult____h690014[43] && - !_theResult____h690014[42] && - !_theResult____h690014[41] && - !_theResult____h690014[40] && - !_theResult____h690014[39] && - !_theResult____h690014[38] && - !_theResult____h690014[37] && - !_theResult____h690014[36] && - !_theResult____h690014[35] && - !_theResult____h690014[34] && - !_theResult____h690014[33] && - !_theResult____h690014[32] && - !_theResult____h690014[31] && - !_theResult____h690014[30] && - !_theResult____h690014[29] && - !_theResult____h690014[28] && - !_theResult____h690014[27] && - !_theResult____h690014[26] && - !_theResult____h690014[25] && - !_theResult____h690014[24] && - !_theResult____h690014[23] && - !_theResult____h690014[22] && - !_theResult____h690014[21] && - !_theResult____h690014[20] && - !_theResult____h690014[19] && - !_theResult____h690014[18] && - !_theResult____h690014[17] && - !_theResult____h690014[16] && - !_theResult____h690014[15] && - !_theResult____h690014[14] && - !_theResult____h690014[13] && - !_theResult____h690014[12] && - !_theResult____h690014[11] && - !_theResult____h690014[10] && - !_theResult____h690014[9] && - !_theResult____h690014[8] && - !_theResult____h690014[7] && - !_theResult____h690014[6] && - !_theResult____h690014[5] && - !_theResult____h690014[4] && - !_theResult____h690014[3] && - !_theResult____h690014[2] && - !_theResult____h690014[1] && - !_theResult____h690014[0]) ? - _theResult____h690014 : - _theResult___snd__h698292 ; - assign _theResult___snd__h698292 = + assign _theResult___snd__h698260 = { _theResult____h690011[55:0], 1'd0 } ; + assign _theResult___snd__h698271 = + (!_theResult____h690011[56] && _theResult____h690011[55]) ? + _theResult___snd__h698273 : + _theResult___snd__h698283 ; + assign _theResult___snd__h698273 = { _theResult____h690011[54:0], 2'd0 } ; + assign _theResult___snd__h698283 = + (!_theResult____h690011[56] && !_theResult____h690011[55] && + !_theResult____h690011[54] && + !_theResult____h690011[53] && + !_theResult____h690011[52] && + !_theResult____h690011[51] && + !_theResult____h690011[50] && + !_theResult____h690011[49] && + !_theResult____h690011[48] && + !_theResult____h690011[47] && + !_theResult____h690011[46] && + !_theResult____h690011[45] && + !_theResult____h690011[44] && + !_theResult____h690011[43] && + !_theResult____h690011[42] && + !_theResult____h690011[41] && + !_theResult____h690011[40] && + !_theResult____h690011[39] && + !_theResult____h690011[38] && + !_theResult____h690011[37] && + !_theResult____h690011[36] && + !_theResult____h690011[35] && + !_theResult____h690011[34] && + !_theResult____h690011[33] && + !_theResult____h690011[32] && + !_theResult____h690011[31] && + !_theResult____h690011[30] && + !_theResult____h690011[29] && + !_theResult____h690011[28] && + !_theResult____h690011[27] && + !_theResult____h690011[26] && + !_theResult____h690011[25] && + !_theResult____h690011[24] && + !_theResult____h690011[23] && + !_theResult____h690011[22] && + !_theResult____h690011[21] && + !_theResult____h690011[20] && + !_theResult____h690011[19] && + !_theResult____h690011[18] && + !_theResult____h690011[17] && + !_theResult____h690011[16] && + !_theResult____h690011[15] && + !_theResult____h690011[14] && + !_theResult____h690011[13] && + !_theResult____h690011[12] && + !_theResult____h690011[11] && + !_theResult____h690011[10] && + !_theResult____h690011[9] && + !_theResult____h690011[8] && + !_theResult____h690011[7] && + !_theResult____h690011[6] && + !_theResult____h690011[5] && + !_theResult____h690011[4] && + !_theResult____h690011[3] && + !_theResult____h690011[2] && + !_theResult____h690011[1] && + !_theResult____h690011[0]) ? + _theResult____h690011 : + _theResult___snd__h698289 ; + assign _theResult___snd__h698289 = { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q121[54:0], 2'd0 } ; - assign _theResult___snd__h698315 = - _theResult____h690014 << + assign _theResult___snd__h698312 = + _theResult____h690011 << IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d11806 ; - assign _theResult___snd__h706883 = + assign _theResult___snd__h706880 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___snd__h706897 : - _theResult___snd__h689095 ; - assign _theResult___snd__h706897 = + _theResult___snd__h706894 : + _theResult___snd__h689092 ; + assign _theResult___snd__h706894 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d11431) ? - sfd__h664775 : - _theResult___snd__h706903 ; - assign _theResult___snd__h706903 = + sfd__h664772 : + _theResult___snd__h706900 ; + assign _theResult___snd__h706900 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q126[54:0], 2'd0 } ; - assign _theResult___snd__h706921 = - sfd__h664775 << + assign _theResult___snd__h706918 = + sfd__h664772 << (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d11880[8] ? 9'h0AA : IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d11880) ; - assign _theResult___snd__h739171 = - (f1_exp__h719832 == 8'd0) ? - _theResult___snd__h739180 : - _theResult___snd__h739173 ; - assign _theResult___snd__h739173 = { f1_sfd__h719833, 34'd0 } ; - assign _theResult___snd__h739180 = - (f1_exp__h719832 == 8'd0 && !f1_sfd__h719833[22] && + assign _theResult___snd__h739167 = + (f1_exp__h719828 == 8'd0) ? + _theResult___snd__h739176 : + _theResult___snd__h739169 ; + assign _theResult___snd__h739169 = { f1_sfd__h719829, 34'd0 } ; + assign _theResult___snd__h739176 = + (f1_exp__h719828 == 8'd0 && !f1_sfd__h719829[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d12813) ? - sfd__h720194 : - _theResult___snd__h739186 ; - assign _theResult___snd__h739186 = + sfd__h720190 : + _theResult___snd__h739182 ; + assign _theResult___snd__h739182 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q146[54:0], 2'd0 } ; - assign _theResult___snd__h739209 = - sfd__h720194 << + assign _theResult___snd__h739205 = + sfd__h720190 << IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d12840 ; - assign _theResult___snd__h748808 = { _theResult____h740561[55:0], 1'd0 } ; - assign _theResult___snd__h748819 = - (!_theResult____h740561[56] && _theResult____h740561[55]) ? - _theResult___snd__h748821 : - _theResult___snd__h748831 ; - assign _theResult___snd__h748821 = { _theResult____h740561[54:0], 2'd0 } ; - assign _theResult___snd__h748831 = - (!_theResult____h740561[56] && !_theResult____h740561[55] && - !_theResult____h740561[54] && - !_theResult____h740561[53] && - !_theResult____h740561[52] && - !_theResult____h740561[51] && - !_theResult____h740561[50] && - !_theResult____h740561[49] && - !_theResult____h740561[48] && - !_theResult____h740561[47] && - !_theResult____h740561[46] && - !_theResult____h740561[45] && - !_theResult____h740561[44] && - !_theResult____h740561[43] && - !_theResult____h740561[42] && - !_theResult____h740561[41] && - !_theResult____h740561[40] && - !_theResult____h740561[39] && - !_theResult____h740561[38] && - !_theResult____h740561[37] && - !_theResult____h740561[36] && - !_theResult____h740561[35] && - !_theResult____h740561[34] && - !_theResult____h740561[33] && - !_theResult____h740561[32] && - !_theResult____h740561[31] && - !_theResult____h740561[30] && - !_theResult____h740561[29] && - !_theResult____h740561[28] && - !_theResult____h740561[27] && - !_theResult____h740561[26] && - !_theResult____h740561[25] && - !_theResult____h740561[24] && - !_theResult____h740561[23] && - !_theResult____h740561[22] && - !_theResult____h740561[21] && - !_theResult____h740561[20] && - !_theResult____h740561[19] && - !_theResult____h740561[18] && - !_theResult____h740561[17] && - !_theResult____h740561[16] && - !_theResult____h740561[15] && - !_theResult____h740561[14] && - !_theResult____h740561[13] && - !_theResult____h740561[12] && - !_theResult____h740561[11] && - !_theResult____h740561[10] && - !_theResult____h740561[9] && - !_theResult____h740561[8] && - !_theResult____h740561[7] && - !_theResult____h740561[6] && - !_theResult____h740561[5] && - !_theResult____h740561[4] && - !_theResult____h740561[3] && - !_theResult____h740561[2] && - !_theResult____h740561[1] && - !_theResult____h740561[0]) ? - _theResult____h740561 : - _theResult___snd__h748837 ; - assign _theResult___snd__h748837 = + assign _theResult___snd__h748804 = { _theResult____h740557[55:0], 1'd0 } ; + assign _theResult___snd__h748815 = + (!_theResult____h740557[56] && _theResult____h740557[55]) ? + _theResult___snd__h748817 : + _theResult___snd__h748827 ; + assign _theResult___snd__h748817 = { _theResult____h740557[54:0], 2'd0 } ; + assign _theResult___snd__h748827 = + (!_theResult____h740557[56] && !_theResult____h740557[55] && + !_theResult____h740557[54] && + !_theResult____h740557[53] && + !_theResult____h740557[52] && + !_theResult____h740557[51] && + !_theResult____h740557[50] && + !_theResult____h740557[49] && + !_theResult____h740557[48] && + !_theResult____h740557[47] && + !_theResult____h740557[46] && + !_theResult____h740557[45] && + !_theResult____h740557[44] && + !_theResult____h740557[43] && + !_theResult____h740557[42] && + !_theResult____h740557[41] && + !_theResult____h740557[40] && + !_theResult____h740557[39] && + !_theResult____h740557[38] && + !_theResult____h740557[37] && + !_theResult____h740557[36] && + !_theResult____h740557[35] && + !_theResult____h740557[34] && + !_theResult____h740557[33] && + !_theResult____h740557[32] && + !_theResult____h740557[31] && + !_theResult____h740557[30] && + !_theResult____h740557[29] && + !_theResult____h740557[28] && + !_theResult____h740557[27] && + !_theResult____h740557[26] && + !_theResult____h740557[25] && + !_theResult____h740557[24] && + !_theResult____h740557[23] && + !_theResult____h740557[22] && + !_theResult____h740557[21] && + !_theResult____h740557[20] && + !_theResult____h740557[19] && + !_theResult____h740557[18] && + !_theResult____h740557[17] && + !_theResult____h740557[16] && + !_theResult____h740557[15] && + !_theResult____h740557[14] && + !_theResult____h740557[13] && + !_theResult____h740557[12] && + !_theResult____h740557[11] && + !_theResult____h740557[10] && + !_theResult____h740557[9] && + !_theResult____h740557[8] && + !_theResult____h740557[7] && + !_theResult____h740557[6] && + !_theResult____h740557[5] && + !_theResult____h740557[4] && + !_theResult____h740557[3] && + !_theResult____h740557[2] && + !_theResult____h740557[1] && + !_theResult____h740557[0]) ? + _theResult____h740557 : + _theResult___snd__h748833 ; + assign _theResult___snd__h748833 = { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q150[54:0], 2'd0 } ; - assign _theResult___snd__h748860 = - _theResult____h740561 << + assign _theResult___snd__h748856 = + _theResult____h740557 << IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d13152 ; - assign _theResult___snd__h757576 = - (f1_exp__h719832 == 8'd0) ? - _theResult___snd__h757590 : - _theResult___snd__h739173 ; - assign _theResult___snd__h757590 = - (f1_exp__h719832 == 8'd0 && !f1_sfd__h719833[22] && + assign _theResult___snd__h757572 = + (f1_exp__h719828 == 8'd0) ? + _theResult___snd__h757586 : + _theResult___snd__h739169 ; + assign _theResult___snd__h757586 = + (f1_exp__h719828 == 8'd0 && !f1_sfd__h719829[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d12813) ? - sfd__h720194 : - _theResult___snd__h757596 ; - assign _theResult___snd__h757596 = + sfd__h720190 : + _theResult___snd__h757592 ; + assign _theResult___snd__h757592 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q153[54:0], 2'd0 } ; - assign _theResult___snd__h757614 = - sfd__h720194 << + assign _theResult___snd__h757610 = + sfd__h720190 << IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d13203 ; - assign _theResult___snd__h778024 = - (f2_exp__h758826 == 8'd0) ? - _theResult___snd__h778033 : - _theResult___snd__h778026 ; - assign _theResult___snd__h778026 = { f2_sfd__h758827, 34'd0 } ; - assign _theResult___snd__h778033 = - (f2_exp__h758826 == 8'd0 && !f2_sfd__h758827[22] && + assign _theResult___snd__h778020 = + (f2_exp__h758822 == 8'd0) ? + _theResult___snd__h778029 : + _theResult___snd__h778022 ; + assign _theResult___snd__h778022 = { f2_sfd__h758823, 34'd0 } ; + assign _theResult___snd__h778029 = + (f2_exp__h758822 == 8'd0 && !f2_sfd__h758823[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d14313) ? - sfd__h759188 : - _theResult___snd__h778039 ; - assign _theResult___snd__h778039 = + sfd__h759184 : + _theResult___snd__h778035 ; + assign _theResult___snd__h778035 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q186[54:0], 2'd0 } ; - assign _theResult___snd__h778062 = - sfd__h759188 << + assign _theResult___snd__h778058 = + sfd__h759184 << IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14340 ; - assign _theResult___snd__h787661 = { _theResult____h779414[55:0], 1'd0 } ; - assign _theResult___snd__h787672 = - (!_theResult____h779414[56] && _theResult____h779414[55]) ? - _theResult___snd__h787674 : - _theResult___snd__h787684 ; - assign _theResult___snd__h787674 = { _theResult____h779414[54:0], 2'd0 } ; - assign _theResult___snd__h787684 = - (!_theResult____h779414[56] && !_theResult____h779414[55] && - !_theResult____h779414[54] && - !_theResult____h779414[53] && - !_theResult____h779414[52] && - !_theResult____h779414[51] && - !_theResult____h779414[50] && - !_theResult____h779414[49] && - !_theResult____h779414[48] && - !_theResult____h779414[47] && - !_theResult____h779414[46] && - !_theResult____h779414[45] && - !_theResult____h779414[44] && - !_theResult____h779414[43] && - !_theResult____h779414[42] && - !_theResult____h779414[41] && - !_theResult____h779414[40] && - !_theResult____h779414[39] && - !_theResult____h779414[38] && - !_theResult____h779414[37] && - !_theResult____h779414[36] && - !_theResult____h779414[35] && - !_theResult____h779414[34] && - !_theResult____h779414[33] && - !_theResult____h779414[32] && - !_theResult____h779414[31] && - !_theResult____h779414[30] && - !_theResult____h779414[29] && - !_theResult____h779414[28] && - !_theResult____h779414[27] && - !_theResult____h779414[26] && - !_theResult____h779414[25] && - !_theResult____h779414[24] && - !_theResult____h779414[23] && - !_theResult____h779414[22] && - !_theResult____h779414[21] && - !_theResult____h779414[20] && - !_theResult____h779414[19] && - !_theResult____h779414[18] && - !_theResult____h779414[17] && - !_theResult____h779414[16] && - !_theResult____h779414[15] && - !_theResult____h779414[14] && - !_theResult____h779414[13] && - !_theResult____h779414[12] && - !_theResult____h779414[11] && - !_theResult____h779414[10] && - !_theResult____h779414[9] && - !_theResult____h779414[8] && - !_theResult____h779414[7] && - !_theResult____h779414[6] && - !_theResult____h779414[5] && - !_theResult____h779414[4] && - !_theResult____h779414[3] && - !_theResult____h779414[2] && - !_theResult____h779414[1] && - !_theResult____h779414[0]) ? - _theResult____h779414 : - _theResult___snd__h787690 ; - assign _theResult___snd__h787690 = + assign _theResult___snd__h787657 = { _theResult____h779410[55:0], 1'd0 } ; + assign _theResult___snd__h787668 = + (!_theResult____h779410[56] && _theResult____h779410[55]) ? + _theResult___snd__h787670 : + _theResult___snd__h787680 ; + assign _theResult___snd__h787670 = { _theResult____h779410[54:0], 2'd0 } ; + assign _theResult___snd__h787680 = + (!_theResult____h779410[56] && !_theResult____h779410[55] && + !_theResult____h779410[54] && + !_theResult____h779410[53] && + !_theResult____h779410[52] && + !_theResult____h779410[51] && + !_theResult____h779410[50] && + !_theResult____h779410[49] && + !_theResult____h779410[48] && + !_theResult____h779410[47] && + !_theResult____h779410[46] && + !_theResult____h779410[45] && + !_theResult____h779410[44] && + !_theResult____h779410[43] && + !_theResult____h779410[42] && + !_theResult____h779410[41] && + !_theResult____h779410[40] && + !_theResult____h779410[39] && + !_theResult____h779410[38] && + !_theResult____h779410[37] && + !_theResult____h779410[36] && + !_theResult____h779410[35] && + !_theResult____h779410[34] && + !_theResult____h779410[33] && + !_theResult____h779410[32] && + !_theResult____h779410[31] && + !_theResult____h779410[30] && + !_theResult____h779410[29] && + !_theResult____h779410[28] && + !_theResult____h779410[27] && + !_theResult____h779410[26] && + !_theResult____h779410[25] && + !_theResult____h779410[24] && + !_theResult____h779410[23] && + !_theResult____h779410[22] && + !_theResult____h779410[21] && + !_theResult____h779410[20] && + !_theResult____h779410[19] && + !_theResult____h779410[18] && + !_theResult____h779410[17] && + !_theResult____h779410[16] && + !_theResult____h779410[15] && + !_theResult____h779410[14] && + !_theResult____h779410[13] && + !_theResult____h779410[12] && + !_theResult____h779410[11] && + !_theResult____h779410[10] && + !_theResult____h779410[9] && + !_theResult____h779410[8] && + !_theResult____h779410[7] && + !_theResult____h779410[6] && + !_theResult____h779410[5] && + !_theResult____h779410[4] && + !_theResult____h779410[3] && + !_theResult____h779410[2] && + !_theResult____h779410[1] && + !_theResult____h779410[0]) ? + _theResult____h779410 : + _theResult___snd__h787686 ; + assign _theResult___snd__h787686 = { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q190[54:0], 2'd0 } ; - assign _theResult___snd__h787713 = - _theResult____h779414 << + assign _theResult___snd__h787709 = + _theResult____h779410 << IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d14637 ; - assign _theResult___snd__h796429 = - (f2_exp__h758826 == 8'd0) ? - _theResult___snd__h796443 : - _theResult___snd__h778026 ; - assign _theResult___snd__h796443 = - (f2_exp__h758826 == 8'd0 && !f2_sfd__h758827[22] && + assign _theResult___snd__h796425 = + (f2_exp__h758822 == 8'd0) ? + _theResult___snd__h796439 : + _theResult___snd__h778022 ; + assign _theResult___snd__h796439 = + (f2_exp__h758822 == 8'd0 && !f2_sfd__h758823[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d14313) ? - sfd__h759188 : - _theResult___snd__h796449 ; - assign _theResult___snd__h796449 = + sfd__h759184 : + _theResult___snd__h796445 ; + assign _theResult___snd__h796445 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q193[54:0], 2'd0 } ; - assign _theResult___snd__h796467 = - sfd__h759188 << + assign _theResult___snd__h796463 = + sfd__h759184 << IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d14688 ; - assign _theResult___snd__h817328 = - (f3_exp__h798130 == 8'd0) ? - _theResult___snd__h817337 : - _theResult___snd__h817330 ; - assign _theResult___snd__h817330 = { f3_sfd__h798131, 34'd0 } ; - assign _theResult___snd__h817337 = - (f3_exp__h798130 == 8'd0 && !f3_sfd__h798131[22] && + assign _theResult___snd__h817324 = + (f3_exp__h798126 == 8'd0) ? + _theResult___snd__h817333 : + _theResult___snd__h817326 ; + assign _theResult___snd__h817326 = { f3_sfd__h798127, 34'd0 } ; + assign _theResult___snd__h817333 = + (f3_exp__h798126 == 8'd0 && !f3_sfd__h798127[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d13543) ? - sfd__h798492 : - _theResult___snd__h817343 ; - assign _theResult___snd__h817343 = + sfd__h798488 : + _theResult___snd__h817339 ; + assign _theResult___snd__h817339 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q163[54:0], 2'd0 } ; - assign _theResult___snd__h817366 = - sfd__h798492 << + assign _theResult___snd__h817362 = + sfd__h798488 << IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13570 ; - assign _theResult___snd__h826965 = { _theResult____h818718[55:0], 1'd0 } ; - assign _theResult___snd__h826976 = - (!_theResult____h818718[56] && _theResult____h818718[55]) ? - _theResult___snd__h826978 : - _theResult___snd__h826988 ; - assign _theResult___snd__h826978 = { _theResult____h818718[54:0], 2'd0 } ; - assign _theResult___snd__h826988 = - (!_theResult____h818718[56] && !_theResult____h818718[55] && - !_theResult____h818718[54] && - !_theResult____h818718[53] && - !_theResult____h818718[52] && - !_theResult____h818718[51] && - !_theResult____h818718[50] && - !_theResult____h818718[49] && - !_theResult____h818718[48] && - !_theResult____h818718[47] && - !_theResult____h818718[46] && - !_theResult____h818718[45] && - !_theResult____h818718[44] && - !_theResult____h818718[43] && - !_theResult____h818718[42] && - !_theResult____h818718[41] && - !_theResult____h818718[40] && - !_theResult____h818718[39] && - !_theResult____h818718[38] && - !_theResult____h818718[37] && - !_theResult____h818718[36] && - !_theResult____h818718[35] && - !_theResult____h818718[34] && - !_theResult____h818718[33] && - !_theResult____h818718[32] && - !_theResult____h818718[31] && - !_theResult____h818718[30] && - !_theResult____h818718[29] && - !_theResult____h818718[28] && - !_theResult____h818718[27] && - !_theResult____h818718[26] && - !_theResult____h818718[25] && - !_theResult____h818718[24] && - !_theResult____h818718[23] && - !_theResult____h818718[22] && - !_theResult____h818718[21] && - !_theResult____h818718[20] && - !_theResult____h818718[19] && - !_theResult____h818718[18] && - !_theResult____h818718[17] && - !_theResult____h818718[16] && - !_theResult____h818718[15] && - !_theResult____h818718[14] && - !_theResult____h818718[13] && - !_theResult____h818718[12] && - !_theResult____h818718[11] && - !_theResult____h818718[10] && - !_theResult____h818718[9] && - !_theResult____h818718[8] && - !_theResult____h818718[7] && - !_theResult____h818718[6] && - !_theResult____h818718[5] && - !_theResult____h818718[4] && - !_theResult____h818718[3] && - !_theResult____h818718[2] && - !_theResult____h818718[1] && - !_theResult____h818718[0]) ? - _theResult____h818718 : - _theResult___snd__h826994 ; - assign _theResult___snd__h826994 = + assign _theResult___snd__h826961 = { _theResult____h818714[55:0], 1'd0 } ; + assign _theResult___snd__h826972 = + (!_theResult____h818714[56] && _theResult____h818714[55]) ? + _theResult___snd__h826974 : + _theResult___snd__h826984 ; + assign _theResult___snd__h826974 = { _theResult____h818714[54:0], 2'd0 } ; + assign _theResult___snd__h826984 = + (!_theResult____h818714[56] && !_theResult____h818714[55] && + !_theResult____h818714[54] && + !_theResult____h818714[53] && + !_theResult____h818714[52] && + !_theResult____h818714[51] && + !_theResult____h818714[50] && + !_theResult____h818714[49] && + !_theResult____h818714[48] && + !_theResult____h818714[47] && + !_theResult____h818714[46] && + !_theResult____h818714[45] && + !_theResult____h818714[44] && + !_theResult____h818714[43] && + !_theResult____h818714[42] && + !_theResult____h818714[41] && + !_theResult____h818714[40] && + !_theResult____h818714[39] && + !_theResult____h818714[38] && + !_theResult____h818714[37] && + !_theResult____h818714[36] && + !_theResult____h818714[35] && + !_theResult____h818714[34] && + !_theResult____h818714[33] && + !_theResult____h818714[32] && + !_theResult____h818714[31] && + !_theResult____h818714[30] && + !_theResult____h818714[29] && + !_theResult____h818714[28] && + !_theResult____h818714[27] && + !_theResult____h818714[26] && + !_theResult____h818714[25] && + !_theResult____h818714[24] && + !_theResult____h818714[23] && + !_theResult____h818714[22] && + !_theResult____h818714[21] && + !_theResult____h818714[20] && + !_theResult____h818714[19] && + !_theResult____h818714[18] && + !_theResult____h818714[17] && + !_theResult____h818714[16] && + !_theResult____h818714[15] && + !_theResult____h818714[14] && + !_theResult____h818714[13] && + !_theResult____h818714[12] && + !_theResult____h818714[11] && + !_theResult____h818714[10] && + !_theResult____h818714[9] && + !_theResult____h818714[8] && + !_theResult____h818714[7] && + !_theResult____h818714[6] && + !_theResult____h818714[5] && + !_theResult____h818714[4] && + !_theResult____h818714[3] && + !_theResult____h818714[2] && + !_theResult____h818714[1] && + !_theResult____h818714[0]) ? + _theResult____h818714 : + _theResult___snd__h826990 ; + assign _theResult___snd__h826990 = { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q167[54:0], 2'd0 } ; - assign _theResult___snd__h827017 = - _theResult____h818718 << + assign _theResult___snd__h827013 = + _theResult____h818714 << IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d13867 ; - assign _theResult___snd__h835733 = - (f3_exp__h798130 == 8'd0) ? - _theResult___snd__h835747 : - _theResult___snd__h817330 ; - assign _theResult___snd__h835747 = - (f3_exp__h798130 == 8'd0 && !f3_sfd__h798131[22] && + assign _theResult___snd__h835729 = + (f3_exp__h798126 == 8'd0) ? + _theResult___snd__h835743 : + _theResult___snd__h817326 ; + assign _theResult___snd__h835743 = + (f3_exp__h798126 == 8'd0 && !f3_sfd__h798127[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d13543) ? - sfd__h798492 : - _theResult___snd__h835753 ; - assign _theResult___snd__h835753 = + sfd__h798488 : + _theResult___snd__h835749 ; + assign _theResult___snd__h835749 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q170[54:0], 2'd0 } ; - assign _theResult___snd__h835771 = - sfd__h798492 << + assign _theResult___snd__h835767 = + sfd__h798488 << IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d13918 ; - assign _theResult___snd__h841227 = - b__h840679[63] ? b___1__h841292 : b__h840679 ; - assign _theResult___snd_fst_exp__h598172 = + assign _theResult___snd__h841223 = + b__h840675[63] ? b___1__h841288 : b__h840675 ; + assign _theResult___snd_fst_exp__h598169 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8227 ? - _theResult___fst_exp__h589587 : - _theResult___fst_exp__h598169 ; - assign _theResult___snd_fst_exp__h615992 = + _theResult___fst_exp__h589584 : + _theResult___fst_exp__h598166 ; + assign _theResult___snd_fst_exp__h615989 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8767 ? - _theResult___fst_exp__h607353 : - _theResult___fst_exp__h615989 ; - assign _theResult___snd_fst_exp__h643921 = + _theResult___fst_exp__h607350 : + _theResult___fst_exp__h615986 ; + assign _theResult___snd_fst_exp__h643918 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9624 ? - _theResult___fst_exp__h635336 : - _theResult___fst_exp__h643918 ; - assign _theResult___snd_fst_exp__h661741 = + _theResult___fst_exp__h635333 : + _theResult___fst_exp__h643915 ; + assign _theResult___snd_fst_exp__h661738 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10164 ? - _theResult___fst_exp__h653102 : - _theResult___fst_exp__h661738 ; - assign _theResult___snd_fst_exp__h689668 = + _theResult___fst_exp__h653099 : + _theResult___fst_exp__h661735 ; + assign _theResult___snd_fst_exp__h689665 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d11021 ? - _theResult___fst_exp__h681083 : - _theResult___fst_exp__h689665 ; - assign _theResult___snd_fst_exp__h707488 = + _theResult___fst_exp__h681080 : + _theResult___fst_exp__h689662 ; + assign _theResult___snd_fst_exp__h707485 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11561 ? - _theResult___fst_exp__h698849 : - _theResult___fst_exp__h707485 ; - assign _theResult___snd_fst_exp__h739981 = + _theResult___fst_exp__h698846 : + _theResult___fst_exp__h707482 ; + assign _theResult___snd_fst_exp__h739977 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12769 ? 11'd0 : - _theResult___fst_exp__h739978 ; - assign _theResult___snd_fst_exp__h758416 = + _theResult___fst_exp__h739974 ; + assign _theResult___snd_fst_exp__h758412 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12905 ? - _theResult___fst_exp__h749629 : - _theResult___fst_exp__h758413 ; - assign _theResult___snd_fst_exp__h778834 = + _theResult___fst_exp__h749625 : + _theResult___fst_exp__h758409 ; + assign _theResult___snd_fst_exp__h778830 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14269 ? 11'd0 : - _theResult___fst_exp__h778831 ; - assign _theResult___snd_fst_exp__h797269 = + _theResult___fst_exp__h778827 ; + assign _theResult___snd_fst_exp__h797265 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14390 ? - _theResult___fst_exp__h788482 : - _theResult___fst_exp__h797266 ; - assign _theResult___snd_fst_exp__h818138 = + _theResult___fst_exp__h788478 : + _theResult___fst_exp__h797262 ; + assign _theResult___snd_fst_exp__h818134 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13499 ? 11'd0 : - _theResult___fst_exp__h818135 ; - assign _theResult___snd_fst_exp__h836573 = + _theResult___fst_exp__h818131 ; + assign _theResult___snd_fst_exp__h836569 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13620 ? - _theResult___fst_exp__h827786 : - _theResult___fst_exp__h836570 ; - assign _theResult___snd_fst_sfd__h573224 = + _theResult___fst_exp__h827782 : + _theResult___fst_exp__h836566 ; + assign _theResult___snd_fst_sfd__h573221 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:34] == 23'd0) ? 23'd2097152 : coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:34] ; - assign _theResult___snd_fst_sfd__h598173 = + assign _theResult___snd_fst_sfd__h598170 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8227 ? - _theResult___fst_sfd__h589588 : - _theResult___fst_sfd__h598170 ; - assign _theResult___snd_fst_sfd__h615993 = + _theResult___fst_sfd__h589585 : + _theResult___fst_sfd__h598167 ; + assign _theResult___snd_fst_sfd__h615990 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8767 ? - _theResult___fst_sfd__h607354 : - _theResult___fst_sfd__h615990 ; - assign _theResult___snd_fst_sfd__h618978 = + _theResult___fst_sfd__h607351 : + _theResult___fst_sfd__h615987 ; + assign _theResult___snd_fst_sfd__h618975 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:34] == 23'd0) ? 23'd2097152 : coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:34] ; - assign _theResult___snd_fst_sfd__h643922 = + assign _theResult___snd_fst_sfd__h643919 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9624 ? - _theResult___fst_sfd__h635337 : - _theResult___fst_sfd__h643919 ; - assign _theResult___snd_fst_sfd__h661742 = + _theResult___fst_sfd__h635334 : + _theResult___fst_sfd__h643916 ; + assign _theResult___snd_fst_sfd__h661739 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10164 ? - _theResult___fst_sfd__h653103 : - _theResult___fst_sfd__h661739 ; - assign _theResult___snd_fst_sfd__h664725 = + _theResult___fst_sfd__h653100 : + _theResult___fst_sfd__h661736 ; + assign _theResult___snd_fst_sfd__h664722 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:34] == 23'd0) ? 23'd2097152 : coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:34] ; - assign _theResult___snd_fst_sfd__h689669 = + assign _theResult___snd_fst_sfd__h689666 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d11021 ? - _theResult___fst_sfd__h681084 : - _theResult___fst_sfd__h689666 ; - assign _theResult___snd_fst_sfd__h707489 = + _theResult___fst_sfd__h681081 : + _theResult___fst_sfd__h689663 ; + assign _theResult___snd_fst_sfd__h707486 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11561 ? - _theResult___fst_sfd__h698850 : - _theResult___fst_sfd__h707486 ; - assign _theResult___snd_fst_sfd__h720148 = - (f1_sfd__h719833 == 23'd0) ? + _theResult___fst_sfd__h698847 : + _theResult___fst_sfd__h707483 ; + assign _theResult___snd_fst_sfd__h720144 = + (f1_sfd__h719829 == 23'd0) ? 52'h4000000000000 : - out___1_sfd__h719896 ; - assign _theResult___snd_fst_sfd__h739982 = + out___1_sfd__h719892 ; + assign _theResult___snd_fst_sfd__h739978 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12769 ? 52'd0 : - _theResult___fst_sfd__h739979 ; - assign _theResult___snd_fst_sfd__h758417 = + _theResult___fst_sfd__h739975 ; + assign _theResult___snd_fst_sfd__h758413 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12905 ? - _theResult___fst_sfd__h749630 : - _theResult___fst_sfd__h758414 ; - assign _theResult___snd_fst_sfd__h759142 = - (f2_sfd__h758827 == 23'd0) ? + _theResult___fst_sfd__h749626 : + _theResult___fst_sfd__h758410 ; + assign _theResult___snd_fst_sfd__h759138 = + (f2_sfd__h758823 == 23'd0) ? 52'h4000000000000 : - out___1_sfd__h758890 ; - assign _theResult___snd_fst_sfd__h778835 = + out___1_sfd__h758886 ; + assign _theResult___snd_fst_sfd__h778831 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14269 ? 52'd0 : - _theResult___fst_sfd__h778832 ; - assign _theResult___snd_fst_sfd__h797270 = + _theResult___fst_sfd__h778828 ; + assign _theResult___snd_fst_sfd__h797266 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14390 ? - _theResult___fst_sfd__h788483 : - _theResult___fst_sfd__h797267 ; - assign _theResult___snd_fst_sfd__h798446 = - (f3_sfd__h798131 == 23'd0) ? + _theResult___fst_sfd__h788479 : + _theResult___fst_sfd__h797263 ; + assign _theResult___snd_fst_sfd__h798442 = + (f3_sfd__h798127 == 23'd0) ? 52'h4000000000000 : - out___1_sfd__h798194 ; - assign _theResult___snd_fst_sfd__h818139 = + out___1_sfd__h798190 ; + assign _theResult___snd_fst_sfd__h818135 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13499 ? 52'd0 : - _theResult___fst_sfd__h818136 ; - assign _theResult___snd_fst_sfd__h836574 = + _theResult___fst_sfd__h818132 ; + assign _theResult___snd_fst_sfd__h836570 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13620 ? - _theResult___fst_sfd__h827787 : - _theResult___fst_sfd__h836571 ; - assign a___1__h840840 = + _theResult___fst_sfd__h827783 : + _theResult___fst_sfd__h836567 ; + assign a___1__h840836 = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd1) ? { 32'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[171:140] } : { {32{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q23[31]}}, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q23 } ; - assign a___1__h841231 = 64'd0 - a__h840678 ; - assign a__h840678 = + assign a___1__h841227 = 64'd0 - a__h840674 ; + assign a__h840674 = coreFix_fpuMulDivExe_0_regToExeQ$first[227] ? - a___1__h840840 : + a___1__h840836 : coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; - assign addBase__h1019550 = - { {48{base__h903652[15]}}, base__h903652 } << + assign addBase__h1019584 = + { {48{base__h903649[15]}}, base__h903649 } << csrf_stcc_reg[33:28] ; - assign addBase__h1019953 = - { {48{base__h860635[15]}}, base__h860635 } << + assign addBase__h1019987 = + { {48{base__h860633[15]}}, base__h860633 } << IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16291 ; - assign addBase__h1020370 = - { {48{base__h903936[15]}}, base__h903936 } << + assign addBase__h1020404 = + { {48{base__h903933[15]}}, base__h903933 } << csrf_mtcc_reg[33:28] ; - assign addBase__h1020773 = - { {48{base__h861628[15]}}, base__h861628 } << + assign addBase__h1020807 = + { {48{base__h861626[15]}}, base__h861626 } << IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16443 ; - assign addBase__h1021443 = - { {48{base__h904281[15]}}, base__h904281 } << + assign addBase__h1021477 = + { {48{base__h904278[15]}}, base__h904278 } << csrf_rg_dpc[33:28] ; - assign addBase__h242757 = - { {48{base__h242592[15]}}, base__h242592 } << + assign addBase__h242754 = + { {48{base__h242589[15]}}, base__h242589 } << coreFix_memExe_regToExeQ$first[265:260] ; - assign addBase__h243914 = - { {48{base__h243749[15]}}, base__h243749 } << + assign addBase__h243911 = + { {48{base__h243746[15]}}, base__h243746 } << coreFix_memExe_regToExeQ$first[102:97] ; - assign addBase__h257535 = - { {48{base__h257370[15]}}, base__h257370 } << + assign addBase__h257532 = + { {48{base__h257367[15]}}, base__h257367 } << coreFix_memExe_dTlb$procResp[334:329] ; - assign addTop__h242866 = - { {50{x__h242965[15]}}, x__h242965 } << + assign addTop__h242863 = + { {50{x__h242962[15]}}, x__h242962 } << coreFix_memExe_regToExeQ$first[265:260] ; - assign addTop__h244023 = - { {50{x__h244122[15]}}, x__h244122 } << + assign addTop__h244020 = + { {50{x__h244119[15]}}, x__h244119 } << coreFix_memExe_regToExeQ$first[102:97] ; - assign addTop__h257644 = - { {50{x__h257743[15]}}, x__h257743 } << + assign addTop__h257641 = + { {50{x__h257740[15]}}, x__h257740 } << coreFix_memExe_dTlb$procResp[334:329] ; - assign addr__h1000333 = + assign addr__h1000330 = (rob$deqPort_0_deq_data[273:272] == 2'd1 && (rob$deqPort_0_deq_data[265:261] == 5'd1 || rob$deqPort_0_deq_data[265:261] == 5'd12)) ? rob$deqPort_0_deq_data[260:197] : rob$deqPort_0_deq_data[191:128] ; - assign addr__h149996 = + assign addr__h149995 = coreFix_memExe_reqLdQ_data_0_lat_0$whas ? coreFix_memExe_reqLdQ_data_0_lat_0$wget[63:0] : coreFix_memExe_reqLdQ_data_0_rl[63:0] ; - assign addr__h153572 = + assign addr__h153571 = CAN_FIRE_RL_coreFix_memExe_doIssueSB ? coreFix_memExe_reqStQ_data_0_lat_0$wget[63:0] : coreFix_memExe_reqStQ_data_0_rl[63:0] ; - assign addr__h238208 = x__h238637[63:0] + csrf_ddc_reg[149:86] ; - assign address__h1010161 = base__h1010122 + { 57'd0, x__h1010320 } ; - assign address__h1010211 = base__h1010176 + { 57'd0, x__h1010320 } ; - assign address__h1010227 = { 2'd0, address__h1010161 } ; - assign address__h1010571 = { 2'd0, base__h1010122 } ; - assign address__h1010884 = { 2'd0, address__h1010211 } ; - assign address__h1011228 = { 2'd0, base__h1010176 } ; - assign address__h1023286 = rob$deqPort_0_deq_data[565:502] + 64'd4 ; - assign address__h874073 = + assign addr__h238205 = x__h238634[63:0] + csrf_ddc_reg[149:86] ; + assign address__h1010195 = base__h1010156 + { 57'd0, x__h1010354 } ; + assign address__h1010245 = base__h1010210 + { 57'd0, x__h1010354 } ; + assign address__h1010261 = { 2'd0, address__h1010195 } ; + assign address__h1010605 = { 2'd0, base__h1010156 } ; + assign address__h1010918 = { 2'd0, address__h1010245 } ; + assign address__h1011262 = { 2'd0, base__h1010210 } ; + assign address__h1023320 = rob$deqPort_0_deq_data[565:502] + 64'd4 ; + assign address__h874071 = coreFix_aluExe_1_regToExeQ$first[241:178] + 64'd4 ; - assign address__h915078 = + assign address__h915075 = coreFix_aluExe_0_regToExeQ$first[241:178] + 64'd4 ; - assign address__h965683 = + assign address__h965680 = fetchStage$pipelines_0_first[526:463] + - { {52{inc__h965682[11]}}, inc__h965682 } ; - assign address__h990659 = + { {52{inc__h965679[11]}}, inc__h965679 } ; + assign address__h990656 = fetchStage$pipelines_1_first[526:463] + - { {52{inc__h990658[11]}}, inc__h990658 } ; - assign b___1__h840841 = + { {52{inc__h990655[11]}}, inc__h990655 } ; + assign b___1__h840837 = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? { {32{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q24[31]}}, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q24 } : { 32'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[107:76] } ; - assign b___1__h841292 = 64'd0 - b__h840679 ; - assign b__h840679 = + assign b___1__h841288 = 64'd0 - b__h840675 ; + assign b__h840675 = coreFix_fpuMulDivExe_0_regToExeQ$first[227] ? - b___1__h840841 : + b___1__h840837 : coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; - assign b__h840826 = { {64{a__h840678[63]}}, a__h840678 } ; - assign b__h840902 = { {64{b__h840679[63]}}, b__h840679 } ; - assign b__h841003 = { 64'd0, a__h840678 } ; - assign b__h841015 = { 64'd0, b__h840679 } ; - assign b_base__h1005869 = + assign b__h840822 = { {64{a__h840674[63]}}, a__h840674 } ; + assign b__h840898 = { {64{b__h840675[63]}}, b__h840675 } ; + assign b__h840999 = { 64'd0, a__h840674 } ; + assign b__h841011 = { 64'd0, b__h840675 } ; + assign b_base__h1005866 = { commitStage_commitTrap[186:176], ~commitStage_commitTrap[175], commitStage_commitTrap[174:173] } ; - assign b_base__h128555 = + assign b_base__h128554 = { coreFix_memExe_respLrScAmoQ_data_0[77:67], ~coreFix_memExe_respLrScAmoQ_data_0[66], coreFix_memExe_respLrScAmoQ_data_0[65:64] } ; - assign b_base__h141699 = + assign b_base__h141698 = { mmio_dataRespQ_data_0[77:67], ~mmio_dataRespQ_data_0[66], mmio_dataRespQ_data_0[65:64] } ; - assign b_base__h185481 = - { x__h185174[77:67], ~x__h185174[66], x__h185174[65:64] } ; - assign b_base__h204544 = - { x__h201338[77:67], ~x__h201338[66], x__h201338[65:64] } ; - assign b_base__h219515 = + assign b_base__h185479 = + { x__h185172[77:67], ~x__h185172[66], x__h185172[65:64] } ; + assign b_base__h204542 = + { x__h201336[77:67], ~x__h201336[66], x__h201336[65:64] } ; + assign b_base__h219513 = { coreFix_memExe_lsq$respLd[77:67], ~coreFix_memExe_lsq$respLd[66], coreFix_memExe_lsq$respLd[65:64] } ; - assign b_base__h873032 = + assign b_base__h873030 = { coreFix_aluExe_1_regToExeQ$first[255:245], ~coreFix_aluExe_1_regToExeQ$first[244], coreFix_aluExe_1_regToExeQ$first[243:242] } ; - assign b_base__h873580 = + assign b_base__h873578 = { coreFix_aluExe_1_regToExeQ$first[126:116], ~coreFix_aluExe_1_regToExeQ$first[115], coreFix_aluExe_1_regToExeQ$first[114:113] } ; - assign b_base__h914073 = + assign b_base__h914070 = { coreFix_aluExe_0_regToExeQ$first[255:245], ~coreFix_aluExe_0_regToExeQ$first[244], coreFix_aluExe_0_regToExeQ$first[243:242] } ; - assign b_base__h914621 = + assign b_base__h914618 = { coreFix_aluExe_0_regToExeQ$first[126:116], ~coreFix_aluExe_0_regToExeQ$first[115], coreFix_aluExe_0_regToExeQ$first[114:113] } ; - assign b_top__h1005868 = + assign b_top__h1005865 = { commitStage_commitTrap[198:190], ~commitStage_commitTrap[189:188], commitStage_commitTrap[187] } ; - assign b_top__h128554 = + assign b_top__h128553 = { coreFix_memExe_respLrScAmoQ_data_0[89:81], ~coreFix_memExe_respLrScAmoQ_data_0[80:79], coreFix_memExe_respLrScAmoQ_data_0[78] } ; - assign b_top__h141698 = + assign b_top__h141697 = { mmio_dataRespQ_data_0[89:81], ~mmio_dataRespQ_data_0[80:79], mmio_dataRespQ_data_0[78] } ; - assign b_top__h185480 = - { x__h185174[89:81], ~x__h185174[80:79], x__h185174[78] } ; - assign b_top__h204543 = - { x__h201338[89:81], ~x__h201338[80:79], x__h201338[78] } ; - assign b_top__h219514 = + assign b_top__h185478 = + { x__h185172[89:81], ~x__h185172[80:79], x__h185172[78] } ; + assign b_top__h204541 = + { x__h201336[89:81], ~x__h201336[80:79], x__h201336[78] } ; + assign b_top__h219512 = { coreFix_memExe_lsq$respLd[89:81], ~coreFix_memExe_lsq$respLd[80:79], coreFix_memExe_lsq$respLd[78] } ; - assign b_top__h873031 = + assign b_top__h873029 = { coreFix_aluExe_1_regToExeQ$first[267:259], ~coreFix_aluExe_1_regToExeQ$first[258:257], coreFix_aluExe_1_regToExeQ$first[256] } ; - assign b_top__h873579 = + assign b_top__h873577 = { coreFix_aluExe_1_regToExeQ$first[138:130], ~coreFix_aluExe_1_regToExeQ$first[129:128], coreFix_aluExe_1_regToExeQ$first[127] } ; - assign b_top__h914072 = + assign b_top__h914069 = { coreFix_aluExe_0_regToExeQ$first[267:259], ~coreFix_aluExe_0_regToExeQ$first[258:257], coreFix_aluExe_0_regToExeQ$first[256] } ; - assign b_top__h914620 = + assign b_top__h914617 = { coreFix_aluExe_0_regToExeQ$first[138:130], ~coreFix_aluExe_0_regToExeQ$first[129:128], coreFix_aluExe_0_regToExeQ$first[127] } ; - assign base__h1008307 = - { (IF_INV_commitStage_commitTrap_2639_BITS_217_TO_ETC___d23037 == - IF_INV_commitStage_commitTrap_2639_BITS_217_TO_ETC___d23039) ? + assign base__h1008341 = + { (IF_INV_commitStage_commitTrap_2639_BITS_217_TO_ETC___d23038 == + IF_INV_commitStage_commitTrap_2639_BITS_217_TO_ETC___d23040) ? 2'd0 : - ((IF_INV_commitStage_commitTrap_2639_BITS_217_TO_ETC___d23037 && - !IF_INV_commitStage_commitTrap_2639_BITS_217_TO_ETC___d23039) ? + ((IF_INV_commitStage_commitTrap_2639_BITS_217_TO_ETC___d23038 && + !IF_INV_commitStage_commitTrap_2639_BITS_217_TO_ETC___d23040) ? 2'd1 : 2'd3), - x__h1005862 } ; - assign base__h1010122 = { csrf_stcc_reg[149:88], 2'b0 } ; - assign base__h1010176 = { csrf_mtcc_reg[149:88], 2'b0 } ; - assign base__h242592 = + x__h1005859 } ; + assign base__h1010156 = { csrf_stcc_reg[149:88], 2'b0 } ; + assign base__h1010210 = { csrf_mtcc_reg[149:88], 2'b0 } ; + assign base__h242589 = { coreFix_memExe_regToExeQ$first[223:222], coreFix_memExe_regToExeQ$first[245:232] } ; - assign base__h243749 = + assign base__h243746 = { coreFix_memExe_regToExeQ$first[60:59], coreFix_memExe_regToExeQ$first[82:69] } ; - assign base__h257370 = + assign base__h257367 = { coreFix_memExe_dTlb$procResp[292:291], coreFix_memExe_dTlb$procResp[314:301] } ; - assign base__h860635 = + assign base__h860633 = { (IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16278 == IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16280) ? 2'd0 : @@ -33205,7 +33230,7 @@ module mkCore(CLK, 2'd1 : 2'd3), IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16275 } ; - assign base__h861628 = + assign base__h861626 = { (IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16430 == IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16432) ? 2'd0 : @@ -33214,7 +33239,7 @@ module mkCore(CLK, 2'd1 : 2'd3), IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16427 } ; - assign base__h903652 = + assign base__h903649 = { (csrf_stcc_reg_read__6237_BITS_13_TO_11_6240_UL_ETC___d16242 == csrf_stcc_reg_read__6237_BITS_85_TO_83_6243_UL_ETC___d16244) ? 2'd0 : @@ -33223,7 +33248,7 @@ module mkCore(CLK, 2'd1 : 2'd3), csrf_stcc_reg[13:0] } ; - assign base__h903936 = + assign base__h903933 = { (csrf_mtcc_reg_read__6389_BITS_13_TO_11_6392_UL_ETC___d16394 == csrf_mtcc_reg_read__6389_BITS_85_TO_83_6395_UL_ETC___d16396) ? 2'd0 : @@ -33232,7 +33257,7 @@ module mkCore(CLK, 2'd1 : 2'd3), csrf_mtcc_reg[13:0] } ; - assign base__h904281 = + assign base__h904278 = { (csrf_rg_dpc_read__6534_BITS_13_TO_11_6537_ULT__ETC___d16539 == csrf_rg_dpc_read__6534_BITS_85_TO_83_6540_ULT__ETC___d16541) ? 2'd0 : @@ -33241,47 +33266,47 @@ module mkCore(CLK, 2'd1 : 2'd3), csrf_rg_dpc[13:0] } ; - assign bot__h1019553 = - { csrf_stcc_reg[149:100] & highBitsfilter__h1019337, 14'd0 } + - addBase__h1019550 ; - assign bot__h1019956 = + assign bot__h1019587 = + { csrf_stcc_reg[149:100] & highBitsfilter__h1019371, 14'd0 } + + addBase__h1019584 ; + assign bot__h1019990 = { IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16295[63:14] & - highBitsfilter__h1019740, + highBitsfilter__h1019774, 14'd0 } + - addBase__h1019953 ; - assign bot__h1020373 = - { csrf_mtcc_reg[149:100] & highBitsfilter__h1020157, 14'd0 } + - addBase__h1020370 ; - assign bot__h1020776 = + addBase__h1019987 ; + assign bot__h1020407 = + { csrf_mtcc_reg[149:100] & highBitsfilter__h1020191, 14'd0 } + + addBase__h1020404 ; + assign bot__h1020810 = { IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16447[63:14] & - highBitsfilter__h1020560, + highBitsfilter__h1020594, 14'd0 } + - addBase__h1020773 ; - assign bot__h1021446 = - { csrf_rg_dpc[149:100] & highBitsfilter__h1021229, 14'd0 } + - addBase__h1021443 ; - assign carry_out__h1005773 = - (topBits__h1005771 < x__h1005862[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h128459 = - (topBits__h128457 < x__h128548[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h141603 = - (topBits__h141601 < x__h141692[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h185385 = - (topBits__h185383 < x__h185474[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h204448 = - (topBits__h204446 < x__h204537[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h219419 = - (topBits__h219417 < x__h219508[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h872935 = - (topBits__h872933 < x__h873025[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h873483 = - (topBits__h873481 < x__h873573[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h913976 = - (topBits__h913974 < x__h914066[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h914524 = - (topBits__h914522 < x__h914614[11:0]) ? 2'b01 : 2'b0 ; - assign cause_code__h1007591 = { 1'd0, i__h1006243 } ; - assign cause_interrupt__h1006051 = + addBase__h1020807 ; + assign bot__h1021480 = + { csrf_rg_dpc[149:100] & highBitsfilter__h1021263, 14'd0 } + + addBase__h1021477 ; + assign carry_out__h1005770 = + (topBits__h1005768 < x__h1005859[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h128458 = + (topBits__h128456 < x__h128547[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h141602 = + (topBits__h141600 < x__h141691[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h185383 = + (topBits__h185381 < x__h185472[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h204446 = + (topBits__h204444 < x__h204535[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h219417 = + (topBits__h219415 < x__h219506[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h872933 = + (topBits__h872931 < x__h873023[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h873481 = + (topBits__h873479 < x__h873571[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h913973 = + (topBits__h913971 < x__h914063[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h914521 = + (topBits__h914519 < x__h914611[11:0]) ? 2'b01 : 2'b0 ; + assign cause_code__h1007625 = { 1'd0, i__h1006266 } ; + assign cause_interrupt__h1006048 = commitStage_commitTrap[44:43] != 2'd1 && commitStage_commitTrap[44:43] != 2'd0 ; assign commitStage_commitTrap_2639_BITS_44_TO_43_2837_ETC___d22877 = @@ -33365,7 +33390,7 @@ module mkCore(CLK, IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19446, IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19638, coreFix_aluExe_0_dispToRegQ$first[124] ? - repBound__h908308 : + repBound__h908305 : 3'd7, NOT_coreFix_aluExe_0_dispToRegQ_first__8612_BI_ETC___d19678 } ; assign coreFix_aluExe_0_exeToFinQ_first__0233_BITS_14_ETC___d20267 = @@ -33427,7 +33452,7 @@ module mkCore(CLK, IF_coreFix_aluExe_1_dispToRegQ_first__5790_BIT_ETC___d17009, IF_coreFix_aluExe_1_dispToRegQ_first__5790_BIT_ETC___d17445, coreFix_aluExe_1_dispToRegQ$first[124] ? - repBound__h866972 : + repBound__h866970 : 3'd7, NOT_coreFix_aluExe_1_dispToRegQ_first__5790_BI_ETC___d17503 } ; assign coreFix_aluExe_1_exeToFinQ_first__8058_BITS_14_ETC___d18093 = @@ -33503,7 +33528,7 @@ module mkCore(CLK, assign coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q84 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] - 11'd1023 ; - assign coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q41 = + assign coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q49 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] - 11'd1023 ; assign coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q119 = @@ -33539,56 +33564,6 @@ module mkCore(CLK, rob$RDY_setExecuted_doFinishFpuMulDiv_0_set && coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_first_data && coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$EMPTY_N ; - assign coreFix_fpuMulDivExe_0_regToExeQ_first__2628_B_ETC___d15109 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || - coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd26 || - coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || - coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && - NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15064 | - ((f3_exp__h798130 != 8'd255 || f3_sfd__h798131 == 23'd0) && - (f3_exp__h798130 != 8'd255 || f3_sfd__h798131 != 23'd0) && - (f3_exp__h798130 != 8'd0 || f3_sfd__h798131 != 23'd0) && - IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15104) ; - assign coreFix_fpuMulDivExe_0_regToExeQ_first__2628_B_ETC___d15145 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || - coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd26 || - coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || - coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && - NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15133 | - ((f3_exp__h798130 != 8'd255 || f3_sfd__h798131 == 23'd0) && - (f3_exp__h798130 != 8'd255 || f3_sfd__h798131 != 23'd0) && - (f3_exp__h798130 != 8'd0 || f3_sfd__h798131 != 23'd0) && - IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15140) ; - assign coreFix_fpuMulDivExe_0_regToExeQ_first__2628_B_ETC___d15193 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || - coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd26 || - coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || - coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && - NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15177 | - ((f3_exp__h798130 != 8'd255 || f3_sfd__h798131 == 23'd0) && - (f3_exp__h798130 != 8'd255 || f3_sfd__h798131 != 23'd0) && - (f3_exp__h798130 != 8'd0 || f3_sfd__h798131 != 23'd0) && - IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15188) ; - assign coreFix_fpuMulDivExe_0_regToExeQ_first__2628_B_ETC___d15235 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || - coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd26 || - coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || - coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && - NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15221 | - ((f3_exp__h798130 != 8'd255 || f3_sfd__h798131 == 23'd0) && - (f3_exp__h798130 != 8'd255 || f3_sfd__h798131 != 23'd0) && - (f3_exp__h798130 != 8'd0 || f3_sfd__h798131 != 23'd0) && - IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15230) ; - assign coreFix_fpuMulDivExe_0_regToExeQ_first__2628_B_ETC___d15277 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || - coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd26 || - coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || - coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && - NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15263 | - ((f3_exp__h798130 != 8'd255 || f3_sfd__h798131 == 23'd0) && - (f3_exp__h798130 != 8'd255 || f3_sfd__h798131 != 23'd0) && - (f3_exp__h798130 != 8'd0 || f3_sfd__h798131 != 23'd0) && - IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15272) ; assign coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q24 = coreFix_fpuMulDivExe_0_regToExeQ$first[107:76] ; assign coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q23 = @@ -33632,7 +33607,7 @@ module mkCore(CLK, !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5046 && coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58] && coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[57:0] == - y__h426316 ; + y__h426314 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_pi_ETC___d5655 = coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == 3'd3 && @@ -35838,12 +35813,12 @@ module mkCore(CLK, assign coreFix_memExe_dTlb_procResp__276_BITS_334_TO__ETC___d4439 = coreFix_memExe_dTlb$procResp[334:329] < 6'd51 && coreFix_memExe_dTlb_procResp__276_BITS_452_TO__ETC___d4426[64:63] - - { 1'd0, x__h257812 } > + { 1'd0, x__h257809 } > 2'd1 ; assign coreFix_memExe_dTlb_procResp__276_BITS_452_TO__ETC___d4426 = - { coreFix_memExe_dTlb$procResp[452:401] & mask__h257645, + { coreFix_memExe_dTlb$procResp[452:401] & mask__h257642, 14'd0 } + - addTop__h257644 ; + addTop__h257641 ; assign coreFix_memExe_dTlb_procResp__276_BITS_490_TO__ETC___d4784 = coreFix_memExe_dTlb$procResp[490:488] == 3'd0 && NOT_coreFix_memExe_dTlb_procResp__276_BITS_560_ETC___d4600 && @@ -35894,15 +35869,15 @@ module mkCore(CLK, 66'd0, IF_coreFix_memExe_dispToRegQ_first__695_BIT_10_ETC___d3599 } ; assign coreFix_memExe_lsq_getOrigBE_coreFix_memExe_re_ETC___d4269 = - { coreFix_memExe_lsq$getOrigBE << pointer__h245528[3:0], - (highOffsetBits__h245537 == 50'd0 && + { coreFix_memExe_lsq$getOrigBE << pointer__h245525[3:0], + (highOffsetBits__h245534 == 50'd0 && IF_SEXT_coreFix_memExe_regToExeQ_first__664_BI_ETC___d4114 || coreFix_memExe_regToExeQ$first[265:260] >= 6'd50) && coreFix_memExe_regToExeQ$first[384], - result_d_address__h245739, - x__h251010[13:0], + result_d_address__h245736, + x__h251007[13:0], coreFix_memExe_regToExeQ$first[303:232], - repBound__h251108, + repBound__h251105, coreFix_memExe_regToExeQ_first__664_BITS_259_T_ETC___d4129, coreFix_memExe_regToExeQ_first__664_BITS_245_T_ETC___d4130, coreFix_memExe_regToExeQ_first__664_BITS_383_T_ETC___d4142, @@ -35923,7 +35898,7 @@ module mkCore(CLK, assign coreFix_memExe_regToExeQ_first__664_BITS_102_T_ETC___d3798 = coreFix_memExe_regToExeQ$first[102:97] < 6'd51 && coreFix_memExe_regToExeQ_first__664_BITS_220_T_ETC___d3785[64:63] - - { 1'd0, x__h244191 } > + { 1'd0, x__h244188 } > 2'd1 ; assign coreFix_memExe_regToExeQ_first__664_BITS_140_T_ETC___d4089 = { coreFix_memExe_regToExeQ$first[140:125], @@ -35936,26 +35911,26 @@ module mkCore(CLK, ~IF_coreFix_memExe_regToExeQ_first__664_BIT_103_ETC___d4036[2], IF_coreFix_memExe_regToExeQ_first__664_BIT_103_ETC___d4036[1:0], coreFix_memExe_regToExeQ$first[218:155] } << - x__h247568 ; + x__h247565 ; assign coreFix_memExe_regToExeQ_first__664_BITS_220_T_ETC___d3785 = - { coreFix_memExe_regToExeQ$first[220:169] & mask__h244024, + { coreFix_memExe_regToExeQ$first[220:169] & mask__h244021, 14'd0 } + - addTop__h244023 ; + addTop__h244020 ; assign coreFix_memExe_regToExeQ_first__664_BITS_245_T_ETC___d4130 = - coreFix_memExe_regToExeQ$first[245:243] < repBound__h251108 ; + coreFix_memExe_regToExeQ$first[245:243] < repBound__h251105 ; assign coreFix_memExe_regToExeQ_first__664_BITS_259_T_ETC___d4129 = - coreFix_memExe_regToExeQ$first[259:257] < repBound__h251108 ; + coreFix_memExe_regToExeQ$first[259:257] < repBound__h251105 ; assign coreFix_memExe_regToExeQ_first__664_BITS_265_T_ETC___d3736 = coreFix_memExe_regToExeQ$first[265:260] < 6'd51 && coreFix_memExe_regToExeQ_first__664_BITS_383_T_ETC___d3723[64:63] - - { 1'd0, x__h243034 } > + { 1'd0, x__h243031 } > 2'd1 ; assign coreFix_memExe_regToExeQ_first__664_BITS_383_T_ETC___d3723 = - { coreFix_memExe_regToExeQ$first[383:332] & mask__h242867, + { coreFix_memExe_regToExeQ$first[383:332] & mask__h242864, 14'd0 } + - addTop__h242866 ; + addTop__h242863 ; assign coreFix_memExe_regToExeQ_first__664_BITS_383_T_ETC___d4132 = - x__h251010[13:11] < repBound__h251108 ; + x__h251007[13:11] < repBound__h251105 ; assign coreFix_memExe_regToExeQ_first__664_BITS_383_T_ETC___d4142 = { coreFix_memExe_regToExeQ_first__664_BITS_383_T_ETC___d4132, (coreFix_memExe_regToExeQ_first__664_BITS_259_T_ETC___d4129 == @@ -35988,48 +35963,48 @@ module mkCore(CLK, coreFix_memExe_regToExeQ$first[434:403] ; assign coreFix_memExe_regToExeQfirst_BITS_60_TO_59__q4 = coreFix_memExe_regToExeQ$first[60:59] ; - assign coreFix_memExe_stb_isEmpty__188_AND_coreFix_me_ETC___d23403 = + assign coreFix_memExe_stb_isEmpty__188_AND_coreFix_me_ETC___d23405 = coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty && - rob$RDY_deqPort_0_deq && - rob$RDY_deqPort_0_deq_data && regRenamingTable$RDY_commit_0_commit && + rob$RDY_deqPort_0_deq_data && + rob$RDY_deqPort_0_deq && fetchStage$iTlbIfc_noPendingReq && coreFix_memExe_dTlb$noPendingReq && - NOT_rob_deqPort_0_deq_data__2632_BITS_469_TO_4_ETC___d23398 ; - assign cr_addrBits__h872618 = + NOT_rob_deqPort_0_deq_data__2632_BITS_469_TO_4_ETC___d23400 ; + assign cr_addrBits__h872616 = INV_coreFix_aluExe_1_regToExeQfirst_BITS_286__ETC__q11[0] ? - x__h872794[13:0] : + x__h872792[13:0] : coreFix_aluExe_1_regToExeQ$first[191:178] ; - assign cr_addrBits__h873166 = + assign cr_addrBits__h873164 = INV_coreFix_aluExe_1_regToExeQfirst_BITS_157__ETC__q12[0] ? - x__h873342[13:0] : + x__h873340[13:0] : coreFix_aluExe_1_regToExeQ$first[62:49] ; - assign cr_addrBits__h913659 = + assign cr_addrBits__h913656 = INV_coreFix_aluExe_0_regToExeQfirst_BITS_286__ETC__q13[0] ? - x__h913835[13:0] : + x__h913832[13:0] : coreFix_aluExe_0_regToExeQ$first[191:178] ; - assign cr_addrBits__h914207 = + assign cr_addrBits__h914204 = INV_coreFix_aluExe_0_regToExeQfirst_BITS_157__ETC__q14[0] ? - x__h914383[13:0] : + x__h914380[13:0] : coreFix_aluExe_0_regToExeQ$first[62:49] ; - assign cr_address__h872617 = + assign cr_address__h872615 = { 2'd0, coreFix_aluExe_1_regToExeQ$first[241:178] } ; - assign cr_address__h873165 = + assign cr_address__h873163 = { 2'd0, coreFix_aluExe_1_regToExeQ$first[112:49] } ; - assign cr_address__h913658 = + assign cr_address__h913655 = { 2'd0, coreFix_aluExe_0_regToExeQ$first[241:178] } ; - assign cr_address__h914206 = + assign cr_address__h914203 = { 2'd0, coreFix_aluExe_0_regToExeQ$first[112:49] } ; - assign cr_flags__h873168 = coreFix_aluExe_1_regToExeQ$first[158] ; - assign cr_flags__h914209 = coreFix_aluExe_0_regToExeQ$first[158] ; - assign cr_reserved__h873169 = coreFix_aluExe_1_regToExeQ$first[160:159] ; - assign cr_reserved__h914210 = coreFix_aluExe_0_regToExeQ$first[160:159] ; + assign cr_flags__h873166 = coreFix_aluExe_1_regToExeQ$first[158] ; + assign cr_flags__h914206 = coreFix_aluExe_0_regToExeQ$first[158] ; + assign cr_reserved__h873167 = coreFix_aluExe_1_regToExeQ$first[160:159] ; + assign cr_reserved__h914207 = coreFix_aluExe_0_regToExeQ$first[160:159] ; assign csrf_ddc_reg_read__078_BITS_13_TO_11_159_ULT_c_ETC___d4163 = - csrf_ddc_reg[13:11] < repBound__h251633 ; + csrf_ddc_reg[13:11] < repBound__h251630 ; assign csrf_ddc_reg_read__078_BITS_27_TO_25_161_ULT_c_ETC___d4162 = - csrf_ddc_reg[27:25] < repBound__h251633 ; + csrf_ddc_reg[27:25] < repBound__h251630 ; assign csrf_ddc_reg_read__078_BITS_85_TO_83_164_ULT_c_ETC___d4165 = - csrf_ddc_reg[85:83] < repBound__h251633 ; + csrf_ddc_reg[85:83] < repBound__h251630 ; assign csrf_ddc_reg_read__078_BITS_85_TO_83_164_ULT_c_ETC___d4175 = { csrf_ddc_reg_read__078_BITS_85_TO_83_164_ULT_c_ETC___d4165, (csrf_ddc_reg_read__078_BITS_27_TO_25_161_ULT_c_ETC___d4162 == @@ -36086,79 +36061,76 @@ module mkCore(CLK, csrf_tw_reg && csrf_prv_reg != 2'd3 ; assign csrf_mtcc_reg_read__6389_BITS_13_TO_11_6392_UL_ETC___d16394 = - csrf_mtcc_reg[13:11] < repBound__h861484 ; - assign csrf_mtcc_reg_read__6389_BITS_149_TO_86_3187_A_ETC___d23190 = - csrf_mtcc_reg[149:86] & mask__h1010890 ; - assign csrf_mtcc_reg_read__6389_BITS_149_TO_86_3187_A_ETC___d23197 = - newAddrDiff__h1010891 == mask__h1010890 ; - assign csrf_mtcc_reg_read__6389_BITS_149_TO_86_3187_A_ETC___d23225 = - newAddrDiff__h1011235 == mask__h1010890 ; + csrf_mtcc_reg[13:11] < repBound__h861482 ; + assign csrf_mtcc_reg_read__6389_BITS_149_TO_86_3189_A_ETC___d23192 = + csrf_mtcc_reg[149:86] & mask__h1010924 ; + assign csrf_mtcc_reg_read__6389_BITS_149_TO_86_3189_A_ETC___d23199 = + newAddrDiff__h1010925 == mask__h1010924 ; + assign csrf_mtcc_reg_read__6389_BITS_149_TO_86_3189_A_ETC___d23227 = + newAddrDiff__h1011269 == mask__h1010924 ; assign csrf_mtcc_reg_read__6389_BITS_85_TO_83_6395_UL_ETC___d16396 = - csrf_mtcc_reg[85:83] < repBound__h861484 ; - assign csrf_prv_reg_read__0574_ULE_1_2990_AND_IF_comm_ETC___d23023 = + csrf_mtcc_reg[85:83] < repBound__h861482 ; + assign csrf_prv_reg_read__0574_ULE_1_2990_AND_IF_comm_ETC___d23024 = csrf_prv_reg_read__0574_ULE_1___d22990 && - ((commitStage_commitTrap[44:43] == 2'd1) ? - _0b0_CONCAT_csrf_medeleg_28_26_reg_read__6352_6_ETC___d23018 : - commitStage_commitTrap[44:43] != 2'd0 && - _0b0_CONCAT_csrf_mideleg_11_reg_read__6363_6364_ETC___d23020) ; + CASE_commitStage_commitTrap_BITS_44_TO_43_0_cs_ETC__q276 ; assign csrf_prv_reg_read__0574_ULE_1___d22990 = csrf_prv_reg <= 2'd1 ; assign csrf_rg_dpc_read__6534_BITS_13_TO_11_6537_ULT__ETC___d16539 = - csrf_rg_dpc[13:11] < repBound__h862314 ; + csrf_rg_dpc[13:11] < repBound__h862312 ; assign csrf_rg_dpc_read__6534_BITS_85_TO_83_6540_ULT__ETC___d16541 = - csrf_rg_dpc[85:83] < repBound__h862314 ; + csrf_rg_dpc[85:83] < repBound__h862312 ; assign csrf_stcc_reg_read__6237_BITS_13_TO_11_6240_UL_ETC___d16242 = - csrf_stcc_reg[13:11] < repBound__h860491 ; - assign csrf_stcc_reg_read__6237_BITS_149_TO_86_3116_A_ETC___d23119 = - csrf_stcc_reg[149:86] & mask__h1010233 ; - assign csrf_stcc_reg_read__6237_BITS_149_TO_86_3116_A_ETC___d23128 = - newAddrDiff__h1010234 == mask__h1010233 ; - assign csrf_stcc_reg_read__6237_BITS_149_TO_86_3116_A_ETC___d23156 = - newAddrDiff__h1010578 == mask__h1010233 ; + csrf_stcc_reg[13:11] < repBound__h860489 ; + assign csrf_stcc_reg_read__6237_BITS_149_TO_86_3118_A_ETC___d23121 = + csrf_stcc_reg[149:86] & mask__h1010267 ; + assign csrf_stcc_reg_read__6237_BITS_149_TO_86_3118_A_ETC___d23130 = + newAddrDiff__h1010268 == mask__h1010267 ; + assign csrf_stcc_reg_read__6237_BITS_149_TO_86_3118_A_ETC___d23158 = + newAddrDiff__h1010612 == mask__h1010267 ; assign csrf_stcc_reg_read__6237_BITS_85_TO_83_6243_UL_ETC___d16244 = - csrf_stcc_reg[85:83] < repBound__h860491 ; - assign data09497_BITS_31_TO_0__q22 = data__h709497[31:0] ; - assign data10443_BITS_31_TO_0__q27 = data__h710443[31:0] ; - assign data___1__h710035 = - { {32{data09497_BITS_31_TO_0__q22[31]}}, - data09497_BITS_31_TO_0__q22 } ; - assign data___1__h710981 = - { {32{data10443_BITS_31_TO_0__q27[31]}}, - data10443_BITS_31_TO_0__q27 } ; - assign data__h572105 = + csrf_stcc_reg[85:83] < repBound__h860489 ; + assign data09494_BITS_31_TO_0__q22 = data__h709494[31:0] ; + assign data10440_BITS_31_TO_0__q27 = data__h710440[31:0] ; + assign data___1__h710032 = + { {32{data09494_BITS_31_TO_0__q22[31]}}, + data09494_BITS_31_TO_0__q22 } ; + assign data___1__h710978 = + { {32{data10440_BITS_31_TO_0__q27[31]}}, + data10440_BITS_31_TO_0__q27 } ; + assign data__h572102 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[39] ? - res_data__h572668 : - res_data__h572663 ; - assign data__h617865 = + res_data__h572665 : + res_data__h572660 ; + assign data__h617862 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[39] ? - res_data__h618422 : - res_data__h618417 ; - assign data__h663612 = + res_data__h618419 : + res_data__h618414 ; + assign data__h663609 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[39] ? - res_data__h664169 : - res_data__h664164 ; - assign data__h709497 = + res_data__h664166 : + res_data__h664161 ; + assign data__h709494 = (coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[35:34] == 2'd0) ? coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_OUT[63:0] : coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_OUT[127:64] ; - assign data__h709528 = + assign data__h709525 = coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[33] ? - data___1__h710035 : - data__h709497 ; - assign data__h710443 = + data___1__h710032 : + data__h709494 ; + assign data__h710440 = (coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[35:34] == 2'd2) ? - x_quotient__h710245 : - x_remainder__h710246 ; - assign data__h710474 = + x_quotient__h710242 : + x_remainder__h710243 ; + assign data__h710471 = coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[33] ? - data___1__h710981 : - data__h710443 ; - assign data_addrBits__h1030200 = { 2'd0, f_gpr_reqs$D_OUT[63:52] } ; - assign data_addrBits__h1031054 = { 2'b0, f_fpr_reqs$D_OUT[63:52] } ; - assign data_address__h1030199 = { 2'd0, f_gpr_reqs$D_OUT[63:0] } ; - assign data_address__h1031053 = { 2'd0, f_fpr_reqs$D_OUT[63:0] } ; - assign dcsr_cause__h1005097 = + data___1__h710978 : + data__h710440 ; + assign data_addrBits__h1030233 = { 2'd0, f_gpr_reqs$D_OUT[63:52] } ; + assign data_addrBits__h1031087 = { 2'b0, f_fpr_reqs$D_OUT[63:52] } ; + assign data_address__h1030232 = { 2'd0, f_gpr_reqs$D_OUT[63:0] } ; + assign data_address__h1031086 = { 2'd0, f_fpr_reqs$D_OUT[63:0] } ; + assign dcsr_cause__h1005094 = (commitStage_commitTrap[44:43] != 2'd0 && commitStage_commitTrap[44:43] != 2'd1 && commitStage_commitTrap[35:32] == 4'd14) ? @@ -36177,98 +36149,98 @@ module mkCore(CLK, commitStage_commitTrap[35:32] != 4'd14) ? 3'd4 : 3'd1) ; - assign din_inc___2_exp__h616023 = _theResult___fst_exp__h588990 + 8'd1 ; - assign din_inc___2_exp__h616047 = _theResult___fst_exp__h597646 + 8'd1 ; - assign din_inc___2_exp__h616077 = _theResult___fst_exp__h606756 + 8'd1 ; - assign din_inc___2_exp__h616101 = _theResult___fst_exp__h615441 + 8'd1 ; - assign din_inc___2_exp__h661772 = _theResult___fst_exp__h634739 + 8'd1 ; - assign din_inc___2_exp__h661796 = _theResult___fst_exp__h643395 + 8'd1 ; - assign din_inc___2_exp__h661826 = _theResult___fst_exp__h652505 + 8'd1 ; - assign din_inc___2_exp__h661850 = _theResult___fst_exp__h661190 + 8'd1 ; - assign din_inc___2_exp__h707519 = _theResult___fst_exp__h680486 + 8'd1 ; - assign din_inc___2_exp__h707543 = _theResult___fst_exp__h689142 + 8'd1 ; - assign din_inc___2_exp__h707573 = _theResult___fst_exp__h698252 + 8'd1 ; - assign din_inc___2_exp__h707597 = _theResult___fst_exp__h706937 + 8'd1 ; - assign din_inc___2_exp__h758470 = _theResult___fst_exp__h739220 + 11'd1 ; - assign din_inc___2_exp__h758505 = _theResult___fst_exp__h748797 + 11'd1 ; - assign din_inc___2_exp__h758531 = _theResult___fst_exp__h757630 + 11'd1 ; - assign din_inc___2_exp__h797323 = _theResult___fst_exp__h778073 + 11'd1 ; - assign din_inc___2_exp__h797358 = _theResult___fst_exp__h787650 + 11'd1 ; - assign din_inc___2_exp__h797384 = _theResult___fst_exp__h796483 + 11'd1 ; - assign din_inc___2_exp__h836627 = _theResult___fst_exp__h817377 + 11'd1 ; - assign din_inc___2_exp__h836662 = _theResult___fst_exp__h826954 + 11'd1 ; - assign din_inc___2_exp__h836688 = _theResult___fst_exp__h835787 + 11'd1 ; - assign enabled_ints___1__h929511 = pend_ints__h928984 & y__h929523 ; - assign enabled_ints__h929557 = - pend_ints__h928984 & - { r1__read_BITS_13_TO_0___h929533, csrf_mideleg_1_0_reg } ; - assign f1_exp19832_MINUS_127__q148 = f1_exp__h719832 - 8'd127 ; - assign f1_exp__h719832 = + assign din_inc___2_exp__h616020 = _theResult___fst_exp__h588987 + 8'd1 ; + assign din_inc___2_exp__h616044 = _theResult___fst_exp__h597643 + 8'd1 ; + assign din_inc___2_exp__h616074 = _theResult___fst_exp__h606753 + 8'd1 ; + assign din_inc___2_exp__h616098 = _theResult___fst_exp__h615438 + 8'd1 ; + assign din_inc___2_exp__h661769 = _theResult___fst_exp__h634736 + 8'd1 ; + assign din_inc___2_exp__h661793 = _theResult___fst_exp__h643392 + 8'd1 ; + assign din_inc___2_exp__h661823 = _theResult___fst_exp__h652502 + 8'd1 ; + assign din_inc___2_exp__h661847 = _theResult___fst_exp__h661187 + 8'd1 ; + assign din_inc___2_exp__h707516 = _theResult___fst_exp__h680483 + 8'd1 ; + assign din_inc___2_exp__h707540 = _theResult___fst_exp__h689139 + 8'd1 ; + assign din_inc___2_exp__h707570 = _theResult___fst_exp__h698249 + 8'd1 ; + assign din_inc___2_exp__h707594 = _theResult___fst_exp__h706934 + 8'd1 ; + assign din_inc___2_exp__h758466 = _theResult___fst_exp__h739216 + 11'd1 ; + assign din_inc___2_exp__h758501 = _theResult___fst_exp__h748793 + 11'd1 ; + assign din_inc___2_exp__h758527 = _theResult___fst_exp__h757626 + 11'd1 ; + assign din_inc___2_exp__h797319 = _theResult___fst_exp__h778069 + 11'd1 ; + assign din_inc___2_exp__h797354 = _theResult___fst_exp__h787646 + 11'd1 ; + assign din_inc___2_exp__h797380 = _theResult___fst_exp__h796479 + 11'd1 ; + assign din_inc___2_exp__h836623 = _theResult___fst_exp__h817373 + 11'd1 ; + assign din_inc___2_exp__h836658 = _theResult___fst_exp__h826950 + 11'd1 ; + assign din_inc___2_exp__h836684 = _theResult___fst_exp__h835783 + 11'd1 ; + assign enabled_ints___1__h929508 = pend_ints__h928981 & y__h929520 ; + assign enabled_ints__h929554 = + pend_ints__h928981 & + { r1__read_BITS_13_TO_0___h929530, csrf_mideleg_1_0_reg } ; + assign f1_exp19828_MINUS_127__q148 = f1_exp__h719828 - 8'd127 ; + assign f1_exp__h719828 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] : 8'd255 ; - assign f1_sfd__h719833 = + assign f1_sfd__h719829 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] : 23'd4194304 ; - assign f2_exp58826_MINUS_127__q188 = f2_exp__h758826 - 8'd127 ; - assign f2_exp__h758826 = + assign f2_exp58822_MINUS_127__q188 = f2_exp__h758822 - 8'd127 ; + assign f2_exp__h758822 = (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] : 8'd255 ; - assign f2_sfd__h758827 = + assign f2_sfd__h758823 = (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] : 23'd4194304 ; - assign f3_exp98130_MINUS_127__q165 = f3_exp__h798130 - 8'd127 ; - assign f3_exp__h798130 = + assign f3_exp98126_MINUS_127__q165 = f3_exp__h798126 - 8'd127 ; + assign f3_exp__h798126 = (coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] : 8'd255 ; - assign f3_sfd__h798131 = + assign f3_sfd__h798127 = (coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] : 23'd4194304 ; - assign f_csr_reqs_first__4359_BITS_63_TO_14_4512_XOR__ETC___d24526 = - (highOffsetBits__h1042906 == 50'd0 && - IF_f_csr_reqs_first__4359_BIT_63_4513_THEN_NOT_ETC___d24523 || - NOT_csrf_stcc_reg_read__6237_BITS_33_TO_28_625_ETC___d23115) && + assign f_csr_reqs_first__4361_BITS_63_TO_14_4514_XOR__ETC___d24528 = + (highOffsetBits__h1042939 == 50'd0 && + IF_f_csr_reqs_first__4361_BIT_63_4515_THEN_NOT_ETC___d24525 || + NOT_csrf_stcc_reg_read__6237_BITS_33_TO_28_625_ETC___d23117) && csrf_stcc_reg[152] ; - assign f_csr_reqs_first__4359_BITS_63_TO_14_4512_XOR__ETC___d24548 = - (highOffsetBits__h1043309 == 50'd0 && - IF_f_csr_reqs_first__4359_BIT_63_4513_THEN_NOT_ETC___d24545 || - NOT_IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN__ETC___d23554) && + assign f_csr_reqs_first__4361_BITS_63_TO_14_4514_XOR__ETC___d24550 = + (highOffsetBits__h1043342 == 50'd0 && + IF_f_csr_reqs_first__4361_BIT_63_4515_THEN_NOT_ETC___d24547 || + NOT_IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN__ETC___d23556) && IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16993 ; - assign f_csr_reqs_first__4359_BITS_63_TO_14_4512_XOR__ETC___d24606 = - (highOffsetBits__h1043726 == 50'd0 && - IF_f_csr_reqs_first__4359_BIT_63_4513_THEN_NOT_ETC___d24603 || - NOT_csrf_mtcc_reg_read__6389_BITS_33_TO_28_640_ETC___d23186) && + assign f_csr_reqs_first__4361_BITS_63_TO_14_4514_XOR__ETC___d24608 = + (highOffsetBits__h1043759 == 50'd0 && + IF_f_csr_reqs_first__4361_BIT_63_4515_THEN_NOT_ETC___d24605 || + NOT_csrf_mtcc_reg_read__6389_BITS_33_TO_28_640_ETC___d23188) && csrf_mtcc_reg[152] ; - assign f_csr_reqs_first__4359_BITS_63_TO_14_4512_XOR__ETC___d24626 = - (highOffsetBits__h1044129 == 50'd0 && - IF_f_csr_reqs_first__4359_BIT_63_4513_THEN_NOT_ETC___d24623 || - NOT_IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN__ETC___d23691) && + assign f_csr_reqs_first__4361_BITS_63_TO_14_4514_XOR__ETC___d24628 = + (highOffsetBits__h1044162 == 50'd0 && + IF_f_csr_reqs_first__4361_BIT_63_4515_THEN_NOT_ETC___d24625 || + NOT_IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN__ETC___d23693) && IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17001 ; - assign f_csr_reqs_first__4359_BITS_63_TO_14_4512_XOR__ETC___d24697 = - (highOffsetBits__h1044796 == 50'd0 && - IF_f_csr_reqs_first__4359_BIT_63_4513_THEN_NOT_ETC___d24694 || - NOT_csrf_rg_dpc_read__6534_BITS_33_TO_28_6551__ETC___d23804) && + assign f_csr_reqs_first__4361_BITS_63_TO_14_4514_XOR__ETC___d24699 = + (highOffsetBits__h1044829 == 50'd0 && + IF_f_csr_reqs_first__4361_BIT_63_4515_THEN_NOT_ETC___d24696 || + NOT_csrf_rg_dpc_read__6534_BITS_33_TO_28_6551__ETC___d23806) && csrf_rg_dpc[152] ; - assign f_csr_rsps_i_notFull__4357_AND_f_csr_reqs_firs_ETC___d24462 = + assign f_csr_rsps_i_notFull__4359_AND_f_csr_reqs_firs_ETC___d24464 = f_csr_rsps$FULL_N && (f_csr_reqs$D_OUT[75:64] != 12'd2049 || csrf_stats_module_writeQ$FULL_N) && (f_csr_reqs$D_OUT[75:64] != 12'd2048 || csrf_terminate_module_terminateQ$FULL_N) ; - assign fallthrough_pc__h948608 = - { fetchStage$pipelines_0_first[591:527], address__h965683 } ; - assign fallthrough_pc__h973095 = - { fetchStage$pipelines_1_first[591:527], address__h990659 } ; - assign fcsr_csr__read__h855634 = { 56'd0, x__h859507 } ; + assign fallthrough_pc__h948605 = + { fetchStage$pipelines_0_first[591:527], address__h965680 } ; + assign fallthrough_pc__h973092 = + { fetchStage$pipelines_1_first[591:527], address__h990656 } ; + assign fcsr_csr__read__h855632 = { 56'd0, x__h859505 } ; assign fetchStage_RDY_pipelines_0_first__0541_AND_fet_ETC___d21553 = fetchStage$RDY_pipelines_0_first && fetchStage$pipelines_1_first[268:266] == 3'd1 && @@ -36531,104 +36503,104 @@ module mkCore(CLK, assign fetchStage_pipelines_1_first__0553_BIT_180_175_ETC___d21852 = { fetchStage$pipelines_1_first[180], CASE_fetchStagepipelines_1_first_BITS_179_TO__ETC__q259 } ; - assign fflags__h1027798 = - NOT_rob_deqPort_0_canDeq__3983_3984_OR_rob_deq_ETC___d24208 ? - y_avValue_snd_fst__h1027858 : - IF_rob_deqPort_0_canDeq__3983_THEN_IF_NOT_rob__ETC___d24215 ; - assign fflags_csr__read__h855609 = { 59'd0, csrf_fflags_reg } ; - assign frm_csr__read__h855620 = { 61'd0, csrf_frm_reg } ; - assign guard__h580889 = - { IF_sfdin88984_BIT_33_THEN_2_ELSE_0__q44[1], - { sfdin__h588984[32:0], 23'd0 } != 56'd0 } ; - assign guard__h589598 = - { IF_theResult___snd97597_BIT_33_THEN_2_ELSE_0__q46[1], - { _theResult___snd__h597597[32:0], 23'd0 } != 56'd0 } ; - assign guard__h598528 = - { IF_sfdin06750_BIT_33_THEN_2_ELSE_0__q52[1], - { sfdin__h606750[32:0], 23'd0 } != 56'd0 } ; - assign guard__h599126 = x__h599228 != 57'd0 ; - assign guard__h607364 = - { IF_theResult___snd15387_BIT_33_THEN_2_ELSE_0__q57[1], - { _theResult___snd__h615387[32:0], 23'd0 } != 56'd0 } ; - assign guard__h626640 = - { IF_sfdin34733_BIT_33_THEN_2_ELSE_0__q77[1], - { sfdin__h634733[32:0], 23'd0 } != 56'd0 } ; - assign guard__h635347 = - { IF_theResult___snd43346_BIT_33_THEN_2_ELSE_0__q79[1], - { _theResult___snd__h643346[32:0], 23'd0 } != 56'd0 } ; - assign guard__h644277 = - { IF_sfdin52499_BIT_33_THEN_2_ELSE_0__q87[1], - { sfdin__h652499[32:0], 23'd0 } != 56'd0 } ; - assign guard__h644875 = x__h644977 != 57'd0 ; - assign guard__h653113 = - { IF_theResult___snd61136_BIT_33_THEN_2_ELSE_0__q92[1], - { _theResult___snd__h661136[32:0], 23'd0 } != 56'd0 } ; - assign guard__h672387 = - { IF_sfdin80480_BIT_33_THEN_2_ELSE_0__q112[1], - { sfdin__h680480[32:0], 23'd0 } != 56'd0 } ; - assign guard__h681094 = - { IF_theResult___snd89093_BIT_33_THEN_2_ELSE_0__q114[1], - { _theResult___snd__h689093[32:0], 23'd0 } != 56'd0 } ; - assign guard__h690024 = - { IF_sfdin98246_BIT_33_THEN_2_ELSE_0__q122[1], - { sfdin__h698246[32:0], 23'd0 } != 56'd0 } ; - assign guard__h690622 = x__h690724 != 57'd0 ; - assign guard__h698860 = - { IF_theResult___snd06883_BIT_33_THEN_2_ELSE_0__q127[1], - { _theResult___snd__h706883[32:0], 23'd0 } != 56'd0 } ; - assign guard__h731259 = - { IF_theResult___snd39171_BIT_4_THEN_2_ELSE_0__q147[1], - { _theResult___snd__h739171[3:0], 52'd0 } != 56'd0 } ; - assign guard__h740571 = - { IF_sfdin48791_BIT_4_THEN_2_ELSE_0__q151[1], - { sfdin__h748791[3:0], 52'd0 } != 56'd0 } ; - assign guard__h741169 = x__h741269 != 57'd0 ; - assign guard__h749640 = - { IF_theResult___snd57576_BIT_4_THEN_2_ELSE_0__q154[1], - { _theResult___snd__h757576[3:0], 52'd0 } != 56'd0 } ; - assign guard__h770112 = - { IF_theResult___snd78024_BIT_4_THEN_2_ELSE_0__q187[1], - { _theResult___snd__h778024[3:0], 52'd0 } != 56'd0 } ; - assign guard__h779424 = - { IF_sfdin87644_BIT_4_THEN_2_ELSE_0__q191[1], - { sfdin__h787644[3:0], 52'd0 } != 56'd0 } ; - assign guard__h780022 = x__h780122 != 57'd0 ; - assign guard__h788493 = - { IF_theResult___snd96429_BIT_4_THEN_2_ELSE_0__q194[1], - { _theResult___snd__h796429[3:0], 52'd0 } != 56'd0 } ; - assign guard__h809416 = - { IF_theResult___snd17328_BIT_4_THEN_2_ELSE_0__q164[1], - { _theResult___snd__h817328[3:0], 52'd0 } != 56'd0 } ; - assign guard__h818728 = - { IF_sfdin26948_BIT_4_THEN_2_ELSE_0__q168[1], - { sfdin__h826948[3:0], 52'd0 } != 56'd0 } ; - assign guard__h819326 = x__h819426 != 57'd0 ; - assign guard__h827797 = - { IF_theResult___snd35733_BIT_4_THEN_2_ELSE_0__q171[1], - { _theResult___snd__h835733[3:0], 52'd0 } != 56'd0 } ; - assign highBitsfilter__h1019337 = + assign fflags__h1027832 = + NOT_rob_deqPort_0_canDeq__3985_3986_OR_rob_deq_ETC___d24210 ? + y_avValue_snd_fst__h1027892 : + IF_rob_deqPort_0_canDeq__3985_THEN_IF_NOT_rob__ETC___d24217 ; + assign fflags_csr__read__h855607 = { 59'd0, csrf_fflags_reg } ; + assign frm_csr__read__h855618 = { 61'd0, csrf_frm_reg } ; + assign guard__h580886 = + { IF_sfdin88981_BIT_33_THEN_2_ELSE_0__q42[1], + { sfdin__h588981[32:0], 23'd0 } != 56'd0 } ; + assign guard__h589595 = + { IF_theResult___snd97594_BIT_33_THEN_2_ELSE_0__q44[1], + { _theResult___snd__h597594[32:0], 23'd0 } != 56'd0 } ; + assign guard__h598525 = + { IF_sfdin06747_BIT_33_THEN_2_ELSE_0__q52[1], + { sfdin__h606747[32:0], 23'd0 } != 56'd0 } ; + assign guard__h599123 = x__h599225 != 57'd0 ; + assign guard__h607361 = + { IF_theResult___snd15384_BIT_33_THEN_2_ELSE_0__q57[1], + { _theResult___snd__h615384[32:0], 23'd0 } != 56'd0 } ; + assign guard__h626637 = + { IF_sfdin34730_BIT_33_THEN_2_ELSE_0__q77[1], + { sfdin__h634730[32:0], 23'd0 } != 56'd0 } ; + assign guard__h635344 = + { IF_theResult___snd43343_BIT_33_THEN_2_ELSE_0__q79[1], + { _theResult___snd__h643343[32:0], 23'd0 } != 56'd0 } ; + assign guard__h644274 = + { IF_sfdin52496_BIT_33_THEN_2_ELSE_0__q87[1], + { sfdin__h652496[32:0], 23'd0 } != 56'd0 } ; + assign guard__h644872 = x__h644974 != 57'd0 ; + assign guard__h653110 = + { IF_theResult___snd61133_BIT_33_THEN_2_ELSE_0__q92[1], + { _theResult___snd__h661133[32:0], 23'd0 } != 56'd0 } ; + assign guard__h672384 = + { IF_sfdin80477_BIT_33_THEN_2_ELSE_0__q112[1], + { sfdin__h680477[32:0], 23'd0 } != 56'd0 } ; + assign guard__h681091 = + { IF_theResult___snd89090_BIT_33_THEN_2_ELSE_0__q114[1], + { _theResult___snd__h689090[32:0], 23'd0 } != 56'd0 } ; + assign guard__h690021 = + { IF_sfdin98243_BIT_33_THEN_2_ELSE_0__q122[1], + { sfdin__h698243[32:0], 23'd0 } != 56'd0 } ; + assign guard__h690619 = x__h690721 != 57'd0 ; + assign guard__h698857 = + { IF_theResult___snd06880_BIT_33_THEN_2_ELSE_0__q127[1], + { _theResult___snd__h706880[32:0], 23'd0 } != 56'd0 } ; + assign guard__h731255 = + { IF_theResult___snd39167_BIT_4_THEN_2_ELSE_0__q147[1], + { _theResult___snd__h739167[3:0], 52'd0 } != 56'd0 } ; + assign guard__h740567 = + { IF_sfdin48787_BIT_4_THEN_2_ELSE_0__q151[1], + { sfdin__h748787[3:0], 52'd0 } != 56'd0 } ; + assign guard__h741165 = x__h741265 != 57'd0 ; + assign guard__h749636 = + { IF_theResult___snd57572_BIT_4_THEN_2_ELSE_0__q154[1], + { _theResult___snd__h757572[3:0], 52'd0 } != 56'd0 } ; + assign guard__h770108 = + { IF_theResult___snd78020_BIT_4_THEN_2_ELSE_0__q187[1], + { _theResult___snd__h778020[3:0], 52'd0 } != 56'd0 } ; + assign guard__h779420 = + { IF_sfdin87640_BIT_4_THEN_2_ELSE_0__q191[1], + { sfdin__h787640[3:0], 52'd0 } != 56'd0 } ; + assign guard__h780018 = x__h780118 != 57'd0 ; + assign guard__h788489 = + { IF_theResult___snd96425_BIT_4_THEN_2_ELSE_0__q194[1], + { _theResult___snd__h796425[3:0], 52'd0 } != 56'd0 } ; + assign guard__h809412 = + { IF_theResult___snd17324_BIT_4_THEN_2_ELSE_0__q164[1], + { _theResult___snd__h817324[3:0], 52'd0 } != 56'd0 } ; + assign guard__h818724 = + { IF_sfdin26944_BIT_4_THEN_2_ELSE_0__q168[1], + { sfdin__h826944[3:0], 52'd0 } != 56'd0 } ; + assign guard__h819322 = x__h819422 != 57'd0 ; + assign guard__h827793 = + { IF_theResult___snd35729_BIT_4_THEN_2_ELSE_0__q171[1], + { _theResult___snd__h835729[3:0], 52'd0 } != 56'd0 } ; + assign highBitsfilter__h1019371 = 50'h3FFFFFFFFFFFF << csrf_stcc_reg[33:28] ; - assign highBitsfilter__h1019740 = + assign highBitsfilter__h1019774 = 50'h3FFFFFFFFFFFF << IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16291 ; - assign highBitsfilter__h1020157 = + assign highBitsfilter__h1020191 = 50'h3FFFFFFFFFFFF << csrf_mtcc_reg[33:28] ; - assign highBitsfilter__h1020560 = + assign highBitsfilter__h1020594 = 50'h3FFFFFFFFFFFF << IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16443 ; - assign highBitsfilter__h1021229 = 50'h3FFFFFFFFFFFF << csrf_rg_dpc[33:28] ; - assign highOffsetBits__h1019338 = x__h1019365 & highBitsfilter__h1019337 ; - assign highOffsetBits__h1019741 = x__h1019365 & highBitsfilter__h1019740 ; - assign highOffsetBits__h1020158 = x__h1019365 & highBitsfilter__h1020157 ; - assign highOffsetBits__h1020561 = x__h1019365 & highBitsfilter__h1020560 ; - assign highOffsetBits__h1021230 = x__h1019365 & highBitsfilter__h1021229 ; - assign highOffsetBits__h1042906 = x__h1042933 & highBitsfilter__h1019337 ; - assign highOffsetBits__h1043309 = x__h1042933 & highBitsfilter__h1019740 ; - assign highOffsetBits__h1043726 = x__h1042933 & highBitsfilter__h1020157 ; - assign highOffsetBits__h1044129 = x__h1042933 & highBitsfilter__h1020560 ; - assign highOffsetBits__h1044796 = x__h1042933 & highBitsfilter__h1021229 ; - assign highOffsetBits__h245537 = x__h245564 & mask__h242758 ; - assign idx__h978724 = + assign highBitsfilter__h1021263 = 50'h3FFFFFFFFFFFF << csrf_rg_dpc[33:28] ; + assign highOffsetBits__h1019372 = x__h1019399 & highBitsfilter__h1019371 ; + assign highOffsetBits__h1019775 = x__h1019399 & highBitsfilter__h1019774 ; + assign highOffsetBits__h1020192 = x__h1019399 & highBitsfilter__h1020191 ; + assign highOffsetBits__h1020595 = x__h1019399 & highBitsfilter__h1020594 ; + assign highOffsetBits__h1021264 = x__h1019399 & highBitsfilter__h1021263 ; + assign highOffsetBits__h1042939 = x__h1042966 & highBitsfilter__h1019371 ; + assign highOffsetBits__h1043342 = x__h1042966 & highBitsfilter__h1019774 ; + assign highOffsetBits__h1043759 = x__h1042966 & highBitsfilter__h1020191 ; + assign highOffsetBits__h1044162 = x__h1042966 & highBitsfilter__h1020594 ; + assign highOffsetBits__h1044829 = x__h1042966 & highBitsfilter__h1021263 ; + assign highOffsetBits__h245534 = x__h245561 & mask__h242755 ; + assign idx__h978721 = fetchStage$pipelines_0_canDeq && NOT_fetchStage_pipelines_0_first__0544_BITS_26_ETC___d21951 || !coreFix_aluExe_0_rsAlu$canEnq || @@ -36636,95 +36608,95 @@ module mkCore(CLK, fetchStage_pipelines_0_first__0544_BITS_268_TO_ETC___d21974) && coreFix_aluExe_1_rsAlu$canEnq && !coreFix_aluExe_0_rsAlu_approximateCount__1496__ETC___d21498 ; - assign impliedTopBits__h1005775 = x__h1005859 + len_correction__h1005774 ; - assign impliedTopBits__h128461 = x__h128545 + len_correction__h128460 ; - assign impliedTopBits__h141605 = x__h141689 + len_correction__h141604 ; - assign impliedTopBits__h185387 = x__h185471 + len_correction__h185386 ; - assign impliedTopBits__h204450 = x__h204534 + len_correction__h204449 ; - assign impliedTopBits__h219421 = x__h219505 + len_correction__h219420 ; - assign impliedTopBits__h872937 = x__h873022 + len_correction__h872936 ; - assign impliedTopBits__h873485 = x__h873570 + len_correction__h873484 ; - assign impliedTopBits__h913978 = x__h914063 + len_correction__h913977 ; - assign impliedTopBits__h914526 = x__h914611 + len_correction__h914525 ; - assign in__h1008389 = pc_address__h1005472 & y__h1008406 ; - assign in__h242697 = coreFix_memExe_regToExeQ$first[383:318] & y__h242714 ; - assign in__h243854 = coreFix_memExe_regToExeQ$first[220:155] & y__h243871 ; - assign in__h257475 = coreFix_memExe_dTlb$procResp[452:387] & y__h257492 ; - assign in__h860569 = csrf_stcc_reg[151:86] & y__h860586 ; - assign in__h860874 = + assign impliedTopBits__h1005772 = x__h1005856 + len_correction__h1005771 ; + assign impliedTopBits__h128460 = x__h128544 + len_correction__h128459 ; + assign impliedTopBits__h141604 = x__h141688 + len_correction__h141603 ; + assign impliedTopBits__h185385 = x__h185469 + len_correction__h185384 ; + assign impliedTopBits__h204448 = x__h204532 + len_correction__h204447 ; + assign impliedTopBits__h219419 = x__h219503 + len_correction__h219418 ; + assign impliedTopBits__h872935 = x__h873020 + len_correction__h872934 ; + assign impliedTopBits__h873483 = x__h873568 + len_correction__h873482 ; + assign impliedTopBits__h913975 = x__h914060 + len_correction__h913974 ; + assign impliedTopBits__h914523 = x__h914608 + len_correction__h914522 ; + assign in__h1008423 = pc_address__h1005469 & y__h1008440 ; + assign in__h242694 = coreFix_memExe_regToExeQ$first[383:318] & y__h242711 ; + assign in__h243851 = coreFix_memExe_regToExeQ$first[220:155] & y__h243868 ; + assign in__h257472 = coreFix_memExe_dTlb$procResp[452:387] & y__h257489 ; + assign in__h860567 = csrf_stcc_reg[151:86] & y__h860584 ; + assign in__h860872 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16295 & - y__h860891 ; - assign in__h861562 = csrf_mtcc_reg[151:86] & y__h861579 ; - assign in__h861866 = + y__h860889 ; + assign in__h861560 = csrf_mtcc_reg[151:86] & y__h861577 ; + assign in__h861864 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16447 & - y__h861883 ; - assign in__h862392 = csrf_rg_dpc[151:86] & y__h862409 ; - assign inc__h965682 = + y__h861881 ; + assign in__h862390 = csrf_rg_dpc[151:86] & y__h862407 ; + assign inc__h965679 = (fetchStage$pipelines_0_first[98:97] == 2'b11) ? 12'd4 : 12'd2 ; - assign inc__h990658 = + assign inc__h990655 = (fetchStage$pipelines_1_first[98:97] == 2'b11) ? 12'd4 : 12'd2 ; - assign k__h954121 = + assign k__h954118 = !coreFix_aluExe_0_rsAlu$canEnq || coreFix_aluExe_1_rsAlu$canEnq && !coreFix_aluExe_0_rsAlu_approximateCount__1496__ETC___d21498 ; - assign len_correction__h1005774 = + assign len_correction__h1005771 = INV_commitStage_commitTrap_BITS_217_TO_199__q15[0] ? 2'b01 : 2'b0 ; - assign len_correction__h128460 = + assign len_correction__h128459 = INV_coreFix_memExe_respLrScAmoQ_data_0_BITS_10_ETC__q8[0] ? 2'b01 : 2'b0 ; - assign len_correction__h141604 = + assign len_correction__h141603 = INV_mmio_dataRespQ_data_0_BITS_108_TO_90__q9[0] ? 2'b01 : 2'b0 ; - assign len_correction__h185386 = - INV_x85174_BITS_108_TO_90__q35[0] ? 2'b01 : 2'b0 ; - assign len_correction__h204449 = - INV_x01338_BITS_108_TO_90__q37[0] ? 2'b01 : 2'b0 ; - assign len_correction__h219420 = + assign len_correction__h185384 = + INV_x85172_BITS_108_TO_90__q35[0] ? 2'b01 : 2'b0 ; + assign len_correction__h204447 = + INV_x01336_BITS_108_TO_90__q37[0] ? 2'b01 : 2'b0 ; + assign len_correction__h219418 = INV_coreFix_memExe_lsqrespLd_BITS_108_TO_90__q10[0] ? 2'b01 : 2'b0 ; - assign len_correction__h872936 = + assign len_correction__h872934 = INV_coreFix_aluExe_1_regToExeQfirst_BITS_286__ETC__q11[0] ? 2'b01 : 2'b0 ; - assign len_correction__h873484 = + assign len_correction__h873482 = INV_coreFix_aluExe_1_regToExeQfirst_BITS_157__ETC__q12[0] ? 2'b01 : 2'b0 ; - assign len_correction__h913977 = + assign len_correction__h913974 = INV_coreFix_aluExe_0_regToExeQfirst_BITS_286__ETC__q13[0] ? 2'b01 : 2'b0 ; - assign len_correction__h914525 = + assign len_correction__h914522 = INV_coreFix_aluExe_0_regToExeQfirst_BITS_157__ETC__q14[0] ? 2'b01 : 2'b0 ; - assign mask__h1010233 = 64'hFFFFFFFFFFFFFFFF << x__h1010294 ; - assign mask__h1010890 = 64'hFFFFFFFFFFFFFFFF << x__h1010951 ; - assign mask__h242758 = + assign mask__h1010267 = 64'hFFFFFFFFFFFFFFFF << x__h1010328 ; + assign mask__h1010924 = 64'hFFFFFFFFFFFFFFFF << x__h1010985 ; + assign mask__h242755 = 50'h3FFFFFFFFFFFF << coreFix_memExe_regToExeQ$first[265:260] ; - assign mask__h242867 = + assign mask__h242864 = 52'hFFFFFFFFFFFFF << coreFix_memExe_regToExeQ$first[265:260] ; - assign mask__h243915 = + assign mask__h243912 = 50'h3FFFFFFFFFFFF << coreFix_memExe_regToExeQ$first[102:97] ; - assign mask__h244024 = + assign mask__h244021 = 52'hFFFFFFFFFFFFF << coreFix_memExe_regToExeQ$first[102:97] ; - assign mask__h257536 = + assign mask__h257533 = 50'h3FFFFFFFFFFFF << coreFix_memExe_dTlb$procResp[334:329] ; - assign mask__h257645 = + assign mask__h257642 = 52'hFFFFFFFFFFFFF << coreFix_memExe_dTlb$procResp[334:329] ; - assign mcause_csr__read__h857301 = - { r1__read__h861916, csrf_mcause_code_reg } ; - assign mcounteren_csr__read__h857035 = - { r1__read__h861612, csrf_mcounteren_cy_reg } ; - assign medeleg_csr__read__h856638 = - { r1__read__h861289, csrf_medeleg_9_0_reg } ; - assign mideleg_csr__read__h856736 = - { r1__read__h861312, csrf_mideleg_1_0_reg } ; - assign mie_csr__read__h856863 = { r1__read__h861336, 1'b0 } ; - assign mip_csr__read__h857540 = { r1__read__h861923, 1'b0 } ; + assign mcause_csr__read__h857299 = + { r1__read__h861914, csrf_mcause_code_reg } ; + assign mcounteren_csr__read__h857033 = + { r1__read__h861610, csrf_mcounteren_cy_reg } ; + assign medeleg_csr__read__h856636 = + { r1__read__h861287, csrf_medeleg_9_0_reg } ; + assign mideleg_csr__read__h856734 = + { r1__read__h861310, csrf_mideleg_1_0_reg } ; + assign mie_csr__read__h856861 = { r1__read__h861334, 1'b0 } ; + assign mip_csr__read__h857538 = { r1__read__h861921, 1'b0 } ; assign mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d20967 = mmio_pRqQ_empty && epochManager$checkEpoch_0_check && (renameStage_rg_m_halt_req[4] || @@ -36766,56 +36738,56 @@ module mkCore(CLK, fetchStage$pipelines_0_first[273:269] != 5'd24 && fetchStage$pipelines_0_first[273:269] != 5'd25 && rg_core_run_state == 2'd2 ; - assign mstatus_csr__read__h856477 = { r1__read__h861164, csrf_ie_vec_0 } ; - assign n__read__h1025204 = + assign mstatus_csr__read__h856475 = { r1__read__h861162, csrf_ie_vec_0 } ; + assign n__read__h1025238 = csrf_minstret_ehr_data_lat_0$whas ? - upd__h1025280 : + upd__h1025314 : csrf_minstret_ehr_data_rl ; assign n__read__h7908 = csrf_mcycle_ehr_data_lat_0$whas ? upd__h7977 : csrf_mcycle_ehr_data_rl ; - assign newAddrBits__h1019520 = - { 2'd0, csrf_stcc_reg[13:0] } + { 2'd0, x__h1019461[13:0] } ; - assign newAddrBits__h1019923 = + assign newAddrBits__h1019554 = + { 2'd0, csrf_stcc_reg[13:0] } + { 2'd0, x__h1019495[13:0] } ; + assign newAddrBits__h1019957 = { 2'd0, IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16275 } + - { 2'd0, x__h1019864[13:0] } ; - assign newAddrBits__h1020340 = - { 2'd0, csrf_mtcc_reg[13:0] } + { 2'd0, x__h1020281[13:0] } ; - assign newAddrBits__h1020743 = + { 2'd0, x__h1019898[13:0] } ; + assign newAddrBits__h1020374 = + { 2'd0, csrf_mtcc_reg[13:0] } + { 2'd0, x__h1020315[13:0] } ; + assign newAddrBits__h1020777 = { 2'd0, IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16427 } + - { 2'd0, x__h1020684[13:0] } ; - assign newAddrBits__h1021412 = - { 2'd0, csrf_rg_dpc[13:0] } + { 2'd0, x__h1021353[13:0] } ; - assign newAddrBits__h1043088 = - { 2'd0, csrf_stcc_reg[13:0] } + { 2'd0, x__h1043029[13:0] } ; - assign newAddrBits__h1043491 = + { 2'd0, x__h1020718[13:0] } ; + assign newAddrBits__h1021446 = + { 2'd0, csrf_rg_dpc[13:0] } + { 2'd0, x__h1021387[13:0] } ; + assign newAddrBits__h1043121 = + { 2'd0, csrf_stcc_reg[13:0] } + { 2'd0, x__h1043062[13:0] } ; + assign newAddrBits__h1043524 = { 2'd0, IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16275 } + - { 2'd0, x__h1043432[13:0] } ; - assign newAddrBits__h1043908 = - { 2'd0, csrf_mtcc_reg[13:0] } + { 2'd0, x__h1043849[13:0] } ; - assign newAddrBits__h1044311 = + { 2'd0, x__h1043465[13:0] } ; + assign newAddrBits__h1043941 = + { 2'd0, csrf_mtcc_reg[13:0] } + { 2'd0, x__h1043882[13:0] } ; + assign newAddrBits__h1044344 = { 2'd0, IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16427 } + - { 2'd0, x__h1044252[13:0] } ; - assign newAddrBits__h1044978 = - { 2'd0, csrf_rg_dpc[13:0] } + { 2'd0, x__h1044919[13:0] } ; - assign newAddrDiff__h1010234 = - csrf_stcc_reg_read__6237_BITS_149_TO_86_3116_A_ETC___d23119 - - (address__h1010161 & mask__h1010233) ; - assign newAddrDiff__h1010578 = - csrf_stcc_reg_read__6237_BITS_149_TO_86_3116_A_ETC___d23119 - - (base__h1010122 & mask__h1010233) ; - assign newAddrDiff__h1010891 = - csrf_mtcc_reg_read__6389_BITS_149_TO_86_3187_A_ETC___d23190 - - (address__h1010211 & mask__h1010890) ; - assign newAddrDiff__h1011235 = - csrf_mtcc_reg_read__6389_BITS_149_TO_86_3187_A_ETC___d23190 - - (base__h1010176 & mask__h1010890) ; - assign new_pc__h880399 = + { 2'd0, x__h1044285[13:0] } ; + assign newAddrBits__h1045011 = + { 2'd0, csrf_rg_dpc[13:0] } + { 2'd0, x__h1044952[13:0] } ; + assign newAddrDiff__h1010268 = + csrf_stcc_reg_read__6237_BITS_149_TO_86_3118_A_ETC___d23121 - + (address__h1010195 & mask__h1010267) ; + assign newAddrDiff__h1010612 = + csrf_stcc_reg_read__6237_BITS_149_TO_86_3118_A_ETC___d23121 - + (base__h1010156 & mask__h1010267) ; + assign newAddrDiff__h1010925 = + csrf_mtcc_reg_read__6389_BITS_149_TO_86_3189_A_ETC___d23192 - + (address__h1010245 & mask__h1010924) ; + assign newAddrDiff__h1011269 = + csrf_mtcc_reg_read__6389_BITS_149_TO_86_3189_A_ETC___d23192 - + (base__h1010210 & mask__h1010924) ; + assign new_pc__h880397 = { coreFix_aluExe_1_exeToFinQ$first[460], coreFix_aluExe_1_exeToFinQ$first[379:364], coreFix_aluExe_1_exeToFinQ$first[362:361], @@ -36827,7 +36799,7 @@ module mkCore(CLK, ~IF_coreFix_aluExe_1_exeToFinQ_first__8058_BIT__ETC___d18226[2], IF_coreFix_aluExe_1_exeToFinQ_first__8058_BIT__ETC___d18226[1:0], coreFix_aluExe_1_exeToFinQ$first[457:394] } ; - assign new_pc__h920773 = + assign new_pc__h920770 = { coreFix_aluExe_0_exeToFinQ$first[460], coreFix_aluExe_0_exeToFinQ$first[379:364], coreFix_aluExe_0_exeToFinQ$first[362:361], @@ -36839,275 +36811,275 @@ module mkCore(CLK, ~IF_coreFix_aluExe_0_exeToFinQ_first__0233_BIT__ETC___d20400[2], IF_coreFix_aluExe_0_exeToFinQ_first__0233_BIT__ETC___d20400[1:0], coreFix_aluExe_0_exeToFinQ$first[457:394] } ; - assign next_deqP___1__h520038 = + assign next_deqP___1__h520035 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP == 3'd7) ? 3'd0 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP + 3'd1 ; - assign next_deqP___1__h530815 = + assign next_deqP___1__h530812 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP + 1'd1 ; - assign next_deqP___1__h538093 = + assign next_deqP___1__h538090 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP + 1'd1 ; - assign next_deqP___1__h548728 = + assign next_deqP___1__h548725 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP + 1'd1 ; - assign next_deqP___1__h562376 = coreFix_memExe_memRespLdQ_deqP + 1'd1 ; - assign next_deqP___1__h566155 = coreFix_memExe_forwardQ_deqP + 1'd1 ; - assign next_pc__h1023233 = + assign next_deqP___1__h562373 = coreFix_memExe_memRespLdQ_deqP + 1'd1 ; + assign next_deqP___1__h566152 = coreFix_memExe_forwardQ_deqP + 1'd1 ; + assign next_pc__h1023267 = (rob$deqPort_0_deq_data[196:195] == 2'd0) ? rob$deqPort_0_deq_data[160:32] : - { rob$deqPort_0_deq_data[630:566], address__h1023286 } ; - assign offset__h1008308 = { 2'd0, pc_addrBits__h1005473 } - base__h1008307 ; - assign offset__h242593 = + { rob$deqPort_0_deq_data[630:566], address__h1023320 } ; + assign offset__h1008342 = { 2'd0, pc_addrBits__h1005470 } - base__h1008341 ; + assign offset__h242590 = { 2'd0, coreFix_memExe_regToExeQ$first[317:304] } - - base__h242592 ; - assign offset__h243750 = + base__h242589 ; + assign offset__h243747 = { 2'd0, coreFix_memExe_regToExeQ$first[154:141] } - - base__h243749 ; - assign offset__h245518 = + base__h243746 ; + assign offset__h245515 = { {32{coreFix_memExe_regToExeQfirst_BITS_434_TO_403__q17[31]}}, coreFix_memExe_regToExeQfirst_BITS_434_TO_403__q17 } ; - assign offset__h257371 = - { 2'd0, coreFix_memExe_dTlb$procResp[386:373] } - base__h257370 ; - assign offset__h860636 = + assign offset__h257368 = + { 2'd0, coreFix_memExe_dTlb$procResp[386:373] } - base__h257367 ; + assign offset__h860634 = { 2'd0, IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16271 } - - base__h860635 ; - assign offset__h861629 = + base__h860633 ; + assign offset__h861627 = { 2'd0, IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16423 } - - base__h861628 ; - assign offset__h903653 = { 2'd0, csrf_stcc_reg[85:72] } - base__h903652 ; - assign offset__h903937 = { 2'd0, csrf_mtcc_reg[85:72] } - base__h903936 ; - assign offset__h904282 = { 2'd0, csrf_rg_dpc[85:72] } - base__h904281 ; - assign out___1_sfd__h719896 = { f1_sfd__h719833, 29'd0 } ; - assign out___1_sfd__h758890 = { f2_sfd__h758827, 29'd0 } ; - assign out___1_sfd__h798194 = { f3_sfd__h798131, 29'd0 } ; - assign out_exp__h589509 = - sfdin__h588984[34] ? - _theResult___exp__h589506 : - _theResult___fst_exp__h588990 ; - assign out_exp__h598091 = - _theResult___snd__h597597[34] ? - _theResult___exp__h598088 : - _theResult___fst_exp__h597646 ; - assign out_exp__h607275 = - sfdin__h606750[34] ? - _theResult___exp__h607272 : - _theResult___fst_exp__h606756 ; - assign out_exp__h615911 = - _theResult___snd__h615387[34] ? - _theResult___exp__h615908 : - _theResult___fst_exp__h615441 ; - assign out_exp__h635258 = - sfdin__h634733[34] ? - _theResult___exp__h635255 : - _theResult___fst_exp__h634739 ; - assign out_exp__h643840 = - _theResult___snd__h643346[34] ? - _theResult___exp__h643837 : - _theResult___fst_exp__h643395 ; - assign out_exp__h653024 = - sfdin__h652499[34] ? - _theResult___exp__h653021 : - _theResult___fst_exp__h652505 ; - assign out_exp__h661660 = - _theResult___snd__h661136[34] ? - _theResult___exp__h661657 : - _theResult___fst_exp__h661190 ; - assign out_exp__h681005 = - sfdin__h680480[34] ? - _theResult___exp__h681002 : - _theResult___fst_exp__h680486 ; - assign out_exp__h689587 = - _theResult___snd__h689093[34] ? - _theResult___exp__h689584 : - _theResult___fst_exp__h689142 ; - assign out_exp__h698771 = - sfdin__h698246[34] ? - _theResult___exp__h698768 : - _theResult___fst_exp__h698252 ; - assign out_exp__h707407 = - _theResult___snd__h706883[34] ? - _theResult___exp__h707404 : - _theResult___fst_exp__h706937 ; - assign out_exp__h739878 = - _theResult___snd__h739171[5] ? - _theResult___exp__h739875 : - _theResult___fst_exp__h739220 ; - assign out_exp__h749529 = - sfdin__h748791[5] ? - _theResult___exp__h749526 : - _theResult___fst_exp__h748797 ; - assign out_exp__h758313 = - _theResult___snd__h757576[5] ? - _theResult___exp__h758310 : - _theResult___fst_exp__h757630 ; - assign out_exp__h778731 = - _theResult___snd__h778024[5] ? - _theResult___exp__h778728 : - _theResult___fst_exp__h778073 ; - assign out_exp__h788382 = - sfdin__h787644[5] ? - _theResult___exp__h788379 : - _theResult___fst_exp__h787650 ; - assign out_exp__h797166 = - _theResult___snd__h796429[5] ? - _theResult___exp__h797163 : - _theResult___fst_exp__h796483 ; - assign out_exp__h818035 = - _theResult___snd__h817328[5] ? - _theResult___exp__h818032 : - _theResult___fst_exp__h817377 ; - assign out_exp__h827686 = - sfdin__h826948[5] ? - _theResult___exp__h827683 : - _theResult___fst_exp__h826954 ; - assign out_exp__h836470 = - _theResult___snd__h835733[5] ? - _theResult___exp__h836467 : - _theResult___fst_exp__h835787 ; - assign out_f_exp__h616287 = - (_theResult___exp__h616010 == 8'd255 && - _theResult___sfd__h616011 != 23'd0 || + base__h861626 ; + assign offset__h903650 = { 2'd0, csrf_stcc_reg[85:72] } - base__h903649 ; + assign offset__h903934 = { 2'd0, csrf_mtcc_reg[85:72] } - base__h903933 ; + assign offset__h904279 = { 2'd0, csrf_rg_dpc[85:72] } - base__h904278 ; + assign out___1_sfd__h719892 = { f1_sfd__h719829, 29'd0 } ; + assign out___1_sfd__h758886 = { f2_sfd__h758823, 29'd0 } ; + assign out___1_sfd__h798190 = { f3_sfd__h798127, 29'd0 } ; + assign out_exp__h589506 = + sfdin__h588981[34] ? + _theResult___exp__h589503 : + _theResult___fst_exp__h588987 ; + assign out_exp__h598088 = + _theResult___snd__h597594[34] ? + _theResult___exp__h598085 : + _theResult___fst_exp__h597643 ; + assign out_exp__h607272 = + sfdin__h606747[34] ? + _theResult___exp__h607269 : + _theResult___fst_exp__h606753 ; + assign out_exp__h615908 = + _theResult___snd__h615384[34] ? + _theResult___exp__h615905 : + _theResult___fst_exp__h615438 ; + assign out_exp__h635255 = + sfdin__h634730[34] ? + _theResult___exp__h635252 : + _theResult___fst_exp__h634736 ; + assign out_exp__h643837 = + _theResult___snd__h643343[34] ? + _theResult___exp__h643834 : + _theResult___fst_exp__h643392 ; + assign out_exp__h653021 = + sfdin__h652496[34] ? + _theResult___exp__h653018 : + _theResult___fst_exp__h652502 ; + assign out_exp__h661657 = + _theResult___snd__h661133[34] ? + _theResult___exp__h661654 : + _theResult___fst_exp__h661187 ; + assign out_exp__h681002 = + sfdin__h680477[34] ? + _theResult___exp__h680999 : + _theResult___fst_exp__h680483 ; + assign out_exp__h689584 = + _theResult___snd__h689090[34] ? + _theResult___exp__h689581 : + _theResult___fst_exp__h689139 ; + assign out_exp__h698768 = + sfdin__h698243[34] ? + _theResult___exp__h698765 : + _theResult___fst_exp__h698249 ; + assign out_exp__h707404 = + _theResult___snd__h706880[34] ? + _theResult___exp__h707401 : + _theResult___fst_exp__h706934 ; + assign out_exp__h739874 = + _theResult___snd__h739167[5] ? + _theResult___exp__h739871 : + _theResult___fst_exp__h739216 ; + assign out_exp__h749525 = + sfdin__h748787[5] ? + _theResult___exp__h749522 : + _theResult___fst_exp__h748793 ; + assign out_exp__h758309 = + _theResult___snd__h757572[5] ? + _theResult___exp__h758306 : + _theResult___fst_exp__h757626 ; + assign out_exp__h778727 = + _theResult___snd__h778020[5] ? + _theResult___exp__h778724 : + _theResult___fst_exp__h778069 ; + assign out_exp__h788378 = + sfdin__h787640[5] ? + _theResult___exp__h788375 : + _theResult___fst_exp__h787646 ; + assign out_exp__h797162 = + _theResult___snd__h796425[5] ? + _theResult___exp__h797159 : + _theResult___fst_exp__h796479 ; + assign out_exp__h818031 = + _theResult___snd__h817324[5] ? + _theResult___exp__h818028 : + _theResult___fst_exp__h817373 ; + assign out_exp__h827682 = + sfdin__h826944[5] ? + _theResult___exp__h827679 : + _theResult___fst_exp__h826950 ; + assign out_exp__h836466 = + _theResult___snd__h835729[5] ? + _theResult___exp__h836463 : + _theResult___fst_exp__h835783 ; + assign out_f_exp__h616284 = + (_theResult___exp__h616007 == 8'd255 && + _theResult___sfd__h616008 != 23'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h616001 ; - assign out_f_exp__h662036 = - (_theResult___exp__h661759 == 8'd255 && - _theResult___sfd__h661760 != 23'd0 || + _theResult___fst_exp__h615998 ; + assign out_f_exp__h662033 = + (_theResult___exp__h661756 == 8'd255 && + _theResult___sfd__h661757 != 23'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h661750 ; - assign out_f_exp__h707783 = - (_theResult___exp__h707506 == 8'd255 && - _theResult___sfd__h707507 != 23'd0 || + _theResult___fst_exp__h661747 ; + assign out_f_exp__h707780 = + (_theResult___exp__h707503 == 8'd255 && + _theResult___sfd__h707504 != 23'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h707497 ; - assign out_f_sfd__h616288 = - (_theResult___exp__h616010 == 8'd255 && - _theResult___sfd__h616011 != 23'd0) ? + _theResult___fst_exp__h707494 ; + assign out_f_sfd__h616285 = + (_theResult___exp__h616007 == 8'd255 && + _theResult___sfd__h616008 != 23'd0) ? 23'd4194304 : - _theResult___sfd__h616011 ; - assign out_f_sfd__h662037 = - (_theResult___exp__h661759 == 8'd255 && - _theResult___sfd__h661760 != 23'd0) ? + _theResult___sfd__h616008 ; + assign out_f_sfd__h662034 = + (_theResult___exp__h661756 == 8'd255 && + _theResult___sfd__h661757 != 23'd0) ? 23'd4194304 : - _theResult___sfd__h661760 ; - assign out_f_sfd__h707784 = - (_theResult___exp__h707506 == 8'd255 && - _theResult___sfd__h707507 != 23'd0) ? + _theResult___sfd__h661757 ; + assign out_f_sfd__h707781 = + (_theResult___exp__h707503 == 8'd255 && + _theResult___sfd__h707504 != 23'd0) ? 23'd4194304 : - _theResult___sfd__h707507 ; - assign out_sfd__h589510 = - sfdin__h588984[34] ? - _theResult___sfd__h589507 : - sfdin__h588984[56:34] ; - assign out_sfd__h598092 = - _theResult___snd__h597597[34] ? - _theResult___sfd__h598089 : - _theResult___snd__h597597[56:34] ; - assign out_sfd__h607276 = - sfdin__h606750[34] ? - _theResult___sfd__h607273 : - sfdin__h606750[56:34] ; - assign out_sfd__h615912 = - _theResult___snd__h615387[34] ? - _theResult___sfd__h615909 : - _theResult___snd__h615387[56:34] ; - assign out_sfd__h635259 = - sfdin__h634733[34] ? - _theResult___sfd__h635256 : - sfdin__h634733[56:34] ; - assign out_sfd__h643841 = - _theResult___snd__h643346[34] ? - _theResult___sfd__h643838 : - _theResult___snd__h643346[56:34] ; - assign out_sfd__h653025 = - sfdin__h652499[34] ? - _theResult___sfd__h653022 : - sfdin__h652499[56:34] ; - assign out_sfd__h661661 = - _theResult___snd__h661136[34] ? - _theResult___sfd__h661658 : - _theResult___snd__h661136[56:34] ; - assign out_sfd__h681006 = - sfdin__h680480[34] ? - _theResult___sfd__h681003 : - sfdin__h680480[56:34] ; - assign out_sfd__h689588 = - _theResult___snd__h689093[34] ? - _theResult___sfd__h689585 : - _theResult___snd__h689093[56:34] ; - assign out_sfd__h698772 = - sfdin__h698246[34] ? - _theResult___sfd__h698769 : - sfdin__h698246[56:34] ; - assign out_sfd__h707408 = - _theResult___snd__h706883[34] ? - _theResult___sfd__h707405 : - _theResult___snd__h706883[56:34] ; - assign out_sfd__h739879 = - _theResult___snd__h739171[5] ? - _theResult___sfd__h739876 : - _theResult___snd__h739171[56:5] ; - assign out_sfd__h749530 = - sfdin__h748791[5] ? - _theResult___sfd__h749527 : - sfdin__h748791[56:5] ; - assign out_sfd__h758314 = - _theResult___snd__h757576[5] ? - _theResult___sfd__h758311 : - _theResult___snd__h757576[56:5] ; - assign out_sfd__h778732 = - _theResult___snd__h778024[5] ? - _theResult___sfd__h778729 : - _theResult___snd__h778024[56:5] ; - assign out_sfd__h788383 = - sfdin__h787644[5] ? - _theResult___sfd__h788380 : - sfdin__h787644[56:5] ; - assign out_sfd__h797167 = - _theResult___snd__h796429[5] ? - _theResult___sfd__h797164 : - _theResult___snd__h796429[56:5] ; - assign out_sfd__h818036 = - _theResult___snd__h817328[5] ? - _theResult___sfd__h818033 : - _theResult___snd__h817328[56:5] ; - assign out_sfd__h827687 = - sfdin__h826948[5] ? - _theResult___sfd__h827684 : - sfdin__h826948[56:5] ; - assign out_sfd__h836471 = - _theResult___snd__h835733[5] ? - _theResult___sfd__h836468 : - _theResult___snd__h835733[56:5] ; - assign pc__h973086 = fetchStage$pipelines_1_first[591:463] ; - assign pc_addrBits__h1005473 = + _theResult___sfd__h707504 ; + assign out_sfd__h589507 = + sfdin__h588981[34] ? + _theResult___sfd__h589504 : + sfdin__h588981[56:34] ; + assign out_sfd__h598089 = + _theResult___snd__h597594[34] ? + _theResult___sfd__h598086 : + _theResult___snd__h597594[56:34] ; + assign out_sfd__h607273 = + sfdin__h606747[34] ? + _theResult___sfd__h607270 : + sfdin__h606747[56:34] ; + assign out_sfd__h615909 = + _theResult___snd__h615384[34] ? + _theResult___sfd__h615906 : + _theResult___snd__h615384[56:34] ; + assign out_sfd__h635256 = + sfdin__h634730[34] ? + _theResult___sfd__h635253 : + sfdin__h634730[56:34] ; + assign out_sfd__h643838 = + _theResult___snd__h643343[34] ? + _theResult___sfd__h643835 : + _theResult___snd__h643343[56:34] ; + assign out_sfd__h653022 = + sfdin__h652496[34] ? + _theResult___sfd__h653019 : + sfdin__h652496[56:34] ; + assign out_sfd__h661658 = + _theResult___snd__h661133[34] ? + _theResult___sfd__h661655 : + _theResult___snd__h661133[56:34] ; + assign out_sfd__h681003 = + sfdin__h680477[34] ? + _theResult___sfd__h681000 : + sfdin__h680477[56:34] ; + assign out_sfd__h689585 = + _theResult___snd__h689090[34] ? + _theResult___sfd__h689582 : + _theResult___snd__h689090[56:34] ; + assign out_sfd__h698769 = + sfdin__h698243[34] ? + _theResult___sfd__h698766 : + sfdin__h698243[56:34] ; + assign out_sfd__h707405 = + _theResult___snd__h706880[34] ? + _theResult___sfd__h707402 : + _theResult___snd__h706880[56:34] ; + assign out_sfd__h739875 = + _theResult___snd__h739167[5] ? + _theResult___sfd__h739872 : + _theResult___snd__h739167[56:5] ; + assign out_sfd__h749526 = + sfdin__h748787[5] ? + _theResult___sfd__h749523 : + sfdin__h748787[56:5] ; + assign out_sfd__h758310 = + _theResult___snd__h757572[5] ? + _theResult___sfd__h758307 : + _theResult___snd__h757572[56:5] ; + assign out_sfd__h778728 = + _theResult___snd__h778020[5] ? + _theResult___sfd__h778725 : + _theResult___snd__h778020[56:5] ; + assign out_sfd__h788379 = + sfdin__h787640[5] ? + _theResult___sfd__h788376 : + sfdin__h787640[56:5] ; + assign out_sfd__h797163 = + _theResult___snd__h796425[5] ? + _theResult___sfd__h797160 : + _theResult___snd__h796425[56:5] ; + assign out_sfd__h818032 = + _theResult___snd__h817324[5] ? + _theResult___sfd__h818029 : + _theResult___snd__h817324[56:5] ; + assign out_sfd__h827683 = + sfdin__h826944[5] ? + _theResult___sfd__h827680 : + sfdin__h826944[56:5] ; + assign out_sfd__h836467 = + _theResult___snd__h835729[5] ? + _theResult___sfd__h836464 : + _theResult___snd__h835729[56:5] ; + assign pc__h973083 = fetchStage$pipelines_1_first[591:463] ; + assign pc_addrBits__h1005470 = INV_commitStage_commitTrap_BITS_217_TO_199__q15[0] ? - x__h1005644[13:0] : + x__h1005641[13:0] : commitStage_commitTrap[122:109] ; - assign pc_address__h1005472 = { 2'd0, commitStage_commitTrap[172:109] } ; - assign pend_ints__h928984 = + assign pc_address__h1005469 = { 2'd0, commitStage_commitTrap[172:109] } ; + assign pend_ints__h928981 = { _0_CONCAT_csrf_external_int_en_vec_3_read__6374_ETC___d20585, csrf_software_int_en_vec_3 & csrf_software_int_pend_vec_3, 1'd0, csrf_software_int_en_vec_1 & csrf_software_int_pend_vec_1, 1'd0 } ; - assign pointer__h245528 = + assign pointer__h245525 = coreFix_memExe_regToExeQ$first[383:318] + - { 2'd0, offset__h245518 } ; - assign prv__h1028891 = csrf_prv_reg ; - assign prv__h1028935 = csrf_mprv_reg ? csrf_mpp_reg : csrf_prv_reg ; - assign q___1__h711056 = + { 2'd0, offset__h245515 } ; + assign prv__h1028925 = csrf_prv_reg ; + assign prv__h1028969 = csrf_mprv_reg ? csrf_mpp_reg : csrf_prv_reg ; + assign q___1__h711053 = 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[203:140] ; - assign r1__read_BITS_13_TO_0___h929533 = + assign r1__read_BITS_13_TO_0___h929530 = { 4'd0, csrf_mideleg_11_reg, 1'b0, @@ -37115,129 +37087,129 @@ module mkCore(CLK, 1'b0, csrf_mideleg_5_3_reg, 1'b0 } ; - assign r1__read_BITS_13_TO_12___h935208 = csrf_fs_reg ; - assign r1__read_BIT_20___h935714 = csrf_tw_reg ; - assign r1__read__h859522 = { r1__read__h859524, csrf_ie_vec_1 } ; - assign r1__read__h859524 = { r1__read__h859526, 2'b0 } ; - assign r1__read__h859526 = { r1__read__h859528, csrf_prev_ie_vec_0 } ; - assign r1__read__h859528 = { r1__read__h859530, csrf_prev_ie_vec_1 } ; - assign r1__read__h859530 = { r1__read__h859532, 2'b0 } ; - assign r1__read__h859532 = { r1__read__h859534, csrf_spp_reg } ; - assign r1__read__h859534 = { r1__read__h859536, 4'b0 } ; - assign r1__read__h859536 = { r1__read__h859538, csrf_fs_reg } ; - assign r1__read__h859538 = { r1__read__h859540, 2'd0 } ; - assign r1__read__h859540 = { r1__read__h859542, 1'b0 } ; - assign r1__read__h859542 = { r1__read__h859544, csrf_sum_reg } ; - assign r1__read__h859544 = { r1__read__h859546, csrf_mxr_reg } ; - assign r1__read__h859546 = { r1__read__h859548, 12'b0 } ; - assign r1__read__h859548 = { r1__read__h859550, 2'b10 } ; - assign r1__read__h859550 = { r__h859554, 29'b0 } ; - assign r1__read__h859926 = - { r1__read__h859928, csrf_software_int_en_vec_1 } ; - assign r1__read__h859928 = { r1__read__h859930, 2'b0 } ; - assign r1__read__h859930 = { r1__read__h859932, 1'b0 } ; - assign r1__read__h859932 = { r1__read__h859934, csrf_timer_int_en_vec_1 } ; - assign r1__read__h859934 = { r1__read__h859936, 2'b0 } ; - assign r1__read__h859936 = { r1__read__h859938, 1'b0 } ; - assign r1__read__h859938 = { 54'b0, csrf_external_int_en_vec_1 } ; - assign r1__read__h860619 = { r1__read__h860621, csrf_scounteren_tm_reg } ; - assign r1__read__h860621 = { 61'd0, csrf_scounteren_ir_reg } ; - assign r1__read__h860924 = { csrf_scause_interrupt_reg, 58'b0 } ; - assign r1__read__h860931 = - { r1__read__h860933, csrf_software_int_pend_vec_1 } ; - assign r1__read__h860933 = { r1__read__h860935, 2'b0 } ; - assign r1__read__h860935 = { r1__read__h860937, 1'b0 } ; - assign r1__read__h860937 = - { r1__read__h860939, csrf_timer_int_pend_vec_1 } ; - assign r1__read__h860939 = { r1__read__h860941, 2'b0 } ; - assign r1__read__h860941 = { r1__read__h860943, 1'b0 } ; - assign r1__read__h860943 = { 54'b0, csrf_external_int_pend_vec_1 } ; - assign r1__read__h861141 = { vm_mode_reg__read__h861147, 16'd0 } ; - assign r1__read__h861164 = { r1__read__h861166, csrf_ie_vec_1 } ; - assign r1__read__h861166 = { r1__read__h861168, 1'b0 } ; - assign r1__read__h861168 = { r1__read__h861170, csrf_ie_vec_3 } ; - assign r1__read__h861170 = { r1__read__h861172, csrf_prev_ie_vec_0 } ; - assign r1__read__h861172 = { r1__read__h861174, csrf_prev_ie_vec_1 } ; - assign r1__read__h861174 = { r1__read__h861176, 1'b0 } ; - assign r1__read__h861176 = { r1__read__h861178, csrf_prev_ie_vec_3 } ; - assign r1__read__h861178 = { r1__read__h861180, csrf_spp_reg } ; - assign r1__read__h861180 = { r1__read__h861182, 2'b0 } ; - assign r1__read__h861182 = { r1__read__h861184, csrf_mpp_reg } ; - assign r1__read__h861184 = { r1__read__h861186, csrf_fs_reg } ; - assign r1__read__h861186 = { r1__read__h861188, 2'd0 } ; - assign r1__read__h861188 = { r1__read__h861190, csrf_mprv_reg } ; - assign r1__read__h861190 = { r1__read__h861192, csrf_sum_reg } ; - assign r1__read__h861192 = { r1__read__h861194, csrf_mxr_reg } ; - assign r1__read__h861194 = { r1__read__h861196, csrf_tvm_reg } ; - assign r1__read__h861196 = { r1__read__h861198, csrf_tw_reg } ; - assign r1__read__h861198 = { r1__read__h861200, csrf_tsr_reg } ; - assign r1__read__h861200 = { r1__read__h861202, 9'b0 } ; + assign r1__read_BITS_13_TO_12___h935205 = csrf_fs_reg ; + assign r1__read_BIT_20___h935711 = csrf_tw_reg ; + assign r1__read__h859520 = { r1__read__h859522, csrf_ie_vec_1 } ; + assign r1__read__h859522 = { r1__read__h859524, 2'b0 } ; + assign r1__read__h859524 = { r1__read__h859526, csrf_prev_ie_vec_0 } ; + assign r1__read__h859526 = { r1__read__h859528, csrf_prev_ie_vec_1 } ; + assign r1__read__h859528 = { r1__read__h859530, 2'b0 } ; + assign r1__read__h859530 = { r1__read__h859532, csrf_spp_reg } ; + assign r1__read__h859532 = { r1__read__h859534, 4'b0 } ; + assign r1__read__h859534 = { r1__read__h859536, csrf_fs_reg } ; + assign r1__read__h859536 = { r1__read__h859538, 2'd0 } ; + assign r1__read__h859538 = { r1__read__h859540, 1'b0 } ; + assign r1__read__h859540 = { r1__read__h859542, csrf_sum_reg } ; + assign r1__read__h859542 = { r1__read__h859544, csrf_mxr_reg } ; + assign r1__read__h859544 = { r1__read__h859546, 12'b0 } ; + assign r1__read__h859546 = { r1__read__h859548, 2'b10 } ; + assign r1__read__h859548 = { r__h859552, 29'b0 } ; + assign r1__read__h859924 = + { r1__read__h859926, csrf_software_int_en_vec_1 } ; + assign r1__read__h859926 = { r1__read__h859928, 2'b0 } ; + assign r1__read__h859928 = { r1__read__h859930, 1'b0 } ; + assign r1__read__h859930 = { r1__read__h859932, csrf_timer_int_en_vec_1 } ; + assign r1__read__h859932 = { r1__read__h859934, 2'b0 } ; + assign r1__read__h859934 = { r1__read__h859936, 1'b0 } ; + assign r1__read__h859936 = { 54'b0, csrf_external_int_en_vec_1 } ; + assign r1__read__h860617 = { r1__read__h860619, csrf_scounteren_tm_reg } ; + assign r1__read__h860619 = { 61'd0, csrf_scounteren_ir_reg } ; + assign r1__read__h860922 = { csrf_scause_interrupt_reg, 58'b0 } ; + assign r1__read__h860929 = + { r1__read__h860931, csrf_software_int_pend_vec_1 } ; + assign r1__read__h860931 = { r1__read__h860933, 2'b0 } ; + assign r1__read__h860933 = { r1__read__h860935, 1'b0 } ; + assign r1__read__h860935 = + { r1__read__h860937, csrf_timer_int_pend_vec_1 } ; + assign r1__read__h860937 = { r1__read__h860939, 2'b0 } ; + assign r1__read__h860939 = { r1__read__h860941, 1'b0 } ; + assign r1__read__h860941 = { 54'b0, csrf_external_int_pend_vec_1 } ; + assign r1__read__h861139 = { vm_mode_reg__read__h861145, 16'd0 } ; + assign r1__read__h861162 = { r1__read__h861164, csrf_ie_vec_1 } ; + assign r1__read__h861164 = { r1__read__h861166, 1'b0 } ; + assign r1__read__h861166 = { r1__read__h861168, csrf_ie_vec_3 } ; + assign r1__read__h861168 = { r1__read__h861170, csrf_prev_ie_vec_0 } ; + assign r1__read__h861170 = { r1__read__h861172, csrf_prev_ie_vec_1 } ; + assign r1__read__h861172 = { r1__read__h861174, 1'b0 } ; + assign r1__read__h861174 = { r1__read__h861176, csrf_prev_ie_vec_3 } ; + assign r1__read__h861176 = { r1__read__h861178, csrf_spp_reg } ; + assign r1__read__h861178 = { r1__read__h861180, 2'b0 } ; + assign r1__read__h861180 = { r1__read__h861182, csrf_mpp_reg } ; + assign r1__read__h861182 = { r1__read__h861184, csrf_fs_reg } ; + assign r1__read__h861184 = { r1__read__h861186, 2'd0 } ; + assign r1__read__h861186 = { r1__read__h861188, csrf_mprv_reg } ; + assign r1__read__h861188 = { r1__read__h861190, csrf_sum_reg } ; + assign r1__read__h861190 = { r1__read__h861192, csrf_mxr_reg } ; + assign r1__read__h861192 = { r1__read__h861194, csrf_tvm_reg } ; + assign r1__read__h861194 = { r1__read__h861196, csrf_tw_reg } ; + assign r1__read__h861196 = { r1__read__h861198, csrf_tsr_reg } ; + assign r1__read__h861198 = { r1__read__h861200, 9'b0 } ; + assign r1__read__h861200 = { r1__read__h861202, 2'b10 } ; assign r1__read__h861202 = { r1__read__h861204, 2'b10 } ; - assign r1__read__h861204 = { r1__read__h861206, 2'b10 } ; - assign r1__read__h861206 = { r__h859554, 27'b0 } ; - assign r1__read__h861289 = { r1__read__h861291, 1'b0 } ; - assign r1__read__h861291 = { r1__read__h861293, csrf_medeleg_13_11_reg } ; - assign r1__read__h861293 = { r1__read__h861295, 1'b0 } ; - assign r1__read__h861295 = { r1__read__h861297, csrf_medeleg_15_reg } ; - assign r1__read__h861297 = { r1__read__h861299, 10'b0 } ; - assign r1__read__h861299 = { 35'b0, csrf_medeleg_28_26_reg } ; - assign r1__read__h861312 = { r1__read__h861314, 1'b0 } ; - assign r1__read__h861314 = { r1__read__h861316, csrf_mideleg_5_3_reg } ; - assign r1__read__h861316 = { r1__read__h861318, 1'b0 } ; - assign r1__read__h861318 = { r1__read__h861320, csrf_mideleg_9_7_reg } ; - assign r1__read__h861320 = { r1__read__h861322, 1'b0 } ; - assign r1__read__h861322 = { 52'b0, csrf_mideleg_11_reg } ; - assign r1__read__h861336 = - { r1__read__h861338, csrf_software_int_en_vec_1 } ; - assign r1__read__h861338 = { r1__read__h861340, 1'b0 } ; - assign r1__read__h861340 = - { r1__read__h861342, csrf_software_int_en_vec_3 } ; - assign r1__read__h861342 = { r1__read__h861344, 1'b0 } ; - assign r1__read__h861344 = { r1__read__h861346, csrf_timer_int_en_vec_1 } ; - assign r1__read__h861346 = { r1__read__h861348, 1'b0 } ; - assign r1__read__h861348 = { r1__read__h861350, csrf_timer_int_en_vec_3 } ; - assign r1__read__h861350 = { r1__read__h861352, 1'b0 } ; - assign r1__read__h861352 = - { r1__read__h861354, csrf_external_int_en_vec_1 } ; - assign r1__read__h861354 = { r1__read__h861356, 1'b0 } ; - assign r1__read__h861356 = { 52'b0, csrf_external_int_en_vec_3 } ; - assign r1__read__h861612 = { r1__read__h861614, csrf_mcounteren_tm_reg } ; - assign r1__read__h861614 = { 61'd0, csrf_mcounteren_ir_reg } ; - assign r1__read__h861916 = { csrf_mcause_interrupt_reg, 58'd0 } ; - assign r1__read__h861923 = - { r1__read__h861925, csrf_software_int_pend_vec_1 } ; - assign r1__read__h861925 = { r1__read__h861927, 1'b0 } ; - assign r1__read__h861927 = - { r1__read__h861929, csrf_software_int_pend_vec_3 } ; - assign r1__read__h861929 = { r1__read__h861931, 1'b0 } ; - assign r1__read__h861931 = - { r1__read__h861933, csrf_timer_int_pend_vec_1 } ; - assign r1__read__h861933 = { r1__read__h861935, 1'b0 } ; - assign r1__read__h861935 = - { r1__read__h861937, csrf_timer_int_pend_vec_3 } ; - assign r1__read__h861937 = { r1__read__h861939, 1'b0 } ; - assign r1__read__h861939 = - { r1__read__h861941, csrf_external_int_pend_vec_1 } ; - assign r1__read__h861941 = { r1__read__h861943, 1'b0 } ; - assign r1__read__h861943 = { 52'b0, csrf_external_int_pend_vec_3 } ; - assign r1__read__h862252 = { 4'd0, csrf_rg_tdata1_dmode } ; - assign rVal1__h719448 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; - assign rVal2__h719449 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; - assign r___1__h711083 = + assign r1__read__h861204 = { r__h859552, 27'b0 } ; + assign r1__read__h861287 = { r1__read__h861289, 1'b0 } ; + assign r1__read__h861289 = { r1__read__h861291, csrf_medeleg_13_11_reg } ; + assign r1__read__h861291 = { r1__read__h861293, 1'b0 } ; + assign r1__read__h861293 = { r1__read__h861295, csrf_medeleg_15_reg } ; + assign r1__read__h861295 = { r1__read__h861297, 10'b0 } ; + assign r1__read__h861297 = { 35'b0, csrf_medeleg_28_26_reg } ; + assign r1__read__h861310 = { r1__read__h861312, 1'b0 } ; + assign r1__read__h861312 = { r1__read__h861314, csrf_mideleg_5_3_reg } ; + assign r1__read__h861314 = { r1__read__h861316, 1'b0 } ; + assign r1__read__h861316 = { r1__read__h861318, csrf_mideleg_9_7_reg } ; + assign r1__read__h861318 = { r1__read__h861320, 1'b0 } ; + assign r1__read__h861320 = { 52'b0, csrf_mideleg_11_reg } ; + assign r1__read__h861334 = + { r1__read__h861336, csrf_software_int_en_vec_1 } ; + assign r1__read__h861336 = { r1__read__h861338, 1'b0 } ; + assign r1__read__h861338 = + { r1__read__h861340, csrf_software_int_en_vec_3 } ; + assign r1__read__h861340 = { r1__read__h861342, 1'b0 } ; + assign r1__read__h861342 = { r1__read__h861344, csrf_timer_int_en_vec_1 } ; + assign r1__read__h861344 = { r1__read__h861346, 1'b0 } ; + assign r1__read__h861346 = { r1__read__h861348, csrf_timer_int_en_vec_3 } ; + assign r1__read__h861348 = { r1__read__h861350, 1'b0 } ; + assign r1__read__h861350 = + { r1__read__h861352, csrf_external_int_en_vec_1 } ; + assign r1__read__h861352 = { r1__read__h861354, 1'b0 } ; + assign r1__read__h861354 = { 52'b0, csrf_external_int_en_vec_3 } ; + assign r1__read__h861610 = { r1__read__h861612, csrf_mcounteren_tm_reg } ; + assign r1__read__h861612 = { 61'd0, csrf_mcounteren_ir_reg } ; + assign r1__read__h861914 = { csrf_mcause_interrupt_reg, 58'd0 } ; + assign r1__read__h861921 = + { r1__read__h861923, csrf_software_int_pend_vec_1 } ; + assign r1__read__h861923 = { r1__read__h861925, 1'b0 } ; + assign r1__read__h861925 = + { r1__read__h861927, csrf_software_int_pend_vec_3 } ; + assign r1__read__h861927 = { r1__read__h861929, 1'b0 } ; + assign r1__read__h861929 = + { r1__read__h861931, csrf_timer_int_pend_vec_1 } ; + assign r1__read__h861931 = { r1__read__h861933, 1'b0 } ; + assign r1__read__h861933 = + { r1__read__h861935, csrf_timer_int_pend_vec_3 } ; + assign r1__read__h861935 = { r1__read__h861937, 1'b0 } ; + assign r1__read__h861937 = + { r1__read__h861939, csrf_external_int_pend_vec_1 } ; + assign r1__read__h861939 = { r1__read__h861941, 1'b0 } ; + assign r1__read__h861941 = { 52'b0, csrf_external_int_pend_vec_3 } ; + assign r1__read__h862250 = { 4'd0, csrf_rg_tdata1_dmode } ; + assign rVal1__h719444 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; + assign rVal2__h719445 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; + assign r___1__h711080 = 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[139:76] ; - assign r__h859554 = csrf_fs_reg == 2'b11 ; - assign r__h861998 = csrf_software_int_pend_vec_3 ; - assign regRenamingTable_RDY_rename_0_claimRename__131_ETC___d21327 = - regRenamingTable$RDY_rename_0_claimRename && - fetchStage$RDY_pipelines_0_deq && + assign r__h859552 = csrf_fs_reg == 2'b11 ; + assign r__h861996 = csrf_software_int_pend_vec_3 ; + assign regRenamingTable_RDY_rename_0_getRename__1316__ETC___d21327 = + regRenamingTable$RDY_rename_0_getRename && + rob$RDY_enqPort_0_enq && fetchStage$RDY_pipelines_0_first && - epochManager$RDY_incrementEpoch && + fetchStage$RDY_pipelines_0_deq && (fetchStage$pipelines_0_first[268:266] != 3'd0 && fetchStage$pipelines_0_first[238:237] != 2'd1 && fetchStage$pipelines_0_first[238:237] != 2'd0 || coreFix_aluExe_0_rsAlu$RDY_enq) ; - assign regRenamingTable_RDY_rename_0_getRename__1315__ETC___d22153 = + assign regRenamingTable_RDY_rename_0_getRename__1316__ETC___d22153 = regRenamingTable$RDY_rename_0_getRename && CASE_fetchStagepipelines_0_first_BITS_265_TO__ETC__q269 && (fetchStage$pipelines_0_first[273:269] == 5'd19 || @@ -37510,85 +37482,85 @@ module mkCore(CLK, fetchStage$pipelines_0_first[69] || checkForException___d20942[13] || !rob$enqPort_0_canEnq ; - assign renaming_spec_bits__h978585 = + assign renaming_spec_bits__h978582 = fetchStage$pipelines_0_canDeq ? - y_avValue_snd_fst__h973229 : + y_avValue_snd_fst__h973226 : specTagManager$currentSpecBits ; - assign repBoundBits__h245543 = + assign repBoundBits__h245540 = { coreFix_memExe_regToExeQ$first[231:229], 11'd0 } ; - assign repBound__h1008332 = x__h1005862[13:11] - 3'b001 ; - assign repBound__h240209 = rf$read_3_rd1[13:11] - 3'b001 ; - assign repBound__h241894 = rf$read_3_rd2[13:11] - 3'b001 ; - assign repBound__h251108 = + assign repBound__h1008366 = x__h1005859[13:11] - 3'b001 ; + assign repBound__h240206 = rf$read_3_rd1[13:11] - 3'b001 ; + assign repBound__h241891 = rf$read_3_rd2[13:11] - 3'b001 ; + assign repBound__h251105 = coreFix_memExe_regToExeQ$first[245:243] - 3'b001 ; - assign repBound__h251633 = csrf_ddc_reg[13:11] - 3'b001 ; - assign repBound__h860491 = csrf_stcc_reg[13:11] - 3'b001 ; - assign repBound__h860813 = + assign repBound__h251630 = csrf_ddc_reg[13:11] - 3'b001 ; + assign repBound__h860489 = csrf_stcc_reg[13:11] - 3'b001 ; + assign repBound__h860811 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16275[13:11] - 3'b001 ; - assign repBound__h861484 = csrf_mtcc_reg[13:11] - 3'b001 ; - assign repBound__h861805 = + assign repBound__h861482 = csrf_mtcc_reg[13:11] - 3'b001 ; + assign repBound__h861803 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16427[13:11] - 3'b001 ; - assign repBound__h862314 = csrf_rg_dpc[13:11] - 3'b001 ; - assign repBound__h863992 = rf$read_1_rd1[13:11] - 3'b001 ; - assign repBound__h866954 = rf$read_1_rd2[13:11] - 3'b001 ; - assign repBound__h866972 = thin_bounds_baseBits__h866837[13:11] - 3'b001 ; - assign repBound__h873086 = x__h873025[13:11] - 3'b001 ; - assign repBound__h873634 = x__h873573[13:11] - 3'b001 ; - assign repBound__h905963 = rf$read_0_rd1[13:11] - 3'b001 ; - assign repBound__h908290 = rf$read_0_rd2[13:11] - 3'b001 ; - assign repBound__h908308 = thin_bounds_baseBits__h908193[13:11] - 3'b001 ; - assign repBound__h914127 = x__h914066[13:11] - 3'b001 ; - assign repBound__h914675 = x__h914614[13:11] - 3'b001 ; - assign res_addrBits__h127850 = + assign repBound__h862312 = csrf_rg_dpc[13:11] - 3'b001 ; + assign repBound__h863990 = rf$read_1_rd1[13:11] - 3'b001 ; + assign repBound__h866952 = rf$read_1_rd2[13:11] - 3'b001 ; + assign repBound__h866970 = thin_bounds_baseBits__h866835[13:11] - 3'b001 ; + assign repBound__h873084 = x__h873023[13:11] - 3'b001 ; + assign repBound__h873632 = x__h873571[13:11] - 3'b001 ; + assign repBound__h905960 = rf$read_0_rd1[13:11] - 3'b001 ; + assign repBound__h908287 = rf$read_0_rd2[13:11] - 3'b001 ; + assign repBound__h908305 = thin_bounds_baseBits__h908190[13:11] - 3'b001 ; + assign repBound__h914124 = x__h914063[13:11] - 3'b001 ; + assign repBound__h914672 = x__h914611[13:11] - 3'b001 ; + assign res_addrBits__h127849 = INV_coreFix_memExe_respLrScAmoQ_data_0_BITS_10_ETC__q8[0] ? - x__h128330[13:0] : + x__h128329[13:0] : coreFix_memExe_respLrScAmoQ_data_0[13:0] ; - assign res_addrBits__h140990 = + assign res_addrBits__h140989 = INV_mmio_dataRespQ_data_0_BITS_108_TO_90__q9[0] ? - x__h141474[13:0] : + x__h141473[13:0] : mmio_dataRespQ_data_0[13:0] ; - assign res_addrBits__h180674 = - INV_x85174_BITS_108_TO_90__q35[0] ? - x__h185256[13:0] : - x__h185174[13:0] ; - assign res_addrBits__h199751 = - INV_x01338_BITS_108_TO_90__q37[0] ? - x__h204319[13:0] : - x__h201338[13:0] ; - assign res_addrBits__h218915 = + assign res_addrBits__h180672 = + INV_x85172_BITS_108_TO_90__q35[0] ? + x__h185254[13:0] : + x__h185172[13:0] ; + assign res_addrBits__h199749 = + INV_x01336_BITS_108_TO_90__q37[0] ? + x__h204317[13:0] : + x__h201336[13:0] ; + assign res_addrBits__h218913 = INV_coreFix_memExe_lsqrespLd_BITS_108_TO_90__q10[0] ? - x__h219290[13:0] : + x__h219288[13:0] : coreFix_memExe_lsq$respLd[13:0] ; - assign res_addrBits__h238215 = { 2'b0, addr__h238208[63:52] } ; - assign res_addrBits__h571772 = + assign res_addrBits__h238212 = { 2'b0, addr__h238205[63:52] } ; + assign res_addrBits__h571768 = { 2'b0, coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[101:90] } ; - assign res_addrBits__h572624 = { 2'b0, data__h572105[63:52] } ; - assign res_addrBits__h618381 = { 2'b0, data__h617865[63:52] } ; - assign res_addrBits__h664128 = { 2'b0, data__h663612[63:52] } ; - assign res_addrBits__h710014 = { 2'b0, data__h709528[63:52] } ; - assign res_addrBits__h710960 = { 2'b0, data__h710474[63:52] } ; - assign res_addrBits__h855060 = { 2'b0, addr__h850291[63:52] } ; - assign res_addrBits__h899823 = { 2'b0, addr__h895062[63:52] } ; - assign res_address__h127849 = + assign res_addrBits__h572621 = { 2'b0, data__h572102[63:52] } ; + assign res_addrBits__h618378 = { 2'b0, data__h617862[63:52] } ; + assign res_addrBits__h664125 = { 2'b0, data__h663609[63:52] } ; + assign res_addrBits__h710011 = { 2'b0, data__h709525[63:52] } ; + assign res_addrBits__h710957 = { 2'b0, data__h710471[63:52] } ; + assign res_addrBits__h855057 = { 2'b0, addr__h850288[63:52] } ; + assign res_addrBits__h899821 = { 2'b0, addr__h895060[63:52] } ; + assign res_address__h127848 = { 2'd0, coreFix_memExe_respLrScAmoQ_data_0[63:0] } ; - assign res_address__h140989 = { 2'd0, mmio_dataRespQ_data_0[63:0] } ; - assign res_address__h180673 = { 2'd0, x__h185174[63:0] } ; - assign res_address__h199750 = { 2'd0, x__h201338[63:0] } ; - assign res_address__h218914 = { 2'd0, coreFix_memExe_lsq$respLd[63:0] } ; - assign res_address__h238214 = { 2'd0, addr__h238208 } ; - assign res_address__h571771 = + assign res_address__h140988 = { 2'd0, mmio_dataRespQ_data_0[63:0] } ; + assign res_address__h180671 = { 2'd0, x__h185172[63:0] } ; + assign res_address__h199748 = { 2'd0, x__h201336[63:0] } ; + assign res_address__h218912 = { 2'd0, coreFix_memExe_lsq$respLd[63:0] } ; + assign res_address__h238211 = { 2'd0, addr__h238205 } ; + assign res_address__h571767 = { 2'd0, coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[101:38] } ; - assign res_address__h572623 = { 2'd0, data__h572105 } ; - assign res_address__h618380 = { 2'd0, data__h617865 } ; - assign res_address__h664127 = { 2'd0, data__h663612 } ; - assign res_address__h710013 = { 2'd0, data__h709528 } ; - assign res_address__h710959 = { 2'd0, data__h710474 } ; - assign res_address__h855059 = { 2'd0, addr__h850291 } ; - assign res_address__h899822 = { 2'd0, addr__h895062 } ; - assign res_data__h572663 = { 32'hFFFFFFFF, x__h572678 } ; - assign res_data__h572668 = + assign res_address__h572620 = { 2'd0, data__h572102 } ; + assign res_address__h618377 = { 2'd0, data__h617862 } ; + assign res_address__h664124 = { 2'd0, data__h663609 } ; + assign res_address__h710010 = { 2'd0, data__h709525 } ; + assign res_address__h710956 = { 2'd0, data__h710471 } ; + assign res_address__h855056 = { 2'd0, addr__h850288 } ; + assign res_address__h899820 = { 2'd0, addr__h895060 } ; + assign res_data__h572660 = { 32'hFFFFFFFF, x__h572675 } ; + assign res_data__h572665 = { (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == @@ -37601,8 +37573,8 @@ module mkCore(CLK, 52'd0) ? 63'h7FF8000000000000 : coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:5] } ; - assign res_data__h618417 = { 32'hFFFFFFFF, x__h618432 } ; - assign res_data__h618422 = + assign res_data__h618414 = { 32'hFFFFFFFF, x__h618429 } ; + assign res_data__h618419 = { (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == @@ -37615,8 +37587,8 @@ module mkCore(CLK, 52'd0) ? 63'h7FF8000000000000 : coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:5] } ; - assign res_data__h664164 = { 32'hFFFFFFFF, x__h664179 } ; - assign res_data__h664169 = + assign res_data__h664161 = { 32'hFFFFFFFF, x__h664176 } ; + assign res_data__h664166 = { (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == @@ -37629,7 +37601,7 @@ module mkCore(CLK, 52'd0) ? 63'h7FF8000000000000 : coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:5] } ; - assign res_fflags__h572664 = + assign res_fflags__h572661 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[38:34] | coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[4:0] | { (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != @@ -37697,7 +37669,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d9474 } ; - assign res_fflags__h618418 = + assign res_fflags__h618415 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[38:34] | coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[4:0] | { (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != @@ -37765,7 +37737,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d10871 } ; - assign res_fflags__h664165 = + assign res_fflags__h664162 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[38:34] | coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[4:0] | { (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != @@ -37833,138 +37805,138 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d12268 } ; - assign resp_addr__h513542 = + assign resp_addr__h513540 = { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot[53:1], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getRq[168:158] } ; - assign result__h243493 = + assign result__h243490 = { 1'd0, ~coreFix_memExe_regToExeQ_first__664_BITS_383_T_ETC___d3723[64], coreFix_memExe_regToExeQ_first__664_BITS_383_T_ETC___d3723[63:0] } ; - assign result__h244650 = + assign result__h244647 = { 1'd0, ~coreFix_memExe_regToExeQ_first__664_BITS_220_T_ETC___d3785[64], coreFix_memExe_regToExeQ_first__664_BITS_220_T_ETC___d3785[63:0] } ; - assign result__h258271 = + assign result__h258268 = { 1'd0, ~coreFix_memExe_dTlb_procResp__276_BITS_452_TO__ETC___d4426[64], coreFix_memExe_dTlb_procResp__276_BITS_452_TO__ETC___d4426[63:0] } ; - assign result__h599131 = + assign result__h599128 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d8772[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d8772[0] | - guard__h599126 } ; - assign result__h644880 = + guard__h599123 } ; + assign result__h644877 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d10169[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d10169[0] | - guard__h644875 } ; - assign result__h690627 = + guard__h644872 } ; + assign result__h690624 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d11566[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d11566[0] | - guard__h690622 } ; - assign result__h741174 = + guard__h690619 } ; + assign result__h741170 = { _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d12910[56:1], _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d12910[0] | - guard__h741169 } ; - assign result__h780027 = + guard__h741165 } ; + assign result__h780023 = { _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d14395[56:1], _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d14395[0] | - guard__h780022 } ; - assign result__h819331 = + guard__h780018 } ; + assign result__h819327 = { _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d13625[56:1], _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d13625[0] | - guard__h819326 } ; - assign result__h924564 = w__h924559 & y__h924593 ; - assign result__h924615 = ~x__h924614 ; - assign result_d_addrBits__h1019532 = + guard__h819322 } ; + assign result__h924561 = w__h924556 & y__h924590 ; + assign result__h924612 = ~x__h924611 ; + assign result_d_addrBits__h1019566 = (csrf_stcc_reg[33:28] == 6'd52) ? - { 1'b0, newAddrBits__h1019520[12:0] } : - newAddrBits__h1019520[13:0] ; - assign result_d_addrBits__h1019935 = + { 1'b0, newAddrBits__h1019554[12:0] } : + newAddrBits__h1019554[13:0] ; + assign result_d_addrBits__h1019969 = (IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16291 == 6'd52) ? - { 1'b0, newAddrBits__h1019923[12:0] } : - newAddrBits__h1019923[13:0] ; - assign result_d_addrBits__h1020352 = + { 1'b0, newAddrBits__h1019957[12:0] } : + newAddrBits__h1019957[13:0] ; + assign result_d_addrBits__h1020386 = (csrf_mtcc_reg[33:28] == 6'd52) ? - { 1'b0, newAddrBits__h1020340[12:0] } : - newAddrBits__h1020340[13:0] ; - assign result_d_addrBits__h1020755 = + { 1'b0, newAddrBits__h1020374[12:0] } : + newAddrBits__h1020374[13:0] ; + assign result_d_addrBits__h1020789 = (IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16443 == 6'd52) ? - { 1'b0, newAddrBits__h1020743[12:0] } : - newAddrBits__h1020743[13:0] ; - assign result_d_addrBits__h1021424 = + { 1'b0, newAddrBits__h1020777[12:0] } : + newAddrBits__h1020777[13:0] ; + assign result_d_addrBits__h1021458 = (csrf_rg_dpc[33:28] == 6'd52) ? - { 1'b0, newAddrBits__h1021412[12:0] } : - newAddrBits__h1021412[13:0] ; - assign result_d_addrBits__h1043100 = + { 1'b0, newAddrBits__h1021446[12:0] } : + newAddrBits__h1021446[13:0] ; + assign result_d_addrBits__h1043133 = (csrf_stcc_reg[33:28] == 6'd52) ? - { 1'b0, newAddrBits__h1043088[12:0] } : - newAddrBits__h1043088[13:0] ; - assign result_d_addrBits__h1043503 = + { 1'b0, newAddrBits__h1043121[12:0] } : + newAddrBits__h1043121[13:0] ; + assign result_d_addrBits__h1043536 = (IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16291 == 6'd52) ? - { 1'b0, newAddrBits__h1043491[12:0] } : - newAddrBits__h1043491[13:0] ; - assign result_d_addrBits__h1043920 = + { 1'b0, newAddrBits__h1043524[12:0] } : + newAddrBits__h1043524[13:0] ; + assign result_d_addrBits__h1043953 = (csrf_mtcc_reg[33:28] == 6'd52) ? - { 1'b0, newAddrBits__h1043908[12:0] } : - newAddrBits__h1043908[13:0] ; - assign result_d_addrBits__h1044323 = + { 1'b0, newAddrBits__h1043941[12:0] } : + newAddrBits__h1043941[13:0] ; + assign result_d_addrBits__h1044356 = (IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16443 == 6'd52) ? - { 1'b0, newAddrBits__h1044311[12:0] } : - newAddrBits__h1044311[13:0] ; - assign result_d_addrBits__h1044990 = + { 1'b0, newAddrBits__h1044344[12:0] } : + newAddrBits__h1044344[13:0] ; + assign result_d_addrBits__h1045023 = (csrf_rg_dpc[33:28] == 6'd52) ? - { 1'b0, newAddrBits__h1044978[12:0] } : - newAddrBits__h1044978[13:0] ; - assign result_d_address__h1019531 = - { 2'd0, bot__h1019553 } + + { 1'b0, newAddrBits__h1045011[12:0] } : + newAddrBits__h1045011[13:0] ; + assign result_d_address__h1019565 = + { 2'd0, bot__h1019587 } + { 2'd0, rob$deqPort_0_deq_data[95:32] } ; - assign result_d_address__h1019934 = - { 2'd0, bot__h1019956 } + + assign result_d_address__h1019968 = + { 2'd0, bot__h1019990 } + { 2'd0, rob$deqPort_0_deq_data[95:32] } ; - assign result_d_address__h1020351 = - { 2'd0, bot__h1020373 } + + assign result_d_address__h1020385 = + { 2'd0, bot__h1020407 } + { 2'd0, rob$deqPort_0_deq_data[95:32] } ; - assign result_d_address__h1020754 = - { 2'd0, bot__h1020776 } + + assign result_d_address__h1020788 = + { 2'd0, bot__h1020810 } + { 2'd0, rob$deqPort_0_deq_data[95:32] } ; - assign result_d_address__h1021423 = - { 2'd0, bot__h1021446 } + + assign result_d_address__h1021457 = + { 2'd0, bot__h1021480 } + { 2'd0, rob$deqPort_0_deq_data[95:32] } ; - assign result_d_address__h1043099 = - { 2'd0, bot__h1019553 } + { 2'd0, f_csr_reqs$D_OUT[63:0] } ; - assign result_d_address__h1043502 = - { 2'd0, bot__h1019956 } + { 2'd0, f_csr_reqs$D_OUT[63:0] } ; - assign result_d_address__h1043919 = - { 2'd0, bot__h1020373 } + { 2'd0, f_csr_reqs$D_OUT[63:0] } ; - assign result_d_address__h1044322 = - { 2'd0, bot__h1020776 } + { 2'd0, f_csr_reqs$D_OUT[63:0] } ; - assign result_d_address__h1044989 = - { 2'd0, bot__h1021446 } + { 2'd0, f_csr_reqs$D_OUT[63:0] } ; - assign result_d_address__h245739 = { 2'd0, pointer__h245528[63:0] } ; - assign ret__h242870 = + assign result_d_address__h1043132 = + { 2'd0, bot__h1019587 } + { 2'd0, f_csr_reqs$D_OUT[63:0] } ; + assign result_d_address__h1043535 = + { 2'd0, bot__h1019990 } + { 2'd0, f_csr_reqs$D_OUT[63:0] } ; + assign result_d_address__h1043952 = + { 2'd0, bot__h1020407 } + { 2'd0, f_csr_reqs$D_OUT[63:0] } ; + assign result_d_address__h1044355 = + { 2'd0, bot__h1020810 } + { 2'd0, f_csr_reqs$D_OUT[63:0] } ; + assign result_d_address__h1045022 = + { 2'd0, bot__h1021480 } + { 2'd0, f_csr_reqs$D_OUT[63:0] } ; + assign result_d_address__h245736 = { 2'd0, pointer__h245525[63:0] } ; + assign ret__h242867 = { 1'd0, coreFix_memExe_regToExeQ_first__664_BITS_383_T_ETC___d3723[64:0] } ; - assign ret__h244027 = + assign ret__h244024 = { 1'd0, coreFix_memExe_regToExeQ_first__664_BITS_220_T_ETC___d3785[64:0] } ; - assign ret__h257648 = + assign ret__h257645 = { 1'd0, coreFix_memExe_dTlb_procResp__276_BITS_452_TO__ETC___d4426[64:0] } ; assign rf_read_0_rd1_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19345 = - rf$read_0_rd1[27:25] < repBound__h905963 ; + rf$read_0_rd1[27:25] < repBound__h905960 ; assign rf_read_0_rd1_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19358 = - rf$read_0_rd1[13:11] < repBound__h905963 ; + rf$read_0_rd1[13:11] < repBound__h905960 ; assign rf_read_0_rd1_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19372 = - rf$read_0_rd1[85:83] < repBound__h905963 ; + rf$read_0_rd1[85:83] < repBound__h905960 ; assign rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19413 = - rf$read_0_rd2[27:25] < repBound__h908290 ; + rf$read_0_rd2[27:25] < repBound__h908287 ; assign rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19414 = - rf$read_0_rd2[13:11] < repBound__h908290 ; + rf$read_0_rd2[13:11] < repBound__h908287 ; assign rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19416 = - rf$read_0_rd2[85:83] < repBound__h908290 ; + rf$read_0_rd2[85:83] < repBound__h908287 ; assign rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19426 = { rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19416, (rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19413 == @@ -37982,17 +37954,17 @@ module mkCore(CLK, 2'd1 : 2'd3) } ; assign rf_read_1_rd1_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16891 = - rf$read_1_rd1[27:25] < repBound__h863992 ; + rf$read_1_rd1[27:25] < repBound__h863990 ; assign rf_read_1_rd1_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16904 = - rf$read_1_rd1[13:11] < repBound__h863992 ; + rf$read_1_rd1[13:11] < repBound__h863990 ; assign rf_read_1_rd1_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16918 = - rf$read_1_rd1[85:83] < repBound__h863992 ; + rf$read_1_rd1[85:83] < repBound__h863990 ; assign rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16959 = - rf$read_1_rd2[27:25] < repBound__h866954 ; + rf$read_1_rd2[27:25] < repBound__h866952 ; assign rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16960 = - rf$read_1_rd2[13:11] < repBound__h866954 ; + rf$read_1_rd2[13:11] < repBound__h866952 ; assign rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16962 = - rf$read_1_rd2[85:83] < repBound__h866954 ; + rf$read_1_rd2[85:83] < repBound__h866952 ; assign rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16972 = { rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16962, (rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16959 == @@ -38010,25 +37982,25 @@ module mkCore(CLK, 2'd1 : 2'd3) } ; assign rf_read_3_rd1_coreFix_memExe_dispToRegQ_first__ETC___d3357 = - rf$read_3_rd1[27:25] < repBound__h240209 ; + rf$read_3_rd1[27:25] < repBound__h240206 ; assign rf_read_3_rd1_coreFix_memExe_dispToRegQ_first__ETC___d3370 = - rf$read_3_rd1[13:11] < repBound__h240209 ; + rf$read_3_rd1[13:11] < repBound__h240206 ; assign rf_read_3_rd1_coreFix_memExe_dispToRegQ_first__ETC___d3384 = - rf$read_3_rd1[85:83] < repBound__h240209 ; + rf$read_3_rd1[85:83] < repBound__h240206 ; assign rf_read_3_rd2_coreFix_memExe_dispToRegQ_first__ETC___d3611 = - rf$read_3_rd2[27:25] < repBound__h241894 ; + rf$read_3_rd2[27:25] < repBound__h241891 ; assign rf_read_3_rd2_coreFix_memExe_dispToRegQ_first__ETC___d3619 = - rf$read_3_rd2[13:11] < repBound__h241894 ; + rf$read_3_rd2[13:11] < repBound__h241891 ; assign rf_read_3_rd2_coreFix_memExe_dispToRegQ_first__ETC___d3628 = - rf$read_3_rd2[85:83] < repBound__h241894 ; - assign rg_core_run_state_read__0970_EQ_2_0971_AND_NOT_ETC___d24283 = + rf$read_3_rd2[85:83] < repBound__h241891 ; + assign rg_core_run_state_read__0970_EQ_2_0971_AND_NOT_ETC___d24285 = rg_core_run_state == 2'd2 && !flush_reservation && !flush_tlbs && !update_vm_info && fetchStage$iTlbIfc_flush_done && coreFix_memExe_dTlb$flush_done && !flush_caches ; - assign rg_tdata1__read__h858641 = - { r1__read__h862252, csrf_rg_tdata1_data } ; + assign rg_tdata1__read__h858639 = + { r1__read__h862250, csrf_rg_tdata1_data } ; assign rob_enqPort_1_canEnq__1933_AND_epochManager_ch_ETC___d21938 = rob$enqPort_1_canEnq && epochManager$checkEpoch_1_check && (!fetchStage$pipelines_0_canDeq || @@ -38038,296 +38010,296 @@ module mkCore(CLK, IF_IF_fetchStage_pipelines_0_first__0544_BITS__ETC___d21530) ; assign robdeqPort_0_deq_data_BITS_95_TO_32__q16 = rob$deqPort_0_deq_data[95:32] ; - assign satp_csr__read__h856331 = { r1__read__h861141, csrf_ppn_reg } ; - assign sbIdx__h153573 = + assign satp_csr__read__h856329 = { r1__read__h861139, csrf_ppn_reg } ; + assign sbIdx__h153572 = CAN_FIRE_RL_coreFix_memExe_doIssueSB ? coreFix_memExe_reqStQ_data_0_lat_0$wget[65:64] : coreFix_memExe_reqStQ_data_0_rl[65:64] ; - assign scause_csr__read__h856128 = - { r1__read__h860924, csrf_scause_code_reg } ; - assign scounteren_csr__read__h855988 = - { r1__read__h860619, csrf_scounteren_cy_reg } ; - assign sfd__h573274 = { value__h581501, 3'd0 } ; - assign sfd__h589082 = + assign scause_csr__read__h856126 = + { r1__read__h860922, csrf_scause_code_reg } ; + assign scounteren_csr__read__h855986 = + { r1__read__h860617, csrf_scounteren_cy_reg } ; + assign sfd__h573271 = { value__h581498, 3'd0 } ; + assign sfd__h589079 = { 1'b0, - _theResult___fst_exp__h588990 != 8'd0, - sfdin__h588984[56:34] } + + _theResult___fst_exp__h588987 != 8'd0, + sfdin__h588981[56:34] } + 25'd1 ; - assign sfd__h597664 = + assign sfd__h597661 = { 1'b0, - _theResult___fst_exp__h597646 != 8'd0, - _theResult___snd__h597597[56:34] } + + _theResult___fst_exp__h597643 != 8'd0, + _theResult___snd__h597594[56:34] } + 25'd1 ; - assign sfd__h606848 = + assign sfd__h606845 = { 1'b0, - _theResult___fst_exp__h606756 != 8'd0, - sfdin__h606750[56:34] } + + _theResult___fst_exp__h606753 != 8'd0, + sfdin__h606747[56:34] } + 25'd1 ; - assign sfd__h615460 = + assign sfd__h615457 = { 1'b0, - _theResult___fst_exp__h615441 != 8'd0, - _theResult___snd__h615387[56:34] } + + _theResult___fst_exp__h615438 != 8'd0, + _theResult___snd__h615384[56:34] } + 25'd1 ; - assign sfd__h619028 = { value__h627250, 3'd0 } ; - assign sfd__h634831 = + assign sfd__h619025 = { value__h627247, 3'd0 } ; + assign sfd__h634828 = { 1'b0, - _theResult___fst_exp__h634739 != 8'd0, - sfdin__h634733[56:34] } + + _theResult___fst_exp__h634736 != 8'd0, + sfdin__h634730[56:34] } + 25'd1 ; - assign sfd__h643413 = + assign sfd__h643410 = { 1'b0, - _theResult___fst_exp__h643395 != 8'd0, - _theResult___snd__h643346[56:34] } + + _theResult___fst_exp__h643392 != 8'd0, + _theResult___snd__h643343[56:34] } + 25'd1 ; - assign sfd__h652597 = + assign sfd__h652594 = { 1'b0, - _theResult___fst_exp__h652505 != 8'd0, - sfdin__h652499[56:34] } + + _theResult___fst_exp__h652502 != 8'd0, + sfdin__h652496[56:34] } + 25'd1 ; - assign sfd__h661209 = + assign sfd__h661206 = { 1'b0, - _theResult___fst_exp__h661190 != 8'd0, - _theResult___snd__h661136[56:34] } + + _theResult___fst_exp__h661187 != 8'd0, + _theResult___snd__h661133[56:34] } + 25'd1 ; - assign sfd__h664775 = { value__h672997, 3'd0 } ; - assign sfd__h680578 = + assign sfd__h664772 = { value__h672994, 3'd0 } ; + assign sfd__h680575 = { 1'b0, - _theResult___fst_exp__h680486 != 8'd0, - sfdin__h680480[56:34] } + + _theResult___fst_exp__h680483 != 8'd0, + sfdin__h680477[56:34] } + 25'd1 ; - assign sfd__h689160 = + assign sfd__h689157 = { 1'b0, - _theResult___fst_exp__h689142 != 8'd0, - _theResult___snd__h689093[56:34] } + + _theResult___fst_exp__h689139 != 8'd0, + _theResult___snd__h689090[56:34] } + 25'd1 ; - assign sfd__h698344 = + assign sfd__h698341 = { 1'b0, - _theResult___fst_exp__h698252 != 8'd0, - sfdin__h698246[56:34] } + + _theResult___fst_exp__h698249 != 8'd0, + sfdin__h698243[56:34] } + 25'd1 ; - assign sfd__h706956 = + assign sfd__h706953 = { 1'b0, - _theResult___fst_exp__h706937 != 8'd0, - _theResult___snd__h706883[56:34] } + + _theResult___fst_exp__h706934 != 8'd0, + _theResult___snd__h706880[56:34] } + 25'd1 ; - assign sfd__h720194 = { value__h724777, 32'd0 } ; - assign sfd__h739238 = + assign sfd__h720190 = { value__h724773, 32'd0 } ; + assign sfd__h739234 = { 1'b0, - _theResult___fst_exp__h739220 != 11'd0, - _theResult___snd__h739171[56:5] } + + _theResult___fst_exp__h739216 != 11'd0, + _theResult___snd__h739167[56:5] } + 54'd1 ; - assign sfd__h748889 = + assign sfd__h748885 = { 1'b0, - _theResult___fst_exp__h748797 != 11'd0, - sfdin__h748791[56:5] } + + _theResult___fst_exp__h748793 != 11'd0, + sfdin__h748787[56:5] } + 54'd1 ; - assign sfd__h757649 = + assign sfd__h757645 = { 1'b0, - _theResult___fst_exp__h757630 != 11'd0, - _theResult___snd__h757576[56:5] } + + _theResult___fst_exp__h757626 != 11'd0, + _theResult___snd__h757572[56:5] } + 54'd1 ; - assign sfd__h759188 = { value__h763630, 32'd0 } ; - assign sfd__h778091 = + assign sfd__h759184 = { value__h763626, 32'd0 } ; + assign sfd__h778087 = { 1'b0, - _theResult___fst_exp__h778073 != 11'd0, - _theResult___snd__h778024[56:5] } + + _theResult___fst_exp__h778069 != 11'd0, + _theResult___snd__h778020[56:5] } + 54'd1 ; - assign sfd__h787742 = + assign sfd__h787738 = { 1'b0, - _theResult___fst_exp__h787650 != 11'd0, - sfdin__h787644[56:5] } + + _theResult___fst_exp__h787646 != 11'd0, + sfdin__h787640[56:5] } + 54'd1 ; - assign sfd__h796502 = + assign sfd__h796498 = { 1'b0, - _theResult___fst_exp__h796483 != 11'd0, - _theResult___snd__h796429[56:5] } + + _theResult___fst_exp__h796479 != 11'd0, + _theResult___snd__h796425[56:5] } + 54'd1 ; - assign sfd__h798492 = { value__h802934, 32'd0 } ; - assign sfd__h817395 = + assign sfd__h798488 = { value__h802930, 32'd0 } ; + assign sfd__h817391 = { 1'b0, - _theResult___fst_exp__h817377 != 11'd0, - _theResult___snd__h817328[56:5] } + + _theResult___fst_exp__h817373 != 11'd0, + _theResult___snd__h817324[56:5] } + 54'd1 ; - assign sfd__h827046 = + assign sfd__h827042 = { 1'b0, - _theResult___fst_exp__h826954 != 11'd0, - sfdin__h826948[56:5] } + + _theResult___fst_exp__h826950 != 11'd0, + sfdin__h826944[56:5] } + 54'd1 ; - assign sfd__h835806 = + assign sfd__h835802 = { 1'b0, - _theResult___fst_exp__h835787 != 11'd0, - _theResult___snd__h835733[56:5] } + + _theResult___fst_exp__h835783 != 11'd0, + _theResult___snd__h835729[56:5] } + 54'd1 ; - assign sfdin__h588984 = - _theResult____h580879[56] ? - _theResult___snd__h589001 : - _theResult___snd__h589012 ; - assign sfdin__h606750 = - _theResult____h598518[56] ? - _theResult___snd__h606767 : - _theResult___snd__h606778 ; - assign sfdin__h634733 = - _theResult____h626630[56] ? - _theResult___snd__h634750 : - _theResult___snd__h634761 ; - assign sfdin__h652499 = - _theResult____h644267[56] ? - _theResult___snd__h652516 : - _theResult___snd__h652527 ; - assign sfdin__h680480 = - _theResult____h672377[56] ? - _theResult___snd__h680497 : - _theResult___snd__h680508 ; - assign sfdin__h698246 = - _theResult____h690014[56] ? - _theResult___snd__h698263 : - _theResult___snd__h698274 ; - assign sfdin__h748791 = - _theResult____h740561[56] ? - _theResult___snd__h748808 : - _theResult___snd__h748819 ; - assign sfdin__h787644 = - _theResult____h779414[56] ? - _theResult___snd__h787661 : - _theResult___snd__h787672 ; - assign sfdin__h826948 = - _theResult____h818718[56] ? - _theResult___snd__h826965 : - _theResult___snd__h826976 ; - assign sie_csr__read__h855900 = { r1__read__h859926, 1'b0 } ; - assign signBits__h1019335 = + assign sfdin__h588981 = + _theResult____h580876[56] ? + _theResult___snd__h588998 : + _theResult___snd__h589009 ; + assign sfdin__h606747 = + _theResult____h598515[56] ? + _theResult___snd__h606764 : + _theResult___snd__h606775 ; + assign sfdin__h634730 = + _theResult____h626627[56] ? + _theResult___snd__h634747 : + _theResult___snd__h634758 ; + assign sfdin__h652496 = + _theResult____h644264[56] ? + _theResult___snd__h652513 : + _theResult___snd__h652524 ; + assign sfdin__h680477 = + _theResult____h672374[56] ? + _theResult___snd__h680494 : + _theResult___snd__h680505 ; + assign sfdin__h698243 = + _theResult____h690011[56] ? + _theResult___snd__h698260 : + _theResult___snd__h698271 ; + assign sfdin__h748787 = + _theResult____h740557[56] ? + _theResult___snd__h748804 : + _theResult___snd__h748815 ; + assign sfdin__h787640 = + _theResult____h779410[56] ? + _theResult___snd__h787657 : + _theResult___snd__h787668 ; + assign sfdin__h826944 = + _theResult____h818714[56] ? + _theResult___snd__h826961 : + _theResult___snd__h826972 ; + assign sie_csr__read__h855898 = { r1__read__h859924, 1'b0 } ; + assign signBits__h1019369 = {50{robdeqPort_0_deq_data_BITS_95_TO_32__q16[63]}} ; - assign signBits__h1042903 = {50{f_csr_reqs$D_OUT[63]}} ; - assign signBits__h245534 = {50{offset__h245518[63]}} ; - assign sip_csr__read__h856268 = { r1__read__h860931, 1'b0 } ; - assign spec_bits__h983636 = specTagManager$currentSpecBits | y__h983649 ; - assign sstatus_csr__read__h855830 = { r1__read__h859522, csrf_ie_vec_0 } ; - assign tb__h873083 = { impliedTopBits__h872937, topBits__h872933[11] } ; - assign tb__h873631 = { impliedTopBits__h873485, topBits__h873481[11] } ; - assign tb__h914124 = { impliedTopBits__h913978, topBits__h913974[11] } ; - assign tb__h914672 = { impliedTopBits__h914526, topBits__h914522[11] } ; - assign thin_address__h1010115 = - csrf_prv_reg_read__0574_ULE_1_2990_AND_IF_comm_ETC___d23023 ? - IF_csrf_stcc_reg_read__6237_BIT_86_3112_AND_NO_ETC___d23280 : - IF_csrf_mtcc_reg_read__6389_BIT_86_3183_AND_NO_ETC___d23281 ; - assign tmpAddr__h245727 = pointer__h245528[63:0] ; - assign tmp_expBotHalf__h1005637 = + assign signBits__h1042936 = {50{f_csr_reqs$D_OUT[63]}} ; + assign signBits__h245531 = {50{offset__h245515[63]}} ; + assign sip_csr__read__h856266 = { r1__read__h860929, 1'b0 } ; + assign spec_bits__h983633 = specTagManager$currentSpecBits | y__h983646 ; + assign sstatus_csr__read__h855828 = { r1__read__h859520, csrf_ie_vec_0 } ; + assign tb__h873081 = { impliedTopBits__h872935, topBits__h872931[11] } ; + assign tb__h873629 = { impliedTopBits__h873483, topBits__h873479[11] } ; + assign tb__h914121 = { impliedTopBits__h913975, topBits__h913971[11] } ; + assign tb__h914669 = { impliedTopBits__h914523, topBits__h914519[11] } ; + assign thin_address__h1010149 = + csrf_prv_reg_read__0574_ULE_1_2990_AND_IF_comm_ETC___d23024 ? + IF_csrf_stcc_reg_read__6237_BIT_86_3114_AND_NO_ETC___d23282 : + IF_csrf_mtcc_reg_read__6389_BIT_86_3185_AND_NO_ETC___d23283 ; + assign tmpAddr__h245724 = pointer__h245525[63:0] ; + assign tmp_expBotHalf__h1005634 = { ~commitStage_commitTrap[175], commitStage_commitTrap[174:173] } ; - assign tmp_expBotHalf__h128323 = + assign tmp_expBotHalf__h128322 = { ~coreFix_memExe_respLrScAmoQ_data_0[66], coreFix_memExe_respLrScAmoQ_data_0[65:64] } ; - assign tmp_expBotHalf__h141467 = + assign tmp_expBotHalf__h141466 = { ~mmio_dataRespQ_data_0[66], mmio_dataRespQ_data_0[65:64] } ; - assign tmp_expBotHalf__h185249 = { ~x__h185174[66], x__h185174[65:64] } ; - assign tmp_expBotHalf__h204312 = { ~x__h201338[66], x__h201338[65:64] } ; - assign tmp_expBotHalf__h219283 = + assign tmp_expBotHalf__h185247 = { ~x__h185172[66], x__h185172[65:64] } ; + assign tmp_expBotHalf__h204310 = { ~x__h201336[66], x__h201336[65:64] } ; + assign tmp_expBotHalf__h219281 = { ~coreFix_memExe_lsq$respLd[66], coreFix_memExe_lsq$respLd[65:64] } ; - assign tmp_expBotHalf__h872786 = + assign tmp_expBotHalf__h872784 = { ~coreFix_aluExe_1_regToExeQ$first[244], coreFix_aluExe_1_regToExeQ$first[243:242] } ; - assign tmp_expBotHalf__h873334 = + assign tmp_expBotHalf__h873332 = { ~coreFix_aluExe_1_regToExeQ$first[115], coreFix_aluExe_1_regToExeQ$first[114:113] } ; - assign tmp_expBotHalf__h913827 = + assign tmp_expBotHalf__h913824 = { ~coreFix_aluExe_0_regToExeQ$first[244], coreFix_aluExe_0_regToExeQ$first[243:242] } ; - assign tmp_expBotHalf__h914375 = + assign tmp_expBotHalf__h914372 = { ~coreFix_aluExe_0_regToExeQ$first[115], coreFix_aluExe_0_regToExeQ$first[114:113] } ; - assign tmp_expTopHalf__h1005635 = + assign tmp_expTopHalf__h1005632 = { ~commitStage_commitTrap[189:188], commitStage_commitTrap[187] } ; - assign tmp_expTopHalf__h128321 = + assign tmp_expTopHalf__h128320 = { ~coreFix_memExe_respLrScAmoQ_data_0[80:79], coreFix_memExe_respLrScAmoQ_data_0[78] } ; - assign tmp_expTopHalf__h141465 = + assign tmp_expTopHalf__h141464 = { ~mmio_dataRespQ_data_0[80:79], mmio_dataRespQ_data_0[78] } ; - assign tmp_expTopHalf__h185247 = { ~x__h185174[80:79], x__h185174[78] } ; - assign tmp_expTopHalf__h204310 = { ~x__h201338[80:79], x__h201338[78] } ; - assign tmp_expTopHalf__h219281 = + assign tmp_expTopHalf__h185245 = { ~x__h185172[80:79], x__h185172[78] } ; + assign tmp_expTopHalf__h204308 = { ~x__h201336[80:79], x__h201336[78] } ; + assign tmp_expTopHalf__h219279 = { ~coreFix_memExe_lsq$respLd[80:79], coreFix_memExe_lsq$respLd[78] } ; - assign tmp_expTopHalf__h872784 = + assign tmp_expTopHalf__h872782 = { ~coreFix_aluExe_1_regToExeQ$first[258:257], coreFix_aluExe_1_regToExeQ$first[256] } ; - assign tmp_expTopHalf__h873332 = + assign tmp_expTopHalf__h873330 = { ~coreFix_aluExe_1_regToExeQ$first[129:128], coreFix_aluExe_1_regToExeQ$first[127] } ; - assign tmp_expTopHalf__h913825 = + assign tmp_expTopHalf__h913822 = { ~coreFix_aluExe_0_regToExeQ$first[258:257], coreFix_aluExe_0_regToExeQ$first[256] } ; - assign tmp_expTopHalf__h914373 = + assign tmp_expTopHalf__h914370 = { ~coreFix_aluExe_0_regToExeQ$first[129:128], coreFix_aluExe_0_regToExeQ$first[127] } ; - assign toBoundsM1__h1019348 = { 3'b110, ~csrf_stcc_reg[10:0] } ; - assign toBoundsM1__h1019751 = + assign toBoundsM1__h1019382 = { 3'b110, ~csrf_stcc_reg[10:0] } ; + assign toBoundsM1__h1019785 = { 3'b110, ~IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16275[10:0] } ; - assign toBoundsM1__h1020168 = { 3'b110, ~csrf_mtcc_reg[10:0] } ; - assign toBoundsM1__h1020571 = + assign toBoundsM1__h1020202 = { 3'b110, ~csrf_mtcc_reg[10:0] } ; + assign toBoundsM1__h1020605 = { 3'b110, ~IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16427[10:0] } ; - assign toBoundsM1__h1021240 = { 3'b110, ~csrf_rg_dpc[10:0] } ; - assign toBoundsM1__h245547 = - repBoundBits__h245543 + + assign toBoundsM1__h1021274 = { 3'b110, ~csrf_rg_dpc[10:0] } ; + assign toBoundsM1__h245544 = + repBoundBits__h245540 + ~coreFix_memExe_regToExeQ$first[317:304] ; - assign toBounds__h1019347 = 14'd14336 - { 3'b0, csrf_stcc_reg[10:0] } ; - assign toBounds__h1019750 = + assign toBounds__h1019381 = 14'd14336 - { 3'b0, csrf_stcc_reg[10:0] } ; + assign toBounds__h1019784 = 14'd14336 - { 3'b0, IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16275[10:0] } ; - assign toBounds__h1020167 = 14'd14336 - { 3'b0, csrf_mtcc_reg[10:0] } ; - assign toBounds__h1020570 = + assign toBounds__h1020201 = 14'd14336 - { 3'b0, csrf_mtcc_reg[10:0] } ; + assign toBounds__h1020604 = 14'd14336 - { 3'b0, IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16427[10:0] } ; - assign toBounds__h1021239 = 14'd14336 - { 3'b0, csrf_rg_dpc[10:0] } ; - assign toBounds__h245546 = - repBoundBits__h245543 - coreFix_memExe_regToExeQ$first[317:304] ; - assign topBits__h1005771 = + assign toBounds__h1021273 = 14'd14336 - { 3'b0, csrf_rg_dpc[10:0] } ; + assign toBounds__h245543 = + repBoundBits__h245540 - coreFix_memExe_regToExeQ$first[317:304] ; + assign topBits__h1005768 = INV_commitStage_commitTrap_BITS_217_TO_199__q15[0] ? { commitStage_commitTrap[198:190], 3'd0 } : - b_top__h1005868 ; - assign topBits__h128457 = + b_top__h1005865 ; + assign topBits__h128456 = INV_coreFix_memExe_respLrScAmoQ_data_0_BITS_10_ETC__q8[0] ? { coreFix_memExe_respLrScAmoQ_data_0[89:81], 3'd0 } : - b_top__h128554 ; - assign topBits__h141601 = + b_top__h128553 ; + assign topBits__h141600 = INV_mmio_dataRespQ_data_0_BITS_108_TO_90__q9[0] ? { mmio_dataRespQ_data_0[89:81], 3'd0 } : - b_top__h141698 ; - assign topBits__h185383 = - INV_x85174_BITS_108_TO_90__q35[0] ? - { x__h185174[89:81], 3'd0 } : - b_top__h185480 ; - assign topBits__h204446 = - INV_x01338_BITS_108_TO_90__q37[0] ? - { x__h201338[89:81], 3'd0 } : - b_top__h204543 ; - assign topBits__h219417 = + b_top__h141697 ; + assign topBits__h185381 = + INV_x85172_BITS_108_TO_90__q35[0] ? + { x__h185172[89:81], 3'd0 } : + b_top__h185478 ; + assign topBits__h204444 = + INV_x01336_BITS_108_TO_90__q37[0] ? + { x__h201336[89:81], 3'd0 } : + b_top__h204541 ; + assign topBits__h219415 = INV_coreFix_memExe_lsqrespLd_BITS_108_TO_90__q10[0] ? { coreFix_memExe_lsq$respLd[89:81], 3'd0 } : - b_top__h219514 ; - assign topBits__h872933 = + b_top__h219512 ; + assign topBits__h872931 = INV_coreFix_aluExe_1_regToExeQfirst_BITS_286__ETC__q11[0] ? { coreFix_aluExe_1_regToExeQ$first[267:259], 3'd0 } : - b_top__h873031 ; - assign topBits__h873481 = + b_top__h873029 ; + assign topBits__h873479 = INV_coreFix_aluExe_1_regToExeQfirst_BITS_157__ETC__q12[0] ? { coreFix_aluExe_1_regToExeQ$first[138:130], 3'd0 } : - b_top__h873579 ; - assign topBits__h913974 = + b_top__h873577 ; + assign topBits__h913971 = INV_coreFix_aluExe_0_regToExeQfirst_BITS_286__ETC__q13[0] ? { coreFix_aluExe_0_regToExeQ$first[267:259], 3'd0 } : - b_top__h914072 ; - assign topBits__h914522 = + b_top__h914069 ; + assign topBits__h914519 = INV_coreFix_aluExe_0_regToExeQfirst_BITS_157__ETC__q14[0] ? { coreFix_aluExe_0_regToExeQ$first[138:130], 3'd0 } : - b_top__h914620 ; - assign trap_val__h1007773 = { 53'd0, x__h1009594 } ; - assign upd__h1025280 = + b_top__h914617 ; + assign trap_val__h1007807 = { 53'd0, x__h1009628 } ; + assign upd__h1025314 = MUX_csrf_minstret_ehr_data_lat_0$wset_1__SEL_1 ? f_csr_reqs$D_OUT[63:0] : rob$deqPort_0_deq_data[95:32] ; @@ -38340,416 +38312,417 @@ module mkCore(CLK, MUX_csrf_mcycle_ehr_data_lat_0$wset_1__SEL_1 ? f_csr_reqs$D_OUT[63:0] : rob$deqPort_0_deq_data[95:32] ; - assign v__h1023555 = + assign v__h1023589 = { csrf_sepcc_reg_data_rl[152], csrf_sepcc_reg_data_rl[71:56], csrf_sepcc_reg_data_rl[54:53], csrf_sepcc_reg_data_rl[55], - CASE_csrf_sepcc_reg_data_rl_BITS_52_TO_35_2621_ETC__q276, + CASE_csrf_sepcc_reg_data_rl_BITS_52_TO_35_2621_ETC__q278, ~csrf_sepcc_reg_data_rl[34], - IF_csrf_sepcc_reg_read_wget__3894_BIT_34_3906__ETC___d23916[25:17], - ~IF_csrf_sepcc_reg_read_wget__3894_BIT_34_3906__ETC___d23916[16:15], - IF_csrf_sepcc_reg_read_wget__3894_BIT_34_3906__ETC___d23916[14:3], - ~IF_csrf_sepcc_reg_read_wget__3894_BIT_34_3906__ETC___d23916[2], - IF_csrf_sepcc_reg_read_wget__3894_BIT_34_3906__ETC___d23916[1:0], + IF_csrf_sepcc_reg_read_wget__3896_BIT_34_3908__ETC___d23918[25:17], + ~IF_csrf_sepcc_reg_read_wget__3896_BIT_34_3908__ETC___d23918[16:15], + IF_csrf_sepcc_reg_read_wget__3896_BIT_34_3908__ETC___d23918[14:3], + ~IF_csrf_sepcc_reg_read_wget__3896_BIT_34_3908__ETC___d23918[2], + IF_csrf_sepcc_reg_read_wget__3896_BIT_34_3908__ETC___d23918[1:0], csrf_sepcc_reg_data_rl[149:86] } ; - assign v__h1024264 = + assign v__h1024298 = { csrf_mepcc_reg_data_rl[152], csrf_mepcc_reg_data_rl[71:56], csrf_mepcc_reg_data_rl[54:53], csrf_mepcc_reg_data_rl[55], - CASE_csrf_mepcc_reg_data_rl_BITS_52_TO_35_2621_ETC__q277, + CASE_csrf_mepcc_reg_data_rl_BITS_52_TO_35_2621_ETC__q279, ~csrf_mepcc_reg_data_rl[34], - IF_csrf_mepcc_reg_read_wget__3928_BIT_34_3940__ETC___d23950[25:17], - ~IF_csrf_mepcc_reg_read_wget__3928_BIT_34_3940__ETC___d23950[16:15], - IF_csrf_mepcc_reg_read_wget__3928_BIT_34_3940__ETC___d23950[14:3], - ~IF_csrf_mepcc_reg_read_wget__3928_BIT_34_3940__ETC___d23950[2], - IF_csrf_mepcc_reg_read_wget__3928_BIT_34_3940__ETC___d23950[1:0], + IF_csrf_mepcc_reg_read_wget__3930_BIT_34_3942__ETC___d23952[25:17], + ~IF_csrf_mepcc_reg_read_wget__3930_BIT_34_3942__ETC___d23952[16:15], + IF_csrf_mepcc_reg_read_wget__3930_BIT_34_3942__ETC___d23952[14:3], + ~IF_csrf_mepcc_reg_read_wget__3930_BIT_34_3942__ETC___d23952[2], + IF_csrf_mepcc_reg_read_wget__3930_BIT_34_3942__ETC___d23952[1:0], csrf_mepcc_reg_data_rl[149:86] } ; - assign v__h519249 = + assign v__h519246 = IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d7318 ? - v__h519444 : + v__h519441 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ; - assign v__h519444 = + assign v__h519441 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd7) ? 3'd0 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP + 3'd1 ; - assign v__h521269 = + assign v__h521266 = IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d7412 ? - v__h521649 : + v__h521646 : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP ; - assign v__h521649 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP + 1'd1 ; - assign v__h536988 = + assign v__h521646 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP + 1'd1 ; + assign v__h536985 = IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d7571 ? - v__h537183 : + v__h537180 : coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP ; - assign v__h537183 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP + 1'd1 ; - assign v__h539437 = + assign v__h537180 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP + 1'd1 ; + assign v__h539434 = IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d7655 ? - v__h539632 : + v__h539629 : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP ; - assign v__h539632 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP + 1'd1 ; - assign v__h560457 = + assign v__h539629 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP + 1'd1 ; + assign v__h560454 = IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d7860 ? - v__h560652 : + v__h560649 : coreFix_memExe_memRespLdQ_enqP ; - assign v__h560652 = coreFix_memExe_memRespLdQ_enqP + 1'd1 ; - assign v__h564236 = + assign v__h560649 = coreFix_memExe_memRespLdQ_enqP + 1'd1 ; + assign v__h564233 = IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d7942 ? - v__h564431 : + v__h564428 : coreFix_memExe_forwardQ_enqP ; - assign v__h564431 = coreFix_memExe_forwardQ_enqP + 1'd1 ; - assign v__h841897 = + assign v__h564428 = coreFix_memExe_forwardQ_enqP + 1'd1 ; + assign v__h841893 = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_deqEn$whas ? - v__h841907 : + v__h841903 : coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit ; - assign v__h841907 = + assign v__h841903 = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit + 2'd1 ; - assign v__h842938 = v__h841897 - 2'd1 ; - assign value__h242587 = x__h242605 | in__h242697[63:0] ; - assign value__h242751 = - { coreFix_memExe_regToExeQ$first[381:332] & mask__h242758, + assign v__h842934 = v__h841893 - 2'd1 ; + assign value_BIT_23___h810070 = f3_exp__h798126 != 8'd0 ; + assign value__h242584 = x__h242602 | in__h242694[63:0] ; + assign value__h242748 = + { coreFix_memExe_regToExeQ$first[381:332] & mask__h242755, 14'd0 } + - addBase__h242757 ; - assign value__h243744 = x__h243762 | in__h243854[63:0] ; - assign value__h243908 = - { coreFix_memExe_regToExeQ$first[218:169] & mask__h243915, + addBase__h242754 ; + assign value__h243741 = x__h243759 | in__h243851[63:0] ; + assign value__h243905 = + { coreFix_memExe_regToExeQ$first[218:169] & mask__h243912, 14'd0 } + - addBase__h243914 ; - assign value__h257365 = x__h257383 | in__h257475[63:0] ; - assign value__h257529 = - { coreFix_memExe_dTlb$procResp[450:401] & mask__h257536, + addBase__h243911 ; + assign value__h257362 = x__h257380 | in__h257472[63:0] ; + assign value__h257526 = + { coreFix_memExe_dTlb$procResp[450:401] & mask__h257533, 14'd0 } + - addBase__h257535 ; - assign value__h581501 = + addBase__h257532 ; + assign value__h581498 = { 1'b0, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != 11'd0, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] } ; - assign value__h627250 = + assign value__h627247 = { 1'b0, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != 11'd0, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] } ; - assign value__h672997 = + assign value__h672994 = { 1'b0, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != 11'd0, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] } ; - assign value__h724777 = { 1'b0, f1_exp__h719832 != 8'd0, f1_sfd__h719833 } ; - assign value__h763630 = { 1'b0, f2_exp__h758826 != 8'd0, f2_sfd__h758827 } ; - assign value__h802934 = { 1'b0, f3_exp__h798130 != 8'd0, f3_sfd__h798131 } ; - assign vm_mode_reg__read__h861147 = { csrf_vm_mode_sv39_reg, 3'b0 } ; - assign w__h924559 = + assign value__h724773 = { 1'b0, f1_exp__h719828 != 8'd0, f1_sfd__h719829 } ; + assign value__h763626 = { 1'b0, f2_exp__h758822 != 8'd0, f2_sfd__h758823 } ; + assign value__h802930 = { 1'b0, value_BIT_23___h810070, f3_sfd__h798127 } ; + assign vm_mode_reg__read__h861145 = { csrf_vm_mode_sv39_reg, 3'b0 } ; + assign w__h924556 = coreFix_globalSpecUpdate_correctSpecTag_0$whas ? - result__h924615 : + result__h924612 : 12'd4095 ; - assign wordIdx__h266170 = + assign wordIdx__h266168 = coreFix_memExe_dMem_cache_m_banks_0_processAmo[165:164] ; - assign x1_avValue_new_pcc_capFat_bounds_baseBits__h1011620 = - csrf_prv_reg_read__0574_ULE_1_2990_AND_IF_comm_ETC___d23023 ? + assign x1_avValue_new_pcc_capFat_bounds_baseBits__h1011654 = + csrf_prv_reg_read__0574_ULE_1_2990_AND_IF_comm_ETC___d23024 ? csrf_stcc_reg[13:0] : csrf_mtcc_reg[13:0] ; - assign x__h1005644 = commitStage_commitTrap[172:109] >> x__h1005682 ; - assign x__h1005682 = - { tmp_expTopHalf__h1005635, tmp_expBotHalf__h1005637 } ; - assign x__h1005842 = { impliedTopBits__h1005775, topBits__h1005771 } ; - assign x__h1005859 = x__h1005862[13:12] + carry_out__h1005773 ; - assign x__h1005862 = + assign x__h1005641 = commitStage_commitTrap[172:109] >> x__h1005679 ; + assign x__h1005679 = + { tmp_expTopHalf__h1005632, tmp_expBotHalf__h1005634 } ; + assign x__h1005839 = { impliedTopBits__h1005772, topBits__h1005768 } ; + assign x__h1005856 = x__h1005859[13:12] + carry_out__h1005770 ; + assign x__h1005859 = INV_commitStage_commitTrap_BITS_217_TO_199__q15[0] ? { commitStage_commitTrap[186:176], 3'd0 } : - b_base__h1005869 ; - assign x__h1008320 = - x__h1008322 << + b_base__h1005866 ; + assign x__h1008354 = + x__h1008356 << IF_INV_commitStage_commitTrap_2639_BITS_217_TO_ETC___d22956 ; - assign x__h1008322 = { {48{offset__h1008308[15]}}, offset__h1008308 } ; - assign x__h1008407 = + assign x__h1008356 = { {48{offset__h1008342[15]}}, offset__h1008342 } ; + assign x__h1008441 = 66'h3FFFFFFFFFFFFFFFF << IF_INV_commitStage_commitTrap_2639_BITS_217_TO_ETC___d22956 ; - assign x__h1009594 = + assign x__h1009628 = { commitStage_commitTrap[42:37], CASE_commitStage_commitTrap_BITS_36_TO_32_0_co_ETC__q26 } ; - assign x__h1010294 = csrf_stcc_reg[33:28] + 6'd14 ; - assign x__h1010320 = { cause_code__h1006053, 2'b0 } ; - assign x__h1010421 = address__h1010227 >> csrf_stcc_reg[33:28] ; - assign x__h1010725 = address__h1010571 >> csrf_stcc_reg[33:28] ; - assign x__h1010951 = csrf_mtcc_reg[33:28] + 6'd14 ; - assign x__h1011078 = address__h1010884 >> csrf_mtcc_reg[33:28] ; - assign x__h1011382 = address__h1011228 >> csrf_mtcc_reg[33:28] ; - assign x__h1011617 = - csrf_prv_reg_read__0574_ULE_1_2990_AND_IF_comm_ETC___d23023 ? + assign x__h1010328 = csrf_stcc_reg[33:28] + 6'd14 ; + assign x__h1010354 = { cause_code__h1006050, 2'b0 } ; + assign x__h1010455 = address__h1010261 >> csrf_stcc_reg[33:28] ; + assign x__h1010759 = address__h1010605 >> csrf_stcc_reg[33:28] ; + assign x__h1010985 = csrf_mtcc_reg[33:28] + 6'd14 ; + assign x__h1011112 = address__h1010918 >> csrf_mtcc_reg[33:28] ; + assign x__h1011416 = address__h1011262 >> csrf_mtcc_reg[33:28] ; + assign x__h1011651 = + csrf_prv_reg_read__0574_ULE_1_2990_AND_IF_comm_ETC___d23024 ? csrf_stcc_reg[27:14] : csrf_mtcc_reg[27:14] ; - assign x__h1011638 = - csrf_prv_reg_read__0574_ULE_1_2990_AND_IF_comm_ETC___d23023 ? + assign x__h1011672 = + csrf_prv_reg_read__0574_ULE_1_2990_AND_IF_comm_ETC___d23024 ? csrf_stcc_reg[33:28] : csrf_mtcc_reg[33:28] ; - assign x__h1019365 = + assign x__h1019399 = robdeqPort_0_deq_data_BITS_95_TO_32__q16[63:14] ^ - signBits__h1019335 ; - assign x__h1019461 = rob$deqPort_0_deq_data[95:32] >> csrf_stcc_reg[33:28] ; - assign x__h1019864 = + signBits__h1019369 ; + assign x__h1019495 = rob$deqPort_0_deq_data[95:32] >> csrf_stcc_reg[33:28] ; + assign x__h1019898 = rob$deqPort_0_deq_data[95:32] >> IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16291 ; - assign x__h1020281 = rob$deqPort_0_deq_data[95:32] >> csrf_mtcc_reg[33:28] ; - assign x__h1020684 = + assign x__h1020315 = rob$deqPort_0_deq_data[95:32] >> csrf_mtcc_reg[33:28] ; + assign x__h1020718 = rob$deqPort_0_deq_data[95:32] >> IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16443 ; - assign x__h1021353 = rob$deqPort_0_deq_data[95:32] >> csrf_rg_dpc[33:28] ; - assign x__h1023576 = { 1'b0, csrf_spp_reg } ; - assign x__h1028046 = - NOT_rob_deqPort_0_canDeq__3983_3984_OR_rob_deq_ETC___d24208 ? - y_avValue_snd_snd_snd_fst__h1027868 : - IF_rob_deqPort_0_canDeq__3983_THEN_IF_NOT_rob__ETC___d24237 ; - assign x__h1042933 = f_csr_reqs$D_OUT[63:14] ^ signBits__h1042903 ; - assign x__h1043029 = f_csr_reqs$D_OUT[63:0] >> csrf_stcc_reg[33:28] ; - assign x__h1043432 = + assign x__h1021387 = rob$deqPort_0_deq_data[95:32] >> csrf_rg_dpc[33:28] ; + assign x__h1023610 = { 1'b0, csrf_spp_reg } ; + assign x__h1028080 = + NOT_rob_deqPort_0_canDeq__3985_3986_OR_rob_deq_ETC___d24210 ? + y_avValue_snd_snd_snd_fst__h1027902 : + IF_rob_deqPort_0_canDeq__3985_THEN_IF_NOT_rob__ETC___d24239 ; + assign x__h1042966 = f_csr_reqs$D_OUT[63:14] ^ signBits__h1042936 ; + assign x__h1043062 = f_csr_reqs$D_OUT[63:0] >> csrf_stcc_reg[33:28] ; + assign x__h1043465 = f_csr_reqs$D_OUT[63:0] >> IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16291 ; - assign x__h1043849 = f_csr_reqs$D_OUT[63:0] >> csrf_mtcc_reg[33:28] ; - assign x__h1044252 = + assign x__h1043882 = f_csr_reqs$D_OUT[63:0] >> csrf_mtcc_reg[33:28] ; + assign x__h1044285 = f_csr_reqs$D_OUT[63:0] >> IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16443 ; - assign x__h1044919 = f_csr_reqs$D_OUT[63:0] >> csrf_rg_dpc[33:28] ; - assign x__h128330 = coreFix_memExe_respLrScAmoQ_data_0[63:0] >> x__h128368 ; - assign x__h128368 = { tmp_expTopHalf__h128321, tmp_expBotHalf__h128323 } ; - assign x__h128528 = { impliedTopBits__h128461, topBits__h128457 } ; - assign x__h128545 = x__h128548[13:12] + carry_out__h128459 ; - assign x__h128548 = + assign x__h1044952 = f_csr_reqs$D_OUT[63:0] >> csrf_rg_dpc[33:28] ; + assign x__h128329 = coreFix_memExe_respLrScAmoQ_data_0[63:0] >> x__h128367 ; + assign x__h128367 = { tmp_expTopHalf__h128320, tmp_expBotHalf__h128322 } ; + assign x__h128527 = { impliedTopBits__h128460, topBits__h128456 } ; + assign x__h128544 = x__h128547[13:12] + carry_out__h128458 ; + assign x__h128547 = INV_coreFix_memExe_respLrScAmoQ_data_0_BITS_10_ETC__q8[0] ? { coreFix_memExe_respLrScAmoQ_data_0[77:67], 3'd0 } : - b_base__h128555 ; - assign x__h141474 = mmio_dataRespQ_data_0[63:0] >> x__h141512 ; - assign x__h141512 = { tmp_expTopHalf__h141465, tmp_expBotHalf__h141467 } ; - assign x__h141672 = { impliedTopBits__h141605, topBits__h141601 } ; - assign x__h141689 = x__h141692[13:12] + carry_out__h141603 ; - assign x__h141692 = + b_base__h128554 ; + assign x__h141473 = mmio_dataRespQ_data_0[63:0] >> x__h141511 ; + assign x__h141511 = { tmp_expTopHalf__h141464, tmp_expBotHalf__h141466 } ; + assign x__h141671 = { impliedTopBits__h141604, topBits__h141600 } ; + assign x__h141688 = x__h141691[13:12] + carry_out__h141602 ; + assign x__h141691 = INV_mmio_dataRespQ_data_0_BITS_108_TO_90__q9[0] ? { mmio_dataRespQ_data_0[77:67], 3'd0 } : - b_base__h141699 ; - assign x__h150548 = + b_base__h141698 ; + assign x__h150547 = coreFix_memExe_reqLdQ_data_0_lat_0$whas ? coreFix_memExe_reqLdQ_data_0_lat_0$wget[68:64] : coreFix_memExe_reqLdQ_data_0_rl[68:64] ; - assign x__h153682 = { 3'd0, sbIdx__h153573 } ; - assign x__h185174 = + assign x__h153681 = { 3'd0, sbIdx__h153572 } ; + assign x__h185172 = (coreFix_memExe_lsq$firstLd[125:110] == 16'd65535) ? coreFix_memExe_respLrScAmoQ_data_0[127:0] : { 64'd0, IF_coreFix_memExe_lsq_firstLd__502_BIT_117_525_ETC___d1917 } ; - assign x__h185256 = x__h185174[63:0] >> x__h185294 ; - assign x__h185294 = { tmp_expTopHalf__h185247, tmp_expBotHalf__h185249 } ; - assign x__h185454 = { impliedTopBits__h185387, topBits__h185383 } ; - assign x__h185471 = x__h185474[13:12] + carry_out__h185385 ; - assign x__h185474 = - INV_x85174_BITS_108_TO_90__q35[0] ? - { x__h185174[77:67], 3'd0 } : - b_base__h185481 ; - assign x__h201338 = + assign x__h185254 = x__h185172[63:0] >> x__h185292 ; + assign x__h185292 = { tmp_expTopHalf__h185245, tmp_expBotHalf__h185247 } ; + assign x__h185452 = { impliedTopBits__h185385, topBits__h185381 } ; + assign x__h185469 = x__h185472[13:12] + carry_out__h185383 ; + assign x__h185472 = + INV_x85172_BITS_108_TO_90__q35[0] ? + { x__h185172[77:67], 3'd0 } : + b_base__h185479 ; + assign x__h201336 = (coreFix_memExe_lsq$firstLd[125:110] == 16'd65535) ? mmio_dataRespQ_data_0[127:0] : { 64'd0, IF_coreFix_memExe_lsq_firstLd__502_BIT_117_525_ETC___d2085 } ; - assign x__h204319 = x__h201338[63:0] >> x__h204357 ; - assign x__h204357 = { tmp_expTopHalf__h204310, tmp_expBotHalf__h204312 } ; - assign x__h204517 = { impliedTopBits__h204450, topBits__h204446 } ; - assign x__h204534 = x__h204537[13:12] + carry_out__h204448 ; - assign x__h204537 = - INV_x01338_BITS_108_TO_90__q37[0] ? - { x__h201338[77:67], 3'd0 } : - b_base__h204544 ; - assign x__h219290 = coreFix_memExe_lsq$respLd[63:0] >> x__h219328 ; - assign x__h219328 = { tmp_expTopHalf__h219281, tmp_expBotHalf__h219283 } ; - assign x__h219488 = { impliedTopBits__h219421, topBits__h219417 } ; - assign x__h219505 = x__h219508[13:12] + carry_out__h219419 ; - assign x__h219508 = + assign x__h204317 = x__h201336[63:0] >> x__h204355 ; + assign x__h204355 = { tmp_expTopHalf__h204308, tmp_expBotHalf__h204310 } ; + assign x__h204515 = { impliedTopBits__h204448, topBits__h204444 } ; + assign x__h204532 = x__h204535[13:12] + carry_out__h204446 ; + assign x__h204535 = + INV_x01336_BITS_108_TO_90__q37[0] ? + { x__h201336[77:67], 3'd0 } : + b_base__h204542 ; + assign x__h219288 = coreFix_memExe_lsq$respLd[63:0] >> x__h219326 ; + assign x__h219326 = { tmp_expTopHalf__h219279, tmp_expBotHalf__h219281 } ; + assign x__h219486 = { impliedTopBits__h219419, topBits__h219415 } ; + assign x__h219503 = x__h219506[13:12] + carry_out__h219417 ; + assign x__h219506 = INV_coreFix_memExe_lsqrespLd_BITS_108_TO_90__q10[0] ? { coreFix_memExe_lsq$respLd[77:67], 3'd0 } : - b_base__h219515 ; - assign x__h238637 = + b_base__h219513 ; + assign x__h238634 = (coreFix_memExe_dispToRegQ$first[110] && coreFix_memExe_dispToRegQ$first[109:103] != 7'd0) ? IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3075 : 66'd0 ; - assign x__h242605 = x__h242607 << coreFix_memExe_regToExeQ$first[265:260] ; - assign x__h242607 = { {48{offset__h242593[15]}}, offset__h242593 } ; - assign x__h242715 = + assign x__h242602 = x__h242604 << coreFix_memExe_regToExeQ$first[265:260] ; + assign x__h242604 = { {48{offset__h242590[15]}}, offset__h242590 } ; + assign x__h242712 = 66'h3FFFFFFFFFFFFFFFF << coreFix_memExe_regToExeQ$first[265:260] ; - assign x__h242863 = + assign x__h242860 = coreFix_memExe_regToExeQ_first__664_BITS_265_T_ETC___d3736 ? - result__h243493 : - ret__h242870 ; - assign x__h242965 = + result__h243490 : + ret__h242867 ; + assign x__h242962 = { coreFix_memExe_regToExeQ$first[225:224], coreFix_memExe_regToExeQ$first[259:246] } ; - assign x__h243034 = + assign x__h243031 = (coreFix_memExe_regToExeQ$first[265:260] == 6'd50) ? coreFix_memExe_regToExeQ$first[245] : coreFix_memExe_regToExeQfirst_BITS_381_TO_332_ETC__q3[49] ; - assign x__h243762 = x__h243764 << coreFix_memExe_regToExeQ$first[102:97] ; - assign x__h243764 = { {48{offset__h243750[15]}}, offset__h243750 } ; - assign x__h243872 = + assign x__h243759 = x__h243761 << coreFix_memExe_regToExeQ$first[102:97] ; + assign x__h243761 = { {48{offset__h243747[15]}}, offset__h243747 } ; + assign x__h243869 = 66'h3FFFFFFFFFFFFFFFF << coreFix_memExe_regToExeQ$first[102:97] ; - assign x__h244020 = + assign x__h244017 = coreFix_memExe_regToExeQ_first__664_BITS_102_T_ETC___d3798 ? - result__h244650 : - ret__h244027 ; - assign x__h244122 = + result__h244647 : + ret__h244024 ; + assign x__h244119 = { coreFix_memExe_regToExeQ$first[62:61], coreFix_memExe_regToExeQ$first[96:83] } ; - assign x__h244191 = + assign x__h244188 = (coreFix_memExe_regToExeQ$first[102:97] == 6'd50) ? coreFix_memExe_regToExeQ$first[82] : coreFix_memExe_regToExeQfirst_BITS_218_TO_169_ETC__q5[49] ; - assign x__h245564 = offset__h245518[63:14] ^ signBits__h245534 ; - assign x__h245667 = - offset__h245518 >> coreFix_memExe_regToExeQ$first[265:260] ; - assign x__h247568 = { pointer__h245528[3:0], 3'b0 } ; - assign x__h251010 = - pointer__h245528 >> coreFix_memExe_regToExeQ$first[265:260] ; - assign x__h252368 = x__h252380 + y__h252381 ; - assign x__h252380 = x__h252392 + y__h252393 ; - assign x__h252392 = x__h252404 + y__h252405 ; - assign x__h252404 = x__h252416 + y__h252417 ; - assign x__h252416 = x__h252428 + y__h252429 ; - assign x__h252428 = x__h252440 + y__h252441 ; - assign x__h252440 = x__h252452 + y__h252453 ; - assign x__h252452 = x__h252464 + y__h252465 ; - assign x__h252464 = x__h252476 + y__h252477 ; - assign x__h252476 = x__h252488 + y__h252489 ; - assign x__h252488 = x__h252500 + y__h252501 ; - assign x__h252500 = x__h252512 + y__h252513 ; - assign x__h252512 = x__h252524 + y__h252525 ; - assign x__h252524 = x__h252536 + y__h252537 ; - assign x__h252536 = { 4'd0, coreFix_memExe_lsq$getOrigBE[15] } ; - assign x__h257383 = x__h257385 << coreFix_memExe_dTlb$procResp[334:329] ; - assign x__h257385 = { {48{offset__h257371[15]}}, offset__h257371 } ; - assign x__h257493 = + assign x__h245561 = offset__h245515[63:14] ^ signBits__h245531 ; + assign x__h245664 = + offset__h245515 >> coreFix_memExe_regToExeQ$first[265:260] ; + assign x__h247565 = { pointer__h245525[3:0], 3'b0 } ; + assign x__h251007 = + pointer__h245525 >> coreFix_memExe_regToExeQ$first[265:260] ; + assign x__h252365 = x__h252377 + y__h252378 ; + assign x__h252377 = x__h252389 + y__h252390 ; + assign x__h252389 = x__h252401 + y__h252402 ; + assign x__h252401 = x__h252413 + y__h252414 ; + assign x__h252413 = x__h252425 + y__h252426 ; + assign x__h252425 = x__h252437 + y__h252438 ; + assign x__h252437 = x__h252449 + y__h252450 ; + assign x__h252449 = x__h252461 + y__h252462 ; + assign x__h252461 = x__h252473 + y__h252474 ; + assign x__h252473 = x__h252485 + y__h252486 ; + assign x__h252485 = x__h252497 + y__h252498 ; + assign x__h252497 = x__h252509 + y__h252510 ; + assign x__h252509 = x__h252521 + y__h252522 ; + assign x__h252521 = x__h252533 + y__h252534 ; + assign x__h252533 = { 4'd0, coreFix_memExe_lsq$getOrigBE[15] } ; + assign x__h257380 = x__h257382 << coreFix_memExe_dTlb$procResp[334:329] ; + assign x__h257382 = { {48{offset__h257368[15]}}, offset__h257368 } ; + assign x__h257490 = 66'h3FFFFFFFFFFFFFFFF << coreFix_memExe_dTlb$procResp[334:329] ; - assign x__h257641 = + assign x__h257638 = coreFix_memExe_dTlb_procResp__276_BITS_334_TO__ETC___d4439 ? - result__h258271 : - ret__h257648 ; - assign x__h257743 = + result__h258268 : + ret__h257645 ; + assign x__h257740 = { coreFix_memExe_dTlb$procResp[294:293], coreFix_memExe_dTlb$procResp[328:315] } ; - assign x__h257812 = + assign x__h257809 = (coreFix_memExe_dTlb$procResp[334:329] == 6'd50) ? coreFix_memExe_dTlb$procResp[314] : coreFix_memExe_dTlbprocResp_BITS_450_TO_401_P_ETC__q7[49] ; - assign x__h526100 = + assign x__h526097 = EN_dCacheToParent_fromP_enq ? coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[2:0] : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[2:0] ; - assign x__h572678 = - { (_theResult___exp__h616010 != 8'd255 || - _theResult___sfd__h616011 == 23'd0) && + assign x__h572675 = + { (_theResult___exp__h616007 != 8'd255 || + _theResult___sfd__h616008 == 23'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9354, - out_f_exp__h616287, - out_f_sfd__h616288 } ; - assign x__h599228 = - sfd__h573274 << (x__h599261[11] ? 12'hAAA : x__h599261) ; - assign x__h599261 = + out_f_exp__h616284, + out_f_sfd__h616285 } ; + assign x__h599225 = + sfd__h573271 << (x__h599258[11] ? 12'hAAA : x__h599258) ; + assign x__h599258 = 12'd57 - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d8768 ; - assign x__h618432 = - { (_theResult___exp__h661759 != 8'd255 || - _theResult___sfd__h661760 == 23'd0) && + assign x__h618429 = + { (_theResult___exp__h661756 != 8'd255 || + _theResult___sfd__h661757 == 23'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10751, - out_f_exp__h662036, - out_f_sfd__h662037 } ; - assign x__h644977 = - sfd__h619028 << (x__h645010[11] ? 12'hAAA : x__h645010) ; - assign x__h645010 = + out_f_exp__h662033, + out_f_sfd__h662034 } ; + assign x__h644974 = + sfd__h619025 << (x__h645007[11] ? 12'hAAA : x__h645007) ; + assign x__h645007 = 12'd57 - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d10165 ; assign x__h65639 = mmio_pRqQ_data_0[31:0] ; - assign x__h664179 = - { (_theResult___exp__h707506 != 8'd255 || - _theResult___sfd__h707507 == 23'd0) && + assign x__h664176 = + { (_theResult___exp__h707503 != 8'd255 || + _theResult___sfd__h707504 == 23'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12148, - out_f_exp__h707783, - out_f_sfd__h707784 } ; - assign x__h690724 = - sfd__h664775 << (x__h690757[11] ? 12'hAAA : x__h690757) ; - assign x__h690757 = + out_f_exp__h707780, + out_f_sfd__h707781 } ; + assign x__h690721 = + sfd__h664772 << (x__h690754[11] ? 12'hAAA : x__h690754) ; + assign x__h690754 = 12'd57 - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d11562 ; - assign x__h719354 = + assign x__h719350 = sbCons$lazyLookup_2_get[3] ? rf$read_2_rd1[149:86] : - y_avValue__h715403 ; - assign x__h719355 = + y_avValue__h715399 ; + assign x__h719351 = sbCons$lazyLookup_2_get[2] ? rf$read_2_rd2[149:86] : - y_avValue__h716111 ; - assign x__h719356 = + y_avValue__h716107 ; + assign x__h719352 = sbCons$lazyLookup_2_get[1] ? rf$read_2_rd3[149:86] : - y_avValue__h716813 ; - assign x__h741269 = sfd__h720194 << x__h741302 ; - assign x__h741302 = + y_avValue__h716809 ; + assign x__h741265 = sfd__h720190 << x__h741298 ; + assign x__h741298 = 12'd57 - _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d12906 ; - assign x__h780122 = sfd__h759188 << x__h780155 ; - assign x__h780155 = + assign x__h780118 = sfd__h759184 << x__h780151 ; + assign x__h780151 = 12'd57 - _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d14391 ; - assign x__h819426 = sfd__h798492 << x__h819459 ; - assign x__h819459 = + assign x__h819422 = sfd__h798488 << x__h819455 ; + assign x__h819455 = 12'd57 - _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d13621 ; - assign x__h841215 = + assign x__h841211 = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? - _theResult___fst__h841226 : - a__h840678 ; - assign x__h841241 = a__h840678[63] ^ b__h840679[63] ; - assign x__h841827 = + _theResult___fst__h841222 : + a__h840674 ; + assign x__h841237 = a__h840674[63] ^ b__h840675[63] ; + assign x__h841823 = (coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$D_OUT == 64'd0) ? { 64'hFFFFFFFFFFFFFFFF, coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$D_OUT[139:76] } : { coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d15402, coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d15403 } ; - assign x__h859507 = { csrf_frm_reg, csrf_fflags_reg } ; - assign x__h860587 = 66'h3FFFFFFFFFFFFFFFF << csrf_stcc_reg[33:28] ; - assign x__h860648 = - x__h860650 << + assign x__h859505 = { csrf_frm_reg, csrf_fflags_reg } ; + assign x__h860585 = 66'h3FFFFFFFFFFFFFFFF << csrf_stcc_reg[33:28] ; + assign x__h860646 = + x__h860648 << IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16291 ; - assign x__h860650 = { {48{offset__h860636[15]}}, offset__h860636 } ; - assign x__h860892 = + assign x__h860648 = { {48{offset__h860634[15]}}, offset__h860634 } ; + assign x__h860890 = 66'h3FFFFFFFFFFFFFFFF << IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16291 ; - assign x__h861580 = 66'h3FFFFFFFFFFFFFFFF << csrf_mtcc_reg[33:28] ; - assign x__h861641 = - x__h861643 << + assign x__h861578 = 66'h3FFFFFFFFFFFFFFFF << csrf_mtcc_reg[33:28] ; + assign x__h861639 = + x__h861641 << IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16443 ; - assign x__h861643 = { {48{offset__h861629[15]}}, offset__h861629 } ; - assign x__h861884 = + assign x__h861641 = { {48{offset__h861627[15]}}, offset__h861627 } ; + assign x__h861882 = 66'h3FFFFFFFFFFFFFFFF << IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16443 ; - assign x__h862410 = 66'h3FFFFFFFFFFFFFFFF << csrf_rg_dpc[33:28] ; - assign x__h872794 = - coreFix_aluExe_1_regToExeQ$first[241:178] >> x__h872832 ; - assign x__h872832 = { tmp_expTopHalf__h872784, tmp_expBotHalf__h872786 } ; - assign x__h873005 = { impliedTopBits__h872937, topBits__h872933 } ; - assign x__h873022 = x__h873025[13:12] + carry_out__h872935 ; - assign x__h873025 = + assign x__h862408 = 66'h3FFFFFFFFFFFFFFFF << csrf_rg_dpc[33:28] ; + assign x__h872792 = + coreFix_aluExe_1_regToExeQ$first[241:178] >> x__h872830 ; + assign x__h872830 = { tmp_expTopHalf__h872782, tmp_expBotHalf__h872784 } ; + assign x__h873003 = { impliedTopBits__h872935, topBits__h872931 } ; + assign x__h873020 = x__h873023[13:12] + carry_out__h872933 ; + assign x__h873023 = INV_coreFix_aluExe_1_regToExeQfirst_BITS_286__ETC__q11[0] ? { coreFix_aluExe_1_regToExeQ$first[255:245], 3'd0 } : - b_base__h873032 ; - assign x__h873342 = coreFix_aluExe_1_regToExeQ$first[112:49] >> x__h873380 ; - assign x__h873380 = { tmp_expTopHalf__h873332, tmp_expBotHalf__h873334 } ; - assign x__h873553 = { impliedTopBits__h873485, topBits__h873481 } ; - assign x__h873570 = x__h873573[13:12] + carry_out__h873483 ; - assign x__h873573 = + b_base__h873030 ; + assign x__h873340 = coreFix_aluExe_1_regToExeQ$first[112:49] >> x__h873378 ; + assign x__h873378 = { tmp_expTopHalf__h873330, tmp_expBotHalf__h873332 } ; + assign x__h873551 = { impliedTopBits__h873483, topBits__h873479 } ; + assign x__h873568 = x__h873571[13:12] + carry_out__h873481 ; + assign x__h873571 = INV_coreFix_aluExe_1_regToExeQfirst_BITS_157__ETC__q12[0] ? { coreFix_aluExe_1_regToExeQ$first[126:116], 3'd0 } : - b_base__h873580 ; - assign x__h873780 = + b_base__h873578 ; + assign x__h873778 = { basicExec___d17927[443], basicExec___d17927[362:347], basicExec___d17927[345:344], @@ -38761,7 +38734,7 @@ module mkCore(CLK, ~IF_basicExec_7927_BIT_325_7938_THEN_basicExec__ETC___d17946[2], IF_basicExec_7927_BIT_325_7938_THEN_basicExec__ETC___d17946[1:0], basicExec___d17927[440:377] } ; - assign x__h887434 = + assign x__h887432 = { coreFix_aluExe_1_exeToFinQ$first[623], coreFix_aluExe_1_exeToFinQ$first[542:527], coreFix_aluExe_1_exeToFinQ$first[525:524], @@ -38773,34 +38746,34 @@ module mkCore(CLK, ~IF_coreFix_aluExe_1_exeToFinQ_first__8058_BIT__ETC___d18268[2], IF_coreFix_aluExe_1_exeToFinQ_first__8058_BIT__ETC___d18268[1:0], coreFix_aluExe_1_exeToFinQ$first[620:557] } ; - assign x__h903665 = x__h903667 << csrf_stcc_reg[33:28] ; - assign x__h903667 = { {48{offset__h903653[15]}}, offset__h903653 } ; - assign x__h903949 = x__h903951 << csrf_mtcc_reg[33:28] ; - assign x__h903951 = { {48{offset__h903937[15]}}, offset__h903937 } ; - assign x__h904219 = + assign x__h903662 = x__h903664 << csrf_stcc_reg[33:28] ; + assign x__h903664 = { {48{offset__h903650[15]}}, offset__h903650 } ; + assign x__h903946 = x__h903948 << csrf_mtcc_reg[33:28] ; + assign x__h903948 = { {48{offset__h903934[15]}}, offset__h903934 } ; + assign x__h904216 = { csrf_mccsr_reg[10:5], CASE_csrf_mccsr_reg_BITS_4_TO_0_0_csrf_mccsr_r_ETC__q25, 5'd3 } ; - assign x__h904294 = x__h904296 << csrf_rg_dpc[33:28] ; - assign x__h904296 = { {48{offset__h904282[15]}}, offset__h904282 } ; - assign x__h913835 = - coreFix_aluExe_0_regToExeQ$first[241:178] >> x__h913873 ; - assign x__h913873 = { tmp_expTopHalf__h913825, tmp_expBotHalf__h913827 } ; - assign x__h914046 = { impliedTopBits__h913978, topBits__h913974 } ; - assign x__h914063 = x__h914066[13:12] + carry_out__h913976 ; - assign x__h914066 = + assign x__h904291 = x__h904293 << csrf_rg_dpc[33:28] ; + assign x__h904293 = { {48{offset__h904279[15]}}, offset__h904279 } ; + assign x__h913832 = + coreFix_aluExe_0_regToExeQ$first[241:178] >> x__h913870 ; + assign x__h913870 = { tmp_expTopHalf__h913822, tmp_expBotHalf__h913824 } ; + assign x__h914043 = { impliedTopBits__h913975, topBits__h913971 } ; + assign x__h914060 = x__h914063[13:12] + carry_out__h913973 ; + assign x__h914063 = INV_coreFix_aluExe_0_regToExeQfirst_BITS_286__ETC__q13[0] ? { coreFix_aluExe_0_regToExeQ$first[255:245], 3'd0 } : - b_base__h914073 ; - assign x__h914383 = coreFix_aluExe_0_regToExeQ$first[112:49] >> x__h914421 ; - assign x__h914421 = { tmp_expTopHalf__h914373, tmp_expBotHalf__h914375 } ; - assign x__h914594 = { impliedTopBits__h914526, topBits__h914522 } ; - assign x__h914611 = x__h914614[13:12] + carry_out__h914524 ; - assign x__h914614 = + b_base__h914070 ; + assign x__h914380 = coreFix_aluExe_0_regToExeQ$first[112:49] >> x__h914418 ; + assign x__h914418 = { tmp_expTopHalf__h914370, tmp_expBotHalf__h914372 } ; + assign x__h914591 = { impliedTopBits__h914523, topBits__h914519 } ; + assign x__h914608 = x__h914611[13:12] + carry_out__h914521 ; + assign x__h914611 = INV_coreFix_aluExe_0_regToExeQfirst_BITS_157__ETC__q14[0] ? { coreFix_aluExe_0_regToExeQ$first[126:116], 3'd0 } : - b_base__h914621 ; - assign x__h914821 = + b_base__h914618 ; + assign x__h914818 = { basicExec___d20102[443], basicExec___d20102[362:347], basicExec___d20102[345:344], @@ -38812,7 +38785,7 @@ module mkCore(CLK, ~IF_basicExec_0102_BIT_325_0113_THEN_basicExec__ETC___d20121[2], IF_basicExec_0102_BIT_325_0113_THEN_basicExec__ETC___d20121[1:0], basicExec___d20102[440:377] } ; - assign x__h923377 = + assign x__h923374 = { coreFix_aluExe_0_exeToFinQ$first[623], coreFix_aluExe_0_exeToFinQ$first[542:527], coreFix_aluExe_0_exeToFinQ$first[525:524], @@ -38824,8 +38797,8 @@ module mkCore(CLK, ~IF_coreFix_aluExe_0_exeToFinQ_first__0233_BIT__ETC___d20442[2], IF_coreFix_aluExe_0_exeToFinQ_first__0233_BIT__ETC___d20442[1:0], coreFix_aluExe_0_exeToFinQ$first[620:557] } ; - assign x__h924563 = 12'd1 << coreFix_aluExe_1_exeToFinQ$first[15:12] ; - assign x__h924614 = 12'd1 << coreFix_aluExe_0_exeToFinQ$first[15:12] ; + assign x__h924560 = 12'd1 << coreFix_aluExe_1_exeToFinQ$first[15:12] ; + assign x__h924611 = 12'd1 << coreFix_aluExe_0_exeToFinQ$first[15:12] ; assign x_addr__h19883 = mmio_dataReqQ_enqReq_lat_0$whas ? mmio_dataReqQ_enqReq_lat_0$wget[214:151] : @@ -38834,7 +38807,7 @@ module mkCore(CLK, mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[214:151] : mmio_cRqQ_enqReq_rl[214:151] ; - assign x_addr__h539799 = + assign x_addr__h539796 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[582:519] : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[582:519] ; @@ -38842,61 +38815,61 @@ module mkCore(CLK, EN_mmioToPlatform_pRq_enq ? mmio_pRqQ_enqReq_lat_0$wget[31:0] : mmio_pRqQ_enqReq_rl[31:0] ; - assign x_decodeInfo_frm__h935002 = csrf_frm_reg ; - assign x_quotient__h710245 = + assign x_decodeInfo_frm__h934999 = csrf_frm_reg ; + assign x_quotient__h710242 = coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[75] ? 64'hFFFFFFFFFFFFFFFF : ((coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[10] && coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[9]) ? - q___1__h711056 : + q___1__h711053 : coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[203:140]) ; - assign x_reg_ifc__read__h855739 = { 63'd0, csrf_stats_module_doStats } ; - assign x_remainder__h710246 = + assign x_reg_ifc__read__h855737 = { 63'd0, csrf_stats_module_doStats } ; + assign x_remainder__h710243 = coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[75] ? coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[74:11] : ((coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[10] && coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[8]) ? - r___1__h711083 : + r___1__h711080 : coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[139:76]) ; - assign y__h1008406 = ~x__h1008407 ; - assign y__h1010350 = { mask__h1010233[62:0], 1'd0 } ; - assign y__h1011007 = { mask__h1010890[62:0], 1'd0 } ; - assign y__h1027821 = - NOT_rob_deqPort_0_canDeq__3983_3984_OR_rob_deq_ETC___d24208 ? - y_avValue_snd_snd_snd_snd_snd__h1027874 : - IF_rob_deqPort_0_canDeq__3983_THEN_IF_NOT_rob__ETC___d24105 ; - assign y__h242714 = ~x__h242715 ; - assign y__h243871 = ~x__h243872 ; - assign y__h252369 = { 4'd0, coreFix_memExe_lsq$getOrigBE[0] } ; - assign y__h252381 = { 4'd0, coreFix_memExe_lsq$getOrigBE[1] } ; - assign y__h252393 = { 4'd0, coreFix_memExe_lsq$getOrigBE[2] } ; - assign y__h252405 = { 4'd0, coreFix_memExe_lsq$getOrigBE[3] } ; - assign y__h252417 = { 4'd0, coreFix_memExe_lsq$getOrigBE[4] } ; - assign y__h252429 = { 4'd0, coreFix_memExe_lsq$getOrigBE[5] } ; - assign y__h252441 = { 4'd0, coreFix_memExe_lsq$getOrigBE[6] } ; - assign y__h252453 = { 4'd0, coreFix_memExe_lsq$getOrigBE[7] } ; - assign y__h252465 = { 4'd0, coreFix_memExe_lsq$getOrigBE[8] } ; - assign y__h252477 = { 4'd0, coreFix_memExe_lsq$getOrigBE[9] } ; - assign y__h252489 = { 4'd0, coreFix_memExe_lsq$getOrigBE[10] } ; - assign y__h252501 = { 4'd0, coreFix_memExe_lsq$getOrigBE[11] } ; - assign y__h252513 = { 4'd0, coreFix_memExe_lsq$getOrigBE[12] } ; - assign y__h252525 = { 4'd0, coreFix_memExe_lsq$getOrigBE[13] } ; - assign y__h252537 = { 4'd0, coreFix_memExe_lsq$getOrigBE[14] } ; - assign y__h257492 = ~x__h257493 ; - assign y__h426316 = + assign y__h1008440 = ~x__h1008441 ; + assign y__h1010384 = { mask__h1010267[62:0], 1'd0 } ; + assign y__h1011041 = { mask__h1010924[62:0], 1'd0 } ; + assign y__h1027855 = + NOT_rob_deqPort_0_canDeq__3985_3986_OR_rob_deq_ETC___d24210 ? + y_avValue_snd_snd_snd_snd_snd__h1027908 : + IF_rob_deqPort_0_canDeq__3985_THEN_IF_NOT_rob__ETC___d24107 ; + assign y__h242711 = ~x__h242712 ; + assign y__h243868 = ~x__h243869 ; + assign y__h252366 = { 4'd0, coreFix_memExe_lsq$getOrigBE[0] } ; + assign y__h252378 = { 4'd0, coreFix_memExe_lsq$getOrigBE[1] } ; + assign y__h252390 = { 4'd0, coreFix_memExe_lsq$getOrigBE[2] } ; + assign y__h252402 = { 4'd0, coreFix_memExe_lsq$getOrigBE[3] } ; + assign y__h252414 = { 4'd0, coreFix_memExe_lsq$getOrigBE[4] } ; + assign y__h252426 = { 4'd0, coreFix_memExe_lsq$getOrigBE[5] } ; + assign y__h252438 = { 4'd0, coreFix_memExe_lsq$getOrigBE[6] } ; + assign y__h252450 = { 4'd0, coreFix_memExe_lsq$getOrigBE[7] } ; + assign y__h252462 = { 4'd0, coreFix_memExe_lsq$getOrigBE[8] } ; + assign y__h252474 = { 4'd0, coreFix_memExe_lsq$getOrigBE[9] } ; + assign y__h252486 = { 4'd0, coreFix_memExe_lsq$getOrigBE[10] } ; + assign y__h252498 = { 4'd0, coreFix_memExe_lsq$getOrigBE[11] } ; + assign y__h252510 = { 4'd0, coreFix_memExe_lsq$getOrigBE[12] } ; + assign y__h252522 = { 4'd0, coreFix_memExe_lsq$getOrigBE[13] } ; + assign y__h252534 = { 4'd0, coreFix_memExe_lsq$getOrigBE[14] } ; + assign y__h257489 = ~x__h257490 ; + assign y__h426314 = { coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[574:522], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[168:164] } ; - assign y__h860586 = ~x__h860587 ; - assign y__h860891 = ~x__h860892 ; - assign y__h861579 = ~x__h861580 ; - assign y__h861883 = ~x__h861884 ; - assign y__h862409 = ~x__h862410 ; - assign y__h874034 = - { coreFix_aluExe_1_regToExeQ$first[306:242], address__h874073 } ; - assign y__h915075 = - { coreFix_aluExe_0_regToExeQ$first[306:242], address__h915078 } ; - assign y__h924593 = ~x__h924563 ; - assign y__h929523 = + assign y__h860584 = ~x__h860585 ; + assign y__h860889 = ~x__h860890 ; + assign y__h861577 = ~x__h861578 ; + assign y__h861881 = ~x__h861882 ; + assign y__h862407 = ~x__h862408 ; + assign y__h874032 = + { coreFix_aluExe_1_regToExeQ$first[306:242], address__h874071 } ; + assign y__h915072 = + { coreFix_aluExe_0_regToExeQ$first[306:242], address__h915075 } ; + assign y__h924590 = ~x__h924560 ; + assign y__h929520 = { 4'd15, ~csrf_mideleg_11_reg, 1'd1, @@ -38905,20 +38878,20 @@ module mkCore(CLK, ~csrf_mideleg_5_3_reg, 1'd1, ~csrf_mideleg_1_0_reg } ; - assign y__h983649 = 12'd1 << specTagManager$nextSpecTag ; - assign y_avValue__h715403 = + assign y__h983646 = 12'd1 << specTagManager$nextSpecTag ; + assign y_avValue__h715399 = NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d12470 ? coreFix_fpuMulDivExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12598 ; - assign y_avValue__h716111 = + assign y_avValue__h716107 = NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d12499 ? coreFix_fpuMulDivExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12607 ; - assign y_avValue__h716813 = + assign y_avValue__h716809 = NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d12525 ? coreFix_fpuMulDivExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12616 ; - assign y_avValue_snd_fst__h1027215 = + assign y_avValue_snd_fst__h1027249 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[274] || rob$deqPort_0_deq_data[469:465] == 5'd0 || @@ -38933,7 +38906,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[469:465] == 5'd25) ? 5'd0 : rob$deqPort_0_deq_data[31:27] ; - assign y_avValue_snd_fst__h1027858 = + assign y_avValue_snd_fst__h1027892 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[274] || rob$deqPort_1_deq_data[469:465] == 5'd0 || @@ -38946,26 +38919,26 @@ module mkCore(CLK, rob$deqPort_1_deq_data[469:465] == 5'd20 || rob$deqPort_1_deq_data[469:465] == 5'd24 || rob$deqPort_1_deq_data[469:465] == 5'd25) ? - IF_rob_deqPort_0_canDeq__3983_THEN_IF_NOT_rob__ETC___d24215 : - y_avValue_snd_fst__h1027887 ; - assign y_avValue_snd_fst__h1027887 = - IF_rob_deqPort_0_canDeq__3983_THEN_IF_NOT_rob__ETC___d24215 | + IF_rob_deqPort_0_canDeq__3985_THEN_IF_NOT_rob__ETC___d24217 : + y_avValue_snd_fst__h1027921 ; + assign y_avValue_snd_fst__h1027921 = + IF_rob_deqPort_0_canDeq__3985_THEN_IF_NOT_rob__ETC___d24217 | rob$deqPort_1_deq_data[31:27] ; - assign y_avValue_snd_fst__h973229 = + assign y_avValue_snd_fst__h973226 = ((fetchStage$pipelines_0_first[268:266] != 3'd1 || specTagManager$canClaim) && regRenamingTable_rename_0_canRename__1456_AND__ETC___d21480) ? - y_avValue_snd_fst__h973271 : + y_avValue_snd_fst__h973268 : specTagManager$currentSpecBits ; - assign y_avValue_snd_fst__h973271 = + assign y_avValue_snd_fst__h973268 = IF_fetchStage_pipelines_0_first__0544_BITS_268_ETC___d21521 ? - y_avValue_snd_fst__h973313 : + y_avValue_snd_fst__h973310 : specTagManager$currentSpecBits ; - assign y_avValue_snd_fst__h973313 = + assign y_avValue_snd_fst__h973310 = (fetchStage$pipelines_0_first[268:266] == 3'd1) ? - spec_bits__h983636 : + spec_bits__h983633 : specTagManager$currentSpecBits ; - assign y_avValue_snd_snd_snd_fst__h1027225 = + assign y_avValue_snd_snd_snd_fst__h1027259 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[274] || rob$deqPort_0_deq_data[469:465] == 5'd0 || @@ -38980,7 +38953,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[469:465] == 5'd25) ? 2'd0 : 2'd1 ; - assign y_avValue_snd_snd_snd_fst__h1027868 = + assign y_avValue_snd_snd_snd_fst__h1027902 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[274] || rob$deqPort_1_deq_data[469:465] == 5'd0 || @@ -38993,12 +38966,12 @@ module mkCore(CLK, rob$deqPort_1_deq_data[469:465] == 5'd20 || rob$deqPort_1_deq_data[469:465] == 5'd24 || rob$deqPort_1_deq_data[469:465] == 5'd25) ? - IF_rob_deqPort_0_canDeq__3983_THEN_IF_NOT_rob__ETC___d24237 : - y_avValue_snd_snd_snd_fst__h1027897 ; - assign y_avValue_snd_snd_snd_fst__h1027897 = - IF_rob_deqPort_0_canDeq__3983_THEN_IF_NOT_rob__ETC___d24237 + + IF_rob_deqPort_0_canDeq__3985_THEN_IF_NOT_rob__ETC___d24239 : + y_avValue_snd_snd_snd_fst__h1027931 ; + assign y_avValue_snd_snd_snd_fst__h1027931 = + IF_rob_deqPort_0_canDeq__3985_THEN_IF_NOT_rob__ETC___d24239 + 2'd1 ; - assign y_avValue_snd_snd_snd_snd_snd__h1027231 = + assign y_avValue_snd_snd_snd_snd_snd__h1027265 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[274] || rob$deqPort_0_deq_data[469:465] == 5'd0 || @@ -39013,7 +38986,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[469:465] == 5'd25) ? 64'd0 : 64'd1 ; - assign y_avValue_snd_snd_snd_snd_snd__h1027874 = + assign y_avValue_snd_snd_snd_snd_snd__h1027908 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[274] || rob$deqPort_1_deq_data[469:465] == 5'd0 || @@ -39026,10 +38999,10 @@ module mkCore(CLK, rob$deqPort_1_deq_data[469:465] == 5'd20 || rob$deqPort_1_deq_data[469:465] == 5'd24 || rob$deqPort_1_deq_data[469:465] == 5'd25) ? - IF_rob_deqPort_0_canDeq__3983_THEN_IF_NOT_rob__ETC___d24105 : - y_avValue_snd_snd_snd_snd_snd__h1027903 ; - assign y_avValue_snd_snd_snd_snd_snd__h1027903 = - IF_rob_deqPort_0_canDeq__3983_THEN_IF_NOT_rob__ETC___d24105 + + IF_rob_deqPort_0_canDeq__3985_THEN_IF_NOT_rob__ETC___d24107 : + y_avValue_snd_snd_snd_snd_snd__h1027937 ; + assign y_avValue_snd_snd_snd_snd_snd__h1027937 = + IF_rob_deqPort_0_canDeq__3985_THEN_IF_NOT_rob__ETC___d24107 + 64'd1 ; always@(mmio_cRqQ_data_0) begin @@ -39054,28 +39027,28 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP) 3'd0: - x__h505455 = + x__h505453 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0; 3'd1: - x__h505455 = + x__h505453 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1; 3'd2: - x__h505455 = + x__h505453 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2; 3'd3: - x__h505455 = + x__h505453 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3; 3'd4: - x__h505455 = + x__h505453 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4; 3'd5: - x__h505455 = + x__h505453 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5; 3'd6: - x__h505455 = + x__h505453 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6; 3'd7: - x__h505455 = + x__h505453 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7; endcase end @@ -39085,10 +39058,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - addr__h509973 = + addr__h509971 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[585:522]; 1'd1: - addr__h509973 = + addr__h509971 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[585:522]; endcase end @@ -39097,16 +39070,16 @@ module mkCore(CLK, coreFix_memExe_memRespLdQ_data_1) begin case (coreFix_memExe_memRespLdQ_deqP) - 1'd0: t__h215266 = coreFix_memExe_memRespLdQ_data_0[133:129]; - 1'd1: t__h215266 = coreFix_memExe_memRespLdQ_data_1[133:129]; + 1'd0: t__h215264 = coreFix_memExe_memRespLdQ_data_0[133:129]; + 1'd1: t__h215264 = coreFix_memExe_memRespLdQ_data_1[133:129]; endcase end always@(coreFix_memExe_forwardQ_deqP or coreFix_memExe_forwardQ_data_0 or coreFix_memExe_forwardQ_data_1) begin case (coreFix_memExe_forwardQ_deqP) - 1'd0: t__h217619 = coreFix_memExe_forwardQ_data_0[133:129]; - 1'd1: t__h217619 = coreFix_memExe_forwardQ_data_1[133:129]; + 1'd0: t__h217617 = coreFix_memExe_forwardQ_data_0[133:129]; + 1'd1: t__h217617 = coreFix_memExe_forwardQ_data_1[133:129]; endcase end always@(coreFix_memExe_dMem_cache_m_banks_0_processAmo or @@ -39165,16 +39138,16 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_processAmo[167:166]) 2'd0: - x__h267669 = + x__h267667 = CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q18; 2'd1: - x__h267669 = + x__h267667 = CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q19; 2'd2: - x__h267669 = + x__h267667 = CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q20; 2'd3: - x__h267669 = + x__h267667 = CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q21; endcase end @@ -39182,8 +39155,8 @@ module mkCore(CLK, begin case (commitStage_commitTrap[35:32]) 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: - i__h1006243 = commitStage_commitTrap[35:32]; - default: i__h1006243 = 4'd15; + i__h1006266 = commitStage_commitTrap[35:32]; + default: i__h1006266 = 4'd15; endcase end always@(csrf_mccsr_reg) @@ -39256,123 +39229,123 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - x__h513123 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[2:0]; + x__h513121 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[2:0]; 1'd1: - x__h513123 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[2:0]; + x__h513121 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[2:0]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h580861 = 8'd255; + 3'd0, 3'd1: _theResult___fst_exp__h580858 = 8'd255; 3'd2: - _theResult___fst_exp__h580861 = + _theResult___fst_exp__h580858 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 8'd254 : 8'd255; 3'd3: - _theResult___fst_exp__h580861 = + _theResult___fst_exp__h580858 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 8'd255 : 8'd254; - 3'd4: _theResult___fst_exp__h580861 = 8'd254; - default: _theResult___fst_exp__h580861 = 8'd0; + 3'd4: _theResult___fst_exp__h580858 = 8'd254; + default: _theResult___fst_exp__h580858 = 8'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_sfd__h580862 = 23'd0; + 3'd0, 3'd1: _theResult___fst_sfd__h580859 = 23'd0; 3'd2: - _theResult___fst_sfd__h580862 = + _theResult___fst_sfd__h580859 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 23'd8388607 : 23'd0; 3'd3: - _theResult___fst_sfd__h580862 = + _theResult___fst_sfd__h580859 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 23'd0 : 23'd8388607; - 3'd4: _theResult___fst_sfd__h580862 = 23'd8388607; - default: _theResult___fst_sfd__h580862 = 23'd0; + 3'd4: _theResult___fst_sfd__h580859 = 23'd8388607; + default: _theResult___fst_sfd__h580859 = 23'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h626612 = 8'd255; + 3'd0, 3'd1: _theResult___fst_exp__h626609 = 8'd255; 3'd2: - _theResult___fst_exp__h626612 = + _theResult___fst_exp__h626609 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 8'd254 : 8'd255; 3'd3: - _theResult___fst_exp__h626612 = + _theResult___fst_exp__h626609 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 8'd255 : 8'd254; - 3'd4: _theResult___fst_exp__h626612 = 8'd254; - default: _theResult___fst_exp__h626612 = 8'd0; + 3'd4: _theResult___fst_exp__h626609 = 8'd254; + default: _theResult___fst_exp__h626609 = 8'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_sfd__h626613 = 23'd0; + 3'd0, 3'd1: _theResult___fst_sfd__h626610 = 23'd0; 3'd2: - _theResult___fst_sfd__h626613 = + _theResult___fst_sfd__h626610 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 23'd8388607 : 23'd0; 3'd3: - _theResult___fst_sfd__h626613 = + _theResult___fst_sfd__h626610 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 23'd0 : 23'd8388607; - 3'd4: _theResult___fst_sfd__h626613 = 23'd8388607; - default: _theResult___fst_sfd__h626613 = 23'd0; + 3'd4: _theResult___fst_sfd__h626610 = 23'd8388607; + default: _theResult___fst_sfd__h626610 = 23'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h672359 = 8'd255; + 3'd0, 3'd1: _theResult___fst_exp__h672356 = 8'd255; 3'd2: - _theResult___fst_exp__h672359 = + _theResult___fst_exp__h672356 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 8'd254 : 8'd255; 3'd3: - _theResult___fst_exp__h672359 = + _theResult___fst_exp__h672356 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 8'd255 : 8'd254; - 3'd4: _theResult___fst_exp__h672359 = 8'd254; - default: _theResult___fst_exp__h672359 = 8'd0; + 3'd4: _theResult___fst_exp__h672356 = 8'd254; + default: _theResult___fst_exp__h672356 = 8'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_sfd__h672360 = 23'd0; + 3'd0, 3'd1: _theResult___fst_sfd__h672357 = 23'd0; 3'd2: - _theResult___fst_sfd__h672360 = + _theResult___fst_sfd__h672357 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 23'd8388607 : 23'd0; 3'd3: - _theResult___fst_sfd__h672360 = + _theResult___fst_sfd__h672357 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 23'd0 : 23'd8388607; - 3'd4: _theResult___fst_sfd__h672360 = 23'd8388607; - default: _theResult___fst_sfd__h672360 = 23'd0; + 3'd4: _theResult___fst_sfd__h672357 = 23'd8388607; + default: _theResult___fst_sfd__h672357 = 23'd0; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) @@ -39524,16 +39497,16 @@ module mkCore(CLK, 5'd12, 5'd13, 5'd15: - i__h1006069 = commitStage_commitTrap[36:32]; - default: i__h1006069 = 5'd28; + i__h1006066 = commitStage_commitTrap[36:32]; + default: i__h1006066 = 5'd28; endcase end - always@(commitStage_commitTrap or cause_code__h1007591 or i__h1006069) + always@(commitStage_commitTrap or cause_code__h1007625 or i__h1006066) begin case (commitStage_commitTrap[44:43]) - 2'd0: cause_code__h1006053 = 5'd28; - 2'd1: cause_code__h1006053 = i__h1006069; - default: cause_code__h1006053 = cause_code__h1007591; + 2'd0: cause_code__h1006050 = 5'd28; + 2'd1: cause_code__h1006050 = i__h1006066; + default: cause_code__h1006050 = cause_code__h1007625; endcase end always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) @@ -39566,6 +39539,23 @@ module mkCore(CLK, endcase end always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) + begin + case (coreFix_memExe_lsq$firstLd[37:36]) + 2'd0: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_235_ETC___d1876 = + coreFix_memExe_respLrScAmoQ_data_0[31:0]; + 2'd1: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_235_ETC___d1876 = + coreFix_memExe_respLrScAmoQ_data_0[63:32]; + 2'd2: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_235_ETC___d1876 = + coreFix_memExe_respLrScAmoQ_data_0[95:64]; + 2'd3: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_235_ETC___d1876 = + coreFix_memExe_respLrScAmoQ_data_0[127:96]; + endcase + end + always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) begin case (coreFix_memExe_lsq$firstLd[37:34]) 4'd0: @@ -39619,23 +39609,6 @@ module mkCore(CLK, endcase end always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) - begin - case (coreFix_memExe_lsq$firstLd[37:36]) - 2'd0: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_235_ETC___d1876 = - coreFix_memExe_respLrScAmoQ_data_0[31:0]; - 2'd1: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_235_ETC___d1876 = - coreFix_memExe_respLrScAmoQ_data_0[63:32]; - 2'd2: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_235_ETC___d1876 = - coreFix_memExe_respLrScAmoQ_data_0[95:64]; - 2'd3: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_235_ETC___d1876 = - coreFix_memExe_respLrScAmoQ_data_0[127:96]; - endcase - end - always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) begin case (coreFix_memExe_lsq$firstLd[37]) 1'd0: @@ -39799,6 +39772,24 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384]; endcase end + always@(coreFix_memExe_dMem_cache_m_banks_0_processAmo or + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first) + begin + case (coreFix_memExe_dMem_cache_m_banks_0_processAmo[167:166]) + 2'd0: + SEL_ARR_NOT_coreFix_memExe_dMem_cache_m_banks__ETC___d4920 = + !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[512]; + 2'd1: + SEL_ARR_NOT_coreFix_memExe_dMem_cache_m_banks__ETC___d4920 = + !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[513]; + 2'd2: + SEL_ARR_NOT_coreFix_memExe_dMem_cache_m_banks__ETC___d4920 = + !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[514]; + 2'd3: + SEL_ARR_NOT_coreFix_memExe_dMem_cache_m_banks__ETC___d4920 = + !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515]; + endcase + end always@(coreFix_memExe_dMem_cache_m_banks_0_processAmo or coreFix_memExe_dMem_cache_m_banks_0_pipeline$first) begin @@ -39823,37 +39814,19 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_processAmo[165:164]) 2'd0: - x__h267824 = + x__h267822 = SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4887[31:0]; 2'd1: - x__h267824 = + x__h267822 = SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4887[63:32]; 2'd2: - x__h267824 = + x__h267822 = SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4881[31:0]; 2'd3: - x__h267824 = + x__h267822 = SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4881[63:32]; endcase end - always@(coreFix_memExe_dMem_cache_m_banks_0_processAmo or - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first) - begin - case (coreFix_memExe_dMem_cache_m_banks_0_processAmo[167:166]) - 2'd0: - SEL_ARR_NOT_coreFix_memExe_dMem_cache_m_banks__ETC___d4920 = - !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[512]; - 2'd1: - SEL_ARR_NOT_coreFix_memExe_dMem_cache_m_banks__ETC___d4920 = - !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[513]; - 2'd2: - SEL_ARR_NOT_coreFix_memExe_dMem_cache_m_banks__ETC___d4920 = - !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[514]; - 2'd3: - SEL_ARR_NOT_coreFix_memExe_dMem_cache_m_banks__ETC___d4920 = - !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515]; - endcase - end always@(coreFix_memExe_dMem_cache_m_banks_0_processAmo or coreFix_memExe_dMem_cache_m_banks_0_pipeline$first) begin @@ -39996,446 +39969,446 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[516]; endcase end - always@(guard__h589598 or - _theResult___fst_exp__h597646 or - out_exp__h598091 or _theResult___exp__h598088) + always@(guard__h589595 or + _theResult___fst_exp__h597643 or + out_exp__h598088 or _theResult___exp__h598085) begin - case (guard__h589598) + case (guard__h589595) 2'b0, 2'b01: - CASE_guard89598_0b0_theResult___fst_exp97646_0_ETC__q47 = - _theResult___fst_exp__h597646; + CASE_guard89595_0b0_theResult___fst_exp97643_0_ETC__q45 = + _theResult___fst_exp__h597643; 2'b10: - CASE_guard89598_0b0_theResult___fst_exp97646_0_ETC__q47 = - out_exp__h598091; + CASE_guard89595_0b0_theResult___fst_exp97643_0_ETC__q45 = + out_exp__h598088; 2'b11: - CASE_guard89598_0b0_theResult___fst_exp97646_0_ETC__q47 = - _theResult___exp__h598088; + CASE_guard89595_0b0_theResult___fst_exp97643_0_ETC__q45 = + _theResult___exp__h598085; endcase end - always@(guard__h589598 or - _theResult___fst_exp__h597646 or _theResult___exp__h598088) + always@(guard__h589595 or + _theResult___fst_exp__h597643 or _theResult___exp__h598085) begin - case (guard__h589598) + case (guard__h589595) 2'b0: - CASE_guard89598_0b0_theResult___fst_exp97646_0_ETC__q48 = - _theResult___fst_exp__h597646; + CASE_guard89595_0b0_theResult___fst_exp97643_0_ETC__q46 = + _theResult___fst_exp__h597643; 2'b01, 2'b10, 2'b11: - CASE_guard89598_0b0_theResult___fst_exp97646_0_ETC__q48 = - _theResult___exp__h598088; + CASE_guard89595_0b0_theResult___fst_exp97643_0_ETC__q46 = + _theResult___exp__h598085; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard89598_0b0_theResult___fst_exp97646_0_ETC__q47 or - CASE_guard89598_0b0_theResult___fst_exp97646_0_ETC__q48 or + CASE_guard89595_0b0_theResult___fst_exp97643_0_ETC__q45 or + CASE_guard89595_0b0_theResult___fst_exp97643_0_ETC__q46 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d8746 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d8748 or - _theResult___fst_exp__h597646) + _theResult___fst_exp__h597643) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h598166 = - CASE_guard89598_0b0_theResult___fst_exp97646_0_ETC__q47; + _theResult___fst_exp__h598163 = + CASE_guard89595_0b0_theResult___fst_exp97643_0_ETC__q45; 3'd1: - _theResult___fst_exp__h598166 = - CASE_guard89598_0b0_theResult___fst_exp97646_0_ETC__q48; + _theResult___fst_exp__h598163 = + CASE_guard89595_0b0_theResult___fst_exp97643_0_ETC__q46; 3'd2: - _theResult___fst_exp__h598166 = + _theResult___fst_exp__h598163 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d8746; 3'd3: - _theResult___fst_exp__h598166 = + _theResult___fst_exp__h598163 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d8748; - 3'd4: _theResult___fst_exp__h598166 = _theResult___fst_exp__h597646; - default: _theResult___fst_exp__h598166 = 8'd0; + 3'd4: _theResult___fst_exp__h598163 = _theResult___fst_exp__h597643; + default: _theResult___fst_exp__h598163 = 8'd0; endcase end - always@(guard__h580889 or - _theResult___fst_exp__h588990 or - out_exp__h589509 or _theResult___exp__h589506) + always@(guard__h580886 or + _theResult___fst_exp__h588987 or + out_exp__h589506 or _theResult___exp__h589503) begin - case (guard__h580889) + case (guard__h580886) 2'b0, 2'b01: - CASE_guard80889_0b0_theResult___fst_exp88990_0_ETC__q49 = - _theResult___fst_exp__h588990; + CASE_guard80886_0b0_theResult___fst_exp88987_0_ETC__q47 = + _theResult___fst_exp__h588987; 2'b10: - CASE_guard80889_0b0_theResult___fst_exp88990_0_ETC__q49 = - out_exp__h589509; + CASE_guard80886_0b0_theResult___fst_exp88987_0_ETC__q47 = + out_exp__h589506; 2'b11: - CASE_guard80889_0b0_theResult___fst_exp88990_0_ETC__q49 = - _theResult___exp__h589506; + CASE_guard80886_0b0_theResult___fst_exp88987_0_ETC__q47 = + _theResult___exp__h589503; endcase end - always@(guard__h580889 or - _theResult___fst_exp__h588990 or _theResult___exp__h589506) + always@(guard__h580886 or + _theResult___fst_exp__h588987 or _theResult___exp__h589503) begin - case (guard__h580889) + case (guard__h580886) 2'b0: - CASE_guard80889_0b0_theResult___fst_exp88990_0_ETC__q50 = - _theResult___fst_exp__h588990; + CASE_guard80886_0b0_theResult___fst_exp88987_0_ETC__q48 = + _theResult___fst_exp__h588987; 2'b01, 2'b10, 2'b11: - CASE_guard80889_0b0_theResult___fst_exp88990_0_ETC__q50 = - _theResult___exp__h589506; + CASE_guard80886_0b0_theResult___fst_exp88987_0_ETC__q48 = + _theResult___exp__h589503; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard80889_0b0_theResult___fst_exp88990_0_ETC__q49 or - CASE_guard80889_0b0_theResult___fst_exp88990_0_ETC__q50 or + CASE_guard80886_0b0_theResult___fst_exp88987_0_ETC__q47 or + CASE_guard80886_0b0_theResult___fst_exp88987_0_ETC__q48 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d8524 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d8527 or - _theResult___fst_exp__h588990) + _theResult___fst_exp__h588987) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h589584 = - CASE_guard80889_0b0_theResult___fst_exp88990_0_ETC__q49; + _theResult___fst_exp__h589581 = + CASE_guard80886_0b0_theResult___fst_exp88987_0_ETC__q47; 3'd1: - _theResult___fst_exp__h589584 = - CASE_guard80889_0b0_theResult___fst_exp88990_0_ETC__q50; + _theResult___fst_exp__h589581 = + CASE_guard80886_0b0_theResult___fst_exp88987_0_ETC__q48; 3'd2: - _theResult___fst_exp__h589584 = + _theResult___fst_exp__h589581 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d8524; 3'd3: - _theResult___fst_exp__h589584 = + _theResult___fst_exp__h589581 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d8527; - 3'd4: _theResult___fst_exp__h589584 = _theResult___fst_exp__h588990; - default: _theResult___fst_exp__h589584 = 8'd0; + 3'd4: _theResult___fst_exp__h589581 = _theResult___fst_exp__h588987; + default: _theResult___fst_exp__h589581 = 8'd0; endcase end - always@(guard__h598528 or - _theResult___fst_exp__h606756 or - out_exp__h607275 or _theResult___exp__h607272) + always@(guard__h598525 or + _theResult___fst_exp__h606753 or + out_exp__h607272 or _theResult___exp__h607269) begin - case (guard__h598528) + case (guard__h598525) 2'b0, 2'b01: - CASE_guard98528_0b0_theResult___fst_exp06756_0_ETC__q53 = - _theResult___fst_exp__h606756; + CASE_guard98525_0b0_theResult___fst_exp06753_0_ETC__q53 = + _theResult___fst_exp__h606753; 2'b10: - CASE_guard98528_0b0_theResult___fst_exp06756_0_ETC__q53 = - out_exp__h607275; + CASE_guard98525_0b0_theResult___fst_exp06753_0_ETC__q53 = + out_exp__h607272; 2'b11: - CASE_guard98528_0b0_theResult___fst_exp06756_0_ETC__q53 = - _theResult___exp__h607272; + CASE_guard98525_0b0_theResult___fst_exp06753_0_ETC__q53 = + _theResult___exp__h607269; endcase end - always@(guard__h598528 or - _theResult___fst_exp__h606756 or _theResult___exp__h607272) + always@(guard__h598525 or + _theResult___fst_exp__h606753 or _theResult___exp__h607269) begin - case (guard__h598528) + case (guard__h598525) 2'b0: - CASE_guard98528_0b0_theResult___fst_exp06756_0_ETC__q54 = - _theResult___fst_exp__h606756; + CASE_guard98525_0b0_theResult___fst_exp06753_0_ETC__q54 = + _theResult___fst_exp__h606753; 2'b01, 2'b10, 2'b11: - CASE_guard98528_0b0_theResult___fst_exp06756_0_ETC__q54 = - _theResult___exp__h607272; + CASE_guard98525_0b0_theResult___fst_exp06753_0_ETC__q54 = + _theResult___exp__h607269; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard98528_0b0_theResult___fst_exp06756_0_ETC__q53 or - CASE_guard98528_0b0_theResult___fst_exp06756_0_ETC__q54 or + CASE_guard98525_0b0_theResult___fst_exp06753_0_ETC__q53 or + CASE_guard98525_0b0_theResult___fst_exp06753_0_ETC__q54 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9071 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9073 or - _theResult___fst_exp__h606756) + _theResult___fst_exp__h606753) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h607350 = - CASE_guard98528_0b0_theResult___fst_exp06756_0_ETC__q53; + _theResult___fst_exp__h607347 = + CASE_guard98525_0b0_theResult___fst_exp06753_0_ETC__q53; 3'd1: - _theResult___fst_exp__h607350 = - CASE_guard98528_0b0_theResult___fst_exp06756_0_ETC__q54; + _theResult___fst_exp__h607347 = + CASE_guard98525_0b0_theResult___fst_exp06753_0_ETC__q54; 3'd2: - _theResult___fst_exp__h607350 = + _theResult___fst_exp__h607347 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9071; 3'd3: - _theResult___fst_exp__h607350 = + _theResult___fst_exp__h607347 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9073; - 3'd4: _theResult___fst_exp__h607350 = _theResult___fst_exp__h606756; - default: _theResult___fst_exp__h607350 = 8'd0; + 3'd4: _theResult___fst_exp__h607347 = _theResult___fst_exp__h606753; + default: _theResult___fst_exp__h607347 = 8'd0; endcase end - always@(guard__h607364 or - _theResult___fst_exp__h615441 or - out_exp__h615911 or _theResult___exp__h615908) + always@(guard__h607361 or + _theResult___fst_exp__h615438 or + out_exp__h615908 or _theResult___exp__h615905) begin - case (guard__h607364) + case (guard__h607361) 2'b0, 2'b01: - CASE_guard07364_0b0_theResult___fst_exp15441_0_ETC__q58 = - _theResult___fst_exp__h615441; + CASE_guard07361_0b0_theResult___fst_exp15438_0_ETC__q58 = + _theResult___fst_exp__h615438; 2'b10: - CASE_guard07364_0b0_theResult___fst_exp15441_0_ETC__q58 = - out_exp__h615911; + CASE_guard07361_0b0_theResult___fst_exp15438_0_ETC__q58 = + out_exp__h615908; 2'b11: - CASE_guard07364_0b0_theResult___fst_exp15441_0_ETC__q58 = - _theResult___exp__h615908; + CASE_guard07361_0b0_theResult___fst_exp15438_0_ETC__q58 = + _theResult___exp__h615905; endcase end - always@(guard__h607364 or - _theResult___fst_exp__h615441 or _theResult___exp__h615908) + always@(guard__h607361 or + _theResult___fst_exp__h615438 or _theResult___exp__h615905) begin - case (guard__h607364) + case (guard__h607361) 2'b0: - CASE_guard07364_0b0_theResult___fst_exp15441_0_ETC__q59 = - _theResult___fst_exp__h615441; + CASE_guard07361_0b0_theResult___fst_exp15438_0_ETC__q59 = + _theResult___fst_exp__h615438; 2'b01, 2'b10, 2'b11: - CASE_guard07364_0b0_theResult___fst_exp15441_0_ETC__q59 = - _theResult___exp__h615908; + CASE_guard07361_0b0_theResult___fst_exp15438_0_ETC__q59 = + _theResult___exp__h615905; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard07364_0b0_theResult___fst_exp15441_0_ETC__q58 or - CASE_guard07364_0b0_theResult___fst_exp15441_0_ETC__q59 or + CASE_guard07361_0b0_theResult___fst_exp15438_0_ETC__q58 or + CASE_guard07361_0b0_theResult___fst_exp15438_0_ETC__q59 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9140 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9142 or - _theResult___fst_exp__h615441) + _theResult___fst_exp__h615438) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h615986 = - CASE_guard07364_0b0_theResult___fst_exp15441_0_ETC__q58; + _theResult___fst_exp__h615983 = + CASE_guard07361_0b0_theResult___fst_exp15438_0_ETC__q58; 3'd1: - _theResult___fst_exp__h615986 = - CASE_guard07364_0b0_theResult___fst_exp15441_0_ETC__q59; + _theResult___fst_exp__h615983 = + CASE_guard07361_0b0_theResult___fst_exp15438_0_ETC__q59; 3'd2: - _theResult___fst_exp__h615986 = + _theResult___fst_exp__h615983 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9140; 3'd3: - _theResult___fst_exp__h615986 = + _theResult___fst_exp__h615983 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9142; - 3'd4: _theResult___fst_exp__h615986 = _theResult___fst_exp__h615441; - default: _theResult___fst_exp__h615986 = 8'd0; + 3'd4: _theResult___fst_exp__h615983 = _theResult___fst_exp__h615438; + default: _theResult___fst_exp__h615983 = 8'd0; endcase end - always@(guard__h580889 or - sfdin__h588984 or out_sfd__h589510 or _theResult___sfd__h589507) + always@(guard__h589595 or + _theResult___snd__h597594 or + out_sfd__h598089 or _theResult___sfd__h598086) begin - case (guard__h580889) + case (guard__h589595) 2'b0, 2'b01: - CASE_guard80889_0b0_sfdin88984_BITS_56_TO_34_0_ETC__q60 = - sfdin__h588984[56:34]; + CASE_guard89595_0b0_theResult___snd97594_BITS__ETC__q60 = + _theResult___snd__h597594[56:34]; 2'b10: - CASE_guard80889_0b0_sfdin88984_BITS_56_TO_34_0_ETC__q60 = - out_sfd__h589510; + CASE_guard89595_0b0_theResult___snd97594_BITS__ETC__q60 = + out_sfd__h598089; 2'b11: - CASE_guard80889_0b0_sfdin88984_BITS_56_TO_34_0_ETC__q60 = - _theResult___sfd__h589507; + CASE_guard89595_0b0_theResult___snd97594_BITS__ETC__q60 = + _theResult___sfd__h598086; endcase end - always@(guard__h580889 or sfdin__h588984 or _theResult___sfd__h589507) + always@(guard__h589595 or + _theResult___snd__h597594 or _theResult___sfd__h598086) begin - case (guard__h580889) + case (guard__h589595) 2'b0: - CASE_guard80889_0b0_sfdin88984_BITS_56_TO_34_0_ETC__q61 = - sfdin__h588984[56:34]; + CASE_guard89595_0b0_theResult___snd97594_BITS__ETC__q61 = + _theResult___snd__h597594[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard80889_0b0_sfdin88984_BITS_56_TO_34_0_ETC__q61 = - _theResult___sfd__h589507; + CASE_guard89595_0b0_theResult___snd97594_BITS__ETC__q61 = + _theResult___sfd__h598086; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard80889_0b0_sfdin88984_BITS_56_TO_34_0_ETC__q60 or - CASE_guard80889_0b0_sfdin88984_BITS_56_TO_34_0_ETC__q61 or - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9171 or - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9173 or - sfdin__h588984) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0: - _theResult___fst_sfd__h589585 = - CASE_guard80889_0b0_sfdin88984_BITS_56_TO_34_0_ETC__q60; - 3'd1: - _theResult___fst_sfd__h589585 = - CASE_guard80889_0b0_sfdin88984_BITS_56_TO_34_0_ETC__q61; - 3'd2: - _theResult___fst_sfd__h589585 = - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9171; - 3'd3: - _theResult___fst_sfd__h589585 = - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9173; - 3'd4: _theResult___fst_sfd__h589585 = sfdin__h588984[56:34]; - default: _theResult___fst_sfd__h589585 = 23'd0; - endcase - end - always@(guard__h589598 or - _theResult___snd__h597597 or - out_sfd__h598092 or _theResult___sfd__h598089) - begin - case (guard__h589598) - 2'b0, 2'b01: - CASE_guard89598_0b0_theResult___snd97597_BITS__ETC__q62 = - _theResult___snd__h597597[56:34]; - 2'b10: - CASE_guard89598_0b0_theResult___snd97597_BITS__ETC__q62 = - out_sfd__h598092; - 2'b11: - CASE_guard89598_0b0_theResult___snd97597_BITS__ETC__q62 = - _theResult___sfd__h598089; - endcase - end - always@(guard__h589598 or - _theResult___snd__h597597 or _theResult___sfd__h598089) - begin - case (guard__h589598) - 2'b0: - CASE_guard89598_0b0_theResult___snd97597_BITS__ETC__q63 = - _theResult___snd__h597597[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard89598_0b0_theResult___snd97597_BITS__ETC__q63 = - _theResult___sfd__h598089; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard89598_0b0_theResult___snd97597_BITS__ETC__q62 or - CASE_guard89598_0b0_theResult___snd97597_BITS__ETC__q63 or + CASE_guard89595_0b0_theResult___snd97594_BITS__ETC__q60 or + CASE_guard89595_0b0_theResult___snd97594_BITS__ETC__q61 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9190 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9192 or - _theResult___snd__h597597) + _theResult___snd__h597594) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h598167 = - CASE_guard89598_0b0_theResult___snd97597_BITS__ETC__q62; + _theResult___fst_sfd__h598164 = + CASE_guard89595_0b0_theResult___snd97594_BITS__ETC__q60; 3'd1: - _theResult___fst_sfd__h598167 = - CASE_guard89598_0b0_theResult___snd97597_BITS__ETC__q63; + _theResult___fst_sfd__h598164 = + CASE_guard89595_0b0_theResult___snd97594_BITS__ETC__q61; 3'd2: - _theResult___fst_sfd__h598167 = + _theResult___fst_sfd__h598164 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9190; 3'd3: - _theResult___fst_sfd__h598167 = + _theResult___fst_sfd__h598164 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9192; - 3'd4: _theResult___fst_sfd__h598167 = _theResult___snd__h597597[56:34]; - default: _theResult___fst_sfd__h598167 = 23'd0; + 3'd4: _theResult___fst_sfd__h598164 = _theResult___snd__h597594[56:34]; + default: _theResult___fst_sfd__h598164 = 23'd0; endcase end - always@(guard__h598528 or - sfdin__h606750 or out_sfd__h607276 or _theResult___sfd__h607273) + always@(guard__h580886 or + sfdin__h588981 or out_sfd__h589507 or _theResult___sfd__h589504) begin - case (guard__h598528) + case (guard__h580886) 2'b0, 2'b01: - CASE_guard98528_0b0_sfdin06750_BITS_56_TO_34_0_ETC__q64 = - sfdin__h606750[56:34]; + CASE_guard80886_0b0_sfdin88981_BITS_56_TO_34_0_ETC__q62 = + sfdin__h588981[56:34]; 2'b10: - CASE_guard98528_0b0_sfdin06750_BITS_56_TO_34_0_ETC__q64 = - out_sfd__h607276; + CASE_guard80886_0b0_sfdin88981_BITS_56_TO_34_0_ETC__q62 = + out_sfd__h589507; 2'b11: - CASE_guard98528_0b0_sfdin06750_BITS_56_TO_34_0_ETC__q64 = - _theResult___sfd__h607273; + CASE_guard80886_0b0_sfdin88981_BITS_56_TO_34_0_ETC__q62 = + _theResult___sfd__h589504; endcase end - always@(guard__h598528 or sfdin__h606750 or _theResult___sfd__h607273) + always@(guard__h580886 or sfdin__h588981 or _theResult___sfd__h589504) begin - case (guard__h598528) + case (guard__h580886) 2'b0: - CASE_guard98528_0b0_sfdin06750_BITS_56_TO_34_0_ETC__q65 = - sfdin__h606750[56:34]; + CASE_guard80886_0b0_sfdin88981_BITS_56_TO_34_0_ETC__q63 = + sfdin__h588981[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard98528_0b0_sfdin06750_BITS_56_TO_34_0_ETC__q65 = - _theResult___sfd__h607273; + CASE_guard80886_0b0_sfdin88981_BITS_56_TO_34_0_ETC__q63 = + _theResult___sfd__h589504; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard98528_0b0_sfdin06750_BITS_56_TO_34_0_ETC__q64 or - CASE_guard98528_0b0_sfdin06750_BITS_56_TO_34_0_ETC__q65 or + CASE_guard80886_0b0_sfdin88981_BITS_56_TO_34_0_ETC__q62 or + CASE_guard80886_0b0_sfdin88981_BITS_56_TO_34_0_ETC__q63 or + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9171 or + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9173 or + sfdin__h588981) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) + 3'd0: + _theResult___fst_sfd__h589582 = + CASE_guard80886_0b0_sfdin88981_BITS_56_TO_34_0_ETC__q62; + 3'd1: + _theResult___fst_sfd__h589582 = + CASE_guard80886_0b0_sfdin88981_BITS_56_TO_34_0_ETC__q63; + 3'd2: + _theResult___fst_sfd__h589582 = + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9171; + 3'd3: + _theResult___fst_sfd__h589582 = + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9173; + 3'd4: _theResult___fst_sfd__h589582 = sfdin__h588981[56:34]; + default: _theResult___fst_sfd__h589582 = 23'd0; + endcase + end + always@(guard__h598525 or + sfdin__h606747 or out_sfd__h607273 or _theResult___sfd__h607270) + begin + case (guard__h598525) + 2'b0, 2'b01: + CASE_guard98525_0b0_sfdin06747_BITS_56_TO_34_0_ETC__q64 = + sfdin__h606747[56:34]; + 2'b10: + CASE_guard98525_0b0_sfdin06747_BITS_56_TO_34_0_ETC__q64 = + out_sfd__h607273; + 2'b11: + CASE_guard98525_0b0_sfdin06747_BITS_56_TO_34_0_ETC__q64 = + _theResult___sfd__h607270; + endcase + end + always@(guard__h598525 or sfdin__h606747 or _theResult___sfd__h607270) + begin + case (guard__h598525) + 2'b0: + CASE_guard98525_0b0_sfdin06747_BITS_56_TO_34_0_ETC__q65 = + sfdin__h606747[56:34]; + 2'b01, 2'b10, 2'b11: + CASE_guard98525_0b0_sfdin06747_BITS_56_TO_34_0_ETC__q65 = + _theResult___sfd__h607270; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or + CASE_guard98525_0b0_sfdin06747_BITS_56_TO_34_0_ETC__q64 or + CASE_guard98525_0b0_sfdin06747_BITS_56_TO_34_0_ETC__q65 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9217 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9219 or - sfdin__h606750) + sfdin__h606747) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h607351 = - CASE_guard98528_0b0_sfdin06750_BITS_56_TO_34_0_ETC__q64; + _theResult___fst_sfd__h607348 = + CASE_guard98525_0b0_sfdin06747_BITS_56_TO_34_0_ETC__q64; 3'd1: - _theResult___fst_sfd__h607351 = - CASE_guard98528_0b0_sfdin06750_BITS_56_TO_34_0_ETC__q65; + _theResult___fst_sfd__h607348 = + CASE_guard98525_0b0_sfdin06747_BITS_56_TO_34_0_ETC__q65; 3'd2: - _theResult___fst_sfd__h607351 = + _theResult___fst_sfd__h607348 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9217; 3'd3: - _theResult___fst_sfd__h607351 = + _theResult___fst_sfd__h607348 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9219; - 3'd4: _theResult___fst_sfd__h607351 = sfdin__h606750[56:34]; - default: _theResult___fst_sfd__h607351 = 23'd0; + 3'd4: _theResult___fst_sfd__h607348 = sfdin__h606747[56:34]; + default: _theResult___fst_sfd__h607348 = 23'd0; endcase end - always@(guard__h607364 or - _theResult___snd__h615387 or - out_sfd__h615912 or _theResult___sfd__h615909) + always@(guard__h607361 or + _theResult___snd__h615384 or + out_sfd__h615909 or _theResult___sfd__h615906) begin - case (guard__h607364) + case (guard__h607361) 2'b0, 2'b01: - CASE_guard07364_0b0_theResult___snd15387_BITS__ETC__q66 = - _theResult___snd__h615387[56:34]; + CASE_guard07361_0b0_theResult___snd15384_BITS__ETC__q66 = + _theResult___snd__h615384[56:34]; 2'b10: - CASE_guard07364_0b0_theResult___snd15387_BITS__ETC__q66 = - out_sfd__h615912; + CASE_guard07361_0b0_theResult___snd15384_BITS__ETC__q66 = + out_sfd__h615909; 2'b11: - CASE_guard07364_0b0_theResult___snd15387_BITS__ETC__q66 = - _theResult___sfd__h615909; + CASE_guard07361_0b0_theResult___snd15384_BITS__ETC__q66 = + _theResult___sfd__h615906; endcase end - always@(guard__h607364 or - _theResult___snd__h615387 or _theResult___sfd__h615909) + always@(guard__h607361 or + _theResult___snd__h615384 or _theResult___sfd__h615906) begin - case (guard__h607364) + case (guard__h607361) 2'b0: - CASE_guard07364_0b0_theResult___snd15387_BITS__ETC__q67 = - _theResult___snd__h615387[56:34]; + CASE_guard07361_0b0_theResult___snd15384_BITS__ETC__q67 = + _theResult___snd__h615384[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard07364_0b0_theResult___snd15387_BITS__ETC__q67 = - _theResult___sfd__h615909; + CASE_guard07361_0b0_theResult___snd15384_BITS__ETC__q67 = + _theResult___sfd__h615906; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard07364_0b0_theResult___snd15387_BITS__ETC__q66 or - CASE_guard07364_0b0_theResult___snd15387_BITS__ETC__q67 or + CASE_guard07361_0b0_theResult___snd15384_BITS__ETC__q66 or + CASE_guard07361_0b0_theResult___snd15384_BITS__ETC__q67 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9236 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9238 or - _theResult___snd__h615387) + _theResult___snd__h615384) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h615987 = - CASE_guard07364_0b0_theResult___snd15387_BITS__ETC__q66; + _theResult___fst_sfd__h615984 = + CASE_guard07361_0b0_theResult___snd15384_BITS__ETC__q66; 3'd1: - _theResult___fst_sfd__h615987 = - CASE_guard07364_0b0_theResult___snd15387_BITS__ETC__q67; + _theResult___fst_sfd__h615984 = + CASE_guard07361_0b0_theResult___snd15384_BITS__ETC__q67; 3'd2: - _theResult___fst_sfd__h615987 = + _theResult___fst_sfd__h615984 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9236; 3'd3: - _theResult___fst_sfd__h615987 = + _theResult___fst_sfd__h615984 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9238; - 3'd4: _theResult___fst_sfd__h615987 = _theResult___snd__h615387[56:34]; - default: _theResult___fst_sfd__h615987 = 23'd0; + 3'd4: _theResult___fst_sfd__h615984 = _theResult___snd__h615384[56:34]; + default: _theResult___fst_sfd__h615984 = 23'd0; endcase end - always@(guard__h580889 or + always@(guard__h580886 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h580889) + case (guard__h580886) 2'b0, 2'b01, 2'b10: - CASE_guard80889_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q68 = + CASE_guard80886_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q68 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard80889_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q68 = - guard__h580889 == 2'b11 && + CASE_guard80886_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q68 = + guard__h580886 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard80889_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q68 or - guard__h580889) + CASE_guard80886_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q68 or + guard__h580886) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9324 = - CASE_guard80889_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q68; + CASE_guard80886_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q68; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9324 = - (guard__h580889 == 2'b0) ? + (guard__h580886 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h580889 == 2'b01 || guard__h580889 == 2'b10 || - guard__h580889 == 2'b11) && + (guard__h580886 == 2'b01 || guard__h580886 == 2'b10 || + guard__h580886 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9324 = @@ -40446,34 +40419,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h580889 or + always@(guard__h580886 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h580889) + case (guard__h580886) 2'b0, 2'b01, 2'b10: - CASE_guard80889_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q69 = + CASE_guard80886_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q69 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard80889_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q69 = - guard__h580889 != 2'b11 || + CASE_guard80886_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q69 = + guard__h580886 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard80889_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q69 or - guard__h580889) + CASE_guard80886_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q69 or + guard__h580886) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9268 = - CASE_guard80889_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q69; + CASE_guard80886_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q69; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9268 = - (guard__h580889 == 2'b0) ? + (guard__h580886 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h580889 != 2'b01 && guard__h580889 != 2'b10 && - guard__h580889 != 2'b11 || + guard__h580886 != 2'b01 && guard__h580886 != 2'b10 && + guard__h580886 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9268 = @@ -40484,34 +40457,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h589598 or + always@(guard__h589595 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h589598) + case (guard__h589595) 2'b0, 2'b01, 2'b10: - CASE_guard89598_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q70 = + CASE_guard89595_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q70 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard89598_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q70 = - guard__h589598 == 2'b11 && + CASE_guard89595_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q70 = + guard__h589595 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard89598_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q70 or - guard__h589598) + CASE_guard89595_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q70 or + guard__h589595) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9331 = - CASE_guard89598_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q70; + CASE_guard89595_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q70; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9331 = - (guard__h589598 == 2'b0) ? + (guard__h589595 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h589598 == 2'b01 || guard__h589598 == 2'b10 || - guard__h589598 == 2'b11) && + (guard__h589595 == 2'b01 || guard__h589595 == 2'b10 || + guard__h589595 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9331 = @@ -40522,34 +40495,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h589598 or + always@(guard__h589595 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h589598) + case (guard__h589595) 2'b0, 2'b01, 2'b10: - CASE_guard89598_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q71 = + CASE_guard89595_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q71 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard89598_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q71 = - guard__h589598 != 2'b11 || + CASE_guard89595_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q71 = + guard__h589595 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard89598_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q71 or - guard__h589598) + CASE_guard89595_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q71 or + guard__h589595) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9281 = - CASE_guard89598_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q71; + CASE_guard89595_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q71; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9281 = - (guard__h589598 == 2'b0) ? + (guard__h589595 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h589598 != 2'b01 && guard__h589598 != 2'b10 && - guard__h589598 != 2'b11 || + guard__h589595 != 2'b01 && guard__h589595 != 2'b10 && + guard__h589595 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9281 = @@ -40560,34 +40533,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h598528 or + always@(guard__h598525 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h598528) + case (guard__h598525) 2'b0, 2'b01, 2'b10: - CASE_guard98528_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q72 = + CASE_guard98525_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q72 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard98528_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q72 = - guard__h598528 == 2'b11 && + CASE_guard98525_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q72 = + guard__h598525 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard98528_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q72 or - guard__h598528) + CASE_guard98525_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q72 or + guard__h598525) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9341 = - CASE_guard98528_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q72; + CASE_guard98525_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q72; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9341 = - (guard__h598528 == 2'b0) ? + (guard__h598525 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h598528 == 2'b01 || guard__h598528 == 2'b10 || - guard__h598528 == 2'b11) && + (guard__h598525 == 2'b01 || guard__h598525 == 2'b10 || + guard__h598525 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9341 = @@ -40598,34 +40571,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h598528 or + always@(guard__h598525 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h598528) + case (guard__h598525) 2'b0, 2'b01, 2'b10: - CASE_guard98528_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q73 = + CASE_guard98525_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q73 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard98528_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q73 = - guard__h598528 != 2'b11 || + CASE_guard98525_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q73 = + guard__h598525 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard98528_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q73 or - guard__h598528) + CASE_guard98525_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q73 or + guard__h598525) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9298 = - CASE_guard98528_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q73; + CASE_guard98525_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q73; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9298 = - (guard__h598528 == 2'b0) ? + (guard__h598525 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h598528 != 2'b01 && guard__h598528 != 2'b10 && - guard__h598528 != 2'b11 || + guard__h598525 != 2'b01 && guard__h598525 != 2'b10 && + guard__h598525 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9298 = @@ -40636,34 +40609,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h607364 or + always@(guard__h607361 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h607364) + case (guard__h607361) 2'b0, 2'b01, 2'b10: - CASE_guard07364_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q74 = + CASE_guard07361_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q74 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard07364_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q74 = - guard__h607364 == 2'b11 && + CASE_guard07361_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q74 = + guard__h607361 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard07364_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q74 or - guard__h607364) + CASE_guard07361_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q74 or + guard__h607361) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9348 = - CASE_guard07364_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q74; + CASE_guard07361_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q74; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9348 = - (guard__h607364 == 2'b0) ? + (guard__h607361 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h607364 == 2'b01 || guard__h607364 == 2'b10 || - guard__h607364 == 2'b11) && + (guard__h607361 == 2'b01 || guard__h607361 == 2'b10 || + guard__h607361 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9348 = @@ -40674,34 +40647,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h607364 or + always@(guard__h607361 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h607364) + case (guard__h607361) 2'b0, 2'b01, 2'b10: - CASE_guard07364_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q75 = + CASE_guard07361_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q75 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard07364_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q75 = - guard__h607364 != 2'b11 || + CASE_guard07361_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q75 = + guard__h607361 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard07364_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q75 or - guard__h607364) + CASE_guard07361_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q75 or + guard__h607361) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9311 = - CASE_guard07364_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q75; + CASE_guard07361_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q75; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9311 = - (guard__h607364 == 2'b0) ? + (guard__h607361 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h607364 != 2'b01 && guard__h607364 != 2'b10 && - guard__h607364 != 2'b11 || + guard__h607361 != 2'b01 && guard__h607361 != 2'b10 && + guard__h607361 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9311 = @@ -40738,446 +40711,446 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h635347 or - _theResult___fst_exp__h643395 or - out_exp__h643840 or _theResult___exp__h643837) + always@(guard__h635344 or + _theResult___fst_exp__h643392 or + out_exp__h643837 or _theResult___exp__h643834) begin - case (guard__h635347) + case (guard__h635344) 2'b0, 2'b01: - CASE_guard35347_0b0_theResult___fst_exp43395_0_ETC__q80 = - _theResult___fst_exp__h643395; + CASE_guard35344_0b0_theResult___fst_exp43392_0_ETC__q80 = + _theResult___fst_exp__h643392; 2'b10: - CASE_guard35347_0b0_theResult___fst_exp43395_0_ETC__q80 = - out_exp__h643840; + CASE_guard35344_0b0_theResult___fst_exp43392_0_ETC__q80 = + out_exp__h643837; 2'b11: - CASE_guard35347_0b0_theResult___fst_exp43395_0_ETC__q80 = - _theResult___exp__h643837; + CASE_guard35344_0b0_theResult___fst_exp43392_0_ETC__q80 = + _theResult___exp__h643834; endcase end - always@(guard__h635347 or - _theResult___fst_exp__h643395 or _theResult___exp__h643837) + always@(guard__h635344 or + _theResult___fst_exp__h643392 or _theResult___exp__h643834) begin - case (guard__h635347) + case (guard__h635344) 2'b0: - CASE_guard35347_0b0_theResult___fst_exp43395_0_ETC__q81 = - _theResult___fst_exp__h643395; + CASE_guard35344_0b0_theResult___fst_exp43392_0_ETC__q81 = + _theResult___fst_exp__h643392; 2'b01, 2'b10, 2'b11: - CASE_guard35347_0b0_theResult___fst_exp43395_0_ETC__q81 = - _theResult___exp__h643837; + CASE_guard35344_0b0_theResult___fst_exp43392_0_ETC__q81 = + _theResult___exp__h643834; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard35347_0b0_theResult___fst_exp43395_0_ETC__q80 or - CASE_guard35347_0b0_theResult___fst_exp43395_0_ETC__q81 or + CASE_guard35344_0b0_theResult___fst_exp43392_0_ETC__q80 or + CASE_guard35344_0b0_theResult___fst_exp43392_0_ETC__q81 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10143 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10145 or - _theResult___fst_exp__h643395) + _theResult___fst_exp__h643392) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h643915 = - CASE_guard35347_0b0_theResult___fst_exp43395_0_ETC__q80; + _theResult___fst_exp__h643912 = + CASE_guard35344_0b0_theResult___fst_exp43392_0_ETC__q80; 3'd1: - _theResult___fst_exp__h643915 = - CASE_guard35347_0b0_theResult___fst_exp43395_0_ETC__q81; + _theResult___fst_exp__h643912 = + CASE_guard35344_0b0_theResult___fst_exp43392_0_ETC__q81; 3'd2: - _theResult___fst_exp__h643915 = + _theResult___fst_exp__h643912 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10143; 3'd3: - _theResult___fst_exp__h643915 = + _theResult___fst_exp__h643912 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10145; - 3'd4: _theResult___fst_exp__h643915 = _theResult___fst_exp__h643395; - default: _theResult___fst_exp__h643915 = 8'd0; + 3'd4: _theResult___fst_exp__h643912 = _theResult___fst_exp__h643392; + default: _theResult___fst_exp__h643912 = 8'd0; endcase end - always@(guard__h626640 or - _theResult___fst_exp__h634739 or - out_exp__h635258 or _theResult___exp__h635255) + always@(guard__h626637 or + _theResult___fst_exp__h634736 or + out_exp__h635255 or _theResult___exp__h635252) begin - case (guard__h626640) + case (guard__h626637) 2'b0, 2'b01: - CASE_guard26640_0b0_theResult___fst_exp34739_0_ETC__q82 = - _theResult___fst_exp__h634739; + CASE_guard26637_0b0_theResult___fst_exp34736_0_ETC__q82 = + _theResult___fst_exp__h634736; 2'b10: - CASE_guard26640_0b0_theResult___fst_exp34739_0_ETC__q82 = - out_exp__h635258; + CASE_guard26637_0b0_theResult___fst_exp34736_0_ETC__q82 = + out_exp__h635255; 2'b11: - CASE_guard26640_0b0_theResult___fst_exp34739_0_ETC__q82 = - _theResult___exp__h635255; + CASE_guard26637_0b0_theResult___fst_exp34736_0_ETC__q82 = + _theResult___exp__h635252; endcase end - always@(guard__h626640 or - _theResult___fst_exp__h634739 or _theResult___exp__h635255) + always@(guard__h626637 or + _theResult___fst_exp__h634736 or _theResult___exp__h635252) begin - case (guard__h626640) + case (guard__h626637) 2'b0: - CASE_guard26640_0b0_theResult___fst_exp34739_0_ETC__q83 = - _theResult___fst_exp__h634739; + CASE_guard26637_0b0_theResult___fst_exp34736_0_ETC__q83 = + _theResult___fst_exp__h634736; 2'b01, 2'b10, 2'b11: - CASE_guard26640_0b0_theResult___fst_exp34739_0_ETC__q83 = - _theResult___exp__h635255; + CASE_guard26637_0b0_theResult___fst_exp34736_0_ETC__q83 = + _theResult___exp__h635252; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard26640_0b0_theResult___fst_exp34739_0_ETC__q82 or - CASE_guard26640_0b0_theResult___fst_exp34739_0_ETC__q83 or + CASE_guard26637_0b0_theResult___fst_exp34736_0_ETC__q82 or + CASE_guard26637_0b0_theResult___fst_exp34736_0_ETC__q83 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9921 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9924 or - _theResult___fst_exp__h634739) + _theResult___fst_exp__h634736) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h635333 = - CASE_guard26640_0b0_theResult___fst_exp34739_0_ETC__q82; + _theResult___fst_exp__h635330 = + CASE_guard26637_0b0_theResult___fst_exp34736_0_ETC__q82; 3'd1: - _theResult___fst_exp__h635333 = - CASE_guard26640_0b0_theResult___fst_exp34739_0_ETC__q83; + _theResult___fst_exp__h635330 = + CASE_guard26637_0b0_theResult___fst_exp34736_0_ETC__q83; 3'd2: - _theResult___fst_exp__h635333 = + _theResult___fst_exp__h635330 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9921; 3'd3: - _theResult___fst_exp__h635333 = + _theResult___fst_exp__h635330 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9924; - 3'd4: _theResult___fst_exp__h635333 = _theResult___fst_exp__h634739; - default: _theResult___fst_exp__h635333 = 8'd0; + 3'd4: _theResult___fst_exp__h635330 = _theResult___fst_exp__h634736; + default: _theResult___fst_exp__h635330 = 8'd0; endcase end - always@(guard__h644277 or - _theResult___fst_exp__h652505 or - out_exp__h653024 or _theResult___exp__h653021) + always@(guard__h644274 or + _theResult___fst_exp__h652502 or + out_exp__h653021 or _theResult___exp__h653018) begin - case (guard__h644277) + case (guard__h644274) 2'b0, 2'b01: - CASE_guard44277_0b0_theResult___fst_exp52505_0_ETC__q88 = - _theResult___fst_exp__h652505; + CASE_guard44274_0b0_theResult___fst_exp52502_0_ETC__q88 = + _theResult___fst_exp__h652502; 2'b10: - CASE_guard44277_0b0_theResult___fst_exp52505_0_ETC__q88 = - out_exp__h653024; + CASE_guard44274_0b0_theResult___fst_exp52502_0_ETC__q88 = + out_exp__h653021; 2'b11: - CASE_guard44277_0b0_theResult___fst_exp52505_0_ETC__q88 = - _theResult___exp__h653021; + CASE_guard44274_0b0_theResult___fst_exp52502_0_ETC__q88 = + _theResult___exp__h653018; endcase end - always@(guard__h644277 or - _theResult___fst_exp__h652505 or _theResult___exp__h653021) + always@(guard__h644274 or + _theResult___fst_exp__h652502 or _theResult___exp__h653018) begin - case (guard__h644277) + case (guard__h644274) 2'b0: - CASE_guard44277_0b0_theResult___fst_exp52505_0_ETC__q89 = - _theResult___fst_exp__h652505; + CASE_guard44274_0b0_theResult___fst_exp52502_0_ETC__q89 = + _theResult___fst_exp__h652502; 2'b01, 2'b10, 2'b11: - CASE_guard44277_0b0_theResult___fst_exp52505_0_ETC__q89 = - _theResult___exp__h653021; + CASE_guard44274_0b0_theResult___fst_exp52502_0_ETC__q89 = + _theResult___exp__h653018; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard44277_0b0_theResult___fst_exp52505_0_ETC__q88 or - CASE_guard44277_0b0_theResult___fst_exp52505_0_ETC__q89 or + CASE_guard44274_0b0_theResult___fst_exp52502_0_ETC__q88 or + CASE_guard44274_0b0_theResult___fst_exp52502_0_ETC__q89 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10468 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10470 or - _theResult___fst_exp__h652505) + _theResult___fst_exp__h652502) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h653099 = - CASE_guard44277_0b0_theResult___fst_exp52505_0_ETC__q88; + _theResult___fst_exp__h653096 = + CASE_guard44274_0b0_theResult___fst_exp52502_0_ETC__q88; 3'd1: - _theResult___fst_exp__h653099 = - CASE_guard44277_0b0_theResult___fst_exp52505_0_ETC__q89; + _theResult___fst_exp__h653096 = + CASE_guard44274_0b0_theResult___fst_exp52502_0_ETC__q89; 3'd2: - _theResult___fst_exp__h653099 = + _theResult___fst_exp__h653096 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10468; 3'd3: - _theResult___fst_exp__h653099 = + _theResult___fst_exp__h653096 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10470; - 3'd4: _theResult___fst_exp__h653099 = _theResult___fst_exp__h652505; - default: _theResult___fst_exp__h653099 = 8'd0; + 3'd4: _theResult___fst_exp__h653096 = _theResult___fst_exp__h652502; + default: _theResult___fst_exp__h653096 = 8'd0; endcase end - always@(guard__h653113 or - _theResult___fst_exp__h661190 or - out_exp__h661660 or _theResult___exp__h661657) + always@(guard__h653110 or + _theResult___fst_exp__h661187 or + out_exp__h661657 or _theResult___exp__h661654) begin - case (guard__h653113) + case (guard__h653110) 2'b0, 2'b01: - CASE_guard53113_0b0_theResult___fst_exp61190_0_ETC__q93 = - _theResult___fst_exp__h661190; + CASE_guard53110_0b0_theResult___fst_exp61187_0_ETC__q93 = + _theResult___fst_exp__h661187; 2'b10: - CASE_guard53113_0b0_theResult___fst_exp61190_0_ETC__q93 = - out_exp__h661660; + CASE_guard53110_0b0_theResult___fst_exp61187_0_ETC__q93 = + out_exp__h661657; 2'b11: - CASE_guard53113_0b0_theResult___fst_exp61190_0_ETC__q93 = - _theResult___exp__h661657; + CASE_guard53110_0b0_theResult___fst_exp61187_0_ETC__q93 = + _theResult___exp__h661654; endcase end - always@(guard__h653113 or - _theResult___fst_exp__h661190 or _theResult___exp__h661657) + always@(guard__h653110 or + _theResult___fst_exp__h661187 or _theResult___exp__h661654) begin - case (guard__h653113) + case (guard__h653110) 2'b0: - CASE_guard53113_0b0_theResult___fst_exp61190_0_ETC__q94 = - _theResult___fst_exp__h661190; + CASE_guard53110_0b0_theResult___fst_exp61187_0_ETC__q94 = + _theResult___fst_exp__h661187; 2'b01, 2'b10, 2'b11: - CASE_guard53113_0b0_theResult___fst_exp61190_0_ETC__q94 = - _theResult___exp__h661657; + CASE_guard53110_0b0_theResult___fst_exp61187_0_ETC__q94 = + _theResult___exp__h661654; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard53113_0b0_theResult___fst_exp61190_0_ETC__q93 or - CASE_guard53113_0b0_theResult___fst_exp61190_0_ETC__q94 or + CASE_guard53110_0b0_theResult___fst_exp61187_0_ETC__q93 or + CASE_guard53110_0b0_theResult___fst_exp61187_0_ETC__q94 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10537 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10539 or - _theResult___fst_exp__h661190) + _theResult___fst_exp__h661187) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h661735 = - CASE_guard53113_0b0_theResult___fst_exp61190_0_ETC__q93; + _theResult___fst_exp__h661732 = + CASE_guard53110_0b0_theResult___fst_exp61187_0_ETC__q93; 3'd1: - _theResult___fst_exp__h661735 = - CASE_guard53113_0b0_theResult___fst_exp61190_0_ETC__q94; + _theResult___fst_exp__h661732 = + CASE_guard53110_0b0_theResult___fst_exp61187_0_ETC__q94; 3'd2: - _theResult___fst_exp__h661735 = + _theResult___fst_exp__h661732 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10537; 3'd3: - _theResult___fst_exp__h661735 = + _theResult___fst_exp__h661732 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10539; - 3'd4: _theResult___fst_exp__h661735 = _theResult___fst_exp__h661190; - default: _theResult___fst_exp__h661735 = 8'd0; + 3'd4: _theResult___fst_exp__h661732 = _theResult___fst_exp__h661187; + default: _theResult___fst_exp__h661732 = 8'd0; endcase end - always@(guard__h635347 or - _theResult___snd__h643346 or - out_sfd__h643841 or _theResult___sfd__h643838) + always@(guard__h626637 or + sfdin__h634730 or out_sfd__h635256 or _theResult___sfd__h635253) begin - case (guard__h635347) + case (guard__h626637) 2'b0, 2'b01: - CASE_guard35347_0b0_theResult___snd43346_BITS__ETC__q95 = - _theResult___snd__h643346[56:34]; + CASE_guard26637_0b0_sfdin34730_BITS_56_TO_34_0_ETC__q95 = + sfdin__h634730[56:34]; 2'b10: - CASE_guard35347_0b0_theResult___snd43346_BITS__ETC__q95 = - out_sfd__h643841; + CASE_guard26637_0b0_sfdin34730_BITS_56_TO_34_0_ETC__q95 = + out_sfd__h635256; 2'b11: - CASE_guard35347_0b0_theResult___snd43346_BITS__ETC__q95 = - _theResult___sfd__h643838; + CASE_guard26637_0b0_sfdin34730_BITS_56_TO_34_0_ETC__q95 = + _theResult___sfd__h635253; endcase end - always@(guard__h635347 or - _theResult___snd__h643346 or _theResult___sfd__h643838) + always@(guard__h626637 or sfdin__h634730 or _theResult___sfd__h635253) begin - case (guard__h635347) + case (guard__h626637) 2'b0: - CASE_guard35347_0b0_theResult___snd43346_BITS__ETC__q96 = - _theResult___snd__h643346[56:34]; + CASE_guard26637_0b0_sfdin34730_BITS_56_TO_34_0_ETC__q96 = + sfdin__h634730[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard35347_0b0_theResult___snd43346_BITS__ETC__q96 = - _theResult___sfd__h643838; + CASE_guard26637_0b0_sfdin34730_BITS_56_TO_34_0_ETC__q96 = + _theResult___sfd__h635253; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard35347_0b0_theResult___snd43346_BITS__ETC__q95 or - CASE_guard35347_0b0_theResult___snd43346_BITS__ETC__q96 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10587 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10589 or - _theResult___snd__h643346) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0: - _theResult___fst_sfd__h643916 = - CASE_guard35347_0b0_theResult___snd43346_BITS__ETC__q95; - 3'd1: - _theResult___fst_sfd__h643916 = - CASE_guard35347_0b0_theResult___snd43346_BITS__ETC__q96; - 3'd2: - _theResult___fst_sfd__h643916 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10587; - 3'd3: - _theResult___fst_sfd__h643916 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10589; - 3'd4: _theResult___fst_sfd__h643916 = _theResult___snd__h643346[56:34]; - default: _theResult___fst_sfd__h643916 = 23'd0; - endcase - end - always@(guard__h626640 or - sfdin__h634733 or out_sfd__h635259 or _theResult___sfd__h635256) - begin - case (guard__h626640) - 2'b0, 2'b01: - CASE_guard26640_0b0_sfdin34733_BITS_56_TO_34_0_ETC__q97 = - sfdin__h634733[56:34]; - 2'b10: - CASE_guard26640_0b0_sfdin34733_BITS_56_TO_34_0_ETC__q97 = - out_sfd__h635259; - 2'b11: - CASE_guard26640_0b0_sfdin34733_BITS_56_TO_34_0_ETC__q97 = - _theResult___sfd__h635256; - endcase - end - always@(guard__h626640 or sfdin__h634733 or _theResult___sfd__h635256) - begin - case (guard__h626640) - 2'b0: - CASE_guard26640_0b0_sfdin34733_BITS_56_TO_34_0_ETC__q98 = - sfdin__h634733[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard26640_0b0_sfdin34733_BITS_56_TO_34_0_ETC__q98 = - _theResult___sfd__h635256; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard26640_0b0_sfdin34733_BITS_56_TO_34_0_ETC__q97 or - CASE_guard26640_0b0_sfdin34733_BITS_56_TO_34_0_ETC__q98 or + CASE_guard26637_0b0_sfdin34730_BITS_56_TO_34_0_ETC__q95 or + CASE_guard26637_0b0_sfdin34730_BITS_56_TO_34_0_ETC__q96 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d10568 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d10570 or - sfdin__h634733) + sfdin__h634730) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h635334 = - CASE_guard26640_0b0_sfdin34733_BITS_56_TO_34_0_ETC__q97; + _theResult___fst_sfd__h635331 = + CASE_guard26637_0b0_sfdin34730_BITS_56_TO_34_0_ETC__q95; 3'd1: - _theResult___fst_sfd__h635334 = - CASE_guard26640_0b0_sfdin34733_BITS_56_TO_34_0_ETC__q98; + _theResult___fst_sfd__h635331 = + CASE_guard26637_0b0_sfdin34730_BITS_56_TO_34_0_ETC__q96; 3'd2: - _theResult___fst_sfd__h635334 = + _theResult___fst_sfd__h635331 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d10568; 3'd3: - _theResult___fst_sfd__h635334 = + _theResult___fst_sfd__h635331 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d10570; - 3'd4: _theResult___fst_sfd__h635334 = sfdin__h634733[56:34]; - default: _theResult___fst_sfd__h635334 = 23'd0; + 3'd4: _theResult___fst_sfd__h635331 = sfdin__h634730[56:34]; + default: _theResult___fst_sfd__h635331 = 23'd0; endcase end - always@(guard__h644277 or - sfdin__h652499 or out_sfd__h653025 or _theResult___sfd__h653022) + always@(guard__h635344 or + _theResult___snd__h643343 or + out_sfd__h643838 or _theResult___sfd__h643835) begin - case (guard__h644277) + case (guard__h635344) 2'b0, 2'b01: - CASE_guard44277_0b0_sfdin52499_BITS_56_TO_34_0_ETC__q99 = - sfdin__h652499[56:34]; + CASE_guard35344_0b0_theResult___snd43343_BITS__ETC__q97 = + _theResult___snd__h643343[56:34]; 2'b10: - CASE_guard44277_0b0_sfdin52499_BITS_56_TO_34_0_ETC__q99 = - out_sfd__h653025; + CASE_guard35344_0b0_theResult___snd43343_BITS__ETC__q97 = + out_sfd__h643838; 2'b11: - CASE_guard44277_0b0_sfdin52499_BITS_56_TO_34_0_ETC__q99 = - _theResult___sfd__h653022; + CASE_guard35344_0b0_theResult___snd43343_BITS__ETC__q97 = + _theResult___sfd__h643835; endcase end - always@(guard__h644277 or sfdin__h652499 or _theResult___sfd__h653022) + always@(guard__h635344 or + _theResult___snd__h643343 or _theResult___sfd__h643835) begin - case (guard__h644277) + case (guard__h635344) 2'b0: - CASE_guard44277_0b0_sfdin52499_BITS_56_TO_34_0_ETC__q100 = - sfdin__h652499[56:34]; + CASE_guard35344_0b0_theResult___snd43343_BITS__ETC__q98 = + _theResult___snd__h643343[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard44277_0b0_sfdin52499_BITS_56_TO_34_0_ETC__q100 = - _theResult___sfd__h653022; + CASE_guard35344_0b0_theResult___snd43343_BITS__ETC__q98 = + _theResult___sfd__h643835; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard44277_0b0_sfdin52499_BITS_56_TO_34_0_ETC__q99 or - CASE_guard44277_0b0_sfdin52499_BITS_56_TO_34_0_ETC__q100 or + CASE_guard35344_0b0_theResult___snd43343_BITS__ETC__q97 or + CASE_guard35344_0b0_theResult___snd43343_BITS__ETC__q98 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10587 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10589 or + _theResult___snd__h643343) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) + 3'd0: + _theResult___fst_sfd__h643913 = + CASE_guard35344_0b0_theResult___snd43343_BITS__ETC__q97; + 3'd1: + _theResult___fst_sfd__h643913 = + CASE_guard35344_0b0_theResult___snd43343_BITS__ETC__q98; + 3'd2: + _theResult___fst_sfd__h643913 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10587; + 3'd3: + _theResult___fst_sfd__h643913 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10589; + 3'd4: _theResult___fst_sfd__h643913 = _theResult___snd__h643343[56:34]; + default: _theResult___fst_sfd__h643913 = 23'd0; + endcase + end + always@(guard__h644274 or + sfdin__h652496 or out_sfd__h653022 or _theResult___sfd__h653019) + begin + case (guard__h644274) + 2'b0, 2'b01: + CASE_guard44274_0b0_sfdin52496_BITS_56_TO_34_0_ETC__q99 = + sfdin__h652496[56:34]; + 2'b10: + CASE_guard44274_0b0_sfdin52496_BITS_56_TO_34_0_ETC__q99 = + out_sfd__h653022; + 2'b11: + CASE_guard44274_0b0_sfdin52496_BITS_56_TO_34_0_ETC__q99 = + _theResult___sfd__h653019; + endcase + end + always@(guard__h644274 or sfdin__h652496 or _theResult___sfd__h653019) + begin + case (guard__h644274) + 2'b0: + CASE_guard44274_0b0_sfdin52496_BITS_56_TO_34_0_ETC__q100 = + sfdin__h652496[56:34]; + 2'b01, 2'b10, 2'b11: + CASE_guard44274_0b0_sfdin52496_BITS_56_TO_34_0_ETC__q100 = + _theResult___sfd__h653019; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or + CASE_guard44274_0b0_sfdin52496_BITS_56_TO_34_0_ETC__q99 or + CASE_guard44274_0b0_sfdin52496_BITS_56_TO_34_0_ETC__q100 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10614 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10616 or - sfdin__h652499) + sfdin__h652496) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h653100 = - CASE_guard44277_0b0_sfdin52499_BITS_56_TO_34_0_ETC__q99; + _theResult___fst_sfd__h653097 = + CASE_guard44274_0b0_sfdin52496_BITS_56_TO_34_0_ETC__q99; 3'd1: - _theResult___fst_sfd__h653100 = - CASE_guard44277_0b0_sfdin52499_BITS_56_TO_34_0_ETC__q100; + _theResult___fst_sfd__h653097 = + CASE_guard44274_0b0_sfdin52496_BITS_56_TO_34_0_ETC__q100; 3'd2: - _theResult___fst_sfd__h653100 = + _theResult___fst_sfd__h653097 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10614; 3'd3: - _theResult___fst_sfd__h653100 = + _theResult___fst_sfd__h653097 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10616; - 3'd4: _theResult___fst_sfd__h653100 = sfdin__h652499[56:34]; - default: _theResult___fst_sfd__h653100 = 23'd0; + 3'd4: _theResult___fst_sfd__h653097 = sfdin__h652496[56:34]; + default: _theResult___fst_sfd__h653097 = 23'd0; endcase end - always@(guard__h653113 or - _theResult___snd__h661136 or - out_sfd__h661661 or _theResult___sfd__h661658) + always@(guard__h653110 or + _theResult___snd__h661133 or + out_sfd__h661658 or _theResult___sfd__h661655) begin - case (guard__h653113) + case (guard__h653110) 2'b0, 2'b01: - CASE_guard53113_0b0_theResult___snd61136_BITS__ETC__q101 = - _theResult___snd__h661136[56:34]; + CASE_guard53110_0b0_theResult___snd61133_BITS__ETC__q101 = + _theResult___snd__h661133[56:34]; 2'b10: - CASE_guard53113_0b0_theResult___snd61136_BITS__ETC__q101 = - out_sfd__h661661; + CASE_guard53110_0b0_theResult___snd61133_BITS__ETC__q101 = + out_sfd__h661658; 2'b11: - CASE_guard53113_0b0_theResult___snd61136_BITS__ETC__q101 = - _theResult___sfd__h661658; + CASE_guard53110_0b0_theResult___snd61133_BITS__ETC__q101 = + _theResult___sfd__h661655; endcase end - always@(guard__h653113 or - _theResult___snd__h661136 or _theResult___sfd__h661658) + always@(guard__h653110 or + _theResult___snd__h661133 or _theResult___sfd__h661655) begin - case (guard__h653113) + case (guard__h653110) 2'b0: - CASE_guard53113_0b0_theResult___snd61136_BITS__ETC__q102 = - _theResult___snd__h661136[56:34]; + CASE_guard53110_0b0_theResult___snd61133_BITS__ETC__q102 = + _theResult___snd__h661133[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard53113_0b0_theResult___snd61136_BITS__ETC__q102 = - _theResult___sfd__h661658; + CASE_guard53110_0b0_theResult___snd61133_BITS__ETC__q102 = + _theResult___sfd__h661655; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard53113_0b0_theResult___snd61136_BITS__ETC__q101 or - CASE_guard53113_0b0_theResult___snd61136_BITS__ETC__q102 or + CASE_guard53110_0b0_theResult___snd61133_BITS__ETC__q101 or + CASE_guard53110_0b0_theResult___snd61133_BITS__ETC__q102 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10633 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10635 or - _theResult___snd__h661136) + _theResult___snd__h661133) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h661736 = - CASE_guard53113_0b0_theResult___snd61136_BITS__ETC__q101; + _theResult___fst_sfd__h661733 = + CASE_guard53110_0b0_theResult___snd61133_BITS__ETC__q101; 3'd1: - _theResult___fst_sfd__h661736 = - CASE_guard53113_0b0_theResult___snd61136_BITS__ETC__q102; + _theResult___fst_sfd__h661733 = + CASE_guard53110_0b0_theResult___snd61133_BITS__ETC__q102; 3'd2: - _theResult___fst_sfd__h661736 = + _theResult___fst_sfd__h661733 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10633; 3'd3: - _theResult___fst_sfd__h661736 = + _theResult___fst_sfd__h661733 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10635; - 3'd4: _theResult___fst_sfd__h661736 = _theResult___snd__h661136[56:34]; - default: _theResult___fst_sfd__h661736 = 23'd0; + 3'd4: _theResult___fst_sfd__h661733 = _theResult___snd__h661133[56:34]; + default: _theResult___fst_sfd__h661733 = 23'd0; endcase end - always@(guard__h626640 or + always@(guard__h626637 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h626640) + case (guard__h626637) 2'b0, 2'b01, 2'b10: - CASE_guard26640_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q103 = + CASE_guard26637_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q103 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard26640_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q103 = - guard__h626640 == 2'b11 && + CASE_guard26637_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q103 = + guard__h626637 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard26640_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q103 or - guard__h626640) + CASE_guard26637_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q103 or + guard__h626637) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10721 = - CASE_guard26640_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q103; + CASE_guard26637_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q103; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10721 = - (guard__h626640 == 2'b0) ? + (guard__h626637 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h626640 == 2'b01 || guard__h626640 == 2'b10 || - guard__h626640 == 2'b11) && + (guard__h626637 == 2'b01 || guard__h626637 == 2'b10 || + guard__h626637 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10721 = @@ -41188,72 +41161,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h626640 or + always@(guard__h635344 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h626640) + case (guard__h635344) 2'b0, 2'b01, 2'b10: - CASE_guard26640_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q104 = - !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; - 2'd3: - CASE_guard26640_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q104 = - guard__h626640 != 2'b11 || - !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard26640_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q104 or - guard__h626640) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0: - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10665 = - CASE_guard26640_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q104; - 3'd1: - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10665 = - (guard__h626640 == 2'b0) ? - !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h626640 != 2'b01 && guard__h626640 != 2'b10 && - guard__h626640 != 2'b11 || - !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; - 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10665 = - !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10665 = - coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] != - 3'd4 || - !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; - endcase - end - always@(guard__h635347 or - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) - begin - case (guard__h635347) - 2'b0, 2'b01, 2'b10: - CASE_guard35347_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q105 = + CASE_guard35344_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q104 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard35347_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q105 = - guard__h635347 == 2'b11 && + CASE_guard35344_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q104 = + guard__h635344 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard35347_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q105 or - guard__h635347) + CASE_guard35344_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q104 or + guard__h635344) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10728 = - CASE_guard35347_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q105; + CASE_guard35344_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q104; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10728 = - (guard__h635347 == 2'b0) ? + (guard__h635344 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h635347 == 2'b01 || guard__h635347 == 2'b10 || - guard__h635347 == 2'b11) && + (guard__h635344 == 2'b01 || guard__h635344 == 2'b10 || + guard__h635344 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10728 = @@ -41264,34 +41199,72 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h635347 or + always@(guard__h626637 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h635347) + case (guard__h626637) 2'b0, 2'b01, 2'b10: - CASE_guard35347_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q106 = + CASE_guard26637_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q105 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard35347_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q106 = - guard__h635347 != 2'b11 || + CASE_guard26637_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q105 = + guard__h626637 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard35347_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q106 or - guard__h635347) + CASE_guard26637_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q105 or + guard__h626637) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) + 3'd0: + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10665 = + CASE_guard26637_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q105; + 3'd1: + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10665 = + (guard__h626637 == 2'b0) ? + !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : + guard__h626637 != 2'b01 && guard__h626637 != 2'b10 && + guard__h626637 != 2'b11 || + !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; + 3'd2, 3'd3: + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10665 = + !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; + default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10665 = + coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] != + 3'd4 || + !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; + endcase + end + always@(guard__h635344 or + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) + begin + case (guard__h635344) + 2'b0, 2'b01, 2'b10: + CASE_guard35344_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q106 = + !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; + 2'd3: + CASE_guard35344_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q106 = + guard__h635344 != 2'b11 || + !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or + CASE_guard35344_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q106 or + guard__h635344) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10678 = - CASE_guard35347_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q106; + CASE_guard35344_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q106; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10678 = - (guard__h635347 == 2'b0) ? + (guard__h635344 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h635347 != 2'b01 && guard__h635347 != 2'b10 && - guard__h635347 != 2'b11 || + guard__h635344 != 2'b01 && guard__h635344 != 2'b10 && + guard__h635344 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10678 = @@ -41302,34 +41275,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h644277 or + always@(guard__h644274 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h644277) + case (guard__h644274) 2'b0, 2'b01, 2'b10: - CASE_guard44277_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q107 = + CASE_guard44274_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q107 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard44277_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q107 = - guard__h644277 == 2'b11 && + CASE_guard44274_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q107 = + guard__h644274 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard44277_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q107 or - guard__h644277) + CASE_guard44274_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q107 or + guard__h644274) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10738 = - CASE_guard44277_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q107; + CASE_guard44274_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q107; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10738 = - (guard__h644277 == 2'b0) ? + (guard__h644274 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h644277 == 2'b01 || guard__h644277 == 2'b10 || - guard__h644277 == 2'b11) && + (guard__h644274 == 2'b01 || guard__h644274 == 2'b10 || + guard__h644274 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10738 = @@ -41340,34 +41313,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h644277 or + always@(guard__h644274 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h644277) + case (guard__h644274) 2'b0, 2'b01, 2'b10: - CASE_guard44277_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q108 = + CASE_guard44274_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q108 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard44277_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q108 = - guard__h644277 != 2'b11 || + CASE_guard44274_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q108 = + guard__h644274 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard44277_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q108 or - guard__h644277) + CASE_guard44274_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q108 or + guard__h644274) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10695 = - CASE_guard44277_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q108; + CASE_guard44274_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q108; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10695 = - (guard__h644277 == 2'b0) ? + (guard__h644274 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h644277 != 2'b01 && guard__h644277 != 2'b10 && - guard__h644277 != 2'b11 || + guard__h644274 != 2'b01 && guard__h644274 != 2'b10 && + guard__h644274 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10695 = @@ -41378,34 +41351,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h653113 or + always@(guard__h653110 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h653113) + case (guard__h653110) 2'b0, 2'b01, 2'b10: - CASE_guard53113_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q109 = + CASE_guard53110_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q109 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard53113_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q109 = - guard__h653113 == 2'b11 && + CASE_guard53110_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q109 = + guard__h653110 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard53113_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q109 or - guard__h653113) + CASE_guard53110_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q109 or + guard__h653110) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10745 = - CASE_guard53113_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q109; + CASE_guard53110_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q109; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10745 = - (guard__h653113 == 2'b0) ? + (guard__h653110 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h653113 == 2'b01 || guard__h653113 == 2'b10 || - guard__h653113 == 2'b11) && + (guard__h653110 == 2'b01 || guard__h653110 == 2'b10 || + guard__h653110 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10745 = @@ -41416,34 +41389,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h653113 or + always@(guard__h653110 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h653113) + case (guard__h653110) 2'b0, 2'b01, 2'b10: - CASE_guard53113_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q110 = + CASE_guard53110_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q110 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard53113_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q110 = - guard__h653113 != 2'b11 || + CASE_guard53110_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q110 = + guard__h653110 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard53113_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q110 or - guard__h653113) + CASE_guard53110_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q110 or + guard__h653110) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10708 = - CASE_guard53113_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q110; + CASE_guard53110_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q110; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10708 = - (guard__h653113 == 2'b0) ? + (guard__h653110 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h653113 != 2'b01 && guard__h653113 != 2'b10 && - guard__h653113 != 2'b11 || + guard__h653110 != 2'b01 && guard__h653110 != 2'b10 && + guard__h653110 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10708 = @@ -41480,446 +41453,394 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h681094 or - _theResult___fst_exp__h689142 or - out_exp__h689587 or _theResult___exp__h689584) + always@(guard__h681091 or + _theResult___fst_exp__h689139 or + out_exp__h689584 or _theResult___exp__h689581) begin - case (guard__h681094) + case (guard__h681091) 2'b0, 2'b01: - CASE_guard81094_0b0_theResult___fst_exp89142_0_ETC__q115 = - _theResult___fst_exp__h689142; + CASE_guard81091_0b0_theResult___fst_exp89139_0_ETC__q115 = + _theResult___fst_exp__h689139; 2'b10: - CASE_guard81094_0b0_theResult___fst_exp89142_0_ETC__q115 = - out_exp__h689587; + CASE_guard81091_0b0_theResult___fst_exp89139_0_ETC__q115 = + out_exp__h689584; 2'b11: - CASE_guard81094_0b0_theResult___fst_exp89142_0_ETC__q115 = - _theResult___exp__h689584; + CASE_guard81091_0b0_theResult___fst_exp89139_0_ETC__q115 = + _theResult___exp__h689581; endcase end - always@(guard__h681094 or - _theResult___fst_exp__h689142 or _theResult___exp__h689584) + always@(guard__h681091 or + _theResult___fst_exp__h689139 or _theResult___exp__h689581) begin - case (guard__h681094) + case (guard__h681091) 2'b0: - CASE_guard81094_0b0_theResult___fst_exp89142_0_ETC__q116 = - _theResult___fst_exp__h689142; + CASE_guard81091_0b0_theResult___fst_exp89139_0_ETC__q116 = + _theResult___fst_exp__h689139; 2'b01, 2'b10, 2'b11: - CASE_guard81094_0b0_theResult___fst_exp89142_0_ETC__q116 = - _theResult___exp__h689584; + CASE_guard81091_0b0_theResult___fst_exp89139_0_ETC__q116 = + _theResult___exp__h689581; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard81094_0b0_theResult___fst_exp89142_0_ETC__q115 or - CASE_guard81094_0b0_theResult___fst_exp89142_0_ETC__q116 or + CASE_guard81091_0b0_theResult___fst_exp89139_0_ETC__q115 or + CASE_guard81091_0b0_theResult___fst_exp89139_0_ETC__q116 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11540 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11542 or - _theResult___fst_exp__h689142) + _theResult___fst_exp__h689139) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h689662 = - CASE_guard81094_0b0_theResult___fst_exp89142_0_ETC__q115; + _theResult___fst_exp__h689659 = + CASE_guard81091_0b0_theResult___fst_exp89139_0_ETC__q115; 3'd1: - _theResult___fst_exp__h689662 = - CASE_guard81094_0b0_theResult___fst_exp89142_0_ETC__q116; + _theResult___fst_exp__h689659 = + CASE_guard81091_0b0_theResult___fst_exp89139_0_ETC__q116; 3'd2: - _theResult___fst_exp__h689662 = + _theResult___fst_exp__h689659 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11540; 3'd3: - _theResult___fst_exp__h689662 = + _theResult___fst_exp__h689659 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11542; - 3'd4: _theResult___fst_exp__h689662 = _theResult___fst_exp__h689142; - default: _theResult___fst_exp__h689662 = 8'd0; + 3'd4: _theResult___fst_exp__h689659 = _theResult___fst_exp__h689139; + default: _theResult___fst_exp__h689659 = 8'd0; endcase end - always@(guard__h672387 or - _theResult___fst_exp__h680486 or - out_exp__h681005 or _theResult___exp__h681002) + always@(guard__h672384 or + _theResult___fst_exp__h680483 or + out_exp__h681002 or _theResult___exp__h680999) begin - case (guard__h672387) + case (guard__h672384) 2'b0, 2'b01: - CASE_guard72387_0b0_theResult___fst_exp80486_0_ETC__q117 = - _theResult___fst_exp__h680486; + CASE_guard72384_0b0_theResult___fst_exp80483_0_ETC__q117 = + _theResult___fst_exp__h680483; 2'b10: - CASE_guard72387_0b0_theResult___fst_exp80486_0_ETC__q117 = - out_exp__h681005; + CASE_guard72384_0b0_theResult___fst_exp80483_0_ETC__q117 = + out_exp__h681002; 2'b11: - CASE_guard72387_0b0_theResult___fst_exp80486_0_ETC__q117 = - _theResult___exp__h681002; + CASE_guard72384_0b0_theResult___fst_exp80483_0_ETC__q117 = + _theResult___exp__h680999; endcase end - always@(guard__h672387 or - _theResult___fst_exp__h680486 or _theResult___exp__h681002) + always@(guard__h672384 or + _theResult___fst_exp__h680483 or _theResult___exp__h680999) begin - case (guard__h672387) + case (guard__h672384) 2'b0: - CASE_guard72387_0b0_theResult___fst_exp80486_0_ETC__q118 = - _theResult___fst_exp__h680486; + CASE_guard72384_0b0_theResult___fst_exp80483_0_ETC__q118 = + _theResult___fst_exp__h680483; 2'b01, 2'b10, 2'b11: - CASE_guard72387_0b0_theResult___fst_exp80486_0_ETC__q118 = - _theResult___exp__h681002; + CASE_guard72384_0b0_theResult___fst_exp80483_0_ETC__q118 = + _theResult___exp__h680999; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard72387_0b0_theResult___fst_exp80486_0_ETC__q117 or - CASE_guard72387_0b0_theResult___fst_exp80486_0_ETC__q118 or + CASE_guard72384_0b0_theResult___fst_exp80483_0_ETC__q117 or + CASE_guard72384_0b0_theResult___fst_exp80483_0_ETC__q118 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11318 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11321 or - _theResult___fst_exp__h680486) + _theResult___fst_exp__h680483) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h681080 = - CASE_guard72387_0b0_theResult___fst_exp80486_0_ETC__q117; + _theResult___fst_exp__h681077 = + CASE_guard72384_0b0_theResult___fst_exp80483_0_ETC__q117; 3'd1: - _theResult___fst_exp__h681080 = - CASE_guard72387_0b0_theResult___fst_exp80486_0_ETC__q118; + _theResult___fst_exp__h681077 = + CASE_guard72384_0b0_theResult___fst_exp80483_0_ETC__q118; 3'd2: - _theResult___fst_exp__h681080 = + _theResult___fst_exp__h681077 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11318; 3'd3: - _theResult___fst_exp__h681080 = + _theResult___fst_exp__h681077 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11321; - 3'd4: _theResult___fst_exp__h681080 = _theResult___fst_exp__h680486; - default: _theResult___fst_exp__h681080 = 8'd0; + 3'd4: _theResult___fst_exp__h681077 = _theResult___fst_exp__h680483; + default: _theResult___fst_exp__h681077 = 8'd0; endcase end - always@(guard__h690024 or - _theResult___fst_exp__h698252 or - out_exp__h698771 or _theResult___exp__h698768) + always@(guard__h690021 or + _theResult___fst_exp__h698249 or + out_exp__h698768 or _theResult___exp__h698765) begin - case (guard__h690024) + case (guard__h690021) 2'b0, 2'b01: - CASE_guard90024_0b0_theResult___fst_exp98252_0_ETC__q123 = - _theResult___fst_exp__h698252; + CASE_guard90021_0b0_theResult___fst_exp98249_0_ETC__q123 = + _theResult___fst_exp__h698249; 2'b10: - CASE_guard90024_0b0_theResult___fst_exp98252_0_ETC__q123 = - out_exp__h698771; + CASE_guard90021_0b0_theResult___fst_exp98249_0_ETC__q123 = + out_exp__h698768; 2'b11: - CASE_guard90024_0b0_theResult___fst_exp98252_0_ETC__q123 = - _theResult___exp__h698768; + CASE_guard90021_0b0_theResult___fst_exp98249_0_ETC__q123 = + _theResult___exp__h698765; endcase end - always@(guard__h690024 or - _theResult___fst_exp__h698252 or _theResult___exp__h698768) + always@(guard__h690021 or + _theResult___fst_exp__h698249 or _theResult___exp__h698765) begin - case (guard__h690024) + case (guard__h690021) 2'b0: - CASE_guard90024_0b0_theResult___fst_exp98252_0_ETC__q124 = - _theResult___fst_exp__h698252; + CASE_guard90021_0b0_theResult___fst_exp98249_0_ETC__q124 = + _theResult___fst_exp__h698249; 2'b01, 2'b10, 2'b11: - CASE_guard90024_0b0_theResult___fst_exp98252_0_ETC__q124 = - _theResult___exp__h698768; + CASE_guard90021_0b0_theResult___fst_exp98249_0_ETC__q124 = + _theResult___exp__h698765; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard90024_0b0_theResult___fst_exp98252_0_ETC__q123 or - CASE_guard90024_0b0_theResult___fst_exp98252_0_ETC__q124 or + CASE_guard90021_0b0_theResult___fst_exp98249_0_ETC__q123 or + CASE_guard90021_0b0_theResult___fst_exp98249_0_ETC__q124 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11865 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11867 or - _theResult___fst_exp__h698252) + _theResult___fst_exp__h698249) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h698846 = - CASE_guard90024_0b0_theResult___fst_exp98252_0_ETC__q123; + _theResult___fst_exp__h698843 = + CASE_guard90021_0b0_theResult___fst_exp98249_0_ETC__q123; 3'd1: - _theResult___fst_exp__h698846 = - CASE_guard90024_0b0_theResult___fst_exp98252_0_ETC__q124; + _theResult___fst_exp__h698843 = + CASE_guard90021_0b0_theResult___fst_exp98249_0_ETC__q124; 3'd2: - _theResult___fst_exp__h698846 = + _theResult___fst_exp__h698843 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11865; 3'd3: - _theResult___fst_exp__h698846 = + _theResult___fst_exp__h698843 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11867; - 3'd4: _theResult___fst_exp__h698846 = _theResult___fst_exp__h698252; - default: _theResult___fst_exp__h698846 = 8'd0; + 3'd4: _theResult___fst_exp__h698843 = _theResult___fst_exp__h698249; + default: _theResult___fst_exp__h698843 = 8'd0; endcase end - always@(guard__h698860 or - _theResult___fst_exp__h706937 or - out_exp__h707407 or _theResult___exp__h707404) + always@(guard__h698857 or + _theResult___fst_exp__h706934 or + out_exp__h707404 or _theResult___exp__h707401) begin - case (guard__h698860) + case (guard__h698857) 2'b0, 2'b01: - CASE_guard98860_0b0_theResult___fst_exp06937_0_ETC__q128 = - _theResult___fst_exp__h706937; + CASE_guard98857_0b0_theResult___fst_exp06934_0_ETC__q128 = + _theResult___fst_exp__h706934; 2'b10: - CASE_guard98860_0b0_theResult___fst_exp06937_0_ETC__q128 = - out_exp__h707407; + CASE_guard98857_0b0_theResult___fst_exp06934_0_ETC__q128 = + out_exp__h707404; 2'b11: - CASE_guard98860_0b0_theResult___fst_exp06937_0_ETC__q128 = - _theResult___exp__h707404; + CASE_guard98857_0b0_theResult___fst_exp06934_0_ETC__q128 = + _theResult___exp__h707401; endcase end - always@(guard__h698860 or - _theResult___fst_exp__h706937 or _theResult___exp__h707404) + always@(guard__h698857 or + _theResult___fst_exp__h706934 or _theResult___exp__h707401) begin - case (guard__h698860) + case (guard__h698857) 2'b0: - CASE_guard98860_0b0_theResult___fst_exp06937_0_ETC__q129 = - _theResult___fst_exp__h706937; + CASE_guard98857_0b0_theResult___fst_exp06934_0_ETC__q129 = + _theResult___fst_exp__h706934; 2'b01, 2'b10, 2'b11: - CASE_guard98860_0b0_theResult___fst_exp06937_0_ETC__q129 = - _theResult___exp__h707404; + CASE_guard98857_0b0_theResult___fst_exp06934_0_ETC__q129 = + _theResult___exp__h707401; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard98860_0b0_theResult___fst_exp06937_0_ETC__q128 or - CASE_guard98860_0b0_theResult___fst_exp06937_0_ETC__q129 or + CASE_guard98857_0b0_theResult___fst_exp06934_0_ETC__q128 or + CASE_guard98857_0b0_theResult___fst_exp06934_0_ETC__q129 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11934 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11936 or - _theResult___fst_exp__h706937) + _theResult___fst_exp__h706934) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h707482 = - CASE_guard98860_0b0_theResult___fst_exp06937_0_ETC__q128; + _theResult___fst_exp__h707479 = + CASE_guard98857_0b0_theResult___fst_exp06934_0_ETC__q128; 3'd1: - _theResult___fst_exp__h707482 = - CASE_guard98860_0b0_theResult___fst_exp06937_0_ETC__q129; + _theResult___fst_exp__h707479 = + CASE_guard98857_0b0_theResult___fst_exp06934_0_ETC__q129; 3'd2: - _theResult___fst_exp__h707482 = + _theResult___fst_exp__h707479 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11934; 3'd3: - _theResult___fst_exp__h707482 = + _theResult___fst_exp__h707479 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11936; - 3'd4: _theResult___fst_exp__h707482 = _theResult___fst_exp__h706937; - default: _theResult___fst_exp__h707482 = 8'd0; + 3'd4: _theResult___fst_exp__h707479 = _theResult___fst_exp__h706934; + default: _theResult___fst_exp__h707479 = 8'd0; endcase end - always@(guard__h681094 or - _theResult___snd__h689093 or - out_sfd__h689588 or _theResult___sfd__h689585) + always@(guard__h681091 or + _theResult___snd__h689090 or + out_sfd__h689585 or _theResult___sfd__h689582) begin - case (guard__h681094) + case (guard__h681091) 2'b0, 2'b01: - CASE_guard81094_0b0_theResult___snd89093_BITS__ETC__q130 = - _theResult___snd__h689093[56:34]; + CASE_guard81091_0b0_theResult___snd89090_BITS__ETC__q130 = + _theResult___snd__h689090[56:34]; 2'b10: - CASE_guard81094_0b0_theResult___snd89093_BITS__ETC__q130 = - out_sfd__h689588; + CASE_guard81091_0b0_theResult___snd89090_BITS__ETC__q130 = + out_sfd__h689585; 2'b11: - CASE_guard81094_0b0_theResult___snd89093_BITS__ETC__q130 = - _theResult___sfd__h689585; + CASE_guard81091_0b0_theResult___snd89090_BITS__ETC__q130 = + _theResult___sfd__h689582; endcase end - always@(guard__h681094 or - _theResult___snd__h689093 or _theResult___sfd__h689585) + always@(guard__h681091 or + _theResult___snd__h689090 or _theResult___sfd__h689582) begin - case (guard__h681094) + case (guard__h681091) 2'b0: - CASE_guard81094_0b0_theResult___snd89093_BITS__ETC__q131 = - _theResult___snd__h689093[56:34]; + CASE_guard81091_0b0_theResult___snd89090_BITS__ETC__q131 = + _theResult___snd__h689090[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard81094_0b0_theResult___snd89093_BITS__ETC__q131 = - _theResult___sfd__h689585; + CASE_guard81091_0b0_theResult___snd89090_BITS__ETC__q131 = + _theResult___sfd__h689582; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard81094_0b0_theResult___snd89093_BITS__ETC__q130 or - CASE_guard81094_0b0_theResult___snd89093_BITS__ETC__q131 or + CASE_guard81091_0b0_theResult___snd89090_BITS__ETC__q130 or + CASE_guard81091_0b0_theResult___snd89090_BITS__ETC__q131 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11984 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11986 or - _theResult___snd__h689093) + _theResult___snd__h689090) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h689663 = - CASE_guard81094_0b0_theResult___snd89093_BITS__ETC__q130; + _theResult___fst_sfd__h689660 = + CASE_guard81091_0b0_theResult___snd89090_BITS__ETC__q130; 3'd1: - _theResult___fst_sfd__h689663 = - CASE_guard81094_0b0_theResult___snd89093_BITS__ETC__q131; + _theResult___fst_sfd__h689660 = + CASE_guard81091_0b0_theResult___snd89090_BITS__ETC__q131; 3'd2: - _theResult___fst_sfd__h689663 = + _theResult___fst_sfd__h689660 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11984; 3'd3: - _theResult___fst_sfd__h689663 = + _theResult___fst_sfd__h689660 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11986; - 3'd4: _theResult___fst_sfd__h689663 = _theResult___snd__h689093[56:34]; - default: _theResult___fst_sfd__h689663 = 23'd0; + 3'd4: _theResult___fst_sfd__h689660 = _theResult___snd__h689090[56:34]; + default: _theResult___fst_sfd__h689660 = 23'd0; endcase end - always@(guard__h672387 or - sfdin__h680480 or out_sfd__h681006 or _theResult___sfd__h681003) + always@(guard__h672384 or + sfdin__h680477 or out_sfd__h681003 or _theResult___sfd__h681000) begin - case (guard__h672387) + case (guard__h672384) 2'b0, 2'b01: - CASE_guard72387_0b0_sfdin80480_BITS_56_TO_34_0_ETC__q132 = - sfdin__h680480[56:34]; + CASE_guard72384_0b0_sfdin80477_BITS_56_TO_34_0_ETC__q132 = + sfdin__h680477[56:34]; 2'b10: - CASE_guard72387_0b0_sfdin80480_BITS_56_TO_34_0_ETC__q132 = - out_sfd__h681006; + CASE_guard72384_0b0_sfdin80477_BITS_56_TO_34_0_ETC__q132 = + out_sfd__h681003; 2'b11: - CASE_guard72387_0b0_sfdin80480_BITS_56_TO_34_0_ETC__q132 = - _theResult___sfd__h681003; + CASE_guard72384_0b0_sfdin80477_BITS_56_TO_34_0_ETC__q132 = + _theResult___sfd__h681000; endcase end - always@(guard__h672387 or sfdin__h680480 or _theResult___sfd__h681003) + always@(guard__h672384 or sfdin__h680477 or _theResult___sfd__h681000) begin - case (guard__h672387) + case (guard__h672384) 2'b0: - CASE_guard72387_0b0_sfdin80480_BITS_56_TO_34_0_ETC__q133 = - sfdin__h680480[56:34]; + CASE_guard72384_0b0_sfdin80477_BITS_56_TO_34_0_ETC__q133 = + sfdin__h680477[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard72387_0b0_sfdin80480_BITS_56_TO_34_0_ETC__q133 = - _theResult___sfd__h681003; + CASE_guard72384_0b0_sfdin80477_BITS_56_TO_34_0_ETC__q133 = + _theResult___sfd__h681000; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard72387_0b0_sfdin80480_BITS_56_TO_34_0_ETC__q132 or - CASE_guard72387_0b0_sfdin80480_BITS_56_TO_34_0_ETC__q133 or + CASE_guard72384_0b0_sfdin80477_BITS_56_TO_34_0_ETC__q132 or + CASE_guard72384_0b0_sfdin80477_BITS_56_TO_34_0_ETC__q133 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11965 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11967 or - sfdin__h680480) + sfdin__h680477) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h681081 = - CASE_guard72387_0b0_sfdin80480_BITS_56_TO_34_0_ETC__q132; + _theResult___fst_sfd__h681078 = + CASE_guard72384_0b0_sfdin80477_BITS_56_TO_34_0_ETC__q132; 3'd1: - _theResult___fst_sfd__h681081 = - CASE_guard72387_0b0_sfdin80480_BITS_56_TO_34_0_ETC__q133; + _theResult___fst_sfd__h681078 = + CASE_guard72384_0b0_sfdin80477_BITS_56_TO_34_0_ETC__q133; 3'd2: - _theResult___fst_sfd__h681081 = + _theResult___fst_sfd__h681078 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11965; 3'd3: - _theResult___fst_sfd__h681081 = + _theResult___fst_sfd__h681078 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11967; - 3'd4: _theResult___fst_sfd__h681081 = sfdin__h680480[56:34]; - default: _theResult___fst_sfd__h681081 = 23'd0; + 3'd4: _theResult___fst_sfd__h681078 = sfdin__h680477[56:34]; + default: _theResult___fst_sfd__h681078 = 23'd0; endcase end - always@(guard__h690024 or - sfdin__h698246 or out_sfd__h698772 or _theResult___sfd__h698769) + always@(guard__h690021 or + sfdin__h698243 or out_sfd__h698769 or _theResult___sfd__h698766) begin - case (guard__h690024) + case (guard__h690021) 2'b0, 2'b01: - CASE_guard90024_0b0_sfdin98246_BITS_56_TO_34_0_ETC__q134 = - sfdin__h698246[56:34]; + CASE_guard90021_0b0_sfdin98243_BITS_56_TO_34_0_ETC__q134 = + sfdin__h698243[56:34]; 2'b10: - CASE_guard90024_0b0_sfdin98246_BITS_56_TO_34_0_ETC__q134 = - out_sfd__h698772; + CASE_guard90021_0b0_sfdin98243_BITS_56_TO_34_0_ETC__q134 = + out_sfd__h698769; 2'b11: - CASE_guard90024_0b0_sfdin98246_BITS_56_TO_34_0_ETC__q134 = - _theResult___sfd__h698769; + CASE_guard90021_0b0_sfdin98243_BITS_56_TO_34_0_ETC__q134 = + _theResult___sfd__h698766; endcase end - always@(guard__h690024 or sfdin__h698246 or _theResult___sfd__h698769) + always@(guard__h690021 or sfdin__h698243 or _theResult___sfd__h698766) begin - case (guard__h690024) + case (guard__h690021) 2'b0: - CASE_guard90024_0b0_sfdin98246_BITS_56_TO_34_0_ETC__q135 = - sfdin__h698246[56:34]; + CASE_guard90021_0b0_sfdin98243_BITS_56_TO_34_0_ETC__q135 = + sfdin__h698243[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard90024_0b0_sfdin98246_BITS_56_TO_34_0_ETC__q135 = - _theResult___sfd__h698769; + CASE_guard90021_0b0_sfdin98243_BITS_56_TO_34_0_ETC__q135 = + _theResult___sfd__h698766; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard90024_0b0_sfdin98246_BITS_56_TO_34_0_ETC__q134 or - CASE_guard90024_0b0_sfdin98246_BITS_56_TO_34_0_ETC__q135 or + CASE_guard90021_0b0_sfdin98243_BITS_56_TO_34_0_ETC__q134 or + CASE_guard90021_0b0_sfdin98243_BITS_56_TO_34_0_ETC__q135 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d12011 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d12013 or - sfdin__h698246) + sfdin__h698243) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h698847 = - CASE_guard90024_0b0_sfdin98246_BITS_56_TO_34_0_ETC__q134; + _theResult___fst_sfd__h698844 = + CASE_guard90021_0b0_sfdin98243_BITS_56_TO_34_0_ETC__q134; 3'd1: - _theResult___fst_sfd__h698847 = - CASE_guard90024_0b0_sfdin98246_BITS_56_TO_34_0_ETC__q135; + _theResult___fst_sfd__h698844 = + CASE_guard90021_0b0_sfdin98243_BITS_56_TO_34_0_ETC__q135; 3'd2: - _theResult___fst_sfd__h698847 = + _theResult___fst_sfd__h698844 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d12011; 3'd3: - _theResult___fst_sfd__h698847 = + _theResult___fst_sfd__h698844 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d12013; - 3'd4: _theResult___fst_sfd__h698847 = sfdin__h698246[56:34]; - default: _theResult___fst_sfd__h698847 = 23'd0; + 3'd4: _theResult___fst_sfd__h698844 = sfdin__h698243[56:34]; + default: _theResult___fst_sfd__h698844 = 23'd0; endcase end - always@(guard__h698860 or - _theResult___snd__h706883 or - out_sfd__h707408 or _theResult___sfd__h707405) - begin - case (guard__h698860) - 2'b0, 2'b01: - CASE_guard98860_0b0_theResult___snd06883_BITS__ETC__q136 = - _theResult___snd__h706883[56:34]; - 2'b10: - CASE_guard98860_0b0_theResult___snd06883_BITS__ETC__q136 = - out_sfd__h707408; - 2'b11: - CASE_guard98860_0b0_theResult___snd06883_BITS__ETC__q136 = - _theResult___sfd__h707405; - endcase - end - always@(guard__h698860 or - _theResult___snd__h706883 or _theResult___sfd__h707405) - begin - case (guard__h698860) - 2'b0: - CASE_guard98860_0b0_theResult___snd06883_BITS__ETC__q137 = - _theResult___snd__h706883[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard98860_0b0_theResult___snd06883_BITS__ETC__q137 = - _theResult___sfd__h707405; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard98860_0b0_theResult___snd06883_BITS__ETC__q136 or - CASE_guard98860_0b0_theResult___snd06883_BITS__ETC__q137 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d12030 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d12032 or - _theResult___snd__h706883) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0: - _theResult___fst_sfd__h707483 = - CASE_guard98860_0b0_theResult___snd06883_BITS__ETC__q136; - 3'd1: - _theResult___fst_sfd__h707483 = - CASE_guard98860_0b0_theResult___snd06883_BITS__ETC__q137; - 3'd2: - _theResult___fst_sfd__h707483 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d12030; - 3'd3: - _theResult___fst_sfd__h707483 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d12032; - 3'd4: _theResult___fst_sfd__h707483 = _theResult___snd__h706883[56:34]; - default: _theResult___fst_sfd__h707483 = 23'd0; - endcase - end - always@(guard__h672387 or + always@(guard__h672384 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h672387) + case (guard__h672384) 2'b0, 2'b01, 2'b10: - CASE_guard72387_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q138 = + CASE_guard72384_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q136 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard72387_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q138 = - guard__h672387 == 2'b11 && + CASE_guard72384_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q136 = + guard__h672384 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard72387_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q138 or - guard__h672387) + CASE_guard72384_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q136 or + guard__h672384) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12118 = - CASE_guard72387_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q138; + CASE_guard72384_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q136; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12118 = - (guard__h672387 == 2'b0) ? + (guard__h672384 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h672387 == 2'b01 || guard__h672387 == 2'b10 || - guard__h672387 == 2'b11) && + (guard__h672384 == 2'b01 || guard__h672384 == 2'b10 || + guard__h672384 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12118 = @@ -41930,34 +41851,86 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h672387 or + always@(guard__h698857 or + _theResult___snd__h706880 or + out_sfd__h707405 or _theResult___sfd__h707402) + begin + case (guard__h698857) + 2'b0, 2'b01: + CASE_guard98857_0b0_theResult___snd06880_BITS__ETC__q137 = + _theResult___snd__h706880[56:34]; + 2'b10: + CASE_guard98857_0b0_theResult___snd06880_BITS__ETC__q137 = + out_sfd__h707405; + 2'b11: + CASE_guard98857_0b0_theResult___snd06880_BITS__ETC__q137 = + _theResult___sfd__h707402; + endcase + end + always@(guard__h698857 or + _theResult___snd__h706880 or _theResult___sfd__h707402) + begin + case (guard__h698857) + 2'b0: + CASE_guard98857_0b0_theResult___snd06880_BITS__ETC__q138 = + _theResult___snd__h706880[56:34]; + 2'b01, 2'b10, 2'b11: + CASE_guard98857_0b0_theResult___snd06880_BITS__ETC__q138 = + _theResult___sfd__h707402; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or + CASE_guard98857_0b0_theResult___snd06880_BITS__ETC__q137 or + CASE_guard98857_0b0_theResult___snd06880_BITS__ETC__q138 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d12030 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d12032 or + _theResult___snd__h706880) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) + 3'd0: + _theResult___fst_sfd__h707480 = + CASE_guard98857_0b0_theResult___snd06880_BITS__ETC__q137; + 3'd1: + _theResult___fst_sfd__h707480 = + CASE_guard98857_0b0_theResult___snd06880_BITS__ETC__q138; + 3'd2: + _theResult___fst_sfd__h707480 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d12030; + 3'd3: + _theResult___fst_sfd__h707480 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d12032; + 3'd4: _theResult___fst_sfd__h707480 = _theResult___snd__h706880[56:34]; + default: _theResult___fst_sfd__h707480 = 23'd0; + endcase + end + always@(guard__h672384 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h672387) + case (guard__h672384) 2'b0, 2'b01, 2'b10: - CASE_guard72387_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q139 = + CASE_guard72384_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q139 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard72387_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q139 = - guard__h672387 != 2'b11 || + CASE_guard72384_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q139 = + guard__h672384 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard72387_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q139 or - guard__h672387) + CASE_guard72384_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q139 or + guard__h672384) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12062 = - CASE_guard72387_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q139; + CASE_guard72384_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q139; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12062 = - (guard__h672387 == 2'b0) ? + (guard__h672384 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h672387 != 2'b01 && guard__h672387 != 2'b10 && - guard__h672387 != 2'b11 || + guard__h672384 != 2'b01 && guard__h672384 != 2'b10 && + guard__h672384 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12062 = @@ -41968,34 +41941,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h681094 or + always@(guard__h681091 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h681094) + case (guard__h681091) 2'b0, 2'b01, 2'b10: - CASE_guard81094_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q140 = + CASE_guard81091_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q140 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard81094_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q140 = - guard__h681094 == 2'b11 && + CASE_guard81091_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q140 = + guard__h681091 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard81094_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q140 or - guard__h681094) + CASE_guard81091_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q140 or + guard__h681091) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12125 = - CASE_guard81094_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q140; + CASE_guard81091_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q140; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12125 = - (guard__h681094 == 2'b0) ? + (guard__h681091 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h681094 == 2'b01 || guard__h681094 == 2'b10 || - guard__h681094 == 2'b11) && + (guard__h681091 == 2'b01 || guard__h681091 == 2'b10 || + guard__h681091 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12125 = @@ -42006,34 +41979,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h681094 or + always@(guard__h681091 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h681094) + case (guard__h681091) 2'b0, 2'b01, 2'b10: - CASE_guard81094_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q141 = + CASE_guard81091_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q141 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard81094_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q141 = - guard__h681094 != 2'b11 || + CASE_guard81091_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q141 = + guard__h681091 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard81094_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q141 or - guard__h681094) + CASE_guard81091_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q141 or + guard__h681091) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12075 = - CASE_guard81094_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q141; + CASE_guard81091_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q141; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12075 = - (guard__h681094 == 2'b0) ? + (guard__h681091 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h681094 != 2'b01 && guard__h681094 != 2'b10 && - guard__h681094 != 2'b11 || + guard__h681091 != 2'b01 && guard__h681091 != 2'b10 && + guard__h681091 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12075 = @@ -42044,34 +42017,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h690024 or + always@(guard__h690021 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h690024) + case (guard__h690021) 2'b0, 2'b01, 2'b10: - CASE_guard90024_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q142 = + CASE_guard90021_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q142 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard90024_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q142 = - guard__h690024 == 2'b11 && + CASE_guard90021_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q142 = + guard__h690021 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard90024_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q142 or - guard__h690024) + CASE_guard90021_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q142 or + guard__h690021) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12135 = - CASE_guard90024_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q142; + CASE_guard90021_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q142; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12135 = - (guard__h690024 == 2'b0) ? + (guard__h690021 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h690024 == 2'b01 || guard__h690024 == 2'b10 || - guard__h690024 == 2'b11) && + (guard__h690021 == 2'b01 || guard__h690021 == 2'b10 || + guard__h690021 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12135 = @@ -42082,34 +42055,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h690024 or + always@(guard__h690021 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h690024) + case (guard__h690021) 2'b0, 2'b01, 2'b10: - CASE_guard90024_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q143 = + CASE_guard90021_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q143 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard90024_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q143 = - guard__h690024 != 2'b11 || + CASE_guard90021_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q143 = + guard__h690021 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard90024_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q143 or - guard__h690024) + CASE_guard90021_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q143 or + guard__h690021) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12092 = - CASE_guard90024_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q143; + CASE_guard90021_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q143; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12092 = - (guard__h690024 == 2'b0) ? + (guard__h690021 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h690024 != 2'b01 && guard__h690024 != 2'b10 && - guard__h690024 != 2'b11 || + guard__h690021 != 2'b01 && guard__h690021 != 2'b10 && + guard__h690021 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12092 = @@ -42120,34 +42093,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h698860 or + always@(guard__h698857 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h698860) + case (guard__h698857) 2'b0, 2'b01, 2'b10: - CASE_guard98860_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q144 = + CASE_guard98857_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q144 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard98860_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q144 = - guard__h698860 == 2'b11 && + CASE_guard98857_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q144 = + guard__h698857 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard98860_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q144 or - guard__h698860) + CASE_guard98857_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q144 or + guard__h698857) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12142 = - CASE_guard98860_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q144; + CASE_guard98857_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q144; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12142 = - (guard__h698860 == 2'b0) ? + (guard__h698857 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h698860 == 2'b01 || guard__h698860 == 2'b10 || - guard__h698860 == 2'b11) && + (guard__h698857 == 2'b01 || guard__h698857 == 2'b10 || + guard__h698857 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12142 = @@ -42158,34 +42131,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h698860 or + always@(guard__h698857 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h698860) + case (guard__h698857) 2'b0, 2'b01, 2'b10: - CASE_guard98860_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q145 = + CASE_guard98857_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q145 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard98860_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q145 = - guard__h698860 != 2'b11 || + CASE_guard98857_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q145 = + guard__h698857 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard98860_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q145 or - guard__h698860) + CASE_guard98857_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q145 or + guard__h698857) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12105 = - CASE_guard98860_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q145; + CASE_guard98857_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q145; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12105 = - (guard__h698860 == 2'b0) ? + (guard__h698857 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h698860 != 2'b01 && guard__h698860 != 2'b10 && - guard__h698860 != 2'b11 || + guard__h698857 != 2'b01 && guard__h698857 != 2'b10 && + guard__h698857 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12105 = @@ -42242,28 +42215,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_request_put; endcase end - always@(guard__h731259 or - _theResult___fst_exp__h739220 or _theResult___exp__h739875) + always@(guard__h731255 or + _theResult___fst_exp__h739216 or _theResult___exp__h739871) begin - case (guard__h731259) + case (guard__h731255) 2'b0: - CASE_guard31259_0b0_theResult___fst_exp39220_0_ETC__q155 = - _theResult___fst_exp__h739220; + CASE_guard31255_0b0_theResult___fst_exp39216_0_ETC__q155 = + _theResult___fst_exp__h739216; 2'b01, 2'b10, 2'b11: - CASE_guard31259_0b0_theResult___fst_exp39220_0_ETC__q155 = - _theResult___exp__h739875; + CASE_guard31255_0b0_theResult___fst_exp39216_0_ETC__q155 = + _theResult___exp__h739871; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h739220 or + _theResult___fst_exp__h739216 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13272 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13270 or - CASE_guard31259_0b0_theResult___fst_exp39220_0_ETC__q155) + CASE_guard31255_0b0_theResult___fst_exp39216_0_ETC__q155) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d13276 = - _theResult___fst_exp__h739220; + _theResult___fst_exp__h739216; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d13276 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13272; @@ -42272,44 +42245,44 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13270; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d13276 = - CASE_guard31259_0b0_theResult___fst_exp39220_0_ETC__q155; + CASE_guard31255_0b0_theResult___fst_exp39216_0_ETC__q155; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d13276 = 11'd0; endcase end - always@(guard__h731259 or - _theResult___fst_exp__h739220 or - out_exp__h739878 or _theResult___exp__h739875) + always@(guard__h731255 or + _theResult___fst_exp__h739216 or + out_exp__h739874 or _theResult___exp__h739871) begin - case (guard__h731259) + case (guard__h731255) 2'b0, 2'b01: - CASE_guard31259_0b0_theResult___fst_exp39220_0_ETC__q156 = - _theResult___fst_exp__h739220; + CASE_guard31255_0b0_theResult___fst_exp39216_0_ETC__q156 = + _theResult___fst_exp__h739216; 2'b10: - CASE_guard31259_0b0_theResult___fst_exp39220_0_ETC__q156 = - out_exp__h739878; + CASE_guard31255_0b0_theResult___fst_exp39216_0_ETC__q156 = + out_exp__h739874; 2'b11: - CASE_guard31259_0b0_theResult___fst_exp39220_0_ETC__q156 = - _theResult___exp__h739875; + CASE_guard31255_0b0_theResult___fst_exp39216_0_ETC__q156 = + _theResult___exp__h739871; endcase end - always@(guard__h731259 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h731255 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h731259) + case (guard__h731255) 2'b0, 2'b01, 2'b10: - CASE_guard31259_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q157 = + CASE_guard31255_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q157 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard31259_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q157 = - guard__h731259 == 2'b11 && + CASE_guard31255_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q157 = + guard__h731255 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h731259) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h731255) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -42319,12 +42292,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q158 = - (guard__h731259 == 2'b0) ? + (guard__h731255 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h731259 == 2'b01 || guard__h731259 == 2'b10 || - guard__h731259 == 2'b11) && + (guard__h731255 == 2'b01 || guard__h731255 == 2'b10 || + guard__h731255 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; @@ -42335,23 +42308,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(guard__h740571 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h740567 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h740571) + case (guard__h740567) 2'b0, 2'b01, 2'b10: - CASE_guard40571_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q159 = + CASE_guard40567_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q159 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard40571_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q159 = - guard__h740571 == 2'b11 && + CASE_guard40567_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q159 = + guard__h740567 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h740571) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h740567) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -42361,12 +42334,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q160 = - (guard__h740571 == 2'b0) ? + (guard__h740567 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h740571 == 2'b01 || guard__h740571 == 2'b10 || - guard__h740571 == 2'b11) && + (guard__h740567 == 2'b01 || guard__h740567 == 2'b10 || + guard__h740567 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; @@ -42377,23 +42350,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(guard__h749640 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h749636 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h749640) + case (guard__h749636) 2'b0, 2'b01, 2'b10: - CASE_guard49640_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q161 = + CASE_guard49636_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q161 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard49640_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q161 = - guard__h749640 == 2'b11 && + CASE_guard49636_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q161 = + guard__h749636 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h749640) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h749636) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -42403,12 +42376,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q162 = - (guard__h749640 == 2'b0) ? + (guard__h749636 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h749640 == 2'b01 || guard__h749640 == 2'b10 || - guard__h749640 == 2'b11) && + (guard__h749636 == 2'b01 || guard__h749636 == 2'b10 || + guard__h749636 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; @@ -42419,28 +42392,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(guard__h809416 or - _theResult___fst_exp__h817377 or _theResult___exp__h818032) + always@(guard__h809412 or + _theResult___fst_exp__h817373 or _theResult___exp__h818028) begin - case (guard__h809416) + case (guard__h809412) 2'b0: - CASE_guard09416_0b0_theResult___fst_exp17377_0_ETC__q172 = - _theResult___fst_exp__h817377; + CASE_guard09412_0b0_theResult___fst_exp17373_0_ETC__q172 = + _theResult___fst_exp__h817373; 2'b01, 2'b10, 2'b11: - CASE_guard09416_0b0_theResult___fst_exp17377_0_ETC__q172 = - _theResult___exp__h818032; + CASE_guard09412_0b0_theResult___fst_exp17373_0_ETC__q172 = + _theResult___exp__h818028; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h817377 or + _theResult___fst_exp__h817373 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13987 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13985 or - CASE_guard09416_0b0_theResult___fst_exp17377_0_ETC__q172) + CASE_guard09412_0b0_theResult___fst_exp17373_0_ETC__q172) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d13991 = - _theResult___fst_exp__h817377; + _theResult___fst_exp__h817373; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d13991 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13987; @@ -42449,42 +42422,42 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13985; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d13991 = - CASE_guard09416_0b0_theResult___fst_exp17377_0_ETC__q172; + CASE_guard09412_0b0_theResult___fst_exp17373_0_ETC__q172; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d13991 = 11'd0; endcase end - always@(guard__h809416 or - _theResult___fst_exp__h817377 or - out_exp__h818035 or _theResult___exp__h818032) + always@(guard__h809412 or + _theResult___fst_exp__h817373 or + out_exp__h818031 or _theResult___exp__h818028) begin - case (guard__h809416) + case (guard__h809412) 2'b0, 2'b01: - CASE_guard09416_0b0_theResult___fst_exp17377_0_ETC__q173 = - _theResult___fst_exp__h817377; + CASE_guard09412_0b0_theResult___fst_exp17373_0_ETC__q173 = + _theResult___fst_exp__h817373; 2'b10: - CASE_guard09416_0b0_theResult___fst_exp17377_0_ETC__q173 = - out_exp__h818035; + CASE_guard09412_0b0_theResult___fst_exp17373_0_ETC__q173 = + out_exp__h818031; 2'b11: - CASE_guard09416_0b0_theResult___fst_exp17377_0_ETC__q173 = - _theResult___exp__h818032; + CASE_guard09412_0b0_theResult___fst_exp17373_0_ETC__q173 = + _theResult___exp__h818028; endcase end - always@(guard__h818728 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h809412 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h818728) + case (guard__h809412) 2'b0, 2'b01, 2'b10: - CASE_guard18728_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q174 = + CASE_guard09412_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q174 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard18728_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q174 = - guard__h818728 == 2'b11 && + CASE_guard09412_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q174 = + guard__h809412 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h818728) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h809412) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -42493,12 +42466,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q175 = - (guard__h818728 == 2'b0) ? + (guard__h809412 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h818728 == 2'b01 || guard__h818728 == 2'b10 || - guard__h818728 == 2'b11) && + (guard__h809412 == 2'b01 || guard__h809412 == 2'b10 || + guard__h809412 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -42509,21 +42482,21 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h809416 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h818724 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h809416) + case (guard__h818724) 2'b0, 2'b01, 2'b10: - CASE_guard09416_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q176 = + CASE_guard18724_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q176 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard09416_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q176 = - guard__h809416 == 2'b11 && + CASE_guard18724_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q176 = + guard__h818724 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h809416) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h818724) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -42532,12 +42505,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q177 = - (guard__h809416 == 2'b0) ? + (guard__h818724 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h809416 == 2'b01 || guard__h809416 == 2'b10 || - guard__h809416 == 2'b11) && + (guard__h818724 == 2'b01 || guard__h818724 == 2'b10 || + guard__h818724 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -42548,21 +42521,21 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h827797 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h827793 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h827797) + case (guard__h827793) 2'b0, 2'b01, 2'b10: - CASE_guard27797_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q178 = + CASE_guard27793_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q178 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard27797_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q178 = - guard__h827797 == 2'b11 && + CASE_guard27793_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q178 = + guard__h827793 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h827797) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h827793) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -42571,12 +42544,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q179 = - (guard__h827797 == 2'b0) ? + (guard__h827793 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h827797 == 2'b01 || guard__h827797 == 2'b10 || - guard__h827797 == 2'b11) && + (guard__h827793 == 2'b01 || guard__h827793 == 2'b10 || + guard__h827793 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -42587,21 +42560,21 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h818728 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h818724 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h818728) + case (guard__h818724) 2'b0, 2'b01, 2'b10: - CASE_guard18728_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q180 = + CASE_guard18724_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q180 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard18728_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q180 = - guard__h818728 != 2'b11 || + CASE_guard18724_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q180 = + guard__h818724 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h818728) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h818724) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -42610,12 +42583,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q181 = - (guard__h818728 == 2'b0) ? + (guard__h818724 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h818728 != 2'b01 && guard__h818728 != 2'b10 && - guard__h818728 != 2'b11 || + guard__h818724 != 2'b01 && guard__h818724 != 2'b10 && + guard__h818724 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -42626,21 +42599,21 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h827797 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h827793 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h827797) + case (guard__h827793) 2'b0, 2'b01, 2'b10: - CASE_guard27797_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q182 = + CASE_guard27793_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q182 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard27797_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q182 = - guard__h827797 != 2'b11 || + CASE_guard27793_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q182 = + guard__h827793 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h827797) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h827793) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -42649,12 +42622,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q183 = - (guard__h827797 == 2'b0) ? + (guard__h827793 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h827797 != 2'b01 && guard__h827797 != 2'b10 && - guard__h827797 != 2'b11 || + guard__h827793 != 2'b01 && guard__h827793 != 2'b10 && + guard__h827793 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -42665,21 +42638,21 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h809416 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h809412 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h809416) + case (guard__h809412) 2'b0, 2'b01, 2'b10: - CASE_guard09416_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q184 = + CASE_guard09412_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q184 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard09416_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q184 = - guard__h809416 != 2'b11 || + CASE_guard09412_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q184 = + guard__h809412 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h809416) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h809412) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -42688,12 +42661,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q185 = - (guard__h809416 == 2'b0) ? + (guard__h809412 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h809416 != 2'b01 && guard__h809416 != 2'b10 && - guard__h809416 != 2'b11 || + guard__h809412 != 2'b01 && guard__h809412 != 2'b10 && + guard__h809412 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -42704,28 +42677,28 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h770112 or - _theResult___fst_exp__h778073 or _theResult___exp__h778728) + always@(guard__h770108 or + _theResult___fst_exp__h778069 or _theResult___exp__h778724) begin - case (guard__h770112) + case (guard__h770108) 2'b0: - CASE_guard70112_0b0_theResult___fst_exp78073_0_ETC__q195 = - _theResult___fst_exp__h778073; + CASE_guard70108_0b0_theResult___fst_exp78069_0_ETC__q195 = + _theResult___fst_exp__h778069; 2'b01, 2'b10, 2'b11: - CASE_guard70112_0b0_theResult___fst_exp78073_0_ETC__q195 = - _theResult___exp__h778728; + CASE_guard70108_0b0_theResult___fst_exp78069_0_ETC__q195 = + _theResult___exp__h778724; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h778073 or + _theResult___fst_exp__h778069 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14757 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14755 or - CASE_guard70112_0b0_theResult___fst_exp78073_0_ETC__q195) + CASE_guard70108_0b0_theResult___fst_exp78069_0_ETC__q195) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14761 = - _theResult___fst_exp__h778073; + _theResult___fst_exp__h778069; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14761 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14757; @@ -42734,100 +42707,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14755; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14761 = - CASE_guard70112_0b0_theResult___fst_exp78073_0_ETC__q195; + CASE_guard70108_0b0_theResult___fst_exp78069_0_ETC__q195; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14761 = 11'd0; endcase end - always@(guard__h770112 or - _theResult___fst_exp__h778073 or - out_exp__h778731 or _theResult___exp__h778728) + always@(guard__h770108 or + _theResult___fst_exp__h778069 or + out_exp__h778727 or _theResult___exp__h778724) begin - case (guard__h770112) + case (guard__h770108) 2'b0, 2'b01: - CASE_guard70112_0b0_theResult___fst_exp78073_0_ETC__q196 = - _theResult___fst_exp__h778073; + CASE_guard70108_0b0_theResult___fst_exp78069_0_ETC__q196 = + _theResult___fst_exp__h778069; 2'b10: - CASE_guard70112_0b0_theResult___fst_exp78073_0_ETC__q196 = - out_exp__h778731; + CASE_guard70108_0b0_theResult___fst_exp78069_0_ETC__q196 = + out_exp__h778727; 2'b11: - CASE_guard70112_0b0_theResult___fst_exp78073_0_ETC__q196 = - _theResult___exp__h778728; + CASE_guard70108_0b0_theResult___fst_exp78069_0_ETC__q196 = + _theResult___exp__h778724; endcase end - always@(guard__h779424 or - _theResult___fst_exp__h787650 or _theResult___exp__h788379) + always@(guard__h788489 or + _theResult___fst_exp__h796479 or _theResult___exp__h797159) begin - case (guard__h779424) + case (guard__h788489) 2'b0: - CASE_guard79424_0b0_theResult___fst_exp87650_0_ETC__q197 = - _theResult___fst_exp__h787650; + CASE_guard88489_0b0_theResult___fst_exp96479_0_ETC__q197 = + _theResult___fst_exp__h796479; 2'b01, 2'b10, 2'b11: - CASE_guard79424_0b0_theResult___fst_exp87650_0_ETC__q197 = - _theResult___exp__h788379; + CASE_guard88489_0b0_theResult___fst_exp96479_0_ETC__q197 = + _theResult___exp__h797159; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h787650 or - IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14795 or - IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14793 or - CASE_guard79424_0b0_theResult___fst_exp87650_0_ETC__q197) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd1: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14799 = - _theResult___fst_exp__h787650; - 3'd2: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14799 = - IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14795; - 3'd3: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14799 = - IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14793; - 3'd4: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14799 = - CASE_guard79424_0b0_theResult___fst_exp87650_0_ETC__q197; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14799 = - 11'd0; - endcase - end - always@(guard__h779424 or - _theResult___fst_exp__h787650 or - out_exp__h788382 or _theResult___exp__h788379) - begin - case (guard__h779424) - 2'b0, 2'b01: - CASE_guard79424_0b0_theResult___fst_exp87650_0_ETC__q198 = - _theResult___fst_exp__h787650; - 2'b10: - CASE_guard79424_0b0_theResult___fst_exp87650_0_ETC__q198 = - out_exp__h788382; - 2'b11: - CASE_guard79424_0b0_theResult___fst_exp87650_0_ETC__q198 = - _theResult___exp__h788379; - endcase - end - always@(guard__h788493 or - _theResult___fst_exp__h796483 or _theResult___exp__h797163) - begin - case (guard__h788493) - 2'b0: - CASE_guard88493_0b0_theResult___fst_exp96483_0_ETC__q199 = - _theResult___fst_exp__h796483; - 2'b01, 2'b10, 2'b11: - CASE_guard88493_0b0_theResult___fst_exp96483_0_ETC__q199 = - _theResult___exp__h797163; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h796483 or + _theResult___fst_exp__h796479 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14826 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14824 or - CASE_guard88493_0b0_theResult___fst_exp96483_0_ETC__q199) + CASE_guard88489_0b0_theResult___fst_exp96479_0_ETC__q197) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14830 = - _theResult___fst_exp__h796483; + _theResult___fst_exp__h796479; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14830 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14826; @@ -42836,49 +42758,100 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14824; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14830 = - CASE_guard88493_0b0_theResult___fst_exp96483_0_ETC__q199; + CASE_guard88489_0b0_theResult___fst_exp96479_0_ETC__q197; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14830 = 11'd0; endcase end - always@(guard__h788493 or - _theResult___fst_exp__h796483 or - out_exp__h797166 or _theResult___exp__h797163) + always@(guard__h788489 or + _theResult___fst_exp__h796479 or + out_exp__h797162 or _theResult___exp__h797159) begin - case (guard__h788493) + case (guard__h788489) 2'b0, 2'b01: - CASE_guard88493_0b0_theResult___fst_exp96483_0_ETC__q200 = - _theResult___fst_exp__h796483; + CASE_guard88489_0b0_theResult___fst_exp96479_0_ETC__q198 = + _theResult___fst_exp__h796479; 2'b10: - CASE_guard88493_0b0_theResult___fst_exp96483_0_ETC__q200 = - out_exp__h797166; + CASE_guard88489_0b0_theResult___fst_exp96479_0_ETC__q198 = + out_exp__h797162; 2'b11: - CASE_guard88493_0b0_theResult___fst_exp96483_0_ETC__q200 = - _theResult___exp__h797163; + CASE_guard88489_0b0_theResult___fst_exp96479_0_ETC__q198 = + _theResult___exp__h797159; endcase end - always@(guard__h818728 or - _theResult___fst_exp__h826954 or _theResult___exp__h827683) + always@(guard__h779420 or + _theResult___fst_exp__h787646 or _theResult___exp__h788375) begin - case (guard__h818728) + case (guard__h779420) 2'b0: - CASE_guard18728_0b0_theResult___fst_exp26954_0_ETC__q201 = - _theResult___fst_exp__h826954; + CASE_guard79420_0b0_theResult___fst_exp87646_0_ETC__q199 = + _theResult___fst_exp__h787646; 2'b01, 2'b10, 2'b11: - CASE_guard18728_0b0_theResult___fst_exp26954_0_ETC__q201 = - _theResult___exp__h827683; + CASE_guard79420_0b0_theResult___fst_exp87646_0_ETC__q199 = + _theResult___exp__h788375; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h826954 or + _theResult___fst_exp__h787646 or + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14795 or + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14793 or + CASE_guard79420_0b0_theResult___fst_exp87646_0_ETC__q199) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd1: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14799 = + _theResult___fst_exp__h787646; + 3'd2: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14799 = + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14795; + 3'd3: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14799 = + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14793; + 3'd4: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14799 = + CASE_guard79420_0b0_theResult___fst_exp87646_0_ETC__q199; + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14799 = + 11'd0; + endcase + end + always@(guard__h779420 or + _theResult___fst_exp__h787646 or + out_exp__h788378 or _theResult___exp__h788375) + begin + case (guard__h779420) + 2'b0, 2'b01: + CASE_guard79420_0b0_theResult___fst_exp87646_0_ETC__q200 = + _theResult___fst_exp__h787646; + 2'b10: + CASE_guard79420_0b0_theResult___fst_exp87646_0_ETC__q200 = + out_exp__h788378; + 2'b11: + CASE_guard79420_0b0_theResult___fst_exp87646_0_ETC__q200 = + _theResult___exp__h788375; + endcase + end + always@(guard__h818724 or + _theResult___fst_exp__h826950 or _theResult___exp__h827679) + begin + case (guard__h818724) + 2'b0: + CASE_guard18724_0b0_theResult___fst_exp26950_0_ETC__q201 = + _theResult___fst_exp__h826950; + 2'b01, 2'b10, 2'b11: + CASE_guard18724_0b0_theResult___fst_exp26950_0_ETC__q201 = + _theResult___exp__h827679; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or + _theResult___fst_exp__h826950 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14025 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14023 or - CASE_guard18728_0b0_theResult___fst_exp26954_0_ETC__q201) + CASE_guard18724_0b0_theResult___fst_exp26950_0_ETC__q201) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14029 = - _theResult___fst_exp__h826954; + _theResult___fst_exp__h826950; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14029 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14025; @@ -42887,49 +42860,49 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14023; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14029 = - CASE_guard18728_0b0_theResult___fst_exp26954_0_ETC__q201; + CASE_guard18724_0b0_theResult___fst_exp26950_0_ETC__q201; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14029 = 11'd0; endcase end - always@(guard__h818728 or - _theResult___fst_exp__h826954 or - out_exp__h827686 or _theResult___exp__h827683) + always@(guard__h818724 or + _theResult___fst_exp__h826950 or + out_exp__h827682 or _theResult___exp__h827679) begin - case (guard__h818728) + case (guard__h818724) 2'b0, 2'b01: - CASE_guard18728_0b0_theResult___fst_exp26954_0_ETC__q202 = - _theResult___fst_exp__h826954; + CASE_guard18724_0b0_theResult___fst_exp26950_0_ETC__q202 = + _theResult___fst_exp__h826950; 2'b10: - CASE_guard18728_0b0_theResult___fst_exp26954_0_ETC__q202 = - out_exp__h827686; + CASE_guard18724_0b0_theResult___fst_exp26950_0_ETC__q202 = + out_exp__h827682; 2'b11: - CASE_guard18728_0b0_theResult___fst_exp26954_0_ETC__q202 = - _theResult___exp__h827683; + CASE_guard18724_0b0_theResult___fst_exp26950_0_ETC__q202 = + _theResult___exp__h827679; endcase end - always@(guard__h827797 or - _theResult___fst_exp__h835787 or _theResult___exp__h836467) + always@(guard__h827793 or + _theResult___fst_exp__h835783 or _theResult___exp__h836463) begin - case (guard__h827797) + case (guard__h827793) 2'b0: - CASE_guard27797_0b0_theResult___fst_exp35787_0_ETC__q203 = - _theResult___fst_exp__h835787; + CASE_guard27793_0b0_theResult___fst_exp35783_0_ETC__q203 = + _theResult___fst_exp__h835783; 2'b01, 2'b10, 2'b11: - CASE_guard27797_0b0_theResult___fst_exp35787_0_ETC__q203 = - _theResult___exp__h836467; + CASE_guard27793_0b0_theResult___fst_exp35783_0_ETC__q203 = + _theResult___exp__h836463; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h835787 or + _theResult___fst_exp__h835783 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14056 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14054 or - CASE_guard27797_0b0_theResult___fst_exp35787_0_ETC__q203) + CASE_guard27793_0b0_theResult___fst_exp35783_0_ETC__q203) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14060 = - _theResult___fst_exp__h835787; + _theResult___fst_exp__h835783; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14060 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14056; @@ -42938,44 +42911,44 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14054; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14060 = - CASE_guard27797_0b0_theResult___fst_exp35787_0_ETC__q203; + CASE_guard27793_0b0_theResult___fst_exp35783_0_ETC__q203; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14060 = 11'd0; endcase end - always@(guard__h827797 or - _theResult___fst_exp__h835787 or - out_exp__h836470 or _theResult___exp__h836467) + always@(guard__h827793 or + _theResult___fst_exp__h835783 or + out_exp__h836466 or _theResult___exp__h836463) begin - case (guard__h827797) + case (guard__h827793) 2'b0, 2'b01: - CASE_guard27797_0b0_theResult___fst_exp35787_0_ETC__q204 = - _theResult___fst_exp__h835787; + CASE_guard27793_0b0_theResult___fst_exp35783_0_ETC__q204 = + _theResult___fst_exp__h835783; 2'b10: - CASE_guard27797_0b0_theResult___fst_exp35787_0_ETC__q204 = - out_exp__h836470; + CASE_guard27793_0b0_theResult___fst_exp35783_0_ETC__q204 = + out_exp__h836466; 2'b11: - CASE_guard27797_0b0_theResult___fst_exp35787_0_ETC__q204 = - _theResult___exp__h836467; + CASE_guard27793_0b0_theResult___fst_exp35783_0_ETC__q204 = + _theResult___exp__h836463; endcase end - always@(guard__h770112 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h770108 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h770112) + case (guard__h770108) 2'b0, 2'b01, 2'b10: - CASE_guard70112_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q205 = + CASE_guard70108_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q205 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard70112_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q205 = - guard__h770112 == 2'b11 && + CASE_guard70108_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q205 = + guard__h770108 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h770112) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h770108) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -42985,12 +42958,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q206 = - (guard__h770112 == 2'b0) ? + (guard__h770108 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h770112 == 2'b01 || guard__h770112 == 2'b10 || - guard__h770112 == 2'b11) && + (guard__h770108 == 2'b01 || guard__h770108 == 2'b10 || + guard__h770108 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -43001,23 +42974,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h779424 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h779420 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h779424) + case (guard__h779420) 2'b0, 2'b01, 2'b10: - CASE_guard79424_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q207 = + CASE_guard79420_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q207 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard79424_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q207 = - guard__h779424 == 2'b11 && + CASE_guard79420_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q207 = + guard__h779420 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h779424) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h779420) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -43027,12 +43000,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q208 = - (guard__h779424 == 2'b0) ? + (guard__h779420 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h779424 == 2'b01 || guard__h779424 == 2'b10 || - guard__h779424 == 2'b11) && + (guard__h779420 == 2'b01 || guard__h779420 == 2'b10 || + guard__h779420 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -43043,23 +43016,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h788493 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h788489 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h788493) + case (guard__h788489) 2'b0, 2'b01, 2'b10: - CASE_guard88493_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q209 = + CASE_guard88489_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q209 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard88493_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q209 = - guard__h788493 == 2'b11 && + CASE_guard88489_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q209 = + guard__h788489 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h788493) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h788489) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -43069,12 +43042,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q210 = - (guard__h788493 == 2'b0) ? + (guard__h788489 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h788493 == 2'b01 || guard__h788493 == 2'b10 || - guard__h788493 == 2'b11) && + (guard__h788489 == 2'b01 || guard__h788489 == 2'b10 || + guard__h788489 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -43085,23 +43058,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h779424 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h779420 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h779424) + case (guard__h779420) 2'b0, 2'b01, 2'b10: - CASE_guard79424_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q211 = + CASE_guard79420_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q211 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard79424_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q211 = - guard__h779424 != 2'b11 || + CASE_guard79420_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q211 = + guard__h779420 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h779424) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h779420) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -43111,12 +43084,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q212 = - (guard__h779424 == 2'b0) ? + (guard__h779420 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h779424 != 2'b01 && guard__h779424 != 2'b10 && - guard__h779424 != 2'b11 || + guard__h779420 != 2'b01 && guard__h779420 != 2'b10 && + guard__h779420 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -43127,23 +43100,23 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h770112 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h788489 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h770112) + case (guard__h788489) 2'b0, 2'b01, 2'b10: - CASE_guard70112_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q213 = + CASE_guard88489_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q213 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard70112_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q213 = - guard__h770112 != 2'b11 || + CASE_guard88489_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q213 = + guard__h788489 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h770112) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h788489) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -43153,12 +43126,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q214 = - (guard__h770112 == 2'b0) ? + (guard__h788489 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h770112 != 2'b01 && guard__h770112 != 2'b10 && - guard__h770112 != 2'b11 || + guard__h788489 != 2'b01 && guard__h788489 != 2'b10 && + guard__h788489 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -43169,23 +43142,23 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h788493 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h770108 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h788493) + case (guard__h770108) 2'b0, 2'b01, 2'b10: - CASE_guard88493_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q215 = + CASE_guard70108_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q215 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard88493_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q215 = - guard__h788493 != 2'b11 || + CASE_guard70108_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q215 = + guard__h770108 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h788493) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h770108) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -43195,12 +43168,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q216 = - (guard__h788493 == 2'b0) ? + (guard__h770108 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h788493 != 2'b01 && guard__h788493 != 2'b10 && - guard__h788493 != 2'b11 || + guard__h770108 != 2'b01 && guard__h770108 != 2'b10 && + guard__h770108 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -43211,28 +43184,28 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h770112 or - _theResult___snd__h778024 or _theResult___sfd__h778729) + always@(guard__h770108 or + _theResult___snd__h778020 or _theResult___sfd__h778725) begin - case (guard__h770112) + case (guard__h770108) 2'b0: - CASE_guard70112_0b0_theResult___snd78024_BITS__ETC__q217 = - _theResult___snd__h778024[56:5]; + CASE_guard70108_0b0_theResult___snd78020_BITS__ETC__q217 = + _theResult___snd__h778020[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard70112_0b0_theResult___snd78024_BITS__ETC__q217 = - _theResult___sfd__h778729; + CASE_guard70108_0b0_theResult___snd78020_BITS__ETC__q217 = + _theResult___sfd__h778725; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h778024 or + _theResult___snd__h778020 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14852 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14850 or - CASE_guard70112_0b0_theResult___snd78024_BITS__ETC__q217) + CASE_guard70108_0b0_theResult___snd78020_BITS__ETC__q217) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14856 = - _theResult___snd__h778024[56:5]; + _theResult___snd__h778020[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14856 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14852; @@ -43241,99 +43214,48 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14850; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14856 = - CASE_guard70112_0b0_theResult___snd78024_BITS__ETC__q217; + CASE_guard70108_0b0_theResult___snd78020_BITS__ETC__q217; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14856 = 52'd0; endcase end - always@(guard__h770112 or - _theResult___snd__h778024 or - out_sfd__h778732 or _theResult___sfd__h778729) + always@(guard__h770108 or + _theResult___snd__h778020 or + out_sfd__h778728 or _theResult___sfd__h778725) begin - case (guard__h770112) + case (guard__h770108) 2'b0, 2'b01: - CASE_guard70112_0b0_theResult___snd78024_BITS__ETC__q218 = - _theResult___snd__h778024[56:5]; + CASE_guard70108_0b0_theResult___snd78020_BITS__ETC__q218 = + _theResult___snd__h778020[56:5]; 2'b10: - CASE_guard70112_0b0_theResult___snd78024_BITS__ETC__q218 = - out_sfd__h778732; + CASE_guard70108_0b0_theResult___snd78020_BITS__ETC__q218 = + out_sfd__h778728; 2'b11: - CASE_guard70112_0b0_theResult___snd78024_BITS__ETC__q218 = - _theResult___sfd__h778729; + CASE_guard70108_0b0_theResult___snd78020_BITS__ETC__q218 = + _theResult___sfd__h778725; endcase end - always@(guard__h788493 or - _theResult___snd__h796429 or _theResult___sfd__h797164) + always@(guard__h779420 or sfdin__h787640 or _theResult___sfd__h788376) begin - case (guard__h788493) + case (guard__h779420) 2'b0: - CASE_guard88493_0b0_theResult___snd96429_BITS__ETC__q219 = - _theResult___snd__h796429[56:5]; + CASE_guard79420_0b0_sfdin87640_BITS_56_TO_5_0b_ETC__q219 = + sfdin__h787640[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard88493_0b0_theResult___snd96429_BITS__ETC__q219 = - _theResult___sfd__h797164; + CASE_guard79420_0b0_sfdin87640_BITS_56_TO_5_0b_ETC__q219 = + _theResult___sfd__h788376; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h796429 or - IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14897 or - IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14895 or - CASE_guard88493_0b0_theResult___snd96429_BITS__ETC__q219) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd1: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14901 = - _theResult___snd__h796429[56:5]; - 3'd2: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14901 = - IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14897; - 3'd3: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14901 = - IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14895; - 3'd4: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14901 = - CASE_guard88493_0b0_theResult___snd96429_BITS__ETC__q219; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14901 = - 52'd0; - endcase - end - always@(guard__h788493 or - _theResult___snd__h796429 or - out_sfd__h797167 or _theResult___sfd__h797164) - begin - case (guard__h788493) - 2'b0, 2'b01: - CASE_guard88493_0b0_theResult___snd96429_BITS__ETC__q220 = - _theResult___snd__h796429[56:5]; - 2'b10: - CASE_guard88493_0b0_theResult___snd96429_BITS__ETC__q220 = - out_sfd__h797167; - 2'b11: - CASE_guard88493_0b0_theResult___snd96429_BITS__ETC__q220 = - _theResult___sfd__h797164; - endcase - end - always@(guard__h779424 or sfdin__h787644 or _theResult___sfd__h788380) - begin - case (guard__h779424) - 2'b0: - CASE_guard79424_0b0_sfdin87644_BITS_56_TO_5_0b_ETC__q221 = - sfdin__h787644[56:5]; - 2'b01, 2'b10, 2'b11: - CASE_guard79424_0b0_sfdin87644_BITS_56_TO_5_0b_ETC__q221 = - _theResult___sfd__h788380; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h787644 or + sfdin__h787640 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14878 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14876 or - CASE_guard79424_0b0_sfdin87644_BITS_56_TO_5_0b_ETC__q221) + CASE_guard79420_0b0_sfdin87640_BITS_56_TO_5_0b_ETC__q219) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14882 = - sfdin__h787644[56:5]; + sfdin__h787640[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14882 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14878; @@ -43342,48 +43264,99 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14876; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14882 = - CASE_guard79424_0b0_sfdin87644_BITS_56_TO_5_0b_ETC__q221; + CASE_guard79420_0b0_sfdin87640_BITS_56_TO_5_0b_ETC__q219; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14882 = 52'd0; endcase end - always@(guard__h779424 or - sfdin__h787644 or out_sfd__h788383 or _theResult___sfd__h788380) + always@(guard__h779420 or + sfdin__h787640 or out_sfd__h788379 or _theResult___sfd__h788376) begin - case (guard__h779424) + case (guard__h779420) 2'b0, 2'b01: - CASE_guard79424_0b0_sfdin87644_BITS_56_TO_5_0b_ETC__q222 = - sfdin__h787644[56:5]; + CASE_guard79420_0b0_sfdin87640_BITS_56_TO_5_0b_ETC__q220 = + sfdin__h787640[56:5]; 2'b10: - CASE_guard79424_0b0_sfdin87644_BITS_56_TO_5_0b_ETC__q222 = - out_sfd__h788383; + CASE_guard79420_0b0_sfdin87640_BITS_56_TO_5_0b_ETC__q220 = + out_sfd__h788379; 2'b11: - CASE_guard79424_0b0_sfdin87644_BITS_56_TO_5_0b_ETC__q222 = - _theResult___sfd__h788380; + CASE_guard79420_0b0_sfdin87640_BITS_56_TO_5_0b_ETC__q220 = + _theResult___sfd__h788376; endcase end - always@(guard__h740571 or - _theResult___fst_exp__h748797 or _theResult___exp__h749526) + always@(guard__h788489 or + _theResult___snd__h796425 or _theResult___sfd__h797160) begin - case (guard__h740571) + case (guard__h788489) 2'b0: - CASE_guard40571_0b0_theResult___fst_exp48797_0_ETC__q223 = - _theResult___fst_exp__h748797; + CASE_guard88489_0b0_theResult___snd96425_BITS__ETC__q221 = + _theResult___snd__h796425[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard40571_0b0_theResult___fst_exp48797_0_ETC__q223 = - _theResult___exp__h749526; + CASE_guard88489_0b0_theResult___snd96425_BITS__ETC__q221 = + _theResult___sfd__h797160; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h748797 or + _theResult___snd__h796425 or + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14897 or + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14895 or + CASE_guard88489_0b0_theResult___snd96425_BITS__ETC__q221) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd1: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14901 = + _theResult___snd__h796425[56:5]; + 3'd2: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14901 = + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14897; + 3'd3: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14901 = + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14895; + 3'd4: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14901 = + CASE_guard88489_0b0_theResult___snd96425_BITS__ETC__q221; + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14901 = + 52'd0; + endcase + end + always@(guard__h788489 or + _theResult___snd__h796425 or + out_sfd__h797163 or _theResult___sfd__h797160) + begin + case (guard__h788489) + 2'b0, 2'b01: + CASE_guard88489_0b0_theResult___snd96425_BITS__ETC__q222 = + _theResult___snd__h796425[56:5]; + 2'b10: + CASE_guard88489_0b0_theResult___snd96425_BITS__ETC__q222 = + out_sfd__h797163; + 2'b11: + CASE_guard88489_0b0_theResult___snd96425_BITS__ETC__q222 = + _theResult___sfd__h797160; + endcase + end + always@(guard__h740567 or + _theResult___fst_exp__h748793 or _theResult___exp__h749522) + begin + case (guard__h740567) + 2'b0: + CASE_guard40567_0b0_theResult___fst_exp48793_0_ETC__q223 = + _theResult___fst_exp__h748793; + 2'b01, 2'b10, 2'b11: + CASE_guard40567_0b0_theResult___fst_exp48793_0_ETC__q223 = + _theResult___exp__h749522; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or + _theResult___fst_exp__h748793 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13315 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13313 or - CASE_guard40571_0b0_theResult___fst_exp48797_0_ETC__q223) + CASE_guard40567_0b0_theResult___fst_exp48793_0_ETC__q223) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d13319 = - _theResult___fst_exp__h748797; + _theResult___fst_exp__h748793; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d13319 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13315; @@ -43392,49 +43365,49 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13313; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d13319 = - CASE_guard40571_0b0_theResult___fst_exp48797_0_ETC__q223; + CASE_guard40567_0b0_theResult___fst_exp48793_0_ETC__q223; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d13319 = 11'd0; endcase end - always@(guard__h740571 or - _theResult___fst_exp__h748797 or - out_exp__h749529 or _theResult___exp__h749526) + always@(guard__h740567 or + _theResult___fst_exp__h748793 or + out_exp__h749525 or _theResult___exp__h749522) begin - case (guard__h740571) + case (guard__h740567) 2'b0, 2'b01: - CASE_guard40571_0b0_theResult___fst_exp48797_0_ETC__q224 = - _theResult___fst_exp__h748797; + CASE_guard40567_0b0_theResult___fst_exp48793_0_ETC__q224 = + _theResult___fst_exp__h748793; 2'b10: - CASE_guard40571_0b0_theResult___fst_exp48797_0_ETC__q224 = - out_exp__h749529; + CASE_guard40567_0b0_theResult___fst_exp48793_0_ETC__q224 = + out_exp__h749525; 2'b11: - CASE_guard40571_0b0_theResult___fst_exp48797_0_ETC__q224 = - _theResult___exp__h749526; + CASE_guard40567_0b0_theResult___fst_exp48793_0_ETC__q224 = + _theResult___exp__h749522; endcase end - always@(guard__h749640 or - _theResult___fst_exp__h757630 or _theResult___exp__h758310) + always@(guard__h749636 or + _theResult___fst_exp__h757626 or _theResult___exp__h758306) begin - case (guard__h749640) + case (guard__h749636) 2'b0: - CASE_guard49640_0b0_theResult___fst_exp57630_0_ETC__q225 = - _theResult___fst_exp__h757630; + CASE_guard49636_0b0_theResult___fst_exp57626_0_ETC__q225 = + _theResult___fst_exp__h757626; 2'b01, 2'b10, 2'b11: - CASE_guard49640_0b0_theResult___fst_exp57630_0_ETC__q225 = - _theResult___exp__h758310; + CASE_guard49636_0b0_theResult___fst_exp57626_0_ETC__q225 = + _theResult___exp__h758306; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h757630 or + _theResult___fst_exp__h757626 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13346 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13344 or - CASE_guard49640_0b0_theResult___fst_exp57630_0_ETC__q225) + CASE_guard49636_0b0_theResult___fst_exp57626_0_ETC__q225) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d13350 = - _theResult___fst_exp__h757630; + _theResult___fst_exp__h757626; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d13350 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13346; @@ -43443,98 +43416,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13344; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d13350 = - CASE_guard49640_0b0_theResult___fst_exp57630_0_ETC__q225; + CASE_guard49636_0b0_theResult___fst_exp57626_0_ETC__q225; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d13350 = 11'd0; endcase end - always@(guard__h749640 or - _theResult___fst_exp__h757630 or - out_exp__h758313 or _theResult___exp__h758310) + always@(guard__h749636 or + _theResult___fst_exp__h757626 or + out_exp__h758309 or _theResult___exp__h758306) begin - case (guard__h749640) + case (guard__h749636) 2'b0, 2'b01: - CASE_guard49640_0b0_theResult___fst_exp57630_0_ETC__q226 = - _theResult___fst_exp__h757630; + CASE_guard49636_0b0_theResult___fst_exp57626_0_ETC__q226 = + _theResult___fst_exp__h757626; 2'b10: - CASE_guard49640_0b0_theResult___fst_exp57630_0_ETC__q226 = - out_exp__h758313; + CASE_guard49636_0b0_theResult___fst_exp57626_0_ETC__q226 = + out_exp__h758309; 2'b11: - CASE_guard49640_0b0_theResult___fst_exp57630_0_ETC__q226 = - _theResult___exp__h758310; + CASE_guard49636_0b0_theResult___fst_exp57626_0_ETC__q226 = + _theResult___exp__h758306; endcase end - always@(guard__h740571 or sfdin__h748791 or _theResult___sfd__h749527) + always@(guard__h731255 or + _theResult___snd__h739167 or _theResult___sfd__h739872) begin - case (guard__h740571) + case (guard__h731255) 2'b0: - CASE_guard40571_0b0_sfdin48791_BITS_56_TO_5_0b_ETC__q227 = - sfdin__h748791[56:5]; + CASE_guard31255_0b0_theResult___snd39167_BITS__ETC__q227 = + _theResult___snd__h739167[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard40571_0b0_sfdin48791_BITS_56_TO_5_0b_ETC__q227 = - _theResult___sfd__h749527; + CASE_guard31255_0b0_theResult___snd39167_BITS__ETC__q227 = + _theResult___sfd__h739872; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h748791 or - IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13399 or - IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13397 or - CASE_guard40571_0b0_sfdin48791_BITS_56_TO_5_0b_ETC__q227) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd1: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d13403 = - sfdin__h748791[56:5]; - 3'd2: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d13403 = - IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13399; - 3'd3: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d13403 = - IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13397; - 3'd4: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d13403 = - CASE_guard40571_0b0_sfdin48791_BITS_56_TO_5_0b_ETC__q227; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d13403 = - 52'd0; - endcase - end - always@(guard__h740571 or - sfdin__h748791 or out_sfd__h749530 or _theResult___sfd__h749527) - begin - case (guard__h740571) - 2'b0, 2'b01: - CASE_guard40571_0b0_sfdin48791_BITS_56_TO_5_0b_ETC__q228 = - sfdin__h748791[56:5]; - 2'b10: - CASE_guard40571_0b0_sfdin48791_BITS_56_TO_5_0b_ETC__q228 = - out_sfd__h749530; - 2'b11: - CASE_guard40571_0b0_sfdin48791_BITS_56_TO_5_0b_ETC__q228 = - _theResult___sfd__h749527; - endcase - end - always@(guard__h731259 or - _theResult___snd__h739171 or _theResult___sfd__h739876) - begin - case (guard__h731259) - 2'b0: - CASE_guard31259_0b0_theResult___snd39171_BITS__ETC__q229 = - _theResult___snd__h739171[56:5]; - 2'b01, 2'b10, 2'b11: - CASE_guard31259_0b0_theResult___snd39171_BITS__ETC__q229 = - _theResult___sfd__h739876; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h739171 or + _theResult___snd__h739167 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13372 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13370 or - CASE_guard31259_0b0_theResult___snd39171_BITS__ETC__q229) + CASE_guard31255_0b0_theResult___snd39167_BITS__ETC__q227) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d13376 = - _theResult___snd__h739171[56:5]; + _theResult___snd__h739167[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d13376 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13372; @@ -43543,49 +43467,98 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13370; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d13376 = - CASE_guard31259_0b0_theResult___snd39171_BITS__ETC__q229; + CASE_guard31255_0b0_theResult___snd39167_BITS__ETC__q227; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d13376 = 52'd0; endcase end - always@(guard__h731259 or - _theResult___snd__h739171 or - out_sfd__h739879 or _theResult___sfd__h739876) + always@(guard__h731255 or + _theResult___snd__h739167 or + out_sfd__h739875 or _theResult___sfd__h739872) begin - case (guard__h731259) + case (guard__h731255) 2'b0, 2'b01: - CASE_guard31259_0b0_theResult___snd39171_BITS__ETC__q230 = - _theResult___snd__h739171[56:5]; + CASE_guard31255_0b0_theResult___snd39167_BITS__ETC__q228 = + _theResult___snd__h739167[56:5]; 2'b10: - CASE_guard31259_0b0_theResult___snd39171_BITS__ETC__q230 = - out_sfd__h739879; + CASE_guard31255_0b0_theResult___snd39167_BITS__ETC__q228 = + out_sfd__h739875; 2'b11: - CASE_guard31259_0b0_theResult___snd39171_BITS__ETC__q230 = - _theResult___sfd__h739876; + CASE_guard31255_0b0_theResult___snd39167_BITS__ETC__q228 = + _theResult___sfd__h739872; endcase end - always@(guard__h749640 or - _theResult___snd__h757576 or _theResult___sfd__h758311) + always@(guard__h740567 or sfdin__h748787 or _theResult___sfd__h749523) begin - case (guard__h749640) + case (guard__h740567) 2'b0: - CASE_guard49640_0b0_theResult___snd57576_BITS__ETC__q231 = - _theResult___snd__h757576[56:5]; + CASE_guard40567_0b0_sfdin48787_BITS_56_TO_5_0b_ETC__q229 = + sfdin__h748787[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard49640_0b0_theResult___snd57576_BITS__ETC__q231 = - _theResult___sfd__h758311; + CASE_guard40567_0b0_sfdin48787_BITS_56_TO_5_0b_ETC__q229 = + _theResult___sfd__h749523; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h757576 or + sfdin__h748787 or + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13399 or + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13397 or + CASE_guard40567_0b0_sfdin48787_BITS_56_TO_5_0b_ETC__q229) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd1: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d13403 = + sfdin__h748787[56:5]; + 3'd2: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d13403 = + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13399; + 3'd3: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d13403 = + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13397; + 3'd4: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d13403 = + CASE_guard40567_0b0_sfdin48787_BITS_56_TO_5_0b_ETC__q229; + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d13403 = + 52'd0; + endcase + end + always@(guard__h740567 or + sfdin__h748787 or out_sfd__h749526 or _theResult___sfd__h749523) + begin + case (guard__h740567) + 2'b0, 2'b01: + CASE_guard40567_0b0_sfdin48787_BITS_56_TO_5_0b_ETC__q230 = + sfdin__h748787[56:5]; + 2'b10: + CASE_guard40567_0b0_sfdin48787_BITS_56_TO_5_0b_ETC__q230 = + out_sfd__h749526; + 2'b11: + CASE_guard40567_0b0_sfdin48787_BITS_56_TO_5_0b_ETC__q230 = + _theResult___sfd__h749523; + endcase + end + always@(guard__h749636 or + _theResult___snd__h757572 or _theResult___sfd__h758307) + begin + case (guard__h749636) + 2'b0: + CASE_guard49636_0b0_theResult___snd57572_BITS__ETC__q231 = + _theResult___snd__h757572[56:5]; + 2'b01, 2'b10, 2'b11: + CASE_guard49636_0b0_theResult___snd57572_BITS__ETC__q231 = + _theResult___sfd__h758307; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or + _theResult___snd__h757572 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13418 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13416 or - CASE_guard49640_0b0_theResult___snd57576_BITS__ETC__q231) + CASE_guard49636_0b0_theResult___snd57572_BITS__ETC__q231) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d13422 = - _theResult___snd__h757576[56:5]; + _theResult___snd__h757572[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d13422 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13418; @@ -43594,49 +43567,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13416; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d13422 = - CASE_guard49640_0b0_theResult___snd57576_BITS__ETC__q231; + CASE_guard49636_0b0_theResult___snd57572_BITS__ETC__q231; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d13422 = 52'd0; endcase end - always@(guard__h749640 or - _theResult___snd__h757576 or - out_sfd__h758314 or _theResult___sfd__h758311) + always@(guard__h749636 or + _theResult___snd__h757572 or + out_sfd__h758310 or _theResult___sfd__h758307) begin - case (guard__h749640) + case (guard__h749636) 2'b0, 2'b01: - CASE_guard49640_0b0_theResult___snd57576_BITS__ETC__q232 = - _theResult___snd__h757576[56:5]; + CASE_guard49636_0b0_theResult___snd57572_BITS__ETC__q232 = + _theResult___snd__h757572[56:5]; 2'b10: - CASE_guard49640_0b0_theResult___snd57576_BITS__ETC__q232 = - out_sfd__h758314; + CASE_guard49636_0b0_theResult___snd57572_BITS__ETC__q232 = + out_sfd__h758310; 2'b11: - CASE_guard49640_0b0_theResult___snd57576_BITS__ETC__q232 = - _theResult___sfd__h758311; + CASE_guard49636_0b0_theResult___snd57572_BITS__ETC__q232 = + _theResult___sfd__h758307; endcase end - always@(guard__h809416 or - _theResult___snd__h817328 or _theResult___sfd__h818033) + always@(guard__h809412 or + _theResult___snd__h817324 or _theResult___sfd__h818029) begin - case (guard__h809416) + case (guard__h809412) 2'b0: - CASE_guard09416_0b0_theResult___snd17328_BITS__ETC__q233 = - _theResult___snd__h817328[56:5]; + CASE_guard09412_0b0_theResult___snd17324_BITS__ETC__q233 = + _theResult___snd__h817324[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard09416_0b0_theResult___snd17328_BITS__ETC__q233 = - _theResult___sfd__h818033; + CASE_guard09412_0b0_theResult___snd17324_BITS__ETC__q233 = + _theResult___sfd__h818029; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h817328 or + _theResult___snd__h817324 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14082 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14080 or - CASE_guard09416_0b0_theResult___snd17328_BITS__ETC__q233) + CASE_guard09412_0b0_theResult___snd17324_BITS__ETC__q233) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14086 = - _theResult___snd__h817328[56:5]; + _theResult___snd__h817324[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14086 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14082; @@ -43645,48 +43618,48 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14080; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14086 = - CASE_guard09416_0b0_theResult___snd17328_BITS__ETC__q233; + CASE_guard09412_0b0_theResult___snd17324_BITS__ETC__q233; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14086 = 52'd0; endcase end - always@(guard__h809416 or - _theResult___snd__h817328 or - out_sfd__h818036 or _theResult___sfd__h818033) + always@(guard__h809412 or + _theResult___snd__h817324 or + out_sfd__h818032 or _theResult___sfd__h818029) begin - case (guard__h809416) + case (guard__h809412) 2'b0, 2'b01: - CASE_guard09416_0b0_theResult___snd17328_BITS__ETC__q234 = - _theResult___snd__h817328[56:5]; + CASE_guard09412_0b0_theResult___snd17324_BITS__ETC__q234 = + _theResult___snd__h817324[56:5]; 2'b10: - CASE_guard09416_0b0_theResult___snd17328_BITS__ETC__q234 = - out_sfd__h818036; + CASE_guard09412_0b0_theResult___snd17324_BITS__ETC__q234 = + out_sfd__h818032; 2'b11: - CASE_guard09416_0b0_theResult___snd17328_BITS__ETC__q234 = - _theResult___sfd__h818033; + CASE_guard09412_0b0_theResult___snd17324_BITS__ETC__q234 = + _theResult___sfd__h818029; endcase end - always@(guard__h818728 or sfdin__h826948 or _theResult___sfd__h827684) + always@(guard__h818724 or sfdin__h826944 or _theResult___sfd__h827680) begin - case (guard__h818728) + case (guard__h818724) 2'b0: - CASE_guard18728_0b0_sfdin26948_BITS_56_TO_5_0b_ETC__q235 = - sfdin__h826948[56:5]; + CASE_guard18724_0b0_sfdin26944_BITS_56_TO_5_0b_ETC__q235 = + sfdin__h826944[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard18728_0b0_sfdin26948_BITS_56_TO_5_0b_ETC__q235 = - _theResult___sfd__h827684; + CASE_guard18724_0b0_sfdin26944_BITS_56_TO_5_0b_ETC__q235 = + _theResult___sfd__h827680; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h826948 or + sfdin__h826944 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14108 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14106 or - CASE_guard18728_0b0_sfdin26948_BITS_56_TO_5_0b_ETC__q235) + CASE_guard18724_0b0_sfdin26944_BITS_56_TO_5_0b_ETC__q235) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14112 = - sfdin__h826948[56:5]; + sfdin__h826944[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14112 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14108; @@ -43695,28 +43668,28 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14106; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14112 = - CASE_guard18728_0b0_sfdin26948_BITS_56_TO_5_0b_ETC__q235; + CASE_guard18724_0b0_sfdin26944_BITS_56_TO_5_0b_ETC__q235; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14112 = 52'd0; endcase end - always@(guard__h818728 or - sfdin__h826948 or out_sfd__h827687 or _theResult___sfd__h827684) + always@(guard__h818724 or + sfdin__h826944 or out_sfd__h827683 or _theResult___sfd__h827680) begin - case (guard__h818728) + case (guard__h818724) 2'b0, 2'b01: - CASE_guard18728_0b0_sfdin26948_BITS_56_TO_5_0b_ETC__q236 = - sfdin__h826948[56:5]; + CASE_guard18724_0b0_sfdin26944_BITS_56_TO_5_0b_ETC__q236 = + sfdin__h826944[56:5]; 2'b10: - CASE_guard18728_0b0_sfdin26948_BITS_56_TO_5_0b_ETC__q236 = - out_sfd__h827687; + CASE_guard18724_0b0_sfdin26944_BITS_56_TO_5_0b_ETC__q236 = + out_sfd__h827683; 2'b11: - CASE_guard18728_0b0_sfdin26948_BITS_56_TO_5_0b_ETC__q236 = - _theResult___sfd__h827684; + CASE_guard18724_0b0_sfdin26944_BITS_56_TO_5_0b_ETC__q236 = + _theResult___sfd__h827680; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - coreFix_fpuMulDivExe_0_regToExeQ_first__2628_B_ETC___d15145 or + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15144 or NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15133 or NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15122) begin @@ -43728,11 +43701,19 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d15147 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15122; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d15147 = - coreFix_fpuMulDivExe_0_regToExeQ_first__2628_B_ETC___d15145; + (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == + 5'd25 || + coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == + 5'd26 || + coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == + 5'd27 || + coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == + 5'd28) && + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15144; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - coreFix_fpuMulDivExe_0_regToExeQ_first__2628_B_ETC___d15109 or + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15108 or NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15064 or NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15022) begin @@ -43744,31 +43725,39 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d15111 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15022; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d15111 = - coreFix_fpuMulDivExe_0_regToExeQ_first__2628_B_ETC___d15109; + (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == + 5'd25 || + coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == + 5'd26 || + coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == + 5'd27 || + coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == + 5'd28) && + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15108; endcase end - always@(guard__h827797 or - _theResult___snd__h835733 or _theResult___sfd__h836468) + always@(guard__h827793 or + _theResult___snd__h835729 or _theResult___sfd__h836464) begin - case (guard__h827797) + case (guard__h827793) 2'b0: - CASE_guard27797_0b0_theResult___snd35733_BITS__ETC__q237 = - _theResult___snd__h835733[56:5]; + CASE_guard27793_0b0_theResult___snd35729_BITS__ETC__q237 = + _theResult___snd__h835729[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard27797_0b0_theResult___snd35733_BITS__ETC__q237 = - _theResult___sfd__h836468; + CASE_guard27793_0b0_theResult___snd35729_BITS__ETC__q237 = + _theResult___sfd__h836464; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h835733 or + _theResult___snd__h835729 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14127 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14125 or - CASE_guard27797_0b0_theResult___snd35733_BITS__ETC__q237) + CASE_guard27793_0b0_theResult___snd35729_BITS__ETC__q237) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14131 = - _theResult___snd__h835733[56:5]; + _theResult___snd__h835729[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14131 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14127; @@ -43777,29 +43766,29 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14125; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14131 = - CASE_guard27797_0b0_theResult___snd35733_BITS__ETC__q237; + CASE_guard27793_0b0_theResult___snd35729_BITS__ETC__q237; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14131 = 52'd0; endcase end - always@(guard__h827797 or - _theResult___snd__h835733 or - out_sfd__h836471 or _theResult___sfd__h836468) + always@(guard__h827793 or + _theResult___snd__h835729 or + out_sfd__h836467 or _theResult___sfd__h836464) begin - case (guard__h827797) + case (guard__h827793) 2'b0, 2'b01: - CASE_guard27797_0b0_theResult___snd35733_BITS__ETC__q238 = - _theResult___snd__h835733[56:5]; + CASE_guard27793_0b0_theResult___snd35729_BITS__ETC__q238 = + _theResult___snd__h835729[56:5]; 2'b10: - CASE_guard27797_0b0_theResult___snd35733_BITS__ETC__q238 = - out_sfd__h836471; + CASE_guard27793_0b0_theResult___snd35729_BITS__ETC__q238 = + out_sfd__h836467; 2'b11: - CASE_guard27797_0b0_theResult___snd35733_BITS__ETC__q238 = - _theResult___sfd__h836468; + CASE_guard27793_0b0_theResult___snd35729_BITS__ETC__q238 = + _theResult___sfd__h836464; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - coreFix_fpuMulDivExe_0_regToExeQ_first__2628_B_ETC___d15193 or + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15192 or NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15177 or NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15162) begin @@ -43811,11 +43800,19 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d15195 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15162; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d15195 = - coreFix_fpuMulDivExe_0_regToExeQ_first__2628_B_ETC___d15193; + (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == + 5'd25 || + coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == + 5'd26 || + coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == + 5'd27 || + coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == + 5'd28) && + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15192; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - coreFix_fpuMulDivExe_0_regToExeQ_first__2628_B_ETC___d15235 or + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15234 or NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15221 or NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15208) begin @@ -43827,11 +43824,19 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d15237 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15208; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d15237 = - coreFix_fpuMulDivExe_0_regToExeQ_first__2628_B_ETC___d15235; + (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == + 5'd25 || + coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == + 5'd26 || + coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == + 5'd27 || + coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == + 5'd28) && + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15234; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - coreFix_fpuMulDivExe_0_regToExeQ_first__2628_B_ETC___d15277 or + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15276 or NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15263 or NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15250) begin @@ -43843,7 +43848,15 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d15279 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15250; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d15279 = - coreFix_fpuMulDivExe_0_regToExeQ_first__2628_B_ETC___d15277; + (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == + 5'd25 || + coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == + 5'd26 || + coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == + 5'd27 || + coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == + 5'd28) && + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15276; endcase end always@(coreFix_aluExe_1_rsAlu$dispatchData) @@ -44347,10 +44360,10 @@ module mkCore(CLK, 4'd14; endcase end - always@(k__h954121 or + always@(k__h954118 or coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq) begin - case (k__h954121) + case (k__h954118) 1'd0: SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__149_ETC___d21502 = !coreFix_aluExe_0_rsAlu$canEnq; @@ -44370,10 +44383,10 @@ module mkCore(CLK, coreFix_memExe_lsq$enqStTag[6]; endcase end - always@(k__h954121 or + always@(k__h954118 or coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq) begin - case (k__h954121) + case (k__h954118) 1'd0: SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__1491_co_ETC___d21524 = coreFix_aluExe_0_rsAlu$canEnq; @@ -44590,7 +44603,7 @@ module mkCore(CLK, 11'd1194; endcase end - always@(idx__h978724 or + always@(idx__h978721 or fetchStage$pipelines_0_canDeq or NOT_fetchStage_pipelines_0_first__0544_BITS_26_ETC___d21951 or coreFix_aluExe_0_rsAlu$canEnq or @@ -44600,7 +44613,7 @@ module mkCore(CLK, fetchStage_pipelines_0_first__0544_BITS_268_TO_ETC___d21956 or coreFix_aluExe_1_rsAlu$canEnq) begin - case (idx__h978724) + case (idx__h978721) 1'd0: SEL_ARR_fetchStage_pipelines_0_canDeq__0542_AN_ETC___d21979 = fetchStage$pipelines_0_canDeq && @@ -44704,15 +44717,15 @@ module mkCore(CLK, regRenamingTable_rename_1_canRename__1585_AND__ETC___d21941; endcase end - always@(k__h954121 or + always@(k__h954118 or coreFix_aluExe_0_rsAlu$RDY_enq or coreFix_aluExe_1_rsAlu$RDY_enq) begin - case (k__h954121) + case (k__h954118) 1'd0: - CASE_k54121_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q268 = + CASE_k54118_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q268 = coreFix_aluExe_0_rsAlu$RDY_enq; 1'd1: - CASE_k54121_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q268 = + CASE_k54118_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q268 = coreFix_aluExe_1_rsAlu$RDY_enq; endcase end @@ -44730,7 +44743,7 @@ module mkCore(CLK, always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or IF_fetchStage_pipelines_0_first__0544_BITS_265_ETC___d21574 or - regRenamingTable_RDY_rename_0_getRename__1315__ETC___d22153 or + regRenamingTable_RDY_rename_0_getRename__1316__ETC___d22153 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq or coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_enq or regRenamingTable$RDY_rename_0_getRename) @@ -44745,10 +44758,10 @@ module mkCore(CLK, fetchStage$pipelines_0_first[268:266] != 3'd2 || !coreFix_memExe_rsMem$canEnq || IF_fetchStage_pipelines_0_first__0544_BITS_265_ETC___d21574 || - regRenamingTable_RDY_rename_0_getRename__1315__ETC___d22153; + regRenamingTable_RDY_rename_0_getRename__1316__ETC___d22153; endcase end - always@(idx__h978724 or + always@(idx__h978721 or fetchStage$pipelines_0_canDeq or fetchStage$pipelines_0_first or specTagManager$canClaim or @@ -44758,7 +44771,7 @@ module mkCore(CLK, NOT_fetchStage_pipelines_0_first__0544_BITS_26_ETC___d22210 or coreFix_aluExe_1_rsAlu$canEnq) begin - case (idx__h978724) + case (idx__h978721) 1'd0: SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__054_ETC___d22215 = (!fetchStage$pipelines_0_canDeq || @@ -44851,17 +44864,6 @@ module mkCore(CLK, NOT_fetchStage_pipelines_0_canDeq__0542_0543_O_ETC___d22249; endcase end - always@(fetchStage$pipelines_0_first or - coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag) - begin - case (fetchStage$pipelines_0_first[265:263]) - 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__0544_BITS_265_ETC___d22360 = - !coreFix_memExe_lsq$enqLdTag[5]; - default: IF_fetchStage_pipelines_0_first__0544_BITS_265_ETC___d22360 = - !coreFix_memExe_lsq$enqStTag[5]; - endcase - end always@(fetchStage$pipelines_0_first or coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag) begin @@ -44878,10 +44880,10 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[265:263]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__0544_BITS_265_ETC___d22366 = - coreFix_memExe_lsq$enqLdTag[3:0]; - default: IF_fetchStage_pipelines_0_first__0544_BITS_265_ETC___d22366 = - coreFix_memExe_lsq$enqStTag[3:0]; + IF_fetchStage_pipelines_0_first__0544_BITS_265_ETC___d22360 = + !coreFix_memExe_lsq$enqLdTag[5]; + default: IF_fetchStage_pipelines_0_first__0544_BITS_265_ETC___d22360 = + !coreFix_memExe_lsq$enqStTag[5]; endcase end always@(fetchStage$pipelines_0_first or @@ -44895,6 +44897,17 @@ module mkCore(CLK, coreFix_memExe_lsq$enqStTag[4:0]; endcase end + always@(fetchStage$pipelines_0_first or + coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag) + begin + case (fetchStage$pipelines_0_first[265:263]) + 3'd0, 3'd2: + IF_fetchStage_pipelines_0_first__0544_BITS_265_ETC___d22366 = + coreFix_memExe_lsq$enqLdTag[3:0]; + default: IF_fetchStage_pipelines_0_first__0544_BITS_265_ETC___d22366 = + coreFix_memExe_lsq$enqStTag[3:0]; + endcase + end always@(fetchStage$pipelines_1_first or coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag) begin @@ -44965,102 +44978,134 @@ module mkCore(CLK, csrf_rg_dcsr[12]; endcase end + always@(commitStage_commitTrap or + _0b0_CONCAT_csrf_mideleg_11_reg_read__6363_6364_ETC___d23021 or + csrf_medeleg_28_26_reg or + _0b0_CONCAT_csrf_medeleg_28_26_reg_read__6352_6_ETC___d23018) + begin + case (commitStage_commitTrap[44:43]) + 2'd0: + CASE_commitStage_commitTrap_BITS_44_TO_43_0_cs_ETC__q276 = + csrf_medeleg_28_26_reg[2]; + 2'd1: + CASE_commitStage_commitTrap_BITS_44_TO_43_0_cs_ETC__q276 = + _0b0_CONCAT_csrf_medeleg_28_26_reg_read__6352_6_ETC___d23018; + default: CASE_commitStage_commitTrap_BITS_44_TO_43_0_cs_ETC__q276 = + _0b0_CONCAT_csrf_mideleg_11_reg_read__6363_6364_ETC___d23021; + endcase + end + always@(commitStage_commitTrap or + _0b0_CONCAT_csrf_mideleg_11_reg_read__6363_6364_ETC___d23021 or + csrf_medeleg_28_26_reg or + _0b0_CONCAT_csrf_medeleg_28_26_reg_read__6352_6_ETC___d23018) + begin + case (commitStage_commitTrap[44:43]) + 2'd0: + CASE_commitStage_commitTrap_BITS_44_TO_43_0_NO_ETC__q277 = + !csrf_medeleg_28_26_reg[2]; + 2'd1: + CASE_commitStage_commitTrap_BITS_44_TO_43_0_NO_ETC__q277 = + !_0b0_CONCAT_csrf_medeleg_28_26_reg_read__6352_6_ETC___d23018; + default: CASE_commitStage_commitTrap_BITS_44_TO_43_0_NO_ETC__q277 = + !_0b0_CONCAT_csrf_mideleg_11_reg_read__6363_6364_ETC___d23021; + endcase + end always@(rob$deqPort_0_deq_data) begin case (rob$deqPort_0_deq_data[287:276]) 12'd1: - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 = 6'd0; + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 = 6'd0; 12'd2: - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 = 6'd1; + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 = 6'd1; 12'd3: - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 = 6'd2; + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 = 6'd2; 12'd256: - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 = 6'd8; + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 = 6'd8; 12'd260: - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 = 6'd9; + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 = 6'd9; 12'd261: - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 = 6'd10; + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 = 6'd10; 12'd262: - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 = 6'd11; + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 = 6'd11; 12'd320: - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 = 6'd12; + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 = 6'd12; 12'd321: - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 = 6'd13; + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 = 6'd13; 12'd322: - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 = 6'd14; + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 = 6'd14; 12'd323: - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 = 6'd15; + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 = 6'd15; 12'd324: - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 = 6'd16; + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 = 6'd16; 12'd384: - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 = 6'd17; + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 = 6'd17; 12'd768: - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 = 6'd19; + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 = 6'd19; 12'd769: - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 = 6'd20; + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 = 6'd20; 12'd770: - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 = 6'd21; + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 = 6'd21; 12'd771: - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 = 6'd22; + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 = 6'd22; 12'd772: - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 = 6'd23; + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 = 6'd23; 12'd773: - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 = 6'd24; + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 = 6'd24; 12'd774: - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 = 6'd25; + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 = 6'd25; 12'd832: - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 = 6'd26; + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 = 6'd26; 12'd833: - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 = 6'd27; + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 = 6'd27; 12'd834: - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 = 6'd28; + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 = 6'd28; 12'd835: - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 = 6'd29; + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 = 6'd29; 12'd836: - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 = 6'd30; + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 = 6'd30; 12'd1952: - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 = 6'd38; + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 = 6'd38; 12'd1953: - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 = 6'd39; + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 = 6'd39; 12'd1954: - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 = 6'd40; + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 = 6'd40; 12'd1955: - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 = 6'd41; + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 = 6'd41; 12'd1968: - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 = 6'd42; + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 = 6'd42; 12'd1969: - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 = 6'd43; + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 = 6'd43; 12'd1970: - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 = 6'd44; + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 = 6'd44; 12'd1971: - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 = 6'd45; + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 = 6'd45; 12'd2048: - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 = 6'd6; + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 = 6'd6; 12'd2049: - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 = 6'd7; + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 = 6'd7; 12'd2496: - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 = 6'd18; + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 = 6'd18; 12'd2816: - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 = 6'd31; + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 = 6'd31; 12'd2818: - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 = 6'd32; + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 = 6'd32; 12'd3008: - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 = 6'd37; + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 = 6'd37; 12'd3072: - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 = 6'd3; + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 = 6'd3; 12'd3073: - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 = 6'd4; + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 = 6'd4; 12'd3074: - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 = 6'd5; + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 = 6'd5; 12'd3857: - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 = 6'd33; + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 = 6'd33; 12'd3858: - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 = 6'd34; + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 = 6'd34; 12'd3859: - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 = 6'd35; + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 = 6'd35; 12'd3860: - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 = 6'd36; - default: IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 = + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 = 6'd36; + default: IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 = 6'd46; endcase end @@ -45068,26 +45113,26 @@ module mkCore(CLK, begin case (rob$deqPort_0_deq_data[293:289]) 5'd0: - IF_rob_deqPort_0_deq_data__2632_BIT_294_3835_T_ETC___d23857 = 4'd0; + IF_rob_deqPort_0_deq_data__2632_BIT_294_3837_T_ETC___d23859 = 4'd0; 5'd1: - IF_rob_deqPort_0_deq_data__2632_BIT_294_3835_T_ETC___d23857 = 4'd1; + IF_rob_deqPort_0_deq_data__2632_BIT_294_3837_T_ETC___d23859 = 4'd1; 5'd12: - IF_rob_deqPort_0_deq_data__2632_BIT_294_3835_T_ETC___d23857 = 4'd2; + IF_rob_deqPort_0_deq_data__2632_BIT_294_3837_T_ETC___d23859 = 4'd2; 5'd13: - IF_rob_deqPort_0_deq_data__2632_BIT_294_3835_T_ETC___d23857 = 4'd3; + IF_rob_deqPort_0_deq_data__2632_BIT_294_3837_T_ETC___d23859 = 4'd3; 5'd14: - IF_rob_deqPort_0_deq_data__2632_BIT_294_3835_T_ETC___d23857 = 4'd4; + IF_rob_deqPort_0_deq_data__2632_BIT_294_3837_T_ETC___d23859 = 4'd4; 5'd15: - IF_rob_deqPort_0_deq_data__2632_BIT_294_3835_T_ETC___d23857 = 4'd5; + IF_rob_deqPort_0_deq_data__2632_BIT_294_3837_T_ETC___d23859 = 4'd5; 5'd28: - IF_rob_deqPort_0_deq_data__2632_BIT_294_3835_T_ETC___d23857 = 4'd6; + IF_rob_deqPort_0_deq_data__2632_BIT_294_3837_T_ETC___d23859 = 4'd6; 5'd29: - IF_rob_deqPort_0_deq_data__2632_BIT_294_3835_T_ETC___d23857 = 4'd7; + IF_rob_deqPort_0_deq_data__2632_BIT_294_3837_T_ETC___d23859 = 4'd7; 5'd30: - IF_rob_deqPort_0_deq_data__2632_BIT_294_3835_T_ETC___d23857 = 4'd8; + IF_rob_deqPort_0_deq_data__2632_BIT_294_3837_T_ETC___d23859 = 4'd8; 5'd31: - IF_rob_deqPort_0_deq_data__2632_BIT_294_3835_T_ETC___d23857 = 4'd9; - default: IF_rob_deqPort_0_deq_data__2632_BIT_294_3835_T_ETC___d23857 = + IF_rob_deqPort_0_deq_data__2632_BIT_294_3837_T_ETC___d23859 = 4'd9; + default: IF_rob_deqPort_0_deq_data__2632_BIT_294_3837_T_ETC___d23859 = 4'd10; endcase end @@ -45095,8 +45140,8 @@ module mkCore(CLK, begin case (csrf_sepcc_reg_data_rl[52:35]) 18'd262142, 18'd262143: - CASE_csrf_sepcc_reg_data_rl_BITS_52_TO_35_2621_ETC__q276 = 18'd0; - default: CASE_csrf_sepcc_reg_data_rl_BITS_52_TO_35_2621_ETC__q276 = + CASE_csrf_sepcc_reg_data_rl_BITS_52_TO_35_2621_ETC__q278 = 18'd0; + default: CASE_csrf_sepcc_reg_data_rl_BITS_52_TO_35_2621_ETC__q278 = ~csrf_sepcc_reg_data_rl[52:35]; endcase end @@ -45104,8 +45149,8 @@ module mkCore(CLK, begin case (csrf_mepcc_reg_data_rl[52:35]) 18'd262142, 18'd262143: - CASE_csrf_mepcc_reg_data_rl_BITS_52_TO_35_2621_ETC__q277 = 18'd0; - default: CASE_csrf_mepcc_reg_data_rl_BITS_52_TO_35_2621_ETC__q277 = + CASE_csrf_mepcc_reg_data_rl_BITS_52_TO_35_2621_ETC__q279 = 18'd0; + default: CASE_csrf_mepcc_reg_data_rl_BITS_52_TO_35_2621_ETC__q279 = ~csrf_mepcc_reg_data_rl[52:35]; endcase end @@ -45115,10 +45160,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q278 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q280 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[515]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q278 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q280 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[515]; endcase end @@ -45128,10 +45173,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q279 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q281 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[514]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q279 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q281 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[514]; endcase end @@ -45141,13 +45186,43 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q280 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q282 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[513]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q280 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q282 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[513]; endcase end + always@(coreFix_memExe_forwardQ_deqP or + coreFix_memExe_forwardQ_data_0 or coreFix_memExe_forwardQ_data_1) + begin + case (coreFix_memExe_forwardQ_deqP) + 1'd0: + SEL_ARR_coreFix_memExe_forwardQ_data_0_224_BIT_ETC___d2238 = + coreFix_memExe_forwardQ_data_0[127:64]; + 1'd1: + SEL_ARR_coreFix_memExe_forwardQ_data_0_224_BIT_ETC___d2238 = + coreFix_memExe_forwardQ_data_1[127:64]; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd0: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14974 = + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]; + 3'd1: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14974 = 3'd4; + 3'd2: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14974 = 3'd3; + 3'd3: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14974 = 3'd2; + 3'd4: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14974 = 3'd1; + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14974 = + 3'd0; + endcase + end always@(coreFix_memExe_memRespLdQ_deqP or coreFix_memExe_memRespLdQ_data_0 or coreFix_memExe_memRespLdQ_data_1) @@ -45174,18 +45249,6 @@ module mkCore(CLK, coreFix_memExe_memRespLdQ_data_1[63:0]; endcase end - always@(coreFix_memExe_forwardQ_deqP or - coreFix_memExe_forwardQ_data_0 or coreFix_memExe_forwardQ_data_1) - begin - case (coreFix_memExe_forwardQ_deqP) - 1'd0: - SEL_ARR_coreFix_memExe_forwardQ_data_0_224_BIT_ETC___d2238 = - coreFix_memExe_forwardQ_data_0[127:64]; - 1'd1: - SEL_ARR_coreFix_memExe_forwardQ_data_0_224_BIT_ETC___d2238 = - coreFix_memExe_forwardQ_data_1[127:64]; - endcase - end always@(coreFix_memExe_forwardQ_deqP or coreFix_memExe_forwardQ_data_0 or coreFix_memExe_forwardQ_data_1) begin @@ -45199,34 +45262,16 @@ module mkCore(CLK, endcase end always@(commitStage_commitTrap or - SEXT__0_CONCAT_IF_INV_commitStage_commitTrap_2_ETC___d23053) + SEXT__0_CONCAT_IF_INV_commitStage_commitTrap_2_ETC___d23054) begin case (commitStage_commitTrap[36:32]) 5'd0, 5'd3: - trap_val__h1007620 = - SEXT__0_CONCAT_IF_INV_commitStage_commitTrap_2_ETC___d23053; + trap_val__h1007654 = + SEXT__0_CONCAT_IF_INV_commitStage_commitTrap_2_ETC___d23054; 5'd1, 5'd4, 5'd5, 5'd6, 5'd7, 5'd12, 5'd13, 5'd15: - trap_val__h1007620 = commitStage_commitTrap[108:45]; - 5'd2: trap_val__h1007620 = { 32'd0, commitStage_commitTrap[31:0] }; - default: trap_val__h1007620 = 64'd0; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd0: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14974 = - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]; - 3'd1: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14974 = 3'd4; - 3'd2: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14974 = 3'd3; - 3'd3: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14974 = 3'd2; - 3'd4: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14974 = 3'd1; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14974 = - 3'd0; + trap_val__h1007654 = commitStage_commitTrap[108:45]; + 5'd2: trap_val__h1007654 = { 32'd0, commitStage_commitTrap[31:0] }; + default: trap_val__h1007654 = 64'd0; endcase end always@(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq or @@ -45459,35 +45504,35 @@ module mkCore(CLK, begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd4, 3'd3, 3'd2, 3'd1, 3'd0: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q281 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q283 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q281 = 3'd7; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q283 = 3'd7; endcase end always@(coreFix_aluExe_1_regToExeQ$first) begin case (coreFix_aluExe_1_regToExeQ$first[791:789]) 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_791_ETC__q282 = + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_791_ETC__q284 = coreFix_aluExe_1_regToExeQ$first[791:789]; - default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_791_ETC__q282 = 3'd7; + default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_791_ETC__q284 = 3'd7; endcase end always@(coreFix_aluExe_1_regToExeQ$first or - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_791_ETC__q282) + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_791_ETC__q284) begin case (coreFix_aluExe_1_regToExeQ$first[817:815]) 3'd0, 3'd1, 3'd2, 3'd3: - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_817_ETC__q283 = + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_817_ETC__q285 = coreFix_aluExe_1_regToExeQ$first[817:788]; 3'd4: - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_817_ETC__q283 = + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_817_ETC__q285 = { coreFix_aluExe_1_regToExeQ$first[817:815], 18'h2AAAA, coreFix_aluExe_1_regToExeQ$first[796:792], - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_791_ETC__q282, + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_791_ETC__q284, coreFix_aluExe_1_regToExeQ$first[788] }; - default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_817_ETC__q283 = + default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_817_ETC__q285 = 30'd715827882; endcase end @@ -45496,13 +45541,13 @@ module mkCore(CLK, begin case (coreFix_aluExe_1_regToExeQ$first[787:786]) 2'd0: - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_787_ETC__q284 = + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_787_ETC__q286 = coreFix_aluExe_1_regToExeQ$first[787:777]; 2'd1: - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_787_ETC__q284 = + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_787_ETC__q286 = { coreFix_aluExe_1_regToExeQ$first[787:786], IF_coreFix_aluExe_1_regToExeQ_first__7524_BITS_ETC___d17666 }; - default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_787_ETC__q284 = + default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_787_ETC__q286 = 11'd1194; endcase end @@ -45555,9 +45600,9 @@ module mkCore(CLK, 12'd3858, 12'd3859, 12'd3860: - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_728_ETC__q285 = + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_728_ETC__q287 = coreFix_aluExe_1_regToExeQ$first[728:717]; - default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_728_ETC__q285 = + default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_728_ETC__q287 = 12'd2303; endcase end @@ -45565,9 +45610,9 @@ module mkCore(CLK, begin case (coreFix_aluExe_1_regToExeQ$first[715:711]) 5'd0, 5'd1, 5'd12, 5'd13, 5'd14, 5'd15, 5'd28, 5'd29, 5'd30, 5'd31: - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_715_ETC__q286 = + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_715_ETC__q288 = coreFix_aluExe_1_regToExeQ$first[715:711]; - default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_715_ETC__q286 = + default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_715_ETC__q288 = 5'd10; endcase end @@ -45575,26 +45620,26 @@ module mkCore(CLK, begin case (coreFix_aluExe_0_regToExeQ$first[791:789]) 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_791_ETC__q287 = + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_791_ETC__q289 = coreFix_aluExe_0_regToExeQ$first[791:789]; - default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_791_ETC__q287 = 3'd7; + default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_791_ETC__q289 = 3'd7; endcase end always@(coreFix_aluExe_0_regToExeQ$first or - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_791_ETC__q287) + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_791_ETC__q289) begin case (coreFix_aluExe_0_regToExeQ$first[817:815]) 3'd0, 3'd1, 3'd2, 3'd3: - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_817_ETC__q288 = + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_817_ETC__q290 = coreFix_aluExe_0_regToExeQ$first[817:788]; 3'd4: - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_817_ETC__q288 = + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_817_ETC__q290 = { coreFix_aluExe_0_regToExeQ$first[817:815], 18'h2AAAA, coreFix_aluExe_0_regToExeQ$first[796:792], - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_791_ETC__q287, + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_791_ETC__q289, coreFix_aluExe_0_regToExeQ$first[788] }; - default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_817_ETC__q288 = + default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_817_ETC__q290 = 30'd715827882; endcase end @@ -45603,13 +45648,13 @@ module mkCore(CLK, begin case (coreFix_aluExe_0_regToExeQ$first[787:786]) 2'd0: - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_787_ETC__q289 = + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_787_ETC__q291 = coreFix_aluExe_0_regToExeQ$first[787:777]; 2'd1: - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_787_ETC__q289 = + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_787_ETC__q291 = { coreFix_aluExe_0_regToExeQ$first[787:786], IF_coreFix_aluExe_0_regToExeQ_first__9699_BITS_ETC___d19841 }; - default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_787_ETC__q289 = + default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_787_ETC__q291 = 11'd1194; endcase end @@ -45662,9 +45707,9 @@ module mkCore(CLK, 12'd3858, 12'd3859, 12'd3860: - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_728_ETC__q290 = + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_728_ETC__q292 = coreFix_aluExe_0_regToExeQ$first[728:717]; - default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_728_ETC__q290 = + default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_728_ETC__q292 = 12'd2303; endcase end @@ -45672,9 +45717,9 @@ module mkCore(CLK, begin case (coreFix_aluExe_0_regToExeQ$first[715:711]) 5'd0, 5'd1, 5'd12, 5'd13, 5'd14, 5'd15, 5'd28, 5'd29, 5'd30, 5'd31: - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_715_ETC__q291 = + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_715_ETC__q293 = coreFix_aluExe_0_regToExeQ$first[715:711]; - default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_715_ETC__q291 = + default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_715_ETC__q293 = 5'd10; endcase end @@ -45741,9 +45786,9 @@ module mkCore(CLK, 5'd24, 5'd25, 5'd26: - CASE_capChecks_179_BITS_4_TO_0_0_capChecks_179_ETC__q292 = + CASE_capChecks_179_BITS_4_TO_0_0_capChecks_179_ETC__q294 = capChecks___d4179[4:0]; - default: CASE_capChecks_179_BITS_4_TO_0_0_capChecks_179_ETC__q292 = + default: CASE_capChecks_179_BITS_4_TO_0_0_capChecks_179_ETC__q294 = 5'd27; endcase end @@ -45753,10 +45798,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q293 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q295 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[514:451]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q293 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q295 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[514:451]; endcase end @@ -45766,10 +45811,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q294 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q296 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[450:387]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q294 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q296 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[450:387]; endcase end @@ -45779,10 +45824,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q295 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q297 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[386:323]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q295 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q297 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[386:323]; endcase end @@ -45792,10 +45837,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q296 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q298 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[322:259]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q296 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q298 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[322:259]; endcase end @@ -45805,10 +45850,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q297 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q299 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[258:195]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q297 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q299 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[258:195]; endcase end @@ -45818,10 +45863,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q298 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q300 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[194:131]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q298 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q300 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[194:131]; endcase end @@ -45831,10 +45876,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q299 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q301 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[511:448]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q299 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q301 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[511:448]; endcase end @@ -45844,10 +45889,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q300 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q302 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[447:384]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q300 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q302 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[447:384]; endcase end @@ -45857,10 +45902,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q301 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q303 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[383:320]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q301 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q303 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[383:320]; endcase end @@ -45870,10 +45915,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q302 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q304 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[319:256]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q302 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q304 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[319:256]; endcase end @@ -45883,10 +45928,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q303 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q305 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[255:192]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q303 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q305 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[255:192]; endcase end @@ -45896,10 +45941,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q304 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q306 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[191:128]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q304 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q306 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[191:128]; endcase end @@ -45909,10 +45954,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q305 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q307 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[515]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q305 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q307 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[515]; endcase end @@ -45922,10 +45967,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q306 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q308 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[130:67]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q306 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q308 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[130:67]; endcase end @@ -45935,10 +45980,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q307 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q309 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[66:3]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q307 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q309 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[66:3]; endcase end @@ -45948,10 +45993,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q308 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q310 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[512]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q308 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q310 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[512]; endcase end @@ -45961,10 +46006,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q309 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q311 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[127:64]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q309 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q311 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[127:64]; endcase end @@ -45974,10 +46019,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q310 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q312 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[63:0]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q310 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q312 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[63:0]; endcase end @@ -45987,10 +46032,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q311 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q313 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[582:519]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q311 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q313 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[582:519]; endcase end @@ -46000,10 +46045,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q312 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q314 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[518:517]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q312 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q314 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[518:517]; endcase end @@ -46013,10 +46058,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q313 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q315 = !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[516]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q313 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q315 = !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[516]; endcase end @@ -46026,10 +46071,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q314 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q316 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[521:520]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q314 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q316 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[521:520]; endcase end @@ -46039,10 +46084,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q315 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q317 = !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[519]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q315 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q317 = !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[519]; endcase end @@ -46073,10 +46118,10 @@ module mkCore(CLK, begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[229:228]) 2'd0, 2'd1: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q316 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q318 = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit != 2'd0 && coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_enq; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q316 = + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q318 = coreFix_fpuMulDivExe_0_mulDivExec_divQ_RDY_enq_ETC___d12684; endcase end @@ -46086,10 +46131,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q317 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q319 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[5:4]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q317 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q319 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[5:4]; endcase end @@ -46099,10 +46144,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q318 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q320 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[3]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q318 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q320 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[3]; endcase end @@ -46112,10 +46157,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q319 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q321 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[2:0]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q319 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q321 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[2:0]; endcase end @@ -46125,10 +46170,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q320 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q322 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[71:8]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q320 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q322 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[71:8]; endcase end @@ -46138,10 +46183,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q321 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q323 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[7:6]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q321 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q323 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[7:6]; endcase end @@ -46151,10 +46196,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q322 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q324 = !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[586]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q322 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q324 = !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[586]; endcase end @@ -46164,10 +46209,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q323 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q325 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[586]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q323 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q325 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[586]; endcase end @@ -46175,9 +46220,9 @@ module mkCore(CLK, begin case (rob$deqPort_0_deq_data[264:261]) 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: - CASE_robdeqPort_0_deq_data_BITS_264_TO_261_0__ETC__q324 = + CASE_robdeqPort_0_deq_data_BITS_264_TO_261_0__ETC__q326 = rob$deqPort_0_deq_data[264:261]; - default: CASE_robdeqPort_0_deq_data_BITS_264_TO_261_0__ETC__q324 = + default: CASE_robdeqPort_0_deq_data_BITS_264_TO_261_0__ETC__q326 = 4'd15; endcase end @@ -46207,9 +46252,9 @@ module mkCore(CLK, 5'd24, 5'd25, 5'd26: - CASE_robdeqPort_0_deq_data_BITS_265_TO_261_0__ETC__q325 = + CASE_robdeqPort_0_deq_data_BITS_265_TO_261_0__ETC__q327 = rob$deqPort_0_deq_data[265:261]; - default: CASE_robdeqPort_0_deq_data_BITS_265_TO_261_0__ETC__q325 = + default: CASE_robdeqPort_0_deq_data_BITS_265_TO_261_0__ETC__q327 = 5'd27; endcase end @@ -46230,31 +46275,31 @@ module mkCore(CLK, 5'd12, 5'd13, 5'd15: - CASE_robdeqPort_0_deq_data_BITS_265_TO_261_0__ETC__q326 = + CASE_robdeqPort_0_deq_data_BITS_265_TO_261_0__ETC__q328 = rob$deqPort_0_deq_data[265:261]; - default: CASE_robdeqPort_0_deq_data_BITS_265_TO_261_0__ETC__q326 = + default: CASE_robdeqPort_0_deq_data_BITS_265_TO_261_0__ETC__q328 = 5'd28; endcase end always@(rob$deqPort_0_deq_data or - CASE_robdeqPort_0_deq_data_BITS_264_TO_261_0__ETC__q324 or - CASE_robdeqPort_0_deq_data_BITS_265_TO_261_0__ETC__q325 or - CASE_robdeqPort_0_deq_data_BITS_265_TO_261_0__ETC__q326) + CASE_robdeqPort_0_deq_data_BITS_264_TO_261_0__ETC__q326 or + CASE_robdeqPort_0_deq_data_BITS_265_TO_261_0__ETC__q327 or + CASE_robdeqPort_0_deq_data_BITS_265_TO_261_0__ETC__q328) begin case (rob$deqPort_0_deq_data[273:272]) 2'd0: - CASE_robdeqPort_0_deq_data_BITS_273_TO_272_0__ETC__q327 = + CASE_robdeqPort_0_deq_data_BITS_273_TO_272_0__ETC__q329 = { 2'd0, rob$deqPort_0_deq_data[271:266], - CASE_robdeqPort_0_deq_data_BITS_265_TO_261_0__ETC__q325 }; + CASE_robdeqPort_0_deq_data_BITS_265_TO_261_0__ETC__q327 }; 2'd1: - CASE_robdeqPort_0_deq_data_BITS_273_TO_272_0__ETC__q327 = + CASE_robdeqPort_0_deq_data_BITS_273_TO_272_0__ETC__q329 = { rob$deqPort_0_deq_data[273:272], 6'h2A, - CASE_robdeqPort_0_deq_data_BITS_265_TO_261_0__ETC__q326 }; - default: CASE_robdeqPort_0_deq_data_BITS_273_TO_272_0__ETC__q327 = + CASE_robdeqPort_0_deq_data_BITS_265_TO_261_0__ETC__q328 }; + default: CASE_robdeqPort_0_deq_data_BITS_273_TO_272_0__ETC__q329 = { 9'd298, - CASE_robdeqPort_0_deq_data_BITS_264_TO_261_0__ETC__q324 }; + CASE_robdeqPort_0_deq_data_BITS_264_TO_261_0__ETC__q326 }; endcase end always@(coreFix_memExe_memRespLdQ_deqP or @@ -46263,10 +46308,10 @@ module mkCore(CLK, begin case (coreFix_memExe_memRespLdQ_deqP) 1'd0: - CASE_coreFix_memExe_memRespLdQ_deqP_0_coreFix__ETC__q328 = + CASE_coreFix_memExe_memRespLdQ_deqP_0_coreFix__ETC__q330 = coreFix_memExe_memRespLdQ_data_0[128]; 1'd1: - CASE_coreFix_memExe_memRespLdQ_deqP_0_coreFix__ETC__q328 = + CASE_coreFix_memExe_memRespLdQ_deqP_0_coreFix__ETC__q330 = coreFix_memExe_memRespLdQ_data_1[128]; endcase end @@ -46275,10 +46320,10 @@ module mkCore(CLK, begin case (coreFix_memExe_forwardQ_deqP) 1'd0: - CASE_coreFix_memExe_forwardQ_deqP_0_coreFix_me_ETC__q329 = + CASE_coreFix_memExe_forwardQ_deqP_0_coreFix_me_ETC__q331 = coreFix_memExe_forwardQ_data_0[128]; 1'd1: - CASE_coreFix_memExe_forwardQ_deqP_0_coreFix_me_ETC__q329 = + CASE_coreFix_memExe_forwardQ_deqP_0_coreFix_me_ETC__q331 = coreFix_memExe_forwardQ_data_1[128]; endcase end @@ -46308,9 +46353,9 @@ module mkCore(CLK, 5'd24, 5'd25, 5'd26: - CASE_f_csr_reqsD_OUT_BITS_9_TO_5_0_f_csr_reqs_ETC__q330 = + CASE_f_csr_reqsD_OUT_BITS_9_TO_5_0_f_csr_reqs_ETC__q332 = f_csr_reqs$D_OUT[9:5]; - default: CASE_f_csr_reqsD_OUT_BITS_9_TO_5_0_f_csr_reqs_ETC__q330 = + default: CASE_f_csr_reqsD_OUT_BITS_9_TO_5_0_f_csr_reqs_ETC__q332 = 5'd27; endcase end @@ -46340,9 +46385,9 @@ module mkCore(CLK, 5'd24, 5'd25, 5'd26: - CASE_robdeqPort_0_deq_data_BITS_95_TO_326_BITS_ETC__q331 = + CASE_robdeqPort_0_deq_data_BITS_95_TO_326_BITS_ETC__q333 = robdeqPort_0_deq_data_BITS_95_TO_32__q16[9:5]; - default: CASE_robdeqPort_0_deq_data_BITS_95_TO_326_BITS_ETC__q331 = + default: CASE_robdeqPort_0_deq_data_BITS_95_TO_326_BITS_ETC__q333 = 5'd27; endcase end @@ -46356,17 +46401,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[123:119]) - 5'd1: thin_addrBits__h864889 = csrf_ddc_reg[85:72]; - 5'd12: thin_addrBits__h864889 = csrf_stcc_reg[85:72]; - 5'd13: thin_addrBits__h864889 = csrf_stdc_reg[85:72]; - 5'd14: thin_addrBits__h864889 = csrf_sScratchC_reg[85:72]; + 5'd1: thin_addrBits__h864887 = csrf_ddc_reg[85:72]; + 5'd12: thin_addrBits__h864887 = csrf_stcc_reg[85:72]; + 5'd13: thin_addrBits__h864887 = csrf_stdc_reg[85:72]; + 5'd14: thin_addrBits__h864887 = csrf_sScratchC_reg[85:72]; 5'd15: - thin_addrBits__h864889 = + thin_addrBits__h864887 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16271; - 5'd28: thin_addrBits__h864889 = csrf_mtcc_reg[85:72]; - 5'd29: thin_addrBits__h864889 = csrf_mtdc_reg[85:72]; - 5'd30: thin_addrBits__h864889 = csrf_mScratchC_reg[85:72]; - default: thin_addrBits__h864889 = + 5'd28: thin_addrBits__h864887 = csrf_mtcc_reg[85:72]; + 5'd29: thin_addrBits__h864887 = csrf_mtdc_reg[85:72]; + 5'd30: thin_addrBits__h864887 = csrf_mScratchC_reg[85:72]; + default: thin_addrBits__h864887 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16423; endcase end @@ -46380,17 +46425,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[123:119]) - 5'd1: thin_addrBits__h906787 = csrf_ddc_reg[85:72]; - 5'd12: thin_addrBits__h906787 = csrf_stcc_reg[85:72]; - 5'd13: thin_addrBits__h906787 = csrf_stdc_reg[85:72]; - 5'd14: thin_addrBits__h906787 = csrf_sScratchC_reg[85:72]; + 5'd1: thin_addrBits__h906784 = csrf_ddc_reg[85:72]; + 5'd12: thin_addrBits__h906784 = csrf_stcc_reg[85:72]; + 5'd13: thin_addrBits__h906784 = csrf_stdc_reg[85:72]; + 5'd14: thin_addrBits__h906784 = csrf_sScratchC_reg[85:72]; 5'd15: - thin_addrBits__h906787 = + thin_addrBits__h906784 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16271; - 5'd28: thin_addrBits__h906787 = csrf_mtcc_reg[85:72]; - 5'd29: thin_addrBits__h906787 = csrf_mtdc_reg[85:72]; - 5'd30: thin_addrBits__h906787 = csrf_mScratchC_reg[85:72]; - default: thin_addrBits__h906787 = + 5'd28: thin_addrBits__h906784 = csrf_mtcc_reg[85:72]; + 5'd29: thin_addrBits__h906784 = csrf_mtdc_reg[85:72]; + 5'd30: thin_addrBits__h906784 = csrf_mScratchC_reg[85:72]; + default: thin_addrBits__h906784 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16423; endcase end @@ -46404,17 +46449,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[123:119]) - 5'd1: thin_bounds_baseBits__h866837 = csrf_ddc_reg[13:0]; - 5'd12: thin_bounds_baseBits__h866837 = csrf_stcc_reg[13:0]; - 5'd13: thin_bounds_baseBits__h866837 = csrf_stdc_reg[13:0]; - 5'd14: thin_bounds_baseBits__h866837 = csrf_sScratchC_reg[13:0]; + 5'd1: thin_bounds_baseBits__h866835 = csrf_ddc_reg[13:0]; + 5'd12: thin_bounds_baseBits__h866835 = csrf_stcc_reg[13:0]; + 5'd13: thin_bounds_baseBits__h866835 = csrf_stdc_reg[13:0]; + 5'd14: thin_bounds_baseBits__h866835 = csrf_sScratchC_reg[13:0]; 5'd15: - thin_bounds_baseBits__h866837 = + thin_bounds_baseBits__h866835 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16275; - 5'd28: thin_bounds_baseBits__h866837 = csrf_mtcc_reg[13:0]; - 5'd29: thin_bounds_baseBits__h866837 = csrf_mtdc_reg[13:0]; - 5'd30: thin_bounds_baseBits__h866837 = csrf_mScratchC_reg[13:0]; - default: thin_bounds_baseBits__h866837 = + 5'd28: thin_bounds_baseBits__h866835 = csrf_mtcc_reg[13:0]; + 5'd29: thin_bounds_baseBits__h866835 = csrf_mtdc_reg[13:0]; + 5'd30: thin_bounds_baseBits__h866835 = csrf_mScratchC_reg[13:0]; + default: thin_bounds_baseBits__h866835 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16427; endcase end @@ -46428,17 +46473,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[123:119]) - 5'd1: thin_bounds_baseBits__h908193 = csrf_ddc_reg[13:0]; - 5'd12: thin_bounds_baseBits__h908193 = csrf_stcc_reg[13:0]; - 5'd13: thin_bounds_baseBits__h908193 = csrf_stdc_reg[13:0]; - 5'd14: thin_bounds_baseBits__h908193 = csrf_sScratchC_reg[13:0]; + 5'd1: thin_bounds_baseBits__h908190 = csrf_ddc_reg[13:0]; + 5'd12: thin_bounds_baseBits__h908190 = csrf_stcc_reg[13:0]; + 5'd13: thin_bounds_baseBits__h908190 = csrf_stdc_reg[13:0]; + 5'd14: thin_bounds_baseBits__h908190 = csrf_sScratchC_reg[13:0]; 5'd15: - thin_bounds_baseBits__h908193 = + thin_bounds_baseBits__h908190 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16275; - 5'd28: thin_bounds_baseBits__h908193 = csrf_mtcc_reg[13:0]; - 5'd29: thin_bounds_baseBits__h908193 = csrf_mtdc_reg[13:0]; - 5'd30: thin_bounds_baseBits__h908193 = csrf_mScratchC_reg[13:0]; - default: thin_bounds_baseBits__h908193 = + 5'd28: thin_bounds_baseBits__h908190 = csrf_mtcc_reg[13:0]; + 5'd29: thin_bounds_baseBits__h908190 = csrf_mtdc_reg[13:0]; + 5'd30: thin_bounds_baseBits__h908190 = csrf_mScratchC_reg[13:0]; + default: thin_bounds_baseBits__h908190 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16427; endcase end @@ -46452,17 +46497,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[123:119]) - 5'd1: thin_address__h864888 = csrf_ddc_reg[151:86]; - 5'd12: thin_address__h864888 = csrf_stcc_reg[151:86]; - 5'd13: thin_address__h864888 = csrf_stdc_reg[151:86]; - 5'd14: thin_address__h864888 = csrf_sScratchC_reg[151:86]; + 5'd1: thin_address__h864886 = csrf_ddc_reg[151:86]; + 5'd12: thin_address__h864886 = csrf_stcc_reg[151:86]; + 5'd13: thin_address__h864886 = csrf_stdc_reg[151:86]; + 5'd14: thin_address__h864886 = csrf_sScratchC_reg[151:86]; 5'd15: - thin_address__h864888 = + thin_address__h864886 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16295; - 5'd28: thin_address__h864888 = csrf_mtcc_reg[151:86]; - 5'd29: thin_address__h864888 = csrf_mtdc_reg[151:86]; - 5'd30: thin_address__h864888 = csrf_mScratchC_reg[151:86]; - default: thin_address__h864888 = + 5'd28: thin_address__h864886 = csrf_mtcc_reg[151:86]; + 5'd29: thin_address__h864886 = csrf_mtdc_reg[151:86]; + 5'd30: thin_address__h864886 = csrf_mScratchC_reg[151:86]; + default: thin_address__h864886 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16447; endcase end @@ -46476,289 +46521,289 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[123:119]) - 5'd1: thin_address__h906786 = csrf_ddc_reg[151:86]; - 5'd12: thin_address__h906786 = csrf_stcc_reg[151:86]; - 5'd13: thin_address__h906786 = csrf_stdc_reg[151:86]; - 5'd14: thin_address__h906786 = csrf_sScratchC_reg[151:86]; + 5'd1: thin_address__h906783 = csrf_ddc_reg[151:86]; + 5'd12: thin_address__h906783 = csrf_stcc_reg[151:86]; + 5'd13: thin_address__h906783 = csrf_stdc_reg[151:86]; + 5'd14: thin_address__h906783 = csrf_sScratchC_reg[151:86]; 5'd15: - thin_address__h906786 = + thin_address__h906783 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16295; - 5'd28: thin_address__h906786 = csrf_mtcc_reg[151:86]; - 5'd29: thin_address__h906786 = csrf_mtdc_reg[151:86]; - 5'd30: thin_address__h906786 = csrf_mScratchC_reg[151:86]; - default: thin_address__h906786 = + 5'd28: thin_address__h906783 = csrf_mtcc_reg[151:86]; + 5'd29: thin_address__h906783 = csrf_mtdc_reg[151:86]; + 5'd30: thin_address__h906783 = csrf_mScratchC_reg[151:86]; + default: thin_address__h906783 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16447; endcase end always@(f_csr_reqs$D_OUT or - fflags_csr__read__h855609 or - frm_csr__read__h855620 or - fcsr_csr__read__h855634 or - sstatus_csr__read__h855830 or - sie_csr__read__h855900 or + fflags_csr__read__h855607 or + frm_csr__read__h855618 or + fcsr_csr__read__h855632 or + sstatus_csr__read__h855828 or + sie_csr__read__h855898 or SEXT__0_CONCAT_csrf_stcc_reg_read__6237_BITS_8_ETC___d16261 or - scounteren_csr__read__h855988 or + scounteren_csr__read__h855986 or csrf_sscratch_csr or SEXT__0_CONCAT_IF_csrf_sepcc_reg_data_lat_0_wh_ETC___d16300 or - scause_csr__read__h856128 or + scause_csr__read__h856126 or csrf_stval_csr or - sip_csr__read__h856268 or - satp_csr__read__h856331 or - mstatus_csr__read__h856477 or - medeleg_csr__read__h856638 or - mideleg_csr__read__h856736 or - mie_csr__read__h856863 or + sip_csr__read__h856266 or + satp_csr__read__h856329 or + mstatus_csr__read__h856475 or + medeleg_csr__read__h856636 or + mideleg_csr__read__h856734 or + mie_csr__read__h856861 or SEXT__0_CONCAT_csrf_mtcc_reg_read__6389_BITS_8_ETC___d16413 or - mcounteren_csr__read__h857035 or + mcounteren_csr__read__h857033 or csrf_mscratch_csr or SEXT__0_CONCAT_IF_csrf_mepcc_reg_data_lat_0_wh_ETC___d16452 or - mcause_csr__read__h857301 or + mcause_csr__read__h857299 or csrf_mtval_csr or - mip_csr__read__h857540 or + mip_csr__read__h857538 or csrf_rg_tselect or - rg_tdata1__read__h858641 or + rg_tdata1__read__h858639 or csrf_rg_tdata2 or csrf_rg_tdata3 or csrf_rg_dcsr or SEXT__0_CONCAT_csrf_rg_dpc_read__6534_BITS_85__ETC___d16558 or csrf_rg_dscratch0 or csrf_rg_dscratch1 or - x_reg_ifc__read__h855739 or + x_reg_ifc__read__h855737 or csrf_mcycle_ehr_data_rl or - csrf_minstret_ehr_data_rl or x__h904219 or csrf_time_reg) + csrf_minstret_ehr_data_rl or x__h904216 or csrf_time_reg) begin case (f_csr_reqs$D_OUT[75:64]) - 12'd1: data_out__h1031472 = fflags_csr__read__h855609; - 12'd2: data_out__h1031472 = frm_csr__read__h855620; - 12'd3: data_out__h1031472 = fcsr_csr__read__h855634; - 12'd256: data_out__h1031472 = sstatus_csr__read__h855830; - 12'd260: data_out__h1031472 = sie_csr__read__h855900; + 12'd1: data_out__h1031505 = fflags_csr__read__h855607; + 12'd2: data_out__h1031505 = frm_csr__read__h855618; + 12'd3: data_out__h1031505 = fcsr_csr__read__h855632; + 12'd256: data_out__h1031505 = sstatus_csr__read__h855828; + 12'd260: data_out__h1031505 = sie_csr__read__h855898; 12'd261: - data_out__h1031472 = + data_out__h1031505 = SEXT__0_CONCAT_csrf_stcc_reg_read__6237_BITS_8_ETC___d16261; - 12'd262: data_out__h1031472 = scounteren_csr__read__h855988; - 12'd320: data_out__h1031472 = csrf_sscratch_csr; + 12'd262: data_out__h1031505 = scounteren_csr__read__h855986; + 12'd320: data_out__h1031505 = csrf_sscratch_csr; 12'd321: - data_out__h1031472 = + data_out__h1031505 = SEXT__0_CONCAT_IF_csrf_sepcc_reg_data_lat_0_wh_ETC___d16300; - 12'd322: data_out__h1031472 = scause_csr__read__h856128; - 12'd323: data_out__h1031472 = csrf_stval_csr; - 12'd324: data_out__h1031472 = sip_csr__read__h856268; - 12'd384: data_out__h1031472 = satp_csr__read__h856331; - 12'd768: data_out__h1031472 = mstatus_csr__read__h856477; - 12'd769: data_out__h1031472 = 64'h800000000014112D; - 12'd770: data_out__h1031472 = medeleg_csr__read__h856638; - 12'd771: data_out__h1031472 = mideleg_csr__read__h856736; - 12'd772: data_out__h1031472 = mie_csr__read__h856863; + 12'd322: data_out__h1031505 = scause_csr__read__h856126; + 12'd323: data_out__h1031505 = csrf_stval_csr; + 12'd324: data_out__h1031505 = sip_csr__read__h856266; + 12'd384: data_out__h1031505 = satp_csr__read__h856329; + 12'd768: data_out__h1031505 = mstatus_csr__read__h856475; + 12'd769: data_out__h1031505 = 64'h800000000014112D; + 12'd770: data_out__h1031505 = medeleg_csr__read__h856636; + 12'd771: data_out__h1031505 = mideleg_csr__read__h856734; + 12'd772: data_out__h1031505 = mie_csr__read__h856861; 12'd773: - data_out__h1031472 = + data_out__h1031505 = SEXT__0_CONCAT_csrf_mtcc_reg_read__6389_BITS_8_ETC___d16413; - 12'd774: data_out__h1031472 = mcounteren_csr__read__h857035; - 12'd832: data_out__h1031472 = csrf_mscratch_csr; + 12'd774: data_out__h1031505 = mcounteren_csr__read__h857033; + 12'd832: data_out__h1031505 = csrf_mscratch_csr; 12'd833: - data_out__h1031472 = + data_out__h1031505 = SEXT__0_CONCAT_IF_csrf_mepcc_reg_data_lat_0_wh_ETC___d16452; - 12'd834: data_out__h1031472 = mcause_csr__read__h857301; - 12'd835: data_out__h1031472 = csrf_mtval_csr; - 12'd836: data_out__h1031472 = mip_csr__read__h857540; - 12'd1952: data_out__h1031472 = csrf_rg_tselect; - 12'd1953: data_out__h1031472 = rg_tdata1__read__h858641; - 12'd1954: data_out__h1031472 = csrf_rg_tdata2; - 12'd1955: data_out__h1031472 = csrf_rg_tdata3; - 12'd1968: data_out__h1031472 = csrf_rg_dcsr; + 12'd834: data_out__h1031505 = mcause_csr__read__h857299; + 12'd835: data_out__h1031505 = csrf_mtval_csr; + 12'd836: data_out__h1031505 = mip_csr__read__h857538; + 12'd1952: data_out__h1031505 = csrf_rg_tselect; + 12'd1953: data_out__h1031505 = rg_tdata1__read__h858639; + 12'd1954: data_out__h1031505 = csrf_rg_tdata2; + 12'd1955: data_out__h1031505 = csrf_rg_tdata3; + 12'd1968: data_out__h1031505 = csrf_rg_dcsr; 12'd1969: - data_out__h1031472 = + data_out__h1031505 = SEXT__0_CONCAT_csrf_rg_dpc_read__6534_BITS_85__ETC___d16558; - 12'd1970: data_out__h1031472 = csrf_rg_dscratch0; - 12'd1971: data_out__h1031472 = csrf_rg_dscratch1; + 12'd1970: data_out__h1031505 = csrf_rg_dscratch0; + 12'd1971: data_out__h1031505 = csrf_rg_dscratch1; 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: - data_out__h1031472 = 64'd0; - 12'd2049: data_out__h1031472 = x_reg_ifc__read__h855739; - 12'd2816, 12'd3072: data_out__h1031472 = csrf_mcycle_ehr_data_rl; - 12'd2818, 12'd3074: data_out__h1031472 = csrf_minstret_ehr_data_rl; - 12'd3008: data_out__h1031472 = { 48'd0, x__h904219 }; - 12'd3073: data_out__h1031472 = csrf_time_reg; - default: data_out__h1031472 = 64'b0; + data_out__h1031505 = 64'd0; + 12'd2049: data_out__h1031505 = x_reg_ifc__read__h855737; + 12'd2816, 12'd3072: data_out__h1031505 = csrf_mcycle_ehr_data_rl; + 12'd2818, 12'd3074: data_out__h1031505 = csrf_minstret_ehr_data_rl; + 12'd3008: data_out__h1031505 = { 48'd0, x__h904216 }; + 12'd3073: data_out__h1031505 = csrf_time_reg; + default: data_out__h1031505 = 64'b0; endcase end always@(coreFix_aluExe_1_dispToRegQ$first or - fflags_csr__read__h855609 or - frm_csr__read__h855620 or - fcsr_csr__read__h855634 or - sstatus_csr__read__h855830 or - sie_csr__read__h855900 or + fflags_csr__read__h855607 or + frm_csr__read__h855618 or + fcsr_csr__read__h855632 or + sstatus_csr__read__h855828 or + sie_csr__read__h855898 or SEXT__0_CONCAT_csrf_stcc_reg_read__6237_BITS_8_ETC___d16261 or - scounteren_csr__read__h855988 or + scounteren_csr__read__h855986 or csrf_sscratch_csr or SEXT__0_CONCAT_IF_csrf_sepcc_reg_data_lat_0_wh_ETC___d16300 or - scause_csr__read__h856128 or + scause_csr__read__h856126 or csrf_stval_csr or - sip_csr__read__h856268 or - satp_csr__read__h856331 or - mstatus_csr__read__h856477 or - medeleg_csr__read__h856638 or - mideleg_csr__read__h856736 or - mie_csr__read__h856863 or + sip_csr__read__h856266 or + satp_csr__read__h856329 or + mstatus_csr__read__h856475 or + medeleg_csr__read__h856636 or + mideleg_csr__read__h856734 or + mie_csr__read__h856861 or SEXT__0_CONCAT_csrf_mtcc_reg_read__6389_BITS_8_ETC___d16413 or - mcounteren_csr__read__h857035 or + mcounteren_csr__read__h857033 or csrf_mscratch_csr or SEXT__0_CONCAT_IF_csrf_mepcc_reg_data_lat_0_wh_ETC___d16452 or - mcause_csr__read__h857301 or + mcause_csr__read__h857299 or csrf_mtval_csr or - mip_csr__read__h857540 or + mip_csr__read__h857538 or csrf_rg_tselect or - rg_tdata1__read__h858641 or + rg_tdata1__read__h858639 or csrf_rg_tdata2 or csrf_rg_tdata3 or csrf_rg_dcsr or SEXT__0_CONCAT_csrf_rg_dpc_read__6534_BITS_85__ETC___d16558 or csrf_rg_dscratch0 or csrf_rg_dscratch1 or - x_reg_ifc__read__h855739 or + x_reg_ifc__read__h855737 or csrf_mcycle_ehr_data_rl or - csrf_minstret_ehr_data_rl or x__h904219 or csrf_time_reg) + csrf_minstret_ehr_data_rl or x__h904216 or csrf_time_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[136:125]) - 12'd1: addr__h850291 = fflags_csr__read__h855609; - 12'd2: addr__h850291 = frm_csr__read__h855620; - 12'd3: addr__h850291 = fcsr_csr__read__h855634; - 12'd256: addr__h850291 = sstatus_csr__read__h855830; - 12'd260: addr__h850291 = sie_csr__read__h855900; + 12'd1: addr__h850288 = fflags_csr__read__h855607; + 12'd2: addr__h850288 = frm_csr__read__h855618; + 12'd3: addr__h850288 = fcsr_csr__read__h855632; + 12'd256: addr__h850288 = sstatus_csr__read__h855828; + 12'd260: addr__h850288 = sie_csr__read__h855898; 12'd261: - addr__h850291 = + addr__h850288 = SEXT__0_CONCAT_csrf_stcc_reg_read__6237_BITS_8_ETC___d16261; - 12'd262: addr__h850291 = scounteren_csr__read__h855988; - 12'd320: addr__h850291 = csrf_sscratch_csr; + 12'd262: addr__h850288 = scounteren_csr__read__h855986; + 12'd320: addr__h850288 = csrf_sscratch_csr; 12'd321: - addr__h850291 = + addr__h850288 = SEXT__0_CONCAT_IF_csrf_sepcc_reg_data_lat_0_wh_ETC___d16300; - 12'd322: addr__h850291 = scause_csr__read__h856128; - 12'd323: addr__h850291 = csrf_stval_csr; - 12'd324: addr__h850291 = sip_csr__read__h856268; - 12'd384: addr__h850291 = satp_csr__read__h856331; - 12'd768: addr__h850291 = mstatus_csr__read__h856477; - 12'd769: addr__h850291 = 64'h800000000014112D; - 12'd770: addr__h850291 = medeleg_csr__read__h856638; - 12'd771: addr__h850291 = mideleg_csr__read__h856736; - 12'd772: addr__h850291 = mie_csr__read__h856863; + 12'd322: addr__h850288 = scause_csr__read__h856126; + 12'd323: addr__h850288 = csrf_stval_csr; + 12'd324: addr__h850288 = sip_csr__read__h856266; + 12'd384: addr__h850288 = satp_csr__read__h856329; + 12'd768: addr__h850288 = mstatus_csr__read__h856475; + 12'd769: addr__h850288 = 64'h800000000014112D; + 12'd770: addr__h850288 = medeleg_csr__read__h856636; + 12'd771: addr__h850288 = mideleg_csr__read__h856734; + 12'd772: addr__h850288 = mie_csr__read__h856861; 12'd773: - addr__h850291 = + addr__h850288 = SEXT__0_CONCAT_csrf_mtcc_reg_read__6389_BITS_8_ETC___d16413; - 12'd774: addr__h850291 = mcounteren_csr__read__h857035; - 12'd832: addr__h850291 = csrf_mscratch_csr; + 12'd774: addr__h850288 = mcounteren_csr__read__h857033; + 12'd832: addr__h850288 = csrf_mscratch_csr; 12'd833: - addr__h850291 = + addr__h850288 = SEXT__0_CONCAT_IF_csrf_mepcc_reg_data_lat_0_wh_ETC___d16452; - 12'd834: addr__h850291 = mcause_csr__read__h857301; - 12'd835: addr__h850291 = csrf_mtval_csr; - 12'd836: addr__h850291 = mip_csr__read__h857540; - 12'd1952: addr__h850291 = csrf_rg_tselect; - 12'd1953: addr__h850291 = rg_tdata1__read__h858641; - 12'd1954: addr__h850291 = csrf_rg_tdata2; - 12'd1955: addr__h850291 = csrf_rg_tdata3; - 12'd1968: addr__h850291 = csrf_rg_dcsr; + 12'd834: addr__h850288 = mcause_csr__read__h857299; + 12'd835: addr__h850288 = csrf_mtval_csr; + 12'd836: addr__h850288 = mip_csr__read__h857538; + 12'd1952: addr__h850288 = csrf_rg_tselect; + 12'd1953: addr__h850288 = rg_tdata1__read__h858639; + 12'd1954: addr__h850288 = csrf_rg_tdata2; + 12'd1955: addr__h850288 = csrf_rg_tdata3; + 12'd1968: addr__h850288 = csrf_rg_dcsr; 12'd1969: - addr__h850291 = + addr__h850288 = SEXT__0_CONCAT_csrf_rg_dpc_read__6534_BITS_85__ETC___d16558; - 12'd1970: addr__h850291 = csrf_rg_dscratch0; - 12'd1971: addr__h850291 = csrf_rg_dscratch1; - 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: addr__h850291 = 64'd0; - 12'd2049: addr__h850291 = x_reg_ifc__read__h855739; - 12'd2816, 12'd3072: addr__h850291 = csrf_mcycle_ehr_data_rl; - 12'd2818, 12'd3074: addr__h850291 = csrf_minstret_ehr_data_rl; - 12'd3008: addr__h850291 = { 48'd0, x__h904219 }; - 12'd3073: addr__h850291 = csrf_time_reg; - default: addr__h850291 = 64'b0; + 12'd1970: addr__h850288 = csrf_rg_dscratch0; + 12'd1971: addr__h850288 = csrf_rg_dscratch1; + 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: addr__h850288 = 64'd0; + 12'd2049: addr__h850288 = x_reg_ifc__read__h855737; + 12'd2816, 12'd3072: addr__h850288 = csrf_mcycle_ehr_data_rl; + 12'd2818, 12'd3074: addr__h850288 = csrf_minstret_ehr_data_rl; + 12'd3008: addr__h850288 = { 48'd0, x__h904216 }; + 12'd3073: addr__h850288 = csrf_time_reg; + default: addr__h850288 = 64'b0; endcase end always@(coreFix_aluExe_0_dispToRegQ$first or - fflags_csr__read__h855609 or - frm_csr__read__h855620 or - fcsr_csr__read__h855634 or - sstatus_csr__read__h855830 or - sie_csr__read__h855900 or + fflags_csr__read__h855607 or + frm_csr__read__h855618 or + fcsr_csr__read__h855632 or + sstatus_csr__read__h855828 or + sie_csr__read__h855898 or SEXT__0_CONCAT_csrf_stcc_reg_read__6237_BITS_8_ETC___d16261 or - scounteren_csr__read__h855988 or + scounteren_csr__read__h855986 or csrf_sscratch_csr or SEXT__0_CONCAT_IF_csrf_sepcc_reg_data_lat_0_wh_ETC___d16300 or - scause_csr__read__h856128 or + scause_csr__read__h856126 or csrf_stval_csr or - sip_csr__read__h856268 or - satp_csr__read__h856331 or - mstatus_csr__read__h856477 or - medeleg_csr__read__h856638 or - mideleg_csr__read__h856736 or - mie_csr__read__h856863 or + sip_csr__read__h856266 or + satp_csr__read__h856329 or + mstatus_csr__read__h856475 or + medeleg_csr__read__h856636 or + mideleg_csr__read__h856734 or + mie_csr__read__h856861 or SEXT__0_CONCAT_csrf_mtcc_reg_read__6389_BITS_8_ETC___d16413 or - mcounteren_csr__read__h857035 or + mcounteren_csr__read__h857033 or csrf_mscratch_csr or SEXT__0_CONCAT_IF_csrf_mepcc_reg_data_lat_0_wh_ETC___d16452 or - mcause_csr__read__h857301 or + mcause_csr__read__h857299 or csrf_mtval_csr or - mip_csr__read__h857540 or + mip_csr__read__h857538 or csrf_rg_tselect or - rg_tdata1__read__h858641 or + rg_tdata1__read__h858639 or csrf_rg_tdata2 or csrf_rg_tdata3 or csrf_rg_dcsr or SEXT__0_CONCAT_csrf_rg_dpc_read__6534_BITS_85__ETC___d16558 or csrf_rg_dscratch0 or csrf_rg_dscratch1 or - x_reg_ifc__read__h855739 or + x_reg_ifc__read__h855737 or csrf_mcycle_ehr_data_rl or - csrf_minstret_ehr_data_rl or x__h904219 or csrf_time_reg) + csrf_minstret_ehr_data_rl or x__h904216 or csrf_time_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[136:125]) - 12'd1: addr__h895062 = fflags_csr__read__h855609; - 12'd2: addr__h895062 = frm_csr__read__h855620; - 12'd3: addr__h895062 = fcsr_csr__read__h855634; - 12'd256: addr__h895062 = sstatus_csr__read__h855830; - 12'd260: addr__h895062 = sie_csr__read__h855900; + 12'd1: addr__h895060 = fflags_csr__read__h855607; + 12'd2: addr__h895060 = frm_csr__read__h855618; + 12'd3: addr__h895060 = fcsr_csr__read__h855632; + 12'd256: addr__h895060 = sstatus_csr__read__h855828; + 12'd260: addr__h895060 = sie_csr__read__h855898; 12'd261: - addr__h895062 = + addr__h895060 = SEXT__0_CONCAT_csrf_stcc_reg_read__6237_BITS_8_ETC___d16261; - 12'd262: addr__h895062 = scounteren_csr__read__h855988; - 12'd320: addr__h895062 = csrf_sscratch_csr; + 12'd262: addr__h895060 = scounteren_csr__read__h855986; + 12'd320: addr__h895060 = csrf_sscratch_csr; 12'd321: - addr__h895062 = + addr__h895060 = SEXT__0_CONCAT_IF_csrf_sepcc_reg_data_lat_0_wh_ETC___d16300; - 12'd322: addr__h895062 = scause_csr__read__h856128; - 12'd323: addr__h895062 = csrf_stval_csr; - 12'd324: addr__h895062 = sip_csr__read__h856268; - 12'd384: addr__h895062 = satp_csr__read__h856331; - 12'd768: addr__h895062 = mstatus_csr__read__h856477; - 12'd769: addr__h895062 = 64'h800000000014112D; - 12'd770: addr__h895062 = medeleg_csr__read__h856638; - 12'd771: addr__h895062 = mideleg_csr__read__h856736; - 12'd772: addr__h895062 = mie_csr__read__h856863; + 12'd322: addr__h895060 = scause_csr__read__h856126; + 12'd323: addr__h895060 = csrf_stval_csr; + 12'd324: addr__h895060 = sip_csr__read__h856266; + 12'd384: addr__h895060 = satp_csr__read__h856329; + 12'd768: addr__h895060 = mstatus_csr__read__h856475; + 12'd769: addr__h895060 = 64'h800000000014112D; + 12'd770: addr__h895060 = medeleg_csr__read__h856636; + 12'd771: addr__h895060 = mideleg_csr__read__h856734; + 12'd772: addr__h895060 = mie_csr__read__h856861; 12'd773: - addr__h895062 = + addr__h895060 = SEXT__0_CONCAT_csrf_mtcc_reg_read__6389_BITS_8_ETC___d16413; - 12'd774: addr__h895062 = mcounteren_csr__read__h857035; - 12'd832: addr__h895062 = csrf_mscratch_csr; + 12'd774: addr__h895060 = mcounteren_csr__read__h857033; + 12'd832: addr__h895060 = csrf_mscratch_csr; 12'd833: - addr__h895062 = + addr__h895060 = SEXT__0_CONCAT_IF_csrf_mepcc_reg_data_lat_0_wh_ETC___d16452; - 12'd834: addr__h895062 = mcause_csr__read__h857301; - 12'd835: addr__h895062 = csrf_mtval_csr; - 12'd836: addr__h895062 = mip_csr__read__h857540; - 12'd1952: addr__h895062 = csrf_rg_tselect; - 12'd1953: addr__h895062 = rg_tdata1__read__h858641; - 12'd1954: addr__h895062 = csrf_rg_tdata2; - 12'd1955: addr__h895062 = csrf_rg_tdata3; - 12'd1968: addr__h895062 = csrf_rg_dcsr; + 12'd834: addr__h895060 = mcause_csr__read__h857299; + 12'd835: addr__h895060 = csrf_mtval_csr; + 12'd836: addr__h895060 = mip_csr__read__h857538; + 12'd1952: addr__h895060 = csrf_rg_tselect; + 12'd1953: addr__h895060 = rg_tdata1__read__h858639; + 12'd1954: addr__h895060 = csrf_rg_tdata2; + 12'd1955: addr__h895060 = csrf_rg_tdata3; + 12'd1968: addr__h895060 = csrf_rg_dcsr; 12'd1969: - addr__h895062 = + addr__h895060 = SEXT__0_CONCAT_csrf_rg_dpc_read__6534_BITS_85__ETC___d16558; - 12'd1970: addr__h895062 = csrf_rg_dscratch0; - 12'd1971: addr__h895062 = csrf_rg_dscratch1; - 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: addr__h895062 = 64'd0; - 12'd2049: addr__h895062 = x_reg_ifc__read__h855739; - 12'd2816, 12'd3072: addr__h895062 = csrf_mcycle_ehr_data_rl; - 12'd2818, 12'd3074: addr__h895062 = csrf_minstret_ehr_data_rl; - 12'd3008: addr__h895062 = { 48'd0, x__h904219 }; - 12'd3073: addr__h895062 = csrf_time_reg; - default: addr__h895062 = 64'b0; + 12'd1970: addr__h895060 = csrf_rg_dscratch0; + 12'd1971: addr__h895060 = csrf_rg_dscratch1; + 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: addr__h895060 = 64'd0; + 12'd2049: addr__h895060 = x_reg_ifc__read__h855737; + 12'd2816, 12'd3072: addr__h895060 = csrf_mcycle_ehr_data_rl; + 12'd2818, 12'd3074: addr__h895060 = csrf_minstret_ehr_data_rl; + 12'd3008: addr__h895060 = { 48'd0, x__h904216 }; + 12'd3073: addr__h895060 = csrf_time_reg; + default: addr__h895060 = 64'b0; endcase end always@(coreFix_aluExe_1_dispToRegQ$first or @@ -47341,17 +47386,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[123:119]) - 5'd1: thin_reserved__h864892 = csrf_ddc_reg[54:53]; - 5'd12: thin_reserved__h864892 = csrf_stcc_reg[54:53]; - 5'd13: thin_reserved__h864892 = csrf_stdc_reg[54:53]; - 5'd14: thin_reserved__h864892 = csrf_sScratchC_reg[54:53]; + 5'd1: thin_reserved__h864890 = csrf_ddc_reg[54:53]; + 5'd12: thin_reserved__h864890 = csrf_stcc_reg[54:53]; + 5'd13: thin_reserved__h864890 = csrf_stdc_reg[54:53]; + 5'd14: thin_reserved__h864890 = csrf_sScratchC_reg[54:53]; 5'd15: - thin_reserved__h864892 = + thin_reserved__h864890 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17359; - 5'd28: thin_reserved__h864892 = csrf_mtcc_reg[54:53]; - 5'd29: thin_reserved__h864892 = csrf_mtdc_reg[54:53]; - 5'd30: thin_reserved__h864892 = csrf_mScratchC_reg[54:53]; - default: thin_reserved__h864892 = + 5'd28: thin_reserved__h864890 = csrf_mtcc_reg[54:53]; + 5'd29: thin_reserved__h864890 = csrf_mtdc_reg[54:53]; + 5'd30: thin_reserved__h864890 = csrf_mScratchC_reg[54:53]; + default: thin_reserved__h864890 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17365; endcase end @@ -47365,17 +47410,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[123:119]) - 5'd1: thin_reserved__h906790 = csrf_ddc_reg[54:53]; - 5'd12: thin_reserved__h906790 = csrf_stcc_reg[54:53]; - 5'd13: thin_reserved__h906790 = csrf_stdc_reg[54:53]; - 5'd14: thin_reserved__h906790 = csrf_sScratchC_reg[54:53]; + 5'd1: thin_reserved__h906787 = csrf_ddc_reg[54:53]; + 5'd12: thin_reserved__h906787 = csrf_stcc_reg[54:53]; + 5'd13: thin_reserved__h906787 = csrf_stdc_reg[54:53]; + 5'd14: thin_reserved__h906787 = csrf_sScratchC_reg[54:53]; 5'd15: - thin_reserved__h906790 = + thin_reserved__h906787 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17359; - 5'd28: thin_reserved__h906790 = csrf_mtcc_reg[54:53]; - 5'd29: thin_reserved__h906790 = csrf_mtdc_reg[54:53]; - 5'd30: thin_reserved__h906790 = csrf_mScratchC_reg[54:53]; - default: thin_reserved__h906790 = + 5'd28: thin_reserved__h906787 = csrf_mtcc_reg[54:53]; + 5'd29: thin_reserved__h906787 = csrf_mtdc_reg[54:53]; + 5'd30: thin_reserved__h906787 = csrf_mScratchC_reg[54:53]; + default: thin_reserved__h906787 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17365; endcase end @@ -47389,17 +47434,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[123:119]) - 5'd1: thin_perms_soft__h865128 = csrf_ddc_reg[71:68]; - 5'd12: thin_perms_soft__h865128 = csrf_stcc_reg[71:68]; - 5'd13: thin_perms_soft__h865128 = csrf_stdc_reg[71:68]; - 5'd14: thin_perms_soft__h865128 = csrf_sScratchC_reg[71:68]; + 5'd1: thin_perms_soft__h865126 = csrf_ddc_reg[71:68]; + 5'd12: thin_perms_soft__h865126 = csrf_stcc_reg[71:68]; + 5'd13: thin_perms_soft__h865126 = csrf_stdc_reg[71:68]; + 5'd14: thin_perms_soft__h865126 = csrf_sScratchC_reg[71:68]; 5'd15: - thin_perms_soft__h865128 = + thin_perms_soft__h865126 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17045; - 5'd28: thin_perms_soft__h865128 = csrf_mtcc_reg[71:68]; - 5'd29: thin_perms_soft__h865128 = csrf_mtdc_reg[71:68]; - 5'd30: thin_perms_soft__h865128 = csrf_mScratchC_reg[71:68]; - default: thin_perms_soft__h865128 = + 5'd28: thin_perms_soft__h865126 = csrf_mtcc_reg[71:68]; + 5'd29: thin_perms_soft__h865126 = csrf_mtdc_reg[71:68]; + 5'd30: thin_perms_soft__h865126 = csrf_mScratchC_reg[71:68]; + default: thin_perms_soft__h865126 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17051; endcase end @@ -47413,17 +47458,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[123:119]) - 5'd1: thin_perms_soft__h906966 = csrf_ddc_reg[71:68]; - 5'd12: thin_perms_soft__h906966 = csrf_stcc_reg[71:68]; - 5'd13: thin_perms_soft__h906966 = csrf_stdc_reg[71:68]; - 5'd14: thin_perms_soft__h906966 = csrf_sScratchC_reg[71:68]; + 5'd1: thin_perms_soft__h906963 = csrf_ddc_reg[71:68]; + 5'd12: thin_perms_soft__h906963 = csrf_stcc_reg[71:68]; + 5'd13: thin_perms_soft__h906963 = csrf_stdc_reg[71:68]; + 5'd14: thin_perms_soft__h906963 = csrf_sScratchC_reg[71:68]; 5'd15: - thin_perms_soft__h906966 = + thin_perms_soft__h906963 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17045; - 5'd28: thin_perms_soft__h906966 = csrf_mtcc_reg[71:68]; - 5'd29: thin_perms_soft__h906966 = csrf_mtdc_reg[71:68]; - 5'd30: thin_perms_soft__h906966 = csrf_mScratchC_reg[71:68]; - default: thin_perms_soft__h906966 = + 5'd28: thin_perms_soft__h906963 = csrf_mtcc_reg[71:68]; + 5'd29: thin_perms_soft__h906963 = csrf_mtdc_reg[71:68]; + 5'd30: thin_perms_soft__h906963 = csrf_mScratchC_reg[71:68]; + default: thin_perms_soft__h906963 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17051; endcase end @@ -47437,17 +47482,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[123:119]) - 5'd1: thin_bounds_topBits__h866836 = csrf_ddc_reg[27:14]; - 5'd12: thin_bounds_topBits__h866836 = csrf_stcc_reg[27:14]; - 5'd13: thin_bounds_topBits__h866836 = csrf_stdc_reg[27:14]; - 5'd14: thin_bounds_topBits__h866836 = csrf_sScratchC_reg[27:14]; + 5'd1: thin_bounds_topBits__h866834 = csrf_ddc_reg[27:14]; + 5'd12: thin_bounds_topBits__h866834 = csrf_stcc_reg[27:14]; + 5'd13: thin_bounds_topBits__h866834 = csrf_stdc_reg[27:14]; + 5'd14: thin_bounds_topBits__h866834 = csrf_sScratchC_reg[27:14]; 5'd15: - thin_bounds_topBits__h866836 = + thin_bounds_topBits__h866834 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17468; - 5'd28: thin_bounds_topBits__h866836 = csrf_mtcc_reg[27:14]; - 5'd29: thin_bounds_topBits__h866836 = csrf_mtdc_reg[27:14]; - 5'd30: thin_bounds_topBits__h866836 = csrf_mScratchC_reg[27:14]; - default: thin_bounds_topBits__h866836 = + 5'd28: thin_bounds_topBits__h866834 = csrf_mtcc_reg[27:14]; + 5'd29: thin_bounds_topBits__h866834 = csrf_mtdc_reg[27:14]; + 5'd30: thin_bounds_topBits__h866834 = csrf_mScratchC_reg[27:14]; + default: thin_bounds_topBits__h866834 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17474; endcase end @@ -47461,17 +47506,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[123:119]) - 5'd1: thin_bounds_topBits__h908192 = csrf_ddc_reg[27:14]; - 5'd12: thin_bounds_topBits__h908192 = csrf_stcc_reg[27:14]; - 5'd13: thin_bounds_topBits__h908192 = csrf_stdc_reg[27:14]; - 5'd14: thin_bounds_topBits__h908192 = csrf_sScratchC_reg[27:14]; + 5'd1: thin_bounds_topBits__h908189 = csrf_ddc_reg[27:14]; + 5'd12: thin_bounds_topBits__h908189 = csrf_stcc_reg[27:14]; + 5'd13: thin_bounds_topBits__h908189 = csrf_stdc_reg[27:14]; + 5'd14: thin_bounds_topBits__h908189 = csrf_sScratchC_reg[27:14]; 5'd15: - thin_bounds_topBits__h908192 = + thin_bounds_topBits__h908189 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17468; - 5'd28: thin_bounds_topBits__h908192 = csrf_mtcc_reg[27:14]; - 5'd29: thin_bounds_topBits__h908192 = csrf_mtdc_reg[27:14]; - 5'd30: thin_bounds_topBits__h908192 = csrf_mScratchC_reg[27:14]; - default: thin_bounds_topBits__h908192 = + 5'd28: thin_bounds_topBits__h908189 = csrf_mtcc_reg[27:14]; + 5'd29: thin_bounds_topBits__h908189 = csrf_mtdc_reg[27:14]; + 5'd30: thin_bounds_topBits__h908189 = csrf_mScratchC_reg[27:14]; + default: thin_bounds_topBits__h908189 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17474; endcase end @@ -47589,44 +47634,6 @@ module mkCore(CLK, IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17095; endcase end - always@(coreFix_aluExe_0_dispToRegQ$first or - IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17139 or - csrf_ddc_reg or - csrf_stcc_reg or - csrf_stdc_reg or - csrf_sScratchC_reg or - IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17133 or - csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) - begin - case (coreFix_aluExe_0_dispToRegQ$first[123:119]) - 5'd1: - IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19509 = - csrf_ddc_reg[64]; - 5'd12: - IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19509 = - csrf_stcc_reg[64]; - 5'd13: - IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19509 = - csrf_stdc_reg[64]; - 5'd14: - IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19509 = - csrf_sScratchC_reg[64]; - 5'd15: - IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19509 = - IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17133; - 5'd28: - IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19509 = - csrf_mtcc_reg[64]; - 5'd29: - IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19509 = - csrf_mtdc_reg[64]; - 5'd30: - IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19509 = - csrf_mScratchC_reg[64]; - default: IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19509 = - IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17139; - endcase - end always@(coreFix_aluExe_0_dispToRegQ$first or IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17117 or csrf_ddc_reg or @@ -47665,6 +47672,44 @@ module mkCore(CLK, IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17117; endcase end + always@(coreFix_aluExe_0_dispToRegQ$first or + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17139 or + csrf_ddc_reg or + csrf_stcc_reg or + csrf_stdc_reg or + csrf_sScratchC_reg or + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17133 or + csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) + begin + case (coreFix_aluExe_0_dispToRegQ$first[123:119]) + 5'd1: + IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19509 = + csrf_ddc_reg[64]; + 5'd12: + IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19509 = + csrf_stcc_reg[64]; + 5'd13: + IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19509 = + csrf_stdc_reg[64]; + 5'd14: + IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19509 = + csrf_sScratchC_reg[64]; + 5'd15: + IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19509 = + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17133; + 5'd28: + IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19509 = + csrf_mtcc_reg[64]; + 5'd29: + IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19509 = + csrf_mtdc_reg[64]; + 5'd30: + IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19509 = + csrf_mScratchC_reg[64]; + default: IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19509 = + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17139; + endcase + end always@(coreFix_aluExe_0_dispToRegQ$first or IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17161 or csrf_ddc_reg or @@ -47703,6 +47748,44 @@ module mkCore(CLK, IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17161; endcase end + always@(coreFix_aluExe_0_dispToRegQ$first or + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17249 or + csrf_ddc_reg or + csrf_stcc_reg or + csrf_stdc_reg or + csrf_sScratchC_reg or + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17243 or + csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) + begin + case (coreFix_aluExe_0_dispToRegQ$first[123:119]) + 5'd1: + IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19554 = + csrf_ddc_reg[59]; + 5'd12: + IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19554 = + csrf_stcc_reg[59]; + 5'd13: + IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19554 = + csrf_stdc_reg[59]; + 5'd14: + IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19554 = + csrf_sScratchC_reg[59]; + 5'd15: + IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19554 = + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17243; + 5'd28: + IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19554 = + csrf_mtcc_reg[59]; + 5'd29: + IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19554 = + csrf_mtdc_reg[59]; + 5'd30: + IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19554 = + csrf_mScratchC_reg[59]; + default: IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19554 = + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17249; + endcase + end always@(coreFix_aluExe_0_dispToRegQ$first or IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17183 or csrf_ddc_reg or @@ -47818,41 +47901,41 @@ module mkCore(CLK, endcase end always@(coreFix_aluExe_0_dispToRegQ$first or - IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17249 or + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17271 or csrf_ddc_reg or csrf_stcc_reg or csrf_stdc_reg or csrf_sScratchC_reg or - IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17243 or + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17265 or csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[123:119]) 5'd1: - IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19554 = - csrf_ddc_reg[59]; + IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19563 = + csrf_ddc_reg[58]; 5'd12: - IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19554 = - csrf_stcc_reg[59]; + IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19563 = + csrf_stcc_reg[58]; 5'd13: - IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19554 = - csrf_stdc_reg[59]; + IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19563 = + csrf_stdc_reg[58]; 5'd14: - IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19554 = - csrf_sScratchC_reg[59]; + IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19563 = + csrf_sScratchC_reg[58]; 5'd15: - IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19554 = - IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17243; + IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19563 = + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17265; 5'd28: - IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19554 = - csrf_mtcc_reg[59]; + IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19563 = + csrf_mtcc_reg[58]; 5'd29: - IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19554 = - csrf_mtdc_reg[59]; + IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19563 = + csrf_mtdc_reg[58]; 5'd30: - IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19554 = - csrf_mScratchC_reg[59]; - default: IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19554 = - IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17249; + IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19563 = + csrf_mScratchC_reg[58]; + default: IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19563 = + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17271; endcase end always@(coreFix_aluExe_0_dispToRegQ$first or @@ -47893,44 +47976,6 @@ module mkCore(CLK, IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17293; endcase end - always@(coreFix_aluExe_0_dispToRegQ$first or - IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17271 or - csrf_ddc_reg or - csrf_stcc_reg or - csrf_stdc_reg or - csrf_sScratchC_reg or - IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17265 or - csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) - begin - case (coreFix_aluExe_0_dispToRegQ$first[123:119]) - 5'd1: - IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19563 = - csrf_ddc_reg[58]; - 5'd12: - IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19563 = - csrf_stcc_reg[58]; - 5'd13: - IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19563 = - csrf_stdc_reg[58]; - 5'd14: - IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19563 = - csrf_sScratchC_reg[58]; - 5'd15: - IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19563 = - IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17265; - 5'd28: - IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19563 = - csrf_mtcc_reg[58]; - 5'd29: - IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19563 = - csrf_mtdc_reg[58]; - 5'd30: - IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19563 = - csrf_mScratchC_reg[58]; - default: IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19563 = - IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17271; - endcase - end always@(coreFix_aluExe_0_dispToRegQ$first or IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17315 or csrf_ddc_reg or @@ -48055,17 +48100,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[123:119]) - 5'd1: thin_otype__h864893 = csrf_ddc_reg[52:35]; - 5'd12: thin_otype__h864893 = csrf_stcc_reg[52:35]; - 5'd13: thin_otype__h864893 = csrf_stdc_reg[52:35]; - 5'd14: thin_otype__h864893 = csrf_sScratchC_reg[52:35]; + 5'd1: thin_otype__h864891 = csrf_ddc_reg[52:35]; + 5'd12: thin_otype__h864891 = csrf_stcc_reg[52:35]; + 5'd13: thin_otype__h864891 = csrf_stdc_reg[52:35]; + 5'd14: thin_otype__h864891 = csrf_sScratchC_reg[52:35]; 5'd15: - thin_otype__h864893 = + thin_otype__h864891 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17381; - 5'd28: thin_otype__h864893 = csrf_mtcc_reg[52:35]; - 5'd29: thin_otype__h864893 = csrf_mtdc_reg[52:35]; - 5'd30: thin_otype__h864893 = csrf_mScratchC_reg[52:35]; - default: thin_otype__h864893 = + 5'd28: thin_otype__h864891 = csrf_mtcc_reg[52:35]; + 5'd29: thin_otype__h864891 = csrf_mtdc_reg[52:35]; + 5'd30: thin_otype__h864891 = csrf_mScratchC_reg[52:35]; + default: thin_otype__h864891 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17387; endcase end @@ -48079,17 +48124,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[123:119]) - 5'd1: thin_otype__h906791 = csrf_ddc_reg[52:35]; - 5'd12: thin_otype__h906791 = csrf_stcc_reg[52:35]; - 5'd13: thin_otype__h906791 = csrf_stdc_reg[52:35]; - 5'd14: thin_otype__h906791 = csrf_sScratchC_reg[52:35]; + 5'd1: thin_otype__h906788 = csrf_ddc_reg[52:35]; + 5'd12: thin_otype__h906788 = csrf_stcc_reg[52:35]; + 5'd13: thin_otype__h906788 = csrf_stdc_reg[52:35]; + 5'd14: thin_otype__h906788 = csrf_sScratchC_reg[52:35]; 5'd15: - thin_otype__h906791 = + thin_otype__h906788 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17381; - 5'd28: thin_otype__h906791 = csrf_mtcc_reg[52:35]; - 5'd29: thin_otype__h906791 = csrf_mtdc_reg[52:35]; - 5'd30: thin_otype__h906791 = csrf_mScratchC_reg[52:35]; - default: thin_otype__h906791 = + 5'd28: thin_otype__h906788 = csrf_mtcc_reg[52:35]; + 5'd29: thin_otype__h906788 = csrf_mtdc_reg[52:35]; + 5'd30: thin_otype__h906788 = csrf_mScratchC_reg[52:35]; + default: thin_otype__h906788 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17387; endcase end @@ -48173,10 +48218,10 @@ module mkCore(CLK, begin case (mmio_dataReqQ_data_0[150:149]) 2'd0, 2'd1, 2'd2: - CASE_mmio_dataReqQ_data_0_BITS_150_TO_149_0_mm_ETC__q332 = + CASE_mmio_dataReqQ_data_0_BITS_150_TO_149_0_mm_ETC__q334 = mmio_dataReqQ_data_0[150:145]; 2'd3: - CASE_mmio_dataReqQ_data_0_BITS_150_TO_149_0_mm_ETC__q332 = + CASE_mmio_dataReqQ_data_0_BITS_150_TO_149_0_mm_ETC__q334 = { 2'd3, mmio_dataReqQ_data_0[148:145] }; endcase end @@ -48184,9 +48229,9 @@ module mkCore(CLK, begin case (coreFix_memExe_lsq$firstSt[3:0]) 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: - CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q333 = + CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q335 = coreFix_memExe_lsq$firstSt[3:0]; - default: CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q333 = + default: CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q335 = 4'd15; endcase end @@ -48216,9 +48261,9 @@ module mkCore(CLK, 5'd24, 5'd25, 5'd26: - CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q334 = + CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q336 = coreFix_memExe_lsq$firstSt[4:0]; - default: CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q334 = + default: CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q336 = 5'd27; endcase end @@ -48239,40 +48284,40 @@ module mkCore(CLK, 5'd12, 5'd13, 5'd15: - CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q335 = + CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q337 = coreFix_memExe_lsq$firstSt[4:0]; - default: CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q335 = + default: CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q337 = 5'd28; endcase end always@(coreFix_memExe_lsq$firstSt or - CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q333 or - CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q334 or - CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q335) + CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q335 or + CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q336 or + CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q337) begin case (coreFix_memExe_lsq$firstSt[12:11]) 2'd0: - CASE_coreFix_memExe_lsqfirstSt_BITS_12_TO_11__ETC__q336 = + CASE_coreFix_memExe_lsqfirstSt_BITS_12_TO_11__ETC__q338 = { 2'd0, coreFix_memExe_lsq$firstSt[10:5], - CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q334 }; + CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q336 }; 2'd1: - CASE_coreFix_memExe_lsqfirstSt_BITS_12_TO_11__ETC__q336 = + CASE_coreFix_memExe_lsqfirstSt_BITS_12_TO_11__ETC__q338 = { coreFix_memExe_lsq$firstSt[12:11], 6'h2A, - CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q335 }; - default: CASE_coreFix_memExe_lsqfirstSt_BITS_12_TO_11__ETC__q336 = + CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q337 }; + default: CASE_coreFix_memExe_lsqfirstSt_BITS_12_TO_11__ETC__q338 = { 9'd298, - CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q333 }; + CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q335 }; endcase end always@(coreFix_memExe_lsq$firstLd) begin case (coreFix_memExe_lsq$firstLd[6:3]) 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: - CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q337 = + CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q339 = coreFix_memExe_lsq$firstLd[6:3]; - default: CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q337 = + default: CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q339 = 4'd15; endcase end @@ -48302,9 +48347,9 @@ module mkCore(CLK, 5'd24, 5'd25, 5'd26: - CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q338 = + CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q340 = coreFix_memExe_lsq$firstLd[7:3]; - default: CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q338 = + default: CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q340 = 5'd27; endcase end @@ -48325,41 +48370,41 @@ module mkCore(CLK, 5'd12, 5'd13, 5'd15: - CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q339 = + CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q341 = coreFix_memExe_lsq$firstLd[7:3]; - default: CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q339 = + default: CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q341 = 5'd28; endcase end always@(coreFix_memExe_lsq$firstLd or - CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q337 or - CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q338 or - CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q339) + CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q339 or + CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q340 or + CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q341) begin case (coreFix_memExe_lsq$firstLd[15:14]) 2'd0: - CASE_coreFix_memExe_lsqfirstLd_BITS_15_TO_14__ETC__q340 = + CASE_coreFix_memExe_lsqfirstLd_BITS_15_TO_14__ETC__q342 = { 2'd0, coreFix_memExe_lsq$firstLd[13:8], - CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q338 }; + CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q340 }; 2'd1: - CASE_coreFix_memExe_lsqfirstLd_BITS_15_TO_14__ETC__q340 = + CASE_coreFix_memExe_lsqfirstLd_BITS_15_TO_14__ETC__q342 = { coreFix_memExe_lsq$firstLd[15:14], 6'h2A, - CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q339 }; - default: CASE_coreFix_memExe_lsqfirstLd_BITS_15_TO_14__ETC__q340 = + CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q341 }; + default: CASE_coreFix_memExe_lsqfirstLd_BITS_15_TO_14__ETC__q342 = { 9'd298, - CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q337 }; + CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q339 }; endcase end always@(mmioToPlatform_pRq_enq_x) begin case (mmioToPlatform_pRq_enq_x[37:36]) 2'd0, 2'd1, 2'd2: - CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q341 = + CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q343 = mmioToPlatform_pRq_enq_x[37:32]; 2'd3: - CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q341 = + CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q343 = { 2'd3, mmioToPlatform_pRq_enq_x[35:32] }; endcase end @@ -48367,26 +48412,26 @@ module mkCore(CLK, begin case (coreFix_aluExe_0_rsAlu$dispatchData[203:201]) 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q342 = + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q344 = coreFix_aluExe_0_rsAlu$dispatchData[203:201]; - default: CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q342 = 3'd7; + default: CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q344 = 3'd7; endcase end always@(coreFix_aluExe_0_rsAlu$dispatchData or - CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q342) + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q344) begin case (coreFix_aluExe_0_rsAlu$dispatchData[229:227]) 3'd0, 3'd1, 3'd2, 3'd3: - CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q343 = + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q345 = coreFix_aluExe_0_rsAlu$dispatchData[229:200]; 3'd4: - CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q343 = + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q345 = { coreFix_aluExe_0_rsAlu$dispatchData[229:227], 18'h2AAAA, coreFix_aluExe_0_rsAlu$dispatchData[208:204], - CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q342, + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q344, coreFix_aluExe_0_rsAlu$dispatchData[200] }; - default: CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q343 = + default: CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q345 = 30'd715827882; endcase end @@ -48395,13 +48440,13 @@ module mkCore(CLK, begin case (coreFix_aluExe_0_rsAlu$dispatchData[199:198]) 2'd0: - CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q344 = + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q346 = coreFix_aluExe_0_rsAlu$dispatchData[199:189]; 2'd1: - CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q344 = + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q346 = { coreFix_aluExe_0_rsAlu$dispatchData[199:198], IF_coreFix_aluExe_0_rsAlu_dispatchData__8313_B_ETC___d18454 }; - default: CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q344 = + default: CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q346 = 11'd1194; endcase end @@ -48454,9 +48499,9 @@ module mkCore(CLK, 12'd3858, 12'd3859, 12'd3860: - CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q345 = + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q347 = coreFix_aluExe_0_rsAlu$dispatchData[140:129]; - default: CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q345 = + default: CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q347 = 12'd2303; endcase end @@ -48464,9 +48509,9 @@ module mkCore(CLK, begin case (coreFix_aluExe_0_rsAlu$dispatchData[127:123]) 5'd0, 5'd1, 5'd12, 5'd13, 5'd14, 5'd15, 5'd28, 5'd29, 5'd30, 5'd31: - CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q346 = + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q348 = coreFix_aluExe_0_rsAlu$dispatchData[127:123]; - default: CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q346 = + default: CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q348 = 5'd10; endcase end @@ -48496,9 +48541,9 @@ module mkCore(CLK, 5'd24, 5'd25, 5'd26: - CASE_basicExec_0102_BITS_270_TO_266_0_basicExe_ETC__q347 = + CASE_basicExec_0102_BITS_270_TO_266_0_basicExe_ETC__q349 = basicExec___d20102[270:266]; - default: CASE_basicExec_0102_BITS_270_TO_266_0_basicExe_ETC__q347 = + default: CASE_basicExec_0102_BITS_270_TO_266_0_basicExe_ETC__q349 = 5'd27; endcase end @@ -48506,26 +48551,26 @@ module mkCore(CLK, begin case (coreFix_aluExe_0_dispToRegQ$first[199:197]) 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_19_ETC__q348 = + CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_19_ETC__q350 = coreFix_aluExe_0_dispToRegQ$first[199:197]; - default: CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_19_ETC__q348 = 3'd7; + default: CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_19_ETC__q350 = 3'd7; endcase end always@(coreFix_aluExe_0_dispToRegQ$first or - CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_19_ETC__q348) + CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_19_ETC__q350) begin case (coreFix_aluExe_0_dispToRegQ$first[225:223]) 3'd0, 3'd1, 3'd2, 3'd3: - CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_22_ETC__q349 = + CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_22_ETC__q351 = coreFix_aluExe_0_dispToRegQ$first[225:196]; 3'd4: - CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_22_ETC__q349 = + CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_22_ETC__q351 = { coreFix_aluExe_0_dispToRegQ$first[225:223], 18'h2AAAA, coreFix_aluExe_0_dispToRegQ$first[204:200], - CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_19_ETC__q348, + CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_19_ETC__q350, coreFix_aluExe_0_dispToRegQ$first[196] }; - default: CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_22_ETC__q349 = + default: CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_22_ETC__q351 = 30'd715827882; endcase end @@ -48534,13 +48579,13 @@ module mkCore(CLK, begin case (coreFix_aluExe_0_dispToRegQ$first[195:194]) 2'd0: - CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_19_ETC__q350 = + CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_19_ETC__q352 = coreFix_aluExe_0_dispToRegQ$first[195:185]; 2'd1: - CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_19_ETC__q350 = + CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_19_ETC__q352 = { coreFix_aluExe_0_dispToRegQ$first[195:194], IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d18867 }; - default: CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_19_ETC__q350 = + default: CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_19_ETC__q352 = 11'd1194; endcase end @@ -48593,9 +48638,9 @@ module mkCore(CLK, 12'd3858, 12'd3859, 12'd3860: - CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q351 = + CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q353 = coreFix_aluExe_0_dispToRegQ$first[136:125]; - default: CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q351 = + default: CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q353 = 12'd2303; endcase end @@ -48603,9 +48648,9 @@ module mkCore(CLK, begin case (coreFix_aluExe_0_dispToRegQ$first[123:119]) 5'd0, 5'd1, 5'd12, 5'd13, 5'd14, 5'd15, 5'd28, 5'd29, 5'd30, 5'd31: - CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_12_ETC__q352 = + CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_12_ETC__q354 = coreFix_aluExe_0_dispToRegQ$first[123:119]; - default: CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_12_ETC__q352 = + default: CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_12_ETC__q354 = 5'd10; endcase end @@ -48613,26 +48658,26 @@ module mkCore(CLK, begin case (coreFix_aluExe_1_rsAlu$dispatchData[203:201]) 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q353 = + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q355 = coreFix_aluExe_1_rsAlu$dispatchData[203:201]; - default: CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q353 = 3'd7; + default: CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q355 = 3'd7; endcase end always@(coreFix_aluExe_1_rsAlu$dispatchData or - CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q353) + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q355) begin case (coreFix_aluExe_1_rsAlu$dispatchData[229:227]) 3'd0, 3'd1, 3'd2, 3'd3: - CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q354 = + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q356 = coreFix_aluExe_1_rsAlu$dispatchData[229:200]; 3'd4: - CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q354 = + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q356 = { coreFix_aluExe_1_rsAlu$dispatchData[229:227], 18'h2AAAA, coreFix_aluExe_1_rsAlu$dispatchData[208:204], - CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q353, + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q355, coreFix_aluExe_1_rsAlu$dispatchData[200] }; - default: CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q354 = + default: CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q356 = 30'd715827882; endcase end @@ -48641,13 +48686,13 @@ module mkCore(CLK, begin case (coreFix_aluExe_1_rsAlu$dispatchData[199:198]) 2'd0: - CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q355 = + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q357 = coreFix_aluExe_1_rsAlu$dispatchData[199:189]; 2'd1: - CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q355 = + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q357 = { coreFix_aluExe_1_rsAlu$dispatchData[199:198], IF_coreFix_aluExe_1_rsAlu_dispatchData__5488_B_ETC___d15631 }; - default: CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q355 = + default: CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q357 = 11'd1194; endcase end @@ -48700,9 +48745,9 @@ module mkCore(CLK, 12'd3858, 12'd3859, 12'd3860: - CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q356 = + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q358 = coreFix_aluExe_1_rsAlu$dispatchData[140:129]; - default: CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q356 = + default: CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q358 = 12'd2303; endcase end @@ -48710,9 +48755,9 @@ module mkCore(CLK, begin case (coreFix_aluExe_1_rsAlu$dispatchData[127:123]) 5'd0, 5'd1, 5'd12, 5'd13, 5'd14, 5'd15, 5'd28, 5'd29, 5'd30, 5'd31: - CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q357 = + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q359 = coreFix_aluExe_1_rsAlu$dispatchData[127:123]; - default: CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q357 = + default: CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q359 = 5'd10; endcase end @@ -48742,9 +48787,9 @@ module mkCore(CLK, 5'd24, 5'd25, 5'd26: - CASE_basicExec_7927_BITS_270_TO_266_0_basicExe_ETC__q358 = + CASE_basicExec_7927_BITS_270_TO_266_0_basicExe_ETC__q360 = basicExec___d17927[270:266]; - default: CASE_basicExec_7927_BITS_270_TO_266_0_basicExe_ETC__q358 = + default: CASE_basicExec_7927_BITS_270_TO_266_0_basicExe_ETC__q360 = 5'd27; endcase end @@ -48752,26 +48797,26 @@ module mkCore(CLK, begin case (coreFix_aluExe_1_dispToRegQ$first[199:197]) 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_19_ETC__q359 = + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_19_ETC__q361 = coreFix_aluExe_1_dispToRegQ$first[199:197]; - default: CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_19_ETC__q359 = 3'd7; + default: CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_19_ETC__q361 = 3'd7; endcase end always@(coreFix_aluExe_1_dispToRegQ$first or - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_19_ETC__q359) + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_19_ETC__q361) begin case (coreFix_aluExe_1_dispToRegQ$first[225:223]) 3'd0, 3'd1, 3'd2, 3'd3: - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_22_ETC__q360 = + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_22_ETC__q362 = coreFix_aluExe_1_dispToRegQ$first[225:196]; 3'd4: - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_22_ETC__q360 = + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_22_ETC__q362 = { coreFix_aluExe_1_dispToRegQ$first[225:223], 18'h2AAAA, coreFix_aluExe_1_dispToRegQ$first[204:200], - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_19_ETC__q359, + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_19_ETC__q361, coreFix_aluExe_1_dispToRegQ$first[196] }; - default: CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_22_ETC__q360 = + default: CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_22_ETC__q362 = 30'd715827882; endcase end @@ -48780,13 +48825,13 @@ module mkCore(CLK, begin case (coreFix_aluExe_1_dispToRegQ$first[195:194]) 2'd0: - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_19_ETC__q361 = + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_19_ETC__q363 = coreFix_aluExe_1_dispToRegQ$first[195:185]; 2'd1: - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_19_ETC__q361 = + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_19_ETC__q363 = { coreFix_aluExe_1_dispToRegQ$first[195:194], IF_coreFix_aluExe_1_dispToRegQ_first__5790_BIT_ETC___d16045 }; - default: CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_19_ETC__q361 = + default: CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_19_ETC__q363 = 11'd1194; endcase end @@ -48839,9 +48884,9 @@ module mkCore(CLK, 12'd3858, 12'd3859, 12'd3860: - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q362 = + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q364 = coreFix_aluExe_1_dispToRegQ$first[136:125]; - default: CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q362 = + default: CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q364 = 12'd2303; endcase end @@ -48849,9 +48894,9 @@ module mkCore(CLK, begin case (coreFix_aluExe_1_dispToRegQ$first[123:119]) 5'd0, 5'd1, 5'd12, 5'd13, 5'd14, 5'd15, 5'd28, 5'd29, 5'd30, 5'd31: - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_12_ETC__q363 = + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_12_ETC__q365 = coreFix_aluExe_1_dispToRegQ$first[123:119]; - default: CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_12_ETC__q363 = + default: CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_12_ETC__q365 = 5'd10; endcase end @@ -48859,26 +48904,26 @@ module mkCore(CLK, begin case (coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[69:67]) 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q364 = + CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q366 = coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[69:67]; - default: CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q364 = 3'd7; + default: CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q366 = 3'd7; endcase end always@(coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData or - CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q364) + CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q366) begin case (coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[95:93]) 3'd0, 3'd1, 3'd2, 3'd3: - CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q365 = + CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q367 = coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[95:66]; 3'd4: - CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q365 = + CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q367 = { coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[95:93], 18'h2AAAA, coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[74:70], - CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q364, + CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q366, coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[66] }; - default: CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q365 = + default: CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q367 = 30'd715827882; endcase end @@ -48890,16 +48935,16 @@ module mkCore(CLK, begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229]) 5'd0: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q366 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q368 = IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14911; 5'd1: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q366 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q368 = coreFix_fpuMulDivExe_0_regToExeQ$first[225] ? { !coreFix_fpuMulDivExe_0_regToExeQ$first[139], coreFix_fpuMulDivExe_0_regToExeQ$first[138:76] } : { IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14964, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14909 }; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q366 = + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q368 = IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d13431; endcase end @@ -48908,9 +48953,9 @@ module mkCore(CLK, begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229]) 5'd0, 5'd1: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q367 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q369 = 64'h3FF0000000000000; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q367 = + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q369 = IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14911; endcase end @@ -48918,26 +48963,26 @@ module mkCore(CLK, begin case (coreFix_fpuMulDivExe_0_dispToRegQ$first[60:58]) 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q368 = + CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q370 = coreFix_fpuMulDivExe_0_dispToRegQ$first[60:58]; - default: CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q368 = 3'd7; + default: CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q370 = 3'd7; endcase end always@(coreFix_fpuMulDivExe_0_dispToRegQ$first or - CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q368) + CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q370) begin case (coreFix_fpuMulDivExe_0_dispToRegQ$first[86:84]) 3'd0, 3'd1, 3'd2, 3'd3: - CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q369 = + CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q371 = coreFix_fpuMulDivExe_0_dispToRegQ$first[86:57]; 3'd4: - CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q369 = + CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q371 = { coreFix_fpuMulDivExe_0_dispToRegQ$first[86:84], 18'h2AAAA, coreFix_fpuMulDivExe_0_dispToRegQ$first[65:61], - CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q368, + CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q370, coreFix_fpuMulDivExe_0_dispToRegQ$first[57] }; - default: CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q369 = + default: CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q371 = 30'd715827882; endcase end @@ -48947,10 +48992,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q370 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q372 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[1:0]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q370 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q372 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[1:0]; endcase end @@ -48961,12 +49006,12 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_processAmo[7:6]) 2'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q371 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q373 = SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4887; 2'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q371 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q373 = SEXT_SEL_ARR_SEL_ARR_coreFix_memExe_dMem_cache_ETC___d4901[63:0]; - default: CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q371 = + default: CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q373 = SEXT_SEL_ARR_SEL_ARR_coreFix_memExe_dMem_cache_ETC___d4909[63:0]; endcase end @@ -48977,12 +49022,12 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_processAmo[7:6]) 2'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q372 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q374 = SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4881; 2'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q372 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q374 = SEXT_SEL_ARR_SEL_ARR_coreFix_memExe_dMem_cache_ETC___d4901[127:64]; - default: CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q372 = + default: CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q374 = SEXT_SEL_ARR_SEL_ARR_coreFix_memExe_dMem_cache_ETC___d4909[127:64]; endcase end @@ -54117,12 +54162,12 @@ module mkCore(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo) $write("'h%h", - CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q371, + CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q373, " "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo) $write("'h%h", - CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q372, + CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q374, " "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo) @@ -54480,7 +54525,7 @@ module mkCore(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2632_BIT_288_3294_T_ETC___d23388 == 6'd6) + IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd6) $display("[Terminate CSR] being written (val = %x), ", "send terminate signal to host", rob$deqPort_0_deq_data[95:32]); @@ -54493,7 +54538,7 @@ module mkCore(CLK, $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && - next_pc__h1023233[63:0] != address__h1023286) + next_pc__h1023267[63:0] != address__h1023320) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && @@ -54651,7 +54696,7 @@ module mkCore(CLK, rob$deqPort_1_deq_data[469:465] != 5'd25) $write("instret:%0d PC:0x%0h instr:0x%08h", commitStage_rg_serial_num + - IF_rob_deqPort_0_canDeq__3983_THEN_IF_NOT_rob__ETC___d24105, + IF_rob_deqPort_0_canDeq__3985_THEN_IF_NOT_rob__ETC___d24107, rob$deqPort_1_deq_data[630:502], rob$deqPort_1_deq_data[501:470], " iType:"); @@ -54895,8 +54940,8 @@ module mkCore(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_aluExe_1_doExeAlu && coreFix_aluExe_1_regToExeQ$first[729] && - (x__h873780 != coreFix_aluExe_1_regToExeQ$first[177:49] || - coreFix_aluExe_1_regToExeQ$first[177:49] != y__h874034)) + (x__h873778 != coreFix_aluExe_1_regToExeQ$first[177:49] || + coreFix_aluExe_1_regToExeQ$first[177:49] != y__h874032)) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_aluExe_1_doExeAlu && @@ -54906,8 +54951,8 @@ module mkCore(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_aluExe_1_doExeAlu && coreFix_aluExe_1_regToExeQ$first[716] && - (x__h873780 != coreFix_aluExe_1_regToExeQ$first[177:49] || - coreFix_aluExe_1_regToExeQ$first[177:49] != y__h874034)) + (x__h873778 != coreFix_aluExe_1_regToExeQ$first[177:49] || + coreFix_aluExe_1_regToExeQ$first[177:49] != y__h874032)) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu && @@ -54922,8 +54967,8 @@ module mkCore(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu && coreFix_aluExe_0_regToExeQ$first[729] && - (x__h914821 != coreFix_aluExe_0_regToExeQ$first[177:49] || - coreFix_aluExe_0_regToExeQ$first[177:49] != y__h915075)) + (x__h914818 != coreFix_aluExe_0_regToExeQ$first[177:49] || + coreFix_aluExe_0_regToExeQ$first[177:49] != y__h915072)) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu && @@ -54933,8 +54978,8 @@ module mkCore(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu && coreFix_aluExe_0_regToExeQ$first[716] && - (x__h914821 != coreFix_aluExe_0_regToExeQ$first[177:49] || - coreFix_aluExe_0_regToExeQ$first[177:49] != y__h915075)) + (x__h914818 != coreFix_aluExe_0_regToExeQ$first[177:49] || + coreFix_aluExe_0_regToExeQ$first[177:49] != y__h915072)) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_aluExe_1_doRegReadAlu && @@ -57482,17 +57527,17 @@ module mkCore(CLK, if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) $write(" o: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) - $write("'h%h", value__h257365); + $write("'h%h", value__h257362); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) $write(" b: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) - $write("'h%h", value__h257529); + $write("'h%h", value__h257526); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) $write(" t: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) - $write("'h%h", x__h257641[64:0]); + $write("'h%h", x__h257638[64:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) $write(" sp: "); if (RST_N != `BSV_RESET_VALUE) @@ -64432,14 +64477,14 @@ module mkCore(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem) begin - v__h215838 = $time; + v__h215836 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem) - $write("%t : ", v__h215838, "[doRespLdMem]", " "); + $write("%t : ", v__h215836, "[doRespLdMem]", " "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem) $write("'h%h", t__h215266); + if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem) $write("'h%h", t__h215264); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem) $write("; "); if (RST_N != `BSV_RESET_VALUE) @@ -64583,15 +64628,15 @@ module mkCore(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward) begin - v__h218174 = $time; + v__h218172 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward) - $write("%t : ", v__h218174, "[doRespLdForward]", " "); + $write("%t : ", v__h218172, "[doRespLdForward]", " "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward) - $write("'h%h", t__h217619); + $write("'h%h", t__h217617); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward) $write("; "); if (RST_N != `BSV_RESET_VALUE) @@ -64760,14 +64805,14 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5614) begin - v__h275405 = $time; + v__h275404 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5614) - $write("%t : [Ld resp] ", v__h275405); + $write("%t : [Ld resp] ", v__h275404); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && @@ -66457,13 +66502,13 @@ module mkCore(CLK, if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5618) begin - v__h351164 = $time; + v__h351162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5618) - $write("%t : [Ld resp] ", v__h351164); + $write("%t : [Ld resp] ", v__h351162); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5618) @@ -68363,7 +68408,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == 3'd0) begin - v__h427780 = $time; + v__h427778 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) @@ -68371,7 +68416,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == 3'd0) - $write("%t : [Ld resp] ", v__h427780); + $write("%t : [Ld resp] ", v__h427778); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && @@ -70880,17 +70925,17 @@ module mkCore(CLK, if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" o: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) - $write("'h%h", value__h242587); + $write("'h%h", value__h242584); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" b: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) - $write("'h%h", value__h242751); + $write("'h%h", value__h242748); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" t: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) - $write("'h%h", x__h242863[64:0]); + $write("'h%h", x__h242860[64:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" sp: "); if (RST_N != `BSV_RESET_VALUE) @@ -70930,17 +70975,17 @@ module mkCore(CLK, if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" o: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) - $write("'h%h", value__h243744); + $write("'h%h", value__h243741); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" b: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) - $write("'h%h", value__h243908); + $write("'h%h", value__h243905); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" t: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) - $write("'h%h", x__h244020[64:0]); + $write("'h%h", x__h244017[64:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" sp: "); if (RST_N != `BSV_RESET_VALUE) @@ -74137,7 +74182,7 @@ module mkCore(CLK, $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas && - v__h841897 == 2'd0) + v__h841893 == 2'd0) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming_SystemInst && diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkCoreW.v b/src_SSITH_P3/Verilog_RTL_sim/mkCoreW.v index 1d77190..ebf9b83 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkCoreW.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkCoreW.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jul 1 17:04:53 BST 2020 +// On Thu Jul 2 02:59:28 BST 2020 // // // Ports: @@ -783,7 +783,7 @@ module mkCoreW(RST_N_dm_power_on_reset, ifcs_1_1_noRoute_currentReq$port1__read, ifcs_1_noRoute_inner_currentReq$port1__read, msNoSynth_1_arNoSynth_buffer_enqw$wget, - msNoSynth_1_awNoSynth_snk_putWire$wget; + msNoSynth_1_awNoSynth_buffer_enqw$wget; wire [74 : 0] tagController_tmp_shimSlave_wff_rv$port0__write_1, tagController_tmp_shimSlave_wff_rv$port1__read, tagController_tmp_shimSlave_wff_rv$port2__read, @@ -3313,12 +3313,12 @@ module mkCoreW(RST_N_dm_power_on_reset, MUX_flitToSink_2$wset_1__SEL_1, MUX_flitToSink_2$wset_1__SEL_3, MUX_ifcs_0_1_state_1$write_1__SEL_1, - MUX_ifcs_0_state$write_1__PSEL_3, + MUX_ifcs_0_state$write_1__PSEL_1, MUX_ifcs_0_state$write_1__SEL_1, MUX_ifcs_0_state$write_1__SEL_2, MUX_ifcs_0_state$write_1__SEL_3, MUX_ifcs_1_1_state_1$write_1__SEL_1, - MUX_ifcs_1_state$write_1__PSEL_3, + MUX_ifcs_1_state$write_1__PSEL_1, MUX_ifcs_1_state$write_1__SEL_1, MUX_ifcs_1_state$write_1__SEL_2, MUX_ifcs_1_state$write_1__SEL_3, @@ -5303,22 +5303,22 @@ module mkCoreW(RST_N_dm_power_on_reset, // rule RL_rl_dm_hart0_reset_wait assign CAN_FIRE_RL_rl_dm_hart0_reset_wait = (rg_hart0_reset_delay != 8'd1 || - proc$RDY_start && - debug_module$RDY_hart0_reset_client_response_put) && + debug_module$RDY_hart0_reset_client_response_put && + proc$RDY_start) && rg_hart0_reset_delay != 8'd0 ; assign WILL_FIRE_RL_rl_dm_hart0_reset_wait = CAN_FIRE_RL_rl_dm_hart0_reset_wait && !EN_start ; // rule RL_ClientServerRequest assign CAN_FIRE_RL_ClientServerRequest = - proc$RDY_hart0_run_halt_server_request_put && - debug_module$RDY_hart0_client_run_halt_request_get ; + debug_module$RDY_hart0_client_run_halt_request_get && + proc$RDY_hart0_run_halt_server_request_put ; assign WILL_FIRE_RL_ClientServerRequest = CAN_FIRE_RL_ClientServerRequest ; // rule RL_ClientServerResponse assign CAN_FIRE_RL_ClientServerResponse = - proc$RDY_hart0_run_halt_server_response_get && - debug_module$RDY_hart0_client_run_halt_response_put ; + debug_module$RDY_hart0_client_run_halt_response_put && + proc$RDY_hart0_run_halt_server_response_get ; assign WILL_FIRE_RL_ClientServerResponse = CAN_FIRE_RL_ClientServerResponse ; @@ -5330,15 +5330,15 @@ module mkCoreW(RST_N_dm_power_on_reset, // rule RL_ClientServerResponse_1 assign CAN_FIRE_RL_ClientServerResponse_1 = - proc$RDY_hart0_gpr_mem_server_response_get && - debug_module$RDY_hart0_gpr_mem_client_response_put ; + debug_module$RDY_hart0_gpr_mem_client_response_put && + proc$RDY_hart0_gpr_mem_server_response_get ; assign WILL_FIRE_RL_ClientServerResponse_1 = CAN_FIRE_RL_ClientServerResponse_1 ; // rule RL_ClientServerResponse_2 assign CAN_FIRE_RL_ClientServerResponse_2 = - proc$RDY_hart0_csr_mem_server_response_get && - debug_module$RDY_hart0_csr_mem_client_response_put ; + debug_module$RDY_hart0_csr_mem_client_response_put && + proc$RDY_hart0_csr_mem_server_response_get ; assign WILL_FIRE_RL_ClientServerResponse_2 = CAN_FIRE_RL_ClientServerResponse_2 ; @@ -7758,15 +7758,15 @@ module mkCoreW(RST_N_dm_power_on_reset, // rule RL_ClientServerRequest_1 assign CAN_FIRE_RL_ClientServerRequest_1 = - proc$RDY_hart0_gpr_mem_server_request_put && - debug_module$RDY_hart0_gpr_mem_client_request_get ; + debug_module$RDY_hart0_gpr_mem_client_request_get && + proc$RDY_hart0_gpr_mem_server_request_put ; assign WILL_FIRE_RL_ClientServerRequest_1 = CAN_FIRE_RL_ClientServerRequest_1 ; // rule RL_ClientServerRequest_2 assign CAN_FIRE_RL_ClientServerRequest_2 = - proc$RDY_hart0_csr_mem_server_request_put && - debug_module$RDY_hart0_csr_mem_client_request_get ; + debug_module$RDY_hart0_csr_mem_client_request_get && + proc$RDY_hart0_csr_mem_server_request_put ; assign WILL_FIRE_RL_ClientServerRequest_2 = CAN_FIRE_RL_ClientServerRequest_2 ; @@ -8623,33 +8623,33 @@ module mkCoreW(RST_N_dm_power_on_reset, assign MUX_ifcs_0_1_state_1$write_1__SEL_1 = WILL_FIRE_RL_ifcs_0_1_followFlits_1 && ssNoSynth_0_rNoSynth_buffer_ff$D_OUT[1] ; - assign MUX_ifcs_0_state$write_1__SEL_1 = - WILL_FIRE_RL_ifcs_0_firstFlit && - IF_merged_0_outflit_whas__501_THEN_NOT_merged__ETC___d1556 ; - assign MUX_ifcs_0_state$write_1__SEL_2 = - WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp && - IF_merged_0_outflit_whas__501_THEN_NOT_merged__ETC___d1556 ; - assign MUX_ifcs_0_state$write_1__PSEL_3 = + assign MUX_ifcs_0_state$write_1__PSEL_1 = WILL_FIRE_RL_ifcs_0_drainFlits || WILL_FIRE_RL_ifcs_0_followFlits ; - assign MUX_ifcs_0_state$write_1__SEL_3 = - MUX_ifcs_0_state$write_1__PSEL_3 && + assign MUX_ifcs_0_state$write_1__SEL_1 = + MUX_ifcs_0_state$write_1__PSEL_1 && IF_merged_0_outflit_whas__501_THEN_merged_0_ou_ETC___d1561 ; + assign MUX_ifcs_0_state$write_1__SEL_2 = + WILL_FIRE_RL_ifcs_0_firstFlit && + IF_merged_0_outflit_whas__501_THEN_NOT_merged__ETC___d1556 ; + assign MUX_ifcs_0_state$write_1__SEL_3 = + WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp && + IF_merged_0_outflit_whas__501_THEN_NOT_merged__ETC___d1556 ; assign MUX_ifcs_1_1_state_1$write_1__SEL_1 = WILL_FIRE_RL_ifcs_1_1_followFlits_1 && ssNoSynth_1_rNoSynth_buffer_ff$D_OUT[1] ; - assign MUX_ifcs_1_state$write_1__SEL_1 = - WILL_FIRE_RL_ifcs_1_firstFlit && - IF_merged_1_outflit_whas__601_THEN_NOT_merged__ETC___d1650 ; - assign MUX_ifcs_1_state$write_1__SEL_2 = - WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp && - IF_merged_1_outflit_whas__601_THEN_NOT_merged__ETC___d1650 ; - assign MUX_ifcs_1_state$write_1__PSEL_3 = + assign MUX_ifcs_1_state$write_1__PSEL_1 = WILL_FIRE_RL_ifcs_1_drainFlits || WILL_FIRE_RL_ifcs_1_followFlits ; - assign MUX_ifcs_1_state$write_1__SEL_3 = - MUX_ifcs_1_state$write_1__PSEL_3 && + assign MUX_ifcs_1_state$write_1__SEL_1 = + MUX_ifcs_1_state$write_1__PSEL_1 && IF_merged_1_outflit_whas__601_THEN_merged_1_ou_ETC___d1655 ; + assign MUX_ifcs_1_state$write_1__SEL_2 = + WILL_FIRE_RL_ifcs_1_firstFlit && + IF_merged_1_outflit_whas__601_THEN_NOT_merged__ETC___d1650 ; + assign MUX_ifcs_1_state$write_1__SEL_3 = + WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp && + IF_merged_1_outflit_whas__601_THEN_NOT_merged__ETC___d1650 ; assign MUX_ifcs_2_1_state$write_1__SEL_1 = WILL_FIRE_RL_ifcs_2_1_followFlits && ssNoSynth_2_rNoSynth_buffer_ff$D_OUT[1] ; @@ -8917,7 +8917,7 @@ module mkCoreW(RST_N_dm_power_on_reset, WILL_FIRE_RL_sinks_1_1_0_doPut ? MUX_ifcs_0_1_snk_putWire$wset_1__VAL_1 : ifcs_0_1_noRouteRsp$D_OUT ; - assign msNoSynth_1_awNoSynth_snk_putWire$wget = + assign msNoSynth_1_awNoSynth_buffer_enqw$wget = { debug_module$master_awid, debug_module$master_awaddr, debug_module$master_awlen, @@ -9706,20 +9706,20 @@ module mkCoreW(RST_N_dm_power_on_reset, MUX_ifcs_0_state$write_1__SEL_2 or MUX_ifcs_0_state$write_1__SEL_3) begin case (1'b1) // synopsys parallel_case - MUX_ifcs_0_state$write_1__SEL_1: ifcs_0_state$D_IN = 2'd1; - MUX_ifcs_0_state$write_1__SEL_2: ifcs_0_state$D_IN = 2'd2; - MUX_ifcs_0_state$write_1__SEL_3: ifcs_0_state$D_IN = 2'd0; + MUX_ifcs_0_state$write_1__SEL_1: ifcs_0_state$D_IN = 2'd0; + MUX_ifcs_0_state$write_1__SEL_2: ifcs_0_state$D_IN = 2'd1; + MUX_ifcs_0_state$write_1__SEL_3: ifcs_0_state$D_IN = 2'd2; default: ifcs_0_state$D_IN = 2'b10 /* unspecified value */ ; endcase end assign ifcs_0_state$EN = + (WILL_FIRE_RL_ifcs_0_drainFlits || + WILL_FIRE_RL_ifcs_0_followFlits) && + IF_merged_0_outflit_whas__501_THEN_merged_0_ou_ETC___d1561 || WILL_FIRE_RL_ifcs_0_firstFlit && IF_merged_0_outflit_whas__501_THEN_NOT_merged__ETC___d1556 || WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp && - IF_merged_0_outflit_whas__501_THEN_NOT_merged__ETC___d1556 || - (WILL_FIRE_RL_ifcs_0_drainFlits || - WILL_FIRE_RL_ifcs_0_followFlits) && - IF_merged_0_outflit_whas__501_THEN_merged_0_ou_ETC___d1561 ; + IF_merged_0_outflit_whas__501_THEN_NOT_merged__ETC___d1556 ; // register ifcs_0_state_1 assign ifcs_0_state_1$D_IN = 1'd0 ; @@ -9764,20 +9764,20 @@ module mkCoreW(RST_N_dm_power_on_reset, MUX_ifcs_1_state$write_1__SEL_2 or MUX_ifcs_1_state$write_1__SEL_3) begin case (1'b1) // synopsys parallel_case - MUX_ifcs_1_state$write_1__SEL_1: ifcs_1_state$D_IN = 2'd1; - MUX_ifcs_1_state$write_1__SEL_2: ifcs_1_state$D_IN = 2'd2; - MUX_ifcs_1_state$write_1__SEL_3: ifcs_1_state$D_IN = 2'd0; + MUX_ifcs_1_state$write_1__SEL_1: ifcs_1_state$D_IN = 2'd0; + MUX_ifcs_1_state$write_1__SEL_2: ifcs_1_state$D_IN = 2'd1; + MUX_ifcs_1_state$write_1__SEL_3: ifcs_1_state$D_IN = 2'd2; default: ifcs_1_state$D_IN = 2'b10 /* unspecified value */ ; endcase end assign ifcs_1_state$EN = + (WILL_FIRE_RL_ifcs_1_drainFlits || + WILL_FIRE_RL_ifcs_1_followFlits) && + IF_merged_1_outflit_whas__601_THEN_merged_1_ou_ETC___d1655 || WILL_FIRE_RL_ifcs_1_firstFlit && IF_merged_1_outflit_whas__601_THEN_NOT_merged__ETC___d1650 || WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp && - IF_merged_1_outflit_whas__601_THEN_NOT_merged__ETC___d1650 || - (WILL_FIRE_RL_ifcs_1_drainFlits || - WILL_FIRE_RL_ifcs_1_followFlits) && - IF_merged_1_outflit_whas__601_THEN_merged_1_ou_ETC___d1655 ; + IF_merged_1_outflit_whas__601_THEN_NOT_merged__ETC___d1650 ; // register ifcs_1_state_1 assign ifcs_1_state_1$D_IN = 1'd0 ; @@ -10332,7 +10332,7 @@ module mkCoreW(RST_N_dm_power_on_reset, assign merged_1_awff$D_IN = msNoSynth_1_awNoSynth_buffer_ff$EMPTY_N ? msNoSynth_1_awNoSynth_buffer_ff$D_OUT : - msNoSynth_1_awNoSynth_snk_putWire$wget ; + msNoSynth_1_awNoSynth_buffer_enqw$wget ; assign merged_1_awff$ENQ = CAN_FIRE_RL_merged_1_awFlit ; assign merged_1_awff$DEQ = CAN_FIRE_RL_merged_1_genFirst ; assign merged_1_awff$CLR = 1'b0 ; @@ -10432,7 +10432,7 @@ module mkCoreW(RST_N_dm_power_on_reset, // submodule msNoSynth_1_awNoSynth_buffer_ff assign msNoSynth_1_awNoSynth_buffer_ff$D_IN = - msNoSynth_1_awNoSynth_snk_putWire$wget ; + msNoSynth_1_awNoSynth_buffer_enqw$wget ; assign msNoSynth_1_awNoSynth_buffer_ff$ENQ = CAN_FIRE_RL_msNoSynth_1_awNoSynth_buffer_enqueue ; assign msNoSynth_1_awNoSynth_buffer_ff$DEQ = diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkDCRqMshrWrapper.v b/src_SSITH_P3/Verilog_RTL_sim/mkDCRqMshrWrapper.v index c90e2ad..43d0db2 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkDCRqMshrWrapper.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkDCRqMshrWrapper.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:40:05 BST 2020 +// On Thu Jul 2 02:54:01 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkDM_Abstract_Commands.v b/src_SSITH_P3/Verilog_RTL_sim/mkDM_Abstract_Commands.v index 7c9f3fb..0dc0892 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkDM_Abstract_Commands.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkDM_Abstract_Commands.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 24 20:09:56 BST 2020 +// On Thu Jul 2 02:46:43 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkDM_Run_Control.v b/src_SSITH_P3/Verilog_RTL_sim/mkDM_Run_Control.v index 36c61c8..2cdae8a 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkDM_Run_Control.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkDM_Run_Control.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 24 20:09:55 BST 2020 +// On Thu Jul 2 02:46:43 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkDM_System_Bus.v b/src_SSITH_P3/Verilog_RTL_sim/mkDM_System_Bus.v index 2011a0e..9f7aa78 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkDM_System_Bus.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkDM_System_Bus.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:31:20 BST 2020 +// On Thu Jul 2 02:46:58 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkDPRqMshrWrapper.v b/src_SSITH_P3/Verilog_RTL_sim/mkDPRqMshrWrapper.v index 2879663..2621c8b 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkDPRqMshrWrapper.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkDPRqMshrWrapper.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:40:06 BST 2020 +// On Thu Jul 2 02:54:03 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkDPipeline.v b/src_SSITH_P3/Verilog_RTL_sim/mkDPipeline.v index 2bd43fd..3a7af31 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkDPipeline.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkDPipeline.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:40:10 BST 2020 +// On Thu Jul 2 02:54:05 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkDTlbSynth.v b/src_SSITH_P3/Verilog_RTL_sim/mkDTlbSynth.v index ca35757..444409e 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkDTlbSynth.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkDTlbSynth.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:40:38 BST 2020 +// On Thu Jul 2 02:54:36 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkDebug_Module.v b/src_SSITH_P3/Verilog_RTL_sim/mkDebug_Module.v index 77766e0..b4ef89f 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkDebug_Module.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkDebug_Module.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:31:22 BST 2020 +// On Thu Jul 2 02:46:59 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkDirPredictor.v b/src_SSITH_P3/Verilog_RTL_sim/mkDirPredictor.v index 40fd2d0..e0ff3ab 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkDirPredictor.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkDirPredictor.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:42:01 BST 2020 +// On Thu Jul 2 02:56:55 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkDivExecQ.v b/src_SSITH_P3/Verilog_RTL_sim/mkDivExecQ.v index 219b59a..9734585 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkDivExecQ.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkDivExecQ.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:41:56 BST 2020 +// On Thu Jul 2 02:55:57 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkDoubleDiv.v b/src_SSITH_P3/Verilog_RTL_sim/mkDoubleDiv.v index c353aa5..8a4c632 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkDoubleDiv.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkDoubleDiv.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:41:35 BST 2020 +// On Thu Jul 2 02:55:36 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkDoubleFMA.v b/src_SSITH_P3/Verilog_RTL_sim/mkDoubleFMA.v index fe0c4fc..52d89f4 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkDoubleFMA.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkDoubleFMA.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:41:42 BST 2020 +// On Thu Jul 2 02:55:43 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkDoubleSqrt.v b/src_SSITH_P3/Verilog_RTL_sim/mkDoubleSqrt.v index 0773421..55616b7 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkDoubleSqrt.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkDoubleSqrt.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:41:39 BST 2020 +// On Thu Jul 2 02:55:40 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkDummyStoreBuffer.v b/src_SSITH_P3/Verilog_RTL_sim/mkDummyStoreBuffer.v index 9a56aa8..2da90a8 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkDummyStoreBuffer.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkDummyStoreBuffer.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:32:19 BST 2020 +// On Thu Jul 2 02:47:50 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkEpochManager.v b/src_SSITH_P3/Verilog_RTL_sim/mkEpochManager.v index 2dc4f3d..4850502 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkEpochManager.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkEpochManager.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:32:07 BST 2020 +// On Thu Jul 2 02:47:40 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkFetchStage.v b/src_SSITH_P3/Verilog_RTL_sim/mkFetchStage.v index ae8d1ab..f9a0b95 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkFetchStage.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkFetchStage.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:42:16 BST 2020 +// On Thu Jul 2 02:57:09 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkFmaExecQ.v b/src_SSITH_P3/Verilog_RTL_sim/mkFmaExecQ.v index 98cc166..03723c1 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkFmaExecQ.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkFmaExecQ.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:41:44 BST 2020 +// On Thu Jul 2 02:55:45 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkFpuMulDivDispToRegFifo.v b/src_SSITH_P3/Verilog_RTL_sim/mkFpuMulDivDispToRegFifo.v index 8ac4bf7..04eb219 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkFpuMulDivDispToRegFifo.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkFpuMulDivDispToRegFifo.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:41:57 BST 2020 +// On Thu Jul 2 02:55:59 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkFpuMulDivRegToExeFifo.v b/src_SSITH_P3/Verilog_RTL_sim/mkFpuMulDivRegToExeFifo.v index b70aea0..e8a3047 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkFpuMulDivRegToExeFifo.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkFpuMulDivRegToExeFifo.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:41:57 BST 2020 +// On Thu Jul 2 02:55:59 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkGSelectGHistReg.v b/src_SSITH_P3/Verilog_RTL_sim/mkGSelectGHistReg.v index fc0a568..093ab4f 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkGSelectGHistReg.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkGSelectGHistReg.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:41:58 BST 2020 +// On Thu Jul 2 02:56:52 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkGSelectPred.v b/src_SSITH_P3/Verilog_RTL_sim/mkGSelectPred.v index 6e95ab6..0663082 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkGSelectPred.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkGSelectPred.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:41:58 BST 2020 +// On Thu Jul 2 02:56:52 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkGShareGHistReg.v b/src_SSITH_P3/Verilog_RTL_sim/mkGShareGHistReg.v index ac25250..6be318e 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkGShareGHistReg.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkGShareGHistReg.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:41:59 BST 2020 +// On Thu Jul 2 02:56:53 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkGSharePred.v b/src_SSITH_P3/Verilog_RTL_sim/mkGSharePred.v index e7257ce..04ed065 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkGSharePred.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkGSharePred.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:41:59 BST 2020 +// On Thu Jul 2 02:56:53 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkIBankWrapper.v b/src_SSITH_P3/Verilog_RTL_sim/mkIBankWrapper.v index 8b6103b..bdb9d65 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkIBankWrapper.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkIBankWrapper.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:40:16 BST 2020 +// On Thu Jul 2 02:54:12 BST 2020 // // // Ports: @@ -587,7 +587,7 @@ module mkIBankWrapper(CLK, SEL_ARR_m_fromPQ_data_0_13_BITS_65_TO_2_22_m_f_ETC___d425, addr__h42425; reg [31 : 0] CASE_m_cRqMshrpipelineResp_getRq_BITS_5_TO_2__ETC__q37, - CASE_sel1595_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36; + CASE_sel1594_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36; reg [2 : 0] CASE_m_rqToPQ_deqP_0_m_rqToPQ_data_0_BITS_2_TO_ETC__q31, x__h45568; reg [1 : 0] CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_1_TO_ETC__q38, @@ -620,7 +620,7 @@ module mkIBankWrapper(CLK, IF_m_pipeline_first__60_BITS_518_TO_516_65_EQ__ETC___d608; wire [5 : 0] IF_m_pipeline_first__60_BITS_521_TO_520_71_EQ__ETC___d613, SEL_ARR_m_rqToPQ_data_0_32_BITS_5_TO_4_42_m_rq_ETC___d854; - wire [3 : 0] sel__h51595; + wire [3 : 0] sel__h51594; wire [2 : 0] IF_m_cRqMshr_pipelineResp_searchEndOfChain_m_c_ETC___d628, SEL_ARR_m_fromPQ_data_0_13_BIT_518_49_m_fromPQ_ETC___d461, SEL_ARR_m_rsToPQ_data_0_58_BIT_515_75_m_rsToPQ_ETC___d787, @@ -1054,7 +1054,7 @@ module mkIBankWrapper(CLK, WILL_FIRE_RL_m_pipelineResp_pRq && !m_pipeline$first[575] ; assign MUX_m_cRqMshr$pipelineResp_setResult_2__VAL_1 = { 4'd15 - m_cRqMshr$pipelineResp_getRq[5:2] != 4'd0, - CASE_sel1595_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36, + CASE_sel1594_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36, 1'd1, CASE_m_cRqMshrpipelineResp_getRq_BITS_5_TO_2__ETC__q37 } ; assign MUX_m_cRqMshr$pipelineResp_setStateSlot_2__VAL_2 = @@ -1713,7 +1713,7 @@ module mkIBankWrapper(CLK, assign resp_addr__h45889 = { m_cRqMshr$sendRsToP_cRq_getSlot[53:1], m_cRqMshr$sendRsToP_cRq_getRq[10:0] } ; - assign sel__h51595 = m_cRqMshr$pipelineResp_getRq[5:2] + 4'd1 ; + assign sel__h51594 = m_cRqMshr$pipelineResp_getRq[5:2] + 4'd1 ; assign v__h10212 = IF_m_rsToPQ_enqReq_lat_1_whas__1_THEN_m_rsToPQ_ETC___d40 ? v__h10363 : @@ -2149,56 +2149,56 @@ module mkIBankWrapper(CLK, m_fromPQ_data_1[586]; endcase end - always@(sel__h51595 or m_pipeline$first) + always@(sel__h51594 or m_pipeline$first) begin - case (sel__h51595) + case (sel__h51594) 4'd0: - CASE_sel1595_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1594_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[31:0]; 4'd1: - CASE_sel1595_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1594_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[63:32]; 4'd2: - CASE_sel1595_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1594_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[95:64]; 4'd3: - CASE_sel1595_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1594_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[127:96]; 4'd4: - CASE_sel1595_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1594_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[159:128]; 4'd5: - CASE_sel1595_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1594_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[191:160]; 4'd6: - CASE_sel1595_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1594_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[223:192]; 4'd7: - CASE_sel1595_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1594_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[255:224]; 4'd8: - CASE_sel1595_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1594_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[287:256]; 4'd9: - CASE_sel1595_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1594_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[319:288]; 4'd10: - CASE_sel1595_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1594_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[351:320]; 4'd11: - CASE_sel1595_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1594_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[383:352]; 4'd12: - CASE_sel1595_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1594_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[415:384]; 4'd13: - CASE_sel1595_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1594_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[447:416]; 4'd14: - CASE_sel1595_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1594_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[479:448]; 4'd15: - CASE_sel1595_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1594_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[511:480]; endcase end diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkICRqMshrWrapper.v b/src_SSITH_P3/Verilog_RTL_sim/mkICRqMshrWrapper.v index c5c0f12..4cb8033 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkICRqMshrWrapper.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkICRqMshrWrapper.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:40:11 BST 2020 +// On Thu Jul 2 02:54:06 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkICoCache.v b/src_SSITH_P3/Verilog_RTL_sim/mkICoCache.v index f2a12f1..4bd3d3a 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkICoCache.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkICoCache.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:40:16 BST 2020 +// On Thu Jul 2 02:54:13 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkIPRqMshrWrapper.v b/src_SSITH_P3/Verilog_RTL_sim/mkIPRqMshrWrapper.v index fe9ca81..92a46f7 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkIPRqMshrWrapper.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkIPRqMshrWrapper.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:40:11 BST 2020 +// On Thu Jul 2 02:54:07 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkIPipeline.v b/src_SSITH_P3/Verilog_RTL_sim/mkIPipeline.v index d5a9732..b185334 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkIPipeline.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkIPipeline.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:40:14 BST 2020 +// On Thu Jul 2 02:54:09 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkITlb.v b/src_SSITH_P3/Verilog_RTL_sim/mkITlb.v index 8023218..0561dd9 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkITlb.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkITlb.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:32:04 BST 2020 +// On Thu Jul 2 02:47:38 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkJtagTap.v b/src_SSITH_P3/Verilog_RTL_sim/mkJtagTap.v index 5c2261b..f64fcce 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkJtagTap.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkJtagTap.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 24 20:09:23 BST 2020 +// On Thu Jul 2 02:46:12 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkL2Tlb.v b/src_SSITH_P3/Verilog_RTL_sim/mkL2Tlb.v index 445eb87..769b318 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkL2Tlb.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkL2Tlb.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:39:45 BST 2020 +// On Thu Jul 2 02:53:38 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkLLCache.v b/src_SSITH_P3/Verilog_RTL_sim/mkLLCache.v index d9cabbe..0edb1fd 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkLLCache.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkLLCache.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:41:29 BST 2020 +// On Thu Jul 2 02:55:29 BST 2020 // // // Ports: @@ -1306,12 +1306,12 @@ module mkLLCache(CLK, SEL_ARR_cache_toCQ_data_0_105_BITS_66_TO_3_114_ETC___d4117, addr__h243512, addr__h261018; - reg [3 : 0] x__h237100, x__h520773; + reg [3 : 0] x__h237100, x__h520774; reg [2 : 0] CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q235, CASE_cache_rsLdToDmaQ_deqP_0_cache_rsLdToDmaQ__ETC__q299, CASE_cache_rsStToDmaQ_deqP_0_cache_rsStToDmaQ__ETC__q5, x__h243454, - x__h506630; + x__h506631; reg [1 : 0] CASE_cache_cRqMshrpipelineResp_getRq_BIT_70_0_ETC__q282, CASE_cache_cRqMshrstuck_get_BITS_3_TO_2_0_cac_ETC__q2, CASE_cache_cRqMshrstuck_get_BITS_7_TO_6_0_cac_ETC__q1, @@ -1561,8 +1561,8 @@ module mkLLCache(CLK, SEL_ARR_NOT_cache_toMQ_data_0_306_BIT_644_307__ETC___d4313, x__h237389, x__h264297, - x__h503463, - x__h503508; + x__h503464, + x__h503509; wire [645 : 0] IF_cache_doLdAfterReplace_262_THEN_2_CONCAT_DO_ETC___d2271; wire [643 : 0] DONTCARE_CONCAT_SEL_ARR_cache_toMQ_data_0_306__ETC___d4328, IF_IF_cache_toMQ_enqReq_lat_1_whas__40_THEN_ca_ETC___d847, @@ -4246,12 +4246,12 @@ module mkLLCache(CLK, { 520'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, SEL_ARR_cache_toCQ_data_0_105_BITS_66_TO_3_114_ETC___d4117, CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q283, - x__h503463 } ; + x__h503464 } ; assign DONTCARE_CONCAT_SEL_ARR_cache_toMQ_data_0_306__ETC___d4328 = { 575'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BITS__ETC__q286, CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_4_ETC__q287, - x__h520773 } ; + x__h520774 } ; assign IF_IF_NOT_cache_cRqMshr_sendRqToC_getSlot_IF_c_ETC___d2795 = (cache_cRqMshr$sendRqToC_getSlot[3:2] == 2'd1 && cache_cRqMshr$sendRqToC_getSlot[7:6] == 2'd1) ? @@ -6055,10 +6055,10 @@ module mkLLCache(CLK, CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q270, SEL_ARR_cache_toCQ_data_0_105_BITS_66_TO_3_114_ETC___d4117 } ; assign SEL_ARR_cache_toCQ_data_0_105_BIT_520_136_cach_ETC___d4203 = - { x__h503508, + { x__h503509, !CASE_cache_toCQ_deqP_0_NOT_cache_toCQ_data_0_B_ETC__q275, SEL_ARR_cache_toCQ_data_0_105_BIT_518_147_cach_ETC___d4196, - x__h506630 } ; + x__h506631 } ; assign SEL_ARR_cache_toMQ_data_0_306_BITS_511_TO_448__ETC___d4663 = { CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BITS__ETC__q254, CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BITS__ETC__q255, @@ -6694,29 +6694,29 @@ module mkLLCache(CLK, always@(cache_toCQ_deqP or cache_toCQ_data_0 or cache_toCQ_data_1) begin case (cache_toCQ_deqP) - 1'd0: x__h503463 = cache_toCQ_data_0[0]; - 1'd1: x__h503463 = cache_toCQ_data_1[0]; + 1'd0: x__h503464 = cache_toCQ_data_0[0]; + 1'd1: x__h503464 = cache_toCQ_data_1[0]; endcase end always@(cache_toCQ_deqP or cache_toCQ_data_0 or cache_toCQ_data_1) begin case (cache_toCQ_deqP) - 1'd0: x__h503508 = cache_toCQ_data_0[520]; - 1'd1: x__h503508 = cache_toCQ_data_1[520]; + 1'd0: x__h503509 = cache_toCQ_data_0[520]; + 1'd1: x__h503509 = cache_toCQ_data_1[520]; endcase end always@(cache_toCQ_deqP or cache_toCQ_data_0 or cache_toCQ_data_1) begin case (cache_toCQ_deqP) - 1'd0: x__h506630 = cache_toCQ_data_0[2:0]; - 1'd1: x__h506630 = cache_toCQ_data_1[2:0]; + 1'd0: x__h506631 = cache_toCQ_data_0[2:0]; + 1'd1: x__h506631 = cache_toCQ_data_1[2:0]; endcase end always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1) begin case (cache_toMQ_deqP) - 1'd0: x__h520773 = cache_toMQ_data_0[3:0]; - 1'd1: x__h520773 = cache_toMQ_data_1[3:0]; + 1'd0: x__h520774 = cache_toMQ_data_0[3:0]; + 1'd1: x__h520774 = cache_toMQ_data_1[3:0]; endcase end always@(cache_rsFromCQ_deqP or diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkLLPipeline.v b/src_SSITH_P3/Verilog_RTL_sim/mkLLPipeline.v index 5ccf49e..8c59b66 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkLLPipeline.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkLLPipeline.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:41:17 BST 2020 +// On Thu Jul 2 02:55:17 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkLSQIssueLdQ.v b/src_SSITH_P3/Verilog_RTL_sim/mkLSQIssueLdQ.v index c68d3fc..f9af01c 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkLSQIssueLdQ.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkLSQIssueLdQ.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:37:37 BST 2020 +// On Thu Jul 2 02:51:59 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkLastLvCRqMshr.v b/src_SSITH_P3/Verilog_RTL_sim/mkLastLvCRqMshr.v index ba40277..7501254 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkLastLvCRqMshr.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkLastLvCRqMshr.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:41:09 BST 2020 +// On Thu Jul 2 02:55:09 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkMMIOInst.v b/src_SSITH_P3/Verilog_RTL_sim/mkMMIOInst.v index b50198d..104987e 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkMMIOInst.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkMMIOInst.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:31:51 BST 2020 +// On Thu Jul 2 02:47:28 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkMemDispToRegFifo.v b/src_SSITH_P3/Verilog_RTL_sim/mkMemDispToRegFifo.v index 6ff6335..4e3e366 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkMemDispToRegFifo.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkMemDispToRegFifo.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:40:29 BST 2020 +// On Thu Jul 2 02:54:27 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkMemLoader.v b/src_SSITH_P3/Verilog_RTL_sim/mkMemLoader.v index 90519e4..60007af 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkMemLoader.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkMemLoader.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:40:44 BST 2020 +// On Thu Jul 2 02:54:45 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkMemRegToExeFifo.v b/src_SSITH_P3/Verilog_RTL_sim/mkMemRegToExeFifo.v index 1bf5605..f7fa977 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkMemRegToExeFifo.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkMemRegToExeFifo.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:40:29 BST 2020 +// On Thu Jul 2 02:54:27 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkMinimumExecQ.v b/src_SSITH_P3/Verilog_RTL_sim/mkMinimumExecQ.v index 3144206..3693886 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkMinimumExecQ.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkMinimumExecQ.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:41:44 BST 2020 +// On Thu Jul 2 02:55:45 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkMulExecQ.v b/src_SSITH_P3/Verilog_RTL_sim/mkMulExecQ.v index 484f163..56cc7ee 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkMulExecQ.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkMulExecQ.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:41:56 BST 2020 +// On Thu Jul 2 02:55:57 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkNullTransCache.v b/src_SSITH_P3/Verilog_RTL_sim/mkNullTransCache.v index 809a84d..4101373 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkNullTransCache.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkNullTransCache.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:31:48 BST 2020 +// On Thu Jul 2 02:47:22 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkP3_Core.v b/src_SSITH_P3/Verilog_RTL_sim/mkP3_Core.v index 707f251..85c4ebe 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkP3_Core.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkP3_Core.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jul 1 17:05:04 BST 2020 +// On Thu Jul 2 02:59:38 BST 2020 // // // Ports: @@ -1338,7 +1338,7 @@ module mkP3_Core(CLK, // rule RL_rl_ndm_reset_wait assign CAN_FIRE_RL_rl_ndm_reset_wait = (rg_ndm_reset_delay != 8'd1 || - corew$RDY_start && corew$RDY_ndm_reset_client_response_put) && + corew$RDY_ndm_reset_client_response_put && corew$RDY_start) && rg_ndm_reset_delay != 8'd0 ; assign WILL_FIRE_RL_rl_ndm_reset_wait = CAN_FIRE_RL_rl_ndm_reset_wait ; diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkPLIC_16_2_7.v b/src_SSITH_P3/Verilog_RTL_sim/mkPLIC_16_2_7.v index 13b3ece..99fff55 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkPLIC_16_2_7.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkPLIC_16_2_7.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:31:11 BST 2020 +// On Thu Jul 2 02:46:52 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkPowerOnReset.v b/src_SSITH_P3/Verilog_RTL_sim/mkPowerOnReset.v index 05a0e23..0f85af6 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkPowerOnReset.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkPowerOnReset.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 24 20:09:19 BST 2020 +// On Thu Jul 2 02:46:07 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkProc.v b/src_SSITH_P3/Verilog_RTL_sim/mkProc.v index 01f9dd3..8126c37 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkProc.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkProc.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jul 1 17:04:41 BST 2020 +// On Thu Jul 2 02:59:16 BST 2020 // // // Ports: @@ -1927,7 +1927,7 @@ module mkProc(CLK, MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_3, MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_4, MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_5, - MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_7, + MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_6, MUX_llc$dma_memReq_enq_1__SEL_1, MUX_llc_mem_server_rg_cacheline_cache_state$write_1__SEL_2, MUX_llc_mem_server_rg_cacheline_cache_state$write_1__SEL_3, @@ -2005,7 +2005,7 @@ module mkProc(CLK, CASE_x23274_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q24, CASE_x23274_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q25, CASE_x23274_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q29, - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1985, + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1986, dword__h150959, ld_data__h188873, v_wdata__h216097, @@ -2034,9 +2034,9 @@ module mkProc(CLK, wire [519 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__572_THE_ETC___d1841; wire [517 : 0] IF_enqDst_1_0_lat_1_whas__645_THEN_enqDst_1_0__ETC___d1691; wire [515 : 0] IF_enqDst_1_0_lat_0_whas__648_THEN_enqDst_1_0__ETC___d1683, - IF_llc_axi4_adapter_rg_rd_rsp_beat_261_BIT_0_2_ETC___d2303, + IF_llc_axi4_adapter_rg_rd_rsp_beat_263_BIT_0_2_ETC___d2305, SEL_ARR_IF_propDstData_1_0_lat_0_whas__572_THE_ETC___d1836; - wire [383 : 0] IF_llc_mem_server_axi4_slave_xactor_shim_awff__ETC___d2033, + wire [383 : 0] IF_llc_mem_server_axi4_slave_xactor_shim_awff__ETC___d2034, SEL_ARR_IF_propDstData_1_0_lat_0_whas__572_THE_ETC___d1818; wire [129 : 0] IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_ETC___d1111, IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_ETC___d1167; @@ -2056,7 +2056,7 @@ module mkProc(CLK, wire [66 : 0] IF_NOT_core_0_mmioToPlatform_cRq_first__21_BIT_ETC___d546, IF_core_0_mmioToPlatform_cRq_first__21_BITS_21_ETC___d544; wire [65 : 0] mmio_axi4_adapter_f_rsps_to_core_first__298_BI_ETC___d1399; - wire [64 : 0] IF_llc_mem_server_propDstData_0_lat_0_whas__11_ETC___d2122; + wire [64 : 0] IF_llc_mem_server_propDstData_0_lat_0_whas__12_ETC___d2123; wire [63 : 0] IF_enqDst_1_0_lat_0_whas__648_THEN_enqDst_1_0__ETC___d1663, IF_mmioPlatform_fromHostQ_empty_80_OR_mmioPlat_ETC___d1162, IF_mmioPlatform_fromHostQ_empty_80_THEN_0_ELSE_ETC___d1160, @@ -2096,10 +2096,10 @@ module mkProc(CLK, IF_mmioPlatform_fetchingWay_370_THEN_mmioPlatf_ETC___d1396, amo_req_data__h39114, lower_data__h44520, - mmioPlatform_mtime_BITS_31_TO_0__q6, - mmioPlatform_mtime_BITS_63_TO_32__q5, - mmioPlatform_mtimecmp_0_BITS_31_TO_0__q8, - mmioPlatform_mtimecmp_0_BITS_63_TO_32__q7, + mmioPlatform_mtime_BITS_31_TO_0__q8, + mmioPlatform_mtime_BITS_63_TO_32__q7, + mmioPlatform_mtimecmp_0_BITS_31_TO_0__q6, + mmioPlatform_mtimecmp_0_BITS_63_TO_32__q5, upper_data__h44521, v__h44376, v__h44413, @@ -2153,8 +2153,8 @@ module mkProc(CLK, IF_enqDst_1_0_lat_0_whas__648_THEN_enqDst_1_0__ETC___d1653, IF_enqDst_1_0_lat_0_whas__648_THEN_enqDst_1_0__ETC___d1673, IF_enqDst_1_0_lat_0_whas__648_THEN_enqDst_1_0__ETC___d1689, - IF_llc_mem_server_enqDst_0_lat_0_whas__127_THE_ETC___d2132, - IF_llc_mem_server_propDstIdx_0_lat_0_whas__112_ETC___d2115, + IF_llc_mem_server_enqDst_0_lat_0_whas__128_THE_ETC___d2133, + IF_llc_mem_server_propDstIdx_0_lat_0_whas__113_ETC___d2116, IF_mmioPlatform_mtimecmp_0_99_ULE_IF_NOT_mmioP_ETC___d1038, IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_ETC___d819, IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_2_ETC___d1100, @@ -2176,9 +2176,9 @@ module mkProc(CLK, NOT_enqDst_0_rl_452_BIT_73_453_458_AND_SEL_ARR_ETC___d1551, NOT_enqDst_1_0_rl_651_BIT_584_652_657_AND_SEL__ETC___d1847, NOT_enqDst_1_0_rl_651_BIT_584_652_657_AND_SEL__ETC___d1852, - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257, - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2336, - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2339, + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259, + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2338, + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2341, NOT_mmioPlatform_curReq_97_BITS_66_TO_64_98_EQ_ETC___d1201, NOT_mmioPlatform_curReq_97_BITS_66_TO_64_98_EQ_ETC___d1296, NOT_mmioPlatform_curReq_97_BITS_66_TO_64_98_EQ_ETC___d1307, @@ -2193,6 +2193,7 @@ module mkProc(CLK, NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d993, SEL_ARR_IF_propDstIdx_0_lat_0_whas__420_THEN_p_ETC___d1488, SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__557_THEN_ETC___d1725, + _dand1mmio_axi4_adapter_f_reqs_from_core$EN_deq, _theResult____h13492, core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d523, core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d525, @@ -2205,9 +2206,9 @@ module mkProc(CLK, core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d781, core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d788, core_0_mmioToPlatform_cRq_notEmpty__07_AND_cor_ETC___d764, - llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2268, - llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2051, - llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1950, + llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2270, + llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2052, + llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1951, mmioPlatform_amoWaitWriteResp_311_OR_core_0_RD_ETC___d1314, mmioPlatform_cycle_90_ULT_99___d491, mmioPlatform_fetchingWay_370_ULT_mmioPlatform__ETC___d1379, @@ -2232,6 +2233,7 @@ module mkProc(CLK, mmio_axi4_adapter_f_reqs_from_core_i_notEmpty__ETC___d8, mmio_axi4_adapter_read_req_addr_79_BIT_3_80_PL_ETC___d181, mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ax_ETC___d217, + whichHalf___1__h15055, x__h100988, x__h10399, x__h116710, @@ -3003,36 +3005,32 @@ module mkProc(CLK, // rule RL_sendPRq assign CAN_FIRE_RL_sendPRq = + llc$RDY_to_child_toC_first && llc$RDY_to_child_toC_deq && core_0$RDY_dCacheToParent_fromP_enq && - llc$RDY_to_child_toC_deq && - llc$RDY_to_child_toC_first && !llc$to_child_toC_first[587] && !llc$to_child_toC_first[0] ; assign WILL_FIRE_RL_sendPRq = CAN_FIRE_RL_sendPRq ; // rule RL_sendPRs assign CAN_FIRE_RL_sendPRs = + llc$RDY_to_child_toC_first && llc$RDY_to_child_toC_deq && core_0$RDY_dCacheToParent_fromP_enq && - llc$RDY_to_child_toC_deq && - llc$RDY_to_child_toC_first && llc$to_child_toC_first[587] && !llc$to_child_toC_first[520] ; assign WILL_FIRE_RL_sendPRs = CAN_FIRE_RL_sendPRs ; // rule RL_sendPRq_1 assign CAN_FIRE_RL_sendPRq_1 = + llc$RDY_to_child_toC_first && llc$RDY_to_child_toC_deq && core_0$RDY_iCacheToParent_fromP_enq && - llc$RDY_to_child_toC_deq && - llc$RDY_to_child_toC_first && !llc$to_child_toC_first[587] && llc$to_child_toC_first[0] ; assign WILL_FIRE_RL_sendPRq_1 = CAN_FIRE_RL_sendPRq_1 ; // rule RL_sendPRs_1 assign CAN_FIRE_RL_sendPRs_1 = + llc$RDY_to_child_toC_first && llc$RDY_to_child_toC_deq && core_0$RDY_iCacheToParent_fromP_enq && - llc$RDY_to_child_toC_deq && - llc$RDY_to_child_toC_first && llc$to_child_toC_first[587] && llc$to_child_toC_first[520] ; assign WILL_FIRE_RL_sendPRs_1 = CAN_FIRE_RL_sendPRs_1 ; @@ -3372,7 +3370,7 @@ module mkProc(CLK, // rule RL_llc_mem_server_rl_cacheline_cache_writeback_finish assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish = - llc$RDY_dma_respSt_deq && llc$RDY_dma_respSt_first && + llc$RDY_dma_respSt_first && llc$RDY_dma_respSt_deq && !llc$dma_respSt_first[4] && llc_mem_server_rg_cacheline_cache_state == 3'd1 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish = @@ -3380,7 +3378,7 @@ module mkProc(CLK, // rule RL_llc_mem_server_rl_cacheline_cache_reload_finish assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish = - llc$RDY_dma_respLd_deq && llc$RDY_dma_respLd_first && + llc$RDY_dma_respLd_first && llc$RDY_dma_respLd_deq && !llc$dma_respLd_first[4] && llc_mem_server_rg_cacheline_cache_state == 3'd2 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish = @@ -3401,21 +3399,21 @@ module mkProc(CLK, // rule RL_llc_mem_server_doEnq assign CAN_FIRE_RL_llc_mem_server_doEnq = llc_mem_server_tlbQ$FULL_N && - IF_llc_mem_server_enqDst_0_lat_0_whas__127_THE_ETC___d2132 ; + IF_llc_mem_server_enqDst_0_lat_0_whas__128_THE_ETC___d2133 ; assign WILL_FIRE_RL_llc_mem_server_doEnq = CAN_FIRE_RL_llc_mem_server_doEnq ; // rule RL_llc_mem_server_sendLdRespToTlb assign CAN_FIRE_RL_llc_mem_server_sendLdRespToTlb = - core_0$RDY_tlbToMem_respLd_enq && llc$RDY_dma_respLd_deq && - llc$RDY_dma_respLd_first && + llc$RDY_dma_respLd_first && llc$RDY_dma_respLd_deq && + core_0$RDY_tlbToMem_respLd_enq && llc$dma_respLd_first[4] ; assign WILL_FIRE_RL_llc_mem_server_sendLdRespToTlb = CAN_FIRE_RL_llc_mem_server_sendLdRespToTlb ; // rule RL_llc_mem_server_sendStRespToTlb assign CAN_FIRE_RL_llc_mem_server_sendStRespToTlb = - llc$RDY_dma_respSt_deq && llc$RDY_dma_respSt_first && + llc$RDY_dma_respSt_first && llc$RDY_dma_respSt_deq && llc$dma_respSt_first[4] ; assign WILL_FIRE_RL_llc_mem_server_sendStRespToTlb = CAN_FIRE_RL_llc_mem_server_sendStRespToTlb ; @@ -3469,7 +3467,7 @@ module mkProc(CLK, !llc_mem_server_axi4_slave_xactor_shim_rff_rv[73] && (llc_mem_server_rg_cacheline_cache_state == 3'd3 || llc_mem_server_rg_cacheline_cache_state == 3'd4) && - llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2051 ; + llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2052 ; assign WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req = CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req ; @@ -3481,7 +3479,7 @@ module mkProc(CLK, !llc_mem_server_axi4_slave_xactor_shim_bff_rv[7] && (llc_mem_server_rg_cacheline_cache_state == 3'd3 || llc_mem_server_rg_cacheline_cache_state == 3'd4) && - llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1950 ; + llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1951 ; assign WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req = CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req && !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged ; @@ -3500,7 +3498,7 @@ module mkProc(CLK, !llc_mem_server_axi4_slave_xactor_clearing && llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[98] && llc_mem_server_rg_cacheline_cache_state == 3'd4 && - !llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1950 ; + !llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1951 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss && !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged ; @@ -3511,7 +3509,7 @@ module mkProc(CLK, !llc_mem_server_axi4_slave_xactor_clearing && llc_mem_server_axi4_slave_xactor_shim_arff_rv$port1__read[98] && llc_mem_server_rg_cacheline_cache_state == 3'd4 && - !llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2051 ; + !llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2052 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss && !WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req && @@ -3524,7 +3522,7 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[98] && llc$RDY_dma_memReq_enq && llc_mem_server_rg_cacheline_cache_state == 3'd3 && - !llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1950 ; + !llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1951 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ; @@ -3534,7 +3532,7 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_shim_arff_rv$port1__read[98] && llc$RDY_dma_memReq_enq && llc_mem_server_rg_cacheline_cache_state == 3'd3 && - !llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2051 ; + !llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2052 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld && !WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req && @@ -3625,8 +3623,8 @@ module mkProc(CLK, // rule RL_llc_axi4_adapter_rl_handle_read_req assign CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req = !llc_axi4_adapter_master_xactor_clearing && - llc$RDY_to_mem_toM_deq && llc$RDY_to_mem_toM_first && + llc$RDY_to_mem_toM_deq && !llc_axi4_adapter_master_xactor_shim_arff_rv[98] && llc_axi4_adapter_f_pending_reads$FULL_N && !llc$to_mem_toM_first[644] && @@ -3733,7 +3731,7 @@ module mkProc(CLK, // rule RL_llc_axi4_adapter_rl_handle_read_rsps assign CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps = !llc_axi4_adapter_master_xactor_clearing && - llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2268 ; + llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2270 ; assign WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps ; @@ -3774,7 +3772,7 @@ module mkProc(CLK, WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && (!mmioPlatform_fetchingWay_370_ULT_mmioPlatform__ETC___d1379 || !mmio_axi4_adapter_f_rsps_to_core$D_OUT[129]) ; - assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_7 = + assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_6 = WILL_FIRE_RL_mmioPlatform_waitMTimeDone || WILL_FIRE_RL_mmioPlatform_waitMTimeCmpDone ; assign MUX_llc$dma_memReq_enq_1__SEL_1 = @@ -3836,11 +3834,11 @@ module mkProc(CLK, WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_master_shim_rff$D_OUT[1] ; assign MUX_core_0$dCacheToParent_fromP_enq_1__VAL_1 = - { 1'd0, llc$to_child_toC_first[586:1] } ; - assign MUX_core_0$dCacheToParent_fromP_enq_1__VAL_2 = { 1'd1, llc$to_child_toC_first[586:521], llc$to_child_toC_first[519:0] } ; + assign MUX_core_0$dCacheToParent_fromP_enq_1__VAL_2 = + { 1'd0, llc$to_child_toC_first[586:1] } ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_2 = { 1'd0, IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_ETC___d844, @@ -3883,9 +3881,9 @@ module mkProc(CLK, { 65'h0AAAAAAAAAAAAAAAA, mmio_axi4_adapter_f_rsps_to_core_first__298_BI_ETC___d1399 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6 = - { 1'd1, mmio_axi4_adapter_f_rsps_to_core$D_OUT } ; - assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_7 = { 2'd3, mmioPlatform_amoResp } ; + assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_7 = + { 1'd1, mmio_axi4_adapter_f_rsps_to_core$D_OUT } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_8 = { 3'd6, mmioPlatform_waitLowerMSIPCRs ? @@ -3927,7 +3925,7 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:33] != 2'd0 && llc_mem_server_rg_cacheline_cache_data[512], - IF_llc_mem_server_axi4_slave_xactor_shim_awff__ETC___d2033, + IF_llc_mem_server_axi4_slave_xactor_shim_awff__ETC___d2034, (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32] == 3'd1) ? data__h141232 : @@ -4130,10 +4128,10 @@ module mkProc(CLK, !llc_mem_server_axi4_slave_xactor_shim_arff_rv[98] ; assign llc_mem_server_propDstIdx_0_lat_1$whas = !llc_mem_server_enqDst_0_rl[65] && - IF_llc_mem_server_propDstIdx_0_lat_0_whas__112_ETC___d2115 ; + IF_llc_mem_server_propDstIdx_0_lat_0_whas__113_ETC___d2116 ; assign llc_mem_server_enqDst_0_lat_0$wget = { 1'd1, - IF_llc_mem_server_propDstData_0_lat_0_whas__11_ETC___d2122 } ; + IF_llc_mem_server_propDstData_0_lat_0_whas__12_ETC___d2123 } ; assign llc_axi4_adapter_master_xactor_master_bSynth_snk_putWire$wget = { master0_bid, master0_bresp } ; assign llc_axi4_adapter_master_xactor_master_bSynth_snk_putWire$whas = @@ -4348,7 +4346,7 @@ module mkProc(CLK, EN_hart0_put_other_req_put ? hart0_put_other_req_put : set_verbosity_verbosity ; - assign cfg_verbosity$EN = EN_hart0_put_other_req_put || EN_set_verbosity ; + assign cfg_verbosity$EN = EN_set_verbosity || EN_hart0_put_other_req_put ; // register enqDst_0_rl assign enqDst_0_rl$D_IN = @@ -4409,7 +4407,7 @@ module mkProc(CLK, // register llc_axi4_adapter_rg_cline assign llc_axi4_adapter_rg_cline$D_IN = - IF_llc_axi4_adapter_rg_rd_rsp_beat_261_BIT_0_2_ETC___d2303 ; + IF_llc_axi4_adapter_rg_rd_rsp_beat_263_BIT_0_2_ETC___d2305 ; assign llc_axi4_adapter_rg_cline$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps ; @@ -4458,7 +4456,7 @@ module mkProc(CLK, // register llc_mem_server_enqDst_0_rl assign llc_mem_server_enqDst_0_rl$D_IN = { !CAN_FIRE_RL_llc_mem_server_doEnq && - IF_llc_mem_server_enqDst_0_lat_0_whas__127_THE_ETC___d2132, + IF_llc_mem_server_enqDst_0_lat_0_whas__128_THE_ETC___d2133, CAN_FIRE_RL_llc_mem_server_doEnq ? 65'h0AAAAAAAAAAAAAAAA : (llc_mem_server_propDstIdx_0_lat_1$whas ? @@ -4468,13 +4466,13 @@ module mkProc(CLK, // register llc_mem_server_propDstData_0_rl assign llc_mem_server_propDstData_0_rl$D_IN = - IF_llc_mem_server_propDstData_0_lat_0_whas__11_ETC___d2122 ; + IF_llc_mem_server_propDstData_0_lat_0_whas__12_ETC___d2123 ; assign llc_mem_server_propDstData_0_rl$EN = 1'd1 ; // register llc_mem_server_propDstIdx_0_rl assign llc_mem_server_propDstIdx_0_rl$D_IN = !llc_mem_server_propDstIdx_0_lat_1$whas && - IF_llc_mem_server_propDstIdx_0_lat_0_whas__112_ETC___d2115 ; + IF_llc_mem_server_propDstIdx_0_lat_0_whas__113_ETC___d2116 ; assign llc_mem_server_propDstIdx_0_rl$EN = 1'd1 ; // register llc_mem_server_rg_cacheline_cache_addr @@ -4861,7 +4859,7 @@ module mkProc(CLK, // register mmio_axi4_adapter_rg_wr_req_beat assign mmio_axi4_adapter_rg_wr_req_beat$D_IN = - mmio_axi4_adapter_f_reqs_from_core$D_OUT[136:129] != 8'd0 && + !whichHalf___1__h15055 && mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] != 8'd0 && !mmio_axi4_adapter_rg_wr_req_beat && x__h17610 ; @@ -4957,7 +4955,7 @@ module mkProc(CLK, assign core_0$coreReq_start_startpc = start_startpc ; assign core_0$coreReq_start_toHostAddr = start_tohostAddr ; assign core_0$dCacheToParent_fromP_enq_x = - WILL_FIRE_RL_sendPRq ? + WILL_FIRE_RL_sendPRs ? MUX_core_0$dCacheToParent_fromP_enq_1__VAL_1 : MUX_core_0$dCacheToParent_fromP_enq_1__VAL_2 ; assign core_0$hart0_csr_mem_server_request_put = @@ -4969,7 +4967,7 @@ module mkProc(CLK, assign core_0$hart0_run_halt_server_request_put = hart0_run_halt_server_request_put ; assign core_0$iCacheToParent_fromP_enq_x = - WILL_FIRE_RL_sendPRq_1 ? + WILL_FIRE_RL_sendPRs_1 ? MUX_core_0$dCacheToParent_fromP_enq_1__VAL_1 : MUX_core_0$dCacheToParent_fromP_enq_1__VAL_2 ; always@(MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_1 or @@ -5006,9 +5004,9 @@ module mkProc(CLK, MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_4 or MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_5 or MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_5 or - WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp or + MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_6 or MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6 or - MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_7 or + WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp or MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_7 or WILL_FIRE_RL_mmioPlatform_waitMSIPDone or MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_8 or @@ -5033,10 +5031,10 @@ module mkProc(CLK, MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_5: core_0$mmioToPlatform_pRs_enq_x = MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_5; - WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp: + MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_6: core_0$mmioToPlatform_pRs_enq_x = MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6; - MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_7: + WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp: core_0$mmioToPlatform_pRs_enq_x = MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_7; WILL_FIRE_RL_mmioPlatform_waitMSIPDone: @@ -5065,11 +5063,11 @@ module mkProc(CLK, assign core_0$EN_dCacheToParent_rsToP_deq = CAN_FIRE_RL_srcPropose_2 ; assign core_0$EN_dCacheToParent_rqToP_deq = CAN_FIRE_RL_srcPropose ; assign core_0$EN_dCacheToParent_fromP_enq = - WILL_FIRE_RL_sendPRq || WILL_FIRE_RL_sendPRs ; + WILL_FIRE_RL_sendPRs || WILL_FIRE_RL_sendPRq ; assign core_0$EN_iCacheToParent_rsToP_deq = CAN_FIRE_RL_srcPropose_3 ; assign core_0$EN_iCacheToParent_rqToP_deq = CAN_FIRE_RL_srcPropose_1 ; assign core_0$EN_iCacheToParent_fromP_enq = - WILL_FIRE_RL_sendPRq_1 || WILL_FIRE_RL_sendPRs_1 ; + WILL_FIRE_RL_sendPRs_1 || WILL_FIRE_RL_sendPRq_1 ; assign core_0$EN_tlbToMem_memReq_deq = CAN_FIRE_RL_llc_mem_server_srcPropose ; assign core_0$EN_tlbToMem_respLd_enq = @@ -5088,9 +5086,9 @@ module mkProc(CLK, WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && (!mmioPlatform_fetchingWay_370_ULT_mmioPlatform__ETC___d1379 || !mmio_axi4_adapter_f_rsps_to_core$D_OUT[129]) || - WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp || WILL_FIRE_RL_mmioPlatform_waitMTimeDone || WILL_FIRE_RL_mmioPlatform_waitMTimeCmpDone || + WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp || WILL_FIRE_RL_mmioPlatform_waitMSIPDone || WILL_FIRE_RL_mmioPlatform_processToHost || WILL_FIRE_RL_mmioPlatform_processFromHost ; @@ -5192,7 +5190,7 @@ module mkProc(CLK, IF_enqDst_1_0_lat_0_whas__648_THEN_enqDst_1_0__ETC___d1683, IF_enqDst_1_0_lat_0_whas__648_THEN_enqDst_1_0__ETC___d1689 } ; assign llc$to_mem_rsFromM_enq_x = - { IF_llc_axi4_adapter_rg_rd_rsp_beat_261_BIT_0_2_ETC___d2303, + { IF_llc_axi4_adapter_rg_rd_rsp_beat_263_BIT_0_2_ETC___d2305, llc_axi4_adapter_f_pending_reads$D_OUT[4:0] } ; assign llc$EN_to_child_rsFromC_enq = CAN_FIRE_RL_doEnq_1 ; assign llc$EN_to_child_rqFromC_enq = CAN_FIRE_RL_doEnq ; @@ -5285,11 +5283,7 @@ module mkProc(CLK, WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req || WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req ; assign mmio_axi4_adapter_f_reqs_from_core$DEQ = - WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && - (mmio_axi4_adapter_f_reqs_from_core$D_OUT[136:129] == 8'd0 || - mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] == 8'd0 || - mmio_axi4_adapter_rg_wr_req_beat || - !mmio_axi4_adapter_soc_map$m_is_IO_addr) || + _dand1mmio_axi4_adapter_f_reqs_from_core$EN_deq || WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St || WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req ; assign mmio_axi4_adapter_f_reqs_from_core$CLR = 1'b0 ; @@ -5372,7 +5366,7 @@ module mkProc(CLK, assign mmio_axi4_adapter_master_shim_wff$D_IN = { wflit_wdata__h17678, wflit_wstrb__h17679, - mmio_axi4_adapter_f_reqs_from_core$D_OUT[136:129] == 8'd0 || + whichHalf___1__h15055 || mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] == 8'd0 || mmio_axi4_adapter_rg_wr_req_beat, 1'd0 } ; @@ -5613,14 +5607,14 @@ module mkProc(CLK, 2'b10 : IF_enqDst_1_0_lat_0_whas__648_THEN_enqDst_1_0__ETC___d1668, IF_enqDst_1_0_lat_1_whas__645_THEN_enqDst_1_0__ETC___d1691 } ; - assign IF_llc_axi4_adapter_rg_rd_rsp_beat_261_BIT_0_2_ETC___d2303 = + assign IF_llc_axi4_adapter_rg_rd_rsp_beat_263_BIT_0_2_ETC___d2305 = { llc_axi4_adapter_rg_rd_rsp_beat[0] ? llc_axi4_adapter_rg_cline[515:512] : { llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[0], llc_axi4_adapter_rg_cline[515:513] }, llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[67:4], llc_axi4_adapter_rg_cline[511:64] } ; - assign IF_llc_mem_server_axi4_slave_xactor_shim_awff__ETC___d2033 = + assign IF_llc_mem_server_axi4_slave_xactor_shim_awff__ETC___d2034 = { (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32] == 3'd7) ? data__h141232 : @@ -5645,15 +5639,15 @@ module mkProc(CLK, 3'd2) ? data__h141232 : llc_mem_server_rg_cacheline_cache_data[191:128] } ; - assign IF_llc_mem_server_enqDst_0_lat_0_whas__127_THE_ETC___d2132 = + assign IF_llc_mem_server_enqDst_0_lat_0_whas__128_THE_ETC___d2133 = llc_mem_server_propDstIdx_0_lat_1$whas ? llc_mem_server_enqDst_0_lat_0$wget[65] : llc_mem_server_enqDst_0_rl[65] ; - assign IF_llc_mem_server_propDstData_0_lat_0_whas__11_ETC___d2122 = + assign IF_llc_mem_server_propDstData_0_lat_0_whas__12_ETC___d2123 = CAN_FIRE_RL_llc_mem_server_srcPropose ? core_0$tlbToMem_memReq_first : llc_mem_server_propDstData_0_rl ; - assign IF_llc_mem_server_propDstIdx_0_lat_0_whas__112_ETC___d2115 = + assign IF_llc_mem_server_propDstIdx_0_lat_0_whas__113_ETC___d2116 = CAN_FIRE_RL_llc_mem_server_srcPropose || llc_mem_server_propDstIdx_0_rl ; assign IF_mmioPlatform_fetchingWay_370_THEN_mmioPlatf_ETC___d1396 = @@ -5698,16 +5692,16 @@ module mkProc(CLK, mmioPlatform_reqData[63:0]) ; assign IF_mmioPlatform_reqBE_05_BIT_4_06_THEN_SEXT_mm_ETC___d1054 = mmioPlatform_reqBE[4] ? - { {32{mmioPlatform_mtime_BITS_63_TO_32__q5[31]}}, - mmioPlatform_mtime_BITS_63_TO_32__q5 } : - { {32{mmioPlatform_mtime_BITS_31_TO_0__q6[31]}}, - mmioPlatform_mtime_BITS_31_TO_0__q6 } ; + { {32{mmioPlatform_mtime_BITS_63_TO_32__q7[31]}}, + mmioPlatform_mtime_BITS_63_TO_32__q7 } : + { {32{mmioPlatform_mtime_BITS_31_TO_0__q8[31]}}, + mmioPlatform_mtime_BITS_31_TO_0__q8 } ; assign IF_mmioPlatform_reqBE_05_BIT_4_06_THEN_SEXT_mm_ETC___d981 = mmioPlatform_reqBE[4] ? - { {32{mmioPlatform_mtimecmp_0_BITS_63_TO_32__q7[31]}}, - mmioPlatform_mtimecmp_0_BITS_63_TO_32__q7 } : - { {32{mmioPlatform_mtimecmp_0_BITS_31_TO_0__q8[31]}}, - mmioPlatform_mtimecmp_0_BITS_31_TO_0__q8 } ; + { {32{mmioPlatform_mtimecmp_0_BITS_63_TO_32__q5[31]}}, + mmioPlatform_mtimecmp_0_BITS_63_TO_32__q5 } : + { {32{mmioPlatform_mtimecmp_0_BITS_31_TO_0__q6[31]}}, + mmioPlatform_mtimecmp_0_BITS_31_TO_0__q6 } ; assign IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_ETC___d1111 = (mmioPlatform_reqFunc[5:4] == 2'd0) ? 130'h2AAAAAAAAAAAAAAA955555554AAAAAAAA : @@ -5784,7 +5778,7 @@ module mkProc(CLK, assign IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d206 = mmio_axi4_adapter_soc_map$m_is_IO_addr ? mmio_axi4_adapter_master_shim_wff$FULL_N && - (mmio_axi4_adapter_f_reqs_from_core$D_OUT[136:129] != 8'd0 && + (!whichHalf___1__h15055 && mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] != 8'd0 && mmio_axi4_adapter_rg_wr_req_beat || mmio_axi4_adapter_master_shim_awff$FULL_N) : @@ -5849,15 +5843,15 @@ module mkProc(CLK, x__h123274 && !CAN_FIRE_RL_srcPropose_3 && !propDstIdx_1_1_rl ; - assign NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257 = + assign NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259 = llc_axi4_adapter_cfg_verbosity > 4'd1 ; - assign NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2336 = - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257 && + assign NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2338 = + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259 && (llc_axi4_adapter_rg_rd_rsp_beat[0] ? !llc_axi4_adapter_rg_cline[515] : !llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[0]) ; - assign NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2339 = - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257 && + assign NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2341 = + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259 && (llc_axi4_adapter_rg_rd_rsp_beat[0] ? llc_axi4_adapter_rg_cline[515] : llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[0]) ; @@ -6011,12 +6005,18 @@ module mkProc(CLK, (IF_propDstIdx_1_0_lat_0_whas__557_THEN_NOT_pro_ETC___d1723 ? IF_propDstIdx_1_1_lat_0_whas__564_THEN_propDst_ETC___d1567 : IF_propDstIdx_1_0_lat_0_whas__557_THEN_propDst_ETC___d1560) ; + assign _dand1mmio_axi4_adapter_f_reqs_from_core$EN_deq = + WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + (whichHalf___1__h15055 || + mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] == 8'd0 || + mmio_axi4_adapter_rg_wr_req_beat || + !mmio_axi4_adapter_soc_map$m_is_IO_addr) ; assign _theResult_____1_awsize_val__h17116 = (x__h15143 + y__h15144 <= 5'd4) ? 3'b010 : 3'b011 ; assign _theResult____h13492 = - (mmio_axi4_adapter_f_reqs_from_core$D_OUT[136:129] == 8'd0 || + (whichHalf___1__h15055 || mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] == 8'd0) ? - mmio_axi4_adapter_f_reqs_from_core$D_OUT[136:129] == 8'd0 : + whichHalf___1__h15055 : mmio_axi4_adapter_rg_wr_req_beat ; assign addr1__h90765 = { mmioPlatform_curReq[63:3], 3'b0 } ; assign amo_req_data__h39114 = @@ -6091,28 +6091,28 @@ module mkProc(CLK, assign data__h141232 = { llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[9] ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[73:66] : - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1985[63:56], + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1986[63:56], llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[8] ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[65:58] : - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1985[55:48], + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1986[55:48], llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[7] ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[57:50] : - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1985[47:40], + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1986[47:40], llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[6] ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[49:42] : - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1985[39:32], + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1986[39:32], llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[5] ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[41:34] : - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1985[31:24], + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1986[31:24], llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[4] ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[33:26] : - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1985[23:16], + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1986[23:16], llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[3] ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[25:18] : - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1985[15:8], + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1986[15:8], llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[2] ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[17:10] : - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1985[7:0] } ; + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1986[7:0] } ; assign failed_testnum__h224472 = { 1'd0, mmioPlatform_toHostQ_data_0[63:1] } ; assign line_addr__h140665 = @@ -6126,16 +6126,16 @@ module mkProc(CLK, llc_axi4_adapter_master_xactor_shim_arff_rv$port1__read[97:0] ; assign llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q32 = llc_axi4_adapter_master_xactor_shim_awff_rv$port1__read[97:0] ; - assign llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2268 = + assign llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2270 = llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[73] && (llc_axi4_adapter_rg_rd_rsp_beat != 3'd7 || llc$RDY_to_mem_rsFromM_enq && llc_axi4_adapter_f_pending_reads$EMPTY_N) ; assign llc_axi4_adapter_master_xactor_shim_wff_rvpor_ETC__q33 = llc_axi4_adapter_master_xactor_shim_wff_rv$port1__read[73:0] ; - assign llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2051 = + assign llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2052 = line_addr__h150776 == llc_mem_server_rg_cacheline_cache_addr ; - assign llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1950 = + assign llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1951 = line_addr__h140665 == llc_mem_server_rg_cacheline_cache_addr ; assign llc_mem_server_axi4_slave_xactor_shim_bff_rvp_ETC__q30 = llc_mem_server_axi4_slave_xactor_shim_bff_rv$port1__read[6:0] ; @@ -6144,7 +6144,7 @@ module mkProc(CLK, assign lower_data__h44520 = mmioPlatform_waitLowerMSIPCRs ? v__h44413 : 32'd0 ; assign mem_req_rd_addr_arlen__h5411 = - (mmio_axi4_adapter_f_reqs_from_core$D_OUT[136:129] != 8'd0 && + (!whichHalf___1__h15055 && mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] != 8'd0) ? 8'd1 : 8'd0 ; @@ -6156,16 +6156,16 @@ module mkProc(CLK, assign mmioPlatform_cycle_90_ULT_99___d491 = mmioPlatform_cycle < 7'd99 ; assign mmioPlatform_fetchingWay_370_ULT_mmioPlatform__ETC___d1379 = mmioPlatform_fetchingWay < mmioPlatform_reqFunc[0] ; - assign mmioPlatform_mtime_BITS_31_TO_0__q6 = mmioPlatform_mtime[31:0] ; - assign mmioPlatform_mtime_BITS_63_TO_32__q5 = mmioPlatform_mtime[63:32] ; + assign mmioPlatform_mtime_BITS_31_TO_0__q8 = mmioPlatform_mtime[31:0] ; + assign mmioPlatform_mtime_BITS_63_TO_32__q7 = mmioPlatform_mtime[63:32] ; assign mmioPlatform_mtime__h59831 = mmioPlatform_mtime ; assign mmioPlatform_mtimecmp_0_99_ULE_IF_NOT_mmioPlat_ETC___d1029 = mmioPlatform_mtimecmp_0 <= newData__h53320 ; assign mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500 = mmioPlatform_mtimecmp_0 <= mmioPlatform_mtime ; - assign mmioPlatform_mtimecmp_0_BITS_31_TO_0__q8 = + assign mmioPlatform_mtimecmp_0_BITS_31_TO_0__q6 = mmioPlatform_mtimecmp_0[31:0] ; - assign mmioPlatform_mtimecmp_0_BITS_63_TO_32__q7 = + assign mmioPlatform_mtimecmp_0_BITS_63_TO_32__q5 = mmioPlatform_mtimecmp_0[63:32] ; assign mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d584 = (mmioPlatform_mtip_0 || @@ -6289,12 +6289,12 @@ module mkProc(CLK, (IF_NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03__ETC___d957 || !mmioPlatform_mtip_0) ; assign mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253 = - (mmio_axi4_adapter_f_reqs_from_core$D_OUT[136:129] == 8'd0 || + (whichHalf___1__h15055 || mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] == 8'd0 || !mmio_axi4_adapter_rg_wr_req_beat) && mmio_axi4_adapter_cfg_verbosity != 4'd0 ; assign mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d259 = - (mmio_axi4_adapter_f_reqs_from_core$D_OUT[136:129] == 8'd0 || + (whichHalf___1__h15055 || mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] == 8'd0 || !mmio_axi4_adapter_rg_wr_req_beat) && mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15 ; @@ -6324,7 +6324,7 @@ module mkProc(CLK, mmio_axi4_adapter_master_shim_rff$D_OUT[67:4] } } ; assign mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ax_ETC___d217 = mmio_axi4_adapter_soc_map$m_is_IO_addr && - (mmio_axi4_adapter_f_reqs_from_core$D_OUT[136:129] == 8'd0 || + (whichHalf___1__h15055 || mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] == 8'd0 || !mmio_axi4_adapter_rg_wr_req_beat) ; assign newData__h45219 = @@ -6345,6 +6345,8 @@ module mkProc(CLK, assign v__h44413 = { 31'd0, core_0$mmioToPlatform_cRs_first } ; assign v_awaddr__h215686 = { llc$to_mem_toM_first[643:586], 6'h0 } ; assign value__h61538 = mmioPlatform_mtimecmp_0 ; + assign whichHalf___1__h15055 = + mmio_axi4_adapter_f_reqs_from_core$D_OUT[136:129] == 8'd0 ; assign x__h100988 = SEL_ARR_IF_propDstIdx_0_lat_0_whas__420_THEN_p_ETC___d1484 ? srcRR_0 : @@ -7075,28 +7077,28 @@ module mkProc(CLK, begin case (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32]) 3'd0: - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1985 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1986 = llc_mem_server_rg_cacheline_cache_data[63:0]; 3'd1: - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1985 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1986 = llc_mem_server_rg_cacheline_cache_data[127:64]; 3'd2: - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1985 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1986 = llc_mem_server_rg_cacheline_cache_data[191:128]; 3'd3: - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1985 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1986 = llc_mem_server_rg_cacheline_cache_data[255:192]; 3'd4: - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1985 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1986 = llc_mem_server_rg_cacheline_cache_data[319:256]; 3'd5: - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1985 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1986 = llc_mem_server_rg_cacheline_cache_data[383:320]; 3'd6: - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1985 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1986 = llc_mem_server_rg_cacheline_cache_data[447:384]; 3'd7: - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1985 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1986 = llc_mem_server_rg_cacheline_cache_data[511:448]; endcase end @@ -8376,7 +8378,7 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_f_reqs_from_core$D_OUT[136:129] != 8'd0 && + !whichHalf___1__h15055 && mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] != 8'd0 && !mmio_axi4_adapter_rg_wr_req_beat) $write("False"); @@ -8384,7 +8386,7 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0 && - (mmio_axi4_adapter_f_reqs_from_core$D_OUT[136:129] == 8'd0 || + (whichHalf___1__h15055 || mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] == 8'd0 || mmio_axi4_adapter_rg_wr_req_beat)) $write("True"); @@ -8403,10 +8405,10 @@ module mkProc(CLK, mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) $write("first: %d, last: %d, whichHalf: %d", - mmio_axi4_adapter_f_reqs_from_core$D_OUT[136:129] == 8'd0 || + whichHalf___1__h15055 || mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] == 8'd0 || !mmio_axi4_adapter_rg_wr_req_beat, - mmio_axi4_adapter_f_reqs_from_core$D_OUT[136:129] == 8'd0 || + whichHalf___1__h15055 || mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] == 8'd0 || mmio_axi4_adapter_rg_wr_req_beat, _theResult____h13492, @@ -11883,7 +11885,7 @@ module mkProc(CLK, $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (!llc_mem_server_enqDst_0_rl[65] && - IF_llc_mem_server_propDstIdx_0_lat_0_whas__112_ETC___d2115 && + IF_llc_mem_server_propDstIdx_0_lat_0_whas__113_ETC___d2116 && !CAN_FIRE_RL_llc_mem_server_srcPropose && !llc_mem_server_propDstIdx_0_rl) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); @@ -13459,103 +13461,103 @@ module mkProc(CLK, $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257) + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257) + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) $write("AXI4_ARFlit { ", "arid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257) + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) $write("'h%h", 5'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257) + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) $write(", ", "araddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257) + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) $write("'h%h", line_addr__h194193); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257) + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) $write(", ", "arlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257) + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) $write("'h%h", 8'd7); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257) + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) $write(", ", "arsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257) + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) $write("AXI4_Size { ", "val: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257) + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) $write("'h%h", 3'b011, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257) + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) $write(", ", "arburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257) + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) $write("INCR"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257) + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) $write(", ", "arlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257) + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) $write("NORMAL"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257) + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) $write(", ", "arcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257) + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) $write("'h%h", 4'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257) + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) $write(", ", "arprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257) + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) $write("'h%h", 3'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257) + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) $write(", ", "arqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257) + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257) + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) $write(", ", "arregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257) + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257) + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) $write(", ", "aruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257) + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257) + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_awSynth_src_warnDoDrop) @@ -13636,7 +13638,7 @@ module mkProc(CLK, $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257) + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) begin v__h194646 = $stime; #0; @@ -13644,54 +13646,54 @@ module mkProc(CLK, v__h194640 = v__h194646 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257) + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsps: beat %0d ", v__h194640, llc_axi4_adapter_rg_rd_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257) + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257) + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) $write("AXI4_RFlit { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257) + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) $write("'h%h", llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[72:68]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257) + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257) + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) $write("'h%h", llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[67:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257) + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257 && + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259 && llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] == 2'd0) $write("OKAY"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257 && + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259 && llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] == 2'd1) $write("EXOKAY"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257 && + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259 && llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] == 2'd2) $write("SLVERR"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257 && + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259 && llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != 2'd0 && llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != @@ -13700,31 +13702,31 @@ module mkProc(CLK, $write("DECERR"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257) + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257 && + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259 && llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257 && + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259 && !llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257) + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257) + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) $write("'h%h", llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[0], " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257) + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && @@ -13818,27 +13820,27 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257) + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) $write(" Response to LLC: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257) + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) $write("MemRsMsg { ", "data: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257) + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) $write("CLine { ", "tag: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257) + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257) + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) $write(", ", "data: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257) + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257) + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257) + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257) + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257) + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257) + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257) + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257) + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257) + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257) + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) $write(" >"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257) + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) $write(" }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257) + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) $write(", ", "child: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257) + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257) + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) $write(", ", "id: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257) + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) $write("LdMemRqId { ", "refill: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257 && + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259 && llc_axi4_adapter_f_pending_reads$D_OUT[4]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257 && + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259 && !llc_axi4_adapter_f_pending_reads$D_OUT[4]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257) + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) $write(", ", "mshrIdx: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257) + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) $write("'h%h", llc_axi4_adapter_f_pending_reads$D_OUT[3:0], " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257) + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) $write(" }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__242_U_ETC___d2257) + NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) $write("\n"); end // synopsys translate_on diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkRFileSynth.v b/src_SSITH_P3/Verilog_RTL_sim/mkRFileSynth.v index af89488..b9d0a8c 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkRFileSynth.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkRFileSynth.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:36:04 BST 2020 +// On Thu Jul 2 02:50:46 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkRas.v b/src_SSITH_P3/Verilog_RTL_sim/mkRas.v index 6cb752e..95d5eb3 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkRas.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkRas.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:37:30 BST 2020 +// On Thu Jul 2 02:51:53 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkRegRenamingTable.v b/src_SSITH_P3/Verilog_RTL_sim/mkRegRenamingTable.v index c2aca51..8a0b586 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkRegRenamingTable.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkRegRenamingTable.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:32:54 BST 2020 +// On Thu Jul 2 02:48:18 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkReorderBufferSynth.v b/src_SSITH_P3/Verilog_RTL_sim/mkReorderBufferSynth.v index dc61ff6..a389c0a 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkReorderBufferSynth.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkReorderBufferSynth.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:36:59 BST 2020 +// On Thu Jul 2 02:51:29 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkReservationStationAlu.v b/src_SSITH_P3/Verilog_RTL_sim/mkReservationStationAlu.v index c294db4..e8bfde3 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkReservationStationAlu.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkReservationStationAlu.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:42:28 BST 2020 +// On Thu Jul 2 02:57:22 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkReservationStationFpuMulDiv.v b/src_SSITH_P3/Verilog_RTL_sim/mkReservationStationFpuMulDiv.v index ab8015a..356a858 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkReservationStationFpuMulDiv.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkReservationStationFpuMulDiv.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:37:17 BST 2020 +// On Thu Jul 2 02:51:43 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkReservationStationMem.v b/src_SSITH_P3/Verilog_RTL_sim/mkReservationStationMem.v index 15070ef..2fa0e20 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkReservationStationMem.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkReservationStationMem.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:37:11 BST 2020 +// On Thu Jul 2 02:51:38 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkRobRowSynth.v b/src_SSITH_P3/Verilog_RTL_sim/mkRobRowSynth.v index a0f6061..c0925ef 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkRobRowSynth.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkRobRowSynth.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:36:16 BST 2020 +// On Thu Jul 2 02:50:56 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkScoreboardAggr.v b/src_SSITH_P3/Verilog_RTL_sim/mkScoreboardAggr.v index 3945e8a..18812ea 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkScoreboardAggr.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkScoreboardAggr.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jul 1 17:02:38 BST 2020 +// On Thu Jul 2 02:53:17 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkScoreboardCons.v b/src_SSITH_P3/Verilog_RTL_sim/mkScoreboardCons.v index 72c2a70..59b7d39 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkScoreboardCons.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkScoreboardCons.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jul 1 17:02:31 BST 2020 +// On Thu Jul 2 02:53:10 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkSimpleRespQ.v b/src_SSITH_P3/Verilog_RTL_sim/mkSimpleRespQ.v index 178c144..7b24c41 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkSimpleRespQ.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkSimpleRespQ.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:41:44 BST 2020 +// On Thu Jul 2 02:55:45 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkSoC_Map.v b/src_SSITH_P3/Verilog_RTL_sim/mkSoC_Map.v index 583a4c3..66bac96 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkSoC_Map.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkSoC_Map.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:31:05 BST 2020 +// On Thu Jul 2 02:46:47 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkSpecTagManager.v b/src_SSITH_P3/Verilog_RTL_sim/mkSpecTagManager.v index 8b321df..f0eff84 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkSpecTagManager.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkSpecTagManager.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:35:51 BST 2020 +// On Thu Jul 2 02:50:37 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkSplitLSQ.v b/src_SSITH_P3/Verilog_RTL_sim/mkSplitLSQ.v index d0475e7..8529c9c 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkSplitLSQ.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkSplitLSQ.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:38:29 BST 2020 +// On Thu Jul 2 02:52:40 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkSplitTransCache.v b/src_SSITH_P3/Verilog_RTL_sim/mkSplitTransCache.v index 86aff82..47eca5f 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkSplitTransCache.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkSplitTransCache.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:31:46 BST 2020 +// On Thu Jul 2 02:47:21 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkStoreBufferEhr.v b/src_SSITH_P3/Verilog_RTL_sim/mkStoreBufferEhr.v index 5fe2c55..f4721c9 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkStoreBufferEhr.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkStoreBufferEhr.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:32:18 BST 2020 +// On Thu Jul 2 02:47:49 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkSyncBramFifo_w36_d512.v b/src_SSITH_P3/Verilog_RTL_sim/mkSyncBramFifo_w36_d512.v index b615a98..fd9fa85 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkSyncBramFifo_w36_d512.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkSyncBramFifo_w36_d512.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 24 20:18:07 BST 2020 +// On Thu Jul 2 02:54:40 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkSyncFifo_w32_d16.v b/src_SSITH_P3/Verilog_RTL_sim/mkSyncFifo_w32_d16.v index 3de176f..ea1de25 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkSyncFifo_w32_d16.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkSyncFifo_w32_d16.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 24 20:18:07 BST 2020 +// On Thu Jul 2 02:54:40 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkTagController.v b/src_SSITH_P3/Verilog_RTL_sim/mkTagController.v index 5dd6ffa..3762815 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkTagController.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkTagController.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 24 20:20:18 BST 2020 +// On Thu Jul 2 02:56:46 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkTourGHistReg.v b/src_SSITH_P3/Verilog_RTL_sim/mkTourGHistReg.v index f634caf..edf6404 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkTourGHistReg.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkTourGHistReg.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:42:00 BST 2020 +// On Thu Jul 2 02:56:53 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkTourPred.v b/src_SSITH_P3/Verilog_RTL_sim/mkTourPred.v index 7dd398c..c8df1e3 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkTourPred.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkTourPred.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:42:00 BST 2020 +// On Thu Jul 2 02:56:53 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkTourPredSecure.v b/src_SSITH_P3/Verilog_RTL_sim/mkTourPredSecure.v index e21695b..3cbec44 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkTourPredSecure.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkTourPredSecure.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:42:00 BST 2020 +// On Thu Jul 2 02:56:54 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpDiv.v b/src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpDiv.v index 8da4f6b..41e1ea0 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpDiv.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpDiv.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 24 20:19:04 BST 2020 +// On Thu Jul 2 02:55:33 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpDivIP.v b/src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpDivIP.v index 3a56d47..fc81e72 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpDivIP.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpDivIP.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 24 20:19:04 BST 2020 +// On Thu Jul 2 02:55:33 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpDivSim.v b/src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpDivSim.v index 2f09d8d..34f12e2 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpDivSim.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpDivSim.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 24 20:19:04 BST 2020 +// On Thu Jul 2 02:55:33 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpFma.v b/src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpFma.v index cffbd64..aaed17d 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpFma.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpFma.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 24 20:19:04 BST 2020 +// On Thu Jul 2 02:55:33 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpFmaIP.v b/src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpFmaIP.v index 9e50327..3f4bc80 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpFmaIP.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpFmaIP.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 24 20:19:04 BST 2020 +// On Thu Jul 2 02:55:33 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpFmaSim.v b/src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpFmaSim.v index 4070a0a..c430b5f 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpFmaSim.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpFmaSim.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 24 20:19:04 BST 2020 +// On Thu Jul 2 02:55:33 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpSqrt.v b/src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpSqrt.v index d0b3f73..a2db787 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpSqrt.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpSqrt.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 24 20:19:04 BST 2020 +// On Thu Jul 2 02:55:33 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpSqrtIP.v b/src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpSqrtIP.v index eb7438d..5635d3c 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpSqrtIP.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpSqrtIP.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 24 20:19:04 BST 2020 +// On Thu Jul 2 02:55:33 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpSqrtSim.v b/src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpSqrtSim.v index 386fe8b..f3d4b75 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpSqrtSim.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkXilinxFpSqrtSim.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 24 20:19:04 BST 2020 +// On Thu Jul 2 02:55:33 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/module_alu.v b/src_SSITH_P3/Verilog_RTL_sim/module_alu.v index d576884..91851d7 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/module_alu.v +++ b/src_SSITH_P3/Verilog_RTL_sim/module_alu.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:31:29 BST 2020 +// On Thu Jul 2 02:47:06 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/module_aluBr.v b/src_SSITH_P3/Verilog_RTL_sim/module_aluBr.v index 8257683..73a1e66 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/module_aluBr.v +++ b/src_SSITH_P3/Verilog_RTL_sim/module_aluBr.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:31:32 BST 2020 +// On Thu Jul 2 02:47:08 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/module_amoExec.v b/src_SSITH_P3/Verilog_RTL_sim/module_amoExec.v index 0f32283..412a430 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/module_amoExec.v +++ b/src_SSITH_P3/Verilog_RTL_sim/module_amoExec.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:31:04 BST 2020 +// On Thu Jul 2 02:46:44 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/module_basicExec.v b/src_SSITH_P3/Verilog_RTL_sim/module_basicExec.v index d016abd..c1a90d7 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/module_basicExec.v +++ b/src_SSITH_P3/Verilog_RTL_sim/module_basicExec.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:31:33 BST 2020 +// On Thu Jul 2 02:47:09 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/module_brAddrCalc.v b/src_SSITH_P3/Verilog_RTL_sim/module_brAddrCalc.v index d750d75..a6aa8bb 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/module_brAddrCalc.v +++ b/src_SSITH_P3/Verilog_RTL_sim/module_brAddrCalc.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:31:32 BST 2020 +// On Thu Jul 2 02:47:08 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/module_capChecks.v b/src_SSITH_P3/Verilog_RTL_sim/module_capChecks.v index 0876b85..a2c3e47 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/module_capChecks.v +++ b/src_SSITH_P3/Verilog_RTL_sim/module_capChecks.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:31:28 BST 2020 +// On Thu Jul 2 02:47:05 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/module_capInspect.v b/src_SSITH_P3/Verilog_RTL_sim/module_capInspect.v index 49aab89..a2f47ba 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/module_capInspect.v +++ b/src_SSITH_P3/Verilog_RTL_sim/module_capInspect.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:31:32 BST 2020 +// On Thu Jul 2 02:47:08 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/module_capModify.v b/src_SSITH_P3/Verilog_RTL_sim/module_capModify.v index 495aa95..1d0a441 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/module_capModify.v +++ b/src_SSITH_P3/Verilog_RTL_sim/module_capModify.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:31:32 BST 2020 +// On Thu Jul 2 02:47:08 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/module_checkForException.v b/src_SSITH_P3/Verilog_RTL_sim/module_checkForException.v index b1c03be..1342568 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/module_checkForException.v +++ b/src_SSITH_P3/Verilog_RTL_sim/module_checkForException.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:31:34 BST 2020 +// On Thu Jul 2 02:47:10 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/module_decode.v b/src_SSITH_P3/Verilog_RTL_sim/module_decode.v index f070e7f..1b51402 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/module_decode.v +++ b/src_SSITH_P3/Verilog_RTL_sim/module_decode.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:37:25 BST 2020 +// On Thu Jul 2 02:51:49 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/module_decodeBrPred.v b/src_SSITH_P3/Verilog_RTL_sim/module_decodeBrPred.v index 48a83ea..9524170 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/module_decodeBrPred.v +++ b/src_SSITH_P3/Verilog_RTL_sim/module_decodeBrPred.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:37:21 BST 2020 +// On Thu Jul 2 02:51:46 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/module_execFpuSimple.v b/src_SSITH_P3/Verilog_RTL_sim/module_execFpuSimple.v index fd1cf0f..016bf77 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/module_execFpuSimple.v +++ b/src_SSITH_P3/Verilog_RTL_sim/module_execFpuSimple.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:41:51 BST 2020 +// On Thu Jul 2 02:55:52 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/module_prepareBoundsCheck.v b/src_SSITH_P3/Verilog_RTL_sim/module_prepareBoundsCheck.v index 51f1860..ac83b4e 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/module_prepareBoundsCheck.v +++ b/src_SSITH_P3/Verilog_RTL_sim/module_prepareBoundsCheck.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:31:29 BST 2020 +// On Thu Jul 2 02:47:06 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/module_setBoundsALU.v b/src_SSITH_P3/Verilog_RTL_sim/module_setBoundsALU.v index 7f3ae8f..49f2643 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/module_setBoundsALU.v +++ b/src_SSITH_P3/Verilog_RTL_sim/module_setBoundsALU.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:31:30 BST 2020 +// On Thu Jul 2 02:47:06 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/module_specialRWALU.v b/src_SSITH_P3/Verilog_RTL_sim/module_specialRWALU.v index 9c97382..42eb20e 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/module_specialRWALU.v +++ b/src_SSITH_P3/Verilog_RTL_sim/module_specialRWALU.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:31:31 BST 2020 +// On Thu Jul 2 02:47:08 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkAluDispToRegFifo.v b/src_SSITH_P3/xilinx_ip/hdl/mkAluDispToRegFifo.v index a697760..eee29a5 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkAluDispToRegFifo.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkAluDispToRegFifo.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:54:34 BST 2020 +// On Thu Jul 2 02:57:22 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkAluExeToFinFifo.v b/src_SSITH_P3/xilinx_ip/hdl/mkAluExeToFinFifo.v index c089657..93ce9d9 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkAluExeToFinFifo.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkAluExeToFinFifo.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:54:35 BST 2020 +// On Thu Jul 2 02:57:23 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkAluRegToExeFifo.v b/src_SSITH_P3/xilinx_ip/hdl/mkAluRegToExeFifo.v index f47c1b6..f841252 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkAluRegToExeFifo.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkAluRegToExeFifo.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:54:34 BST 2020 +// On Thu Jul 2 02:57:23 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkBht.v b/src_SSITH_P3/xilinx_ip/hdl/mkBht.v index aceaf5a..1c572c0 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkBht.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkBht.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:53:27 BST 2020 +// On Thu Jul 2 02:55:23 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkCore.v b/src_SSITH_P3/xilinx_ip/hdl/mkCore.v index 8016884..e9a044b 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkCore.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkCore.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jul 1 17:06:51 BST 2020 +// On Thu Jul 2 02:58:25 BST 2020 // // // Ports: @@ -3539,7 +3539,7 @@ module mkCore(CLK, MUX_fetchStage$redirect_1__VAL_1, MUX_fetchStage$redirect_1__VAL_6; wire [64 : 0] MUX_f_csr_rsps$enq_1__VAL_3, MUX_f_fpr_rsps$enq_1__VAL_3; - wire [63 : 0] MUX_commitStage_rg_serial_num$write_1__VAL_2, + wire [63 : 0] MUX_commitStage_rg_serial_num$write_1__VAL_1, MUX_commitStage_rg_serial_num$write_1__VAL_3, MUX_csrf_minstret_ehr_data_lat_0$wset_1__VAL_2, MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1, @@ -3694,7 +3694,7 @@ module mkCore(CLK, MUX_epochManager$updatePrevEpoch_0_update_1__SEL_2, MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2, MUX_f_run_halt_rsps$enq_1__SEL_1, - MUX_flush_reservation$write_1__SEL_1, + MUX_flush_reservation$write_1__SEL_2, MUX_flush_tlbs$write_1__SEL_1, MUX_regRenamingTable$rename_0_getRename_1__SEL_1, MUX_regRenamingTable$rename_0_getRename_1__SEL_2, @@ -3716,47 +3716,48 @@ module mkCore(CLK, MUX_sbAggr$setReady_4_put_1__SEL_2, MUX_sbCons$setReady_3_put_1__SEL_1, MUX_sbCons$setReady_3_put_1__SEL_2, - MUX_sbCons$setReady_3_put_1__SEL_3; + MUX_sbCons$setReady_3_put_1__SEL_3, + MUX_started$write_1__SEL_1; // declarations used by system tasks // synopsys translate_off - reg [63 : 0] v__h213413; - reg [63 : 0] v__h215682; - reg [63 : 0] v__h271939; - reg [63 : 0] v__h347457; - reg [63 : 0] v__h423783; + reg [63 : 0] v__h213411; + reg [63 : 0] v__h215680; + reg [63 : 0] v__h271938; + reg [63 : 0] v__h347456; + reg [63 : 0] v__h423782; // synopsys translate_on // remaining internal signals reg [515 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5488; reg [127 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d4891; - reg [65 : 0] thin_address__h858473, thin_address__h899109; - reg [63 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q365, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q366, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q293, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q294, + reg [65 : 0] thin_address__h858472, thin_address__h899107; + reg [63 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q367, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q368, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q295, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q296, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q297, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q298, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q306, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q307, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q299, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q300, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q308, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q309, CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q18, CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q19, CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q20, CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q21, - CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q370, - CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q371, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q319, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q299, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q300, + CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q372, + CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q373, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q321, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q301, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q302, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q303, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q304, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q309, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q310, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q305, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q306, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q311, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q312, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q313, CASE_coreFix_memExe_lsqfirstLd_BIT_37_0_coreF_ETC__q33, CASE_coreFix_memExe_lsqfirstLd_BIT_37_0_mmio__ETC__q35, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14095, @@ -3769,33 +3770,33 @@ module mkCore(CLK, SEL_ARR_coreFix_memExe_forwardQ_data_0_216_BIT_ETC___d2234, SEL_ARR_coreFix_memExe_memRespLdQ_data_0_133_B_ETC___d2147, SEL_ARR_coreFix_memExe_memRespLdQ_data_0_133_B_ETC___d2151, - addr__h505615, - addr__h843950, - addr__h887459, - data_out__h1019990, - trap_val__h996887, - x__h264732; + addr__h505614, + addr__h843948, + addr__h887458, + data_out__h1020024, + trap_val__h996922, + x__h264730; reg [51 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q28, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q30, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q32, - CASE_guard04483_0b0_theResult___snd12395_BITS__ETC__q233, - CASE_guard04483_0b0_theResult___snd12395_BITS__ETC__q234, - CASE_guard13795_0b0_sfdin22015_BITS_56_TO_5_0b_ETC__q235, - CASE_guard13795_0b0_sfdin22015_BITS_56_TO_5_0b_ETC__q236, - CASE_guard22864_0b0_theResult___snd30800_BITS__ETC__q237, - CASE_guard22864_0b0_theResult___snd30800_BITS__ETC__q238, - CASE_guard26326_0b0_theResult___snd34238_BITS__ETC__q227, - CASE_guard26326_0b0_theResult___snd34238_BITS__ETC__q228, - CASE_guard35638_0b0_sfdin43858_BITS_56_TO_5_0b_ETC__q229, - CASE_guard35638_0b0_sfdin43858_BITS_56_TO_5_0b_ETC__q230, - CASE_guard44707_0b0_theResult___snd52643_BITS__ETC__q231, - CASE_guard44707_0b0_theResult___snd52643_BITS__ETC__q232, - CASE_guard65179_0b0_theResult___snd73091_BITS__ETC__q217, - CASE_guard65179_0b0_theResult___snd73091_BITS__ETC__q218, - CASE_guard74491_0b0_sfdin82711_BITS_56_TO_5_0b_ETC__q219, - CASE_guard74491_0b0_sfdin82711_BITS_56_TO_5_0b_ETC__q220, - CASE_guard83560_0b0_theResult___snd91496_BITS__ETC__q221, - CASE_guard83560_0b0_theResult___snd91496_BITS__ETC__q222, + CASE_guard04480_0b0_theResult___snd12392_BITS__ETC__q233, + CASE_guard04480_0b0_theResult___snd12392_BITS__ETC__q234, + CASE_guard13792_0b0_sfdin22012_BITS_56_TO_5_0b_ETC__q235, + CASE_guard13792_0b0_sfdin22012_BITS_56_TO_5_0b_ETC__q236, + CASE_guard22861_0b0_theResult___snd30797_BITS__ETC__q237, + CASE_guard22861_0b0_theResult___snd30797_BITS__ETC__q238, + CASE_guard26323_0b0_theResult___snd34235_BITS__ETC__q225, + CASE_guard26323_0b0_theResult___snd34235_BITS__ETC__q226, + CASE_guard35635_0b0_sfdin43855_BITS_56_TO_5_0b_ETC__q229, + CASE_guard35635_0b0_sfdin43855_BITS_56_TO_5_0b_ETC__q230, + CASE_guard44704_0b0_theResult___snd52640_BITS__ETC__q231, + CASE_guard44704_0b0_theResult___snd52640_BITS__ETC__q232, + CASE_guard65176_0b0_theResult___snd73088_BITS__ETC__q217, + CASE_guard65176_0b0_theResult___snd73088_BITS__ETC__q218, + CASE_guard74488_0b0_sfdin82708_BITS_56_TO_5_0b_ETC__q219, + CASE_guard74488_0b0_sfdin82708_BITS_56_TO_5_0b_ETC__q220, + CASE_guard83557_0b0_theResult___snd91493_BITS__ETC__q221, + CASE_guard83557_0b0_theResult___snd91493_BITS__ETC__q222, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13270, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13297, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13316, @@ -3809,108 +3810,108 @@ module mkCore(CLK, IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d17257; reg [31 : 0] SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1872, SEL_ARR_mmio_dataRespQ_data_0_389_BITS_31_TO_0_ETC___d2040, - x__h264887; - reg [29 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_22_ETC__q348, - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_817_ETC__q288, - CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q342, - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_22_ETC__q359, - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_817_ETC__q283, - CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q353, - CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q368, - CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q364, + x__h264885; + reg [29 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_22_ETC__q350, + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_817_ETC__q290, + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q344, + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_22_ETC__q361, + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_817_ETC__q285, + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q355, + CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q370, + CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q366, IF_fetchStage_pipelines_0_first__0256_BITS_268_ETC___d20382, IF_fetchStage_pipelines_1_first__0265_BITS_268_ETC___d21343; - reg [22 : 0] CASE_guard02939_0b0_theResult___snd10962_BITS__ETC__q66, - CASE_guard02939_0b0_theResult___snd10962_BITS__ETC__q67, - CASE_guard22215_0b0_sfdin30308_BITS_56_TO_34_0_ETC__q96, - CASE_guard22215_0b0_sfdin30308_BITS_56_TO_34_0_ETC__q97, - CASE_guard30922_0b0_theResult___snd38921_BITS__ETC__q94, - CASE_guard30922_0b0_theResult___snd38921_BITS__ETC__q95, - CASE_guard39852_0b0_sfdin48074_BITS_56_TO_34_0_ETC__q98, - CASE_guard39852_0b0_sfdin48074_BITS_56_TO_34_0_ETC__q99, - CASE_guard48688_0b0_theResult___snd56711_BITS__ETC__q100, - CASE_guard48688_0b0_theResult___snd56711_BITS__ETC__q101, - CASE_guard67962_0b0_sfdin76055_BITS_56_TO_34_0_ETC__q129, - CASE_guard67962_0b0_sfdin76055_BITS_56_TO_34_0_ETC__q130, - CASE_guard76464_0b0_sfdin84559_BITS_56_TO_34_0_ETC__q61, - CASE_guard76464_0b0_sfdin84559_BITS_56_TO_34_0_ETC__q62, - CASE_guard76669_0b0_theResult___snd84668_BITS__ETC__q131, - CASE_guard76669_0b0_theResult___snd84668_BITS__ETC__q132, - CASE_guard85173_0b0_theResult___snd93172_BITS__ETC__q59, - CASE_guard85173_0b0_theResult___snd93172_BITS__ETC__q60, - CASE_guard85599_0b0_sfdin93821_BITS_56_TO_34_0_ETC__q133, - CASE_guard85599_0b0_sfdin93821_BITS_56_TO_34_0_ETC__q134, - CASE_guard94103_0b0_sfdin02325_BITS_56_TO_34_0_ETC__q63, - CASE_guard94103_0b0_sfdin02325_BITS_56_TO_34_0_ETC__q64, - CASE_guard94435_0b0_theResult___snd02458_BITS__ETC__q135, - CASE_guard94435_0b0_theResult___snd02458_BITS__ETC__q136, - _theResult___fst_sfd__h576437, - _theResult___fst_sfd__h585160, - _theResult___fst_sfd__h593742, - _theResult___fst_sfd__h602926, - _theResult___fst_sfd__h611562, - _theResult___fst_sfd__h622188, - _theResult___fst_sfd__h630909, - _theResult___fst_sfd__h639491, - _theResult___fst_sfd__h648675, - _theResult___fst_sfd__h657311, - _theResult___fst_sfd__h667935, - _theResult___fst_sfd__h676656, - _theResult___fst_sfd__h685238, - _theResult___fst_sfd__h694422, - _theResult___fst_sfd__h703058; - reg [17 : 0] CASE_csrf_mepcc_reg_data_rl_BITS_52_TO_35_2621_ETC__q277, - CASE_csrf_sepcc_reg_data_rl_BITS_52_TO_35_2621_ETC__q276, - thin_otype__h858478, - thin_otype__h899114; + reg [22 : 0] CASE_guard02937_0b0_theResult___snd10960_BITS__ETC__q65, + CASE_guard02937_0b0_theResult___snd10960_BITS__ETC__q66, + CASE_guard22213_0b0_sfdin30306_BITS_56_TO_34_0_ETC__q96, + CASE_guard22213_0b0_sfdin30306_BITS_56_TO_34_0_ETC__q97, + CASE_guard30920_0b0_theResult___snd38919_BITS__ETC__q94, + CASE_guard30920_0b0_theResult___snd38919_BITS__ETC__q95, + CASE_guard39850_0b0_sfdin48072_BITS_56_TO_34_0_ETC__q98, + CASE_guard39850_0b0_sfdin48072_BITS_56_TO_34_0_ETC__q99, + CASE_guard48686_0b0_theResult___snd56709_BITS__ETC__q101, + CASE_guard48686_0b0_theResult___snd56709_BITS__ETC__q102, + CASE_guard67960_0b0_sfdin76053_BITS_56_TO_34_0_ETC__q131, + CASE_guard67960_0b0_sfdin76053_BITS_56_TO_34_0_ETC__q132, + CASE_guard76462_0b0_sfdin84557_BITS_56_TO_34_0_ETC__q61, + CASE_guard76462_0b0_sfdin84557_BITS_56_TO_34_0_ETC__q62, + CASE_guard76667_0b0_theResult___snd84666_BITS__ETC__q129, + CASE_guard76667_0b0_theResult___snd84666_BITS__ETC__q130, + CASE_guard85171_0b0_theResult___snd93170_BITS__ETC__q59, + CASE_guard85171_0b0_theResult___snd93170_BITS__ETC__q60, + CASE_guard85597_0b0_sfdin93819_BITS_56_TO_34_0_ETC__q133, + CASE_guard85597_0b0_sfdin93819_BITS_56_TO_34_0_ETC__q134, + CASE_guard94101_0b0_sfdin02323_BITS_56_TO_34_0_ETC__q63, + CASE_guard94101_0b0_sfdin02323_BITS_56_TO_34_0_ETC__q64, + CASE_guard94433_0b0_theResult___snd02456_BITS__ETC__q135, + CASE_guard94433_0b0_theResult___snd02456_BITS__ETC__q136, + _theResult___fst_sfd__h576435, + _theResult___fst_sfd__h585158, + _theResult___fst_sfd__h593740, + _theResult___fst_sfd__h602924, + _theResult___fst_sfd__h611560, + _theResult___fst_sfd__h622186, + _theResult___fst_sfd__h630907, + _theResult___fst_sfd__h639489, + _theResult___fst_sfd__h648673, + _theResult___fst_sfd__h657309, + _theResult___fst_sfd__h667933, + _theResult___fst_sfd__h676654, + _theResult___fst_sfd__h685236, + _theResult___fst_sfd__h694420, + _theResult___fst_sfd__h703056; + reg [17 : 0] CASE_csrf_mepcc_reg_data_rl_BITS_52_TO_35_2621_ETC__q279, + CASE_csrf_sepcc_reg_data_rl_BITS_52_TO_35_2621_ETC__q278, + thin_otype__h858477, + thin_otype__h899112; reg [15 : 0] SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1885, SEL_ARR_mmio_dataRespQ_data_0_389_BITS_15_TO_0_ETC___d2052; - reg [13 : 0] thin_addrBits__h858474, - thin_addrBits__h899110, - thin_bounds_baseBits__h860422, - thin_bounds_baseBits__h900516, - thin_bounds_topBits__h860421, - thin_bounds_topBits__h900515; - reg [12 : 0] CASE_coreFix_memExe_lsqfirstLd_BITS_15_TO_14__ETC__q339, - CASE_coreFix_memExe_lsqfirstSt_BITS_12_TO_11__ETC__q335, - CASE_robdeqPort_0_deq_data_BITS_273_TO_272_0__ETC__q326; - reg [11 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q350, - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_728_ETC__q290, - CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q344, - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q361, - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_728_ETC__q285, - CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q355, + reg [13 : 0] thin_addrBits__h858473, + thin_addrBits__h899108, + thin_bounds_baseBits__h860421, + thin_bounds_baseBits__h900514, + thin_bounds_topBits__h860420, + thin_bounds_topBits__h900513; + reg [12 : 0] CASE_coreFix_memExe_lsqfirstLd_BITS_15_TO_14__ETC__q341, + CASE_coreFix_memExe_lsqfirstSt_BITS_12_TO_11__ETC__q337, + CASE_robdeqPort_0_deq_data_BITS_273_TO_272_0__ETC__q328; + reg [11 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q352, + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_728_ETC__q292, + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q346, + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q363, + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_728_ETC__q287, + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q357, CASE_fetchStagepipelines_0_first_BITS_179_TO__ETC__q254, CASE_fetchStagepipelines_1_first_BITS_179_TO__ETC__q259; - reg [10 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_19_ETC__q349, - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_787_ETC__q289, - CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q343, - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_19_ETC__q360, - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_787_ETC__q284, - CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q354, + reg [10 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_19_ETC__q351, + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_787_ETC__q291, + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q345, + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_19_ETC__q362, + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_787_ETC__q286, + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q356, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q27, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q29, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q31, CASE_fetchStagepipelines_0_first_BITS_238_TO__ETC__q256, CASE_fetchStagepipelines_1_first_BITS_238_TO__ETC__q264, - CASE_guard04483_0b0_theResult___fst_exp12444_0_ETC__q172, - CASE_guard04483_0b0_theResult___fst_exp12444_0_ETC__q173, - CASE_guard13795_0b0_theResult___fst_exp22021_0_ETC__q201, - CASE_guard13795_0b0_theResult___fst_exp22021_0_ETC__q202, - CASE_guard22864_0b0_theResult___fst_exp30854_0_ETC__q203, - CASE_guard22864_0b0_theResult___fst_exp30854_0_ETC__q204, - CASE_guard26326_0b0_theResult___fst_exp34287_0_ETC__q155, - CASE_guard26326_0b0_theResult___fst_exp34287_0_ETC__q156, - CASE_guard35638_0b0_theResult___fst_exp43864_0_ETC__q223, - CASE_guard35638_0b0_theResult___fst_exp43864_0_ETC__q224, - CASE_guard44707_0b0_theResult___fst_exp52697_0_ETC__q225, - CASE_guard44707_0b0_theResult___fst_exp52697_0_ETC__q226, - CASE_guard65179_0b0_theResult___fst_exp73140_0_ETC__q195, - CASE_guard65179_0b0_theResult___fst_exp73140_0_ETC__q196, - CASE_guard74491_0b0_theResult___fst_exp82717_0_ETC__q199, - CASE_guard74491_0b0_theResult___fst_exp82717_0_ETC__q200, - CASE_guard83560_0b0_theResult___fst_exp91550_0_ETC__q197, - CASE_guard83560_0b0_theResult___fst_exp91550_0_ETC__q198, + CASE_guard04480_0b0_theResult___fst_exp12441_0_ETC__q172, + CASE_guard04480_0b0_theResult___fst_exp12441_0_ETC__q173, + CASE_guard13792_0b0_theResult___fst_exp22018_0_ETC__q203, + CASE_guard13792_0b0_theResult___fst_exp22018_0_ETC__q204, + CASE_guard22861_0b0_theResult___fst_exp30851_0_ETC__q201, + CASE_guard22861_0b0_theResult___fst_exp30851_0_ETC__q202, + CASE_guard26323_0b0_theResult___fst_exp34284_0_ETC__q155, + CASE_guard26323_0b0_theResult___fst_exp34284_0_ETC__q156, + CASE_guard35635_0b0_theResult___fst_exp43861_0_ETC__q223, + CASE_guard35635_0b0_theResult___fst_exp43861_0_ETC__q224, + CASE_guard44704_0b0_theResult___fst_exp52694_0_ETC__q227, + CASE_guard44704_0b0_theResult___fst_exp52694_0_ETC__q228, + CASE_guard65176_0b0_theResult___fst_exp73137_0_ETC__q195, + CASE_guard65176_0b0_theResult___fst_exp73137_0_ETC__q196, + CASE_guard74488_0b0_theResult___fst_exp82714_0_ETC__q197, + CASE_guard74488_0b0_theResult___fst_exp82714_0_ETC__q198, + CASE_guard83557_0b0_theResult___fst_exp91547_0_ETC__q199, + CASE_guard83557_0b0_theResult___fst_exp91547_0_ETC__q200, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13170, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13213, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13244, @@ -3920,79 +3921,79 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14655, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14693, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14724; - reg [7 : 0] CASE_guard02939_0b0_theResult___fst_exp11016_0_ETC__q57, - CASE_guard02939_0b0_theResult___fst_exp11016_0_ETC__q58, - CASE_guard22215_0b0_theResult___fst_exp30314_0_ETC__q81, - CASE_guard22215_0b0_theResult___fst_exp30314_0_ETC__q82, - CASE_guard30922_0b0_theResult___fst_exp38970_0_ETC__q79, - CASE_guard30922_0b0_theResult___fst_exp38970_0_ETC__q80, - CASE_guard39852_0b0_theResult___fst_exp48080_0_ETC__q87, - CASE_guard39852_0b0_theResult___fst_exp48080_0_ETC__q88, - CASE_guard48688_0b0_theResult___fst_exp56765_0_ETC__q92, - CASE_guard48688_0b0_theResult___fst_exp56765_0_ETC__q93, - CASE_guard67962_0b0_theResult___fst_exp76061_0_ETC__q116, - CASE_guard67962_0b0_theResult___fst_exp76061_0_ETC__q117, - CASE_guard76464_0b0_theResult___fst_exp84565_0_ETC__q46, - CASE_guard76464_0b0_theResult___fst_exp84565_0_ETC__q47, - CASE_guard76669_0b0_theResult___fst_exp84717_0_ETC__q114, - CASE_guard76669_0b0_theResult___fst_exp84717_0_ETC__q115, - CASE_guard85173_0b0_theResult___fst_exp93221_0_ETC__q44, - CASE_guard85173_0b0_theResult___fst_exp93221_0_ETC__q45, - CASE_guard85599_0b0_theResult___fst_exp93827_0_ETC__q122, - CASE_guard85599_0b0_theResult___fst_exp93827_0_ETC__q123, - CASE_guard94103_0b0_theResult___fst_exp02331_0_ETC__q52, - CASE_guard94103_0b0_theResult___fst_exp02331_0_ETC__q53, - CASE_guard94435_0b0_theResult___fst_exp02512_0_ETC__q127, - CASE_guard94435_0b0_theResult___fst_exp02512_0_ETC__q128, + reg [7 : 0] CASE_guard02937_0b0_theResult___fst_exp11014_0_ETC__q57, + CASE_guard02937_0b0_theResult___fst_exp11014_0_ETC__q58, + CASE_guard22213_0b0_theResult___fst_exp30312_0_ETC__q81, + CASE_guard22213_0b0_theResult___fst_exp30312_0_ETC__q82, + CASE_guard30920_0b0_theResult___fst_exp38968_0_ETC__q79, + CASE_guard30920_0b0_theResult___fst_exp38968_0_ETC__q80, + CASE_guard39850_0b0_theResult___fst_exp48078_0_ETC__q87, + CASE_guard39850_0b0_theResult___fst_exp48078_0_ETC__q88, + CASE_guard48686_0b0_theResult___fst_exp56763_0_ETC__q92, + CASE_guard48686_0b0_theResult___fst_exp56763_0_ETC__q93, + CASE_guard67960_0b0_theResult___fst_exp76059_0_ETC__q116, + CASE_guard67960_0b0_theResult___fst_exp76059_0_ETC__q117, + CASE_guard76462_0b0_theResult___fst_exp84563_0_ETC__q46, + CASE_guard76462_0b0_theResult___fst_exp84563_0_ETC__q47, + CASE_guard76667_0b0_theResult___fst_exp84715_0_ETC__q114, + CASE_guard76667_0b0_theResult___fst_exp84715_0_ETC__q115, + CASE_guard85171_0b0_theResult___fst_exp93219_0_ETC__q44, + CASE_guard85171_0b0_theResult___fst_exp93219_0_ETC__q45, + CASE_guard85597_0b0_theResult___fst_exp93825_0_ETC__q122, + CASE_guard85597_0b0_theResult___fst_exp93825_0_ETC__q123, + CASE_guard94101_0b0_theResult___fst_exp02329_0_ETC__q52, + CASE_guard94101_0b0_theResult___fst_exp02329_0_ETC__q53, + CASE_guard94433_0b0_theResult___fst_exp02510_0_ETC__q127, + CASE_guard94433_0b0_theResult___fst_exp02510_0_ETC__q128, SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1907, SEL_ARR_mmio_dataRespQ_data_0_389_BITS_7_TO_0__ETC___d2073, - _theResult___fst_exp__h576436, - _theResult___fst_exp__h585159, - _theResult___fst_exp__h593741, - _theResult___fst_exp__h602925, - _theResult___fst_exp__h611561, - _theResult___fst_exp__h622187, - _theResult___fst_exp__h630908, - _theResult___fst_exp__h639490, - _theResult___fst_exp__h648674, - _theResult___fst_exp__h657310, - _theResult___fst_exp__h667934, - _theResult___fst_exp__h676655, - _theResult___fst_exp__h685237, - _theResult___fst_exp__h694421, - _theResult___fst_exp__h703057; - reg [5 : 0] CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q340, + _theResult___fst_exp__h576434, + _theResult___fst_exp__h585157, + _theResult___fst_exp__h593739, + _theResult___fst_exp__h602923, + _theResult___fst_exp__h611559, + _theResult___fst_exp__h622185, + _theResult___fst_exp__h630906, + _theResult___fst_exp__h639488, + _theResult___fst_exp__h648672, + _theResult___fst_exp__h657308, + _theResult___fst_exp__h667932, + _theResult___fst_exp__h676653, + _theResult___fst_exp__h685235, + _theResult___fst_exp__h694419, + _theResult___fst_exp__h703055; + reg [5 : 0] CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q342, CASE_mmio_cRqQ_data_0_BITS_150_TO_149_0_mmio_c_ETC__q1, - CASE_mmio_dataReqQ_data_0_BITS_150_TO_149_0_mm_ETC__q331, - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012; - reg [4 : 0] CASE_basicExec_7743_BITS_270_TO_266_0_basicExe_ETC__q357, - CASE_basicExec_9859_BITS_270_TO_266_0_basicExe_ETC__q346, - CASE_capChecks_160_BITS_4_TO_0_0_capChecks_160_ETC__q292, + CASE_mmio_dataReqQ_data_0_BITS_150_TO_149_0_mm_ETC__q333, + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014; + reg [4 : 0] CASE_basicExec_7743_BITS_270_TO_266_0_basicExe_ETC__q359, + CASE_basicExec_9859_BITS_270_TO_266_0_basicExe_ETC__q348, + CASE_capChecks_160_BITS_4_TO_0_0_capChecks_160_ETC__q294, CASE_checkForException_0654_BITS_4_TO_0_0_chec_ETC__q257, CASE_commitStage_commitTrap_BITS_36_TO_32_0_co_ETC__q25, - CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_12_ETC__q351, - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_715_ETC__q291, - CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q345, - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_12_ETC__q362, - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_715_ETC__q286, - CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q356, - CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q337, - CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q338, - CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q333, - CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q334, + CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_12_ETC__q353, + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_715_ETC__q293, + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q347, + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_12_ETC__q364, + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_715_ETC__q288, + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q358, + CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q339, + CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q340, + CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q335, + CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q336, CASE_csrf_mccsr_reg_BITS_4_TO_0_0_csrf_mccsr_r_ETC__q24, - CASE_f_csr_reqsD_OUT_BITS_9_TO_5_0_f_csr_reqs_ETC__q329, + CASE_f_csr_reqsD_OUT_BITS_9_TO_5_0_f_csr_reqs_ETC__q331, CASE_fetchStagepipelines_0_first_BITS_166_TO__ETC__q253, CASE_fetchStagepipelines_1_first_BITS_166_TO__ETC__q263, - CASE_robdeqPort_0_deq_data_BITS_265_TO_261_0__ETC__q324, - CASE_robdeqPort_0_deq_data_BITS_265_TO_261_0__ETC__q325, - CASE_robdeqPort_0_deq_data_BITS_95_TO_326_BITS_ETC__q330, + CASE_robdeqPort_0_deq_data_BITS_265_TO_261_0__ETC__q326, + CASE_robdeqPort_0_deq_data_BITS_265_TO_261_0__ETC__q327, + CASE_robdeqPort_0_deq_data_BITS_95_TO_327_BITS_ETC__q332, IF_fetchStage_pipelines_0_first__0256_BITS_265_ETC___d22045, IF_fetchStage_pipelines_1_first__0265_BITS_265_ETC___d22190, - cause_code__h995320, - i__h995336, - t__h212841, - t__h215127; + cause_code__h995318, + i__h995334, + t__h212839, + t__h215125; reg [3 : 0] CASE_IF_coreFix_aluExe_0_dispToRegQ_first__838_ETC__q248, CASE_IF_coreFix_aluExe_0_regToExeQ_first__9457_ETC__q250, CASE_IF_coreFix_aluExe_0_rsAlu_dispatchData__8_ETC__q246, @@ -4002,9 +4003,9 @@ module mkCore(CLK, CASE_IF_fetchStage_pipelines_0_first__0256_BIT_ETC__q252, CASE_IF_fetchStage_pipelines_1_first__0265_BIT_ETC__q261, CASE_checkForException_0654_BITS_4_TO_0_0_0_1__ETC__q258, - CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q336, - CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q332, - CASE_robdeqPort_0_deq_data_BITS_264_TO_261_0__ETC__q323, + CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q338, + CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q334, + CASE_robdeqPort_0_deq_data_BITS_264_TO_261_0__ETC__q325, IF_checkForException_0654_BITS_3_TO_0_0907_EQ__ETC___d20927, IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d18527, IF_coreFix_aluExe_0_regToExeQ_first__9457_BITS_ETC___d19515, @@ -4017,10 +4018,10 @@ module mkCore(CLK, IF_fetchStage_pipelines_0_first__0256_BIT_69_0_ETC___d20812, IF_fetchStage_pipelines_1_first__0265_BITS_236_ETC___d21371, IF_fetchStage_pipelines_1_first__0265_BITS_265_ETC___d22191, - IF_rob_deqPort_0_deq_data__2261_BIT_294_3454_T_ETC___d23476, - i__h995510, - thin_perms_soft__h858713, - thin_perms_soft__h899289; + IF_rob_deqPort_0_deq_data__2261_BIT_294_3456_T_ETC___d23478, + i__h995534, + thin_perms_soft__h858712, + thin_perms_soft__h899287; reg [2 : 0] CASE_IF_coreFix_aluExe_0_dispToRegQ_first__838_ETC__q247, CASE_IF_coreFix_aluExe_0_regToExeQ_first__9457_ETC__q249, CASE_IF_coreFix_aluExe_0_rsAlu_dispatchData__8_ETC__q245, @@ -4029,16 +4030,16 @@ module mkCore(CLK, CASE_IF_coreFix_aluExe_1_rsAlu_dispatchData__5_ETC__q241, CASE_IF_fetchStage_pipelines_0_first__0256_BIT_ETC__q251, CASE_IF_fetchStage_pipelines_1_first__0265_BIT_ETC__q260, - CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_19_ETC__q347, - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_791_ETC__q287, - CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q341, - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_19_ETC__q358, - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_791_ETC__q282, - CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q352, - CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q367, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q281, - CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q363, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q318, + CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_19_ETC__q349, + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_791_ETC__q289, + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q343, + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_19_ETC__q360, + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_791_ETC__q284, + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q354, + CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q369, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q283, + CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q365, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q320, CASE_fetchStagepipelines_0_first_BITS_242_TO__ETC__q255, CASE_fetchStagepipelines_1_first_BITS_242_TO__ETC__q262, IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d18559, @@ -4050,16 +4051,18 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14868, IF_fetchStage_pipelines_0_first__0256_BITS_232_ETC___d20442, IF_fetchStage_pipelines_1_first__0265_BITS_232_ETC___d21403, - x__h501097, - x__h508765; - reg [1 : 0] CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q314, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q369, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q316, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q320, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q312, - thin_reserved__h858477, - thin_reserved__h899113; - reg CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q158, + x__h501096, + x__h508764; + reg [1 : 0] CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q316, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q371, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q318, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q322, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q314, + thin_reserved__h858476, + thin_reserved__h899111; + reg CASE_commitStage_commitTrap_BITS_44_TO_43_0_NO_ETC__q277, + CASE_commitStage_commitTrap_BITS_44_TO_43_0_cs_ETC__q276, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q158, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q160, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q162, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q175, @@ -4074,21 +4077,21 @@ module mkCore(CLK, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q212, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q214, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q216, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q305, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q315, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q321, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q322, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q307, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q317, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q323, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q324, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q37, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q38, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q39, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q317, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q278, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q279, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q319, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q280, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q308, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q313, - CASE_coreFix_memExe_forwardQ_deqP_0_coreFix_me_ETC__q328, - CASE_coreFix_memExe_memRespLdQ_deqP_0_coreFix__ETC__q327, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q281, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q282, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q310, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q315, + CASE_coreFix_memExe_forwardQ_deqP_0_coreFix_me_ETC__q329, + CASE_coreFix_memExe_memRespLdQ_deqP_0_coreFix__ETC__q330, CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q274, CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q275, CASE_fetchStage_pipelines_0_canDeq__0254_AND_N_ETC__q270, @@ -4099,46 +4102,46 @@ module mkCore(CLK, CASE_fetchStagepipelines_1_first_BITS_265_TO__ETC__q267, CASE_fetchStagepipelines_1_first_BITS_265_TO__ETC__q271, CASE_fetchStagepipelines_1_first_BITS_268_TO__ETC__q273, - CASE_guard02939_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q74, - CASE_guard02939_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q73, - CASE_guard04483_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q184, - CASE_guard04483_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q174, - CASE_guard13795_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q180, - CASE_guard13795_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q176, - CASE_guard22215_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q103, - CASE_guard22215_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q102, - CASE_guard22864_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q182, - CASE_guard22864_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q178, - CASE_guard26326_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q157, - CASE_guard30922_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q105, - CASE_guard30922_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q104, - CASE_guard35638_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q159, - CASE_guard39852_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q107, - CASE_guard39852_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q106, - CASE_guard44707_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q161, - CASE_guard48688_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q109, - CASE_guard48688_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q108, - CASE_guard65179_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q215, - CASE_guard65179_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q205, - CASE_guard67962_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q139, - CASE_guard67962_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q137, - CASE_guard74491_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q211, - CASE_guard74491_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q207, - CASE_guard76464_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q68, - CASE_guard76464_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q65, - CASE_guard76669_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q140, - CASE_guard76669_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q138, - CASE_guard83560_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q213, - CASE_guard83560_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q209, - CASE_guard85173_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q70, - CASE_guard85173_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q69, - CASE_guard85599_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q142, - CASE_guard85599_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q141, - CASE_guard94103_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q72, - CASE_guard94103_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q71, - CASE_guard94435_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q144, - CASE_guard94435_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q143, - CASE_k45030_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q268, + CASE_guard02937_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q74, + CASE_guard02937_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q73, + CASE_guard04480_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q184, + CASE_guard04480_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q176, + CASE_guard13792_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q180, + CASE_guard13792_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q174, + CASE_guard22213_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q103, + CASE_guard22213_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q100, + CASE_guard22861_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q182, + CASE_guard22861_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q178, + CASE_guard26323_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q157, + CASE_guard30920_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q105, + CASE_guard30920_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q104, + CASE_guard35635_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q159, + CASE_guard39850_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q107, + CASE_guard39850_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q106, + CASE_guard44704_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q161, + CASE_guard48686_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q109, + CASE_guard48686_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q108, + CASE_guard65176_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q215, + CASE_guard65176_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q205, + CASE_guard67960_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q138, + CASE_guard67960_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q137, + CASE_guard74488_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q211, + CASE_guard74488_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q207, + CASE_guard76462_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q68, + CASE_guard76462_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q67, + CASE_guard76667_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q140, + CASE_guard76667_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q139, + CASE_guard83557_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q213, + CASE_guard83557_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q209, + CASE_guard85171_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q70, + CASE_guard85171_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q69, + CASE_guard85597_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q142, + CASE_guard85597_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q141, + CASE_guard94101_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q72, + CASE_guard94101_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q71, + CASE_guard94433_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q144, + CASE_guard94433_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q143, + CASE_k45028_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q268, IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19204, IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19240, IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19249, @@ -4243,12 +4246,12 @@ module mkCore(CLK, wire [515 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5171, IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d5172, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d7137, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d24448; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d24450; wire [511 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d4943; wire [457 : 0] coreFix_memExe_lsq_getOrigBE_coreFix_memExe_re_ETC___d4250; wire [383 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5169, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d7127, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d24438; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d24440; wire [294 : 0] fetchStage_pipelines_0_first__0256_BIT_167_059_ETC___d21145; wire [278 : 0] IF_coreFix_memExe_lsq_getOrigBE_coreFix_memExe_ETC___d4249; wire [265 : 0] prepareBoundsCheck___d4244; @@ -4269,27 +4272,27 @@ module mkCore(CLK, IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d5560; wire [128 : 0] amoExec___d4922, amoExec___d773, - new_pc__h872925, - new_pc__h912073, - next_pc__h1012222, - pc__h963242, - v__h1012261, - v__h1012970, - x__h879903, - x__h914620; + new_pc__h872924, + new_pc__h912071, + next_pc__h1012257, + pc__h963240, + v__h1012296, + v__h1013005, + x__h879902, + x__h914618; wire [127 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5165, SEXT_SEL_ARR_SEL_ARR_coreFix_memExe_dMem_cache_ETC___d4881, SEXT_SEL_ARR_SEL_ARR_coreFix_memExe_dMem_cache_ETC___d4889, coreFix_memExe_regToExeQ_first__645_BITS_140_T_ETC___d4070, - x__h183399, - x__h199251; + x__h183397, + x__h199249; wire [109 : 0] IF_fetchStage_pipelines_0_first__0256_BITS_238_ETC___d20622, IF_fetchStage_pipelines_1_first__0265_BITS_238_ETC___d21583; wire [85 : 0] IF_coreFix_memExe_dispToRegQ_first__686_BIT_10_ETC___d3580; wire [71 : 0] IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19395, IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d17261, - IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d23335, - IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d23198; + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d23337, + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d23200; wire [68 : 0] execFpuSimple___d15207; wire [66 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d7036; wire [65 : 0] IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__840_ETC___d18813, @@ -4308,91 +4311,91 @@ module mkCore(CLK, IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16423, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3048, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3417, - addTop__h239973, - addTop__h241130, - addTop__h254754, - address__h1000151, - address__h1000495, - address__h999494, - address__h999838, + addTop__h239970, + addTop__h241127, + addTop__h254751, + address__h1000186, + address__h1000530, + address__h999529, + address__h999873, coreFix_memExe_dTlb_procResp__257_BITS_452_TO__ETC___d4407, coreFix_memExe_regToExeQ_first__645_BITS_220_T_ETC___d3766, coreFix_memExe_regToExeQ_first__645_BITS_383_T_ETC___d3704, - cr_address__h866671, - cr_address__h867219, - cr_address__h906357, - cr_address__h906905, - data_address__h1018717, - data_address__h1019571, - in__h239804, - in__h240961, - in__h254585, - in__h854154, - in__h854459, - in__h855147, - in__h855451, - in__h855977, - in__h997656, - pc_address__h994739, - pointer__h242638, - res_address__h126822, - res_address__h139734, - res_address__h178898, - res_address__h197663, - res_address__h216422, - res_address__h235323, - res_address__h567346, - res_address__h568198, - res_address__h613955, - res_address__h659702, - res_address__h705511, - res_address__h706371, - res_address__h848644, - res_address__h892145, - result__h240600, - result__h241757, - result__h255381, - result_d_address__h1008566, - result_d_address__h1008969, - result_d_address__h1009386, - result_d_address__h1009789, - result_d_address__h1010458, - result_d_address__h1031617, - result_d_address__h1032020, - result_d_address__h1032437, - result_d_address__h1032840, - result_d_address__h1033507, - result_d_address__h242849, - ret__h239977, - ret__h241134, - ret__h254758, - x__h1000345, - x__h1000649, - x__h235746, - x__h239822, - x__h239970, - x__h240979, - x__h241127, - x__h248120, - x__h254603, - x__h254751, - x__h854172, - x__h854477, - x__h855165, - x__h855469, - x__h855995, - x__h997674, - x__h999688, - x__h999992, - y__h239821, - y__h240978, - y__h254602, - y__h854171, - y__h854476, - y__h855164, - y__h855468, - y__h855994, - y__h997673; + cr_address__h866670, + cr_address__h867218, + cr_address__h906355, + cr_address__h906903, + data_address__h1018751, + data_address__h1019605, + in__h239801, + in__h240958, + in__h254582, + in__h854153, + in__h854458, + in__h855146, + in__h855450, + in__h855976, + in__h997691, + pc_address__h994737, + pointer__h242635, + res_address__h126821, + res_address__h139733, + res_address__h178896, + res_address__h197661, + res_address__h216420, + res_address__h235320, + res_address__h567343, + res_address__h568196, + res_address__h613953, + res_address__h659700, + res_address__h705509, + res_address__h706369, + res_address__h848642, + res_address__h892144, + result__h240597, + result__h241754, + result__h255378, + result_d_address__h1008601, + result_d_address__h1009004, + result_d_address__h1009421, + result_d_address__h1009824, + result_d_address__h1010493, + result_d_address__h1031651, + result_d_address__h1032054, + result_d_address__h1032471, + result_d_address__h1032874, + result_d_address__h1033541, + result_d_address__h242846, + ret__h239974, + ret__h241131, + ret__h254755, + x__h1000027, + x__h1000380, + x__h1000684, + x__h235743, + x__h239819, + x__h239967, + x__h240976, + x__h241124, + x__h248117, + x__h254600, + x__h254748, + x__h854171, + x__h854476, + x__h855164, + x__h855468, + x__h855994, + x__h997709, + x__h999723, + y__h239818, + y__h240975, + y__h254599, + y__h854170, + y__h854475, + y__h855163, + y__h855467, + y__h855993, + y__h997708; wire [63 : 0] IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13324, IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12485, IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12486, @@ -4412,214 +4415,214 @@ module mkCore(CLK, IF_coreFix_memExe_lsq_firstLd__498_BIT_113_513_ETC___d2078, IF_coreFix_memExe_lsq_firstLd__498_BIT_117_521_ETC___d1913, IF_coreFix_memExe_lsq_firstLd__498_BIT_117_521_ETC___d2079, - IF_csrf_mtcc_reg_read__6198_BIT_86_2807_AND_NO_ETC___d22905, - IF_csrf_stcc_reg_read__6046_BIT_86_2736_AND_NO_ETC___d22904, - IF_rob_deqPort_0_canDeq__3598_THEN_IF_NOT_rob__ETC___d23719, - SEXT__0_CONCAT_IF_INV_commitStage_commitTrap_2_ETC___d22677, + IF_csrf_mtcc_reg_read__6198_BIT_86_2809_AND_NO_ETC___d22907, + IF_csrf_stcc_reg_read__6046_BIT_86_2738_AND_NO_ETC___d22906, + IF_rob_deqPort_0_canDeq__3600_THEN_IF_NOT_rob__ETC___d23721, + SEXT__0_CONCAT_IF_INV_commitStage_commitTrap_2_ETC___d22678, SEXT__0_CONCAT_IF_csrf_mepcc_reg_data_lat_0_wh_ETC___d16261, SEXT__0_CONCAT_IF_csrf_sepcc_reg_data_lat_0_wh_ETC___d16109, SEXT__0_CONCAT_csrf_mtcc_reg_read__6198_BITS_8_ETC___d16222, SEXT__0_CONCAT_csrf_rg_dpc_read__6343_BITS_85__ETC___d16367, SEXT__0_CONCAT_csrf_stcc_reg_read__6046_BITS_8_ETC___d16070, - _18446744073709551615_SL_csrf_mtcc_reg_read__61_ETC___d22824, - _18446744073709551615_SL_csrf_stcc_reg_read__60_ETC___d22755, - _theResult___fst__h836129, - _theResult___snd__h836130, - a___1__h835848, - a___1__h836134, - a__h835707, - addBase__h1008585, - addBase__h1008988, - addBase__h1009405, - addBase__h1009808, - addBase__h1010478, - addBase__h239864, - addBase__h241021, - addBase__h254645, - addr__h148439, - addr__h152015, - addr__h235317, - addr__h989736, - address__h1013682, - address__h999428, - address__h999478, - b___1__h835849, - b___1__h836179, - b__h835708, - base__h999389, - base__h999443, - bot__h1008588, - bot__h1008991, - bot__h1009408, - bot__h1009811, - bot__h1010481, - csrf_mtcc_reg_read__6198_BITS_149_TO_86_2811_A_ETC___d22814, - csrf_stcc_reg_read__6046_BITS_149_TO_86_2740_A_ETC___d22743, - data___1__h705533, - data___1__h706393, - data__h567680, - data__h613440, - data__h659187, - data__h705001, - data__h705833, - data__h705864, - fcsr_csr__read__h849219, - fflags_csr__read__h849194, - frm_csr__read__h849205, - mask__h1000157, - mask__h999500, - mcause_csr__read__h850886, - mcounteren_csr__read__h850620, - medeleg_csr__read__h850223, - mideleg_csr__read__h850321, - mie_csr__read__h850448, - mip_csr__read__h851125, - mstatus_csr__read__h850062, - n__read__h1014112, + _18446744073709551615_SL_csrf_mtcc_reg_read__61_ETC___d22826, + _18446744073709551615_SL_csrf_stcc_reg_read__60_ETC___d22757, + _theResult___fst__h836126, + _theResult___snd__h836127, + a___1__h835845, + a___1__h836131, + a__h835704, + addBase__h1008620, + addBase__h1009023, + addBase__h1009440, + addBase__h1009843, + addBase__h1010513, + addBase__h239861, + addBase__h241018, + addBase__h254642, + addr__h148438, + addr__h152014, + addr__h235314, + addr__h989734, + address__h1013717, + address__h999463, + address__h999513, + b___1__h835846, + b___1__h836176, + b__h835705, + base__h999424, + base__h999478, + bot__h1008623, + bot__h1009026, + bot__h1009443, + bot__h1009846, + bot__h1010516, + csrf_mtcc_reg_read__6198_BITS_149_TO_86_2813_A_ETC___d22816, + csrf_stcc_reg_read__6046_BITS_149_TO_86_2742_A_ETC___d22745, + data___1__h705531, + data___1__h706391, + data__h567678, + data__h613438, + data__h659185, + data__h704999, + data__h705831, + data__h705862, + fcsr_csr__read__h849218, + fflags_csr__read__h849193, + frm_csr__read__h849204, + mask__h1000192, + mask__h999535, + mcause_csr__read__h850885, + mcounteren_csr__read__h850619, + medeleg_csr__read__h850222, + mideleg_csr__read__h850320, + mie_csr__read__h850447, + mip_csr__read__h851124, + mstatus_csr__read__h850061, + n__read__h1014147, n__read__h7908, - newAddrDiff__h1000158, - newAddrDiff__h1000502, - newAddrDiff__h999501, - newAddrDiff__h999845, - offset__h242628, - q___1__h706458, - rVal1__h714520, - rVal2__h714521, - r___1__h706484, - res_data__h568238, - res_data__h568243, - res_data__h613992, - res_data__h613997, - res_data__h659739, - res_data__h659744, - resp_addr__h509111, - rg_tdata1__read__h852226, - robdeqPort_0_deq_data_BITS_95_TO_32__q16, - satp_csr__read__h849916, - scause_csr__read__h849713, - scounteren_csr__read__h849573, - sie_csr__read__h849485, - sip_csr__read__h849853, - sstatus_csr__read__h849415, - thin_address__h999382, - tmpAddr__h242837, - trap_val__h997040, - upd__h1014188, + newAddrDiff__h1000193, + newAddrDiff__h1000537, + newAddrDiff__h999536, + newAddrDiff__h999880, + offset__h242625, + q___1__h706456, + rVal1__h714517, + rVal2__h714518, + r___1__h706482, + res_data__h568236, + res_data__h568241, + res_data__h613990, + res_data__h613995, + res_data__h659737, + res_data__h659742, + resp_addr__h509110, + rg_tdata1__read__h852225, + robdeqPort_0_deq_data_BITS_95_TO_32__q17, + satp_csr__read__h849915, + scause_csr__read__h849712, + scounteren_csr__read__h849572, + sie_csr__read__h849484, + sip_csr__read__h849852, + sstatus_csr__read__h849414, + thin_address__h999417, + tmpAddr__h242834, + trap_val__h997075, + upd__h1014223, upd__h3066, upd__h3676, upd__h7977, - value__h239694, - value__h239858, - value__h240851, - value__h241015, - value__h254475, - value__h254639, - x__h1008496, - x__h1008899, - x__h1009316, - x__h1009719, - x__h1010388, - x__h1031547, - x__h1031950, - x__h1032367, - x__h1032770, - x__h1033437, - x__h127303, - x__h140219, - x__h183481, - x__h202232, - x__h216798, - x__h239712, - x__h239714, - x__h240869, - x__h240871, - x__h242777, - x__h254493, - x__h254495, - x__h714429, - x__h714430, - x__h714431, - x__h854233, - x__h854235, - x__h855226, - x__h855228, - x__h866848, - x__h867396, + value__h239691, + value__h239855, + value__h240848, + value__h241012, + value__h254472, + value__h254636, + x__h1008531, + x__h1008934, + x__h1009351, + x__h1009754, + x__h1010423, + x__h1031581, + x__h1031984, + x__h1032401, + x__h1032804, + x__h1033471, + x__h127302, + x__h140218, + x__h183479, + x__h202230, + x__h216796, + x__h239709, + x__h239711, + x__h240866, + x__h240868, + x__h242774, + x__h254490, + x__h254492, + x__h714426, + x__h714427, + x__h714428, + x__h854232, + x__h854234, + x__h855225, + x__h855227, + x__h866847, + x__h867395, + x__h895986, x__h895988, - x__h895990, + x__h896270, x__h896272, - x__h896274, + x__h896615, x__h896617, - x__h896619, - x__h906534, - x__h907082, - x__h994911, - x__h997587, - x__h997589, + x__h906532, + x__h907080, + x__h994909, + x__h997622, + x__h997624, x_addr__h19883, x_addr__h44252, - x_addr__h535374, - x_quotient__h705747, - x_reg_ifc__read__h849324, - x_remainder__h705748, - y__h1000274, - y__h1016339, - y__h999617, - y_avValue__h710475, - y_avValue__h711108, - y_avValue__h711735, - y_avValue_snd_snd_snd_snd_snd__h1015810, - y_avValue_snd_snd_snd_snd_snd__h1016392, - y_avValue_snd_snd_snd_snd_snd__h1016421; + x_addr__h535372, + x_quotient__h705745, + x_reg_ifc__read__h849323, + x_remainder__h705746, + y__h1000309, + y__h1016374, + y__h999652, + y_avValue__h710472, + y_avValue__h711105, + y_avValue__h711732, + y_avValue_snd_snd_snd_snd_snd__h1015845, + y_avValue_snd_snd_snd_snd_snd__h1016427, + y_avValue_snd_snd_snd_snd_snd__h1016456; wire [62 : 0] IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14033, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14803, - r1__read__h853107, - r1__read__h853511, - r1__read__h854204, - r1__read__h854516, - r1__read__h854749, - r1__read__h854921, - r1__read__h855197, - r1__read__h855508; - wire [61 : 0] r1__read__h853109, - r1__read__h853513, - r1__read__h854206, - r1__read__h854518, - r1__read__h854751, - r1__read__h854897, - r1__read__h854923, - r1__read__h855199, - r1__read__h855510; - wire [60 : 0] r1__read__h854753, - r1__read__h854899, - r1__read__h854925, - r1__read__h855512; - wire [59 : 0] r1__read__h853111, - r1__read__h853515, - r1__read__h854520, - r1__read__h854755, - r1__read__h854927, - r1__read__h855514; + r1__read__h853106, + r1__read__h853510, + r1__read__h854203, + r1__read__h854515, + r1__read__h854748, + r1__read__h854920, + r1__read__h855196, + r1__read__h855507; + wire [61 : 0] r1__read__h853108, + r1__read__h853512, + r1__read__h854205, + r1__read__h854517, + r1__read__h854750, + r1__read__h854896, + r1__read__h854922, + r1__read__h855198, + r1__read__h855509; + wire [60 : 0] r1__read__h854752, + r1__read__h854898, + r1__read__h854924, + r1__read__h855511; + wire [59 : 0] r1__read__h853110, + r1__read__h853514, + r1__read__h854519, + r1__read__h854754, + r1__read__h854926, + r1__read__h855513; wire [58 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5496, IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5538, IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d6974, - r1__read__h853113, - r1__read__h853517, - r1__read__h854509, - r1__read__h854522, - r1__read__h854757, - r1__read__h854929, - r1__read__h855501, - r1__read__h855516; + r1__read__h853112, + r1__read__h853516, + r1__read__h854508, + r1__read__h854521, + r1__read__h854756, + r1__read__h854928, + r1__read__h855500, + r1__read__h855515; wire [57 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d7211, - r1__read__h853115, - r1__read__h853519, - r1__read__h854524, - r1__read__h854759, - r1__read__h854901, - r1__read__h854931, - r1__read__h855518, - y__h422565; + r1__read__h853114, + r1__read__h853518, + r1__read__h854523, + r1__read__h854758, + r1__read__h854900, + r1__read__h854930, + r1__read__h855517, + y__h422564; wire [56 : 0] IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q110, IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q40, IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q75, @@ -4647,195 +4650,195 @@ module mkCore(CLK, _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d10078, _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d11475, _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d8681, - _theResult____h576454, - _theResult____h594093, - _theResult____h622205, - _theResult____h639842, - _theResult____h667952, - _theResult____h685589, - _theResult____h735628, - _theResult____h774481, - _theResult____h813785, - _theResult___snd__h584576, + _theResult____h576452, + _theResult____h594091, + _theResult____h622203, + _theResult____h639840, + _theResult____h667950, + _theResult____h685587, + _theResult____h735625, + _theResult____h774478, + _theResult____h813782, + _theResult___snd__h584574, + _theResult___snd__h584585, _theResult___snd__h584587, - _theResult___snd__h584589, - _theResult___snd__h584599, - _theResult___snd__h584605, - _theResult___snd__h584628, + _theResult___snd__h584597, + _theResult___snd__h584603, + _theResult___snd__h584626, + _theResult___snd__h593170, _theResult___snd__h593172, - _theResult___snd__h593174, - _theResult___snd__h593181, - _theResult___snd__h593187, - _theResult___snd__h593210, - _theResult___snd__h602342, + _theResult___snd__h593179, + _theResult___snd__h593185, + _theResult___snd__h593208, + _theResult___snd__h602340, + _theResult___snd__h602351, _theResult___snd__h602353, - _theResult___snd__h602355, - _theResult___snd__h602365, - _theResult___snd__h602371, - _theResult___snd__h602394, - _theResult___snd__h610962, - _theResult___snd__h610976, - _theResult___snd__h610982, - _theResult___snd__h611000, - _theResult___snd__h630325, + _theResult___snd__h602363, + _theResult___snd__h602369, + _theResult___snd__h602392, + _theResult___snd__h610960, + _theResult___snd__h610974, + _theResult___snd__h610980, + _theResult___snd__h610998, + _theResult___snd__h630323, + _theResult___snd__h630334, _theResult___snd__h630336, - _theResult___snd__h630338, - _theResult___snd__h630348, - _theResult___snd__h630354, - _theResult___snd__h630377, + _theResult___snd__h630346, + _theResult___snd__h630352, + _theResult___snd__h630375, + _theResult___snd__h638919, _theResult___snd__h638921, - _theResult___snd__h638923, - _theResult___snd__h638930, - _theResult___snd__h638936, - _theResult___snd__h638959, - _theResult___snd__h648091, + _theResult___snd__h638928, + _theResult___snd__h638934, + _theResult___snd__h638957, + _theResult___snd__h648089, + _theResult___snd__h648100, _theResult___snd__h648102, - _theResult___snd__h648104, - _theResult___snd__h648114, - _theResult___snd__h648120, - _theResult___snd__h648143, - _theResult___snd__h656711, - _theResult___snd__h656725, - _theResult___snd__h656731, - _theResult___snd__h656749, - _theResult___snd__h676072, + _theResult___snd__h648112, + _theResult___snd__h648118, + _theResult___snd__h648141, + _theResult___snd__h656709, + _theResult___snd__h656723, + _theResult___snd__h656729, + _theResult___snd__h656747, + _theResult___snd__h676070, + _theResult___snd__h676081, _theResult___snd__h676083, - _theResult___snd__h676085, - _theResult___snd__h676095, - _theResult___snd__h676101, - _theResult___snd__h676124, + _theResult___snd__h676093, + _theResult___snd__h676099, + _theResult___snd__h676122, + _theResult___snd__h684666, _theResult___snd__h684668, - _theResult___snd__h684670, - _theResult___snd__h684677, - _theResult___snd__h684683, - _theResult___snd__h684706, - _theResult___snd__h693838, + _theResult___snd__h684675, + _theResult___snd__h684681, + _theResult___snd__h684704, + _theResult___snd__h693836, + _theResult___snd__h693847, _theResult___snd__h693849, - _theResult___snd__h693851, - _theResult___snd__h693861, - _theResult___snd__h693867, - _theResult___snd__h693890, - _theResult___snd__h702458, - _theResult___snd__h702472, - _theResult___snd__h702478, - _theResult___snd__h702496, - _theResult___snd__h734238, - _theResult___snd__h734240, - _theResult___snd__h734247, - _theResult___snd__h734253, - _theResult___snd__h734276, - _theResult___snd__h743875, - _theResult___snd__h743886, - _theResult___snd__h743888, - _theResult___snd__h743898, - _theResult___snd__h743904, - _theResult___snd__h743927, - _theResult___snd__h752643, - _theResult___snd__h752657, - _theResult___snd__h752663, - _theResult___snd__h752681, - _theResult___snd__h773091, - _theResult___snd__h773093, - _theResult___snd__h773100, - _theResult___snd__h773106, - _theResult___snd__h773129, - _theResult___snd__h782728, - _theResult___snd__h782739, - _theResult___snd__h782741, - _theResult___snd__h782751, - _theResult___snd__h782757, - _theResult___snd__h782780, - _theResult___snd__h791496, - _theResult___snd__h791510, - _theResult___snd__h791516, - _theResult___snd__h791534, - _theResult___snd__h812395, - _theResult___snd__h812397, - _theResult___snd__h812404, - _theResult___snd__h812410, - _theResult___snd__h812433, - _theResult___snd__h822032, - _theResult___snd__h822043, - _theResult___snd__h822045, - _theResult___snd__h822055, - _theResult___snd__h822061, - _theResult___snd__h822084, - _theResult___snd__h830800, - _theResult___snd__h830814, - _theResult___snd__h830820, - _theResult___snd__h830838, - r1__read__h854761, - r1__read__h854903, - r1__read__h854933, - r1__read__h855520, - result__h594706, - result__h640455, - result__h686202, - result__h736241, - result__h775094, - result__h814398, - sfd__h568849, - sfd__h614603, - sfd__h660350, - sfd__h715261, - sfd__h754255, - sfd__h793559, - sfdin__h584559, - sfdin__h602325, - sfdin__h630308, - sfdin__h648074, - sfdin__h676055, - sfdin__h693821, - sfdin__h743858, - sfdin__h782711, - sfdin__h822015, - x__h594803, - x__h640552, - x__h686299, - x__h736336, - x__h775189, - x__h814493; + _theResult___snd__h693859, + _theResult___snd__h693865, + _theResult___snd__h693888, + _theResult___snd__h702456, + _theResult___snd__h702470, + _theResult___snd__h702476, + _theResult___snd__h702494, + _theResult___snd__h734235, + _theResult___snd__h734237, + _theResult___snd__h734244, + _theResult___snd__h734250, + _theResult___snd__h734273, + _theResult___snd__h743872, + _theResult___snd__h743883, + _theResult___snd__h743885, + _theResult___snd__h743895, + _theResult___snd__h743901, + _theResult___snd__h743924, + _theResult___snd__h752640, + _theResult___snd__h752654, + _theResult___snd__h752660, + _theResult___snd__h752678, + _theResult___snd__h773088, + _theResult___snd__h773090, + _theResult___snd__h773097, + _theResult___snd__h773103, + _theResult___snd__h773126, + _theResult___snd__h782725, + _theResult___snd__h782736, + _theResult___snd__h782738, + _theResult___snd__h782748, + _theResult___snd__h782754, + _theResult___snd__h782777, + _theResult___snd__h791493, + _theResult___snd__h791507, + _theResult___snd__h791513, + _theResult___snd__h791531, + _theResult___snd__h812392, + _theResult___snd__h812394, + _theResult___snd__h812401, + _theResult___snd__h812407, + _theResult___snd__h812430, + _theResult___snd__h822029, + _theResult___snd__h822040, + _theResult___snd__h822042, + _theResult___snd__h822052, + _theResult___snd__h822058, + _theResult___snd__h822081, + _theResult___snd__h830797, + _theResult___snd__h830811, + _theResult___snd__h830817, + _theResult___snd__h830835, + r1__read__h854760, + r1__read__h854902, + r1__read__h854932, + r1__read__h855519, + result__h594704, + result__h640453, + result__h686200, + result__h736238, + result__h775091, + result__h814395, + sfd__h568847, + sfd__h614601, + sfd__h660348, + sfd__h715258, + sfd__h754252, + sfd__h793556, + sfdin__h584557, + sfdin__h602323, + sfdin__h630306, + sfdin__h648072, + sfdin__h676053, + sfdin__h693819, + sfdin__h743855, + sfdin__h782708, + sfdin__h822012, + x__h594801, + x__h640550, + x__h686297, + x__h736333, + x__h775186, + x__h814490; wire [55 : 0] coreFix_memExe_dispToRegQ_first__686_BIT_102_6_ETC___d3579, - r1__read__h853117, - r1__read__h853521, - r1__read__h854526, - r1__read__h854763, - r1__read__h854935, - r1__read__h855522; + r1__read__h853116, + r1__read__h853520, + r1__read__h854525, + r1__read__h854762, + r1__read__h854934, + r1__read__h855521; wire [54 : 0] IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19394, IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d17260, - r1__read__h853119, - r1__read__h853523, - r1__read__h854528, - r1__read__h854765, - r1__read__h854937, - r1__read__h855524; - wire [53 : 0] r1__read__h854874, - r1__read__h854905, - r1__read__h854939, - r1__read__h855526, - sfd__h734305, - sfd__h743956, - sfd__h752716, - sfd__h773158, - sfd__h782809, - sfd__h791569, - sfd__h812462, - sfd__h822113, - sfd__h830873, - value__h577076, - value__h622825, - value__h668572; + r1__read__h853118, + r1__read__h853522, + r1__read__h854527, + r1__read__h854764, + r1__read__h854936, + r1__read__h855523; + wire [53 : 0] r1__read__h854873, + r1__read__h854904, + r1__read__h854938, + r1__read__h855525, + sfd__h734302, + sfd__h743953, + sfd__h752713, + sfd__h773155, + sfd__h782806, + sfd__h791566, + sfd__h812459, + sfd__h822110, + sfd__h830870, + value__h577074, + value__h622823, + value__h668570; wire [52 : 0] IF_coreFix_memExe_dispToRegQ_first__686_BIT_10_ETC___d3578, INV_coreFix_aluExe_0_regToExeQ_first__9457_BIT_ETC___d19771, INV_coreFix_aluExe_0_regToExeQ_first__9457_BIT_ETC___d19835, INV_coreFix_aluExe_1_regToExeQ_first__7341_BIT_ETC___d17655, INV_coreFix_aluExe_1_regToExeQ_first__7341_BIT_ETC___d17719, - r1__read__h854767, - r1__read__h854876, - r1__read__h854907, - r1__read__h854941, - r1__read__h855528; + r1__read__h854766, + r1__read__h854875, + r1__read__h854906, + r1__read__h854940, + r1__read__h855527; wire [51 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13291, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13293, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14000, @@ -4857,107 +4860,107 @@ module mkCore(CLK, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13323, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14032, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14802, - _theResult___fst_sfd__h719215, + _theResult___fst_sfd__h719212, + _theResult___fst_sfd__h735040, _theResult___fst_sfd__h735043, - _theResult___fst_sfd__h735046, + _theResult___fst_sfd__h744691, _theResult___fst_sfd__h744694, - _theResult___fst_sfd__h744697, + _theResult___fst_sfd__h753475, _theResult___fst_sfd__h753478, - _theResult___fst_sfd__h753481, - _theResult___fst_sfd__h753490, - _theResult___fst_sfd__h753496, - _theResult___fst_sfd__h758068, + _theResult___fst_sfd__h753487, + _theResult___fst_sfd__h753493, + _theResult___fst_sfd__h758065, + _theResult___fst_sfd__h773893, _theResult___fst_sfd__h773896, - _theResult___fst_sfd__h773899, + _theResult___fst_sfd__h783544, _theResult___fst_sfd__h783547, - _theResult___fst_sfd__h783550, + _theResult___fst_sfd__h792328, _theResult___fst_sfd__h792331, - _theResult___fst_sfd__h792334, - _theResult___fst_sfd__h792343, - _theResult___fst_sfd__h792349, - _theResult___fst_sfd__h797372, + _theResult___fst_sfd__h792340, + _theResult___fst_sfd__h792346, + _theResult___fst_sfd__h797369, + _theResult___fst_sfd__h813197, _theResult___fst_sfd__h813200, - _theResult___fst_sfd__h813203, + _theResult___fst_sfd__h822848, _theResult___fst_sfd__h822851, - _theResult___fst_sfd__h822854, + _theResult___fst_sfd__h831632, _theResult___fst_sfd__h831635, - _theResult___fst_sfd__h831638, - _theResult___fst_sfd__h831647, - _theResult___fst_sfd__h831653, - _theResult___sfd__h734943, - _theResult___sfd__h744594, - _theResult___sfd__h753378, - _theResult___sfd__h773796, - _theResult___sfd__h783447, - _theResult___sfd__h792231, - _theResult___sfd__h813100, - _theResult___sfd__h822751, - _theResult___sfd__h831535, - _theResult___snd_fst_sfd__h715215, - _theResult___snd_fst_sfd__h735049, - _theResult___snd_fst_sfd__h753484, - _theResult___snd_fst_sfd__h754209, - _theResult___snd_fst_sfd__h773902, - _theResult___snd_fst_sfd__h792337, - _theResult___snd_fst_sfd__h793513, - _theResult___snd_fst_sfd__h813206, - _theResult___snd_fst_sfd__h831641, - mask__h239974, - mask__h241131, - mask__h254755, - out___1_sfd__h714963, - out___1_sfd__h753957, - out___1_sfd__h793261, - out_sfd__h734946, - out_sfd__h744597, - out_sfd__h753381, - out_sfd__h773799, - out_sfd__h783450, - out_sfd__h792234, - out_sfd__h813103, - out_sfd__h822754, - out_sfd__h831538; - wire [50 : 0] r1__read__h853121, r1__read__h854769; + _theResult___fst_sfd__h831644, + _theResult___fst_sfd__h831650, + _theResult___sfd__h734940, + _theResult___sfd__h744591, + _theResult___sfd__h753375, + _theResult___sfd__h773793, + _theResult___sfd__h783444, + _theResult___sfd__h792228, + _theResult___sfd__h813097, + _theResult___sfd__h822748, + _theResult___sfd__h831532, + _theResult___snd_fst_sfd__h715212, + _theResult___snd_fst_sfd__h735046, + _theResult___snd_fst_sfd__h753481, + _theResult___snd_fst_sfd__h754206, + _theResult___snd_fst_sfd__h773899, + _theResult___snd_fst_sfd__h792334, + _theResult___snd_fst_sfd__h793510, + _theResult___snd_fst_sfd__h813203, + _theResult___snd_fst_sfd__h831638, + mask__h239971, + mask__h241128, + mask__h254752, + out___1_sfd__h714960, + out___1_sfd__h753954, + out___1_sfd__h793258, + out_sfd__h734943, + out_sfd__h744594, + out_sfd__h753378, + out_sfd__h773796, + out_sfd__h783447, + out_sfd__h792231, + out_sfd__h813100, + out_sfd__h822751, + out_sfd__h831535; + wire [50 : 0] r1__read__h853120, r1__read__h854768; wire [49 : 0] coreFix_memExe_dTlbprocResp_BITS_450_TO_401_P_ETC__q7, coreFix_memExe_regToExeQfirst_BITS_218_TO_169_ETC__q5, coreFix_memExe_regToExeQfirst_BITS_381_TO_332_ETC__q3, - highBitsfilter__h1008372, - highBitsfilter__h1008775, - highBitsfilter__h1009192, - highBitsfilter__h1009595, - highBitsfilter__h1010264, - highOffsetBits__h1008373, - highOffsetBits__h1008776, - highOffsetBits__h1009193, - highOffsetBits__h1009596, - highOffsetBits__h1010265, - highOffsetBits__h1031424, - highOffsetBits__h1031827, - highOffsetBits__h1032244, - highOffsetBits__h1032647, - highOffsetBits__h1033314, - highOffsetBits__h242647, - mask__h239865, - mask__h241022, - mask__h254646, - r1__read__h854878, - signBits__h1008370, - signBits__h1031421, - signBits__h242644, - x__h1008400, - x__h1031451, - x__h242674; - wire [48 : 0] r1__read__h853123, r1__read__h854771, r1__read__h854880; - wire [47 : 0] r1__read__h854882; - wire [46 : 0] r1__read__h853125, r1__read__h854773; - wire [45 : 0] r1__read__h853127, r1__read__h854775; - wire [44 : 0] r1__read__h853129, r1__read__h854777; - wire [43 : 0] r1__read__h853131, r1__read__h854779; - wire [42 : 0] r1__read__h854781; - wire [41 : 0] r1__read__h854783; - wire [40 : 0] r1__read__h854785; - wire [38 : 0] IF_csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_c_ETC___d22876; - wire [37 : 0] r1__read__h854884; + highBitsfilter__h1008407, + highBitsfilter__h1008810, + highBitsfilter__h1009227, + highBitsfilter__h1009630, + highBitsfilter__h1010299, + highOffsetBits__h1008408, + highOffsetBits__h1008811, + highOffsetBits__h1009228, + highOffsetBits__h1009631, + highOffsetBits__h1010300, + highOffsetBits__h1031458, + highOffsetBits__h1031861, + highOffsetBits__h1032278, + highOffsetBits__h1032681, + highOffsetBits__h1033348, + highOffsetBits__h242644, + mask__h239862, + mask__h241019, + mask__h254643, + r1__read__h854877, + signBits__h1008405, + signBits__h1031455, + signBits__h242641, + x__h1008435, + x__h1031485, + x__h242671; + wire [48 : 0] r1__read__h853122, r1__read__h854770, r1__read__h854879; + wire [47 : 0] r1__read__h854881; + wire [46 : 0] r1__read__h853124, r1__read__h854772; + wire [45 : 0] r1__read__h853126, r1__read__h854774; + wire [44 : 0] r1__read__h853128, r1__read__h854776; + wire [43 : 0] r1__read__h853130, r1__read__h854778; + wire [42 : 0] r1__read__h854780; + wire [41 : 0] r1__read__h854782; + wire [40 : 0] r1__read__h854784; + wire [38 : 0] IF_csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_c_ETC___d22878; + wire [37 : 0] r1__read__h854883; wire [33 : 0] IF_INV_IF_coreFix_memExe_lsq_firstLd__498_BITS_ETC___d1954, IF_INV_IF_coreFix_memExe_lsq_firstLd__498_BITS_ETC___d2120, IF_INV_coreFix_memExe_lsq_respLd_159_BITS_108__ETC___d2210, @@ -4980,41 +4983,41 @@ module mkCore(CLK, wire [31 : 0] IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q145, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q23, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q22, - coreFix_memExe_regToExeQfirst_BITS_434_TO_403__q17, - data05833_BITS_31_TO_0__q26, - r1__read__h853133, - r1__read__h854787, - x__h568253, - x__h614007, + coreFix_memExe_regToExeQfirst_BITS_434_TO_403__q15, + data05831_BITS_31_TO_0__q26, + r1__read__h853132, + r1__read__h854786, + x__h568251, + x__h614005, x__h65639, - x__h659754, + x__h659752, x_data__h60140; - wire [29 : 0] r1__read__h853135, r1__read__h854789; - wire [27 : 0] r1__read__h854791; - wire [25 : 0] IF_IF_csrf_prv_reg_read__0286_ULE_1_2614_AND_I_ETC___d22894, + wire [29 : 0] r1__read__h853134, r1__read__h854788; + wire [27 : 0] r1__read__h854790; + wire [25 : 0] IF_IF_csrf_prv_reg_read__0286_ULE_1_2614_AND_I_ETC___d22896, IF_coreFix_aluExe_0_exeToFinQ_first__9946_BIT__ETC___d20111, IF_coreFix_aluExe_0_exeToFinQ_first__9946_BIT__ETC___d20142, IF_coreFix_aluExe_1_exeToFinQ_first__7830_BIT__ETC___d17996, IF_coreFix_aluExe_1_exeToFinQ_first__7830_BIT__ETC___d18027, IF_coreFix_memExe_regToExeQ_first__645_BIT_103_ETC___d4017, - IF_csrf_mepcc_reg_read_wget__3540_BIT_34_3552__ETC___d23562, - IF_csrf_rg_dpc_read__6343_BIT_34_4349_THEN_csr_ETC___d24357, - IF_csrf_sepcc_reg_read_wget__3506_BIT_34_3518__ETC___d23528; - wire [24 : 0] sfd__h584657, - sfd__h593239, - sfd__h602423, - sfd__h611035, - sfd__h630406, - sfd__h638988, - sfd__h648172, - sfd__h656784, - sfd__h676153, - sfd__h684735, - sfd__h693919, - sfd__h702531, - value__h719844, - value__h758697, - value__h798001; + IF_csrf_mepcc_reg_read_wget__3542_BIT_34_3554__ETC___d23564, + IF_csrf_rg_dpc_read__6343_BIT_34_4351_THEN_csr_ETC___d24359, + IF_csrf_sepcc_reg_read_wget__3508_BIT_34_3520__ETC___d23530; + wire [24 : 0] sfd__h584655, + sfd__h593237, + sfd__h602421, + sfd__h611033, + sfd__h630404, + sfd__h638986, + sfd__h648170, + sfd__h656782, + sfd__h676151, + sfd__h684733, + sfd__h693917, + sfd__h702529, + value__h719841, + value__h758694, + value__h797998; wire [22 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d10477, IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d10479, IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11874, @@ -5039,68 +5042,68 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9101, IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9145, IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9147, - _theResult___fst_sfd__h585163, - _theResult___fst_sfd__h593745, - _theResult___fst_sfd__h602929, - _theResult___fst_sfd__h611565, - _theResult___fst_sfd__h611574, - _theResult___fst_sfd__h611580, - _theResult___fst_sfd__h630912, - _theResult___fst_sfd__h639494, - _theResult___fst_sfd__h648678, - _theResult___fst_sfd__h657314, - _theResult___fst_sfd__h657323, - _theResult___fst_sfd__h657329, - _theResult___fst_sfd__h676659, - _theResult___fst_sfd__h685241, - _theResult___fst_sfd__h694425, - _theResult___fst_sfd__h703061, - _theResult___fst_sfd__h703070, - _theResult___fst_sfd__h703076, - _theResult___sfd__h585082, - _theResult___sfd__h593664, - _theResult___sfd__h602848, - _theResult___sfd__h611484, - _theResult___sfd__h611586, - _theResult___sfd__h630831, - _theResult___sfd__h639413, - _theResult___sfd__h648597, - _theResult___sfd__h657233, - _theResult___sfd__h657335, - _theResult___sfd__h676578, - _theResult___sfd__h685160, - _theResult___sfd__h694344, - _theResult___sfd__h702980, - _theResult___sfd__h703082, - _theResult___snd_fst_sfd__h568799, - _theResult___snd_fst_sfd__h593748, - _theResult___snd_fst_sfd__h611568, - _theResult___snd_fst_sfd__h614553, - _theResult___snd_fst_sfd__h639497, - _theResult___snd_fst_sfd__h657317, - _theResult___snd_fst_sfd__h660300, - _theResult___snd_fst_sfd__h685244, - _theResult___snd_fst_sfd__h703064, - f1_sfd__h714900, - f2_sfd__h753894, - f3_sfd__h793198, - out_f_sfd__h611863, - out_f_sfd__h657612, - out_f_sfd__h703359, - out_sfd__h585085, - out_sfd__h593667, - out_sfd__h602851, - out_sfd__h611487, - out_sfd__h630834, - out_sfd__h639416, - out_sfd__h648600, - out_sfd__h657236, - out_sfd__h676581, - out_sfd__h685163, - out_sfd__h694347, - out_sfd__h702983; - wire [19 : 0] r1__read__h854726; - wire [18 : 0] INV_commitStage_commitTrap_BITS_217_TO_199__q15, + _theResult___fst_sfd__h585161, + _theResult___fst_sfd__h593743, + _theResult___fst_sfd__h602927, + _theResult___fst_sfd__h611563, + _theResult___fst_sfd__h611572, + _theResult___fst_sfd__h611578, + _theResult___fst_sfd__h630910, + _theResult___fst_sfd__h639492, + _theResult___fst_sfd__h648676, + _theResult___fst_sfd__h657312, + _theResult___fst_sfd__h657321, + _theResult___fst_sfd__h657327, + _theResult___fst_sfd__h676657, + _theResult___fst_sfd__h685239, + _theResult___fst_sfd__h694423, + _theResult___fst_sfd__h703059, + _theResult___fst_sfd__h703068, + _theResult___fst_sfd__h703074, + _theResult___sfd__h585080, + _theResult___sfd__h593662, + _theResult___sfd__h602846, + _theResult___sfd__h611482, + _theResult___sfd__h611584, + _theResult___sfd__h630829, + _theResult___sfd__h639411, + _theResult___sfd__h648595, + _theResult___sfd__h657231, + _theResult___sfd__h657333, + _theResult___sfd__h676576, + _theResult___sfd__h685158, + _theResult___sfd__h694342, + _theResult___sfd__h702978, + _theResult___sfd__h703080, + _theResult___snd_fst_sfd__h568797, + _theResult___snd_fst_sfd__h593746, + _theResult___snd_fst_sfd__h611566, + _theResult___snd_fst_sfd__h614551, + _theResult___snd_fst_sfd__h639495, + _theResult___snd_fst_sfd__h657315, + _theResult___snd_fst_sfd__h660298, + _theResult___snd_fst_sfd__h685242, + _theResult___snd_fst_sfd__h703062, + f1_sfd__h714897, + f2_sfd__h753891, + f3_sfd__h793195, + out_f_sfd__h611861, + out_f_sfd__h657610, + out_f_sfd__h703357, + out_sfd__h585083, + out_sfd__h593665, + out_sfd__h602849, + out_sfd__h611485, + out_sfd__h630832, + out_sfd__h639414, + out_sfd__h648598, + out_sfd__h657234, + out_sfd__h676579, + out_sfd__h685161, + out_sfd__h694345, + out_sfd__h702981; + wire [19 : 0] r1__read__h854725; + wire [18 : 0] INV_commitStage_commitTrap_BITS_217_TO_199__q16, INV_coreFix_aluExe_0_regToExeQfirst_BITS_157__ETC__q14, INV_coreFix_aluExe_0_regToExeQfirst_BITS_286__ETC__q13, INV_coreFix_aluExe_1_regToExeQfirst_BITS_157__ETC__q12, @@ -5108,8 +5111,8 @@ module mkCore(CLK, INV_coreFix_memExe_lsqrespLd_BITS_108_TO_90__q10, INV_coreFix_memExe_respLrScAmoQ_data_0_BITS_10_ETC__q8, INV_mmio_dataRespQ_data_0_BITS_108_TO_90__q9, - INV_x83399_BITS_108_TO_90__q34, - INV_x99251_BITS_108_TO_90__q36; + INV_x83397_BITS_108_TO_90__q34, + INV_x99249_BITS_108_TO_90__q36; wire [17 : 0] IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__840_ETC___d19042, IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__840_ETC___d19043, IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__564_ETC___d16647, @@ -5126,43 +5129,43 @@ module mkCore(CLK, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3559; wire [15 : 0] IF_IF_NOT_csrf_prv_reg_read__0286_EQ_3_0287_02_ETC___d20323, IF_coreFix_memExe_dispToRegQ_first__686_BIT_10_ETC___d3536, - _theResult____h920232, - base__h239699, - base__h240856, - base__h254480, - base__h854220, - base__h855213, - base__h895975, - base__h896259, - base__h896604, - base__h997574, - enabled_ints___1__h920757, - enabled_ints__h920803, - newAddrBits__h1008555, - newAddrBits__h1008958, - newAddrBits__h1009375, - newAddrBits__h1009778, - newAddrBits__h1010447, - newAddrBits__h1031606, - newAddrBits__h1032009, - newAddrBits__h1032426, - newAddrBits__h1032829, - newAddrBits__h1033496, - offset__h239700, - offset__h240857, - offset__h254481, - offset__h854221, - offset__h855214, - offset__h895976, - offset__h896260, - offset__h896605, - offset__h997575, - pend_ints__h920230, - x__h240072, - x__h241229, - x__h254853, - x__h896542, - y__h920769; + _theResult____h920230, + base__h239696, + base__h240853, + base__h254477, + base__h854219, + base__h855212, + base__h895973, + base__h896257, + base__h896602, + base__h997609, + enabled_ints___1__h920755, + enabled_ints__h920801, + newAddrBits__h1008590, + newAddrBits__h1008993, + newAddrBits__h1009410, + newAddrBits__h1009813, + newAddrBits__h1010482, + newAddrBits__h1031640, + newAddrBits__h1032043, + newAddrBits__h1032460, + newAddrBits__h1032863, + newAddrBits__h1033530, + offset__h239697, + offset__h240854, + offset__h254478, + offset__h854220, + offset__h855213, + offset__h895974, + offset__h896258, + offset__h896603, + offset__h997610, + pend_ints__h920228, + x__h240069, + x__h241226, + x__h254850, + x__h896540, + y__h920767; wire [13 : 0] IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__840_ETC___d18828, IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__840_ETC___d18829, IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__564_ETC___d16433, @@ -5184,85 +5187,85 @@ module mkCore(CLK, IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16438, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3068, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3425, - b_base__h127528, - b_base__h140444, - b_base__h183706, - b_base__h202457, - b_base__h217023, - b_base__h867086, - b_base__h867634, - b_base__h906772, - b_base__h907320, - b_base__h995136, + b_base__h127527, + b_base__h140443, + b_base__h183704, + b_base__h202455, + b_base__h217021, + b_base__h867085, + b_base__h867633, + b_base__h906770, + b_base__h907318, + b_base__h995134, checkForException___d20654, checkForException___d21604, - cr_addrBits__h866672, - cr_addrBits__h867220, - cr_addrBits__h906358, - cr_addrBits__h906906, - data_addrBits__h1018718, - data_addrBits__h1019572, - pc_addrBits__h994740, - r1__read_BITS_13_TO_0___h920779, - repBoundBits__h242653, - res_addrBits__h126823, - res_addrBits__h139735, - res_addrBits__h178899, - res_addrBits__h197664, - res_addrBits__h216423, - res_addrBits__h235324, - res_addrBits__h567347, - res_addrBits__h568199, - res_addrBits__h613956, - res_addrBits__h659703, - res_addrBits__h705512, - res_addrBits__h706372, - res_addrBits__h848645, - res_addrBits__h892146, - result_d_addrBits__h1008567, - result_d_addrBits__h1008970, - result_d_addrBits__h1009387, - result_d_addrBits__h1009790, - result_d_addrBits__h1010459, - result_d_addrBits__h1031618, - result_d_addrBits__h1032021, - result_d_addrBits__h1032438, - result_d_addrBits__h1032841, - result_d_addrBits__h1033508, - toBoundsM1__h1008383, - toBoundsM1__h1008786, - toBoundsM1__h1009203, - toBoundsM1__h1009606, - toBoundsM1__h1010275, - toBoundsM1__h242657, - toBounds__h1008382, - toBounds__h1008785, - toBounds__h1009202, - toBounds__h1009605, - toBounds__h1010274, - toBounds__h242656, - x1_avValue_new_pcc_capFat_bounds_baseBits__h1000887, - x__h1000884, - x__h127501, - x__h127521, - x__h140417, - x__h140437, - x__h183679, - x__h183699, - x__h202430, - x__h202450, - x__h216996, - x__h217016, - x__h867059, - x__h867079, - x__h867607, - x__h867627, - x__h906745, - x__h906765, - x__h907293, - x__h907313, - x__h995109, - x__h995129; + cr_addrBits__h866671, + cr_addrBits__h867219, + cr_addrBits__h906356, + cr_addrBits__h906904, + data_addrBits__h1018752, + data_addrBits__h1019606, + pc_addrBits__h994738, + r1__read_BITS_13_TO_0___h920777, + repBoundBits__h242650, + res_addrBits__h126822, + res_addrBits__h139734, + res_addrBits__h178897, + res_addrBits__h197662, + res_addrBits__h216421, + res_addrBits__h235321, + res_addrBits__h567344, + res_addrBits__h568197, + res_addrBits__h613954, + res_addrBits__h659701, + res_addrBits__h705510, + res_addrBits__h706370, + res_addrBits__h848643, + res_addrBits__h892145, + result_d_addrBits__h1008602, + result_d_addrBits__h1009005, + result_d_addrBits__h1009422, + result_d_addrBits__h1009825, + result_d_addrBits__h1010494, + result_d_addrBits__h1031652, + result_d_addrBits__h1032055, + result_d_addrBits__h1032472, + result_d_addrBits__h1032875, + result_d_addrBits__h1033542, + toBoundsM1__h1008418, + toBoundsM1__h1008821, + toBoundsM1__h1009238, + toBoundsM1__h1009641, + toBoundsM1__h1010310, + toBoundsM1__h242654, + toBounds__h1008417, + toBounds__h1008820, + toBounds__h1009237, + toBounds__h1009640, + toBounds__h1010309, + toBounds__h242653, + x1_avValue_new_pcc_capFat_bounds_baseBits__h1000922, + x__h1000919, + x__h127500, + x__h127520, + x__h140416, + x__h140436, + x__h183677, + x__h183697, + x__h202428, + x__h202448, + x__h216994, + x__h217014, + x__h867058, + x__h867078, + x__h867606, + x__h867626, + x__h906743, + x__h906763, + x__h907291, + x__h907311, + x__h995107, + x__h995127; wire [12 : 0] IF_IF_coreFix_memExe_dTlb_procResp__257_BIT_27_ETC___d4757, IF_NOT_renameStage_rg_m_halt_req_0283_BIT_4_02_ETC___d20987, IF_NOT_renameStage_rg_m_halt_req_0283_BIT_4_02_ETC___d20988, @@ -5298,45 +5301,45 @@ module mkCore(CLK, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d10074, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d11471, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d8677, - b_top__h127527, - b_top__h140443, - b_top__h183705, - b_top__h202456, - b_top__h217022, - b_top__h867085, - b_top__h867633, - b_top__h906771, - b_top__h907319, - b_top__h995135, + b_top__h127526, + b_top__h140442, + b_top__h183703, + b_top__h202454, + b_top__h217020, + b_top__h867084, + b_top__h867632, + b_top__h906769, + b_top__h907317, + b_top__h995133, capChecks___d4160, - renaming_spec_bits__h968741, - result__h915810, - result__h915861, - spec_bits__h973792, - topBits__h127430, - topBits__h140346, - topBits__h183608, - topBits__h202359, - topBits__h216925, - topBits__h866987, - topBits__h867535, - topBits__h906673, - topBits__h907221, - topBits__h995038, - w__h915805, - x__h594836, - x__h640585, - x__h686332, - x__h736369, - x__h775222, - x__h814526, - x__h915809, - x__h915860, - y__h915839, - y__h973805, - y_avValue_snd_fst__h963385, - y_avValue_snd_fst__h963427, - y_avValue_snd_fst__h963469; + renaming_spec_bits__h968739, + result__h915808, + result__h915859, + spec_bits__h973790, + topBits__h127429, + topBits__h140345, + topBits__h183606, + topBits__h202357, + topBits__h216923, + topBits__h866986, + topBits__h867534, + topBits__h906671, + topBits__h907219, + topBits__h995036, + w__h915803, + x__h594834, + x__h640583, + x__h686330, + x__h736366, + x__h775219, + x__h814523, + x__h915807, + x__h915858, + y__h915837, + y__h973803, + y_avValue_snd_fst__h963383, + y_avValue_snd_fst__h963425, + y_avValue_snd_fst__h963467; wire [10 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13207, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13209, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13917, @@ -5360,103 +5363,103 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q152, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q169, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q192, - _theResult___exp__h734942, - _theResult___exp__h744593, - _theResult___exp__h753377, - _theResult___exp__h773795, - _theResult___exp__h783446, - _theResult___exp__h792230, - _theResult___exp__h813099, - _theResult___exp__h822750, - _theResult___exp__h831534, - _theResult___fst_exp__h719214, - _theResult___fst_exp__h734278, + _theResult___exp__h734939, + _theResult___exp__h744590, + _theResult___exp__h753374, + _theResult___exp__h773792, + _theResult___exp__h783443, + _theResult___exp__h792227, + _theResult___exp__h813096, + _theResult___exp__h822747, + _theResult___exp__h831531, + _theResult___fst_exp__h719211, + _theResult___fst_exp__h734275, + _theResult___fst_exp__h734281, _theResult___fst_exp__h734284, - _theResult___fst_exp__h734287, + _theResult___fst_exp__h735039, _theResult___fst_exp__h735042, - _theResult___fst_exp__h735045, - _theResult___fst_exp__h743864, - _theResult___fst_exp__h743929, + _theResult___fst_exp__h743861, + _theResult___fst_exp__h743926, + _theResult___fst_exp__h743932, _theResult___fst_exp__h743935, - _theResult___fst_exp__h743938, + _theResult___fst_exp__h744690, _theResult___fst_exp__h744693, - _theResult___fst_exp__h744696, - _theResult___fst_exp__h752649, - _theResult___fst_exp__h752688, + _theResult___fst_exp__h752646, + _theResult___fst_exp__h752685, + _theResult___fst_exp__h752691, _theResult___fst_exp__h752694, - _theResult___fst_exp__h752697, + _theResult___fst_exp__h753474, _theResult___fst_exp__h753477, - _theResult___fst_exp__h753480, + _theResult___fst_exp__h753486, _theResult___fst_exp__h753489, - _theResult___fst_exp__h753492, - _theResult___fst_exp__h758067, - _theResult___fst_exp__h773131, + _theResult___fst_exp__h758064, + _theResult___fst_exp__h773128, + _theResult___fst_exp__h773134, _theResult___fst_exp__h773137, - _theResult___fst_exp__h773140, + _theResult___fst_exp__h773892, _theResult___fst_exp__h773895, - _theResult___fst_exp__h773898, - _theResult___fst_exp__h782717, - _theResult___fst_exp__h782782, + _theResult___fst_exp__h782714, + _theResult___fst_exp__h782779, + _theResult___fst_exp__h782785, _theResult___fst_exp__h782788, - _theResult___fst_exp__h782791, + _theResult___fst_exp__h783543, _theResult___fst_exp__h783546, - _theResult___fst_exp__h783549, - _theResult___fst_exp__h791502, - _theResult___fst_exp__h791541, + _theResult___fst_exp__h791499, + _theResult___fst_exp__h791538, + _theResult___fst_exp__h791544, _theResult___fst_exp__h791547, - _theResult___fst_exp__h791550, + _theResult___fst_exp__h792327, _theResult___fst_exp__h792330, - _theResult___fst_exp__h792333, + _theResult___fst_exp__h792339, _theResult___fst_exp__h792342, - _theResult___fst_exp__h792345, - _theResult___fst_exp__h797371, - _theResult___fst_exp__h812435, + _theResult___fst_exp__h797368, + _theResult___fst_exp__h812432, + _theResult___fst_exp__h812438, _theResult___fst_exp__h812441, - _theResult___fst_exp__h812444, + _theResult___fst_exp__h813196, _theResult___fst_exp__h813199, - _theResult___fst_exp__h813202, - _theResult___fst_exp__h822021, - _theResult___fst_exp__h822086, + _theResult___fst_exp__h822018, + _theResult___fst_exp__h822083, + _theResult___fst_exp__h822089, _theResult___fst_exp__h822092, - _theResult___fst_exp__h822095, + _theResult___fst_exp__h822847, _theResult___fst_exp__h822850, - _theResult___fst_exp__h822853, - _theResult___fst_exp__h830806, - _theResult___fst_exp__h830845, + _theResult___fst_exp__h830803, + _theResult___fst_exp__h830842, + _theResult___fst_exp__h830848, _theResult___fst_exp__h830851, - _theResult___fst_exp__h830854, + _theResult___fst_exp__h831631, _theResult___fst_exp__h831634, - _theResult___fst_exp__h831637, + _theResult___fst_exp__h831643, _theResult___fst_exp__h831646, - _theResult___fst_exp__h831649, - _theResult___snd_fst_exp__h735048, - _theResult___snd_fst_exp__h753483, - _theResult___snd_fst_exp__h773901, - _theResult___snd_fst_exp__h792336, - _theResult___snd_fst_exp__h813205, - _theResult___snd_fst_exp__h831640, + _theResult___snd_fst_exp__h735045, + _theResult___snd_fst_exp__h753480, + _theResult___snd_fst_exp__h773898, + _theResult___snd_fst_exp__h792333, + _theResult___snd_fst_exp__h813202, + _theResult___snd_fst_exp__h831637, coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q83, coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q48, coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q118, - din_inc___2_exp__h753537, - din_inc___2_exp__h753572, - din_inc___2_exp__h753598, - din_inc___2_exp__h792390, - din_inc___2_exp__h792425, - din_inc___2_exp__h792451, - din_inc___2_exp__h831694, - din_inc___2_exp__h831729, - din_inc___2_exp__h831755, - out_exp__h734945, - out_exp__h744596, - out_exp__h753380, - out_exp__h773798, - out_exp__h783449, - out_exp__h792233, - out_exp__h813102, - out_exp__h822753, - out_exp__h831537, - x__h998861; + din_inc___2_exp__h753534, + din_inc___2_exp__h753569, + din_inc___2_exp__h753595, + din_inc___2_exp__h792387, + din_inc___2_exp__h792422, + din_inc___2_exp__h792448, + din_inc___2_exp__h831691, + din_inc___2_exp__h831726, + din_inc___2_exp__h831752, + out_exp__h734942, + out_exp__h744593, + out_exp__h753377, + out_exp__h773795, + out_exp__h783446, + out_exp__h792230, + out_exp__h813099, + out_exp__h822750, + out_exp__h831534, + x__h998896; wire [9 : 0] IF_coreFix_memExe_dispToRegQ_first__686_BIT_10_ETC___d3635; wire [8 : 0] IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d10392, IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d11789, @@ -5512,128 +5515,128 @@ module mkCore(CLK, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q89, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q54, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q124, - _theResult___exp__h585081, - _theResult___exp__h593663, - _theResult___exp__h602847, - _theResult___exp__h611483, - _theResult___exp__h611585, - _theResult___exp__h630830, - _theResult___exp__h639412, - _theResult___exp__h648596, - _theResult___exp__h657232, - _theResult___exp__h657334, - _theResult___exp__h676577, - _theResult___exp__h685159, - _theResult___exp__h694343, - _theResult___exp__h702979, - _theResult___exp__h703081, - _theResult___fst_exp__h584565, - _theResult___fst_exp__h584630, - _theResult___fst_exp__h584636, - _theResult___fst_exp__h584639, - _theResult___fst_exp__h585162, - _theResult___fst_exp__h593212, - _theResult___fst_exp__h593218, - _theResult___fst_exp__h593221, - _theResult___fst_exp__h593744, - _theResult___fst_exp__h602331, - _theResult___fst_exp__h602396, - _theResult___fst_exp__h602402, - _theResult___fst_exp__h602405, - _theResult___fst_exp__h602928, - _theResult___fst_exp__h610968, - _theResult___fst_exp__h611007, - _theResult___fst_exp__h611013, - _theResult___fst_exp__h611016, - _theResult___fst_exp__h611564, - _theResult___fst_exp__h611573, - _theResult___fst_exp__h611576, - _theResult___fst_exp__h630314, - _theResult___fst_exp__h630379, - _theResult___fst_exp__h630385, - _theResult___fst_exp__h630388, - _theResult___fst_exp__h630911, - _theResult___fst_exp__h638961, - _theResult___fst_exp__h638967, - _theResult___fst_exp__h638970, - _theResult___fst_exp__h639493, - _theResult___fst_exp__h648080, - _theResult___fst_exp__h648145, - _theResult___fst_exp__h648151, - _theResult___fst_exp__h648154, - _theResult___fst_exp__h648677, - _theResult___fst_exp__h656717, - _theResult___fst_exp__h656756, - _theResult___fst_exp__h656762, - _theResult___fst_exp__h656765, - _theResult___fst_exp__h657313, - _theResult___fst_exp__h657322, - _theResult___fst_exp__h657325, - _theResult___fst_exp__h676061, - _theResult___fst_exp__h676126, - _theResult___fst_exp__h676132, - _theResult___fst_exp__h676135, - _theResult___fst_exp__h676658, - _theResult___fst_exp__h684708, - _theResult___fst_exp__h684714, - _theResult___fst_exp__h684717, - _theResult___fst_exp__h685240, - _theResult___fst_exp__h693827, - _theResult___fst_exp__h693892, - _theResult___fst_exp__h693898, - _theResult___fst_exp__h693901, - _theResult___fst_exp__h694424, - _theResult___fst_exp__h702464, - _theResult___fst_exp__h702503, - _theResult___fst_exp__h702509, - _theResult___fst_exp__h702512, - _theResult___fst_exp__h703060, - _theResult___fst_exp__h703069, - _theResult___fst_exp__h703072, - _theResult___snd_fst_exp__h593747, - _theResult___snd_fst_exp__h611567, - _theResult___snd_fst_exp__h639496, - _theResult___snd_fst_exp__h657316, - _theResult___snd_fst_exp__h685243, - _theResult___snd_fst_exp__h703063, - din_inc___2_exp__h611598, - din_inc___2_exp__h611622, - din_inc___2_exp__h611652, - din_inc___2_exp__h611676, - din_inc___2_exp__h657347, - din_inc___2_exp__h657371, - din_inc___2_exp__h657401, - din_inc___2_exp__h657425, - din_inc___2_exp__h703094, - din_inc___2_exp__h703118, - din_inc___2_exp__h703148, - din_inc___2_exp__h703172, - f1_exp14899_MINUS_127__q148, - f1_exp__h714899, - f2_exp53893_MINUS_127__q188, - f2_exp__h753893, - f3_exp93197_MINUS_127__q165, - f3_exp__h793197, - out_exp__h585084, - out_exp__h593666, - out_exp__h602850, - out_exp__h611486, - out_exp__h630833, - out_exp__h639415, - out_exp__h648599, - out_exp__h657235, - out_exp__h676580, - out_exp__h685162, - out_exp__h694346, - out_exp__h702982, - out_f_exp__h611862, - out_f_exp__h657611, - out_f_exp__h703358, - x__h853092; + _theResult___exp__h585079, + _theResult___exp__h593661, + _theResult___exp__h602845, + _theResult___exp__h611481, + _theResult___exp__h611583, + _theResult___exp__h630828, + _theResult___exp__h639410, + _theResult___exp__h648594, + _theResult___exp__h657230, + _theResult___exp__h657332, + _theResult___exp__h676575, + _theResult___exp__h685157, + _theResult___exp__h694341, + _theResult___exp__h702977, + _theResult___exp__h703079, + _theResult___fst_exp__h584563, + _theResult___fst_exp__h584628, + _theResult___fst_exp__h584634, + _theResult___fst_exp__h584637, + _theResult___fst_exp__h585160, + _theResult___fst_exp__h593210, + _theResult___fst_exp__h593216, + _theResult___fst_exp__h593219, + _theResult___fst_exp__h593742, + _theResult___fst_exp__h602329, + _theResult___fst_exp__h602394, + _theResult___fst_exp__h602400, + _theResult___fst_exp__h602403, + _theResult___fst_exp__h602926, + _theResult___fst_exp__h610966, + _theResult___fst_exp__h611005, + _theResult___fst_exp__h611011, + _theResult___fst_exp__h611014, + _theResult___fst_exp__h611562, + _theResult___fst_exp__h611571, + _theResult___fst_exp__h611574, + _theResult___fst_exp__h630312, + _theResult___fst_exp__h630377, + _theResult___fst_exp__h630383, + _theResult___fst_exp__h630386, + _theResult___fst_exp__h630909, + _theResult___fst_exp__h638959, + _theResult___fst_exp__h638965, + _theResult___fst_exp__h638968, + _theResult___fst_exp__h639491, + _theResult___fst_exp__h648078, + _theResult___fst_exp__h648143, + _theResult___fst_exp__h648149, + _theResult___fst_exp__h648152, + _theResult___fst_exp__h648675, + _theResult___fst_exp__h656715, + _theResult___fst_exp__h656754, + _theResult___fst_exp__h656760, + _theResult___fst_exp__h656763, + _theResult___fst_exp__h657311, + _theResult___fst_exp__h657320, + _theResult___fst_exp__h657323, + _theResult___fst_exp__h676059, + _theResult___fst_exp__h676124, + _theResult___fst_exp__h676130, + _theResult___fst_exp__h676133, + _theResult___fst_exp__h676656, + _theResult___fst_exp__h684706, + _theResult___fst_exp__h684712, + _theResult___fst_exp__h684715, + _theResult___fst_exp__h685238, + _theResult___fst_exp__h693825, + _theResult___fst_exp__h693890, + _theResult___fst_exp__h693896, + _theResult___fst_exp__h693899, + _theResult___fst_exp__h694422, + _theResult___fst_exp__h702462, + _theResult___fst_exp__h702501, + _theResult___fst_exp__h702507, + _theResult___fst_exp__h702510, + _theResult___fst_exp__h703058, + _theResult___fst_exp__h703067, + _theResult___fst_exp__h703070, + _theResult___snd_fst_exp__h593745, + _theResult___snd_fst_exp__h611565, + _theResult___snd_fst_exp__h639494, + _theResult___snd_fst_exp__h657314, + _theResult___snd_fst_exp__h685241, + _theResult___snd_fst_exp__h703061, + din_inc___2_exp__h611596, + din_inc___2_exp__h611620, + din_inc___2_exp__h611650, + din_inc___2_exp__h611674, + din_inc___2_exp__h657345, + din_inc___2_exp__h657369, + din_inc___2_exp__h657399, + din_inc___2_exp__h657423, + din_inc___2_exp__h703092, + din_inc___2_exp__h703116, + din_inc___2_exp__h703146, + din_inc___2_exp__h703170, + f1_exp14896_MINUS_127__q148, + f1_exp__h714896, + f2_exp53890_MINUS_127__q188, + f2_exp__h753890, + f3_exp93194_MINUS_127__q165, + f3_exp__h793194, + out_exp__h585082, + out_exp__h593664, + out_exp__h602848, + out_exp__h611484, + out_exp__h630831, + out_exp__h639413, + out_exp__h648597, + out_exp__h657233, + out_exp__h676578, + out_exp__h685160, + out_exp__h694344, + out_exp__h702980, + out_f_exp__h611860, + out_f_exp__h657609, + out_f_exp__h703356, + x__h853091; wire [6 : 0] NOT_coreFix_aluExe_0_dispToRegQ_first__8383_BI_ETC___d19436, NOT_coreFix_aluExe_1_dispToRegQ_first__5620_BI_ETC___d17320, - x__h244678, - x__h999587; + x__h244675, + x__h999622; wire [5 : 0] IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d11164, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d8370, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d9767, @@ -5659,22 +5662,22 @@ module mkCore(CLK, IF_fetchStage_pipelines_0_first__0256_BITS_265_ETC___d22051, IF_fetchStage_pipelines_1_first__0265_BITS_265_ETC___d22194, NOT_coreFix_memExe_dispToRegQ_first__686_BIT_1_ETC___d3634, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d24474, + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d24476, fetchStage_pipelines_0_first__0256_BIT_167_059_ETC___d20616, fetchStage_pipelines_1_first__0265_BIT_167_155_ETC___d21577, - x__h1000218, - x__h1000905, - x__h127341, - x__h140257, - x__h183519, - x__h202270, - x__h216836, - x__h866886, - x__h867434, - x__h906572, - x__h907120, - x__h994949, - x__h999561; + x__h1000253, + x__h1000940, + x__h127340, + x__h140256, + x__h183517, + x__h202268, + x__h216834, + x__h866885, + x__h867433, + x__h906570, + x__h907118, + x__h994947, + x__h999596; wire [4 : 0] IF_IF_coreFix_aluExe_0_exeToFinQ_first__9946_B_ETC___d20090, IF_IF_coreFix_aluExe_0_exeToFinQ_first__9946_B_ETC___d20091, IF_IF_coreFix_aluExe_1_exeToFinQ_first__7830_B_ETC___d17975, @@ -5701,7 +5704,7 @@ module mkCore(CLK, IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17739, IF_NOT_fetchStage_pipelines_0_first__0256_BITS_ETC___d22088, IF_NOT_fetchStage_pipelines_1_first__0265_BITS_ETC___d22242, - IF_rob_deqPort_0_canDeq__3598_THEN_IF_NOT_rob__ETC___d23825, + IF_rob_deqPort_0_canDeq__3600_THEN_IF_NOT_rob__ETC___d23827, _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d10694, _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d12091, _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d9297, @@ -5717,51 +5720,51 @@ module mkCore(CLK, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d10706, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d12103, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d9309, - cause_code__h996858, + cause_code__h996893, coreFix_memExe_regToExeQ_first__645_BITS_383_T_ETC___d4123, csrf_ddc_reg_read__051_BITS_85_TO_83_145_ULT_c_ETC___d4156, - fflags__h1016316, - r1__read__h855837, - res_fflags__h568239, - res_fflags__h613993, - res_fflags__h659740, + fflags__h1016351, + r1__read__h855836, + res_fflags__h568237, + res_fflags__h613991, + res_fflags__h659738, rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19181, rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16786, - x__h148991, - x__h152125, - x__h249478, - x__h249490, - x__h249502, - x__h249514, - x__h249526, - x__h249538, - x__h249550, - x__h249562, - x__h249574, - x__h249586, - x__h249598, - x__h249610, - x__h249622, - x__h249634, - x__h249646, - y__h249479, - y__h249491, - y__h249503, - y__h249515, - y__h249527, - y__h249539, - y__h249551, - y__h249563, - y__h249575, - y__h249587, - y__h249599, - y__h249611, - y__h249623, - y__h249635, - y__h249647, - y_avValue_snd_fst__h1015794, - y_avValue_snd_fst__h1016376, - y_avValue_snd_fst__h1016405; + x__h148990, + x__h152124, + x__h249475, + x__h249487, + x__h249499, + x__h249511, + x__h249523, + x__h249535, + x__h249547, + x__h249559, + x__h249571, + x__h249583, + x__h249595, + x__h249607, + x__h249619, + x__h249631, + x__h249643, + y__h249476, + y__h249488, + y__h249500, + y__h249512, + y__h249524, + y__h249536, + y__h249548, + y__h249560, + y__h249572, + y__h249584, + y__h249596, + y__h249608, + y__h249620, + y__h249632, + y__h249644, + y_avValue_snd_fst__h1015829, + y_avValue_snd_fst__h1016411, + y_avValue_snd_fst__h1016440; wire [3 : 0] IF_IF_coreFix_aluExe_0_dispToRegQ_first__8383__ETC___d19433, IF_IF_coreFix_aluExe_1_dispToRegQ_first__5620__ETC___d17317, IF_IF_renameStage_rg_m_halt_req_0283_BIT_4_028_ETC___d20977, @@ -5806,7 +5809,7 @@ module mkCore(CLK, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3390, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3433, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3632, - vm_mode_reg__read__h854732; + vm_mode_reg__read__h854731; wire [2 : 0] IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__840_ETC___d19088, IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__840_ETC___d19089, IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__564_ETC___d16693, @@ -5822,58 +5825,58 @@ module mkCore(CLK, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3327, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3589, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d7096, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d24407, - _theResult_____2__h515368, - dcsr_cause__h994364, - next_deqP___1__h515613, - repBound__h237318, - repBound__h239003, - repBound__h248218, - repBound__h248743, - repBound__h854076, - repBound__h854398, - repBound__h855069, - repBound__h855390, - repBound__h855899, - repBound__h857577, - repBound__h860539, - repBound__h860557, - repBound__h867140, - repBound__h867688, - repBound__h898286, - repBound__h900613, - repBound__h900631, - repBound__h906826, - repBound__h907374, - repBound__h997599, - tb__h867137, - tb__h867685, - tb__h906823, - tb__h907371, - tmp_expBotHalf__h127296, - tmp_expBotHalf__h140212, - tmp_expBotHalf__h183474, - tmp_expBotHalf__h202225, - tmp_expBotHalf__h216791, - tmp_expBotHalf__h866840, - tmp_expBotHalf__h867388, - tmp_expBotHalf__h906526, - tmp_expBotHalf__h907074, - tmp_expBotHalf__h994904, - tmp_expTopHalf__h127294, - tmp_expTopHalf__h140210, - tmp_expTopHalf__h183472, - tmp_expTopHalf__h202223, - tmp_expTopHalf__h216789, - tmp_expTopHalf__h866838, - tmp_expTopHalf__h867386, - tmp_expTopHalf__h906524, - tmp_expTopHalf__h907072, - tmp_expTopHalf__h994902, - v__h514824, - v__h515019, - x__h521675, - x_decodeInfo_frm__h926248; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d24409, + _theResult_____2__h515366, + dcsr_cause__h994362, + next_deqP___1__h515611, + repBound__h237315, + repBound__h239000, + repBound__h248215, + repBound__h248740, + repBound__h854075, + repBound__h854397, + repBound__h855068, + repBound__h855389, + repBound__h855898, + repBound__h857576, + repBound__h860538, + repBound__h860556, + repBound__h867139, + repBound__h867687, + repBound__h898284, + repBound__h900611, + repBound__h900629, + repBound__h906824, + repBound__h907372, + repBound__h997634, + tb__h867136, + tb__h867684, + tb__h906821, + tb__h907369, + tmp_expBotHalf__h127295, + tmp_expBotHalf__h140211, + tmp_expBotHalf__h183472, + tmp_expBotHalf__h202223, + tmp_expBotHalf__h216789, + tmp_expBotHalf__h866839, + tmp_expBotHalf__h867387, + tmp_expBotHalf__h906524, + tmp_expBotHalf__h907072, + tmp_expBotHalf__h994902, + tmp_expTopHalf__h127293, + tmp_expTopHalf__h140209, + tmp_expTopHalf__h183470, + tmp_expTopHalf__h202221, + tmp_expTopHalf__h216787, + tmp_expTopHalf__h866837, + tmp_expTopHalf__h867385, + tmp_expTopHalf__h906522, + tmp_expTopHalf__h907070, + tmp_expTopHalf__h994900, + v__h514822, + v__h515017, + x__h521673, + x_decodeInfo_frm__h926246; wire [1 : 0] IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__840_ETC___d19029, IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__840_ETC___d19030, IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__564_ETC___d16634, @@ -5884,113 +5887,113 @@ module mkCore(CLK, IF_NOT_coreFix_memExe_bypassWire_0_whas__704_7_ETC___d3547, IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17182, IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17176, - IF_rob_deqPort_0_canDeq__3598_THEN_IF_NOT_rob__ETC___d23847, + IF_rob_deqPort_0_canDeq__3600_THEN_IF_NOT_rob__ETC___d23849, IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d19034, IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16639, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3269, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3551, - IF_sfdin02325_BIT_33_THEN_2_ELSE_0__q51, - IF_sfdin22015_BIT_4_THEN_2_ELSE_0__q168, - IF_sfdin30308_BIT_33_THEN_2_ELSE_0__q76, - IF_sfdin43858_BIT_4_THEN_2_ELSE_0__q151, - IF_sfdin48074_BIT_33_THEN_2_ELSE_0__q86, - IF_sfdin76055_BIT_33_THEN_2_ELSE_0__q111, - IF_sfdin82711_BIT_4_THEN_2_ELSE_0__q191, - IF_sfdin84559_BIT_33_THEN_2_ELSE_0__q41, - IF_sfdin93821_BIT_33_THEN_2_ELSE_0__q121, - IF_theResult___snd02458_BIT_33_THEN_2_ELSE_0__q126, - IF_theResult___snd10962_BIT_33_THEN_2_ELSE_0__q56, - IF_theResult___snd12395_BIT_4_THEN_2_ELSE_0__q164, - IF_theResult___snd30800_BIT_4_THEN_2_ELSE_0__q171, - IF_theResult___snd34238_BIT_4_THEN_2_ELSE_0__q147, - IF_theResult___snd38921_BIT_33_THEN_2_ELSE_0__q78, - IF_theResult___snd52643_BIT_4_THEN_2_ELSE_0__q154, - IF_theResult___snd56711_BIT_33_THEN_2_ELSE_0__q91, - IF_theResult___snd73091_BIT_4_THEN_2_ELSE_0__q187, - IF_theResult___snd84668_BIT_33_THEN_2_ELSE_0__q113, - IF_theResult___snd91496_BIT_4_THEN_2_ELSE_0__q194, - IF_theResult___snd93172_BIT_33_THEN_2_ELSE_0__q43, - carry_out__h127432, - carry_out__h140348, - carry_out__h183610, - carry_out__h202361, - carry_out__h216927, - carry_out__h866989, - carry_out__h867537, - carry_out__h906675, - carry_out__h907223, - carry_out__h995040, + IF_sfdin02323_BIT_33_THEN_2_ELSE_0__q51, + IF_sfdin22012_BIT_4_THEN_2_ELSE_0__q168, + IF_sfdin30306_BIT_33_THEN_2_ELSE_0__q76, + IF_sfdin43855_BIT_4_THEN_2_ELSE_0__q151, + IF_sfdin48072_BIT_33_THEN_2_ELSE_0__q86, + IF_sfdin76053_BIT_33_THEN_2_ELSE_0__q111, + IF_sfdin82708_BIT_4_THEN_2_ELSE_0__q191, + IF_sfdin84557_BIT_33_THEN_2_ELSE_0__q41, + IF_sfdin93819_BIT_33_THEN_2_ELSE_0__q121, + IF_theResult___snd02456_BIT_33_THEN_2_ELSE_0__q126, + IF_theResult___snd10960_BIT_33_THEN_2_ELSE_0__q56, + IF_theResult___snd12392_BIT_4_THEN_2_ELSE_0__q164, + IF_theResult___snd30797_BIT_4_THEN_2_ELSE_0__q171, + IF_theResult___snd34235_BIT_4_THEN_2_ELSE_0__q147, + IF_theResult___snd38919_BIT_33_THEN_2_ELSE_0__q78, + IF_theResult___snd52640_BIT_4_THEN_2_ELSE_0__q154, + IF_theResult___snd56709_BIT_33_THEN_2_ELSE_0__q91, + IF_theResult___snd73088_BIT_4_THEN_2_ELSE_0__q187, + IF_theResult___snd84666_BIT_33_THEN_2_ELSE_0__q113, + IF_theResult___snd91493_BIT_4_THEN_2_ELSE_0__q194, + IF_theResult___snd93170_BIT_33_THEN_2_ELSE_0__q43, + carry_out__h127431, + carry_out__h140347, + carry_out__h183608, + carry_out__h202359, + carry_out__h216925, + carry_out__h866988, + carry_out__h867536, + carry_out__h906673, + carry_out__h907221, + carry_out__h995038, coreFix_memExe_dTlbprocResp_BITS_292_TO_291__q6, coreFix_memExe_regToExeQfirst_BITS_223_TO_222__q2, coreFix_memExe_regToExeQfirst_BITS_60_TO_59__q4, - cr_reserved__h866675, - cr_reserved__h867223, - cr_reserved__h906361, - cr_reserved__h906909, - guard__h576464, - guard__h585173, - guard__h594103, - guard__h602939, - guard__h622215, - guard__h630922, - guard__h639852, - guard__h648688, - guard__h667962, - guard__h676669, - guard__h685599, - guard__h694435, - guard__h726326, - guard__h735638, - guard__h744707, - guard__h765179, - guard__h774491, - guard__h783560, - guard__h804483, - guard__h813795, - guard__h822864, - impliedTopBits__h127434, - impliedTopBits__h140350, - impliedTopBits__h183612, - impliedTopBits__h202363, - impliedTopBits__h216929, - impliedTopBits__h866991, - impliedTopBits__h867539, - impliedTopBits__h906677, - impliedTopBits__h907225, - impliedTopBits__h995042, - len_correction__h127433, - len_correction__h140349, - len_correction__h183611, - len_correction__h202362, - len_correction__h216928, - len_correction__h866990, - len_correction__h867538, - len_correction__h906676, - len_correction__h907224, - len_correction__h995041, - prv__h1017409, - prv__h1017453, - r1__read_BITS_13_TO_12___h926454, - sbIdx__h152016, - v__h836642, - v__h836652, - v__h837287, - wordIdx__h263233, - x__h1012282, - x__h1016564, - x__h127518, - x__h140434, - x__h183696, - x__h202447, - x__h217013, - x__h867076, - x__h867624, - x__h906762, - x__h907310, - x__h995126, - y_avValue_snd_snd_snd_fst__h1015804, - y_avValue_snd_snd_snd_fst__h1016386, - y_avValue_snd_snd_snd_fst__h1016415; + cr_reserved__h866674, + cr_reserved__h867222, + cr_reserved__h906359, + cr_reserved__h906907, + guard__h576462, + guard__h585171, + guard__h594101, + guard__h602937, + guard__h622213, + guard__h630920, + guard__h639850, + guard__h648686, + guard__h667960, + guard__h676667, + guard__h685597, + guard__h694433, + guard__h726323, + guard__h735635, + guard__h744704, + guard__h765176, + guard__h774488, + guard__h783557, + guard__h804480, + guard__h813792, + guard__h822861, + impliedTopBits__h127433, + impliedTopBits__h140349, + impliedTopBits__h183610, + impliedTopBits__h202361, + impliedTopBits__h216927, + impliedTopBits__h866990, + impliedTopBits__h867538, + impliedTopBits__h906675, + impliedTopBits__h907223, + impliedTopBits__h995040, + len_correction__h127432, + len_correction__h140348, + len_correction__h183609, + len_correction__h202360, + len_correction__h216926, + len_correction__h866989, + len_correction__h867537, + len_correction__h906674, + len_correction__h907222, + len_correction__h995039, + prv__h1017444, + prv__h1017488, + r1__read_BITS_13_TO_12___h926452, + sbIdx__h152015, + v__h836639, + v__h836649, + v__h837284, + wordIdx__h263231, + x__h1012317, + x__h1016599, + x__h127517, + x__h140433, + x__h183694, + x__h202445, + x__h217011, + x__h867075, + x__h867623, + x__h906760, + x__h907308, + x__h995124, + y_avValue_snd_snd_snd_fst__h1015839, + y_avValue_snd_snd_snd_fst__h1016421, + y_avValue_snd_snd_snd_fst__h1016450; wire IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d10589, IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d10639, IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d11986, @@ -6062,13 +6065,13 @@ module mkCore(CLK, IF_IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_w_ETC___d7806, IF_IF_fetchStage_pipelines_0_first__0256_BITS__ETC___d21231, IF_IF_fetchStage_pipelines_0_first__0256_BITS__ETC___d21876, - IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23130, - IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23174, - IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23269, - IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23311, - IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23424, - IF_INV_commitStage_commitTrap_2268_BITS_217_TO_ETC___d22661, - IF_INV_commitStage_commitTrap_2268_BITS_217_TO_ETC___d22663, + IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23132, + IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23176, + IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23271, + IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23313, + IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23426, + IF_INV_commitStage_commitTrap_2268_BITS_217_TO_ETC___d22662, + IF_INV_commitStage_commitTrap_2268_BITS_217_TO_ETC___d22664, IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19778, IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19779, IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19781, @@ -6261,7 +6264,7 @@ module mkCore(CLK, IF_NOT_fetchStage_pipelines_0_canDeq__0254_025_ETC___d21829, IF_NOT_fetchStage_pipelines_1_first__0265_BITS_ETC___d21741, IF_NOT_fetchStage_pipelines_1_first__0265_BITS_ETC___d21828, - IF_NOT_rob_deqPort_1_deq_data__3605_BIT_25_360_ETC___d23838, + IF_NOT_rob_deqPort_1_deq_data__3607_BIT_25_360_ETC___d23840, IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d13138, IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d13853, IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d14087, @@ -6380,11 +6383,11 @@ module mkCore(CLK, IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17132, IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17160, IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17227, - IF_csrf_mtcc_reg_read__6198_BITS_149_TO_86_281_ETC___d22840, - IF_csrf_mtcc_reg_read__6198_BITS_149_TO_86_281_ETC___d22843, - IF_csrf_mtcc_reg_read__6198_BITS_149_TO_86_281_ETC___d22865, - IF_csrf_mtcc_reg_read__6198_BITS_149_TO_86_281_ETC___d22868, - IF_csrf_mtcc_reg_read__6198_BIT_86_2807_AND_NO_ETC___d22871, + IF_csrf_mtcc_reg_read__6198_BITS_149_TO_86_281_ETC___d22842, + IF_csrf_mtcc_reg_read__6198_BITS_149_TO_86_281_ETC___d22845, + IF_csrf_mtcc_reg_read__6198_BITS_149_TO_86_281_ETC___d22867, + IF_csrf_mtcc_reg_read__6198_BITS_149_TO_86_281_ETC___d22870, + IF_csrf_mtcc_reg_read__6198_BIT_86_2809_AND_NO_ETC___d22873, IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16087, IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16089, IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16810, @@ -6402,16 +6405,16 @@ module mkCore(CLK, IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17126, IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17154, IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17221, - IF_csrf_stcc_reg_read__6046_BITS_149_TO_86_274_ETC___d22771, - IF_csrf_stcc_reg_read__6046_BITS_149_TO_86_274_ETC___d22774, - IF_csrf_stcc_reg_read__6046_BITS_149_TO_86_274_ETC___d22796, - IF_csrf_stcc_reg_read__6046_BITS_149_TO_86_274_ETC___d22799, - IF_csrf_stcc_reg_read__6046_BIT_86_2736_AND_NO_ETC___d22802, - IF_f_csr_reqs_first__3969_BIT_63_4123_THEN_NOT_ETC___d24133, - IF_f_csr_reqs_first__3969_BIT_63_4123_THEN_NOT_ETC___d24155, - IF_f_csr_reqs_first__3969_BIT_63_4123_THEN_NOT_ETC___d24213, - IF_f_csr_reqs_first__3969_BIT_63_4123_THEN_NOT_ETC___d24233, - IF_f_csr_reqs_first__3969_BIT_63_4123_THEN_NOT_ETC___d24304, + IF_csrf_stcc_reg_read__6046_BITS_149_TO_86_274_ETC___d22773, + IF_csrf_stcc_reg_read__6046_BITS_149_TO_86_274_ETC___d22776, + IF_csrf_stcc_reg_read__6046_BITS_149_TO_86_274_ETC___d22798, + IF_csrf_stcc_reg_read__6046_BITS_149_TO_86_274_ETC___d22801, + IF_csrf_stcc_reg_read__6046_BIT_86_2738_AND_NO_ETC___d22804, + IF_f_csr_reqs_first__3971_BIT_63_4125_THEN_NOT_ETC___d24135, + IF_f_csr_reqs_first__3971_BIT_63_4125_THEN_NOT_ETC___d24157, + IF_f_csr_reqs_first__3971_BIT_63_4125_THEN_NOT_ETC___d24215, + IF_f_csr_reqs_first__3971_BIT_63_4125_THEN_NOT_ETC___d24235, + IF_f_csr_reqs_first__3971_BIT_63_4125_THEN_NOT_ETC___d24306, IF_fetchStage_RDY_pipelines_0_first__0253_AND__ETC___d21186, IF_fetchStage_RDY_pipelines_1_first__0264_AND__ETC___d21743, IF_fetchStage_RDY_pipelines_1_first__0264_AND__ETC___d21818, @@ -6438,12 +6441,12 @@ module mkCore(CLK, IF_mmio_dataRespQ_enqReq_lat_1_whas__73_THEN_m_ETC___d182, IF_mmio_pRqQ_enqReq_lat_1_whas__56_THEN_mmio_p_ETC___d565, IF_mmio_pRsQ_enqReq_lat_1_whas__15_THEN_mmio_p_ETC___d424, - IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23133, - IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23179, - IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23272, - IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23316, - IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23430, - IF_rob_deqPort_1_canDeq__3602_THEN_IF_NOT_rob__ETC___d23839, + IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23135, + IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23181, + IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23274, + IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23318, + IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23432, + IF_rob_deqPort_1_canDeq__3604_THEN_IF_NOT_rob__ETC___d23841, IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18759, IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18859, IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18872, @@ -6525,7 +6528,7 @@ module mkCore(CLK, NOT_IF_IF_NOT_csrf_prv_reg_read__0286_EQ_3_028_ETC___d21068, NOT_IF_IF_NOT_csrf_prv_reg_read__0286_EQ_3_028_ETC___d21173, NOT_IF_IF_NOT_csrf_prv_reg_read__0286_EQ_3_028_ETC___d21631, - NOT_IF_NOT_rob_deqPort_0_canDeq__3598_3599_OR__ETC___d23844, + NOT_IF_NOT_rob_deqPort_0_canDeq__3600_3601_OR__ETC___d23846, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d12707, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d13437, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d14207, @@ -6539,11 +6542,11 @@ module mkCore(CLK, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15115, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15144, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15157, - NOT_IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN__ETC___d23314, - NOT_IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN__ETC___d23177, + NOT_IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN__ETC___d23316, + NOT_IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN__ETC___d23179, NOT_commitStage_commitTrap_2268_BITS_44_TO_43__ETC___d22534, NOT_commitStage_commitTrap_2268_BITS_44_TO_43__ETC___d22535, - NOT_commitStage_rg_run_state_2266_2267_AND_NOT_ETC___d23033, + NOT_commitStage_rg_run_state_2266_2267_AND_NOT_ETC___d23035, NOT_coreFix_aluExe_0_bypassWire_0_whas__8403_8_ETC___d18430, NOT_coreFix_aluExe_0_bypassWire_0_whas__8403_8_ETC___d18458, NOT_coreFix_aluExe_0_exeToFinQ_first__9946_BIT_ETC___d19993, @@ -6589,10 +6592,10 @@ module mkCore(CLK, NOT_csrf_fs_reg_read__6010_EQ_0_0640_0641_OR_N_ETC___d21066, NOT_csrf_fs_reg_read__6010_EQ_0_0640_0641_OR_N_ETC___d21171, NOT_csrf_fs_reg_read__6010_EQ_0_0640_0641_OR_N_ETC___d21629, - NOT_csrf_mtcc_reg_read__6198_BITS_33_TO_28_621_ETC___d22810, - NOT_csrf_prv_reg_read__0286_ULE_1_2614_2729_OR_ETC___d22734, - NOT_csrf_rg_dpc_read__6343_BITS_33_TO_28_6360__ETC___d23427, - NOT_csrf_stcc_reg_read__6046_BITS_33_TO_28_606_ETC___d22739, + NOT_csrf_mtcc_reg_read__6198_BITS_33_TO_28_621_ETC___d22812, + NOT_csrf_prv_reg_read__0286_ULE_1_2614_2730_OR_ETC___d22736, + NOT_csrf_rg_dpc_read__6343_BITS_33_TO_28_6360__ETC___d23429, + NOT_csrf_stcc_reg_read__6046_BITS_33_TO_28_606_ETC___d22741, NOT_fetchStage_pipelines_0_canDeq__0254_0255_O_ETC___d21283, NOT_fetchStage_pipelines_0_canDeq__0254_0255_O_ETC___d21723, NOT_fetchStage_pipelines_0_canDeq__0254_0255_O_ETC___d21792, @@ -6631,10 +6634,10 @@ module mkCore(CLK, NOT_renameStage_rg_m_halt_req_0283_BIT_4_0284__ETC___d21178, NOT_renameStage_rg_m_halt_req_0283_BIT_4_0284__ETC___d21789, NOT_renameStage_rg_m_halt_req_0283_BIT_4_0284__ETC___d21809, - NOT_rob_deqPort_0_canDeq__3598_3599_OR_rob_RDY_ETC___d23639, - NOT_rob_deqPort_0_canDeq__3598_3599_OR_rob_deq_ETC___d23818, - NOT_rob_deqPort_0_deq_data__2261_BITS_469_TO_4_ETC___d23022, - NOT_rob_deqPort_1_deq_data__3605_BIT_25_3606_3_ETC___d23636, + NOT_rob_deqPort_0_canDeq__3600_3601_OR_regRena_ETC___d23641, + NOT_rob_deqPort_0_canDeq__3600_3601_OR_rob_deq_ETC___d23820, + NOT_rob_deqPort_0_deq_data__2261_BITS_469_TO_4_ETC___d23024, + NOT_rob_deqPort_1_deq_data__3607_BIT_25_3608_3_ETC___d23638, NOT_specTagManager_canClaim__1149_1248_OR_NOT__ETC___d21921, NOT_specTagManager_canClaim__1149_1248_OR_NOT__ETC___d21990, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12798, @@ -6670,15 +6673,15 @@ module mkCore(CLK, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d11790, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d8603, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d8996, - _0_CONCAT_csrf_mtcc_reg_read__6198_BITS_149_TO__ETC___d22832, - _0_CONCAT_csrf_mtcc_reg_read__6198_BITS_149_TO__ETC___d22857, - _0_CONCAT_csrf_stcc_reg_read__6046_BITS_149_TO__ETC___d22763, - _0_CONCAT_csrf_stcc_reg_read__6046_BITS_149_TO__ETC___d22788, + _0_CONCAT_csrf_mtcc_reg_read__6198_BITS_149_TO__ETC___d22834, + _0_CONCAT_csrf_mtcc_reg_read__6198_BITS_149_TO__ETC___d22859, + _0_CONCAT_csrf_stcc_reg_read__6046_BITS_149_TO__ETC___d22765, + _0_CONCAT_csrf_stcc_reg_read__6046_BITS_149_TO__ETC___d22790, _0_OR_NOT_fetchStage_pipelines_0_first__0256_BI_ETC___d21841, _0_OR_NOT_fetchStage_pipelines_1_first__0265_BI_ETC___d21739, _0_OR_NOT_fetchStage_pipelines_1_first__0265_BI_ETC___d21934, _0b0_CONCAT_csrf_medeleg_28_26_reg_read__6161_6_ETC___d22642, - _0b0_CONCAT_csrf_mideleg_11_reg_read__6172_6173_ETC___d22644, + _0b0_CONCAT_csrf_mideleg_11_reg_read__6172_6173_ETC___d22645, _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10709, _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10734, _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10761, @@ -6733,12 +6736,12 @@ module mkCore(CLK, _dor1sbAggr$EN_setReady_3_put, _dor1sbCons$EN_setReady_0_put, _dor1sbCons$EN_setReady_1_put, - _theResult_____2__h526145, - _theResult_____2__h533238, - _theResult_____2__h543873, - _theResult_____2__h557706, - _theResult_____2__h561485, - cause_interrupt__h995318, + _theResult_____2__h526143, + _theResult_____2__h533236, + _theResult_____2__h543871, + _theResult_____2__h557704, + _theResult_____2__h561483, + cause_interrupt__h995316, commitStage_commitTrap_2268_BITS_44_TO_43_2461_ETC___d22501, commitStage_commitTrap_2268_BITS_44_TO_43_2461_ETC___d22508, commitStage_commitTrap_2268_BITS_44_TO_43_2461_ETC___d22613, @@ -7121,11 +7124,11 @@ module mkCore(CLK, coreFix_memExe_regToExeQ_first__645_BITS_259_T_ETC___d4110, coreFix_memExe_regToExeQ_first__645_BITS_265_T_ETC___d3717, coreFix_memExe_regToExeQ_first__645_BITS_383_T_ETC___d4113, - coreFix_memExe_stb_isEmpty__186_AND_coreFix_me_ETC___d23027, - cr_flags__h866674, - cr_flags__h867222, - cr_flags__h906360, - cr_flags__h906908, + coreFix_memExe_stb_isEmpty__186_AND_coreFix_me_ETC___d23029, + cr_flags__h866673, + cr_flags__h867221, + cr_flags__h906358, + cr_flags__h906906, csrf_ddc_reg_read__051_BITS_13_TO_11_140_ULT_c_ETC___d4144, csrf_ddc_reg_read__051_BITS_27_TO_25_142_ULT_c_ETC___d4143, csrf_ddc_reg_read__051_BITS_85_TO_83_145_ULT_c_ETC___d4146, @@ -7133,23 +7136,23 @@ module mkCore(CLK, csrf_fs_reg_read__6010_EQ_0_0640_AND_fetchStag_ETC___d21258, csrf_fs_reg_read__6010_EQ_0_0640_AND_fetchStag_ETC___d21700, csrf_mtcc_reg_read__6198_BITS_13_TO_11_6201_UL_ETC___d16203, - csrf_mtcc_reg_read__6198_BITS_149_TO_86_2811_A_ETC___d22821, - csrf_mtcc_reg_read__6198_BITS_149_TO_86_2811_A_ETC___d22849, + csrf_mtcc_reg_read__6198_BITS_149_TO_86_2813_A_ETC___d22823, + csrf_mtcc_reg_read__6198_BITS_149_TO_86_2813_A_ETC___d22851, csrf_mtcc_reg_read__6198_BITS_85_TO_83_6204_UL_ETC___d16205, - csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22647, + csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22648, csrf_prv_reg_read__0286_ULE_1___d22614, csrf_rg_dpc_read__6343_BITS_13_TO_11_6346_ULT__ETC___d16348, csrf_rg_dpc_read__6343_BITS_85_TO_83_6349_ULT__ETC___d16350, csrf_stcc_reg_read__6046_BITS_13_TO_11_6049_UL_ETC___d16051, - csrf_stcc_reg_read__6046_BITS_149_TO_86_2740_A_ETC___d22752, - csrf_stcc_reg_read__6046_BITS_149_TO_86_2740_A_ETC___d22780, + csrf_stcc_reg_read__6046_BITS_149_TO_86_2742_A_ETC___d22754, + csrf_stcc_reg_read__6046_BITS_149_TO_86_2742_A_ETC___d22782, csrf_stcc_reg_read__6046_BITS_85_TO_83_6052_UL_ETC___d16053, - f_csr_reqs_first__3969_BITS_63_TO_14_4122_XOR__ETC___d24136, - f_csr_reqs_first__3969_BITS_63_TO_14_4122_XOR__ETC___d24158, - f_csr_reqs_first__3969_BITS_63_TO_14_4122_XOR__ETC___d24216, - f_csr_reqs_first__3969_BITS_63_TO_14_4122_XOR__ETC___d24236, - f_csr_reqs_first__3969_BITS_63_TO_14_4122_XOR__ETC___d24307, - f_csr_rsps_i_notFull__3967_AND_f_csr_reqs_firs_ETC___d24072, + f_csr_reqs_first__3971_BITS_63_TO_14_4124_XOR__ETC___d24138, + f_csr_reqs_first__3971_BITS_63_TO_14_4124_XOR__ETC___d24160, + f_csr_reqs_first__3971_BITS_63_TO_14_4124_XOR__ETC___d24218, + f_csr_reqs_first__3971_BITS_63_TO_14_4124_XOR__ETC___d24238, + f_csr_reqs_first__3971_BITS_63_TO_14_4124_XOR__ETC___d24309, + f_csr_rsps_i_notFull__3969_AND_f_csr_reqs_firs_ETC___d24074, fetchStage_RDY_pipelines_0_first__0253_AND_fet_ETC___d21254, fetchStage_RDY_pipelines_1_deq__0268_AND_NOT_f_ETC___d21994, fetchStage_pipelines_0_canDeq__0254_AND_NOT_fe_ETC___d21932, @@ -7177,29 +7180,29 @@ module mkCore(CLK, fetchStage_pipelines_1_first__0265_BITS_268_TO_ETC___d21888, fetchStage_pipelines_1_first__0265_BITS_268_TO_ETC___d22174, fetchStage_pipelines_1_first__0265_BITS_273_TO_ETC___d21899, - guard__h594701, - guard__h640450, - guard__h686197, - guard__h736236, - guard__h775089, - guard__h814393, - idx__h968880, - k__h945030, + guard__h594699, + guard__h640448, + guard__h686195, + guard__h736233, + guard__h775086, + guard__h814390, + idx__h968878, + k__h945028, mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d20679, mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d21071, mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d21091, mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d22008, mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d22010, - next_deqP___1__h526390, - next_deqP___1__h533668, - next_deqP___1__h544303, - next_deqP___1__h557951, - next_deqP___1__h561730, - r1__read_BIT_20___h926960, - r__h853139, - r__h855583, - regRenamingTable_RDY_rename_0_claimRename__102_ETC___d21039, - regRenamingTable_RDY_rename_0_getRename__1027__ETC___d21854, + next_deqP___1__h526388, + next_deqP___1__h533666, + next_deqP___1__h544301, + next_deqP___1__h557949, + next_deqP___1__h561728, + r1__read_BIT_20___h926958, + r__h853138, + r__h855582, + regRenamingTable_RDY_rename_0_getRename__1028__ETC___d21039, + regRenamingTable_RDY_rename_0_getRename__1028__ETC___d21854, regRenamingTable_rename_0_canRename__1151_AND__ETC___d21180, regRenamingTable_rename_0_canRename__1151_AND__ETC___d21245, regRenamingTable_rename_0_canRename__1151_AND__ETC___d21249, @@ -7236,25 +7239,26 @@ module mkCore(CLK, rf_read_3_rd2_coreFix_memExe_dispToRegQ_first__ETC___d3592, rf_read_3_rd2_coreFix_memExe_dispToRegQ_first__ETC___d3600, rf_read_3_rd2_coreFix_memExe_dispToRegQ_first__ETC___d3609, - rg_core_run_state_read__0682_EQ_2_0683_AND_NOT_ETC___d23893, + rg_core_run_state_read__0682_EQ_2_0683_AND_NOT_ETC___d23895, rob_enqPort_1_canEnq__1634_AND_epochManager_ch_ETC___d21639, sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d12442, sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d12443, sbCons_lazyLookup_3_get_coreFix_memExe_dispToR_ETC___d2768, - v__h516844, - v__h517224, - v__h532563, - v__h532758, - v__h535012, - v__h535207, - v__h556032, - v__h556227, - v__h559811, - v__h560006, - x__h240141, - x__h241298, - x__h254922, - x__h836143; + v__h516842, + v__h517222, + v__h532561, + v__h532756, + v__h535010, + v__h535205, + v__h556030, + v__h556225, + v__h559809, + v__h560004, + value_BIT_52___h677325, + x__h240138, + x__h241295, + x__h254919, + x__h836140; // action method coreReq_start assign RDY_coreReq_start = !renameStage_rg_m_halt_req[4] ; @@ -7292,10 +7296,10 @@ module mkCore(CLK, // value method dCacheToParent_rsToP_first assign dCacheToParent_rsToP_first = - { CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q311, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q312, - !CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q313, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d24448 } ; + { CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q313, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q314, + !CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q315, + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d24450 } ; assign RDY_dCacheToParent_rsToP_first = !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty ; @@ -7313,9 +7317,9 @@ module mkCore(CLK, // value method dCacheToParent_rqToP_first assign dCacheToParent_rqToP_first = - { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q319, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q320, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d24474 } ; + { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q321, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q322, + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d24476 } ; assign RDY_dCacheToParent_rqToP_first = !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty ; @@ -9178,32 +9182,32 @@ module mkCore(CLK, // rule RL_sendDTlbReq assign CAN_FIRE_RL_sendDTlbReq = - coreFix_memExe_dTlb$RDY_toParent_rqToP_deq && coreFix_memExe_dTlb$RDY_toParent_rqToP_first && + coreFix_memExe_dTlb$RDY_toParent_rqToP_deq && l2Tlb$RDY_toChildren_rqFromC_put ; assign WILL_FIRE_RL_sendDTlbReq = CAN_FIRE_RL_sendDTlbReq ; // rule RL_sendITlbReq assign CAN_FIRE_RL_sendITlbReq = - fetchStage$RDY_iTlbIfc_toParent_rqToP_deq && + l2Tlb$RDY_toChildren_rqFromC_put && fetchStage$RDY_iTlbIfc_toParent_rqToP_first && - l2Tlb$RDY_toChildren_rqFromC_put ; + fetchStage$RDY_iTlbIfc_toParent_rqToP_deq ; assign WILL_FIRE_RL_sendITlbReq = CAN_FIRE_RL_sendITlbReq && !WILL_FIRE_RL_sendDTlbReq ; // rule RL_sendRsToDTlb assign CAN_FIRE_RL_sendRsToDTlb = - l2Tlb$RDY_toChildren_rsToC_deq && l2Tlb$RDY_toChildren_rsToC_first && + l2Tlb$RDY_toChildren_rsToC_deq && coreFix_memExe_dTlb$RDY_toParent_ldTransRsFromP_enq && l2Tlb$toChildren_rsToC_first[83] ; assign WILL_FIRE_RL_sendRsToDTlb = CAN_FIRE_RL_sendRsToDTlb ; // rule RL_sendRsToITlb assign CAN_FIRE_RL_sendRsToITlb = - fetchStage$RDY_iTlbIfc_toParent_rsFromP_enq && - l2Tlb$RDY_toChildren_rsToC_deq && l2Tlb$RDY_toChildren_rsToC_first && + l2Tlb$RDY_toChildren_rsToC_deq && + fetchStage$RDY_iTlbIfc_toParent_rsFromP_enq && !l2Tlb$toChildren_rsToC_first[83] ; assign WILL_FIRE_RL_sendRsToITlb = CAN_FIRE_RL_sendRsToITlb ; @@ -9215,16 +9219,16 @@ module mkCore(CLK, // rule RL_mkConnectionGetPut_1 assign CAN_FIRE_RL_mkConnectionGetPut_1 = - fetchStage$RDY_iTlbIfc_toParent_flush_request_get && - l2Tlb$RDY_toChildren_iTlbReqFlush_put ; + l2Tlb$RDY_toChildren_iTlbReqFlush_put && + fetchStage$RDY_iTlbIfc_toParent_flush_request_get ; assign WILL_FIRE_RL_mkConnectionGetPut_1 = CAN_FIRE_RL_mkConnectionGetPut_1 ; // rule RL_sendFlushDone assign CAN_FIRE_RL_sendFlushDone = - fetchStage$RDY_iTlbIfc_toParent_flush_response_put && coreFix_memExe_dTlb$RDY_toParent_flush_response_put && - l2Tlb$RDY_toChildren_flushDone_get ; + l2Tlb$RDY_toChildren_flushDone_get && + fetchStage$RDY_iTlbIfc_toParent_flush_response_put ; assign WILL_FIRE_RL_sendFlushDone = CAN_FIRE_RL_sendFlushDone ; // rule RL_sendRobEnqTime @@ -9245,7 +9249,7 @@ module mkCore(CLK, // rule RL_readyToFetch assign CAN_FIRE_RL_readyToFetch = fetchStage$RDY_done_flushing && - rg_core_run_state_read__0682_EQ_2_0683_AND_NOT_ETC___d23893 && + rg_core_run_state_read__0682_EQ_2_0683_AND_NOT_ETC___d23895 && !flush_brpred && fetchStage$iMemIfc_flush_done && fetchStage$flush_predictors_done ; @@ -9373,9 +9377,9 @@ module mkCore(CLK, // rule RL_mmio_sendInstReq assign CAN_FIRE_RL_mmio_sendInstReq = - !mmio_cRqQ_full && fetchStage$RDY_mmioIfc_instReq_deq && + !mmio_cRqQ_full && fetchStage$RDY_mmioIfc_instReq_first_snd && fetchStage$RDY_mmioIfc_instReq_first_fst && - fetchStage$RDY_mmioIfc_instReq_first_snd ; + fetchStage$RDY_mmioIfc_instReq_deq ; assign WILL_FIRE_RL_mmio_sendInstReq = CAN_FIRE_RL_mmio_sendInstReq && !WILL_FIRE_RL_mmio_sendDataReq ; @@ -9456,16 +9460,16 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doDeqLdQ_fault assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_fault = - rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_firstLd && - coreFix_memExe_lsq$RDY_deqLd && + rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_deqLd && + coreFix_memExe_lsq$RDY_firstLd && coreFix_memExe_lsq$firstLd[16] ; assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault = CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ; // rule RL_coreFix_memExe_doDeqLdQ_Ld_Mem assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem = - rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_firstLd && - coreFix_memExe_lsq$RDY_deqLd && + rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_deqLd && + coreFix_memExe_lsq$RDY_firstLd && !coreFix_memExe_lsq$firstLd[16] && !coreFix_memExe_lsq$firstLd[126] && !coreFix_memExe_lsq$firstLd[33] ; @@ -9697,7 +9701,7 @@ module mkCore(CLK, // rule RL_commitStage_doCommitTrap_flush assign CAN_FIRE_RL_commitStage_doCommitTrap_flush = - rob$RDY_deqPort_0_deq && rob$RDY_deqPort_0_deq_data && + rob$RDY_deqPort_0_deq_data && rob$RDY_deqPort_0_deq && (rob$deqPort_0_deq_data[12] || epochManager$RDY_incrementEpoch) && !commitStage_rg_run_state && @@ -9750,15 +9754,15 @@ module mkCore(CLK, // rule RL_rl_debug_csr_write assign CAN_FIRE_RL_rl_debug_csr_write = f_csr_reqs$EMPTY_N && - f_csr_rsps_i_notFull__3967_AND_f_csr_reqs_firs_ETC___d24072 && + f_csr_rsps_i_notFull__3969_AND_f_csr_reqs_firs_ETC___d24074 && rg_core_run_state == 2'd1 && f_csr_reqs$D_OUT[76] ; assign WILL_FIRE_RL_rl_debug_csr_write = CAN_FIRE_RL_rl_debug_csr_write ; // rule RL_commitStage_doCommitKilledLd assign CAN_FIRE_RL_commitStage_doCommitKilledLd = - rob$RDY_deqPort_0_deq && rob$RDY_deqPort_0_deq_data && - epochManager$RDY_incrementEpoch && + epochManager$RDY_incrementEpoch && rob$RDY_deqPort_0_deq_data && + rob$RDY_deqPort_0_deq && !commitStage_rg_run_state && !commitStage_commitTrap[238] && !rob$deqPort_0_deq_data[274] && @@ -9788,8 +9792,8 @@ module mkCore(CLK, // rule RL_commitStage_doCommitSystemInst assign CAN_FIRE_RL_commitStage_doCommitSystemInst = - coreFix_memExe_stb_isEmpty__186_AND_coreFix_me_ETC___d23027 && - NOT_commitStage_rg_run_state_2266_2267_AND_NOT_ETC___d23033 && + coreFix_memExe_stb_isEmpty__186_AND_coreFix_me_ETC___d23029 && + NOT_commitStage_rg_run_state_2266_2267_AND_NOT_ETC___d23035 && (rob$deqPort_0_deq_data[469:465] == 5'd0 || rob$deqPort_0_deq_data[469:465] == 5'd26 || rob$deqPort_0_deq_data[469:465] == 5'd22 || @@ -9832,8 +9836,8 @@ module mkCore(CLK, // rule RL_commitStage_doCommitNormalInst assign CAN_FIRE_RL_commitStage_doCommitNormalInst = rob$RDY_deqPort_0_deq_data && - NOT_rob_deqPort_0_canDeq__3598_3599_OR_rob_RDY_ETC___d23639 && - NOT_commitStage_rg_run_state_2266_2267_AND_NOT_ETC___d23033 && + NOT_rob_deqPort_0_canDeq__3600_3601_OR_regRena_ETC___d23641 && + NOT_commitStage_rg_run_state_2266_2267_AND_NOT_ETC___d23035 && rob$deqPort_0_deq_data[469:465] != 5'd0 && rob$deqPort_0_deq_data[469:465] != 5'd26 && rob$deqPort_0_deq_data[469:465] != 5'd22 && @@ -9993,8 +9997,8 @@ module mkCore(CLK, // rule RL_coreFix_aluExe_0_doDispatchAlu assign CAN_FIRE_RL_coreFix_aluExe_0_doDispatchAlu = coreFix_aluExe_0_dispToRegQ$RDY_enq && - coreFix_aluExe_0_rsAlu$RDY_dispatchData && - coreFix_aluExe_0_rsAlu$RDY_doDispatch ; + coreFix_aluExe_0_rsAlu$RDY_doDispatch && + coreFix_aluExe_0_rsAlu$RDY_dispatchData ; assign WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu = CAN_FIRE_RL_coreFix_aluExe_0_doDispatchAlu && !WILL_FIRE_RL_commitStage_doCommitKilledLd && @@ -10005,8 +10009,8 @@ module mkCore(CLK, // rule RL_coreFix_aluExe_1_doDispatchAlu assign CAN_FIRE_RL_coreFix_aluExe_1_doDispatchAlu = coreFix_aluExe_1_dispToRegQ$RDY_enq && - coreFix_aluExe_1_rsAlu$RDY_dispatchData && - coreFix_aluExe_1_rsAlu$RDY_doDispatch ; + coreFix_aluExe_1_rsAlu$RDY_doDispatch && + coreFix_aluExe_1_rsAlu$RDY_dispatchData ; assign WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu = CAN_FIRE_RL_coreFix_aluExe_1_doDispatchAlu && !WILL_FIRE_RL_commitStage_doCommitKilledLd && @@ -10018,8 +10022,8 @@ module mkCore(CLK, assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq = !coreFix_memExe_respLrScAmoQ_empty && rob$RDY_setExecuted_deqLSQ && - coreFix_memExe_lsq$RDY_firstLd && coreFix_memExe_lsq$RDY_deqLd && + coreFix_memExe_lsq$RDY_firstLd && coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd1 ; assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq = CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && @@ -10043,8 +10047,8 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doFinishMem assign CAN_FIRE_RL_coreFix_memExe_doFinishMem = rob$RDY_setExecuted_doFinishMem && - coreFix_memExe_dTlb$RDY_procResp && - coreFix_memExe_dTlb$RDY_deqProcResp ; + coreFix_memExe_dTlb$RDY_deqProcResp && + coreFix_memExe_dTlb$RDY_procResp ; assign WILL_FIRE_RL_coreFix_memExe_doFinishMem = CAN_FIRE_RL_coreFix_memExe_doFinishMem ; @@ -10132,16 +10136,16 @@ module mkCore(CLK, // rule RL_prepareCachesAndTlbs assign CAN_FIRE_RL_prepareCachesAndTlbs = (!flush_tlbs || - fetchStage$RDY_iTlbIfc_flush && - coreFix_memExe_dTlb$RDY_flush) && + coreFix_memExe_dTlb$RDY_flush && + fetchStage$RDY_iTlbIfc_flush) && (flush_reservation || flush_tlbs || update_vm_info) ; assign WILL_FIRE_RL_prepareCachesAndTlbs = CAN_FIRE_RL_prepareCachesAndTlbs ; // rule RL_rl_debug_resume assign CAN_FIRE_RL_rl_debug_resume = - commitStage_rg_run_state && fetchStage$RDY_iTlbIfc_flush && - coreFix_memExe_dTlb$RDY_flush && + commitStage_rg_run_state && coreFix_memExe_dTlb$RDY_flush && + fetchStage$RDY_iTlbIfc_flush && f_run_halt_reqs$EMPTY_N && f_run_halt_rsps$FULL_N && rg_core_run_state == 2'd1 && @@ -10149,9 +10153,7 @@ module mkCore(CLK, !f_gpr_reqs$EMPTY_N && !f_fpr_reqs$EMPTY_N && !f_csr_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_debug_resume = - CAN_FIRE_RL_rl_debug_resume && - !WILL_FIRE_RL_prepareCachesAndTlbs ; + assign WILL_FIRE_RL_rl_debug_resume = MUX_started$write_1__SEL_1 ; // rule RL_coreFix_memExe_doRegReadMem assign CAN_FIRE_RL_coreFix_memExe_doRegReadMem = @@ -10169,8 +10171,8 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doDispatchMem assign CAN_FIRE_RL_coreFix_memExe_doDispatchMem = coreFix_memExe_dispToRegQ$RDY_enq && - coreFix_memExe_rsMem$RDY_dispatchData && - coreFix_memExe_rsMem$RDY_doDispatch ; + coreFix_memExe_rsMem$RDY_doDispatch && + coreFix_memExe_rsMem$RDY_dispatchData ; assign WILL_FIRE_RL_coreFix_memExe_doDispatchMem = CAN_FIRE_RL_coreFix_memExe_doDispatchMem && !WILL_FIRE_RL_commitStage_doCommitKilledLd && @@ -10305,8 +10307,8 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doDeqStQ_fault assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_fault = - rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_firstSt && - coreFix_memExe_lsq$RDY_deqSt && + rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_deqSt && + coreFix_memExe_lsq$RDY_firstSt && coreFix_memExe_lsq$firstSt[13] ; assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault = CAN_FIRE_RL_coreFix_memExe_doDeqStQ_fault && @@ -10328,8 +10330,8 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doDeqStQ_Fence assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_Fence = - rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_firstSt && - coreFix_memExe_lsq$RDY_deqSt && + rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_deqSt && + coreFix_memExe_lsq$RDY_firstSt && !coreFix_memExe_lsq$firstSt[13] && coreFix_memExe_lsq$firstSt[240:239] == 2'd3 && (!coreFix_memExe_lsq$firstSt[233] || @@ -10356,8 +10358,8 @@ module mkCore(CLK, assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq = !coreFix_memExe_respLrScAmoQ_empty && rob$RDY_setExecuted_deqLSQ && - coreFix_memExe_lsq$RDY_firstSt && coreFix_memExe_lsq$RDY_deqSt && + coreFix_memExe_lsq$RDY_firstSt && coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd2 ; assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq = CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && @@ -10515,8 +10517,8 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doDeqStQ_St_Mem assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem = - coreFix_memExe_stb$RDY_enq && coreFix_memExe_lsq$RDY_firstSt && - coreFix_memExe_lsq$RDY_deqSt && + coreFix_memExe_stb$RDY_enq && coreFix_memExe_lsq$RDY_deqSt && + coreFix_memExe_lsq$RDY_firstSt && !coreFix_memExe_lsq$firstSt[13] && coreFix_memExe_lsq$firstSt[240:239] == 2'd0 && !coreFix_memExe_lsq$firstSt[159] && @@ -10536,7 +10538,7 @@ module mkCore(CLK, !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty && coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_send && coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_getEmptyEntryInit && - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q321 ; + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q323 ; assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer = CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer ; @@ -10565,7 +10567,7 @@ module mkCore(CLK, assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer = !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty && coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_send && - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q322 ; + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q324 ; assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer = CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer ; @@ -10741,8 +10743,8 @@ module mkCore(CLK, // rule RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv = coreFix_fpuMulDivExe_0_dispToRegQ$RDY_enq && - coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_dispatchData && - coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_doDispatch ; + coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_doDispatch && + coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_dispatchData ; assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv = CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv && !WILL_FIRE_RL_commitStage_doCommitKilledLd && @@ -10762,9 +10764,9 @@ module mkCore(CLK, // rule RL_renameStage_doRenaming_Trap assign CAN_FIRE_RL_renameStage_doRenaming_Trap = - rob$RDY_enqPort_0_enq && fetchStage$RDY_pipelines_0_deq && + epochManager$RDY_incrementEpoch && rob$RDY_enqPort_0_enq && fetchStage$RDY_pipelines_0_first && - epochManager$RDY_incrementEpoch && + fetchStage$RDY_pipelines_0_deq && mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d20679 && rob$isEmpty && rg_core_run_state == 2'd2 ; @@ -10777,9 +10779,9 @@ module mkCore(CLK, // rule RL_renameStage_doRenaming_SystemInst assign CAN_FIRE_RL_renameStage_doRenaming_SystemInst = - rob$RDY_enqPort_0_enq && - regRenamingTable$RDY_rename_0_getRename && - regRenamingTable_RDY_rename_0_claimRename__102_ETC___d21039 && + epochManager$RDY_incrementEpoch && + regRenamingTable$RDY_rename_0_claimRename && + regRenamingTable_RDY_rename_0_getRename__1028__ETC___d21039 && mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d21091 && rg_core_run_state == 2'd2 ; assign WILL_FIRE_RL_renameStage_doRenaming_SystemInst = @@ -10880,10 +10882,7 @@ module mkCore(CLK, WILL_FIRE_RL_commitStage_doCommitKilledLd || WILL_FIRE_RL_commitStage_doCommitTrap_flush ; assign MUX_coreFix_aluExe_0_rsAlu$enq_1__SEL_1 = - WILL_FIRE_RL_renameStage_doRenaming_SystemInst && - (fetchStage$pipelines_0_first[268:266] == 3'd0 || - fetchStage$pipelines_0_first[238:237] == 2'd1 || - fetchStage$pipelines_0_first[238:237] == 2'd0) ; + WILL_FIRE_RL_renameStage_doRenaming && _dfoo18 ; assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple && coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] ; @@ -11048,9 +11047,9 @@ module mkCore(CLK, assign MUX_csrf_external_int_en_vec_1$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - (IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + (IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd9 || - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd23) ; assign MUX_csrf_external_int_en_vec_3$write_1__SEL_1 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11058,9 +11057,9 @@ module mkCore(CLK, assign MUX_csrf_external_int_pend_vec_1$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - (IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + (IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd16 || - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd30) ; assign MUX_csrf_external_int_pend_vec_1$write_1__SEL_2 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11068,13 +11067,13 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd836) ; assign MUX_csrf_fflags_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitNormalInst && - NOT_IF_NOT_rob_deqPort_0_canDeq__3598_3599_OR__ETC___d23844 ; + NOT_IF_NOT_rob_deqPort_0_canDeq__3600_3601_OR__ETC___d23846 ; assign MUX_csrf_fflags_reg$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - (IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + (IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd0 || - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd2) ; assign MUX_csrf_fflags_reg$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11083,22 +11082,22 @@ module mkCore(CLK, assign MUX_csrf_frm_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - (IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + (IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd1 || - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd2) ; assign MUX_csrf_fs_reg$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - (IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + (IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd0 || - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd1 || - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd2 || - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd8 || - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd19) ; assign MUX_csrf_fs_reg$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11110,9 +11109,9 @@ module mkCore(CLK, assign MUX_csrf_ie_vec_0$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - (IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + (IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd8 || - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd19) ; assign MUX_csrf_ie_vec_0$write_1__SEL_2 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11123,7 +11122,7 @@ module mkCore(CLK, assign MUX_csrf_ie_vec_1$write_1__SEL_3 = WILL_FIRE_RL_commitStage_doCommitTrap_handle && commitStage_commitTrap_2268_BITS_44_TO_43_2461_ETC___d22613 && - csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22647 ; + csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22648 ; assign MUX_csrf_ie_vec_3$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo30 ; assign MUX_csrf_ie_vec_3$write_1__SEL_2 = @@ -11132,11 +11131,11 @@ module mkCore(CLK, assign MUX_csrf_ie_vec_3$write_1__SEL_3 = WILL_FIRE_RL_commitStage_doCommitTrap_handle && commitStage_commitTrap_2268_BITS_44_TO_43_2461_ETC___d22613 && - NOT_csrf_prv_reg_read__0286_ULE_1_2614_2729_OR_ETC___d22734 ; + NOT_csrf_prv_reg_read__0286_ULE_1_2614_2730_OR_ETC___d22736 ; assign MUX_csrf_mcause_code_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd28 ; assign MUX_csrf_mcause_code_reg$write_1__SEL_2 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11154,8 +11153,7 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd770 ; assign MUX_csrf_mepcc_reg_data_lat_1$wset_1__SEL_1 = - WILL_FIRE_RL_rl_debug_csr_write && - f_csr_reqs$D_OUT[75:64] == 12'd833 ; + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; assign MUX_csrf_mideleg_11_reg$write_1__SEL_1 = WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd771 ; @@ -11168,12 +11166,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd832 ; assign MUX_csrf_mtcc_reg$write_1__SEL_1 = - WILL_FIRE_RL_rl_debug_csr_write && - f_csr_reqs$D_OUT[75:64] == 12'd773 ; + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 ; assign MUX_csrf_mtval_csr$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd29 ; assign MUX_csrf_mtval_csr$write_1__SEL_2 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11193,12 +11190,12 @@ module mkCore(CLK, assign MUX_csrf_rg_dcsr$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd42 ; assign MUX_csrf_rg_dpc$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd43 ; assign MUX_csrf_rg_dpc$write_1__SEL_2 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11224,7 +11221,7 @@ module mkCore(CLK, assign MUX_csrf_scause_code_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd14 ; assign MUX_csrf_scause_code_reg$write_1__SEL_2 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11233,8 +11230,7 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd262 ; assign MUX_csrf_sepcc_reg_data_lat_1$wset_1__SEL_1 = - WILL_FIRE_RL_rl_debug_csr_write && - f_csr_reqs$D_OUT[75:64] == 12'd321 ; + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo36 ; assign MUX_csrf_spp_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo40 ; assign MUX_csrf_sscratch_csr$write_1__SEL_1 = @@ -11244,12 +11240,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd2049 ; assign MUX_csrf_stcc_reg$write_1__SEL_1 = - WILL_FIRE_RL_rl_debug_csr_write && - f_csr_reqs$D_OUT[75:64] == 12'd261 ; + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo38 ; assign MUX_csrf_stval_csr$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd15 ; assign MUX_csrf_stval_csr$write_1__SEL_2 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11267,7 +11262,7 @@ module mkCore(CLK, assign MUX_f_run_halt_rsps$enq_1__SEL_1 = WILL_FIRE_RL_rl_debug_halted || WILL_FIRE_RL_rl_debug_halt_req_already_halted ; - assign MUX_flush_reservation$write_1__SEL_1 = + assign MUX_flush_reservation$write_1__SEL_2 = WILL_FIRE_RL_prepareCachesAndTlbs && flush_reservation ; assign MUX_flush_tlbs$write_1__SEL_1 = WILL_FIRE_RL_prepareCachesAndTlbs && flush_tlbs ; @@ -11320,6 +11315,9 @@ module mkCore(CLK, coreFix_memExe_lsq$firstLd[106] ; assign MUX_sbCons$setReady_3_put_1__SEL_3 = MUX_rf$write_3_wr_1__PSEL_5 && coreFix_memExe_lsq$respLd[137] ; + assign MUX_started$write_1__SEL_1 = + CAN_FIRE_RL_rl_debug_resume && + !WILL_FIRE_RL_prepareCachesAndTlbs ; assign MUX_regRenamingTable$rename_0_getRename_1__VAL_2 = { 2'd2, f_gpr_reqs$D_OUT[68:64], 20'd345386 } ; assign MUX_regRenamingTable$rename_0_getRename_1__VAL_3 = @@ -11327,25 +11325,15 @@ module mkCore(CLK, assign MUX_commitStage_commitTrap$write_1__VAL_2 = { 1'd1, rob$deqPort_0_deq_data[630:502], - addr__h989736, - CASE_robdeqPort_0_deq_data_BITS_273_TO_272_0__ETC__q326, + addr__h989734, + CASE_robdeqPort_0_deq_data_BITS_273_TO_272_0__ETC__q328, rob$deqPort_0_deq_data[501:470] } ; - assign MUX_commitStage_rg_serial_num$write_1__VAL_2 = + assign MUX_commitStage_rg_serial_num$write_1__VAL_1 = commitStage_rg_serial_num + 64'd1 ; assign MUX_commitStage_rg_serial_num$write_1__VAL_3 = - commitStage_rg_serial_num + y__h1016339 ; + commitStage_rg_serial_num + y__h1016374 ; assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_1 = - { fetchStage$pipelines_0_first[273:269], - IF_fetchStage_pipelines_0_first__0256_BITS_268_ETC___d20382, - IF_fetchStage_pipelines_0_first__0256_BITS_238_ETC___d20622, - fetchStage$pipelines_0_first[329:306], - regRenamingTable$rename_0_getRename, - rob$enqPort_0_getEnqInstTag, - specTagManager$currentSpecBits, - 5'd10, - sbAggr$eagerLookup_0_get } ; - assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_2 = - (k__h945030 == 1'd0 && fetchStage$pipelines_0_canDeq && + (k__h945028 == 1'd0 && fetchStage$pipelines_0_canDeq && NOT_fetchStage_pipelines_0_first__0256_BITS_26_ETC___d22015) ? { fetchStage$pipelines_0_first[273:269], IF_fetchStage_pipelines_0_first__0256_BITS_268_ETC___d20382, @@ -11363,10 +11351,20 @@ module mkCore(CLK, fetchStage$pipelines_1_first[329:306], regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h968741, + renaming_spec_bits__h968739, fetchStage$pipelines_1_first[268:266] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; + assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_2 = + { fetchStage$pipelines_0_first[273:269], + IF_fetchStage_pipelines_0_first__0256_BITS_268_ETC___d20382, + IF_fetchStage_pipelines_0_first__0256_BITS_238_ETC___d20622, + fetchStage$pipelines_0_first[329:306], + regRenamingTable$rename_0_getRename, + rob$enqPort_0_getEnqInstTag, + specTagManager$currentSpecBits, + 5'd10, + sbAggr$eagerLookup_0_get } ; assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1 = { 1'd1, coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[31:25] } ; assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2 = @@ -11461,7 +11459,7 @@ module mkCore(CLK, assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_1 = { 521'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq[221:158], - x__h501097 } ; + x__h501096 } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_2 = { 521'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d7036 } ; @@ -11471,7 +11469,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_4 = { 2'd2, - addr__h505615, + addr__h505614, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d7144 } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_1 = { 1'd1, @@ -11488,12 +11486,12 @@ module mkCore(CLK, coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget : coreFix_memExe_reqLrScAmoQ_data_0_rl ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_2 = - { x__h148991, - addr__h148439, + { x__h148990, + addr__h148438, 158'h20AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_3 = - { x__h152125, - addr__h152015, + { x__h152124, + addr__h152014, 158'h32AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_1 = { 1'd1, @@ -11503,7 +11501,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[581:579] } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_1 = { 1'd1, - resp_addr__h509111, + resp_addr__h509110, 2'd0, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getData } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_2 = @@ -11511,8 +11509,8 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getRq, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getData } ; assign MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1 = - { prv__h1017453, - prv__h1017453 != 2'd3 && csrf_vm_mode_sv39_reg, + { prv__h1017488, + prv__h1017488 != 2'd3 && csrf_vm_mode_sv39_reg, csrf_mxr_reg, csrf_sum_reg, csrf_ppn_reg } ; @@ -11537,11 +11535,11 @@ module mkCore(CLK, coreFix_memExe_stb$search[128:0] : 129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; assign MUX_coreFix_memExe_lsq$respLd_2__VAL_1 = - { CASE_coreFix_memExe_memRespLdQ_deqP_0_coreFix__ETC__q327, + { CASE_coreFix_memExe_memRespLdQ_deqP_0_coreFix__ETC__q330, SEL_ARR_coreFix_memExe_memRespLdQ_data_0_133_B_ETC___d2147, SEL_ARR_coreFix_memExe_memRespLdQ_data_0_133_B_ETC___d2151 } ; assign MUX_coreFix_memExe_lsq$respLd_2__VAL_2 = - { CASE_coreFix_memExe_forwardQ_deqP_0_coreFix_me_ETC__q328, + { CASE_coreFix_memExe_forwardQ_deqP_0_coreFix_me_ETC__q329, SEL_ARR_coreFix_memExe_forwardQ_data_0_216_BIT_ETC___d2230, SEL_ARR_coreFix_memExe_forwardQ_data_0_216_BIT_ETC___d2234 } ; assign MUX_coreFix_memExe_memRespLdQ_enqReq_lat_0$wset_1__VAL_1 = @@ -11581,55 +11579,55 @@ module mkCore(CLK, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4854, IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d4891 } ; assign MUX_coreFix_trainBPQ_0$enq_1__VAL_1 = - { x__h914620, - new_pc__h912073, + { x__h914618, + new_pc__h912071, coreFix_aluExe_0_exeToFinQ$first[1066:1062], coreFix_aluExe_0_exeToFinQ$first[297], coreFix_aluExe_0_exeToFinQ$first[1040:1017], 1'd0, coreFix_aluExe_0_exeToFinQ$first[1016] } ; assign MUX_coreFix_trainBPQ_0$enq_1__VAL_2 = - { x__h914620, - new_pc__h912073, + { x__h914618, + new_pc__h912071, coreFix_aluExe_0_exeToFinQ$first[1066:1062], coreFix_aluExe_0_exeToFinQ$first[297], coreFix_aluExe_0_exeToFinQ$first[1040:1017], 1'd1, coreFix_aluExe_0_exeToFinQ$first[1016] } ; assign MUX_coreFix_trainBPQ_1$enq_1__VAL_1 = - { x__h879903, - new_pc__h872925, + { x__h879902, + new_pc__h872924, coreFix_aluExe_1_exeToFinQ$first[1066:1062], coreFix_aluExe_1_exeToFinQ$first[297], coreFix_aluExe_1_exeToFinQ$first[1040:1017], 1'd0, coreFix_aluExe_1_exeToFinQ$first[1016] } ; assign MUX_coreFix_trainBPQ_1$enq_1__VAL_2 = - { x__h879903, - new_pc__h872925, + { x__h879902, + new_pc__h872924, coreFix_aluExe_1_exeToFinQ$first[1066:1062], coreFix_aluExe_1_exeToFinQ$first[297], coreFix_aluExe_1_exeToFinQ$first[1040:1017], 1'd1, coreFix_aluExe_1_exeToFinQ$first[1016] } ; assign MUX_csrf_fflags_reg$write_1__VAL_1 = - csrf_fflags_reg | fflags__h1016316 ; + csrf_fflags_reg | fflags__h1016351 ; assign MUX_csrf_frm_reg$write_1__VAL_1 = - (IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + (IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd1) ? - robdeqPort_0_deq_data_BITS_95_TO_32__q16[2:0] : - robdeqPort_0_deq_data_BITS_95_TO_32__q16[7:5] ; + robdeqPort_0_deq_data_BITS_95_TO_32__q17[2:0] : + robdeqPort_0_deq_data_BITS_95_TO_32__q17[7:5] ; assign MUX_csrf_frm_reg$write_1__VAL_2 = (f_csr_reqs$D_OUT[75:64] == 12'd2) ? f_csr_reqs$D_OUT[2:0] : f_csr_reqs$D_OUT[7:5] ; - always@(IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 or - robdeqPort_0_deq_data_BITS_95_TO_32__q16) + always@(IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 or + robdeqPort_0_deq_data_BITS_95_TO_32__q17) begin - case (IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012) + case (IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014) 6'd0, 6'd1, 6'd2: MUX_csrf_fs_reg$write_1__VAL_2 = 2'b11; default: MUX_csrf_fs_reg$write_1__VAL_2 = - robdeqPort_0_deq_data_BITS_95_TO_32__q16[14:13]; + robdeqPort_0_deq_data_BITS_95_TO_32__q17[14:13]; endcase end always@(f_csr_reqs$D_OUT) @@ -11641,163 +11639,163 @@ module mkCore(CLK, end assign MUX_csrf_ie_vec_1$write_1__VAL_1 = (rob$deqPort_0_deq_data[469:465] == 5'd17 && - (IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + (IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd8 || - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd19)) ? - robdeqPort_0_deq_data_BITS_95_TO_32__q16[1] : + robdeqPort_0_deq_data_BITS_95_TO_32__q17[1] : csrf_prev_ie_vec_1 ; assign MUX_csrf_ie_vec_3$write_1__VAL_1 = (rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd19) ? - robdeqPort_0_deq_data_BITS_95_TO_32__q16[3] : + robdeqPort_0_deq_data_BITS_95_TO_32__q17[3] : csrf_prev_ie_vec_3 ; assign MUX_csrf_mccsr_reg$write_1__VAL_1 = { f_csr_reqs$D_OUT[15:10], - CASE_f_csr_reqsD_OUT_BITS_9_TO_5_0_f_csr_reqs_ETC__q329 } ; + CASE_f_csr_reqsD_OUT_BITS_9_TO_5_0_f_csr_reqs_ETC__q331 } ; assign MUX_csrf_mccsr_reg$write_1__VAL_2 = - { robdeqPort_0_deq_data_BITS_95_TO_32__q16[15:10], - CASE_robdeqPort_0_deq_data_BITS_95_TO_326_BITS_ETC__q330 } ; + { robdeqPort_0_deq_data_BITS_95_TO_32__q17[15:10], + CASE_robdeqPort_0_deq_data_BITS_95_TO_327_BITS_ETC__q332 } ; assign MUX_csrf_mepcc_reg_data_lat_1$wset_1__VAL_1 = - { f_csr_reqs_first__3969_BITS_63_TO_14_4122_XOR__ETC___d24236, - result_d_address__h1032840, - result_d_addrBits__h1032841, - IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d23335 } ; - assign MUX_csrf_mepcc_reg_data_lat_1$wset_1__VAL_2 = (rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd27) ? - { IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23316, - result_d_address__h1009789, - result_d_addrBits__h1009790, - IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d23335 } : + { IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23318, + result_d_address__h1009824, + result_d_addrBits__h1009825, + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d23337 } : rob$deqPort_0_deq_data[194:42] ; + assign MUX_csrf_mepcc_reg_data_lat_1$wset_1__VAL_2 = + { f_csr_reqs_first__3971_BITS_63_TO_14_4124_XOR__ETC___d24238, + result_d_address__h1032874, + result_d_addrBits__h1032875, + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d23337 } ; assign MUX_csrf_minstret_ehr_data_lat_0$wset_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ; assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1 = - n__read__h1014112 + 64'd1 ; + n__read__h1014147 + 64'd1 ; assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2 = - n__read__h1014112 + { 62'd0, x__h1016564 } ; + n__read__h1014147 + { 62'd0, x__h1016599 } ; assign MUX_csrf_mpp_reg$write_1__VAL_1 = (rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd19) ? MUX_csrf_minstret_ehr_data_lat_0$wset_1__VAL_2[12:11] : 2'd0 ; assign MUX_csrf_mtcc_reg$write_1__VAL_1 = - { f_csr_reqs_first__3969_BITS_63_TO_14_4122_XOR__ETC___d24216, - result_d_address__h1032437, - result_d_addrBits__h1032438, - csrf_mtcc_reg[71:0] } ; - assign MUX_csrf_mtcc_reg$write_1__VAL_2 = (rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd24) ? - { IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23272, - result_d_address__h1009386, - result_d_addrBits__h1009387, + { IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23274, + result_d_address__h1009421, + result_d_addrBits__h1009422, csrf_mtcc_reg[71:0] } : rob$deqPort_0_deq_data[194:42] ; + assign MUX_csrf_mtcc_reg$write_1__VAL_2 = + { f_csr_reqs_first__3971_BITS_63_TO_14_4124_XOR__ETC___d24218, + result_d_address__h1032471, + result_d_addrBits__h1032472, + csrf_mtcc_reg[71:0] } ; assign MUX_csrf_mtval_csr$write_1__VAL_1 = rob$deqPort_0_deq_data[95:32] ; - always@(commitStage_commitTrap or trap_val__h997040 or trap_val__h996887) + always@(commitStage_commitTrap or trap_val__h997075 or trap_val__h996922) begin case (commitStage_commitTrap[44:43]) - 2'd0: MUX_csrf_mtval_csr$write_1__VAL_3 = trap_val__h997040; - 2'd1: MUX_csrf_mtval_csr$write_1__VAL_3 = trap_val__h996887; + 2'd0: MUX_csrf_mtval_csr$write_1__VAL_3 = trap_val__h997075; + 2'd1: MUX_csrf_mtval_csr$write_1__VAL_3 = trap_val__h996922; default: MUX_csrf_mtval_csr$write_1__VAL_3 = 64'd0; endcase end assign MUX_csrf_prev_ie_vec_1$write_1__VAL_1 = rob$deqPort_0_deq_data[469:465] != 5'd17 || - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 != + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 != 6'd8 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 != + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 != 6'd19 || MUX_csrf_mtval_csr$write_1__VAL_1[5] ; assign MUX_csrf_prev_ie_vec_3$write_1__VAL_1 = rob$deqPort_0_deq_data[469:465] != 5'd17 || - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 != + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 != 6'd19 || MUX_csrf_mtval_csr$write_1__VAL_1[7] ; assign MUX_csrf_prv_reg$write_1__VAL_1 = (rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd42) ? MUX_csrf_mtval_csr$write_1__VAL_1[1:0] : ((rob$deqPort_0_deq_data[469:465] == 5'd24) ? - x__h1012282 : + x__h1012317 : csrf_mpp_reg) ; assign MUX_csrf_prv_reg$write_1__VAL_3 = - csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22647 ? + csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22648 ? 2'd1 : 2'd3 ; assign MUX_csrf_rg_dcsr$write_1__VAL_1 = rob$deqPort_0_deq_data[95:32] ; assign MUX_csrf_rg_dcsr$write_1__VAL_3 = { 32'b0, csrf_rg_dcsr[31:9], - dcsr_cause__h994364, + dcsr_cause__h994362, csrf_rg_dcsr[5:2], csrf_prv_reg } ; assign MUX_csrf_rg_dpc$write_1__VAL_1 = - { IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23430, - result_d_address__h1010458, - result_d_addrBits__h1010459, + { IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23432, + result_d_address__h1010493, + result_d_addrBits__h1010494, csrf_rg_dpc[71:0] } ; assign MUX_csrf_rg_dpc$write_1__VAL_2 = - { f_csr_reqs_first__3969_BITS_63_TO_14_4122_XOR__ETC___d24307, - result_d_address__h1033507, - result_d_addrBits__h1033508, + { f_csr_reqs_first__3971_BITS_63_TO_14_4124_XOR__ETC___d24309, + result_d_address__h1033541, + result_d_addrBits__h1033542, csrf_rg_dpc[71:0] } ; assign MUX_csrf_rg_dpc$write_1__VAL_3 = { commitStage_commitTrap[237], - pc_address__h994739, - pc_addrBits__h994740, + pc_address__h994737, + pc_addrBits__h994738, commitStage_commitTrap[236:221], commitStage_commitTrap[218], commitStage_commitTrap[220:219], ~commitStage_commitTrap[217:199], IF_INV_commitStage_commitTrap_2268_BITS_217_TO_ETC___d22580, - x__h995109, - x__h995129 } ; + x__h995107, + x__h995127 } ; assign MUX_csrf_rg_tselect$write_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ; assign MUX_csrf_sepcc_reg_data_lat_1$wset_1__VAL_1 = - { f_csr_reqs_first__3969_BITS_63_TO_14_4122_XOR__ETC___d24158, - result_d_address__h1032020, - result_d_addrBits__h1032021, - IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d23198 } ; - assign MUX_csrf_sepcc_reg_data_lat_1$wset_1__VAL_2 = (rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd13) ? - { IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23179, - result_d_address__h1008969, - result_d_addrBits__h1008970, - IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d23198 } : + { IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23181, + result_d_address__h1009004, + result_d_addrBits__h1009005, + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d23200 } : rob$deqPort_0_deq_data[194:42] ; + assign MUX_csrf_sepcc_reg_data_lat_1$wset_1__VAL_2 = + { f_csr_reqs_first__3971_BITS_63_TO_14_4124_XOR__ETC___d24160, + result_d_address__h1032054, + result_d_addrBits__h1032055, + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d23200 } ; assign MUX_csrf_spp_reg$write_1__VAL_1 = rob$deqPort_0_deq_data[469:465] == 5'd17 && - (IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + (IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd8 || - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd19) && MUX_csrf_rg_tselect$write_1__VAL_2[8] ; assign MUX_csrf_stcc_reg$write_1__VAL_1 = - { f_csr_reqs_first__3969_BITS_63_TO_14_4122_XOR__ETC___d24136, - result_d_address__h1031617, - result_d_addrBits__h1031618, - csrf_stcc_reg[71:0] } ; - assign MUX_csrf_stcc_reg$write_1__VAL_2 = (rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd10) ? - { IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23133, - result_d_address__h1008566, - result_d_addrBits__h1008567, + { IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23135, + result_d_address__h1008601, + result_d_addrBits__h1008602, csrf_stcc_reg[71:0] } : rob$deqPort_0_deq_data[194:42] ; + assign MUX_csrf_stcc_reg$write_1__VAL_2 = + { f_csr_reqs_first__3971_BITS_63_TO_14_4124_XOR__ETC___d24138, + result_d_address__h1031651, + result_d_addrBits__h1031652, + csrf_stcc_reg[71:0] } ; assign MUX_csrf_stval_csr$write_1__VAL_1 = rob$deqPort_0_deq_data[95:32] ; - assign MUX_f_csr_rsps$enq_1__VAL_3 = { 1'd1, data_out__h1019990 } ; + assign MUX_f_csr_rsps$enq_1__VAL_3 = { 1'd1, data_out__h1020024 } ; assign MUX_f_fpr_rsps$enq_1__VAL_3 = { 1'd1, rf$read_4_rd1[149:86] } ; assign MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 = { csrf_prv_reg, @@ -11806,21 +11804,21 @@ module mkCore(CLK, csrf_sum_reg, csrf_ppn_reg } ; assign MUX_fetchStage$redirect_1__VAL_1 = - { IF_csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_c_ETC___d22876[38:19], - ~IF_csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_c_ETC___d22876[18:0], - IF_IF_csrf_prv_reg_read__0286_ULE_1_2614_AND_I_ETC___d22894[25:17], - ~IF_IF_csrf_prv_reg_read__0286_ULE_1_2614_AND_I_ETC___d22894[16:15], - IF_IF_csrf_prv_reg_read__0286_ULE_1_2614_AND_I_ETC___d22894[14:3], - ~IF_IF_csrf_prv_reg_read__0286_ULE_1_2614_AND_I_ETC___d22894[2], - IF_IF_csrf_prv_reg_read__0286_ULE_1_2614_AND_I_ETC___d22894[1:0], - thin_address__h999382 } ; + { IF_csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_c_ETC___d22878[38:19], + ~IF_csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_c_ETC___d22878[18:0], + IF_IF_csrf_prv_reg_read__0286_ULE_1_2614_AND_I_ETC___d22896[25:17], + ~IF_IF_csrf_prv_reg_read__0286_ULE_1_2614_AND_I_ETC___d22896[16:15], + IF_IF_csrf_prv_reg_read__0286_ULE_1_2614_AND_I_ETC___d22896[14:3], + ~IF_IF_csrf_prv_reg_read__0286_ULE_1_2614_AND_I_ETC___d22896[2], + IF_IF_csrf_prv_reg_read__0286_ULE_1_2614_AND_I_ETC___d22896[1:0], + thin_address__h999417 } ; always@(rob$deqPort_0_deq_data or - next_pc__h1012222 or v__h1012261 or v__h1012970) + next_pc__h1012257 or v__h1012296 or v__h1013005) begin case (rob$deqPort_0_deq_data[469:465]) - 5'd24: MUX_fetchStage$redirect_1__VAL_5 = v__h1012261; - 5'd25: MUX_fetchStage$redirect_1__VAL_5 = v__h1012970; - default: MUX_fetchStage$redirect_1__VAL_5 = next_pc__h1012222; + 5'd24: MUX_fetchStage$redirect_1__VAL_5 = v__h1012296; + 5'd25: MUX_fetchStage$redirect_1__VAL_5 = v__h1013005; + default: MUX_fetchStage$redirect_1__VAL_5 = next_pc__h1012257; endcase end assign MUX_fetchStage$redirect_1__VAL_6 = @@ -11829,11 +11827,11 @@ module mkCore(CLK, csrf_rg_dpc[54:53], csrf_rg_dpc[55], ~csrf_rg_dpc[52:34], - IF_csrf_rg_dpc_read__6343_BIT_34_4349_THEN_csr_ETC___d24357[25:17], - ~IF_csrf_rg_dpc_read__6343_BIT_34_4349_THEN_csr_ETC___d24357[16:15], - IF_csrf_rg_dpc_read__6343_BIT_34_4349_THEN_csr_ETC___d24357[14:3], - ~IF_csrf_rg_dpc_read__6343_BIT_34_4349_THEN_csr_ETC___d24357[2], - IF_csrf_rg_dpc_read__6343_BIT_34_4349_THEN_csr_ETC___d24357[1:0], + IF_csrf_rg_dpc_read__6343_BIT_34_4351_THEN_csr_ETC___d24359[25:17], + ~IF_csrf_rg_dpc_read__6343_BIT_34_4351_THEN_csr_ETC___d24359[16:15], + IF_csrf_rg_dpc_read__6343_BIT_34_4351_THEN_csr_ETC___d24359[14:3], + ~IF_csrf_rg_dpc_read__6343_BIT_34_4351_THEN_csr_ETC___d24359[2], + IF_csrf_rg_dpc_read__6343_BIT_34_4351_THEN_csr_ETC___d24359[1:0], csrf_rg_dpc[149:86] } ; assign MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_1 = { 1'd1, @@ -11844,7 +11842,7 @@ module mkCore(CLK, assign MUX_mmio_cRqQ_enqReq_lat_0$wset_1__VAL_1 = { 1'd1, mmio_dataReqQ_data_0[214:151], - CASE_mmio_dataReqQ_data_0_BITS_150_TO_149_0_mm_ETC__q331, + CASE_mmio_dataReqQ_data_0_BITS_150_TO_149_0_mm_ETC__q333, mmio_dataReqQ_data_0[144:0] } ; assign MUX_mmio_cRqQ_enqReq_lat_0$wset_1__VAL_2 = { 1'd1, @@ -11867,38 +11865,38 @@ module mkCore(CLK, 112'hAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; assign MUX_rf$write_2_wr_2__VAL_1 = { 1'd0, - res_address__h567346, - res_addrBits__h567347, + res_address__h567343, + res_addrBits__h567344, 72'h00001FFFFF44000000 } ; assign MUX_rf$write_2_wr_2__VAL_2 = { 1'd0, - res_address__h568198, - res_addrBits__h568199, + res_address__h568196, + res_addrBits__h568197, 72'h00001FFFFF44000000 } ; assign MUX_rf$write_2_wr_2__VAL_3 = { 1'd0, - res_address__h613955, - res_addrBits__h613956, + res_address__h613953, + res_addrBits__h613954, 72'h00001FFFFF44000000 } ; assign MUX_rf$write_2_wr_2__VAL_4 = { 1'd0, - res_address__h659702, - res_addrBits__h659703, + res_address__h659700, + res_addrBits__h659701, 72'h00001FFFFF44000000 } ; assign MUX_rf$write_2_wr_2__VAL_5 = { 1'd0, - res_address__h705511, - res_addrBits__h705512, + res_address__h705509, + res_addrBits__h705510, 72'h00001FFFFF44000000 } ; assign MUX_rf$write_2_wr_2__VAL_6 = { 1'd0, - res_address__h706371, - res_addrBits__h706372, + res_address__h706369, + res_addrBits__h706370, 72'h00001FFFFF44000000 } ; assign MUX_rf$write_3_wr_2__VAL_1 = { coreFix_memExe_respLrScAmoQ_data_0[128], - res_address__h126822, - res_addrBits__h126823, + res_address__h126821, + res_addrBits__h126822, coreFix_memExe_respLrScAmoQ_data_0[127:112], coreFix_memExe_respLrScAmoQ_data_0[109], coreFix_memExe_respLrScAmoQ_data_0[111:110], @@ -11906,8 +11904,8 @@ module mkCore(CLK, IF_INV_coreFix_memExe_respLrScAmoQ_data_0_233__ETC___d1273 } ; assign MUX_rf$write_3_wr_2__VAL_2 = { mmio_dataRespQ_data_0[128], - res_address__h139734, - res_addrBits__h139735, + res_address__h139733, + res_addrBits__h139734, mmio_dataRespQ_data_0[127:112], mmio_dataRespQ_data_0[109], mmio_dataRespQ_data_0[111:110], @@ -11916,27 +11914,27 @@ module mkCore(CLK, assign MUX_rf$write_3_wr_2__VAL_3 = { coreFix_memExe_lsq$firstLd[125:110] == 16'd65535 && coreFix_memExe_respLrScAmoQ_data_0[128], - res_address__h178898, - res_addrBits__h178899, - x__h183399[127:112], - x__h183399[109], - x__h183399[111:110], - ~x__h183399[108:90], + res_address__h178896, + res_addrBits__h178897, + x__h183397[127:112], + x__h183397[109], + x__h183397[111:110], + ~x__h183397[108:90], IF_INV_IF_coreFix_memExe_lsq_firstLd__498_BITS_ETC___d1954 } ; assign MUX_rf$write_3_wr_2__VAL_4 = { coreFix_memExe_lsq$firstLd[125:110] == 16'd65535 && mmio_dataRespQ_data_0[128], - res_address__h197663, - res_addrBits__h197664, - x__h199251[127:112], - x__h199251[109], - x__h199251[111:110], - ~x__h199251[108:90], + res_address__h197661, + res_addrBits__h197662, + x__h199249[127:112], + x__h199249[109], + x__h199249[111:110], + ~x__h199249[108:90], IF_INV_IF_coreFix_memExe_lsq_firstLd__498_BITS_ETC___d2120 } ; assign MUX_rf$write_3_wr_2__VAL_5 = { coreFix_memExe_lsq$respLd[128], - res_address__h216422, - res_addrBits__h216423, + res_address__h216420, + res_addrBits__h216421, coreFix_memExe_lsq$respLd[127:112], coreFix_memExe_lsq$respLd[109], coreFix_memExe_lsq$respLd[111:110], @@ -11944,13 +11942,13 @@ module mkCore(CLK, IF_INV_coreFix_memExe_lsq_respLd_159_BITS_108__ETC___d2210 } ; assign MUX_rf$write_4_wr_2__VAL_1 = { 1'd1, - data_address__h1018717, - data_addrBits__h1018718, + data_address__h1018751, + data_addrBits__h1018752, 72'hFFFF1FFFFF44000000 } ; assign MUX_rf$write_4_wr_2__VAL_2 = { 1'd0, - data_address__h1019571, - data_addrBits__h1019572, + data_address__h1019605, + data_addrBits__h1019606, 72'h00001FFFFF44000000 } ; assign MUX_rob$enqPort_0_enq_1__VAL_1 = { fetchStage$pipelines_0_first[591:463], @@ -12005,22 +12003,22 @@ module mkCore(CLK, fetchStage_pipelines_0_first__0256_BIT_167_059_ETC___d21145 } ; assign MUX_rob$setExecuted_deqLSQ_2__VAL_2 = { 1'd1, - CASE_coreFix_memExe_lsqfirstSt_BITS_12_TO_11__ETC__q335 } ; + CASE_coreFix_memExe_lsqfirstSt_BITS_12_TO_11__ETC__q337 } ; assign MUX_rob$setExecuted_deqLSQ_2__VAL_6 = { 1'd1, - CASE_coreFix_memExe_lsqfirstLd_BITS_15_TO_14__ETC__q339 } ; + CASE_coreFix_memExe_lsqfirstLd_BITS_15_TO_14__ETC__q341 } ; assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_2 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[4:0] : - res_fflags__h568239 ; + res_fflags__h568237 ; assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_3 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[4:0] : - res_fflags__h613993 ; + res_fflags__h613991 ; assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_4 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[4:0] : - res_fflags__h659740 ; + res_fflags__h659738 ; // inlined wires assign csrf_minstret_ehr_data_lat_0$whas = @@ -12028,7 +12026,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd2818 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd32 ; assign csrf_minstret_ehr_data_lat_1$whas = WILL_FIRE_RL_commitStage_doCommitSystemInst || @@ -12038,24 +12036,24 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd2816 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd31 ; assign csrf_sepcc_reg_data_lat_1$wget = MUX_csrf_sepcc_reg_data_lat_1$wset_1__SEL_1 ? MUX_csrf_sepcc_reg_data_lat_1$wset_1__VAL_1 : MUX_csrf_sepcc_reg_data_lat_1$wset_1__VAL_2 ; assign csrf_sepcc_reg_data_lat_1$whas = + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo36 || WILL_FIRE_RL_rl_debug_csr_write && - f_csr_reqs$D_OUT[75:64] == 12'd321 || - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo36 ; + f_csr_reqs$D_OUT[75:64] == 12'd321 ; assign csrf_mepcc_reg_data_lat_1$wget = MUX_csrf_mepcc_reg_data_lat_1$wset_1__SEL_1 ? MUX_csrf_mepcc_reg_data_lat_1$wset_1__VAL_1 : MUX_csrf_mepcc_reg_data_lat_1$wset_1__VAL_2 ; assign csrf_mepcc_reg_data_lat_1$whas = + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 || WILL_FIRE_RL_rl_debug_csr_write && - f_csr_reqs$D_OUT[75:64] == 12'd833 || - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; + f_csr_reqs$D_OUT[75:64] == 12'd833 ; assign csrInstOrInterruptInflight_lat_0$whas = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 || @@ -12103,7 +12101,7 @@ module mkCore(CLK, assign mmio_pRqQ_enqReq_lat_0$wget = { 1'd1, mmioToPlatform_pRq_enq_x[38], - CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q340, + CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q342, mmioToPlatform_pRq_enq_x[31:0] } ; assign mmio_cRsQ_enqReq_lat_0$wget = { 1'd1, csrf_software_int_pend_vec_3 } ; @@ -12390,7 +12388,7 @@ module mkCore(CLK, // register commitStage_rg_serial_num always@(MUX_commitStage_rg_serial_num$write_1__SEL_1 or - MUX_commitStage_rg_serial_num$write_1__VAL_2 or + MUX_commitStage_rg_serial_num$write_1__VAL_1 or WILL_FIRE_RL_commitStage_doCommitSystemInst or WILL_FIRE_RL_commitStage_doCommitNormalInst or MUX_commitStage_rg_serial_num$write_1__VAL_3) @@ -12398,10 +12396,10 @@ module mkCore(CLK, case (1'b1) // synopsys parallel_case MUX_commitStage_rg_serial_num$write_1__SEL_1: commitStage_rg_serial_num$D_IN = - MUX_commitStage_rg_serial_num$write_1__VAL_2; + MUX_commitStage_rg_serial_num$write_1__VAL_1; WILL_FIRE_RL_commitStage_doCommitSystemInst: commitStage_rg_serial_num$D_IN = - MUX_commitStage_rg_serial_num$write_1__VAL_2; + MUX_commitStage_rg_serial_num$write_1__VAL_1; WILL_FIRE_RL_commitStage_doCommitNormalInst: commitStage_rg_serial_num$D_IN = MUX_commitStage_rg_serial_num$write_1__VAL_3; @@ -12434,8 +12432,8 @@ module mkCore(CLK, // register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$D_IN = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas ? - v__h837287 : - v__h836642 ; + v__h837284 : + v__h836639 ; assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$EN = 1'd1 ; // register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0 @@ -12533,7 +12531,7 @@ module mkCore(CLK, assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$D_IN = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl ? 3'd0 : - _theResult_____2__h515368 ; + _theResult_____2__h515366 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl @@ -12552,7 +12550,7 @@ module mkCore(CLK, assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$D_IN = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl ? 3'd0 : - v__h514824 ; + v__h514822 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl @@ -12594,7 +12592,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$D_IN = !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl && - _theResult_____2__h526145 ; + _theResult_____2__h526143 ; assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl @@ -12613,7 +12611,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$D_IN = !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl && - v__h516844 ; + v__h516842 ; assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl @@ -12710,7 +12708,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$D_IN = !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl && - _theResult_____2__h533238 ; + _theResult_____2__h533236 ; assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl @@ -12726,7 +12724,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$D_IN = !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl && - v__h532563 ; + v__h532561 ; assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl @@ -12746,7 +12744,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$D_IN = - { x_addr__h535374, + { x_addr__h535372, coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[518:517] : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[518:517], @@ -12773,7 +12771,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$D_IN = !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl && - _theResult_____2__h543873 ; + _theResult_____2__h543871 ; assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl @@ -12792,7 +12790,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$D_IN = !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl && - v__h535012 ; + v__h535010 ; assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl @@ -12868,7 +12866,7 @@ module mkCore(CLK, // register coreFix_memExe_forwardQ_deqP assign coreFix_memExe_forwardQ_deqP$D_IN = !coreFix_memExe_forwardQ_clearReq_rl && - _theResult_____2__h561485 ; + _theResult_____2__h561483 ; assign coreFix_memExe_forwardQ_deqP$EN = 1'd1 ; // register coreFix_memExe_forwardQ_deqReq_rl @@ -12883,7 +12881,7 @@ module mkCore(CLK, // register coreFix_memExe_forwardQ_enqP assign coreFix_memExe_forwardQ_enqP$D_IN = - !coreFix_memExe_forwardQ_clearReq_rl && v__h559811 ; + !coreFix_memExe_forwardQ_clearReq_rl && v__h559809 ; assign coreFix_memExe_forwardQ_enqP$EN = 1'd1 ; // register coreFix_memExe_forwardQ_enqReq_rl @@ -12924,7 +12922,7 @@ module mkCore(CLK, // register coreFix_memExe_memRespLdQ_deqP assign coreFix_memExe_memRespLdQ_deqP$D_IN = !coreFix_memExe_memRespLdQ_clearReq_rl && - _theResult_____2__h557706 ; + _theResult_____2__h557704 ; assign coreFix_memExe_memRespLdQ_deqP$EN = 1'd1 ; // register coreFix_memExe_memRespLdQ_deqReq_rl @@ -12939,7 +12937,7 @@ module mkCore(CLK, // register coreFix_memExe_memRespLdQ_enqP assign coreFix_memExe_memRespLdQ_enqP$D_IN = - !coreFix_memExe_memRespLdQ_clearReq_rl && v__h556032 ; + !coreFix_memExe_memRespLdQ_clearReq_rl && v__h556030 ; assign coreFix_memExe_memRespLdQ_enqP$EN = 1'd1 ; // register coreFix_memExe_memRespLdQ_enqReq_rl @@ -13104,7 +13102,7 @@ module mkCore(CLK, assign csrf_ddc_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd18 && - IF_rob_deqPort_0_deq_data__2261_BIT_294_3454_T_ETC___d23476 == + IF_rob_deqPort_0_deq_data__2261_BIT_294_3456_T_ETC___d23478 == 4'd1 ; // register csrf_external_int_en_vec_0 @@ -13132,7 +13130,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd772 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd23 ; // register csrf_external_int_pend_vec_0 @@ -13183,12 +13181,12 @@ module mkCore(CLK, assign csrf_fflags_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - (IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + (IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd0 || - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd2) || WILL_FIRE_RL_commitStage_doCommitNormalInst && - NOT_IF_NOT_rob_deqPort_0_canDeq__3598_3599_OR__ETC___d23844 || + NOT_IF_NOT_rob_deqPort_0_canDeq__3600_3601_OR__ETC___d23846 || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd1 || f_csr_reqs$D_OUT[75:64] == 12'd3) ; @@ -13201,9 +13199,9 @@ module mkCore(CLK, assign csrf_frm_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - (IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + (IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd1 || - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd2) || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd2 || @@ -13225,7 +13223,7 @@ module mkCore(CLK, assign csrf_fs_reg$EN = MUX_csrf_fs_reg$write_1__SEL_2 || WILL_FIRE_RL_commitStage_doCommitNormalInst && - NOT_IF_NOT_rob_deqPort_0_canDeq__3598_3599_OR__ETC___d23844 || + NOT_IF_NOT_rob_deqPort_0_canDeq__3600_3601_OR__ETC___d23846 || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd1 || f_csr_reqs$D_OUT[75:64] == 12'd2 || @@ -13258,13 +13256,13 @@ module mkCore(CLK, default: csrf_ie_vec_1$D_IN = 1'b0 /* unspecified value */ ; endcase assign csrf_ie_vec_1$EN = + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo40 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && commitStage_commitTrap_2268_BITS_44_TO_43_2461_ETC___d22613 && - csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22647 || + csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22648 || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd256 || - f_csr_reqs$D_OUT[75:64] == 12'd768) || - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo40 ; + f_csr_reqs$D_OUT[75:64] == 12'd768) ; // register csrf_ie_vec_3 always@(MUX_csrf_ie_vec_3$write_1__SEL_1 or @@ -13280,19 +13278,19 @@ module mkCore(CLK, default: csrf_ie_vec_3$D_IN = 1'b0 /* unspecified value */ ; endcase assign csrf_ie_vec_3$EN = + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo30 || WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && commitStage_commitTrap_2268_BITS_44_TO_43_2461_ETC___d22613 && - NOT_csrf_prv_reg_read__0286_ULE_1_2614_2729_OR_ETC___d22734 || - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo30 ; + NOT_csrf_prv_reg_read__0286_ULE_1_2614_2730_OR_ETC___d22736 ; // register csrf_mScratchC_reg assign csrf_mScratchC_reg$D_IN = rob$deqPort_0_deq_data[194:42] ; assign csrf_mScratchC_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd18 && - IF_rob_deqPort_0_deq_data__2261_BIT_294_3454_T_ETC___d23476 == + IF_rob_deqPort_0_deq_data__2261_BIT_294_3456_T_ETC___d23478 == 4'd8 ; // register csrf_mcause_code_reg @@ -13300,14 +13298,14 @@ module mkCore(CLK, MUX_csrf_stval_csr$write_1__VAL_1 or MUX_csrf_mcause_code_reg$write_1__SEL_2 or f_csr_reqs$D_OUT or - MUX_csrf_ie_vec_3$write_1__SEL_3 or cause_code__h995320) + MUX_csrf_ie_vec_3$write_1__SEL_3 or cause_code__h995318) case (1'b1) MUX_csrf_mcause_code_reg$write_1__SEL_1: csrf_mcause_code_reg$D_IN = MUX_csrf_stval_csr$write_1__VAL_1[4:0]; MUX_csrf_mcause_code_reg$write_1__SEL_2: csrf_mcause_code_reg$D_IN = f_csr_reqs$D_OUT[4:0]; MUX_csrf_ie_vec_3$write_1__SEL_3: - csrf_mcause_code_reg$D_IN = cause_code__h995320; + csrf_mcause_code_reg$D_IN = cause_code__h995318; default: csrf_mcause_code_reg$D_IN = 5'b01010 /* unspecified value */ ; endcase assign csrf_mcause_code_reg$EN = @@ -13315,10 +13313,10 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd834 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && commitStage_commitTrap_2268_BITS_44_TO_43_2461_ETC___d22613 && - NOT_csrf_prv_reg_read__0286_ULE_1_2614_2729_OR_ETC___d22734 || + NOT_csrf_prv_reg_read__0286_ULE_1_2614_2730_OR_ETC___d22736 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd28 ; // register csrf_mcause_interrupt_reg @@ -13326,7 +13324,7 @@ module mkCore(CLK, MUX_csrf_stval_csr$write_1__VAL_1 or MUX_csrf_mcause_code_reg$write_1__SEL_2 or f_csr_reqs$D_OUT or - MUX_csrf_ie_vec_3$write_1__SEL_3 or cause_interrupt__h995318) + MUX_csrf_ie_vec_3$write_1__SEL_3 or cause_interrupt__h995316) case (1'b1) MUX_csrf_mcause_code_reg$write_1__SEL_1: csrf_mcause_interrupt_reg$D_IN = @@ -13334,7 +13332,7 @@ module mkCore(CLK, MUX_csrf_mcause_code_reg$write_1__SEL_2: csrf_mcause_interrupt_reg$D_IN = f_csr_reqs$D_OUT[63]; MUX_csrf_ie_vec_3$write_1__SEL_3: - csrf_mcause_interrupt_reg$D_IN = cause_interrupt__h995318; + csrf_mcause_interrupt_reg$D_IN = cause_interrupt__h995316; default: csrf_mcause_interrupt_reg$D_IN = 1'b0 /* unspecified value */ ; endcase assign csrf_mcause_interrupt_reg$EN = @@ -13342,10 +13340,10 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd834 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && commitStage_commitTrap_2268_BITS_44_TO_43_2461_ETC___d22613 && - NOT_csrf_prv_reg_read__0286_ULE_1_2614_2729_OR_ETC___d22734 || + NOT_csrf_prv_reg_read__0286_ULE_1_2614_2730_OR_ETC___d22736 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd28 ; // register csrf_mccsr_reg @@ -13358,7 +13356,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd3008 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd37 ; // register csrf_mcounteren_cy_reg @@ -13371,7 +13369,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd774 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd25 ; // register csrf_mcounteren_ir_reg @@ -13384,7 +13382,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd774 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd25 ; // register csrf_mcounteren_tm_reg @@ -13397,7 +13395,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd774 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd25 ; // register csrf_mcycle_ehr_data_rl @@ -13414,7 +13412,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd770 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd21 ; // register csrf_medeleg_15_reg @@ -13427,7 +13425,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd770 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd21 ; // register csrf_medeleg_28_26_reg @@ -13440,7 +13438,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd770 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd21 ; // register csrf_medeleg_9_0_reg @@ -13453,7 +13451,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd770 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd21 ; // register csrf_mepcc_reg_data_rl @@ -13475,7 +13473,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd771 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd22 ; // register csrf_mideleg_1_0_reg @@ -13488,7 +13486,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd771 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd22 ; // register csrf_mideleg_5_3_reg @@ -13501,7 +13499,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd771 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd22 ; // register csrf_mideleg_9_7_reg @@ -13514,14 +13512,14 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd771 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd22 ; // register csrf_minstret_ehr_data_rl assign csrf_minstret_ehr_data_rl$D_IN = csrf_minstret_ehr_data_lat_1$whas ? upd__h3066 : - n__read__h1014112 ; + n__read__h1014147 ; assign csrf_minstret_ehr_data_rl$EN = 1'd1 ; // register csrf_mpp_reg @@ -13539,12 +13537,12 @@ module mkCore(CLK, default: csrf_mpp_reg$D_IN = 2'b10 /* unspecified value */ ; endcase assign csrf_mpp_reg$EN = + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo30 || WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && commitStage_commitTrap_2268_BITS_44_TO_43_2461_ETC___d22613 && - NOT_csrf_prv_reg_read__0286_ULE_1_2614_2729_OR_ETC___d22734 || - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo30 ; + NOT_csrf_prv_reg_read__0286_ULE_1_2614_2730_OR_ETC___d22736 ; // register csrf_mprv_reg assign csrf_mprv_reg$D_IN = @@ -13556,7 +13554,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd19 ; // register csrf_mscratch_csr @@ -13569,7 +13567,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd832 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd26 ; // register csrf_mtcc_reg @@ -13578,16 +13576,16 @@ module mkCore(CLK, MUX_csrf_mtcc_reg$write_1__VAL_1 : MUX_csrf_mtcc_reg$write_1__VAL_2 ; assign csrf_mtcc_reg$EN = + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 || WILL_FIRE_RL_rl_debug_csr_write && - f_csr_reqs$D_OUT[75:64] == 12'd773 || - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 ; + f_csr_reqs$D_OUT[75:64] == 12'd773 ; // register csrf_mtdc_reg assign csrf_mtdc_reg$D_IN = rob$deqPort_0_deq_data[194:42] ; assign csrf_mtdc_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd18 && - IF_rob_deqPort_0_deq_data__2261_BIT_294_3454_T_ETC___d23476 == + IF_rob_deqPort_0_deq_data__2261_BIT_294_3456_T_ETC___d23478 == 4'd7 ; // register csrf_mtval_csr @@ -13612,10 +13610,10 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd835 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && commitStage_commitTrap_2268_BITS_44_TO_43_2461_ETC___d22613 && - NOT_csrf_prv_reg_read__0286_ULE_1_2614_2729_OR_ETC___d22734 || + NOT_csrf_prv_reg_read__0286_ULE_1_2614_2730_OR_ETC___d22736 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd29 ; // register csrf_mxr_reg @@ -13639,7 +13637,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd384 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd17 ; // register csrf_prev_ie_vec_0 @@ -13668,13 +13666,13 @@ module mkCore(CLK, default: csrf_prev_ie_vec_1$D_IN = 1'b0 /* unspecified value */ ; endcase assign csrf_prev_ie_vec_1$EN = + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo40 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && commitStage_commitTrap_2268_BITS_44_TO_43_2461_ETC___d22613 && - csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22647 || + csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22648 || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd256 || - f_csr_reqs$D_OUT[75:64] == 12'd768) || - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo40 ; + f_csr_reqs$D_OUT[75:64] == 12'd768) ; // register csrf_prev_ie_vec_3 always@(MUX_csrf_prev_ie_vec_3$write_1__SEL_1 or @@ -13691,12 +13689,12 @@ module mkCore(CLK, default: csrf_prev_ie_vec_3$D_IN = 1'b0 /* unspecified value */ ; endcase assign csrf_prev_ie_vec_3$EN = + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo30 || WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && commitStage_commitTrap_2268_BITS_44_TO_43_2461_ETC___d22613 && - NOT_csrf_prv_reg_read__0286_ULE_1_2614_2729_OR_ETC___d22734 || - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo30 ; + NOT_csrf_prv_reg_read__0286_ULE_1_2614_2730_OR_ETC___d22736 ; // register csrf_prv_reg always@(MUX_csrf_prv_reg$write_1__SEL_1 or @@ -13715,11 +13713,11 @@ module mkCore(CLK, default: csrf_prv_reg$D_IN = 2'b10 /* unspecified value */ ; endcase assign csrf_prv_reg$EN = + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo24 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && commitStage_commitTrap_2268_BITS_44_TO_43_2461_ETC___d22613 || WILL_FIRE_RL_rl_debug_csr_write && - f_csr_reqs$D_OUT[75:64] == 12'd1968 || - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo24 ; + f_csr_reqs$D_OUT[75:64] == 12'd1968 ; // register csrf_rg_dcsr always@(MUX_csrf_rg_dcsr$write_1__SEL_1 or @@ -13745,7 +13743,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1968 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd42 ; // register csrf_rg_dpc @@ -13772,7 +13770,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1969 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd43 ; // register csrf_rg_dscratch0 @@ -13785,7 +13783,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1970 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd44 ; // register csrf_rg_dscratch1 @@ -13798,7 +13796,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1971 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd45 ; // register csrf_rg_tdata1_data @@ -13811,7 +13809,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1953 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd39 ; // register csrf_rg_tdata1_dmode @@ -13824,7 +13822,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1953 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd39 ; // register csrf_rg_tdata2 @@ -13837,7 +13835,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1954 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd40 ; // register csrf_rg_tdata3 @@ -13850,7 +13848,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1955 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd41 ; // register csrf_rg_tselect @@ -13863,7 +13861,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1952 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd38 ; // register csrf_sScratchC_reg @@ -13871,7 +13869,7 @@ module mkCore(CLK, assign csrf_sScratchC_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd18 && - IF_rob_deqPort_0_deq_data__2261_BIT_294_3454_T_ETC___d23476 == + IF_rob_deqPort_0_deq_data__2261_BIT_294_3456_T_ETC___d23478 == 4'd4 ; // register csrf_scause_code_reg @@ -13879,14 +13877,14 @@ module mkCore(CLK, MUX_csrf_stval_csr$write_1__VAL_1 or MUX_csrf_scause_code_reg$write_1__SEL_2 or f_csr_reqs$D_OUT or - MUX_csrf_ie_vec_1$write_1__SEL_3 or cause_code__h995320) + MUX_csrf_ie_vec_1$write_1__SEL_3 or cause_code__h995318) case (1'b1) MUX_csrf_scause_code_reg$write_1__SEL_1: csrf_scause_code_reg$D_IN = MUX_csrf_stval_csr$write_1__VAL_1[4:0]; MUX_csrf_scause_code_reg$write_1__SEL_2: csrf_scause_code_reg$D_IN = f_csr_reqs$D_OUT[4:0]; MUX_csrf_ie_vec_1$write_1__SEL_3: - csrf_scause_code_reg$D_IN = cause_code__h995320; + csrf_scause_code_reg$D_IN = cause_code__h995318; default: csrf_scause_code_reg$D_IN = 5'b01010 /* unspecified value */ ; endcase assign csrf_scause_code_reg$EN = @@ -13894,10 +13892,10 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd322 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && commitStage_commitTrap_2268_BITS_44_TO_43_2461_ETC___d22613 && - csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22647 || + csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22648 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd14 ; // register csrf_scause_interrupt_reg @@ -13905,7 +13903,7 @@ module mkCore(CLK, MUX_csrf_stval_csr$write_1__VAL_1 or MUX_csrf_scause_code_reg$write_1__SEL_2 or f_csr_reqs$D_OUT or - MUX_csrf_ie_vec_1$write_1__SEL_3 or cause_interrupt__h995318) + MUX_csrf_ie_vec_1$write_1__SEL_3 or cause_interrupt__h995316) case (1'b1) MUX_csrf_scause_code_reg$write_1__SEL_1: csrf_scause_interrupt_reg$D_IN = @@ -13913,7 +13911,7 @@ module mkCore(CLK, MUX_csrf_scause_code_reg$write_1__SEL_2: csrf_scause_interrupt_reg$D_IN = f_csr_reqs$D_OUT[63]; MUX_csrf_ie_vec_1$write_1__SEL_3: - csrf_scause_interrupt_reg$D_IN = cause_interrupt__h995318; + csrf_scause_interrupt_reg$D_IN = cause_interrupt__h995316; default: csrf_scause_interrupt_reg$D_IN = 1'b0 /* unspecified value */ ; endcase assign csrf_scause_interrupt_reg$EN = @@ -13921,10 +13919,10 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd322 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && commitStage_commitTrap_2268_BITS_44_TO_43_2461_ETC___d22613 && - csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22647 || + csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22648 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd14 ; // register csrf_scounteren_cy_reg @@ -13937,7 +13935,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd262 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd11 ; // register csrf_scounteren_ir_reg @@ -13950,7 +13948,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd262 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd11 ; // register csrf_scounteren_tm_reg @@ -13963,7 +13961,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd262 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd11 ; // register csrf_sepcc_reg_data_rl @@ -14000,7 +13998,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd772 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd23 ; // register csrf_software_int_pend_vec_0 @@ -14042,13 +14040,13 @@ module mkCore(CLK, default: csrf_spp_reg$D_IN = 1'b0 /* unspecified value */ ; endcase assign csrf_spp_reg$EN = + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo40 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && commitStage_commitTrap_2268_BITS_44_TO_43_2461_ETC___d22613 && - csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22647 || + csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22648 || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd256 || - f_csr_reqs$D_OUT[75:64] == 12'd768) || - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo40 ; + f_csr_reqs$D_OUT[75:64] == 12'd768) ; // register csrf_sscratch_csr assign csrf_sscratch_csr$D_IN = @@ -14060,7 +14058,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd320 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd12 ; // register csrf_stats_module_doStats @@ -14073,16 +14071,16 @@ module mkCore(CLK, MUX_csrf_stcc_reg$write_1__VAL_1 : MUX_csrf_stcc_reg$write_1__VAL_2 ; assign csrf_stcc_reg$EN = + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo38 || WILL_FIRE_RL_rl_debug_csr_write && - f_csr_reqs$D_OUT[75:64] == 12'd261 || - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo38 ; + f_csr_reqs$D_OUT[75:64] == 12'd261 ; // register csrf_stdc_reg assign csrf_stdc_reg$D_IN = rob$deqPort_0_deq_data[194:42] ; assign csrf_stdc_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd18 && - IF_rob_deqPort_0_deq_data__2261_BIT_294_3454_T_ETC___d23476 == + IF_rob_deqPort_0_deq_data__2261_BIT_294_3456_T_ETC___d23478 == 4'd3 ; // register csrf_stval_csr @@ -14107,10 +14105,10 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd323 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && commitStage_commitTrap_2268_BITS_44_TO_43_2461_ETC___d22613 && - csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22647 || + csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22648 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd15 ; // register csrf_sum_reg @@ -14153,7 +14151,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd772 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd23 ; // register csrf_timer_int_pend_vec_0 @@ -14187,7 +14185,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd19 ; // register csrf_tvm_reg @@ -14200,7 +14198,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd19 ; // register csrf_tw_reg @@ -14213,7 +14211,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd19 ; // register csrf_vm_mode_sv39_reg @@ -14226,7 +14224,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd384 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd17 ; // register flush_brpred @@ -14244,10 +14242,10 @@ module mkCore(CLK, WILL_FIRE_RL_flushCaches ; // register flush_reservation - assign flush_reservation$D_IN = !MUX_flush_reservation$write_1__SEL_1 ; + assign flush_reservation$D_IN = !MUX_flush_reservation$write_1__SEL_2 ; assign flush_reservation$EN = - WILL_FIRE_RL_prepareCachesAndTlbs && flush_reservation || WILL_FIRE_RL_commitStage_doCommitTrap_handle && _dfoo20 || + WILL_FIRE_RL_prepareCachesAndTlbs && flush_reservation || WILL_FIRE_RL_commitStage_doCommitSystemInst ; // register flush_tlbs @@ -14259,7 +14257,7 @@ module mkCore(CLK, WILL_FIRE_RL_commitStage_doCommitSystemInst && (rob$deqPort_0_deq_data[469:465] == 5'd21 || rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd17) ; // register mmio_cRqQ_clearReq_rl @@ -14626,19 +14624,19 @@ module mkCore(CLK, assign update_vm_info$D_IN = !MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1 ; assign update_vm_info$EN = - WILL_FIRE_RL_prepareCachesAndTlbs && update_vm_info || WILL_FIRE_RL_commitStage_doCommitTrap_handle && _dfoo20 || + WILL_FIRE_RL_prepareCachesAndTlbs && update_vm_info || WILL_FIRE_RL_commitStage_doCommitSystemInst ; // submodule coreFix_aluExe_0_dispToRegQ assign coreFix_aluExe_0_dispToRegQ$enq_x = { coreFix_aluExe_0_rsAlu$dispatchData[234:230], - CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q342, - CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q343, - coreFix_aluExe_0_rsAlu$dispatchData[188:141], CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q344, - coreFix_aluExe_0_rsAlu$dispatchData[128], CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q345, + coreFix_aluExe_0_rsAlu$dispatchData[188:141], + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q346, + coreFix_aluExe_0_rsAlu$dispatchData[128], + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q347, coreFix_aluExe_0_rsAlu$dispatchData[122:90], coreFix_aluExe_0_rsAlu$dispatchData[65:21], coreFix_aluExe_0_rsAlu$dispatchData[89:66], @@ -14692,7 +14690,7 @@ module mkCore(CLK, coreFix_aluExe_0_regToExeQ$first[822:818] == 5'd18, basicExec___d19859[932:770], basicExec___d19859[606:271], - CASE_basicExec_9859_BITS_270_TO_266_0_basicExe_ETC__q346, + CASE_basicExec_9859_BITS_270_TO_266_0_basicExe_ETC__q348, basicExec___d19859[265:0], coreFix_aluExe_0_regToExeQ$first[16:0] } ; assign coreFix_aluExe_0_exeToFinQ$specUpdate_correctSpeculation_mask = @@ -14734,12 +14732,12 @@ module mkCore(CLK, // submodule coreFix_aluExe_0_regToExeQ assign coreFix_aluExe_0_regToExeQ$enq_x = { coreFix_aluExe_0_dispToRegQ$first[230:226], - CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_22_ETC__q348, - CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_19_ETC__q349, + CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_22_ETC__q350, + CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_19_ETC__q351, coreFix_aluExe_0_dispToRegQ$first[184:137], - CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q350, + CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q352, coreFix_aluExe_0_dispToRegQ$first[124], - CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_12_ETC__q351, + CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_12_ETC__q353, coreFix_aluExe_0_dispToRegQ$first[118:86], coreFix_aluExe_0_dispToRegQ$first[61:17], NOT_coreFix_aluExe_0_dispToRegQ_first__8383_BI_ETC___d19448, @@ -14877,11 +14875,11 @@ module mkCore(CLK, endcase end assign coreFix_aluExe_0_rsAlu$EN_enq = + WILL_FIRE_RL_renameStage_doRenaming && _dfoo18 || WILL_FIRE_RL_renameStage_doRenaming_SystemInst && (fetchStage$pipelines_0_first[268:266] == 3'd0 || fetchStage$pipelines_0_first[238:237] == 2'd1 || - fetchStage$pipelines_0_first[238:237] == 2'd0) || - WILL_FIRE_RL_renameStage_doRenaming && _dfoo18 ; + fetchStage$pipelines_0_first[238:237] == 2'd0) ; assign coreFix_aluExe_0_rsAlu$EN_setRobEnqTime = 1'd1 ; assign coreFix_aluExe_0_rsAlu$EN_doDispatch = WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu ; @@ -14934,12 +14932,12 @@ module mkCore(CLK, // submodule coreFix_aluExe_1_dispToRegQ assign coreFix_aluExe_1_dispToRegQ$enq_x = { coreFix_aluExe_1_rsAlu$dispatchData[234:230], - CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q353, - CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q354, - coreFix_aluExe_1_rsAlu$dispatchData[188:141], CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q355, - coreFix_aluExe_1_rsAlu$dispatchData[128], CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q356, + coreFix_aluExe_1_rsAlu$dispatchData[188:141], + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q357, + coreFix_aluExe_1_rsAlu$dispatchData[128], + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q358, coreFix_aluExe_1_rsAlu$dispatchData[122:90], coreFix_aluExe_1_rsAlu$dispatchData[65:21], coreFix_aluExe_1_rsAlu$dispatchData[89:66], @@ -14992,7 +14990,7 @@ module mkCore(CLK, coreFix_aluExe_1_regToExeQ$first[822:818] == 5'd18, basicExec___d17743[932:770], basicExec___d17743[606:271], - CASE_basicExec_7743_BITS_270_TO_266_0_basicExe_ETC__q357, + CASE_basicExec_7743_BITS_270_TO_266_0_basicExe_ETC__q359, basicExec___d17743[265:0], coreFix_aluExe_1_regToExeQ$first[16:0] } ; assign coreFix_aluExe_1_exeToFinQ$specUpdate_correctSpeculation_mask = @@ -15034,12 +15032,12 @@ module mkCore(CLK, // submodule coreFix_aluExe_1_regToExeQ assign coreFix_aluExe_1_regToExeQ$enq_x = { coreFix_aluExe_1_dispToRegQ$first[230:226], - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_22_ETC__q359, - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_19_ETC__q360, + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_22_ETC__q361, + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_19_ETC__q362, coreFix_aluExe_1_dispToRegQ$first[184:137], - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q361, + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q363, coreFix_aluExe_1_dispToRegQ$first[124], - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_12_ETC__q362, + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_12_ETC__q364, coreFix_aluExe_1_dispToRegQ$first[118:86], coreFix_aluExe_1_dispToRegQ$first[61:17], NOT_coreFix_aluExe_1_dispToRegQ_first__5620_BI_ETC___d17332, @@ -15081,7 +15079,7 @@ module mkCore(CLK, // submodule coreFix_aluExe_1_rsAlu assign coreFix_aluExe_1_rsAlu$enq_x = - (k__h945030 == 1'd1 && fetchStage$pipelines_0_canDeq && + (k__h945028 == 1'd1 && fetchStage$pipelines_0_canDeq && NOT_fetchStage_pipelines_0_first__0256_BITS_26_ETC___d22015) ? { fetchStage$pipelines_0_first[273:269], IF_fetchStage_pipelines_0_first__0256_BITS_268_ETC___d20382, @@ -15099,7 +15097,7 @@ module mkCore(CLK, fetchStage$pipelines_1_first[329:306], regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h968741, + renaming_spec_bits__h968739, fetchStage$pipelines_1_first[268:266] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -15248,7 +15246,7 @@ module mkCore(CLK, // submodule coreFix_fpuMulDivExe_0_dispToRegQ assign coreFix_fpuMulDivExe_0_dispToRegQ$enq_x = - { CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q364, + { CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q366, coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[65:9] } ; assign coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_correctSpeculation_mask = IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d20197 ; @@ -15360,8 +15358,8 @@ module mkCore(CLK, assign coreFix_fpuMulDivExe_0_fpuExec_double_fma$request_put = { coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd2, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14095, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q365, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q366, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q367, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q368, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14868 } ; assign coreFix_fpuMulDivExe_0_fpuExec_double_fma$EN_request_put = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && @@ -15578,19 +15576,19 @@ module mkCore(CLK, // submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tdata = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? - _theResult___fst__h836129 : - a__h835707 ; + _theResult___fst__h836126 : + a__h835704 ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tuser = - { b__h835708 == 64'd0, - a__h835707, + { b__h835705 == 64'd0, + a__h835704, coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0, - x__h836143, - a__h835707[63], + x__h836140, + a__h835704[63], 8'd0 } ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_divisor_tdata = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? - _theResult___snd__h836130 : - b__h835708 ; + _theResult___snd__h836127 : + b__h835705 ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tvalid = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && coreFix_fpuMulDivExe_0_regToExeQ$first[254:252] == 3'd3 && @@ -15651,20 +15649,20 @@ module mkCore(CLK, 1'd1 ; // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned - assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$A = a__h835707 ; - assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$B = b__h835708 ; + assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$A = a__h835704 ; + assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$B = b__h835705 ; // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned$A = - a__h835707 ; + a__h835704 ; assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned$B = - b__h835708 ; + b__h835705 ; // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned$A = - a__h835707 ; + a__h835704 ; assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned$B = - b__h835708 ; + b__h835705 ; // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ always@(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1 or @@ -15691,11 +15689,11 @@ module mkCore(CLK, // submodule coreFix_fpuMulDivExe_0_regToExeQ assign coreFix_fpuMulDivExe_0_regToExeQ$enq_x = - { CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q368, + { CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q370, coreFix_fpuMulDivExe_0_dispToRegQ$first[32:12], - x__h714429, - x__h714430, - x__h714431, + x__h714426, + x__h714427, + x__h714428, coreFix_fpuMulDivExe_0_dispToRegQ$first[11:0] } ; assign coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_correctSpeculation_mask = IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d20197 ; @@ -15747,7 +15745,7 @@ module mkCore(CLK, { IF_fetchStage_pipelines_1_first__0265_BITS_268_ETC___d21343, regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h968741, + renaming_spec_bits__h968739, fetchStage$pipelines_1_first[268:266] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -15901,7 +15899,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget : coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq_n = - x__h501097 ; + x__h501096 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n = (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[583:582] == 2'd0) ? @@ -16011,7 +16009,7 @@ module mkCore(CLK, // submodule coreFix_memExe_dMem_cache_m_banks_0_pRqMshr assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit_r = { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d7056, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q369 } ; + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q371 } ; assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq_n = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[580:579] ; assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getState_n = @@ -16333,7 +16331,7 @@ module mkCore(CLK, (fetchStage$pipelines_0_canDeq && regRenamingTable_rename_0_canRename__1151_AND__ETC___d22059) ? specTagManager$currentSpecBits : - renaming_spec_bits__h968741 ; + renaming_spec_bits__h968739 ; assign coreFix_memExe_lsq$enqSt_dst = (fetchStage$pipelines_0_canDeq && regRenamingTable_rename_0_canRename__1151_AND__ETC___d22068) ? @@ -16353,7 +16351,7 @@ module mkCore(CLK, (fetchStage$pipelines_0_canDeq && regRenamingTable_rename_0_canRename__1151_AND__ETC___d22068) ? specTagManager$currentSpecBits : - renaming_spec_bits__h968741 ; + renaming_spec_bits__h968739 ; assign coreFix_memExe_lsq$getHit_t = MUX_coreFix_memExe_lsq$getHit_1__SEL_1 ? MUX_coreFix_memExe_lsq$getHit_1__VAL_1 : @@ -16382,8 +16380,8 @@ module mkCore(CLK, MUX_coreFix_memExe_lsq$respLd_2__VAL_2 ; assign coreFix_memExe_lsq$respLd_t = WILL_FIRE_RL_coreFix_memExe_doRespLdMem ? - t__h212841 : - t__h215127 ; + t__h212839 : + t__h215125 ; assign coreFix_memExe_lsq$setAtCommit_0_put = rob$deqPort_0_deq_data[24:19] ; assign coreFix_memExe_lsq$setAtCommit_1_put = @@ -16436,7 +16434,7 @@ module mkCore(CLK, ~IF_coreFix_memExe_regToExeQ_first__645_BIT_103_ETC___d4017[2], IF_coreFix_memExe_regToExeQ_first__645_BIT_103_ETC___d4017[1:0], coreFix_memExe_regToExeQ$first[218:155] } : - { pointer__h242638[3:0] == 4'd0 && + { pointer__h242635[3:0] == 4'd0 && coreFix_memExe_lsq$getOrigBE[0] && coreFix_memExe_lsq$getOrigBE[1] && coreFix_memExe_lsq$getOrigBE[2] && @@ -16606,7 +16604,7 @@ module mkCore(CLK, !fetchStage$pipelines_1_first[239], regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h968741, + renaming_spec_bits__h968739, fetchStage$pipelines_1_first[268:266] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -16828,7 +16826,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd2049 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd7 ; assign csrf_stats_module_writeQ$DEQ = EN_sendDoStats ; assign csrf_stats_module_writeQ$CLR = 1'b0 ; @@ -16839,7 +16837,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd2048 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd6 ; assign csrf_terminate_module_terminateQ$DEQ = EN_coreIndInv_terminate ; assign csrf_terminate_module_terminateQ$CLR = 1'b0 ; @@ -17019,9 +17017,9 @@ module mkCore(CLK, always@(MUX_commitStage_rg_serial_num$write_1__SEL_1 or MUX_fetchStage$redirect_1__VAL_1 or WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or - new_pc__h872925 or + new_pc__h872924 or WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or - new_pc__h912073 or + new_pc__h912071 or WILL_FIRE_RL_commitStage_doCommitKilledLd or rob$deqPort_0_deq_data or WILL_FIRE_RL_commitStage_doCommitSystemInst or @@ -17032,9 +17030,9 @@ module mkCore(CLK, MUX_commitStage_rg_serial_num$write_1__SEL_1: fetchStage$redirect_pc = MUX_fetchStage$redirect_1__VAL_1; WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T: - fetchStage$redirect_pc = new_pc__h872925; + fetchStage$redirect_pc = new_pc__h872924; WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T: - fetchStage$redirect_pc = new_pc__h912073; + fetchStage$redirect_pc = new_pc__h912071; WILL_FIRE_RL_commitStage_doCommitKilledLd: fetchStage$redirect_pc = rob$deqPort_0_deq_data[630:502]; WILL_FIRE_RL_commitStage_doCommitSystemInst: @@ -17224,7 +17222,7 @@ module mkCore(CLK, assign regRenamingTable$rename_1_claimRename_r = fetchStage$pipelines_1_first[96:70] ; assign regRenamingTable$rename_1_claimRename_sb = - renaming_spec_bits__h968741 ; + renaming_spec_bits__h968739 ; assign regRenamingTable$rename_1_getRename_r = fetchStage$pipelines_1_first[96:70] ; assign regRenamingTable$specUpdate_correctSpeculation_mask = @@ -17501,7 +17499,7 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__0265_BITS_265_ETC___d22188, IF_NOT_fetchStage_pipelines_1_first__0265_BITS_ETC___d22242, 7'd32, - renaming_spec_bits__h968741 } ; + renaming_spec_bits__h968739 } ; assign rob$getOrigPC_0_get_x = coreFix_aluExe_0_dispToRegQ$first[52:41] ; assign rob$getOrigPC_1_get_x = coreFix_aluExe_1_dispToRegQ$first[52:41] ; assign rob$getOrigPC_2_get_x = 12'h0 ; @@ -17585,29 +17583,29 @@ module mkCore(CLK, always@(WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple or coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first or WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma or - data__h567680 or + data__h567678 or WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv or - data__h613440 or + data__h613438 or WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt or - data__h659187 or + data__h659185 or WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul or - data__h705001 or - WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv or data__h705864) + data__h704999 or + WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv or data__h705862) begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple: rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[101:38]; WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma: - rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = data__h567680; + rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = data__h567678; WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv: - rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = data__h613440; + rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = data__h613438; WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt: - rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = data__h659187; + rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = data__h659185; WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul: - rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = data__h705001; + rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = data__h704999; WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv: - rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = data__h705864; + rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = data__h705862; default: rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase @@ -18064,11 +18062,11 @@ module mkCore(CLK, module_amoExec instance_amoExec_5(.amoExec_amo_inst({ mmio_pRqQ_data_0[35:32], 4'd8 }), .amoExec_wordIdx(2'd0), - .amoExec_current({ 128'd0, r__h855583 }), + .amoExec_current({ 128'd0, r__h855582 }), .amoExec_inpt({ 97'd0, x__h65639 }), .amoExec(amoExec___d773)); module_amoExec instance_amoExec_4(.amoExec_amo_inst(coreFix_memExe_dMem_cache_m_banks_0_processAmo[11:4]), - .amoExec_wordIdx(wordIdx__h263233), + .amoExec_wordIdx(wordIdx__h263231), .amoExec_current({ SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4854, { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4861, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4867 } }), @@ -18085,12 +18083,12 @@ module mkCore(CLK, fetchStage$pipelines_0_first[81:77], { fetchStage$pipelines_0_first[76], fetchStage$pipelines_0_first[75:70] } } }), - .checkForException_csrState({ x_decodeInfo_frm__h926248, - r1__read_BITS_13_TO_12___h926454 != + .checkForException_csrState({ x_decodeInfo_frm__h926246, + r1__read_BITS_13_TO_12___h926452 != 2'd0, - { prv__h1017409, + { prv__h1017444, csrf_tvm_reg, - { r1__read_BIT_20___h926960, + { r1__read_BIT_20___h926958, csrf_tsr_reg, { csrf_mcounteren_cy_reg, csrf_mcounteren_cy_reg && @@ -18116,12 +18114,12 @@ module mkCore(CLK, fetchStage$pipelines_1_first[81:77], { fetchStage$pipelines_1_first[76], fetchStage$pipelines_1_first[75:70] } } }), - .checkForException_csrState({ x_decodeInfo_frm__h926248, - r1__read_BITS_13_TO_12___h926454 != + .checkForException_csrState({ x_decodeInfo_frm__h926246, + r1__read_BITS_13_TO_12___h926452 != 2'd0, - { prv__h1017409, + { prv__h1017444, csrf_tvm_reg, - { r1__read_BIT_20___h926960, + { r1__read_BIT_20___h926958, csrf_tsr_reg, { csrf_mcounteren_cy_reg, csrf_mcounteren_cy_reg && @@ -18132,14 +18130,14 @@ module mkCore(CLK, { csrf_mcounteren_tm_reg, csrf_mcounteren_tm_reg && csrf_scounteren_tm_reg } } } } } }), - .checkForException_pcc(pc__h963242), + .checkForException_pcc(pc__h963240), .checkForException_fourByteInst(fetchStage$pipelines_1_first[98:97] == 2'b11), .checkForException(checkForException___d21604)); module_capChecks instance_capChecks_0(.capChecks_a(coreFix_memExe_regToExeQ$first[384:222]), .capChecks_b(coreFix_memExe_regToExeQ$first[221:59]), .capChecks_ddc({ csrf_ddc_reg, - repBound__h248743, + repBound__h248740, { csrf_ddc_reg_read__051_BITS_27_TO_25_142_ULT_c_ETC___d4143, csrf_ddc_reg_read__051_BITS_13_TO_11_140_ULT_c_ETC___d4144, csrf_ddc_reg_read__051_BITS_85_TO_83_145_ULT_c_ETC___d4156 } }), @@ -18150,84 +18148,84 @@ module mkCore(CLK, .prepareBoundsCheck_b(coreFix_memExe_regToExeQ$first[221:59]), .prepareBoundsCheck_pcc(163'h400000000000000000003FFFC7FFFFD10000003F0), .prepareBoundsCheck_ddc({ csrf_ddc_reg, - repBound__h248743, + repBound__h248740, { csrf_ddc_reg_read__051_BITS_27_TO_25_142_ULT_c_ETC___d4143, csrf_ddc_reg_read__051_BITS_13_TO_11_140_ULT_c_ETC___d4144, csrf_ddc_reg_read__051_BITS_85_TO_83_145_ULT_c_ETC___d4156 } }), - .prepareBoundsCheck_vaddr(tmpAddr__h242837), - .prepareBoundsCheck_size(x__h249478 + - y__h249479), + .prepareBoundsCheck_vaddr(tmpAddr__h242834), + .prepareBoundsCheck_size(x__h249475 + + y__h249476), .prepareBoundsCheck_toCheck(coreFix_memExe_regToExeQ$first[58:12]), .prepareBoundsCheck(prepareBoundsCheck___d4244)); module_execFpuSimple instance_execFpuSimple_3(.execFpuSimple_fpu_inst({ coreFix_fpuMulDivExe_0_regToExeQ$first[233:229], - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q281, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q283, coreFix_fpuMulDivExe_0_regToExeQ$first[225] }), - .execFpuSimple_rVal1(rVal1__h714520), - .execFpuSimple_rVal2(rVal2__h714521), + .execFpuSimple_rVal1(rVal1__h714517), + .execFpuSimple_rVal2(rVal2__h714518), .execFpuSimple(execFpuSimple___d15207)); module_basicExec instance_basicExec_8(.basicExec_dInst({ coreFix_aluExe_1_regToExeQ$first[822:818], - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_817_ETC__q283, - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_787_ETC__q284, + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_817_ETC__q285, + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_787_ETC__q286, coreFix_aluExe_1_regToExeQ$first[776:729], - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_728_ETC__q285, + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_728_ETC__q287, coreFix_aluExe_1_regToExeQ$first[716], - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_715_ETC__q286, + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_715_ETC__q288, coreFix_aluExe_1_regToExeQ$first[710:678] }), .basicExec_rVal1(coreFix_aluExe_1_regToExeQ$first[632:470]), .basicExec_rVal2(coreFix_aluExe_1_regToExeQ$first[469:307]), .basicExec_pcc({ coreFix_aluExe_1_regToExeQ$first[306], - { cr_address__h866671, - cr_addrBits__h866672, + { cr_address__h866670, + cr_addrBits__h866671, { coreFix_aluExe_1_regToExeQ$first[305:290], - { cr_flags__h866674, - cr_reserved__h866675 }, + { cr_flags__h866673, + cr_reserved__h866674 }, INV_coreFix_aluExe_1_regToExeQ_first__7341_BIT_ETC___d17655 } }, - repBound__h867140, + repBound__h867139, { IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17662, IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17663, IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17675 } }), .basicExec_ppc({ coreFix_aluExe_1_regToExeQ$first[177], - { cr_address__h867219, - cr_addrBits__h867220, + { cr_address__h867218, + cr_addrBits__h867219, { coreFix_aluExe_1_regToExeQ$first[176:161], - { cr_flags__h867222, - cr_reserved__h867223 }, + { cr_flags__h867221, + cr_reserved__h867222 }, INV_coreFix_aluExe_1_regToExeQ_first__7341_BIT_ETC___d17719 } }, - repBound__h867688, + repBound__h867687, { IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17726, IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17727, IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17739 } }), .basicExec_orig_inst(coreFix_aluExe_1_regToExeQ$first[48:17]), .basicExec(basicExec___d17743)); module_basicExec instance_basicExec_7(.basicExec_dInst({ coreFix_aluExe_0_regToExeQ$first[822:818], - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_817_ETC__q288, - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_787_ETC__q289, + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_817_ETC__q290, + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_787_ETC__q291, coreFix_aluExe_0_regToExeQ$first[776:729], - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_728_ETC__q290, + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_728_ETC__q292, coreFix_aluExe_0_regToExeQ$first[716], - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_715_ETC__q291, + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_715_ETC__q293, coreFix_aluExe_0_regToExeQ$first[710:678] }), .basicExec_rVal1(coreFix_aluExe_0_regToExeQ$first[632:470]), .basicExec_rVal2(coreFix_aluExe_0_regToExeQ$first[469:307]), .basicExec_pcc({ coreFix_aluExe_0_regToExeQ$first[306], - { cr_address__h906357, - cr_addrBits__h906358, + { cr_address__h906355, + cr_addrBits__h906356, { coreFix_aluExe_0_regToExeQ$first[305:290], - { cr_flags__h906360, - cr_reserved__h906361 }, + { cr_flags__h906358, + cr_reserved__h906359 }, INV_coreFix_aluExe_0_regToExeQ_first__9457_BIT_ETC___d19771 } }, - repBound__h906826, + repBound__h906824, { IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19778, IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19779, IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19791 } }), .basicExec_ppc({ coreFix_aluExe_0_regToExeQ$first[177], - { cr_address__h906905, - cr_addrBits__h906906, + { cr_address__h906903, + cr_addrBits__h906904, { coreFix_aluExe_0_regToExeQ$first[176:161], - { cr_flags__h906908, - cr_reserved__h906909 }, + { cr_flags__h906906, + cr_reserved__h906907 }, INV_coreFix_aluExe_0_regToExeQ_first__9457_BIT_ETC___d19835 } }, - repBound__h907374, + repBound__h907372, { IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19842, IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19843, IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19855 } }), @@ -18235,1191 +18233,1191 @@ module mkCore(CLK, .basicExec(basicExec___d19859)); assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q110 = _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d11166 ? - _theResult___snd__h676124 : - _theResult____h667952 ; + _theResult___snd__h676122 : + _theResult____h667950 ; assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q40 = _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d8372 ? - _theResult___snd__h584628 : - _theResult____h576454 ; + _theResult___snd__h584626 : + _theResult____h576452 ; assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q75 = _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d9769 ? - _theResult___snd__h630377 : - _theResult____h622205 ; + _theResult___snd__h630375 : + _theResult____h622203 ; assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q150 = _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d13048 ? - _theResult___snd__h743927 : - _theResult____h735628 ; + _theResult___snd__h743924 : + _theResult____h735625 ; assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q167 = _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d13763 ? - _theResult___snd__h822084 : - _theResult____h813785 ; + _theResult___snd__h822081 : + _theResult____h813782 ; assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q190 = _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14533 ? - _theResult___snd__h782780 : - _theResult____h774481 ; + _theResult___snd__h782777 : + _theResult____h774478 ; assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q120 = _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d11717 ? - _theResult___snd__h693890 : - _theResult____h685589 ; + _theResult___snd__h693888 : + _theResult____h685587 ; assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q50 = _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d8923 ? - _theResult___snd__h602394 : - _theResult____h594093 ; + _theResult___snd__h602392 : + _theResult____h594091 ; assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q85 = _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d10320 ? - _theResult___snd__h648143 : - _theResult____h639842 ; + _theResult___snd__h648141 : + _theResult____h639840 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q146 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d12736 ? - _theResult___snd__h734276 : + _theResult___snd__h734273 : 57'd0 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q153 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d13098 ? - _theResult___snd__h734276 : - _theResult___snd__h752681 ; + _theResult___snd__h734273 : + _theResult___snd__h752678 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q163 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d13466 ? - _theResult___snd__h812433 : + _theResult___snd__h812430 : 57'd0 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q170 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d13813 ? - _theResult___snd__h812433 : - _theResult___snd__h830838 ; + _theResult___snd__h812430 : + _theResult___snd__h830835 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q186 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14236 ? - _theResult___snd__h773129 : + _theResult___snd__h773126 : 57'd0 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q193 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14583 ? - _theResult___snd__h773129 : - _theResult___snd__h791534 ; + _theResult___snd__h773126 : + _theResult___snd__h791531 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q112 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d11397 ? - _theResult___snd__h684706 : + _theResult___snd__h684704 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q125 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d11790 ? - _theResult___snd__h684706 : - _theResult___snd__h702496 ; + _theResult___snd__h684704 : + _theResult___snd__h702494 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q42 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d8603 ? - _theResult___snd__h593210 : + _theResult___snd__h593208 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q55 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d8996 ? - _theResult___snd__h593210 : - _theResult___snd__h611000 ; + _theResult___snd__h593208 : + _theResult___snd__h610998 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q77 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d10000 ? - _theResult___snd__h638959 : + _theResult___snd__h638957 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q90 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d10393 ? - _theResult___snd__h638959 : - _theResult___snd__h656749 ; + _theResult___snd__h638957 : + _theResult___snd__h656747 ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d10589 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9533 ? - ((_theResult___fst_exp__h630314 == 8'd255) ? + ((_theResult___fst_exp__h630312 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10574) : - ((_theResult___fst_exp__h638970 == 8'd255) ? + ((_theResult___fst_exp__h638968 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10587) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d10639 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9533 ? - ((_theResult___fst_exp__h630314 == 8'd255) ? + ((_theResult___fst_exp__h630312 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10630) : - ((_theResult___fst_exp__h638970 == 8'd255) ? + ((_theResult___fst_exp__h638968 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10637) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d11986 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10930 ? - ((_theResult___fst_exp__h676061 == 8'd255) ? + ((_theResult___fst_exp__h676059 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11971) : - ((_theResult___fst_exp__h684717 == 8'd255) ? + ((_theResult___fst_exp__h684715 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11984) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d12036 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10930 ? - ((_theResult___fst_exp__h676061 == 8'd255) ? + ((_theResult___fst_exp__h676059 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12027) : - ((_theResult___fst_exp__h684717 == 8'd255) ? + ((_theResult___fst_exp__h684715 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12034) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d9192 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8136 ? - ((_theResult___fst_exp__h584565 == 8'd255) ? + ((_theResult___fst_exp__h584563 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9177) : - ((_theResult___fst_exp__h593221 == 8'd255) ? + ((_theResult___fst_exp__h593219 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9190) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d9242 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8136 ? - ((_theResult___fst_exp__h584565 == 8'd255) ? + ((_theResult___fst_exp__h584563 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9233) : - ((_theResult___fst_exp__h593221 == 8'd255) ? + ((_theResult___fst_exp__h593219 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9240) ; assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d11164 = - (_theResult____h667952[56] ? + (_theResult____h667950[56] ? 6'd0 : - (_theResult____h667952[55] ? + (_theResult____h667950[55] ? 6'd1 : - (_theResult____h667952[54] ? + (_theResult____h667950[54] ? 6'd2 : - (_theResult____h667952[53] ? + (_theResult____h667950[53] ? 6'd3 : - (_theResult____h667952[52] ? + (_theResult____h667950[52] ? 6'd4 : - (_theResult____h667952[51] ? + (_theResult____h667950[51] ? 6'd5 : - (_theResult____h667952[50] ? + (_theResult____h667950[50] ? 6'd6 : - (_theResult____h667952[49] ? + (_theResult____h667950[49] ? 6'd7 : - (_theResult____h667952[48] ? + (_theResult____h667950[48] ? 6'd8 : - (_theResult____h667952[47] ? + (_theResult____h667950[47] ? 6'd9 : - (_theResult____h667952[46] ? + (_theResult____h667950[46] ? 6'd10 : - (_theResult____h667952[45] ? + (_theResult____h667950[45] ? 6'd11 : - (_theResult____h667952[44] ? + (_theResult____h667950[44] ? 6'd12 : - (_theResult____h667952[43] ? + (_theResult____h667950[43] ? 6'd13 : - (_theResult____h667952[42] ? + (_theResult____h667950[42] ? 6'd14 : - (_theResult____h667952[41] ? + (_theResult____h667950[41] ? 6'd15 : - (_theResult____h667952[40] ? + (_theResult____h667950[40] ? 6'd16 : - (_theResult____h667952[39] ? + (_theResult____h667950[39] ? 6'd17 : - (_theResult____h667952[38] ? + (_theResult____h667950[38] ? 6'd18 : - (_theResult____h667952[37] ? + (_theResult____h667950[37] ? 6'd19 : - (_theResult____h667952[36] ? + (_theResult____h667950[36] ? 6'd20 : - (_theResult____h667952[35] ? + (_theResult____h667950[35] ? 6'd21 : - (_theResult____h667952[34] ? + (_theResult____h667950[34] ? 6'd22 : - (_theResult____h667952[33] ? + (_theResult____h667950[33] ? 6'd23 : - (_theResult____h667952[32] ? + (_theResult____h667950[32] ? 6'd24 : - (_theResult____h667952[31] ? + (_theResult____h667950[31] ? 6'd25 : - (_theResult____h667952[30] ? + (_theResult____h667950[30] ? 6'd26 : - (_theResult____h667952[29] ? + (_theResult____h667950[29] ? 6'd27 : - (_theResult____h667952[28] ? + (_theResult____h667950[28] ? 6'd28 : - (_theResult____h667952[27] ? + (_theResult____h667950[27] ? 6'd29 : - (_theResult____h667952[26] ? + (_theResult____h667950[26] ? 6'd30 : - (_theResult____h667952[25] ? + (_theResult____h667950[25] ? 6'd31 : - (_theResult____h667952[24] ? + (_theResult____h667950[24] ? 6'd32 : - (_theResult____h667952[23] ? + (_theResult____h667950[23] ? 6'd33 : - (_theResult____h667952[22] ? + (_theResult____h667950[22] ? 6'd34 : - (_theResult____h667952[21] ? + (_theResult____h667950[21] ? 6'd35 : - (_theResult____h667952[20] ? + (_theResult____h667950[20] ? 6'd36 : - (_theResult____h667952[19] ? + (_theResult____h667950[19] ? 6'd37 : - (_theResult____h667952[18] ? + (_theResult____h667950[18] ? 6'd38 : - (_theResult____h667952[17] ? + (_theResult____h667950[17] ? 6'd39 : - (_theResult____h667952[16] ? + (_theResult____h667950[16] ? 6'd40 : - (_theResult____h667952[15] ? + (_theResult____h667950[15] ? 6'd41 : - (_theResult____h667952[14] ? + (_theResult____h667950[14] ? 6'd42 : - (_theResult____h667952[13] ? + (_theResult____h667950[13] ? 6'd43 : - (_theResult____h667952[12] ? + (_theResult____h667950[12] ? 6'd44 : - (_theResult____h667952[11] ? + (_theResult____h667950[11] ? 6'd45 : - (_theResult____h667952[10] ? + (_theResult____h667950[10] ? 6'd46 : - (_theResult____h667952[9] ? + (_theResult____h667950[9] ? 6'd47 : - (_theResult____h667952[8] ? + (_theResult____h667950[8] ? 6'd48 : - (_theResult____h667952[7] ? + (_theResult____h667950[7] ? 6'd49 : - (_theResult____h667952[6] ? + (_theResult____h667950[6] ? 6'd50 : - (_theResult____h667952[5] ? + (_theResult____h667950[5] ? 6'd51 : - (_theResult____h667952[4] ? + (_theResult____h667950[4] ? 6'd52 : - (_theResult____h667952[3] ? + (_theResult____h667950[3] ? 6'd53 : - (_theResult____h667952[2] ? + (_theResult____h667950[2] ? 6'd54 : - (_theResult____h667952[1] ? + (_theResult____h667950[1] ? 6'd55 : - (_theResult____h667952[0] ? + (_theResult____h667950[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d8370 = - (_theResult____h576454[56] ? + (_theResult____h576452[56] ? 6'd0 : - (_theResult____h576454[55] ? + (_theResult____h576452[55] ? 6'd1 : - (_theResult____h576454[54] ? + (_theResult____h576452[54] ? 6'd2 : - (_theResult____h576454[53] ? + (_theResult____h576452[53] ? 6'd3 : - (_theResult____h576454[52] ? + (_theResult____h576452[52] ? 6'd4 : - (_theResult____h576454[51] ? + (_theResult____h576452[51] ? 6'd5 : - (_theResult____h576454[50] ? + (_theResult____h576452[50] ? 6'd6 : - (_theResult____h576454[49] ? + (_theResult____h576452[49] ? 6'd7 : - (_theResult____h576454[48] ? + (_theResult____h576452[48] ? 6'd8 : - (_theResult____h576454[47] ? + (_theResult____h576452[47] ? 6'd9 : - (_theResult____h576454[46] ? + (_theResult____h576452[46] ? 6'd10 : - (_theResult____h576454[45] ? + (_theResult____h576452[45] ? 6'd11 : - (_theResult____h576454[44] ? + (_theResult____h576452[44] ? 6'd12 : - (_theResult____h576454[43] ? + (_theResult____h576452[43] ? 6'd13 : - (_theResult____h576454[42] ? + (_theResult____h576452[42] ? 6'd14 : - (_theResult____h576454[41] ? + (_theResult____h576452[41] ? 6'd15 : - (_theResult____h576454[40] ? + (_theResult____h576452[40] ? 6'd16 : - (_theResult____h576454[39] ? + (_theResult____h576452[39] ? 6'd17 : - (_theResult____h576454[38] ? + (_theResult____h576452[38] ? 6'd18 : - (_theResult____h576454[37] ? + (_theResult____h576452[37] ? 6'd19 : - (_theResult____h576454[36] ? + (_theResult____h576452[36] ? 6'd20 : - (_theResult____h576454[35] ? + (_theResult____h576452[35] ? 6'd21 : - (_theResult____h576454[34] ? + (_theResult____h576452[34] ? 6'd22 : - (_theResult____h576454[33] ? + (_theResult____h576452[33] ? 6'd23 : - (_theResult____h576454[32] ? + (_theResult____h576452[32] ? 6'd24 : - (_theResult____h576454[31] ? + (_theResult____h576452[31] ? 6'd25 : - (_theResult____h576454[30] ? + (_theResult____h576452[30] ? 6'd26 : - (_theResult____h576454[29] ? + (_theResult____h576452[29] ? 6'd27 : - (_theResult____h576454[28] ? + (_theResult____h576452[28] ? 6'd28 : - (_theResult____h576454[27] ? + (_theResult____h576452[27] ? 6'd29 : - (_theResult____h576454[26] ? + (_theResult____h576452[26] ? 6'd30 : - (_theResult____h576454[25] ? + (_theResult____h576452[25] ? 6'd31 : - (_theResult____h576454[24] ? + (_theResult____h576452[24] ? 6'd32 : - (_theResult____h576454[23] ? + (_theResult____h576452[23] ? 6'd33 : - (_theResult____h576454[22] ? + (_theResult____h576452[22] ? 6'd34 : - (_theResult____h576454[21] ? + (_theResult____h576452[21] ? 6'd35 : - (_theResult____h576454[20] ? + (_theResult____h576452[20] ? 6'd36 : - (_theResult____h576454[19] ? + (_theResult____h576452[19] ? 6'd37 : - (_theResult____h576454[18] ? + (_theResult____h576452[18] ? 6'd38 : - (_theResult____h576454[17] ? + (_theResult____h576452[17] ? 6'd39 : - (_theResult____h576454[16] ? + (_theResult____h576452[16] ? 6'd40 : - (_theResult____h576454[15] ? + (_theResult____h576452[15] ? 6'd41 : - (_theResult____h576454[14] ? + (_theResult____h576452[14] ? 6'd42 : - (_theResult____h576454[13] ? + (_theResult____h576452[13] ? 6'd43 : - (_theResult____h576454[12] ? + (_theResult____h576452[12] ? 6'd44 : - (_theResult____h576454[11] ? + (_theResult____h576452[11] ? 6'd45 : - (_theResult____h576454[10] ? + (_theResult____h576452[10] ? 6'd46 : - (_theResult____h576454[9] ? + (_theResult____h576452[9] ? 6'd47 : - (_theResult____h576454[8] ? + (_theResult____h576452[8] ? 6'd48 : - (_theResult____h576454[7] ? + (_theResult____h576452[7] ? 6'd49 : - (_theResult____h576454[6] ? + (_theResult____h576452[6] ? 6'd50 : - (_theResult____h576454[5] ? + (_theResult____h576452[5] ? 6'd51 : - (_theResult____h576454[4] ? + (_theResult____h576452[4] ? 6'd52 : - (_theResult____h576454[3] ? + (_theResult____h576452[3] ? 6'd53 : - (_theResult____h576454[2] ? + (_theResult____h576452[2] ? 6'd54 : - (_theResult____h576454[1] ? + (_theResult____h576452[1] ? 6'd55 : - (_theResult____h576454[0] ? + (_theResult____h576452[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d9767 = - (_theResult____h622205[56] ? + (_theResult____h622203[56] ? 6'd0 : - (_theResult____h622205[55] ? + (_theResult____h622203[55] ? 6'd1 : - (_theResult____h622205[54] ? + (_theResult____h622203[54] ? 6'd2 : - (_theResult____h622205[53] ? + (_theResult____h622203[53] ? 6'd3 : - (_theResult____h622205[52] ? + (_theResult____h622203[52] ? 6'd4 : - (_theResult____h622205[51] ? + (_theResult____h622203[51] ? 6'd5 : - (_theResult____h622205[50] ? + (_theResult____h622203[50] ? 6'd6 : - (_theResult____h622205[49] ? + (_theResult____h622203[49] ? 6'd7 : - (_theResult____h622205[48] ? + (_theResult____h622203[48] ? 6'd8 : - (_theResult____h622205[47] ? + (_theResult____h622203[47] ? 6'd9 : - (_theResult____h622205[46] ? + (_theResult____h622203[46] ? 6'd10 : - (_theResult____h622205[45] ? + (_theResult____h622203[45] ? 6'd11 : - (_theResult____h622205[44] ? + (_theResult____h622203[44] ? 6'd12 : - (_theResult____h622205[43] ? + (_theResult____h622203[43] ? 6'd13 : - (_theResult____h622205[42] ? + (_theResult____h622203[42] ? 6'd14 : - (_theResult____h622205[41] ? + (_theResult____h622203[41] ? 6'd15 : - (_theResult____h622205[40] ? + (_theResult____h622203[40] ? 6'd16 : - (_theResult____h622205[39] ? + (_theResult____h622203[39] ? 6'd17 : - (_theResult____h622205[38] ? + (_theResult____h622203[38] ? 6'd18 : - (_theResult____h622205[37] ? + (_theResult____h622203[37] ? 6'd19 : - (_theResult____h622205[36] ? + (_theResult____h622203[36] ? 6'd20 : - (_theResult____h622205[35] ? + (_theResult____h622203[35] ? 6'd21 : - (_theResult____h622205[34] ? + (_theResult____h622203[34] ? 6'd22 : - (_theResult____h622205[33] ? + (_theResult____h622203[33] ? 6'd23 : - (_theResult____h622205[32] ? + (_theResult____h622203[32] ? 6'd24 : - (_theResult____h622205[31] ? + (_theResult____h622203[31] ? 6'd25 : - (_theResult____h622205[30] ? + (_theResult____h622203[30] ? 6'd26 : - (_theResult____h622205[29] ? + (_theResult____h622203[29] ? 6'd27 : - (_theResult____h622205[28] ? + (_theResult____h622203[28] ? 6'd28 : - (_theResult____h622205[27] ? + (_theResult____h622203[27] ? 6'd29 : - (_theResult____h622205[26] ? + (_theResult____h622203[26] ? 6'd30 : - (_theResult____h622205[25] ? + (_theResult____h622203[25] ? 6'd31 : - (_theResult____h622205[24] ? + (_theResult____h622203[24] ? 6'd32 : - (_theResult____h622205[23] ? + (_theResult____h622203[23] ? 6'd33 : - (_theResult____h622205[22] ? + (_theResult____h622203[22] ? 6'd34 : - (_theResult____h622205[21] ? + (_theResult____h622203[21] ? 6'd35 : - (_theResult____h622205[20] ? + (_theResult____h622203[20] ? 6'd36 : - (_theResult____h622205[19] ? + (_theResult____h622203[19] ? 6'd37 : - (_theResult____h622205[18] ? + (_theResult____h622203[18] ? 6'd38 : - (_theResult____h622205[17] ? + (_theResult____h622203[17] ? 6'd39 : - (_theResult____h622205[16] ? + (_theResult____h622203[16] ? 6'd40 : - (_theResult____h622205[15] ? + (_theResult____h622203[15] ? 6'd41 : - (_theResult____h622205[14] ? + (_theResult____h622203[14] ? 6'd42 : - (_theResult____h622205[13] ? + (_theResult____h622203[13] ? 6'd43 : - (_theResult____h622205[12] ? + (_theResult____h622203[12] ? 6'd44 : - (_theResult____h622205[11] ? + (_theResult____h622203[11] ? 6'd45 : - (_theResult____h622205[10] ? + (_theResult____h622203[10] ? 6'd46 : - (_theResult____h622205[9] ? + (_theResult____h622203[9] ? 6'd47 : - (_theResult____h622205[8] ? + (_theResult____h622203[8] ? 6'd48 : - (_theResult____h622205[7] ? + (_theResult____h622203[7] ? 6'd49 : - (_theResult____h622205[6] ? + (_theResult____h622203[6] ? 6'd50 : - (_theResult____h622205[5] ? + (_theResult____h622203[5] ? 6'd51 : - (_theResult____h622205[4] ? + (_theResult____h622203[4] ? 6'd52 : - (_theResult____h622205[3] ? + (_theResult____h622203[3] ? 6'd53 : - (_theResult____h622205[2] ? + (_theResult____h622203[2] ? 6'd54 : - (_theResult____h622205[1] ? + (_theResult____h622203[1] ? 6'd55 : - (_theResult____h622205[0] ? + (_theResult____h622203[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d13046 = - (_theResult____h735628[56] ? + (_theResult____h735625[56] ? 6'd0 : - (_theResult____h735628[55] ? + (_theResult____h735625[55] ? 6'd1 : - (_theResult____h735628[54] ? + (_theResult____h735625[54] ? 6'd2 : - (_theResult____h735628[53] ? + (_theResult____h735625[53] ? 6'd3 : - (_theResult____h735628[52] ? + (_theResult____h735625[52] ? 6'd4 : - (_theResult____h735628[51] ? + (_theResult____h735625[51] ? 6'd5 : - (_theResult____h735628[50] ? + (_theResult____h735625[50] ? 6'd6 : - (_theResult____h735628[49] ? + (_theResult____h735625[49] ? 6'd7 : - (_theResult____h735628[48] ? + (_theResult____h735625[48] ? 6'd8 : - (_theResult____h735628[47] ? + (_theResult____h735625[47] ? 6'd9 : - (_theResult____h735628[46] ? + (_theResult____h735625[46] ? 6'd10 : - (_theResult____h735628[45] ? + (_theResult____h735625[45] ? 6'd11 : - (_theResult____h735628[44] ? + (_theResult____h735625[44] ? 6'd12 : - (_theResult____h735628[43] ? + (_theResult____h735625[43] ? 6'd13 : - (_theResult____h735628[42] ? + (_theResult____h735625[42] ? 6'd14 : - (_theResult____h735628[41] ? + (_theResult____h735625[41] ? 6'd15 : - (_theResult____h735628[40] ? + (_theResult____h735625[40] ? 6'd16 : - (_theResult____h735628[39] ? + (_theResult____h735625[39] ? 6'd17 : - (_theResult____h735628[38] ? + (_theResult____h735625[38] ? 6'd18 : - (_theResult____h735628[37] ? + (_theResult____h735625[37] ? 6'd19 : - (_theResult____h735628[36] ? + (_theResult____h735625[36] ? 6'd20 : - (_theResult____h735628[35] ? + (_theResult____h735625[35] ? 6'd21 : - (_theResult____h735628[34] ? + (_theResult____h735625[34] ? 6'd22 : - (_theResult____h735628[33] ? + (_theResult____h735625[33] ? 6'd23 : - (_theResult____h735628[32] ? + (_theResult____h735625[32] ? 6'd24 : - (_theResult____h735628[31] ? + (_theResult____h735625[31] ? 6'd25 : - (_theResult____h735628[30] ? + (_theResult____h735625[30] ? 6'd26 : - (_theResult____h735628[29] ? + (_theResult____h735625[29] ? 6'd27 : - (_theResult____h735628[28] ? + (_theResult____h735625[28] ? 6'd28 : - (_theResult____h735628[27] ? + (_theResult____h735625[27] ? 6'd29 : - (_theResult____h735628[26] ? + (_theResult____h735625[26] ? 6'd30 : - (_theResult____h735628[25] ? + (_theResult____h735625[25] ? 6'd31 : - (_theResult____h735628[24] ? + (_theResult____h735625[24] ? 6'd32 : - (_theResult____h735628[23] ? + (_theResult____h735625[23] ? 6'd33 : - (_theResult____h735628[22] ? + (_theResult____h735625[22] ? 6'd34 : - (_theResult____h735628[21] ? + (_theResult____h735625[21] ? 6'd35 : - (_theResult____h735628[20] ? + (_theResult____h735625[20] ? 6'd36 : - (_theResult____h735628[19] ? + (_theResult____h735625[19] ? 6'd37 : - (_theResult____h735628[18] ? + (_theResult____h735625[18] ? 6'd38 : - (_theResult____h735628[17] ? + (_theResult____h735625[17] ? 6'd39 : - (_theResult____h735628[16] ? + (_theResult____h735625[16] ? 6'd40 : - (_theResult____h735628[15] ? + (_theResult____h735625[15] ? 6'd41 : - (_theResult____h735628[14] ? + (_theResult____h735625[14] ? 6'd42 : - (_theResult____h735628[13] ? + (_theResult____h735625[13] ? 6'd43 : - (_theResult____h735628[12] ? + (_theResult____h735625[12] ? 6'd44 : - (_theResult____h735628[11] ? + (_theResult____h735625[11] ? 6'd45 : - (_theResult____h735628[10] ? + (_theResult____h735625[10] ? 6'd46 : - (_theResult____h735628[9] ? + (_theResult____h735625[9] ? 6'd47 : - (_theResult____h735628[8] ? + (_theResult____h735625[8] ? 6'd48 : - (_theResult____h735628[7] ? + (_theResult____h735625[7] ? 6'd49 : - (_theResult____h735628[6] ? + (_theResult____h735625[6] ? 6'd50 : - (_theResult____h735628[5] ? + (_theResult____h735625[5] ? 6'd51 : - (_theResult____h735628[4] ? + (_theResult____h735625[4] ? 6'd52 : - (_theResult____h735628[3] ? + (_theResult____h735625[3] ? 6'd53 : - (_theResult____h735628[2] ? + (_theResult____h735625[2] ? 6'd54 : - (_theResult____h735628[1] ? + (_theResult____h735625[1] ? 6'd55 : - (_theResult____h735628[0] ? + (_theResult____h735625[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d13761 = - (_theResult____h813785[56] ? + (_theResult____h813782[56] ? 6'd0 : - (_theResult____h813785[55] ? + (_theResult____h813782[55] ? 6'd1 : - (_theResult____h813785[54] ? + (_theResult____h813782[54] ? 6'd2 : - (_theResult____h813785[53] ? + (_theResult____h813782[53] ? 6'd3 : - (_theResult____h813785[52] ? + (_theResult____h813782[52] ? 6'd4 : - (_theResult____h813785[51] ? + (_theResult____h813782[51] ? 6'd5 : - (_theResult____h813785[50] ? + (_theResult____h813782[50] ? 6'd6 : - (_theResult____h813785[49] ? + (_theResult____h813782[49] ? 6'd7 : - (_theResult____h813785[48] ? + (_theResult____h813782[48] ? 6'd8 : - (_theResult____h813785[47] ? + (_theResult____h813782[47] ? 6'd9 : - (_theResult____h813785[46] ? + (_theResult____h813782[46] ? 6'd10 : - (_theResult____h813785[45] ? + (_theResult____h813782[45] ? 6'd11 : - (_theResult____h813785[44] ? + (_theResult____h813782[44] ? 6'd12 : - (_theResult____h813785[43] ? + (_theResult____h813782[43] ? 6'd13 : - (_theResult____h813785[42] ? + (_theResult____h813782[42] ? 6'd14 : - (_theResult____h813785[41] ? + (_theResult____h813782[41] ? 6'd15 : - (_theResult____h813785[40] ? + (_theResult____h813782[40] ? 6'd16 : - (_theResult____h813785[39] ? + (_theResult____h813782[39] ? 6'd17 : - (_theResult____h813785[38] ? + (_theResult____h813782[38] ? 6'd18 : - (_theResult____h813785[37] ? + (_theResult____h813782[37] ? 6'd19 : - (_theResult____h813785[36] ? + (_theResult____h813782[36] ? 6'd20 : - (_theResult____h813785[35] ? + (_theResult____h813782[35] ? 6'd21 : - (_theResult____h813785[34] ? + (_theResult____h813782[34] ? 6'd22 : - (_theResult____h813785[33] ? + (_theResult____h813782[33] ? 6'd23 : - (_theResult____h813785[32] ? + (_theResult____h813782[32] ? 6'd24 : - (_theResult____h813785[31] ? + (_theResult____h813782[31] ? 6'd25 : - (_theResult____h813785[30] ? + (_theResult____h813782[30] ? 6'd26 : - (_theResult____h813785[29] ? + (_theResult____h813782[29] ? 6'd27 : - (_theResult____h813785[28] ? + (_theResult____h813782[28] ? 6'd28 : - (_theResult____h813785[27] ? + (_theResult____h813782[27] ? 6'd29 : - (_theResult____h813785[26] ? + (_theResult____h813782[26] ? 6'd30 : - (_theResult____h813785[25] ? + (_theResult____h813782[25] ? 6'd31 : - (_theResult____h813785[24] ? + (_theResult____h813782[24] ? 6'd32 : - (_theResult____h813785[23] ? + (_theResult____h813782[23] ? 6'd33 : - (_theResult____h813785[22] ? + (_theResult____h813782[22] ? 6'd34 : - (_theResult____h813785[21] ? + (_theResult____h813782[21] ? 6'd35 : - (_theResult____h813785[20] ? + (_theResult____h813782[20] ? 6'd36 : - (_theResult____h813785[19] ? + (_theResult____h813782[19] ? 6'd37 : - (_theResult____h813785[18] ? + (_theResult____h813782[18] ? 6'd38 : - (_theResult____h813785[17] ? + (_theResult____h813782[17] ? 6'd39 : - (_theResult____h813785[16] ? + (_theResult____h813782[16] ? 6'd40 : - (_theResult____h813785[15] ? + (_theResult____h813782[15] ? 6'd41 : - (_theResult____h813785[14] ? + (_theResult____h813782[14] ? 6'd42 : - (_theResult____h813785[13] ? + (_theResult____h813782[13] ? 6'd43 : - (_theResult____h813785[12] ? + (_theResult____h813782[12] ? 6'd44 : - (_theResult____h813785[11] ? + (_theResult____h813782[11] ? 6'd45 : - (_theResult____h813785[10] ? + (_theResult____h813782[10] ? 6'd46 : - (_theResult____h813785[9] ? + (_theResult____h813782[9] ? 6'd47 : - (_theResult____h813785[8] ? + (_theResult____h813782[8] ? 6'd48 : - (_theResult____h813785[7] ? + (_theResult____h813782[7] ? 6'd49 : - (_theResult____h813785[6] ? + (_theResult____h813782[6] ? 6'd50 : - (_theResult____h813785[5] ? + (_theResult____h813782[5] ? 6'd51 : - (_theResult____h813785[4] ? + (_theResult____h813782[4] ? 6'd52 : - (_theResult____h813785[3] ? + (_theResult____h813782[3] ? 6'd53 : - (_theResult____h813785[2] ? + (_theResult____h813782[2] ? 6'd54 : - (_theResult____h813785[1] ? + (_theResult____h813782[1] ? 6'd55 : - (_theResult____h813785[0] ? + (_theResult____h813782[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d14531 = - (_theResult____h774481[56] ? + (_theResult____h774478[56] ? 6'd0 : - (_theResult____h774481[55] ? + (_theResult____h774478[55] ? 6'd1 : - (_theResult____h774481[54] ? + (_theResult____h774478[54] ? 6'd2 : - (_theResult____h774481[53] ? + (_theResult____h774478[53] ? 6'd3 : - (_theResult____h774481[52] ? + (_theResult____h774478[52] ? 6'd4 : - (_theResult____h774481[51] ? + (_theResult____h774478[51] ? 6'd5 : - (_theResult____h774481[50] ? + (_theResult____h774478[50] ? 6'd6 : - (_theResult____h774481[49] ? + (_theResult____h774478[49] ? 6'd7 : - (_theResult____h774481[48] ? + (_theResult____h774478[48] ? 6'd8 : - (_theResult____h774481[47] ? + (_theResult____h774478[47] ? 6'd9 : - (_theResult____h774481[46] ? + (_theResult____h774478[46] ? 6'd10 : - (_theResult____h774481[45] ? + (_theResult____h774478[45] ? 6'd11 : - (_theResult____h774481[44] ? + (_theResult____h774478[44] ? 6'd12 : - (_theResult____h774481[43] ? + (_theResult____h774478[43] ? 6'd13 : - (_theResult____h774481[42] ? + (_theResult____h774478[42] ? 6'd14 : - (_theResult____h774481[41] ? + (_theResult____h774478[41] ? 6'd15 : - (_theResult____h774481[40] ? + (_theResult____h774478[40] ? 6'd16 : - (_theResult____h774481[39] ? + (_theResult____h774478[39] ? 6'd17 : - (_theResult____h774481[38] ? + (_theResult____h774478[38] ? 6'd18 : - (_theResult____h774481[37] ? + (_theResult____h774478[37] ? 6'd19 : - (_theResult____h774481[36] ? + (_theResult____h774478[36] ? 6'd20 : - (_theResult____h774481[35] ? + (_theResult____h774478[35] ? 6'd21 : - (_theResult____h774481[34] ? + (_theResult____h774478[34] ? 6'd22 : - (_theResult____h774481[33] ? + (_theResult____h774478[33] ? 6'd23 : - (_theResult____h774481[32] ? + (_theResult____h774478[32] ? 6'd24 : - (_theResult____h774481[31] ? + (_theResult____h774478[31] ? 6'd25 : - (_theResult____h774481[30] ? + (_theResult____h774478[30] ? 6'd26 : - (_theResult____h774481[29] ? + (_theResult____h774478[29] ? 6'd27 : - (_theResult____h774481[28] ? + (_theResult____h774478[28] ? 6'd28 : - (_theResult____h774481[27] ? + (_theResult____h774478[27] ? 6'd29 : - (_theResult____h774481[26] ? + (_theResult____h774478[26] ? 6'd30 : - (_theResult____h774481[25] ? + (_theResult____h774478[25] ? 6'd31 : - (_theResult____h774481[24] ? + (_theResult____h774478[24] ? 6'd32 : - (_theResult____h774481[23] ? + (_theResult____h774478[23] ? 6'd33 : - (_theResult____h774481[22] ? + (_theResult____h774478[22] ? 6'd34 : - (_theResult____h774481[21] ? + (_theResult____h774478[21] ? 6'd35 : - (_theResult____h774481[20] ? + (_theResult____h774478[20] ? 6'd36 : - (_theResult____h774481[19] ? + (_theResult____h774478[19] ? 6'd37 : - (_theResult____h774481[18] ? + (_theResult____h774478[18] ? 6'd38 : - (_theResult____h774481[17] ? + (_theResult____h774478[17] ? 6'd39 : - (_theResult____h774481[16] ? + (_theResult____h774478[16] ? 6'd40 : - (_theResult____h774481[15] ? + (_theResult____h774478[15] ? 6'd41 : - (_theResult____h774481[14] ? + (_theResult____h774478[14] ? 6'd42 : - (_theResult____h774481[13] ? + (_theResult____h774478[13] ? 6'd43 : - (_theResult____h774481[12] ? + (_theResult____h774478[12] ? 6'd44 : - (_theResult____h774481[11] ? + (_theResult____h774478[11] ? 6'd45 : - (_theResult____h774481[10] ? + (_theResult____h774478[10] ? 6'd46 : - (_theResult____h774481[9] ? + (_theResult____h774478[9] ? 6'd47 : - (_theResult____h774481[8] ? + (_theResult____h774478[8] ? 6'd48 : - (_theResult____h774481[7] ? + (_theResult____h774478[7] ? 6'd49 : - (_theResult____h774481[6] ? + (_theResult____h774478[6] ? 6'd50 : - (_theResult____h774481[5] ? + (_theResult____h774478[5] ? 6'd51 : - (_theResult____h774481[4] ? + (_theResult____h774478[4] ? 6'd52 : - (_theResult____h774481[3] ? + (_theResult____h774478[3] ? 6'd53 : - (_theResult____h774481[2] ? + (_theResult____h774478[2] ? 6'd54 : - (_theResult____h774481[1] ? + (_theResult____h774478[1] ? 6'd55 : - (_theResult____h774481[0] ? + (_theResult____h774478[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d10318 = - (_theResult____h639842[56] ? + (_theResult____h639840[56] ? 6'd0 : - (_theResult____h639842[55] ? + (_theResult____h639840[55] ? 6'd1 : - (_theResult____h639842[54] ? + (_theResult____h639840[54] ? 6'd2 : - (_theResult____h639842[53] ? + (_theResult____h639840[53] ? 6'd3 : - (_theResult____h639842[52] ? + (_theResult____h639840[52] ? 6'd4 : - (_theResult____h639842[51] ? + (_theResult____h639840[51] ? 6'd5 : - (_theResult____h639842[50] ? + (_theResult____h639840[50] ? 6'd6 : - (_theResult____h639842[49] ? + (_theResult____h639840[49] ? 6'd7 : - (_theResult____h639842[48] ? + (_theResult____h639840[48] ? 6'd8 : - (_theResult____h639842[47] ? + (_theResult____h639840[47] ? 6'd9 : - (_theResult____h639842[46] ? + (_theResult____h639840[46] ? 6'd10 : - (_theResult____h639842[45] ? + (_theResult____h639840[45] ? 6'd11 : - (_theResult____h639842[44] ? + (_theResult____h639840[44] ? 6'd12 : - (_theResult____h639842[43] ? + (_theResult____h639840[43] ? 6'd13 : - (_theResult____h639842[42] ? + (_theResult____h639840[42] ? 6'd14 : - (_theResult____h639842[41] ? + (_theResult____h639840[41] ? 6'd15 : - (_theResult____h639842[40] ? + (_theResult____h639840[40] ? 6'd16 : - (_theResult____h639842[39] ? + (_theResult____h639840[39] ? 6'd17 : - (_theResult____h639842[38] ? + (_theResult____h639840[38] ? 6'd18 : - (_theResult____h639842[37] ? + (_theResult____h639840[37] ? 6'd19 : - (_theResult____h639842[36] ? + (_theResult____h639840[36] ? 6'd20 : - (_theResult____h639842[35] ? + (_theResult____h639840[35] ? 6'd21 : - (_theResult____h639842[34] ? + (_theResult____h639840[34] ? 6'd22 : - (_theResult____h639842[33] ? + (_theResult____h639840[33] ? 6'd23 : - (_theResult____h639842[32] ? + (_theResult____h639840[32] ? 6'd24 : - (_theResult____h639842[31] ? + (_theResult____h639840[31] ? 6'd25 : - (_theResult____h639842[30] ? + (_theResult____h639840[30] ? 6'd26 : - (_theResult____h639842[29] ? + (_theResult____h639840[29] ? 6'd27 : - (_theResult____h639842[28] ? + (_theResult____h639840[28] ? 6'd28 : - (_theResult____h639842[27] ? + (_theResult____h639840[27] ? 6'd29 : - (_theResult____h639842[26] ? + (_theResult____h639840[26] ? 6'd30 : - (_theResult____h639842[25] ? + (_theResult____h639840[25] ? 6'd31 : - (_theResult____h639842[24] ? + (_theResult____h639840[24] ? 6'd32 : - (_theResult____h639842[23] ? + (_theResult____h639840[23] ? 6'd33 : - (_theResult____h639842[22] ? + (_theResult____h639840[22] ? 6'd34 : - (_theResult____h639842[21] ? + (_theResult____h639840[21] ? 6'd35 : - (_theResult____h639842[20] ? + (_theResult____h639840[20] ? 6'd36 : - (_theResult____h639842[19] ? + (_theResult____h639840[19] ? 6'd37 : - (_theResult____h639842[18] ? + (_theResult____h639840[18] ? 6'd38 : - (_theResult____h639842[17] ? + (_theResult____h639840[17] ? 6'd39 : - (_theResult____h639842[16] ? + (_theResult____h639840[16] ? 6'd40 : - (_theResult____h639842[15] ? + (_theResult____h639840[15] ? 6'd41 : - (_theResult____h639842[14] ? + (_theResult____h639840[14] ? 6'd42 : - (_theResult____h639842[13] ? + (_theResult____h639840[13] ? 6'd43 : - (_theResult____h639842[12] ? + (_theResult____h639840[12] ? 6'd44 : - (_theResult____h639842[11] ? + (_theResult____h639840[11] ? 6'd45 : - (_theResult____h639842[10] ? + (_theResult____h639840[10] ? 6'd46 : - (_theResult____h639842[9] ? + (_theResult____h639840[9] ? 6'd47 : - (_theResult____h639842[8] ? + (_theResult____h639840[8] ? 6'd48 : - (_theResult____h639842[7] ? + (_theResult____h639840[7] ? 6'd49 : - (_theResult____h639842[6] ? + (_theResult____h639840[6] ? 6'd50 : - (_theResult____h639842[5] ? + (_theResult____h639840[5] ? 6'd51 : - (_theResult____h639842[4] ? + (_theResult____h639840[4] ? 6'd52 : - (_theResult____h639842[3] ? + (_theResult____h639840[3] ? 6'd53 : - (_theResult____h639842[2] ? + (_theResult____h639840[2] ? 6'd54 : - (_theResult____h639842[1] ? + (_theResult____h639840[1] ? 6'd55 : - (_theResult____h639842[0] ? + (_theResult____h639840[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d11715 = - (_theResult____h685589[56] ? + (_theResult____h685587[56] ? 6'd0 : - (_theResult____h685589[55] ? + (_theResult____h685587[55] ? 6'd1 : - (_theResult____h685589[54] ? + (_theResult____h685587[54] ? 6'd2 : - (_theResult____h685589[53] ? + (_theResult____h685587[53] ? 6'd3 : - (_theResult____h685589[52] ? + (_theResult____h685587[52] ? 6'd4 : - (_theResult____h685589[51] ? + (_theResult____h685587[51] ? 6'd5 : - (_theResult____h685589[50] ? + (_theResult____h685587[50] ? 6'd6 : - (_theResult____h685589[49] ? + (_theResult____h685587[49] ? 6'd7 : - (_theResult____h685589[48] ? + (_theResult____h685587[48] ? 6'd8 : - (_theResult____h685589[47] ? + (_theResult____h685587[47] ? 6'd9 : - (_theResult____h685589[46] ? + (_theResult____h685587[46] ? 6'd10 : - (_theResult____h685589[45] ? + (_theResult____h685587[45] ? 6'd11 : - (_theResult____h685589[44] ? + (_theResult____h685587[44] ? 6'd12 : - (_theResult____h685589[43] ? + (_theResult____h685587[43] ? 6'd13 : - (_theResult____h685589[42] ? + (_theResult____h685587[42] ? 6'd14 : - (_theResult____h685589[41] ? + (_theResult____h685587[41] ? 6'd15 : - (_theResult____h685589[40] ? + (_theResult____h685587[40] ? 6'd16 : - (_theResult____h685589[39] ? + (_theResult____h685587[39] ? 6'd17 : - (_theResult____h685589[38] ? + (_theResult____h685587[38] ? 6'd18 : - (_theResult____h685589[37] ? + (_theResult____h685587[37] ? 6'd19 : - (_theResult____h685589[36] ? + (_theResult____h685587[36] ? 6'd20 : - (_theResult____h685589[35] ? + (_theResult____h685587[35] ? 6'd21 : - (_theResult____h685589[34] ? + (_theResult____h685587[34] ? 6'd22 : - (_theResult____h685589[33] ? + (_theResult____h685587[33] ? 6'd23 : - (_theResult____h685589[32] ? + (_theResult____h685587[32] ? 6'd24 : - (_theResult____h685589[31] ? + (_theResult____h685587[31] ? 6'd25 : - (_theResult____h685589[30] ? + (_theResult____h685587[30] ? 6'd26 : - (_theResult____h685589[29] ? + (_theResult____h685587[29] ? 6'd27 : - (_theResult____h685589[28] ? + (_theResult____h685587[28] ? 6'd28 : - (_theResult____h685589[27] ? + (_theResult____h685587[27] ? 6'd29 : - (_theResult____h685589[26] ? + (_theResult____h685587[26] ? 6'd30 : - (_theResult____h685589[25] ? + (_theResult____h685587[25] ? 6'd31 : - (_theResult____h685589[24] ? + (_theResult____h685587[24] ? 6'd32 : - (_theResult____h685589[23] ? + (_theResult____h685587[23] ? 6'd33 : - (_theResult____h685589[22] ? + (_theResult____h685587[22] ? 6'd34 : - (_theResult____h685589[21] ? + (_theResult____h685587[21] ? 6'd35 : - (_theResult____h685589[20] ? + (_theResult____h685587[20] ? 6'd36 : - (_theResult____h685589[19] ? + (_theResult____h685587[19] ? 6'd37 : - (_theResult____h685589[18] ? + (_theResult____h685587[18] ? 6'd38 : - (_theResult____h685589[17] ? + (_theResult____h685587[17] ? 6'd39 : - (_theResult____h685589[16] ? + (_theResult____h685587[16] ? 6'd40 : - (_theResult____h685589[15] ? + (_theResult____h685587[15] ? 6'd41 : - (_theResult____h685589[14] ? + (_theResult____h685587[14] ? 6'd42 : - (_theResult____h685589[13] ? + (_theResult____h685587[13] ? 6'd43 : - (_theResult____h685589[12] ? + (_theResult____h685587[12] ? 6'd44 : - (_theResult____h685589[11] ? + (_theResult____h685587[11] ? 6'd45 : - (_theResult____h685589[10] ? + (_theResult____h685587[10] ? 6'd46 : - (_theResult____h685589[9] ? + (_theResult____h685587[9] ? 6'd47 : - (_theResult____h685589[8] ? + (_theResult____h685587[8] ? 6'd48 : - (_theResult____h685589[7] ? + (_theResult____h685587[7] ? 6'd49 : - (_theResult____h685589[6] ? + (_theResult____h685587[6] ? 6'd50 : - (_theResult____h685589[5] ? + (_theResult____h685587[5] ? 6'd51 : - (_theResult____h685589[4] ? + (_theResult____h685587[4] ? 6'd52 : - (_theResult____h685589[3] ? + (_theResult____h685587[3] ? 6'd53 : - (_theResult____h685589[2] ? + (_theResult____h685587[2] ? 6'd54 : - (_theResult____h685589[1] ? + (_theResult____h685587[1] ? 6'd55 : - (_theResult____h685589[0] ? + (_theResult____h685587[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d8921 = - (_theResult____h594093[56] ? + (_theResult____h594091[56] ? 6'd0 : - (_theResult____h594093[55] ? + (_theResult____h594091[55] ? 6'd1 : - (_theResult____h594093[54] ? + (_theResult____h594091[54] ? 6'd2 : - (_theResult____h594093[53] ? + (_theResult____h594091[53] ? 6'd3 : - (_theResult____h594093[52] ? + (_theResult____h594091[52] ? 6'd4 : - (_theResult____h594093[51] ? + (_theResult____h594091[51] ? 6'd5 : - (_theResult____h594093[50] ? + (_theResult____h594091[50] ? 6'd6 : - (_theResult____h594093[49] ? + (_theResult____h594091[49] ? 6'd7 : - (_theResult____h594093[48] ? + (_theResult____h594091[48] ? 6'd8 : - (_theResult____h594093[47] ? + (_theResult____h594091[47] ? 6'd9 : - (_theResult____h594093[46] ? + (_theResult____h594091[46] ? 6'd10 : - (_theResult____h594093[45] ? + (_theResult____h594091[45] ? 6'd11 : - (_theResult____h594093[44] ? + (_theResult____h594091[44] ? 6'd12 : - (_theResult____h594093[43] ? + (_theResult____h594091[43] ? 6'd13 : - (_theResult____h594093[42] ? + (_theResult____h594091[42] ? 6'd14 : - (_theResult____h594093[41] ? + (_theResult____h594091[41] ? 6'd15 : - (_theResult____h594093[40] ? + (_theResult____h594091[40] ? 6'd16 : - (_theResult____h594093[39] ? + (_theResult____h594091[39] ? 6'd17 : - (_theResult____h594093[38] ? + (_theResult____h594091[38] ? 6'd18 : - (_theResult____h594093[37] ? + (_theResult____h594091[37] ? 6'd19 : - (_theResult____h594093[36] ? + (_theResult____h594091[36] ? 6'd20 : - (_theResult____h594093[35] ? + (_theResult____h594091[35] ? 6'd21 : - (_theResult____h594093[34] ? + (_theResult____h594091[34] ? 6'd22 : - (_theResult____h594093[33] ? + (_theResult____h594091[33] ? 6'd23 : - (_theResult____h594093[32] ? + (_theResult____h594091[32] ? 6'd24 : - (_theResult____h594093[31] ? + (_theResult____h594091[31] ? 6'd25 : - (_theResult____h594093[30] ? + (_theResult____h594091[30] ? 6'd26 : - (_theResult____h594093[29] ? + (_theResult____h594091[29] ? 6'd27 : - (_theResult____h594093[28] ? + (_theResult____h594091[28] ? 6'd28 : - (_theResult____h594093[27] ? + (_theResult____h594091[27] ? 6'd29 : - (_theResult____h594093[26] ? + (_theResult____h594091[26] ? 6'd30 : - (_theResult____h594093[25] ? + (_theResult____h594091[25] ? 6'd31 : - (_theResult____h594093[24] ? + (_theResult____h594091[24] ? 6'd32 : - (_theResult____h594093[23] ? + (_theResult____h594091[23] ? 6'd33 : - (_theResult____h594093[22] ? + (_theResult____h594091[22] ? 6'd34 : - (_theResult____h594093[21] ? + (_theResult____h594091[21] ? 6'd35 : - (_theResult____h594093[20] ? + (_theResult____h594091[20] ? 6'd36 : - (_theResult____h594093[19] ? + (_theResult____h594091[19] ? 6'd37 : - (_theResult____h594093[18] ? + (_theResult____h594091[18] ? 6'd38 : - (_theResult____h594093[17] ? + (_theResult____h594091[17] ? 6'd39 : - (_theResult____h594093[16] ? + (_theResult____h594091[16] ? 6'd40 : - (_theResult____h594093[15] ? + (_theResult____h594091[15] ? 6'd41 : - (_theResult____h594093[14] ? + (_theResult____h594091[14] ? 6'd42 : - (_theResult____h594093[13] ? + (_theResult____h594091[13] ? 6'd43 : - (_theResult____h594093[12] ? + (_theResult____h594091[12] ? 6'd44 : - (_theResult____h594093[11] ? + (_theResult____h594091[11] ? 6'd45 : - (_theResult____h594093[10] ? + (_theResult____h594091[10] ? 6'd46 : - (_theResult____h594093[9] ? + (_theResult____h594091[9] ? 6'd47 : - (_theResult____h594093[8] ? + (_theResult____h594091[8] ? 6'd48 : - (_theResult____h594093[7] ? + (_theResult____h594091[7] ? 6'd49 : - (_theResult____h594093[6] ? + (_theResult____h594091[6] ? 6'd50 : - (_theResult____h594093[5] ? + (_theResult____h594091[5] ? 6'd51 : - (_theResult____h594093[4] ? + (_theResult____h594091[4] ? 6'd52 : - (_theResult____h594093[3] ? + (_theResult____h594091[3] ? 6'd53 : - (_theResult____h594093[2] ? + (_theResult____h594091[2] ? 6'd54 : - (_theResult____h594093[1] ? + (_theResult____h594091[1] ? 6'd55 : - (_theResult____h594093[0] ? + (_theResult____h594091[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d13090 = - (_theResult___fst_exp__h743864 == 11'd2047) ? + (_theResult___fst_exp__h743861 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : @@ -19427,10 +19425,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard35638_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q159 : + CASE_guard35635_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q159 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q160) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d13805 = - (_theResult___fst_exp__h822021 == 11'd2047) ? + (_theResult___fst_exp__h822018 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -19438,10 +19436,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard13795_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q176 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q177) ; + CASE_guard13792_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q174 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q175) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d14073 = - (_theResult___fst_exp__h822021 == 11'd2047) ? + (_theResult___fst_exp__h822018 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -19449,10 +19447,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard13795_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q180 : + CASE_guard13792_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q180 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q181) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d14575 = - (_theResult___fst_exp__h782717 == 11'd2047) ? + (_theResult___fst_exp__h782714 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -19460,10 +19458,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard74491_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q207 : + CASE_guard74488_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q207 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q208) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d14842 = - (_theResult___fst_exp__h782717 == 11'd2047) ? + (_theResult___fst_exp__h782714 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -19471,404 +19469,404 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard74491_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q211 : + CASE_guard74488_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q211 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q212) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d10477 = - (guard__h622215 == 2'b0 || + (guard__h622213 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - sfdin__h630308[56:34] : - _theResult___sfd__h630831 ; + sfdin__h630306[56:34] : + _theResult___sfd__h630829 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d10479 = - (guard__h622215 == 2'b0) ? - sfdin__h630308[56:34] : + (guard__h622213 == 2'b0) ? + sfdin__h630306[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h630831 : - sfdin__h630308[56:34]) ; + _theResult___sfd__h630829 : + sfdin__h630306[56:34]) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11227 = - (guard__h667962 == 2'b0 || + (guard__h667960 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h676061 : - _theResult___exp__h676577 ; + _theResult___fst_exp__h676059 : + _theResult___exp__h676575 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11230 = - (guard__h667962 == 2'b0) ? - _theResult___fst_exp__h676061 : + (guard__h667960 == 2'b0) ? + _theResult___fst_exp__h676059 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h676577 : - _theResult___fst_exp__h676061) ; + _theResult___exp__h676575 : + _theResult___fst_exp__h676059) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11874 = - (guard__h667962 == 2'b0 || + (guard__h667960 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - sfdin__h676055[56:34] : - _theResult___sfd__h676578 ; + sfdin__h676053[56:34] : + _theResult___sfd__h676576 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11876 = - (guard__h667962 == 2'b0) ? - sfdin__h676055[56:34] : + (guard__h667960 == 2'b0) ? + sfdin__h676053[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h676578 : - sfdin__h676055[56:34]) ; + _theResult___sfd__h676576 : + sfdin__h676053[56:34]) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d8433 = - (guard__h576464 == 2'b0 || + (guard__h576462 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h584565 : - _theResult___exp__h585081 ; + _theResult___fst_exp__h584563 : + _theResult___exp__h585079 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d8436 = - (guard__h576464 == 2'b0) ? - _theResult___fst_exp__h584565 : + (guard__h576462 == 2'b0) ? + _theResult___fst_exp__h584563 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h585081 : - _theResult___fst_exp__h584565) ; + _theResult___exp__h585079 : + _theResult___fst_exp__h584563) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9080 = - (guard__h576464 == 2'b0 || + (guard__h576462 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - sfdin__h584559[56:34] : - _theResult___sfd__h585082 ; + sfdin__h584557[56:34] : + _theResult___sfd__h585080 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9082 = - (guard__h576464 == 2'b0) ? - sfdin__h584559[56:34] : + (guard__h576462 == 2'b0) ? + sfdin__h584557[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h585082 : - sfdin__h584559[56:34]) ; + _theResult___sfd__h585080 : + sfdin__h584557[56:34]) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9830 = - (guard__h622215 == 2'b0 || + (guard__h622213 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h630314 : - _theResult___exp__h630830 ; + _theResult___fst_exp__h630312 : + _theResult___exp__h630828 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9833 = - (guard__h622215 == 2'b0) ? - _theResult___fst_exp__h630314 : + (guard__h622213 == 2'b0) ? + _theResult___fst_exp__h630312 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h630830 : - _theResult___fst_exp__h630314) ; + _theResult___exp__h630828 : + _theResult___fst_exp__h630312) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13207 = - (guard__h735638 == 2'b0 || + (guard__h735635 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___fst_exp__h743864 : - _theResult___exp__h744593 ; + _theResult___fst_exp__h743861 : + _theResult___exp__h744590 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13209 = - (guard__h735638 == 2'b0) ? - _theResult___fst_exp__h743864 : + (guard__h735635 == 2'b0) ? + _theResult___fst_exp__h743861 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___exp__h744593 : - _theResult___fst_exp__h743864) ; + _theResult___exp__h744590 : + _theResult___fst_exp__h743861) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13291 = - (guard__h735638 == 2'b0 || + (guard__h735635 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - sfdin__h743858[56:5] : - _theResult___sfd__h744594 ; + sfdin__h743855[56:5] : + _theResult___sfd__h744591 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13293 = - (guard__h735638 == 2'b0) ? - sfdin__h743858[56:5] : + (guard__h735635 == 2'b0) ? + sfdin__h743855[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___sfd__h744594 : - sfdin__h743858[56:5]) ; + _theResult___sfd__h744591 : + sfdin__h743855[56:5]) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13917 = - (guard__h813795 == 2'b0 || + (guard__h813792 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___fst_exp__h822021 : - _theResult___exp__h822750 ; + _theResult___fst_exp__h822018 : + _theResult___exp__h822747 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13919 = - (guard__h813795 == 2'b0) ? - _theResult___fst_exp__h822021 : + (guard__h813792 == 2'b0) ? + _theResult___fst_exp__h822018 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___exp__h822750 : - _theResult___fst_exp__h822021) ; + _theResult___exp__h822747 : + _theResult___fst_exp__h822018) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14000 = - (guard__h813795 == 2'b0 || + (guard__h813792 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - sfdin__h822015[56:5] : - _theResult___sfd__h822751 ; + sfdin__h822012[56:5] : + _theResult___sfd__h822748 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14002 = - (guard__h813795 == 2'b0) ? - sfdin__h822015[56:5] : + (guard__h813792 == 2'b0) ? + sfdin__h822012[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___sfd__h822751 : - sfdin__h822015[56:5]) ; + _theResult___sfd__h822748 : + sfdin__h822012[56:5]) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14687 = - (guard__h774491 == 2'b0 || + (guard__h774488 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___fst_exp__h782717 : - _theResult___exp__h783446 ; + _theResult___fst_exp__h782714 : + _theResult___exp__h783443 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14689 = - (guard__h774491 == 2'b0) ? - _theResult___fst_exp__h782717 : + (guard__h774488 == 2'b0) ? + _theResult___fst_exp__h782714 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___exp__h783446 : - _theResult___fst_exp__h782717) ; + _theResult___exp__h783443 : + _theResult___fst_exp__h782714) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14770 = - (guard__h774491 == 2'b0 || + (guard__h774488 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - sfdin__h782711[56:5] : - _theResult___sfd__h783447 ; + sfdin__h782708[56:5] : + _theResult___sfd__h783444 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14772 = - (guard__h774491 == 2'b0) ? - sfdin__h782711[56:5] : + (guard__h774488 == 2'b0) ? + sfdin__h782708[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___sfd__h783447 : - sfdin__h782711[56:5]) ; + _theResult___sfd__h783444 : + sfdin__h782708[56:5]) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10377 = - (guard__h639852 == 2'b0 || + (guard__h639850 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h648080 : - _theResult___exp__h648596 ; + _theResult___fst_exp__h648078 : + _theResult___exp__h648594 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10379 = - (guard__h639852 == 2'b0) ? - _theResult___fst_exp__h648080 : + (guard__h639850 == 2'b0) ? + _theResult___fst_exp__h648078 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h648596 : - _theResult___fst_exp__h648080) ; + _theResult___exp__h648594 : + _theResult___fst_exp__h648078) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10523 = - (guard__h639852 == 2'b0 || + (guard__h639850 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - sfdin__h648074[56:34] : - _theResult___sfd__h648597 ; + sfdin__h648072[56:34] : + _theResult___sfd__h648595 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10525 = - (guard__h639852 == 2'b0) ? - sfdin__h648074[56:34] : + (guard__h639850 == 2'b0) ? + sfdin__h648072[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h648597 : - sfdin__h648074[56:34]) ; + _theResult___sfd__h648595 : + sfdin__h648072[56:34]) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11774 = - (guard__h685599 == 2'b0 || + (guard__h685597 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h693827 : - _theResult___exp__h694343 ; + _theResult___fst_exp__h693825 : + _theResult___exp__h694341 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11776 = - (guard__h685599 == 2'b0) ? - _theResult___fst_exp__h693827 : + (guard__h685597 == 2'b0) ? + _theResult___fst_exp__h693825 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h694343 : - _theResult___fst_exp__h693827) ; + _theResult___exp__h694341 : + _theResult___fst_exp__h693825) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11920 = - (guard__h685599 == 2'b0 || + (guard__h685597 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - sfdin__h693821[56:34] : - _theResult___sfd__h694344 ; + sfdin__h693819[56:34] : + _theResult___sfd__h694342 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11922 = - (guard__h685599 == 2'b0) ? - sfdin__h693821[56:34] : + (guard__h685597 == 2'b0) ? + sfdin__h693819[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h694344 : - sfdin__h693821[56:34]) ; + _theResult___sfd__h694342 : + sfdin__h693819[56:34]) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d8980 = - (guard__h594103 == 2'b0 || + (guard__h594101 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h602331 : - _theResult___exp__h602847 ; + _theResult___fst_exp__h602329 : + _theResult___exp__h602845 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d8982 = - (guard__h594103 == 2'b0) ? - _theResult___fst_exp__h602331 : + (guard__h594101 == 2'b0) ? + _theResult___fst_exp__h602329 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h602847 : - _theResult___fst_exp__h602331) ; + _theResult___exp__h602845 : + _theResult___fst_exp__h602329) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9126 = - (guard__h594103 == 2'b0 || + (guard__h594101 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - sfdin__h602325[56:34] : - _theResult___sfd__h602848 ; + sfdin__h602323[56:34] : + _theResult___sfd__h602846 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9128 = - (guard__h594103 == 2'b0) ? - sfdin__h602325[56:34] : + (guard__h594101 == 2'b0) ? + sfdin__h602323[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h602848 : - sfdin__h602325[56:34]) ; + _theResult___sfd__h602846 : + sfdin__h602323[56:34]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13164 = - (guard__h726326 == 2'b0 || + (guard__h726323 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___fst_exp__h734287 : - _theResult___exp__h734942 ; + _theResult___fst_exp__h734284 : + _theResult___exp__h734939 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13166 = - (guard__h726326 == 2'b0) ? - _theResult___fst_exp__h734287 : + (guard__h726323 == 2'b0) ? + _theResult___fst_exp__h734284 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___exp__h734942 : - _theResult___fst_exp__h734287) ; + _theResult___exp__h734939 : + _theResult___fst_exp__h734284) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13238 = - (guard__h744707 == 2'b0 || + (guard__h744704 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___fst_exp__h752697 : - _theResult___exp__h753377 ; + _theResult___fst_exp__h752694 : + _theResult___exp__h753374 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13240 = - (guard__h744707 == 2'b0) ? - _theResult___fst_exp__h752697 : + (guard__h744704 == 2'b0) ? + _theResult___fst_exp__h752694 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___exp__h753377 : - _theResult___fst_exp__h752697) ; + _theResult___exp__h753374 : + _theResult___fst_exp__h752694) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13264 = - (guard__h726326 == 2'b0 || + (guard__h726323 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___snd__h734238[56:5] : - _theResult___sfd__h734943 ; + _theResult___snd__h734235[56:5] : + _theResult___sfd__h734940 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13266 = - (guard__h726326 == 2'b0) ? - _theResult___snd__h734238[56:5] : + (guard__h726323 == 2'b0) ? + _theResult___snd__h734235[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___sfd__h734943 : - _theResult___snd__h734238[56:5]) ; + _theResult___sfd__h734940 : + _theResult___snd__h734235[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13310 = - (guard__h744707 == 2'b0 || + (guard__h744704 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___snd__h752643[56:5] : - _theResult___sfd__h753378 ; + _theResult___snd__h752640[56:5] : + _theResult___sfd__h753375 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13312 = - (guard__h744707 == 2'b0) ? - _theResult___snd__h752643[56:5] : + (guard__h744704 == 2'b0) ? + _theResult___snd__h752640[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___sfd__h753378 : - _theResult___snd__h752643[56:5]) ; + _theResult___sfd__h753375 : + _theResult___snd__h752640[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13879 = - (guard__h804483 == 2'b0 || + (guard__h804480 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___fst_exp__h812444 : - _theResult___exp__h813099 ; + _theResult___fst_exp__h812441 : + _theResult___exp__h813096 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13881 = - (guard__h804483 == 2'b0) ? - _theResult___fst_exp__h812444 : + (guard__h804480 == 2'b0) ? + _theResult___fst_exp__h812441 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___exp__h813099 : - _theResult___fst_exp__h812444) ; + _theResult___exp__h813096 : + _theResult___fst_exp__h812441) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13948 = - (guard__h822864 == 2'b0 || + (guard__h822861 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___fst_exp__h830854 : - _theResult___exp__h831534 ; + _theResult___fst_exp__h830851 : + _theResult___exp__h831531 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13950 = - (guard__h822864 == 2'b0) ? - _theResult___fst_exp__h830854 : + (guard__h822861 == 2'b0) ? + _theResult___fst_exp__h830851 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___exp__h831534 : - _theResult___fst_exp__h830854) ; + _theResult___exp__h831531 : + _theResult___fst_exp__h830851) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13974 = - (guard__h804483 == 2'b0 || + (guard__h804480 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___snd__h812395[56:5] : - _theResult___sfd__h813100 ; + _theResult___snd__h812392[56:5] : + _theResult___sfd__h813097 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13976 = - (guard__h804483 == 2'b0) ? - _theResult___snd__h812395[56:5] : + (guard__h804480 == 2'b0) ? + _theResult___snd__h812392[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___sfd__h813100 : - _theResult___snd__h812395[56:5]) ; + _theResult___sfd__h813097 : + _theResult___snd__h812392[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14019 = - (guard__h822864 == 2'b0 || + (guard__h822861 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___snd__h830800[56:5] : - _theResult___sfd__h831535 ; + _theResult___snd__h830797[56:5] : + _theResult___sfd__h831532 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14021 = - (guard__h822864 == 2'b0) ? - _theResult___snd__h830800[56:5] : + (guard__h822861 == 2'b0) ? + _theResult___snd__h830797[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___sfd__h831535 : - _theResult___snd__h830800[56:5]) ; + _theResult___sfd__h831532 : + _theResult___snd__h830797[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14649 = - (guard__h765179 == 2'b0 || + (guard__h765176 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___fst_exp__h773140 : - _theResult___exp__h773795 ; + _theResult___fst_exp__h773137 : + _theResult___exp__h773792 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14651 = - (guard__h765179 == 2'b0) ? - _theResult___fst_exp__h773140 : + (guard__h765176 == 2'b0) ? + _theResult___fst_exp__h773137 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___exp__h773795 : - _theResult___fst_exp__h773140) ; + _theResult___exp__h773792 : + _theResult___fst_exp__h773137) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14718 = - (guard__h783560 == 2'b0 || + (guard__h783557 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___fst_exp__h791550 : - _theResult___exp__h792230 ; + _theResult___fst_exp__h791547 : + _theResult___exp__h792227 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14720 = - (guard__h783560 == 2'b0) ? - _theResult___fst_exp__h791550 : + (guard__h783557 == 2'b0) ? + _theResult___fst_exp__h791547 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___exp__h792230 : - _theResult___fst_exp__h791550) ; + _theResult___exp__h792227 : + _theResult___fst_exp__h791547) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14744 = - (guard__h765179 == 2'b0 || + (guard__h765176 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___snd__h773091[56:5] : - _theResult___sfd__h773796 ; + _theResult___snd__h773088[56:5] : + _theResult___sfd__h773793 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14746 = - (guard__h765179 == 2'b0) ? - _theResult___snd__h773091[56:5] : + (guard__h765176 == 2'b0) ? + _theResult___snd__h773088[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___sfd__h773796 : - _theResult___snd__h773091[56:5]) ; + _theResult___sfd__h773793 : + _theResult___snd__h773088[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14789 = - (guard__h783560 == 2'b0 || + (guard__h783557 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___snd__h791496[56:5] : - _theResult___sfd__h792231 ; + _theResult___snd__h791493[56:5] : + _theResult___sfd__h792228 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14791 = - (guard__h783560 == 2'b0) ? - _theResult___snd__h791496[56:5] : + (guard__h783557 == 2'b0) ? + _theResult___snd__h791493[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___sfd__h792231 : - _theResult___snd__h791496[56:5]) ; + _theResult___sfd__h792228 : + _theResult___snd__h791493[56:5]) ; assign IF_IF_IF_NOT_csrf_prv_reg_read__0286_EQ_3_0287_ETC___d20929 = (IF_IF_NOT_csrf_prv_reg_read__0286_EQ_3_0287_02_ETC___d20323[0] || IF_IF_NOT_csrf_prv_reg_read__0286_EQ_3_0287_02_ETC___d20323[1] || @@ -20080,139 +20078,139 @@ module mkCore(CLK, IF_checkForException_0654_BITS_3_TO_0_0907_EQ__ETC___d20927 == 4'd9 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10052 = - (guard__h630922 == 2'b0 || + (guard__h630920 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h638970 : - _theResult___exp__h639412 ; + _theResult___fst_exp__h638968 : + _theResult___exp__h639410 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10054 = - (guard__h630922 == 2'b0) ? - _theResult___fst_exp__h638970 : + (guard__h630920 == 2'b0) ? + _theResult___fst_exp__h638968 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h639412 : - _theResult___fst_exp__h638970) ; + _theResult___exp__h639410 : + _theResult___fst_exp__h638968) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10446 = - (guard__h648688 == 2'b0 || + (guard__h648686 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h656765 : - _theResult___exp__h657232 ; + _theResult___fst_exp__h656763 : + _theResult___exp__h657230 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10448 = - (guard__h648688 == 2'b0) ? - _theResult___fst_exp__h656765 : + (guard__h648686 == 2'b0) ? + _theResult___fst_exp__h656763 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h657232 : - _theResult___fst_exp__h656765) ; + _theResult___exp__h657230 : + _theResult___fst_exp__h656763) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10496 = - (guard__h630922 == 2'b0 || + (guard__h630920 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___snd__h638921[56:34] : - _theResult___sfd__h639413 ; + _theResult___snd__h638919[56:34] : + _theResult___sfd__h639411 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10498 = - (guard__h630922 == 2'b0) ? - _theResult___snd__h638921[56:34] : + (guard__h630920 == 2'b0) ? + _theResult___snd__h638919[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h639413 : - _theResult___snd__h638921[56:34]) ; + _theResult___sfd__h639411 : + _theResult___snd__h638919[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10542 = - (guard__h648688 == 2'b0 || + (guard__h648686 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___snd__h656711[56:34] : - _theResult___sfd__h657233 ; + _theResult___snd__h656709[56:34] : + _theResult___sfd__h657231 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10544 = - (guard__h648688 == 2'b0) ? - _theResult___snd__h656711[56:34] : + (guard__h648686 == 2'b0) ? + _theResult___snd__h656709[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h657233 : - _theResult___snd__h656711[56:34]) ; + _theResult___sfd__h657231 : + _theResult___snd__h656709[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11449 = - (guard__h676669 == 2'b0 || + (guard__h676667 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h684717 : - _theResult___exp__h685159 ; + _theResult___fst_exp__h684715 : + _theResult___exp__h685157 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11451 = - (guard__h676669 == 2'b0) ? - _theResult___fst_exp__h684717 : + (guard__h676667 == 2'b0) ? + _theResult___fst_exp__h684715 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h685159 : - _theResult___fst_exp__h684717) ; + _theResult___exp__h685157 : + _theResult___fst_exp__h684715) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11843 = - (guard__h694435 == 2'b0 || + (guard__h694433 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h702512 : - _theResult___exp__h702979 ; + _theResult___fst_exp__h702510 : + _theResult___exp__h702977 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11845 = - (guard__h694435 == 2'b0) ? - _theResult___fst_exp__h702512 : + (guard__h694433 == 2'b0) ? + _theResult___fst_exp__h702510 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h702979 : - _theResult___fst_exp__h702512) ; + _theResult___exp__h702977 : + _theResult___fst_exp__h702510) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11893 = - (guard__h676669 == 2'b0 || + (guard__h676667 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___snd__h684668[56:34] : - _theResult___sfd__h685160 ; + _theResult___snd__h684666[56:34] : + _theResult___sfd__h685158 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11895 = - (guard__h676669 == 2'b0) ? - _theResult___snd__h684668[56:34] : + (guard__h676667 == 2'b0) ? + _theResult___snd__h684666[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h685160 : - _theResult___snd__h684668[56:34]) ; + _theResult___sfd__h685158 : + _theResult___snd__h684666[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11939 = - (guard__h694435 == 2'b0 || + (guard__h694433 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___snd__h702458[56:34] : - _theResult___sfd__h702980 ; + _theResult___snd__h702456[56:34] : + _theResult___sfd__h702978 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11941 = - (guard__h694435 == 2'b0) ? - _theResult___snd__h702458[56:34] : + (guard__h694433 == 2'b0) ? + _theResult___snd__h702456[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h702980 : - _theResult___snd__h702458[56:34]) ; + _theResult___sfd__h702978 : + _theResult___snd__h702456[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d8655 = - (guard__h585173 == 2'b0 || + (guard__h585171 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h593221 : - _theResult___exp__h593663 ; + _theResult___fst_exp__h593219 : + _theResult___exp__h593661 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d8657 = - (guard__h585173 == 2'b0) ? - _theResult___fst_exp__h593221 : + (guard__h585171 == 2'b0) ? + _theResult___fst_exp__h593219 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h593663 : - _theResult___fst_exp__h593221) ; + _theResult___exp__h593661 : + _theResult___fst_exp__h593219) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9049 = - (guard__h602939 == 2'b0 || + (guard__h602937 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h611016 : - _theResult___exp__h611483 ; + _theResult___fst_exp__h611014 : + _theResult___exp__h611481 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9051 = - (guard__h602939 == 2'b0) ? - _theResult___fst_exp__h611016 : + (guard__h602937 == 2'b0) ? + _theResult___fst_exp__h611014 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h611483 : - _theResult___fst_exp__h611016) ; + _theResult___exp__h611481 : + _theResult___fst_exp__h611014) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9099 = - (guard__h585173 == 2'b0 || + (guard__h585171 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___snd__h593172[56:34] : - _theResult___sfd__h593664 ; + _theResult___snd__h593170[56:34] : + _theResult___sfd__h593662 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9101 = - (guard__h585173 == 2'b0) ? - _theResult___snd__h593172[56:34] : + (guard__h585171 == 2'b0) ? + _theResult___snd__h593170[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h593664 : - _theResult___snd__h593172[56:34]) ; + _theResult___sfd__h593662 : + _theResult___snd__h593170[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9145 = - (guard__h602939 == 2'b0 || + (guard__h602937 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___snd__h610962[56:34] : - _theResult___sfd__h611484 ; + _theResult___snd__h610960[56:34] : + _theResult___sfd__h611482 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9147 = - (guard__h602939 == 2'b0) ? - _theResult___snd__h610962[56:34] : + (guard__h602937 == 2'b0) ? + _theResult___snd__h610960[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h611484 : - _theResult___snd__h610962[56:34]) ; + _theResult___sfd__h611482 : + _theResult___snd__h610960[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d13136 = - (_theResult___fst_exp__h752697 == 11'd2047) ? + (_theResult___fst_exp__h752694 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : @@ -20220,10 +20218,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard44707_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q161 : + CASE_guard44704_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q161 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q162) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d13851 = - (_theResult___fst_exp__h830854 == 11'd2047) ? + (_theResult___fst_exp__h830851 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -20231,10 +20229,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard22864_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q178 : + CASE_guard22861_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q178 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q179) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d14058 = - (_theResult___fst_exp__h812444 == 11'd2047) ? + (_theResult___fst_exp__h812441 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -20242,10 +20240,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard04483_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q184 : + CASE_guard04480_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q184 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q185) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d14085 = - (_theResult___fst_exp__h830854 == 11'd2047) ? + (_theResult___fst_exp__h830851 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -20253,10 +20251,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard22864_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q182 : + CASE_guard22861_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q182 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q183) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d14621 = - (_theResult___fst_exp__h791550 == 11'd2047) ? + (_theResult___fst_exp__h791547 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -20264,10 +20262,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard83560_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q209 : + CASE_guard83557_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q209 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q210) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d14827 = - (_theResult___fst_exp__h773140 == 11'd2047) ? + (_theResult___fst_exp__h773137 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -20275,10 +20273,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard65179_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q215 : + CASE_guard65176_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q215 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q216) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d14854 = - (_theResult___fst_exp__h791550 == 11'd2047) ? + (_theResult___fst_exp__h791547 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -20286,14 +20284,14 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard83560_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q213 : + CASE_guard83557_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q213 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q214) ; assign IF_IF_NOT_csrf_prv_reg_read__0286_EQ_3_0287_02_ETC___d20323 = - (_theResult____h920232 == 16'd0 && + (_theResult____h920230 == 16'd0 && (csrf_prv_reg == 2'd0 || csrf_prv_reg == 2'd1 && csrf_ie_vec_1)) ? - enabled_ints__h920803 : - _theResult____h920232 ; + enabled_ints__h920801 : + _theResult____h920230 ; assign IF_IF_NOT_csrf_prv_reg_read__0286_EQ_3_0287_02_ETC___d20676 = IF_IF_NOT_csrf_prv_reg_read__0286_EQ_3_0287_02_ETC___d20323[0] || IF_IF_NOT_csrf_prv_reg_read__0286_EQ_3_0287_02_ETC___d20323[1] || @@ -20738,148 +20736,148 @@ module mkCore(CLK, 5'd0 : IF_IF_coreFix_aluExe_1_exeToFinQ_first__7830_B_ETC___d17975 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d12734 = - ((f1_exp__h714899 == 8'd0) ? - (f1_sfd__h714900[22] ? + ((f1_exp__h714896 == 8'd0) ? + (f1_sfd__h714897[22] ? 6'd2 : - (f1_sfd__h714900[21] ? + (f1_sfd__h714897[21] ? 6'd3 : - (f1_sfd__h714900[20] ? + (f1_sfd__h714897[20] ? 6'd4 : - (f1_sfd__h714900[19] ? + (f1_sfd__h714897[19] ? 6'd5 : - (f1_sfd__h714900[18] ? + (f1_sfd__h714897[18] ? 6'd6 : - (f1_sfd__h714900[17] ? + (f1_sfd__h714897[17] ? 6'd7 : - (f1_sfd__h714900[16] ? + (f1_sfd__h714897[16] ? 6'd8 : - (f1_sfd__h714900[15] ? + (f1_sfd__h714897[15] ? 6'd9 : - (f1_sfd__h714900[14] ? + (f1_sfd__h714897[14] ? 6'd10 : - (f1_sfd__h714900[13] ? + (f1_sfd__h714897[13] ? 6'd11 : - (f1_sfd__h714900[12] ? + (f1_sfd__h714897[12] ? 6'd12 : - (f1_sfd__h714900[11] ? + (f1_sfd__h714897[11] ? 6'd13 : - (f1_sfd__h714900[10] ? + (f1_sfd__h714897[10] ? 6'd14 : - (f1_sfd__h714900[9] ? + (f1_sfd__h714897[9] ? 6'd15 : - (f1_sfd__h714900[8] ? + (f1_sfd__h714897[8] ? 6'd16 : - (f1_sfd__h714900[7] ? + (f1_sfd__h714897[7] ? 6'd17 : - (f1_sfd__h714900[6] ? + (f1_sfd__h714897[6] ? 6'd18 : - (f1_sfd__h714900[5] ? + (f1_sfd__h714897[5] ? 6'd19 : - (f1_sfd__h714900[4] ? + (f1_sfd__h714897[4] ? 6'd20 : - (f1_sfd__h714900[3] ? + (f1_sfd__h714897[3] ? 6'd21 : - (f1_sfd__h714900[2] ? + (f1_sfd__h714897[2] ? 6'd22 : - (f1_sfd__h714900[1] ? + (f1_sfd__h714897[1] ? 6'd23 : - (f1_sfd__h714900[0] ? + (f1_sfd__h714897[0] ? 6'd24 : 6'd57))))))))))))))))))))))) : 6'd1) - 6'd1 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13140 = - (f1_exp__h714899 == 8'd255 && f1_sfd__h714900 != 23'd0 || - (f1_exp__h714899 == 8'd255 || f1_exp__h714899 == 8'd0) && - f1_sfd__h714900 == 23'd0) ? + (f1_exp__h714896 == 8'd255 && f1_sfd__h714897 != 23'd0 || + (f1_exp__h714896 == 8'd255 || f1_exp__h714896 == 8'd0) && + f1_sfd__h714897 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - ((f1_exp__h714899 == 8'd0) ? + ((f1_exp__h714896 == 8'd0) ? IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d12795 : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d13138) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13323 = - (f1_exp__h714899 == 8'd255 && f1_sfd__h714900 != 23'd0) ? - _theResult___snd_fst_sfd__h715215 : - _theResult___fst_sfd__h753496 ; + (f1_exp__h714896 == 8'd255 && f1_sfd__h714897 != 23'd0) ? + _theResult___snd_fst_sfd__h715212 : + _theResult___fst_sfd__h753493 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13324 = { IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13140, - (f1_exp__h714899 == 8'd255) ? + (f1_exp__h714896 == 8'd255) ? 11'd2047 : - _theResult___fst_exp__h753492, + _theResult___fst_exp__h753489, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13323 } ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13464 = - ((f3_exp__h793197 == 8'd0) ? - (f3_sfd__h793198[22] ? + ((f3_exp__h793194 == 8'd0) ? + (f3_sfd__h793195[22] ? 6'd2 : - (f3_sfd__h793198[21] ? + (f3_sfd__h793195[21] ? 6'd3 : - (f3_sfd__h793198[20] ? + (f3_sfd__h793195[20] ? 6'd4 : - (f3_sfd__h793198[19] ? + (f3_sfd__h793195[19] ? 6'd5 : - (f3_sfd__h793198[18] ? + (f3_sfd__h793195[18] ? 6'd6 : - (f3_sfd__h793198[17] ? + (f3_sfd__h793195[17] ? 6'd7 : - (f3_sfd__h793198[16] ? + (f3_sfd__h793195[16] ? 6'd8 : - (f3_sfd__h793198[15] ? + (f3_sfd__h793195[15] ? 6'd9 : - (f3_sfd__h793198[14] ? + (f3_sfd__h793195[14] ? 6'd10 : - (f3_sfd__h793198[13] ? + (f3_sfd__h793195[13] ? 6'd11 : - (f3_sfd__h793198[12] ? + (f3_sfd__h793195[12] ? 6'd12 : - (f3_sfd__h793198[11] ? + (f3_sfd__h793195[11] ? 6'd13 : - (f3_sfd__h793198[10] ? + (f3_sfd__h793195[10] ? 6'd14 : - (f3_sfd__h793198[9] ? + (f3_sfd__h793195[9] ? 6'd15 : - (f3_sfd__h793198[8] ? + (f3_sfd__h793195[8] ? 6'd16 : - (f3_sfd__h793198[7] ? + (f3_sfd__h793195[7] ? 6'd17 : - (f3_sfd__h793198[6] ? + (f3_sfd__h793195[6] ? 6'd18 : - (f3_sfd__h793198[5] ? + (f3_sfd__h793195[5] ? 6'd19 : - (f3_sfd__h793198[4] ? + (f3_sfd__h793195[4] ? 6'd20 : - (f3_sfd__h793198[3] ? + (f3_sfd__h793195[3] ? 6'd21 : - (f3_sfd__h793198[2] ? + (f3_sfd__h793195[2] ? 6'd22 : - (f3_sfd__h793198[1] ? + (f3_sfd__h793195[1] ? 6'd23 : - (f3_sfd__h793198[0] ? + (f3_sfd__h793195[0] ? 6'd24 : 6'd57))))))))))))))))))))))) : 6'd1) - 6'd1 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13855 = - (f3_exp__h793197 == 8'd255 && f3_sfd__h793198 != 23'd0 || - (f3_exp__h793197 == 8'd255 || f3_exp__h793197 == 8'd0) && - f3_sfd__h793198 == 23'd0) ? + (f3_exp__h793194 == 8'd255 && f3_sfd__h793195 != 23'd0 || + (f3_exp__h793194 == 8'd255 || f3_exp__h793194 == 8'd0) && + f3_sfd__h793195 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - ((f3_exp__h793197 == 8'd0) ? + ((f3_exp__h793194 == 8'd0) ? IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d13510 : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d13853) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14032 = - (f3_exp__h793197 == 8'd255 && f3_sfd__h793198 != 23'd0) ? - _theResult___snd_fst_sfd__h793513 : - _theResult___fst_sfd__h831653 ; + (f3_exp__h793194 == 8'd255 && f3_sfd__h793195 != 23'd0) ? + _theResult___snd_fst_sfd__h793510 : + _theResult___fst_sfd__h831650 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14033 = - { (f3_exp__h793197 == 8'd255) ? + { (f3_exp__h793194 == 8'd255) ? 11'd2047 : - _theResult___fst_exp__h831649, + _theResult___fst_exp__h831646, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14032 } ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14088 = - (f3_exp__h793197 == 8'd0) ? + (f3_exp__h793194 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13391 ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13393 ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != @@ -20889,85 +20887,85 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14060) : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d14087 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14089 = - (f3_exp__h793197 == 8'd255 && f3_sfd__h793198 != 23'd0 || - (f3_exp__h793197 == 8'd255 || f3_exp__h793197 == 8'd0) && - f3_sfd__h793198 == 23'd0) ? + (f3_exp__h793194 == 8'd255 && f3_sfd__h793195 != 23'd0 || + (f3_exp__h793194 == 8'd255 || f3_exp__h793194 == 8'd0) && + f3_sfd__h793195 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14088 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14234 = - ((f2_exp__h753893 == 8'd0) ? - (f2_sfd__h753894[22] ? + ((f2_exp__h753890 == 8'd0) ? + (f2_sfd__h753891[22] ? 6'd2 : - (f2_sfd__h753894[21] ? + (f2_sfd__h753891[21] ? 6'd3 : - (f2_sfd__h753894[20] ? + (f2_sfd__h753891[20] ? 6'd4 : - (f2_sfd__h753894[19] ? + (f2_sfd__h753891[19] ? 6'd5 : - (f2_sfd__h753894[18] ? + (f2_sfd__h753891[18] ? 6'd6 : - (f2_sfd__h753894[17] ? + (f2_sfd__h753891[17] ? 6'd7 : - (f2_sfd__h753894[16] ? + (f2_sfd__h753891[16] ? 6'd8 : - (f2_sfd__h753894[15] ? + (f2_sfd__h753891[15] ? 6'd9 : - (f2_sfd__h753894[14] ? + (f2_sfd__h753891[14] ? 6'd10 : - (f2_sfd__h753894[13] ? + (f2_sfd__h753891[13] ? 6'd11 : - (f2_sfd__h753894[12] ? + (f2_sfd__h753891[12] ? 6'd12 : - (f2_sfd__h753894[11] ? + (f2_sfd__h753891[11] ? 6'd13 : - (f2_sfd__h753894[10] ? + (f2_sfd__h753891[10] ? 6'd14 : - (f2_sfd__h753894[9] ? + (f2_sfd__h753891[9] ? 6'd15 : - (f2_sfd__h753894[8] ? + (f2_sfd__h753891[8] ? 6'd16 : - (f2_sfd__h753894[7] ? + (f2_sfd__h753891[7] ? 6'd17 : - (f2_sfd__h753894[6] ? + (f2_sfd__h753891[6] ? 6'd18 : - (f2_sfd__h753894[5] ? + (f2_sfd__h753891[5] ? 6'd19 : - (f2_sfd__h753894[4] ? + (f2_sfd__h753891[4] ? 6'd20 : - (f2_sfd__h753894[3] ? + (f2_sfd__h753891[3] ? 6'd21 : - (f2_sfd__h753894[2] ? + (f2_sfd__h753891[2] ? 6'd22 : - (f2_sfd__h753894[1] ? + (f2_sfd__h753891[1] ? 6'd23 : - (f2_sfd__h753894[0] ? + (f2_sfd__h753891[0] ? 6'd24 : 6'd57))))))))))))))))))))))) : 6'd1) - 6'd1 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14625 = - (f2_exp__h753893 == 8'd255 && f2_sfd__h753894 != 23'd0 || - (f2_exp__h753893 == 8'd255 || f2_exp__h753893 == 8'd0) && - f2_sfd__h753894 == 23'd0) ? + (f2_exp__h753890 == 8'd255 && f2_sfd__h753891 != 23'd0 || + (f2_exp__h753890 == 8'd255 || f2_exp__h753890 == 8'd0) && + f2_sfd__h753891 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - ((f2_exp__h753893 == 8'd0) ? + ((f2_exp__h753890 == 8'd0) ? IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d14280 : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d14623) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14802 = - (f2_exp__h753893 == 8'd255 && f2_sfd__h753894 != 23'd0) ? - _theResult___snd_fst_sfd__h754209 : - _theResult___fst_sfd__h792349 ; + (f2_exp__h753890 == 8'd255 && f2_sfd__h753891 != 23'd0) ? + _theResult___snd_fst_sfd__h754206 : + _theResult___fst_sfd__h792346 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14803 = - { (f2_exp__h753893 == 8'd255) ? + { (f2_exp__h753890 == 8'd255) ? 11'd2047 : - _theResult___fst_exp__h792345, + _theResult___fst_exp__h792342, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14802 } ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14857 = - (f2_exp__h753893 == 8'd0) ? + (f2_exp__h753890 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14161 ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14163 ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != @@ -20977,15 +20975,15 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14829) : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d14856 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14858 = - (f2_exp__h753893 == 8'd255 && f2_sfd__h753894 != 23'd0 || - (f2_exp__h753893 == 8'd255 || f2_exp__h753893 == 8'd0) && - f2_sfd__h753894 == 23'd0) ? + (f2_exp__h753890 == 8'd255 && f2_sfd__h753891 != 23'd0 || + (f2_exp__h753890 == 8'd255 || f2_exp__h753890 == 8'd0) && + f2_sfd__h753891 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14857 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14913 = - (f1_exp__h714899 == 8'd0) ? + (f1_exp__h714896 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12661 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12663 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14892[4] : @@ -20993,7 +20991,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12799 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14909[4] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14954 = - (f2_exp__h753893 == 8'd0) ? + (f2_exp__h753890 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14161 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14163 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14933[4] : @@ -21001,7 +20999,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14284 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14950[4] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14998 = - (f3_exp__h793197 == 8'd0) ? + (f3_exp__h793194 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13391 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13393 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14977[4] : @@ -21009,7 +21007,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13514 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14994[4] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15013 = - (f1_exp__h714899 == 8'd0) ? + (f1_exp__h714896 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12661 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12663 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14892[3] : @@ -21017,7 +21015,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12799 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14909[3] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15023 = - (f2_exp__h753893 == 8'd0) ? + (f2_exp__h753890 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14161 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14163 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14933[3] : @@ -21025,7 +21023,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14284 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14950[3] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15034 = - (f3_exp__h793197 == 8'd0) ? + (f3_exp__h793194 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13391 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13393 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14977[3] : @@ -21033,70 +21031,70 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13514 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14994[3] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15053 = - (f1_exp__h714899 == 8'd0) ? + (f1_exp__h714896 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12661 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12663 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14892[2] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12798 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15051 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15067 = - (f2_exp__h753893 == 8'd0) ? + (f2_exp__h753890 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14161 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14163 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14933[2] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14283 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15065 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15082 = - (f3_exp__h793197 == 8'd0) ? + (f3_exp__h793194 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13391 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13393 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14977[2] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13513 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15080 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15099 = - (f1_exp__h714899 == 8'd0) ? + (f1_exp__h714896 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12661 && (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12663 || _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14892[1]) : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12798 && IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15097 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15111 = - (f2_exp__h753893 == 8'd0) ? + (f2_exp__h753890 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14161 && (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14163 || _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14933[1]) : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14283 && IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15109 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15124 = - (f3_exp__h793197 == 8'd0) ? + (f3_exp__h793194 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13391 && (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13393 || _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14977[1]) : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13513 && IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15122 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15141 = - (f1_exp__h714899 == 8'd0) ? + (f1_exp__h714896 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12661 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12663 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14892[0] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12798 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15139 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15153 = - (f2_exp__h753893 == 8'd0) ? + (f2_exp__h753890 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14161 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14163 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14933[0] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14283 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15151 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15166 = - (f3_exp__h793197 == 8'd0) ? + (f3_exp__h793194 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13391 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13393 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14977[0] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13513 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15164 ; assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_cRqR_ETC___d7249 = - _theResult_____2__h515368 == v__h514824 ; + _theResult_____2__h515366 == v__h514822 ; assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_cRqR_ETC___d7257 = IF_IF_coreFix_memExe_dMem_cache_m_banks_0_cRqR_ETC___d7249 && (IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d7227 || @@ -21111,7 +21109,7 @@ module mkCore(CLK, (IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d7240 || coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty) ; assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_from_ETC___d7340 = - _theResult_____2__h526145 == v__h516844 ; + _theResult_____2__h526143 == v__h516842 ; assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_from_ETC___d7349 = IF_IF_coreFix_memExe_dMem_cache_m_banks_0_from_ETC___d7340 && (IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d7321 || @@ -21140,9 +21138,9 @@ module mkCore(CLK, EN_dCacheToParent_fromP_enq ? coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[518:3] : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[518:3], - x__h521675 } ; + x__h521673 } ; assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_rqTo_ETC___d7500 = - _theResult_____2__h533238 == v__h532563 ; + _theResult_____2__h533236 == v__h532561 ; assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_rqTo_ETC___d7508 = IF_IF_coreFix_memExe_dMem_cache_m_banks_0_rqTo_ETC___d7500 && (IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d7480 || @@ -21157,7 +21155,7 @@ module mkCore(CLK, (IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d7493 || coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty) ; assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_rsTo_ETC___d7584 = - _theResult_____2__h543873 == v__h535012 ; + _theResult_____2__h543871 == v__h535010 ; assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_rsTo_ETC___d7592 = IF_IF_coreFix_memExe_dMem_cache_m_banks_0_rsTo_ETC___d7584 && (IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d7564 || @@ -21554,7 +21552,7 @@ module mkCore(CLK, 5'd15 : 5'd28))))))))))))) } ; assign IF_IF_coreFix_memExe_forwardQ_deqReq_lat_1_wha_ETC___d7870 = - _theResult_____2__h561485 == v__h559811 ; + _theResult_____2__h561483 == v__h559809 ; assign IF_IF_coreFix_memExe_forwardQ_deqReq_lat_1_wha_ETC___d7878 = IF_IF_coreFix_memExe_forwardQ_deqReq_lat_1_wha_ETC___d7870 && (IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d7851 || @@ -21569,7 +21567,7 @@ module mkCore(CLK, (IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d7864 || coreFix_memExe_forwardQ_empty) ; assign IF_IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_w_ETC___d7788 = - _theResult_____2__h557706 == v__h556032 ; + _theResult_____2__h557704 == v__h556030 ; assign IF_IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_w_ETC___d7796 = IF_IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_w_ETC___d7788 && (IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d7769 || @@ -21583,16 +21581,16 @@ module mkCore(CLK, !coreFix_memExe_memRespLdQ_enqReq_rl[134]) && (IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d7782 || coreFix_memExe_memRespLdQ_empty) ; - assign IF_IF_csrf_prv_reg_read__0286_ULE_1_2614_AND_I_ETC___d22894 = - (csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22647 ? + assign IF_IF_csrf_prv_reg_read__0286_ULE_1_2614_AND_I_ETC___d22896 = + (csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22648 ? !csrf_stcc_reg[34] : !csrf_mtcc_reg[34]) ? - { x__h1000884[11:0], - x1_avValue_new_pcc_capFat_bounds_baseBits__h1000887 } : - { x__h1000884[11:3], - x__h1000905[5:3], - x1_avValue_new_pcc_capFat_bounds_baseBits__h1000887[13:3], - x__h1000905[2:0] } ; + { x__h1000919[11:0], + x1_avValue_new_pcc_capFat_bounds_baseBits__h1000922 } : + { x__h1000919[11:3], + x__h1000940[5:3], + x1_avValue_new_pcc_capFat_bounds_baseBits__h1000922[13:3], + x__h1000940[2:0] } ; assign IF_IF_fetchStage_pipelines_0_first__0256_BITS__ETC___d21231 = IF_fetchStage_pipelines_0_first__0256_BITS_268_ETC___d21222 ? !csrf_rg_dcsr[2] && @@ -21832,48 +21830,48 @@ module mkCore(CLK, IF_IF_IF_NOT_csrf_prv_reg_read__0286_EQ_3_0287_ETC___d20929) ? 4'd0 : IF_IF_renameStage_rg_m_halt_req_0283_BIT_4_028_ETC___d20984 ; - assign IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23130 = - robdeqPort_0_deq_data_BITS_95_TO_32__q16[63] ? - x__h1008496[13:0] >= toBounds__h1008382 : - x__h1008496[13:0] <= toBoundsM1__h1008383 ; - assign IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23174 = + assign IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23132 = + robdeqPort_0_deq_data_BITS_95_TO_32__q17[63] ? + x__h1008531[13:0] >= toBounds__h1008417 : + x__h1008531[13:0] <= toBoundsM1__h1008418 ; + assign IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23176 = MUX_csrf_rg_dcsr$write_1__VAL_1[63] ? - x__h1008899[13:0] >= toBounds__h1008785 : - x__h1008899[13:0] <= toBoundsM1__h1008786 ; - assign IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23269 = - robdeqPort_0_deq_data_BITS_95_TO_32__q16[63] ? - x__h1009316[13:0] >= toBounds__h1009202 : - x__h1009316[13:0] <= toBoundsM1__h1009203 ; - assign IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23311 = + x__h1008934[13:0] >= toBounds__h1008820 : + x__h1008934[13:0] <= toBoundsM1__h1008821 ; + assign IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23271 = + robdeqPort_0_deq_data_BITS_95_TO_32__q17[63] ? + x__h1009351[13:0] >= toBounds__h1009237 : + x__h1009351[13:0] <= toBoundsM1__h1009238 ; + assign IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23313 = MUX_csrf_rg_dcsr$write_1__VAL_1[63] ? - x__h1009719[13:0] >= toBounds__h1009605 : - x__h1009719[13:0] <= toBoundsM1__h1009606 ; - assign IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23424 = - robdeqPort_0_deq_data_BITS_95_TO_32__q16[63] ? - x__h1010388[13:0] >= toBounds__h1010274 : - x__h1010388[13:0] <= toBoundsM1__h1010275 ; + x__h1009754[13:0] >= toBounds__h1009640 : + x__h1009754[13:0] <= toBoundsM1__h1009641 ; + assign IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23426 = + robdeqPort_0_deq_data_BITS_95_TO_32__q17[63] ? + x__h1010423[13:0] >= toBounds__h1010309 : + x__h1010423[13:0] <= toBoundsM1__h1010310 ; assign IF_INV_IF_coreFix_memExe_lsq_firstLd__498_BITS_ETC___d1954 = - { INV_x83399_BITS_108_TO_90__q34[0] ? x__h183519 : 6'd0, - x__h183679, - x__h183699 } ; + { INV_x83397_BITS_108_TO_90__q34[0] ? x__h183517 : 6'd0, + x__h183677, + x__h183697 } ; assign IF_INV_IF_coreFix_memExe_lsq_firstLd__498_BITS_ETC___d2120 = - { INV_x99251_BITS_108_TO_90__q36[0] ? x__h202270 : 6'd0, - x__h202430, - x__h202450 } ; + { INV_x99249_BITS_108_TO_90__q36[0] ? x__h202268 : 6'd0, + x__h202428, + x__h202448 } ; assign IF_INV_commitStage_commitTrap_2268_BITS_217_TO_ETC___d22580 = - INV_commitStage_commitTrap_BITS_217_TO_199__q15[0] ? - x__h994949 : + INV_commitStage_commitTrap_BITS_217_TO_199__q16[0] ? + x__h994947 : 6'd0 ; - assign IF_INV_commitStage_commitTrap_2268_BITS_217_TO_ETC___d22661 = - x__h995129[13:11] < repBound__h997599 ; - assign IF_INV_commitStage_commitTrap_2268_BITS_217_TO_ETC___d22663 = - pc_addrBits__h994740[13:11] < repBound__h997599 ; + assign IF_INV_commitStage_commitTrap_2268_BITS_217_TO_ETC___d22662 = + x__h995127[13:11] < repBound__h997634 ; + assign IF_INV_commitStage_commitTrap_2268_BITS_217_TO_ETC___d22664 = + pc_addrBits__h994738[13:11] < repBound__h997634 ; assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19778 = - tb__h906823 < repBound__h906826 ; + tb__h906821 < repBound__h906824 ; assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19779 = - x__h906765[13:11] < repBound__h906826 ; + x__h906763[13:11] < repBound__h906824 ; assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19781 = - cr_addrBits__h906358[13:11] < repBound__h906826 ; + cr_addrBits__h906356[13:11] < repBound__h906824 ; assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19791 = { IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19781, (IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19778 == @@ -21891,11 +21889,11 @@ module mkCore(CLK, 2'd1 : 2'd3) } ; assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19842 = - tb__h907371 < repBound__h907374 ; + tb__h907369 < repBound__h907372 ; assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19843 = - x__h907313[13:11] < repBound__h907374 ; + x__h907311[13:11] < repBound__h907372 ; assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19845 = - cr_addrBits__h906906[13:11] < repBound__h907374 ; + cr_addrBits__h906904[13:11] < repBound__h907372 ; assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19855 = { IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19845, (IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19842 == @@ -21913,11 +21911,11 @@ module mkCore(CLK, 2'd1 : 2'd3) } ; assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17662 = - tb__h867137 < repBound__h867140 ; + tb__h867136 < repBound__h867139 ; assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17663 = - x__h867079[13:11] < repBound__h867140 ; + x__h867078[13:11] < repBound__h867139 ; assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17665 = - cr_addrBits__h866672[13:11] < repBound__h867140 ; + cr_addrBits__h866671[13:11] < repBound__h867139 ; assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17675 = { IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17665, (IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17662 == @@ -21935,11 +21933,11 @@ module mkCore(CLK, 2'd1 : 2'd3) } ; assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17726 = - tb__h867685 < repBound__h867688 ; + tb__h867684 < repBound__h867687 ; assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17727 = - x__h867627[13:11] < repBound__h867688 ; + x__h867626[13:11] < repBound__h867687 ; assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17729 = - cr_addrBits__h867220[13:11] < repBound__h867688 ; + cr_addrBits__h867219[13:11] < repBound__h867687 ; assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17739 = { IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17729, (IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17726 == @@ -21958,26 +21956,26 @@ module mkCore(CLK, 2'd3) } ; assign IF_INV_coreFix_memExe_lsq_respLd_159_BITS_108__ETC___d2210 = { INV_coreFix_memExe_lsqrespLd_BITS_108_TO_90__q10[0] ? - x__h216836 : + x__h216834 : 6'd0, - x__h216996, - x__h217016 } ; + x__h216994, + x__h217014 } ; assign IF_INV_coreFix_memExe_respLrScAmoQ_data_0_233__ETC___d1273 = { INV_coreFix_memExe_respLrScAmoQ_data_0_BITS_10_ETC__q8[0] ? - x__h127341 : + x__h127340 : 6'd0, - x__h127501, - x__h127521 } ; + x__h127500, + x__h127520 } ; assign IF_INV_mmio_dataRespQ_data_0_389_BITS_108_TO_9_ETC___d1433 = { INV_mmio_dataRespQ_data_0_BITS_108_TO_90__q9[0] ? - x__h140257 : + x__h140256 : 6'd0, - x__h140417, - x__h140437 } ; + x__h140416, + x__h140436 } ; assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d12795 = (!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12661 || _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12663 || - _theResult___fst_exp__h734287 == 11'd2047) ? + _theResult___fst_exp__h734284 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : @@ -21985,12 +21983,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard26326_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q157 : + CASE_guard26323_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q157 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q158) ; assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d13510 = (!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13391 || _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13393 || - _theResult___fst_exp__h812444 == 11'd2047) ? + _theResult___fst_exp__h812441 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -21998,12 +21996,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard04483_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q174 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q175) ; + CASE_guard04480_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q176 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q177) ; assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d14280 = (!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14161 || _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14163 || - _theResult___fst_exp__h773140 == 11'd2047) ? + _theResult___fst_exp__h773137 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -22011,7 +22009,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard65179_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q205 : + CASE_guard65176_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q205 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q206) ; assign IF_NOT_IF_IF_NOT_csrf_prv_reg_read__0286_EQ_3__ETC___d20905 = IF_IF_NOT_csrf_prv_reg_read__0286_EQ_3_0287_02_ETC___d20323[0] ? @@ -23659,7 +23657,7 @@ module mkCore(CLK, checkForException___d20654[10:5], CASE_checkForException_0654_BITS_4_TO_0_0_chec_ETC__q257 } : IF_NOT_renameStage_rg_m_halt_req_0283_BIT_4_02_ETC___d20987 ; - assign IF_NOT_rob_deqPort_1_deq_data__3605_BIT_25_360_ETC___d23838 = + assign IF_NOT_rob_deqPort_1_deq_data__3607_BIT_25_360_ETC___d23840 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[274] || rob$deqPort_1_deq_data[469:465] == 5'd0 || @@ -23735,48 +23733,48 @@ module mkCore(CLK, assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15051 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12799 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14909[2] : - _theResult___fst_exp__h753480 == 11'd2047 && - _theResult___fst_sfd__h753481 == 52'd0 ; + _theResult___fst_exp__h753477 == 11'd2047 && + _theResult___fst_sfd__h753478 == 52'd0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15065 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14284 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14950[2] : - _theResult___fst_exp__h792333 == 11'd2047 && - _theResult___fst_sfd__h792334 == 52'd0 ; + _theResult___fst_exp__h792330 == 11'd2047 && + _theResult___fst_sfd__h792331 == 52'd0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15080 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13514 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14994[2] : - _theResult___fst_exp__h831637 == 11'd2047 && - _theResult___fst_sfd__h831638 == 52'd0 ; + _theResult___fst_exp__h831634 == 11'd2047 && + _theResult___fst_sfd__h831635 == 52'd0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15097 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12799 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14909[1] : - _theResult___fst_exp__h752697 == 11'd0 && - guard__h744707 != 2'b0 ; + _theResult___fst_exp__h752694 == 11'd0 && + guard__h744704 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15109 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14284 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14950[1] : - _theResult___fst_exp__h791550 == 11'd0 && - guard__h783560 != 2'b0 ; + _theResult___fst_exp__h791547 == 11'd0 && + guard__h783557 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15122 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13514 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14994[1] : - _theResult___fst_exp__h830854 == 11'd0 && - guard__h822864 != 2'b0 ; + _theResult___fst_exp__h830851 == 11'd0 && + guard__h822861 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15139 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12799 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14909[0] : - _theResult___fst_exp__h752697 != 11'd2047 && - guard__h744707 != 2'b0 ; + _theResult___fst_exp__h752694 != 11'd2047 && + guard__h744704 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15151 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14284 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14950[0] : - _theResult___fst_exp__h791550 != 11'd2047 && - guard__h783560 != 2'b0 ; + _theResult___fst_exp__h791547 != 11'd2047 && + guard__h783557 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15164 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13514 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14994[0] : - _theResult___fst_exp__h830854 != 11'd2047 && - guard__h822864 != 2'b0 ; + _theResult___fst_exp__h830851 != 11'd2047 && + guard__h822861 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d10392 = ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q84[7:0] == 8'd0) ? @@ -23786,35 +23784,35 @@ module mkCore(CLK, 9'd386 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d10619 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10073 ? - ((_theResult___fst_exp__h648080 == 8'd255) ? + ((_theResult___fst_exp__h648078 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10604) : - ((_theResult___fst_exp__h656765 == 8'd255) ? + ((_theResult___fst_exp__h656763 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10617) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d10656 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10073 ? - ((_theResult___fst_exp__h648080 == 8'd255) ? + ((_theResult___fst_exp__h648078 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10647) : - ((_theResult___fst_exp__h656765 == 8'd255) ? + ((_theResult___fst_exp__h656763 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10654) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d10752 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10073 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d10723[2] : - _theResult___fst_exp__h657313 == 8'd255 && - _theResult___fst_sfd__h657314 == 23'd0 ; + _theResult___fst_exp__h657311 == 8'd255 && + _theResult___fst_sfd__h657312 == 23'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d10765 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10073 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d10723[1] : - _theResult___fst_exp__h656765 == 8'd0 && - guard__h648688 != 2'b0 ; + _theResult___fst_exp__h656763 == 8'd0 && + guard__h648686 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d10778 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10073 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d10723[0] : - _theResult___fst_exp__h656765 != 8'd255 && - guard__h648688 != 2'b0 ; + _theResult___fst_exp__h656763 != 8'd255 && + guard__h648686 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d11789 = ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q119[7:0] == 8'd0) ? @@ -23824,35 +23822,35 @@ module mkCore(CLK, 9'd386 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d12016 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11470 ? - ((_theResult___fst_exp__h693827 == 8'd255) ? + ((_theResult___fst_exp__h693825 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12001) : - ((_theResult___fst_exp__h702512 == 8'd255) ? + ((_theResult___fst_exp__h702510 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12014) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d12053 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11470 ? - ((_theResult___fst_exp__h693827 == 8'd255) ? + ((_theResult___fst_exp__h693825 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12044) : - ((_theResult___fst_exp__h702512 == 8'd255) ? + ((_theResult___fst_exp__h702510 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12051) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d12149 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11470 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d12120[2] : - _theResult___fst_exp__h703060 == 8'd255 && - _theResult___fst_sfd__h703061 == 23'd0 ; + _theResult___fst_exp__h703058 == 8'd255 && + _theResult___fst_sfd__h703059 == 23'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d12162 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11470 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d12120[1] : - _theResult___fst_exp__h702512 == 8'd0 && - guard__h694435 != 2'b0 ; + _theResult___fst_exp__h702510 == 8'd0 && + guard__h694433 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d12175 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11470 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d12120[0] : - _theResult___fst_exp__h702512 != 8'd255 && - guard__h694435 != 2'b0 ; + _theResult___fst_exp__h702510 != 8'd255 && + guard__h694433 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8995 = ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q49[7:0] == 8'd0) ? @@ -23862,41 +23860,41 @@ module mkCore(CLK, 9'd386 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d9222 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8676 ? - ((_theResult___fst_exp__h602331 == 8'd255) ? + ((_theResult___fst_exp__h602329 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9207) : - ((_theResult___fst_exp__h611016 == 8'd255) ? + ((_theResult___fst_exp__h611014 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9220) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d9259 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8676 ? - ((_theResult___fst_exp__h602331 == 8'd255) ? + ((_theResult___fst_exp__h602329 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9250) : - ((_theResult___fst_exp__h611016 == 8'd255) ? + ((_theResult___fst_exp__h611014 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9257) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d9355 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8676 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d9326[2] : - _theResult___fst_exp__h611564 == 8'd255 && - _theResult___fst_sfd__h611565 == 23'd0 ; + _theResult___fst_exp__h611562 == 8'd255 && + _theResult___fst_sfd__h611563 == 23'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d9368 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8676 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d9326[1] : - _theResult___fst_exp__h611016 == 8'd0 && - guard__h602939 != 2'b0 ; + _theResult___fst_exp__h611014 == 8'd0 && + guard__h602937 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d9381 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8676 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d9326[0] : - _theResult___fst_exp__h611016 != 8'd255 && - guard__h602939 != 2'b0 ; + _theResult___fst_exp__h611014 != 8'd255 && + guard__h602937 != 2'b0 ; assign IF_SEXT_coreFix_memExe_regToExeQ_first__645_BI_ETC___d4095 = - offset__h242628[63] ? - x__h242777[13:0] >= toBounds__h242656 && - repBoundBits__h242653 != + offset__h242625[63] ? + x__h242774[13:0] >= toBounds__h242653 && + repBoundBits__h242650 != coreFix_memExe_regToExeQ$first[317:304] : - x__h242777[13:0] < toBoundsM1__h242657 ; + x__h242774[13:0] < toBoundsM1__h242654 ; assign IF_coreFix_aluExe_0_dispToRegQ_RDY_first__8382_ETC___d18414 = (coreFix_aluExe_0_dispToRegQ$RDY_first && coreFix_aluExe_0_bypassWire_0$whas && @@ -23984,24 +23982,24 @@ module mkCore(CLK, IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d18608 ; assign IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d18820 = coreFix_aluExe_0_dispToRegQ$first[137] ? - res_address__h892145 : + res_address__h892144 : ((coreFix_aluExe_0_dispToRegQ$first[85] && coreFix_aluExe_0_dispToRegQ$first[84:78] != 7'd0) ? IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18818 : 66'd0) ; assign IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d18835 = coreFix_aluExe_0_dispToRegQ$first[137] ? - res_addrBits__h892146 : + res_addrBits__h892145 : ((coreFix_aluExe_0_dispToRegQ$first[85] && coreFix_aluExe_0_dispToRegQ$first[84:78] != 7'd0) ? IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18833 : 14'd0) ; assign IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19394 = { coreFix_aluExe_0_dispToRegQ$first[124] ? - thin_reserved__h899113 : + thin_reserved__h899111 : 2'd0, coreFix_aluExe_0_dispToRegQ$first[124] ? - thin_otype__h899114 : + thin_otype__h899112 : 18'd262143, !coreFix_aluExe_0_dispToRegQ$first[124] || IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19382, @@ -24010,7 +24008,7 @@ module mkCore(CLK, 34'h344000000 } ; assign IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19395 = { coreFix_aluExe_0_dispToRegQ$first[124] ? - thin_perms_soft__h899289 : + thin_perms_soft__h899287 : 4'd0, coreFix_aluExe_0_dispToRegQ$first[124] && IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19240, @@ -24041,18 +24039,18 @@ module mkCore(CLK, IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19394 } ; assign IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19396 = { coreFix_aluExe_0_dispToRegQ$first[124] ? - thin_address__h899109 : + thin_address__h899107 : 66'd0, coreFix_aluExe_0_dispToRegQ$first[124] ? - thin_addrBits__h899110 : + thin_addrBits__h899108 : 14'd0, IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19395 } ; assign IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19417 = - thin_bounds_topBits__h900515[13:11] < repBound__h900631 ; + thin_bounds_topBits__h900513[13:11] < repBound__h900629 ; assign IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19419 = - thin_bounds_baseBits__h900516[13:11] < repBound__h900631 ; + thin_bounds_baseBits__h900514[13:11] < repBound__h900629 ; assign IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19422 = - thin_addrBits__h899110[13:11] < repBound__h900631 ; + thin_addrBits__h899108[13:11] < repBound__h900629 ; assign IF_coreFix_aluExe_0_exeToFinQ_first__9946_BIT__ETC___d20092 = { (coreFix_aluExe_0_exeToFinQ$first[282] && !coreFix_aluExe_0_exeToFinQ$first[294]) ? @@ -24299,24 +24297,24 @@ module mkCore(CLK, IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d15845 ; assign IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d16425 = coreFix_aluExe_1_dispToRegQ$first[137] ? - res_address__h848644 : + res_address__h848642 : ((coreFix_aluExe_1_dispToRegQ$first[85] && coreFix_aluExe_1_dispToRegQ$first[84:78] != 7'd0) ? IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16423 : 66'd0) ; assign IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d16440 = coreFix_aluExe_1_dispToRegQ$first[137] ? - res_addrBits__h848645 : + res_addrBits__h848643 : ((coreFix_aluExe_1_dispToRegQ$first[85] && coreFix_aluExe_1_dispToRegQ$first[84:78] != 7'd0) ? IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16438 : 14'd0) ; assign IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d17260 = { coreFix_aluExe_1_dispToRegQ$first[124] ? - thin_reserved__h858477 : + thin_reserved__h858476 : 2'd0, coreFix_aluExe_1_dispToRegQ$first[124] ? - thin_otype__h858478 : + thin_otype__h858477 : 18'd262143, !coreFix_aluExe_1_dispToRegQ$first[124] || IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d17235, @@ -24325,7 +24323,7 @@ module mkCore(CLK, 34'h344000000 } ; assign IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d17261 = { coreFix_aluExe_1_dispToRegQ$first[124] ? - thin_perms_soft__h858713 : + thin_perms_soft__h858712 : 4'd0, coreFix_aluExe_1_dispToRegQ$first[124] && IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d16898, @@ -24356,18 +24354,18 @@ module mkCore(CLK, IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d17260 } ; assign IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d17262 = { coreFix_aluExe_1_dispToRegQ$first[124] ? - thin_address__h858473 : + thin_address__h858472 : 66'd0, coreFix_aluExe_1_dispToRegQ$first[124] ? - thin_addrBits__h858474 : + thin_addrBits__h858473 : 14'd0, IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d17261 } ; assign IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d17301 = - thin_bounds_topBits__h860421[13:11] < repBound__h860557 ; + thin_bounds_topBits__h860420[13:11] < repBound__h860556 ; assign IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d17303 = - thin_bounds_baseBits__h860422[13:11] < repBound__h860557 ; + thin_bounds_baseBits__h860421[13:11] < repBound__h860556 ; assign IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d17306 = - thin_addrBits__h858474[13:11] < repBound__h860557 ; + thin_addrBits__h858473[13:11] < repBound__h860556 ; assign IF_coreFix_aluExe_1_exeToFinQ_first__7830_BIT__ETC___d17977 = { (coreFix_aluExe_1_exeToFinQ$first[282] && !coreFix_aluExe_1_exeToFinQ$first[294]) ? @@ -25151,8 +25149,8 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107] ; assign IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d20197 = coreFix_globalSpecUpdate_correctSpecTag_1$whas ? - result__h915810 : - w__h915805 ; + result__h915808 : + w__h915803 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5011 = (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == 3'd3 && @@ -25364,12 +25362,12 @@ module mkCore(CLK, 64'd0 : 64'd1 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d7203 = - !MUX_flush_reservation$write_1__SEL_1 && + !MUX_flush_reservation$write_1__SEL_2 && (coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget[58] : coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58]) ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d7211 = - MUX_flush_reservation$write_1__SEL_1 ? + MUX_flush_reservation$write_1__SEL_2 ? 58'h2AAAAAAAAAAAAAA : (coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget[57:0] : @@ -25626,15 +25624,15 @@ module mkCore(CLK, NOT_coreFix_memExe_dispToRegQ_first__686_BIT_1_ETC___d3634 } ; assign IF_coreFix_memExe_dispToRegQ_first__686_BIT_12_ETC___d3070 = coreFix_memExe_dispToRegQ$first[12] ? - res_addrBits__h235324 : + res_addrBits__h235321 : ((coreFix_memExe_dispToRegQ$first[110] && coreFix_memExe_dispToRegQ$first[109:103] != 7'd0) ? IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3068 : 14'd0) ; assign IF_coreFix_memExe_dispToRegQ_first__686_BIT_12_ETC___d3315 = { coreFix_memExe_dispToRegQ$first[12] ? - res_address__h235323 : - x__h235746, + res_address__h235320 : + x__h235743, IF_coreFix_memExe_dispToRegQ_first__686_BIT_12_ETC___d3070, coreFix_memExe_dispToRegQ$first[12] ? 4'd0 : @@ -25773,15 +25771,15 @@ module mkCore(CLK, IF_coreFix_memExe_lsq_firstLd__498_BIT_113_513_ETC___d2078 ; assign IF_coreFix_memExe_lsq_getOrigBE_coreFix_memExe_ETC___d4249 = { coreFix_memExe_lsq$getOrigBE[15] ? - pointer__h242638[3:0] != 4'd0 : + pointer__h242635[3:0] != 4'd0 : (coreFix_memExe_lsq$getOrigBE[7] ? - pointer__h242638[2:0] != 3'd0 : + pointer__h242635[2:0] != 3'd0 : (coreFix_memExe_lsq$getOrigBE[3] ? - pointer__h242638[1:0] != 2'd0 : + pointer__h242635[1:0] != 2'd0 : coreFix_memExe_lsq$getOrigBE[1] && - pointer__h242638[0])), + pointer__h242635[0])), capChecks___d4160[11:5], - CASE_capChecks_160_BITS_4_TO_0_0_capChecks_160_ETC__q292, + CASE_capChecks_160_BITS_4_TO_0_0_capChecks_160_ETC__q294, prepareBoundsCheck___d4244 } ; assign IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d7782 = WILL_FIRE_RL_coreFix_memExe_doRespLdMem || @@ -25811,10 +25809,10 @@ module mkCore(CLK, csrf_mepcc_reg_data_rl[13:0] ; assign IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16239 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16236[13:11] < - repBound__h855390 ; + repBound__h855389 ; assign IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16241 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16232[13:11] < - repBound__h855390 ; + repBound__h855389 ; assign IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16252 = MUX_csrf_ie_vec_3$write_1__SEL_3 ? MUX_csrf_rg_dpc$write_1__VAL_3[33:28] : @@ -25903,86 +25901,86 @@ module mkCore(CLK, MUX_csrf_ie_vec_3$write_1__SEL_3 ? MUX_csrf_rg_dpc$write_1__VAL_3[27:14] : csrf_mepcc_reg_data_rl[27:14] ; - assign IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d23335 = + assign IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d23337 = MUX_csrf_ie_vec_3$write_1__SEL_3 ? MUX_csrf_rg_dpc$write_1__VAL_3[71:0] : csrf_mepcc_reg_data_rl[71:0] ; - assign IF_csrf_mepcc_reg_read_wget__3540_BIT_34_3552__ETC___d23562 = + assign IF_csrf_mepcc_reg_read_wget__3542_BIT_34_3554__ETC___d23564 = csrf_mepcc_reg_data_rl[34] ? { csrf_mepcc_reg_data_rl[25:17], csrf_mepcc_reg_data_rl[33:31], csrf_mepcc_reg_data_rl[13:3], csrf_mepcc_reg_data_rl[30:28] } : csrf_mepcc_reg_data_rl[25:0] ; - assign IF_csrf_mtcc_reg_read__6198_BITS_149_TO_86_281_ETC___d22840 = - ((newAddrDiff__h1000158 == 64'd0) ? + assign IF_csrf_mtcc_reg_read__6198_BITS_149_TO_86_281_ETC___d22842 = + ((newAddrDiff__h1000193 == 64'd0) ? 2'd0 : - (csrf_mtcc_reg_read__6198_BITS_149_TO_86_2811_A_ETC___d22821 ? + (csrf_mtcc_reg_read__6198_BITS_149_TO_86_2813_A_ETC___d22823 ? 2'd3 : 2'd1)) == ((csrf_mtcc_reg_read__6198_BITS_85_TO_83_6204_UL_ETC___d16205 && - _0_CONCAT_csrf_mtcc_reg_read__6198_BITS_149_TO__ETC___d22832) ? + _0_CONCAT_csrf_mtcc_reg_read__6198_BITS_149_TO__ETC___d22834) ? 2'd0 : ((csrf_mtcc_reg_read__6198_BITS_85_TO_83_6204_UL_ETC___d16205 && - !_0_CONCAT_csrf_mtcc_reg_read__6198_BITS_149_TO__ETC___d22832) ? + !_0_CONCAT_csrf_mtcc_reg_read__6198_BITS_149_TO__ETC___d22834) ? 2'd1 : ((!csrf_mtcc_reg_read__6198_BITS_85_TO_83_6204_UL_ETC___d16205 && - _0_CONCAT_csrf_mtcc_reg_read__6198_BITS_149_TO__ETC___d22832) ? + _0_CONCAT_csrf_mtcc_reg_read__6198_BITS_149_TO__ETC___d22834) ? 2'd3 : 2'd0))) ; - assign IF_csrf_mtcc_reg_read__6198_BITS_149_TO_86_281_ETC___d22843 = - IF_csrf_mtcc_reg_read__6198_BITS_149_TO_86_281_ETC___d22840 && - (newAddrDiff__h1000158 == 64'd0 || - csrf_mtcc_reg_read__6198_BITS_149_TO_86_2811_A_ETC___d22821 || - newAddrDiff__h1000158 == - _18446744073709551615_SL_csrf_mtcc_reg_read__61_ETC___d22824) ; - assign IF_csrf_mtcc_reg_read__6198_BITS_149_TO_86_281_ETC___d22865 = - ((newAddrDiff__h1000502 == 64'd0) ? + assign IF_csrf_mtcc_reg_read__6198_BITS_149_TO_86_281_ETC___d22845 = + IF_csrf_mtcc_reg_read__6198_BITS_149_TO_86_281_ETC___d22842 && + (newAddrDiff__h1000193 == 64'd0 || + csrf_mtcc_reg_read__6198_BITS_149_TO_86_2813_A_ETC___d22823 || + newAddrDiff__h1000193 == + _18446744073709551615_SL_csrf_mtcc_reg_read__61_ETC___d22826) ; + assign IF_csrf_mtcc_reg_read__6198_BITS_149_TO_86_281_ETC___d22867 = + ((newAddrDiff__h1000537 == 64'd0) ? 2'd0 : - (csrf_mtcc_reg_read__6198_BITS_149_TO_86_2811_A_ETC___d22849 ? + (csrf_mtcc_reg_read__6198_BITS_149_TO_86_2813_A_ETC___d22851 ? 2'd3 : 2'd1)) == ((csrf_mtcc_reg_read__6198_BITS_85_TO_83_6204_UL_ETC___d16205 && - _0_CONCAT_csrf_mtcc_reg_read__6198_BITS_149_TO__ETC___d22857) ? + _0_CONCAT_csrf_mtcc_reg_read__6198_BITS_149_TO__ETC___d22859) ? 2'd0 : ((csrf_mtcc_reg_read__6198_BITS_85_TO_83_6204_UL_ETC___d16205 && - !_0_CONCAT_csrf_mtcc_reg_read__6198_BITS_149_TO__ETC___d22857) ? + !_0_CONCAT_csrf_mtcc_reg_read__6198_BITS_149_TO__ETC___d22859) ? 2'd1 : ((!csrf_mtcc_reg_read__6198_BITS_85_TO_83_6204_UL_ETC___d16205 && - _0_CONCAT_csrf_mtcc_reg_read__6198_BITS_149_TO__ETC___d22857) ? + _0_CONCAT_csrf_mtcc_reg_read__6198_BITS_149_TO__ETC___d22859) ? 2'd3 : 2'd0))) ; - assign IF_csrf_mtcc_reg_read__6198_BITS_149_TO_86_281_ETC___d22868 = - IF_csrf_mtcc_reg_read__6198_BITS_149_TO_86_281_ETC___d22865 && - (newAddrDiff__h1000502 == 64'd0 || - csrf_mtcc_reg_read__6198_BITS_149_TO_86_2811_A_ETC___d22849 || - newAddrDiff__h1000502 == - _18446744073709551615_SL_csrf_mtcc_reg_read__61_ETC___d22824) ; - assign IF_csrf_mtcc_reg_read__6198_BIT_86_2807_AND_NO_ETC___d22871 = - (csrf_mtcc_reg[86] && cause_interrupt__h995318) ? - (NOT_csrf_mtcc_reg_read__6198_BITS_33_TO_28_621_ETC___d22810 || - IF_csrf_mtcc_reg_read__6198_BITS_149_TO_86_281_ETC___d22843) && + assign IF_csrf_mtcc_reg_read__6198_BITS_149_TO_86_281_ETC___d22870 = + IF_csrf_mtcc_reg_read__6198_BITS_149_TO_86_281_ETC___d22867 && + (newAddrDiff__h1000537 == 64'd0 || + csrf_mtcc_reg_read__6198_BITS_149_TO_86_2813_A_ETC___d22851 || + newAddrDiff__h1000537 == + _18446744073709551615_SL_csrf_mtcc_reg_read__61_ETC___d22826) ; + assign IF_csrf_mtcc_reg_read__6198_BIT_86_2809_AND_NO_ETC___d22873 = + (csrf_mtcc_reg[86] && cause_interrupt__h995316) ? + (NOT_csrf_mtcc_reg_read__6198_BITS_33_TO_28_621_ETC___d22812 || + IF_csrf_mtcc_reg_read__6198_BITS_149_TO_86_281_ETC___d22845) && csrf_mtcc_reg[152] : - (NOT_csrf_mtcc_reg_read__6198_BITS_33_TO_28_621_ETC___d22810 || - IF_csrf_mtcc_reg_read__6198_BITS_149_TO_86_281_ETC___d22868) && + (NOT_csrf_mtcc_reg_read__6198_BITS_33_TO_28_621_ETC___d22812 || + IF_csrf_mtcc_reg_read__6198_BITS_149_TO_86_281_ETC___d22870) && csrf_mtcc_reg[152] ; - assign IF_csrf_mtcc_reg_read__6198_BIT_86_2807_AND_NO_ETC___d22905 = - (csrf_mtcc_reg[86] && cause_interrupt__h995318) ? - address__h999478 : - base__h999443 ; - assign IF_csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_c_ETC___d22876 = - csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22647 ? - { IF_csrf_stcc_reg_read__6046_BIT_86_2736_AND_NO_ETC___d22802, + assign IF_csrf_mtcc_reg_read__6198_BIT_86_2809_AND_NO_ETC___d22907 = + (csrf_mtcc_reg[86] && cause_interrupt__h995316) ? + address__h999513 : + base__h999478 ; + assign IF_csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_c_ETC___d22878 = + csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22648 ? + { IF_csrf_stcc_reg_read__6046_BIT_86_2738_AND_NO_ETC___d22804, csrf_stcc_reg[71:56], csrf_stcc_reg[54:53], csrf_stcc_reg[55], csrf_stcc_reg[52:34] } : - { IF_csrf_mtcc_reg_read__6198_BIT_86_2807_AND_NO_ETC___d22871, + { IF_csrf_mtcc_reg_read__6198_BIT_86_2809_AND_NO_ETC___d22873, csrf_mtcc_reg[71:56], csrf_mtcc_reg[54:53], csrf_mtcc_reg[55], csrf_mtcc_reg[52:34] } ; - assign IF_csrf_rg_dpc_read__6343_BIT_34_4349_THEN_csr_ETC___d24357 = + assign IF_csrf_rg_dpc_read__6343_BIT_34_4351_THEN_csr_ETC___d24359 = csrf_rg_dpc[34] ? { csrf_rg_dpc[25:17], csrf_rg_dpc[33:31], @@ -25999,10 +25997,10 @@ module mkCore(CLK, csrf_sepcc_reg_data_rl[13:0] ; assign IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16087 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16084[13:11] < - repBound__h854398 ; + repBound__h854397 ; assign IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16089 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16080[13:11] < - repBound__h854398 ; + repBound__h854397 ; assign IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16100 = MUX_csrf_ie_vec_1$write_1__SEL_3 ? MUX_csrf_rg_dpc$write_1__VAL_3[33:28] : @@ -26091,93 +26089,93 @@ module mkCore(CLK, MUX_csrf_ie_vec_1$write_1__SEL_3 ? MUX_csrf_rg_dpc$write_1__VAL_3[27:14] : csrf_sepcc_reg_data_rl[27:14] ; - assign IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d23198 = + assign IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d23200 = MUX_csrf_ie_vec_1$write_1__SEL_3 ? MUX_csrf_rg_dpc$write_1__VAL_3[71:0] : csrf_sepcc_reg_data_rl[71:0] ; - assign IF_csrf_sepcc_reg_read_wget__3506_BIT_34_3518__ETC___d23528 = + assign IF_csrf_sepcc_reg_read_wget__3508_BIT_34_3520__ETC___d23530 = csrf_sepcc_reg_data_rl[34] ? { csrf_sepcc_reg_data_rl[25:17], csrf_sepcc_reg_data_rl[33:31], csrf_sepcc_reg_data_rl[13:3], csrf_sepcc_reg_data_rl[30:28] } : csrf_sepcc_reg_data_rl[25:0] ; - assign IF_csrf_stcc_reg_read__6046_BITS_149_TO_86_274_ETC___d22771 = - ((newAddrDiff__h999501 == 64'd0) ? + assign IF_csrf_stcc_reg_read__6046_BITS_149_TO_86_274_ETC___d22773 = + ((newAddrDiff__h999536 == 64'd0) ? 2'd0 : - (csrf_stcc_reg_read__6046_BITS_149_TO_86_2740_A_ETC___d22752 ? + (csrf_stcc_reg_read__6046_BITS_149_TO_86_2742_A_ETC___d22754 ? 2'd3 : 2'd1)) == ((csrf_stcc_reg_read__6046_BITS_85_TO_83_6052_UL_ETC___d16053 && - _0_CONCAT_csrf_stcc_reg_read__6046_BITS_149_TO__ETC___d22763) ? + _0_CONCAT_csrf_stcc_reg_read__6046_BITS_149_TO__ETC___d22765) ? 2'd0 : ((csrf_stcc_reg_read__6046_BITS_85_TO_83_6052_UL_ETC___d16053 && - !_0_CONCAT_csrf_stcc_reg_read__6046_BITS_149_TO__ETC___d22763) ? + !_0_CONCAT_csrf_stcc_reg_read__6046_BITS_149_TO__ETC___d22765) ? 2'd1 : ((!csrf_stcc_reg_read__6046_BITS_85_TO_83_6052_UL_ETC___d16053 && - _0_CONCAT_csrf_stcc_reg_read__6046_BITS_149_TO__ETC___d22763) ? + _0_CONCAT_csrf_stcc_reg_read__6046_BITS_149_TO__ETC___d22765) ? 2'd3 : 2'd0))) ; - assign IF_csrf_stcc_reg_read__6046_BITS_149_TO_86_274_ETC___d22774 = - IF_csrf_stcc_reg_read__6046_BITS_149_TO_86_274_ETC___d22771 && - (newAddrDiff__h999501 == 64'd0 || - csrf_stcc_reg_read__6046_BITS_149_TO_86_2740_A_ETC___d22752 || - newAddrDiff__h999501 == - _18446744073709551615_SL_csrf_stcc_reg_read__60_ETC___d22755) ; - assign IF_csrf_stcc_reg_read__6046_BITS_149_TO_86_274_ETC___d22796 = - ((newAddrDiff__h999845 == 64'd0) ? + assign IF_csrf_stcc_reg_read__6046_BITS_149_TO_86_274_ETC___d22776 = + IF_csrf_stcc_reg_read__6046_BITS_149_TO_86_274_ETC___d22773 && + (newAddrDiff__h999536 == 64'd0 || + csrf_stcc_reg_read__6046_BITS_149_TO_86_2742_A_ETC___d22754 || + newAddrDiff__h999536 == + _18446744073709551615_SL_csrf_stcc_reg_read__60_ETC___d22757) ; + assign IF_csrf_stcc_reg_read__6046_BITS_149_TO_86_274_ETC___d22798 = + ((newAddrDiff__h999880 == 64'd0) ? 2'd0 : - (csrf_stcc_reg_read__6046_BITS_149_TO_86_2740_A_ETC___d22780 ? + (csrf_stcc_reg_read__6046_BITS_149_TO_86_2742_A_ETC___d22782 ? 2'd3 : 2'd1)) == ((csrf_stcc_reg_read__6046_BITS_85_TO_83_6052_UL_ETC___d16053 && - _0_CONCAT_csrf_stcc_reg_read__6046_BITS_149_TO__ETC___d22788) ? + _0_CONCAT_csrf_stcc_reg_read__6046_BITS_149_TO__ETC___d22790) ? 2'd0 : ((csrf_stcc_reg_read__6046_BITS_85_TO_83_6052_UL_ETC___d16053 && - !_0_CONCAT_csrf_stcc_reg_read__6046_BITS_149_TO__ETC___d22788) ? + !_0_CONCAT_csrf_stcc_reg_read__6046_BITS_149_TO__ETC___d22790) ? 2'd1 : ((!csrf_stcc_reg_read__6046_BITS_85_TO_83_6052_UL_ETC___d16053 && - _0_CONCAT_csrf_stcc_reg_read__6046_BITS_149_TO__ETC___d22788) ? + _0_CONCAT_csrf_stcc_reg_read__6046_BITS_149_TO__ETC___d22790) ? 2'd3 : 2'd0))) ; - assign IF_csrf_stcc_reg_read__6046_BITS_149_TO_86_274_ETC___d22799 = - IF_csrf_stcc_reg_read__6046_BITS_149_TO_86_274_ETC___d22796 && - (newAddrDiff__h999845 == 64'd0 || - csrf_stcc_reg_read__6046_BITS_149_TO_86_2740_A_ETC___d22780 || - newAddrDiff__h999845 == - _18446744073709551615_SL_csrf_stcc_reg_read__60_ETC___d22755) ; - assign IF_csrf_stcc_reg_read__6046_BIT_86_2736_AND_NO_ETC___d22802 = - (csrf_stcc_reg[86] && cause_interrupt__h995318) ? - (NOT_csrf_stcc_reg_read__6046_BITS_33_TO_28_606_ETC___d22739 || - IF_csrf_stcc_reg_read__6046_BITS_149_TO_86_274_ETC___d22774) && + assign IF_csrf_stcc_reg_read__6046_BITS_149_TO_86_274_ETC___d22801 = + IF_csrf_stcc_reg_read__6046_BITS_149_TO_86_274_ETC___d22798 && + (newAddrDiff__h999880 == 64'd0 || + csrf_stcc_reg_read__6046_BITS_149_TO_86_2742_A_ETC___d22782 || + newAddrDiff__h999880 == + _18446744073709551615_SL_csrf_stcc_reg_read__60_ETC___d22757) ; + assign IF_csrf_stcc_reg_read__6046_BIT_86_2738_AND_NO_ETC___d22804 = + (csrf_stcc_reg[86] && cause_interrupt__h995316) ? + (NOT_csrf_stcc_reg_read__6046_BITS_33_TO_28_606_ETC___d22741 || + IF_csrf_stcc_reg_read__6046_BITS_149_TO_86_274_ETC___d22776) && csrf_stcc_reg[152] : - (NOT_csrf_stcc_reg_read__6046_BITS_33_TO_28_606_ETC___d22739 || - IF_csrf_stcc_reg_read__6046_BITS_149_TO_86_274_ETC___d22799) && + (NOT_csrf_stcc_reg_read__6046_BITS_33_TO_28_606_ETC___d22741 || + IF_csrf_stcc_reg_read__6046_BITS_149_TO_86_274_ETC___d22801) && csrf_stcc_reg[152] ; - assign IF_csrf_stcc_reg_read__6046_BIT_86_2736_AND_NO_ETC___d22904 = - (csrf_stcc_reg[86] && cause_interrupt__h995318) ? - address__h999428 : - base__h999389 ; - assign IF_f_csr_reqs_first__3969_BIT_63_4123_THEN_NOT_ETC___d24133 = + assign IF_csrf_stcc_reg_read__6046_BIT_86_2738_AND_NO_ETC___d22906 = + (csrf_stcc_reg[86] && cause_interrupt__h995316) ? + address__h999463 : + base__h999424 ; + assign IF_f_csr_reqs_first__3971_BIT_63_4125_THEN_NOT_ETC___d24135 = f_csr_reqs$D_OUT[63] ? - x__h1031547[13:0] >= toBounds__h1008382 : - x__h1031547[13:0] <= toBoundsM1__h1008383 ; - assign IF_f_csr_reqs_first__3969_BIT_63_4123_THEN_NOT_ETC___d24155 = + x__h1031581[13:0] >= toBounds__h1008417 : + x__h1031581[13:0] <= toBoundsM1__h1008418 ; + assign IF_f_csr_reqs_first__3971_BIT_63_4125_THEN_NOT_ETC___d24157 = f_csr_reqs$D_OUT[63] ? - x__h1031950[13:0] >= toBounds__h1008785 : - x__h1031950[13:0] <= toBoundsM1__h1008786 ; - assign IF_f_csr_reqs_first__3969_BIT_63_4123_THEN_NOT_ETC___d24213 = + x__h1031984[13:0] >= toBounds__h1008820 : + x__h1031984[13:0] <= toBoundsM1__h1008821 ; + assign IF_f_csr_reqs_first__3971_BIT_63_4125_THEN_NOT_ETC___d24215 = f_csr_reqs$D_OUT[63] ? - x__h1032367[13:0] >= toBounds__h1009202 : - x__h1032367[13:0] <= toBoundsM1__h1009203 ; - assign IF_f_csr_reqs_first__3969_BIT_63_4123_THEN_NOT_ETC___d24233 = + x__h1032401[13:0] >= toBounds__h1009237 : + x__h1032401[13:0] <= toBoundsM1__h1009238 ; + assign IF_f_csr_reqs_first__3971_BIT_63_4125_THEN_NOT_ETC___d24235 = f_csr_reqs$D_OUT[63] ? - x__h1032770[13:0] >= toBounds__h1009605 : - x__h1032770[13:0] <= toBoundsM1__h1009606 ; - assign IF_f_csr_reqs_first__3969_BIT_63_4123_THEN_NOT_ETC___d24304 = + x__h1032804[13:0] >= toBounds__h1009640 : + x__h1032804[13:0] <= toBoundsM1__h1009641 ; + assign IF_f_csr_reqs_first__3971_BIT_63_4125_THEN_NOT_ETC___d24306 = f_csr_reqs$D_OUT[63] ? - x__h1033437[13:0] >= toBounds__h1010274 : - x__h1033437[13:0] <= toBoundsM1__h1010275 ; + x__h1033471[13:0] >= toBounds__h1010309 : + x__h1033471[13:0] <= toBoundsM1__h1010310 ; assign IF_fetchStage_RDY_pipelines_0_first__0253_AND__ETC___d21186 = (fetchStage$RDY_pipelines_0_first && (fetchStage$pipelines_0_first[268:266] != 3'd1 || @@ -26360,9 +26358,9 @@ module mkCore(CLK, IF_fetchStage_pipelines_0_first__0256_BITS_268_ETC___d21279 ; assign IF_fetchStage_pipelines_0_first__0256_BITS_268_ETC___d21867 = IF_fetchStage_pipelines_0_first__0256_BITS_268_ETC___d21860 || - rob$RDY_enqPort_0_enq && - regRenamingTable$RDY_rename_0_getRename && regRenamingTable$RDY_rename_0_claimRename && + regRenamingTable$RDY_rename_0_getRename && + rob$RDY_enqPort_0_enq && fetchStage$RDY_pipelines_0_deq && (fetchStage$pipelines_0_first[268:266] != 3'd1 || specTagManager$RDY_claimSpecTag) ; @@ -26513,9 +26511,9 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__0265_BITS_268_ETC___d21955 && IF_fetchStage_RDY_pipelines_1_first__0264_AND__ETC___d21743 && (IF_fetchStage_pipelines_1_first__0265_BITS_268_ETC___d21984 || - rob$RDY_enqPort_1_enq && - regRenamingTable$RDY_rename_1_getRename && regRenamingTable$RDY_rename_1_claimRename && + regRenamingTable$RDY_rename_1_getRename && + rob$RDY_enqPort_1_enq && fetchStage_RDY_pipelines_1_deq__0268_AND_NOT_f_ETC___d21994) ; assign IF_mmio_cRqQ_enqReq_lat_1_whas__87_THEN_mmio_c_ETC___d296 = mmio_cRqQ_enqReq_lat_0$whas ? @@ -26601,44 +26599,44 @@ module mkCore(CLK, !rf_read_3_rd2_coreFix_memExe_dispToRegQ_first__ETC___d3609) ? 2'd1 : 2'd3) } ; - assign IF_rob_deqPort_0_canDeq__3598_THEN_IF_NOT_rob__ETC___d23719 = + assign IF_rob_deqPort_0_canDeq__3600_THEN_IF_NOT_rob__ETC___d23721 = rob$deqPort_0_canDeq ? - y_avValue_snd_snd_snd_snd_snd__h1015810 : + y_avValue_snd_snd_snd_snd_snd__h1015845 : 64'd0 ; - assign IF_rob_deqPort_0_canDeq__3598_THEN_IF_NOT_rob__ETC___d23825 = - rob$deqPort_0_canDeq ? y_avValue_snd_fst__h1015794 : 5'd0 ; - assign IF_rob_deqPort_0_canDeq__3598_THEN_IF_NOT_rob__ETC___d23847 = + assign IF_rob_deqPort_0_canDeq__3600_THEN_IF_NOT_rob__ETC___d23827 = + rob$deqPort_0_canDeq ? y_avValue_snd_fst__h1015829 : 5'd0 ; + assign IF_rob_deqPort_0_canDeq__3600_THEN_IF_NOT_rob__ETC___d23849 = rob$deqPort_0_canDeq ? - y_avValue_snd_snd_snd_fst__h1015804 : + y_avValue_snd_snd_snd_fst__h1015839 : 2'd0 ; - assign IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23133 = - (highOffsetBits__h1008373 == 50'd0 && - IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23130 || - NOT_csrf_stcc_reg_read__6046_BITS_33_TO_28_606_ETC___d22739) && + assign IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23135 = + (highOffsetBits__h1008408 == 50'd0 && + IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23132 || + NOT_csrf_stcc_reg_read__6046_BITS_33_TO_28_606_ETC___d22741) && csrf_stcc_reg[152] ; - assign IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23179 = - (highOffsetBits__h1008776 == 50'd0 && - IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23174 || - NOT_IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN__ETC___d23177) && + assign IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23181 = + (highOffsetBits__h1008811 == 50'd0 && + IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23176 || + NOT_IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN__ETC___d23179) && IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16810 ; - assign IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23272 = - (highOffsetBits__h1009193 == 50'd0 && - IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23269 || - NOT_csrf_mtcc_reg_read__6198_BITS_33_TO_28_621_ETC___d22810) && + assign IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23274 = + (highOffsetBits__h1009228 == 50'd0 && + IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23271 || + NOT_csrf_mtcc_reg_read__6198_BITS_33_TO_28_621_ETC___d22812) && csrf_mtcc_reg[152] ; - assign IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23316 = - (highOffsetBits__h1009596 == 50'd0 && - IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23311 || - NOT_IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN__ETC___d23314) && + assign IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23318 = + (highOffsetBits__h1009631 == 50'd0 && + IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23313 || + NOT_IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN__ETC___d23316) && IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16818 ; - assign IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23430 = - (highOffsetBits__h1010265 == 50'd0 && - IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23424 || - NOT_csrf_rg_dpc_read__6343_BITS_33_TO_28_6360__ETC___d23427) && + assign IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23432 = + (highOffsetBits__h1010300 == 50'd0 && + IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23426 || + NOT_csrf_rg_dpc_read__6343_BITS_33_TO_28_6360__ETC___d23429) && csrf_rg_dpc[152] ; - assign IF_rob_deqPort_1_canDeq__3602_THEN_IF_NOT_rob__ETC___d23839 = + assign IF_rob_deqPort_1_canDeq__3604_THEN_IF_NOT_rob__ETC___d23841 = rob$deqPort_1_canDeq ? - IF_NOT_rob_deqPort_1_deq_data__3605_BIT_25_360_ETC___d23838 : + IF_NOT_rob_deqPort_1_deq_data__3607_BIT_25_360_ETC___d23840 : rob$deqPort_0_canDeq && rob$deqPort_0_deq_data[26] ; assign IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18759 = sbCons$lazyLookup_0_get[3] ? @@ -26768,7 +26766,7 @@ module mkCore(CLK, IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__840_ETC___d19071) ; assign IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d19093 = sbCons$lazyLookup_0_get[3] ? - repBound__h898286 : + repBound__h898284 : (NOT_coreFix_aluExe_0_bypassWire_0_whas__8403_8_ETC___d18430 ? coreFix_aluExe_0_bypassWire_3$wget[9:7] : IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__840_ETC___d19089) ; @@ -26799,7 +26797,7 @@ module mkCore(CLK, assign IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d19196 = sbCons$lazyLookup_0_get[2] ? { rf$read_0_rd2, - repBound__h900613, + repBound__h900611, rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19168, rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19169, rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19181 } : @@ -26934,7 +26932,7 @@ module mkCore(CLK, IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__564_ETC___d16676) ; assign IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16698 = sbCons$lazyLookup_1_get[3] ? - repBound__h857577 : + repBound__h857576 : (NOT_coreFix_aluExe_1_bypassWire_0_whas__5640_5_ETC___d15667 ? coreFix_aluExe_0_bypassWire_3$wget[9:7] : IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__564_ETC___d16694) ; @@ -26965,7 +26963,7 @@ module mkCore(CLK, assign IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16801 = sbCons$lazyLookup_1_get[2] ? { rf$read_1_rd2, - repBound__h860539, + repBound__h860538, rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16773, rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16774, rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16786 } : @@ -27100,7 +27098,7 @@ module mkCore(CLK, IF_NOT_coreFix_memExe_bypassWire_0_whas__704_7_ETC___d3305) ; assign IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3327 = sbCons$lazyLookup_3_get[3] ? - repBound__h237318 : + repBound__h237315 : (NOT_coreFix_memExe_bypassWire_0_whas__704_710__ETC___d2731 ? coreFix_aluExe_0_bypassWire_3$wget[9:7] : IF_NOT_coreFix_memExe_bypassWire_0_whas__704_7_ETC___d3323) ; @@ -27256,7 +27254,7 @@ module mkCore(CLK, IF_NOT_coreFix_memExe_bypassWire_0_whas__704_7_ETC___d3572) ; assign IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3589 = sbCons$lazyLookup_3_get[2] ? - repBound__h239003 : + repBound__h239000 : (NOT_coreFix_memExe_bypassWire_0_whas__704_710__ETC___d2758 ? coreFix_aluExe_0_bypassWire_3$wget[9:7] : IF_NOT_coreFix_memExe_bypassWire_0_whas__704_7_ETC___d3585) ; @@ -27284,64 +27282,64 @@ module mkCore(CLK, (NOT_coreFix_memExe_bypassWire_0_whas__704_710__ETC___d2758 ? coreFix_aluExe_0_bypassWire_3$wget[3:0] : IF_NOT_coreFix_memExe_bypassWire_0_whas__704_7_ETC___d3628) ; - assign IF_sfdin02325_BIT_33_THEN_2_ELSE_0__q51 = - sfdin__h602325[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin22015_BIT_4_THEN_2_ELSE_0__q168 = - sfdin__h822015[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin30308_BIT_33_THEN_2_ELSE_0__q76 = - sfdin__h630308[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin43858_BIT_4_THEN_2_ELSE_0__q151 = - sfdin__h743858[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin48074_BIT_33_THEN_2_ELSE_0__q86 = - sfdin__h648074[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin76055_BIT_33_THEN_2_ELSE_0__q111 = - sfdin__h676055[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin82711_BIT_4_THEN_2_ELSE_0__q191 = - sfdin__h782711[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin84559_BIT_33_THEN_2_ELSE_0__q41 = - sfdin__h584559[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin93821_BIT_33_THEN_2_ELSE_0__q121 = - sfdin__h693821[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd02458_BIT_33_THEN_2_ELSE_0__q126 = - _theResult___snd__h702458[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd10962_BIT_33_THEN_2_ELSE_0__q56 = - _theResult___snd__h610962[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd12395_BIT_4_THEN_2_ELSE_0__q164 = - _theResult___snd__h812395[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd30800_BIT_4_THEN_2_ELSE_0__q171 = - _theResult___snd__h830800[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd34238_BIT_4_THEN_2_ELSE_0__q147 = - _theResult___snd__h734238[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd38921_BIT_33_THEN_2_ELSE_0__q78 = - _theResult___snd__h638921[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd52643_BIT_4_THEN_2_ELSE_0__q154 = - _theResult___snd__h752643[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd56711_BIT_33_THEN_2_ELSE_0__q91 = - _theResult___snd__h656711[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd73091_BIT_4_THEN_2_ELSE_0__q187 = - _theResult___snd__h773091[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd84668_BIT_33_THEN_2_ELSE_0__q113 = - _theResult___snd__h684668[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd91496_BIT_4_THEN_2_ELSE_0__q194 = - _theResult___snd__h791496[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd93172_BIT_33_THEN_2_ELSE_0__q43 = - _theResult___snd__h593172[33] ? 2'd2 : 2'd0 ; - assign INV_commitStage_commitTrap_BITS_217_TO_199__q15 = + assign IF_sfdin02323_BIT_33_THEN_2_ELSE_0__q51 = + sfdin__h602323[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin22012_BIT_4_THEN_2_ELSE_0__q168 = + sfdin__h822012[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin30306_BIT_33_THEN_2_ELSE_0__q76 = + sfdin__h630306[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin43855_BIT_4_THEN_2_ELSE_0__q151 = + sfdin__h743855[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin48072_BIT_33_THEN_2_ELSE_0__q86 = + sfdin__h648072[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin76053_BIT_33_THEN_2_ELSE_0__q111 = + sfdin__h676053[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin82708_BIT_4_THEN_2_ELSE_0__q191 = + sfdin__h782708[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin84557_BIT_33_THEN_2_ELSE_0__q41 = + sfdin__h584557[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin93819_BIT_33_THEN_2_ELSE_0__q121 = + sfdin__h693819[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd02456_BIT_33_THEN_2_ELSE_0__q126 = + _theResult___snd__h702456[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd10960_BIT_33_THEN_2_ELSE_0__q56 = + _theResult___snd__h610960[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd12392_BIT_4_THEN_2_ELSE_0__q164 = + _theResult___snd__h812392[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd30797_BIT_4_THEN_2_ELSE_0__q171 = + _theResult___snd__h830797[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd34235_BIT_4_THEN_2_ELSE_0__q147 = + _theResult___snd__h734235[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd38919_BIT_33_THEN_2_ELSE_0__q78 = + _theResult___snd__h638919[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd52640_BIT_4_THEN_2_ELSE_0__q154 = + _theResult___snd__h752640[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd56709_BIT_33_THEN_2_ELSE_0__q91 = + _theResult___snd__h656709[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd73088_BIT_4_THEN_2_ELSE_0__q187 = + _theResult___snd__h773088[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd84666_BIT_33_THEN_2_ELSE_0__q113 = + _theResult___snd__h684666[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd91493_BIT_4_THEN_2_ELSE_0__q194 = + _theResult___snd__h791493[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd93170_BIT_33_THEN_2_ELSE_0__q43 = + _theResult___snd__h593170[33] ? 2'd2 : 2'd0 ; + assign INV_commitStage_commitTrap_BITS_217_TO_199__q16 = ~commitStage_commitTrap[217:199] ; assign INV_coreFix_aluExe_0_regToExeQ_first__9457_BIT_ETC___d19771 = { ~coreFix_aluExe_0_regToExeQ$first[286:268], INV_coreFix_aluExe_0_regToExeQfirst_BITS_286__ETC__q13[0] ? - x__h906572 : + x__h906570 : 6'd0, - x__h906745, - x__h906765 } ; + x__h906743, + x__h906763 } ; assign INV_coreFix_aluExe_0_regToExeQ_first__9457_BIT_ETC___d19835 = { ~coreFix_aluExe_0_regToExeQ$first[157:139], INV_coreFix_aluExe_0_regToExeQfirst_BITS_157__ETC__q14[0] ? - x__h907120 : + x__h907118 : 6'd0, - x__h907293, - x__h907313 } ; + x__h907291, + x__h907311 } ; assign INV_coreFix_aluExe_0_regToExeQfirst_BITS_157__ETC__q14 = ~coreFix_aluExe_0_regToExeQ$first[157:139] ; assign INV_coreFix_aluExe_0_regToExeQfirst_BITS_286__ETC__q13 = @@ -27349,17 +27347,17 @@ module mkCore(CLK, assign INV_coreFix_aluExe_1_regToExeQ_first__7341_BIT_ETC___d17655 = { ~coreFix_aluExe_1_regToExeQ$first[286:268], INV_coreFix_aluExe_1_regToExeQfirst_BITS_286__ETC__q11[0] ? - x__h866886 : + x__h866885 : 6'd0, - x__h867059, - x__h867079 } ; + x__h867058, + x__h867078 } ; assign INV_coreFix_aluExe_1_regToExeQ_first__7341_BIT_ETC___d17719 = { ~coreFix_aluExe_1_regToExeQ$first[157:139], INV_coreFix_aluExe_1_regToExeQfirst_BITS_157__ETC__q12[0] ? - x__h867434 : + x__h867433 : 6'd0, - x__h867607, - x__h867627 } ; + x__h867606, + x__h867626 } ; assign INV_coreFix_aluExe_1_regToExeQfirst_BITS_157__ETC__q12 = ~coreFix_aluExe_1_regToExeQ$first[157:139] ; assign INV_coreFix_aluExe_1_regToExeQfirst_BITS_286__ETC__q11 = @@ -27370,8 +27368,8 @@ module mkCore(CLK, ~coreFix_memExe_respLrScAmoQ_data_0[108:90] ; assign INV_mmio_dataRespQ_data_0_BITS_108_TO_90__q9 = ~mmio_dataRespQ_data_0[108:90] ; - assign INV_x83399_BITS_108_TO_90__q34 = ~x__h183399[108:90] ; - assign INV_x99251_BITS_108_TO_90__q36 = ~x__h199251[108:90] ; + assign INV_x83397_BITS_108_TO_90__q34 = ~x__h183397[108:90] ; + assign INV_x99249_BITS_108_TO_90__q36 = ~x__h199249[108:90] ; assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d10746 = !_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9532 || (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9533 ? @@ -27459,136 +27457,136 @@ module mkCore(CLK, !IF_IF_NOT_csrf_prv_reg_read__0286_EQ_3_0287_02_ETC___d20323[15] && !checkForException___d21604[13] && NOT_csrf_fs_reg_read__6010_EQ_0_0640_0641_OR_N_ETC___d21629 ; - assign NOT_IF_NOT_rob_deqPort_0_canDeq__3598_3599_OR__ETC___d23844 = - (fflags__h1016316 & csrf_fflags_reg) != fflags__h1016316 || - !r__h853139 && - (IF_rob_deqPort_1_canDeq__3602_THEN_IF_NOT_rob__ETC___d23839 || - fflags__h1016316 != 5'd0) ; + assign NOT_IF_NOT_rob_deqPort_0_canDeq__3600_3601_OR__ETC___d23846 = + (fflags__h1016351 & csrf_fflags_reg) != fflags__h1016351 || + !r__h853138 && + (IF_rob_deqPort_1_canDeq__3604_THEN_IF_NOT_rob__ETC___d23841 || + fflags__h1016351 != 5'd0) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d12707 = - !f1_sfd__h714900[21] && !f1_sfd__h714900[20] && - !f1_sfd__h714900[19] && - !f1_sfd__h714900[18] && - !f1_sfd__h714900[17] && - !f1_sfd__h714900[16] && - !f1_sfd__h714900[15] && - !f1_sfd__h714900[14] && - !f1_sfd__h714900[13] && - !f1_sfd__h714900[12] && - !f1_sfd__h714900[11] && - !f1_sfd__h714900[10] && - !f1_sfd__h714900[9] && - !f1_sfd__h714900[8] && - !f1_sfd__h714900[7] && - !f1_sfd__h714900[6] && - !f1_sfd__h714900[5] && - !f1_sfd__h714900[4] && - !f1_sfd__h714900[3] && - !f1_sfd__h714900[2] && - !f1_sfd__h714900[1] && - !f1_sfd__h714900[0] ; + !f1_sfd__h714897[21] && !f1_sfd__h714897[20] && + !f1_sfd__h714897[19] && + !f1_sfd__h714897[18] && + !f1_sfd__h714897[17] && + !f1_sfd__h714897[16] && + !f1_sfd__h714897[15] && + !f1_sfd__h714897[14] && + !f1_sfd__h714897[13] && + !f1_sfd__h714897[12] && + !f1_sfd__h714897[11] && + !f1_sfd__h714897[10] && + !f1_sfd__h714897[9] && + !f1_sfd__h714897[8] && + !f1_sfd__h714897[7] && + !f1_sfd__h714897[6] && + !f1_sfd__h714897[5] && + !f1_sfd__h714897[4] && + !f1_sfd__h714897[3] && + !f1_sfd__h714897[2] && + !f1_sfd__h714897[1] && + !f1_sfd__h714897[0] ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d13437 = - !f3_sfd__h793198[21] && !f3_sfd__h793198[20] && - !f3_sfd__h793198[19] && - !f3_sfd__h793198[18] && - !f3_sfd__h793198[17] && - !f3_sfd__h793198[16] && - !f3_sfd__h793198[15] && - !f3_sfd__h793198[14] && - !f3_sfd__h793198[13] && - !f3_sfd__h793198[12] && - !f3_sfd__h793198[11] && - !f3_sfd__h793198[10] && - !f3_sfd__h793198[9] && - !f3_sfd__h793198[8] && - !f3_sfd__h793198[7] && - !f3_sfd__h793198[6] && - !f3_sfd__h793198[5] && - !f3_sfd__h793198[4] && - !f3_sfd__h793198[3] && - !f3_sfd__h793198[2] && - !f3_sfd__h793198[1] && - !f3_sfd__h793198[0] ; + !f3_sfd__h793195[21] && !f3_sfd__h793195[20] && + !f3_sfd__h793195[19] && + !f3_sfd__h793195[18] && + !f3_sfd__h793195[17] && + !f3_sfd__h793195[16] && + !f3_sfd__h793195[15] && + !f3_sfd__h793195[14] && + !f3_sfd__h793195[13] && + !f3_sfd__h793195[12] && + !f3_sfd__h793195[11] && + !f3_sfd__h793195[10] && + !f3_sfd__h793195[9] && + !f3_sfd__h793195[8] && + !f3_sfd__h793195[7] && + !f3_sfd__h793195[6] && + !f3_sfd__h793195[5] && + !f3_sfd__h793195[4] && + !f3_sfd__h793195[3] && + !f3_sfd__h793195[2] && + !f3_sfd__h793195[1] && + !f3_sfd__h793195[0] ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d14207 = - !f2_sfd__h753894[21] && !f2_sfd__h753894[20] && - !f2_sfd__h753894[19] && - !f2_sfd__h753894[18] && - !f2_sfd__h753894[17] && - !f2_sfd__h753894[16] && - !f2_sfd__h753894[15] && - !f2_sfd__h753894[14] && - !f2_sfd__h753894[13] && - !f2_sfd__h753894[12] && - !f2_sfd__h753894[11] && - !f2_sfd__h753894[10] && - !f2_sfd__h753894[9] && - !f2_sfd__h753894[8] && - !f2_sfd__h753894[7] && - !f2_sfd__h753894[6] && - !f2_sfd__h753894[5] && - !f2_sfd__h753894[4] && - !f2_sfd__h753894[3] && - !f2_sfd__h753894[2] && - !f2_sfd__h753894[1] && - !f2_sfd__h753894[0] ; + !f2_sfd__h753891[21] && !f2_sfd__h753891[20] && + !f2_sfd__h753891[19] && + !f2_sfd__h753891[18] && + !f2_sfd__h753891[17] && + !f2_sfd__h753891[16] && + !f2_sfd__h753891[15] && + !f2_sfd__h753891[14] && + !f2_sfd__h753891[13] && + !f2_sfd__h753891[12] && + !f2_sfd__h753891[11] && + !f2_sfd__h753891[10] && + !f2_sfd__h753891[9] && + !f2_sfd__h753891[8] && + !f2_sfd__h753891[7] && + !f2_sfd__h753891[6] && + !f2_sfd__h753891[5] && + !f2_sfd__h753891[4] && + !f2_sfd__h753891[3] && + !f2_sfd__h753891[2] && + !f2_sfd__h753891[1] && + !f2_sfd__h753891[0] ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d14916 = - (f1_exp__h714899 != 8'd255 || f1_sfd__h714900 == 23'd0) && - (f1_exp__h714899 != 8'd255 || f1_sfd__h714900 != 23'd0) && - (f1_exp__h714899 != 8'd0 || f1_sfd__h714900 != 23'd0) && + (f1_exp__h714896 != 8'd255 || f1_sfd__h714897 == 23'd0) && + (f1_exp__h714896 != 8'd255 || f1_sfd__h714897 != 23'd0) && + (f1_exp__h714896 != 8'd0 || f1_sfd__h714897 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14913 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d14958 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d14916 | - ((f2_exp__h753893 != 8'd255 || f2_sfd__h753894 == 23'd0) && - (f2_exp__h753893 != 8'd255 || f2_sfd__h753894 != 23'd0) && - (f2_exp__h753893 != 8'd0 || f2_sfd__h753894 != 23'd0) && + ((f2_exp__h753890 != 8'd255 || f2_sfd__h753891 == 23'd0) && + (f2_exp__h753890 != 8'd255 || f2_sfd__h753891 != 23'd0) && + (f2_exp__h753890 != 8'd0 || f2_sfd__h753891 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14954) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15016 = - (f1_exp__h714899 != 8'd255 || f1_sfd__h714900 == 23'd0) && - (f1_exp__h714899 != 8'd255 || f1_sfd__h714900 != 23'd0) && - (f1_exp__h714899 != 8'd0 || f1_sfd__h714900 != 23'd0) && + (f1_exp__h714896 != 8'd255 || f1_sfd__h714897 == 23'd0) && + (f1_exp__h714896 != 8'd255 || f1_sfd__h714897 != 23'd0) && + (f1_exp__h714896 != 8'd0 || f1_sfd__h714897 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15013 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15027 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15016 | - ((f2_exp__h753893 != 8'd255 || f2_sfd__h753894 == 23'd0) && - (f2_exp__h753893 != 8'd255 || f2_sfd__h753894 != 23'd0) && - (f2_exp__h753893 != 8'd0 || f2_sfd__h753894 != 23'd0) && + ((f2_exp__h753890 != 8'd255 || f2_sfd__h753891 == 23'd0) && + (f2_exp__h753890 != 8'd255 || f2_sfd__h753891 != 23'd0) && + (f2_exp__h753890 != 8'd0 || f2_sfd__h753891 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15023) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15056 = - (f1_exp__h714899 != 8'd255 || f1_sfd__h714900 == 23'd0) && - (f1_exp__h714899 != 8'd255 || f1_sfd__h714900 != 23'd0) && - (f1_exp__h714899 != 8'd0 || f1_sfd__h714900 != 23'd0) && + (f1_exp__h714896 != 8'd255 || f1_sfd__h714897 == 23'd0) && + (f1_exp__h714896 != 8'd255 || f1_sfd__h714897 != 23'd0) && + (f1_exp__h714896 != 8'd0 || f1_sfd__h714897 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15053 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15071 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15056 | - ((f2_exp__h753893 != 8'd255 || f2_sfd__h753894 == 23'd0) && - (f2_exp__h753893 != 8'd255 || f2_sfd__h753894 != 23'd0) && - (f2_exp__h753893 != 8'd0 || f2_sfd__h753894 != 23'd0) && + ((f2_exp__h753890 != 8'd255 || f2_sfd__h753891 == 23'd0) && + (f2_exp__h753890 != 8'd255 || f2_sfd__h753891 != 23'd0) && + (f2_exp__h753890 != 8'd0 || f2_sfd__h753891 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15067) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15102 = - (f1_exp__h714899 != 8'd255 || f1_sfd__h714900 == 23'd0) && - (f1_exp__h714899 != 8'd255 || f1_sfd__h714900 != 23'd0) && - (f1_exp__h714899 != 8'd0 || f1_sfd__h714900 != 23'd0) && + (f1_exp__h714896 != 8'd255 || f1_sfd__h714897 == 23'd0) && + (f1_exp__h714896 != 8'd255 || f1_sfd__h714897 != 23'd0) && + (f1_exp__h714896 != 8'd0 || f1_sfd__h714897 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15099 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15115 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15102 | - ((f2_exp__h753893 != 8'd255 || f2_sfd__h753894 == 23'd0) && - (f2_exp__h753893 != 8'd255 || f2_sfd__h753894 != 23'd0) && - (f2_exp__h753893 != 8'd0 || f2_sfd__h753894 != 23'd0) && + ((f2_exp__h753890 != 8'd255 || f2_sfd__h753891 == 23'd0) && + (f2_exp__h753890 != 8'd255 || f2_sfd__h753891 != 23'd0) && + (f2_exp__h753890 != 8'd0 || f2_sfd__h753891 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15111) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15144 = - (f1_exp__h714899 != 8'd255 || f1_sfd__h714900 == 23'd0) && - (f1_exp__h714899 != 8'd255 || f1_sfd__h714900 != 23'd0) && - (f1_exp__h714899 != 8'd0 || f1_sfd__h714900 != 23'd0) && + (f1_exp__h714896 != 8'd255 || f1_sfd__h714897 == 23'd0) && + (f1_exp__h714896 != 8'd255 || f1_sfd__h714897 != 23'd0) && + (f1_exp__h714896 != 8'd0 || f1_sfd__h714897 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15141 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15157 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15144 | - ((f2_exp__h753893 != 8'd255 || f2_sfd__h753894 == 23'd0) && - (f2_exp__h753893 != 8'd255 || f2_sfd__h753894 != 23'd0) && - (f2_exp__h753893 != 8'd0 || f2_sfd__h753894 != 23'd0) && + ((f2_exp__h753890 != 8'd255 || f2_sfd__h753891 == 23'd0) && + (f2_exp__h753890 != 8'd255 || f2_sfd__h753891 != 23'd0) && + (f2_exp__h753890 != 8'd0 || f2_sfd__h753891 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15153) ; - assign NOT_IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN__ETC___d23314 = + assign NOT_IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN__ETC___d23316 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16252 >= 6'd50 ; - assign NOT_IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN__ETC___d23177 = + assign NOT_IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN__ETC___d23179 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16100 >= 6'd50 ; assign NOT_commitStage_commitTrap_2268_BITS_44_TO_43__ETC___d22534 = @@ -27611,7 +27609,7 @@ module mkCore(CLK, coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty && fetchStage$iTlbIfc_noPendingReq && coreFix_memExe_dTlb$noPendingReq ; - assign NOT_commitStage_rg_run_state_2266_2267_AND_NOT_ETC___d23033 = + assign NOT_commitStage_rg_run_state_2266_2267_AND_NOT_ETC___d23035 = !commitStage_rg_run_state && !commitStage_commitTrap[238] && !rob$deqPort_0_deq_data[274] && !rob$deqPort_0_deq_data[18] && @@ -28360,17 +28358,14 @@ module mkCore(CLK, (fetchStage$pipelines_1_first[305:274] != 32'h10500073 || !csrf_tw_reg || csrf_prv_reg == 2'd3) ; - assign NOT_csrf_mtcc_reg_read__6198_BITS_33_TO_28_621_ETC___d22810 = + assign NOT_csrf_mtcc_reg_read__6198_BITS_33_TO_28_621_ETC___d22812 = csrf_mtcc_reg[33:28] >= 6'd50 ; - assign NOT_csrf_prv_reg_read__0286_ULE_1_2614_2729_OR_ETC___d22734 = + assign NOT_csrf_prv_reg_read__0286_ULE_1_2614_2730_OR_ETC___d22736 = !csrf_prv_reg_read__0286_ULE_1___d22614 || - ((commitStage_commitTrap[44:43] == 2'd1) ? - !_0b0_CONCAT_csrf_medeleg_28_26_reg_read__6161_6_ETC___d22642 : - commitStage_commitTrap[44:43] == 2'd0 || - !_0b0_CONCAT_csrf_mideleg_11_reg_read__6172_6173_ETC___d22644) ; - assign NOT_csrf_rg_dpc_read__6343_BITS_33_TO_28_6360__ETC___d23427 = + CASE_commitStage_commitTrap_BITS_44_TO_43_0_NO_ETC__q277 ; + assign NOT_csrf_rg_dpc_read__6343_BITS_33_TO_28_6360__ETC___d23429 = csrf_rg_dpc[33:28] >= 6'd50 ; - assign NOT_csrf_stcc_reg_read__6046_BITS_33_TO_28_606_ETC___d22739 = + assign NOT_csrf_stcc_reg_read__6046_BITS_33_TO_28_606_ETC___d22741 = csrf_stcc_reg[33:28] >= 6'd50 ; assign NOT_fetchStage_pipelines_0_canDeq__0254_0255_O_ETC___d21283 = !fetchStage$pipelines_0_canDeq || @@ -28596,12 +28591,12 @@ module mkCore(CLK, epochManager$checkEpoch_1_check ; assign NOT_mmio_dataPendQ_empty_80_378_AND_rob_RDY_se_ETC___d1379 = !mmio_dataPendQ_empty && rob$RDY_setExecuted_deqLSQ && - coreFix_memExe_lsq$RDY_firstSt && - coreFix_memExe_lsq$RDY_deqSt ; + coreFix_memExe_lsq$RDY_deqSt && + coreFix_memExe_lsq$RDY_firstSt ; assign NOT_mmio_dataPendQ_empty_80_378_AND_rob_RDY_se_ETC___d2026 = !mmio_dataPendQ_empty && rob$RDY_setExecuted_deqLSQ && - coreFix_memExe_lsq$RDY_firstLd && - coreFix_memExe_lsq$RDY_deqLd ; + coreFix_memExe_lsq$RDY_deqLd && + coreFix_memExe_lsq$RDY_firstLd ; assign NOT_regRenamingTable_rename_0_canRename__1151__ETC___d21667 = !regRenamingTable$rename_0_canRename || fetchStage$pipelines_0_first[273:269] == 5'd0 || @@ -28669,14 +28664,14 @@ module mkCore(CLK, epochManager$checkEpoch_1_check && (!fetchStage$pipelines_0_canDeq || NOT_fetchStage_pipelines_0_first__0256_BITS_26_ETC___d21805) ; - assign NOT_rob_deqPort_0_canDeq__3598_3599_OR_rob_RDY_ETC___d23639 = + assign NOT_rob_deqPort_0_canDeq__3600_3601_OR_regRena_ETC___d23641 = (!rob$deqPort_0_canDeq || - rob$RDY_deqPort_0_deq && - regRenamingTable$RDY_commit_0_commit) && + regRenamingTable$RDY_commit_0_commit && + rob$RDY_deqPort_0_deq) && (!rob$deqPort_1_canDeq || rob$RDY_deqPort_1_deq_data && - NOT_rob_deqPort_1_deq_data__3605_BIT_25_3606_3_ETC___d23636) ; - assign NOT_rob_deqPort_0_canDeq__3598_3599_OR_rob_deq_ETC___d23818 = + NOT_rob_deqPort_1_deq_data__3607_BIT_25_3608_3_ETC___d23638) ; + assign NOT_rob_deqPort_0_canDeq__3600_3601_OR_rob_deq_ETC___d23820 = (!rob$deqPort_0_canDeq || rob$deqPort_0_deq_data[25] && !rob$deqPort_0_deq_data[18] && !rob$deqPort_0_deq_data[274] && @@ -28691,15 +28686,15 @@ module mkCore(CLK, rob$deqPort_0_deq_data[469:465] != 5'd24 && rob$deqPort_0_deq_data[469:465] != 5'd25) && rob$deqPort_1_canDeq ; - assign NOT_rob_deqPort_0_deq_data__2261_BITS_469_TO_4_ETC___d23022 = + assign NOT_rob_deqPort_0_deq_data__2261_BITS_469_TO_4_ETC___d23024 = rob$deqPort_0_deq_data[469:465] != 5'd17 || - (IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 != + (IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 != 6'd7 || csrf_stats_module_writeQ$FULL_N) && - (IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 != + (IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 != 6'd6 || csrf_terminate_module_terminateQ$FULL_N) ; - assign NOT_rob_deqPort_1_deq_data__3605_BIT_25_3606_3_ETC___d23636 = + assign NOT_rob_deqPort_1_deq_data__3607_BIT_25_3608_3_ETC___d23638 = !rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[274] || rob$deqPort_1_deq_data[469:465] == 5'd0 || @@ -28712,7 +28707,7 @@ module mkCore(CLK, rob$deqPort_1_deq_data[469:465] == 5'd20 || rob$deqPort_1_deq_data[469:465] == 5'd24 || rob$deqPort_1_deq_data[469:465] == 5'd25 || - rob$RDY_deqPort_1_deq && regRenamingTable$RDY_commit_1_commit ; + regRenamingTable$RDY_commit_1_commit && rob$RDY_deqPort_1_deq ; assign NOT_specTagManager_canClaim__1149_1248_OR_NOT__ETC___d21921 = !specTagManager$canClaim || !regRenamingTable$rename_0_canRename || @@ -28732,47 +28727,47 @@ module mkCore(CLK, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q38, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q39 } ; assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d7127 = - { CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q293, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q294, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q295, + { CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q295, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q296, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q297, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q298 } ; + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q298, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q299, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q300 } ; assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d7137 = { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d7096, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q305, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q307, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d7127, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q306, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q307 } ; + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q308, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q309 } ; assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d7144 = - { CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q314, - !CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q315, + { CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q316, + !CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q317, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d7137, - x__h508765 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d24474 = - { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q316, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q317, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q318 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d24407 = - { CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q278, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q279, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q280 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d24438 = - { CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q299, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q300, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q301, + x__h508764 } ; + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d24476 = + { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q318, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q319, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q320 } ; + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d24409 = + { CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q280, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q281, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q282 } ; + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d24440 = + { CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q301, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q302, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q303, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q304 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d24448 = - { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d24407, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q308, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d24438, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q309, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q310 } ; + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q304, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q305, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q306 } ; + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d24450 = + { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d24409, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q310, + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d24440, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q311, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q312 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12797 = - { {4{f1_exp14899_MINUS_127__q148[7]}}, - f1_exp14899_MINUS_127__q148 } ; + { {4{f1_exp14896_MINUS_127__q148[7]}}, + f1_exp14896_MINUS_127__q148 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12798 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12797 ^ 12'h800) <= @@ -28782,8 +28777,8 @@ module mkCore(CLK, 12'h800) < 12'd1026 ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13512 = - { {4{f3_exp93197_MINUS_127__q165[7]}}, - f3_exp93197_MINUS_127__q165 } ; + { {4{f3_exp93194_MINUS_127__q165[7]}}, + f3_exp93194_MINUS_127__q165 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13513 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13512 ^ 12'h800) <= @@ -28793,8 +28788,8 @@ module mkCore(CLK, 12'h800) < 12'd1026 ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14282 = - { {4{f2_exp53893_MINUS_127__q188[7]}}, - f2_exp53893_MINUS_127__q188 } ; + { {4{f2_exp53890_MINUS_127__q188[7]}}, + f2_exp53890_MINUS_127__q188 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14283 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14282 ^ 12'h800) <= @@ -28822,21 +28817,21 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q189[10:0] - 11'd1023 ; assign SEXT_SEL_ARR_SEL_ARR_coreFix_memExe_dMem_cache_ETC___d4881 = - { {64{x__h264732[63]}}, x__h264732 } ; + { {64{x__h264730[63]}}, x__h264730 } ; assign SEXT_SEL_ARR_SEL_ARR_coreFix_memExe_dMem_cache_ETC___d4889 = - { {96{x__h264887[31]}}, x__h264887 } ; - assign SEXT__0_CONCAT_IF_INV_commitStage_commitTrap_2_ETC___d22677 = - x__h997587 | in__h997656[63:0] ; + { {96{x__h264885[31]}}, x__h264885 } ; + assign SEXT__0_CONCAT_IF_INV_commitStage_commitTrap_2_ETC___d22678 = + x__h997622 | in__h997691[63:0] ; assign SEXT__0_CONCAT_IF_csrf_mepcc_reg_data_lat_0_wh_ETC___d16261 = - x__h855226 | in__h855451[63:0] ; + x__h855225 | in__h855450[63:0] ; assign SEXT__0_CONCAT_IF_csrf_sepcc_reg_data_lat_0_wh_ETC___d16109 = - x__h854233 | in__h854459[63:0] ; + x__h854232 | in__h854458[63:0] ; assign SEXT__0_CONCAT_csrf_mtcc_reg_read__6198_BITS_8_ETC___d16222 = - x__h896272 | in__h855147[63:0] ; + x__h896270 | in__h855146[63:0] ; assign SEXT__0_CONCAT_csrf_rg_dpc_read__6343_BITS_85__ETC___d16367 = - x__h896617 | in__h855977[63:0] ; + x__h896615 | in__h855976[63:0] ; assign SEXT__0_CONCAT_csrf_stcc_reg_read__6046_BITS_8_ETC___d16070 = - x__h895988 | in__h854154[63:0] ; + x__h895986 | in__h854153[63:0] ; assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10071 = { coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q83[10], coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q83 } ; @@ -28890,15 +28885,15 @@ module mkCore(CLK, 8'd127 ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d10694 = { 3'd0, - _theResult___fst_exp__h630314 == 8'd0 && - (sfdin__h630308[56:34] == 23'd0 || guard__h622215 != 2'b0), + _theResult___fst_exp__h630312 == 8'd0 && + (sfdin__h630306[56:34] == 23'd0 || guard__h622213 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h630911 == 8'd255 && - _theResult___fst_sfd__h630912 == 23'd0, + _theResult___fst_exp__h630909 == 8'd255 && + _theResult___fst_sfd__h630910 == 23'd0, 1'd0, - _theResult___fst_exp__h630314 != 8'd255 && - guard__h622215 != 2'b0 } ; + _theResult___fst_exp__h630312 != 8'd255 && + guard__h622213 != 2'b0 } ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d11166 = ({ 3'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d11164 } ^ @@ -28906,15 +28901,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d12091 = { 3'd0, - _theResult___fst_exp__h676061 == 8'd0 && - (sfdin__h676055[56:34] == 23'd0 || guard__h667962 != 2'b0), + _theResult___fst_exp__h676059 == 8'd0 && + (sfdin__h676053[56:34] == 23'd0 || guard__h667960 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h676658 == 8'd255 && - _theResult___fst_sfd__h676659 == 23'd0, + _theResult___fst_exp__h676656 == 8'd255 && + _theResult___fst_sfd__h676657 == 23'd0, 1'd0, - _theResult___fst_exp__h676061 != 8'd255 && - guard__h667962 != 2'b0 } ; + _theResult___fst_exp__h676059 != 8'd255 && + guard__h667960 != 2'b0 } ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d8372 = ({ 3'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d8370 } ^ @@ -28922,15 +28917,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d9297 = { 3'd0, - _theResult___fst_exp__h584565 == 8'd0 && - (sfdin__h584559[56:34] == 23'd0 || guard__h576464 != 2'b0), + _theResult___fst_exp__h584563 == 8'd0 && + (sfdin__h584557[56:34] == 23'd0 || guard__h576462 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h585162 == 8'd255 && - _theResult___fst_sfd__h585163 == 23'd0, + _theResult___fst_exp__h585160 == 8'd255 && + _theResult___fst_sfd__h585161 == 23'd0, 1'd0, - _theResult___fst_exp__h584565 != 8'd255 && - guard__h576464 != 2'b0 } ; + _theResult___fst_exp__h584563 != 8'd255 && + guard__h576462 != 2'b0 } ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d9769 = ({ 3'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d9767 } ^ @@ -28953,37 +28948,37 @@ module mkCore(CLK, 12'd2048 ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14909 = { 3'd0, - _theResult___fst_exp__h743864 == 11'd0 && - (sfdin__h743858[56:5] == 52'd0 || guard__h735638 != 2'b0), + _theResult___fst_exp__h743861 == 11'd0 && + (sfdin__h743855[56:5] == 52'd0 || guard__h735635 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h744696 == 11'd2047 && - _theResult___fst_sfd__h744697 == 52'd0, + _theResult___fst_exp__h744693 == 11'd2047 && + _theResult___fst_sfd__h744694 == 52'd0, 1'd0, - _theResult___fst_exp__h743864 != 11'd2047 && - guard__h735638 != 2'b0 } ; + _theResult___fst_exp__h743861 != 11'd2047 && + guard__h735635 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14950 = { 3'd0, - _theResult___fst_exp__h782717 == 11'd0 && - (sfdin__h782711[56:5] == 52'd0 || guard__h774491 != 2'b0), + _theResult___fst_exp__h782714 == 11'd0 && + (sfdin__h782708[56:5] == 52'd0 || guard__h774488 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h783549 == 11'd2047 && - _theResult___fst_sfd__h783550 == 52'd0, + _theResult___fst_exp__h783546 == 11'd2047 && + _theResult___fst_sfd__h783547 == 52'd0, 1'd0, - _theResult___fst_exp__h782717 != 11'd2047 && - guard__h774491 != 2'b0 } ; + _theResult___fst_exp__h782714 != 11'd2047 && + guard__h774488 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14994 = { 3'd0, - _theResult___fst_exp__h822021 == 11'd0 && - (sfdin__h822015[56:5] == 52'd0 || guard__h813795 != 2'b0), + _theResult___fst_exp__h822018 == 11'd0 && + (sfdin__h822012[56:5] == 52'd0 || guard__h813792 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h822853 == 11'd2047 && - _theResult___fst_sfd__h822854 == 52'd0, + _theResult___fst_exp__h822850 == 11'd2047 && + _theResult___fst_sfd__h822851 == 52'd0, 1'd0, - _theResult___fst_exp__h822021 != 11'd2047 && - guard__h813795 != 2'b0 } ; + _theResult___fst_exp__h822018 != 11'd2047 && + guard__h813792 != 2'b0 } ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d10320 = ({ 3'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d10318 } ^ @@ -28991,15 +28986,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d10723 = { 3'd0, - _theResult___fst_exp__h648080 == 8'd0 && - (sfdin__h648074[56:34] == 23'd0 || guard__h639852 != 2'b0), + _theResult___fst_exp__h648078 == 8'd0 && + (sfdin__h648072[56:34] == 23'd0 || guard__h639850 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h648677 == 8'd255 && - _theResult___fst_sfd__h648678 == 23'd0, + _theResult___fst_exp__h648675 == 8'd255 && + _theResult___fst_sfd__h648676 == 23'd0, 1'd0, - _theResult___fst_exp__h648080 != 8'd255 && - guard__h639852 != 2'b0 } ; + _theResult___fst_exp__h648078 != 8'd255 && + guard__h639850 != 2'b0 } ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d11717 = ({ 3'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d11715 } ^ @@ -29007,15 +29002,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d12120 = { 3'd0, - _theResult___fst_exp__h693827 == 8'd0 && - (sfdin__h693821[56:34] == 23'd0 || guard__h685599 != 2'b0), + _theResult___fst_exp__h693825 == 8'd0 && + (sfdin__h693819[56:34] == 23'd0 || guard__h685597 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h694424 == 8'd255 && - _theResult___fst_sfd__h694425 == 23'd0, + _theResult___fst_exp__h694422 == 8'd255 && + _theResult___fst_sfd__h694423 == 23'd0, 1'd0, - _theResult___fst_exp__h693827 != 8'd255 && - guard__h685599 != 2'b0 } ; + _theResult___fst_exp__h693825 != 8'd255 && + guard__h685597 != 2'b0 } ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d8923 = ({ 3'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d8921 } ^ @@ -29023,15 +29018,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d9326 = { 3'd0, - _theResult___fst_exp__h602331 == 8'd0 && - (sfdin__h602325[56:34] == 23'd0 || guard__h594103 != 2'b0), + _theResult___fst_exp__h602329 == 8'd0 && + (sfdin__h602323[56:34] == 23'd0 || guard__h594101 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h602928 == 8'd255 && - _theResult___fst_sfd__h602929 == 23'd0, + _theResult___fst_exp__h602926 == 8'd255 && + _theResult___fst_sfd__h602927 == 23'd0, 1'd0, - _theResult___fst_exp__h602331 != 8'd255 && - guard__h594103 != 2'b0 } ; + _theResult___fst_exp__h602329 != 8'd255 && + guard__h594101 != 2'b0 } ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d12736 = ({ 6'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d12734 } ^ @@ -29067,37 +29062,37 @@ module mkCore(CLK, 12'h800) ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14892 = { 3'd0, - _theResult___fst_exp__h734287 == 11'd0 && - guard__h726326 != 2'b0, + _theResult___fst_exp__h734284 == 11'd0 && + guard__h726323 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h735045 == 11'd2047 && - _theResult___fst_sfd__h735046 == 52'd0, + _theResult___fst_exp__h735042 == 11'd2047 && + _theResult___fst_sfd__h735043 == 52'd0, 1'd0, - _theResult___fst_exp__h734287 != 11'd2047 && - guard__h726326 != 2'b0 } ; + _theResult___fst_exp__h734284 != 11'd2047 && + guard__h726323 != 2'b0 } ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14933 = { 3'd0, - _theResult___fst_exp__h773140 == 11'd0 && - guard__h765179 != 2'b0, + _theResult___fst_exp__h773137 == 11'd0 && + guard__h765176 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h773898 == 11'd2047 && - _theResult___fst_sfd__h773899 == 52'd0, + _theResult___fst_exp__h773895 == 11'd2047 && + _theResult___fst_sfd__h773896 == 52'd0, 1'd0, - _theResult___fst_exp__h773140 != 11'd2047 && - guard__h765179 != 2'b0 } ; + _theResult___fst_exp__h773137 != 11'd2047 && + guard__h765176 != 2'b0 } ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14977 = { 3'd0, - _theResult___fst_exp__h812444 == 11'd0 && - guard__h804483 != 2'b0, + _theResult___fst_exp__h812441 == 11'd0 && + guard__h804480 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h813202 == 11'd2047 && - _theResult___fst_sfd__h813203 == 52'd0, + _theResult___fst_exp__h813199 == 11'd2047 && + _theResult___fst_sfd__h813200 == 52'd0, 1'd0, - _theResult___fst_exp__h812444 != 11'd2047 && - guard__h804483 != 2'b0 } ; + _theResult___fst_exp__h812441 != 11'd2047 && + guard__h804480 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d10000 = ({ 3'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d9998 } ^ @@ -29111,15 +29106,15 @@ module mkCore(CLK, 9'h100) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d10706 = { 3'd0, - _theResult___fst_exp__h638970 == 8'd0 && - guard__h630922 != 2'b0, + _theResult___fst_exp__h638968 == 8'd0 && + guard__h630920 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h639493 == 8'd255 && - _theResult___fst_sfd__h639494 == 23'd0, + _theResult___fst_exp__h639491 == 8'd255 && + _theResult___fst_sfd__h639492 == 23'd0, 1'd0, - _theResult___fst_exp__h638970 != 8'd255 && - guard__h630922 != 2'b0 } ; + _theResult___fst_exp__h638968 != 8'd255 && + guard__h630920 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d11397 = ({ 3'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d11395 } ^ @@ -29133,15 +29128,15 @@ module mkCore(CLK, 9'h100) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d12103 = { 3'd0, - _theResult___fst_exp__h684717 == 8'd0 && - guard__h676669 != 2'b0, + _theResult___fst_exp__h684715 == 8'd0 && + guard__h676667 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h685240 == 8'd255 && - _theResult___fst_sfd__h685241 == 23'd0, + _theResult___fst_exp__h685238 == 8'd255 && + _theResult___fst_sfd__h685239 == 23'd0, 1'd0, - _theResult___fst_exp__h684717 != 8'd255 && - guard__h676669 != 2'b0 } ; + _theResult___fst_exp__h684715 != 8'd255 && + guard__h676667 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d8603 = ({ 3'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d8601 } ^ @@ -29155,15 +29150,15 @@ module mkCore(CLK, 9'h100) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d9309 = { 3'd0, - _theResult___fst_exp__h593221 == 8'd0 && - guard__h585173 != 2'b0, + _theResult___fst_exp__h593219 == 8'd0 && + guard__h585171 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h593744 == 8'd255 && - _theResult___fst_sfd__h593745 == 23'd0, + _theResult___fst_exp__h593742 == 8'd255 && + _theResult___fst_sfd__h593743 == 23'd0, 1'd0, - _theResult___fst_exp__h593221 != 8'd255 && - guard__h585173 != 2'b0 } ; + _theResult___fst_exp__h593219 != 8'd255 && + guard__h585171 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_memExe_dTlb_procResp__257__ETC___d4668 = { 2'd0, (coreFix_memExe_dTlb$procResp[277] && @@ -29183,18 +29178,18 @@ module mkCore(CLK, 1'd0, csrf_timer_int_en_vec_1 & csrf_timer_int_pend_vec_1, 1'd0 } ; - assign _0_CONCAT_csrf_mtcc_reg_read__6198_BITS_149_TO__ETC___d22832 = - x__h1000345[13:11] < repBound__h855069 ; - assign _0_CONCAT_csrf_mtcc_reg_read__6198_BITS_149_TO__ETC___d22857 = - x__h1000649[13:11] < repBound__h855069 ; - assign _0_CONCAT_csrf_stcc_reg_read__6046_BITS_149_TO__ETC___d22763 = - x__h999688[13:11] < repBound__h854076 ; - assign _0_CONCAT_csrf_stcc_reg_read__6046_BITS_149_TO__ETC___d22788 = - x__h999992[13:11] < repBound__h854076 ; + assign _0_CONCAT_csrf_mtcc_reg_read__6198_BITS_149_TO__ETC___d22834 = + x__h1000380[13:11] < repBound__h855068 ; + assign _0_CONCAT_csrf_mtcc_reg_read__6198_BITS_149_TO__ETC___d22859 = + x__h1000684[13:11] < repBound__h855068 ; + assign _0_CONCAT_csrf_stcc_reg_read__6046_BITS_149_TO__ETC___d22765 = + x__h999723[13:11] < repBound__h854075 ; + assign _0_CONCAT_csrf_stcc_reg_read__6046_BITS_149_TO__ETC___d22790 = + x__h1000027[13:11] < repBound__h854075 ; assign _0_OR_NOT_fetchStage_pipelines_0_first__0256_BI_ETC___d21841 = (fetchStage$pipelines_0_first[268:266] != 3'd1 || specTagManager$RDY_nextSpecTag) && - CASE_k45030_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q268 ; + CASE_k45028_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q268 ; assign _0_OR_NOT_fetchStage_pipelines_1_first__0265_BI_ETC___d21739 = (fetchStage$pipelines_1_first[268:266] != 3'd1 || !fetchStage$pipelines_0_canDeq || @@ -29208,37 +29203,37 @@ module mkCore(CLK, specTagManager$RDY_nextSpecTag) && CASE_fetchStage_pipelines_0_canDeq__0254_AND_N_ETC__q270 ; assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d12804 = - sfd__h715261 >> + sfd__h715258 >> _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d12800 ; assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d13519 = - sfd__h793559 >> + sfd__h793556 >> _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d13515 ; assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d14289 = - sfd__h754255 >> + sfd__h754252 >> _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d14285 ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d10078 = - sfd__h614603 >> + sfd__h614601 >> (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d10074[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d10074) ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d11475 = - sfd__h660350 >> + sfd__h660348 >> (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d11471[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d11471) ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d8681 = - sfd__h568849 >> + sfd__h568847 >> (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d8677[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d8677) ; assign _0b0_CONCAT_csrf_medeleg_28_26_reg_read__6161_6_ETC___d22642 = - medeleg_csr__read__h850223[i__h995336] ; - assign _0b0_CONCAT_csrf_mideleg_11_reg_read__6172_6173_ETC___d22644 = - mideleg_csr__read__h850321[i__h995510] ; - assign _18446744073709551615_SL_csrf_mtcc_reg_read__61_ETC___d22824 = - mask__h1000157 ^ y__h1000274 ; - assign _18446744073709551615_SL_csrf_stcc_reg_read__60_ETC___d22755 = - mask__h999500 ^ y__h999617 ; + medeleg_csr__read__h850222[i__h995334] ; + assign _0b0_CONCAT_csrf_mideleg_11_reg_read__6172_6173_ETC___d22645 = + mideleg_csr__read__h850320[i__h995534] ; + assign _18446744073709551615_SL_csrf_mtcc_reg_read__61_ETC___d22826 = + mask__h1000192 ^ y__h1000309 ; + assign _18446744073709551615_SL_csrf_stcc_reg_read__60_ETC___d22757 = + mask__h999535 ^ y__h999652 ; assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10709 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9532 && (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9533 ? @@ -29644,51 +29639,51 @@ module mkCore(CLK, assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12660 = 12'd3970 - { 7'd0, - f1_sfd__h714900[22] ? + f1_sfd__h714897[22] ? 5'd0 : - (f1_sfd__h714900[21] ? + (f1_sfd__h714897[21] ? 5'd1 : - (f1_sfd__h714900[20] ? + (f1_sfd__h714897[20] ? 5'd2 : - (f1_sfd__h714900[19] ? + (f1_sfd__h714897[19] ? 5'd3 : - (f1_sfd__h714900[18] ? + (f1_sfd__h714897[18] ? 5'd4 : - (f1_sfd__h714900[17] ? + (f1_sfd__h714897[17] ? 5'd5 : - (f1_sfd__h714900[16] ? + (f1_sfd__h714897[16] ? 5'd6 : - (f1_sfd__h714900[15] ? + (f1_sfd__h714897[15] ? 5'd7 : - (f1_sfd__h714900[14] ? + (f1_sfd__h714897[14] ? 5'd8 : - (f1_sfd__h714900[13] ? + (f1_sfd__h714897[13] ? 5'd9 : - (f1_sfd__h714900[12] ? + (f1_sfd__h714897[12] ? 5'd10 : - (f1_sfd__h714900[11] ? + (f1_sfd__h714897[11] ? 5'd11 : - (f1_sfd__h714900[10] ? + (f1_sfd__h714897[10] ? 5'd12 : - (f1_sfd__h714900[9] ? + (f1_sfd__h714897[9] ? 5'd13 : - (f1_sfd__h714900[8] ? + (f1_sfd__h714897[8] ? 5'd14 : - (f1_sfd__h714900[7] ? + (f1_sfd__h714897[7] ? 5'd15 : - (f1_sfd__h714900[6] ? + (f1_sfd__h714897[6] ? 5'd16 : - (f1_sfd__h714900[5] ? + (f1_sfd__h714897[5] ? 5'd17 : - (f1_sfd__h714900[4] ? + (f1_sfd__h714897[4] ? 5'd18 : - (f1_sfd__h714900[3] ? + (f1_sfd__h714897[3] ? 5'd19 : - (f1_sfd__h714900[2] ? + (f1_sfd__h714897[2] ? 5'd20 : - (f1_sfd__h714900[1] ? + (f1_sfd__h714897[1] ? 5'd21 : - (f1_sfd__h714900[0] ? + (f1_sfd__h714897[0] ? 5'd22 : 5'd23)))))))))))))))))))))) } ; assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12661 = @@ -29702,51 +29697,51 @@ module mkCore(CLK, assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13390 = 12'd3970 - { 7'd0, - f3_sfd__h793198[22] ? + f3_sfd__h793195[22] ? 5'd0 : - (f3_sfd__h793198[21] ? + (f3_sfd__h793195[21] ? 5'd1 : - (f3_sfd__h793198[20] ? + (f3_sfd__h793195[20] ? 5'd2 : - (f3_sfd__h793198[19] ? + (f3_sfd__h793195[19] ? 5'd3 : - (f3_sfd__h793198[18] ? + (f3_sfd__h793195[18] ? 5'd4 : - (f3_sfd__h793198[17] ? + (f3_sfd__h793195[17] ? 5'd5 : - (f3_sfd__h793198[16] ? + (f3_sfd__h793195[16] ? 5'd6 : - (f3_sfd__h793198[15] ? + (f3_sfd__h793195[15] ? 5'd7 : - (f3_sfd__h793198[14] ? + (f3_sfd__h793195[14] ? 5'd8 : - (f3_sfd__h793198[13] ? + (f3_sfd__h793195[13] ? 5'd9 : - (f3_sfd__h793198[12] ? + (f3_sfd__h793195[12] ? 5'd10 : - (f3_sfd__h793198[11] ? + (f3_sfd__h793195[11] ? 5'd11 : - (f3_sfd__h793198[10] ? + (f3_sfd__h793195[10] ? 5'd12 : - (f3_sfd__h793198[9] ? + (f3_sfd__h793195[9] ? 5'd13 : - (f3_sfd__h793198[8] ? + (f3_sfd__h793195[8] ? 5'd14 : - (f3_sfd__h793198[7] ? + (f3_sfd__h793195[7] ? 5'd15 : - (f3_sfd__h793198[6] ? + (f3_sfd__h793195[6] ? 5'd16 : - (f3_sfd__h793198[5] ? + (f3_sfd__h793195[5] ? 5'd17 : - (f3_sfd__h793198[4] ? + (f3_sfd__h793195[4] ? 5'd18 : - (f3_sfd__h793198[3] ? + (f3_sfd__h793195[3] ? 5'd19 : - (f3_sfd__h793198[2] ? + (f3_sfd__h793195[2] ? 5'd20 : - (f3_sfd__h793198[1] ? + (f3_sfd__h793195[1] ? 5'd21 : - (f3_sfd__h793198[0] ? + (f3_sfd__h793195[0] ? 5'd22 : 5'd23)))))))))))))))))))))) } ; assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13391 = @@ -29760,51 +29755,51 @@ module mkCore(CLK, assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14160 = 12'd3970 - { 7'd0, - f2_sfd__h753894[22] ? + f2_sfd__h753891[22] ? 5'd0 : - (f2_sfd__h753894[21] ? + (f2_sfd__h753891[21] ? 5'd1 : - (f2_sfd__h753894[20] ? + (f2_sfd__h753891[20] ? 5'd2 : - (f2_sfd__h753894[19] ? + (f2_sfd__h753891[19] ? 5'd3 : - (f2_sfd__h753894[18] ? + (f2_sfd__h753891[18] ? 5'd4 : - (f2_sfd__h753894[17] ? + (f2_sfd__h753891[17] ? 5'd5 : - (f2_sfd__h753894[16] ? + (f2_sfd__h753891[16] ? 5'd6 : - (f2_sfd__h753894[15] ? + (f2_sfd__h753891[15] ? 5'd7 : - (f2_sfd__h753894[14] ? + (f2_sfd__h753891[14] ? 5'd8 : - (f2_sfd__h753894[13] ? + (f2_sfd__h753891[13] ? 5'd9 : - (f2_sfd__h753894[12] ? + (f2_sfd__h753891[12] ? 5'd10 : - (f2_sfd__h753894[11] ? + (f2_sfd__h753891[11] ? 5'd11 : - (f2_sfd__h753894[10] ? + (f2_sfd__h753891[10] ? 5'd12 : - (f2_sfd__h753894[9] ? + (f2_sfd__h753891[9] ? 5'd13 : - (f2_sfd__h753894[8] ? + (f2_sfd__h753891[8] ? 5'd14 : - (f2_sfd__h753894[7] ? + (f2_sfd__h753891[7] ? 5'd15 : - (f2_sfd__h753894[6] ? + (f2_sfd__h753891[6] ? 5'd16 : - (f2_sfd__h753894[5] ? + (f2_sfd__h753891[5] ? 5'd17 : - (f2_sfd__h753894[4] ? + (f2_sfd__h753891[4] ? 5'd18 : - (f2_sfd__h753894[3] ? + (f2_sfd__h753891[3] ? 5'd19 : - (f2_sfd__h753894[2] ? + (f2_sfd__h753891[2] ? 5'd20 : - (f2_sfd__h753894[1] ? + (f2_sfd__h753891[1] ? 5'd21 : - (f2_sfd__h753894[0] ? + (f2_sfd__h753891[0] ? 5'd22 : 5'd23)))))))))))))))))))))) } ; assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14161 = @@ -29845,7 +29840,7 @@ module mkCore(CLK, fetchStage$pipelines_1_first[238:237] != 2'd1 && fetchStage_pipelines_1_first__0265_BITS_268_TO_ETC___d22174 ; assign _dfoo16 = - k__h945030 == 1'd1 && fetchStage$pipelines_0_canDeq && + k__h945028 == 1'd1 && fetchStage$pipelines_0_canDeq && NOT_fetchStage_pipelines_0_first__0256_BITS_26_ETC___d22015 || (fetchStage_pipelines_0_canDeq__0254_AND_NOT_fe_ETC___d22100 || NOT_fetchStage_pipelines_0_canDeq__0254_0255_O_ETC___d22113) == @@ -29853,7 +29848,7 @@ module mkCore(CLK, NOT_fetchStage_pipelines_0_canDeq__0254_0255_O_ETC___d22118 && NOT_fetchStage_pipelines_1_first__0265_BITS_26_ETC___d22130 ; assign _dfoo18 = - k__h945030 == 1'd0 && fetchStage$pipelines_0_canDeq && + k__h945028 == 1'd0 && fetchStage$pipelines_0_canDeq && NOT_fetchStage_pipelines_0_first__0256_BITS_26_ETC___d22015 || (fetchStage_pipelines_0_canDeq__0254_AND_NOT_fe_ETC___d22100 || NOT_fetchStage_pipelines_0_canDeq__0254_0255_O_ETC___d22113) == @@ -29876,48 +29871,48 @@ module mkCore(CLK, commitStage_commitTrap_2268_BITS_44_TO_43_2461_ETC___d22613 ; assign _dfoo24 = rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd42 || rob$deqPort_0_deq_data[469:465] == 5'd24 || rob$deqPort_0_deq_data[469:465] == 5'd25 ; assign _dfoo26 = rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd27 || rob$deqPort_0_deq_data[469:465] == 5'd18 && - IF_rob_deqPort_0_deq_data__2261_BIT_294_3454_T_ETC___d23476 == + IF_rob_deqPort_0_deq_data__2261_BIT_294_3456_T_ETC___d23478 == 4'd9 ; assign _dfoo28 = rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd24 || rob$deqPort_0_deq_data[469:465] == 5'd18 && - IF_rob_deqPort_0_deq_data__2261_BIT_294_3454_T_ETC___d23476 == + IF_rob_deqPort_0_deq_data__2261_BIT_294_3456_T_ETC___d23478 == 4'd6 ; assign _dfoo30 = rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd19 || rob$deqPort_0_deq_data[469:465] == 5'd25 ; assign _dfoo36 = rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd13 || rob$deqPort_0_deq_data[469:465] == 5'd18 && - IF_rob_deqPort_0_deq_data__2261_BIT_294_3454_T_ETC___d23476 == + IF_rob_deqPort_0_deq_data__2261_BIT_294_3456_T_ETC___d23478 == 4'd5 ; assign _dfoo38 = rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd10 || rob$deqPort_0_deq_data[469:465] == 5'd18 && - IF_rob_deqPort_0_deq_data__2261_BIT_294_3454_T_ETC___d23476 == + IF_rob_deqPort_0_deq_data__2261_BIT_294_3456_T_ETC___d23478 == 4'd2 ; assign _dfoo40 = rob$deqPort_0_deq_data[469:465] == 5'd17 && - (IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + (IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd8 || - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd19) || rob$deqPort_0_deq_data[469:465] == 5'd24 ; assign _dfoo7 = @@ -29988,1415 +29983,1415 @@ module mkCore(CLK, assign _dor1sbCons$EN_setReady_1_put = WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F || WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; - assign _theResult_____2__h515368 = + assign _theResult_____2__h515366 = IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d7240 ? - next_deqP___1__h515613 : + next_deqP___1__h515611 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP ; - assign _theResult_____2__h526145 = + assign _theResult_____2__h526143 = IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d7334 ? - next_deqP___1__h526390 : + next_deqP___1__h526388 : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP ; - assign _theResult_____2__h533238 = + assign _theResult_____2__h533236 = IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d7493 ? - next_deqP___1__h533668 : + next_deqP___1__h533666 : coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP ; - assign _theResult_____2__h543873 = + assign _theResult_____2__h543871 = IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d7577 ? - next_deqP___1__h544303 : + next_deqP___1__h544301 : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP ; - assign _theResult_____2__h557706 = + assign _theResult_____2__h557704 = IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d7782 ? - next_deqP___1__h557951 : + next_deqP___1__h557949 : coreFix_memExe_memRespLdQ_deqP ; - assign _theResult_____2__h561485 = + assign _theResult_____2__h561483 = IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d7864 ? - next_deqP___1__h561730 : + next_deqP___1__h561728 : coreFix_memExe_forwardQ_deqP ; - assign _theResult____h576454 = - (value__h577076 == 54'd0) ? sfd__h568849 : 57'd1 ; - assign _theResult____h594093 = + assign _theResult____h576452 = + (value__h577074 == 54'd0) ? sfd__h568847 : 57'd1 ; + assign _theResult____h594091 = ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d8677 ^ 12'h800) < 12'd2105) ? - result__h594706 : - _theResult____h576454 ; - assign _theResult____h622205 = - (value__h622825 == 54'd0) ? sfd__h614603 : 57'd1 ; - assign _theResult____h639842 = + result__h594704 : + _theResult____h576452 ; + assign _theResult____h622203 = + (value__h622823 == 54'd0) ? sfd__h614601 : 57'd1 ; + assign _theResult____h639840 = ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d10074 ^ 12'h800) < 12'd2105) ? - result__h640455 : - _theResult____h622205 ; - assign _theResult____h667952 = - (value__h668572 == 54'd0) ? sfd__h660350 : 57'd1 ; - assign _theResult____h685589 = + result__h640453 : + _theResult____h622203 ; + assign _theResult____h667950 = + (value__h668570 == 54'd0) ? sfd__h660348 : 57'd1 ; + assign _theResult____h685587 = ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d11471 ^ 12'h800) < 12'd2105) ? - result__h686202 : - _theResult____h667952 ; - assign _theResult____h735628 = + result__h686200 : + _theResult____h667950 ; + assign _theResult____h735625 = ((_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d12800 ^ 12'h800) < 12'd2105) ? - result__h736241 : - ((value__h719844 == 25'd0) ? sfd__h715261 : 57'd1) ; - assign _theResult____h774481 = + result__h736238 : + ((value__h719841 == 25'd0) ? sfd__h715258 : 57'd1) ; + assign _theResult____h774478 = ((_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d14285 ^ 12'h800) < 12'd2105) ? - result__h775094 : - ((value__h758697 == 25'd0) ? sfd__h754255 : 57'd1) ; - assign _theResult____h813785 = + result__h775091 : + ((value__h758694 == 25'd0) ? sfd__h754252 : 57'd1) ; + assign _theResult____h813782 = ((_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d13515 ^ 12'h800) < 12'd2105) ? - result__h814398 : - ((value__h798001 == 25'd0) ? sfd__h793559 : 57'd1) ; - assign _theResult____h920232 = + result__h814395 : + ((value__h797998 == 25'd0) ? sfd__h793556 : 57'd1) ; + assign _theResult____h920230 = (csrf_prv_reg != 2'd3 || csrf_ie_vec_3) ? - enabled_ints___1__h920757 : + enabled_ints___1__h920755 : 16'd0 ; - assign _theResult___exp__h585081 = - sfd__h584657[24] ? - ((_theResult___fst_exp__h584565 == 8'd254) ? + assign _theResult___exp__h585079 = + sfd__h584655[24] ? + ((_theResult___fst_exp__h584563 == 8'd254) ? 8'd255 : - din_inc___2_exp__h611598) : - ((_theResult___fst_exp__h584565 == 8'd0 && - sfd__h584657[24:23] == 2'b01) ? + din_inc___2_exp__h611596) : + ((_theResult___fst_exp__h584563 == 8'd0 && + sfd__h584655[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h584565) ; - assign _theResult___exp__h593663 = - sfd__h593239[24] ? - ((_theResult___fst_exp__h593221 == 8'd254) ? + _theResult___fst_exp__h584563) ; + assign _theResult___exp__h593661 = + sfd__h593237[24] ? + ((_theResult___fst_exp__h593219 == 8'd254) ? 8'd255 : - din_inc___2_exp__h611622) : - ((_theResult___fst_exp__h593221 == 8'd0 && - sfd__h593239[24:23] == 2'b01) ? + din_inc___2_exp__h611620) : + ((_theResult___fst_exp__h593219 == 8'd0 && + sfd__h593237[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h593221) ; - assign _theResult___exp__h602847 = - sfd__h602423[24] ? - ((_theResult___fst_exp__h602331 == 8'd254) ? + _theResult___fst_exp__h593219) ; + assign _theResult___exp__h602845 = + sfd__h602421[24] ? + ((_theResult___fst_exp__h602329 == 8'd254) ? 8'd255 : - din_inc___2_exp__h611652) : - ((_theResult___fst_exp__h602331 == 8'd0 && - sfd__h602423[24:23] == 2'b01) ? + din_inc___2_exp__h611650) : + ((_theResult___fst_exp__h602329 == 8'd0 && + sfd__h602421[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h602331) ; - assign _theResult___exp__h611483 = - sfd__h611035[24] ? - ((_theResult___fst_exp__h611016 == 8'd254) ? + _theResult___fst_exp__h602329) ; + assign _theResult___exp__h611481 = + sfd__h611033[24] ? + ((_theResult___fst_exp__h611014 == 8'd254) ? 8'd255 : - din_inc___2_exp__h611676) : - ((_theResult___fst_exp__h611016 == 8'd0 && - sfd__h611035[24:23] == 2'b01) ? + din_inc___2_exp__h611674) : + ((_theResult___fst_exp__h611014 == 8'd0 && + sfd__h611033[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h611016) ; - assign _theResult___exp__h611585 = + _theResult___fst_exp__h611014) ; + assign _theResult___exp__h611583 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h611576 ; - assign _theResult___exp__h630830 = - sfd__h630406[24] ? - ((_theResult___fst_exp__h630314 == 8'd254) ? + _theResult___fst_exp__h611574 ; + assign _theResult___exp__h630828 = + sfd__h630404[24] ? + ((_theResult___fst_exp__h630312 == 8'd254) ? 8'd255 : - din_inc___2_exp__h657347) : - ((_theResult___fst_exp__h630314 == 8'd0 && - sfd__h630406[24:23] == 2'b01) ? + din_inc___2_exp__h657345) : + ((_theResult___fst_exp__h630312 == 8'd0 && + sfd__h630404[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h630314) ; - assign _theResult___exp__h639412 = - sfd__h638988[24] ? - ((_theResult___fst_exp__h638970 == 8'd254) ? + _theResult___fst_exp__h630312) ; + assign _theResult___exp__h639410 = + sfd__h638986[24] ? + ((_theResult___fst_exp__h638968 == 8'd254) ? 8'd255 : - din_inc___2_exp__h657371) : - ((_theResult___fst_exp__h638970 == 8'd0 && - sfd__h638988[24:23] == 2'b01) ? + din_inc___2_exp__h657369) : + ((_theResult___fst_exp__h638968 == 8'd0 && + sfd__h638986[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h638970) ; - assign _theResult___exp__h648596 = - sfd__h648172[24] ? - ((_theResult___fst_exp__h648080 == 8'd254) ? + _theResult___fst_exp__h638968) ; + assign _theResult___exp__h648594 = + sfd__h648170[24] ? + ((_theResult___fst_exp__h648078 == 8'd254) ? 8'd255 : - din_inc___2_exp__h657401) : - ((_theResult___fst_exp__h648080 == 8'd0 && - sfd__h648172[24:23] == 2'b01) ? + din_inc___2_exp__h657399) : + ((_theResult___fst_exp__h648078 == 8'd0 && + sfd__h648170[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h648080) ; - assign _theResult___exp__h657232 = - sfd__h656784[24] ? - ((_theResult___fst_exp__h656765 == 8'd254) ? + _theResult___fst_exp__h648078) ; + assign _theResult___exp__h657230 = + sfd__h656782[24] ? + ((_theResult___fst_exp__h656763 == 8'd254) ? 8'd255 : - din_inc___2_exp__h657425) : - ((_theResult___fst_exp__h656765 == 8'd0 && - sfd__h656784[24:23] == 2'b01) ? + din_inc___2_exp__h657423) : + ((_theResult___fst_exp__h656763 == 8'd0 && + sfd__h656782[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h656765) ; - assign _theResult___exp__h657334 = + _theResult___fst_exp__h656763) ; + assign _theResult___exp__h657332 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h657325 ; - assign _theResult___exp__h676577 = - sfd__h676153[24] ? - ((_theResult___fst_exp__h676061 == 8'd254) ? + _theResult___fst_exp__h657323 ; + assign _theResult___exp__h676575 = + sfd__h676151[24] ? + ((_theResult___fst_exp__h676059 == 8'd254) ? 8'd255 : - din_inc___2_exp__h703094) : - ((_theResult___fst_exp__h676061 == 8'd0 && - sfd__h676153[24:23] == 2'b01) ? + din_inc___2_exp__h703092) : + ((_theResult___fst_exp__h676059 == 8'd0 && + sfd__h676151[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h676061) ; - assign _theResult___exp__h685159 = - sfd__h684735[24] ? - ((_theResult___fst_exp__h684717 == 8'd254) ? + _theResult___fst_exp__h676059) ; + assign _theResult___exp__h685157 = + sfd__h684733[24] ? + ((_theResult___fst_exp__h684715 == 8'd254) ? 8'd255 : - din_inc___2_exp__h703118) : - ((_theResult___fst_exp__h684717 == 8'd0 && - sfd__h684735[24:23] == 2'b01) ? + din_inc___2_exp__h703116) : + ((_theResult___fst_exp__h684715 == 8'd0 && + sfd__h684733[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h684717) ; - assign _theResult___exp__h694343 = - sfd__h693919[24] ? - ((_theResult___fst_exp__h693827 == 8'd254) ? + _theResult___fst_exp__h684715) ; + assign _theResult___exp__h694341 = + sfd__h693917[24] ? + ((_theResult___fst_exp__h693825 == 8'd254) ? 8'd255 : - din_inc___2_exp__h703148) : - ((_theResult___fst_exp__h693827 == 8'd0 && - sfd__h693919[24:23] == 2'b01) ? + din_inc___2_exp__h703146) : + ((_theResult___fst_exp__h693825 == 8'd0 && + sfd__h693917[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h693827) ; - assign _theResult___exp__h702979 = - sfd__h702531[24] ? - ((_theResult___fst_exp__h702512 == 8'd254) ? + _theResult___fst_exp__h693825) ; + assign _theResult___exp__h702977 = + sfd__h702529[24] ? + ((_theResult___fst_exp__h702510 == 8'd254) ? 8'd255 : - din_inc___2_exp__h703172) : - ((_theResult___fst_exp__h702512 == 8'd0 && - sfd__h702531[24:23] == 2'b01) ? + din_inc___2_exp__h703170) : + ((_theResult___fst_exp__h702510 == 8'd0 && + sfd__h702529[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h702512) ; - assign _theResult___exp__h703081 = + _theResult___fst_exp__h702510) ; + assign _theResult___exp__h703079 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h703072 ; - assign _theResult___exp__h734942 = - sfd__h734305[53] ? - ((_theResult___fst_exp__h734287 == 11'd2046) ? + _theResult___fst_exp__h703070 ; + assign _theResult___exp__h734939 = + sfd__h734302[53] ? + ((_theResult___fst_exp__h734284 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h753537) : - ((_theResult___fst_exp__h734287 == 11'd0 && - sfd__h734305[53:52] == 2'b01) ? + din_inc___2_exp__h753534) : + ((_theResult___fst_exp__h734284 == 11'd0 && + sfd__h734302[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h734287) ; - assign _theResult___exp__h744593 = - sfd__h743956[53] ? - ((_theResult___fst_exp__h743864 == 11'd2046) ? + _theResult___fst_exp__h734284) ; + assign _theResult___exp__h744590 = + sfd__h743953[53] ? + ((_theResult___fst_exp__h743861 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h753572) : - ((_theResult___fst_exp__h743864 == 11'd0 && - sfd__h743956[53:52] == 2'b01) ? + din_inc___2_exp__h753569) : + ((_theResult___fst_exp__h743861 == 11'd0 && + sfd__h743953[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h743864) ; - assign _theResult___exp__h753377 = - sfd__h752716[53] ? - ((_theResult___fst_exp__h752697 == 11'd2046) ? + _theResult___fst_exp__h743861) ; + assign _theResult___exp__h753374 = + sfd__h752713[53] ? + ((_theResult___fst_exp__h752694 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h753598) : - ((_theResult___fst_exp__h752697 == 11'd0 && - sfd__h752716[53:52] == 2'b01) ? + din_inc___2_exp__h753595) : + ((_theResult___fst_exp__h752694 == 11'd0 && + sfd__h752713[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h752697) ; - assign _theResult___exp__h773795 = - sfd__h773158[53] ? - ((_theResult___fst_exp__h773140 == 11'd2046) ? + _theResult___fst_exp__h752694) ; + assign _theResult___exp__h773792 = + sfd__h773155[53] ? + ((_theResult___fst_exp__h773137 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h792390) : - ((_theResult___fst_exp__h773140 == 11'd0 && - sfd__h773158[53:52] == 2'b01) ? + din_inc___2_exp__h792387) : + ((_theResult___fst_exp__h773137 == 11'd0 && + sfd__h773155[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h773140) ; - assign _theResult___exp__h783446 = - sfd__h782809[53] ? - ((_theResult___fst_exp__h782717 == 11'd2046) ? + _theResult___fst_exp__h773137) ; + assign _theResult___exp__h783443 = + sfd__h782806[53] ? + ((_theResult___fst_exp__h782714 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h792425) : - ((_theResult___fst_exp__h782717 == 11'd0 && - sfd__h782809[53:52] == 2'b01) ? + din_inc___2_exp__h792422) : + ((_theResult___fst_exp__h782714 == 11'd0 && + sfd__h782806[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h782717) ; - assign _theResult___exp__h792230 = - sfd__h791569[53] ? - ((_theResult___fst_exp__h791550 == 11'd2046) ? + _theResult___fst_exp__h782714) ; + assign _theResult___exp__h792227 = + sfd__h791566[53] ? + ((_theResult___fst_exp__h791547 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h792451) : - ((_theResult___fst_exp__h791550 == 11'd0 && - sfd__h791569[53:52] == 2'b01) ? + din_inc___2_exp__h792448) : + ((_theResult___fst_exp__h791547 == 11'd0 && + sfd__h791566[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h791550) ; - assign _theResult___exp__h813099 = - sfd__h812462[53] ? - ((_theResult___fst_exp__h812444 == 11'd2046) ? + _theResult___fst_exp__h791547) ; + assign _theResult___exp__h813096 = + sfd__h812459[53] ? + ((_theResult___fst_exp__h812441 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h831694) : - ((_theResult___fst_exp__h812444 == 11'd0 && - sfd__h812462[53:52] == 2'b01) ? + din_inc___2_exp__h831691) : + ((_theResult___fst_exp__h812441 == 11'd0 && + sfd__h812459[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h812444) ; - assign _theResult___exp__h822750 = - sfd__h822113[53] ? - ((_theResult___fst_exp__h822021 == 11'd2046) ? + _theResult___fst_exp__h812441) ; + assign _theResult___exp__h822747 = + sfd__h822110[53] ? + ((_theResult___fst_exp__h822018 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h831729) : - ((_theResult___fst_exp__h822021 == 11'd0 && - sfd__h822113[53:52] == 2'b01) ? + din_inc___2_exp__h831726) : + ((_theResult___fst_exp__h822018 == 11'd0 && + sfd__h822110[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h822021) ; - assign _theResult___exp__h831534 = - sfd__h830873[53] ? - ((_theResult___fst_exp__h830854 == 11'd2046) ? + _theResult___fst_exp__h822018) ; + assign _theResult___exp__h831531 = + sfd__h830870[53] ? + ((_theResult___fst_exp__h830851 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h831755) : - ((_theResult___fst_exp__h830854 == 11'd0 && - sfd__h830873[53:52] == 2'b01) ? + din_inc___2_exp__h831752) : + ((_theResult___fst_exp__h830851 == 11'd0 && + sfd__h830870[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h830854) ; - assign _theResult___fst__h836129 = - a__h835707[63] ? a___1__h836134 : a__h835707 ; - assign _theResult___fst_exp__h584565 = - _theResult____h576454[56] ? + _theResult___fst_exp__h830851) ; + assign _theResult___fst__h836126 = + a__h835704[63] ? a___1__h836131 : a__h835704 ; + assign _theResult___fst_exp__h584563 = + _theResult____h576452[56] ? 8'd2 : - _theResult___fst_exp__h584639 ; - assign _theResult___fst_exp__h584630 = + _theResult___fst_exp__h584637 ; + assign _theResult___fst_exp__h584628 = 8'd0 - { 2'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d8370 } ; - assign _theResult___fst_exp__h584636 = - (!_theResult____h576454[56] && !_theResult____h576454[55] && - !_theResult____h576454[54] && - !_theResult____h576454[53] && - !_theResult____h576454[52] && - !_theResult____h576454[51] && - !_theResult____h576454[50] && - !_theResult____h576454[49] && - !_theResult____h576454[48] && - !_theResult____h576454[47] && - !_theResult____h576454[46] && - !_theResult____h576454[45] && - !_theResult____h576454[44] && - !_theResult____h576454[43] && - !_theResult____h576454[42] && - !_theResult____h576454[41] && - !_theResult____h576454[40] && - !_theResult____h576454[39] && - !_theResult____h576454[38] && - !_theResult____h576454[37] && - !_theResult____h576454[36] && - !_theResult____h576454[35] && - !_theResult____h576454[34] && - !_theResult____h576454[33] && - !_theResult____h576454[32] && - !_theResult____h576454[31] && - !_theResult____h576454[30] && - !_theResult____h576454[29] && - !_theResult____h576454[28] && - !_theResult____h576454[27] && - !_theResult____h576454[26] && - !_theResult____h576454[25] && - !_theResult____h576454[24] && - !_theResult____h576454[23] && - !_theResult____h576454[22] && - !_theResult____h576454[21] && - !_theResult____h576454[20] && - !_theResult____h576454[19] && - !_theResult____h576454[18] && - !_theResult____h576454[17] && - !_theResult____h576454[16] && - !_theResult____h576454[15] && - !_theResult____h576454[14] && - !_theResult____h576454[13] && - !_theResult____h576454[12] && - !_theResult____h576454[11] && - !_theResult____h576454[10] && - !_theResult____h576454[9] && - !_theResult____h576454[8] && - !_theResult____h576454[7] && - !_theResult____h576454[6] && - !_theResult____h576454[5] && - !_theResult____h576454[4] && - !_theResult____h576454[3] && - !_theResult____h576454[2] && - !_theResult____h576454[1] && - !_theResult____h576454[0] || + assign _theResult___fst_exp__h584634 = + (!_theResult____h576452[56] && !_theResult____h576452[55] && + !_theResult____h576452[54] && + !_theResult____h576452[53] && + !_theResult____h576452[52] && + !_theResult____h576452[51] && + !_theResult____h576452[50] && + !_theResult____h576452[49] && + !_theResult____h576452[48] && + !_theResult____h576452[47] && + !_theResult____h576452[46] && + !_theResult____h576452[45] && + !_theResult____h576452[44] && + !_theResult____h576452[43] && + !_theResult____h576452[42] && + !_theResult____h576452[41] && + !_theResult____h576452[40] && + !_theResult____h576452[39] && + !_theResult____h576452[38] && + !_theResult____h576452[37] && + !_theResult____h576452[36] && + !_theResult____h576452[35] && + !_theResult____h576452[34] && + !_theResult____h576452[33] && + !_theResult____h576452[32] && + !_theResult____h576452[31] && + !_theResult____h576452[30] && + !_theResult____h576452[29] && + !_theResult____h576452[28] && + !_theResult____h576452[27] && + !_theResult____h576452[26] && + !_theResult____h576452[25] && + !_theResult____h576452[24] && + !_theResult____h576452[23] && + !_theResult____h576452[22] && + !_theResult____h576452[21] && + !_theResult____h576452[20] && + !_theResult____h576452[19] && + !_theResult____h576452[18] && + !_theResult____h576452[17] && + !_theResult____h576452[16] && + !_theResult____h576452[15] && + !_theResult____h576452[14] && + !_theResult____h576452[13] && + !_theResult____h576452[12] && + !_theResult____h576452[11] && + !_theResult____h576452[10] && + !_theResult____h576452[9] && + !_theResult____h576452[8] && + !_theResult____h576452[7] && + !_theResult____h576452[6] && + !_theResult____h576452[5] && + !_theResult____h576452[4] && + !_theResult____h576452[3] && + !_theResult____h576452[2] && + !_theResult____h576452[1] && + !_theResult____h576452[0] || !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d8372) ? 8'd0 : - _theResult___fst_exp__h584630 ; - assign _theResult___fst_exp__h584639 = - (!_theResult____h576454[56] && _theResult____h576454[55]) ? + _theResult___fst_exp__h584628 ; + assign _theResult___fst_exp__h584637 = + (!_theResult____h576452[56] && _theResult____h576452[55]) ? 8'd1 : - _theResult___fst_exp__h584636 ; - assign _theResult___fst_exp__h585162 = - (_theResult___fst_exp__h584565 == 8'd255) ? - _theResult___fst_exp__h584565 : - _theResult___fst_exp__h585159 ; - assign _theResult___fst_exp__h593212 = + _theResult___fst_exp__h584634 ; + assign _theResult___fst_exp__h585160 = + (_theResult___fst_exp__h584563 == 8'd255) ? + _theResult___fst_exp__h584563 : + _theResult___fst_exp__h585157 ; + assign _theResult___fst_exp__h593210 = 8'd129 - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d8601 } ; - assign _theResult___fst_exp__h593218 = + assign _theResult___fst_exp__h593216 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d8546 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d8603) ? 8'd0 : - _theResult___fst_exp__h593212 ; - assign _theResult___fst_exp__h593221 = + _theResult___fst_exp__h593210 ; + assign _theResult___fst_exp__h593219 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h593218 : + _theResult___fst_exp__h593216 : 8'd129 ; - assign _theResult___fst_exp__h593744 = - (_theResult___fst_exp__h593221 == 8'd255) ? - _theResult___fst_exp__h593221 : - _theResult___fst_exp__h593741 ; - assign _theResult___fst_exp__h602331 = - _theResult____h594093[56] ? + assign _theResult___fst_exp__h593742 = + (_theResult___fst_exp__h593219 == 8'd255) ? + _theResult___fst_exp__h593219 : + _theResult___fst_exp__h593739 ; + assign _theResult___fst_exp__h602329 = + _theResult____h594091[56] ? 8'd2 : - _theResult___fst_exp__h602405 ; - assign _theResult___fst_exp__h602396 = + _theResult___fst_exp__h602403 ; + assign _theResult___fst_exp__h602394 = 8'd0 - { 2'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d8921 } ; - assign _theResult___fst_exp__h602402 = - (!_theResult____h594093[56] && !_theResult____h594093[55] && - !_theResult____h594093[54] && - !_theResult____h594093[53] && - !_theResult____h594093[52] && - !_theResult____h594093[51] && - !_theResult____h594093[50] && - !_theResult____h594093[49] && - !_theResult____h594093[48] && - !_theResult____h594093[47] && - !_theResult____h594093[46] && - !_theResult____h594093[45] && - !_theResult____h594093[44] && - !_theResult____h594093[43] && - !_theResult____h594093[42] && - !_theResult____h594093[41] && - !_theResult____h594093[40] && - !_theResult____h594093[39] && - !_theResult____h594093[38] && - !_theResult____h594093[37] && - !_theResult____h594093[36] && - !_theResult____h594093[35] && - !_theResult____h594093[34] && - !_theResult____h594093[33] && - !_theResult____h594093[32] && - !_theResult____h594093[31] && - !_theResult____h594093[30] && - !_theResult____h594093[29] && - !_theResult____h594093[28] && - !_theResult____h594093[27] && - !_theResult____h594093[26] && - !_theResult____h594093[25] && - !_theResult____h594093[24] && - !_theResult____h594093[23] && - !_theResult____h594093[22] && - !_theResult____h594093[21] && - !_theResult____h594093[20] && - !_theResult____h594093[19] && - !_theResult____h594093[18] && - !_theResult____h594093[17] && - !_theResult____h594093[16] && - !_theResult____h594093[15] && - !_theResult____h594093[14] && - !_theResult____h594093[13] && - !_theResult____h594093[12] && - !_theResult____h594093[11] && - !_theResult____h594093[10] && - !_theResult____h594093[9] && - !_theResult____h594093[8] && - !_theResult____h594093[7] && - !_theResult____h594093[6] && - !_theResult____h594093[5] && - !_theResult____h594093[4] && - !_theResult____h594093[3] && - !_theResult____h594093[2] && - !_theResult____h594093[1] && - !_theResult____h594093[0] || + assign _theResult___fst_exp__h602400 = + (!_theResult____h594091[56] && !_theResult____h594091[55] && + !_theResult____h594091[54] && + !_theResult____h594091[53] && + !_theResult____h594091[52] && + !_theResult____h594091[51] && + !_theResult____h594091[50] && + !_theResult____h594091[49] && + !_theResult____h594091[48] && + !_theResult____h594091[47] && + !_theResult____h594091[46] && + !_theResult____h594091[45] && + !_theResult____h594091[44] && + !_theResult____h594091[43] && + !_theResult____h594091[42] && + !_theResult____h594091[41] && + !_theResult____h594091[40] && + !_theResult____h594091[39] && + !_theResult____h594091[38] && + !_theResult____h594091[37] && + !_theResult____h594091[36] && + !_theResult____h594091[35] && + !_theResult____h594091[34] && + !_theResult____h594091[33] && + !_theResult____h594091[32] && + !_theResult____h594091[31] && + !_theResult____h594091[30] && + !_theResult____h594091[29] && + !_theResult____h594091[28] && + !_theResult____h594091[27] && + !_theResult____h594091[26] && + !_theResult____h594091[25] && + !_theResult____h594091[24] && + !_theResult____h594091[23] && + !_theResult____h594091[22] && + !_theResult____h594091[21] && + !_theResult____h594091[20] && + !_theResult____h594091[19] && + !_theResult____h594091[18] && + !_theResult____h594091[17] && + !_theResult____h594091[16] && + !_theResult____h594091[15] && + !_theResult____h594091[14] && + !_theResult____h594091[13] && + !_theResult____h594091[12] && + !_theResult____h594091[11] && + !_theResult____h594091[10] && + !_theResult____h594091[9] && + !_theResult____h594091[8] && + !_theResult____h594091[7] && + !_theResult____h594091[6] && + !_theResult____h594091[5] && + !_theResult____h594091[4] && + !_theResult____h594091[3] && + !_theResult____h594091[2] && + !_theResult____h594091[1] && + !_theResult____h594091[0] || !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d8923) ? 8'd0 : - _theResult___fst_exp__h602396 ; - assign _theResult___fst_exp__h602405 = - (!_theResult____h594093[56] && _theResult____h594093[55]) ? + _theResult___fst_exp__h602394 ; + assign _theResult___fst_exp__h602403 = + (!_theResult____h594091[56] && _theResult____h594091[55]) ? 8'd1 : - _theResult___fst_exp__h602402 ; - assign _theResult___fst_exp__h602928 = - (_theResult___fst_exp__h602331 == 8'd255) ? - _theResult___fst_exp__h602331 : - _theResult___fst_exp__h602925 ; - assign _theResult___fst_exp__h610968 = + _theResult___fst_exp__h602400 ; + assign _theResult___fst_exp__h602926 = + (_theResult___fst_exp__h602329 == 8'd255) ? + _theResult___fst_exp__h602329 : + _theResult___fst_exp__h602923 ; + assign _theResult___fst_exp__h610966 = (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q49[7:0] == 8'd0) ? 8'd1 : SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q49[7:0] ; - assign _theResult___fst_exp__h611007 = + assign _theResult___fst_exp__h611005 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q49[7:0] - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d8601 } ; - assign _theResult___fst_exp__h611013 = + assign _theResult___fst_exp__h611011 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d8546 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d8996) ? 8'd0 : - _theResult___fst_exp__h611007 ; - assign _theResult___fst_exp__h611016 = + _theResult___fst_exp__h611005 ; + assign _theResult___fst_exp__h611014 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h611013 : - _theResult___fst_exp__h610968 ; - assign _theResult___fst_exp__h611564 = - (_theResult___fst_exp__h611016 == 8'd255) ? - _theResult___fst_exp__h611016 : - _theResult___fst_exp__h611561 ; - assign _theResult___fst_exp__h611573 = + _theResult___fst_exp__h611011 : + _theResult___fst_exp__h610966 ; + assign _theResult___fst_exp__h611562 = + (_theResult___fst_exp__h611014 == 8'd255) ? + _theResult___fst_exp__h611014 : + _theResult___fst_exp__h611559 ; + assign _theResult___fst_exp__h611571 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8135 ? - _theResult___snd_fst_exp__h593747 : - _theResult___fst_exp__h576436) : + _theResult___snd_fst_exp__h593745 : + _theResult___fst_exp__h576434) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8675 ? - _theResult___snd_fst_exp__h611567 : - _theResult___fst_exp__h576436) ; - assign _theResult___fst_exp__h611576 = + _theResult___snd_fst_exp__h611565 : + _theResult___fst_exp__h576434) ; + assign _theResult___fst_exp__h611574 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == 52'd0) ? 8'd0 : - _theResult___fst_exp__h611573 ; - assign _theResult___fst_exp__h630314 = - _theResult____h622205[56] ? + _theResult___fst_exp__h611571 ; + assign _theResult___fst_exp__h630312 = + _theResult____h622203[56] ? 8'd2 : - _theResult___fst_exp__h630388 ; - assign _theResult___fst_exp__h630379 = + _theResult___fst_exp__h630386 ; + assign _theResult___fst_exp__h630377 = 8'd0 - { 2'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d9767 } ; - assign _theResult___fst_exp__h630385 = - (!_theResult____h622205[56] && !_theResult____h622205[55] && - !_theResult____h622205[54] && - !_theResult____h622205[53] && - !_theResult____h622205[52] && - !_theResult____h622205[51] && - !_theResult____h622205[50] && - !_theResult____h622205[49] && - !_theResult____h622205[48] && - !_theResult____h622205[47] && - !_theResult____h622205[46] && - !_theResult____h622205[45] && - !_theResult____h622205[44] && - !_theResult____h622205[43] && - !_theResult____h622205[42] && - !_theResult____h622205[41] && - !_theResult____h622205[40] && - !_theResult____h622205[39] && - !_theResult____h622205[38] && - !_theResult____h622205[37] && - !_theResult____h622205[36] && - !_theResult____h622205[35] && - !_theResult____h622205[34] && - !_theResult____h622205[33] && - !_theResult____h622205[32] && - !_theResult____h622205[31] && - !_theResult____h622205[30] && - !_theResult____h622205[29] && - !_theResult____h622205[28] && - !_theResult____h622205[27] && - !_theResult____h622205[26] && - !_theResult____h622205[25] && - !_theResult____h622205[24] && - !_theResult____h622205[23] && - !_theResult____h622205[22] && - !_theResult____h622205[21] && - !_theResult____h622205[20] && - !_theResult____h622205[19] && - !_theResult____h622205[18] && - !_theResult____h622205[17] && - !_theResult____h622205[16] && - !_theResult____h622205[15] && - !_theResult____h622205[14] && - !_theResult____h622205[13] && - !_theResult____h622205[12] && - !_theResult____h622205[11] && - !_theResult____h622205[10] && - !_theResult____h622205[9] && - !_theResult____h622205[8] && - !_theResult____h622205[7] && - !_theResult____h622205[6] && - !_theResult____h622205[5] && - !_theResult____h622205[4] && - !_theResult____h622205[3] && - !_theResult____h622205[2] && - !_theResult____h622205[1] && - !_theResult____h622205[0] || + assign _theResult___fst_exp__h630383 = + (!_theResult____h622203[56] && !_theResult____h622203[55] && + !_theResult____h622203[54] && + !_theResult____h622203[53] && + !_theResult____h622203[52] && + !_theResult____h622203[51] && + !_theResult____h622203[50] && + !_theResult____h622203[49] && + !_theResult____h622203[48] && + !_theResult____h622203[47] && + !_theResult____h622203[46] && + !_theResult____h622203[45] && + !_theResult____h622203[44] && + !_theResult____h622203[43] && + !_theResult____h622203[42] && + !_theResult____h622203[41] && + !_theResult____h622203[40] && + !_theResult____h622203[39] && + !_theResult____h622203[38] && + !_theResult____h622203[37] && + !_theResult____h622203[36] && + !_theResult____h622203[35] && + !_theResult____h622203[34] && + !_theResult____h622203[33] && + !_theResult____h622203[32] && + !_theResult____h622203[31] && + !_theResult____h622203[30] && + !_theResult____h622203[29] && + !_theResult____h622203[28] && + !_theResult____h622203[27] && + !_theResult____h622203[26] && + !_theResult____h622203[25] && + !_theResult____h622203[24] && + !_theResult____h622203[23] && + !_theResult____h622203[22] && + !_theResult____h622203[21] && + !_theResult____h622203[20] && + !_theResult____h622203[19] && + !_theResult____h622203[18] && + !_theResult____h622203[17] && + !_theResult____h622203[16] && + !_theResult____h622203[15] && + !_theResult____h622203[14] && + !_theResult____h622203[13] && + !_theResult____h622203[12] && + !_theResult____h622203[11] && + !_theResult____h622203[10] && + !_theResult____h622203[9] && + !_theResult____h622203[8] && + !_theResult____h622203[7] && + !_theResult____h622203[6] && + !_theResult____h622203[5] && + !_theResult____h622203[4] && + !_theResult____h622203[3] && + !_theResult____h622203[2] && + !_theResult____h622203[1] && + !_theResult____h622203[0] || !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d9769) ? 8'd0 : - _theResult___fst_exp__h630379 ; - assign _theResult___fst_exp__h630388 = - (!_theResult____h622205[56] && _theResult____h622205[55]) ? + _theResult___fst_exp__h630377 ; + assign _theResult___fst_exp__h630386 = + (!_theResult____h622203[56] && _theResult____h622203[55]) ? 8'd1 : - _theResult___fst_exp__h630385 ; - assign _theResult___fst_exp__h630911 = - (_theResult___fst_exp__h630314 == 8'd255) ? - _theResult___fst_exp__h630314 : - _theResult___fst_exp__h630908 ; - assign _theResult___fst_exp__h638961 = + _theResult___fst_exp__h630383 ; + assign _theResult___fst_exp__h630909 = + (_theResult___fst_exp__h630312 == 8'd255) ? + _theResult___fst_exp__h630312 : + _theResult___fst_exp__h630906 ; + assign _theResult___fst_exp__h638959 = 8'd129 - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d9998 } ; - assign _theResult___fst_exp__h638967 = + assign _theResult___fst_exp__h638965 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d9943 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d10000) ? 8'd0 : - _theResult___fst_exp__h638961 ; - assign _theResult___fst_exp__h638970 = + _theResult___fst_exp__h638959 ; + assign _theResult___fst_exp__h638968 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h638967 : + _theResult___fst_exp__h638965 : 8'd129 ; - assign _theResult___fst_exp__h639493 = - (_theResult___fst_exp__h638970 == 8'd255) ? - _theResult___fst_exp__h638970 : - _theResult___fst_exp__h639490 ; - assign _theResult___fst_exp__h648080 = - _theResult____h639842[56] ? + assign _theResult___fst_exp__h639491 = + (_theResult___fst_exp__h638968 == 8'd255) ? + _theResult___fst_exp__h638968 : + _theResult___fst_exp__h639488 ; + assign _theResult___fst_exp__h648078 = + _theResult____h639840[56] ? 8'd2 : - _theResult___fst_exp__h648154 ; - assign _theResult___fst_exp__h648145 = + _theResult___fst_exp__h648152 ; + assign _theResult___fst_exp__h648143 = 8'd0 - { 2'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d10318 } ; - assign _theResult___fst_exp__h648151 = - (!_theResult____h639842[56] && !_theResult____h639842[55] && - !_theResult____h639842[54] && - !_theResult____h639842[53] && - !_theResult____h639842[52] && - !_theResult____h639842[51] && - !_theResult____h639842[50] && - !_theResult____h639842[49] && - !_theResult____h639842[48] && - !_theResult____h639842[47] && - !_theResult____h639842[46] && - !_theResult____h639842[45] && - !_theResult____h639842[44] && - !_theResult____h639842[43] && - !_theResult____h639842[42] && - !_theResult____h639842[41] && - !_theResult____h639842[40] && - !_theResult____h639842[39] && - !_theResult____h639842[38] && - !_theResult____h639842[37] && - !_theResult____h639842[36] && - !_theResult____h639842[35] && - !_theResult____h639842[34] && - !_theResult____h639842[33] && - !_theResult____h639842[32] && - !_theResult____h639842[31] && - !_theResult____h639842[30] && - !_theResult____h639842[29] && - !_theResult____h639842[28] && - !_theResult____h639842[27] && - !_theResult____h639842[26] && - !_theResult____h639842[25] && - !_theResult____h639842[24] && - !_theResult____h639842[23] && - !_theResult____h639842[22] && - !_theResult____h639842[21] && - !_theResult____h639842[20] && - !_theResult____h639842[19] && - !_theResult____h639842[18] && - !_theResult____h639842[17] && - !_theResult____h639842[16] && - !_theResult____h639842[15] && - !_theResult____h639842[14] && - !_theResult____h639842[13] && - !_theResult____h639842[12] && - !_theResult____h639842[11] && - !_theResult____h639842[10] && - !_theResult____h639842[9] && - !_theResult____h639842[8] && - !_theResult____h639842[7] && - !_theResult____h639842[6] && - !_theResult____h639842[5] && - !_theResult____h639842[4] && - !_theResult____h639842[3] && - !_theResult____h639842[2] && - !_theResult____h639842[1] && - !_theResult____h639842[0] || + assign _theResult___fst_exp__h648149 = + (!_theResult____h639840[56] && !_theResult____h639840[55] && + !_theResult____h639840[54] && + !_theResult____h639840[53] && + !_theResult____h639840[52] && + !_theResult____h639840[51] && + !_theResult____h639840[50] && + !_theResult____h639840[49] && + !_theResult____h639840[48] && + !_theResult____h639840[47] && + !_theResult____h639840[46] && + !_theResult____h639840[45] && + !_theResult____h639840[44] && + !_theResult____h639840[43] && + !_theResult____h639840[42] && + !_theResult____h639840[41] && + !_theResult____h639840[40] && + !_theResult____h639840[39] && + !_theResult____h639840[38] && + !_theResult____h639840[37] && + !_theResult____h639840[36] && + !_theResult____h639840[35] && + !_theResult____h639840[34] && + !_theResult____h639840[33] && + !_theResult____h639840[32] && + !_theResult____h639840[31] && + !_theResult____h639840[30] && + !_theResult____h639840[29] && + !_theResult____h639840[28] && + !_theResult____h639840[27] && + !_theResult____h639840[26] && + !_theResult____h639840[25] && + !_theResult____h639840[24] && + !_theResult____h639840[23] && + !_theResult____h639840[22] && + !_theResult____h639840[21] && + !_theResult____h639840[20] && + !_theResult____h639840[19] && + !_theResult____h639840[18] && + !_theResult____h639840[17] && + !_theResult____h639840[16] && + !_theResult____h639840[15] && + !_theResult____h639840[14] && + !_theResult____h639840[13] && + !_theResult____h639840[12] && + !_theResult____h639840[11] && + !_theResult____h639840[10] && + !_theResult____h639840[9] && + !_theResult____h639840[8] && + !_theResult____h639840[7] && + !_theResult____h639840[6] && + !_theResult____h639840[5] && + !_theResult____h639840[4] && + !_theResult____h639840[3] && + !_theResult____h639840[2] && + !_theResult____h639840[1] && + !_theResult____h639840[0] || !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d10320) ? 8'd0 : - _theResult___fst_exp__h648145 ; - assign _theResult___fst_exp__h648154 = - (!_theResult____h639842[56] && _theResult____h639842[55]) ? + _theResult___fst_exp__h648143 ; + assign _theResult___fst_exp__h648152 = + (!_theResult____h639840[56] && _theResult____h639840[55]) ? 8'd1 : - _theResult___fst_exp__h648151 ; - assign _theResult___fst_exp__h648677 = - (_theResult___fst_exp__h648080 == 8'd255) ? - _theResult___fst_exp__h648080 : - _theResult___fst_exp__h648674 ; - assign _theResult___fst_exp__h656717 = + _theResult___fst_exp__h648149 ; + assign _theResult___fst_exp__h648675 = + (_theResult___fst_exp__h648078 == 8'd255) ? + _theResult___fst_exp__h648078 : + _theResult___fst_exp__h648672 ; + assign _theResult___fst_exp__h656715 = (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q84[7:0] == 8'd0) ? 8'd1 : SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q84[7:0] ; - assign _theResult___fst_exp__h656756 = + assign _theResult___fst_exp__h656754 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q84[7:0] - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d9998 } ; - assign _theResult___fst_exp__h656762 = + assign _theResult___fst_exp__h656760 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d9943 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d10393) ? 8'd0 : - _theResult___fst_exp__h656756 ; - assign _theResult___fst_exp__h656765 = + _theResult___fst_exp__h656754 ; + assign _theResult___fst_exp__h656763 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h656762 : - _theResult___fst_exp__h656717 ; - assign _theResult___fst_exp__h657313 = - (_theResult___fst_exp__h656765 == 8'd255) ? - _theResult___fst_exp__h656765 : - _theResult___fst_exp__h657310 ; - assign _theResult___fst_exp__h657322 = + _theResult___fst_exp__h656760 : + _theResult___fst_exp__h656715 ; + assign _theResult___fst_exp__h657311 = + (_theResult___fst_exp__h656763 == 8'd255) ? + _theResult___fst_exp__h656763 : + _theResult___fst_exp__h657308 ; + assign _theResult___fst_exp__h657320 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9532 ? - _theResult___snd_fst_exp__h639496 : - _theResult___fst_exp__h622187) : + _theResult___snd_fst_exp__h639494 : + _theResult___fst_exp__h622185) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10072 ? - _theResult___snd_fst_exp__h657316 : - _theResult___fst_exp__h622187) ; - assign _theResult___fst_exp__h657325 = + _theResult___snd_fst_exp__h657314 : + _theResult___fst_exp__h622185) ; + assign _theResult___fst_exp__h657323 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == 52'd0) ? 8'd0 : - _theResult___fst_exp__h657322 ; - assign _theResult___fst_exp__h676061 = - _theResult____h667952[56] ? + _theResult___fst_exp__h657320 ; + assign _theResult___fst_exp__h676059 = + _theResult____h667950[56] ? 8'd2 : - _theResult___fst_exp__h676135 ; - assign _theResult___fst_exp__h676126 = + _theResult___fst_exp__h676133 ; + assign _theResult___fst_exp__h676124 = 8'd0 - { 2'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d11164 } ; - assign _theResult___fst_exp__h676132 = - (!_theResult____h667952[56] && !_theResult____h667952[55] && - !_theResult____h667952[54] && - !_theResult____h667952[53] && - !_theResult____h667952[52] && - !_theResult____h667952[51] && - !_theResult____h667952[50] && - !_theResult____h667952[49] && - !_theResult____h667952[48] && - !_theResult____h667952[47] && - !_theResult____h667952[46] && - !_theResult____h667952[45] && - !_theResult____h667952[44] && - !_theResult____h667952[43] && - !_theResult____h667952[42] && - !_theResult____h667952[41] && - !_theResult____h667952[40] && - !_theResult____h667952[39] && - !_theResult____h667952[38] && - !_theResult____h667952[37] && - !_theResult____h667952[36] && - !_theResult____h667952[35] && - !_theResult____h667952[34] && - !_theResult____h667952[33] && - !_theResult____h667952[32] && - !_theResult____h667952[31] && - !_theResult____h667952[30] && - !_theResult____h667952[29] && - !_theResult____h667952[28] && - !_theResult____h667952[27] && - !_theResult____h667952[26] && - !_theResult____h667952[25] && - !_theResult____h667952[24] && - !_theResult____h667952[23] && - !_theResult____h667952[22] && - !_theResult____h667952[21] && - !_theResult____h667952[20] && - !_theResult____h667952[19] && - !_theResult____h667952[18] && - !_theResult____h667952[17] && - !_theResult____h667952[16] && - !_theResult____h667952[15] && - !_theResult____h667952[14] && - !_theResult____h667952[13] && - !_theResult____h667952[12] && - !_theResult____h667952[11] && - !_theResult____h667952[10] && - !_theResult____h667952[9] && - !_theResult____h667952[8] && - !_theResult____h667952[7] && - !_theResult____h667952[6] && - !_theResult____h667952[5] && - !_theResult____h667952[4] && - !_theResult____h667952[3] && - !_theResult____h667952[2] && - !_theResult____h667952[1] && - !_theResult____h667952[0] || + assign _theResult___fst_exp__h676130 = + (!_theResult____h667950[56] && !_theResult____h667950[55] && + !_theResult____h667950[54] && + !_theResult____h667950[53] && + !_theResult____h667950[52] && + !_theResult____h667950[51] && + !_theResult____h667950[50] && + !_theResult____h667950[49] && + !_theResult____h667950[48] && + !_theResult____h667950[47] && + !_theResult____h667950[46] && + !_theResult____h667950[45] && + !_theResult____h667950[44] && + !_theResult____h667950[43] && + !_theResult____h667950[42] && + !_theResult____h667950[41] && + !_theResult____h667950[40] && + !_theResult____h667950[39] && + !_theResult____h667950[38] && + !_theResult____h667950[37] && + !_theResult____h667950[36] && + !_theResult____h667950[35] && + !_theResult____h667950[34] && + !_theResult____h667950[33] && + !_theResult____h667950[32] && + !_theResult____h667950[31] && + !_theResult____h667950[30] && + !_theResult____h667950[29] && + !_theResult____h667950[28] && + !_theResult____h667950[27] && + !_theResult____h667950[26] && + !_theResult____h667950[25] && + !_theResult____h667950[24] && + !_theResult____h667950[23] && + !_theResult____h667950[22] && + !_theResult____h667950[21] && + !_theResult____h667950[20] && + !_theResult____h667950[19] && + !_theResult____h667950[18] && + !_theResult____h667950[17] && + !_theResult____h667950[16] && + !_theResult____h667950[15] && + !_theResult____h667950[14] && + !_theResult____h667950[13] && + !_theResult____h667950[12] && + !_theResult____h667950[11] && + !_theResult____h667950[10] && + !_theResult____h667950[9] && + !_theResult____h667950[8] && + !_theResult____h667950[7] && + !_theResult____h667950[6] && + !_theResult____h667950[5] && + !_theResult____h667950[4] && + !_theResult____h667950[3] && + !_theResult____h667950[2] && + !_theResult____h667950[1] && + !_theResult____h667950[0] || !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d11166) ? 8'd0 : - _theResult___fst_exp__h676126 ; - assign _theResult___fst_exp__h676135 = - (!_theResult____h667952[56] && _theResult____h667952[55]) ? + _theResult___fst_exp__h676124 ; + assign _theResult___fst_exp__h676133 = + (!_theResult____h667950[56] && _theResult____h667950[55]) ? 8'd1 : - _theResult___fst_exp__h676132 ; - assign _theResult___fst_exp__h676658 = - (_theResult___fst_exp__h676061 == 8'd255) ? - _theResult___fst_exp__h676061 : - _theResult___fst_exp__h676655 ; - assign _theResult___fst_exp__h684708 = + _theResult___fst_exp__h676130 ; + assign _theResult___fst_exp__h676656 = + (_theResult___fst_exp__h676059 == 8'd255) ? + _theResult___fst_exp__h676059 : + _theResult___fst_exp__h676653 ; + assign _theResult___fst_exp__h684706 = 8'd129 - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d11395 } ; - assign _theResult___fst_exp__h684714 = + assign _theResult___fst_exp__h684712 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d11340 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d11397) ? 8'd0 : - _theResult___fst_exp__h684708 ; - assign _theResult___fst_exp__h684717 = + _theResult___fst_exp__h684706 ; + assign _theResult___fst_exp__h684715 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h684714 : + _theResult___fst_exp__h684712 : 8'd129 ; - assign _theResult___fst_exp__h685240 = - (_theResult___fst_exp__h684717 == 8'd255) ? - _theResult___fst_exp__h684717 : - _theResult___fst_exp__h685237 ; - assign _theResult___fst_exp__h693827 = - _theResult____h685589[56] ? + assign _theResult___fst_exp__h685238 = + (_theResult___fst_exp__h684715 == 8'd255) ? + _theResult___fst_exp__h684715 : + _theResult___fst_exp__h685235 ; + assign _theResult___fst_exp__h693825 = + _theResult____h685587[56] ? 8'd2 : - _theResult___fst_exp__h693901 ; - assign _theResult___fst_exp__h693892 = + _theResult___fst_exp__h693899 ; + assign _theResult___fst_exp__h693890 = 8'd0 - { 2'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d11715 } ; - assign _theResult___fst_exp__h693898 = - (!_theResult____h685589[56] && !_theResult____h685589[55] && - !_theResult____h685589[54] && - !_theResult____h685589[53] && - !_theResult____h685589[52] && - !_theResult____h685589[51] && - !_theResult____h685589[50] && - !_theResult____h685589[49] && - !_theResult____h685589[48] && - !_theResult____h685589[47] && - !_theResult____h685589[46] && - !_theResult____h685589[45] && - !_theResult____h685589[44] && - !_theResult____h685589[43] && - !_theResult____h685589[42] && - !_theResult____h685589[41] && - !_theResult____h685589[40] && - !_theResult____h685589[39] && - !_theResult____h685589[38] && - !_theResult____h685589[37] && - !_theResult____h685589[36] && - !_theResult____h685589[35] && - !_theResult____h685589[34] && - !_theResult____h685589[33] && - !_theResult____h685589[32] && - !_theResult____h685589[31] && - !_theResult____h685589[30] && - !_theResult____h685589[29] && - !_theResult____h685589[28] && - !_theResult____h685589[27] && - !_theResult____h685589[26] && - !_theResult____h685589[25] && - !_theResult____h685589[24] && - !_theResult____h685589[23] && - !_theResult____h685589[22] && - !_theResult____h685589[21] && - !_theResult____h685589[20] && - !_theResult____h685589[19] && - !_theResult____h685589[18] && - !_theResult____h685589[17] && - !_theResult____h685589[16] && - !_theResult____h685589[15] && - !_theResult____h685589[14] && - !_theResult____h685589[13] && - !_theResult____h685589[12] && - !_theResult____h685589[11] && - !_theResult____h685589[10] && - !_theResult____h685589[9] && - !_theResult____h685589[8] && - !_theResult____h685589[7] && - !_theResult____h685589[6] && - !_theResult____h685589[5] && - !_theResult____h685589[4] && - !_theResult____h685589[3] && - !_theResult____h685589[2] && - !_theResult____h685589[1] && - !_theResult____h685589[0] || + assign _theResult___fst_exp__h693896 = + (!_theResult____h685587[56] && !_theResult____h685587[55] && + !_theResult____h685587[54] && + !_theResult____h685587[53] && + !_theResult____h685587[52] && + !_theResult____h685587[51] && + !_theResult____h685587[50] && + !_theResult____h685587[49] && + !_theResult____h685587[48] && + !_theResult____h685587[47] && + !_theResult____h685587[46] && + !_theResult____h685587[45] && + !_theResult____h685587[44] && + !_theResult____h685587[43] && + !_theResult____h685587[42] && + !_theResult____h685587[41] && + !_theResult____h685587[40] && + !_theResult____h685587[39] && + !_theResult____h685587[38] && + !_theResult____h685587[37] && + !_theResult____h685587[36] && + !_theResult____h685587[35] && + !_theResult____h685587[34] && + !_theResult____h685587[33] && + !_theResult____h685587[32] && + !_theResult____h685587[31] && + !_theResult____h685587[30] && + !_theResult____h685587[29] && + !_theResult____h685587[28] && + !_theResult____h685587[27] && + !_theResult____h685587[26] && + !_theResult____h685587[25] && + !_theResult____h685587[24] && + !_theResult____h685587[23] && + !_theResult____h685587[22] && + !_theResult____h685587[21] && + !_theResult____h685587[20] && + !_theResult____h685587[19] && + !_theResult____h685587[18] && + !_theResult____h685587[17] && + !_theResult____h685587[16] && + !_theResult____h685587[15] && + !_theResult____h685587[14] && + !_theResult____h685587[13] && + !_theResult____h685587[12] && + !_theResult____h685587[11] && + !_theResult____h685587[10] && + !_theResult____h685587[9] && + !_theResult____h685587[8] && + !_theResult____h685587[7] && + !_theResult____h685587[6] && + !_theResult____h685587[5] && + !_theResult____h685587[4] && + !_theResult____h685587[3] && + !_theResult____h685587[2] && + !_theResult____h685587[1] && + !_theResult____h685587[0] || !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d11717) ? 8'd0 : - _theResult___fst_exp__h693892 ; - assign _theResult___fst_exp__h693901 = - (!_theResult____h685589[56] && _theResult____h685589[55]) ? + _theResult___fst_exp__h693890 ; + assign _theResult___fst_exp__h693899 = + (!_theResult____h685587[56] && _theResult____h685587[55]) ? 8'd1 : - _theResult___fst_exp__h693898 ; - assign _theResult___fst_exp__h694424 = - (_theResult___fst_exp__h693827 == 8'd255) ? - _theResult___fst_exp__h693827 : - _theResult___fst_exp__h694421 ; - assign _theResult___fst_exp__h702464 = + _theResult___fst_exp__h693896 ; + assign _theResult___fst_exp__h694422 = + (_theResult___fst_exp__h693825 == 8'd255) ? + _theResult___fst_exp__h693825 : + _theResult___fst_exp__h694419 ; + assign _theResult___fst_exp__h702462 = (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q119[7:0] == 8'd0) ? 8'd1 : SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q119[7:0] ; - assign _theResult___fst_exp__h702503 = + assign _theResult___fst_exp__h702501 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q119[7:0] - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d11395 } ; - assign _theResult___fst_exp__h702509 = + assign _theResult___fst_exp__h702507 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d11340 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d11790) ? 8'd0 : - _theResult___fst_exp__h702503 ; - assign _theResult___fst_exp__h702512 = + _theResult___fst_exp__h702501 ; + assign _theResult___fst_exp__h702510 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h702509 : - _theResult___fst_exp__h702464 ; - assign _theResult___fst_exp__h703060 = - (_theResult___fst_exp__h702512 == 8'd255) ? - _theResult___fst_exp__h702512 : - _theResult___fst_exp__h703057 ; - assign _theResult___fst_exp__h703069 = + _theResult___fst_exp__h702507 : + _theResult___fst_exp__h702462 ; + assign _theResult___fst_exp__h703058 = + (_theResult___fst_exp__h702510 == 8'd255) ? + _theResult___fst_exp__h702510 : + _theResult___fst_exp__h703055 ; + assign _theResult___fst_exp__h703067 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10929 ? - _theResult___snd_fst_exp__h685243 : - _theResult___fst_exp__h667934) : + _theResult___snd_fst_exp__h685241 : + _theResult___fst_exp__h667932) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11469 ? - _theResult___snd_fst_exp__h703063 : - _theResult___fst_exp__h667934) ; - assign _theResult___fst_exp__h703072 = + _theResult___snd_fst_exp__h703061 : + _theResult___fst_exp__h667932) ; + assign _theResult___fst_exp__h703070 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == 52'd0) ? 8'd0 : - _theResult___fst_exp__h703069 ; - assign _theResult___fst_exp__h719214 = + _theResult___fst_exp__h703067 ; + assign _theResult___fst_exp__h719211 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q27 ; - assign _theResult___fst_exp__h734278 = + assign _theResult___fst_exp__h734275 = 11'd897 - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d12734 } ; - assign _theResult___fst_exp__h734284 = - (f1_exp__h714899 == 8'd0 && !f1_sfd__h714900[22] && + assign _theResult___fst_exp__h734281 = + (f1_exp__h714896 == 8'd0 && !f1_sfd__h714897[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d12707 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d12736) ? 11'd0 : - _theResult___fst_exp__h734278 ; - assign _theResult___fst_exp__h734287 = - (f1_exp__h714899 == 8'd0) ? - _theResult___fst_exp__h734284 : + _theResult___fst_exp__h734275 ; + assign _theResult___fst_exp__h734284 = + (f1_exp__h714896 == 8'd0) ? + _theResult___fst_exp__h734281 : 11'd897 ; - assign _theResult___fst_exp__h735042 = + assign _theResult___fst_exp__h735039 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard26326_0b0_theResult___fst_exp34287_0_ETC__q156 : + CASE_guard26323_0b0_theResult___fst_exp34284_0_ETC__q156 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13170 ; - assign _theResult___fst_exp__h735045 = - (_theResult___fst_exp__h734287 == 11'd2047) ? - _theResult___fst_exp__h734287 : - _theResult___fst_exp__h735042 ; - assign _theResult___fst_exp__h743864 = - _theResult____h735628[56] ? + assign _theResult___fst_exp__h735042 = + (_theResult___fst_exp__h734284 == 11'd2047) ? + _theResult___fst_exp__h734284 : + _theResult___fst_exp__h735039 ; + assign _theResult___fst_exp__h743861 = + _theResult____h735625[56] ? 11'd2 : - _theResult___fst_exp__h743938 ; - assign _theResult___fst_exp__h743929 = + _theResult___fst_exp__h743935 ; + assign _theResult___fst_exp__h743926 = 11'd0 - { 5'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d13046 } ; - assign _theResult___fst_exp__h743935 = - (!_theResult____h735628[56] && !_theResult____h735628[55] && - !_theResult____h735628[54] && - !_theResult____h735628[53] && - !_theResult____h735628[52] && - !_theResult____h735628[51] && - !_theResult____h735628[50] && - !_theResult____h735628[49] && - !_theResult____h735628[48] && - !_theResult____h735628[47] && - !_theResult____h735628[46] && - !_theResult____h735628[45] && - !_theResult____h735628[44] && - !_theResult____h735628[43] && - !_theResult____h735628[42] && - !_theResult____h735628[41] && - !_theResult____h735628[40] && - !_theResult____h735628[39] && - !_theResult____h735628[38] && - !_theResult____h735628[37] && - !_theResult____h735628[36] && - !_theResult____h735628[35] && - !_theResult____h735628[34] && - !_theResult____h735628[33] && - !_theResult____h735628[32] && - !_theResult____h735628[31] && - !_theResult____h735628[30] && - !_theResult____h735628[29] && - !_theResult____h735628[28] && - !_theResult____h735628[27] && - !_theResult____h735628[26] && - !_theResult____h735628[25] && - !_theResult____h735628[24] && - !_theResult____h735628[23] && - !_theResult____h735628[22] && - !_theResult____h735628[21] && - !_theResult____h735628[20] && - !_theResult____h735628[19] && - !_theResult____h735628[18] && - !_theResult____h735628[17] && - !_theResult____h735628[16] && - !_theResult____h735628[15] && - !_theResult____h735628[14] && - !_theResult____h735628[13] && - !_theResult____h735628[12] && - !_theResult____h735628[11] && - !_theResult____h735628[10] && - !_theResult____h735628[9] && - !_theResult____h735628[8] && - !_theResult____h735628[7] && - !_theResult____h735628[6] && - !_theResult____h735628[5] && - !_theResult____h735628[4] && - !_theResult____h735628[3] && - !_theResult____h735628[2] && - !_theResult____h735628[1] && - !_theResult____h735628[0] || + assign _theResult___fst_exp__h743932 = + (!_theResult____h735625[56] && !_theResult____h735625[55] && + !_theResult____h735625[54] && + !_theResult____h735625[53] && + !_theResult____h735625[52] && + !_theResult____h735625[51] && + !_theResult____h735625[50] && + !_theResult____h735625[49] && + !_theResult____h735625[48] && + !_theResult____h735625[47] && + !_theResult____h735625[46] && + !_theResult____h735625[45] && + !_theResult____h735625[44] && + !_theResult____h735625[43] && + !_theResult____h735625[42] && + !_theResult____h735625[41] && + !_theResult____h735625[40] && + !_theResult____h735625[39] && + !_theResult____h735625[38] && + !_theResult____h735625[37] && + !_theResult____h735625[36] && + !_theResult____h735625[35] && + !_theResult____h735625[34] && + !_theResult____h735625[33] && + !_theResult____h735625[32] && + !_theResult____h735625[31] && + !_theResult____h735625[30] && + !_theResult____h735625[29] && + !_theResult____h735625[28] && + !_theResult____h735625[27] && + !_theResult____h735625[26] && + !_theResult____h735625[25] && + !_theResult____h735625[24] && + !_theResult____h735625[23] && + !_theResult____h735625[22] && + !_theResult____h735625[21] && + !_theResult____h735625[20] && + !_theResult____h735625[19] && + !_theResult____h735625[18] && + !_theResult____h735625[17] && + !_theResult____h735625[16] && + !_theResult____h735625[15] && + !_theResult____h735625[14] && + !_theResult____h735625[13] && + !_theResult____h735625[12] && + !_theResult____h735625[11] && + !_theResult____h735625[10] && + !_theResult____h735625[9] && + !_theResult____h735625[8] && + !_theResult____h735625[7] && + !_theResult____h735625[6] && + !_theResult____h735625[5] && + !_theResult____h735625[4] && + !_theResult____h735625[3] && + !_theResult____h735625[2] && + !_theResult____h735625[1] && + !_theResult____h735625[0] || !_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d13048) ? 11'd0 : - _theResult___fst_exp__h743929 ; - assign _theResult___fst_exp__h743938 = - (!_theResult____h735628[56] && _theResult____h735628[55]) ? + _theResult___fst_exp__h743926 ; + assign _theResult___fst_exp__h743935 = + (!_theResult____h735625[56] && _theResult____h735625[55]) ? 11'd1 : - _theResult___fst_exp__h743935 ; - assign _theResult___fst_exp__h744693 = + _theResult___fst_exp__h743932 ; + assign _theResult___fst_exp__h744690 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard35638_0b0_theResult___fst_exp43864_0_ETC__q224 : + CASE_guard35635_0b0_theResult___fst_exp43861_0_ETC__q224 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13213 ; - assign _theResult___fst_exp__h744696 = - (_theResult___fst_exp__h743864 == 11'd2047) ? - _theResult___fst_exp__h743864 : - _theResult___fst_exp__h744693 ; - assign _theResult___fst_exp__h752649 = + assign _theResult___fst_exp__h744693 = + (_theResult___fst_exp__h743861 == 11'd2047) ? + _theResult___fst_exp__h743861 : + _theResult___fst_exp__h744690 ; + assign _theResult___fst_exp__h752646 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q149[10:0] == 11'd0) ? 11'd1 : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q149[10:0] ; - assign _theResult___fst_exp__h752688 = + assign _theResult___fst_exp__h752685 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q149[10:0] - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d12734 } ; - assign _theResult___fst_exp__h752694 = - (f1_exp__h714899 == 8'd0 && !f1_sfd__h714900[22] && + assign _theResult___fst_exp__h752691 = + (f1_exp__h714896 == 8'd0 && !f1_sfd__h714897[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d12707 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d13098) ? 11'd0 : - _theResult___fst_exp__h752688 ; - assign _theResult___fst_exp__h752697 = - (f1_exp__h714899 == 8'd0) ? - _theResult___fst_exp__h752694 : - _theResult___fst_exp__h752649 ; - assign _theResult___fst_exp__h753477 = + _theResult___fst_exp__h752685 ; + assign _theResult___fst_exp__h752694 = + (f1_exp__h714896 == 8'd0) ? + _theResult___fst_exp__h752691 : + _theResult___fst_exp__h752646 ; + assign _theResult___fst_exp__h753474 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard44707_0b0_theResult___fst_exp52697_0_ETC__q226 : + CASE_guard44704_0b0_theResult___fst_exp52694_0_ETC__q228 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13244 ; - assign _theResult___fst_exp__h753480 = - (_theResult___fst_exp__h752697 == 11'd2047) ? - _theResult___fst_exp__h752697 : - _theResult___fst_exp__h753477 ; - assign _theResult___fst_exp__h753489 = - (f1_exp__h714899 == 8'd0) ? + assign _theResult___fst_exp__h753477 = + (_theResult___fst_exp__h752694 == 11'd2047) ? + _theResult___fst_exp__h752694 : + _theResult___fst_exp__h753474 ; + assign _theResult___fst_exp__h753486 = + (f1_exp__h714896 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12661 ? - _theResult___snd_fst_exp__h735048 : - _theResult___fst_exp__h719214) : + _theResult___snd_fst_exp__h735045 : + _theResult___fst_exp__h719211) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12798 ? - _theResult___snd_fst_exp__h753483 : - _theResult___fst_exp__h719214) ; - assign _theResult___fst_exp__h753492 = - (f1_exp__h714899 == 8'd0 && f1_sfd__h714900 == 23'd0) ? + _theResult___snd_fst_exp__h753480 : + _theResult___fst_exp__h719211) ; + assign _theResult___fst_exp__h753489 = + (f1_exp__h714896 == 8'd0 && f1_sfd__h714897 == 23'd0) ? 11'd0 : - _theResult___fst_exp__h753489 ; - assign _theResult___fst_exp__h758067 = + _theResult___fst_exp__h753486 ; + assign _theResult___fst_exp__h758064 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q29 ; - assign _theResult___fst_exp__h773131 = + assign _theResult___fst_exp__h773128 = 11'd897 - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14234 } ; - assign _theResult___fst_exp__h773137 = - (f2_exp__h753893 == 8'd0 && !f2_sfd__h753894[22] && + assign _theResult___fst_exp__h773134 = + (f2_exp__h753890 == 8'd0 && !f2_sfd__h753891[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d14207 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14236) ? 11'd0 : - _theResult___fst_exp__h773131 ; - assign _theResult___fst_exp__h773140 = - (f2_exp__h753893 == 8'd0) ? - _theResult___fst_exp__h773137 : + _theResult___fst_exp__h773128 ; + assign _theResult___fst_exp__h773137 = + (f2_exp__h753890 == 8'd0) ? + _theResult___fst_exp__h773134 : 11'd897 ; - assign _theResult___fst_exp__h773895 = + assign _theResult___fst_exp__h773892 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard65179_0b0_theResult___fst_exp73140_0_ETC__q196 : + CASE_guard65176_0b0_theResult___fst_exp73137_0_ETC__q196 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14655 ; - assign _theResult___fst_exp__h773898 = - (_theResult___fst_exp__h773140 == 11'd2047) ? - _theResult___fst_exp__h773140 : - _theResult___fst_exp__h773895 ; - assign _theResult___fst_exp__h782717 = - _theResult____h774481[56] ? + assign _theResult___fst_exp__h773895 = + (_theResult___fst_exp__h773137 == 11'd2047) ? + _theResult___fst_exp__h773137 : + _theResult___fst_exp__h773892 ; + assign _theResult___fst_exp__h782714 = + _theResult____h774478[56] ? 11'd2 : - _theResult___fst_exp__h782791 ; - assign _theResult___fst_exp__h782782 = + _theResult___fst_exp__h782788 ; + assign _theResult___fst_exp__h782779 = 11'd0 - { 5'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d14531 } ; - assign _theResult___fst_exp__h782788 = - (!_theResult____h774481[56] && !_theResult____h774481[55] && - !_theResult____h774481[54] && - !_theResult____h774481[53] && - !_theResult____h774481[52] && - !_theResult____h774481[51] && - !_theResult____h774481[50] && - !_theResult____h774481[49] && - !_theResult____h774481[48] && - !_theResult____h774481[47] && - !_theResult____h774481[46] && - !_theResult____h774481[45] && - !_theResult____h774481[44] && - !_theResult____h774481[43] && - !_theResult____h774481[42] && - !_theResult____h774481[41] && - !_theResult____h774481[40] && - !_theResult____h774481[39] && - !_theResult____h774481[38] && - !_theResult____h774481[37] && - !_theResult____h774481[36] && - !_theResult____h774481[35] && - !_theResult____h774481[34] && - !_theResult____h774481[33] && - !_theResult____h774481[32] && - !_theResult____h774481[31] && - !_theResult____h774481[30] && - !_theResult____h774481[29] && - !_theResult____h774481[28] && - !_theResult____h774481[27] && - !_theResult____h774481[26] && - !_theResult____h774481[25] && - !_theResult____h774481[24] && - !_theResult____h774481[23] && - !_theResult____h774481[22] && - !_theResult____h774481[21] && - !_theResult____h774481[20] && - !_theResult____h774481[19] && - !_theResult____h774481[18] && - !_theResult____h774481[17] && - !_theResult____h774481[16] && - !_theResult____h774481[15] && - !_theResult____h774481[14] && - !_theResult____h774481[13] && - !_theResult____h774481[12] && - !_theResult____h774481[11] && - !_theResult____h774481[10] && - !_theResult____h774481[9] && - !_theResult____h774481[8] && - !_theResult____h774481[7] && - !_theResult____h774481[6] && - !_theResult____h774481[5] && - !_theResult____h774481[4] && - !_theResult____h774481[3] && - !_theResult____h774481[2] && - !_theResult____h774481[1] && - !_theResult____h774481[0] || + assign _theResult___fst_exp__h782785 = + (!_theResult____h774478[56] && !_theResult____h774478[55] && + !_theResult____h774478[54] && + !_theResult____h774478[53] && + !_theResult____h774478[52] && + !_theResult____h774478[51] && + !_theResult____h774478[50] && + !_theResult____h774478[49] && + !_theResult____h774478[48] && + !_theResult____h774478[47] && + !_theResult____h774478[46] && + !_theResult____h774478[45] && + !_theResult____h774478[44] && + !_theResult____h774478[43] && + !_theResult____h774478[42] && + !_theResult____h774478[41] && + !_theResult____h774478[40] && + !_theResult____h774478[39] && + !_theResult____h774478[38] && + !_theResult____h774478[37] && + !_theResult____h774478[36] && + !_theResult____h774478[35] && + !_theResult____h774478[34] && + !_theResult____h774478[33] && + !_theResult____h774478[32] && + !_theResult____h774478[31] && + !_theResult____h774478[30] && + !_theResult____h774478[29] && + !_theResult____h774478[28] && + !_theResult____h774478[27] && + !_theResult____h774478[26] && + !_theResult____h774478[25] && + !_theResult____h774478[24] && + !_theResult____h774478[23] && + !_theResult____h774478[22] && + !_theResult____h774478[21] && + !_theResult____h774478[20] && + !_theResult____h774478[19] && + !_theResult____h774478[18] && + !_theResult____h774478[17] && + !_theResult____h774478[16] && + !_theResult____h774478[15] && + !_theResult____h774478[14] && + !_theResult____h774478[13] && + !_theResult____h774478[12] && + !_theResult____h774478[11] && + !_theResult____h774478[10] && + !_theResult____h774478[9] && + !_theResult____h774478[8] && + !_theResult____h774478[7] && + !_theResult____h774478[6] && + !_theResult____h774478[5] && + !_theResult____h774478[4] && + !_theResult____h774478[3] && + !_theResult____h774478[2] && + !_theResult____h774478[1] && + !_theResult____h774478[0] || !_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d14533) ? 11'd0 : - _theResult___fst_exp__h782782 ; - assign _theResult___fst_exp__h782791 = - (!_theResult____h774481[56] && _theResult____h774481[55]) ? + _theResult___fst_exp__h782779 ; + assign _theResult___fst_exp__h782788 = + (!_theResult____h774478[56] && _theResult____h774478[55]) ? 11'd1 : - _theResult___fst_exp__h782788 ; - assign _theResult___fst_exp__h783546 = + _theResult___fst_exp__h782785 ; + assign _theResult___fst_exp__h783543 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard74491_0b0_theResult___fst_exp82717_0_ETC__q200 : + CASE_guard74488_0b0_theResult___fst_exp82714_0_ETC__q198 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14693 ; - assign _theResult___fst_exp__h783549 = - (_theResult___fst_exp__h782717 == 11'd2047) ? - _theResult___fst_exp__h782717 : - _theResult___fst_exp__h783546 ; - assign _theResult___fst_exp__h791502 = + assign _theResult___fst_exp__h783546 = + (_theResult___fst_exp__h782714 == 11'd2047) ? + _theResult___fst_exp__h782714 : + _theResult___fst_exp__h783543 ; + assign _theResult___fst_exp__h791499 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q189[10:0] == 11'd0) ? 11'd1 : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q189[10:0] ; - assign _theResult___fst_exp__h791541 = + assign _theResult___fst_exp__h791538 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q189[10:0] - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14234 } ; - assign _theResult___fst_exp__h791547 = - (f2_exp__h753893 == 8'd0 && !f2_sfd__h753894[22] && + assign _theResult___fst_exp__h791544 = + (f2_exp__h753890 == 8'd0 && !f2_sfd__h753891[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d14207 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d14583) ? 11'd0 : - _theResult___fst_exp__h791541 ; - assign _theResult___fst_exp__h791550 = - (f2_exp__h753893 == 8'd0) ? - _theResult___fst_exp__h791547 : - _theResult___fst_exp__h791502 ; - assign _theResult___fst_exp__h792330 = + _theResult___fst_exp__h791538 ; + assign _theResult___fst_exp__h791547 = + (f2_exp__h753890 == 8'd0) ? + _theResult___fst_exp__h791544 : + _theResult___fst_exp__h791499 ; + assign _theResult___fst_exp__h792327 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard83560_0b0_theResult___fst_exp91550_0_ETC__q198 : + CASE_guard83557_0b0_theResult___fst_exp91547_0_ETC__q200 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14724 ; - assign _theResult___fst_exp__h792333 = - (_theResult___fst_exp__h791550 == 11'd2047) ? - _theResult___fst_exp__h791550 : - _theResult___fst_exp__h792330 ; - assign _theResult___fst_exp__h792342 = - (f2_exp__h753893 == 8'd0) ? + assign _theResult___fst_exp__h792330 = + (_theResult___fst_exp__h791547 == 11'd2047) ? + _theResult___fst_exp__h791547 : + _theResult___fst_exp__h792327 ; + assign _theResult___fst_exp__h792339 = + (f2_exp__h753890 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14161 ? - _theResult___snd_fst_exp__h773901 : - _theResult___fst_exp__h758067) : + _theResult___snd_fst_exp__h773898 : + _theResult___fst_exp__h758064) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14283 ? - _theResult___snd_fst_exp__h792336 : - _theResult___fst_exp__h758067) ; - assign _theResult___fst_exp__h792345 = - (f2_exp__h753893 == 8'd0 && f2_sfd__h753894 == 23'd0) ? + _theResult___snd_fst_exp__h792333 : + _theResult___fst_exp__h758064) ; + assign _theResult___fst_exp__h792342 = + (f2_exp__h753890 == 8'd0 && f2_sfd__h753891 == 23'd0) ? 11'd0 : - _theResult___fst_exp__h792342 ; - assign _theResult___fst_exp__h797371 = + _theResult___fst_exp__h792339 ; + assign _theResult___fst_exp__h797368 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q31 ; - assign _theResult___fst_exp__h812435 = + assign _theResult___fst_exp__h812432 = 11'd897 - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13464 } ; - assign _theResult___fst_exp__h812441 = - (f3_exp__h793197 == 8'd0 && !f3_sfd__h793198[22] && + assign _theResult___fst_exp__h812438 = + (f3_exp__h793194 == 8'd0 && !f3_sfd__h793195[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d13437 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d13466) ? 11'd0 : - _theResult___fst_exp__h812435 ; - assign _theResult___fst_exp__h812444 = - (f3_exp__h793197 == 8'd0) ? - _theResult___fst_exp__h812441 : + _theResult___fst_exp__h812432 ; + assign _theResult___fst_exp__h812441 = + (f3_exp__h793194 == 8'd0) ? + _theResult___fst_exp__h812438 : 11'd897 ; - assign _theResult___fst_exp__h813199 = + assign _theResult___fst_exp__h813196 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard04483_0b0_theResult___fst_exp12444_0_ETC__q173 : + CASE_guard04480_0b0_theResult___fst_exp12441_0_ETC__q173 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13885 ; - assign _theResult___fst_exp__h813202 = - (_theResult___fst_exp__h812444 == 11'd2047) ? - _theResult___fst_exp__h812444 : - _theResult___fst_exp__h813199 ; - assign _theResult___fst_exp__h822021 = - _theResult____h813785[56] ? + assign _theResult___fst_exp__h813199 = + (_theResult___fst_exp__h812441 == 11'd2047) ? + _theResult___fst_exp__h812441 : + _theResult___fst_exp__h813196 ; + assign _theResult___fst_exp__h822018 = + _theResult____h813782[56] ? 11'd2 : - _theResult___fst_exp__h822095 ; - assign _theResult___fst_exp__h822086 = + _theResult___fst_exp__h822092 ; + assign _theResult___fst_exp__h822083 = 11'd0 - { 5'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d13761 } ; - assign _theResult___fst_exp__h822092 = - (!_theResult____h813785[56] && !_theResult____h813785[55] && - !_theResult____h813785[54] && - !_theResult____h813785[53] && - !_theResult____h813785[52] && - !_theResult____h813785[51] && - !_theResult____h813785[50] && - !_theResult____h813785[49] && - !_theResult____h813785[48] && - !_theResult____h813785[47] && - !_theResult____h813785[46] && - !_theResult____h813785[45] && - !_theResult____h813785[44] && - !_theResult____h813785[43] && - !_theResult____h813785[42] && - !_theResult____h813785[41] && - !_theResult____h813785[40] && - !_theResult____h813785[39] && - !_theResult____h813785[38] && - !_theResult____h813785[37] && - !_theResult____h813785[36] && - !_theResult____h813785[35] && - !_theResult____h813785[34] && - !_theResult____h813785[33] && - !_theResult____h813785[32] && - !_theResult____h813785[31] && - !_theResult____h813785[30] && - !_theResult____h813785[29] && - !_theResult____h813785[28] && - !_theResult____h813785[27] && - !_theResult____h813785[26] && - !_theResult____h813785[25] && - !_theResult____h813785[24] && - !_theResult____h813785[23] && - !_theResult____h813785[22] && - !_theResult____h813785[21] && - !_theResult____h813785[20] && - !_theResult____h813785[19] && - !_theResult____h813785[18] && - !_theResult____h813785[17] && - !_theResult____h813785[16] && - !_theResult____h813785[15] && - !_theResult____h813785[14] && - !_theResult____h813785[13] && - !_theResult____h813785[12] && - !_theResult____h813785[11] && - !_theResult____h813785[10] && - !_theResult____h813785[9] && - !_theResult____h813785[8] && - !_theResult____h813785[7] && - !_theResult____h813785[6] && - !_theResult____h813785[5] && - !_theResult____h813785[4] && - !_theResult____h813785[3] && - !_theResult____h813785[2] && - !_theResult____h813785[1] && - !_theResult____h813785[0] || + assign _theResult___fst_exp__h822089 = + (!_theResult____h813782[56] && !_theResult____h813782[55] && + !_theResult____h813782[54] && + !_theResult____h813782[53] && + !_theResult____h813782[52] && + !_theResult____h813782[51] && + !_theResult____h813782[50] && + !_theResult____h813782[49] && + !_theResult____h813782[48] && + !_theResult____h813782[47] && + !_theResult____h813782[46] && + !_theResult____h813782[45] && + !_theResult____h813782[44] && + !_theResult____h813782[43] && + !_theResult____h813782[42] && + !_theResult____h813782[41] && + !_theResult____h813782[40] && + !_theResult____h813782[39] && + !_theResult____h813782[38] && + !_theResult____h813782[37] && + !_theResult____h813782[36] && + !_theResult____h813782[35] && + !_theResult____h813782[34] && + !_theResult____h813782[33] && + !_theResult____h813782[32] && + !_theResult____h813782[31] && + !_theResult____h813782[30] && + !_theResult____h813782[29] && + !_theResult____h813782[28] && + !_theResult____h813782[27] && + !_theResult____h813782[26] && + !_theResult____h813782[25] && + !_theResult____h813782[24] && + !_theResult____h813782[23] && + !_theResult____h813782[22] && + !_theResult____h813782[21] && + !_theResult____h813782[20] && + !_theResult____h813782[19] && + !_theResult____h813782[18] && + !_theResult____h813782[17] && + !_theResult____h813782[16] && + !_theResult____h813782[15] && + !_theResult____h813782[14] && + !_theResult____h813782[13] && + !_theResult____h813782[12] && + !_theResult____h813782[11] && + !_theResult____h813782[10] && + !_theResult____h813782[9] && + !_theResult____h813782[8] && + !_theResult____h813782[7] && + !_theResult____h813782[6] && + !_theResult____h813782[5] && + !_theResult____h813782[4] && + !_theResult____h813782[3] && + !_theResult____h813782[2] && + !_theResult____h813782[1] && + !_theResult____h813782[0] || !_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d13763) ? 11'd0 : - _theResult___fst_exp__h822086 ; - assign _theResult___fst_exp__h822095 = - (!_theResult____h813785[56] && _theResult____h813785[55]) ? + _theResult___fst_exp__h822083 ; + assign _theResult___fst_exp__h822092 = + (!_theResult____h813782[56] && _theResult____h813782[55]) ? 11'd1 : - _theResult___fst_exp__h822092 ; - assign _theResult___fst_exp__h822850 = + _theResult___fst_exp__h822089 ; + assign _theResult___fst_exp__h822847 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard13795_0b0_theResult___fst_exp22021_0_ETC__q202 : + CASE_guard13792_0b0_theResult___fst_exp22018_0_ETC__q204 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13923 ; - assign _theResult___fst_exp__h822853 = - (_theResult___fst_exp__h822021 == 11'd2047) ? - _theResult___fst_exp__h822021 : - _theResult___fst_exp__h822850 ; - assign _theResult___fst_exp__h830806 = + assign _theResult___fst_exp__h822850 = + (_theResult___fst_exp__h822018 == 11'd2047) ? + _theResult___fst_exp__h822018 : + _theResult___fst_exp__h822847 ; + assign _theResult___fst_exp__h830803 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q166[10:0] == 11'd0) ? 11'd1 : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q166[10:0] ; - assign _theResult___fst_exp__h830845 = + assign _theResult___fst_exp__h830842 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q166[10:0] - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13464 } ; - assign _theResult___fst_exp__h830851 = - (f3_exp__h793197 == 8'd0 && !f3_sfd__h793198[22] && + assign _theResult___fst_exp__h830848 = + (f3_exp__h793194 == 8'd0 && !f3_sfd__h793195[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d13437 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d13813) ? 11'd0 : - _theResult___fst_exp__h830845 ; - assign _theResult___fst_exp__h830854 = - (f3_exp__h793197 == 8'd0) ? - _theResult___fst_exp__h830851 : - _theResult___fst_exp__h830806 ; - assign _theResult___fst_exp__h831634 = + _theResult___fst_exp__h830842 ; + assign _theResult___fst_exp__h830851 = + (f3_exp__h793194 == 8'd0) ? + _theResult___fst_exp__h830848 : + _theResult___fst_exp__h830803 ; + assign _theResult___fst_exp__h831631 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard22864_0b0_theResult___fst_exp30854_0_ETC__q204 : + CASE_guard22861_0b0_theResult___fst_exp30851_0_ETC__q202 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13954 ; - assign _theResult___fst_exp__h831637 = - (_theResult___fst_exp__h830854 == 11'd2047) ? - _theResult___fst_exp__h830854 : - _theResult___fst_exp__h831634 ; - assign _theResult___fst_exp__h831646 = - (f3_exp__h793197 == 8'd0) ? + assign _theResult___fst_exp__h831634 = + (_theResult___fst_exp__h830851 == 11'd2047) ? + _theResult___fst_exp__h830851 : + _theResult___fst_exp__h831631 ; + assign _theResult___fst_exp__h831643 = + (f3_exp__h793194 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13391 ? - _theResult___snd_fst_exp__h813205 : - _theResult___fst_exp__h797371) : + _theResult___snd_fst_exp__h813202 : + _theResult___fst_exp__h797368) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13513 ? - _theResult___snd_fst_exp__h831640 : - _theResult___fst_exp__h797371) ; - assign _theResult___fst_exp__h831649 = - (f3_exp__h793197 == 8'd0 && f3_sfd__h793198 == 23'd0) ? + _theResult___snd_fst_exp__h831637 : + _theResult___fst_exp__h797368) ; + assign _theResult___fst_exp__h831646 = + (f3_exp__h793194 == 8'd0 && f3_sfd__h793195 == 23'd0) ? 11'd0 : - _theResult___fst_exp__h831646 ; - assign _theResult___fst_sfd__h585163 = - (_theResult___fst_exp__h584565 == 8'd255) ? - sfdin__h584559[56:34] : - _theResult___fst_sfd__h585160 ; - assign _theResult___fst_sfd__h593745 = - (_theResult___fst_exp__h593221 == 8'd255) ? - _theResult___snd__h593172[56:34] : - _theResult___fst_sfd__h593742 ; - assign _theResult___fst_sfd__h602929 = - (_theResult___fst_exp__h602331 == 8'd255) ? - sfdin__h602325[56:34] : - _theResult___fst_sfd__h602926 ; - assign _theResult___fst_sfd__h611565 = - (_theResult___fst_exp__h611016 == 8'd255) ? - _theResult___snd__h610962[56:34] : - _theResult___fst_sfd__h611562 ; - assign _theResult___fst_sfd__h611574 = + _theResult___fst_exp__h831643 ; + assign _theResult___fst_sfd__h585161 = + (_theResult___fst_exp__h584563 == 8'd255) ? + sfdin__h584557[56:34] : + _theResult___fst_sfd__h585158 ; + assign _theResult___fst_sfd__h593743 = + (_theResult___fst_exp__h593219 == 8'd255) ? + _theResult___snd__h593170[56:34] : + _theResult___fst_sfd__h593740 ; + assign _theResult___fst_sfd__h602927 = + (_theResult___fst_exp__h602329 == 8'd255) ? + sfdin__h602323[56:34] : + _theResult___fst_sfd__h602924 ; + assign _theResult___fst_sfd__h611563 = + (_theResult___fst_exp__h611014 == 8'd255) ? + _theResult___snd__h610960[56:34] : + _theResult___fst_sfd__h611560 ; + assign _theResult___fst_sfd__h611572 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8135 ? - _theResult___snd_fst_sfd__h593748 : - _theResult___fst_sfd__h576437) : + _theResult___snd_fst_sfd__h593746 : + _theResult___fst_sfd__h576435) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8675 ? - _theResult___snd_fst_sfd__h611568 : - _theResult___fst_sfd__h576437) ; - assign _theResult___fst_sfd__h611580 = + _theResult___snd_fst_sfd__h611566 : + _theResult___fst_sfd__h576435) ; + assign _theResult___fst_sfd__h611578 = ((coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == @@ -31404,33 +31399,33 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == 52'd0) ? 23'd0 : - _theResult___fst_sfd__h611574 ; - assign _theResult___fst_sfd__h630912 = - (_theResult___fst_exp__h630314 == 8'd255) ? - sfdin__h630308[56:34] : - _theResult___fst_sfd__h630909 ; - assign _theResult___fst_sfd__h639494 = - (_theResult___fst_exp__h638970 == 8'd255) ? - _theResult___snd__h638921[56:34] : - _theResult___fst_sfd__h639491 ; - assign _theResult___fst_sfd__h648678 = - (_theResult___fst_exp__h648080 == 8'd255) ? - sfdin__h648074[56:34] : - _theResult___fst_sfd__h648675 ; - assign _theResult___fst_sfd__h657314 = - (_theResult___fst_exp__h656765 == 8'd255) ? - _theResult___snd__h656711[56:34] : - _theResult___fst_sfd__h657311 ; - assign _theResult___fst_sfd__h657323 = + _theResult___fst_sfd__h611572 ; + assign _theResult___fst_sfd__h630910 = + (_theResult___fst_exp__h630312 == 8'd255) ? + sfdin__h630306[56:34] : + _theResult___fst_sfd__h630907 ; + assign _theResult___fst_sfd__h639492 = + (_theResult___fst_exp__h638968 == 8'd255) ? + _theResult___snd__h638919[56:34] : + _theResult___fst_sfd__h639489 ; + assign _theResult___fst_sfd__h648676 = + (_theResult___fst_exp__h648078 == 8'd255) ? + sfdin__h648072[56:34] : + _theResult___fst_sfd__h648673 ; + assign _theResult___fst_sfd__h657312 = + (_theResult___fst_exp__h656763 == 8'd255) ? + _theResult___snd__h656709[56:34] : + _theResult___fst_sfd__h657309 ; + assign _theResult___fst_sfd__h657321 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9532 ? - _theResult___snd_fst_sfd__h639497 : - _theResult___fst_sfd__h622188) : + _theResult___snd_fst_sfd__h639495 : + _theResult___fst_sfd__h622186) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10072 ? - _theResult___snd_fst_sfd__h657317 : - _theResult___fst_sfd__h622188) ; - assign _theResult___fst_sfd__h657329 = + _theResult___snd_fst_sfd__h657315 : + _theResult___fst_sfd__h622186) ; + assign _theResult___fst_sfd__h657327 = ((coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == @@ -31438,33 +31433,33 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == 52'd0) ? 23'd0 : - _theResult___fst_sfd__h657323 ; - assign _theResult___fst_sfd__h676659 = - (_theResult___fst_exp__h676061 == 8'd255) ? - sfdin__h676055[56:34] : - _theResult___fst_sfd__h676656 ; - assign _theResult___fst_sfd__h685241 = - (_theResult___fst_exp__h684717 == 8'd255) ? - _theResult___snd__h684668[56:34] : - _theResult___fst_sfd__h685238 ; - assign _theResult___fst_sfd__h694425 = - (_theResult___fst_exp__h693827 == 8'd255) ? - sfdin__h693821[56:34] : - _theResult___fst_sfd__h694422 ; - assign _theResult___fst_sfd__h703061 = - (_theResult___fst_exp__h702512 == 8'd255) ? - _theResult___snd__h702458[56:34] : - _theResult___fst_sfd__h703058 ; - assign _theResult___fst_sfd__h703070 = + _theResult___fst_sfd__h657321 ; + assign _theResult___fst_sfd__h676657 = + (_theResult___fst_exp__h676059 == 8'd255) ? + sfdin__h676053[56:34] : + _theResult___fst_sfd__h676654 ; + assign _theResult___fst_sfd__h685239 = + (_theResult___fst_exp__h684715 == 8'd255) ? + _theResult___snd__h684666[56:34] : + _theResult___fst_sfd__h685236 ; + assign _theResult___fst_sfd__h694423 = + (_theResult___fst_exp__h693825 == 8'd255) ? + sfdin__h693819[56:34] : + _theResult___fst_sfd__h694420 ; + assign _theResult___fst_sfd__h703059 = + (_theResult___fst_exp__h702510 == 8'd255) ? + _theResult___snd__h702456[56:34] : + _theResult___fst_sfd__h703056 ; + assign _theResult___fst_sfd__h703068 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10929 ? - _theResult___snd_fst_sfd__h685244 : - _theResult___fst_sfd__h667935) : + _theResult___snd_fst_sfd__h685242 : + _theResult___fst_sfd__h667933) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11469 ? - _theResult___snd_fst_sfd__h703064 : - _theResult___fst_sfd__h667935) ; - assign _theResult___fst_sfd__h703076 = + _theResult___snd_fst_sfd__h703062 : + _theResult___fst_sfd__h667933) ; + assign _theResult___fst_sfd__h703074 = ((coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == @@ -31472,1441 +31467,1441 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == 52'd0) ? 23'd0 : - _theResult___fst_sfd__h703070 ; - assign _theResult___fst_sfd__h719215 = + _theResult___fst_sfd__h703068 ; + assign _theResult___fst_sfd__h719212 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q28 ; - assign _theResult___fst_sfd__h735043 = + assign _theResult___fst_sfd__h735040 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard26326_0b0_theResult___snd34238_BITS__ETC__q228 : + CASE_guard26323_0b0_theResult___snd34235_BITS__ETC__q226 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13270 ; - assign _theResult___fst_sfd__h735046 = - (_theResult___fst_exp__h734287 == 11'd2047) ? - _theResult___snd__h734238[56:5] : - _theResult___fst_sfd__h735043 ; - assign _theResult___fst_sfd__h744694 = + assign _theResult___fst_sfd__h735043 = + (_theResult___fst_exp__h734284 == 11'd2047) ? + _theResult___snd__h734235[56:5] : + _theResult___fst_sfd__h735040 ; + assign _theResult___fst_sfd__h744691 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard35638_0b0_sfdin43858_BITS_56_TO_5_0b_ETC__q230 : + CASE_guard35635_0b0_sfdin43855_BITS_56_TO_5_0b_ETC__q230 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13297 ; - assign _theResult___fst_sfd__h744697 = - (_theResult___fst_exp__h743864 == 11'd2047) ? - sfdin__h743858[56:5] : - _theResult___fst_sfd__h744694 ; - assign _theResult___fst_sfd__h753478 = + assign _theResult___fst_sfd__h744694 = + (_theResult___fst_exp__h743861 == 11'd2047) ? + sfdin__h743855[56:5] : + _theResult___fst_sfd__h744691 ; + assign _theResult___fst_sfd__h753475 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard44707_0b0_theResult___snd52643_BITS__ETC__q232 : + CASE_guard44704_0b0_theResult___snd52640_BITS__ETC__q232 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13316 ; - assign _theResult___fst_sfd__h753481 = - (_theResult___fst_exp__h752697 == 11'd2047) ? - _theResult___snd__h752643[56:5] : - _theResult___fst_sfd__h753478 ; - assign _theResult___fst_sfd__h753490 = - (f1_exp__h714899 == 8'd0) ? + assign _theResult___fst_sfd__h753478 = + (_theResult___fst_exp__h752694 == 11'd2047) ? + _theResult___snd__h752640[56:5] : + _theResult___fst_sfd__h753475 ; + assign _theResult___fst_sfd__h753487 = + (f1_exp__h714896 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12661 ? - _theResult___snd_fst_sfd__h735049 : - _theResult___fst_sfd__h719215) : + _theResult___snd_fst_sfd__h735046 : + _theResult___fst_sfd__h719212) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12798 ? - _theResult___snd_fst_sfd__h753484 : - _theResult___fst_sfd__h719215) ; - assign _theResult___fst_sfd__h753496 = - ((f1_exp__h714899 == 8'd255 || f1_exp__h714899 == 8'd0) && - f1_sfd__h714900 == 23'd0) ? + _theResult___snd_fst_sfd__h753481 : + _theResult___fst_sfd__h719212) ; + assign _theResult___fst_sfd__h753493 = + ((f1_exp__h714896 == 8'd255 || f1_exp__h714896 == 8'd0) && + f1_sfd__h714897 == 23'd0) ? 52'd0 : - _theResult___fst_sfd__h753490 ; - assign _theResult___fst_sfd__h758068 = + _theResult___fst_sfd__h753487 ; + assign _theResult___fst_sfd__h758065 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q30 ; - assign _theResult___fst_sfd__h773896 = + assign _theResult___fst_sfd__h773893 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard65179_0b0_theResult___snd73091_BITS__ETC__q218 : + CASE_guard65176_0b0_theResult___snd73088_BITS__ETC__q218 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14750 ; - assign _theResult___fst_sfd__h773899 = - (_theResult___fst_exp__h773140 == 11'd2047) ? - _theResult___snd__h773091[56:5] : - _theResult___fst_sfd__h773896 ; - assign _theResult___fst_sfd__h783547 = + assign _theResult___fst_sfd__h773896 = + (_theResult___fst_exp__h773137 == 11'd2047) ? + _theResult___snd__h773088[56:5] : + _theResult___fst_sfd__h773893 ; + assign _theResult___fst_sfd__h783544 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard74491_0b0_sfdin82711_BITS_56_TO_5_0b_ETC__q220 : + CASE_guard74488_0b0_sfdin82708_BITS_56_TO_5_0b_ETC__q220 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14776 ; - assign _theResult___fst_sfd__h783550 = - (_theResult___fst_exp__h782717 == 11'd2047) ? - sfdin__h782711[56:5] : - _theResult___fst_sfd__h783547 ; - assign _theResult___fst_sfd__h792331 = + assign _theResult___fst_sfd__h783547 = + (_theResult___fst_exp__h782714 == 11'd2047) ? + sfdin__h782708[56:5] : + _theResult___fst_sfd__h783544 ; + assign _theResult___fst_sfd__h792328 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard83560_0b0_theResult___snd91496_BITS__ETC__q222 : + CASE_guard83557_0b0_theResult___snd91493_BITS__ETC__q222 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14795 ; - assign _theResult___fst_sfd__h792334 = - (_theResult___fst_exp__h791550 == 11'd2047) ? - _theResult___snd__h791496[56:5] : - _theResult___fst_sfd__h792331 ; - assign _theResult___fst_sfd__h792343 = - (f2_exp__h753893 == 8'd0) ? + assign _theResult___fst_sfd__h792331 = + (_theResult___fst_exp__h791547 == 11'd2047) ? + _theResult___snd__h791493[56:5] : + _theResult___fst_sfd__h792328 ; + assign _theResult___fst_sfd__h792340 = + (f2_exp__h753890 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14161 ? - _theResult___snd_fst_sfd__h773902 : - _theResult___fst_sfd__h758068) : + _theResult___snd_fst_sfd__h773899 : + _theResult___fst_sfd__h758065) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14283 ? - _theResult___snd_fst_sfd__h792337 : - _theResult___fst_sfd__h758068) ; - assign _theResult___fst_sfd__h792349 = - ((f2_exp__h753893 == 8'd255 || f2_exp__h753893 == 8'd0) && - f2_sfd__h753894 == 23'd0) ? + _theResult___snd_fst_sfd__h792334 : + _theResult___fst_sfd__h758065) ; + assign _theResult___fst_sfd__h792346 = + ((f2_exp__h753890 == 8'd255 || f2_exp__h753890 == 8'd0) && + f2_sfd__h753891 == 23'd0) ? 52'd0 : - _theResult___fst_sfd__h792343 ; - assign _theResult___fst_sfd__h797372 = + _theResult___fst_sfd__h792340 ; + assign _theResult___fst_sfd__h797369 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q32 ; - assign _theResult___fst_sfd__h813200 = + assign _theResult___fst_sfd__h813197 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard04483_0b0_theResult___snd12395_BITS__ETC__q234 : + CASE_guard04480_0b0_theResult___snd12392_BITS__ETC__q234 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13980 ; - assign _theResult___fst_sfd__h813203 = - (_theResult___fst_exp__h812444 == 11'd2047) ? - _theResult___snd__h812395[56:5] : - _theResult___fst_sfd__h813200 ; - assign _theResult___fst_sfd__h822851 = + assign _theResult___fst_sfd__h813200 = + (_theResult___fst_exp__h812441 == 11'd2047) ? + _theResult___snd__h812392[56:5] : + _theResult___fst_sfd__h813197 ; + assign _theResult___fst_sfd__h822848 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard13795_0b0_sfdin22015_BITS_56_TO_5_0b_ETC__q236 : + CASE_guard13792_0b0_sfdin22012_BITS_56_TO_5_0b_ETC__q236 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14006 ; - assign _theResult___fst_sfd__h822854 = - (_theResult___fst_exp__h822021 == 11'd2047) ? - sfdin__h822015[56:5] : - _theResult___fst_sfd__h822851 ; - assign _theResult___fst_sfd__h831635 = + assign _theResult___fst_sfd__h822851 = + (_theResult___fst_exp__h822018 == 11'd2047) ? + sfdin__h822012[56:5] : + _theResult___fst_sfd__h822848 ; + assign _theResult___fst_sfd__h831632 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard22864_0b0_theResult___snd30800_BITS__ETC__q238 : + CASE_guard22861_0b0_theResult___snd30797_BITS__ETC__q238 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14025 ; - assign _theResult___fst_sfd__h831638 = - (_theResult___fst_exp__h830854 == 11'd2047) ? - _theResult___snd__h830800[56:5] : - _theResult___fst_sfd__h831635 ; - assign _theResult___fst_sfd__h831647 = - (f3_exp__h793197 == 8'd0) ? + assign _theResult___fst_sfd__h831635 = + (_theResult___fst_exp__h830851 == 11'd2047) ? + _theResult___snd__h830797[56:5] : + _theResult___fst_sfd__h831632 ; + assign _theResult___fst_sfd__h831644 = + (f3_exp__h793194 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13391 ? - _theResult___snd_fst_sfd__h813206 : - _theResult___fst_sfd__h797372) : + _theResult___snd_fst_sfd__h813203 : + _theResult___fst_sfd__h797369) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13513 ? - _theResult___snd_fst_sfd__h831641 : - _theResult___fst_sfd__h797372) ; - assign _theResult___fst_sfd__h831653 = - ((f3_exp__h793197 == 8'd255 || f3_exp__h793197 == 8'd0) && - f3_sfd__h793198 == 23'd0) ? + _theResult___snd_fst_sfd__h831638 : + _theResult___fst_sfd__h797369) ; + assign _theResult___fst_sfd__h831650 = + ((f3_exp__h793194 == 8'd255 || f3_exp__h793194 == 8'd0) && + f3_sfd__h793195 == 23'd0) ? 52'd0 : - _theResult___fst_sfd__h831647 ; - assign _theResult___sfd__h585082 = - sfd__h584657[24] ? - ((_theResult___fst_exp__h584565 == 8'd254) ? + _theResult___fst_sfd__h831644 ; + assign _theResult___sfd__h585080 = + sfd__h584655[24] ? + ((_theResult___fst_exp__h584563 == 8'd254) ? 23'd0 : - sfd__h584657[23:1]) : - sfd__h584657[22:0] ; - assign _theResult___sfd__h593664 = - sfd__h593239[24] ? - ((_theResult___fst_exp__h593221 == 8'd254) ? + sfd__h584655[23:1]) : + sfd__h584655[22:0] ; + assign _theResult___sfd__h593662 = + sfd__h593237[24] ? + ((_theResult___fst_exp__h593219 == 8'd254) ? 23'd0 : - sfd__h593239[23:1]) : - sfd__h593239[22:0] ; - assign _theResult___sfd__h602848 = - sfd__h602423[24] ? - ((_theResult___fst_exp__h602331 == 8'd254) ? + sfd__h593237[23:1]) : + sfd__h593237[22:0] ; + assign _theResult___sfd__h602846 = + sfd__h602421[24] ? + ((_theResult___fst_exp__h602329 == 8'd254) ? 23'd0 : - sfd__h602423[23:1]) : - sfd__h602423[22:0] ; - assign _theResult___sfd__h611484 = - sfd__h611035[24] ? - ((_theResult___fst_exp__h611016 == 8'd254) ? + sfd__h602421[23:1]) : + sfd__h602421[22:0] ; + assign _theResult___sfd__h611482 = + sfd__h611033[24] ? + ((_theResult___fst_exp__h611014 == 8'd254) ? 23'd0 : - sfd__h611035[23:1]) : - sfd__h611035[22:0] ; - assign _theResult___sfd__h611586 = + sfd__h611033[23:1]) : + sfd__h611033[22:0] ; + assign _theResult___sfd__h611584 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h568799 : - _theResult___fst_sfd__h611580 ; - assign _theResult___sfd__h630831 = - sfd__h630406[24] ? - ((_theResult___fst_exp__h630314 == 8'd254) ? + _theResult___snd_fst_sfd__h568797 : + _theResult___fst_sfd__h611578 ; + assign _theResult___sfd__h630829 = + sfd__h630404[24] ? + ((_theResult___fst_exp__h630312 == 8'd254) ? 23'd0 : - sfd__h630406[23:1]) : - sfd__h630406[22:0] ; - assign _theResult___sfd__h639413 = - sfd__h638988[24] ? - ((_theResult___fst_exp__h638970 == 8'd254) ? + sfd__h630404[23:1]) : + sfd__h630404[22:0] ; + assign _theResult___sfd__h639411 = + sfd__h638986[24] ? + ((_theResult___fst_exp__h638968 == 8'd254) ? 23'd0 : - sfd__h638988[23:1]) : - sfd__h638988[22:0] ; - assign _theResult___sfd__h648597 = - sfd__h648172[24] ? - ((_theResult___fst_exp__h648080 == 8'd254) ? + sfd__h638986[23:1]) : + sfd__h638986[22:0] ; + assign _theResult___sfd__h648595 = + sfd__h648170[24] ? + ((_theResult___fst_exp__h648078 == 8'd254) ? 23'd0 : - sfd__h648172[23:1]) : - sfd__h648172[22:0] ; - assign _theResult___sfd__h657233 = - sfd__h656784[24] ? - ((_theResult___fst_exp__h656765 == 8'd254) ? + sfd__h648170[23:1]) : + sfd__h648170[22:0] ; + assign _theResult___sfd__h657231 = + sfd__h656782[24] ? + ((_theResult___fst_exp__h656763 == 8'd254) ? 23'd0 : - sfd__h656784[23:1]) : - sfd__h656784[22:0] ; - assign _theResult___sfd__h657335 = + sfd__h656782[23:1]) : + sfd__h656782[22:0] ; + assign _theResult___sfd__h657333 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h614553 : - _theResult___fst_sfd__h657329 ; - assign _theResult___sfd__h676578 = - sfd__h676153[24] ? - ((_theResult___fst_exp__h676061 == 8'd254) ? + _theResult___snd_fst_sfd__h614551 : + _theResult___fst_sfd__h657327 ; + assign _theResult___sfd__h676576 = + sfd__h676151[24] ? + ((_theResult___fst_exp__h676059 == 8'd254) ? 23'd0 : - sfd__h676153[23:1]) : - sfd__h676153[22:0] ; - assign _theResult___sfd__h685160 = - sfd__h684735[24] ? - ((_theResult___fst_exp__h684717 == 8'd254) ? + sfd__h676151[23:1]) : + sfd__h676151[22:0] ; + assign _theResult___sfd__h685158 = + sfd__h684733[24] ? + ((_theResult___fst_exp__h684715 == 8'd254) ? 23'd0 : - sfd__h684735[23:1]) : - sfd__h684735[22:0] ; - assign _theResult___sfd__h694344 = - sfd__h693919[24] ? - ((_theResult___fst_exp__h693827 == 8'd254) ? + sfd__h684733[23:1]) : + sfd__h684733[22:0] ; + assign _theResult___sfd__h694342 = + sfd__h693917[24] ? + ((_theResult___fst_exp__h693825 == 8'd254) ? 23'd0 : - sfd__h693919[23:1]) : - sfd__h693919[22:0] ; - assign _theResult___sfd__h702980 = - sfd__h702531[24] ? - ((_theResult___fst_exp__h702512 == 8'd254) ? + sfd__h693917[23:1]) : + sfd__h693917[22:0] ; + assign _theResult___sfd__h702978 = + sfd__h702529[24] ? + ((_theResult___fst_exp__h702510 == 8'd254) ? 23'd0 : - sfd__h702531[23:1]) : - sfd__h702531[22:0] ; - assign _theResult___sfd__h703082 = + sfd__h702529[23:1]) : + sfd__h702529[22:0] ; + assign _theResult___sfd__h703080 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h660300 : - _theResult___fst_sfd__h703076 ; - assign _theResult___sfd__h734943 = - sfd__h734305[53] ? - ((_theResult___fst_exp__h734287 == 11'd2046) ? + _theResult___snd_fst_sfd__h660298 : + _theResult___fst_sfd__h703074 ; + assign _theResult___sfd__h734940 = + sfd__h734302[53] ? + ((_theResult___fst_exp__h734284 == 11'd2046) ? 52'd0 : - sfd__h734305[52:1]) : - sfd__h734305[51:0] ; - assign _theResult___sfd__h744594 = - sfd__h743956[53] ? - ((_theResult___fst_exp__h743864 == 11'd2046) ? + sfd__h734302[52:1]) : + sfd__h734302[51:0] ; + assign _theResult___sfd__h744591 = + sfd__h743953[53] ? + ((_theResult___fst_exp__h743861 == 11'd2046) ? 52'd0 : - sfd__h743956[52:1]) : - sfd__h743956[51:0] ; - assign _theResult___sfd__h753378 = - sfd__h752716[53] ? - ((_theResult___fst_exp__h752697 == 11'd2046) ? + sfd__h743953[52:1]) : + sfd__h743953[51:0] ; + assign _theResult___sfd__h753375 = + sfd__h752713[53] ? + ((_theResult___fst_exp__h752694 == 11'd2046) ? 52'd0 : - sfd__h752716[52:1]) : - sfd__h752716[51:0] ; - assign _theResult___sfd__h773796 = - sfd__h773158[53] ? - ((_theResult___fst_exp__h773140 == 11'd2046) ? + sfd__h752713[52:1]) : + sfd__h752713[51:0] ; + assign _theResult___sfd__h773793 = + sfd__h773155[53] ? + ((_theResult___fst_exp__h773137 == 11'd2046) ? 52'd0 : - sfd__h773158[52:1]) : - sfd__h773158[51:0] ; - assign _theResult___sfd__h783447 = - sfd__h782809[53] ? - ((_theResult___fst_exp__h782717 == 11'd2046) ? + sfd__h773155[52:1]) : + sfd__h773155[51:0] ; + assign _theResult___sfd__h783444 = + sfd__h782806[53] ? + ((_theResult___fst_exp__h782714 == 11'd2046) ? 52'd0 : - sfd__h782809[52:1]) : - sfd__h782809[51:0] ; - assign _theResult___sfd__h792231 = - sfd__h791569[53] ? - ((_theResult___fst_exp__h791550 == 11'd2046) ? + sfd__h782806[52:1]) : + sfd__h782806[51:0] ; + assign _theResult___sfd__h792228 = + sfd__h791566[53] ? + ((_theResult___fst_exp__h791547 == 11'd2046) ? 52'd0 : - sfd__h791569[52:1]) : - sfd__h791569[51:0] ; - assign _theResult___sfd__h813100 = - sfd__h812462[53] ? - ((_theResult___fst_exp__h812444 == 11'd2046) ? + sfd__h791566[52:1]) : + sfd__h791566[51:0] ; + assign _theResult___sfd__h813097 = + sfd__h812459[53] ? + ((_theResult___fst_exp__h812441 == 11'd2046) ? 52'd0 : - sfd__h812462[52:1]) : - sfd__h812462[51:0] ; - assign _theResult___sfd__h822751 = - sfd__h822113[53] ? - ((_theResult___fst_exp__h822021 == 11'd2046) ? + sfd__h812459[52:1]) : + sfd__h812459[51:0] ; + assign _theResult___sfd__h822748 = + sfd__h822110[53] ? + ((_theResult___fst_exp__h822018 == 11'd2046) ? 52'd0 : - sfd__h822113[52:1]) : - sfd__h822113[51:0] ; - assign _theResult___sfd__h831535 = - sfd__h830873[53] ? - ((_theResult___fst_exp__h830854 == 11'd2046) ? + sfd__h822110[52:1]) : + sfd__h822110[51:0] ; + assign _theResult___sfd__h831532 = + sfd__h830870[53] ? + ((_theResult___fst_exp__h830851 == 11'd2046) ? 52'd0 : - sfd__h830873[52:1]) : - sfd__h830873[51:0] ; - assign _theResult___snd__h584576 = { _theResult____h576454[55:0], 1'd0 } ; - assign _theResult___snd__h584587 = - (!_theResult____h576454[56] && _theResult____h576454[55]) ? - _theResult___snd__h584589 : - _theResult___snd__h584599 ; - assign _theResult___snd__h584589 = { _theResult____h576454[54:0], 2'd0 } ; - assign _theResult___snd__h584599 = - (!_theResult____h576454[56] && !_theResult____h576454[55] && - !_theResult____h576454[54] && - !_theResult____h576454[53] && - !_theResult____h576454[52] && - !_theResult____h576454[51] && - !_theResult____h576454[50] && - !_theResult____h576454[49] && - !_theResult____h576454[48] && - !_theResult____h576454[47] && - !_theResult____h576454[46] && - !_theResult____h576454[45] && - !_theResult____h576454[44] && - !_theResult____h576454[43] && - !_theResult____h576454[42] && - !_theResult____h576454[41] && - !_theResult____h576454[40] && - !_theResult____h576454[39] && - !_theResult____h576454[38] && - !_theResult____h576454[37] && - !_theResult____h576454[36] && - !_theResult____h576454[35] && - !_theResult____h576454[34] && - !_theResult____h576454[33] && - !_theResult____h576454[32] && - !_theResult____h576454[31] && - !_theResult____h576454[30] && - !_theResult____h576454[29] && - !_theResult____h576454[28] && - !_theResult____h576454[27] && - !_theResult____h576454[26] && - !_theResult____h576454[25] && - !_theResult____h576454[24] && - !_theResult____h576454[23] && - !_theResult____h576454[22] && - !_theResult____h576454[21] && - !_theResult____h576454[20] && - !_theResult____h576454[19] && - !_theResult____h576454[18] && - !_theResult____h576454[17] && - !_theResult____h576454[16] && - !_theResult____h576454[15] && - !_theResult____h576454[14] && - !_theResult____h576454[13] && - !_theResult____h576454[12] && - !_theResult____h576454[11] && - !_theResult____h576454[10] && - !_theResult____h576454[9] && - !_theResult____h576454[8] && - !_theResult____h576454[7] && - !_theResult____h576454[6] && - !_theResult____h576454[5] && - !_theResult____h576454[4] && - !_theResult____h576454[3] && - !_theResult____h576454[2] && - !_theResult____h576454[1] && - !_theResult____h576454[0]) ? - _theResult____h576454 : - _theResult___snd__h584605 ; - assign _theResult___snd__h584605 = + sfd__h830870[52:1]) : + sfd__h830870[51:0] ; + assign _theResult___snd__h584574 = { _theResult____h576452[55:0], 1'd0 } ; + assign _theResult___snd__h584585 = + (!_theResult____h576452[56] && _theResult____h576452[55]) ? + _theResult___snd__h584587 : + _theResult___snd__h584597 ; + assign _theResult___snd__h584587 = { _theResult____h576452[54:0], 2'd0 } ; + assign _theResult___snd__h584597 = + (!_theResult____h576452[56] && !_theResult____h576452[55] && + !_theResult____h576452[54] && + !_theResult____h576452[53] && + !_theResult____h576452[52] && + !_theResult____h576452[51] && + !_theResult____h576452[50] && + !_theResult____h576452[49] && + !_theResult____h576452[48] && + !_theResult____h576452[47] && + !_theResult____h576452[46] && + !_theResult____h576452[45] && + !_theResult____h576452[44] && + !_theResult____h576452[43] && + !_theResult____h576452[42] && + !_theResult____h576452[41] && + !_theResult____h576452[40] && + !_theResult____h576452[39] && + !_theResult____h576452[38] && + !_theResult____h576452[37] && + !_theResult____h576452[36] && + !_theResult____h576452[35] && + !_theResult____h576452[34] && + !_theResult____h576452[33] && + !_theResult____h576452[32] && + !_theResult____h576452[31] && + !_theResult____h576452[30] && + !_theResult____h576452[29] && + !_theResult____h576452[28] && + !_theResult____h576452[27] && + !_theResult____h576452[26] && + !_theResult____h576452[25] && + !_theResult____h576452[24] && + !_theResult____h576452[23] && + !_theResult____h576452[22] && + !_theResult____h576452[21] && + !_theResult____h576452[20] && + !_theResult____h576452[19] && + !_theResult____h576452[18] && + !_theResult____h576452[17] && + !_theResult____h576452[16] && + !_theResult____h576452[15] && + !_theResult____h576452[14] && + !_theResult____h576452[13] && + !_theResult____h576452[12] && + !_theResult____h576452[11] && + !_theResult____h576452[10] && + !_theResult____h576452[9] && + !_theResult____h576452[8] && + !_theResult____h576452[7] && + !_theResult____h576452[6] && + !_theResult____h576452[5] && + !_theResult____h576452[4] && + !_theResult____h576452[3] && + !_theResult____h576452[2] && + !_theResult____h576452[1] && + !_theResult____h576452[0]) ? + _theResult____h576452 : + _theResult___snd__h584603 ; + assign _theResult___snd__h584603 = { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q40[54:0], 2'd0 } ; - assign _theResult___snd__h584628 = - _theResult____h576454 << + assign _theResult___snd__h584626 = + _theResult____h576452 << IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d8370 ; - assign _theResult___snd__h593172 = + assign _theResult___snd__h593170 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___snd__h593181 : - _theResult___snd__h593174 ; - assign _theResult___snd__h593174 = + _theResult___snd__h593179 : + _theResult___snd__h593172 ; + assign _theResult___snd__h593172 = { coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5], 5'd0 } ; - assign _theResult___snd__h593181 = + assign _theResult___snd__h593179 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d8546) ? - sfd__h568849 : - _theResult___snd__h593187 ; - assign _theResult___snd__h593187 = + sfd__h568847 : + _theResult___snd__h593185 ; + assign _theResult___snd__h593185 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q42[54:0], 2'd0 } ; - assign _theResult___snd__h593210 = - sfd__h568849 << + assign _theResult___snd__h593208 = + sfd__h568847 << IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d8601 ; - assign _theResult___snd__h602342 = { _theResult____h594093[55:0], 1'd0 } ; - assign _theResult___snd__h602353 = - (!_theResult____h594093[56] && _theResult____h594093[55]) ? - _theResult___snd__h602355 : - _theResult___snd__h602365 ; - assign _theResult___snd__h602355 = { _theResult____h594093[54:0], 2'd0 } ; - assign _theResult___snd__h602365 = - (!_theResult____h594093[56] && !_theResult____h594093[55] && - !_theResult____h594093[54] && - !_theResult____h594093[53] && - !_theResult____h594093[52] && - !_theResult____h594093[51] && - !_theResult____h594093[50] && - !_theResult____h594093[49] && - !_theResult____h594093[48] && - !_theResult____h594093[47] && - !_theResult____h594093[46] && - !_theResult____h594093[45] && - !_theResult____h594093[44] && - !_theResult____h594093[43] && - !_theResult____h594093[42] && - !_theResult____h594093[41] && - !_theResult____h594093[40] && - !_theResult____h594093[39] && - !_theResult____h594093[38] && - !_theResult____h594093[37] && - !_theResult____h594093[36] && - !_theResult____h594093[35] && - !_theResult____h594093[34] && - !_theResult____h594093[33] && - !_theResult____h594093[32] && - !_theResult____h594093[31] && - !_theResult____h594093[30] && - !_theResult____h594093[29] && - !_theResult____h594093[28] && - !_theResult____h594093[27] && - !_theResult____h594093[26] && - !_theResult____h594093[25] && - !_theResult____h594093[24] && - !_theResult____h594093[23] && - !_theResult____h594093[22] && - !_theResult____h594093[21] && - !_theResult____h594093[20] && - !_theResult____h594093[19] && - !_theResult____h594093[18] && - !_theResult____h594093[17] && - !_theResult____h594093[16] && - !_theResult____h594093[15] && - !_theResult____h594093[14] && - !_theResult____h594093[13] && - !_theResult____h594093[12] && - !_theResult____h594093[11] && - !_theResult____h594093[10] && - !_theResult____h594093[9] && - !_theResult____h594093[8] && - !_theResult____h594093[7] && - !_theResult____h594093[6] && - !_theResult____h594093[5] && - !_theResult____h594093[4] && - !_theResult____h594093[3] && - !_theResult____h594093[2] && - !_theResult____h594093[1] && - !_theResult____h594093[0]) ? - _theResult____h594093 : - _theResult___snd__h602371 ; - assign _theResult___snd__h602371 = + assign _theResult___snd__h602340 = { _theResult____h594091[55:0], 1'd0 } ; + assign _theResult___snd__h602351 = + (!_theResult____h594091[56] && _theResult____h594091[55]) ? + _theResult___snd__h602353 : + _theResult___snd__h602363 ; + assign _theResult___snd__h602353 = { _theResult____h594091[54:0], 2'd0 } ; + assign _theResult___snd__h602363 = + (!_theResult____h594091[56] && !_theResult____h594091[55] && + !_theResult____h594091[54] && + !_theResult____h594091[53] && + !_theResult____h594091[52] && + !_theResult____h594091[51] && + !_theResult____h594091[50] && + !_theResult____h594091[49] && + !_theResult____h594091[48] && + !_theResult____h594091[47] && + !_theResult____h594091[46] && + !_theResult____h594091[45] && + !_theResult____h594091[44] && + !_theResult____h594091[43] && + !_theResult____h594091[42] && + !_theResult____h594091[41] && + !_theResult____h594091[40] && + !_theResult____h594091[39] && + !_theResult____h594091[38] && + !_theResult____h594091[37] && + !_theResult____h594091[36] && + !_theResult____h594091[35] && + !_theResult____h594091[34] && + !_theResult____h594091[33] && + !_theResult____h594091[32] && + !_theResult____h594091[31] && + !_theResult____h594091[30] && + !_theResult____h594091[29] && + !_theResult____h594091[28] && + !_theResult____h594091[27] && + !_theResult____h594091[26] && + !_theResult____h594091[25] && + !_theResult____h594091[24] && + !_theResult____h594091[23] && + !_theResult____h594091[22] && + !_theResult____h594091[21] && + !_theResult____h594091[20] && + !_theResult____h594091[19] && + !_theResult____h594091[18] && + !_theResult____h594091[17] && + !_theResult____h594091[16] && + !_theResult____h594091[15] && + !_theResult____h594091[14] && + !_theResult____h594091[13] && + !_theResult____h594091[12] && + !_theResult____h594091[11] && + !_theResult____h594091[10] && + !_theResult____h594091[9] && + !_theResult____h594091[8] && + !_theResult____h594091[7] && + !_theResult____h594091[6] && + !_theResult____h594091[5] && + !_theResult____h594091[4] && + !_theResult____h594091[3] && + !_theResult____h594091[2] && + !_theResult____h594091[1] && + !_theResult____h594091[0]) ? + _theResult____h594091 : + _theResult___snd__h602369 ; + assign _theResult___snd__h602369 = { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q50[54:0], 2'd0 } ; - assign _theResult___snd__h602394 = - _theResult____h594093 << + assign _theResult___snd__h602392 = + _theResult____h594091 << IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d8921 ; - assign _theResult___snd__h610962 = + assign _theResult___snd__h610960 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___snd__h610976 : - _theResult___snd__h593174 ; - assign _theResult___snd__h610976 = + _theResult___snd__h610974 : + _theResult___snd__h593172 ; + assign _theResult___snd__h610974 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d8546) ? - sfd__h568849 : - _theResult___snd__h610982 ; - assign _theResult___snd__h610982 = + sfd__h568847 : + _theResult___snd__h610980 ; + assign _theResult___snd__h610980 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q55[54:0], 2'd0 } ; - assign _theResult___snd__h611000 = - sfd__h568849 << + assign _theResult___snd__h610998 = + sfd__h568847 << (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8995[8] ? 9'h0AA : IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8995) ; - assign _theResult___snd__h630325 = { _theResult____h622205[55:0], 1'd0 } ; - assign _theResult___snd__h630336 = - (!_theResult____h622205[56] && _theResult____h622205[55]) ? - _theResult___snd__h630338 : - _theResult___snd__h630348 ; - assign _theResult___snd__h630338 = { _theResult____h622205[54:0], 2'd0 } ; - assign _theResult___snd__h630348 = - (!_theResult____h622205[56] && !_theResult____h622205[55] && - !_theResult____h622205[54] && - !_theResult____h622205[53] && - !_theResult____h622205[52] && - !_theResult____h622205[51] && - !_theResult____h622205[50] && - !_theResult____h622205[49] && - !_theResult____h622205[48] && - !_theResult____h622205[47] && - !_theResult____h622205[46] && - !_theResult____h622205[45] && - !_theResult____h622205[44] && - !_theResult____h622205[43] && - !_theResult____h622205[42] && - !_theResult____h622205[41] && - !_theResult____h622205[40] && - !_theResult____h622205[39] && - !_theResult____h622205[38] && - !_theResult____h622205[37] && - !_theResult____h622205[36] && - !_theResult____h622205[35] && - !_theResult____h622205[34] && - !_theResult____h622205[33] && - !_theResult____h622205[32] && - !_theResult____h622205[31] && - !_theResult____h622205[30] && - !_theResult____h622205[29] && - !_theResult____h622205[28] && - !_theResult____h622205[27] && - !_theResult____h622205[26] && - !_theResult____h622205[25] && - !_theResult____h622205[24] && - !_theResult____h622205[23] && - !_theResult____h622205[22] && - !_theResult____h622205[21] && - !_theResult____h622205[20] && - !_theResult____h622205[19] && - !_theResult____h622205[18] && - !_theResult____h622205[17] && - !_theResult____h622205[16] && - !_theResult____h622205[15] && - !_theResult____h622205[14] && - !_theResult____h622205[13] && - !_theResult____h622205[12] && - !_theResult____h622205[11] && - !_theResult____h622205[10] && - !_theResult____h622205[9] && - !_theResult____h622205[8] && - !_theResult____h622205[7] && - !_theResult____h622205[6] && - !_theResult____h622205[5] && - !_theResult____h622205[4] && - !_theResult____h622205[3] && - !_theResult____h622205[2] && - !_theResult____h622205[1] && - !_theResult____h622205[0]) ? - _theResult____h622205 : - _theResult___snd__h630354 ; - assign _theResult___snd__h630354 = + assign _theResult___snd__h630323 = { _theResult____h622203[55:0], 1'd0 } ; + assign _theResult___snd__h630334 = + (!_theResult____h622203[56] && _theResult____h622203[55]) ? + _theResult___snd__h630336 : + _theResult___snd__h630346 ; + assign _theResult___snd__h630336 = { _theResult____h622203[54:0], 2'd0 } ; + assign _theResult___snd__h630346 = + (!_theResult____h622203[56] && !_theResult____h622203[55] && + !_theResult____h622203[54] && + !_theResult____h622203[53] && + !_theResult____h622203[52] && + !_theResult____h622203[51] && + !_theResult____h622203[50] && + !_theResult____h622203[49] && + !_theResult____h622203[48] && + !_theResult____h622203[47] && + !_theResult____h622203[46] && + !_theResult____h622203[45] && + !_theResult____h622203[44] && + !_theResult____h622203[43] && + !_theResult____h622203[42] && + !_theResult____h622203[41] && + !_theResult____h622203[40] && + !_theResult____h622203[39] && + !_theResult____h622203[38] && + !_theResult____h622203[37] && + !_theResult____h622203[36] && + !_theResult____h622203[35] && + !_theResult____h622203[34] && + !_theResult____h622203[33] && + !_theResult____h622203[32] && + !_theResult____h622203[31] && + !_theResult____h622203[30] && + !_theResult____h622203[29] && + !_theResult____h622203[28] && + !_theResult____h622203[27] && + !_theResult____h622203[26] && + !_theResult____h622203[25] && + !_theResult____h622203[24] && + !_theResult____h622203[23] && + !_theResult____h622203[22] && + !_theResult____h622203[21] && + !_theResult____h622203[20] && + !_theResult____h622203[19] && + !_theResult____h622203[18] && + !_theResult____h622203[17] && + !_theResult____h622203[16] && + !_theResult____h622203[15] && + !_theResult____h622203[14] && + !_theResult____h622203[13] && + !_theResult____h622203[12] && + !_theResult____h622203[11] && + !_theResult____h622203[10] && + !_theResult____h622203[9] && + !_theResult____h622203[8] && + !_theResult____h622203[7] && + !_theResult____h622203[6] && + !_theResult____h622203[5] && + !_theResult____h622203[4] && + !_theResult____h622203[3] && + !_theResult____h622203[2] && + !_theResult____h622203[1] && + !_theResult____h622203[0]) ? + _theResult____h622203 : + _theResult___snd__h630352 ; + assign _theResult___snd__h630352 = { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q75[54:0], 2'd0 } ; - assign _theResult___snd__h630377 = - _theResult____h622205 << + assign _theResult___snd__h630375 = + _theResult____h622203 << IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d9767 ; - assign _theResult___snd__h638921 = + assign _theResult___snd__h638919 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___snd__h638930 : - _theResult___snd__h638923 ; - assign _theResult___snd__h638923 = + _theResult___snd__h638928 : + _theResult___snd__h638921 ; + assign _theResult___snd__h638921 = { coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5], 5'd0 } ; - assign _theResult___snd__h638930 = + assign _theResult___snd__h638928 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d9943) ? - sfd__h614603 : - _theResult___snd__h638936 ; - assign _theResult___snd__h638936 = + sfd__h614601 : + _theResult___snd__h638934 ; + assign _theResult___snd__h638934 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q77[54:0], 2'd0 } ; - assign _theResult___snd__h638959 = - sfd__h614603 << + assign _theResult___snd__h638957 = + sfd__h614601 << IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d9998 ; - assign _theResult___snd__h648091 = { _theResult____h639842[55:0], 1'd0 } ; - assign _theResult___snd__h648102 = - (!_theResult____h639842[56] && _theResult____h639842[55]) ? - _theResult___snd__h648104 : - _theResult___snd__h648114 ; - assign _theResult___snd__h648104 = { _theResult____h639842[54:0], 2'd0 } ; - assign _theResult___snd__h648114 = - (!_theResult____h639842[56] && !_theResult____h639842[55] && - !_theResult____h639842[54] && - !_theResult____h639842[53] && - !_theResult____h639842[52] && - !_theResult____h639842[51] && - !_theResult____h639842[50] && - !_theResult____h639842[49] && - !_theResult____h639842[48] && - !_theResult____h639842[47] && - !_theResult____h639842[46] && - !_theResult____h639842[45] && - !_theResult____h639842[44] && - !_theResult____h639842[43] && - !_theResult____h639842[42] && - !_theResult____h639842[41] && - !_theResult____h639842[40] && - !_theResult____h639842[39] && - !_theResult____h639842[38] && - !_theResult____h639842[37] && - !_theResult____h639842[36] && - !_theResult____h639842[35] && - !_theResult____h639842[34] && - !_theResult____h639842[33] && - !_theResult____h639842[32] && - !_theResult____h639842[31] && - !_theResult____h639842[30] && - !_theResult____h639842[29] && - !_theResult____h639842[28] && - !_theResult____h639842[27] && - !_theResult____h639842[26] && - !_theResult____h639842[25] && - !_theResult____h639842[24] && - !_theResult____h639842[23] && - !_theResult____h639842[22] && - !_theResult____h639842[21] && - !_theResult____h639842[20] && - !_theResult____h639842[19] && - !_theResult____h639842[18] && - !_theResult____h639842[17] && - !_theResult____h639842[16] && - !_theResult____h639842[15] && - !_theResult____h639842[14] && - !_theResult____h639842[13] && - !_theResult____h639842[12] && - !_theResult____h639842[11] && - !_theResult____h639842[10] && - !_theResult____h639842[9] && - !_theResult____h639842[8] && - !_theResult____h639842[7] && - !_theResult____h639842[6] && - !_theResult____h639842[5] && - !_theResult____h639842[4] && - !_theResult____h639842[3] && - !_theResult____h639842[2] && - !_theResult____h639842[1] && - !_theResult____h639842[0]) ? - _theResult____h639842 : - _theResult___snd__h648120 ; - assign _theResult___snd__h648120 = + assign _theResult___snd__h648089 = { _theResult____h639840[55:0], 1'd0 } ; + assign _theResult___snd__h648100 = + (!_theResult____h639840[56] && _theResult____h639840[55]) ? + _theResult___snd__h648102 : + _theResult___snd__h648112 ; + assign _theResult___snd__h648102 = { _theResult____h639840[54:0], 2'd0 } ; + assign _theResult___snd__h648112 = + (!_theResult____h639840[56] && !_theResult____h639840[55] && + !_theResult____h639840[54] && + !_theResult____h639840[53] && + !_theResult____h639840[52] && + !_theResult____h639840[51] && + !_theResult____h639840[50] && + !_theResult____h639840[49] && + !_theResult____h639840[48] && + !_theResult____h639840[47] && + !_theResult____h639840[46] && + !_theResult____h639840[45] && + !_theResult____h639840[44] && + !_theResult____h639840[43] && + !_theResult____h639840[42] && + !_theResult____h639840[41] && + !_theResult____h639840[40] && + !_theResult____h639840[39] && + !_theResult____h639840[38] && + !_theResult____h639840[37] && + !_theResult____h639840[36] && + !_theResult____h639840[35] && + !_theResult____h639840[34] && + !_theResult____h639840[33] && + !_theResult____h639840[32] && + !_theResult____h639840[31] && + !_theResult____h639840[30] && + !_theResult____h639840[29] && + !_theResult____h639840[28] && + !_theResult____h639840[27] && + !_theResult____h639840[26] && + !_theResult____h639840[25] && + !_theResult____h639840[24] && + !_theResult____h639840[23] && + !_theResult____h639840[22] && + !_theResult____h639840[21] && + !_theResult____h639840[20] && + !_theResult____h639840[19] && + !_theResult____h639840[18] && + !_theResult____h639840[17] && + !_theResult____h639840[16] && + !_theResult____h639840[15] && + !_theResult____h639840[14] && + !_theResult____h639840[13] && + !_theResult____h639840[12] && + !_theResult____h639840[11] && + !_theResult____h639840[10] && + !_theResult____h639840[9] && + !_theResult____h639840[8] && + !_theResult____h639840[7] && + !_theResult____h639840[6] && + !_theResult____h639840[5] && + !_theResult____h639840[4] && + !_theResult____h639840[3] && + !_theResult____h639840[2] && + !_theResult____h639840[1] && + !_theResult____h639840[0]) ? + _theResult____h639840 : + _theResult___snd__h648118 ; + assign _theResult___snd__h648118 = { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q85[54:0], 2'd0 } ; - assign _theResult___snd__h648143 = - _theResult____h639842 << + assign _theResult___snd__h648141 = + _theResult____h639840 << IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d10318 ; - assign _theResult___snd__h656711 = + assign _theResult___snd__h656709 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___snd__h656725 : - _theResult___snd__h638923 ; - assign _theResult___snd__h656725 = + _theResult___snd__h656723 : + _theResult___snd__h638921 ; + assign _theResult___snd__h656723 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d9943) ? - sfd__h614603 : - _theResult___snd__h656731 ; - assign _theResult___snd__h656731 = + sfd__h614601 : + _theResult___snd__h656729 ; + assign _theResult___snd__h656729 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q90[54:0], 2'd0 } ; - assign _theResult___snd__h656749 = - sfd__h614603 << + assign _theResult___snd__h656747 = + sfd__h614601 << (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d10392[8] ? 9'h0AA : IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d10392) ; - assign _theResult___snd__h676072 = { _theResult____h667952[55:0], 1'd0 } ; - assign _theResult___snd__h676083 = - (!_theResult____h667952[56] && _theResult____h667952[55]) ? - _theResult___snd__h676085 : - _theResult___snd__h676095 ; - assign _theResult___snd__h676085 = { _theResult____h667952[54:0], 2'd0 } ; - assign _theResult___snd__h676095 = - (!_theResult____h667952[56] && !_theResult____h667952[55] && - !_theResult____h667952[54] && - !_theResult____h667952[53] && - !_theResult____h667952[52] && - !_theResult____h667952[51] && - !_theResult____h667952[50] && - !_theResult____h667952[49] && - !_theResult____h667952[48] && - !_theResult____h667952[47] && - !_theResult____h667952[46] && - !_theResult____h667952[45] && - !_theResult____h667952[44] && - !_theResult____h667952[43] && - !_theResult____h667952[42] && - !_theResult____h667952[41] && - !_theResult____h667952[40] && - !_theResult____h667952[39] && - !_theResult____h667952[38] && - !_theResult____h667952[37] && - !_theResult____h667952[36] && - !_theResult____h667952[35] && - !_theResult____h667952[34] && - !_theResult____h667952[33] && - !_theResult____h667952[32] && - !_theResult____h667952[31] && - !_theResult____h667952[30] && - !_theResult____h667952[29] && - !_theResult____h667952[28] && - !_theResult____h667952[27] && - !_theResult____h667952[26] && - !_theResult____h667952[25] && - !_theResult____h667952[24] && - !_theResult____h667952[23] && - !_theResult____h667952[22] && - !_theResult____h667952[21] && - !_theResult____h667952[20] && - !_theResult____h667952[19] && - !_theResult____h667952[18] && - !_theResult____h667952[17] && - !_theResult____h667952[16] && - !_theResult____h667952[15] && - !_theResult____h667952[14] && - !_theResult____h667952[13] && - !_theResult____h667952[12] && - !_theResult____h667952[11] && - !_theResult____h667952[10] && - !_theResult____h667952[9] && - !_theResult____h667952[8] && - !_theResult____h667952[7] && - !_theResult____h667952[6] && - !_theResult____h667952[5] && - !_theResult____h667952[4] && - !_theResult____h667952[3] && - !_theResult____h667952[2] && - !_theResult____h667952[1] && - !_theResult____h667952[0]) ? - _theResult____h667952 : - _theResult___snd__h676101 ; - assign _theResult___snd__h676101 = + assign _theResult___snd__h676070 = { _theResult____h667950[55:0], 1'd0 } ; + assign _theResult___snd__h676081 = + (!_theResult____h667950[56] && _theResult____h667950[55]) ? + _theResult___snd__h676083 : + _theResult___snd__h676093 ; + assign _theResult___snd__h676083 = { _theResult____h667950[54:0], 2'd0 } ; + assign _theResult___snd__h676093 = + (!_theResult____h667950[56] && !_theResult____h667950[55] && + !_theResult____h667950[54] && + !_theResult____h667950[53] && + !_theResult____h667950[52] && + !_theResult____h667950[51] && + !_theResult____h667950[50] && + !_theResult____h667950[49] && + !_theResult____h667950[48] && + !_theResult____h667950[47] && + !_theResult____h667950[46] && + !_theResult____h667950[45] && + !_theResult____h667950[44] && + !_theResult____h667950[43] && + !_theResult____h667950[42] && + !_theResult____h667950[41] && + !_theResult____h667950[40] && + !_theResult____h667950[39] && + !_theResult____h667950[38] && + !_theResult____h667950[37] && + !_theResult____h667950[36] && + !_theResult____h667950[35] && + !_theResult____h667950[34] && + !_theResult____h667950[33] && + !_theResult____h667950[32] && + !_theResult____h667950[31] && + !_theResult____h667950[30] && + !_theResult____h667950[29] && + !_theResult____h667950[28] && + !_theResult____h667950[27] && + !_theResult____h667950[26] && + !_theResult____h667950[25] && + !_theResult____h667950[24] && + !_theResult____h667950[23] && + !_theResult____h667950[22] && + !_theResult____h667950[21] && + !_theResult____h667950[20] && + !_theResult____h667950[19] && + !_theResult____h667950[18] && + !_theResult____h667950[17] && + !_theResult____h667950[16] && + !_theResult____h667950[15] && + !_theResult____h667950[14] && + !_theResult____h667950[13] && + !_theResult____h667950[12] && + !_theResult____h667950[11] && + !_theResult____h667950[10] && + !_theResult____h667950[9] && + !_theResult____h667950[8] && + !_theResult____h667950[7] && + !_theResult____h667950[6] && + !_theResult____h667950[5] && + !_theResult____h667950[4] && + !_theResult____h667950[3] && + !_theResult____h667950[2] && + !_theResult____h667950[1] && + !_theResult____h667950[0]) ? + _theResult____h667950 : + _theResult___snd__h676099 ; + assign _theResult___snd__h676099 = { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q110[54:0], 2'd0 } ; - assign _theResult___snd__h676124 = - _theResult____h667952 << + assign _theResult___snd__h676122 = + _theResult____h667950 << IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d11164 ; - assign _theResult___snd__h684668 = + assign _theResult___snd__h684666 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___snd__h684677 : - _theResult___snd__h684670 ; - assign _theResult___snd__h684670 = + _theResult___snd__h684675 : + _theResult___snd__h684668 ; + assign _theResult___snd__h684668 = { coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5], 5'd0 } ; - assign _theResult___snd__h684677 = + assign _theResult___snd__h684675 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d11340) ? - sfd__h660350 : - _theResult___snd__h684683 ; - assign _theResult___snd__h684683 = + sfd__h660348 : + _theResult___snd__h684681 ; + assign _theResult___snd__h684681 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q112[54:0], 2'd0 } ; - assign _theResult___snd__h684706 = - sfd__h660350 << + assign _theResult___snd__h684704 = + sfd__h660348 << IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d11395 ; - assign _theResult___snd__h693838 = { _theResult____h685589[55:0], 1'd0 } ; - assign _theResult___snd__h693849 = - (!_theResult____h685589[56] && _theResult____h685589[55]) ? - _theResult___snd__h693851 : - _theResult___snd__h693861 ; - assign _theResult___snd__h693851 = { _theResult____h685589[54:0], 2'd0 } ; - assign _theResult___snd__h693861 = - (!_theResult____h685589[56] && !_theResult____h685589[55] && - !_theResult____h685589[54] && - !_theResult____h685589[53] && - !_theResult____h685589[52] && - !_theResult____h685589[51] && - !_theResult____h685589[50] && - !_theResult____h685589[49] && - !_theResult____h685589[48] && - !_theResult____h685589[47] && - !_theResult____h685589[46] && - !_theResult____h685589[45] && - !_theResult____h685589[44] && - !_theResult____h685589[43] && - !_theResult____h685589[42] && - !_theResult____h685589[41] && - !_theResult____h685589[40] && - !_theResult____h685589[39] && - !_theResult____h685589[38] && - !_theResult____h685589[37] && - !_theResult____h685589[36] && - !_theResult____h685589[35] && - !_theResult____h685589[34] && - !_theResult____h685589[33] && - !_theResult____h685589[32] && - !_theResult____h685589[31] && - !_theResult____h685589[30] && - !_theResult____h685589[29] && - !_theResult____h685589[28] && - !_theResult____h685589[27] && - !_theResult____h685589[26] && - !_theResult____h685589[25] && - !_theResult____h685589[24] && - !_theResult____h685589[23] && - !_theResult____h685589[22] && - !_theResult____h685589[21] && - !_theResult____h685589[20] && - !_theResult____h685589[19] && - !_theResult____h685589[18] && - !_theResult____h685589[17] && - !_theResult____h685589[16] && - !_theResult____h685589[15] && - !_theResult____h685589[14] && - !_theResult____h685589[13] && - !_theResult____h685589[12] && - !_theResult____h685589[11] && - !_theResult____h685589[10] && - !_theResult____h685589[9] && - !_theResult____h685589[8] && - !_theResult____h685589[7] && - !_theResult____h685589[6] && - !_theResult____h685589[5] && - !_theResult____h685589[4] && - !_theResult____h685589[3] && - !_theResult____h685589[2] && - !_theResult____h685589[1] && - !_theResult____h685589[0]) ? - _theResult____h685589 : - _theResult___snd__h693867 ; - assign _theResult___snd__h693867 = + assign _theResult___snd__h693836 = { _theResult____h685587[55:0], 1'd0 } ; + assign _theResult___snd__h693847 = + (!_theResult____h685587[56] && _theResult____h685587[55]) ? + _theResult___snd__h693849 : + _theResult___snd__h693859 ; + assign _theResult___snd__h693849 = { _theResult____h685587[54:0], 2'd0 } ; + assign _theResult___snd__h693859 = + (!_theResult____h685587[56] && !_theResult____h685587[55] && + !_theResult____h685587[54] && + !_theResult____h685587[53] && + !_theResult____h685587[52] && + !_theResult____h685587[51] && + !_theResult____h685587[50] && + !_theResult____h685587[49] && + !_theResult____h685587[48] && + !_theResult____h685587[47] && + !_theResult____h685587[46] && + !_theResult____h685587[45] && + !_theResult____h685587[44] && + !_theResult____h685587[43] && + !_theResult____h685587[42] && + !_theResult____h685587[41] && + !_theResult____h685587[40] && + !_theResult____h685587[39] && + !_theResult____h685587[38] && + !_theResult____h685587[37] && + !_theResult____h685587[36] && + !_theResult____h685587[35] && + !_theResult____h685587[34] && + !_theResult____h685587[33] && + !_theResult____h685587[32] && + !_theResult____h685587[31] && + !_theResult____h685587[30] && + !_theResult____h685587[29] && + !_theResult____h685587[28] && + !_theResult____h685587[27] && + !_theResult____h685587[26] && + !_theResult____h685587[25] && + !_theResult____h685587[24] && + !_theResult____h685587[23] && + !_theResult____h685587[22] && + !_theResult____h685587[21] && + !_theResult____h685587[20] && + !_theResult____h685587[19] && + !_theResult____h685587[18] && + !_theResult____h685587[17] && + !_theResult____h685587[16] && + !_theResult____h685587[15] && + !_theResult____h685587[14] && + !_theResult____h685587[13] && + !_theResult____h685587[12] && + !_theResult____h685587[11] && + !_theResult____h685587[10] && + !_theResult____h685587[9] && + !_theResult____h685587[8] && + !_theResult____h685587[7] && + !_theResult____h685587[6] && + !_theResult____h685587[5] && + !_theResult____h685587[4] && + !_theResult____h685587[3] && + !_theResult____h685587[2] && + !_theResult____h685587[1] && + !_theResult____h685587[0]) ? + _theResult____h685587 : + _theResult___snd__h693865 ; + assign _theResult___snd__h693865 = { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q120[54:0], 2'd0 } ; - assign _theResult___snd__h693890 = - _theResult____h685589 << + assign _theResult___snd__h693888 = + _theResult____h685587 << IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d11715 ; - assign _theResult___snd__h702458 = + assign _theResult___snd__h702456 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___snd__h702472 : - _theResult___snd__h684670 ; - assign _theResult___snd__h702472 = + _theResult___snd__h702470 : + _theResult___snd__h684668 ; + assign _theResult___snd__h702470 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d11340) ? - sfd__h660350 : - _theResult___snd__h702478 ; - assign _theResult___snd__h702478 = + sfd__h660348 : + _theResult___snd__h702476 ; + assign _theResult___snd__h702476 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q125[54:0], 2'd0 } ; - assign _theResult___snd__h702496 = - sfd__h660350 << + assign _theResult___snd__h702494 = + sfd__h660348 << (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d11789[8] ? 9'h0AA : IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d11789) ; - assign _theResult___snd__h734238 = - (f1_exp__h714899 == 8'd0) ? - _theResult___snd__h734247 : - _theResult___snd__h734240 ; - assign _theResult___snd__h734240 = { f1_sfd__h714900, 34'd0 } ; - assign _theResult___snd__h734247 = - (f1_exp__h714899 == 8'd0 && !f1_sfd__h714900[22] && + assign _theResult___snd__h734235 = + (f1_exp__h714896 == 8'd0) ? + _theResult___snd__h734244 : + _theResult___snd__h734237 ; + assign _theResult___snd__h734237 = { f1_sfd__h714897, 34'd0 } ; + assign _theResult___snd__h734244 = + (f1_exp__h714896 == 8'd0 && !f1_sfd__h714897[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d12707) ? - sfd__h715261 : - _theResult___snd__h734253 ; - assign _theResult___snd__h734253 = + sfd__h715258 : + _theResult___snd__h734250 ; + assign _theResult___snd__h734250 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q146[54:0], 2'd0 } ; - assign _theResult___snd__h734276 = - sfd__h715261 << + assign _theResult___snd__h734273 = + sfd__h715258 << IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d12734 ; - assign _theResult___snd__h743875 = { _theResult____h735628[55:0], 1'd0 } ; - assign _theResult___snd__h743886 = - (!_theResult____h735628[56] && _theResult____h735628[55]) ? - _theResult___snd__h743888 : - _theResult___snd__h743898 ; - assign _theResult___snd__h743888 = { _theResult____h735628[54:0], 2'd0 } ; - assign _theResult___snd__h743898 = - (!_theResult____h735628[56] && !_theResult____h735628[55] && - !_theResult____h735628[54] && - !_theResult____h735628[53] && - !_theResult____h735628[52] && - !_theResult____h735628[51] && - !_theResult____h735628[50] && - !_theResult____h735628[49] && - !_theResult____h735628[48] && - !_theResult____h735628[47] && - !_theResult____h735628[46] && - !_theResult____h735628[45] && - !_theResult____h735628[44] && - !_theResult____h735628[43] && - !_theResult____h735628[42] && - !_theResult____h735628[41] && - !_theResult____h735628[40] && - !_theResult____h735628[39] && - !_theResult____h735628[38] && - !_theResult____h735628[37] && - !_theResult____h735628[36] && - !_theResult____h735628[35] && - !_theResult____h735628[34] && - !_theResult____h735628[33] && - !_theResult____h735628[32] && - !_theResult____h735628[31] && - !_theResult____h735628[30] && - !_theResult____h735628[29] && - !_theResult____h735628[28] && - !_theResult____h735628[27] && - !_theResult____h735628[26] && - !_theResult____h735628[25] && - !_theResult____h735628[24] && - !_theResult____h735628[23] && - !_theResult____h735628[22] && - !_theResult____h735628[21] && - !_theResult____h735628[20] && - !_theResult____h735628[19] && - !_theResult____h735628[18] && - !_theResult____h735628[17] && - !_theResult____h735628[16] && - !_theResult____h735628[15] && - !_theResult____h735628[14] && - !_theResult____h735628[13] && - !_theResult____h735628[12] && - !_theResult____h735628[11] && - !_theResult____h735628[10] && - !_theResult____h735628[9] && - !_theResult____h735628[8] && - !_theResult____h735628[7] && - !_theResult____h735628[6] && - !_theResult____h735628[5] && - !_theResult____h735628[4] && - !_theResult____h735628[3] && - !_theResult____h735628[2] && - !_theResult____h735628[1] && - !_theResult____h735628[0]) ? - _theResult____h735628 : - _theResult___snd__h743904 ; - assign _theResult___snd__h743904 = + assign _theResult___snd__h743872 = { _theResult____h735625[55:0], 1'd0 } ; + assign _theResult___snd__h743883 = + (!_theResult____h735625[56] && _theResult____h735625[55]) ? + _theResult___snd__h743885 : + _theResult___snd__h743895 ; + assign _theResult___snd__h743885 = { _theResult____h735625[54:0], 2'd0 } ; + assign _theResult___snd__h743895 = + (!_theResult____h735625[56] && !_theResult____h735625[55] && + !_theResult____h735625[54] && + !_theResult____h735625[53] && + !_theResult____h735625[52] && + !_theResult____h735625[51] && + !_theResult____h735625[50] && + !_theResult____h735625[49] && + !_theResult____h735625[48] && + !_theResult____h735625[47] && + !_theResult____h735625[46] && + !_theResult____h735625[45] && + !_theResult____h735625[44] && + !_theResult____h735625[43] && + !_theResult____h735625[42] && + !_theResult____h735625[41] && + !_theResult____h735625[40] && + !_theResult____h735625[39] && + !_theResult____h735625[38] && + !_theResult____h735625[37] && + !_theResult____h735625[36] && + !_theResult____h735625[35] && + !_theResult____h735625[34] && + !_theResult____h735625[33] && + !_theResult____h735625[32] && + !_theResult____h735625[31] && + !_theResult____h735625[30] && + !_theResult____h735625[29] && + !_theResult____h735625[28] && + !_theResult____h735625[27] && + !_theResult____h735625[26] && + !_theResult____h735625[25] && + !_theResult____h735625[24] && + !_theResult____h735625[23] && + !_theResult____h735625[22] && + !_theResult____h735625[21] && + !_theResult____h735625[20] && + !_theResult____h735625[19] && + !_theResult____h735625[18] && + !_theResult____h735625[17] && + !_theResult____h735625[16] && + !_theResult____h735625[15] && + !_theResult____h735625[14] && + !_theResult____h735625[13] && + !_theResult____h735625[12] && + !_theResult____h735625[11] && + !_theResult____h735625[10] && + !_theResult____h735625[9] && + !_theResult____h735625[8] && + !_theResult____h735625[7] && + !_theResult____h735625[6] && + !_theResult____h735625[5] && + !_theResult____h735625[4] && + !_theResult____h735625[3] && + !_theResult____h735625[2] && + !_theResult____h735625[1] && + !_theResult____h735625[0]) ? + _theResult____h735625 : + _theResult___snd__h743901 ; + assign _theResult___snd__h743901 = { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q150[54:0], 2'd0 } ; - assign _theResult___snd__h743927 = - _theResult____h735628 << + assign _theResult___snd__h743924 = + _theResult____h735625 << IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d13046 ; - assign _theResult___snd__h752643 = - (f1_exp__h714899 == 8'd0) ? - _theResult___snd__h752657 : - _theResult___snd__h734240 ; - assign _theResult___snd__h752657 = - (f1_exp__h714899 == 8'd0 && !f1_sfd__h714900[22] && + assign _theResult___snd__h752640 = + (f1_exp__h714896 == 8'd0) ? + _theResult___snd__h752654 : + _theResult___snd__h734237 ; + assign _theResult___snd__h752654 = + (f1_exp__h714896 == 8'd0 && !f1_sfd__h714897[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d12707) ? - sfd__h715261 : - _theResult___snd__h752663 ; - assign _theResult___snd__h752663 = + sfd__h715258 : + _theResult___snd__h752660 ; + assign _theResult___snd__h752660 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q153[54:0], 2'd0 } ; - assign _theResult___snd__h752681 = - sfd__h715261 << + assign _theResult___snd__h752678 = + sfd__h715258 << IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d13097 ; - assign _theResult___snd__h773091 = - (f2_exp__h753893 == 8'd0) ? - _theResult___snd__h773100 : - _theResult___snd__h773093 ; - assign _theResult___snd__h773093 = { f2_sfd__h753894, 34'd0 } ; - assign _theResult___snd__h773100 = - (f2_exp__h753893 == 8'd0 && !f2_sfd__h753894[22] && + assign _theResult___snd__h773088 = + (f2_exp__h753890 == 8'd0) ? + _theResult___snd__h773097 : + _theResult___snd__h773090 ; + assign _theResult___snd__h773090 = { f2_sfd__h753891, 34'd0 } ; + assign _theResult___snd__h773097 = + (f2_exp__h753890 == 8'd0 && !f2_sfd__h753891[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d14207) ? - sfd__h754255 : - _theResult___snd__h773106 ; - assign _theResult___snd__h773106 = + sfd__h754252 : + _theResult___snd__h773103 ; + assign _theResult___snd__h773103 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q186[54:0], 2'd0 } ; - assign _theResult___snd__h773129 = - sfd__h754255 << + assign _theResult___snd__h773126 = + sfd__h754252 << IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14234 ; - assign _theResult___snd__h782728 = { _theResult____h774481[55:0], 1'd0 } ; - assign _theResult___snd__h782739 = - (!_theResult____h774481[56] && _theResult____h774481[55]) ? - _theResult___snd__h782741 : - _theResult___snd__h782751 ; - assign _theResult___snd__h782741 = { _theResult____h774481[54:0], 2'd0 } ; - assign _theResult___snd__h782751 = - (!_theResult____h774481[56] && !_theResult____h774481[55] && - !_theResult____h774481[54] && - !_theResult____h774481[53] && - !_theResult____h774481[52] && - !_theResult____h774481[51] && - !_theResult____h774481[50] && - !_theResult____h774481[49] && - !_theResult____h774481[48] && - !_theResult____h774481[47] && - !_theResult____h774481[46] && - !_theResult____h774481[45] && - !_theResult____h774481[44] && - !_theResult____h774481[43] && - !_theResult____h774481[42] && - !_theResult____h774481[41] && - !_theResult____h774481[40] && - !_theResult____h774481[39] && - !_theResult____h774481[38] && - !_theResult____h774481[37] && - !_theResult____h774481[36] && - !_theResult____h774481[35] && - !_theResult____h774481[34] && - !_theResult____h774481[33] && - !_theResult____h774481[32] && - !_theResult____h774481[31] && - !_theResult____h774481[30] && - !_theResult____h774481[29] && - !_theResult____h774481[28] && - !_theResult____h774481[27] && - !_theResult____h774481[26] && - !_theResult____h774481[25] && - !_theResult____h774481[24] && - !_theResult____h774481[23] && - !_theResult____h774481[22] && - !_theResult____h774481[21] && - !_theResult____h774481[20] && - !_theResult____h774481[19] && - !_theResult____h774481[18] && - !_theResult____h774481[17] && - !_theResult____h774481[16] && - !_theResult____h774481[15] && - !_theResult____h774481[14] && - !_theResult____h774481[13] && - !_theResult____h774481[12] && - !_theResult____h774481[11] && - !_theResult____h774481[10] && - !_theResult____h774481[9] && - !_theResult____h774481[8] && - !_theResult____h774481[7] && - !_theResult____h774481[6] && - !_theResult____h774481[5] && - !_theResult____h774481[4] && - !_theResult____h774481[3] && - !_theResult____h774481[2] && - !_theResult____h774481[1] && - !_theResult____h774481[0]) ? - _theResult____h774481 : - _theResult___snd__h782757 ; - assign _theResult___snd__h782757 = + assign _theResult___snd__h782725 = { _theResult____h774478[55:0], 1'd0 } ; + assign _theResult___snd__h782736 = + (!_theResult____h774478[56] && _theResult____h774478[55]) ? + _theResult___snd__h782738 : + _theResult___snd__h782748 ; + assign _theResult___snd__h782738 = { _theResult____h774478[54:0], 2'd0 } ; + assign _theResult___snd__h782748 = + (!_theResult____h774478[56] && !_theResult____h774478[55] && + !_theResult____h774478[54] && + !_theResult____h774478[53] && + !_theResult____h774478[52] && + !_theResult____h774478[51] && + !_theResult____h774478[50] && + !_theResult____h774478[49] && + !_theResult____h774478[48] && + !_theResult____h774478[47] && + !_theResult____h774478[46] && + !_theResult____h774478[45] && + !_theResult____h774478[44] && + !_theResult____h774478[43] && + !_theResult____h774478[42] && + !_theResult____h774478[41] && + !_theResult____h774478[40] && + !_theResult____h774478[39] && + !_theResult____h774478[38] && + !_theResult____h774478[37] && + !_theResult____h774478[36] && + !_theResult____h774478[35] && + !_theResult____h774478[34] && + !_theResult____h774478[33] && + !_theResult____h774478[32] && + !_theResult____h774478[31] && + !_theResult____h774478[30] && + !_theResult____h774478[29] && + !_theResult____h774478[28] && + !_theResult____h774478[27] && + !_theResult____h774478[26] && + !_theResult____h774478[25] && + !_theResult____h774478[24] && + !_theResult____h774478[23] && + !_theResult____h774478[22] && + !_theResult____h774478[21] && + !_theResult____h774478[20] && + !_theResult____h774478[19] && + !_theResult____h774478[18] && + !_theResult____h774478[17] && + !_theResult____h774478[16] && + !_theResult____h774478[15] && + !_theResult____h774478[14] && + !_theResult____h774478[13] && + !_theResult____h774478[12] && + !_theResult____h774478[11] && + !_theResult____h774478[10] && + !_theResult____h774478[9] && + !_theResult____h774478[8] && + !_theResult____h774478[7] && + !_theResult____h774478[6] && + !_theResult____h774478[5] && + !_theResult____h774478[4] && + !_theResult____h774478[3] && + !_theResult____h774478[2] && + !_theResult____h774478[1] && + !_theResult____h774478[0]) ? + _theResult____h774478 : + _theResult___snd__h782754 ; + assign _theResult___snd__h782754 = { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q190[54:0], 2'd0 } ; - assign _theResult___snd__h782780 = - _theResult____h774481 << + assign _theResult___snd__h782777 = + _theResult____h774478 << IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d14531 ; - assign _theResult___snd__h791496 = - (f2_exp__h753893 == 8'd0) ? - _theResult___snd__h791510 : - _theResult___snd__h773093 ; - assign _theResult___snd__h791510 = - (f2_exp__h753893 == 8'd0 && !f2_sfd__h753894[22] && + assign _theResult___snd__h791493 = + (f2_exp__h753890 == 8'd0) ? + _theResult___snd__h791507 : + _theResult___snd__h773090 ; + assign _theResult___snd__h791507 = + (f2_exp__h753890 == 8'd0 && !f2_sfd__h753891[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d14207) ? - sfd__h754255 : - _theResult___snd__h791516 ; - assign _theResult___snd__h791516 = + sfd__h754252 : + _theResult___snd__h791513 ; + assign _theResult___snd__h791513 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q193[54:0], 2'd0 } ; - assign _theResult___snd__h791534 = - sfd__h754255 << + assign _theResult___snd__h791531 = + sfd__h754252 << IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d14582 ; - assign _theResult___snd__h812395 = - (f3_exp__h793197 == 8'd0) ? - _theResult___snd__h812404 : - _theResult___snd__h812397 ; - assign _theResult___snd__h812397 = { f3_sfd__h793198, 34'd0 } ; - assign _theResult___snd__h812404 = - (f3_exp__h793197 == 8'd0 && !f3_sfd__h793198[22] && + assign _theResult___snd__h812392 = + (f3_exp__h793194 == 8'd0) ? + _theResult___snd__h812401 : + _theResult___snd__h812394 ; + assign _theResult___snd__h812394 = { f3_sfd__h793195, 34'd0 } ; + assign _theResult___snd__h812401 = + (f3_exp__h793194 == 8'd0 && !f3_sfd__h793195[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d13437) ? - sfd__h793559 : - _theResult___snd__h812410 ; - assign _theResult___snd__h812410 = + sfd__h793556 : + _theResult___snd__h812407 ; + assign _theResult___snd__h812407 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q163[54:0], 2'd0 } ; - assign _theResult___snd__h812433 = - sfd__h793559 << + assign _theResult___snd__h812430 = + sfd__h793556 << IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13464 ; - assign _theResult___snd__h822032 = { _theResult____h813785[55:0], 1'd0 } ; - assign _theResult___snd__h822043 = - (!_theResult____h813785[56] && _theResult____h813785[55]) ? - _theResult___snd__h822045 : - _theResult___snd__h822055 ; - assign _theResult___snd__h822045 = { _theResult____h813785[54:0], 2'd0 } ; - assign _theResult___snd__h822055 = - (!_theResult____h813785[56] && !_theResult____h813785[55] && - !_theResult____h813785[54] && - !_theResult____h813785[53] && - !_theResult____h813785[52] && - !_theResult____h813785[51] && - !_theResult____h813785[50] && - !_theResult____h813785[49] && - !_theResult____h813785[48] && - !_theResult____h813785[47] && - !_theResult____h813785[46] && - !_theResult____h813785[45] && - !_theResult____h813785[44] && - !_theResult____h813785[43] && - !_theResult____h813785[42] && - !_theResult____h813785[41] && - !_theResult____h813785[40] && - !_theResult____h813785[39] && - !_theResult____h813785[38] && - !_theResult____h813785[37] && - !_theResult____h813785[36] && - !_theResult____h813785[35] && - !_theResult____h813785[34] && - !_theResult____h813785[33] && - !_theResult____h813785[32] && - !_theResult____h813785[31] && - !_theResult____h813785[30] && - !_theResult____h813785[29] && - !_theResult____h813785[28] && - !_theResult____h813785[27] && - !_theResult____h813785[26] && - !_theResult____h813785[25] && - !_theResult____h813785[24] && - !_theResult____h813785[23] && - !_theResult____h813785[22] && - !_theResult____h813785[21] && - !_theResult____h813785[20] && - !_theResult____h813785[19] && - !_theResult____h813785[18] && - !_theResult____h813785[17] && - !_theResult____h813785[16] && - !_theResult____h813785[15] && - !_theResult____h813785[14] && - !_theResult____h813785[13] && - !_theResult____h813785[12] && - !_theResult____h813785[11] && - !_theResult____h813785[10] && - !_theResult____h813785[9] && - !_theResult____h813785[8] && - !_theResult____h813785[7] && - !_theResult____h813785[6] && - !_theResult____h813785[5] && - !_theResult____h813785[4] && - !_theResult____h813785[3] && - !_theResult____h813785[2] && - !_theResult____h813785[1] && - !_theResult____h813785[0]) ? - _theResult____h813785 : - _theResult___snd__h822061 ; - assign _theResult___snd__h822061 = + assign _theResult___snd__h822029 = { _theResult____h813782[55:0], 1'd0 } ; + assign _theResult___snd__h822040 = + (!_theResult____h813782[56] && _theResult____h813782[55]) ? + _theResult___snd__h822042 : + _theResult___snd__h822052 ; + assign _theResult___snd__h822042 = { _theResult____h813782[54:0], 2'd0 } ; + assign _theResult___snd__h822052 = + (!_theResult____h813782[56] && !_theResult____h813782[55] && + !_theResult____h813782[54] && + !_theResult____h813782[53] && + !_theResult____h813782[52] && + !_theResult____h813782[51] && + !_theResult____h813782[50] && + !_theResult____h813782[49] && + !_theResult____h813782[48] && + !_theResult____h813782[47] && + !_theResult____h813782[46] && + !_theResult____h813782[45] && + !_theResult____h813782[44] && + !_theResult____h813782[43] && + !_theResult____h813782[42] && + !_theResult____h813782[41] && + !_theResult____h813782[40] && + !_theResult____h813782[39] && + !_theResult____h813782[38] && + !_theResult____h813782[37] && + !_theResult____h813782[36] && + !_theResult____h813782[35] && + !_theResult____h813782[34] && + !_theResult____h813782[33] && + !_theResult____h813782[32] && + !_theResult____h813782[31] && + !_theResult____h813782[30] && + !_theResult____h813782[29] && + !_theResult____h813782[28] && + !_theResult____h813782[27] && + !_theResult____h813782[26] && + !_theResult____h813782[25] && + !_theResult____h813782[24] && + !_theResult____h813782[23] && + !_theResult____h813782[22] && + !_theResult____h813782[21] && + !_theResult____h813782[20] && + !_theResult____h813782[19] && + !_theResult____h813782[18] && + !_theResult____h813782[17] && + !_theResult____h813782[16] && + !_theResult____h813782[15] && + !_theResult____h813782[14] && + !_theResult____h813782[13] && + !_theResult____h813782[12] && + !_theResult____h813782[11] && + !_theResult____h813782[10] && + !_theResult____h813782[9] && + !_theResult____h813782[8] && + !_theResult____h813782[7] && + !_theResult____h813782[6] && + !_theResult____h813782[5] && + !_theResult____h813782[4] && + !_theResult____h813782[3] && + !_theResult____h813782[2] && + !_theResult____h813782[1] && + !_theResult____h813782[0]) ? + _theResult____h813782 : + _theResult___snd__h822058 ; + assign _theResult___snd__h822058 = { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q167[54:0], 2'd0 } ; - assign _theResult___snd__h822084 = - _theResult____h813785 << + assign _theResult___snd__h822081 = + _theResult____h813782 << IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d13761 ; - assign _theResult___snd__h830800 = - (f3_exp__h793197 == 8'd0) ? - _theResult___snd__h830814 : - _theResult___snd__h812397 ; - assign _theResult___snd__h830814 = - (f3_exp__h793197 == 8'd0 && !f3_sfd__h793198[22] && + assign _theResult___snd__h830797 = + (f3_exp__h793194 == 8'd0) ? + _theResult___snd__h830811 : + _theResult___snd__h812394 ; + assign _theResult___snd__h830811 = + (f3_exp__h793194 == 8'd0 && !f3_sfd__h793195[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d13437) ? - sfd__h793559 : - _theResult___snd__h830820 ; - assign _theResult___snd__h830820 = + sfd__h793556 : + _theResult___snd__h830817 ; + assign _theResult___snd__h830817 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q170[54:0], 2'd0 } ; - assign _theResult___snd__h830838 = - sfd__h793559 << + assign _theResult___snd__h830835 = + sfd__h793556 << IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d13812 ; - assign _theResult___snd__h836130 = - b__h835708[63] ? b___1__h836179 : b__h835708 ; - assign _theResult___snd_fst_exp__h593747 = + assign _theResult___snd__h836127 = + b__h835705[63] ? b___1__h836176 : b__h835705 ; + assign _theResult___snd_fst_exp__h593745 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8136 ? - _theResult___fst_exp__h585162 : - _theResult___fst_exp__h593744 ; - assign _theResult___snd_fst_exp__h611567 = + _theResult___fst_exp__h585160 : + _theResult___fst_exp__h593742 ; + assign _theResult___snd_fst_exp__h611565 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8676 ? - _theResult___fst_exp__h602928 : - _theResult___fst_exp__h611564 ; - assign _theResult___snd_fst_exp__h639496 = + _theResult___fst_exp__h602926 : + _theResult___fst_exp__h611562 ; + assign _theResult___snd_fst_exp__h639494 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9533 ? - _theResult___fst_exp__h630911 : - _theResult___fst_exp__h639493 ; - assign _theResult___snd_fst_exp__h657316 = + _theResult___fst_exp__h630909 : + _theResult___fst_exp__h639491 ; + assign _theResult___snd_fst_exp__h657314 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10073 ? - _theResult___fst_exp__h648677 : - _theResult___fst_exp__h657313 ; - assign _theResult___snd_fst_exp__h685243 = + _theResult___fst_exp__h648675 : + _theResult___fst_exp__h657311 ; + assign _theResult___snd_fst_exp__h685241 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10930 ? - _theResult___fst_exp__h676658 : - _theResult___fst_exp__h685240 ; - assign _theResult___snd_fst_exp__h703063 = + _theResult___fst_exp__h676656 : + _theResult___fst_exp__h685238 ; + assign _theResult___snd_fst_exp__h703061 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11470 ? - _theResult___fst_exp__h694424 : - _theResult___fst_exp__h703060 ; - assign _theResult___snd_fst_exp__h735048 = + _theResult___fst_exp__h694422 : + _theResult___fst_exp__h703058 ; + assign _theResult___snd_fst_exp__h735045 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12663 ? 11'd0 : - _theResult___fst_exp__h735045 ; - assign _theResult___snd_fst_exp__h753483 = + _theResult___fst_exp__h735042 ; + assign _theResult___snd_fst_exp__h753480 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12799 ? - _theResult___fst_exp__h744696 : - _theResult___fst_exp__h753480 ; - assign _theResult___snd_fst_exp__h773901 = + _theResult___fst_exp__h744693 : + _theResult___fst_exp__h753477 ; + assign _theResult___snd_fst_exp__h773898 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14163 ? 11'd0 : - _theResult___fst_exp__h773898 ; - assign _theResult___snd_fst_exp__h792336 = + _theResult___fst_exp__h773895 ; + assign _theResult___snd_fst_exp__h792333 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14284 ? - _theResult___fst_exp__h783549 : - _theResult___fst_exp__h792333 ; - assign _theResult___snd_fst_exp__h813205 = + _theResult___fst_exp__h783546 : + _theResult___fst_exp__h792330 ; + assign _theResult___snd_fst_exp__h813202 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13393 ? 11'd0 : - _theResult___fst_exp__h813202 ; - assign _theResult___snd_fst_exp__h831640 = + _theResult___fst_exp__h813199 ; + assign _theResult___snd_fst_exp__h831637 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13514 ? - _theResult___fst_exp__h822853 : - _theResult___fst_exp__h831637 ; - assign _theResult___snd_fst_sfd__h568799 = + _theResult___fst_exp__h822850 : + _theResult___fst_exp__h831634 ; + assign _theResult___snd_fst_sfd__h568797 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:34] == 23'd0) ? 23'd2097152 : coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:34] ; - assign _theResult___snd_fst_sfd__h593748 = + assign _theResult___snd_fst_sfd__h593746 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8136 ? - _theResult___fst_sfd__h585163 : - _theResult___fst_sfd__h593745 ; - assign _theResult___snd_fst_sfd__h611568 = + _theResult___fst_sfd__h585161 : + _theResult___fst_sfd__h593743 ; + assign _theResult___snd_fst_sfd__h611566 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d8676 ? - _theResult___fst_sfd__h602929 : - _theResult___fst_sfd__h611565 ; - assign _theResult___snd_fst_sfd__h614553 = + _theResult___fst_sfd__h602927 : + _theResult___fst_sfd__h611563 ; + assign _theResult___snd_fst_sfd__h614551 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:34] == 23'd0) ? 23'd2097152 : coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:34] ; - assign _theResult___snd_fst_sfd__h639497 = + assign _theResult___snd_fst_sfd__h639495 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9533 ? - _theResult___fst_sfd__h630912 : - _theResult___fst_sfd__h639494 ; - assign _theResult___snd_fst_sfd__h657317 = + _theResult___fst_sfd__h630910 : + _theResult___fst_sfd__h639492 ; + assign _theResult___snd_fst_sfd__h657315 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10073 ? - _theResult___fst_sfd__h648678 : - _theResult___fst_sfd__h657314 ; - assign _theResult___snd_fst_sfd__h660300 = + _theResult___fst_sfd__h648676 : + _theResult___fst_sfd__h657312 ; + assign _theResult___snd_fst_sfd__h660298 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:34] == 23'd0) ? 23'd2097152 : coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:34] ; - assign _theResult___snd_fst_sfd__h685244 = + assign _theResult___snd_fst_sfd__h685242 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10930 ? - _theResult___fst_sfd__h676659 : - _theResult___fst_sfd__h685241 ; - assign _theResult___snd_fst_sfd__h703064 = + _theResult___fst_sfd__h676657 : + _theResult___fst_sfd__h685239 ; + assign _theResult___snd_fst_sfd__h703062 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d11470 ? - _theResult___fst_sfd__h694425 : - _theResult___fst_sfd__h703061 ; - assign _theResult___snd_fst_sfd__h715215 = - (f1_sfd__h714900 == 23'd0) ? + _theResult___fst_sfd__h694423 : + _theResult___fst_sfd__h703059 ; + assign _theResult___snd_fst_sfd__h715212 = + (f1_sfd__h714897 == 23'd0) ? 52'h4000000000000 : - out___1_sfd__h714963 ; - assign _theResult___snd_fst_sfd__h735049 = + out___1_sfd__h714960 ; + assign _theResult___snd_fst_sfd__h735046 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d12663 ? 52'd0 : - _theResult___fst_sfd__h735046 ; - assign _theResult___snd_fst_sfd__h753484 = + _theResult___fst_sfd__h735043 ; + assign _theResult___snd_fst_sfd__h753481 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d12799 ? - _theResult___fst_sfd__h744697 : - _theResult___fst_sfd__h753481 ; - assign _theResult___snd_fst_sfd__h754209 = - (f2_sfd__h753894 == 23'd0) ? + _theResult___fst_sfd__h744694 : + _theResult___fst_sfd__h753478 ; + assign _theResult___snd_fst_sfd__h754206 = + (f2_sfd__h753891 == 23'd0) ? 52'h4000000000000 : - out___1_sfd__h753957 ; - assign _theResult___snd_fst_sfd__h773902 = + out___1_sfd__h753954 ; + assign _theResult___snd_fst_sfd__h773899 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d14163 ? 52'd0 : - _theResult___fst_sfd__h773899 ; - assign _theResult___snd_fst_sfd__h792337 = + _theResult___fst_sfd__h773896 ; + assign _theResult___snd_fst_sfd__h792334 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d14284 ? - _theResult___fst_sfd__h783550 : - _theResult___fst_sfd__h792334 ; - assign _theResult___snd_fst_sfd__h793513 = - (f3_sfd__h793198 == 23'd0) ? + _theResult___fst_sfd__h783547 : + _theResult___fst_sfd__h792331 ; + assign _theResult___snd_fst_sfd__h793510 = + (f3_sfd__h793195 == 23'd0) ? 52'h4000000000000 : - out___1_sfd__h793261 ; - assign _theResult___snd_fst_sfd__h813206 = + out___1_sfd__h793258 ; + assign _theResult___snd_fst_sfd__h813203 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d13393 ? 52'd0 : - _theResult___fst_sfd__h813203 ; - assign _theResult___snd_fst_sfd__h831641 = + _theResult___fst_sfd__h813200 ; + assign _theResult___snd_fst_sfd__h831638 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13514 ? - _theResult___fst_sfd__h822854 : - _theResult___fst_sfd__h831638 ; - assign a___1__h835848 = + _theResult___fst_sfd__h822851 : + _theResult___fst_sfd__h831635 ; + assign a___1__h835845 = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd1) ? { 32'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[171:140] } : { {32{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q22[31]}}, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q22 } ; - assign a___1__h836134 = 64'd0 - a__h835707 ; - assign a__h835707 = + assign a___1__h836131 = 64'd0 - a__h835704 ; + assign a__h835704 = coreFix_fpuMulDivExe_0_regToExeQ$first[227] ? - a___1__h835848 : + a___1__h835845 : coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; - assign addBase__h1008585 = - { {48{base__h895975[15]}}, base__h895975 } << + assign addBase__h1008620 = + { {48{base__h895973[15]}}, base__h895973 } << csrf_stcc_reg[33:28] ; - assign addBase__h1008988 = - { {48{base__h854220[15]}}, base__h854220 } << + assign addBase__h1009023 = + { {48{base__h854219[15]}}, base__h854219 } << IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16100 ; - assign addBase__h1009405 = - { {48{base__h896259[15]}}, base__h896259 } << + assign addBase__h1009440 = + { {48{base__h896257[15]}}, base__h896257 } << csrf_mtcc_reg[33:28] ; - assign addBase__h1009808 = - { {48{base__h855213[15]}}, base__h855213 } << + assign addBase__h1009843 = + { {48{base__h855212[15]}}, base__h855212 } << IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16252 ; - assign addBase__h1010478 = - { {48{base__h896604[15]}}, base__h896604 } << + assign addBase__h1010513 = + { {48{base__h896602[15]}}, base__h896602 } << csrf_rg_dpc[33:28] ; - assign addBase__h239864 = - { {48{base__h239699[15]}}, base__h239699 } << + assign addBase__h239861 = + { {48{base__h239696[15]}}, base__h239696 } << coreFix_memExe_regToExeQ$first[265:260] ; - assign addBase__h241021 = - { {48{base__h240856[15]}}, base__h240856 } << + assign addBase__h241018 = + { {48{base__h240853[15]}}, base__h240853 } << coreFix_memExe_regToExeQ$first[102:97] ; - assign addBase__h254645 = - { {48{base__h254480[15]}}, base__h254480 } << + assign addBase__h254642 = + { {48{base__h254477[15]}}, base__h254477 } << coreFix_memExe_dTlb$procResp[334:329] ; - assign addTop__h239973 = - { {50{x__h240072[15]}}, x__h240072 } << + assign addTop__h239970 = + { {50{x__h240069[15]}}, x__h240069 } << coreFix_memExe_regToExeQ$first[265:260] ; - assign addTop__h241130 = - { {50{x__h241229[15]}}, x__h241229 } << + assign addTop__h241127 = + { {50{x__h241226[15]}}, x__h241226 } << coreFix_memExe_regToExeQ$first[102:97] ; - assign addTop__h254754 = - { {50{x__h254853[15]}}, x__h254853 } << + assign addTop__h254751 = + { {50{x__h254850[15]}}, x__h254850 } << coreFix_memExe_dTlb$procResp[334:329] ; - assign addr__h148439 = + assign addr__h148438 = coreFix_memExe_reqLdQ_data_0_lat_0$whas ? coreFix_memExe_reqLdQ_data_0_lat_0$wget[63:0] : coreFix_memExe_reqLdQ_data_0_rl[63:0] ; - assign addr__h152015 = + assign addr__h152014 = CAN_FIRE_RL_coreFix_memExe_doIssueSB ? coreFix_memExe_reqStQ_data_0_lat_0$wget[63:0] : coreFix_memExe_reqStQ_data_0_rl[63:0] ; - assign addr__h235317 = x__h235746[63:0] + csrf_ddc_reg[149:86] ; - assign addr__h989736 = + assign addr__h235314 = x__h235743[63:0] + csrf_ddc_reg[149:86] ; + assign addr__h989734 = (rob$deqPort_0_deq_data[273:272] == 2'd1 && (rob$deqPort_0_deq_data[265:261] == 5'd1 || rob$deqPort_0_deq_data[265:261] == 5'd12)) ? rob$deqPort_0_deq_data[260:197] : rob$deqPort_0_deq_data[191:128] ; - assign address__h1000151 = { 2'd0, address__h999478 } ; - assign address__h1000495 = { 2'd0, base__h999443 } ; - assign address__h1013682 = rob$deqPort_0_deq_data[565:502] + 64'd4 ; - assign address__h999428 = base__h999389 + { 57'd0, x__h999587 } ; - assign address__h999478 = base__h999443 + { 57'd0, x__h999587 } ; - assign address__h999494 = { 2'd0, address__h999428 } ; - assign address__h999838 = { 2'd0, base__h999389 } ; - assign b___1__h835849 = + assign address__h1000186 = { 2'd0, address__h999513 } ; + assign address__h1000530 = { 2'd0, base__h999478 } ; + assign address__h1013717 = rob$deqPort_0_deq_data[565:502] + 64'd4 ; + assign address__h999463 = base__h999424 + { 57'd0, x__h999622 } ; + assign address__h999513 = base__h999478 + { 57'd0, x__h999622 } ; + assign address__h999529 = { 2'd0, address__h999463 } ; + assign address__h999873 = { 2'd0, base__h999424 } ; + assign b___1__h835846 = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? { {32{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q23[31]}}, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q23 } : { 32'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[107:76] } ; - assign b___1__h836179 = 64'd0 - b__h835708 ; - assign b__h835708 = + assign b___1__h836176 = 64'd0 - b__h835705 ; + assign b__h835705 = coreFix_fpuMulDivExe_0_regToExeQ$first[227] ? - b___1__h835849 : + b___1__h835846 : coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; - assign b_base__h127528 = + assign b_base__h127527 = { coreFix_memExe_respLrScAmoQ_data_0[77:67], ~coreFix_memExe_respLrScAmoQ_data_0[66], coreFix_memExe_respLrScAmoQ_data_0[65:64] } ; - assign b_base__h140444 = + assign b_base__h140443 = { mmio_dataRespQ_data_0[77:67], ~mmio_dataRespQ_data_0[66], mmio_dataRespQ_data_0[65:64] } ; - assign b_base__h183706 = - { x__h183399[77:67], ~x__h183399[66], x__h183399[65:64] } ; - assign b_base__h202457 = - { x__h199251[77:67], ~x__h199251[66], x__h199251[65:64] } ; - assign b_base__h217023 = + assign b_base__h183704 = + { x__h183397[77:67], ~x__h183397[66], x__h183397[65:64] } ; + assign b_base__h202455 = + { x__h199249[77:67], ~x__h199249[66], x__h199249[65:64] } ; + assign b_base__h217021 = { coreFix_memExe_lsq$respLd[77:67], ~coreFix_memExe_lsq$respLd[66], coreFix_memExe_lsq$respLd[65:64] } ; - assign b_base__h867086 = + assign b_base__h867085 = { coreFix_aluExe_1_regToExeQ$first[255:245], ~coreFix_aluExe_1_regToExeQ$first[244], coreFix_aluExe_1_regToExeQ$first[243:242] } ; - assign b_base__h867634 = + assign b_base__h867633 = { coreFix_aluExe_1_regToExeQ$first[126:116], ~coreFix_aluExe_1_regToExeQ$first[115], coreFix_aluExe_1_regToExeQ$first[114:113] } ; - assign b_base__h906772 = + assign b_base__h906770 = { coreFix_aluExe_0_regToExeQ$first[255:245], ~coreFix_aluExe_0_regToExeQ$first[244], coreFix_aluExe_0_regToExeQ$first[243:242] } ; - assign b_base__h907320 = + assign b_base__h907318 = { coreFix_aluExe_0_regToExeQ$first[126:116], ~coreFix_aluExe_0_regToExeQ$first[115], coreFix_aluExe_0_regToExeQ$first[114:113] } ; - assign b_base__h995136 = + assign b_base__h995134 = { commitStage_commitTrap[186:176], ~commitStage_commitTrap[175], commitStage_commitTrap[174:173] } ; - assign b_top__h127527 = + assign b_top__h127526 = { coreFix_memExe_respLrScAmoQ_data_0[89:81], ~coreFix_memExe_respLrScAmoQ_data_0[80:79], coreFix_memExe_respLrScAmoQ_data_0[78] } ; - assign b_top__h140443 = + assign b_top__h140442 = { mmio_dataRespQ_data_0[89:81], ~mmio_dataRespQ_data_0[80:79], mmio_dataRespQ_data_0[78] } ; - assign b_top__h183705 = - { x__h183399[89:81], ~x__h183399[80:79], x__h183399[78] } ; - assign b_top__h202456 = - { x__h199251[89:81], ~x__h199251[80:79], x__h199251[78] } ; - assign b_top__h217022 = + assign b_top__h183703 = + { x__h183397[89:81], ~x__h183397[80:79], x__h183397[78] } ; + assign b_top__h202454 = + { x__h199249[89:81], ~x__h199249[80:79], x__h199249[78] } ; + assign b_top__h217020 = { coreFix_memExe_lsq$respLd[89:81], ~coreFix_memExe_lsq$respLd[80:79], coreFix_memExe_lsq$respLd[78] } ; - assign b_top__h867085 = + assign b_top__h867084 = { coreFix_aluExe_1_regToExeQ$first[267:259], ~coreFix_aluExe_1_regToExeQ$first[258:257], coreFix_aluExe_1_regToExeQ$first[256] } ; - assign b_top__h867633 = + assign b_top__h867632 = { coreFix_aluExe_1_regToExeQ$first[138:130], ~coreFix_aluExe_1_regToExeQ$first[129:128], coreFix_aluExe_1_regToExeQ$first[127] } ; - assign b_top__h906771 = + assign b_top__h906769 = { coreFix_aluExe_0_regToExeQ$first[267:259], ~coreFix_aluExe_0_regToExeQ$first[258:257], coreFix_aluExe_0_regToExeQ$first[256] } ; - assign b_top__h907319 = + assign b_top__h907317 = { coreFix_aluExe_0_regToExeQ$first[138:130], ~coreFix_aluExe_0_regToExeQ$first[129:128], coreFix_aluExe_0_regToExeQ$first[127] } ; - assign b_top__h995135 = + assign b_top__h995133 = { commitStage_commitTrap[198:190], ~commitStage_commitTrap[189:188], commitStage_commitTrap[187] } ; - assign base__h239699 = + assign base__h239696 = { coreFix_memExe_regToExeQ$first[223:222], coreFix_memExe_regToExeQ$first[245:232] } ; - assign base__h240856 = + assign base__h240853 = { coreFix_memExe_regToExeQ$first[60:59], coreFix_memExe_regToExeQ$first[82:69] } ; - assign base__h254480 = + assign base__h254477 = { coreFix_memExe_dTlb$procResp[292:291], coreFix_memExe_dTlb$procResp[314:301] } ; - assign base__h854220 = + assign base__h854219 = { (IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16087 == IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16089) ? 2'd0 : @@ -32915,7 +32910,7 @@ module mkCore(CLK, 2'd1 : 2'd3), IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16084 } ; - assign base__h855213 = + assign base__h855212 = { (IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16239 == IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16241) ? 2'd0 : @@ -32924,7 +32919,7 @@ module mkCore(CLK, 2'd1 : 2'd3), IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16236 } ; - assign base__h895975 = + assign base__h895973 = { (csrf_stcc_reg_read__6046_BITS_13_TO_11_6049_UL_ETC___d16051 == csrf_stcc_reg_read__6046_BITS_85_TO_83_6052_UL_ETC___d16053) ? 2'd0 : @@ -32933,7 +32928,7 @@ module mkCore(CLK, 2'd1 : 2'd3), csrf_stcc_reg[13:0] } ; - assign base__h896259 = + assign base__h896257 = { (csrf_mtcc_reg_read__6198_BITS_13_TO_11_6201_UL_ETC___d16203 == csrf_mtcc_reg_read__6198_BITS_85_TO_83_6204_UL_ETC___d16205) ? 2'd0 : @@ -32942,7 +32937,7 @@ module mkCore(CLK, 2'd1 : 2'd3), csrf_mtcc_reg[13:0] } ; - assign base__h896604 = + assign base__h896602 = { (csrf_rg_dpc_read__6343_BITS_13_TO_11_6346_ULT__ETC___d16348 == csrf_rg_dpc_read__6343_BITS_85_TO_83_6349_ULT__ETC___d16350) ? 2'd0 : @@ -32951,58 +32946,58 @@ module mkCore(CLK, 2'd1 : 2'd3), csrf_rg_dpc[13:0] } ; - assign base__h997574 = - { (IF_INV_commitStage_commitTrap_2268_BITS_217_TO_ETC___d22661 == - IF_INV_commitStage_commitTrap_2268_BITS_217_TO_ETC___d22663) ? + assign base__h997609 = + { (IF_INV_commitStage_commitTrap_2268_BITS_217_TO_ETC___d22662 == + IF_INV_commitStage_commitTrap_2268_BITS_217_TO_ETC___d22664) ? 2'd0 : - ((IF_INV_commitStage_commitTrap_2268_BITS_217_TO_ETC___d22661 && - !IF_INV_commitStage_commitTrap_2268_BITS_217_TO_ETC___d22663) ? + ((IF_INV_commitStage_commitTrap_2268_BITS_217_TO_ETC___d22662 && + !IF_INV_commitStage_commitTrap_2268_BITS_217_TO_ETC___d22664) ? 2'd1 : 2'd3), - x__h995129 } ; - assign base__h999389 = { csrf_stcc_reg[149:88], 2'b0 } ; - assign base__h999443 = { csrf_mtcc_reg[149:88], 2'b0 } ; - assign bot__h1008588 = - { csrf_stcc_reg[149:100] & highBitsfilter__h1008372, 14'd0 } + - addBase__h1008585 ; - assign bot__h1008991 = + x__h995127 } ; + assign base__h999424 = { csrf_stcc_reg[149:88], 2'b0 } ; + assign base__h999478 = { csrf_mtcc_reg[149:88], 2'b0 } ; + assign bot__h1008623 = + { csrf_stcc_reg[149:100] & highBitsfilter__h1008407, 14'd0 } + + addBase__h1008620 ; + assign bot__h1009026 = { IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16104[63:14] & - highBitsfilter__h1008775, + highBitsfilter__h1008810, 14'd0 } + - addBase__h1008988 ; - assign bot__h1009408 = - { csrf_mtcc_reg[149:100] & highBitsfilter__h1009192, 14'd0 } + - addBase__h1009405 ; - assign bot__h1009811 = + addBase__h1009023 ; + assign bot__h1009443 = + { csrf_mtcc_reg[149:100] & highBitsfilter__h1009227, 14'd0 } + + addBase__h1009440 ; + assign bot__h1009846 = { IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16256[63:14] & - highBitsfilter__h1009595, + highBitsfilter__h1009630, 14'd0 } + - addBase__h1009808 ; - assign bot__h1010481 = - { csrf_rg_dpc[149:100] & highBitsfilter__h1010264, 14'd0 } + - addBase__h1010478 ; - assign carry_out__h127432 = - (topBits__h127430 < x__h127521[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h140348 = - (topBits__h140346 < x__h140437[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h183610 = - (topBits__h183608 < x__h183699[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h202361 = - (topBits__h202359 < x__h202450[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h216927 = - (topBits__h216925 < x__h217016[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h866989 = - (topBits__h866987 < x__h867079[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h867537 = - (topBits__h867535 < x__h867627[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h906675 = - (topBits__h906673 < x__h906765[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h907223 = - (topBits__h907221 < x__h907313[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h995040 = - (topBits__h995038 < x__h995129[11:0]) ? 2'b01 : 2'b0 ; - assign cause_code__h996858 = { 1'd0, i__h995510 } ; - assign cause_interrupt__h995318 = + addBase__h1009843 ; + assign bot__h1010516 = + { csrf_rg_dpc[149:100] & highBitsfilter__h1010299, 14'd0 } + + addBase__h1010513 ; + assign carry_out__h127431 = + (topBits__h127429 < x__h127520[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h140347 = + (topBits__h140345 < x__h140436[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h183608 = + (topBits__h183606 < x__h183697[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h202359 = + (topBits__h202357 < x__h202448[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h216925 = + (topBits__h216923 < x__h217014[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h866988 = + (topBits__h866986 < x__h867078[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h867536 = + (topBits__h867534 < x__h867626[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h906673 = + (topBits__h906671 < x__h906763[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h907221 = + (topBits__h907219 < x__h907311[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h995038 = + (topBits__h995036 < x__h995127[11:0]) ? 2'b01 : 2'b0 ; + assign cause_code__h996893 = { 1'd0, i__h995534 } ; + assign cause_interrupt__h995316 = commitStage_commitTrap[44:43] != 2'd1 && commitStage_commitTrap[44:43] != 2'd0 ; assign commitStage_commitTrap_2268_BITS_44_TO_43_2461_ETC___d22501 = @@ -33067,7 +33062,7 @@ module mkCore(CLK, IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19204, IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19396, coreFix_aluExe_0_dispToRegQ$first[124] ? - repBound__h900631 : + repBound__h900629 : 3'd7, NOT_coreFix_aluExe_0_dispToRegQ_first__8383_BI_ETC___d19436 } ; assign coreFix_aluExe_0_dispToRegQ_first__8383_BIT_13_ETC___d18468 = @@ -33118,7 +33113,7 @@ module mkCore(CLK, IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d16826, IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d17262, coreFix_aluExe_1_dispToRegQ$first[124] ? - repBound__h860557 : + repBound__h860556 : 3'd7, NOT_coreFix_aluExe_1_dispToRegQ_first__5620_BI_ETC___d17320 } ; assign coreFix_aluExe_1_dispToRegQ_first__5620_BIT_13_ETC___d15705 = @@ -33223,9 +33218,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d14958 | - ((f3_exp__h793197 != 8'd255 || f3_sfd__h793198 == 23'd0) && - (f3_exp__h793197 != 8'd255 || f3_sfd__h793198 != 23'd0) && - (f3_exp__h793197 != 8'd0 || f3_sfd__h793198 != 23'd0) && + ((f3_exp__h793194 != 8'd255 || f3_sfd__h793195 == 23'd0) && + (f3_exp__h793194 != 8'd255 || f3_sfd__h793195 != 23'd0) && + (f3_exp__h793194 != 8'd0 || f3_sfd__h793195 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14998) ; assign coreFix_fpuMulDivExe_0_regToExeQ_first__2522_B_ETC___d15039 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || @@ -33233,9 +33228,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15027 | - ((f3_exp__h793197 != 8'd255 || f3_sfd__h793198 == 23'd0) && - (f3_exp__h793197 != 8'd255 || f3_sfd__h793198 != 23'd0) && - (f3_exp__h793197 != 8'd0 || f3_sfd__h793198 != 23'd0) && + ((f3_exp__h793194 != 8'd255 || f3_sfd__h793195 == 23'd0) && + (f3_exp__h793194 != 8'd255 || f3_sfd__h793195 != 23'd0) && + (f3_exp__h793194 != 8'd0 || f3_sfd__h793195 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15034) ; assign coreFix_fpuMulDivExe_0_regToExeQ_first__2522_B_ETC___d15087 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || @@ -33243,9 +33238,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15071 | - ((f3_exp__h793197 != 8'd255 || f3_sfd__h793198 == 23'd0) && - (f3_exp__h793197 != 8'd255 || f3_sfd__h793198 != 23'd0) && - (f3_exp__h793197 != 8'd0 || f3_sfd__h793198 != 23'd0) && + ((f3_exp__h793194 != 8'd255 || f3_sfd__h793195 == 23'd0) && + (f3_exp__h793194 != 8'd255 || f3_sfd__h793195 != 23'd0) && + (f3_exp__h793194 != 8'd0 || f3_sfd__h793195 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15082) ; assign coreFix_fpuMulDivExe_0_regToExeQ_first__2522_B_ETC___d15129 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || @@ -33253,9 +33248,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15115 | - ((f3_exp__h793197 != 8'd255 || f3_sfd__h793198 == 23'd0) && - (f3_exp__h793197 != 8'd255 || f3_sfd__h793198 != 23'd0) && - (f3_exp__h793197 != 8'd0 || f3_sfd__h793198 != 23'd0) && + ((f3_exp__h793194 != 8'd255 || f3_sfd__h793195 == 23'd0) && + (f3_exp__h793194 != 8'd255 || f3_sfd__h793195 != 23'd0) && + (f3_exp__h793194 != 8'd0 || f3_sfd__h793195 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15124) ; assign coreFix_fpuMulDivExe_0_regToExeQ_first__2522_B_ETC___d15171 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || @@ -33263,9 +33258,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d15157 | - ((f3_exp__h793197 != 8'd255 || f3_sfd__h793198 == 23'd0) && - (f3_exp__h793197 != 8'd255 || f3_sfd__h793198 != 23'd0) && - (f3_exp__h793197 != 8'd0 || f3_sfd__h793198 != 23'd0) && + ((f3_exp__h793194 != 8'd255 || f3_sfd__h793195 == 23'd0) && + (f3_exp__h793194 != 8'd255 || f3_sfd__h793195 != 23'd0) && + (f3_exp__h793194 != 8'd0 || f3_sfd__h793195 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d15166) ; assign coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q23 = coreFix_fpuMulDivExe_0_regToExeQ$first[107:76] ; @@ -33304,7 +33299,7 @@ module mkCore(CLK, !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5023 && coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58] && coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[57:0] == - y__h422565 ; + y__h422564 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_pi_ETC___d5632 = coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == 3'd3 && @@ -35484,12 +35479,12 @@ module mkCore(CLK, assign coreFix_memExe_dTlb_procResp__257_BITS_334_TO__ETC___d4420 = coreFix_memExe_dTlb$procResp[334:329] < 6'd51 && coreFix_memExe_dTlb_procResp__257_BITS_452_TO__ETC___d4407[64:63] - - { 1'd0, x__h254922 } > + { 1'd0, x__h254919 } > 2'd1 ; assign coreFix_memExe_dTlb_procResp__257_BITS_452_TO__ETC___d4407 = - { coreFix_memExe_dTlb$procResp[452:401] & mask__h254755, + { coreFix_memExe_dTlb$procResp[452:401] & mask__h254752, 14'd0 } + - addTop__h254754 ; + addTop__h254751 ; assign coreFix_memExe_dTlb_procResp__257_BITS_560_TO__ETC___d4557 = coreFix_memExe_dTlb$procResp[560:500] < 61'd402653184 ; assign coreFix_memExe_dTlb_procResp__257_BITS_560_TO__ETC___d4558 = @@ -35535,15 +35530,15 @@ module mkCore(CLK, 66'd0, IF_coreFix_memExe_dispToRegQ_first__686_BIT_10_ETC___d3580 } ; assign coreFix_memExe_lsq_getOrigBE_coreFix_memExe_re_ETC___d4250 = - { coreFix_memExe_lsq$getOrigBE << pointer__h242638[3:0], - (highOffsetBits__h242647 == 50'd0 && + { coreFix_memExe_lsq$getOrigBE << pointer__h242635[3:0], + (highOffsetBits__h242644 == 50'd0 && IF_SEXT_coreFix_memExe_regToExeQ_first__645_BI_ETC___d4095 || coreFix_memExe_regToExeQ$first[265:260] >= 6'd50) && coreFix_memExe_regToExeQ$first[384], - result_d_address__h242849, - x__h248120[13:0], + result_d_address__h242846, + x__h248117[13:0], coreFix_memExe_regToExeQ$first[303:232], - repBound__h248218, + repBound__h248215, coreFix_memExe_regToExeQ_first__645_BITS_259_T_ETC___d4110, coreFix_memExe_regToExeQ_first__645_BITS_245_T_ETC___d4111, coreFix_memExe_regToExeQ_first__645_BITS_383_T_ETC___d4123, @@ -35551,7 +35546,7 @@ module mkCore(CLK, assign coreFix_memExe_regToExeQ_first__645_BITS_102_T_ETC___d3779 = coreFix_memExe_regToExeQ$first[102:97] < 6'd51 && coreFix_memExe_regToExeQ_first__645_BITS_220_T_ETC___d3766[64:63] - - { 1'd0, x__h241298 } > + { 1'd0, x__h241295 } > 2'd1 ; assign coreFix_memExe_regToExeQ_first__645_BITS_140_T_ETC___d4070 = { coreFix_memExe_regToExeQ$first[140:125], @@ -35564,26 +35559,26 @@ module mkCore(CLK, ~IF_coreFix_memExe_regToExeQ_first__645_BIT_103_ETC___d4017[2], IF_coreFix_memExe_regToExeQ_first__645_BIT_103_ETC___d4017[1:0], coreFix_memExe_regToExeQ$first[218:155] } << - x__h244678 ; + x__h244675 ; assign coreFix_memExe_regToExeQ_first__645_BITS_220_T_ETC___d3766 = - { coreFix_memExe_regToExeQ$first[220:169] & mask__h241131, + { coreFix_memExe_regToExeQ$first[220:169] & mask__h241128, 14'd0 } + - addTop__h241130 ; + addTop__h241127 ; assign coreFix_memExe_regToExeQ_first__645_BITS_245_T_ETC___d4111 = - coreFix_memExe_regToExeQ$first[245:243] < repBound__h248218 ; + coreFix_memExe_regToExeQ$first[245:243] < repBound__h248215 ; assign coreFix_memExe_regToExeQ_first__645_BITS_259_T_ETC___d4110 = - coreFix_memExe_regToExeQ$first[259:257] < repBound__h248218 ; + coreFix_memExe_regToExeQ$first[259:257] < repBound__h248215 ; assign coreFix_memExe_regToExeQ_first__645_BITS_265_T_ETC___d3717 = coreFix_memExe_regToExeQ$first[265:260] < 6'd51 && coreFix_memExe_regToExeQ_first__645_BITS_383_T_ETC___d3704[64:63] - - { 1'd0, x__h240141 } > + { 1'd0, x__h240138 } > 2'd1 ; assign coreFix_memExe_regToExeQ_first__645_BITS_383_T_ETC___d3704 = - { coreFix_memExe_regToExeQ$first[383:332] & mask__h239974, + { coreFix_memExe_regToExeQ$first[383:332] & mask__h239971, 14'd0 } + - addTop__h239973 ; + addTop__h239970 ; assign coreFix_memExe_regToExeQ_first__645_BITS_383_T_ETC___d4113 = - x__h248120[13:11] < repBound__h248218 ; + x__h248117[13:11] < repBound__h248215 ; assign coreFix_memExe_regToExeQ_first__645_BITS_383_T_ETC___d4123 = { coreFix_memExe_regToExeQ_first__645_BITS_383_T_ETC___d4113, (coreFix_memExe_regToExeQ_first__645_BITS_259_T_ETC___d4110 == @@ -35612,56 +35607,56 @@ module mkCore(CLK, ({ {48{coreFix_memExe_regToExeQfirst_BITS_223_TO_222__q2[1]}}, coreFix_memExe_regToExeQfirst_BITS_223_TO_222__q2 } << coreFix_memExe_regToExeQ$first[265:260]) ; - assign coreFix_memExe_regToExeQfirst_BITS_434_TO_403__q17 = + assign coreFix_memExe_regToExeQfirst_BITS_434_TO_403__q15 = coreFix_memExe_regToExeQ$first[434:403] ; assign coreFix_memExe_regToExeQfirst_BITS_60_TO_59__q4 = coreFix_memExe_regToExeQ$first[60:59] ; - assign coreFix_memExe_stb_isEmpty__186_AND_coreFix_me_ETC___d23027 = + assign coreFix_memExe_stb_isEmpty__186_AND_coreFix_me_ETC___d23029 = coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty && - rob$RDY_deqPort_0_deq && - rob$RDY_deqPort_0_deq_data && regRenamingTable$RDY_commit_0_commit && + rob$RDY_deqPort_0_deq_data && + rob$RDY_deqPort_0_deq && fetchStage$iTlbIfc_noPendingReq && coreFix_memExe_dTlb$noPendingReq && - NOT_rob_deqPort_0_deq_data__2261_BITS_469_TO_4_ETC___d23022 ; - assign cr_addrBits__h866672 = + NOT_rob_deqPort_0_deq_data__2261_BITS_469_TO_4_ETC___d23024 ; + assign cr_addrBits__h866671 = INV_coreFix_aluExe_1_regToExeQfirst_BITS_286__ETC__q11[0] ? - x__h866848[13:0] : + x__h866847[13:0] : coreFix_aluExe_1_regToExeQ$first[191:178] ; - assign cr_addrBits__h867220 = + assign cr_addrBits__h867219 = INV_coreFix_aluExe_1_regToExeQfirst_BITS_157__ETC__q12[0] ? - x__h867396[13:0] : + x__h867395[13:0] : coreFix_aluExe_1_regToExeQ$first[62:49] ; - assign cr_addrBits__h906358 = + assign cr_addrBits__h906356 = INV_coreFix_aluExe_0_regToExeQfirst_BITS_286__ETC__q13[0] ? - x__h906534[13:0] : + x__h906532[13:0] : coreFix_aluExe_0_regToExeQ$first[191:178] ; - assign cr_addrBits__h906906 = + assign cr_addrBits__h906904 = INV_coreFix_aluExe_0_regToExeQfirst_BITS_157__ETC__q14[0] ? - x__h907082[13:0] : + x__h907080[13:0] : coreFix_aluExe_0_regToExeQ$first[62:49] ; - assign cr_address__h866671 = + assign cr_address__h866670 = { 2'd0, coreFix_aluExe_1_regToExeQ$first[241:178] } ; - assign cr_address__h867219 = + assign cr_address__h867218 = { 2'd0, coreFix_aluExe_1_regToExeQ$first[112:49] } ; - assign cr_address__h906357 = + assign cr_address__h906355 = { 2'd0, coreFix_aluExe_0_regToExeQ$first[241:178] } ; - assign cr_address__h906905 = + assign cr_address__h906903 = { 2'd0, coreFix_aluExe_0_regToExeQ$first[112:49] } ; - assign cr_flags__h866674 = coreFix_aluExe_1_regToExeQ$first[287] ; - assign cr_flags__h867222 = coreFix_aluExe_1_regToExeQ$first[158] ; - assign cr_flags__h906360 = coreFix_aluExe_0_regToExeQ$first[287] ; - assign cr_flags__h906908 = coreFix_aluExe_0_regToExeQ$first[158] ; - assign cr_reserved__h866675 = coreFix_aluExe_1_regToExeQ$first[289:288] ; - assign cr_reserved__h867223 = coreFix_aluExe_1_regToExeQ$first[160:159] ; - assign cr_reserved__h906361 = coreFix_aluExe_0_regToExeQ$first[289:288] ; - assign cr_reserved__h906909 = coreFix_aluExe_0_regToExeQ$first[160:159] ; + assign cr_flags__h866673 = coreFix_aluExe_1_regToExeQ$first[287] ; + assign cr_flags__h867221 = coreFix_aluExe_1_regToExeQ$first[158] ; + assign cr_flags__h906358 = coreFix_aluExe_0_regToExeQ$first[287] ; + assign cr_flags__h906906 = coreFix_aluExe_0_regToExeQ$first[158] ; + assign cr_reserved__h866674 = coreFix_aluExe_1_regToExeQ$first[289:288] ; + assign cr_reserved__h867222 = coreFix_aluExe_1_regToExeQ$first[160:159] ; + assign cr_reserved__h906359 = coreFix_aluExe_0_regToExeQ$first[289:288] ; + assign cr_reserved__h906907 = coreFix_aluExe_0_regToExeQ$first[160:159] ; assign csrf_ddc_reg_read__051_BITS_13_TO_11_140_ULT_c_ETC___d4144 = - csrf_ddc_reg[13:11] < repBound__h248743 ; + csrf_ddc_reg[13:11] < repBound__h248740 ; assign csrf_ddc_reg_read__051_BITS_27_TO_25_142_ULT_c_ETC___d4143 = - csrf_ddc_reg[27:25] < repBound__h248743 ; + csrf_ddc_reg[27:25] < repBound__h248740 ; assign csrf_ddc_reg_read__051_BITS_85_TO_83_145_ULT_c_ETC___d4146 = - csrf_ddc_reg[85:83] < repBound__h248743 ; + csrf_ddc_reg[85:83] < repBound__h248740 ; assign csrf_ddc_reg_read__051_BITS_85_TO_83_145_ULT_c_ETC___d4156 = { csrf_ddc_reg_read__051_BITS_85_TO_83_145_ULT_c_ETC___d4146, (csrf_ddc_reg_read__051_BITS_27_TO_25_142_ULT_c_ETC___d4143 == @@ -35718,73 +35713,70 @@ module mkCore(CLK, csrf_tw_reg && csrf_prv_reg != 2'd3 ; assign csrf_mtcc_reg_read__6198_BITS_13_TO_11_6201_UL_ETC___d16203 = - csrf_mtcc_reg[13:11] < repBound__h855069 ; - assign csrf_mtcc_reg_read__6198_BITS_149_TO_86_2811_A_ETC___d22814 = - csrf_mtcc_reg[149:86] & mask__h1000157 ; - assign csrf_mtcc_reg_read__6198_BITS_149_TO_86_2811_A_ETC___d22821 = - newAddrDiff__h1000158 == mask__h1000157 ; - assign csrf_mtcc_reg_read__6198_BITS_149_TO_86_2811_A_ETC___d22849 = - newAddrDiff__h1000502 == mask__h1000157 ; + csrf_mtcc_reg[13:11] < repBound__h855068 ; + assign csrf_mtcc_reg_read__6198_BITS_149_TO_86_2813_A_ETC___d22816 = + csrf_mtcc_reg[149:86] & mask__h1000192 ; + assign csrf_mtcc_reg_read__6198_BITS_149_TO_86_2813_A_ETC___d22823 = + newAddrDiff__h1000193 == mask__h1000192 ; + assign csrf_mtcc_reg_read__6198_BITS_149_TO_86_2813_A_ETC___d22851 = + newAddrDiff__h1000537 == mask__h1000192 ; assign csrf_mtcc_reg_read__6198_BITS_85_TO_83_6204_UL_ETC___d16205 = - csrf_mtcc_reg[85:83] < repBound__h855069 ; - assign csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22647 = + csrf_mtcc_reg[85:83] < repBound__h855068 ; + assign csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22648 = csrf_prv_reg_read__0286_ULE_1___d22614 && - ((commitStage_commitTrap[44:43] == 2'd1) ? - _0b0_CONCAT_csrf_medeleg_28_26_reg_read__6161_6_ETC___d22642 : - commitStage_commitTrap[44:43] != 2'd0 && - _0b0_CONCAT_csrf_mideleg_11_reg_read__6172_6173_ETC___d22644) ; + CASE_commitStage_commitTrap_BITS_44_TO_43_0_cs_ETC__q276 ; assign csrf_prv_reg_read__0286_ULE_1___d22614 = csrf_prv_reg <= 2'd1 ; assign csrf_rg_dpc_read__6343_BITS_13_TO_11_6346_ULT__ETC___d16348 = - csrf_rg_dpc[13:11] < repBound__h855899 ; + csrf_rg_dpc[13:11] < repBound__h855898 ; assign csrf_rg_dpc_read__6343_BITS_85_TO_83_6349_ULT__ETC___d16350 = - csrf_rg_dpc[85:83] < repBound__h855899 ; + csrf_rg_dpc[85:83] < repBound__h855898 ; assign csrf_stcc_reg_read__6046_BITS_13_TO_11_6049_UL_ETC___d16051 = - csrf_stcc_reg[13:11] < repBound__h854076 ; - assign csrf_stcc_reg_read__6046_BITS_149_TO_86_2740_A_ETC___d22743 = - csrf_stcc_reg[149:86] & mask__h999500 ; - assign csrf_stcc_reg_read__6046_BITS_149_TO_86_2740_A_ETC___d22752 = - newAddrDiff__h999501 == mask__h999500 ; - assign csrf_stcc_reg_read__6046_BITS_149_TO_86_2740_A_ETC___d22780 = - newAddrDiff__h999845 == mask__h999500 ; + csrf_stcc_reg[13:11] < repBound__h854075 ; + assign csrf_stcc_reg_read__6046_BITS_149_TO_86_2742_A_ETC___d22745 = + csrf_stcc_reg[149:86] & mask__h999535 ; + assign csrf_stcc_reg_read__6046_BITS_149_TO_86_2742_A_ETC___d22754 = + newAddrDiff__h999536 == mask__h999535 ; + assign csrf_stcc_reg_read__6046_BITS_149_TO_86_2742_A_ETC___d22782 = + newAddrDiff__h999880 == mask__h999535 ; assign csrf_stcc_reg_read__6046_BITS_85_TO_83_6052_UL_ETC___d16053 = - csrf_stcc_reg[85:83] < repBound__h854076 ; - assign data05833_BITS_31_TO_0__q26 = data__h705833[31:0] ; - assign data___1__h705533 = + csrf_stcc_reg[85:83] < repBound__h854075 ; + assign data05831_BITS_31_TO_0__q26 = data__h705831[31:0] ; + assign data___1__h705531 = { {32{IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q145[31]}}, IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q145 } ; - assign data___1__h706393 = - { {32{data05833_BITS_31_TO_0__q26[31]}}, - data05833_BITS_31_TO_0__q26 } ; - assign data__h567680 = + assign data___1__h706391 = + { {32{data05831_BITS_31_TO_0__q26[31]}}, + data05831_BITS_31_TO_0__q26 } ; + assign data__h567678 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[39] ? - res_data__h568243 : - res_data__h568238 ; - assign data__h613440 = + res_data__h568241 : + res_data__h568236 ; + assign data__h613438 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[39] ? - res_data__h613997 : - res_data__h613992 ; - assign data__h659187 = + res_data__h613995 : + res_data__h613990 ; + assign data__h659185 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[39] ? - res_data__h659744 : - res_data__h659739 ; - assign data__h705001 = + res_data__h659742 : + res_data__h659737 ; + assign data__h704999 = coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[33] ? - data___1__h705533 : + data___1__h705531 : IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC___d12208 ; - assign data__h705833 = + assign data__h705831 = (coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[35:34] == 2'd2) ? - x_quotient__h705747 : - x_remainder__h705748 ; - assign data__h705864 = + x_quotient__h705745 : + x_remainder__h705746 ; + assign data__h705862 = coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[33] ? - data___1__h706393 : - data__h705833 ; - assign data_addrBits__h1018718 = { 2'd0, f_gpr_reqs$D_OUT[63:52] } ; - assign data_addrBits__h1019572 = { 2'b0, f_fpr_reqs$D_OUT[63:52] } ; - assign data_address__h1018717 = { 2'd0, f_gpr_reqs$D_OUT[63:0] } ; - assign data_address__h1019571 = { 2'd0, f_fpr_reqs$D_OUT[63:0] } ; - assign dcsr_cause__h994364 = + data___1__h706391 : + data__h705831 ; + assign data_addrBits__h1018752 = { 2'd0, f_gpr_reqs$D_OUT[63:52] } ; + assign data_addrBits__h1019606 = { 2'b0, f_fpr_reqs$D_OUT[63:52] } ; + assign data_address__h1018751 = { 2'd0, f_gpr_reqs$D_OUT[63:0] } ; + assign data_address__h1019605 = { 2'd0, f_fpr_reqs$D_OUT[63:0] } ; + assign dcsr_cause__h994362 = (commitStage_commitTrap[44:43] != 2'd0 && commitStage_commitTrap[44:43] != 2'd1 && commitStage_commitTrap[35:32] == 4'd14) ? @@ -35803,94 +35795,94 @@ module mkCore(CLK, commitStage_commitTrap[35:32] != 4'd14) ? 3'd4 : 3'd1) ; - assign din_inc___2_exp__h611598 = _theResult___fst_exp__h584565 + 8'd1 ; - assign din_inc___2_exp__h611622 = _theResult___fst_exp__h593221 + 8'd1 ; - assign din_inc___2_exp__h611652 = _theResult___fst_exp__h602331 + 8'd1 ; - assign din_inc___2_exp__h611676 = _theResult___fst_exp__h611016 + 8'd1 ; - assign din_inc___2_exp__h657347 = _theResult___fst_exp__h630314 + 8'd1 ; - assign din_inc___2_exp__h657371 = _theResult___fst_exp__h638970 + 8'd1 ; - assign din_inc___2_exp__h657401 = _theResult___fst_exp__h648080 + 8'd1 ; - assign din_inc___2_exp__h657425 = _theResult___fst_exp__h656765 + 8'd1 ; - assign din_inc___2_exp__h703094 = _theResult___fst_exp__h676061 + 8'd1 ; - assign din_inc___2_exp__h703118 = _theResult___fst_exp__h684717 + 8'd1 ; - assign din_inc___2_exp__h703148 = _theResult___fst_exp__h693827 + 8'd1 ; - assign din_inc___2_exp__h703172 = _theResult___fst_exp__h702512 + 8'd1 ; - assign din_inc___2_exp__h753537 = _theResult___fst_exp__h734287 + 11'd1 ; - assign din_inc___2_exp__h753572 = _theResult___fst_exp__h743864 + 11'd1 ; - assign din_inc___2_exp__h753598 = _theResult___fst_exp__h752697 + 11'd1 ; - assign din_inc___2_exp__h792390 = _theResult___fst_exp__h773140 + 11'd1 ; - assign din_inc___2_exp__h792425 = _theResult___fst_exp__h782717 + 11'd1 ; - assign din_inc___2_exp__h792451 = _theResult___fst_exp__h791550 + 11'd1 ; - assign din_inc___2_exp__h831694 = _theResult___fst_exp__h812444 + 11'd1 ; - assign din_inc___2_exp__h831729 = _theResult___fst_exp__h822021 + 11'd1 ; - assign din_inc___2_exp__h831755 = _theResult___fst_exp__h830854 + 11'd1 ; - assign enabled_ints___1__h920757 = pend_ints__h920230 & y__h920769 ; - assign enabled_ints__h920803 = - pend_ints__h920230 & - { r1__read_BITS_13_TO_0___h920779, csrf_mideleg_1_0_reg } ; - assign f1_exp14899_MINUS_127__q148 = f1_exp__h714899 - 8'd127 ; - assign f1_exp__h714899 = + assign din_inc___2_exp__h611596 = _theResult___fst_exp__h584563 + 8'd1 ; + assign din_inc___2_exp__h611620 = _theResult___fst_exp__h593219 + 8'd1 ; + assign din_inc___2_exp__h611650 = _theResult___fst_exp__h602329 + 8'd1 ; + assign din_inc___2_exp__h611674 = _theResult___fst_exp__h611014 + 8'd1 ; + assign din_inc___2_exp__h657345 = _theResult___fst_exp__h630312 + 8'd1 ; + assign din_inc___2_exp__h657369 = _theResult___fst_exp__h638968 + 8'd1 ; + assign din_inc___2_exp__h657399 = _theResult___fst_exp__h648078 + 8'd1 ; + assign din_inc___2_exp__h657423 = _theResult___fst_exp__h656763 + 8'd1 ; + assign din_inc___2_exp__h703092 = _theResult___fst_exp__h676059 + 8'd1 ; + assign din_inc___2_exp__h703116 = _theResult___fst_exp__h684715 + 8'd1 ; + assign din_inc___2_exp__h703146 = _theResult___fst_exp__h693825 + 8'd1 ; + assign din_inc___2_exp__h703170 = _theResult___fst_exp__h702510 + 8'd1 ; + assign din_inc___2_exp__h753534 = _theResult___fst_exp__h734284 + 11'd1 ; + assign din_inc___2_exp__h753569 = _theResult___fst_exp__h743861 + 11'd1 ; + assign din_inc___2_exp__h753595 = _theResult___fst_exp__h752694 + 11'd1 ; + assign din_inc___2_exp__h792387 = _theResult___fst_exp__h773137 + 11'd1 ; + assign din_inc___2_exp__h792422 = _theResult___fst_exp__h782714 + 11'd1 ; + assign din_inc___2_exp__h792448 = _theResult___fst_exp__h791547 + 11'd1 ; + assign din_inc___2_exp__h831691 = _theResult___fst_exp__h812441 + 11'd1 ; + assign din_inc___2_exp__h831726 = _theResult___fst_exp__h822018 + 11'd1 ; + assign din_inc___2_exp__h831752 = _theResult___fst_exp__h830851 + 11'd1 ; + assign enabled_ints___1__h920755 = pend_ints__h920228 & y__h920767 ; + assign enabled_ints__h920801 = + pend_ints__h920228 & + { r1__read_BITS_13_TO_0___h920777, csrf_mideleg_1_0_reg } ; + assign f1_exp14896_MINUS_127__q148 = f1_exp__h714896 - 8'd127 ; + assign f1_exp__h714896 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] : 8'd255 ; - assign f1_sfd__h714900 = + assign f1_sfd__h714897 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] : 23'd4194304 ; - assign f2_exp53893_MINUS_127__q188 = f2_exp__h753893 - 8'd127 ; - assign f2_exp__h753893 = + assign f2_exp53890_MINUS_127__q188 = f2_exp__h753890 - 8'd127 ; + assign f2_exp__h753890 = (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] : 8'd255 ; - assign f2_sfd__h753894 = + assign f2_sfd__h753891 = (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] : 23'd4194304 ; - assign f3_exp93197_MINUS_127__q165 = f3_exp__h793197 - 8'd127 ; - assign f3_exp__h793197 = + assign f3_exp93194_MINUS_127__q165 = f3_exp__h793194 - 8'd127 ; + assign f3_exp__h793194 = (coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] : 8'd255 ; - assign f3_sfd__h793198 = + assign f3_sfd__h793195 = (coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] : 23'd4194304 ; - assign f_csr_reqs_first__3969_BITS_63_TO_14_4122_XOR__ETC___d24136 = - (highOffsetBits__h1031424 == 50'd0 && - IF_f_csr_reqs_first__3969_BIT_63_4123_THEN_NOT_ETC___d24133 || - NOT_csrf_stcc_reg_read__6046_BITS_33_TO_28_606_ETC___d22739) && + assign f_csr_reqs_first__3971_BITS_63_TO_14_4124_XOR__ETC___d24138 = + (highOffsetBits__h1031458 == 50'd0 && + IF_f_csr_reqs_first__3971_BIT_63_4125_THEN_NOT_ETC___d24135 || + NOT_csrf_stcc_reg_read__6046_BITS_33_TO_28_606_ETC___d22741) && csrf_stcc_reg[152] ; - assign f_csr_reqs_first__3969_BITS_63_TO_14_4122_XOR__ETC___d24158 = - (highOffsetBits__h1031827 == 50'd0 && - IF_f_csr_reqs_first__3969_BIT_63_4123_THEN_NOT_ETC___d24155 || - NOT_IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN__ETC___d23177) && + assign f_csr_reqs_first__3971_BITS_63_TO_14_4124_XOR__ETC___d24160 = + (highOffsetBits__h1031861 == 50'd0 && + IF_f_csr_reqs_first__3971_BIT_63_4125_THEN_NOT_ETC___d24157 || + NOT_IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN__ETC___d23179) && IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16810 ; - assign f_csr_reqs_first__3969_BITS_63_TO_14_4122_XOR__ETC___d24216 = - (highOffsetBits__h1032244 == 50'd0 && - IF_f_csr_reqs_first__3969_BIT_63_4123_THEN_NOT_ETC___d24213 || - NOT_csrf_mtcc_reg_read__6198_BITS_33_TO_28_621_ETC___d22810) && + assign f_csr_reqs_first__3971_BITS_63_TO_14_4124_XOR__ETC___d24218 = + (highOffsetBits__h1032278 == 50'd0 && + IF_f_csr_reqs_first__3971_BIT_63_4125_THEN_NOT_ETC___d24215 || + NOT_csrf_mtcc_reg_read__6198_BITS_33_TO_28_621_ETC___d22812) && csrf_mtcc_reg[152] ; - assign f_csr_reqs_first__3969_BITS_63_TO_14_4122_XOR__ETC___d24236 = - (highOffsetBits__h1032647 == 50'd0 && - IF_f_csr_reqs_first__3969_BIT_63_4123_THEN_NOT_ETC___d24233 || - NOT_IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN__ETC___d23314) && + assign f_csr_reqs_first__3971_BITS_63_TO_14_4124_XOR__ETC___d24238 = + (highOffsetBits__h1032681 == 50'd0 && + IF_f_csr_reqs_first__3971_BIT_63_4125_THEN_NOT_ETC___d24235 || + NOT_IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN__ETC___d23316) && IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16818 ; - assign f_csr_reqs_first__3969_BITS_63_TO_14_4122_XOR__ETC___d24307 = - (highOffsetBits__h1033314 == 50'd0 && - IF_f_csr_reqs_first__3969_BIT_63_4123_THEN_NOT_ETC___d24304 || - NOT_csrf_rg_dpc_read__6343_BITS_33_TO_28_6360__ETC___d23427) && + assign f_csr_reqs_first__3971_BITS_63_TO_14_4124_XOR__ETC___d24309 = + (highOffsetBits__h1033348 == 50'd0 && + IF_f_csr_reqs_first__3971_BIT_63_4125_THEN_NOT_ETC___d24306 || + NOT_csrf_rg_dpc_read__6343_BITS_33_TO_28_6360__ETC___d23429) && csrf_rg_dpc[152] ; - assign f_csr_rsps_i_notFull__3967_AND_f_csr_reqs_firs_ETC___d24072 = + assign f_csr_rsps_i_notFull__3969_AND_f_csr_reqs_firs_ETC___d24074 = f_csr_rsps$FULL_N && (f_csr_reqs$D_OUT[75:64] != 12'd2049 || csrf_stats_module_writeQ$FULL_N) && (f_csr_reqs$D_OUT[75:64] != 12'd2048 || csrf_terminate_module_terminateQ$FULL_N) ; - assign fcsr_csr__read__h849219 = { 56'd0, x__h853092 } ; + assign fcsr_csr__read__h849218 = { 56'd0, x__h853091 } ; assign fetchStage_RDY_pipelines_0_first__0253_AND_fet_ETC___d21254 = fetchStage$RDY_pipelines_0_first && fetchStage$pipelines_1_first[268:266] == 3'd1 && @@ -36164,104 +36156,104 @@ module mkCore(CLK, assign fetchStage_pipelines_1_first__0265_BIT_180_145_ETC___d21553 = { fetchStage$pipelines_1_first[180], CASE_fetchStagepipelines_1_first_BITS_179_TO__ETC__q259 } ; - assign fflags__h1016316 = - NOT_rob_deqPort_0_canDeq__3598_3599_OR_rob_deq_ETC___d23818 ? - y_avValue_snd_fst__h1016376 : - IF_rob_deqPort_0_canDeq__3598_THEN_IF_NOT_rob__ETC___d23825 ; - assign fflags_csr__read__h849194 = { 59'd0, csrf_fflags_reg } ; - assign frm_csr__read__h849205 = { 61'd0, csrf_frm_reg } ; - assign guard__h576464 = - { IF_sfdin84559_BIT_33_THEN_2_ELSE_0__q41[1], - { sfdin__h584559[32:0], 23'd0 } != 56'd0 } ; - assign guard__h585173 = - { IF_theResult___snd93172_BIT_33_THEN_2_ELSE_0__q43[1], - { _theResult___snd__h593172[32:0], 23'd0 } != 56'd0 } ; - assign guard__h594103 = - { IF_sfdin02325_BIT_33_THEN_2_ELSE_0__q51[1], - { sfdin__h602325[32:0], 23'd0 } != 56'd0 } ; - assign guard__h594701 = x__h594803 != 57'd0 ; - assign guard__h602939 = - { IF_theResult___snd10962_BIT_33_THEN_2_ELSE_0__q56[1], - { _theResult___snd__h610962[32:0], 23'd0 } != 56'd0 } ; - assign guard__h622215 = - { IF_sfdin30308_BIT_33_THEN_2_ELSE_0__q76[1], - { sfdin__h630308[32:0], 23'd0 } != 56'd0 } ; - assign guard__h630922 = - { IF_theResult___snd38921_BIT_33_THEN_2_ELSE_0__q78[1], - { _theResult___snd__h638921[32:0], 23'd0 } != 56'd0 } ; - assign guard__h639852 = - { IF_sfdin48074_BIT_33_THEN_2_ELSE_0__q86[1], - { sfdin__h648074[32:0], 23'd0 } != 56'd0 } ; - assign guard__h640450 = x__h640552 != 57'd0 ; - assign guard__h648688 = - { IF_theResult___snd56711_BIT_33_THEN_2_ELSE_0__q91[1], - { _theResult___snd__h656711[32:0], 23'd0 } != 56'd0 } ; - assign guard__h667962 = - { IF_sfdin76055_BIT_33_THEN_2_ELSE_0__q111[1], - { sfdin__h676055[32:0], 23'd0 } != 56'd0 } ; - assign guard__h676669 = - { IF_theResult___snd84668_BIT_33_THEN_2_ELSE_0__q113[1], - { _theResult___snd__h684668[32:0], 23'd0 } != 56'd0 } ; - assign guard__h685599 = - { IF_sfdin93821_BIT_33_THEN_2_ELSE_0__q121[1], - { sfdin__h693821[32:0], 23'd0 } != 56'd0 } ; - assign guard__h686197 = x__h686299 != 57'd0 ; - assign guard__h694435 = - { IF_theResult___snd02458_BIT_33_THEN_2_ELSE_0__q126[1], - { _theResult___snd__h702458[32:0], 23'd0 } != 56'd0 } ; - assign guard__h726326 = - { IF_theResult___snd34238_BIT_4_THEN_2_ELSE_0__q147[1], - { _theResult___snd__h734238[3:0], 52'd0 } != 56'd0 } ; - assign guard__h735638 = - { IF_sfdin43858_BIT_4_THEN_2_ELSE_0__q151[1], - { sfdin__h743858[3:0], 52'd0 } != 56'd0 } ; - assign guard__h736236 = x__h736336 != 57'd0 ; - assign guard__h744707 = - { IF_theResult___snd52643_BIT_4_THEN_2_ELSE_0__q154[1], - { _theResult___snd__h752643[3:0], 52'd0 } != 56'd0 } ; - assign guard__h765179 = - { IF_theResult___snd73091_BIT_4_THEN_2_ELSE_0__q187[1], - { _theResult___snd__h773091[3:0], 52'd0 } != 56'd0 } ; - assign guard__h774491 = - { IF_sfdin82711_BIT_4_THEN_2_ELSE_0__q191[1], - { sfdin__h782711[3:0], 52'd0 } != 56'd0 } ; - assign guard__h775089 = x__h775189 != 57'd0 ; - assign guard__h783560 = - { IF_theResult___snd91496_BIT_4_THEN_2_ELSE_0__q194[1], - { _theResult___snd__h791496[3:0], 52'd0 } != 56'd0 } ; - assign guard__h804483 = - { IF_theResult___snd12395_BIT_4_THEN_2_ELSE_0__q164[1], - { _theResult___snd__h812395[3:0], 52'd0 } != 56'd0 } ; - assign guard__h813795 = - { IF_sfdin22015_BIT_4_THEN_2_ELSE_0__q168[1], - { sfdin__h822015[3:0], 52'd0 } != 56'd0 } ; - assign guard__h814393 = x__h814493 != 57'd0 ; - assign guard__h822864 = - { IF_theResult___snd30800_BIT_4_THEN_2_ELSE_0__q171[1], - { _theResult___snd__h830800[3:0], 52'd0 } != 56'd0 } ; - assign highBitsfilter__h1008372 = + assign fflags__h1016351 = + NOT_rob_deqPort_0_canDeq__3600_3601_OR_rob_deq_ETC___d23820 ? + y_avValue_snd_fst__h1016411 : + IF_rob_deqPort_0_canDeq__3600_THEN_IF_NOT_rob__ETC___d23827 ; + assign fflags_csr__read__h849193 = { 59'd0, csrf_fflags_reg } ; + assign frm_csr__read__h849204 = { 61'd0, csrf_frm_reg } ; + assign guard__h576462 = + { IF_sfdin84557_BIT_33_THEN_2_ELSE_0__q41[1], + { sfdin__h584557[32:0], 23'd0 } != 56'd0 } ; + assign guard__h585171 = + { IF_theResult___snd93170_BIT_33_THEN_2_ELSE_0__q43[1], + { _theResult___snd__h593170[32:0], 23'd0 } != 56'd0 } ; + assign guard__h594101 = + { IF_sfdin02323_BIT_33_THEN_2_ELSE_0__q51[1], + { sfdin__h602323[32:0], 23'd0 } != 56'd0 } ; + assign guard__h594699 = x__h594801 != 57'd0 ; + assign guard__h602937 = + { IF_theResult___snd10960_BIT_33_THEN_2_ELSE_0__q56[1], + { _theResult___snd__h610960[32:0], 23'd0 } != 56'd0 } ; + assign guard__h622213 = + { IF_sfdin30306_BIT_33_THEN_2_ELSE_0__q76[1], + { sfdin__h630306[32:0], 23'd0 } != 56'd0 } ; + assign guard__h630920 = + { IF_theResult___snd38919_BIT_33_THEN_2_ELSE_0__q78[1], + { _theResult___snd__h638919[32:0], 23'd0 } != 56'd0 } ; + assign guard__h639850 = + { IF_sfdin48072_BIT_33_THEN_2_ELSE_0__q86[1], + { sfdin__h648072[32:0], 23'd0 } != 56'd0 } ; + assign guard__h640448 = x__h640550 != 57'd0 ; + assign guard__h648686 = + { IF_theResult___snd56709_BIT_33_THEN_2_ELSE_0__q91[1], + { _theResult___snd__h656709[32:0], 23'd0 } != 56'd0 } ; + assign guard__h667960 = + { IF_sfdin76053_BIT_33_THEN_2_ELSE_0__q111[1], + { sfdin__h676053[32:0], 23'd0 } != 56'd0 } ; + assign guard__h676667 = + { IF_theResult___snd84666_BIT_33_THEN_2_ELSE_0__q113[1], + { _theResult___snd__h684666[32:0], 23'd0 } != 56'd0 } ; + assign guard__h685597 = + { IF_sfdin93819_BIT_33_THEN_2_ELSE_0__q121[1], + { sfdin__h693819[32:0], 23'd0 } != 56'd0 } ; + assign guard__h686195 = x__h686297 != 57'd0 ; + assign guard__h694433 = + { IF_theResult___snd02456_BIT_33_THEN_2_ELSE_0__q126[1], + { _theResult___snd__h702456[32:0], 23'd0 } != 56'd0 } ; + assign guard__h726323 = + { IF_theResult___snd34235_BIT_4_THEN_2_ELSE_0__q147[1], + { _theResult___snd__h734235[3:0], 52'd0 } != 56'd0 } ; + assign guard__h735635 = + { IF_sfdin43855_BIT_4_THEN_2_ELSE_0__q151[1], + { sfdin__h743855[3:0], 52'd0 } != 56'd0 } ; + assign guard__h736233 = x__h736333 != 57'd0 ; + assign guard__h744704 = + { IF_theResult___snd52640_BIT_4_THEN_2_ELSE_0__q154[1], + { _theResult___snd__h752640[3:0], 52'd0 } != 56'd0 } ; + assign guard__h765176 = + { IF_theResult___snd73088_BIT_4_THEN_2_ELSE_0__q187[1], + { _theResult___snd__h773088[3:0], 52'd0 } != 56'd0 } ; + assign guard__h774488 = + { IF_sfdin82708_BIT_4_THEN_2_ELSE_0__q191[1], + { sfdin__h782708[3:0], 52'd0 } != 56'd0 } ; + assign guard__h775086 = x__h775186 != 57'd0 ; + assign guard__h783557 = + { IF_theResult___snd91493_BIT_4_THEN_2_ELSE_0__q194[1], + { _theResult___snd__h791493[3:0], 52'd0 } != 56'd0 } ; + assign guard__h804480 = + { IF_theResult___snd12392_BIT_4_THEN_2_ELSE_0__q164[1], + { _theResult___snd__h812392[3:0], 52'd0 } != 56'd0 } ; + assign guard__h813792 = + { IF_sfdin22012_BIT_4_THEN_2_ELSE_0__q168[1], + { sfdin__h822012[3:0], 52'd0 } != 56'd0 } ; + assign guard__h814390 = x__h814490 != 57'd0 ; + assign guard__h822861 = + { IF_theResult___snd30797_BIT_4_THEN_2_ELSE_0__q171[1], + { _theResult___snd__h830797[3:0], 52'd0 } != 56'd0 } ; + assign highBitsfilter__h1008407 = 50'h3FFFFFFFFFFFF << csrf_stcc_reg[33:28] ; - assign highBitsfilter__h1008775 = + assign highBitsfilter__h1008810 = 50'h3FFFFFFFFFFFF << IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16100 ; - assign highBitsfilter__h1009192 = + assign highBitsfilter__h1009227 = 50'h3FFFFFFFFFFFF << csrf_mtcc_reg[33:28] ; - assign highBitsfilter__h1009595 = + assign highBitsfilter__h1009630 = 50'h3FFFFFFFFFFFF << IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16252 ; - assign highBitsfilter__h1010264 = 50'h3FFFFFFFFFFFF << csrf_rg_dpc[33:28] ; - assign highOffsetBits__h1008373 = x__h1008400 & highBitsfilter__h1008372 ; - assign highOffsetBits__h1008776 = x__h1008400 & highBitsfilter__h1008775 ; - assign highOffsetBits__h1009193 = x__h1008400 & highBitsfilter__h1009192 ; - assign highOffsetBits__h1009596 = x__h1008400 & highBitsfilter__h1009595 ; - assign highOffsetBits__h1010265 = x__h1008400 & highBitsfilter__h1010264 ; - assign highOffsetBits__h1031424 = x__h1031451 & highBitsfilter__h1008372 ; - assign highOffsetBits__h1031827 = x__h1031451 & highBitsfilter__h1008775 ; - assign highOffsetBits__h1032244 = x__h1031451 & highBitsfilter__h1009192 ; - assign highOffsetBits__h1032647 = x__h1031451 & highBitsfilter__h1009595 ; - assign highOffsetBits__h1033314 = x__h1031451 & highBitsfilter__h1010264 ; - assign highOffsetBits__h242647 = x__h242674 & mask__h239865 ; - assign idx__h968880 = + assign highBitsfilter__h1010299 = 50'h3FFFFFFFFFFFF << csrf_rg_dpc[33:28] ; + assign highOffsetBits__h1008408 = x__h1008435 & highBitsfilter__h1008407 ; + assign highOffsetBits__h1008811 = x__h1008435 & highBitsfilter__h1008810 ; + assign highOffsetBits__h1009228 = x__h1008435 & highBitsfilter__h1009227 ; + assign highOffsetBits__h1009631 = x__h1008435 & highBitsfilter__h1009630 ; + assign highOffsetBits__h1010300 = x__h1008435 & highBitsfilter__h1010299 ; + assign highOffsetBits__h1031458 = x__h1031485 & highBitsfilter__h1008407 ; + assign highOffsetBits__h1031861 = x__h1031485 & highBitsfilter__h1008810 ; + assign highOffsetBits__h1032278 = x__h1031485 & highBitsfilter__h1009227 ; + assign highOffsetBits__h1032681 = x__h1031485 & highBitsfilter__h1009630 ; + assign highOffsetBits__h1033348 = x__h1031485 & highBitsfilter__h1010299 ; + assign highOffsetBits__h242644 = x__h242671 & mask__h239862 ; + assign idx__h968878 = fetchStage$pipelines_0_canDeq && NOT_fetchStage_pipelines_0_first__0256_BITS_26_ETC___d21652 || !coreFix_aluExe_0_rsAlu$canEnq || @@ -36269,91 +36261,91 @@ module mkCore(CLK, fetchStage_pipelines_0_first__0256_BITS_268_TO_ETC___d21675) && coreFix_aluExe_1_rsAlu$canEnq && !coreFix_aluExe_0_rsAlu_approximateCount__1196__ETC___d21198 ; - assign impliedTopBits__h127434 = x__h127518 + len_correction__h127433 ; - assign impliedTopBits__h140350 = x__h140434 + len_correction__h140349 ; - assign impliedTopBits__h183612 = x__h183696 + len_correction__h183611 ; - assign impliedTopBits__h202363 = x__h202447 + len_correction__h202362 ; - assign impliedTopBits__h216929 = x__h217013 + len_correction__h216928 ; - assign impliedTopBits__h866991 = x__h867076 + len_correction__h866990 ; - assign impliedTopBits__h867539 = x__h867624 + len_correction__h867538 ; - assign impliedTopBits__h906677 = x__h906762 + len_correction__h906676 ; - assign impliedTopBits__h907225 = x__h907310 + len_correction__h907224 ; - assign impliedTopBits__h995042 = x__h995126 + len_correction__h995041 ; - assign in__h239804 = coreFix_memExe_regToExeQ$first[383:318] & y__h239821 ; - assign in__h240961 = coreFix_memExe_regToExeQ$first[220:155] & y__h240978 ; - assign in__h254585 = coreFix_memExe_dTlb$procResp[452:387] & y__h254602 ; - assign in__h854154 = csrf_stcc_reg[151:86] & y__h854171 ; - assign in__h854459 = + assign impliedTopBits__h127433 = x__h127517 + len_correction__h127432 ; + assign impliedTopBits__h140349 = x__h140433 + len_correction__h140348 ; + assign impliedTopBits__h183610 = x__h183694 + len_correction__h183609 ; + assign impliedTopBits__h202361 = x__h202445 + len_correction__h202360 ; + assign impliedTopBits__h216927 = x__h217011 + len_correction__h216926 ; + assign impliedTopBits__h866990 = x__h867075 + len_correction__h866989 ; + assign impliedTopBits__h867538 = x__h867623 + len_correction__h867537 ; + assign impliedTopBits__h906675 = x__h906760 + len_correction__h906674 ; + assign impliedTopBits__h907223 = x__h907308 + len_correction__h907222 ; + assign impliedTopBits__h995040 = x__h995124 + len_correction__h995039 ; + assign in__h239801 = coreFix_memExe_regToExeQ$first[383:318] & y__h239818 ; + assign in__h240958 = coreFix_memExe_regToExeQ$first[220:155] & y__h240975 ; + assign in__h254582 = coreFix_memExe_dTlb$procResp[452:387] & y__h254599 ; + assign in__h854153 = csrf_stcc_reg[151:86] & y__h854170 ; + assign in__h854458 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16104 & - y__h854476 ; - assign in__h855147 = csrf_mtcc_reg[151:86] & y__h855164 ; - assign in__h855451 = + y__h854475 ; + assign in__h855146 = csrf_mtcc_reg[151:86] & y__h855163 ; + assign in__h855450 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16256 & - y__h855468 ; - assign in__h855977 = csrf_rg_dpc[151:86] & y__h855994 ; - assign in__h997656 = pc_address__h994739 & y__h997673 ; - assign k__h945030 = + y__h855467 ; + assign in__h855976 = csrf_rg_dpc[151:86] & y__h855993 ; + assign in__h997691 = pc_address__h994737 & y__h997708 ; + assign k__h945028 = !coreFix_aluExe_0_rsAlu$canEnq || coreFix_aluExe_1_rsAlu$canEnq && !coreFix_aluExe_0_rsAlu_approximateCount__1196__ETC___d21198 ; - assign len_correction__h127433 = + assign len_correction__h127432 = INV_coreFix_memExe_respLrScAmoQ_data_0_BITS_10_ETC__q8[0] ? 2'b01 : 2'b0 ; - assign len_correction__h140349 = + assign len_correction__h140348 = INV_mmio_dataRespQ_data_0_BITS_108_TO_90__q9[0] ? 2'b01 : 2'b0 ; - assign len_correction__h183611 = - INV_x83399_BITS_108_TO_90__q34[0] ? 2'b01 : 2'b0 ; - assign len_correction__h202362 = - INV_x99251_BITS_108_TO_90__q36[0] ? 2'b01 : 2'b0 ; - assign len_correction__h216928 = + assign len_correction__h183609 = + INV_x83397_BITS_108_TO_90__q34[0] ? 2'b01 : 2'b0 ; + assign len_correction__h202360 = + INV_x99249_BITS_108_TO_90__q36[0] ? 2'b01 : 2'b0 ; + assign len_correction__h216926 = INV_coreFix_memExe_lsqrespLd_BITS_108_TO_90__q10[0] ? 2'b01 : 2'b0 ; - assign len_correction__h866990 = + assign len_correction__h866989 = INV_coreFix_aluExe_1_regToExeQfirst_BITS_286__ETC__q11[0] ? 2'b01 : 2'b0 ; - assign len_correction__h867538 = + assign len_correction__h867537 = INV_coreFix_aluExe_1_regToExeQfirst_BITS_157__ETC__q12[0] ? 2'b01 : 2'b0 ; - assign len_correction__h906676 = + assign len_correction__h906674 = INV_coreFix_aluExe_0_regToExeQfirst_BITS_286__ETC__q13[0] ? 2'b01 : 2'b0 ; - assign len_correction__h907224 = + assign len_correction__h907222 = INV_coreFix_aluExe_0_regToExeQfirst_BITS_157__ETC__q14[0] ? 2'b01 : 2'b0 ; - assign len_correction__h995041 = - INV_commitStage_commitTrap_BITS_217_TO_199__q15[0] ? + assign len_correction__h995039 = + INV_commitStage_commitTrap_BITS_217_TO_199__q16[0] ? 2'b01 : 2'b0 ; - assign mask__h1000157 = 64'hFFFFFFFFFFFFFFFF << x__h1000218 ; - assign mask__h239865 = + assign mask__h1000192 = 64'hFFFFFFFFFFFFFFFF << x__h1000253 ; + assign mask__h239862 = 50'h3FFFFFFFFFFFF << coreFix_memExe_regToExeQ$first[265:260] ; - assign mask__h239974 = + assign mask__h239971 = 52'hFFFFFFFFFFFFF << coreFix_memExe_regToExeQ$first[265:260] ; - assign mask__h241022 = + assign mask__h241019 = 50'h3FFFFFFFFFFFF << coreFix_memExe_regToExeQ$first[102:97] ; - assign mask__h241131 = + assign mask__h241128 = 52'hFFFFFFFFFFFFF << coreFix_memExe_regToExeQ$first[102:97] ; - assign mask__h254646 = + assign mask__h254643 = 50'h3FFFFFFFFFFFF << coreFix_memExe_dTlb$procResp[334:329] ; - assign mask__h254755 = + assign mask__h254752 = 52'hFFFFFFFFFFFFF << coreFix_memExe_dTlb$procResp[334:329] ; - assign mask__h999500 = 64'hFFFFFFFFFFFFFFFF << x__h999561 ; - assign mcause_csr__read__h850886 = - { r1__read__h855501, csrf_mcause_code_reg } ; - assign mcounteren_csr__read__h850620 = - { r1__read__h855197, csrf_mcounteren_cy_reg } ; - assign medeleg_csr__read__h850223 = - { r1__read__h854874, csrf_medeleg_9_0_reg } ; - assign mideleg_csr__read__h850321 = - { r1__read__h854897, csrf_mideleg_1_0_reg } ; - assign mie_csr__read__h850448 = { r1__read__h854921, 1'b0 } ; - assign mip_csr__read__h851125 = { r1__read__h855508, 1'b0 } ; + assign mask__h999535 = 64'hFFFFFFFFFFFFFFFF << x__h999596 ; + assign mcause_csr__read__h850885 = + { r1__read__h855500, csrf_mcause_code_reg } ; + assign mcounteren_csr__read__h850619 = + { r1__read__h855196, csrf_mcounteren_cy_reg } ; + assign medeleg_csr__read__h850222 = + { r1__read__h854873, csrf_medeleg_9_0_reg } ; + assign mideleg_csr__read__h850320 = + { r1__read__h854896, csrf_mideleg_1_0_reg } ; + assign mie_csr__read__h850447 = { r1__read__h854920, 1'b0 } ; + assign mip_csr__read__h851124 = { r1__read__h855507, 1'b0 } ; assign mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d20679 = mmio_pRqQ_empty && epochManager$checkEpoch_0_check && (renameStage_rg_m_halt_req[4] || @@ -36395,56 +36387,56 @@ module mkCore(CLK, fetchStage$pipelines_0_first[273:269] != 5'd24 && fetchStage$pipelines_0_first[273:269] != 5'd25 && rg_core_run_state == 2'd2 ; - assign mstatus_csr__read__h850062 = { r1__read__h854749, csrf_ie_vec_0 } ; - assign n__read__h1014112 = + assign mstatus_csr__read__h850061 = { r1__read__h854748, csrf_ie_vec_0 } ; + assign n__read__h1014147 = csrf_minstret_ehr_data_lat_0$whas ? - upd__h1014188 : + upd__h1014223 : csrf_minstret_ehr_data_rl ; assign n__read__h7908 = csrf_mcycle_ehr_data_lat_0$whas ? upd__h7977 : csrf_mcycle_ehr_data_rl ; - assign newAddrBits__h1008555 = - { 2'd0, csrf_stcc_reg[13:0] } + { 2'd0, x__h1008496[13:0] } ; - assign newAddrBits__h1008958 = + assign newAddrBits__h1008590 = + { 2'd0, csrf_stcc_reg[13:0] } + { 2'd0, x__h1008531[13:0] } ; + assign newAddrBits__h1008993 = { 2'd0, IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16084 } + - { 2'd0, x__h1008899[13:0] } ; - assign newAddrBits__h1009375 = - { 2'd0, csrf_mtcc_reg[13:0] } + { 2'd0, x__h1009316[13:0] } ; - assign newAddrBits__h1009778 = + { 2'd0, x__h1008934[13:0] } ; + assign newAddrBits__h1009410 = + { 2'd0, csrf_mtcc_reg[13:0] } + { 2'd0, x__h1009351[13:0] } ; + assign newAddrBits__h1009813 = { 2'd0, IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16236 } + - { 2'd0, x__h1009719[13:0] } ; - assign newAddrBits__h1010447 = - { 2'd0, csrf_rg_dpc[13:0] } + { 2'd0, x__h1010388[13:0] } ; - assign newAddrBits__h1031606 = - { 2'd0, csrf_stcc_reg[13:0] } + { 2'd0, x__h1031547[13:0] } ; - assign newAddrBits__h1032009 = + { 2'd0, x__h1009754[13:0] } ; + assign newAddrBits__h1010482 = + { 2'd0, csrf_rg_dpc[13:0] } + { 2'd0, x__h1010423[13:0] } ; + assign newAddrBits__h1031640 = + { 2'd0, csrf_stcc_reg[13:0] } + { 2'd0, x__h1031581[13:0] } ; + assign newAddrBits__h1032043 = { 2'd0, IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16084 } + - { 2'd0, x__h1031950[13:0] } ; - assign newAddrBits__h1032426 = - { 2'd0, csrf_mtcc_reg[13:0] } + { 2'd0, x__h1032367[13:0] } ; - assign newAddrBits__h1032829 = + { 2'd0, x__h1031984[13:0] } ; + assign newAddrBits__h1032460 = + { 2'd0, csrf_mtcc_reg[13:0] } + { 2'd0, x__h1032401[13:0] } ; + assign newAddrBits__h1032863 = { 2'd0, IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16236 } + - { 2'd0, x__h1032770[13:0] } ; - assign newAddrBits__h1033496 = - { 2'd0, csrf_rg_dpc[13:0] } + { 2'd0, x__h1033437[13:0] } ; - assign newAddrDiff__h1000158 = - csrf_mtcc_reg_read__6198_BITS_149_TO_86_2811_A_ETC___d22814 - - (address__h999478 & mask__h1000157) ; - assign newAddrDiff__h1000502 = - csrf_mtcc_reg_read__6198_BITS_149_TO_86_2811_A_ETC___d22814 - - (base__h999443 & mask__h1000157) ; - assign newAddrDiff__h999501 = - csrf_stcc_reg_read__6046_BITS_149_TO_86_2740_A_ETC___d22743 - - (address__h999428 & mask__h999500) ; - assign newAddrDiff__h999845 = - csrf_stcc_reg_read__6046_BITS_149_TO_86_2740_A_ETC___d22743 - - (base__h999389 & mask__h999500) ; - assign new_pc__h872925 = + { 2'd0, x__h1032804[13:0] } ; + assign newAddrBits__h1033530 = + { 2'd0, csrf_rg_dpc[13:0] } + { 2'd0, x__h1033471[13:0] } ; + assign newAddrDiff__h1000193 = + csrf_mtcc_reg_read__6198_BITS_149_TO_86_2813_A_ETC___d22816 - + (address__h999513 & mask__h1000192) ; + assign newAddrDiff__h1000537 = + csrf_mtcc_reg_read__6198_BITS_149_TO_86_2813_A_ETC___d22816 - + (base__h999478 & mask__h1000192) ; + assign newAddrDiff__h999536 = + csrf_stcc_reg_read__6046_BITS_149_TO_86_2742_A_ETC___d22745 - + (address__h999463 & mask__h999535) ; + assign newAddrDiff__h999880 = + csrf_stcc_reg_read__6046_BITS_149_TO_86_2742_A_ETC___d22745 - + (base__h999424 & mask__h999535) ; + assign new_pc__h872924 = { coreFix_aluExe_1_exeToFinQ$first[460], coreFix_aluExe_1_exeToFinQ$first[379:364], coreFix_aluExe_1_exeToFinQ$first[362:361], @@ -36456,7 +36448,7 @@ module mkCore(CLK, ~IF_coreFix_aluExe_1_exeToFinQ_first__7830_BIT__ETC___d17996[2], IF_coreFix_aluExe_1_exeToFinQ_first__7830_BIT__ETC___d17996[1:0], coreFix_aluExe_1_exeToFinQ$first[457:394] } ; - assign new_pc__h912073 = + assign new_pc__h912071 = { coreFix_aluExe_0_exeToFinQ$first[460], coreFix_aluExe_0_exeToFinQ$first[379:364], coreFix_aluExe_0_exeToFinQ$first[362:361], @@ -36468,275 +36460,275 @@ module mkCore(CLK, ~IF_coreFix_aluExe_0_exeToFinQ_first__9946_BIT__ETC___d20111[2], IF_coreFix_aluExe_0_exeToFinQ_first__9946_BIT__ETC___d20111[1:0], coreFix_aluExe_0_exeToFinQ$first[457:394] } ; - assign next_deqP___1__h515613 = + assign next_deqP___1__h515611 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP == 3'd7) ? 3'd0 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP + 3'd1 ; - assign next_deqP___1__h526390 = + assign next_deqP___1__h526388 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP + 1'd1 ; - assign next_deqP___1__h533668 = + assign next_deqP___1__h533666 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP + 1'd1 ; - assign next_deqP___1__h544303 = + assign next_deqP___1__h544301 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP + 1'd1 ; - assign next_deqP___1__h557951 = coreFix_memExe_memRespLdQ_deqP + 1'd1 ; - assign next_deqP___1__h561730 = coreFix_memExe_forwardQ_deqP + 1'd1 ; - assign next_pc__h1012222 = + assign next_deqP___1__h557949 = coreFix_memExe_memRespLdQ_deqP + 1'd1 ; + assign next_deqP___1__h561728 = coreFix_memExe_forwardQ_deqP + 1'd1 ; + assign next_pc__h1012257 = (rob$deqPort_0_deq_data[196:195] == 2'd0) ? rob$deqPort_0_deq_data[160:32] : - { rob$deqPort_0_deq_data[630:566], address__h1013682 } ; - assign offset__h239700 = + { rob$deqPort_0_deq_data[630:566], address__h1013717 } ; + assign offset__h239697 = { 2'd0, coreFix_memExe_regToExeQ$first[317:304] } - - base__h239699 ; - assign offset__h240857 = + base__h239696 ; + assign offset__h240854 = { 2'd0, coreFix_memExe_regToExeQ$first[154:141] } - - base__h240856 ; - assign offset__h242628 = - { {32{coreFix_memExe_regToExeQfirst_BITS_434_TO_403__q17[31]}}, - coreFix_memExe_regToExeQfirst_BITS_434_TO_403__q17 } ; - assign offset__h254481 = - { 2'd0, coreFix_memExe_dTlb$procResp[386:373] } - base__h254480 ; - assign offset__h854221 = + base__h240853 ; + assign offset__h242625 = + { {32{coreFix_memExe_regToExeQfirst_BITS_434_TO_403__q15[31]}}, + coreFix_memExe_regToExeQfirst_BITS_434_TO_403__q15 } ; + assign offset__h254478 = + { 2'd0, coreFix_memExe_dTlb$procResp[386:373] } - base__h254477 ; + assign offset__h854220 = { 2'd0, IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16080 } - - base__h854220 ; - assign offset__h855214 = + base__h854219 ; + assign offset__h855213 = { 2'd0, IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16232 } - - base__h855213 ; - assign offset__h895976 = { 2'd0, csrf_stcc_reg[85:72] } - base__h895975 ; - assign offset__h896260 = { 2'd0, csrf_mtcc_reg[85:72] } - base__h896259 ; - assign offset__h896605 = { 2'd0, csrf_rg_dpc[85:72] } - base__h896604 ; - assign offset__h997575 = { 2'd0, pc_addrBits__h994740 } - base__h997574 ; - assign out___1_sfd__h714963 = { f1_sfd__h714900, 29'd0 } ; - assign out___1_sfd__h753957 = { f2_sfd__h753894, 29'd0 } ; - assign out___1_sfd__h793261 = { f3_sfd__h793198, 29'd0 } ; - assign out_exp__h585084 = - sfdin__h584559[34] ? - _theResult___exp__h585081 : - _theResult___fst_exp__h584565 ; - assign out_exp__h593666 = - _theResult___snd__h593172[34] ? - _theResult___exp__h593663 : - _theResult___fst_exp__h593221 ; - assign out_exp__h602850 = - sfdin__h602325[34] ? - _theResult___exp__h602847 : - _theResult___fst_exp__h602331 ; - assign out_exp__h611486 = - _theResult___snd__h610962[34] ? - _theResult___exp__h611483 : - _theResult___fst_exp__h611016 ; - assign out_exp__h630833 = - sfdin__h630308[34] ? - _theResult___exp__h630830 : - _theResult___fst_exp__h630314 ; - assign out_exp__h639415 = - _theResult___snd__h638921[34] ? - _theResult___exp__h639412 : - _theResult___fst_exp__h638970 ; - assign out_exp__h648599 = - sfdin__h648074[34] ? - _theResult___exp__h648596 : - _theResult___fst_exp__h648080 ; - assign out_exp__h657235 = - _theResult___snd__h656711[34] ? - _theResult___exp__h657232 : - _theResult___fst_exp__h656765 ; - assign out_exp__h676580 = - sfdin__h676055[34] ? - _theResult___exp__h676577 : - _theResult___fst_exp__h676061 ; - assign out_exp__h685162 = - _theResult___snd__h684668[34] ? - _theResult___exp__h685159 : - _theResult___fst_exp__h684717 ; - assign out_exp__h694346 = - sfdin__h693821[34] ? - _theResult___exp__h694343 : - _theResult___fst_exp__h693827 ; - assign out_exp__h702982 = - _theResult___snd__h702458[34] ? - _theResult___exp__h702979 : - _theResult___fst_exp__h702512 ; - assign out_exp__h734945 = - _theResult___snd__h734238[5] ? - _theResult___exp__h734942 : - _theResult___fst_exp__h734287 ; - assign out_exp__h744596 = - sfdin__h743858[5] ? - _theResult___exp__h744593 : - _theResult___fst_exp__h743864 ; - assign out_exp__h753380 = - _theResult___snd__h752643[5] ? - _theResult___exp__h753377 : - _theResult___fst_exp__h752697 ; - assign out_exp__h773798 = - _theResult___snd__h773091[5] ? - _theResult___exp__h773795 : - _theResult___fst_exp__h773140 ; - assign out_exp__h783449 = - sfdin__h782711[5] ? - _theResult___exp__h783446 : - _theResult___fst_exp__h782717 ; - assign out_exp__h792233 = - _theResult___snd__h791496[5] ? - _theResult___exp__h792230 : - _theResult___fst_exp__h791550 ; - assign out_exp__h813102 = - _theResult___snd__h812395[5] ? - _theResult___exp__h813099 : - _theResult___fst_exp__h812444 ; - assign out_exp__h822753 = - sfdin__h822015[5] ? - _theResult___exp__h822750 : - _theResult___fst_exp__h822021 ; - assign out_exp__h831537 = - _theResult___snd__h830800[5] ? - _theResult___exp__h831534 : - _theResult___fst_exp__h830854 ; - assign out_f_exp__h611862 = - (_theResult___exp__h611585 == 8'd255 && - _theResult___sfd__h611586 != 23'd0 || + base__h855212 ; + assign offset__h895974 = { 2'd0, csrf_stcc_reg[85:72] } - base__h895973 ; + assign offset__h896258 = { 2'd0, csrf_mtcc_reg[85:72] } - base__h896257 ; + assign offset__h896603 = { 2'd0, csrf_rg_dpc[85:72] } - base__h896602 ; + assign offset__h997610 = { 2'd0, pc_addrBits__h994738 } - base__h997609 ; + assign out___1_sfd__h714960 = { f1_sfd__h714897, 29'd0 } ; + assign out___1_sfd__h753954 = { f2_sfd__h753891, 29'd0 } ; + assign out___1_sfd__h793258 = { f3_sfd__h793195, 29'd0 } ; + assign out_exp__h585082 = + sfdin__h584557[34] ? + _theResult___exp__h585079 : + _theResult___fst_exp__h584563 ; + assign out_exp__h593664 = + _theResult___snd__h593170[34] ? + _theResult___exp__h593661 : + _theResult___fst_exp__h593219 ; + assign out_exp__h602848 = + sfdin__h602323[34] ? + _theResult___exp__h602845 : + _theResult___fst_exp__h602329 ; + assign out_exp__h611484 = + _theResult___snd__h610960[34] ? + _theResult___exp__h611481 : + _theResult___fst_exp__h611014 ; + assign out_exp__h630831 = + sfdin__h630306[34] ? + _theResult___exp__h630828 : + _theResult___fst_exp__h630312 ; + assign out_exp__h639413 = + _theResult___snd__h638919[34] ? + _theResult___exp__h639410 : + _theResult___fst_exp__h638968 ; + assign out_exp__h648597 = + sfdin__h648072[34] ? + _theResult___exp__h648594 : + _theResult___fst_exp__h648078 ; + assign out_exp__h657233 = + _theResult___snd__h656709[34] ? + _theResult___exp__h657230 : + _theResult___fst_exp__h656763 ; + assign out_exp__h676578 = + sfdin__h676053[34] ? + _theResult___exp__h676575 : + _theResult___fst_exp__h676059 ; + assign out_exp__h685160 = + _theResult___snd__h684666[34] ? + _theResult___exp__h685157 : + _theResult___fst_exp__h684715 ; + assign out_exp__h694344 = + sfdin__h693819[34] ? + _theResult___exp__h694341 : + _theResult___fst_exp__h693825 ; + assign out_exp__h702980 = + _theResult___snd__h702456[34] ? + _theResult___exp__h702977 : + _theResult___fst_exp__h702510 ; + assign out_exp__h734942 = + _theResult___snd__h734235[5] ? + _theResult___exp__h734939 : + _theResult___fst_exp__h734284 ; + assign out_exp__h744593 = + sfdin__h743855[5] ? + _theResult___exp__h744590 : + _theResult___fst_exp__h743861 ; + assign out_exp__h753377 = + _theResult___snd__h752640[5] ? + _theResult___exp__h753374 : + _theResult___fst_exp__h752694 ; + assign out_exp__h773795 = + _theResult___snd__h773088[5] ? + _theResult___exp__h773792 : + _theResult___fst_exp__h773137 ; + assign out_exp__h783446 = + sfdin__h782708[5] ? + _theResult___exp__h783443 : + _theResult___fst_exp__h782714 ; + assign out_exp__h792230 = + _theResult___snd__h791493[5] ? + _theResult___exp__h792227 : + _theResult___fst_exp__h791547 ; + assign out_exp__h813099 = + _theResult___snd__h812392[5] ? + _theResult___exp__h813096 : + _theResult___fst_exp__h812441 ; + assign out_exp__h822750 = + sfdin__h822012[5] ? + _theResult___exp__h822747 : + _theResult___fst_exp__h822018 ; + assign out_exp__h831534 = + _theResult___snd__h830797[5] ? + _theResult___exp__h831531 : + _theResult___fst_exp__h830851 ; + assign out_f_exp__h611860 = + (_theResult___exp__h611583 == 8'd255 && + _theResult___sfd__h611584 != 23'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h611576 ; - assign out_f_exp__h657611 = - (_theResult___exp__h657334 == 8'd255 && - _theResult___sfd__h657335 != 23'd0 || + _theResult___fst_exp__h611574 ; + assign out_f_exp__h657609 = + (_theResult___exp__h657332 == 8'd255 && + _theResult___sfd__h657333 != 23'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h657325 ; - assign out_f_exp__h703358 = - (_theResult___exp__h703081 == 8'd255 && - _theResult___sfd__h703082 != 23'd0 || + _theResult___fst_exp__h657323 ; + assign out_f_exp__h703356 = + (_theResult___exp__h703079 == 8'd255 && + _theResult___sfd__h703080 != 23'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h703072 ; - assign out_f_sfd__h611863 = - (_theResult___exp__h611585 == 8'd255 && - _theResult___sfd__h611586 != 23'd0) ? + _theResult___fst_exp__h703070 ; + assign out_f_sfd__h611861 = + (_theResult___exp__h611583 == 8'd255 && + _theResult___sfd__h611584 != 23'd0) ? 23'd4194304 : - _theResult___sfd__h611586 ; - assign out_f_sfd__h657612 = - (_theResult___exp__h657334 == 8'd255 && - _theResult___sfd__h657335 != 23'd0) ? + _theResult___sfd__h611584 ; + assign out_f_sfd__h657610 = + (_theResult___exp__h657332 == 8'd255 && + _theResult___sfd__h657333 != 23'd0) ? 23'd4194304 : - _theResult___sfd__h657335 ; - assign out_f_sfd__h703359 = - (_theResult___exp__h703081 == 8'd255 && - _theResult___sfd__h703082 != 23'd0) ? + _theResult___sfd__h657333 ; + assign out_f_sfd__h703357 = + (_theResult___exp__h703079 == 8'd255 && + _theResult___sfd__h703080 != 23'd0) ? 23'd4194304 : - _theResult___sfd__h703082 ; - assign out_sfd__h585085 = - sfdin__h584559[34] ? - _theResult___sfd__h585082 : - sfdin__h584559[56:34] ; - assign out_sfd__h593667 = - _theResult___snd__h593172[34] ? - _theResult___sfd__h593664 : - _theResult___snd__h593172[56:34] ; - assign out_sfd__h602851 = - sfdin__h602325[34] ? - _theResult___sfd__h602848 : - sfdin__h602325[56:34] ; - assign out_sfd__h611487 = - _theResult___snd__h610962[34] ? - _theResult___sfd__h611484 : - _theResult___snd__h610962[56:34] ; - assign out_sfd__h630834 = - sfdin__h630308[34] ? - _theResult___sfd__h630831 : - sfdin__h630308[56:34] ; - assign out_sfd__h639416 = - _theResult___snd__h638921[34] ? - _theResult___sfd__h639413 : - _theResult___snd__h638921[56:34] ; - assign out_sfd__h648600 = - sfdin__h648074[34] ? - _theResult___sfd__h648597 : - sfdin__h648074[56:34] ; - assign out_sfd__h657236 = - _theResult___snd__h656711[34] ? - _theResult___sfd__h657233 : - _theResult___snd__h656711[56:34] ; - assign out_sfd__h676581 = - sfdin__h676055[34] ? - _theResult___sfd__h676578 : - sfdin__h676055[56:34] ; - assign out_sfd__h685163 = - _theResult___snd__h684668[34] ? - _theResult___sfd__h685160 : - _theResult___snd__h684668[56:34] ; - assign out_sfd__h694347 = - sfdin__h693821[34] ? - _theResult___sfd__h694344 : - sfdin__h693821[56:34] ; - assign out_sfd__h702983 = - _theResult___snd__h702458[34] ? - _theResult___sfd__h702980 : - _theResult___snd__h702458[56:34] ; - assign out_sfd__h734946 = - _theResult___snd__h734238[5] ? - _theResult___sfd__h734943 : - _theResult___snd__h734238[56:5] ; - assign out_sfd__h744597 = - sfdin__h743858[5] ? - _theResult___sfd__h744594 : - sfdin__h743858[56:5] ; - assign out_sfd__h753381 = - _theResult___snd__h752643[5] ? - _theResult___sfd__h753378 : - _theResult___snd__h752643[56:5] ; - assign out_sfd__h773799 = - _theResult___snd__h773091[5] ? - _theResult___sfd__h773796 : - _theResult___snd__h773091[56:5] ; - assign out_sfd__h783450 = - sfdin__h782711[5] ? - _theResult___sfd__h783447 : - sfdin__h782711[56:5] ; - assign out_sfd__h792234 = - _theResult___snd__h791496[5] ? - _theResult___sfd__h792231 : - _theResult___snd__h791496[56:5] ; - assign out_sfd__h813103 = - _theResult___snd__h812395[5] ? - _theResult___sfd__h813100 : - _theResult___snd__h812395[56:5] ; - assign out_sfd__h822754 = - sfdin__h822015[5] ? - _theResult___sfd__h822751 : - sfdin__h822015[56:5] ; - assign out_sfd__h831538 = - _theResult___snd__h830800[5] ? - _theResult___sfd__h831535 : - _theResult___snd__h830800[56:5] ; - assign pc__h963242 = fetchStage$pipelines_1_first[591:463] ; - assign pc_addrBits__h994740 = - INV_commitStage_commitTrap_BITS_217_TO_199__q15[0] ? - x__h994911[13:0] : + _theResult___sfd__h703080 ; + assign out_sfd__h585083 = + sfdin__h584557[34] ? + _theResult___sfd__h585080 : + sfdin__h584557[56:34] ; + assign out_sfd__h593665 = + _theResult___snd__h593170[34] ? + _theResult___sfd__h593662 : + _theResult___snd__h593170[56:34] ; + assign out_sfd__h602849 = + sfdin__h602323[34] ? + _theResult___sfd__h602846 : + sfdin__h602323[56:34] ; + assign out_sfd__h611485 = + _theResult___snd__h610960[34] ? + _theResult___sfd__h611482 : + _theResult___snd__h610960[56:34] ; + assign out_sfd__h630832 = + sfdin__h630306[34] ? + _theResult___sfd__h630829 : + sfdin__h630306[56:34] ; + assign out_sfd__h639414 = + _theResult___snd__h638919[34] ? + _theResult___sfd__h639411 : + _theResult___snd__h638919[56:34] ; + assign out_sfd__h648598 = + sfdin__h648072[34] ? + _theResult___sfd__h648595 : + sfdin__h648072[56:34] ; + assign out_sfd__h657234 = + _theResult___snd__h656709[34] ? + _theResult___sfd__h657231 : + _theResult___snd__h656709[56:34] ; + assign out_sfd__h676579 = + sfdin__h676053[34] ? + _theResult___sfd__h676576 : + sfdin__h676053[56:34] ; + assign out_sfd__h685161 = + _theResult___snd__h684666[34] ? + _theResult___sfd__h685158 : + _theResult___snd__h684666[56:34] ; + assign out_sfd__h694345 = + sfdin__h693819[34] ? + _theResult___sfd__h694342 : + sfdin__h693819[56:34] ; + assign out_sfd__h702981 = + _theResult___snd__h702456[34] ? + _theResult___sfd__h702978 : + _theResult___snd__h702456[56:34] ; + assign out_sfd__h734943 = + _theResult___snd__h734235[5] ? + _theResult___sfd__h734940 : + _theResult___snd__h734235[56:5] ; + assign out_sfd__h744594 = + sfdin__h743855[5] ? + _theResult___sfd__h744591 : + sfdin__h743855[56:5] ; + assign out_sfd__h753378 = + _theResult___snd__h752640[5] ? + _theResult___sfd__h753375 : + _theResult___snd__h752640[56:5] ; + assign out_sfd__h773796 = + _theResult___snd__h773088[5] ? + _theResult___sfd__h773793 : + _theResult___snd__h773088[56:5] ; + assign out_sfd__h783447 = + sfdin__h782708[5] ? + _theResult___sfd__h783444 : + sfdin__h782708[56:5] ; + assign out_sfd__h792231 = + _theResult___snd__h791493[5] ? + _theResult___sfd__h792228 : + _theResult___snd__h791493[56:5] ; + assign out_sfd__h813100 = + _theResult___snd__h812392[5] ? + _theResult___sfd__h813097 : + _theResult___snd__h812392[56:5] ; + assign out_sfd__h822751 = + sfdin__h822012[5] ? + _theResult___sfd__h822748 : + sfdin__h822012[56:5] ; + assign out_sfd__h831535 = + _theResult___snd__h830797[5] ? + _theResult___sfd__h831532 : + _theResult___snd__h830797[56:5] ; + assign pc__h963240 = fetchStage$pipelines_1_first[591:463] ; + assign pc_addrBits__h994738 = + INV_commitStage_commitTrap_BITS_217_TO_199__q16[0] ? + x__h994909[13:0] : commitStage_commitTrap[122:109] ; - assign pc_address__h994739 = { 2'd0, commitStage_commitTrap[172:109] } ; - assign pend_ints__h920230 = + assign pc_address__h994737 = { 2'd0, commitStage_commitTrap[172:109] } ; + assign pend_ints__h920228 = { _0_CONCAT_csrf_external_int_en_vec_3_read__6183_ETC___d20297, csrf_software_int_en_vec_3 & csrf_software_int_pend_vec_3, 1'd0, csrf_software_int_en_vec_1 & csrf_software_int_pend_vec_1, 1'd0 } ; - assign pointer__h242638 = + assign pointer__h242635 = coreFix_memExe_regToExeQ$first[383:318] + - { 2'd0, offset__h242628 } ; - assign prv__h1017409 = csrf_prv_reg ; - assign prv__h1017453 = csrf_mprv_reg ? csrf_mpp_reg : csrf_prv_reg ; - assign q___1__h706458 = + { 2'd0, offset__h242625 } ; + assign prv__h1017444 = csrf_prv_reg ; + assign prv__h1017488 = csrf_mprv_reg ? csrf_mpp_reg : csrf_prv_reg ; + assign q___1__h706456 = 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[127:64] ; - assign r1__read_BITS_13_TO_0___h920779 = + assign r1__read_BITS_13_TO_0___h920777 = { 4'd0, csrf_mideleg_11_reg, 1'b0, @@ -36744,129 +36736,129 @@ module mkCore(CLK, 1'b0, csrf_mideleg_5_3_reg, 1'b0 } ; - assign r1__read_BITS_13_TO_12___h926454 = csrf_fs_reg ; - assign r1__read_BIT_20___h926960 = csrf_tw_reg ; - assign r1__read__h853107 = { r1__read__h853109, csrf_ie_vec_1 } ; - assign r1__read__h853109 = { r1__read__h853111, 2'b0 } ; - assign r1__read__h853111 = { r1__read__h853113, csrf_prev_ie_vec_0 } ; - assign r1__read__h853113 = { r1__read__h853115, csrf_prev_ie_vec_1 } ; - assign r1__read__h853115 = { r1__read__h853117, 2'b0 } ; - assign r1__read__h853117 = { r1__read__h853119, csrf_spp_reg } ; - assign r1__read__h853119 = { r1__read__h853121, 4'b0 } ; - assign r1__read__h853121 = { r1__read__h853123, csrf_fs_reg } ; - assign r1__read__h853123 = { r1__read__h853125, 2'd0 } ; - assign r1__read__h853125 = { r1__read__h853127, 1'b0 } ; - assign r1__read__h853127 = { r1__read__h853129, csrf_sum_reg } ; - assign r1__read__h853129 = { r1__read__h853131, csrf_mxr_reg } ; - assign r1__read__h853131 = { r1__read__h853133, 12'b0 } ; - assign r1__read__h853133 = { r1__read__h853135, 2'b10 } ; - assign r1__read__h853135 = { r__h853139, 29'b0 } ; - assign r1__read__h853511 = - { r1__read__h853513, csrf_software_int_en_vec_1 } ; - assign r1__read__h853513 = { r1__read__h853515, 2'b0 } ; - assign r1__read__h853515 = { r1__read__h853517, 1'b0 } ; - assign r1__read__h853517 = { r1__read__h853519, csrf_timer_int_en_vec_1 } ; - assign r1__read__h853519 = { r1__read__h853521, 2'b0 } ; - assign r1__read__h853521 = { r1__read__h853523, 1'b0 } ; - assign r1__read__h853523 = { 54'b0, csrf_external_int_en_vec_1 } ; - assign r1__read__h854204 = { r1__read__h854206, csrf_scounteren_tm_reg } ; - assign r1__read__h854206 = { 61'd0, csrf_scounteren_ir_reg } ; - assign r1__read__h854509 = { csrf_scause_interrupt_reg, 58'b0 } ; - assign r1__read__h854516 = - { r1__read__h854518, csrf_software_int_pend_vec_1 } ; - assign r1__read__h854518 = { r1__read__h854520, 2'b0 } ; - assign r1__read__h854520 = { r1__read__h854522, 1'b0 } ; - assign r1__read__h854522 = - { r1__read__h854524, csrf_timer_int_pend_vec_1 } ; - assign r1__read__h854524 = { r1__read__h854526, 2'b0 } ; - assign r1__read__h854526 = { r1__read__h854528, 1'b0 } ; - assign r1__read__h854528 = { 54'b0, csrf_external_int_pend_vec_1 } ; - assign r1__read__h854726 = { vm_mode_reg__read__h854732, 16'd0 } ; - assign r1__read__h854749 = { r1__read__h854751, csrf_ie_vec_1 } ; - assign r1__read__h854751 = { r1__read__h854753, 1'b0 } ; - assign r1__read__h854753 = { r1__read__h854755, csrf_ie_vec_3 } ; - assign r1__read__h854755 = { r1__read__h854757, csrf_prev_ie_vec_0 } ; - assign r1__read__h854757 = { r1__read__h854759, csrf_prev_ie_vec_1 } ; - assign r1__read__h854759 = { r1__read__h854761, 1'b0 } ; - assign r1__read__h854761 = { r1__read__h854763, csrf_prev_ie_vec_3 } ; - assign r1__read__h854763 = { r1__read__h854765, csrf_spp_reg } ; - assign r1__read__h854765 = { r1__read__h854767, 2'b0 } ; - assign r1__read__h854767 = { r1__read__h854769, csrf_mpp_reg } ; - assign r1__read__h854769 = { r1__read__h854771, csrf_fs_reg } ; - assign r1__read__h854771 = { r1__read__h854773, 2'd0 } ; - assign r1__read__h854773 = { r1__read__h854775, csrf_mprv_reg } ; - assign r1__read__h854775 = { r1__read__h854777, csrf_sum_reg } ; - assign r1__read__h854777 = { r1__read__h854779, csrf_mxr_reg } ; - assign r1__read__h854779 = { r1__read__h854781, csrf_tvm_reg } ; - assign r1__read__h854781 = { r1__read__h854783, csrf_tw_reg } ; - assign r1__read__h854783 = { r1__read__h854785, csrf_tsr_reg } ; - assign r1__read__h854785 = { r1__read__h854787, 9'b0 } ; - assign r1__read__h854787 = { r1__read__h854789, 2'b10 } ; - assign r1__read__h854789 = { r1__read__h854791, 2'b10 } ; - assign r1__read__h854791 = { r__h853139, 27'b0 } ; - assign r1__read__h854874 = { r1__read__h854876, 1'b0 } ; - assign r1__read__h854876 = { r1__read__h854878, csrf_medeleg_13_11_reg } ; - assign r1__read__h854878 = { r1__read__h854880, 1'b0 } ; - assign r1__read__h854880 = { r1__read__h854882, csrf_medeleg_15_reg } ; - assign r1__read__h854882 = { r1__read__h854884, 10'b0 } ; - assign r1__read__h854884 = { 35'b0, csrf_medeleg_28_26_reg } ; - assign r1__read__h854897 = { r1__read__h854899, 1'b0 } ; - assign r1__read__h854899 = { r1__read__h854901, csrf_mideleg_5_3_reg } ; - assign r1__read__h854901 = { r1__read__h854903, 1'b0 } ; - assign r1__read__h854903 = { r1__read__h854905, csrf_mideleg_9_7_reg } ; - assign r1__read__h854905 = { r1__read__h854907, 1'b0 } ; - assign r1__read__h854907 = { 52'b0, csrf_mideleg_11_reg } ; - assign r1__read__h854921 = - { r1__read__h854923, csrf_software_int_en_vec_1 } ; - assign r1__read__h854923 = { r1__read__h854925, 1'b0 } ; - assign r1__read__h854925 = - { r1__read__h854927, csrf_software_int_en_vec_3 } ; - assign r1__read__h854927 = { r1__read__h854929, 1'b0 } ; - assign r1__read__h854929 = { r1__read__h854931, csrf_timer_int_en_vec_1 } ; - assign r1__read__h854931 = { r1__read__h854933, 1'b0 } ; - assign r1__read__h854933 = { r1__read__h854935, csrf_timer_int_en_vec_3 } ; - assign r1__read__h854935 = { r1__read__h854937, 1'b0 } ; - assign r1__read__h854937 = - { r1__read__h854939, csrf_external_int_en_vec_1 } ; - assign r1__read__h854939 = { r1__read__h854941, 1'b0 } ; - assign r1__read__h854941 = { 52'b0, csrf_external_int_en_vec_3 } ; - assign r1__read__h855197 = { r1__read__h855199, csrf_mcounteren_tm_reg } ; - assign r1__read__h855199 = { 61'd0, csrf_mcounteren_ir_reg } ; - assign r1__read__h855501 = { csrf_mcause_interrupt_reg, 58'd0 } ; - assign r1__read__h855508 = - { r1__read__h855510, csrf_software_int_pend_vec_1 } ; - assign r1__read__h855510 = { r1__read__h855512, 1'b0 } ; - assign r1__read__h855512 = - { r1__read__h855514, csrf_software_int_pend_vec_3 } ; - assign r1__read__h855514 = { r1__read__h855516, 1'b0 } ; - assign r1__read__h855516 = - { r1__read__h855518, csrf_timer_int_pend_vec_1 } ; - assign r1__read__h855518 = { r1__read__h855520, 1'b0 } ; - assign r1__read__h855520 = - { r1__read__h855522, csrf_timer_int_pend_vec_3 } ; - assign r1__read__h855522 = { r1__read__h855524, 1'b0 } ; - assign r1__read__h855524 = - { r1__read__h855526, csrf_external_int_pend_vec_1 } ; - assign r1__read__h855526 = { r1__read__h855528, 1'b0 } ; - assign r1__read__h855528 = { 52'b0, csrf_external_int_pend_vec_3 } ; - assign r1__read__h855837 = { 4'd0, csrf_rg_tdata1_dmode } ; - assign rVal1__h714520 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; - assign rVal2__h714521 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; - assign r___1__h706484 = + assign r1__read_BITS_13_TO_12___h926452 = csrf_fs_reg ; + assign r1__read_BIT_20___h926958 = csrf_tw_reg ; + assign r1__read__h853106 = { r1__read__h853108, csrf_ie_vec_1 } ; + assign r1__read__h853108 = { r1__read__h853110, 2'b0 } ; + assign r1__read__h853110 = { r1__read__h853112, csrf_prev_ie_vec_0 } ; + assign r1__read__h853112 = { r1__read__h853114, csrf_prev_ie_vec_1 } ; + assign r1__read__h853114 = { r1__read__h853116, 2'b0 } ; + assign r1__read__h853116 = { r1__read__h853118, csrf_spp_reg } ; + assign r1__read__h853118 = { r1__read__h853120, 4'b0 } ; + assign r1__read__h853120 = { r1__read__h853122, csrf_fs_reg } ; + assign r1__read__h853122 = { r1__read__h853124, 2'd0 } ; + assign r1__read__h853124 = { r1__read__h853126, 1'b0 } ; + assign r1__read__h853126 = { r1__read__h853128, csrf_sum_reg } ; + assign r1__read__h853128 = { r1__read__h853130, csrf_mxr_reg } ; + assign r1__read__h853130 = { r1__read__h853132, 12'b0 } ; + assign r1__read__h853132 = { r1__read__h853134, 2'b10 } ; + assign r1__read__h853134 = { r__h853138, 29'b0 } ; + assign r1__read__h853510 = + { r1__read__h853512, csrf_software_int_en_vec_1 } ; + assign r1__read__h853512 = { r1__read__h853514, 2'b0 } ; + assign r1__read__h853514 = { r1__read__h853516, 1'b0 } ; + assign r1__read__h853516 = { r1__read__h853518, csrf_timer_int_en_vec_1 } ; + assign r1__read__h853518 = { r1__read__h853520, 2'b0 } ; + assign r1__read__h853520 = { r1__read__h853522, 1'b0 } ; + assign r1__read__h853522 = { 54'b0, csrf_external_int_en_vec_1 } ; + assign r1__read__h854203 = { r1__read__h854205, csrf_scounteren_tm_reg } ; + assign r1__read__h854205 = { 61'd0, csrf_scounteren_ir_reg } ; + assign r1__read__h854508 = { csrf_scause_interrupt_reg, 58'b0 } ; + assign r1__read__h854515 = + { r1__read__h854517, csrf_software_int_pend_vec_1 } ; + assign r1__read__h854517 = { r1__read__h854519, 2'b0 } ; + assign r1__read__h854519 = { r1__read__h854521, 1'b0 } ; + assign r1__read__h854521 = + { r1__read__h854523, csrf_timer_int_pend_vec_1 } ; + assign r1__read__h854523 = { r1__read__h854525, 2'b0 } ; + assign r1__read__h854525 = { r1__read__h854527, 1'b0 } ; + assign r1__read__h854527 = { 54'b0, csrf_external_int_pend_vec_1 } ; + assign r1__read__h854725 = { vm_mode_reg__read__h854731, 16'd0 } ; + assign r1__read__h854748 = { r1__read__h854750, csrf_ie_vec_1 } ; + assign r1__read__h854750 = { r1__read__h854752, 1'b0 } ; + assign r1__read__h854752 = { r1__read__h854754, csrf_ie_vec_3 } ; + assign r1__read__h854754 = { r1__read__h854756, csrf_prev_ie_vec_0 } ; + assign r1__read__h854756 = { r1__read__h854758, csrf_prev_ie_vec_1 } ; + assign r1__read__h854758 = { r1__read__h854760, 1'b0 } ; + assign r1__read__h854760 = { r1__read__h854762, csrf_prev_ie_vec_3 } ; + assign r1__read__h854762 = { r1__read__h854764, csrf_spp_reg } ; + assign r1__read__h854764 = { r1__read__h854766, 2'b0 } ; + assign r1__read__h854766 = { r1__read__h854768, csrf_mpp_reg } ; + assign r1__read__h854768 = { r1__read__h854770, csrf_fs_reg } ; + assign r1__read__h854770 = { r1__read__h854772, 2'd0 } ; + assign r1__read__h854772 = { r1__read__h854774, csrf_mprv_reg } ; + assign r1__read__h854774 = { r1__read__h854776, csrf_sum_reg } ; + assign r1__read__h854776 = { r1__read__h854778, csrf_mxr_reg } ; + assign r1__read__h854778 = { r1__read__h854780, csrf_tvm_reg } ; + assign r1__read__h854780 = { r1__read__h854782, csrf_tw_reg } ; + assign r1__read__h854782 = { r1__read__h854784, csrf_tsr_reg } ; + assign r1__read__h854784 = { r1__read__h854786, 9'b0 } ; + assign r1__read__h854786 = { r1__read__h854788, 2'b10 } ; + assign r1__read__h854788 = { r1__read__h854790, 2'b10 } ; + assign r1__read__h854790 = { r__h853138, 27'b0 } ; + assign r1__read__h854873 = { r1__read__h854875, 1'b0 } ; + assign r1__read__h854875 = { r1__read__h854877, csrf_medeleg_13_11_reg } ; + assign r1__read__h854877 = { r1__read__h854879, 1'b0 } ; + assign r1__read__h854879 = { r1__read__h854881, csrf_medeleg_15_reg } ; + assign r1__read__h854881 = { r1__read__h854883, 10'b0 } ; + assign r1__read__h854883 = { 35'b0, csrf_medeleg_28_26_reg } ; + assign r1__read__h854896 = { r1__read__h854898, 1'b0 } ; + assign r1__read__h854898 = { r1__read__h854900, csrf_mideleg_5_3_reg } ; + assign r1__read__h854900 = { r1__read__h854902, 1'b0 } ; + assign r1__read__h854902 = { r1__read__h854904, csrf_mideleg_9_7_reg } ; + assign r1__read__h854904 = { r1__read__h854906, 1'b0 } ; + assign r1__read__h854906 = { 52'b0, csrf_mideleg_11_reg } ; + assign r1__read__h854920 = + { r1__read__h854922, csrf_software_int_en_vec_1 } ; + assign r1__read__h854922 = { r1__read__h854924, 1'b0 } ; + assign r1__read__h854924 = + { r1__read__h854926, csrf_software_int_en_vec_3 } ; + assign r1__read__h854926 = { r1__read__h854928, 1'b0 } ; + assign r1__read__h854928 = { r1__read__h854930, csrf_timer_int_en_vec_1 } ; + assign r1__read__h854930 = { r1__read__h854932, 1'b0 } ; + assign r1__read__h854932 = { r1__read__h854934, csrf_timer_int_en_vec_3 } ; + assign r1__read__h854934 = { r1__read__h854936, 1'b0 } ; + assign r1__read__h854936 = + { r1__read__h854938, csrf_external_int_en_vec_1 } ; + assign r1__read__h854938 = { r1__read__h854940, 1'b0 } ; + assign r1__read__h854940 = { 52'b0, csrf_external_int_en_vec_3 } ; + assign r1__read__h855196 = { r1__read__h855198, csrf_mcounteren_tm_reg } ; + assign r1__read__h855198 = { 61'd0, csrf_mcounteren_ir_reg } ; + assign r1__read__h855500 = { csrf_mcause_interrupt_reg, 58'd0 } ; + assign r1__read__h855507 = + { r1__read__h855509, csrf_software_int_pend_vec_1 } ; + assign r1__read__h855509 = { r1__read__h855511, 1'b0 } ; + assign r1__read__h855511 = + { r1__read__h855513, csrf_software_int_pend_vec_3 } ; + assign r1__read__h855513 = { r1__read__h855515, 1'b0 } ; + assign r1__read__h855515 = + { r1__read__h855517, csrf_timer_int_pend_vec_1 } ; + assign r1__read__h855517 = { r1__read__h855519, 1'b0 } ; + assign r1__read__h855519 = + { r1__read__h855521, csrf_timer_int_pend_vec_3 } ; + assign r1__read__h855521 = { r1__read__h855523, 1'b0 } ; + assign r1__read__h855523 = + { r1__read__h855525, csrf_external_int_pend_vec_1 } ; + assign r1__read__h855525 = { r1__read__h855527, 1'b0 } ; + assign r1__read__h855527 = { 52'b0, csrf_external_int_pend_vec_3 } ; + assign r1__read__h855836 = { 4'd0, csrf_rg_tdata1_dmode } ; + assign rVal1__h714517 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; + assign rVal2__h714518 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; + assign r___1__h706482 = 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[63:0] ; - assign r__h853139 = csrf_fs_reg == 2'b11 ; - assign r__h855583 = csrf_software_int_pend_vec_3 ; - assign regRenamingTable_RDY_rename_0_claimRename__102_ETC___d21039 = - regRenamingTable$RDY_rename_0_claimRename && - fetchStage$RDY_pipelines_0_deq && + assign r__h853138 = csrf_fs_reg == 2'b11 ; + assign r__h855582 = csrf_software_int_pend_vec_3 ; + assign regRenamingTable_RDY_rename_0_getRename__1028__ETC___d21039 = + regRenamingTable$RDY_rename_0_getRename && + rob$RDY_enqPort_0_enq && fetchStage$RDY_pipelines_0_first && - epochManager$RDY_incrementEpoch && + fetchStage$RDY_pipelines_0_deq && (fetchStage$pipelines_0_first[268:266] != 3'd0 && fetchStage$pipelines_0_first[238:237] != 2'd1 && fetchStage$pipelines_0_first[238:237] != 2'd0 || coreFix_aluExe_0_rsAlu$RDY_enq) ; - assign regRenamingTable_RDY_rename_0_getRename__1027__ETC___d21854 = + assign regRenamingTable_RDY_rename_0_getRename__1028__ETC___d21854 = regRenamingTable$RDY_rename_0_getRename && CASE_fetchStagepipelines_0_first_BITS_265_TO__ETC__q269 && (fetchStage$pipelines_0_first[273:269] == 5'd19 || @@ -37059,85 +37051,85 @@ module mkCore(CLK, fetchStage$pipelines_0_first[69] || checkForException___d20654[13] || !rob$enqPort_0_canEnq ; - assign renaming_spec_bits__h968741 = + assign renaming_spec_bits__h968739 = fetchStage$pipelines_0_canDeq ? - y_avValue_snd_fst__h963385 : + y_avValue_snd_fst__h963383 : specTagManager$currentSpecBits ; - assign repBoundBits__h242653 = + assign repBoundBits__h242650 = { coreFix_memExe_regToExeQ$first[231:229], 11'd0 } ; - assign repBound__h237318 = rf$read_3_rd1[13:11] - 3'b001 ; - assign repBound__h239003 = rf$read_3_rd2[13:11] - 3'b001 ; - assign repBound__h248218 = + assign repBound__h237315 = rf$read_3_rd1[13:11] - 3'b001 ; + assign repBound__h239000 = rf$read_3_rd2[13:11] - 3'b001 ; + assign repBound__h248215 = coreFix_memExe_regToExeQ$first[245:243] - 3'b001 ; - assign repBound__h248743 = csrf_ddc_reg[13:11] - 3'b001 ; - assign repBound__h854076 = csrf_stcc_reg[13:11] - 3'b001 ; - assign repBound__h854398 = + assign repBound__h248740 = csrf_ddc_reg[13:11] - 3'b001 ; + assign repBound__h854075 = csrf_stcc_reg[13:11] - 3'b001 ; + assign repBound__h854397 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16084[13:11] - 3'b001 ; - assign repBound__h855069 = csrf_mtcc_reg[13:11] - 3'b001 ; - assign repBound__h855390 = + assign repBound__h855068 = csrf_mtcc_reg[13:11] - 3'b001 ; + assign repBound__h855389 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16236[13:11] - 3'b001 ; - assign repBound__h855899 = csrf_rg_dpc[13:11] - 3'b001 ; - assign repBound__h857577 = rf$read_1_rd1[13:11] - 3'b001 ; - assign repBound__h860539 = rf$read_1_rd2[13:11] - 3'b001 ; - assign repBound__h860557 = thin_bounds_baseBits__h860422[13:11] - 3'b001 ; - assign repBound__h867140 = x__h867079[13:11] - 3'b001 ; - assign repBound__h867688 = x__h867627[13:11] - 3'b001 ; - assign repBound__h898286 = rf$read_0_rd1[13:11] - 3'b001 ; - assign repBound__h900613 = rf$read_0_rd2[13:11] - 3'b001 ; - assign repBound__h900631 = thin_bounds_baseBits__h900516[13:11] - 3'b001 ; - assign repBound__h906826 = x__h906765[13:11] - 3'b001 ; - assign repBound__h907374 = x__h907313[13:11] - 3'b001 ; - assign repBound__h997599 = x__h995129[13:11] - 3'b001 ; - assign res_addrBits__h126823 = + assign repBound__h855898 = csrf_rg_dpc[13:11] - 3'b001 ; + assign repBound__h857576 = rf$read_1_rd1[13:11] - 3'b001 ; + assign repBound__h860538 = rf$read_1_rd2[13:11] - 3'b001 ; + assign repBound__h860556 = thin_bounds_baseBits__h860421[13:11] - 3'b001 ; + assign repBound__h867139 = x__h867078[13:11] - 3'b001 ; + assign repBound__h867687 = x__h867626[13:11] - 3'b001 ; + assign repBound__h898284 = rf$read_0_rd1[13:11] - 3'b001 ; + assign repBound__h900611 = rf$read_0_rd2[13:11] - 3'b001 ; + assign repBound__h900629 = thin_bounds_baseBits__h900514[13:11] - 3'b001 ; + assign repBound__h906824 = x__h906763[13:11] - 3'b001 ; + assign repBound__h907372 = x__h907311[13:11] - 3'b001 ; + assign repBound__h997634 = x__h995127[13:11] - 3'b001 ; + assign res_addrBits__h126822 = INV_coreFix_memExe_respLrScAmoQ_data_0_BITS_10_ETC__q8[0] ? - x__h127303[13:0] : + x__h127302[13:0] : coreFix_memExe_respLrScAmoQ_data_0[13:0] ; - assign res_addrBits__h139735 = + assign res_addrBits__h139734 = INV_mmio_dataRespQ_data_0_BITS_108_TO_90__q9[0] ? - x__h140219[13:0] : + x__h140218[13:0] : mmio_dataRespQ_data_0[13:0] ; - assign res_addrBits__h178899 = - INV_x83399_BITS_108_TO_90__q34[0] ? - x__h183481[13:0] : - x__h183399[13:0] ; - assign res_addrBits__h197664 = - INV_x99251_BITS_108_TO_90__q36[0] ? - x__h202232[13:0] : - x__h199251[13:0] ; - assign res_addrBits__h216423 = + assign res_addrBits__h178897 = + INV_x83397_BITS_108_TO_90__q34[0] ? + x__h183479[13:0] : + x__h183397[13:0] ; + assign res_addrBits__h197662 = + INV_x99249_BITS_108_TO_90__q36[0] ? + x__h202230[13:0] : + x__h199249[13:0] ; + assign res_addrBits__h216421 = INV_coreFix_memExe_lsqrespLd_BITS_108_TO_90__q10[0] ? - x__h216798[13:0] : + x__h216796[13:0] : coreFix_memExe_lsq$respLd[13:0] ; - assign res_addrBits__h235324 = { 2'b0, addr__h235317[63:52] } ; - assign res_addrBits__h567347 = + assign res_addrBits__h235321 = { 2'b0, addr__h235314[63:52] } ; + assign res_addrBits__h567344 = { 2'b0, coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[101:90] } ; - assign res_addrBits__h568199 = { 2'b0, data__h567680[63:52] } ; - assign res_addrBits__h613956 = { 2'b0, data__h613440[63:52] } ; - assign res_addrBits__h659703 = { 2'b0, data__h659187[63:52] } ; - assign res_addrBits__h705512 = { 2'b0, data__h705001[63:52] } ; - assign res_addrBits__h706372 = { 2'b0, data__h705864[63:52] } ; - assign res_addrBits__h848645 = { 2'b0, addr__h843950[63:52] } ; - assign res_addrBits__h892146 = { 2'b0, addr__h887459[63:52] } ; - assign res_address__h126822 = + assign res_addrBits__h568197 = { 2'b0, data__h567678[63:52] } ; + assign res_addrBits__h613954 = { 2'b0, data__h613438[63:52] } ; + assign res_addrBits__h659701 = { 2'b0, data__h659185[63:52] } ; + assign res_addrBits__h705510 = { 2'b0, data__h704999[63:52] } ; + assign res_addrBits__h706370 = { 2'b0, data__h705862[63:52] } ; + assign res_addrBits__h848643 = { 2'b0, addr__h843948[63:52] } ; + assign res_addrBits__h892145 = { 2'b0, addr__h887458[63:52] } ; + assign res_address__h126821 = { 2'd0, coreFix_memExe_respLrScAmoQ_data_0[63:0] } ; - assign res_address__h139734 = { 2'd0, mmio_dataRespQ_data_0[63:0] } ; - assign res_address__h178898 = { 2'd0, x__h183399[63:0] } ; - assign res_address__h197663 = { 2'd0, x__h199251[63:0] } ; - assign res_address__h216422 = { 2'd0, coreFix_memExe_lsq$respLd[63:0] } ; - assign res_address__h235323 = { 2'd0, addr__h235317 } ; - assign res_address__h567346 = + assign res_address__h139733 = { 2'd0, mmio_dataRespQ_data_0[63:0] } ; + assign res_address__h178896 = { 2'd0, x__h183397[63:0] } ; + assign res_address__h197661 = { 2'd0, x__h199249[63:0] } ; + assign res_address__h216420 = { 2'd0, coreFix_memExe_lsq$respLd[63:0] } ; + assign res_address__h235320 = { 2'd0, addr__h235314 } ; + assign res_address__h567343 = { 2'd0, coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[101:38] } ; - assign res_address__h568198 = { 2'd0, data__h567680 } ; - assign res_address__h613955 = { 2'd0, data__h613440 } ; - assign res_address__h659702 = { 2'd0, data__h659187 } ; - assign res_address__h705511 = { 2'd0, data__h705001 } ; - assign res_address__h706371 = { 2'd0, data__h705864 } ; - assign res_address__h848644 = { 2'd0, addr__h843950 } ; - assign res_address__h892145 = { 2'd0, addr__h887459 } ; - assign res_data__h568238 = { 32'hFFFFFFFF, x__h568253 } ; - assign res_data__h568243 = + assign res_address__h568196 = { 2'd0, data__h567678 } ; + assign res_address__h613953 = { 2'd0, data__h613438 } ; + assign res_address__h659700 = { 2'd0, data__h659185 } ; + assign res_address__h705509 = { 2'd0, data__h704999 } ; + assign res_address__h706369 = { 2'd0, data__h705862 } ; + assign res_address__h848642 = { 2'd0, addr__h843948 } ; + assign res_address__h892144 = { 2'd0, addr__h887458 } ; + assign res_data__h568236 = { 32'hFFFFFFFF, x__h568251 } ; + assign res_data__h568241 = { (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == @@ -37150,8 +37142,8 @@ module mkCore(CLK, 52'd0) ? 63'h7FF8000000000000 : coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:5] } ; - assign res_data__h613992 = { 32'hFFFFFFFF, x__h614007 } ; - assign res_data__h613997 = + assign res_data__h613990 = { 32'hFFFFFFFF, x__h614005 } ; + assign res_data__h613995 = { (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == @@ -37164,8 +37156,8 @@ module mkCore(CLK, 52'd0) ? 63'h7FF8000000000000 : coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:5] } ; - assign res_data__h659739 = { 32'hFFFFFFFF, x__h659754 } ; - assign res_data__h659744 = + assign res_data__h659737 = { 32'hFFFFFFFF, x__h659752 } ; + assign res_data__h659742 = { (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == @@ -37178,7 +37170,7 @@ module mkCore(CLK, 52'd0) ? 63'h7FF8000000000000 : coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:5] } ; - assign res_fflags__h568239 = + assign res_fflags__h568237 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[38:34] | coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[4:0] | { (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != @@ -37246,7 +37238,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d9383 } ; - assign res_fflags__h613993 = + assign res_fflags__h613991 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[38:34] | coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[4:0] | { (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != @@ -37314,7 +37306,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d10780 } ; - assign res_fflags__h659740 = + assign res_fflags__h659738 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[38:34] | coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[4:0] | { (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != @@ -37325,8 +37317,7 @@ module mkCore(CLK, 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && - (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != - 11'd0 || + (value_BIT_52___h677325 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d12124, @@ -37338,8 +37329,7 @@ module mkCore(CLK, 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && - (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != - 11'd0 || + (value_BIT_52___h677325 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d12135, @@ -37351,8 +37341,7 @@ module mkCore(CLK, 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && - (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != - 11'd0 || + (value_BIT_52___h677325 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d12151, @@ -37364,8 +37353,7 @@ module mkCore(CLK, 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && - (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != - 11'd0 || + (value_BIT_52___h677325 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d12164, @@ -37377,143 +37365,142 @@ module mkCore(CLK, 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && - (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != - 11'd0 || + (value_BIT_52___h677325 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d12177 } ; - assign resp_addr__h509111 = + assign resp_addr__h509110 = { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot[53:1], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getRq[168:158] } ; - assign result__h240600 = + assign result__h240597 = { 1'd0, ~coreFix_memExe_regToExeQ_first__645_BITS_383_T_ETC___d3704[64], coreFix_memExe_regToExeQ_first__645_BITS_383_T_ETC___d3704[63:0] } ; - assign result__h241757 = + assign result__h241754 = { 1'd0, ~coreFix_memExe_regToExeQ_first__645_BITS_220_T_ETC___d3766[64], coreFix_memExe_regToExeQ_first__645_BITS_220_T_ETC___d3766[63:0] } ; - assign result__h255381 = + assign result__h255378 = { 1'd0, ~coreFix_memExe_dTlb_procResp__257_BITS_452_TO__ETC___d4407[64], coreFix_memExe_dTlb_procResp__257_BITS_452_TO__ETC___d4407[63:0] } ; - assign result__h594706 = + assign result__h594704 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d8681[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d8681[0] | - guard__h594701 } ; - assign result__h640455 = + guard__h594699 } ; + assign result__h640453 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d10078[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d10078[0] | - guard__h640450 } ; - assign result__h686202 = + guard__h640448 } ; + assign result__h686200 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d11475[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d11475[0] | - guard__h686197 } ; - assign result__h736241 = + guard__h686195 } ; + assign result__h736238 = { _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d12804[56:1], _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d12804[0] | - guard__h736236 } ; - assign result__h775094 = + guard__h736233 } ; + assign result__h775091 = { _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d14289[56:1], _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d14289[0] | - guard__h775089 } ; - assign result__h814398 = + guard__h775086 } ; + assign result__h814395 = { _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d13519[56:1], _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d13519[0] | - guard__h814393 } ; - assign result__h915810 = w__h915805 & y__h915839 ; - assign result__h915861 = ~x__h915860 ; - assign result_d_addrBits__h1008567 = + guard__h814390 } ; + assign result__h915808 = w__h915803 & y__h915837 ; + assign result__h915859 = ~x__h915858 ; + assign result_d_addrBits__h1008602 = (csrf_stcc_reg[33:28] == 6'd52) ? - { 1'b0, newAddrBits__h1008555[12:0] } : - newAddrBits__h1008555[13:0] ; - assign result_d_addrBits__h1008970 = + { 1'b0, newAddrBits__h1008590[12:0] } : + newAddrBits__h1008590[13:0] ; + assign result_d_addrBits__h1009005 = (IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16100 == 6'd52) ? - { 1'b0, newAddrBits__h1008958[12:0] } : - newAddrBits__h1008958[13:0] ; - assign result_d_addrBits__h1009387 = + { 1'b0, newAddrBits__h1008993[12:0] } : + newAddrBits__h1008993[13:0] ; + assign result_d_addrBits__h1009422 = (csrf_mtcc_reg[33:28] == 6'd52) ? - { 1'b0, newAddrBits__h1009375[12:0] } : - newAddrBits__h1009375[13:0] ; - assign result_d_addrBits__h1009790 = + { 1'b0, newAddrBits__h1009410[12:0] } : + newAddrBits__h1009410[13:0] ; + assign result_d_addrBits__h1009825 = (IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16252 == 6'd52) ? - { 1'b0, newAddrBits__h1009778[12:0] } : - newAddrBits__h1009778[13:0] ; - assign result_d_addrBits__h1010459 = + { 1'b0, newAddrBits__h1009813[12:0] } : + newAddrBits__h1009813[13:0] ; + assign result_d_addrBits__h1010494 = (csrf_rg_dpc[33:28] == 6'd52) ? - { 1'b0, newAddrBits__h1010447[12:0] } : - newAddrBits__h1010447[13:0] ; - assign result_d_addrBits__h1031618 = + { 1'b0, newAddrBits__h1010482[12:0] } : + newAddrBits__h1010482[13:0] ; + assign result_d_addrBits__h1031652 = (csrf_stcc_reg[33:28] == 6'd52) ? - { 1'b0, newAddrBits__h1031606[12:0] } : - newAddrBits__h1031606[13:0] ; - assign result_d_addrBits__h1032021 = + { 1'b0, newAddrBits__h1031640[12:0] } : + newAddrBits__h1031640[13:0] ; + assign result_d_addrBits__h1032055 = (IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16100 == 6'd52) ? - { 1'b0, newAddrBits__h1032009[12:0] } : - newAddrBits__h1032009[13:0] ; - assign result_d_addrBits__h1032438 = + { 1'b0, newAddrBits__h1032043[12:0] } : + newAddrBits__h1032043[13:0] ; + assign result_d_addrBits__h1032472 = (csrf_mtcc_reg[33:28] == 6'd52) ? - { 1'b0, newAddrBits__h1032426[12:0] } : - newAddrBits__h1032426[13:0] ; - assign result_d_addrBits__h1032841 = + { 1'b0, newAddrBits__h1032460[12:0] } : + newAddrBits__h1032460[13:0] ; + assign result_d_addrBits__h1032875 = (IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16252 == 6'd52) ? - { 1'b0, newAddrBits__h1032829[12:0] } : - newAddrBits__h1032829[13:0] ; - assign result_d_addrBits__h1033508 = + { 1'b0, newAddrBits__h1032863[12:0] } : + newAddrBits__h1032863[13:0] ; + assign result_d_addrBits__h1033542 = (csrf_rg_dpc[33:28] == 6'd52) ? - { 1'b0, newAddrBits__h1033496[12:0] } : - newAddrBits__h1033496[13:0] ; - assign result_d_address__h1008566 = - { 2'd0, bot__h1008588 } + + { 1'b0, newAddrBits__h1033530[12:0] } : + newAddrBits__h1033530[13:0] ; + assign result_d_address__h1008601 = + { 2'd0, bot__h1008623 } + { 2'd0, rob$deqPort_0_deq_data[95:32] } ; - assign result_d_address__h1008969 = - { 2'd0, bot__h1008991 } + + assign result_d_address__h1009004 = + { 2'd0, bot__h1009026 } + { 2'd0, rob$deqPort_0_deq_data[95:32] } ; - assign result_d_address__h1009386 = - { 2'd0, bot__h1009408 } + + assign result_d_address__h1009421 = + { 2'd0, bot__h1009443 } + { 2'd0, rob$deqPort_0_deq_data[95:32] } ; - assign result_d_address__h1009789 = - { 2'd0, bot__h1009811 } + + assign result_d_address__h1009824 = + { 2'd0, bot__h1009846 } + { 2'd0, rob$deqPort_0_deq_data[95:32] } ; - assign result_d_address__h1010458 = - { 2'd0, bot__h1010481 } + + assign result_d_address__h1010493 = + { 2'd0, bot__h1010516 } + { 2'd0, rob$deqPort_0_deq_data[95:32] } ; - assign result_d_address__h1031617 = - { 2'd0, bot__h1008588 } + { 2'd0, f_csr_reqs$D_OUT[63:0] } ; - assign result_d_address__h1032020 = - { 2'd0, bot__h1008991 } + { 2'd0, f_csr_reqs$D_OUT[63:0] } ; - assign result_d_address__h1032437 = - { 2'd0, bot__h1009408 } + { 2'd0, f_csr_reqs$D_OUT[63:0] } ; - assign result_d_address__h1032840 = - { 2'd0, bot__h1009811 } + { 2'd0, f_csr_reqs$D_OUT[63:0] } ; - assign result_d_address__h1033507 = - { 2'd0, bot__h1010481 } + { 2'd0, f_csr_reqs$D_OUT[63:0] } ; - assign result_d_address__h242849 = { 2'd0, pointer__h242638[63:0] } ; - assign ret__h239977 = + assign result_d_address__h1031651 = + { 2'd0, bot__h1008623 } + { 2'd0, f_csr_reqs$D_OUT[63:0] } ; + assign result_d_address__h1032054 = + { 2'd0, bot__h1009026 } + { 2'd0, f_csr_reqs$D_OUT[63:0] } ; + assign result_d_address__h1032471 = + { 2'd0, bot__h1009443 } + { 2'd0, f_csr_reqs$D_OUT[63:0] } ; + assign result_d_address__h1032874 = + { 2'd0, bot__h1009846 } + { 2'd0, f_csr_reqs$D_OUT[63:0] } ; + assign result_d_address__h1033541 = + { 2'd0, bot__h1010516 } + { 2'd0, f_csr_reqs$D_OUT[63:0] } ; + assign result_d_address__h242846 = { 2'd0, pointer__h242635[63:0] } ; + assign ret__h239974 = { 1'd0, coreFix_memExe_regToExeQ_first__645_BITS_383_T_ETC___d3704[64:0] } ; - assign ret__h241134 = + assign ret__h241131 = { 1'd0, coreFix_memExe_regToExeQ_first__645_BITS_220_T_ETC___d3766[64:0] } ; - assign ret__h254758 = + assign ret__h254755 = { 1'd0, coreFix_memExe_dTlb_procResp__257_BITS_452_TO__ETC___d4407[64:0] } ; assign rf_read_0_rd1_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19097 = - rf$read_0_rd1[27:25] < repBound__h898286 ; + rf$read_0_rd1[27:25] < repBound__h898284 ; assign rf_read_0_rd1_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19110 = - rf$read_0_rd1[13:11] < repBound__h898286 ; + rf$read_0_rd1[13:11] < repBound__h898284 ; assign rf_read_0_rd1_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19124 = - rf$read_0_rd1[85:83] < repBound__h898286 ; + rf$read_0_rd1[85:83] < repBound__h898284 ; assign rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19168 = - rf$read_0_rd2[27:25] < repBound__h900613 ; + rf$read_0_rd2[27:25] < repBound__h900611 ; assign rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19169 = - rf$read_0_rd2[13:11] < repBound__h900613 ; + rf$read_0_rd2[13:11] < repBound__h900611 ; assign rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19171 = - rf$read_0_rd2[85:83] < repBound__h900613 ; + rf$read_0_rd2[85:83] < repBound__h900611 ; assign rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19181 = { rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19171, (rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19168 == @@ -37531,17 +37518,17 @@ module mkCore(CLK, 2'd1 : 2'd3) } ; assign rf_read_1_rd1_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16702 = - rf$read_1_rd1[27:25] < repBound__h857577 ; + rf$read_1_rd1[27:25] < repBound__h857576 ; assign rf_read_1_rd1_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16715 = - rf$read_1_rd1[13:11] < repBound__h857577 ; + rf$read_1_rd1[13:11] < repBound__h857576 ; assign rf_read_1_rd1_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16729 = - rf$read_1_rd1[85:83] < repBound__h857577 ; + rf$read_1_rd1[85:83] < repBound__h857576 ; assign rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16773 = - rf$read_1_rd2[27:25] < repBound__h860539 ; + rf$read_1_rd2[27:25] < repBound__h860538 ; assign rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16774 = - rf$read_1_rd2[13:11] < repBound__h860539 ; + rf$read_1_rd2[13:11] < repBound__h860538 ; assign rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16776 = - rf$read_1_rd2[85:83] < repBound__h860539 ; + rf$read_1_rd2[85:83] < repBound__h860538 ; assign rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16786 = { rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16776, (rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16773 == @@ -37559,25 +37546,25 @@ module mkCore(CLK, 2'd1 : 2'd3) } ; assign rf_read_3_rd1_coreFix_memExe_dispToRegQ_first__ETC___d3331 = - rf$read_3_rd1[27:25] < repBound__h237318 ; + rf$read_3_rd1[27:25] < repBound__h237315 ; assign rf_read_3_rd1_coreFix_memExe_dispToRegQ_first__ETC___d3344 = - rf$read_3_rd1[13:11] < repBound__h237318 ; + rf$read_3_rd1[13:11] < repBound__h237315 ; assign rf_read_3_rd1_coreFix_memExe_dispToRegQ_first__ETC___d3358 = - rf$read_3_rd1[85:83] < repBound__h237318 ; + rf$read_3_rd1[85:83] < repBound__h237315 ; assign rf_read_3_rd2_coreFix_memExe_dispToRegQ_first__ETC___d3592 = - rf$read_3_rd2[27:25] < repBound__h239003 ; + rf$read_3_rd2[27:25] < repBound__h239000 ; assign rf_read_3_rd2_coreFix_memExe_dispToRegQ_first__ETC___d3600 = - rf$read_3_rd2[13:11] < repBound__h239003 ; + rf$read_3_rd2[13:11] < repBound__h239000 ; assign rf_read_3_rd2_coreFix_memExe_dispToRegQ_first__ETC___d3609 = - rf$read_3_rd2[85:83] < repBound__h239003 ; - assign rg_core_run_state_read__0682_EQ_2_0683_AND_NOT_ETC___d23893 = + rf$read_3_rd2[85:83] < repBound__h239000 ; + assign rg_core_run_state_read__0682_EQ_2_0683_AND_NOT_ETC___d23895 = rg_core_run_state == 2'd2 && !flush_reservation && !flush_tlbs && !update_vm_info && fetchStage$iTlbIfc_flush_done && coreFix_memExe_dTlb$flush_done && !flush_caches ; - assign rg_tdata1__read__h852226 = - { r1__read__h855837, csrf_rg_tdata1_data } ; + assign rg_tdata1__read__h852225 = + { r1__read__h855836, csrf_rg_tdata1_data } ; assign rob_enqPort_1_canEnq__1634_AND_epochManager_ch_ETC___d21639 = rob$enqPort_1_canEnq && epochManager$checkEpoch_1_check && (!fetchStage$pipelines_0_canDeq || @@ -37585,9 +37572,9 @@ module mkCore(CLK, specTagManager$canClaim) && regRenamingTable_rename_0_canRename__1151_AND__ETC___d21245 && IF_IF_fetchStage_pipelines_0_first__0256_BITS__ETC___d21231) ; - assign robdeqPort_0_deq_data_BITS_95_TO_32__q16 = + assign robdeqPort_0_deq_data_BITS_95_TO_32__q17 = rob$deqPort_0_deq_data[95:32] ; - assign satp_csr__read__h849916 = { r1__read__h854726, csrf_ppn_reg } ; + assign satp_csr__read__h849915 = { r1__read__h854725, csrf_ppn_reg } ; assign sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d12442 = (sbCons$lazyLookup_2_get[2] || IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d12398 && @@ -37607,295 +37594,295 @@ module mkCore(CLK, (sbCons$lazyLookup_3_get[2] || IF_coreFix_memExe_dispToRegQ_RDY_first__685_AN_ETC___d2748 && IF_NOT_coreFix_memExe_bypassWire_0_whas__704_7_ETC___d2765) ; - assign sbIdx__h152016 = + assign sbIdx__h152015 = CAN_FIRE_RL_coreFix_memExe_doIssueSB ? coreFix_memExe_reqStQ_data_0_lat_0$wget[65:64] : coreFix_memExe_reqStQ_data_0_rl[65:64] ; - assign scause_csr__read__h849713 = - { r1__read__h854509, csrf_scause_code_reg } ; - assign scounteren_csr__read__h849573 = - { r1__read__h854204, csrf_scounteren_cy_reg } ; - assign sfd__h568849 = { value__h577076, 3'd0 } ; - assign sfd__h584657 = + assign scause_csr__read__h849712 = + { r1__read__h854508, csrf_scause_code_reg } ; + assign scounteren_csr__read__h849572 = + { r1__read__h854203, csrf_scounteren_cy_reg } ; + assign sfd__h568847 = { value__h577074, 3'd0 } ; + assign sfd__h584655 = { 1'b0, - _theResult___fst_exp__h584565 != 8'd0, - sfdin__h584559[56:34] } + + _theResult___fst_exp__h584563 != 8'd0, + sfdin__h584557[56:34] } + 25'd1 ; - assign sfd__h593239 = + assign sfd__h593237 = { 1'b0, - _theResult___fst_exp__h593221 != 8'd0, - _theResult___snd__h593172[56:34] } + + _theResult___fst_exp__h593219 != 8'd0, + _theResult___snd__h593170[56:34] } + 25'd1 ; - assign sfd__h602423 = + assign sfd__h602421 = { 1'b0, - _theResult___fst_exp__h602331 != 8'd0, - sfdin__h602325[56:34] } + + _theResult___fst_exp__h602329 != 8'd0, + sfdin__h602323[56:34] } + 25'd1 ; - assign sfd__h611035 = + assign sfd__h611033 = { 1'b0, - _theResult___fst_exp__h611016 != 8'd0, - _theResult___snd__h610962[56:34] } + + _theResult___fst_exp__h611014 != 8'd0, + _theResult___snd__h610960[56:34] } + 25'd1 ; - assign sfd__h614603 = { value__h622825, 3'd0 } ; - assign sfd__h630406 = + assign sfd__h614601 = { value__h622823, 3'd0 } ; + assign sfd__h630404 = { 1'b0, - _theResult___fst_exp__h630314 != 8'd0, - sfdin__h630308[56:34] } + + _theResult___fst_exp__h630312 != 8'd0, + sfdin__h630306[56:34] } + 25'd1 ; - assign sfd__h638988 = + assign sfd__h638986 = { 1'b0, - _theResult___fst_exp__h638970 != 8'd0, - _theResult___snd__h638921[56:34] } + + _theResult___fst_exp__h638968 != 8'd0, + _theResult___snd__h638919[56:34] } + 25'd1 ; - assign sfd__h648172 = + assign sfd__h648170 = { 1'b0, - _theResult___fst_exp__h648080 != 8'd0, - sfdin__h648074[56:34] } + + _theResult___fst_exp__h648078 != 8'd0, + sfdin__h648072[56:34] } + 25'd1 ; - assign sfd__h656784 = + assign sfd__h656782 = { 1'b0, - _theResult___fst_exp__h656765 != 8'd0, - _theResult___snd__h656711[56:34] } + + _theResult___fst_exp__h656763 != 8'd0, + _theResult___snd__h656709[56:34] } + 25'd1 ; - assign sfd__h660350 = { value__h668572, 3'd0 } ; - assign sfd__h676153 = + assign sfd__h660348 = { value__h668570, 3'd0 } ; + assign sfd__h676151 = { 1'b0, - _theResult___fst_exp__h676061 != 8'd0, - sfdin__h676055[56:34] } + + _theResult___fst_exp__h676059 != 8'd0, + sfdin__h676053[56:34] } + 25'd1 ; - assign sfd__h684735 = + assign sfd__h684733 = { 1'b0, - _theResult___fst_exp__h684717 != 8'd0, - _theResult___snd__h684668[56:34] } + + _theResult___fst_exp__h684715 != 8'd0, + _theResult___snd__h684666[56:34] } + 25'd1 ; - assign sfd__h693919 = + assign sfd__h693917 = { 1'b0, - _theResult___fst_exp__h693827 != 8'd0, - sfdin__h693821[56:34] } + + _theResult___fst_exp__h693825 != 8'd0, + sfdin__h693819[56:34] } + 25'd1 ; - assign sfd__h702531 = + assign sfd__h702529 = { 1'b0, - _theResult___fst_exp__h702512 != 8'd0, - _theResult___snd__h702458[56:34] } + + _theResult___fst_exp__h702510 != 8'd0, + _theResult___snd__h702456[56:34] } + 25'd1 ; - assign sfd__h715261 = { value__h719844, 32'd0 } ; - assign sfd__h734305 = + assign sfd__h715258 = { value__h719841, 32'd0 } ; + assign sfd__h734302 = { 1'b0, - _theResult___fst_exp__h734287 != 11'd0, - _theResult___snd__h734238[56:5] } + + _theResult___fst_exp__h734284 != 11'd0, + _theResult___snd__h734235[56:5] } + 54'd1 ; - assign sfd__h743956 = + assign sfd__h743953 = { 1'b0, - _theResult___fst_exp__h743864 != 11'd0, - sfdin__h743858[56:5] } + + _theResult___fst_exp__h743861 != 11'd0, + sfdin__h743855[56:5] } + 54'd1 ; - assign sfd__h752716 = + assign sfd__h752713 = { 1'b0, - _theResult___fst_exp__h752697 != 11'd0, - _theResult___snd__h752643[56:5] } + + _theResult___fst_exp__h752694 != 11'd0, + _theResult___snd__h752640[56:5] } + 54'd1 ; - assign sfd__h754255 = { value__h758697, 32'd0 } ; - assign sfd__h773158 = + assign sfd__h754252 = { value__h758694, 32'd0 } ; + assign sfd__h773155 = { 1'b0, - _theResult___fst_exp__h773140 != 11'd0, - _theResult___snd__h773091[56:5] } + + _theResult___fst_exp__h773137 != 11'd0, + _theResult___snd__h773088[56:5] } + 54'd1 ; - assign sfd__h782809 = + assign sfd__h782806 = { 1'b0, - _theResult___fst_exp__h782717 != 11'd0, - sfdin__h782711[56:5] } + + _theResult___fst_exp__h782714 != 11'd0, + sfdin__h782708[56:5] } + 54'd1 ; - assign sfd__h791569 = + assign sfd__h791566 = { 1'b0, - _theResult___fst_exp__h791550 != 11'd0, - _theResult___snd__h791496[56:5] } + + _theResult___fst_exp__h791547 != 11'd0, + _theResult___snd__h791493[56:5] } + 54'd1 ; - assign sfd__h793559 = { value__h798001, 32'd0 } ; - assign sfd__h812462 = + assign sfd__h793556 = { value__h797998, 32'd0 } ; + assign sfd__h812459 = { 1'b0, - _theResult___fst_exp__h812444 != 11'd0, - _theResult___snd__h812395[56:5] } + + _theResult___fst_exp__h812441 != 11'd0, + _theResult___snd__h812392[56:5] } + 54'd1 ; - assign sfd__h822113 = + assign sfd__h822110 = { 1'b0, - _theResult___fst_exp__h822021 != 11'd0, - sfdin__h822015[56:5] } + + _theResult___fst_exp__h822018 != 11'd0, + sfdin__h822012[56:5] } + 54'd1 ; - assign sfd__h830873 = + assign sfd__h830870 = { 1'b0, - _theResult___fst_exp__h830854 != 11'd0, - _theResult___snd__h830800[56:5] } + + _theResult___fst_exp__h830851 != 11'd0, + _theResult___snd__h830797[56:5] } + 54'd1 ; - assign sfdin__h584559 = - _theResult____h576454[56] ? - _theResult___snd__h584576 : - _theResult___snd__h584587 ; - assign sfdin__h602325 = - _theResult____h594093[56] ? - _theResult___snd__h602342 : - _theResult___snd__h602353 ; - assign sfdin__h630308 = - _theResult____h622205[56] ? - _theResult___snd__h630325 : - _theResult___snd__h630336 ; - assign sfdin__h648074 = - _theResult____h639842[56] ? - _theResult___snd__h648091 : - _theResult___snd__h648102 ; - assign sfdin__h676055 = - _theResult____h667952[56] ? - _theResult___snd__h676072 : - _theResult___snd__h676083 ; - assign sfdin__h693821 = - _theResult____h685589[56] ? - _theResult___snd__h693838 : - _theResult___snd__h693849 ; - assign sfdin__h743858 = - _theResult____h735628[56] ? - _theResult___snd__h743875 : - _theResult___snd__h743886 ; - assign sfdin__h782711 = - _theResult____h774481[56] ? - _theResult___snd__h782728 : - _theResult___snd__h782739 ; - assign sfdin__h822015 = - _theResult____h813785[56] ? - _theResult___snd__h822032 : - _theResult___snd__h822043 ; - assign sie_csr__read__h849485 = { r1__read__h853511, 1'b0 } ; - assign signBits__h1008370 = - {50{robdeqPort_0_deq_data_BITS_95_TO_32__q16[63]}} ; - assign signBits__h1031421 = {50{f_csr_reqs$D_OUT[63]}} ; - assign signBits__h242644 = {50{offset__h242628[63]}} ; - assign sip_csr__read__h849853 = { r1__read__h854516, 1'b0 } ; - assign spec_bits__h973792 = specTagManager$currentSpecBits | y__h973805 ; - assign sstatus_csr__read__h849415 = { r1__read__h853107, csrf_ie_vec_0 } ; - assign tb__h867137 = { impliedTopBits__h866991, topBits__h866987[11] } ; - assign tb__h867685 = { impliedTopBits__h867539, topBits__h867535[11] } ; - assign tb__h906823 = { impliedTopBits__h906677, topBits__h906673[11] } ; - assign tb__h907371 = { impliedTopBits__h907225, topBits__h907221[11] } ; - assign thin_address__h999382 = - csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22647 ? - IF_csrf_stcc_reg_read__6046_BIT_86_2736_AND_NO_ETC___d22904 : - IF_csrf_mtcc_reg_read__6198_BIT_86_2807_AND_NO_ETC___d22905 ; - assign tmpAddr__h242837 = pointer__h242638[63:0] ; - assign tmp_expBotHalf__h127296 = + assign sfdin__h584557 = + _theResult____h576452[56] ? + _theResult___snd__h584574 : + _theResult___snd__h584585 ; + assign sfdin__h602323 = + _theResult____h594091[56] ? + _theResult___snd__h602340 : + _theResult___snd__h602351 ; + assign sfdin__h630306 = + _theResult____h622203[56] ? + _theResult___snd__h630323 : + _theResult___snd__h630334 ; + assign sfdin__h648072 = + _theResult____h639840[56] ? + _theResult___snd__h648089 : + _theResult___snd__h648100 ; + assign sfdin__h676053 = + _theResult____h667950[56] ? + _theResult___snd__h676070 : + _theResult___snd__h676081 ; + assign sfdin__h693819 = + _theResult____h685587[56] ? + _theResult___snd__h693836 : + _theResult___snd__h693847 ; + assign sfdin__h743855 = + _theResult____h735625[56] ? + _theResult___snd__h743872 : + _theResult___snd__h743883 ; + assign sfdin__h782708 = + _theResult____h774478[56] ? + _theResult___snd__h782725 : + _theResult___snd__h782736 ; + assign sfdin__h822012 = + _theResult____h813782[56] ? + _theResult___snd__h822029 : + _theResult___snd__h822040 ; + assign sie_csr__read__h849484 = { r1__read__h853510, 1'b0 } ; + assign signBits__h1008405 = + {50{robdeqPort_0_deq_data_BITS_95_TO_32__q17[63]}} ; + assign signBits__h1031455 = {50{f_csr_reqs$D_OUT[63]}} ; + assign signBits__h242641 = {50{offset__h242625[63]}} ; + assign sip_csr__read__h849852 = { r1__read__h854515, 1'b0 } ; + assign spec_bits__h973790 = specTagManager$currentSpecBits | y__h973803 ; + assign sstatus_csr__read__h849414 = { r1__read__h853106, csrf_ie_vec_0 } ; + assign tb__h867136 = { impliedTopBits__h866990, topBits__h866986[11] } ; + assign tb__h867684 = { impliedTopBits__h867538, topBits__h867534[11] } ; + assign tb__h906821 = { impliedTopBits__h906675, topBits__h906671[11] } ; + assign tb__h907369 = { impliedTopBits__h907223, topBits__h907219[11] } ; + assign thin_address__h999417 = + csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22648 ? + IF_csrf_stcc_reg_read__6046_BIT_86_2738_AND_NO_ETC___d22906 : + IF_csrf_mtcc_reg_read__6198_BIT_86_2809_AND_NO_ETC___d22907 ; + assign tmpAddr__h242834 = pointer__h242635[63:0] ; + assign tmp_expBotHalf__h127295 = { ~coreFix_memExe_respLrScAmoQ_data_0[66], coreFix_memExe_respLrScAmoQ_data_0[65:64] } ; - assign tmp_expBotHalf__h140212 = + assign tmp_expBotHalf__h140211 = { ~mmio_dataRespQ_data_0[66], mmio_dataRespQ_data_0[65:64] } ; - assign tmp_expBotHalf__h183474 = { ~x__h183399[66], x__h183399[65:64] } ; - assign tmp_expBotHalf__h202225 = { ~x__h199251[66], x__h199251[65:64] } ; - assign tmp_expBotHalf__h216791 = + assign tmp_expBotHalf__h183472 = { ~x__h183397[66], x__h183397[65:64] } ; + assign tmp_expBotHalf__h202223 = { ~x__h199249[66], x__h199249[65:64] } ; + assign tmp_expBotHalf__h216789 = { ~coreFix_memExe_lsq$respLd[66], coreFix_memExe_lsq$respLd[65:64] } ; - assign tmp_expBotHalf__h866840 = + assign tmp_expBotHalf__h866839 = { ~coreFix_aluExe_1_regToExeQ$first[244], coreFix_aluExe_1_regToExeQ$first[243:242] } ; - assign tmp_expBotHalf__h867388 = + assign tmp_expBotHalf__h867387 = { ~coreFix_aluExe_1_regToExeQ$first[115], coreFix_aluExe_1_regToExeQ$first[114:113] } ; - assign tmp_expBotHalf__h906526 = + assign tmp_expBotHalf__h906524 = { ~coreFix_aluExe_0_regToExeQ$first[244], coreFix_aluExe_0_regToExeQ$first[243:242] } ; - assign tmp_expBotHalf__h907074 = + assign tmp_expBotHalf__h907072 = { ~coreFix_aluExe_0_regToExeQ$first[115], coreFix_aluExe_0_regToExeQ$first[114:113] } ; - assign tmp_expBotHalf__h994904 = + assign tmp_expBotHalf__h994902 = { ~commitStage_commitTrap[175], commitStage_commitTrap[174:173] } ; - assign tmp_expTopHalf__h127294 = + assign tmp_expTopHalf__h127293 = { ~coreFix_memExe_respLrScAmoQ_data_0[80:79], coreFix_memExe_respLrScAmoQ_data_0[78] } ; - assign tmp_expTopHalf__h140210 = + assign tmp_expTopHalf__h140209 = { ~mmio_dataRespQ_data_0[80:79], mmio_dataRespQ_data_0[78] } ; - assign tmp_expTopHalf__h183472 = { ~x__h183399[80:79], x__h183399[78] } ; - assign tmp_expTopHalf__h202223 = { ~x__h199251[80:79], x__h199251[78] } ; - assign tmp_expTopHalf__h216789 = + assign tmp_expTopHalf__h183470 = { ~x__h183397[80:79], x__h183397[78] } ; + assign tmp_expTopHalf__h202221 = { ~x__h199249[80:79], x__h199249[78] } ; + assign tmp_expTopHalf__h216787 = { ~coreFix_memExe_lsq$respLd[80:79], coreFix_memExe_lsq$respLd[78] } ; - assign tmp_expTopHalf__h866838 = + assign tmp_expTopHalf__h866837 = { ~coreFix_aluExe_1_regToExeQ$first[258:257], coreFix_aluExe_1_regToExeQ$first[256] } ; - assign tmp_expTopHalf__h867386 = + assign tmp_expTopHalf__h867385 = { ~coreFix_aluExe_1_regToExeQ$first[129:128], coreFix_aluExe_1_regToExeQ$first[127] } ; - assign tmp_expTopHalf__h906524 = + assign tmp_expTopHalf__h906522 = { ~coreFix_aluExe_0_regToExeQ$first[258:257], coreFix_aluExe_0_regToExeQ$first[256] } ; - assign tmp_expTopHalf__h907072 = + assign tmp_expTopHalf__h907070 = { ~coreFix_aluExe_0_regToExeQ$first[129:128], coreFix_aluExe_0_regToExeQ$first[127] } ; - assign tmp_expTopHalf__h994902 = + assign tmp_expTopHalf__h994900 = { ~commitStage_commitTrap[189:188], commitStage_commitTrap[187] } ; - assign toBoundsM1__h1008383 = { 3'b110, ~csrf_stcc_reg[10:0] } ; - assign toBoundsM1__h1008786 = + assign toBoundsM1__h1008418 = { 3'b110, ~csrf_stcc_reg[10:0] } ; + assign toBoundsM1__h1008821 = { 3'b110, ~IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16084[10:0] } ; - assign toBoundsM1__h1009203 = { 3'b110, ~csrf_mtcc_reg[10:0] } ; - assign toBoundsM1__h1009606 = + assign toBoundsM1__h1009238 = { 3'b110, ~csrf_mtcc_reg[10:0] } ; + assign toBoundsM1__h1009641 = { 3'b110, ~IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16236[10:0] } ; - assign toBoundsM1__h1010275 = { 3'b110, ~csrf_rg_dpc[10:0] } ; - assign toBoundsM1__h242657 = - repBoundBits__h242653 + + assign toBoundsM1__h1010310 = { 3'b110, ~csrf_rg_dpc[10:0] } ; + assign toBoundsM1__h242654 = + repBoundBits__h242650 + ~coreFix_memExe_regToExeQ$first[317:304] ; - assign toBounds__h1008382 = 14'd14336 - { 3'b0, csrf_stcc_reg[10:0] } ; - assign toBounds__h1008785 = + assign toBounds__h1008417 = 14'd14336 - { 3'b0, csrf_stcc_reg[10:0] } ; + assign toBounds__h1008820 = 14'd14336 - { 3'b0, IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16084[10:0] } ; - assign toBounds__h1009202 = 14'd14336 - { 3'b0, csrf_mtcc_reg[10:0] } ; - assign toBounds__h1009605 = + assign toBounds__h1009237 = 14'd14336 - { 3'b0, csrf_mtcc_reg[10:0] } ; + assign toBounds__h1009640 = 14'd14336 - { 3'b0, IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16236[10:0] } ; - assign toBounds__h1010274 = 14'd14336 - { 3'b0, csrf_rg_dpc[10:0] } ; - assign toBounds__h242656 = - repBoundBits__h242653 - coreFix_memExe_regToExeQ$first[317:304] ; - assign topBits__h127430 = + assign toBounds__h1010309 = 14'd14336 - { 3'b0, csrf_rg_dpc[10:0] } ; + assign toBounds__h242653 = + repBoundBits__h242650 - coreFix_memExe_regToExeQ$first[317:304] ; + assign topBits__h127429 = INV_coreFix_memExe_respLrScAmoQ_data_0_BITS_10_ETC__q8[0] ? { coreFix_memExe_respLrScAmoQ_data_0[89:81], 3'd0 } : - b_top__h127527 ; - assign topBits__h140346 = + b_top__h127526 ; + assign topBits__h140345 = INV_mmio_dataRespQ_data_0_BITS_108_TO_90__q9[0] ? { mmio_dataRespQ_data_0[89:81], 3'd0 } : - b_top__h140443 ; - assign topBits__h183608 = - INV_x83399_BITS_108_TO_90__q34[0] ? - { x__h183399[89:81], 3'd0 } : - b_top__h183705 ; - assign topBits__h202359 = - INV_x99251_BITS_108_TO_90__q36[0] ? - { x__h199251[89:81], 3'd0 } : - b_top__h202456 ; - assign topBits__h216925 = + b_top__h140442 ; + assign topBits__h183606 = + INV_x83397_BITS_108_TO_90__q34[0] ? + { x__h183397[89:81], 3'd0 } : + b_top__h183703 ; + assign topBits__h202357 = + INV_x99249_BITS_108_TO_90__q36[0] ? + { x__h199249[89:81], 3'd0 } : + b_top__h202454 ; + assign topBits__h216923 = INV_coreFix_memExe_lsqrespLd_BITS_108_TO_90__q10[0] ? { coreFix_memExe_lsq$respLd[89:81], 3'd0 } : - b_top__h217022 ; - assign topBits__h866987 = + b_top__h217020 ; + assign topBits__h866986 = INV_coreFix_aluExe_1_regToExeQfirst_BITS_286__ETC__q11[0] ? { coreFix_aluExe_1_regToExeQ$first[267:259], 3'd0 } : - b_top__h867085 ; - assign topBits__h867535 = + b_top__h867084 ; + assign topBits__h867534 = INV_coreFix_aluExe_1_regToExeQfirst_BITS_157__ETC__q12[0] ? { coreFix_aluExe_1_regToExeQ$first[138:130], 3'd0 } : - b_top__h867633 ; - assign topBits__h906673 = + b_top__h867632 ; + assign topBits__h906671 = INV_coreFix_aluExe_0_regToExeQfirst_BITS_286__ETC__q13[0] ? { coreFix_aluExe_0_regToExeQ$first[267:259], 3'd0 } : - b_top__h906771 ; - assign topBits__h907221 = + b_top__h906769 ; + assign topBits__h907219 = INV_coreFix_aluExe_0_regToExeQfirst_BITS_157__ETC__q14[0] ? { coreFix_aluExe_0_regToExeQ$first[138:130], 3'd0 } : - b_top__h907319 ; - assign topBits__h995038 = - INV_commitStage_commitTrap_BITS_217_TO_199__q15[0] ? + b_top__h907317 ; + assign topBits__h995036 = + INV_commitStage_commitTrap_BITS_217_TO_199__q16[0] ? { commitStage_commitTrap[198:190], 3'd0 } : - b_top__h995135 ; - assign trap_val__h997040 = { 53'd0, x__h998861 } ; - assign upd__h1014188 = + b_top__h995133 ; + assign trap_val__h997075 = { 53'd0, x__h998896 } ; + assign upd__h1014223 = MUX_csrf_minstret_ehr_data_lat_0$wset_1__SEL_1 ? f_csr_reqs$D_OUT[63:0] : rob$deqPort_0_deq_data[95:32] ; @@ -37908,382 +37895,385 @@ module mkCore(CLK, MUX_csrf_mcycle_ehr_data_lat_0$wset_1__SEL_1 ? f_csr_reqs$D_OUT[63:0] : rob$deqPort_0_deq_data[95:32] ; - assign v__h1012261 = + assign v__h1012296 = { csrf_sepcc_reg_data_rl[152], csrf_sepcc_reg_data_rl[71:56], csrf_sepcc_reg_data_rl[54:53], csrf_sepcc_reg_data_rl[55], - CASE_csrf_sepcc_reg_data_rl_BITS_52_TO_35_2621_ETC__q276, + CASE_csrf_sepcc_reg_data_rl_BITS_52_TO_35_2621_ETC__q278, ~csrf_sepcc_reg_data_rl[34], - IF_csrf_sepcc_reg_read_wget__3506_BIT_34_3518__ETC___d23528[25:17], - ~IF_csrf_sepcc_reg_read_wget__3506_BIT_34_3518__ETC___d23528[16:15], - IF_csrf_sepcc_reg_read_wget__3506_BIT_34_3518__ETC___d23528[14:3], - ~IF_csrf_sepcc_reg_read_wget__3506_BIT_34_3518__ETC___d23528[2], - IF_csrf_sepcc_reg_read_wget__3506_BIT_34_3518__ETC___d23528[1:0], + IF_csrf_sepcc_reg_read_wget__3508_BIT_34_3520__ETC___d23530[25:17], + ~IF_csrf_sepcc_reg_read_wget__3508_BIT_34_3520__ETC___d23530[16:15], + IF_csrf_sepcc_reg_read_wget__3508_BIT_34_3520__ETC___d23530[14:3], + ~IF_csrf_sepcc_reg_read_wget__3508_BIT_34_3520__ETC___d23530[2], + IF_csrf_sepcc_reg_read_wget__3508_BIT_34_3520__ETC___d23530[1:0], csrf_sepcc_reg_data_rl[149:86] } ; - assign v__h1012970 = + assign v__h1013005 = { csrf_mepcc_reg_data_rl[152], csrf_mepcc_reg_data_rl[71:56], csrf_mepcc_reg_data_rl[54:53], csrf_mepcc_reg_data_rl[55], - CASE_csrf_mepcc_reg_data_rl_BITS_52_TO_35_2621_ETC__q277, + CASE_csrf_mepcc_reg_data_rl_BITS_52_TO_35_2621_ETC__q279, ~csrf_mepcc_reg_data_rl[34], - IF_csrf_mepcc_reg_read_wget__3540_BIT_34_3552__ETC___d23562[25:17], - ~IF_csrf_mepcc_reg_read_wget__3540_BIT_34_3552__ETC___d23562[16:15], - IF_csrf_mepcc_reg_read_wget__3540_BIT_34_3552__ETC___d23562[14:3], - ~IF_csrf_mepcc_reg_read_wget__3540_BIT_34_3552__ETC___d23562[2], - IF_csrf_mepcc_reg_read_wget__3540_BIT_34_3552__ETC___d23562[1:0], + IF_csrf_mepcc_reg_read_wget__3542_BIT_34_3554__ETC___d23564[25:17], + ~IF_csrf_mepcc_reg_read_wget__3542_BIT_34_3554__ETC___d23564[16:15], + IF_csrf_mepcc_reg_read_wget__3542_BIT_34_3554__ETC___d23564[14:3], + ~IF_csrf_mepcc_reg_read_wget__3542_BIT_34_3554__ETC___d23564[2], + IF_csrf_mepcc_reg_read_wget__3542_BIT_34_3554__ETC___d23564[1:0], csrf_mepcc_reg_data_rl[149:86] } ; - assign v__h514824 = + assign v__h514822 = IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d7227 ? - v__h515019 : + v__h515017 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ; - assign v__h515019 = + assign v__h515017 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd7) ? 3'd0 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP + 3'd1 ; - assign v__h516844 = + assign v__h516842 = IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d7321 ? - v__h517224 : + v__h517222 : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP ; - assign v__h517224 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP + 1'd1 ; - assign v__h532563 = + assign v__h517222 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP + 1'd1 ; + assign v__h532561 = IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d7480 ? - v__h532758 : + v__h532756 : coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP ; - assign v__h532758 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP + 1'd1 ; - assign v__h535012 = + assign v__h532756 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP + 1'd1 ; + assign v__h535010 = IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d7564 ? - v__h535207 : + v__h535205 : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP ; - assign v__h535207 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP + 1'd1 ; - assign v__h556032 = + assign v__h535205 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP + 1'd1 ; + assign v__h556030 = IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d7769 ? - v__h556227 : + v__h556225 : coreFix_memExe_memRespLdQ_enqP ; - assign v__h556227 = coreFix_memExe_memRespLdQ_enqP + 1'd1 ; - assign v__h559811 = + assign v__h556225 = coreFix_memExe_memRespLdQ_enqP + 1'd1 ; + assign v__h559809 = IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d7851 ? - v__h560006 : + v__h560004 : coreFix_memExe_forwardQ_enqP ; - assign v__h560006 = coreFix_memExe_forwardQ_enqP + 1'd1 ; - assign v__h836642 = + assign v__h560004 = coreFix_memExe_forwardQ_enqP + 1'd1 ; + assign v__h836639 = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_deqEn$whas ? - v__h836652 : + v__h836649 : coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit ; - assign v__h836652 = + assign v__h836649 = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit + 2'd1 ; - assign v__h837287 = v__h836642 - 2'd1 ; - assign value__h239694 = x__h239712 | in__h239804[63:0] ; - assign value__h239858 = - { coreFix_memExe_regToExeQ$first[381:332] & mask__h239865, + assign v__h837284 = v__h836639 - 2'd1 ; + assign value_BIT_52___h677325 = + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != + 11'd0 ; + assign value__h239691 = x__h239709 | in__h239801[63:0] ; + assign value__h239855 = + { coreFix_memExe_regToExeQ$first[381:332] & mask__h239862, 14'd0 } + - addBase__h239864 ; - assign value__h240851 = x__h240869 | in__h240961[63:0] ; - assign value__h241015 = - { coreFix_memExe_regToExeQ$first[218:169] & mask__h241022, + addBase__h239861 ; + assign value__h240848 = x__h240866 | in__h240958[63:0] ; + assign value__h241012 = + { coreFix_memExe_regToExeQ$first[218:169] & mask__h241019, 14'd0 } + - addBase__h241021 ; - assign value__h254475 = x__h254493 | in__h254585[63:0] ; - assign value__h254639 = - { coreFix_memExe_dTlb$procResp[450:401] & mask__h254646, + addBase__h241018 ; + assign value__h254472 = x__h254490 | in__h254582[63:0] ; + assign value__h254636 = + { coreFix_memExe_dTlb$procResp[450:401] & mask__h254643, 14'd0 } + - addBase__h254645 ; - assign value__h577076 = + addBase__h254642 ; + assign value__h577074 = { 1'b0, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != 11'd0, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] } ; - assign value__h622825 = + assign value__h622823 = { 1'b0, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != 11'd0, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] } ; - assign value__h668572 = + assign value__h668570 = { 1'b0, - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != - 11'd0, + value_BIT_52___h677325, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] } ; - assign value__h719844 = { 1'b0, f1_exp__h714899 != 8'd0, f1_sfd__h714900 } ; - assign value__h758697 = { 1'b0, f2_exp__h753893 != 8'd0, f2_sfd__h753894 } ; - assign value__h798001 = { 1'b0, f3_exp__h793197 != 8'd0, f3_sfd__h793198 } ; - assign vm_mode_reg__read__h854732 = { csrf_vm_mode_sv39_reg, 3'b0 } ; - assign w__h915805 = + assign value__h719841 = { 1'b0, f1_exp__h714896 != 8'd0, f1_sfd__h714897 } ; + assign value__h758694 = { 1'b0, f2_exp__h753890 != 8'd0, f2_sfd__h753891 } ; + assign value__h797998 = { 1'b0, f3_exp__h793194 != 8'd0, f3_sfd__h793195 } ; + assign vm_mode_reg__read__h854731 = { csrf_vm_mode_sv39_reg, 3'b0 } ; + assign w__h915803 = coreFix_globalSpecUpdate_correctSpecTag_0$whas ? - result__h915861 : + result__h915859 : 12'd4095 ; - assign wordIdx__h263233 = + assign wordIdx__h263231 = coreFix_memExe_dMem_cache_m_banks_0_processAmo[165:164] ; - assign x1_avValue_new_pcc_capFat_bounds_baseBits__h1000887 = - csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22647 ? + assign x1_avValue_new_pcc_capFat_bounds_baseBits__h1000922 = + csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22648 ? csrf_stcc_reg[13:0] : csrf_mtcc_reg[13:0] ; - assign x__h1000218 = csrf_mtcc_reg[33:28] + 6'd14 ; - assign x__h1000345 = address__h1000151 >> csrf_mtcc_reg[33:28] ; - assign x__h1000649 = address__h1000495 >> csrf_mtcc_reg[33:28] ; - assign x__h1000884 = - csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22647 ? + assign x__h1000027 = address__h999873 >> csrf_stcc_reg[33:28] ; + assign x__h1000253 = csrf_mtcc_reg[33:28] + 6'd14 ; + assign x__h1000380 = address__h1000186 >> csrf_mtcc_reg[33:28] ; + assign x__h1000684 = address__h1000530 >> csrf_mtcc_reg[33:28] ; + assign x__h1000919 = + csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22648 ? csrf_stcc_reg[27:14] : csrf_mtcc_reg[27:14] ; - assign x__h1000905 = - csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22647 ? + assign x__h1000940 = + csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22648 ? csrf_stcc_reg[33:28] : csrf_mtcc_reg[33:28] ; - assign x__h1008400 = - robdeqPort_0_deq_data_BITS_95_TO_32__q16[63:14] ^ - signBits__h1008370 ; - assign x__h1008496 = rob$deqPort_0_deq_data[95:32] >> csrf_stcc_reg[33:28] ; - assign x__h1008899 = + assign x__h1008435 = + robdeqPort_0_deq_data_BITS_95_TO_32__q17[63:14] ^ + signBits__h1008405 ; + assign x__h1008531 = rob$deqPort_0_deq_data[95:32] >> csrf_stcc_reg[33:28] ; + assign x__h1008934 = rob$deqPort_0_deq_data[95:32] >> IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16100 ; - assign x__h1009316 = rob$deqPort_0_deq_data[95:32] >> csrf_mtcc_reg[33:28] ; - assign x__h1009719 = + assign x__h1009351 = rob$deqPort_0_deq_data[95:32] >> csrf_mtcc_reg[33:28] ; + assign x__h1009754 = rob$deqPort_0_deq_data[95:32] >> IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16252 ; - assign x__h1010388 = rob$deqPort_0_deq_data[95:32] >> csrf_rg_dpc[33:28] ; - assign x__h1012282 = { 1'b0, csrf_spp_reg } ; - assign x__h1016564 = - NOT_rob_deqPort_0_canDeq__3598_3599_OR_rob_deq_ETC___d23818 ? - y_avValue_snd_snd_snd_fst__h1016386 : - IF_rob_deqPort_0_canDeq__3598_THEN_IF_NOT_rob__ETC___d23847 ; - assign x__h1031451 = f_csr_reqs$D_OUT[63:14] ^ signBits__h1031421 ; - assign x__h1031547 = f_csr_reqs$D_OUT[63:0] >> csrf_stcc_reg[33:28] ; - assign x__h1031950 = + assign x__h1010423 = rob$deqPort_0_deq_data[95:32] >> csrf_rg_dpc[33:28] ; + assign x__h1012317 = { 1'b0, csrf_spp_reg } ; + assign x__h1016599 = + NOT_rob_deqPort_0_canDeq__3600_3601_OR_rob_deq_ETC___d23820 ? + y_avValue_snd_snd_snd_fst__h1016421 : + IF_rob_deqPort_0_canDeq__3600_THEN_IF_NOT_rob__ETC___d23849 ; + assign x__h1031485 = f_csr_reqs$D_OUT[63:14] ^ signBits__h1031455 ; + assign x__h1031581 = f_csr_reqs$D_OUT[63:0] >> csrf_stcc_reg[33:28] ; + assign x__h1031984 = f_csr_reqs$D_OUT[63:0] >> IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16100 ; - assign x__h1032367 = f_csr_reqs$D_OUT[63:0] >> csrf_mtcc_reg[33:28] ; - assign x__h1032770 = + assign x__h1032401 = f_csr_reqs$D_OUT[63:0] >> csrf_mtcc_reg[33:28] ; + assign x__h1032804 = f_csr_reqs$D_OUT[63:0] >> IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16252 ; - assign x__h1033437 = f_csr_reqs$D_OUT[63:0] >> csrf_rg_dpc[33:28] ; - assign x__h127303 = coreFix_memExe_respLrScAmoQ_data_0[63:0] >> x__h127341 ; - assign x__h127341 = { tmp_expTopHalf__h127294, tmp_expBotHalf__h127296 } ; - assign x__h127501 = { impliedTopBits__h127434, topBits__h127430 } ; - assign x__h127518 = x__h127521[13:12] + carry_out__h127432 ; - assign x__h127521 = + assign x__h1033471 = f_csr_reqs$D_OUT[63:0] >> csrf_rg_dpc[33:28] ; + assign x__h127302 = coreFix_memExe_respLrScAmoQ_data_0[63:0] >> x__h127340 ; + assign x__h127340 = { tmp_expTopHalf__h127293, tmp_expBotHalf__h127295 } ; + assign x__h127500 = { impliedTopBits__h127433, topBits__h127429 } ; + assign x__h127517 = x__h127520[13:12] + carry_out__h127431 ; + assign x__h127520 = INV_coreFix_memExe_respLrScAmoQ_data_0_BITS_10_ETC__q8[0] ? { coreFix_memExe_respLrScAmoQ_data_0[77:67], 3'd0 } : - b_base__h127528 ; - assign x__h140219 = mmio_dataRespQ_data_0[63:0] >> x__h140257 ; - assign x__h140257 = { tmp_expTopHalf__h140210, tmp_expBotHalf__h140212 } ; - assign x__h140417 = { impliedTopBits__h140350, topBits__h140346 } ; - assign x__h140434 = x__h140437[13:12] + carry_out__h140348 ; - assign x__h140437 = + b_base__h127527 ; + assign x__h140218 = mmio_dataRespQ_data_0[63:0] >> x__h140256 ; + assign x__h140256 = { tmp_expTopHalf__h140209, tmp_expBotHalf__h140211 } ; + assign x__h140416 = { impliedTopBits__h140349, topBits__h140345 } ; + assign x__h140433 = x__h140436[13:12] + carry_out__h140347 ; + assign x__h140436 = INV_mmio_dataRespQ_data_0_BITS_108_TO_90__q9[0] ? { mmio_dataRespQ_data_0[77:67], 3'd0 } : - b_base__h140444 ; - assign x__h148991 = + b_base__h140443 ; + assign x__h148990 = coreFix_memExe_reqLdQ_data_0_lat_0$whas ? coreFix_memExe_reqLdQ_data_0_lat_0$wget[68:64] : coreFix_memExe_reqLdQ_data_0_rl[68:64] ; - assign x__h152125 = { 3'd0, sbIdx__h152016 } ; - assign x__h183399 = + assign x__h152124 = { 3'd0, sbIdx__h152015 } ; + assign x__h183397 = (coreFix_memExe_lsq$firstLd[125:110] == 16'd65535) ? coreFix_memExe_respLrScAmoQ_data_0[127:0] : { 64'd0, IF_coreFix_memExe_lsq_firstLd__498_BIT_117_521_ETC___d1913 } ; - assign x__h183481 = x__h183399[63:0] >> x__h183519 ; - assign x__h183519 = { tmp_expTopHalf__h183472, tmp_expBotHalf__h183474 } ; - assign x__h183679 = { impliedTopBits__h183612, topBits__h183608 } ; - assign x__h183696 = x__h183699[13:12] + carry_out__h183610 ; - assign x__h183699 = - INV_x83399_BITS_108_TO_90__q34[0] ? - { x__h183399[77:67], 3'd0 } : - b_base__h183706 ; - assign x__h199251 = + assign x__h183479 = x__h183397[63:0] >> x__h183517 ; + assign x__h183517 = { tmp_expTopHalf__h183470, tmp_expBotHalf__h183472 } ; + assign x__h183677 = { impliedTopBits__h183610, topBits__h183606 } ; + assign x__h183694 = x__h183697[13:12] + carry_out__h183608 ; + assign x__h183697 = + INV_x83397_BITS_108_TO_90__q34[0] ? + { x__h183397[77:67], 3'd0 } : + b_base__h183704 ; + assign x__h199249 = (coreFix_memExe_lsq$firstLd[125:110] == 16'd65535) ? mmio_dataRespQ_data_0[127:0] : { 64'd0, IF_coreFix_memExe_lsq_firstLd__498_BIT_117_521_ETC___d2079 } ; - assign x__h202232 = x__h199251[63:0] >> x__h202270 ; - assign x__h202270 = { tmp_expTopHalf__h202223, tmp_expBotHalf__h202225 } ; - assign x__h202430 = { impliedTopBits__h202363, topBits__h202359 } ; - assign x__h202447 = x__h202450[13:12] + carry_out__h202361 ; - assign x__h202450 = - INV_x99251_BITS_108_TO_90__q36[0] ? - { x__h199251[77:67], 3'd0 } : - b_base__h202457 ; - assign x__h216798 = coreFix_memExe_lsq$respLd[63:0] >> x__h216836 ; - assign x__h216836 = { tmp_expTopHalf__h216789, tmp_expBotHalf__h216791 } ; - assign x__h216996 = { impliedTopBits__h216929, topBits__h216925 } ; - assign x__h217013 = x__h217016[13:12] + carry_out__h216927 ; - assign x__h217016 = + assign x__h202230 = x__h199249[63:0] >> x__h202268 ; + assign x__h202268 = { tmp_expTopHalf__h202221, tmp_expBotHalf__h202223 } ; + assign x__h202428 = { impliedTopBits__h202361, topBits__h202357 } ; + assign x__h202445 = x__h202448[13:12] + carry_out__h202359 ; + assign x__h202448 = + INV_x99249_BITS_108_TO_90__q36[0] ? + { x__h199249[77:67], 3'd0 } : + b_base__h202455 ; + assign x__h216796 = coreFix_memExe_lsq$respLd[63:0] >> x__h216834 ; + assign x__h216834 = { tmp_expTopHalf__h216787, tmp_expBotHalf__h216789 } ; + assign x__h216994 = { impliedTopBits__h216927, topBits__h216923 } ; + assign x__h217011 = x__h217014[13:12] + carry_out__h216925 ; + assign x__h217014 = INV_coreFix_memExe_lsqrespLd_BITS_108_TO_90__q10[0] ? { coreFix_memExe_lsq$respLd[77:67], 3'd0 } : - b_base__h217023 ; - assign x__h235746 = + b_base__h217021 ; + assign x__h235743 = (coreFix_memExe_dispToRegQ$first[110] && coreFix_memExe_dispToRegQ$first[109:103] != 7'd0) ? IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3048 : 66'd0 ; - assign x__h239712 = x__h239714 << coreFix_memExe_regToExeQ$first[265:260] ; - assign x__h239714 = { {48{offset__h239700[15]}}, offset__h239700 } ; - assign x__h239822 = + assign x__h239709 = x__h239711 << coreFix_memExe_regToExeQ$first[265:260] ; + assign x__h239711 = { {48{offset__h239697[15]}}, offset__h239697 } ; + assign x__h239819 = 66'h3FFFFFFFFFFFFFFFF << coreFix_memExe_regToExeQ$first[265:260] ; - assign x__h239970 = + assign x__h239967 = coreFix_memExe_regToExeQ_first__645_BITS_265_T_ETC___d3717 ? - result__h240600 : - ret__h239977 ; - assign x__h240072 = + result__h240597 : + ret__h239974 ; + assign x__h240069 = { coreFix_memExe_regToExeQ$first[225:224], coreFix_memExe_regToExeQ$first[259:246] } ; - assign x__h240141 = + assign x__h240138 = (coreFix_memExe_regToExeQ$first[265:260] == 6'd50) ? coreFix_memExe_regToExeQ$first[245] : coreFix_memExe_regToExeQfirst_BITS_381_TO_332_ETC__q3[49] ; - assign x__h240869 = x__h240871 << coreFix_memExe_regToExeQ$first[102:97] ; - assign x__h240871 = { {48{offset__h240857[15]}}, offset__h240857 } ; - assign x__h240979 = + assign x__h240866 = x__h240868 << coreFix_memExe_regToExeQ$first[102:97] ; + assign x__h240868 = { {48{offset__h240854[15]}}, offset__h240854 } ; + assign x__h240976 = 66'h3FFFFFFFFFFFFFFFF << coreFix_memExe_regToExeQ$first[102:97] ; - assign x__h241127 = + assign x__h241124 = coreFix_memExe_regToExeQ_first__645_BITS_102_T_ETC___d3779 ? - result__h241757 : - ret__h241134 ; - assign x__h241229 = + result__h241754 : + ret__h241131 ; + assign x__h241226 = { coreFix_memExe_regToExeQ$first[62:61], coreFix_memExe_regToExeQ$first[96:83] } ; - assign x__h241298 = + assign x__h241295 = (coreFix_memExe_regToExeQ$first[102:97] == 6'd50) ? coreFix_memExe_regToExeQ$first[82] : coreFix_memExe_regToExeQfirst_BITS_218_TO_169_ETC__q5[49] ; - assign x__h242674 = offset__h242628[63:14] ^ signBits__h242644 ; - assign x__h242777 = - offset__h242628 >> coreFix_memExe_regToExeQ$first[265:260] ; - assign x__h244678 = { pointer__h242638[3:0], 3'b0 } ; - assign x__h248120 = - pointer__h242638 >> coreFix_memExe_regToExeQ$first[265:260] ; - assign x__h249478 = x__h249490 + y__h249491 ; - assign x__h249490 = x__h249502 + y__h249503 ; - assign x__h249502 = x__h249514 + y__h249515 ; - assign x__h249514 = x__h249526 + y__h249527 ; - assign x__h249526 = x__h249538 + y__h249539 ; - assign x__h249538 = x__h249550 + y__h249551 ; - assign x__h249550 = x__h249562 + y__h249563 ; - assign x__h249562 = x__h249574 + y__h249575 ; - assign x__h249574 = x__h249586 + y__h249587 ; - assign x__h249586 = x__h249598 + y__h249599 ; - assign x__h249598 = x__h249610 + y__h249611 ; - assign x__h249610 = x__h249622 + y__h249623 ; - assign x__h249622 = x__h249634 + y__h249635 ; - assign x__h249634 = x__h249646 + y__h249647 ; - assign x__h249646 = { 4'd0, coreFix_memExe_lsq$getOrigBE[15] } ; - assign x__h254493 = x__h254495 << coreFix_memExe_dTlb$procResp[334:329] ; - assign x__h254495 = { {48{offset__h254481[15]}}, offset__h254481 } ; - assign x__h254603 = + assign x__h242671 = offset__h242625[63:14] ^ signBits__h242641 ; + assign x__h242774 = + offset__h242625 >> coreFix_memExe_regToExeQ$first[265:260] ; + assign x__h244675 = { pointer__h242635[3:0], 3'b0 } ; + assign x__h248117 = + pointer__h242635 >> coreFix_memExe_regToExeQ$first[265:260] ; + assign x__h249475 = x__h249487 + y__h249488 ; + assign x__h249487 = x__h249499 + y__h249500 ; + assign x__h249499 = x__h249511 + y__h249512 ; + assign x__h249511 = x__h249523 + y__h249524 ; + assign x__h249523 = x__h249535 + y__h249536 ; + assign x__h249535 = x__h249547 + y__h249548 ; + assign x__h249547 = x__h249559 + y__h249560 ; + assign x__h249559 = x__h249571 + y__h249572 ; + assign x__h249571 = x__h249583 + y__h249584 ; + assign x__h249583 = x__h249595 + y__h249596 ; + assign x__h249595 = x__h249607 + y__h249608 ; + assign x__h249607 = x__h249619 + y__h249620 ; + assign x__h249619 = x__h249631 + y__h249632 ; + assign x__h249631 = x__h249643 + y__h249644 ; + assign x__h249643 = { 4'd0, coreFix_memExe_lsq$getOrigBE[15] } ; + assign x__h254490 = x__h254492 << coreFix_memExe_dTlb$procResp[334:329] ; + assign x__h254492 = { {48{offset__h254478[15]}}, offset__h254478 } ; + assign x__h254600 = 66'h3FFFFFFFFFFFFFFFF << coreFix_memExe_dTlb$procResp[334:329] ; - assign x__h254751 = + assign x__h254748 = coreFix_memExe_dTlb_procResp__257_BITS_334_TO__ETC___d4420 ? - result__h255381 : - ret__h254758 ; - assign x__h254853 = + result__h255378 : + ret__h254755 ; + assign x__h254850 = { coreFix_memExe_dTlb$procResp[294:293], coreFix_memExe_dTlb$procResp[328:315] } ; - assign x__h254922 = + assign x__h254919 = (coreFix_memExe_dTlb$procResp[334:329] == 6'd50) ? coreFix_memExe_dTlb$procResp[314] : coreFix_memExe_dTlbprocResp_BITS_450_TO_401_P_ETC__q7[49] ; - assign x__h521675 = + assign x__h521673 = EN_dCacheToParent_fromP_enq ? coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[2:0] : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[2:0] ; - assign x__h568253 = - { (_theResult___exp__h611585 != 8'd255 || - _theResult___sfd__h611586 == 23'd0) && + assign x__h568251 = + { (_theResult___exp__h611583 != 8'd255 || + _theResult___sfd__h611584 == 23'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9263, - out_f_exp__h611862, - out_f_sfd__h611863 } ; - assign x__h594803 = - sfd__h568849 << (x__h594836[11] ? 12'hAAA : x__h594836) ; - assign x__h594836 = + out_f_exp__h611860, + out_f_sfd__h611861 } ; + assign x__h594801 = + sfd__h568847 << (x__h594834[11] ? 12'hAAA : x__h594834) ; + assign x__h594834 = 12'd57 - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d8677 ; - assign x__h614007 = - { (_theResult___exp__h657334 != 8'd255 || - _theResult___sfd__h657335 == 23'd0) && + assign x__h614005 = + { (_theResult___exp__h657332 != 8'd255 || + _theResult___sfd__h657333 == 23'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10660, - out_f_exp__h657611, - out_f_sfd__h657612 } ; - assign x__h640552 = - sfd__h614603 << (x__h640585[11] ? 12'hAAA : x__h640585) ; - assign x__h640585 = + out_f_exp__h657609, + out_f_sfd__h657610 } ; + assign x__h640550 = + sfd__h614601 << (x__h640583[11] ? 12'hAAA : x__h640583) ; + assign x__h640583 = 12'd57 - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d10074 ; assign x__h65639 = mmio_pRqQ_data_0[31:0] ; - assign x__h659754 = - { (_theResult___exp__h703081 != 8'd255 || - _theResult___sfd__h703082 == 23'd0) && + assign x__h659752 = + { (_theResult___exp__h703079 != 8'd255 || + _theResult___sfd__h703080 == 23'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12057, - out_f_exp__h703358, - out_f_sfd__h703359 } ; - assign x__h686299 = - sfd__h660350 << (x__h686332[11] ? 12'hAAA : x__h686332) ; - assign x__h686332 = + out_f_exp__h703356, + out_f_sfd__h703357 } ; + assign x__h686297 = + sfd__h660348 << (x__h686330[11] ? 12'hAAA : x__h686330) ; + assign x__h686330 = 12'd57 - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d11471 ; - assign x__h714429 = + assign x__h714426 = sbCons$lazyLookup_2_get[3] ? rf$read_2_rd1[149:86] : - y_avValue__h710475 ; - assign x__h714430 = + y_avValue__h710472 ; + assign x__h714427 = sbCons$lazyLookup_2_get[2] ? rf$read_2_rd2[149:86] : - y_avValue__h711108 ; - assign x__h714431 = + y_avValue__h711105 ; + assign x__h714428 = sbCons$lazyLookup_2_get[1] ? rf$read_2_rd3[149:86] : - y_avValue__h711735 ; - assign x__h736336 = sfd__h715261 << x__h736369 ; - assign x__h736369 = + y_avValue__h711732 ; + assign x__h736333 = sfd__h715258 << x__h736366 ; + assign x__h736366 = 12'd57 - _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d12800 ; - assign x__h775189 = sfd__h754255 << x__h775222 ; - assign x__h775222 = + assign x__h775186 = sfd__h754252 << x__h775219 ; + assign x__h775219 = 12'd57 - _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d14285 ; - assign x__h814493 = sfd__h793559 << x__h814526 ; - assign x__h814526 = + assign x__h814490 = sfd__h793556 << x__h814523 ; + assign x__h814523 = 12'd57 - _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d13515 ; - assign x__h836143 = a__h835707[63] ^ b__h835708[63] ; - assign x__h853092 = { csrf_frm_reg, csrf_fflags_reg } ; - assign x__h854172 = 66'h3FFFFFFFFFFFFFFFF << csrf_stcc_reg[33:28] ; - assign x__h854233 = - x__h854235 << + assign x__h836140 = a__h835704[63] ^ b__h835705[63] ; + assign x__h853091 = { csrf_frm_reg, csrf_fflags_reg } ; + assign x__h854171 = 66'h3FFFFFFFFFFFFFFFF << csrf_stcc_reg[33:28] ; + assign x__h854232 = + x__h854234 << IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16100 ; - assign x__h854235 = { {48{offset__h854221[15]}}, offset__h854221 } ; - assign x__h854477 = + assign x__h854234 = { {48{offset__h854220[15]}}, offset__h854220 } ; + assign x__h854476 = 66'h3FFFFFFFFFFFFFFFF << IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16100 ; - assign x__h855165 = 66'h3FFFFFFFFFFFFFFFF << csrf_mtcc_reg[33:28] ; - assign x__h855226 = - x__h855228 << + assign x__h855164 = 66'h3FFFFFFFFFFFFFFFF << csrf_mtcc_reg[33:28] ; + assign x__h855225 = + x__h855227 << IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16252 ; - assign x__h855228 = { {48{offset__h855214[15]}}, offset__h855214 } ; - assign x__h855469 = + assign x__h855227 = { {48{offset__h855213[15]}}, offset__h855213 } ; + assign x__h855468 = 66'h3FFFFFFFFFFFFFFFF << IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16252 ; - assign x__h855995 = 66'h3FFFFFFFFFFFFFFFF << csrf_rg_dpc[33:28] ; - assign x__h866848 = - coreFix_aluExe_1_regToExeQ$first[241:178] >> x__h866886 ; - assign x__h866886 = { tmp_expTopHalf__h866838, tmp_expBotHalf__h866840 } ; - assign x__h867059 = { impliedTopBits__h866991, topBits__h866987 } ; - assign x__h867076 = x__h867079[13:12] + carry_out__h866989 ; - assign x__h867079 = + assign x__h855994 = 66'h3FFFFFFFFFFFFFFFF << csrf_rg_dpc[33:28] ; + assign x__h866847 = + coreFix_aluExe_1_regToExeQ$first[241:178] >> x__h866885 ; + assign x__h866885 = { tmp_expTopHalf__h866837, tmp_expBotHalf__h866839 } ; + assign x__h867058 = { impliedTopBits__h866990, topBits__h866986 } ; + assign x__h867075 = x__h867078[13:12] + carry_out__h866988 ; + assign x__h867078 = INV_coreFix_aluExe_1_regToExeQfirst_BITS_286__ETC__q11[0] ? { coreFix_aluExe_1_regToExeQ$first[255:245], 3'd0 } : - b_base__h867086 ; - assign x__h867396 = coreFix_aluExe_1_regToExeQ$first[112:49] >> x__h867434 ; - assign x__h867434 = { tmp_expTopHalf__h867386, tmp_expBotHalf__h867388 } ; - assign x__h867607 = { impliedTopBits__h867539, topBits__h867535 } ; - assign x__h867624 = x__h867627[13:12] + carry_out__h867537 ; - assign x__h867627 = + b_base__h867085 ; + assign x__h867395 = coreFix_aluExe_1_regToExeQ$first[112:49] >> x__h867433 ; + assign x__h867433 = { tmp_expTopHalf__h867385, tmp_expBotHalf__h867387 } ; + assign x__h867606 = { impliedTopBits__h867538, topBits__h867534 } ; + assign x__h867623 = x__h867626[13:12] + carry_out__h867536 ; + assign x__h867626 = INV_coreFix_aluExe_1_regToExeQfirst_BITS_157__ETC__q12[0] ? { coreFix_aluExe_1_regToExeQ$first[126:116], 3'd0 } : - b_base__h867634 ; - assign x__h879903 = + b_base__h867633 ; + assign x__h879902 = { coreFix_aluExe_1_exeToFinQ$first[623], coreFix_aluExe_1_exeToFinQ$first[542:527], coreFix_aluExe_1_exeToFinQ$first[525:524], @@ -38295,34 +38285,34 @@ module mkCore(CLK, ~IF_coreFix_aluExe_1_exeToFinQ_first__7830_BIT__ETC___d18027[2], IF_coreFix_aluExe_1_exeToFinQ_first__7830_BIT__ETC___d18027[1:0], coreFix_aluExe_1_exeToFinQ$first[620:557] } ; - assign x__h895988 = x__h895990 << csrf_stcc_reg[33:28] ; - assign x__h895990 = { {48{offset__h895976[15]}}, offset__h895976 } ; - assign x__h896272 = x__h896274 << csrf_mtcc_reg[33:28] ; - assign x__h896274 = { {48{offset__h896260[15]}}, offset__h896260 } ; - assign x__h896542 = + assign x__h895986 = x__h895988 << csrf_stcc_reg[33:28] ; + assign x__h895988 = { {48{offset__h895974[15]}}, offset__h895974 } ; + assign x__h896270 = x__h896272 << csrf_mtcc_reg[33:28] ; + assign x__h896272 = { {48{offset__h896258[15]}}, offset__h896258 } ; + assign x__h896540 = { csrf_mccsr_reg[10:5], CASE_csrf_mccsr_reg_BITS_4_TO_0_0_csrf_mccsr_r_ETC__q24, 5'd3 } ; - assign x__h896617 = x__h896619 << csrf_rg_dpc[33:28] ; - assign x__h896619 = { {48{offset__h896605[15]}}, offset__h896605 } ; - assign x__h906534 = - coreFix_aluExe_0_regToExeQ$first[241:178] >> x__h906572 ; - assign x__h906572 = { tmp_expTopHalf__h906524, tmp_expBotHalf__h906526 } ; - assign x__h906745 = { impliedTopBits__h906677, topBits__h906673 } ; - assign x__h906762 = x__h906765[13:12] + carry_out__h906675 ; - assign x__h906765 = + assign x__h896615 = x__h896617 << csrf_rg_dpc[33:28] ; + assign x__h896617 = { {48{offset__h896603[15]}}, offset__h896603 } ; + assign x__h906532 = + coreFix_aluExe_0_regToExeQ$first[241:178] >> x__h906570 ; + assign x__h906570 = { tmp_expTopHalf__h906522, tmp_expBotHalf__h906524 } ; + assign x__h906743 = { impliedTopBits__h906675, topBits__h906671 } ; + assign x__h906760 = x__h906763[13:12] + carry_out__h906673 ; + assign x__h906763 = INV_coreFix_aluExe_0_regToExeQfirst_BITS_286__ETC__q13[0] ? { coreFix_aluExe_0_regToExeQ$first[255:245], 3'd0 } : - b_base__h906772 ; - assign x__h907082 = coreFix_aluExe_0_regToExeQ$first[112:49] >> x__h907120 ; - assign x__h907120 = { tmp_expTopHalf__h907072, tmp_expBotHalf__h907074 } ; - assign x__h907293 = { impliedTopBits__h907225, topBits__h907221 } ; - assign x__h907310 = x__h907313[13:12] + carry_out__h907223 ; - assign x__h907313 = + b_base__h906770 ; + assign x__h907080 = coreFix_aluExe_0_regToExeQ$first[112:49] >> x__h907118 ; + assign x__h907118 = { tmp_expTopHalf__h907070, tmp_expBotHalf__h907072 } ; + assign x__h907291 = { impliedTopBits__h907223, topBits__h907219 } ; + assign x__h907308 = x__h907311[13:12] + carry_out__h907221 ; + assign x__h907311 = INV_coreFix_aluExe_0_regToExeQfirst_BITS_157__ETC__q14[0] ? { coreFix_aluExe_0_regToExeQ$first[126:116], 3'd0 } : - b_base__h907320 ; - assign x__h914620 = + b_base__h907318 ; + assign x__h914618 = { coreFix_aluExe_0_exeToFinQ$first[623], coreFix_aluExe_0_exeToFinQ$first[542:527], coreFix_aluExe_0_exeToFinQ$first[525:524], @@ -38334,30 +38324,29 @@ module mkCore(CLK, ~IF_coreFix_aluExe_0_exeToFinQ_first__9946_BIT__ETC___d20142[2], IF_coreFix_aluExe_0_exeToFinQ_first__9946_BIT__ETC___d20142[1:0], coreFix_aluExe_0_exeToFinQ$first[620:557] } ; - assign x__h915809 = 12'd1 << coreFix_aluExe_1_exeToFinQ$first[15:12] ; - assign x__h915860 = 12'd1 << coreFix_aluExe_0_exeToFinQ$first[15:12] ; - assign x__h994911 = commitStage_commitTrap[172:109] >> x__h994949 ; - assign x__h994949 = { tmp_expTopHalf__h994902, tmp_expBotHalf__h994904 } ; - assign x__h995109 = { impliedTopBits__h995042, topBits__h995038 } ; - assign x__h995126 = x__h995129[13:12] + carry_out__h995040 ; - assign x__h995129 = - INV_commitStage_commitTrap_BITS_217_TO_199__q15[0] ? + assign x__h915807 = 12'd1 << coreFix_aluExe_1_exeToFinQ$first[15:12] ; + assign x__h915858 = 12'd1 << coreFix_aluExe_0_exeToFinQ$first[15:12] ; + assign x__h994909 = commitStage_commitTrap[172:109] >> x__h994947 ; + assign x__h994947 = { tmp_expTopHalf__h994900, tmp_expBotHalf__h994902 } ; + assign x__h995107 = { impliedTopBits__h995040, topBits__h995036 } ; + assign x__h995124 = x__h995127[13:12] + carry_out__h995038 ; + assign x__h995127 = + INV_commitStage_commitTrap_BITS_217_TO_199__q16[0] ? { commitStage_commitTrap[186:176], 3'd0 } : - b_base__h995136 ; - assign x__h997587 = - x__h997589 << + b_base__h995134 ; + assign x__h997622 = + x__h997624 << IF_INV_commitStage_commitTrap_2268_BITS_217_TO_ETC___d22580 ; - assign x__h997589 = { {48{offset__h997575[15]}}, offset__h997575 } ; - assign x__h997674 = + assign x__h997624 = { {48{offset__h997610[15]}}, offset__h997610 } ; + assign x__h997709 = 66'h3FFFFFFFFFFFFFFFF << IF_INV_commitStage_commitTrap_2268_BITS_217_TO_ETC___d22580 ; - assign x__h998861 = + assign x__h998896 = { commitStage_commitTrap[42:37], CASE_commitStage_commitTrap_BITS_36_TO_32_0_co_ETC__q25 } ; - assign x__h999561 = csrf_stcc_reg[33:28] + 6'd14 ; - assign x__h999587 = { cause_code__h995320, 2'b0 } ; - assign x__h999688 = address__h999494 >> csrf_stcc_reg[33:28] ; - assign x__h999992 = address__h999838 >> csrf_stcc_reg[33:28] ; + assign x__h999596 = csrf_stcc_reg[33:28] + 6'd14 ; + assign x__h999622 = { cause_code__h995318, 2'b0 } ; + assign x__h999723 = address__h999529 >> csrf_stcc_reg[33:28] ; assign x_addr__h19883 = mmio_dataReqQ_enqReq_lat_0$whas ? mmio_dataReqQ_enqReq_lat_0$wget[214:151] : @@ -38366,7 +38355,7 @@ module mkCore(CLK, mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[214:151] : mmio_cRqQ_enqReq_rl[214:151] ; - assign x_addr__h535374 = + assign x_addr__h535372 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[582:519] : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[582:519] ; @@ -38374,55 +38363,55 @@ module mkCore(CLK, EN_mmioToPlatform_pRq_enq ? mmio_pRqQ_enqReq_lat_0$wget[31:0] : mmio_pRqQ_enqReq_rl[31:0] ; - assign x_decodeInfo_frm__h926248 = csrf_frm_reg ; - assign x_quotient__h705747 = + assign x_decodeInfo_frm__h926246 = csrf_frm_reg ; + assign x_quotient__h705745 = coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[75] ? 64'hFFFFFFFFFFFFFFFF : ((coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[10] && coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[9]) ? - q___1__h706458 : + q___1__h706456 : coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[127:64]) ; - assign x_reg_ifc__read__h849324 = { 63'd0, csrf_stats_module_doStats } ; - assign x_remainder__h705748 = + assign x_reg_ifc__read__h849323 = { 63'd0, csrf_stats_module_doStats } ; + assign x_remainder__h705746 = coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[75] ? coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[74:11] : ((coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[10] && coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[8]) ? - r___1__h706484 : + r___1__h706482 : coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[63:0]) ; - assign y__h1000274 = { mask__h1000157[62:0], 1'd0 } ; - assign y__h1016339 = - NOT_rob_deqPort_0_canDeq__3598_3599_OR_rob_deq_ETC___d23818 ? - y_avValue_snd_snd_snd_snd_snd__h1016392 : - IF_rob_deqPort_0_canDeq__3598_THEN_IF_NOT_rob__ETC___d23719 ; - assign y__h239821 = ~x__h239822 ; - assign y__h240978 = ~x__h240979 ; - assign y__h249479 = { 4'd0, coreFix_memExe_lsq$getOrigBE[0] } ; - assign y__h249491 = { 4'd0, coreFix_memExe_lsq$getOrigBE[1] } ; - assign y__h249503 = { 4'd0, coreFix_memExe_lsq$getOrigBE[2] } ; - assign y__h249515 = { 4'd0, coreFix_memExe_lsq$getOrigBE[3] } ; - assign y__h249527 = { 4'd0, coreFix_memExe_lsq$getOrigBE[4] } ; - assign y__h249539 = { 4'd0, coreFix_memExe_lsq$getOrigBE[5] } ; - assign y__h249551 = { 4'd0, coreFix_memExe_lsq$getOrigBE[6] } ; - assign y__h249563 = { 4'd0, coreFix_memExe_lsq$getOrigBE[7] } ; - assign y__h249575 = { 4'd0, coreFix_memExe_lsq$getOrigBE[8] } ; - assign y__h249587 = { 4'd0, coreFix_memExe_lsq$getOrigBE[9] } ; - assign y__h249599 = { 4'd0, coreFix_memExe_lsq$getOrigBE[10] } ; - assign y__h249611 = { 4'd0, coreFix_memExe_lsq$getOrigBE[11] } ; - assign y__h249623 = { 4'd0, coreFix_memExe_lsq$getOrigBE[12] } ; - assign y__h249635 = { 4'd0, coreFix_memExe_lsq$getOrigBE[13] } ; - assign y__h249647 = { 4'd0, coreFix_memExe_lsq$getOrigBE[14] } ; - assign y__h254602 = ~x__h254603 ; - assign y__h422565 = + assign y__h1000309 = { mask__h1000192[62:0], 1'd0 } ; + assign y__h1016374 = + NOT_rob_deqPort_0_canDeq__3600_3601_OR_rob_deq_ETC___d23820 ? + y_avValue_snd_snd_snd_snd_snd__h1016427 : + IF_rob_deqPort_0_canDeq__3600_THEN_IF_NOT_rob__ETC___d23721 ; + assign y__h239818 = ~x__h239819 ; + assign y__h240975 = ~x__h240976 ; + assign y__h249476 = { 4'd0, coreFix_memExe_lsq$getOrigBE[0] } ; + assign y__h249488 = { 4'd0, coreFix_memExe_lsq$getOrigBE[1] } ; + assign y__h249500 = { 4'd0, coreFix_memExe_lsq$getOrigBE[2] } ; + assign y__h249512 = { 4'd0, coreFix_memExe_lsq$getOrigBE[3] } ; + assign y__h249524 = { 4'd0, coreFix_memExe_lsq$getOrigBE[4] } ; + assign y__h249536 = { 4'd0, coreFix_memExe_lsq$getOrigBE[5] } ; + assign y__h249548 = { 4'd0, coreFix_memExe_lsq$getOrigBE[6] } ; + assign y__h249560 = { 4'd0, coreFix_memExe_lsq$getOrigBE[7] } ; + assign y__h249572 = { 4'd0, coreFix_memExe_lsq$getOrigBE[8] } ; + assign y__h249584 = { 4'd0, coreFix_memExe_lsq$getOrigBE[9] } ; + assign y__h249596 = { 4'd0, coreFix_memExe_lsq$getOrigBE[10] } ; + assign y__h249608 = { 4'd0, coreFix_memExe_lsq$getOrigBE[11] } ; + assign y__h249620 = { 4'd0, coreFix_memExe_lsq$getOrigBE[12] } ; + assign y__h249632 = { 4'd0, coreFix_memExe_lsq$getOrigBE[13] } ; + assign y__h249644 = { 4'd0, coreFix_memExe_lsq$getOrigBE[14] } ; + assign y__h254599 = ~x__h254600 ; + assign y__h422564 = { coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[574:522], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[168:164] } ; - assign y__h854171 = ~x__h854172 ; - assign y__h854476 = ~x__h854477 ; - assign y__h855164 = ~x__h855165 ; - assign y__h855468 = ~x__h855469 ; - assign y__h855994 = ~x__h855995 ; - assign y__h915839 = ~x__h915809 ; - assign y__h920769 = + assign y__h854170 = ~x__h854171 ; + assign y__h854475 = ~x__h854476 ; + assign y__h855163 = ~x__h855164 ; + assign y__h855467 = ~x__h855468 ; + assign y__h855993 = ~x__h855994 ; + assign y__h915837 = ~x__h915807 ; + assign y__h920767 = { 4'd15, ~csrf_mideleg_11_reg, 1'd1, @@ -38431,22 +38420,22 @@ module mkCore(CLK, ~csrf_mideleg_5_3_reg, 1'd1, ~csrf_mideleg_1_0_reg } ; - assign y__h973805 = 12'd1 << specTagManager$nextSpecTag ; - assign y__h997673 = ~x__h997674 ; - assign y__h999617 = { mask__h999500[62:0], 1'd0 } ; - assign y_avValue__h710475 = + assign y__h973803 = 12'd1 << specTagManager$nextSpecTag ; + assign y__h997708 = ~x__h997709 ; + assign y__h999652 = { mask__h999535[62:0], 1'd0 } ; + assign y_avValue__h710472 = NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d12381 ? coreFix_fpuMulDivExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12486 ; - assign y_avValue__h711108 = + assign y_avValue__h711105 = NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d12408 ? coreFix_fpuMulDivExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12498 ; - assign y_avValue__h711735 = + assign y_avValue__h711732 = NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d12432 ? coreFix_fpuMulDivExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12510 ; - assign y_avValue_snd_fst__h1015794 = + assign y_avValue_snd_fst__h1015829 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[274] || rob$deqPort_0_deq_data[469:465] == 5'd0 || @@ -38461,7 +38450,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[469:465] == 5'd25) ? 5'd0 : rob$deqPort_0_deq_data[31:27] ; - assign y_avValue_snd_fst__h1016376 = + assign y_avValue_snd_fst__h1016411 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[274] || rob$deqPort_1_deq_data[469:465] == 5'd0 || @@ -38474,26 +38463,26 @@ module mkCore(CLK, rob$deqPort_1_deq_data[469:465] == 5'd20 || rob$deqPort_1_deq_data[469:465] == 5'd24 || rob$deqPort_1_deq_data[469:465] == 5'd25) ? - IF_rob_deqPort_0_canDeq__3598_THEN_IF_NOT_rob__ETC___d23825 : - y_avValue_snd_fst__h1016405 ; - assign y_avValue_snd_fst__h1016405 = - IF_rob_deqPort_0_canDeq__3598_THEN_IF_NOT_rob__ETC___d23825 | + IF_rob_deqPort_0_canDeq__3600_THEN_IF_NOT_rob__ETC___d23827 : + y_avValue_snd_fst__h1016440 ; + assign y_avValue_snd_fst__h1016440 = + IF_rob_deqPort_0_canDeq__3600_THEN_IF_NOT_rob__ETC___d23827 | rob$deqPort_1_deq_data[31:27] ; - assign y_avValue_snd_fst__h963385 = + assign y_avValue_snd_fst__h963383 = ((fetchStage$pipelines_0_first[268:266] != 3'd1 || specTagManager$canClaim) && regRenamingTable_rename_0_canRename__1151_AND__ETC___d21180) ? - y_avValue_snd_fst__h963427 : + y_avValue_snd_fst__h963425 : specTagManager$currentSpecBits ; - assign y_avValue_snd_fst__h963427 = + assign y_avValue_snd_fst__h963425 = IF_fetchStage_pipelines_0_first__0256_BITS_268_ETC___d21222 ? - y_avValue_snd_fst__h963469 : + y_avValue_snd_fst__h963467 : specTagManager$currentSpecBits ; - assign y_avValue_snd_fst__h963469 = + assign y_avValue_snd_fst__h963467 = (fetchStage$pipelines_0_first[268:266] == 3'd1) ? - spec_bits__h973792 : + spec_bits__h973790 : specTagManager$currentSpecBits ; - assign y_avValue_snd_snd_snd_fst__h1015804 = + assign y_avValue_snd_snd_snd_fst__h1015839 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[274] || rob$deqPort_0_deq_data[469:465] == 5'd0 || @@ -38508,7 +38497,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[469:465] == 5'd25) ? 2'd0 : 2'd1 ; - assign y_avValue_snd_snd_snd_fst__h1016386 = + assign y_avValue_snd_snd_snd_fst__h1016421 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[274] || rob$deqPort_1_deq_data[469:465] == 5'd0 || @@ -38521,12 +38510,12 @@ module mkCore(CLK, rob$deqPort_1_deq_data[469:465] == 5'd20 || rob$deqPort_1_deq_data[469:465] == 5'd24 || rob$deqPort_1_deq_data[469:465] == 5'd25) ? - IF_rob_deqPort_0_canDeq__3598_THEN_IF_NOT_rob__ETC___d23847 : - y_avValue_snd_snd_snd_fst__h1016415 ; - assign y_avValue_snd_snd_snd_fst__h1016415 = - IF_rob_deqPort_0_canDeq__3598_THEN_IF_NOT_rob__ETC___d23847 + + IF_rob_deqPort_0_canDeq__3600_THEN_IF_NOT_rob__ETC___d23849 : + y_avValue_snd_snd_snd_fst__h1016450 ; + assign y_avValue_snd_snd_snd_fst__h1016450 = + IF_rob_deqPort_0_canDeq__3600_THEN_IF_NOT_rob__ETC___d23849 + 2'd1 ; - assign y_avValue_snd_snd_snd_snd_snd__h1015810 = + assign y_avValue_snd_snd_snd_snd_snd__h1015845 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[274] || rob$deqPort_0_deq_data[469:465] == 5'd0 || @@ -38541,7 +38530,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[469:465] == 5'd25) ? 64'd0 : 64'd1 ; - assign y_avValue_snd_snd_snd_snd_snd__h1016392 = + assign y_avValue_snd_snd_snd_snd_snd__h1016427 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[274] || rob$deqPort_1_deq_data[469:465] == 5'd0 || @@ -38554,10 +38543,10 @@ module mkCore(CLK, rob$deqPort_1_deq_data[469:465] == 5'd20 || rob$deqPort_1_deq_data[469:465] == 5'd24 || rob$deqPort_1_deq_data[469:465] == 5'd25) ? - IF_rob_deqPort_0_canDeq__3598_THEN_IF_NOT_rob__ETC___d23719 : - y_avValue_snd_snd_snd_snd_snd__h1016421 ; - assign y_avValue_snd_snd_snd_snd_snd__h1016421 = - IF_rob_deqPort_0_canDeq__3598_THEN_IF_NOT_rob__ETC___d23719 + + IF_rob_deqPort_0_canDeq__3600_THEN_IF_NOT_rob__ETC___d23721 : + y_avValue_snd_snd_snd_snd_snd__h1016456 ; + assign y_avValue_snd_snd_snd_snd_snd__h1016456 = + IF_rob_deqPort_0_canDeq__3600_THEN_IF_NOT_rob__ETC___d23721 + 64'd1 ; always@(mmio_cRqQ_data_0) begin @@ -38582,28 +38571,28 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP) 3'd0: - x__h501097 = + x__h501096 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0; 3'd1: - x__h501097 = + x__h501096 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1; 3'd2: - x__h501097 = + x__h501096 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2; 3'd3: - x__h501097 = + x__h501096 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3; 3'd4: - x__h501097 = + x__h501096 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4; 3'd5: - x__h501097 = + x__h501096 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5; 3'd6: - x__h501097 = + x__h501096 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6; 3'd7: - x__h501097 = + x__h501096 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7; endcase end @@ -38613,10 +38602,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - addr__h505615 = + addr__h505614 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[585:522]; 1'd1: - addr__h505615 = + addr__h505614 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[585:522]; endcase end @@ -38625,16 +38614,16 @@ module mkCore(CLK, coreFix_memExe_memRespLdQ_data_1) begin case (coreFix_memExe_memRespLdQ_deqP) - 1'd0: t__h212841 = coreFix_memExe_memRespLdQ_data_0[133:129]; - 1'd1: t__h212841 = coreFix_memExe_memRespLdQ_data_1[133:129]; + 1'd0: t__h212839 = coreFix_memExe_memRespLdQ_data_0[133:129]; + 1'd1: t__h212839 = coreFix_memExe_memRespLdQ_data_1[133:129]; endcase end always@(coreFix_memExe_forwardQ_deqP or coreFix_memExe_forwardQ_data_0 or coreFix_memExe_forwardQ_data_1) begin case (coreFix_memExe_forwardQ_deqP) - 1'd0: t__h215127 = coreFix_memExe_forwardQ_data_0[133:129]; - 1'd1: t__h215127 = coreFix_memExe_forwardQ_data_1[133:129]; + 1'd0: t__h215125 = coreFix_memExe_forwardQ_data_0[133:129]; + 1'd1: t__h215125 = coreFix_memExe_forwardQ_data_1[133:129]; endcase end always@(coreFix_memExe_dMem_cache_m_banks_0_processAmo or @@ -38693,16 +38682,16 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_processAmo[167:166]) 2'd0: - x__h264732 = + x__h264730 = CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q18; 2'd1: - x__h264732 = + x__h264730 = CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q19; 2'd2: - x__h264732 = + x__h264730 = CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q20; 2'd3: - x__h264732 = + x__h264730 = CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q21; endcase end @@ -38710,8 +38699,8 @@ module mkCore(CLK, begin case (commitStage_commitTrap[35:32]) 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: - i__h995510 = commitStage_commitTrap[35:32]; - default: i__h995510 = 4'd15; + i__h995534 = commitStage_commitTrap[35:32]; + default: i__h995534 = 4'd15; endcase end always@(csrf_mccsr_reg) @@ -38784,123 +38773,123 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - x__h508765 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[2:0]; + x__h508764 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[2:0]; 1'd1: - x__h508765 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[2:0]; + x__h508764 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[2:0]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h576436 = 8'd255; + 3'd0, 3'd1: _theResult___fst_exp__h576434 = 8'd255; 3'd2: - _theResult___fst_exp__h576436 = + _theResult___fst_exp__h576434 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 8'd254 : 8'd255; 3'd3: - _theResult___fst_exp__h576436 = + _theResult___fst_exp__h576434 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 8'd255 : 8'd254; - 3'd4: _theResult___fst_exp__h576436 = 8'd254; - default: _theResult___fst_exp__h576436 = 8'd0; + 3'd4: _theResult___fst_exp__h576434 = 8'd254; + default: _theResult___fst_exp__h576434 = 8'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_sfd__h576437 = 23'd0; + 3'd0, 3'd1: _theResult___fst_sfd__h576435 = 23'd0; 3'd2: - _theResult___fst_sfd__h576437 = + _theResult___fst_sfd__h576435 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 23'd8388607 : 23'd0; 3'd3: - _theResult___fst_sfd__h576437 = + _theResult___fst_sfd__h576435 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 23'd0 : 23'd8388607; - 3'd4: _theResult___fst_sfd__h576437 = 23'd8388607; - default: _theResult___fst_sfd__h576437 = 23'd0; + 3'd4: _theResult___fst_sfd__h576435 = 23'd8388607; + default: _theResult___fst_sfd__h576435 = 23'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h622187 = 8'd255; + 3'd0, 3'd1: _theResult___fst_exp__h622185 = 8'd255; 3'd2: - _theResult___fst_exp__h622187 = + _theResult___fst_exp__h622185 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 8'd254 : 8'd255; 3'd3: - _theResult___fst_exp__h622187 = + _theResult___fst_exp__h622185 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 8'd255 : 8'd254; - 3'd4: _theResult___fst_exp__h622187 = 8'd254; - default: _theResult___fst_exp__h622187 = 8'd0; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h667934 = 8'd255; - 3'd2: - _theResult___fst_exp__h667934 = - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - 8'd254 : - 8'd255; - 3'd3: - _theResult___fst_exp__h667934 = - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - 8'd255 : - 8'd254; - 3'd4: _theResult___fst_exp__h667934 = 8'd254; - default: _theResult___fst_exp__h667934 = 8'd0; + 3'd4: _theResult___fst_exp__h622185 = 8'd254; + default: _theResult___fst_exp__h622185 = 8'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_sfd__h622188 = 23'd0; + 3'd0, 3'd1: _theResult___fst_sfd__h622186 = 23'd0; 3'd2: - _theResult___fst_sfd__h622188 = + _theResult___fst_sfd__h622186 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 23'd8388607 : 23'd0; 3'd3: - _theResult___fst_sfd__h622188 = + _theResult___fst_sfd__h622186 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 23'd0 : 23'd8388607; - 3'd4: _theResult___fst_sfd__h622188 = 23'd8388607; - default: _theResult___fst_sfd__h622188 = 23'd0; + 3'd4: _theResult___fst_sfd__h622186 = 23'd8388607; + default: _theResult___fst_sfd__h622186 = 23'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_sfd__h667935 = 23'd0; + 3'd0, 3'd1: _theResult___fst_exp__h667932 = 8'd255; 3'd2: - _theResult___fst_sfd__h667935 = + _theResult___fst_exp__h667932 = + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? + 8'd254 : + 8'd255; + 3'd3: + _theResult___fst_exp__h667932 = + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? + 8'd255 : + 8'd254; + 3'd4: _theResult___fst_exp__h667932 = 8'd254; + default: _theResult___fst_exp__h667932 = 8'd0; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) + 3'd0, 3'd1: _theResult___fst_sfd__h667933 = 23'd0; + 3'd2: + _theResult___fst_sfd__h667933 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 23'd8388607 : 23'd0; 3'd3: - _theResult___fst_sfd__h667935 = + _theResult___fst_sfd__h667933 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 23'd0 : 23'd8388607; - 3'd4: _theResult___fst_sfd__h667935 = 23'd8388607; - default: _theResult___fst_sfd__h667935 = 23'd0; + 3'd4: _theResult___fst_sfd__h667933 = 23'd8388607; + default: _theResult___fst_sfd__h667933 = 23'd0; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) @@ -39052,16 +39041,62 @@ module mkCore(CLK, 5'd12, 5'd13, 5'd15: - i__h995336 = commitStage_commitTrap[36:32]; - default: i__h995336 = 5'd28; + i__h995334 = commitStage_commitTrap[36:32]; + default: i__h995334 = 5'd28; endcase end - always@(commitStage_commitTrap or cause_code__h996858 or i__h995336) + always@(commitStage_commitTrap or cause_code__h996893 or i__h995334) begin case (commitStage_commitTrap[44:43]) - 2'd0: cause_code__h995320 = 5'd28; - 2'd1: cause_code__h995320 = i__h995336; - default: cause_code__h995320 = cause_code__h996858; + 2'd0: cause_code__h995318 = 5'd28; + 2'd1: cause_code__h995318 = i__h995334; + default: cause_code__h995318 = cause_code__h996893; + endcase + end + always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) + begin + case (coreFix_memExe_lsq$firstLd[37:35]) + 3'd0: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1885 = + coreFix_memExe_respLrScAmoQ_data_0[15:0]; + 3'd1: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1885 = + coreFix_memExe_respLrScAmoQ_data_0[31:16]; + 3'd2: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1885 = + coreFix_memExe_respLrScAmoQ_data_0[47:32]; + 3'd3: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1885 = + coreFix_memExe_respLrScAmoQ_data_0[63:48]; + 3'd4: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1885 = + coreFix_memExe_respLrScAmoQ_data_0[79:64]; + 3'd5: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1885 = + coreFix_memExe_respLrScAmoQ_data_0[95:80]; + 3'd6: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1885 = + coreFix_memExe_respLrScAmoQ_data_0[111:96]; + 3'd7: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1885 = + coreFix_memExe_respLrScAmoQ_data_0[127:112]; + endcase + end + always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) + begin + case (coreFix_memExe_lsq$firstLd[37:36]) + 2'd0: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1872 = + coreFix_memExe_respLrScAmoQ_data_0[31:0]; + 2'd1: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1872 = + coreFix_memExe_respLrScAmoQ_data_0[63:32]; + 2'd2: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1872 = + coreFix_memExe_respLrScAmoQ_data_0[95:64]; + 2'd3: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1872 = + coreFix_memExe_respLrScAmoQ_data_0[127:96]; endcase end always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) @@ -39118,52 +39153,6 @@ module mkCore(CLK, endcase end always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) - begin - case (coreFix_memExe_lsq$firstLd[37:35]) - 3'd0: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1885 = - coreFix_memExe_respLrScAmoQ_data_0[15:0]; - 3'd1: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1885 = - coreFix_memExe_respLrScAmoQ_data_0[31:16]; - 3'd2: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1885 = - coreFix_memExe_respLrScAmoQ_data_0[47:32]; - 3'd3: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1885 = - coreFix_memExe_respLrScAmoQ_data_0[63:48]; - 3'd4: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1885 = - coreFix_memExe_respLrScAmoQ_data_0[79:64]; - 3'd5: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1885 = - coreFix_memExe_respLrScAmoQ_data_0[95:80]; - 3'd6: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1885 = - coreFix_memExe_respLrScAmoQ_data_0[111:96]; - 3'd7: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1885 = - coreFix_memExe_respLrScAmoQ_data_0[127:112]; - endcase - end - always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) - begin - case (coreFix_memExe_lsq$firstLd[37:36]) - 2'd0: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1872 = - coreFix_memExe_respLrScAmoQ_data_0[31:0]; - 2'd1: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1872 = - coreFix_memExe_respLrScAmoQ_data_0[63:32]; - 2'd2: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1872 = - coreFix_memExe_respLrScAmoQ_data_0[95:64]; - 2'd3: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1872 = - coreFix_memExe_respLrScAmoQ_data_0[127:96]; - endcase - end - always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) begin case (coreFix_memExe_lsq$firstLd[37]) 1'd0: @@ -39309,24 +39298,6 @@ module mkCore(CLK, !coreFix_memExe_forwardQ_data_1[128]; endcase end - always@(coreFix_memExe_dMem_cache_m_banks_0_processAmo or - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first) - begin - case (coreFix_memExe_dMem_cache_m_banks_0_processAmo[167:166]) - 2'd0: - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4867 = - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0]; - 2'd1: - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4867 = - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128]; - 2'd2: - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4867 = - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256]; - 2'd3: - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4867 = - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384]; - endcase - end always@(coreFix_memExe_dMem_cache_m_banks_0_processAmo or coreFix_memExe_dMem_cache_m_banks_0_pipeline$first) begin @@ -39345,22 +39316,40 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448]; endcase end + always@(coreFix_memExe_dMem_cache_m_banks_0_processAmo or + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first) + begin + case (coreFix_memExe_dMem_cache_m_banks_0_processAmo[167:166]) + 2'd0: + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4867 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0]; + 2'd1: + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4867 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128]; + 2'd2: + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4867 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256]; + 2'd3: + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4867 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384]; + endcase + end always@(coreFix_memExe_dMem_cache_m_banks_0_processAmo or SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4867 or SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4861) begin case (coreFix_memExe_dMem_cache_m_banks_0_processAmo[165:164]) 2'd0: - x__h264887 = + x__h264885 = SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4867[31:0]; 2'd1: - x__h264887 = + x__h264885 = SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4867[63:32]; 2'd2: - x__h264887 = + x__h264885 = SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4861[31:0]; 2'd3: - x__h264887 = + x__h264885 = SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4861[63:32]; endcase end @@ -39524,394 +39513,446 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[516]; endcase end - always@(guard__h585173 or - _theResult___fst_exp__h593221 or - out_exp__h593666 or _theResult___exp__h593663) + always@(guard__h585171 or + _theResult___fst_exp__h593219 or + out_exp__h593664 or _theResult___exp__h593661) begin - case (guard__h585173) + case (guard__h585171) 2'b0, 2'b01: - CASE_guard85173_0b0_theResult___fst_exp93221_0_ETC__q44 = - _theResult___fst_exp__h593221; + CASE_guard85171_0b0_theResult___fst_exp93219_0_ETC__q44 = + _theResult___fst_exp__h593219; 2'b10: - CASE_guard85173_0b0_theResult___fst_exp93221_0_ETC__q44 = - out_exp__h593666; + CASE_guard85171_0b0_theResult___fst_exp93219_0_ETC__q44 = + out_exp__h593664; 2'b11: - CASE_guard85173_0b0_theResult___fst_exp93221_0_ETC__q44 = - _theResult___exp__h593663; + CASE_guard85171_0b0_theResult___fst_exp93219_0_ETC__q44 = + _theResult___exp__h593661; endcase end - always@(guard__h585173 or - _theResult___fst_exp__h593221 or _theResult___exp__h593663) + always@(guard__h585171 or + _theResult___fst_exp__h593219 or _theResult___exp__h593661) begin - case (guard__h585173) + case (guard__h585171) 2'b0: - CASE_guard85173_0b0_theResult___fst_exp93221_0_ETC__q45 = - _theResult___fst_exp__h593221; + CASE_guard85171_0b0_theResult___fst_exp93219_0_ETC__q45 = + _theResult___fst_exp__h593219; 2'b01, 2'b10, 2'b11: - CASE_guard85173_0b0_theResult___fst_exp93221_0_ETC__q45 = - _theResult___exp__h593663; + CASE_guard85171_0b0_theResult___fst_exp93219_0_ETC__q45 = + _theResult___exp__h593661; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard85173_0b0_theResult___fst_exp93221_0_ETC__q44 or - CASE_guard85173_0b0_theResult___fst_exp93221_0_ETC__q45 or + CASE_guard85171_0b0_theResult___fst_exp93219_0_ETC__q44 or + CASE_guard85171_0b0_theResult___fst_exp93219_0_ETC__q45 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d8655 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d8657 or - _theResult___fst_exp__h593221) + _theResult___fst_exp__h593219) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h593741 = - CASE_guard85173_0b0_theResult___fst_exp93221_0_ETC__q44; + _theResult___fst_exp__h593739 = + CASE_guard85171_0b0_theResult___fst_exp93219_0_ETC__q44; 3'd1: - _theResult___fst_exp__h593741 = - CASE_guard85173_0b0_theResult___fst_exp93221_0_ETC__q45; + _theResult___fst_exp__h593739 = + CASE_guard85171_0b0_theResult___fst_exp93219_0_ETC__q45; 3'd2: - _theResult___fst_exp__h593741 = + _theResult___fst_exp__h593739 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d8655; 3'd3: - _theResult___fst_exp__h593741 = + _theResult___fst_exp__h593739 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d8657; - 3'd4: _theResult___fst_exp__h593741 = _theResult___fst_exp__h593221; - default: _theResult___fst_exp__h593741 = 8'd0; + 3'd4: _theResult___fst_exp__h593739 = _theResult___fst_exp__h593219; + default: _theResult___fst_exp__h593739 = 8'd0; endcase end - always@(guard__h576464 or - _theResult___fst_exp__h584565 or - out_exp__h585084 or _theResult___exp__h585081) + always@(guard__h576462 or + _theResult___fst_exp__h584563 or + out_exp__h585082 or _theResult___exp__h585079) begin - case (guard__h576464) + case (guard__h576462) 2'b0, 2'b01: - CASE_guard76464_0b0_theResult___fst_exp84565_0_ETC__q46 = - _theResult___fst_exp__h584565; + CASE_guard76462_0b0_theResult___fst_exp84563_0_ETC__q46 = + _theResult___fst_exp__h584563; 2'b10: - CASE_guard76464_0b0_theResult___fst_exp84565_0_ETC__q46 = - out_exp__h585084; + CASE_guard76462_0b0_theResult___fst_exp84563_0_ETC__q46 = + out_exp__h585082; 2'b11: - CASE_guard76464_0b0_theResult___fst_exp84565_0_ETC__q46 = - _theResult___exp__h585081; + CASE_guard76462_0b0_theResult___fst_exp84563_0_ETC__q46 = + _theResult___exp__h585079; endcase end - always@(guard__h576464 or - _theResult___fst_exp__h584565 or _theResult___exp__h585081) + always@(guard__h576462 or + _theResult___fst_exp__h584563 or _theResult___exp__h585079) begin - case (guard__h576464) + case (guard__h576462) 2'b0: - CASE_guard76464_0b0_theResult___fst_exp84565_0_ETC__q47 = - _theResult___fst_exp__h584565; + CASE_guard76462_0b0_theResult___fst_exp84563_0_ETC__q47 = + _theResult___fst_exp__h584563; 2'b01, 2'b10, 2'b11: - CASE_guard76464_0b0_theResult___fst_exp84565_0_ETC__q47 = - _theResult___exp__h585081; + CASE_guard76462_0b0_theResult___fst_exp84563_0_ETC__q47 = + _theResult___exp__h585079; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard76464_0b0_theResult___fst_exp84565_0_ETC__q46 or - CASE_guard76464_0b0_theResult___fst_exp84565_0_ETC__q47 or + CASE_guard76462_0b0_theResult___fst_exp84563_0_ETC__q46 or + CASE_guard76462_0b0_theResult___fst_exp84563_0_ETC__q47 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d8433 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d8436 or - _theResult___fst_exp__h584565) + _theResult___fst_exp__h584563) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h585159 = - CASE_guard76464_0b0_theResult___fst_exp84565_0_ETC__q46; + _theResult___fst_exp__h585157 = + CASE_guard76462_0b0_theResult___fst_exp84563_0_ETC__q46; 3'd1: - _theResult___fst_exp__h585159 = - CASE_guard76464_0b0_theResult___fst_exp84565_0_ETC__q47; + _theResult___fst_exp__h585157 = + CASE_guard76462_0b0_theResult___fst_exp84563_0_ETC__q47; 3'd2: - _theResult___fst_exp__h585159 = + _theResult___fst_exp__h585157 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d8433; 3'd3: - _theResult___fst_exp__h585159 = + _theResult___fst_exp__h585157 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d8436; - 3'd4: _theResult___fst_exp__h585159 = _theResult___fst_exp__h584565; - default: _theResult___fst_exp__h585159 = 8'd0; + 3'd4: _theResult___fst_exp__h585157 = _theResult___fst_exp__h584563; + default: _theResult___fst_exp__h585157 = 8'd0; endcase end - always@(guard__h594103 or - _theResult___fst_exp__h602331 or - out_exp__h602850 or _theResult___exp__h602847) + always@(guard__h594101 or + _theResult___fst_exp__h602329 or + out_exp__h602848 or _theResult___exp__h602845) begin - case (guard__h594103) + case (guard__h594101) 2'b0, 2'b01: - CASE_guard94103_0b0_theResult___fst_exp02331_0_ETC__q52 = - _theResult___fst_exp__h602331; + CASE_guard94101_0b0_theResult___fst_exp02329_0_ETC__q52 = + _theResult___fst_exp__h602329; 2'b10: - CASE_guard94103_0b0_theResult___fst_exp02331_0_ETC__q52 = - out_exp__h602850; + CASE_guard94101_0b0_theResult___fst_exp02329_0_ETC__q52 = + out_exp__h602848; 2'b11: - CASE_guard94103_0b0_theResult___fst_exp02331_0_ETC__q52 = - _theResult___exp__h602847; + CASE_guard94101_0b0_theResult___fst_exp02329_0_ETC__q52 = + _theResult___exp__h602845; endcase end - always@(guard__h594103 or - _theResult___fst_exp__h602331 or _theResult___exp__h602847) + always@(guard__h594101 or + _theResult___fst_exp__h602329 or _theResult___exp__h602845) begin - case (guard__h594103) + case (guard__h594101) 2'b0: - CASE_guard94103_0b0_theResult___fst_exp02331_0_ETC__q53 = - _theResult___fst_exp__h602331; + CASE_guard94101_0b0_theResult___fst_exp02329_0_ETC__q53 = + _theResult___fst_exp__h602329; 2'b01, 2'b10, 2'b11: - CASE_guard94103_0b0_theResult___fst_exp02331_0_ETC__q53 = - _theResult___exp__h602847; + CASE_guard94101_0b0_theResult___fst_exp02329_0_ETC__q53 = + _theResult___exp__h602845; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard94103_0b0_theResult___fst_exp02331_0_ETC__q52 or - CASE_guard94103_0b0_theResult___fst_exp02331_0_ETC__q53 or + CASE_guard94101_0b0_theResult___fst_exp02329_0_ETC__q52 or + CASE_guard94101_0b0_theResult___fst_exp02329_0_ETC__q53 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d8980 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d8982 or - _theResult___fst_exp__h602331) + _theResult___fst_exp__h602329) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h602925 = - CASE_guard94103_0b0_theResult___fst_exp02331_0_ETC__q52; + _theResult___fst_exp__h602923 = + CASE_guard94101_0b0_theResult___fst_exp02329_0_ETC__q52; 3'd1: - _theResult___fst_exp__h602925 = - CASE_guard94103_0b0_theResult___fst_exp02331_0_ETC__q53; + _theResult___fst_exp__h602923 = + CASE_guard94101_0b0_theResult___fst_exp02329_0_ETC__q53; 3'd2: - _theResult___fst_exp__h602925 = + _theResult___fst_exp__h602923 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d8980; 3'd3: - _theResult___fst_exp__h602925 = + _theResult___fst_exp__h602923 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d8982; - 3'd4: _theResult___fst_exp__h602925 = _theResult___fst_exp__h602331; - default: _theResult___fst_exp__h602925 = 8'd0; + 3'd4: _theResult___fst_exp__h602923 = _theResult___fst_exp__h602329; + default: _theResult___fst_exp__h602923 = 8'd0; endcase end - always@(guard__h602939 or - _theResult___fst_exp__h611016 or - out_exp__h611486 or _theResult___exp__h611483) + always@(guard__h602937 or + _theResult___fst_exp__h611014 or + out_exp__h611484 or _theResult___exp__h611481) begin - case (guard__h602939) + case (guard__h602937) 2'b0, 2'b01: - CASE_guard02939_0b0_theResult___fst_exp11016_0_ETC__q57 = - _theResult___fst_exp__h611016; + CASE_guard02937_0b0_theResult___fst_exp11014_0_ETC__q57 = + _theResult___fst_exp__h611014; 2'b10: - CASE_guard02939_0b0_theResult___fst_exp11016_0_ETC__q57 = - out_exp__h611486; + CASE_guard02937_0b0_theResult___fst_exp11014_0_ETC__q57 = + out_exp__h611484; 2'b11: - CASE_guard02939_0b0_theResult___fst_exp11016_0_ETC__q57 = - _theResult___exp__h611483; + CASE_guard02937_0b0_theResult___fst_exp11014_0_ETC__q57 = + _theResult___exp__h611481; endcase end - always@(guard__h602939 or - _theResult___fst_exp__h611016 or _theResult___exp__h611483) + always@(guard__h602937 or + _theResult___fst_exp__h611014 or _theResult___exp__h611481) begin - case (guard__h602939) + case (guard__h602937) 2'b0: - CASE_guard02939_0b0_theResult___fst_exp11016_0_ETC__q58 = - _theResult___fst_exp__h611016; + CASE_guard02937_0b0_theResult___fst_exp11014_0_ETC__q58 = + _theResult___fst_exp__h611014; 2'b01, 2'b10, 2'b11: - CASE_guard02939_0b0_theResult___fst_exp11016_0_ETC__q58 = - _theResult___exp__h611483; + CASE_guard02937_0b0_theResult___fst_exp11014_0_ETC__q58 = + _theResult___exp__h611481; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard02939_0b0_theResult___fst_exp11016_0_ETC__q57 or - CASE_guard02939_0b0_theResult___fst_exp11016_0_ETC__q58 or + CASE_guard02937_0b0_theResult___fst_exp11014_0_ETC__q57 or + CASE_guard02937_0b0_theResult___fst_exp11014_0_ETC__q58 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9049 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9051 or - _theResult___fst_exp__h611016) + _theResult___fst_exp__h611014) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h611561 = - CASE_guard02939_0b0_theResult___fst_exp11016_0_ETC__q57; + _theResult___fst_exp__h611559 = + CASE_guard02937_0b0_theResult___fst_exp11014_0_ETC__q57; 3'd1: - _theResult___fst_exp__h611561 = - CASE_guard02939_0b0_theResult___fst_exp11016_0_ETC__q58; + _theResult___fst_exp__h611559 = + CASE_guard02937_0b0_theResult___fst_exp11014_0_ETC__q58; 3'd2: - _theResult___fst_exp__h611561 = + _theResult___fst_exp__h611559 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9049; 3'd3: - _theResult___fst_exp__h611561 = + _theResult___fst_exp__h611559 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9051; - 3'd4: _theResult___fst_exp__h611561 = _theResult___fst_exp__h611016; - default: _theResult___fst_exp__h611561 = 8'd0; + 3'd4: _theResult___fst_exp__h611559 = _theResult___fst_exp__h611014; + default: _theResult___fst_exp__h611559 = 8'd0; endcase end - always@(guard__h585173 or - _theResult___snd__h593172 or - out_sfd__h593667 or _theResult___sfd__h593664) + always@(guard__h585171 or + _theResult___snd__h593170 or + out_sfd__h593665 or _theResult___sfd__h593662) begin - case (guard__h585173) + case (guard__h585171) 2'b0, 2'b01: - CASE_guard85173_0b0_theResult___snd93172_BITS__ETC__q59 = - _theResult___snd__h593172[56:34]; + CASE_guard85171_0b0_theResult___snd93170_BITS__ETC__q59 = + _theResult___snd__h593170[56:34]; 2'b10: - CASE_guard85173_0b0_theResult___snd93172_BITS__ETC__q59 = - out_sfd__h593667; + CASE_guard85171_0b0_theResult___snd93170_BITS__ETC__q59 = + out_sfd__h593665; 2'b11: - CASE_guard85173_0b0_theResult___snd93172_BITS__ETC__q59 = - _theResult___sfd__h593664; + CASE_guard85171_0b0_theResult___snd93170_BITS__ETC__q59 = + _theResult___sfd__h593662; endcase end - always@(guard__h585173 or - _theResult___snd__h593172 or _theResult___sfd__h593664) + always@(guard__h585171 or + _theResult___snd__h593170 or _theResult___sfd__h593662) begin - case (guard__h585173) + case (guard__h585171) 2'b0: - CASE_guard85173_0b0_theResult___snd93172_BITS__ETC__q60 = - _theResult___snd__h593172[56:34]; + CASE_guard85171_0b0_theResult___snd93170_BITS__ETC__q60 = + _theResult___snd__h593170[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard85173_0b0_theResult___snd93172_BITS__ETC__q60 = - _theResult___sfd__h593664; + CASE_guard85171_0b0_theResult___snd93170_BITS__ETC__q60 = + _theResult___sfd__h593662; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard85173_0b0_theResult___snd93172_BITS__ETC__q59 or - CASE_guard85173_0b0_theResult___snd93172_BITS__ETC__q60 or + CASE_guard85171_0b0_theResult___snd93170_BITS__ETC__q59 or + CASE_guard85171_0b0_theResult___snd93170_BITS__ETC__q60 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9099 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9101 or - _theResult___snd__h593172) + _theResult___snd__h593170) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h593742 = - CASE_guard85173_0b0_theResult___snd93172_BITS__ETC__q59; + _theResult___fst_sfd__h593740 = + CASE_guard85171_0b0_theResult___snd93170_BITS__ETC__q59; 3'd1: - _theResult___fst_sfd__h593742 = - CASE_guard85173_0b0_theResult___snd93172_BITS__ETC__q60; + _theResult___fst_sfd__h593740 = + CASE_guard85171_0b0_theResult___snd93170_BITS__ETC__q60; 3'd2: - _theResult___fst_sfd__h593742 = + _theResult___fst_sfd__h593740 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9099; 3'd3: - _theResult___fst_sfd__h593742 = + _theResult___fst_sfd__h593740 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9101; - 3'd4: _theResult___fst_sfd__h593742 = _theResult___snd__h593172[56:34]; - default: _theResult___fst_sfd__h593742 = 23'd0; + 3'd4: _theResult___fst_sfd__h593740 = _theResult___snd__h593170[56:34]; + default: _theResult___fst_sfd__h593740 = 23'd0; endcase end - always@(guard__h576464 or - sfdin__h584559 or out_sfd__h585085 or _theResult___sfd__h585082) + always@(guard__h576462 or + sfdin__h584557 or out_sfd__h585083 or _theResult___sfd__h585080) begin - case (guard__h576464) + case (guard__h576462) 2'b0, 2'b01: - CASE_guard76464_0b0_sfdin84559_BITS_56_TO_34_0_ETC__q61 = - sfdin__h584559[56:34]; + CASE_guard76462_0b0_sfdin84557_BITS_56_TO_34_0_ETC__q61 = + sfdin__h584557[56:34]; 2'b10: - CASE_guard76464_0b0_sfdin84559_BITS_56_TO_34_0_ETC__q61 = - out_sfd__h585085; + CASE_guard76462_0b0_sfdin84557_BITS_56_TO_34_0_ETC__q61 = + out_sfd__h585083; 2'b11: - CASE_guard76464_0b0_sfdin84559_BITS_56_TO_34_0_ETC__q61 = - _theResult___sfd__h585082; + CASE_guard76462_0b0_sfdin84557_BITS_56_TO_34_0_ETC__q61 = + _theResult___sfd__h585080; endcase end - always@(guard__h576464 or sfdin__h584559 or _theResult___sfd__h585082) + always@(guard__h576462 or sfdin__h584557 or _theResult___sfd__h585080) begin - case (guard__h576464) + case (guard__h576462) 2'b0: - CASE_guard76464_0b0_sfdin84559_BITS_56_TO_34_0_ETC__q62 = - sfdin__h584559[56:34]; + CASE_guard76462_0b0_sfdin84557_BITS_56_TO_34_0_ETC__q62 = + sfdin__h584557[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard76464_0b0_sfdin84559_BITS_56_TO_34_0_ETC__q62 = - _theResult___sfd__h585082; + CASE_guard76462_0b0_sfdin84557_BITS_56_TO_34_0_ETC__q62 = + _theResult___sfd__h585080; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard76464_0b0_sfdin84559_BITS_56_TO_34_0_ETC__q61 or - CASE_guard76464_0b0_sfdin84559_BITS_56_TO_34_0_ETC__q62 or + CASE_guard76462_0b0_sfdin84557_BITS_56_TO_34_0_ETC__q61 or + CASE_guard76462_0b0_sfdin84557_BITS_56_TO_34_0_ETC__q62 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9080 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9082 or - sfdin__h584559) + sfdin__h584557) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h585160 = - CASE_guard76464_0b0_sfdin84559_BITS_56_TO_34_0_ETC__q61; + _theResult___fst_sfd__h585158 = + CASE_guard76462_0b0_sfdin84557_BITS_56_TO_34_0_ETC__q61; 3'd1: - _theResult___fst_sfd__h585160 = - CASE_guard76464_0b0_sfdin84559_BITS_56_TO_34_0_ETC__q62; + _theResult___fst_sfd__h585158 = + CASE_guard76462_0b0_sfdin84557_BITS_56_TO_34_0_ETC__q62; 3'd2: - _theResult___fst_sfd__h585160 = + _theResult___fst_sfd__h585158 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9080; 3'd3: - _theResult___fst_sfd__h585160 = + _theResult___fst_sfd__h585158 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9082; - 3'd4: _theResult___fst_sfd__h585160 = sfdin__h584559[56:34]; - default: _theResult___fst_sfd__h585160 = 23'd0; + 3'd4: _theResult___fst_sfd__h585158 = sfdin__h584557[56:34]; + default: _theResult___fst_sfd__h585158 = 23'd0; endcase end - always@(guard__h594103 or - sfdin__h602325 or out_sfd__h602851 or _theResult___sfd__h602848) + always@(guard__h594101 or + sfdin__h602323 or out_sfd__h602849 or _theResult___sfd__h602846) begin - case (guard__h594103) + case (guard__h594101) 2'b0, 2'b01: - CASE_guard94103_0b0_sfdin02325_BITS_56_TO_34_0_ETC__q63 = - sfdin__h602325[56:34]; + CASE_guard94101_0b0_sfdin02323_BITS_56_TO_34_0_ETC__q63 = + sfdin__h602323[56:34]; 2'b10: - CASE_guard94103_0b0_sfdin02325_BITS_56_TO_34_0_ETC__q63 = - out_sfd__h602851; + CASE_guard94101_0b0_sfdin02323_BITS_56_TO_34_0_ETC__q63 = + out_sfd__h602849; 2'b11: - CASE_guard94103_0b0_sfdin02325_BITS_56_TO_34_0_ETC__q63 = - _theResult___sfd__h602848; + CASE_guard94101_0b0_sfdin02323_BITS_56_TO_34_0_ETC__q63 = + _theResult___sfd__h602846; endcase end - always@(guard__h594103 or sfdin__h602325 or _theResult___sfd__h602848) + always@(guard__h594101 or sfdin__h602323 or _theResult___sfd__h602846) begin - case (guard__h594103) + case (guard__h594101) 2'b0: - CASE_guard94103_0b0_sfdin02325_BITS_56_TO_34_0_ETC__q64 = - sfdin__h602325[56:34]; + CASE_guard94101_0b0_sfdin02323_BITS_56_TO_34_0_ETC__q64 = + sfdin__h602323[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard94103_0b0_sfdin02325_BITS_56_TO_34_0_ETC__q64 = - _theResult___sfd__h602848; + CASE_guard94101_0b0_sfdin02323_BITS_56_TO_34_0_ETC__q64 = + _theResult___sfd__h602846; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard94103_0b0_sfdin02325_BITS_56_TO_34_0_ETC__q63 or - CASE_guard94103_0b0_sfdin02325_BITS_56_TO_34_0_ETC__q64 or + CASE_guard94101_0b0_sfdin02323_BITS_56_TO_34_0_ETC__q63 or + CASE_guard94101_0b0_sfdin02323_BITS_56_TO_34_0_ETC__q64 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9126 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9128 or - sfdin__h602325) + sfdin__h602323) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h602926 = - CASE_guard94103_0b0_sfdin02325_BITS_56_TO_34_0_ETC__q63; + _theResult___fst_sfd__h602924 = + CASE_guard94101_0b0_sfdin02323_BITS_56_TO_34_0_ETC__q63; 3'd1: - _theResult___fst_sfd__h602926 = - CASE_guard94103_0b0_sfdin02325_BITS_56_TO_34_0_ETC__q64; + _theResult___fst_sfd__h602924 = + CASE_guard94101_0b0_sfdin02323_BITS_56_TO_34_0_ETC__q64; 3'd2: - _theResult___fst_sfd__h602926 = + _theResult___fst_sfd__h602924 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9126; 3'd3: - _theResult___fst_sfd__h602926 = + _theResult___fst_sfd__h602924 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9128; - 3'd4: _theResult___fst_sfd__h602926 = sfdin__h602325[56:34]; - default: _theResult___fst_sfd__h602926 = 23'd0; + 3'd4: _theResult___fst_sfd__h602924 = sfdin__h602323[56:34]; + default: _theResult___fst_sfd__h602924 = 23'd0; endcase end - always@(guard__h576464 or + always@(guard__h602937 or + _theResult___snd__h610960 or + out_sfd__h611485 or _theResult___sfd__h611482) + begin + case (guard__h602937) + 2'b0, 2'b01: + CASE_guard02937_0b0_theResult___snd10960_BITS__ETC__q65 = + _theResult___snd__h610960[56:34]; + 2'b10: + CASE_guard02937_0b0_theResult___snd10960_BITS__ETC__q65 = + out_sfd__h611485; + 2'b11: + CASE_guard02937_0b0_theResult___snd10960_BITS__ETC__q65 = + _theResult___sfd__h611482; + endcase + end + always@(guard__h602937 or + _theResult___snd__h610960 or _theResult___sfd__h611482) + begin + case (guard__h602937) + 2'b0: + CASE_guard02937_0b0_theResult___snd10960_BITS__ETC__q66 = + _theResult___snd__h610960[56:34]; + 2'b01, 2'b10, 2'b11: + CASE_guard02937_0b0_theResult___snd10960_BITS__ETC__q66 = + _theResult___sfd__h611482; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or + CASE_guard02937_0b0_theResult___snd10960_BITS__ETC__q65 or + CASE_guard02937_0b0_theResult___snd10960_BITS__ETC__q66 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9145 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9147 or + _theResult___snd__h610960) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) + 3'd0: + _theResult___fst_sfd__h611560 = + CASE_guard02937_0b0_theResult___snd10960_BITS__ETC__q65; + 3'd1: + _theResult___fst_sfd__h611560 = + CASE_guard02937_0b0_theResult___snd10960_BITS__ETC__q66; + 3'd2: + _theResult___fst_sfd__h611560 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9145; + 3'd3: + _theResult___fst_sfd__h611560 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9147; + 3'd4: _theResult___fst_sfd__h611560 = _theResult___snd__h610960[56:34]; + default: _theResult___fst_sfd__h611560 = 23'd0; + endcase + end + always@(guard__h576462 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h576464) + case (guard__h576462) 2'b0, 2'b01, 2'b10: - CASE_guard76464_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q65 = + CASE_guard76462_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q67 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard76464_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q65 = - guard__h576464 == 2'b11 && + CASE_guard76462_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q67 = + guard__h576462 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard76464_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q65 or - guard__h576464) + CASE_guard76462_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q67 or + guard__h576462) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9233 = - CASE_guard76464_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q65; + CASE_guard76462_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q67; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9233 = - (guard__h576464 == 2'b0) ? + (guard__h576462 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h576464 == 2'b01 || guard__h576464 == 2'b10 || - guard__h576464 == 2'b11) && + (guard__h576462 == 2'b01 || guard__h576462 == 2'b10 || + guard__h576462 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9233 = @@ -39922,86 +39963,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h602939 or - _theResult___snd__h610962 or - out_sfd__h611487 or _theResult___sfd__h611484) - begin - case (guard__h602939) - 2'b0, 2'b01: - CASE_guard02939_0b0_theResult___snd10962_BITS__ETC__q66 = - _theResult___snd__h610962[56:34]; - 2'b10: - CASE_guard02939_0b0_theResult___snd10962_BITS__ETC__q66 = - out_sfd__h611487; - 2'b11: - CASE_guard02939_0b0_theResult___snd10962_BITS__ETC__q66 = - _theResult___sfd__h611484; - endcase - end - always@(guard__h602939 or - _theResult___snd__h610962 or _theResult___sfd__h611484) - begin - case (guard__h602939) - 2'b0: - CASE_guard02939_0b0_theResult___snd10962_BITS__ETC__q67 = - _theResult___snd__h610962[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard02939_0b0_theResult___snd10962_BITS__ETC__q67 = - _theResult___sfd__h611484; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard02939_0b0_theResult___snd10962_BITS__ETC__q66 or - CASE_guard02939_0b0_theResult___snd10962_BITS__ETC__q67 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9145 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9147 or - _theResult___snd__h610962) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0: - _theResult___fst_sfd__h611562 = - CASE_guard02939_0b0_theResult___snd10962_BITS__ETC__q66; - 3'd1: - _theResult___fst_sfd__h611562 = - CASE_guard02939_0b0_theResult___snd10962_BITS__ETC__q67; - 3'd2: - _theResult___fst_sfd__h611562 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9145; - 3'd3: - _theResult___fst_sfd__h611562 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d9147; - 3'd4: _theResult___fst_sfd__h611562 = _theResult___snd__h610962[56:34]; - default: _theResult___fst_sfd__h611562 = 23'd0; - endcase - end - always@(guard__h576464 or + always@(guard__h576462 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h576464) + case (guard__h576462) 2'b0, 2'b01, 2'b10: - CASE_guard76464_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q68 = + CASE_guard76462_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q68 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard76464_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q68 = - guard__h576464 != 2'b11 || + CASE_guard76462_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q68 = + guard__h576462 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard76464_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q68 or - guard__h576464) + CASE_guard76462_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q68 or + guard__h576462) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9177 = - CASE_guard76464_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q68; + CASE_guard76462_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q68; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9177 = - (guard__h576464 == 2'b0) ? + (guard__h576462 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h576464 != 2'b01 && guard__h576464 != 2'b10 && - guard__h576464 != 2'b11 || + guard__h576462 != 2'b01 && guard__h576462 != 2'b10 && + guard__h576462 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9177 = @@ -40012,34 +40001,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h585173 or + always@(guard__h585171 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h585173) + case (guard__h585171) 2'b0, 2'b01, 2'b10: - CASE_guard85173_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q69 = + CASE_guard85171_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q69 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard85173_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q69 = - guard__h585173 == 2'b11 && + CASE_guard85171_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q69 = + guard__h585171 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard85173_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q69 or - guard__h585173) + CASE_guard85171_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q69 or + guard__h585171) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9240 = - CASE_guard85173_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q69; + CASE_guard85171_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q69; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9240 = - (guard__h585173 == 2'b0) ? + (guard__h585171 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h585173 == 2'b01 || guard__h585173 == 2'b10 || - guard__h585173 == 2'b11) && + (guard__h585171 == 2'b01 || guard__h585171 == 2'b10 || + guard__h585171 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9240 = @@ -40050,34 +40039,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h585173 or + always@(guard__h585171 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h585173) + case (guard__h585171) 2'b0, 2'b01, 2'b10: - CASE_guard85173_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q70 = + CASE_guard85171_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q70 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard85173_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q70 = - guard__h585173 != 2'b11 || + CASE_guard85171_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q70 = + guard__h585171 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard85173_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q70 or - guard__h585173) + CASE_guard85171_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q70 or + guard__h585171) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9190 = - CASE_guard85173_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q70; + CASE_guard85171_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q70; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9190 = - (guard__h585173 == 2'b0) ? + (guard__h585171 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h585173 != 2'b01 && guard__h585173 != 2'b10 && - guard__h585173 != 2'b11 || + guard__h585171 != 2'b01 && guard__h585171 != 2'b10 && + guard__h585171 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9190 = @@ -40088,34 +40077,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h594103 or + always@(guard__h594101 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h594103) + case (guard__h594101) 2'b0, 2'b01, 2'b10: - CASE_guard94103_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q71 = + CASE_guard94101_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q71 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard94103_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q71 = - guard__h594103 == 2'b11 && + CASE_guard94101_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q71 = + guard__h594101 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard94103_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q71 or - guard__h594103) + CASE_guard94101_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q71 or + guard__h594101) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9250 = - CASE_guard94103_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q71; + CASE_guard94101_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q71; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9250 = - (guard__h594103 == 2'b0) ? + (guard__h594101 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h594103 == 2'b01 || guard__h594103 == 2'b10 || - guard__h594103 == 2'b11) && + (guard__h594101 == 2'b01 || guard__h594101 == 2'b10 || + guard__h594101 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9250 = @@ -40126,34 +40115,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h594103 or + always@(guard__h594101 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h594103) + case (guard__h594101) 2'b0, 2'b01, 2'b10: - CASE_guard94103_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q72 = + CASE_guard94101_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q72 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard94103_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q72 = - guard__h594103 != 2'b11 || + CASE_guard94101_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q72 = + guard__h594101 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard94103_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q72 or - guard__h594103) + CASE_guard94101_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q72 or + guard__h594101) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9207 = - CASE_guard94103_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q72; + CASE_guard94101_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q72; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9207 = - (guard__h594103 == 2'b0) ? + (guard__h594101 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h594103 != 2'b01 && guard__h594103 != 2'b10 && - guard__h594103 != 2'b11 || + guard__h594101 != 2'b01 && guard__h594101 != 2'b10 && + guard__h594101 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9207 = @@ -40164,34 +40153,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h602939 or + always@(guard__h602937 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h602939) + case (guard__h602937) 2'b0, 2'b01, 2'b10: - CASE_guard02939_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q73 = + CASE_guard02937_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q73 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard02939_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q73 = - guard__h602939 == 2'b11 && + CASE_guard02937_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q73 = + guard__h602937 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard02939_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q73 or - guard__h602939) + CASE_guard02937_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q73 or + guard__h602937) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9257 = - CASE_guard02939_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q73; + CASE_guard02937_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q73; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9257 = - (guard__h602939 == 2'b0) ? + (guard__h602937 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h602939 == 2'b01 || guard__h602939 == 2'b10 || - guard__h602939 == 2'b11) && + (guard__h602937 == 2'b01 || guard__h602937 == 2'b10 || + guard__h602937 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9257 = @@ -40202,34 +40191,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h602939 or + always@(guard__h602937 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h602939) + case (guard__h602937) 2'b0, 2'b01, 2'b10: - CASE_guard02939_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q74 = + CASE_guard02937_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q74 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard02939_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q74 = - guard__h602939 != 2'b11 || + CASE_guard02937_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q74 = + guard__h602937 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard02939_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q74 or - guard__h602939) + CASE_guard02937_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q74 or + guard__h602937) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9220 = - CASE_guard02939_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q74; + CASE_guard02937_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q74; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9220 = - (guard__h602939 == 2'b0) ? + (guard__h602937 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h602939 != 2'b01 && guard__h602939 != 2'b10 && - guard__h602939 != 2'b11 || + guard__h602937 != 2'b01 && guard__h602937 != 2'b10 && + guard__h602937 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d9220 = @@ -40266,446 +40255,394 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h630922 or - _theResult___fst_exp__h638970 or - out_exp__h639415 or _theResult___exp__h639412) + always@(guard__h630920 or + _theResult___fst_exp__h638968 or + out_exp__h639413 or _theResult___exp__h639410) begin - case (guard__h630922) + case (guard__h630920) 2'b0, 2'b01: - CASE_guard30922_0b0_theResult___fst_exp38970_0_ETC__q79 = - _theResult___fst_exp__h638970; + CASE_guard30920_0b0_theResult___fst_exp38968_0_ETC__q79 = + _theResult___fst_exp__h638968; 2'b10: - CASE_guard30922_0b0_theResult___fst_exp38970_0_ETC__q79 = - out_exp__h639415; + CASE_guard30920_0b0_theResult___fst_exp38968_0_ETC__q79 = + out_exp__h639413; 2'b11: - CASE_guard30922_0b0_theResult___fst_exp38970_0_ETC__q79 = - _theResult___exp__h639412; + CASE_guard30920_0b0_theResult___fst_exp38968_0_ETC__q79 = + _theResult___exp__h639410; endcase end - always@(guard__h630922 or - _theResult___fst_exp__h638970 or _theResult___exp__h639412) + always@(guard__h630920 or + _theResult___fst_exp__h638968 or _theResult___exp__h639410) begin - case (guard__h630922) + case (guard__h630920) 2'b0: - CASE_guard30922_0b0_theResult___fst_exp38970_0_ETC__q80 = - _theResult___fst_exp__h638970; + CASE_guard30920_0b0_theResult___fst_exp38968_0_ETC__q80 = + _theResult___fst_exp__h638968; 2'b01, 2'b10, 2'b11: - CASE_guard30922_0b0_theResult___fst_exp38970_0_ETC__q80 = - _theResult___exp__h639412; + CASE_guard30920_0b0_theResult___fst_exp38968_0_ETC__q80 = + _theResult___exp__h639410; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard30922_0b0_theResult___fst_exp38970_0_ETC__q79 or - CASE_guard30922_0b0_theResult___fst_exp38970_0_ETC__q80 or + CASE_guard30920_0b0_theResult___fst_exp38968_0_ETC__q79 or + CASE_guard30920_0b0_theResult___fst_exp38968_0_ETC__q80 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10052 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10054 or - _theResult___fst_exp__h638970) + _theResult___fst_exp__h638968) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h639490 = - CASE_guard30922_0b0_theResult___fst_exp38970_0_ETC__q79; + _theResult___fst_exp__h639488 = + CASE_guard30920_0b0_theResult___fst_exp38968_0_ETC__q79; 3'd1: - _theResult___fst_exp__h639490 = - CASE_guard30922_0b0_theResult___fst_exp38970_0_ETC__q80; + _theResult___fst_exp__h639488 = + CASE_guard30920_0b0_theResult___fst_exp38968_0_ETC__q80; 3'd2: - _theResult___fst_exp__h639490 = + _theResult___fst_exp__h639488 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10052; 3'd3: - _theResult___fst_exp__h639490 = + _theResult___fst_exp__h639488 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10054; - 3'd4: _theResult___fst_exp__h639490 = _theResult___fst_exp__h638970; - default: _theResult___fst_exp__h639490 = 8'd0; + 3'd4: _theResult___fst_exp__h639488 = _theResult___fst_exp__h638968; + default: _theResult___fst_exp__h639488 = 8'd0; endcase end - always@(guard__h622215 or - _theResult___fst_exp__h630314 or - out_exp__h630833 or _theResult___exp__h630830) + always@(guard__h622213 or + _theResult___fst_exp__h630312 or + out_exp__h630831 or _theResult___exp__h630828) begin - case (guard__h622215) + case (guard__h622213) 2'b0, 2'b01: - CASE_guard22215_0b0_theResult___fst_exp30314_0_ETC__q81 = - _theResult___fst_exp__h630314; + CASE_guard22213_0b0_theResult___fst_exp30312_0_ETC__q81 = + _theResult___fst_exp__h630312; 2'b10: - CASE_guard22215_0b0_theResult___fst_exp30314_0_ETC__q81 = - out_exp__h630833; + CASE_guard22213_0b0_theResult___fst_exp30312_0_ETC__q81 = + out_exp__h630831; 2'b11: - CASE_guard22215_0b0_theResult___fst_exp30314_0_ETC__q81 = - _theResult___exp__h630830; + CASE_guard22213_0b0_theResult___fst_exp30312_0_ETC__q81 = + _theResult___exp__h630828; endcase end - always@(guard__h622215 or - _theResult___fst_exp__h630314 or _theResult___exp__h630830) + always@(guard__h622213 or + _theResult___fst_exp__h630312 or _theResult___exp__h630828) begin - case (guard__h622215) + case (guard__h622213) 2'b0: - CASE_guard22215_0b0_theResult___fst_exp30314_0_ETC__q82 = - _theResult___fst_exp__h630314; + CASE_guard22213_0b0_theResult___fst_exp30312_0_ETC__q82 = + _theResult___fst_exp__h630312; 2'b01, 2'b10, 2'b11: - CASE_guard22215_0b0_theResult___fst_exp30314_0_ETC__q82 = - _theResult___exp__h630830; + CASE_guard22213_0b0_theResult___fst_exp30312_0_ETC__q82 = + _theResult___exp__h630828; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard22215_0b0_theResult___fst_exp30314_0_ETC__q81 or - CASE_guard22215_0b0_theResult___fst_exp30314_0_ETC__q82 or + CASE_guard22213_0b0_theResult___fst_exp30312_0_ETC__q81 or + CASE_guard22213_0b0_theResult___fst_exp30312_0_ETC__q82 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9830 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9833 or - _theResult___fst_exp__h630314) + _theResult___fst_exp__h630312) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h630908 = - CASE_guard22215_0b0_theResult___fst_exp30314_0_ETC__q81; + _theResult___fst_exp__h630906 = + CASE_guard22213_0b0_theResult___fst_exp30312_0_ETC__q81; 3'd1: - _theResult___fst_exp__h630908 = - CASE_guard22215_0b0_theResult___fst_exp30314_0_ETC__q82; + _theResult___fst_exp__h630906 = + CASE_guard22213_0b0_theResult___fst_exp30312_0_ETC__q82; 3'd2: - _theResult___fst_exp__h630908 = + _theResult___fst_exp__h630906 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9830; 3'd3: - _theResult___fst_exp__h630908 = + _theResult___fst_exp__h630906 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d9833; - 3'd4: _theResult___fst_exp__h630908 = _theResult___fst_exp__h630314; - default: _theResult___fst_exp__h630908 = 8'd0; + 3'd4: _theResult___fst_exp__h630906 = _theResult___fst_exp__h630312; + default: _theResult___fst_exp__h630906 = 8'd0; endcase end - always@(guard__h639852 or - _theResult___fst_exp__h648080 or - out_exp__h648599 or _theResult___exp__h648596) + always@(guard__h639850 or + _theResult___fst_exp__h648078 or + out_exp__h648597 or _theResult___exp__h648594) begin - case (guard__h639852) + case (guard__h639850) 2'b0, 2'b01: - CASE_guard39852_0b0_theResult___fst_exp48080_0_ETC__q87 = - _theResult___fst_exp__h648080; + CASE_guard39850_0b0_theResult___fst_exp48078_0_ETC__q87 = + _theResult___fst_exp__h648078; 2'b10: - CASE_guard39852_0b0_theResult___fst_exp48080_0_ETC__q87 = - out_exp__h648599; + CASE_guard39850_0b0_theResult___fst_exp48078_0_ETC__q87 = + out_exp__h648597; 2'b11: - CASE_guard39852_0b0_theResult___fst_exp48080_0_ETC__q87 = - _theResult___exp__h648596; + CASE_guard39850_0b0_theResult___fst_exp48078_0_ETC__q87 = + _theResult___exp__h648594; endcase end - always@(guard__h639852 or - _theResult___fst_exp__h648080 or _theResult___exp__h648596) + always@(guard__h639850 or + _theResult___fst_exp__h648078 or _theResult___exp__h648594) begin - case (guard__h639852) + case (guard__h639850) 2'b0: - CASE_guard39852_0b0_theResult___fst_exp48080_0_ETC__q88 = - _theResult___fst_exp__h648080; + CASE_guard39850_0b0_theResult___fst_exp48078_0_ETC__q88 = + _theResult___fst_exp__h648078; 2'b01, 2'b10, 2'b11: - CASE_guard39852_0b0_theResult___fst_exp48080_0_ETC__q88 = - _theResult___exp__h648596; + CASE_guard39850_0b0_theResult___fst_exp48078_0_ETC__q88 = + _theResult___exp__h648594; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard39852_0b0_theResult___fst_exp48080_0_ETC__q87 or - CASE_guard39852_0b0_theResult___fst_exp48080_0_ETC__q88 or + CASE_guard39850_0b0_theResult___fst_exp48078_0_ETC__q87 or + CASE_guard39850_0b0_theResult___fst_exp48078_0_ETC__q88 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10377 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10379 or - _theResult___fst_exp__h648080) + _theResult___fst_exp__h648078) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h648674 = - CASE_guard39852_0b0_theResult___fst_exp48080_0_ETC__q87; + _theResult___fst_exp__h648672 = + CASE_guard39850_0b0_theResult___fst_exp48078_0_ETC__q87; 3'd1: - _theResult___fst_exp__h648674 = - CASE_guard39852_0b0_theResult___fst_exp48080_0_ETC__q88; + _theResult___fst_exp__h648672 = + CASE_guard39850_0b0_theResult___fst_exp48078_0_ETC__q88; 3'd2: - _theResult___fst_exp__h648674 = + _theResult___fst_exp__h648672 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10377; 3'd3: - _theResult___fst_exp__h648674 = + _theResult___fst_exp__h648672 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10379; - 3'd4: _theResult___fst_exp__h648674 = _theResult___fst_exp__h648080; - default: _theResult___fst_exp__h648674 = 8'd0; + 3'd4: _theResult___fst_exp__h648672 = _theResult___fst_exp__h648078; + default: _theResult___fst_exp__h648672 = 8'd0; endcase end - always@(guard__h648688 or - _theResult___fst_exp__h656765 or - out_exp__h657235 or _theResult___exp__h657232) + always@(guard__h648686 or + _theResult___fst_exp__h656763 or + out_exp__h657233 or _theResult___exp__h657230) begin - case (guard__h648688) + case (guard__h648686) 2'b0, 2'b01: - CASE_guard48688_0b0_theResult___fst_exp56765_0_ETC__q92 = - _theResult___fst_exp__h656765; + CASE_guard48686_0b0_theResult___fst_exp56763_0_ETC__q92 = + _theResult___fst_exp__h656763; 2'b10: - CASE_guard48688_0b0_theResult___fst_exp56765_0_ETC__q92 = - out_exp__h657235; + CASE_guard48686_0b0_theResult___fst_exp56763_0_ETC__q92 = + out_exp__h657233; 2'b11: - CASE_guard48688_0b0_theResult___fst_exp56765_0_ETC__q92 = - _theResult___exp__h657232; + CASE_guard48686_0b0_theResult___fst_exp56763_0_ETC__q92 = + _theResult___exp__h657230; endcase end - always@(guard__h648688 or - _theResult___fst_exp__h656765 or _theResult___exp__h657232) + always@(guard__h648686 or + _theResult___fst_exp__h656763 or _theResult___exp__h657230) begin - case (guard__h648688) + case (guard__h648686) 2'b0: - CASE_guard48688_0b0_theResult___fst_exp56765_0_ETC__q93 = - _theResult___fst_exp__h656765; + CASE_guard48686_0b0_theResult___fst_exp56763_0_ETC__q93 = + _theResult___fst_exp__h656763; 2'b01, 2'b10, 2'b11: - CASE_guard48688_0b0_theResult___fst_exp56765_0_ETC__q93 = - _theResult___exp__h657232; + CASE_guard48686_0b0_theResult___fst_exp56763_0_ETC__q93 = + _theResult___exp__h657230; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard48688_0b0_theResult___fst_exp56765_0_ETC__q92 or - CASE_guard48688_0b0_theResult___fst_exp56765_0_ETC__q93 or + CASE_guard48686_0b0_theResult___fst_exp56763_0_ETC__q92 or + CASE_guard48686_0b0_theResult___fst_exp56763_0_ETC__q93 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10446 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10448 or - _theResult___fst_exp__h656765) + _theResult___fst_exp__h656763) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h657310 = - CASE_guard48688_0b0_theResult___fst_exp56765_0_ETC__q92; + _theResult___fst_exp__h657308 = + CASE_guard48686_0b0_theResult___fst_exp56763_0_ETC__q92; 3'd1: - _theResult___fst_exp__h657310 = - CASE_guard48688_0b0_theResult___fst_exp56765_0_ETC__q93; + _theResult___fst_exp__h657308 = + CASE_guard48686_0b0_theResult___fst_exp56763_0_ETC__q93; 3'd2: - _theResult___fst_exp__h657310 = + _theResult___fst_exp__h657308 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10446; 3'd3: - _theResult___fst_exp__h657310 = + _theResult___fst_exp__h657308 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10448; - 3'd4: _theResult___fst_exp__h657310 = _theResult___fst_exp__h656765; - default: _theResult___fst_exp__h657310 = 8'd0; + 3'd4: _theResult___fst_exp__h657308 = _theResult___fst_exp__h656763; + default: _theResult___fst_exp__h657308 = 8'd0; endcase end - always@(guard__h630922 or - _theResult___snd__h638921 or - out_sfd__h639416 or _theResult___sfd__h639413) + always@(guard__h630920 or + _theResult___snd__h638919 or + out_sfd__h639414 or _theResult___sfd__h639411) begin - case (guard__h630922) + case (guard__h630920) 2'b0, 2'b01: - CASE_guard30922_0b0_theResult___snd38921_BITS__ETC__q94 = - _theResult___snd__h638921[56:34]; + CASE_guard30920_0b0_theResult___snd38919_BITS__ETC__q94 = + _theResult___snd__h638919[56:34]; 2'b10: - CASE_guard30922_0b0_theResult___snd38921_BITS__ETC__q94 = - out_sfd__h639416; + CASE_guard30920_0b0_theResult___snd38919_BITS__ETC__q94 = + out_sfd__h639414; 2'b11: - CASE_guard30922_0b0_theResult___snd38921_BITS__ETC__q94 = - _theResult___sfd__h639413; + CASE_guard30920_0b0_theResult___snd38919_BITS__ETC__q94 = + _theResult___sfd__h639411; endcase end - always@(guard__h630922 or - _theResult___snd__h638921 or _theResult___sfd__h639413) + always@(guard__h630920 or + _theResult___snd__h638919 or _theResult___sfd__h639411) begin - case (guard__h630922) + case (guard__h630920) 2'b0: - CASE_guard30922_0b0_theResult___snd38921_BITS__ETC__q95 = - _theResult___snd__h638921[56:34]; + CASE_guard30920_0b0_theResult___snd38919_BITS__ETC__q95 = + _theResult___snd__h638919[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard30922_0b0_theResult___snd38921_BITS__ETC__q95 = - _theResult___sfd__h639413; + CASE_guard30920_0b0_theResult___snd38919_BITS__ETC__q95 = + _theResult___sfd__h639411; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard30922_0b0_theResult___snd38921_BITS__ETC__q94 or - CASE_guard30922_0b0_theResult___snd38921_BITS__ETC__q95 or + CASE_guard30920_0b0_theResult___snd38919_BITS__ETC__q94 or + CASE_guard30920_0b0_theResult___snd38919_BITS__ETC__q95 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10496 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10498 or - _theResult___snd__h638921) + _theResult___snd__h638919) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h639491 = - CASE_guard30922_0b0_theResult___snd38921_BITS__ETC__q94; + _theResult___fst_sfd__h639489 = + CASE_guard30920_0b0_theResult___snd38919_BITS__ETC__q94; 3'd1: - _theResult___fst_sfd__h639491 = - CASE_guard30922_0b0_theResult___snd38921_BITS__ETC__q95; + _theResult___fst_sfd__h639489 = + CASE_guard30920_0b0_theResult___snd38919_BITS__ETC__q95; 3'd2: - _theResult___fst_sfd__h639491 = + _theResult___fst_sfd__h639489 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10496; 3'd3: - _theResult___fst_sfd__h639491 = + _theResult___fst_sfd__h639489 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10498; - 3'd4: _theResult___fst_sfd__h639491 = _theResult___snd__h638921[56:34]; - default: _theResult___fst_sfd__h639491 = 23'd0; + 3'd4: _theResult___fst_sfd__h639489 = _theResult___snd__h638919[56:34]; + default: _theResult___fst_sfd__h639489 = 23'd0; endcase end - always@(guard__h622215 or - sfdin__h630308 or out_sfd__h630834 or _theResult___sfd__h630831) + always@(guard__h622213 or + sfdin__h630306 or out_sfd__h630832 or _theResult___sfd__h630829) begin - case (guard__h622215) + case (guard__h622213) 2'b0, 2'b01: - CASE_guard22215_0b0_sfdin30308_BITS_56_TO_34_0_ETC__q96 = - sfdin__h630308[56:34]; + CASE_guard22213_0b0_sfdin30306_BITS_56_TO_34_0_ETC__q96 = + sfdin__h630306[56:34]; 2'b10: - CASE_guard22215_0b0_sfdin30308_BITS_56_TO_34_0_ETC__q96 = - out_sfd__h630834; + CASE_guard22213_0b0_sfdin30306_BITS_56_TO_34_0_ETC__q96 = + out_sfd__h630832; 2'b11: - CASE_guard22215_0b0_sfdin30308_BITS_56_TO_34_0_ETC__q96 = - _theResult___sfd__h630831; + CASE_guard22213_0b0_sfdin30306_BITS_56_TO_34_0_ETC__q96 = + _theResult___sfd__h630829; endcase end - always@(guard__h622215 or sfdin__h630308 or _theResult___sfd__h630831) + always@(guard__h622213 or sfdin__h630306 or _theResult___sfd__h630829) begin - case (guard__h622215) + case (guard__h622213) 2'b0: - CASE_guard22215_0b0_sfdin30308_BITS_56_TO_34_0_ETC__q97 = - sfdin__h630308[56:34]; + CASE_guard22213_0b0_sfdin30306_BITS_56_TO_34_0_ETC__q97 = + sfdin__h630306[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard22215_0b0_sfdin30308_BITS_56_TO_34_0_ETC__q97 = - _theResult___sfd__h630831; + CASE_guard22213_0b0_sfdin30306_BITS_56_TO_34_0_ETC__q97 = + _theResult___sfd__h630829; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard22215_0b0_sfdin30308_BITS_56_TO_34_0_ETC__q96 or - CASE_guard22215_0b0_sfdin30308_BITS_56_TO_34_0_ETC__q97 or + CASE_guard22213_0b0_sfdin30306_BITS_56_TO_34_0_ETC__q96 or + CASE_guard22213_0b0_sfdin30306_BITS_56_TO_34_0_ETC__q97 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d10477 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d10479 or - sfdin__h630308) + sfdin__h630306) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h630909 = - CASE_guard22215_0b0_sfdin30308_BITS_56_TO_34_0_ETC__q96; + _theResult___fst_sfd__h630907 = + CASE_guard22213_0b0_sfdin30306_BITS_56_TO_34_0_ETC__q96; 3'd1: - _theResult___fst_sfd__h630909 = - CASE_guard22215_0b0_sfdin30308_BITS_56_TO_34_0_ETC__q97; + _theResult___fst_sfd__h630907 = + CASE_guard22213_0b0_sfdin30306_BITS_56_TO_34_0_ETC__q97; 3'd2: - _theResult___fst_sfd__h630909 = + _theResult___fst_sfd__h630907 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d10477; 3'd3: - _theResult___fst_sfd__h630909 = + _theResult___fst_sfd__h630907 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d10479; - 3'd4: _theResult___fst_sfd__h630909 = sfdin__h630308[56:34]; - default: _theResult___fst_sfd__h630909 = 23'd0; + 3'd4: _theResult___fst_sfd__h630907 = sfdin__h630306[56:34]; + default: _theResult___fst_sfd__h630907 = 23'd0; endcase end - always@(guard__h639852 or - sfdin__h648074 or out_sfd__h648600 or _theResult___sfd__h648597) + always@(guard__h639850 or + sfdin__h648072 or out_sfd__h648598 or _theResult___sfd__h648595) begin - case (guard__h639852) + case (guard__h639850) 2'b0, 2'b01: - CASE_guard39852_0b0_sfdin48074_BITS_56_TO_34_0_ETC__q98 = - sfdin__h648074[56:34]; + CASE_guard39850_0b0_sfdin48072_BITS_56_TO_34_0_ETC__q98 = + sfdin__h648072[56:34]; 2'b10: - CASE_guard39852_0b0_sfdin48074_BITS_56_TO_34_0_ETC__q98 = - out_sfd__h648600; + CASE_guard39850_0b0_sfdin48072_BITS_56_TO_34_0_ETC__q98 = + out_sfd__h648598; 2'b11: - CASE_guard39852_0b0_sfdin48074_BITS_56_TO_34_0_ETC__q98 = - _theResult___sfd__h648597; + CASE_guard39850_0b0_sfdin48072_BITS_56_TO_34_0_ETC__q98 = + _theResult___sfd__h648595; endcase end - always@(guard__h639852 or sfdin__h648074 or _theResult___sfd__h648597) + always@(guard__h639850 or sfdin__h648072 or _theResult___sfd__h648595) begin - case (guard__h639852) + case (guard__h639850) 2'b0: - CASE_guard39852_0b0_sfdin48074_BITS_56_TO_34_0_ETC__q99 = - sfdin__h648074[56:34]; + CASE_guard39850_0b0_sfdin48072_BITS_56_TO_34_0_ETC__q99 = + sfdin__h648072[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard39852_0b0_sfdin48074_BITS_56_TO_34_0_ETC__q99 = - _theResult___sfd__h648597; + CASE_guard39850_0b0_sfdin48072_BITS_56_TO_34_0_ETC__q99 = + _theResult___sfd__h648595; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard39852_0b0_sfdin48074_BITS_56_TO_34_0_ETC__q98 or - CASE_guard39852_0b0_sfdin48074_BITS_56_TO_34_0_ETC__q99 or + CASE_guard39850_0b0_sfdin48072_BITS_56_TO_34_0_ETC__q98 or + CASE_guard39850_0b0_sfdin48072_BITS_56_TO_34_0_ETC__q99 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10523 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10525 or - sfdin__h648074) + sfdin__h648072) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h648675 = - CASE_guard39852_0b0_sfdin48074_BITS_56_TO_34_0_ETC__q98; + _theResult___fst_sfd__h648673 = + CASE_guard39850_0b0_sfdin48072_BITS_56_TO_34_0_ETC__q98; 3'd1: - _theResult___fst_sfd__h648675 = - CASE_guard39852_0b0_sfdin48074_BITS_56_TO_34_0_ETC__q99; + _theResult___fst_sfd__h648673 = + CASE_guard39850_0b0_sfdin48072_BITS_56_TO_34_0_ETC__q99; 3'd2: - _theResult___fst_sfd__h648675 = + _theResult___fst_sfd__h648673 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10523; 3'd3: - _theResult___fst_sfd__h648675 = + _theResult___fst_sfd__h648673 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10525; - 3'd4: _theResult___fst_sfd__h648675 = sfdin__h648074[56:34]; - default: _theResult___fst_sfd__h648675 = 23'd0; + 3'd4: _theResult___fst_sfd__h648673 = sfdin__h648072[56:34]; + default: _theResult___fst_sfd__h648673 = 23'd0; endcase end - always@(guard__h648688 or - _theResult___snd__h656711 or - out_sfd__h657236 or _theResult___sfd__h657233) - begin - case (guard__h648688) - 2'b0, 2'b01: - CASE_guard48688_0b0_theResult___snd56711_BITS__ETC__q100 = - _theResult___snd__h656711[56:34]; - 2'b10: - CASE_guard48688_0b0_theResult___snd56711_BITS__ETC__q100 = - out_sfd__h657236; - 2'b11: - CASE_guard48688_0b0_theResult___snd56711_BITS__ETC__q100 = - _theResult___sfd__h657233; - endcase - end - always@(guard__h648688 or - _theResult___snd__h656711 or _theResult___sfd__h657233) - begin - case (guard__h648688) - 2'b0: - CASE_guard48688_0b0_theResult___snd56711_BITS__ETC__q101 = - _theResult___snd__h656711[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard48688_0b0_theResult___snd56711_BITS__ETC__q101 = - _theResult___sfd__h657233; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard48688_0b0_theResult___snd56711_BITS__ETC__q100 or - CASE_guard48688_0b0_theResult___snd56711_BITS__ETC__q101 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10542 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10544 or - _theResult___snd__h656711) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0: - _theResult___fst_sfd__h657311 = - CASE_guard48688_0b0_theResult___snd56711_BITS__ETC__q100; - 3'd1: - _theResult___fst_sfd__h657311 = - CASE_guard48688_0b0_theResult___snd56711_BITS__ETC__q101; - 3'd2: - _theResult___fst_sfd__h657311 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10542; - 3'd3: - _theResult___fst_sfd__h657311 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10544; - 3'd4: _theResult___fst_sfd__h657311 = _theResult___snd__h656711[56:34]; - default: _theResult___fst_sfd__h657311 = 23'd0; - endcase - end - always@(guard__h622215 or + always@(guard__h622213 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h622215) + case (guard__h622213) 2'b0, 2'b01, 2'b10: - CASE_guard22215_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q102 = + CASE_guard22213_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q100 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard22215_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q102 = - guard__h622215 == 2'b11 && + CASE_guard22213_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q100 = + guard__h622213 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard22215_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q102 or - guard__h622215) + CASE_guard22213_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q100 or + guard__h622213) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10630 = - CASE_guard22215_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q102; + CASE_guard22213_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q100; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10630 = - (guard__h622215 == 2'b0) ? + (guard__h622213 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h622215 == 2'b01 || guard__h622215 == 2'b10 || - guard__h622215 == 2'b11) && + (guard__h622213 == 2'b01 || guard__h622213 == 2'b10 || + guard__h622213 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10630 = @@ -40716,34 +40653,86 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h622215 or + always@(guard__h648686 or + _theResult___snd__h656709 or + out_sfd__h657234 or _theResult___sfd__h657231) + begin + case (guard__h648686) + 2'b0, 2'b01: + CASE_guard48686_0b0_theResult___snd56709_BITS__ETC__q101 = + _theResult___snd__h656709[56:34]; + 2'b10: + CASE_guard48686_0b0_theResult___snd56709_BITS__ETC__q101 = + out_sfd__h657234; + 2'b11: + CASE_guard48686_0b0_theResult___snd56709_BITS__ETC__q101 = + _theResult___sfd__h657231; + endcase + end + always@(guard__h648686 or + _theResult___snd__h656709 or _theResult___sfd__h657231) + begin + case (guard__h648686) + 2'b0: + CASE_guard48686_0b0_theResult___snd56709_BITS__ETC__q102 = + _theResult___snd__h656709[56:34]; + 2'b01, 2'b10, 2'b11: + CASE_guard48686_0b0_theResult___snd56709_BITS__ETC__q102 = + _theResult___sfd__h657231; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or + CASE_guard48686_0b0_theResult___snd56709_BITS__ETC__q101 or + CASE_guard48686_0b0_theResult___snd56709_BITS__ETC__q102 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10542 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10544 or + _theResult___snd__h656709) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) + 3'd0: + _theResult___fst_sfd__h657309 = + CASE_guard48686_0b0_theResult___snd56709_BITS__ETC__q101; + 3'd1: + _theResult___fst_sfd__h657309 = + CASE_guard48686_0b0_theResult___snd56709_BITS__ETC__q102; + 3'd2: + _theResult___fst_sfd__h657309 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10542; + 3'd3: + _theResult___fst_sfd__h657309 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d10544; + 3'd4: _theResult___fst_sfd__h657309 = _theResult___snd__h656709[56:34]; + default: _theResult___fst_sfd__h657309 = 23'd0; + endcase + end + always@(guard__h622213 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h622215) + case (guard__h622213) 2'b0, 2'b01, 2'b10: - CASE_guard22215_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q103 = + CASE_guard22213_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q103 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard22215_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q103 = - guard__h622215 != 2'b11 || + CASE_guard22213_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q103 = + guard__h622213 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard22215_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q103 or - guard__h622215) + CASE_guard22213_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q103 or + guard__h622213) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10574 = - CASE_guard22215_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q103; + CASE_guard22213_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q103; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10574 = - (guard__h622215 == 2'b0) ? + (guard__h622213 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h622215 != 2'b01 && guard__h622215 != 2'b10 && - guard__h622215 != 2'b11 || + guard__h622213 != 2'b01 && guard__h622213 != 2'b10 && + guard__h622213 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10574 = @@ -40754,34 +40743,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h630922 or + always@(guard__h630920 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h630922) + case (guard__h630920) 2'b0, 2'b01, 2'b10: - CASE_guard30922_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q104 = + CASE_guard30920_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q104 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard30922_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q104 = - guard__h630922 == 2'b11 && + CASE_guard30920_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q104 = + guard__h630920 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard30922_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q104 or - guard__h630922) + CASE_guard30920_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q104 or + guard__h630920) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10637 = - CASE_guard30922_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q104; + CASE_guard30920_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q104; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10637 = - (guard__h630922 == 2'b0) ? + (guard__h630920 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h630922 == 2'b01 || guard__h630922 == 2'b10 || - guard__h630922 == 2'b11) && + (guard__h630920 == 2'b01 || guard__h630920 == 2'b10 || + guard__h630920 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10637 = @@ -40792,34 +40781,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h630922 or + always@(guard__h630920 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h630922) + case (guard__h630920) 2'b0, 2'b01, 2'b10: - CASE_guard30922_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q105 = + CASE_guard30920_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q105 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard30922_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q105 = - guard__h630922 != 2'b11 || + CASE_guard30920_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q105 = + guard__h630920 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard30922_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q105 or - guard__h630922) + CASE_guard30920_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q105 or + guard__h630920) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10587 = - CASE_guard30922_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q105; + CASE_guard30920_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q105; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10587 = - (guard__h630922 == 2'b0) ? + (guard__h630920 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h630922 != 2'b01 && guard__h630922 != 2'b10 && - guard__h630922 != 2'b11 || + guard__h630920 != 2'b01 && guard__h630920 != 2'b10 && + guard__h630920 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10587 = @@ -40830,34 +40819,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h639852 or + always@(guard__h639850 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h639852) + case (guard__h639850) 2'b0, 2'b01, 2'b10: - CASE_guard39852_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q106 = + CASE_guard39850_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q106 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard39852_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q106 = - guard__h639852 == 2'b11 && + CASE_guard39850_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q106 = + guard__h639850 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard39852_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q106 or - guard__h639852) + CASE_guard39850_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q106 or + guard__h639850) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10647 = - CASE_guard39852_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q106; + CASE_guard39850_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q106; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10647 = - (guard__h639852 == 2'b0) ? + (guard__h639850 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h639852 == 2'b01 || guard__h639852 == 2'b10 || - guard__h639852 == 2'b11) && + (guard__h639850 == 2'b01 || guard__h639850 == 2'b10 || + guard__h639850 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10647 = @@ -40868,34 +40857,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h639852 or + always@(guard__h639850 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h639852) + case (guard__h639850) 2'b0, 2'b01, 2'b10: - CASE_guard39852_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q107 = + CASE_guard39850_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q107 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard39852_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q107 = - guard__h639852 != 2'b11 || + CASE_guard39850_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q107 = + guard__h639850 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard39852_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q107 or - guard__h639852) + CASE_guard39850_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q107 or + guard__h639850) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10604 = - CASE_guard39852_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q107; + CASE_guard39850_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q107; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10604 = - (guard__h639852 == 2'b0) ? + (guard__h639850 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h639852 != 2'b01 && guard__h639852 != 2'b10 && - guard__h639852 != 2'b11 || + guard__h639850 != 2'b01 && guard__h639850 != 2'b10 && + guard__h639850 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10604 = @@ -40906,34 +40895,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h648688 or + always@(guard__h648686 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h648688) + case (guard__h648686) 2'b0, 2'b01, 2'b10: - CASE_guard48688_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q108 = + CASE_guard48686_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q108 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard48688_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q108 = - guard__h648688 == 2'b11 && + CASE_guard48686_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q108 = + guard__h648686 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard48688_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q108 or - guard__h648688) + CASE_guard48686_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q108 or + guard__h648686) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10654 = - CASE_guard48688_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q108; + CASE_guard48686_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q108; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10654 = - (guard__h648688 == 2'b0) ? + (guard__h648686 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h648688 == 2'b01 || guard__h648688 == 2'b10 || - guard__h648688 == 2'b11) && + (guard__h648686 == 2'b01 || guard__h648686 == 2'b10 || + guard__h648686 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10654 = @@ -40944,34 +40933,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h648688 or + always@(guard__h648686 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h648688) + case (guard__h648686) 2'b0, 2'b01, 2'b10: - CASE_guard48688_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q109 = + CASE_guard48686_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q109 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard48688_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q109 = - guard__h648688 != 2'b11 || + CASE_guard48686_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q109 = + guard__h648686 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard48688_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q109 or - guard__h648688) + CASE_guard48686_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q109 or + guard__h648686) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10617 = - CASE_guard48688_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q109; + CASE_guard48686_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q109; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10617 = - (guard__h648688 == 2'b0) ? + (guard__h648686 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h648688 != 2'b01 && guard__h648688 != 2'b10 && - guard__h648688 != 2'b11 || + guard__h648686 != 2'b01 && guard__h648686 != 2'b10 && + guard__h648686 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d10617 = @@ -41008,446 +40997,446 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h676669 or - _theResult___fst_exp__h684717 or - out_exp__h685162 or _theResult___exp__h685159) + always@(guard__h676667 or + _theResult___fst_exp__h684715 or + out_exp__h685160 or _theResult___exp__h685157) begin - case (guard__h676669) + case (guard__h676667) 2'b0, 2'b01: - CASE_guard76669_0b0_theResult___fst_exp84717_0_ETC__q114 = - _theResult___fst_exp__h684717; + CASE_guard76667_0b0_theResult___fst_exp84715_0_ETC__q114 = + _theResult___fst_exp__h684715; 2'b10: - CASE_guard76669_0b0_theResult___fst_exp84717_0_ETC__q114 = - out_exp__h685162; + CASE_guard76667_0b0_theResult___fst_exp84715_0_ETC__q114 = + out_exp__h685160; 2'b11: - CASE_guard76669_0b0_theResult___fst_exp84717_0_ETC__q114 = - _theResult___exp__h685159; + CASE_guard76667_0b0_theResult___fst_exp84715_0_ETC__q114 = + _theResult___exp__h685157; endcase end - always@(guard__h676669 or - _theResult___fst_exp__h684717 or _theResult___exp__h685159) + always@(guard__h676667 or + _theResult___fst_exp__h684715 or _theResult___exp__h685157) begin - case (guard__h676669) + case (guard__h676667) 2'b0: - CASE_guard76669_0b0_theResult___fst_exp84717_0_ETC__q115 = - _theResult___fst_exp__h684717; + CASE_guard76667_0b0_theResult___fst_exp84715_0_ETC__q115 = + _theResult___fst_exp__h684715; 2'b01, 2'b10, 2'b11: - CASE_guard76669_0b0_theResult___fst_exp84717_0_ETC__q115 = - _theResult___exp__h685159; + CASE_guard76667_0b0_theResult___fst_exp84715_0_ETC__q115 = + _theResult___exp__h685157; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard76669_0b0_theResult___fst_exp84717_0_ETC__q114 or - CASE_guard76669_0b0_theResult___fst_exp84717_0_ETC__q115 or + CASE_guard76667_0b0_theResult___fst_exp84715_0_ETC__q114 or + CASE_guard76667_0b0_theResult___fst_exp84715_0_ETC__q115 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11449 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11451 or - _theResult___fst_exp__h684717) + _theResult___fst_exp__h684715) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h685237 = - CASE_guard76669_0b0_theResult___fst_exp84717_0_ETC__q114; + _theResult___fst_exp__h685235 = + CASE_guard76667_0b0_theResult___fst_exp84715_0_ETC__q114; 3'd1: - _theResult___fst_exp__h685237 = - CASE_guard76669_0b0_theResult___fst_exp84717_0_ETC__q115; + _theResult___fst_exp__h685235 = + CASE_guard76667_0b0_theResult___fst_exp84715_0_ETC__q115; 3'd2: - _theResult___fst_exp__h685237 = + _theResult___fst_exp__h685235 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11449; 3'd3: - _theResult___fst_exp__h685237 = + _theResult___fst_exp__h685235 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11451; - 3'd4: _theResult___fst_exp__h685237 = _theResult___fst_exp__h684717; - default: _theResult___fst_exp__h685237 = 8'd0; + 3'd4: _theResult___fst_exp__h685235 = _theResult___fst_exp__h684715; + default: _theResult___fst_exp__h685235 = 8'd0; endcase end - always@(guard__h667962 or - _theResult___fst_exp__h676061 or - out_exp__h676580 or _theResult___exp__h676577) + always@(guard__h667960 or + _theResult___fst_exp__h676059 or + out_exp__h676578 or _theResult___exp__h676575) begin - case (guard__h667962) + case (guard__h667960) 2'b0, 2'b01: - CASE_guard67962_0b0_theResult___fst_exp76061_0_ETC__q116 = - _theResult___fst_exp__h676061; + CASE_guard67960_0b0_theResult___fst_exp76059_0_ETC__q116 = + _theResult___fst_exp__h676059; 2'b10: - CASE_guard67962_0b0_theResult___fst_exp76061_0_ETC__q116 = - out_exp__h676580; + CASE_guard67960_0b0_theResult___fst_exp76059_0_ETC__q116 = + out_exp__h676578; 2'b11: - CASE_guard67962_0b0_theResult___fst_exp76061_0_ETC__q116 = - _theResult___exp__h676577; + CASE_guard67960_0b0_theResult___fst_exp76059_0_ETC__q116 = + _theResult___exp__h676575; endcase end - always@(guard__h667962 or - _theResult___fst_exp__h676061 or _theResult___exp__h676577) + always@(guard__h667960 or + _theResult___fst_exp__h676059 or _theResult___exp__h676575) begin - case (guard__h667962) + case (guard__h667960) 2'b0: - CASE_guard67962_0b0_theResult___fst_exp76061_0_ETC__q117 = - _theResult___fst_exp__h676061; + CASE_guard67960_0b0_theResult___fst_exp76059_0_ETC__q117 = + _theResult___fst_exp__h676059; 2'b01, 2'b10, 2'b11: - CASE_guard67962_0b0_theResult___fst_exp76061_0_ETC__q117 = - _theResult___exp__h676577; + CASE_guard67960_0b0_theResult___fst_exp76059_0_ETC__q117 = + _theResult___exp__h676575; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard67962_0b0_theResult___fst_exp76061_0_ETC__q116 or - CASE_guard67962_0b0_theResult___fst_exp76061_0_ETC__q117 or + CASE_guard67960_0b0_theResult___fst_exp76059_0_ETC__q116 or + CASE_guard67960_0b0_theResult___fst_exp76059_0_ETC__q117 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11227 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11230 or - _theResult___fst_exp__h676061) + _theResult___fst_exp__h676059) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h676655 = - CASE_guard67962_0b0_theResult___fst_exp76061_0_ETC__q116; + _theResult___fst_exp__h676653 = + CASE_guard67960_0b0_theResult___fst_exp76059_0_ETC__q116; 3'd1: - _theResult___fst_exp__h676655 = - CASE_guard67962_0b0_theResult___fst_exp76061_0_ETC__q117; + _theResult___fst_exp__h676653 = + CASE_guard67960_0b0_theResult___fst_exp76059_0_ETC__q117; 3'd2: - _theResult___fst_exp__h676655 = + _theResult___fst_exp__h676653 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11227; 3'd3: - _theResult___fst_exp__h676655 = + _theResult___fst_exp__h676653 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11230; - 3'd4: _theResult___fst_exp__h676655 = _theResult___fst_exp__h676061; - default: _theResult___fst_exp__h676655 = 8'd0; + 3'd4: _theResult___fst_exp__h676653 = _theResult___fst_exp__h676059; + default: _theResult___fst_exp__h676653 = 8'd0; endcase end - always@(guard__h685599 or - _theResult___fst_exp__h693827 or - out_exp__h694346 or _theResult___exp__h694343) + always@(guard__h685597 or + _theResult___fst_exp__h693825 or + out_exp__h694344 or _theResult___exp__h694341) begin - case (guard__h685599) + case (guard__h685597) 2'b0, 2'b01: - CASE_guard85599_0b0_theResult___fst_exp93827_0_ETC__q122 = - _theResult___fst_exp__h693827; + CASE_guard85597_0b0_theResult___fst_exp93825_0_ETC__q122 = + _theResult___fst_exp__h693825; 2'b10: - CASE_guard85599_0b0_theResult___fst_exp93827_0_ETC__q122 = - out_exp__h694346; + CASE_guard85597_0b0_theResult___fst_exp93825_0_ETC__q122 = + out_exp__h694344; 2'b11: - CASE_guard85599_0b0_theResult___fst_exp93827_0_ETC__q122 = - _theResult___exp__h694343; + CASE_guard85597_0b0_theResult___fst_exp93825_0_ETC__q122 = + _theResult___exp__h694341; endcase end - always@(guard__h685599 or - _theResult___fst_exp__h693827 or _theResult___exp__h694343) + always@(guard__h685597 or + _theResult___fst_exp__h693825 or _theResult___exp__h694341) begin - case (guard__h685599) + case (guard__h685597) 2'b0: - CASE_guard85599_0b0_theResult___fst_exp93827_0_ETC__q123 = - _theResult___fst_exp__h693827; + CASE_guard85597_0b0_theResult___fst_exp93825_0_ETC__q123 = + _theResult___fst_exp__h693825; 2'b01, 2'b10, 2'b11: - CASE_guard85599_0b0_theResult___fst_exp93827_0_ETC__q123 = - _theResult___exp__h694343; + CASE_guard85597_0b0_theResult___fst_exp93825_0_ETC__q123 = + _theResult___exp__h694341; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard85599_0b0_theResult___fst_exp93827_0_ETC__q122 or - CASE_guard85599_0b0_theResult___fst_exp93827_0_ETC__q123 or + CASE_guard85597_0b0_theResult___fst_exp93825_0_ETC__q122 or + CASE_guard85597_0b0_theResult___fst_exp93825_0_ETC__q123 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11774 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11776 or - _theResult___fst_exp__h693827) + _theResult___fst_exp__h693825) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h694421 = - CASE_guard85599_0b0_theResult___fst_exp93827_0_ETC__q122; + _theResult___fst_exp__h694419 = + CASE_guard85597_0b0_theResult___fst_exp93825_0_ETC__q122; 3'd1: - _theResult___fst_exp__h694421 = - CASE_guard85599_0b0_theResult___fst_exp93827_0_ETC__q123; + _theResult___fst_exp__h694419 = + CASE_guard85597_0b0_theResult___fst_exp93825_0_ETC__q123; 3'd2: - _theResult___fst_exp__h694421 = + _theResult___fst_exp__h694419 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11774; 3'd3: - _theResult___fst_exp__h694421 = + _theResult___fst_exp__h694419 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11776; - 3'd4: _theResult___fst_exp__h694421 = _theResult___fst_exp__h693827; - default: _theResult___fst_exp__h694421 = 8'd0; + 3'd4: _theResult___fst_exp__h694419 = _theResult___fst_exp__h693825; + default: _theResult___fst_exp__h694419 = 8'd0; endcase end - always@(guard__h694435 or - _theResult___fst_exp__h702512 or - out_exp__h702982 or _theResult___exp__h702979) + always@(guard__h694433 or + _theResult___fst_exp__h702510 or + out_exp__h702980 or _theResult___exp__h702977) begin - case (guard__h694435) + case (guard__h694433) 2'b0, 2'b01: - CASE_guard94435_0b0_theResult___fst_exp02512_0_ETC__q127 = - _theResult___fst_exp__h702512; + CASE_guard94433_0b0_theResult___fst_exp02510_0_ETC__q127 = + _theResult___fst_exp__h702510; 2'b10: - CASE_guard94435_0b0_theResult___fst_exp02512_0_ETC__q127 = - out_exp__h702982; + CASE_guard94433_0b0_theResult___fst_exp02510_0_ETC__q127 = + out_exp__h702980; 2'b11: - CASE_guard94435_0b0_theResult___fst_exp02512_0_ETC__q127 = - _theResult___exp__h702979; + CASE_guard94433_0b0_theResult___fst_exp02510_0_ETC__q127 = + _theResult___exp__h702977; endcase end - always@(guard__h694435 or - _theResult___fst_exp__h702512 or _theResult___exp__h702979) + always@(guard__h694433 or + _theResult___fst_exp__h702510 or _theResult___exp__h702977) begin - case (guard__h694435) + case (guard__h694433) 2'b0: - CASE_guard94435_0b0_theResult___fst_exp02512_0_ETC__q128 = - _theResult___fst_exp__h702512; + CASE_guard94433_0b0_theResult___fst_exp02510_0_ETC__q128 = + _theResult___fst_exp__h702510; 2'b01, 2'b10, 2'b11: - CASE_guard94435_0b0_theResult___fst_exp02512_0_ETC__q128 = - _theResult___exp__h702979; + CASE_guard94433_0b0_theResult___fst_exp02510_0_ETC__q128 = + _theResult___exp__h702977; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard94435_0b0_theResult___fst_exp02512_0_ETC__q127 or - CASE_guard94435_0b0_theResult___fst_exp02512_0_ETC__q128 or + CASE_guard94433_0b0_theResult___fst_exp02510_0_ETC__q127 or + CASE_guard94433_0b0_theResult___fst_exp02510_0_ETC__q128 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11843 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11845 or - _theResult___fst_exp__h702512) + _theResult___fst_exp__h702510) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h703057 = - CASE_guard94435_0b0_theResult___fst_exp02512_0_ETC__q127; + _theResult___fst_exp__h703055 = + CASE_guard94433_0b0_theResult___fst_exp02510_0_ETC__q127; 3'd1: - _theResult___fst_exp__h703057 = - CASE_guard94435_0b0_theResult___fst_exp02512_0_ETC__q128; + _theResult___fst_exp__h703055 = + CASE_guard94433_0b0_theResult___fst_exp02510_0_ETC__q128; 3'd2: - _theResult___fst_exp__h703057 = + _theResult___fst_exp__h703055 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11843; 3'd3: - _theResult___fst_exp__h703057 = + _theResult___fst_exp__h703055 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11845; - 3'd4: _theResult___fst_exp__h703057 = _theResult___fst_exp__h702512; - default: _theResult___fst_exp__h703057 = 8'd0; + 3'd4: _theResult___fst_exp__h703055 = _theResult___fst_exp__h702510; + default: _theResult___fst_exp__h703055 = 8'd0; endcase end - always@(guard__h667962 or - sfdin__h676055 or out_sfd__h676581 or _theResult___sfd__h676578) + always@(guard__h676667 or + _theResult___snd__h684666 or + out_sfd__h685161 or _theResult___sfd__h685158) begin - case (guard__h667962) + case (guard__h676667) 2'b0, 2'b01: - CASE_guard67962_0b0_sfdin76055_BITS_56_TO_34_0_ETC__q129 = - sfdin__h676055[56:34]; + CASE_guard76667_0b0_theResult___snd84666_BITS__ETC__q129 = + _theResult___snd__h684666[56:34]; 2'b10: - CASE_guard67962_0b0_sfdin76055_BITS_56_TO_34_0_ETC__q129 = - out_sfd__h676581; + CASE_guard76667_0b0_theResult___snd84666_BITS__ETC__q129 = + out_sfd__h685161; 2'b11: - CASE_guard67962_0b0_sfdin76055_BITS_56_TO_34_0_ETC__q129 = - _theResult___sfd__h676578; + CASE_guard76667_0b0_theResult___snd84666_BITS__ETC__q129 = + _theResult___sfd__h685158; endcase end - always@(guard__h667962 or sfdin__h676055 or _theResult___sfd__h676578) + always@(guard__h676667 or + _theResult___snd__h684666 or _theResult___sfd__h685158) begin - case (guard__h667962) + case (guard__h676667) 2'b0: - CASE_guard67962_0b0_sfdin76055_BITS_56_TO_34_0_ETC__q130 = - sfdin__h676055[56:34]; + CASE_guard76667_0b0_theResult___snd84666_BITS__ETC__q130 = + _theResult___snd__h684666[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard67962_0b0_sfdin76055_BITS_56_TO_34_0_ETC__q130 = - _theResult___sfd__h676578; + CASE_guard76667_0b0_theResult___snd84666_BITS__ETC__q130 = + _theResult___sfd__h685158; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard67962_0b0_sfdin76055_BITS_56_TO_34_0_ETC__q129 or - CASE_guard67962_0b0_sfdin76055_BITS_56_TO_34_0_ETC__q130 or - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11874 or - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11876 or - sfdin__h676055) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0: - _theResult___fst_sfd__h676656 = - CASE_guard67962_0b0_sfdin76055_BITS_56_TO_34_0_ETC__q129; - 3'd1: - _theResult___fst_sfd__h676656 = - CASE_guard67962_0b0_sfdin76055_BITS_56_TO_34_0_ETC__q130; - 3'd2: - _theResult___fst_sfd__h676656 = - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11874; - 3'd3: - _theResult___fst_sfd__h676656 = - IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11876; - 3'd4: _theResult___fst_sfd__h676656 = sfdin__h676055[56:34]; - default: _theResult___fst_sfd__h676656 = 23'd0; - endcase - end - always@(guard__h676669 or - _theResult___snd__h684668 or - out_sfd__h685163 or _theResult___sfd__h685160) - begin - case (guard__h676669) - 2'b0, 2'b01: - CASE_guard76669_0b0_theResult___snd84668_BITS__ETC__q131 = - _theResult___snd__h684668[56:34]; - 2'b10: - CASE_guard76669_0b0_theResult___snd84668_BITS__ETC__q131 = - out_sfd__h685163; - 2'b11: - CASE_guard76669_0b0_theResult___snd84668_BITS__ETC__q131 = - _theResult___sfd__h685160; - endcase - end - always@(guard__h676669 or - _theResult___snd__h684668 or _theResult___sfd__h685160) - begin - case (guard__h676669) - 2'b0: - CASE_guard76669_0b0_theResult___snd84668_BITS__ETC__q132 = - _theResult___snd__h684668[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard76669_0b0_theResult___snd84668_BITS__ETC__q132 = - _theResult___sfd__h685160; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard76669_0b0_theResult___snd84668_BITS__ETC__q131 or - CASE_guard76669_0b0_theResult___snd84668_BITS__ETC__q132 or + CASE_guard76667_0b0_theResult___snd84666_BITS__ETC__q129 or + CASE_guard76667_0b0_theResult___snd84666_BITS__ETC__q130 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11893 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11895 or - _theResult___snd__h684668) + _theResult___snd__h684666) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h685238 = - CASE_guard76669_0b0_theResult___snd84668_BITS__ETC__q131; + _theResult___fst_sfd__h685236 = + CASE_guard76667_0b0_theResult___snd84666_BITS__ETC__q129; 3'd1: - _theResult___fst_sfd__h685238 = - CASE_guard76669_0b0_theResult___snd84668_BITS__ETC__q132; + _theResult___fst_sfd__h685236 = + CASE_guard76667_0b0_theResult___snd84666_BITS__ETC__q130; 3'd2: - _theResult___fst_sfd__h685238 = + _theResult___fst_sfd__h685236 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11893; 3'd3: - _theResult___fst_sfd__h685238 = + _theResult___fst_sfd__h685236 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11895; - 3'd4: _theResult___fst_sfd__h685238 = _theResult___snd__h684668[56:34]; - default: _theResult___fst_sfd__h685238 = 23'd0; + 3'd4: _theResult___fst_sfd__h685236 = _theResult___snd__h684666[56:34]; + default: _theResult___fst_sfd__h685236 = 23'd0; endcase end - always@(guard__h685599 or - sfdin__h693821 or out_sfd__h694347 or _theResult___sfd__h694344) + always@(guard__h667960 or + sfdin__h676053 or out_sfd__h676579 or _theResult___sfd__h676576) begin - case (guard__h685599) + case (guard__h667960) 2'b0, 2'b01: - CASE_guard85599_0b0_sfdin93821_BITS_56_TO_34_0_ETC__q133 = - sfdin__h693821[56:34]; + CASE_guard67960_0b0_sfdin76053_BITS_56_TO_34_0_ETC__q131 = + sfdin__h676053[56:34]; 2'b10: - CASE_guard85599_0b0_sfdin93821_BITS_56_TO_34_0_ETC__q133 = - out_sfd__h694347; + CASE_guard67960_0b0_sfdin76053_BITS_56_TO_34_0_ETC__q131 = + out_sfd__h676579; 2'b11: - CASE_guard85599_0b0_sfdin93821_BITS_56_TO_34_0_ETC__q133 = - _theResult___sfd__h694344; + CASE_guard67960_0b0_sfdin76053_BITS_56_TO_34_0_ETC__q131 = + _theResult___sfd__h676576; endcase end - always@(guard__h685599 or sfdin__h693821 or _theResult___sfd__h694344) + always@(guard__h667960 or sfdin__h676053 or _theResult___sfd__h676576) begin - case (guard__h685599) + case (guard__h667960) 2'b0: - CASE_guard85599_0b0_sfdin93821_BITS_56_TO_34_0_ETC__q134 = - sfdin__h693821[56:34]; + CASE_guard67960_0b0_sfdin76053_BITS_56_TO_34_0_ETC__q132 = + sfdin__h676053[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard85599_0b0_sfdin93821_BITS_56_TO_34_0_ETC__q134 = - _theResult___sfd__h694344; + CASE_guard67960_0b0_sfdin76053_BITS_56_TO_34_0_ETC__q132 = + _theResult___sfd__h676576; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard85599_0b0_sfdin93821_BITS_56_TO_34_0_ETC__q133 or - CASE_guard85599_0b0_sfdin93821_BITS_56_TO_34_0_ETC__q134 or + CASE_guard67960_0b0_sfdin76053_BITS_56_TO_34_0_ETC__q131 or + CASE_guard67960_0b0_sfdin76053_BITS_56_TO_34_0_ETC__q132 or + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11874 or + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11876 or + sfdin__h676053) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) + 3'd0: + _theResult___fst_sfd__h676654 = + CASE_guard67960_0b0_sfdin76053_BITS_56_TO_34_0_ETC__q131; + 3'd1: + _theResult___fst_sfd__h676654 = + CASE_guard67960_0b0_sfdin76053_BITS_56_TO_34_0_ETC__q132; + 3'd2: + _theResult___fst_sfd__h676654 = + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11874; + 3'd3: + _theResult___fst_sfd__h676654 = + IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d11876; + 3'd4: _theResult___fst_sfd__h676654 = sfdin__h676053[56:34]; + default: _theResult___fst_sfd__h676654 = 23'd0; + endcase + end + always@(guard__h685597 or + sfdin__h693819 or out_sfd__h694345 or _theResult___sfd__h694342) + begin + case (guard__h685597) + 2'b0, 2'b01: + CASE_guard85597_0b0_sfdin93819_BITS_56_TO_34_0_ETC__q133 = + sfdin__h693819[56:34]; + 2'b10: + CASE_guard85597_0b0_sfdin93819_BITS_56_TO_34_0_ETC__q133 = + out_sfd__h694345; + 2'b11: + CASE_guard85597_0b0_sfdin93819_BITS_56_TO_34_0_ETC__q133 = + _theResult___sfd__h694342; + endcase + end + always@(guard__h685597 or sfdin__h693819 or _theResult___sfd__h694342) + begin + case (guard__h685597) + 2'b0: + CASE_guard85597_0b0_sfdin93819_BITS_56_TO_34_0_ETC__q134 = + sfdin__h693819[56:34]; + 2'b01, 2'b10, 2'b11: + CASE_guard85597_0b0_sfdin93819_BITS_56_TO_34_0_ETC__q134 = + _theResult___sfd__h694342; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or + CASE_guard85597_0b0_sfdin93819_BITS_56_TO_34_0_ETC__q133 or + CASE_guard85597_0b0_sfdin93819_BITS_56_TO_34_0_ETC__q134 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11920 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11922 or - sfdin__h693821) + sfdin__h693819) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h694422 = - CASE_guard85599_0b0_sfdin93821_BITS_56_TO_34_0_ETC__q133; + _theResult___fst_sfd__h694420 = + CASE_guard85597_0b0_sfdin93819_BITS_56_TO_34_0_ETC__q133; 3'd1: - _theResult___fst_sfd__h694422 = - CASE_guard85599_0b0_sfdin93821_BITS_56_TO_34_0_ETC__q134; + _theResult___fst_sfd__h694420 = + CASE_guard85597_0b0_sfdin93819_BITS_56_TO_34_0_ETC__q134; 3'd2: - _theResult___fst_sfd__h694422 = + _theResult___fst_sfd__h694420 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11920; 3'd3: - _theResult___fst_sfd__h694422 = + _theResult___fst_sfd__h694420 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d11922; - 3'd4: _theResult___fst_sfd__h694422 = sfdin__h693821[56:34]; - default: _theResult___fst_sfd__h694422 = 23'd0; + 3'd4: _theResult___fst_sfd__h694420 = sfdin__h693819[56:34]; + default: _theResult___fst_sfd__h694420 = 23'd0; endcase end - always@(guard__h694435 or - _theResult___snd__h702458 or - out_sfd__h702983 or _theResult___sfd__h702980) + always@(guard__h694433 or + _theResult___snd__h702456 or + out_sfd__h702981 or _theResult___sfd__h702978) begin - case (guard__h694435) + case (guard__h694433) 2'b0, 2'b01: - CASE_guard94435_0b0_theResult___snd02458_BITS__ETC__q135 = - _theResult___snd__h702458[56:34]; + CASE_guard94433_0b0_theResult___snd02456_BITS__ETC__q135 = + _theResult___snd__h702456[56:34]; 2'b10: - CASE_guard94435_0b0_theResult___snd02458_BITS__ETC__q135 = - out_sfd__h702983; + CASE_guard94433_0b0_theResult___snd02456_BITS__ETC__q135 = + out_sfd__h702981; 2'b11: - CASE_guard94435_0b0_theResult___snd02458_BITS__ETC__q135 = - _theResult___sfd__h702980; + CASE_guard94433_0b0_theResult___snd02456_BITS__ETC__q135 = + _theResult___sfd__h702978; endcase end - always@(guard__h694435 or - _theResult___snd__h702458 or _theResult___sfd__h702980) + always@(guard__h694433 or + _theResult___snd__h702456 or _theResult___sfd__h702978) begin - case (guard__h694435) + case (guard__h694433) 2'b0: - CASE_guard94435_0b0_theResult___snd02458_BITS__ETC__q136 = - _theResult___snd__h702458[56:34]; + CASE_guard94433_0b0_theResult___snd02456_BITS__ETC__q136 = + _theResult___snd__h702456[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard94435_0b0_theResult___snd02458_BITS__ETC__q136 = - _theResult___sfd__h702980; + CASE_guard94433_0b0_theResult___snd02456_BITS__ETC__q136 = + _theResult___sfd__h702978; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard94435_0b0_theResult___snd02458_BITS__ETC__q135 or - CASE_guard94435_0b0_theResult___snd02458_BITS__ETC__q136 or + CASE_guard94433_0b0_theResult___snd02456_BITS__ETC__q135 or + CASE_guard94433_0b0_theResult___snd02456_BITS__ETC__q136 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11939 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11941 or - _theResult___snd__h702458) + _theResult___snd__h702456) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h703058 = - CASE_guard94435_0b0_theResult___snd02458_BITS__ETC__q135; + _theResult___fst_sfd__h703056 = + CASE_guard94433_0b0_theResult___snd02456_BITS__ETC__q135; 3'd1: - _theResult___fst_sfd__h703058 = - CASE_guard94435_0b0_theResult___snd02458_BITS__ETC__q136; + _theResult___fst_sfd__h703056 = + CASE_guard94433_0b0_theResult___snd02456_BITS__ETC__q136; 3'd2: - _theResult___fst_sfd__h703058 = + _theResult___fst_sfd__h703056 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11939; 3'd3: - _theResult___fst_sfd__h703058 = + _theResult___fst_sfd__h703056 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d11941; - 3'd4: _theResult___fst_sfd__h703058 = _theResult___snd__h702458[56:34]; - default: _theResult___fst_sfd__h703058 = 23'd0; + 3'd4: _theResult___fst_sfd__h703056 = _theResult___snd__h702456[56:34]; + default: _theResult___fst_sfd__h703056 = 23'd0; endcase end - always@(guard__h667962 or + always@(guard__h667960 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h667962) + case (guard__h667960) 2'b0, 2'b01, 2'b10: - CASE_guard67962_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q137 = + CASE_guard67960_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q137 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard67962_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q137 = - guard__h667962 == 2'b11 && + CASE_guard67960_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q137 = + guard__h667960 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard67962_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q137 or - guard__h667962) + CASE_guard67960_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q137 or + guard__h667960) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12027 = - CASE_guard67962_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q137; + CASE_guard67960_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q137; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12027 = - (guard__h667962 == 2'b0) ? + (guard__h667960 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h667962 == 2'b01 || guard__h667962 == 2'b10 || - guard__h667962 == 2'b11) && + (guard__h667960 == 2'b01 || guard__h667960 == 2'b10 || + guard__h667960 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12027 = @@ -41458,72 +41447,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h676669 or + always@(guard__h667960 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h676669) + case (guard__h667960) 2'b0, 2'b01, 2'b10: - CASE_guard76669_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q138 = - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - 2'd3: - CASE_guard76669_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q138 = - guard__h676669 == 2'b11 && - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard76669_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q138 or - guard__h676669) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12034 = - CASE_guard76669_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q138; - 3'd1: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12034 = - (guard__h676669 == 2'b0) ? - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h676669 == 2'b01 || guard__h676669 == 2'b10 || - guard__h676669 == 2'b11) && - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12034 = - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12034 = - coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] == - 3'd4 && - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - endcase - end - always@(guard__h667962 or - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) - begin - case (guard__h667962) - 2'b0, 2'b01, 2'b10: - CASE_guard67962_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q139 = + CASE_guard67960_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q138 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard67962_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q139 = - guard__h667962 != 2'b11 || + CASE_guard67960_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q138 = + guard__h667960 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard67962_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q139 or - guard__h667962) + CASE_guard67960_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q138 or + guard__h667960) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11971 = - CASE_guard67962_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q139; + CASE_guard67960_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q138; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11971 = - (guard__h667962 == 2'b0) ? + (guard__h667960 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h667962 != 2'b01 && guard__h667962 != 2'b10 && - guard__h667962 != 2'b11 || + guard__h667960 != 2'b01 && guard__h667960 != 2'b10 && + guard__h667960 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11971 = @@ -41534,34 +41485,72 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h676669 or + always@(guard__h676667 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h676669) + case (guard__h676667) 2'b0, 2'b01, 2'b10: - CASE_guard76669_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q140 = + CASE_guard76667_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q139 = + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + 2'd3: + CASE_guard76667_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q139 = + guard__h676667 == 2'b11 && + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or + CASE_guard76667_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q139 or + guard__h676667) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) + 3'd0: + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12034 = + CASE_guard76667_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q139; + 3'd1: + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12034 = + (guard__h676667 == 2'b0) ? + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : + (guard__h676667 == 2'b01 || guard__h676667 == 2'b10 || + guard__h676667 == 2'b11) && + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + 3'd2, 3'd3: + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12034 = + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12034 = + coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] == + 3'd4 && + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + endcase + end + always@(guard__h676667 or + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) + begin + case (guard__h676667) + 2'b0, 2'b01, 2'b10: + CASE_guard76667_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q140 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard76669_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q140 = - guard__h676669 != 2'b11 || + CASE_guard76667_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q140 = + guard__h676667 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard76669_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q140 or - guard__h676669) + CASE_guard76667_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q140 or + guard__h676667) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11984 = - CASE_guard76669_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q140; + CASE_guard76667_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q140; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11984 = - (guard__h676669 == 2'b0) ? + (guard__h676667 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h676669 != 2'b01 && guard__h676669 != 2'b10 && - guard__h676669 != 2'b11 || + guard__h676667 != 2'b01 && guard__h676667 != 2'b10 && + guard__h676667 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d11984 = @@ -41572,34 +41561,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h685599 or + always@(guard__h685597 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h685599) + case (guard__h685597) 2'b0, 2'b01, 2'b10: - CASE_guard85599_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q141 = + CASE_guard85597_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q141 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard85599_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q141 = - guard__h685599 == 2'b11 && + CASE_guard85597_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q141 = + guard__h685597 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard85599_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q141 or - guard__h685599) + CASE_guard85597_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q141 or + guard__h685597) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12044 = - CASE_guard85599_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q141; + CASE_guard85597_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q141; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12044 = - (guard__h685599 == 2'b0) ? + (guard__h685597 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h685599 == 2'b01 || guard__h685599 == 2'b10 || - guard__h685599 == 2'b11) && + (guard__h685597 == 2'b01 || guard__h685597 == 2'b10 || + guard__h685597 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12044 = @@ -41610,34 +41599,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h685599 or + always@(guard__h685597 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h685599) + case (guard__h685597) 2'b0, 2'b01, 2'b10: - CASE_guard85599_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q142 = + CASE_guard85597_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q142 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard85599_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q142 = - guard__h685599 != 2'b11 || + CASE_guard85597_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q142 = + guard__h685597 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard85599_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q142 or - guard__h685599) + CASE_guard85597_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q142 or + guard__h685597) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12001 = - CASE_guard85599_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q142; + CASE_guard85597_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q142; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12001 = - (guard__h685599 == 2'b0) ? + (guard__h685597 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h685599 != 2'b01 && guard__h685599 != 2'b10 && - guard__h685599 != 2'b11 || + guard__h685597 != 2'b01 && guard__h685597 != 2'b10 && + guard__h685597 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12001 = @@ -41648,34 +41637,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h694435 or + always@(guard__h694433 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h694435) + case (guard__h694433) 2'b0, 2'b01, 2'b10: - CASE_guard94435_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q143 = + CASE_guard94433_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q143 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard94435_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q143 = - guard__h694435 == 2'b11 && + CASE_guard94433_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q143 = + guard__h694433 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard94435_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q143 or - guard__h694435) + CASE_guard94433_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q143 or + guard__h694433) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12051 = - CASE_guard94435_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q143; + CASE_guard94433_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q143; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12051 = - (guard__h694435 == 2'b0) ? + (guard__h694433 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h694435 == 2'b01 || guard__h694435 == 2'b10 || - guard__h694435 == 2'b11) && + (guard__h694433 == 2'b01 || guard__h694433 == 2'b10 || + guard__h694433 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12051 = @@ -41686,34 +41675,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h694435 or + always@(guard__h694433 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h694435) + case (guard__h694433) 2'b0, 2'b01, 2'b10: - CASE_guard94435_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q144 = + CASE_guard94433_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q144 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard94435_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q144 = - guard__h694435 != 2'b11 || + CASE_guard94433_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q144 = + guard__h694433 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard94435_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q144 or - guard__h694435) + CASE_guard94433_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q144 or + guard__h694433) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12014 = - CASE_guard94435_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q144; + CASE_guard94433_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q144; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12014 = - (guard__h694435 == 2'b0) ? + (guard__h694433 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h694435 != 2'b01 && guard__h694435 != 2'b10 && - guard__h694435 != 2'b11 || + guard__h694433 != 2'b01 && guard__h694433 != 2'b10 && + guard__h694433 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d12014 = @@ -41770,28 +41759,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_request_put; endcase end - always@(guard__h726326 or - _theResult___fst_exp__h734287 or _theResult___exp__h734942) + always@(guard__h726323 or + _theResult___fst_exp__h734284 or _theResult___exp__h734939) begin - case (guard__h726326) + case (guard__h726323) 2'b0: - CASE_guard26326_0b0_theResult___fst_exp34287_0_ETC__q155 = - _theResult___fst_exp__h734287; + CASE_guard26323_0b0_theResult___fst_exp34284_0_ETC__q155 = + _theResult___fst_exp__h734284; 2'b01, 2'b10, 2'b11: - CASE_guard26326_0b0_theResult___fst_exp34287_0_ETC__q155 = - _theResult___exp__h734942; + CASE_guard26323_0b0_theResult___fst_exp34284_0_ETC__q155 = + _theResult___exp__h734939; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h734287 or + _theResult___fst_exp__h734284 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13166 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13164 or - CASE_guard26326_0b0_theResult___fst_exp34287_0_ETC__q155) + CASE_guard26323_0b0_theResult___fst_exp34284_0_ETC__q155) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13170 = - _theResult___fst_exp__h734287; + _theResult___fst_exp__h734284; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13170 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13166; @@ -41800,44 +41789,44 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13164; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13170 = - CASE_guard26326_0b0_theResult___fst_exp34287_0_ETC__q155; + CASE_guard26323_0b0_theResult___fst_exp34284_0_ETC__q155; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13170 = 11'd0; endcase end - always@(guard__h726326 or - _theResult___fst_exp__h734287 or - out_exp__h734945 or _theResult___exp__h734942) + always@(guard__h726323 or + _theResult___fst_exp__h734284 or + out_exp__h734942 or _theResult___exp__h734939) begin - case (guard__h726326) + case (guard__h726323) 2'b0, 2'b01: - CASE_guard26326_0b0_theResult___fst_exp34287_0_ETC__q156 = - _theResult___fst_exp__h734287; + CASE_guard26323_0b0_theResult___fst_exp34284_0_ETC__q156 = + _theResult___fst_exp__h734284; 2'b10: - CASE_guard26326_0b0_theResult___fst_exp34287_0_ETC__q156 = - out_exp__h734945; + CASE_guard26323_0b0_theResult___fst_exp34284_0_ETC__q156 = + out_exp__h734942; 2'b11: - CASE_guard26326_0b0_theResult___fst_exp34287_0_ETC__q156 = - _theResult___exp__h734942; + CASE_guard26323_0b0_theResult___fst_exp34284_0_ETC__q156 = + _theResult___exp__h734939; endcase end - always@(guard__h726326 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h726323 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h726326) + case (guard__h726323) 2'b0, 2'b01, 2'b10: - CASE_guard26326_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q157 = + CASE_guard26323_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q157 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard26326_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q157 = - guard__h726326 == 2'b11 && + CASE_guard26323_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q157 = + guard__h726323 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h726326) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h726323) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -41847,12 +41836,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q158 = - (guard__h726326 == 2'b0) ? + (guard__h726323 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h726326 == 2'b01 || guard__h726326 == 2'b10 || - guard__h726326 == 2'b11) && + (guard__h726323 == 2'b01 || guard__h726323 == 2'b10 || + guard__h726323 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; @@ -41863,23 +41852,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(guard__h735638 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h735635 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h735638) + case (guard__h735635) 2'b0, 2'b01, 2'b10: - CASE_guard35638_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q159 = + CASE_guard35635_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q159 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard35638_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q159 = - guard__h735638 == 2'b11 && + CASE_guard35635_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q159 = + guard__h735635 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h735638) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h735635) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -41889,12 +41878,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q160 = - (guard__h735638 == 2'b0) ? + (guard__h735635 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h735638 == 2'b01 || guard__h735638 == 2'b10 || - guard__h735638 == 2'b11) && + (guard__h735635 == 2'b01 || guard__h735635 == 2'b10 || + guard__h735635 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; @@ -41905,23 +41894,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(guard__h744707 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h744704 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h744707) + case (guard__h744704) 2'b0, 2'b01, 2'b10: - CASE_guard44707_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q161 = + CASE_guard44704_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q161 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard44707_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q161 = - guard__h744707 == 2'b11 && + CASE_guard44704_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q161 = + guard__h744704 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h744707) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h744704) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -41931,12 +41920,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q162 = - (guard__h744707 == 2'b0) ? + (guard__h744704 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h744707 == 2'b01 || guard__h744707 == 2'b10 || - guard__h744707 == 2'b11) && + (guard__h744704 == 2'b01 || guard__h744704 == 2'b10 || + guard__h744704 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; @@ -41947,28 +41936,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(guard__h804483 or - _theResult___fst_exp__h812444 or _theResult___exp__h813099) + always@(guard__h804480 or + _theResult___fst_exp__h812441 or _theResult___exp__h813096) begin - case (guard__h804483) + case (guard__h804480) 2'b0: - CASE_guard04483_0b0_theResult___fst_exp12444_0_ETC__q172 = - _theResult___fst_exp__h812444; + CASE_guard04480_0b0_theResult___fst_exp12441_0_ETC__q172 = + _theResult___fst_exp__h812441; 2'b01, 2'b10, 2'b11: - CASE_guard04483_0b0_theResult___fst_exp12444_0_ETC__q172 = - _theResult___exp__h813099; + CASE_guard04480_0b0_theResult___fst_exp12441_0_ETC__q172 = + _theResult___exp__h813096; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h812444 or + _theResult___fst_exp__h812441 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13881 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13879 or - CASE_guard04483_0b0_theResult___fst_exp12444_0_ETC__q172) + CASE_guard04480_0b0_theResult___fst_exp12441_0_ETC__q172) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13885 = - _theResult___fst_exp__h812444; + _theResult___fst_exp__h812441; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13885 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13881; @@ -41977,42 +41966,42 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13879; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13885 = - CASE_guard04483_0b0_theResult___fst_exp12444_0_ETC__q172; + CASE_guard04480_0b0_theResult___fst_exp12441_0_ETC__q172; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13885 = 11'd0; endcase end - always@(guard__h804483 or - _theResult___fst_exp__h812444 or - out_exp__h813102 or _theResult___exp__h813099) + always@(guard__h804480 or + _theResult___fst_exp__h812441 or + out_exp__h813099 or _theResult___exp__h813096) begin - case (guard__h804483) + case (guard__h804480) 2'b0, 2'b01: - CASE_guard04483_0b0_theResult___fst_exp12444_0_ETC__q173 = - _theResult___fst_exp__h812444; + CASE_guard04480_0b0_theResult___fst_exp12441_0_ETC__q173 = + _theResult___fst_exp__h812441; 2'b10: - CASE_guard04483_0b0_theResult___fst_exp12444_0_ETC__q173 = - out_exp__h813102; + CASE_guard04480_0b0_theResult___fst_exp12441_0_ETC__q173 = + out_exp__h813099; 2'b11: - CASE_guard04483_0b0_theResult___fst_exp12444_0_ETC__q173 = - _theResult___exp__h813099; + CASE_guard04480_0b0_theResult___fst_exp12441_0_ETC__q173 = + _theResult___exp__h813096; endcase end - always@(guard__h804483 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h813792 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h804483) + case (guard__h813792) 2'b0, 2'b01, 2'b10: - CASE_guard04483_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q174 = + CASE_guard13792_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q174 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard04483_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q174 = - guard__h804483 == 2'b11 && + CASE_guard13792_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q174 = + guard__h813792 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h804483) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h813792) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -42021,12 +42010,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q175 = - (guard__h804483 == 2'b0) ? + (guard__h813792 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h804483 == 2'b01 || guard__h804483 == 2'b10 || - guard__h804483 == 2'b11) && + (guard__h813792 == 2'b01 || guard__h813792 == 2'b10 || + guard__h813792 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -42037,21 +42026,21 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h813795 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h804480 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h813795) + case (guard__h804480) 2'b0, 2'b01, 2'b10: - CASE_guard13795_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q176 = + CASE_guard04480_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q176 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard13795_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q176 = - guard__h813795 == 2'b11 && + CASE_guard04480_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q176 = + guard__h804480 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h813795) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h804480) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -42060,12 +42049,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q177 = - (guard__h813795 == 2'b0) ? + (guard__h804480 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h813795 == 2'b01 || guard__h813795 == 2'b10 || - guard__h813795 == 2'b11) && + (guard__h804480 == 2'b01 || guard__h804480 == 2'b10 || + guard__h804480 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -42076,21 +42065,21 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h822864 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h822861 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h822864) + case (guard__h822861) 2'b0, 2'b01, 2'b10: - CASE_guard22864_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q178 = + CASE_guard22861_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q178 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard22864_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q178 = - guard__h822864 == 2'b11 && + CASE_guard22861_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q178 = + guard__h822861 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h822864) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h822861) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -42099,12 +42088,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q179 = - (guard__h822864 == 2'b0) ? + (guard__h822861 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h822864 == 2'b01 || guard__h822864 == 2'b10 || - guard__h822864 == 2'b11) && + (guard__h822861 == 2'b01 || guard__h822861 == 2'b10 || + guard__h822861 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -42115,21 +42104,21 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h813795 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h813792 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h813795) + case (guard__h813792) 2'b0, 2'b01, 2'b10: - CASE_guard13795_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q180 = + CASE_guard13792_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q180 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard13795_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q180 = - guard__h813795 != 2'b11 || + CASE_guard13792_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q180 = + guard__h813792 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h813795) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h813792) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -42138,12 +42127,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q181 = - (guard__h813795 == 2'b0) ? + (guard__h813792 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h813795 != 2'b01 && guard__h813795 != 2'b10 && - guard__h813795 != 2'b11 || + guard__h813792 != 2'b01 && guard__h813792 != 2'b10 && + guard__h813792 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -42154,21 +42143,21 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h822864 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h822861 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h822864) + case (guard__h822861) 2'b0, 2'b01, 2'b10: - CASE_guard22864_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q182 = + CASE_guard22861_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q182 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard22864_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q182 = - guard__h822864 != 2'b11 || + CASE_guard22861_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q182 = + guard__h822861 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h822864) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h822861) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -42177,12 +42166,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q183 = - (guard__h822864 == 2'b0) ? + (guard__h822861 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h822864 != 2'b01 && guard__h822864 != 2'b10 && - guard__h822864 != 2'b11 || + guard__h822861 != 2'b01 && guard__h822861 != 2'b10 && + guard__h822861 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -42193,21 +42182,21 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h804483 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h804480 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h804483) + case (guard__h804480) 2'b0, 2'b01, 2'b10: - CASE_guard04483_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q184 = + CASE_guard04480_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q184 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard04483_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q184 = - guard__h804483 != 2'b11 || + CASE_guard04480_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q184 = + guard__h804480 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h804483) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h804480) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -42216,12 +42205,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q185 = - (guard__h804483 == 2'b0) ? + (guard__h804480 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h804483 != 2'b01 && guard__h804483 != 2'b10 && - guard__h804483 != 2'b11 || + guard__h804480 != 2'b01 && guard__h804480 != 2'b10 && + guard__h804480 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -42232,28 +42221,28 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h765179 or - _theResult___fst_exp__h773140 or _theResult___exp__h773795) + always@(guard__h765176 or + _theResult___fst_exp__h773137 or _theResult___exp__h773792) begin - case (guard__h765179) + case (guard__h765176) 2'b0: - CASE_guard65179_0b0_theResult___fst_exp73140_0_ETC__q195 = - _theResult___fst_exp__h773140; + CASE_guard65176_0b0_theResult___fst_exp73137_0_ETC__q195 = + _theResult___fst_exp__h773137; 2'b01, 2'b10, 2'b11: - CASE_guard65179_0b0_theResult___fst_exp73140_0_ETC__q195 = - _theResult___exp__h773795; + CASE_guard65176_0b0_theResult___fst_exp73137_0_ETC__q195 = + _theResult___exp__h773792; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h773140 or + _theResult___fst_exp__h773137 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14651 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14649 or - CASE_guard65179_0b0_theResult___fst_exp73140_0_ETC__q195) + CASE_guard65176_0b0_theResult___fst_exp73137_0_ETC__q195) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14655 = - _theResult___fst_exp__h773140; + _theResult___fst_exp__h773137; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14655 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14651; @@ -42262,100 +42251,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14649; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14655 = - CASE_guard65179_0b0_theResult___fst_exp73140_0_ETC__q195; + CASE_guard65176_0b0_theResult___fst_exp73137_0_ETC__q195; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14655 = 11'd0; endcase end - always@(guard__h765179 or - _theResult___fst_exp__h773140 or - out_exp__h773798 or _theResult___exp__h773795) + always@(guard__h765176 or + _theResult___fst_exp__h773137 or + out_exp__h773795 or _theResult___exp__h773792) begin - case (guard__h765179) + case (guard__h765176) 2'b0, 2'b01: - CASE_guard65179_0b0_theResult___fst_exp73140_0_ETC__q196 = - _theResult___fst_exp__h773140; + CASE_guard65176_0b0_theResult___fst_exp73137_0_ETC__q196 = + _theResult___fst_exp__h773137; 2'b10: - CASE_guard65179_0b0_theResult___fst_exp73140_0_ETC__q196 = - out_exp__h773798; + CASE_guard65176_0b0_theResult___fst_exp73137_0_ETC__q196 = + out_exp__h773795; 2'b11: - CASE_guard65179_0b0_theResult___fst_exp73140_0_ETC__q196 = - _theResult___exp__h773795; + CASE_guard65176_0b0_theResult___fst_exp73137_0_ETC__q196 = + _theResult___exp__h773792; endcase end - always@(guard__h783560 or - _theResult___fst_exp__h791550 or _theResult___exp__h792230) + always@(guard__h774488 or + _theResult___fst_exp__h782714 or _theResult___exp__h783443) begin - case (guard__h783560) + case (guard__h774488) 2'b0: - CASE_guard83560_0b0_theResult___fst_exp91550_0_ETC__q197 = - _theResult___fst_exp__h791550; + CASE_guard74488_0b0_theResult___fst_exp82714_0_ETC__q197 = + _theResult___fst_exp__h782714; 2'b01, 2'b10, 2'b11: - CASE_guard83560_0b0_theResult___fst_exp91550_0_ETC__q197 = - _theResult___exp__h792230; + CASE_guard74488_0b0_theResult___fst_exp82714_0_ETC__q197 = + _theResult___exp__h783443; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h791550 or - IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14720 or - IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14718 or - CASE_guard83560_0b0_theResult___fst_exp91550_0_ETC__q197) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd1: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14724 = - _theResult___fst_exp__h791550; - 3'd2: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14724 = - IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14720; - 3'd3: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14724 = - IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14718; - 3'd4: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14724 = - CASE_guard83560_0b0_theResult___fst_exp91550_0_ETC__q197; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14724 = - 11'd0; - endcase - end - always@(guard__h783560 or - _theResult___fst_exp__h791550 or - out_exp__h792233 or _theResult___exp__h792230) - begin - case (guard__h783560) - 2'b0, 2'b01: - CASE_guard83560_0b0_theResult___fst_exp91550_0_ETC__q198 = - _theResult___fst_exp__h791550; - 2'b10: - CASE_guard83560_0b0_theResult___fst_exp91550_0_ETC__q198 = - out_exp__h792233; - 2'b11: - CASE_guard83560_0b0_theResult___fst_exp91550_0_ETC__q198 = - _theResult___exp__h792230; - endcase - end - always@(guard__h774491 or - _theResult___fst_exp__h782717 or _theResult___exp__h783446) - begin - case (guard__h774491) - 2'b0: - CASE_guard74491_0b0_theResult___fst_exp82717_0_ETC__q199 = - _theResult___fst_exp__h782717; - 2'b01, 2'b10, 2'b11: - CASE_guard74491_0b0_theResult___fst_exp82717_0_ETC__q199 = - _theResult___exp__h783446; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h782717 or + _theResult___fst_exp__h782714 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14689 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14687 or - CASE_guard74491_0b0_theResult___fst_exp82717_0_ETC__q199) + CASE_guard74488_0b0_theResult___fst_exp82714_0_ETC__q197) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14693 = - _theResult___fst_exp__h782717; + _theResult___fst_exp__h782714; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14693 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14689; @@ -42364,100 +42302,100 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14687; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14693 = - CASE_guard74491_0b0_theResult___fst_exp82717_0_ETC__q199; + CASE_guard74488_0b0_theResult___fst_exp82714_0_ETC__q197; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14693 = 11'd0; endcase end - always@(guard__h774491 or - _theResult___fst_exp__h782717 or - out_exp__h783449 or _theResult___exp__h783446) + always@(guard__h774488 or + _theResult___fst_exp__h782714 or + out_exp__h783446 or _theResult___exp__h783443) begin - case (guard__h774491) + case (guard__h774488) 2'b0, 2'b01: - CASE_guard74491_0b0_theResult___fst_exp82717_0_ETC__q200 = - _theResult___fst_exp__h782717; + CASE_guard74488_0b0_theResult___fst_exp82714_0_ETC__q198 = + _theResult___fst_exp__h782714; 2'b10: - CASE_guard74491_0b0_theResult___fst_exp82717_0_ETC__q200 = - out_exp__h783449; + CASE_guard74488_0b0_theResult___fst_exp82714_0_ETC__q198 = + out_exp__h783446; 2'b11: - CASE_guard74491_0b0_theResult___fst_exp82717_0_ETC__q200 = - _theResult___exp__h783446; + CASE_guard74488_0b0_theResult___fst_exp82714_0_ETC__q198 = + _theResult___exp__h783443; endcase end - always@(guard__h813795 or - _theResult___fst_exp__h822021 or _theResult___exp__h822750) + always@(guard__h783557 or + _theResult___fst_exp__h791547 or _theResult___exp__h792227) begin - case (guard__h813795) + case (guard__h783557) 2'b0: - CASE_guard13795_0b0_theResult___fst_exp22021_0_ETC__q201 = - _theResult___fst_exp__h822021; + CASE_guard83557_0b0_theResult___fst_exp91547_0_ETC__q199 = + _theResult___fst_exp__h791547; 2'b01, 2'b10, 2'b11: - CASE_guard13795_0b0_theResult___fst_exp22021_0_ETC__q201 = - _theResult___exp__h822750; + CASE_guard83557_0b0_theResult___fst_exp91547_0_ETC__q199 = + _theResult___exp__h792227; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h822021 or - IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13919 or - IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13917 or - CASE_guard13795_0b0_theResult___fst_exp22021_0_ETC__q201) + _theResult___fst_exp__h791547 or + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14720 or + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14718 or + CASE_guard83557_0b0_theResult___fst_exp91547_0_ETC__q199) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13923 = - _theResult___fst_exp__h822021; + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14724 = + _theResult___fst_exp__h791547; 3'd2: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13923 = - IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13919; + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14724 = + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14720; 3'd3: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13923 = - IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13917; + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14724 = + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14718; 3'd4: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13923 = - CASE_guard13795_0b0_theResult___fst_exp22021_0_ETC__q201; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13923 = + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14724 = + CASE_guard83557_0b0_theResult___fst_exp91547_0_ETC__q199; + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14724 = 11'd0; endcase end - always@(guard__h813795 or - _theResult___fst_exp__h822021 or - out_exp__h822753 or _theResult___exp__h822750) + always@(guard__h783557 or + _theResult___fst_exp__h791547 or + out_exp__h792230 or _theResult___exp__h792227) begin - case (guard__h813795) + case (guard__h783557) 2'b0, 2'b01: - CASE_guard13795_0b0_theResult___fst_exp22021_0_ETC__q202 = - _theResult___fst_exp__h822021; + CASE_guard83557_0b0_theResult___fst_exp91547_0_ETC__q200 = + _theResult___fst_exp__h791547; 2'b10: - CASE_guard13795_0b0_theResult___fst_exp22021_0_ETC__q202 = - out_exp__h822753; + CASE_guard83557_0b0_theResult___fst_exp91547_0_ETC__q200 = + out_exp__h792230; 2'b11: - CASE_guard13795_0b0_theResult___fst_exp22021_0_ETC__q202 = - _theResult___exp__h822750; + CASE_guard83557_0b0_theResult___fst_exp91547_0_ETC__q200 = + _theResult___exp__h792227; endcase end - always@(guard__h822864 or - _theResult___fst_exp__h830854 or _theResult___exp__h831534) + always@(guard__h822861 or + _theResult___fst_exp__h830851 or _theResult___exp__h831531) begin - case (guard__h822864) + case (guard__h822861) 2'b0: - CASE_guard22864_0b0_theResult___fst_exp30854_0_ETC__q203 = - _theResult___fst_exp__h830854; + CASE_guard22861_0b0_theResult___fst_exp30851_0_ETC__q201 = + _theResult___fst_exp__h830851; 2'b01, 2'b10, 2'b11: - CASE_guard22864_0b0_theResult___fst_exp30854_0_ETC__q203 = - _theResult___exp__h831534; + CASE_guard22861_0b0_theResult___fst_exp30851_0_ETC__q201 = + _theResult___exp__h831531; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h830854 or + _theResult___fst_exp__h830851 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13950 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13948 or - CASE_guard22864_0b0_theResult___fst_exp30854_0_ETC__q203) + CASE_guard22861_0b0_theResult___fst_exp30851_0_ETC__q201) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13954 = - _theResult___fst_exp__h830854; + _theResult___fst_exp__h830851; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13954 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13950; @@ -42466,44 +42404,95 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13948; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13954 = - CASE_guard22864_0b0_theResult___fst_exp30854_0_ETC__q203; + CASE_guard22861_0b0_theResult___fst_exp30851_0_ETC__q201; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13954 = 11'd0; endcase end - always@(guard__h822864 or - _theResult___fst_exp__h830854 or - out_exp__h831537 or _theResult___exp__h831534) + always@(guard__h822861 or + _theResult___fst_exp__h830851 or + out_exp__h831534 or _theResult___exp__h831531) begin - case (guard__h822864) + case (guard__h822861) 2'b0, 2'b01: - CASE_guard22864_0b0_theResult___fst_exp30854_0_ETC__q204 = - _theResult___fst_exp__h830854; + CASE_guard22861_0b0_theResult___fst_exp30851_0_ETC__q202 = + _theResult___fst_exp__h830851; 2'b10: - CASE_guard22864_0b0_theResult___fst_exp30854_0_ETC__q204 = - out_exp__h831537; + CASE_guard22861_0b0_theResult___fst_exp30851_0_ETC__q202 = + out_exp__h831534; 2'b11: - CASE_guard22864_0b0_theResult___fst_exp30854_0_ETC__q204 = - _theResult___exp__h831534; + CASE_guard22861_0b0_theResult___fst_exp30851_0_ETC__q202 = + _theResult___exp__h831531; endcase end - always@(guard__h765179 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h813792 or + _theResult___fst_exp__h822018 or _theResult___exp__h822747) begin - case (guard__h765179) + case (guard__h813792) + 2'b0: + CASE_guard13792_0b0_theResult___fst_exp22018_0_ETC__q203 = + _theResult___fst_exp__h822018; + 2'b01, 2'b10, 2'b11: + CASE_guard13792_0b0_theResult___fst_exp22018_0_ETC__q203 = + _theResult___exp__h822747; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or + _theResult___fst_exp__h822018 or + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13919 or + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13917 or + CASE_guard13792_0b0_theResult___fst_exp22018_0_ETC__q203) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd1: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13923 = + _theResult___fst_exp__h822018; + 3'd2: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13923 = + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13919; + 3'd3: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13923 = + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13917; + 3'd4: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13923 = + CASE_guard13792_0b0_theResult___fst_exp22018_0_ETC__q203; + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13923 = + 11'd0; + endcase + end + always@(guard__h813792 or + _theResult___fst_exp__h822018 or + out_exp__h822750 or _theResult___exp__h822747) + begin + case (guard__h813792) + 2'b0, 2'b01: + CASE_guard13792_0b0_theResult___fst_exp22018_0_ETC__q204 = + _theResult___fst_exp__h822018; + 2'b10: + CASE_guard13792_0b0_theResult___fst_exp22018_0_ETC__q204 = + out_exp__h822750; + 2'b11: + CASE_guard13792_0b0_theResult___fst_exp22018_0_ETC__q204 = + _theResult___exp__h822747; + endcase + end + always@(guard__h765176 or coreFix_fpuMulDivExe_0_regToExeQ$first) + begin + case (guard__h765176) 2'b0, 2'b01, 2'b10: - CASE_guard65179_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q205 = + CASE_guard65176_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q205 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard65179_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q205 = - guard__h765179 == 2'b11 && + CASE_guard65176_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q205 = + guard__h765176 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h765179) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h765176) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -42513,12 +42502,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q206 = - (guard__h765179 == 2'b0) ? + (guard__h765176 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h765179 == 2'b01 || guard__h765179 == 2'b10 || - guard__h765179 == 2'b11) && + (guard__h765176 == 2'b01 || guard__h765176 == 2'b10 || + guard__h765176 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -42529,23 +42518,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h774491 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h774488 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h774491) + case (guard__h774488) 2'b0, 2'b01, 2'b10: - CASE_guard74491_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q207 = + CASE_guard74488_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q207 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard74491_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q207 = - guard__h774491 == 2'b11 && + CASE_guard74488_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q207 = + guard__h774488 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h774491) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h774488) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -42555,12 +42544,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q208 = - (guard__h774491 == 2'b0) ? + (guard__h774488 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h774491 == 2'b01 || guard__h774491 == 2'b10 || - guard__h774491 == 2'b11) && + (guard__h774488 == 2'b01 || guard__h774488 == 2'b10 || + guard__h774488 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -42571,23 +42560,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h783560 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h783557 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h783560) + case (guard__h783557) 2'b0, 2'b01, 2'b10: - CASE_guard83560_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q209 = + CASE_guard83557_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q209 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard83560_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q209 = - guard__h783560 == 2'b11 && + CASE_guard83557_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q209 = + guard__h783557 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h783560) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h783557) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -42597,12 +42586,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q210 = - (guard__h783560 == 2'b0) ? + (guard__h783557 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h783560 == 2'b01 || guard__h783560 == 2'b10 || - guard__h783560 == 2'b11) && + (guard__h783557 == 2'b01 || guard__h783557 == 2'b10 || + guard__h783557 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -42613,23 +42602,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h774491 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h774488 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h774491) + case (guard__h774488) 2'b0, 2'b01, 2'b10: - CASE_guard74491_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q211 = + CASE_guard74488_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q211 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard74491_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q211 = - guard__h774491 != 2'b11 || + CASE_guard74488_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q211 = + guard__h774488 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h774491) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h774488) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -42639,12 +42628,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q212 = - (guard__h774491 == 2'b0) ? + (guard__h774488 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h774491 != 2'b01 && guard__h774491 != 2'b10 && - guard__h774491 != 2'b11 || + guard__h774488 != 2'b01 && guard__h774488 != 2'b10 && + guard__h774488 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -42655,23 +42644,23 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h783560 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h783557 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h783560) + case (guard__h783557) 2'b0, 2'b01, 2'b10: - CASE_guard83560_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q213 = + CASE_guard83557_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q213 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard83560_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q213 = - guard__h783560 != 2'b11 || + CASE_guard83557_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q213 = + guard__h783557 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h783560) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h783557) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -42681,12 +42670,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q214 = - (guard__h783560 == 2'b0) ? + (guard__h783557 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h783560 != 2'b01 && guard__h783560 != 2'b10 && - guard__h783560 != 2'b11 || + guard__h783557 != 2'b01 && guard__h783557 != 2'b10 && + guard__h783557 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -42697,23 +42686,23 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h765179 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h765176 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h765179) + case (guard__h765176) 2'b0, 2'b01, 2'b10: - CASE_guard65179_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q215 = + CASE_guard65176_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q215 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard65179_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q215 = - guard__h765179 != 2'b11 || + CASE_guard65176_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q215 = + guard__h765176 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h765179) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h765176) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -42723,12 +42712,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q216 = - (guard__h765179 == 2'b0) ? + (guard__h765176 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h765179 != 2'b01 && guard__h765179 != 2'b10 && - guard__h765179 != 2'b11 || + guard__h765176 != 2'b01 && guard__h765176 != 2'b10 && + guard__h765176 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -42739,28 +42728,28 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h765179 or - _theResult___snd__h773091 or _theResult___sfd__h773796) + always@(guard__h765176 or + _theResult___snd__h773088 or _theResult___sfd__h773793) begin - case (guard__h765179) + case (guard__h765176) 2'b0: - CASE_guard65179_0b0_theResult___snd73091_BITS__ETC__q217 = - _theResult___snd__h773091[56:5]; + CASE_guard65176_0b0_theResult___snd73088_BITS__ETC__q217 = + _theResult___snd__h773088[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard65179_0b0_theResult___snd73091_BITS__ETC__q217 = - _theResult___sfd__h773796; + CASE_guard65176_0b0_theResult___snd73088_BITS__ETC__q217 = + _theResult___sfd__h773793; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h773091 or + _theResult___snd__h773088 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14746 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14744 or - CASE_guard65179_0b0_theResult___snd73091_BITS__ETC__q217) + CASE_guard65176_0b0_theResult___snd73088_BITS__ETC__q217) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14750 = - _theResult___snd__h773091[56:5]; + _theResult___snd__h773088[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14750 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14746; @@ -42769,48 +42758,48 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14744; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14750 = - CASE_guard65179_0b0_theResult___snd73091_BITS__ETC__q217; + CASE_guard65176_0b0_theResult___snd73088_BITS__ETC__q217; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14750 = 52'd0; endcase end - always@(guard__h765179 or - _theResult___snd__h773091 or - out_sfd__h773799 or _theResult___sfd__h773796) + always@(guard__h765176 or + _theResult___snd__h773088 or + out_sfd__h773796 or _theResult___sfd__h773793) begin - case (guard__h765179) + case (guard__h765176) 2'b0, 2'b01: - CASE_guard65179_0b0_theResult___snd73091_BITS__ETC__q218 = - _theResult___snd__h773091[56:5]; + CASE_guard65176_0b0_theResult___snd73088_BITS__ETC__q218 = + _theResult___snd__h773088[56:5]; 2'b10: - CASE_guard65179_0b0_theResult___snd73091_BITS__ETC__q218 = - out_sfd__h773799; + CASE_guard65176_0b0_theResult___snd73088_BITS__ETC__q218 = + out_sfd__h773796; 2'b11: - CASE_guard65179_0b0_theResult___snd73091_BITS__ETC__q218 = - _theResult___sfd__h773796; + CASE_guard65176_0b0_theResult___snd73088_BITS__ETC__q218 = + _theResult___sfd__h773793; endcase end - always@(guard__h774491 or sfdin__h782711 or _theResult___sfd__h783447) + always@(guard__h774488 or sfdin__h782708 or _theResult___sfd__h783444) begin - case (guard__h774491) + case (guard__h774488) 2'b0: - CASE_guard74491_0b0_sfdin82711_BITS_56_TO_5_0b_ETC__q219 = - sfdin__h782711[56:5]; + CASE_guard74488_0b0_sfdin82708_BITS_56_TO_5_0b_ETC__q219 = + sfdin__h782708[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard74491_0b0_sfdin82711_BITS_56_TO_5_0b_ETC__q219 = - _theResult___sfd__h783447; + CASE_guard74488_0b0_sfdin82708_BITS_56_TO_5_0b_ETC__q219 = + _theResult___sfd__h783444; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h782711 or + sfdin__h782708 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14772 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14770 or - CASE_guard74491_0b0_sfdin82711_BITS_56_TO_5_0b_ETC__q219) + CASE_guard74488_0b0_sfdin82708_BITS_56_TO_5_0b_ETC__q219) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14776 = - sfdin__h782711[56:5]; + sfdin__h782708[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14776 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14772; @@ -42819,48 +42808,48 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14770; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14776 = - CASE_guard74491_0b0_sfdin82711_BITS_56_TO_5_0b_ETC__q219; + CASE_guard74488_0b0_sfdin82708_BITS_56_TO_5_0b_ETC__q219; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14776 = 52'd0; endcase end - always@(guard__h774491 or - sfdin__h782711 or out_sfd__h783450 or _theResult___sfd__h783447) + always@(guard__h774488 or + sfdin__h782708 or out_sfd__h783447 or _theResult___sfd__h783444) begin - case (guard__h774491) + case (guard__h774488) 2'b0, 2'b01: - CASE_guard74491_0b0_sfdin82711_BITS_56_TO_5_0b_ETC__q220 = - sfdin__h782711[56:5]; + CASE_guard74488_0b0_sfdin82708_BITS_56_TO_5_0b_ETC__q220 = + sfdin__h782708[56:5]; 2'b10: - CASE_guard74491_0b0_sfdin82711_BITS_56_TO_5_0b_ETC__q220 = - out_sfd__h783450; + CASE_guard74488_0b0_sfdin82708_BITS_56_TO_5_0b_ETC__q220 = + out_sfd__h783447; 2'b11: - CASE_guard74491_0b0_sfdin82711_BITS_56_TO_5_0b_ETC__q220 = - _theResult___sfd__h783447; + CASE_guard74488_0b0_sfdin82708_BITS_56_TO_5_0b_ETC__q220 = + _theResult___sfd__h783444; endcase end - always@(guard__h783560 or - _theResult___snd__h791496 or _theResult___sfd__h792231) + always@(guard__h783557 or + _theResult___snd__h791493 or _theResult___sfd__h792228) begin - case (guard__h783560) + case (guard__h783557) 2'b0: - CASE_guard83560_0b0_theResult___snd91496_BITS__ETC__q221 = - _theResult___snd__h791496[56:5]; + CASE_guard83557_0b0_theResult___snd91493_BITS__ETC__q221 = + _theResult___snd__h791493[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard83560_0b0_theResult___snd91496_BITS__ETC__q221 = - _theResult___sfd__h792231; + CASE_guard83557_0b0_theResult___snd91493_BITS__ETC__q221 = + _theResult___sfd__h792228; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h791496 or + _theResult___snd__h791493 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14791 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14789 or - CASE_guard83560_0b0_theResult___snd91496_BITS__ETC__q221) + CASE_guard83557_0b0_theResult___snd91493_BITS__ETC__q221) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14795 = - _theResult___snd__h791496[56:5]; + _theResult___snd__h791493[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14795 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14791; @@ -42869,49 +42858,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14789; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14795 = - CASE_guard83560_0b0_theResult___snd91496_BITS__ETC__q221; + CASE_guard83557_0b0_theResult___snd91493_BITS__ETC__q221; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14795 = 52'd0; endcase end - always@(guard__h783560 or - _theResult___snd__h791496 or - out_sfd__h792234 or _theResult___sfd__h792231) + always@(guard__h783557 or + _theResult___snd__h791493 or + out_sfd__h792231 or _theResult___sfd__h792228) begin - case (guard__h783560) + case (guard__h783557) 2'b0, 2'b01: - CASE_guard83560_0b0_theResult___snd91496_BITS__ETC__q222 = - _theResult___snd__h791496[56:5]; + CASE_guard83557_0b0_theResult___snd91493_BITS__ETC__q222 = + _theResult___snd__h791493[56:5]; 2'b10: - CASE_guard83560_0b0_theResult___snd91496_BITS__ETC__q222 = - out_sfd__h792234; + CASE_guard83557_0b0_theResult___snd91493_BITS__ETC__q222 = + out_sfd__h792231; 2'b11: - CASE_guard83560_0b0_theResult___snd91496_BITS__ETC__q222 = - _theResult___sfd__h792231; + CASE_guard83557_0b0_theResult___snd91493_BITS__ETC__q222 = + _theResult___sfd__h792228; endcase end - always@(guard__h735638 or - _theResult___fst_exp__h743864 or _theResult___exp__h744593) + always@(guard__h735635 or + _theResult___fst_exp__h743861 or _theResult___exp__h744590) begin - case (guard__h735638) + case (guard__h735635) 2'b0: - CASE_guard35638_0b0_theResult___fst_exp43864_0_ETC__q223 = - _theResult___fst_exp__h743864; + CASE_guard35635_0b0_theResult___fst_exp43861_0_ETC__q223 = + _theResult___fst_exp__h743861; 2'b01, 2'b10, 2'b11: - CASE_guard35638_0b0_theResult___fst_exp43864_0_ETC__q223 = - _theResult___exp__h744593; + CASE_guard35635_0b0_theResult___fst_exp43861_0_ETC__q223 = + _theResult___exp__h744590; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h743864 or + _theResult___fst_exp__h743861 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13209 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13207 or - CASE_guard35638_0b0_theResult___fst_exp43864_0_ETC__q223) + CASE_guard35635_0b0_theResult___fst_exp43861_0_ETC__q223) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13213 = - _theResult___fst_exp__h743864; + _theResult___fst_exp__h743861; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13213 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13209; @@ -42920,100 +42909,49 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13207; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13213 = - CASE_guard35638_0b0_theResult___fst_exp43864_0_ETC__q223; + CASE_guard35635_0b0_theResult___fst_exp43861_0_ETC__q223; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13213 = 11'd0; endcase end - always@(guard__h735638 or - _theResult___fst_exp__h743864 or - out_exp__h744596 or _theResult___exp__h744593) + always@(guard__h735635 or + _theResult___fst_exp__h743861 or + out_exp__h744593 or _theResult___exp__h744590) begin - case (guard__h735638) + case (guard__h735635) 2'b0, 2'b01: - CASE_guard35638_0b0_theResult___fst_exp43864_0_ETC__q224 = - _theResult___fst_exp__h743864; + CASE_guard35635_0b0_theResult___fst_exp43861_0_ETC__q224 = + _theResult___fst_exp__h743861; 2'b10: - CASE_guard35638_0b0_theResult___fst_exp43864_0_ETC__q224 = - out_exp__h744596; + CASE_guard35635_0b0_theResult___fst_exp43861_0_ETC__q224 = + out_exp__h744593; 2'b11: - CASE_guard35638_0b0_theResult___fst_exp43864_0_ETC__q224 = - _theResult___exp__h744593; + CASE_guard35635_0b0_theResult___fst_exp43861_0_ETC__q224 = + _theResult___exp__h744590; endcase end - always@(guard__h744707 or - _theResult___fst_exp__h752697 or _theResult___exp__h753377) + always@(guard__h726323 or + _theResult___snd__h734235 or _theResult___sfd__h734940) begin - case (guard__h744707) + case (guard__h726323) 2'b0: - CASE_guard44707_0b0_theResult___fst_exp52697_0_ETC__q225 = - _theResult___fst_exp__h752697; + CASE_guard26323_0b0_theResult___snd34235_BITS__ETC__q225 = + _theResult___snd__h734235[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard44707_0b0_theResult___fst_exp52697_0_ETC__q225 = - _theResult___exp__h753377; + CASE_guard26323_0b0_theResult___snd34235_BITS__ETC__q225 = + _theResult___sfd__h734940; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h752697 or - IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13240 or - IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13238 or - CASE_guard44707_0b0_theResult___fst_exp52697_0_ETC__q225) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd1: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13244 = - _theResult___fst_exp__h752697; - 3'd2: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13244 = - IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13240; - 3'd3: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13244 = - IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13238; - 3'd4: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13244 = - CASE_guard44707_0b0_theResult___fst_exp52697_0_ETC__q225; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13244 = - 11'd0; - endcase - end - always@(guard__h744707 or - _theResult___fst_exp__h752697 or - out_exp__h753380 or _theResult___exp__h753377) - begin - case (guard__h744707) - 2'b0, 2'b01: - CASE_guard44707_0b0_theResult___fst_exp52697_0_ETC__q226 = - _theResult___fst_exp__h752697; - 2'b10: - CASE_guard44707_0b0_theResult___fst_exp52697_0_ETC__q226 = - out_exp__h753380; - 2'b11: - CASE_guard44707_0b0_theResult___fst_exp52697_0_ETC__q226 = - _theResult___exp__h753377; - endcase - end - always@(guard__h726326 or - _theResult___snd__h734238 or _theResult___sfd__h734943) - begin - case (guard__h726326) - 2'b0: - CASE_guard26326_0b0_theResult___snd34238_BITS__ETC__q227 = - _theResult___snd__h734238[56:5]; - 2'b01, 2'b10, 2'b11: - CASE_guard26326_0b0_theResult___snd34238_BITS__ETC__q227 = - _theResult___sfd__h734943; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h734238 or + _theResult___snd__h734235 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13266 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13264 or - CASE_guard26326_0b0_theResult___snd34238_BITS__ETC__q227) + CASE_guard26323_0b0_theResult___snd34235_BITS__ETC__q225) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13270 = - _theResult___snd__h734238[56:5]; + _theResult___snd__h734235[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13270 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13266; @@ -43022,48 +42960,99 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13264; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13270 = - CASE_guard26326_0b0_theResult___snd34238_BITS__ETC__q227; + CASE_guard26323_0b0_theResult___snd34235_BITS__ETC__q225; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13270 = 52'd0; endcase end - always@(guard__h726326 or - _theResult___snd__h734238 or - out_sfd__h734946 or _theResult___sfd__h734943) + always@(guard__h726323 or + _theResult___snd__h734235 or + out_sfd__h734943 or _theResult___sfd__h734940) begin - case (guard__h726326) + case (guard__h726323) 2'b0, 2'b01: - CASE_guard26326_0b0_theResult___snd34238_BITS__ETC__q228 = - _theResult___snd__h734238[56:5]; + CASE_guard26323_0b0_theResult___snd34235_BITS__ETC__q226 = + _theResult___snd__h734235[56:5]; 2'b10: - CASE_guard26326_0b0_theResult___snd34238_BITS__ETC__q228 = - out_sfd__h734946; + CASE_guard26323_0b0_theResult___snd34235_BITS__ETC__q226 = + out_sfd__h734943; 2'b11: - CASE_guard26326_0b0_theResult___snd34238_BITS__ETC__q228 = - _theResult___sfd__h734943; + CASE_guard26323_0b0_theResult___snd34235_BITS__ETC__q226 = + _theResult___sfd__h734940; endcase end - always@(guard__h735638 or sfdin__h743858 or _theResult___sfd__h744594) + always@(guard__h744704 or + _theResult___fst_exp__h752694 or _theResult___exp__h753374) begin - case (guard__h735638) + case (guard__h744704) 2'b0: - CASE_guard35638_0b0_sfdin43858_BITS_56_TO_5_0b_ETC__q229 = - sfdin__h743858[56:5]; + CASE_guard44704_0b0_theResult___fst_exp52694_0_ETC__q227 = + _theResult___fst_exp__h752694; 2'b01, 2'b10, 2'b11: - CASE_guard35638_0b0_sfdin43858_BITS_56_TO_5_0b_ETC__q229 = - _theResult___sfd__h744594; + CASE_guard44704_0b0_theResult___fst_exp52694_0_ETC__q227 = + _theResult___exp__h753374; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h743858 or + _theResult___fst_exp__h752694 or + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13240 or + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13238 or + CASE_guard44704_0b0_theResult___fst_exp52694_0_ETC__q227) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd1: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13244 = + _theResult___fst_exp__h752694; + 3'd2: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13244 = + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13240; + 3'd3: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13244 = + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13238; + 3'd4: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13244 = + CASE_guard44704_0b0_theResult___fst_exp52694_0_ETC__q227; + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13244 = + 11'd0; + endcase + end + always@(guard__h744704 or + _theResult___fst_exp__h752694 or + out_exp__h753377 or _theResult___exp__h753374) + begin + case (guard__h744704) + 2'b0, 2'b01: + CASE_guard44704_0b0_theResult___fst_exp52694_0_ETC__q228 = + _theResult___fst_exp__h752694; + 2'b10: + CASE_guard44704_0b0_theResult___fst_exp52694_0_ETC__q228 = + out_exp__h753377; + 2'b11: + CASE_guard44704_0b0_theResult___fst_exp52694_0_ETC__q228 = + _theResult___exp__h753374; + endcase + end + always@(guard__h735635 or sfdin__h743855 or _theResult___sfd__h744591) + begin + case (guard__h735635) + 2'b0: + CASE_guard35635_0b0_sfdin43855_BITS_56_TO_5_0b_ETC__q229 = + sfdin__h743855[56:5]; + 2'b01, 2'b10, 2'b11: + CASE_guard35635_0b0_sfdin43855_BITS_56_TO_5_0b_ETC__q229 = + _theResult___sfd__h744591; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or + sfdin__h743855 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13293 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13291 or - CASE_guard35638_0b0_sfdin43858_BITS_56_TO_5_0b_ETC__q229) + CASE_guard35635_0b0_sfdin43855_BITS_56_TO_5_0b_ETC__q229) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13297 = - sfdin__h743858[56:5]; + sfdin__h743855[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13297 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13293; @@ -43072,48 +43061,48 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13291; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13297 = - CASE_guard35638_0b0_sfdin43858_BITS_56_TO_5_0b_ETC__q229; + CASE_guard35635_0b0_sfdin43855_BITS_56_TO_5_0b_ETC__q229; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13297 = 52'd0; endcase end - always@(guard__h735638 or - sfdin__h743858 or out_sfd__h744597 or _theResult___sfd__h744594) + always@(guard__h735635 or + sfdin__h743855 or out_sfd__h744594 or _theResult___sfd__h744591) begin - case (guard__h735638) + case (guard__h735635) 2'b0, 2'b01: - CASE_guard35638_0b0_sfdin43858_BITS_56_TO_5_0b_ETC__q230 = - sfdin__h743858[56:5]; + CASE_guard35635_0b0_sfdin43855_BITS_56_TO_5_0b_ETC__q230 = + sfdin__h743855[56:5]; 2'b10: - CASE_guard35638_0b0_sfdin43858_BITS_56_TO_5_0b_ETC__q230 = - out_sfd__h744597; + CASE_guard35635_0b0_sfdin43855_BITS_56_TO_5_0b_ETC__q230 = + out_sfd__h744594; 2'b11: - CASE_guard35638_0b0_sfdin43858_BITS_56_TO_5_0b_ETC__q230 = - _theResult___sfd__h744594; + CASE_guard35635_0b0_sfdin43855_BITS_56_TO_5_0b_ETC__q230 = + _theResult___sfd__h744591; endcase end - always@(guard__h744707 or - _theResult___snd__h752643 or _theResult___sfd__h753378) + always@(guard__h744704 or + _theResult___snd__h752640 or _theResult___sfd__h753375) begin - case (guard__h744707) + case (guard__h744704) 2'b0: - CASE_guard44707_0b0_theResult___snd52643_BITS__ETC__q231 = - _theResult___snd__h752643[56:5]; + CASE_guard44704_0b0_theResult___snd52640_BITS__ETC__q231 = + _theResult___snd__h752640[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard44707_0b0_theResult___snd52643_BITS__ETC__q231 = - _theResult___sfd__h753378; + CASE_guard44704_0b0_theResult___snd52640_BITS__ETC__q231 = + _theResult___sfd__h753375; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h752643 or + _theResult___snd__h752640 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13312 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13310 or - CASE_guard44707_0b0_theResult___snd52643_BITS__ETC__q231) + CASE_guard44704_0b0_theResult___snd52640_BITS__ETC__q231) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13316 = - _theResult___snd__h752643[56:5]; + _theResult___snd__h752640[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13316 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13312; @@ -43122,49 +43111,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13310; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13316 = - CASE_guard44707_0b0_theResult___snd52643_BITS__ETC__q231; + CASE_guard44704_0b0_theResult___snd52640_BITS__ETC__q231; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13316 = 52'd0; endcase end - always@(guard__h744707 or - _theResult___snd__h752643 or - out_sfd__h753381 or _theResult___sfd__h753378) + always@(guard__h744704 or + _theResult___snd__h752640 or + out_sfd__h753378 or _theResult___sfd__h753375) begin - case (guard__h744707) + case (guard__h744704) 2'b0, 2'b01: - CASE_guard44707_0b0_theResult___snd52643_BITS__ETC__q232 = - _theResult___snd__h752643[56:5]; + CASE_guard44704_0b0_theResult___snd52640_BITS__ETC__q232 = + _theResult___snd__h752640[56:5]; 2'b10: - CASE_guard44707_0b0_theResult___snd52643_BITS__ETC__q232 = - out_sfd__h753381; + CASE_guard44704_0b0_theResult___snd52640_BITS__ETC__q232 = + out_sfd__h753378; 2'b11: - CASE_guard44707_0b0_theResult___snd52643_BITS__ETC__q232 = - _theResult___sfd__h753378; + CASE_guard44704_0b0_theResult___snd52640_BITS__ETC__q232 = + _theResult___sfd__h753375; endcase end - always@(guard__h804483 or - _theResult___snd__h812395 or _theResult___sfd__h813100) + always@(guard__h804480 or + _theResult___snd__h812392 or _theResult___sfd__h813097) begin - case (guard__h804483) + case (guard__h804480) 2'b0: - CASE_guard04483_0b0_theResult___snd12395_BITS__ETC__q233 = - _theResult___snd__h812395[56:5]; + CASE_guard04480_0b0_theResult___snd12392_BITS__ETC__q233 = + _theResult___snd__h812392[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard04483_0b0_theResult___snd12395_BITS__ETC__q233 = - _theResult___sfd__h813100; + CASE_guard04480_0b0_theResult___snd12392_BITS__ETC__q233 = + _theResult___sfd__h813097; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h812395 or + _theResult___snd__h812392 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13976 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13974 or - CASE_guard04483_0b0_theResult___snd12395_BITS__ETC__q233) + CASE_guard04480_0b0_theResult___snd12392_BITS__ETC__q233) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13980 = - _theResult___snd__h812395[56:5]; + _theResult___snd__h812392[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13980 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13976; @@ -43173,48 +43162,48 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d13974; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13980 = - CASE_guard04483_0b0_theResult___snd12395_BITS__ETC__q233; + CASE_guard04480_0b0_theResult___snd12392_BITS__ETC__q233; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13980 = 52'd0; endcase end - always@(guard__h804483 or - _theResult___snd__h812395 or - out_sfd__h813103 or _theResult___sfd__h813100) + always@(guard__h804480 or + _theResult___snd__h812392 or + out_sfd__h813100 or _theResult___sfd__h813097) begin - case (guard__h804483) + case (guard__h804480) 2'b0, 2'b01: - CASE_guard04483_0b0_theResult___snd12395_BITS__ETC__q234 = - _theResult___snd__h812395[56:5]; + CASE_guard04480_0b0_theResult___snd12392_BITS__ETC__q234 = + _theResult___snd__h812392[56:5]; 2'b10: - CASE_guard04483_0b0_theResult___snd12395_BITS__ETC__q234 = - out_sfd__h813103; + CASE_guard04480_0b0_theResult___snd12392_BITS__ETC__q234 = + out_sfd__h813100; 2'b11: - CASE_guard04483_0b0_theResult___snd12395_BITS__ETC__q234 = - _theResult___sfd__h813100; + CASE_guard04480_0b0_theResult___snd12392_BITS__ETC__q234 = + _theResult___sfd__h813097; endcase end - always@(guard__h813795 or sfdin__h822015 or _theResult___sfd__h822751) + always@(guard__h813792 or sfdin__h822012 or _theResult___sfd__h822748) begin - case (guard__h813795) + case (guard__h813792) 2'b0: - CASE_guard13795_0b0_sfdin22015_BITS_56_TO_5_0b_ETC__q235 = - sfdin__h822015[56:5]; + CASE_guard13792_0b0_sfdin22012_BITS_56_TO_5_0b_ETC__q235 = + sfdin__h822012[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard13795_0b0_sfdin22015_BITS_56_TO_5_0b_ETC__q235 = - _theResult___sfd__h822751; + CASE_guard13792_0b0_sfdin22012_BITS_56_TO_5_0b_ETC__q235 = + _theResult___sfd__h822748; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h822015 or + sfdin__h822012 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14002 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14000 or - CASE_guard13795_0b0_sfdin22015_BITS_56_TO_5_0b_ETC__q235) + CASE_guard13792_0b0_sfdin22012_BITS_56_TO_5_0b_ETC__q235) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14006 = - sfdin__h822015[56:5]; + sfdin__h822012[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14006 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14002; @@ -43223,24 +43212,24 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14000; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14006 = - CASE_guard13795_0b0_sfdin22015_BITS_56_TO_5_0b_ETC__q235; + CASE_guard13792_0b0_sfdin22012_BITS_56_TO_5_0b_ETC__q235; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14006 = 52'd0; endcase end - always@(guard__h813795 or - sfdin__h822015 or out_sfd__h822754 or _theResult___sfd__h822751) + always@(guard__h813792 or + sfdin__h822012 or out_sfd__h822751 or _theResult___sfd__h822748) begin - case (guard__h813795) + case (guard__h813792) 2'b0, 2'b01: - CASE_guard13795_0b0_sfdin22015_BITS_56_TO_5_0b_ETC__q236 = - sfdin__h822015[56:5]; + CASE_guard13792_0b0_sfdin22012_BITS_56_TO_5_0b_ETC__q236 = + sfdin__h822012[56:5]; 2'b10: - CASE_guard13795_0b0_sfdin22015_BITS_56_TO_5_0b_ETC__q236 = - out_sfd__h822754; + CASE_guard13792_0b0_sfdin22012_BITS_56_TO_5_0b_ETC__q236 = + out_sfd__h822751; 2'b11: - CASE_guard13795_0b0_sfdin22015_BITS_56_TO_5_0b_ETC__q236 = - _theResult___sfd__h822751; + CASE_guard13792_0b0_sfdin22012_BITS_56_TO_5_0b_ETC__q236 = + _theResult___sfd__h822748; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or @@ -43275,28 +43264,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ_first__2522_B_ETC___d15003; endcase end - always@(guard__h822864 or - _theResult___snd__h830800 or _theResult___sfd__h831535) + always@(guard__h822861 or + _theResult___snd__h830797 or _theResult___sfd__h831532) begin - case (guard__h822864) + case (guard__h822861) 2'b0: - CASE_guard22864_0b0_theResult___snd30800_BITS__ETC__q237 = - _theResult___snd__h830800[56:5]; + CASE_guard22861_0b0_theResult___snd30797_BITS__ETC__q237 = + _theResult___snd__h830797[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard22864_0b0_theResult___snd30800_BITS__ETC__q237 = - _theResult___sfd__h831535; + CASE_guard22861_0b0_theResult___snd30797_BITS__ETC__q237 = + _theResult___sfd__h831532; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h830800 or + _theResult___snd__h830797 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14021 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14019 or - CASE_guard22864_0b0_theResult___snd30800_BITS__ETC__q237) + CASE_guard22861_0b0_theResult___snd30797_BITS__ETC__q237) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14025 = - _theResult___snd__h830800[56:5]; + _theResult___snd__h830797[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14025 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14021; @@ -43305,25 +43294,25 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d14019; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14025 = - CASE_guard22864_0b0_theResult___snd30800_BITS__ETC__q237; + CASE_guard22861_0b0_theResult___snd30797_BITS__ETC__q237; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14025 = 52'd0; endcase end - always@(guard__h822864 or - _theResult___snd__h830800 or - out_sfd__h831538 or _theResult___sfd__h831535) + always@(guard__h822861 or + _theResult___snd__h830797 or + out_sfd__h831535 or _theResult___sfd__h831532) begin - case (guard__h822864) + case (guard__h822861) 2'b0, 2'b01: - CASE_guard22864_0b0_theResult___snd30800_BITS__ETC__q238 = - _theResult___snd__h830800[56:5]; + CASE_guard22861_0b0_theResult___snd30797_BITS__ETC__q238 = + _theResult___snd__h830797[56:5]; 2'b10: - CASE_guard22864_0b0_theResult___snd30800_BITS__ETC__q238 = - out_sfd__h831538; + CASE_guard22861_0b0_theResult___snd30797_BITS__ETC__q238 = + out_sfd__h831535; 2'b11: - CASE_guard22864_0b0_theResult___snd30800_BITS__ETC__q238 = - _theResult___sfd__h831535; + CASE_guard22861_0b0_theResult___snd30797_BITS__ETC__q238 = + _theResult___sfd__h831532; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or @@ -43495,16 +43484,6 @@ module mkCore(CLK, endcase end always@(coreFix_aluExe_0_rsAlu$dispatchData) - begin - case (coreFix_aluExe_0_rsAlu$dispatchData[197:194]) - 4'd7, 4'd8, 4'd9, 4'd10, 4'd11: - IF_coreFix_aluExe_0_rsAlu_dispatchData__8084_B_ETC___d18143 = - coreFix_aluExe_0_rsAlu$dispatchData[197:194]; - default: IF_coreFix_aluExe_0_rsAlu_dispatchData__8084_B_ETC___d18143 = - 4'd12; - endcase - end - always@(coreFix_aluExe_0_rsAlu$dispatchData) begin case (coreFix_aluExe_0_rsAlu$dispatchData[193:191]) 3'd2, 3'd3: @@ -43514,6 +43493,16 @@ module mkCore(CLK, 3'd4; endcase end + always@(coreFix_aluExe_0_rsAlu$dispatchData) + begin + case (coreFix_aluExe_0_rsAlu$dispatchData[197:194]) + 4'd7, 4'd8, 4'd9, 4'd10, 4'd11: + IF_coreFix_aluExe_0_rsAlu_dispatchData__8084_B_ETC___d18143 = + coreFix_aluExe_0_rsAlu$dispatchData[197:194]; + default: IF_coreFix_aluExe_0_rsAlu_dispatchData__8084_B_ETC___d18143 = + 4'd12; + endcase + end always@(IF_coreFix_aluExe_0_rsAlu_dispatchData__8084_B_ETC___d18175) begin case (IF_coreFix_aluExe_0_rsAlu_dispatchData__8084_B_ETC___d18175) @@ -43875,10 +43864,10 @@ module mkCore(CLK, 4'd14; endcase end - always@(k__h945030 or + always@(k__h945028 or coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq) begin - case (k__h945030) + case (k__h945028) 1'd0: SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__119_ETC___d21202 = !coreFix_aluExe_0_rsAlu$canEnq; @@ -43898,10 +43887,10 @@ module mkCore(CLK, coreFix_memExe_lsq$enqStTag[6]; endcase end - always@(k__h945030 or + always@(k__h945028 or coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq) begin - case (k__h945030) + case (k__h945028) 1'd0: SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__1191_co_ETC___d21225 = coreFix_aluExe_0_rsAlu$canEnq; @@ -44118,7 +44107,7 @@ module mkCore(CLK, 11'd1194; endcase end - always@(idx__h968880 or + always@(idx__h968878 or fetchStage$pipelines_0_canDeq or NOT_fetchStage_pipelines_0_first__0256_BITS_26_ETC___d21652 or coreFix_aluExe_0_rsAlu$canEnq or @@ -44128,7 +44117,7 @@ module mkCore(CLK, fetchStage_pipelines_0_first__0256_BITS_268_TO_ETC___d21657 or coreFix_aluExe_1_rsAlu$canEnq) begin - case (idx__h968880) + case (idx__h968878) 1'd0: SEL_ARR_fetchStage_pipelines_0_canDeq__0254_AN_ETC___d21680 = fetchStage$pipelines_0_canDeq && @@ -44232,15 +44221,15 @@ module mkCore(CLK, regRenamingTable_rename_1_canRename__1286_AND__ETC___d21642; endcase end - always@(k__h945030 or + always@(k__h945028 or coreFix_aluExe_0_rsAlu$RDY_enq or coreFix_aluExe_1_rsAlu$RDY_enq) begin - case (k__h945030) + case (k__h945028) 1'd0: - CASE_k45030_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q268 = + CASE_k45028_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q268 = coreFix_aluExe_0_rsAlu$RDY_enq; 1'd1: - CASE_k45030_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q268 = + CASE_k45028_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q268 = coreFix_aluExe_1_rsAlu$RDY_enq; endcase end @@ -44258,7 +44247,7 @@ module mkCore(CLK, always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or IF_fetchStage_pipelines_0_first__0256_BITS_265_ETC___d21275 or - regRenamingTable_RDY_rename_0_getRename__1027__ETC___d21854 or + regRenamingTable_RDY_rename_0_getRename__1028__ETC___d21854 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq or coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_enq or regRenamingTable$RDY_rename_0_getRename) @@ -44273,10 +44262,10 @@ module mkCore(CLK, fetchStage$pipelines_0_first[268:266] != 3'd2 || !coreFix_memExe_rsMem$canEnq || IF_fetchStage_pipelines_0_first__0256_BITS_265_ETC___d21275 || - regRenamingTable_RDY_rename_0_getRename__1027__ETC___d21854; + regRenamingTable_RDY_rename_0_getRename__1028__ETC___d21854; endcase end - always@(idx__h968880 or + always@(idx__h968878 or fetchStage$pipelines_0_canDeq or fetchStage$pipelines_0_first or specTagManager$canClaim or @@ -44286,7 +44275,7 @@ module mkCore(CLK, NOT_fetchStage_pipelines_0_first__0256_BITS_26_ETC___d21911 or coreFix_aluExe_1_rsAlu$canEnq) begin - case (idx__h968880) + case (idx__h968878) 1'd0: SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__025_ETC___d21916 = (!fetchStage$pipelines_0_canDeq || @@ -44493,102 +44482,134 @@ module mkCore(CLK, csrf_rg_dcsr[12]; endcase end + always@(commitStage_commitTrap or + _0b0_CONCAT_csrf_mideleg_11_reg_read__6172_6173_ETC___d22645 or + csrf_medeleg_28_26_reg or + _0b0_CONCAT_csrf_medeleg_28_26_reg_read__6161_6_ETC___d22642) + begin + case (commitStage_commitTrap[44:43]) + 2'd0: + CASE_commitStage_commitTrap_BITS_44_TO_43_0_cs_ETC__q276 = + csrf_medeleg_28_26_reg[2]; + 2'd1: + CASE_commitStage_commitTrap_BITS_44_TO_43_0_cs_ETC__q276 = + _0b0_CONCAT_csrf_medeleg_28_26_reg_read__6161_6_ETC___d22642; + default: CASE_commitStage_commitTrap_BITS_44_TO_43_0_cs_ETC__q276 = + _0b0_CONCAT_csrf_mideleg_11_reg_read__6172_6173_ETC___d22645; + endcase + end + always@(commitStage_commitTrap or + _0b0_CONCAT_csrf_mideleg_11_reg_read__6172_6173_ETC___d22645 or + csrf_medeleg_28_26_reg or + _0b0_CONCAT_csrf_medeleg_28_26_reg_read__6161_6_ETC___d22642) + begin + case (commitStage_commitTrap[44:43]) + 2'd0: + CASE_commitStage_commitTrap_BITS_44_TO_43_0_NO_ETC__q277 = + !csrf_medeleg_28_26_reg[2]; + 2'd1: + CASE_commitStage_commitTrap_BITS_44_TO_43_0_NO_ETC__q277 = + !_0b0_CONCAT_csrf_medeleg_28_26_reg_read__6161_6_ETC___d22642; + default: CASE_commitStage_commitTrap_BITS_44_TO_43_0_NO_ETC__q277 = + !_0b0_CONCAT_csrf_mideleg_11_reg_read__6172_6173_ETC___d22645; + endcase + end always@(rob$deqPort_0_deq_data) begin case (rob$deqPort_0_deq_data[287:276]) 12'd1: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd0; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd0; 12'd2: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd1; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd1; 12'd3: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd2; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd2; 12'd256: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd8; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd8; 12'd260: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd9; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd9; 12'd261: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd10; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd10; 12'd262: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd11; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd11; 12'd320: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd12; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd12; 12'd321: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd13; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd13; 12'd322: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd14; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd14; 12'd323: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd15; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd15; 12'd324: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd16; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd16; 12'd384: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd17; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd17; 12'd768: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd19; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd19; 12'd769: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd20; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd20; 12'd770: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd21; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd21; 12'd771: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd22; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd22; 12'd772: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd23; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd23; 12'd773: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd24; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd24; 12'd774: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd25; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd25; 12'd832: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd26; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd26; 12'd833: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd27; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd27; 12'd834: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd28; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd28; 12'd835: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd29; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd29; 12'd836: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd30; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd30; 12'd1952: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd38; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd38; 12'd1953: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd39; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd39; 12'd1954: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd40; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd40; 12'd1955: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd41; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd41; 12'd1968: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd42; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd42; 12'd1969: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd43; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd43; 12'd1970: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd44; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd44; 12'd1971: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd45; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd45; 12'd2048: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd6; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd6; 12'd2049: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd7; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd7; 12'd2496: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd18; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd18; 12'd2816: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd31; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd31; 12'd2818: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd32; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd32; 12'd3008: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd37; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd37; 12'd3072: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd3; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd3; 12'd3073: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd4; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd4; 12'd3074: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd5; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd5; 12'd3857: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd33; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd33; 12'd3858: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd34; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd34; 12'd3859: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd35; + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd35; 12'd3860: - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = 6'd36; - default: IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 = + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd36; + default: IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 = 6'd46; endcase end @@ -44596,26 +44617,26 @@ module mkCore(CLK, begin case (rob$deqPort_0_deq_data[293:289]) 5'd0: - IF_rob_deqPort_0_deq_data__2261_BIT_294_3454_T_ETC___d23476 = 4'd0; + IF_rob_deqPort_0_deq_data__2261_BIT_294_3456_T_ETC___d23478 = 4'd0; 5'd1: - IF_rob_deqPort_0_deq_data__2261_BIT_294_3454_T_ETC___d23476 = 4'd1; + IF_rob_deqPort_0_deq_data__2261_BIT_294_3456_T_ETC___d23478 = 4'd1; 5'd12: - IF_rob_deqPort_0_deq_data__2261_BIT_294_3454_T_ETC___d23476 = 4'd2; + IF_rob_deqPort_0_deq_data__2261_BIT_294_3456_T_ETC___d23478 = 4'd2; 5'd13: - IF_rob_deqPort_0_deq_data__2261_BIT_294_3454_T_ETC___d23476 = 4'd3; + IF_rob_deqPort_0_deq_data__2261_BIT_294_3456_T_ETC___d23478 = 4'd3; 5'd14: - IF_rob_deqPort_0_deq_data__2261_BIT_294_3454_T_ETC___d23476 = 4'd4; + IF_rob_deqPort_0_deq_data__2261_BIT_294_3456_T_ETC___d23478 = 4'd4; 5'd15: - IF_rob_deqPort_0_deq_data__2261_BIT_294_3454_T_ETC___d23476 = 4'd5; + IF_rob_deqPort_0_deq_data__2261_BIT_294_3456_T_ETC___d23478 = 4'd5; 5'd28: - IF_rob_deqPort_0_deq_data__2261_BIT_294_3454_T_ETC___d23476 = 4'd6; + IF_rob_deqPort_0_deq_data__2261_BIT_294_3456_T_ETC___d23478 = 4'd6; 5'd29: - IF_rob_deqPort_0_deq_data__2261_BIT_294_3454_T_ETC___d23476 = 4'd7; + IF_rob_deqPort_0_deq_data__2261_BIT_294_3456_T_ETC___d23478 = 4'd7; 5'd30: - IF_rob_deqPort_0_deq_data__2261_BIT_294_3454_T_ETC___d23476 = 4'd8; + IF_rob_deqPort_0_deq_data__2261_BIT_294_3456_T_ETC___d23478 = 4'd8; 5'd31: - IF_rob_deqPort_0_deq_data__2261_BIT_294_3454_T_ETC___d23476 = 4'd9; - default: IF_rob_deqPort_0_deq_data__2261_BIT_294_3454_T_ETC___d23476 = + IF_rob_deqPort_0_deq_data__2261_BIT_294_3456_T_ETC___d23478 = 4'd9; + default: IF_rob_deqPort_0_deq_data__2261_BIT_294_3456_T_ETC___d23478 = 4'd10; endcase end @@ -44623,8 +44644,8 @@ module mkCore(CLK, begin case (csrf_sepcc_reg_data_rl[52:35]) 18'd262142, 18'd262143: - CASE_csrf_sepcc_reg_data_rl_BITS_52_TO_35_2621_ETC__q276 = 18'd0; - default: CASE_csrf_sepcc_reg_data_rl_BITS_52_TO_35_2621_ETC__q276 = + CASE_csrf_sepcc_reg_data_rl_BITS_52_TO_35_2621_ETC__q278 = 18'd0; + default: CASE_csrf_sepcc_reg_data_rl_BITS_52_TO_35_2621_ETC__q278 = ~csrf_sepcc_reg_data_rl[52:35]; endcase end @@ -44632,8 +44653,8 @@ module mkCore(CLK, begin case (csrf_mepcc_reg_data_rl[52:35]) 18'd262142, 18'd262143: - CASE_csrf_mepcc_reg_data_rl_BITS_52_TO_35_2621_ETC__q277 = 18'd0; - default: CASE_csrf_mepcc_reg_data_rl_BITS_52_TO_35_2621_ETC__q277 = + CASE_csrf_mepcc_reg_data_rl_BITS_52_TO_35_2621_ETC__q279 = 18'd0; + default: CASE_csrf_mepcc_reg_data_rl_BITS_52_TO_35_2621_ETC__q279 = ~csrf_mepcc_reg_data_rl[52:35]; endcase end @@ -44643,10 +44664,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q278 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q280 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[515]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q278 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q280 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[515]; endcase end @@ -44656,10 +44677,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q279 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q281 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[514]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q279 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q281 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[514]; endcase end @@ -44669,10 +44690,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q280 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q282 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[513]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q280 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q282 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[513]; endcase end @@ -44726,19 +44747,6 @@ module mkCore(CLK, coreFix_memExe_forwardQ_data_1[63:0]; endcase end - always@(commitStage_commitTrap or - SEXT__0_CONCAT_IF_INV_commitStage_commitTrap_2_ETC___d22677) - begin - case (commitStage_commitTrap[36:32]) - 5'd0, 5'd3: - trap_val__h996887 = - SEXT__0_CONCAT_IF_INV_commitStage_commitTrap_2_ETC___d22677; - 5'd1, 5'd4, 5'd5, 5'd6, 5'd7, 5'd12, 5'd13, 5'd15: - trap_val__h996887 = commitStage_commitTrap[108:45]; - 5'd2: trap_val__h996887 = { 32'd0, commitStage_commitTrap[31:0] }; - default: trap_val__h996887 = 64'd0; - endcase - end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) @@ -44757,6 +44765,19 @@ module mkCore(CLK, 3'd0; endcase end + always@(commitStage_commitTrap or + SEXT__0_CONCAT_IF_INV_commitStage_commitTrap_2_ETC___d22678) + begin + case (commitStage_commitTrap[36:32]) + 5'd0, 5'd3: + trap_val__h996922 = + SEXT__0_CONCAT_IF_INV_commitStage_commitTrap_2_ETC___d22678; + 5'd1, 5'd4, 5'd5, 5'd6, 5'd7, 5'd12, 5'd13, 5'd15: + trap_val__h996922 = commitStage_commitTrap[108:45]; + 5'd2: trap_val__h996922 = { 32'd0, commitStage_commitTrap[31:0] }; + default: trap_val__h996922 = 64'd0; + endcase + end always@(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq or coreFix_memExe_dMem_cache_m_banks_0_pipeline$first or coreFix_memExe_stb$deq or @@ -44987,35 +45008,35 @@ module mkCore(CLK, begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd4, 3'd3, 3'd2, 3'd1, 3'd0: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q281 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q283 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q281 = 3'd7; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q283 = 3'd7; endcase end always@(coreFix_aluExe_1_regToExeQ$first) begin case (coreFix_aluExe_1_regToExeQ$first[791:789]) 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_791_ETC__q282 = + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_791_ETC__q284 = coreFix_aluExe_1_regToExeQ$first[791:789]; - default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_791_ETC__q282 = 3'd7; + default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_791_ETC__q284 = 3'd7; endcase end always@(coreFix_aluExe_1_regToExeQ$first or - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_791_ETC__q282) + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_791_ETC__q284) begin case (coreFix_aluExe_1_regToExeQ$first[817:815]) 3'd0, 3'd1, 3'd2, 3'd3: - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_817_ETC__q283 = + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_817_ETC__q285 = coreFix_aluExe_1_regToExeQ$first[817:788]; 3'd4: - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_817_ETC__q283 = + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_817_ETC__q285 = { coreFix_aluExe_1_regToExeQ$first[817:815], 18'h2AAAA, coreFix_aluExe_1_regToExeQ$first[796:792], - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_791_ETC__q282, + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_791_ETC__q284, coreFix_aluExe_1_regToExeQ$first[788] }; - default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_817_ETC__q283 = + default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_817_ETC__q285 = 30'd715827882; endcase end @@ -45024,13 +45045,13 @@ module mkCore(CLK, begin case (coreFix_aluExe_1_regToExeQ$first[787:786]) 2'd0: - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_787_ETC__q284 = + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_787_ETC__q286 = coreFix_aluExe_1_regToExeQ$first[787:777]; 2'd1: - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_787_ETC__q284 = + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_787_ETC__q286 = { coreFix_aluExe_1_regToExeQ$first[787:786], IF_coreFix_aluExe_1_regToExeQ_first__7341_BITS_ETC___d17481 }; - default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_787_ETC__q284 = + default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_787_ETC__q286 = 11'd1194; endcase end @@ -45083,9 +45104,9 @@ module mkCore(CLK, 12'd3858, 12'd3859, 12'd3860: - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_728_ETC__q285 = + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_728_ETC__q287 = coreFix_aluExe_1_regToExeQ$first[728:717]; - default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_728_ETC__q285 = + default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_728_ETC__q287 = 12'd2303; endcase end @@ -45093,9 +45114,9 @@ module mkCore(CLK, begin case (coreFix_aluExe_1_regToExeQ$first[715:711]) 5'd0, 5'd1, 5'd12, 5'd13, 5'd14, 5'd15, 5'd28, 5'd29, 5'd30, 5'd31: - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_715_ETC__q286 = + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_715_ETC__q288 = coreFix_aluExe_1_regToExeQ$first[715:711]; - default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_715_ETC__q286 = + default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_715_ETC__q288 = 5'd10; endcase end @@ -45103,26 +45124,26 @@ module mkCore(CLK, begin case (coreFix_aluExe_0_regToExeQ$first[791:789]) 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_791_ETC__q287 = + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_791_ETC__q289 = coreFix_aluExe_0_regToExeQ$first[791:789]; - default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_791_ETC__q287 = 3'd7; + default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_791_ETC__q289 = 3'd7; endcase end always@(coreFix_aluExe_0_regToExeQ$first or - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_791_ETC__q287) + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_791_ETC__q289) begin case (coreFix_aluExe_0_regToExeQ$first[817:815]) 3'd0, 3'd1, 3'd2, 3'd3: - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_817_ETC__q288 = + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_817_ETC__q290 = coreFix_aluExe_0_regToExeQ$first[817:788]; 3'd4: - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_817_ETC__q288 = + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_817_ETC__q290 = { coreFix_aluExe_0_regToExeQ$first[817:815], 18'h2AAAA, coreFix_aluExe_0_regToExeQ$first[796:792], - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_791_ETC__q287, + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_791_ETC__q289, coreFix_aluExe_0_regToExeQ$first[788] }; - default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_817_ETC__q288 = + default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_817_ETC__q290 = 30'd715827882; endcase end @@ -45131,13 +45152,13 @@ module mkCore(CLK, begin case (coreFix_aluExe_0_regToExeQ$first[787:786]) 2'd0: - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_787_ETC__q289 = + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_787_ETC__q291 = coreFix_aluExe_0_regToExeQ$first[787:777]; 2'd1: - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_787_ETC__q289 = + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_787_ETC__q291 = { coreFix_aluExe_0_regToExeQ$first[787:786], IF_coreFix_aluExe_0_regToExeQ_first__9457_BITS_ETC___d19597 }; - default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_787_ETC__q289 = + default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_787_ETC__q291 = 11'd1194; endcase end @@ -45190,9 +45211,9 @@ module mkCore(CLK, 12'd3858, 12'd3859, 12'd3860: - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_728_ETC__q290 = + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_728_ETC__q292 = coreFix_aluExe_0_regToExeQ$first[728:717]; - default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_728_ETC__q290 = + default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_728_ETC__q292 = 12'd2303; endcase end @@ -45200,9 +45221,9 @@ module mkCore(CLK, begin case (coreFix_aluExe_0_regToExeQ$first[715:711]) 5'd0, 5'd1, 5'd12, 5'd13, 5'd14, 5'd15, 5'd28, 5'd29, 5'd30, 5'd31: - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_715_ETC__q291 = + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_715_ETC__q293 = coreFix_aluExe_0_regToExeQ$first[715:711]; - default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_715_ETC__q291 = + default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_715_ETC__q293 = 5'd10; endcase end @@ -45269,9 +45290,9 @@ module mkCore(CLK, 5'd24, 5'd25, 5'd26: - CASE_capChecks_160_BITS_4_TO_0_0_capChecks_160_ETC__q292 = + CASE_capChecks_160_BITS_4_TO_0_0_capChecks_160_ETC__q294 = capChecks___d4160[4:0]; - default: CASE_capChecks_160_BITS_4_TO_0_0_capChecks_160_ETC__q292 = + default: CASE_capChecks_160_BITS_4_TO_0_0_capChecks_160_ETC__q294 = 5'd27; endcase end @@ -45281,10 +45302,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q293 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q295 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[514:451]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q293 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q295 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[514:451]; endcase end @@ -45294,10 +45315,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q294 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q296 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[450:387]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q294 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q296 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[450:387]; endcase end @@ -45307,10 +45328,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q295 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q297 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[386:323]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q295 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q297 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[386:323]; endcase end @@ -45320,10 +45341,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q296 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q298 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[322:259]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q296 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q298 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[322:259]; endcase end @@ -45333,10 +45354,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q297 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q299 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[258:195]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q297 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q299 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[258:195]; endcase end @@ -45346,10 +45367,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q298 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q300 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[194:131]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q298 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q300 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[194:131]; endcase end @@ -45359,10 +45380,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q299 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q301 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[511:448]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q299 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q301 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[511:448]; endcase end @@ -45372,10 +45393,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q300 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q302 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[447:384]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q300 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q302 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[447:384]; endcase end @@ -45385,10 +45406,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q301 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q303 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[383:320]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q301 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q303 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[383:320]; endcase end @@ -45398,10 +45419,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q302 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q304 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[319:256]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q302 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q304 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[319:256]; endcase end @@ -45411,10 +45432,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q303 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q305 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[255:192]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q303 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q305 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[255:192]; endcase end @@ -45424,10 +45445,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q304 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q306 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[191:128]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q304 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q306 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[191:128]; endcase end @@ -45437,10 +45458,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q305 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q307 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[515]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q305 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q307 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[515]; endcase end @@ -45450,10 +45471,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q306 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q308 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[130:67]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q306 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q308 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[130:67]; endcase end @@ -45463,10 +45484,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q307 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q309 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[66:3]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q307 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q309 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[66:3]; endcase end @@ -45476,10 +45497,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q308 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q310 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[512]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q308 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q310 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[512]; endcase end @@ -45489,10 +45510,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q309 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q311 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[127:64]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q309 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q311 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[127:64]; endcase end @@ -45502,10 +45523,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q310 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q312 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[63:0]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q310 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q312 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[63:0]; endcase end @@ -45515,10 +45536,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q311 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q313 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[582:519]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q311 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q313 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[582:519]; endcase end @@ -45528,10 +45549,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q312 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q314 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[518:517]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q312 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q314 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[518:517]; endcase end @@ -45541,10 +45562,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q313 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q315 = !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[516]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q313 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q315 = !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[516]; endcase end @@ -45554,10 +45575,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q314 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q316 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[521:520]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q314 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q316 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[521:520]; endcase end @@ -45567,10 +45588,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q315 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q317 = !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[519]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q315 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q317 = !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[519]; endcase end @@ -45622,10 +45643,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q316 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q318 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[5:4]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q316 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q318 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[5:4]; endcase end @@ -45635,10 +45656,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q317 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q319 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[3]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q317 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q319 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[3]; endcase end @@ -45648,10 +45669,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q318 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q320 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[2:0]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q318 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q320 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[2:0]; endcase end @@ -45661,10 +45682,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q319 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q321 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[71:8]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q319 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q321 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[71:8]; endcase end @@ -45674,10 +45695,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q320 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q322 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[7:6]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q320 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q322 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[7:6]; endcase end @@ -45687,10 +45708,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q321 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q323 = !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[586]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q321 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q323 = !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[586]; endcase end @@ -45700,10 +45721,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q322 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q324 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[586]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q322 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q324 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[586]; endcase end @@ -45711,9 +45732,9 @@ module mkCore(CLK, begin case (rob$deqPort_0_deq_data[264:261]) 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: - CASE_robdeqPort_0_deq_data_BITS_264_TO_261_0__ETC__q323 = + CASE_robdeqPort_0_deq_data_BITS_264_TO_261_0__ETC__q325 = rob$deqPort_0_deq_data[264:261]; - default: CASE_robdeqPort_0_deq_data_BITS_264_TO_261_0__ETC__q323 = + default: CASE_robdeqPort_0_deq_data_BITS_264_TO_261_0__ETC__q325 = 4'd15; endcase end @@ -45743,9 +45764,9 @@ module mkCore(CLK, 5'd24, 5'd25, 5'd26: - CASE_robdeqPort_0_deq_data_BITS_265_TO_261_0__ETC__q324 = + CASE_robdeqPort_0_deq_data_BITS_265_TO_261_0__ETC__q326 = rob$deqPort_0_deq_data[265:261]; - default: CASE_robdeqPort_0_deq_data_BITS_265_TO_261_0__ETC__q324 = + default: CASE_robdeqPort_0_deq_data_BITS_265_TO_261_0__ETC__q326 = 5'd27; endcase end @@ -45766,31 +45787,43 @@ module mkCore(CLK, 5'd12, 5'd13, 5'd15: - CASE_robdeqPort_0_deq_data_BITS_265_TO_261_0__ETC__q325 = + CASE_robdeqPort_0_deq_data_BITS_265_TO_261_0__ETC__q327 = rob$deqPort_0_deq_data[265:261]; - default: CASE_robdeqPort_0_deq_data_BITS_265_TO_261_0__ETC__q325 = + default: CASE_robdeqPort_0_deq_data_BITS_265_TO_261_0__ETC__q327 = 5'd28; endcase end always@(rob$deqPort_0_deq_data or - CASE_robdeqPort_0_deq_data_BITS_264_TO_261_0__ETC__q323 or - CASE_robdeqPort_0_deq_data_BITS_265_TO_261_0__ETC__q324 or - CASE_robdeqPort_0_deq_data_BITS_265_TO_261_0__ETC__q325) + CASE_robdeqPort_0_deq_data_BITS_264_TO_261_0__ETC__q325 or + CASE_robdeqPort_0_deq_data_BITS_265_TO_261_0__ETC__q326 or + CASE_robdeqPort_0_deq_data_BITS_265_TO_261_0__ETC__q327) begin case (rob$deqPort_0_deq_data[273:272]) 2'd0: - CASE_robdeqPort_0_deq_data_BITS_273_TO_272_0__ETC__q326 = + CASE_robdeqPort_0_deq_data_BITS_273_TO_272_0__ETC__q328 = { 2'd0, rob$deqPort_0_deq_data[271:266], - CASE_robdeqPort_0_deq_data_BITS_265_TO_261_0__ETC__q324 }; + CASE_robdeqPort_0_deq_data_BITS_265_TO_261_0__ETC__q326 }; 2'd1: - CASE_robdeqPort_0_deq_data_BITS_273_TO_272_0__ETC__q326 = + CASE_robdeqPort_0_deq_data_BITS_273_TO_272_0__ETC__q328 = { rob$deqPort_0_deq_data[273:272], 6'h2A, - CASE_robdeqPort_0_deq_data_BITS_265_TO_261_0__ETC__q325 }; - default: CASE_robdeqPort_0_deq_data_BITS_273_TO_272_0__ETC__q326 = + CASE_robdeqPort_0_deq_data_BITS_265_TO_261_0__ETC__q327 }; + default: CASE_robdeqPort_0_deq_data_BITS_273_TO_272_0__ETC__q328 = { 9'd298, - CASE_robdeqPort_0_deq_data_BITS_264_TO_261_0__ETC__q323 }; + CASE_robdeqPort_0_deq_data_BITS_264_TO_261_0__ETC__q325 }; + endcase + end + always@(coreFix_memExe_forwardQ_deqP or + coreFix_memExe_forwardQ_data_0 or coreFix_memExe_forwardQ_data_1) + begin + case (coreFix_memExe_forwardQ_deqP) + 1'd0: + CASE_coreFix_memExe_forwardQ_deqP_0_coreFix_me_ETC__q329 = + coreFix_memExe_forwardQ_data_0[128]; + 1'd1: + CASE_coreFix_memExe_forwardQ_deqP_0_coreFix_me_ETC__q329 = + coreFix_memExe_forwardQ_data_1[128]; endcase end always@(coreFix_memExe_memRespLdQ_deqP or @@ -45799,25 +45832,13 @@ module mkCore(CLK, begin case (coreFix_memExe_memRespLdQ_deqP) 1'd0: - CASE_coreFix_memExe_memRespLdQ_deqP_0_coreFix__ETC__q327 = + CASE_coreFix_memExe_memRespLdQ_deqP_0_coreFix__ETC__q330 = coreFix_memExe_memRespLdQ_data_0[128]; 1'd1: - CASE_coreFix_memExe_memRespLdQ_deqP_0_coreFix__ETC__q327 = + CASE_coreFix_memExe_memRespLdQ_deqP_0_coreFix__ETC__q330 = coreFix_memExe_memRespLdQ_data_1[128]; endcase end - always@(coreFix_memExe_forwardQ_deqP or - coreFix_memExe_forwardQ_data_0 or coreFix_memExe_forwardQ_data_1) - begin - case (coreFix_memExe_forwardQ_deqP) - 1'd0: - CASE_coreFix_memExe_forwardQ_deqP_0_coreFix_me_ETC__q328 = - coreFix_memExe_forwardQ_data_0[128]; - 1'd1: - CASE_coreFix_memExe_forwardQ_deqP_0_coreFix_me_ETC__q328 = - coreFix_memExe_forwardQ_data_1[128]; - endcase - end always@(f_csr_reqs$D_OUT) begin case (f_csr_reqs$D_OUT[9:5]) @@ -45844,15 +45865,15 @@ module mkCore(CLK, 5'd24, 5'd25, 5'd26: - CASE_f_csr_reqsD_OUT_BITS_9_TO_5_0_f_csr_reqs_ETC__q329 = + CASE_f_csr_reqsD_OUT_BITS_9_TO_5_0_f_csr_reqs_ETC__q331 = f_csr_reqs$D_OUT[9:5]; - default: CASE_f_csr_reqsD_OUT_BITS_9_TO_5_0_f_csr_reqs_ETC__q329 = + default: CASE_f_csr_reqsD_OUT_BITS_9_TO_5_0_f_csr_reqs_ETC__q331 = 5'd27; endcase end - always@(robdeqPort_0_deq_data_BITS_95_TO_32__q16) + always@(robdeqPort_0_deq_data_BITS_95_TO_32__q17) begin - case (robdeqPort_0_deq_data_BITS_95_TO_32__q16[9:5]) + case (robdeqPort_0_deq_data_BITS_95_TO_32__q17[9:5]) 5'd0, 5'd1, 5'd2, @@ -45876,9 +45897,9 @@ module mkCore(CLK, 5'd24, 5'd25, 5'd26: - CASE_robdeqPort_0_deq_data_BITS_95_TO_326_BITS_ETC__q330 = - robdeqPort_0_deq_data_BITS_95_TO_32__q16[9:5]; - default: CASE_robdeqPort_0_deq_data_BITS_95_TO_326_BITS_ETC__q330 = + CASE_robdeqPort_0_deq_data_BITS_95_TO_327_BITS_ETC__q332 = + robdeqPort_0_deq_data_BITS_95_TO_32__q17[9:5]; + default: CASE_robdeqPort_0_deq_data_BITS_95_TO_327_BITS_ETC__q332 = 5'd27; endcase end @@ -45892,17 +45913,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[123:119]) - 5'd1: thin_addrBits__h858474 = csrf_ddc_reg[85:72]; - 5'd12: thin_addrBits__h858474 = csrf_stcc_reg[85:72]; - 5'd13: thin_addrBits__h858474 = csrf_stdc_reg[85:72]; - 5'd14: thin_addrBits__h858474 = csrf_sScratchC_reg[85:72]; + 5'd1: thin_addrBits__h858473 = csrf_ddc_reg[85:72]; + 5'd12: thin_addrBits__h858473 = csrf_stcc_reg[85:72]; + 5'd13: thin_addrBits__h858473 = csrf_stdc_reg[85:72]; + 5'd14: thin_addrBits__h858473 = csrf_sScratchC_reg[85:72]; 5'd15: - thin_addrBits__h858474 = + thin_addrBits__h858473 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16080; - 5'd28: thin_addrBits__h858474 = csrf_mtcc_reg[85:72]; - 5'd29: thin_addrBits__h858474 = csrf_mtdc_reg[85:72]; - 5'd30: thin_addrBits__h858474 = csrf_mScratchC_reg[85:72]; - default: thin_addrBits__h858474 = + 5'd28: thin_addrBits__h858473 = csrf_mtcc_reg[85:72]; + 5'd29: thin_addrBits__h858473 = csrf_mtdc_reg[85:72]; + 5'd30: thin_addrBits__h858473 = csrf_mScratchC_reg[85:72]; + default: thin_addrBits__h858473 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16232; endcase end @@ -45916,17 +45937,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[123:119]) - 5'd1: thin_addrBits__h899110 = csrf_ddc_reg[85:72]; - 5'd12: thin_addrBits__h899110 = csrf_stcc_reg[85:72]; - 5'd13: thin_addrBits__h899110 = csrf_stdc_reg[85:72]; - 5'd14: thin_addrBits__h899110 = csrf_sScratchC_reg[85:72]; + 5'd1: thin_addrBits__h899108 = csrf_ddc_reg[85:72]; + 5'd12: thin_addrBits__h899108 = csrf_stcc_reg[85:72]; + 5'd13: thin_addrBits__h899108 = csrf_stdc_reg[85:72]; + 5'd14: thin_addrBits__h899108 = csrf_sScratchC_reg[85:72]; 5'd15: - thin_addrBits__h899110 = + thin_addrBits__h899108 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16080; - 5'd28: thin_addrBits__h899110 = csrf_mtcc_reg[85:72]; - 5'd29: thin_addrBits__h899110 = csrf_mtdc_reg[85:72]; - 5'd30: thin_addrBits__h899110 = csrf_mScratchC_reg[85:72]; - default: thin_addrBits__h899110 = + 5'd28: thin_addrBits__h899108 = csrf_mtcc_reg[85:72]; + 5'd29: thin_addrBits__h899108 = csrf_mtdc_reg[85:72]; + 5'd30: thin_addrBits__h899108 = csrf_mScratchC_reg[85:72]; + default: thin_addrBits__h899108 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16232; endcase end @@ -45940,17 +45961,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[123:119]) - 5'd1: thin_bounds_baseBits__h860422 = csrf_ddc_reg[13:0]; - 5'd12: thin_bounds_baseBits__h860422 = csrf_stcc_reg[13:0]; - 5'd13: thin_bounds_baseBits__h860422 = csrf_stdc_reg[13:0]; - 5'd14: thin_bounds_baseBits__h860422 = csrf_sScratchC_reg[13:0]; + 5'd1: thin_bounds_baseBits__h860421 = csrf_ddc_reg[13:0]; + 5'd12: thin_bounds_baseBits__h860421 = csrf_stcc_reg[13:0]; + 5'd13: thin_bounds_baseBits__h860421 = csrf_stdc_reg[13:0]; + 5'd14: thin_bounds_baseBits__h860421 = csrf_sScratchC_reg[13:0]; 5'd15: - thin_bounds_baseBits__h860422 = + thin_bounds_baseBits__h860421 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16084; - 5'd28: thin_bounds_baseBits__h860422 = csrf_mtcc_reg[13:0]; - 5'd29: thin_bounds_baseBits__h860422 = csrf_mtdc_reg[13:0]; - 5'd30: thin_bounds_baseBits__h860422 = csrf_mScratchC_reg[13:0]; - default: thin_bounds_baseBits__h860422 = + 5'd28: thin_bounds_baseBits__h860421 = csrf_mtcc_reg[13:0]; + 5'd29: thin_bounds_baseBits__h860421 = csrf_mtdc_reg[13:0]; + 5'd30: thin_bounds_baseBits__h860421 = csrf_mScratchC_reg[13:0]; + default: thin_bounds_baseBits__h860421 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16236; endcase end @@ -45964,17 +45985,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[123:119]) - 5'd1: thin_bounds_baseBits__h900516 = csrf_ddc_reg[13:0]; - 5'd12: thin_bounds_baseBits__h900516 = csrf_stcc_reg[13:0]; - 5'd13: thin_bounds_baseBits__h900516 = csrf_stdc_reg[13:0]; - 5'd14: thin_bounds_baseBits__h900516 = csrf_sScratchC_reg[13:0]; + 5'd1: thin_bounds_baseBits__h900514 = csrf_ddc_reg[13:0]; + 5'd12: thin_bounds_baseBits__h900514 = csrf_stcc_reg[13:0]; + 5'd13: thin_bounds_baseBits__h900514 = csrf_stdc_reg[13:0]; + 5'd14: thin_bounds_baseBits__h900514 = csrf_sScratchC_reg[13:0]; 5'd15: - thin_bounds_baseBits__h900516 = + thin_bounds_baseBits__h900514 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16084; - 5'd28: thin_bounds_baseBits__h900516 = csrf_mtcc_reg[13:0]; - 5'd29: thin_bounds_baseBits__h900516 = csrf_mtdc_reg[13:0]; - 5'd30: thin_bounds_baseBits__h900516 = csrf_mScratchC_reg[13:0]; - default: thin_bounds_baseBits__h900516 = + 5'd28: thin_bounds_baseBits__h900514 = csrf_mtcc_reg[13:0]; + 5'd29: thin_bounds_baseBits__h900514 = csrf_mtdc_reg[13:0]; + 5'd30: thin_bounds_baseBits__h900514 = csrf_mScratchC_reg[13:0]; + default: thin_bounds_baseBits__h900514 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16236; endcase end @@ -45988,17 +46009,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[123:119]) - 5'd1: thin_address__h858473 = csrf_ddc_reg[151:86]; - 5'd12: thin_address__h858473 = csrf_stcc_reg[151:86]; - 5'd13: thin_address__h858473 = csrf_stdc_reg[151:86]; - 5'd14: thin_address__h858473 = csrf_sScratchC_reg[151:86]; + 5'd1: thin_address__h858472 = csrf_ddc_reg[151:86]; + 5'd12: thin_address__h858472 = csrf_stcc_reg[151:86]; + 5'd13: thin_address__h858472 = csrf_stdc_reg[151:86]; + 5'd14: thin_address__h858472 = csrf_sScratchC_reg[151:86]; 5'd15: - thin_address__h858473 = + thin_address__h858472 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16104; - 5'd28: thin_address__h858473 = csrf_mtcc_reg[151:86]; - 5'd29: thin_address__h858473 = csrf_mtdc_reg[151:86]; - 5'd30: thin_address__h858473 = csrf_mScratchC_reg[151:86]; - default: thin_address__h858473 = + 5'd28: thin_address__h858472 = csrf_mtcc_reg[151:86]; + 5'd29: thin_address__h858472 = csrf_mtdc_reg[151:86]; + 5'd30: thin_address__h858472 = csrf_mScratchC_reg[151:86]; + default: thin_address__h858472 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16256; endcase end @@ -46012,289 +46033,289 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[123:119]) - 5'd1: thin_address__h899109 = csrf_ddc_reg[151:86]; - 5'd12: thin_address__h899109 = csrf_stcc_reg[151:86]; - 5'd13: thin_address__h899109 = csrf_stdc_reg[151:86]; - 5'd14: thin_address__h899109 = csrf_sScratchC_reg[151:86]; + 5'd1: thin_address__h899107 = csrf_ddc_reg[151:86]; + 5'd12: thin_address__h899107 = csrf_stcc_reg[151:86]; + 5'd13: thin_address__h899107 = csrf_stdc_reg[151:86]; + 5'd14: thin_address__h899107 = csrf_sScratchC_reg[151:86]; 5'd15: - thin_address__h899109 = + thin_address__h899107 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16104; - 5'd28: thin_address__h899109 = csrf_mtcc_reg[151:86]; - 5'd29: thin_address__h899109 = csrf_mtdc_reg[151:86]; - 5'd30: thin_address__h899109 = csrf_mScratchC_reg[151:86]; - default: thin_address__h899109 = + 5'd28: thin_address__h899107 = csrf_mtcc_reg[151:86]; + 5'd29: thin_address__h899107 = csrf_mtdc_reg[151:86]; + 5'd30: thin_address__h899107 = csrf_mScratchC_reg[151:86]; + default: thin_address__h899107 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16256; endcase end always@(f_csr_reqs$D_OUT or - fflags_csr__read__h849194 or - frm_csr__read__h849205 or - fcsr_csr__read__h849219 or - sstatus_csr__read__h849415 or - sie_csr__read__h849485 or + fflags_csr__read__h849193 or + frm_csr__read__h849204 or + fcsr_csr__read__h849218 or + sstatus_csr__read__h849414 or + sie_csr__read__h849484 or SEXT__0_CONCAT_csrf_stcc_reg_read__6046_BITS_8_ETC___d16070 or - scounteren_csr__read__h849573 or + scounteren_csr__read__h849572 or csrf_sscratch_csr or SEXT__0_CONCAT_IF_csrf_sepcc_reg_data_lat_0_wh_ETC___d16109 or - scause_csr__read__h849713 or + scause_csr__read__h849712 or csrf_stval_csr or - sip_csr__read__h849853 or - satp_csr__read__h849916 or - mstatus_csr__read__h850062 or - medeleg_csr__read__h850223 or - mideleg_csr__read__h850321 or - mie_csr__read__h850448 or + sip_csr__read__h849852 or + satp_csr__read__h849915 or + mstatus_csr__read__h850061 or + medeleg_csr__read__h850222 or + mideleg_csr__read__h850320 or + mie_csr__read__h850447 or SEXT__0_CONCAT_csrf_mtcc_reg_read__6198_BITS_8_ETC___d16222 or - mcounteren_csr__read__h850620 or + mcounteren_csr__read__h850619 or csrf_mscratch_csr or SEXT__0_CONCAT_IF_csrf_mepcc_reg_data_lat_0_wh_ETC___d16261 or - mcause_csr__read__h850886 or + mcause_csr__read__h850885 or csrf_mtval_csr or - mip_csr__read__h851125 or + mip_csr__read__h851124 or csrf_rg_tselect or - rg_tdata1__read__h852226 or + rg_tdata1__read__h852225 or csrf_rg_tdata2 or csrf_rg_tdata3 or csrf_rg_dcsr or SEXT__0_CONCAT_csrf_rg_dpc_read__6343_BITS_85__ETC___d16367 or csrf_rg_dscratch0 or csrf_rg_dscratch1 or - x_reg_ifc__read__h849324 or + x_reg_ifc__read__h849323 or csrf_mcycle_ehr_data_rl or - csrf_minstret_ehr_data_rl or x__h896542 or csrf_time_reg) + csrf_minstret_ehr_data_rl or x__h896540 or csrf_time_reg) begin case (f_csr_reqs$D_OUT[75:64]) - 12'd1: data_out__h1019990 = fflags_csr__read__h849194; - 12'd2: data_out__h1019990 = frm_csr__read__h849205; - 12'd3: data_out__h1019990 = fcsr_csr__read__h849219; - 12'd256: data_out__h1019990 = sstatus_csr__read__h849415; - 12'd260: data_out__h1019990 = sie_csr__read__h849485; + 12'd1: data_out__h1020024 = fflags_csr__read__h849193; + 12'd2: data_out__h1020024 = frm_csr__read__h849204; + 12'd3: data_out__h1020024 = fcsr_csr__read__h849218; + 12'd256: data_out__h1020024 = sstatus_csr__read__h849414; + 12'd260: data_out__h1020024 = sie_csr__read__h849484; 12'd261: - data_out__h1019990 = + data_out__h1020024 = SEXT__0_CONCAT_csrf_stcc_reg_read__6046_BITS_8_ETC___d16070; - 12'd262: data_out__h1019990 = scounteren_csr__read__h849573; - 12'd320: data_out__h1019990 = csrf_sscratch_csr; + 12'd262: data_out__h1020024 = scounteren_csr__read__h849572; + 12'd320: data_out__h1020024 = csrf_sscratch_csr; 12'd321: - data_out__h1019990 = + data_out__h1020024 = SEXT__0_CONCAT_IF_csrf_sepcc_reg_data_lat_0_wh_ETC___d16109; - 12'd322: data_out__h1019990 = scause_csr__read__h849713; - 12'd323: data_out__h1019990 = csrf_stval_csr; - 12'd324: data_out__h1019990 = sip_csr__read__h849853; - 12'd384: data_out__h1019990 = satp_csr__read__h849916; - 12'd768: data_out__h1019990 = mstatus_csr__read__h850062; - 12'd769: data_out__h1019990 = 64'h800000000014112D; - 12'd770: data_out__h1019990 = medeleg_csr__read__h850223; - 12'd771: data_out__h1019990 = mideleg_csr__read__h850321; - 12'd772: data_out__h1019990 = mie_csr__read__h850448; + 12'd322: data_out__h1020024 = scause_csr__read__h849712; + 12'd323: data_out__h1020024 = csrf_stval_csr; + 12'd324: data_out__h1020024 = sip_csr__read__h849852; + 12'd384: data_out__h1020024 = satp_csr__read__h849915; + 12'd768: data_out__h1020024 = mstatus_csr__read__h850061; + 12'd769: data_out__h1020024 = 64'h800000000014112D; + 12'd770: data_out__h1020024 = medeleg_csr__read__h850222; + 12'd771: data_out__h1020024 = mideleg_csr__read__h850320; + 12'd772: data_out__h1020024 = mie_csr__read__h850447; 12'd773: - data_out__h1019990 = + data_out__h1020024 = SEXT__0_CONCAT_csrf_mtcc_reg_read__6198_BITS_8_ETC___d16222; - 12'd774: data_out__h1019990 = mcounteren_csr__read__h850620; - 12'd832: data_out__h1019990 = csrf_mscratch_csr; + 12'd774: data_out__h1020024 = mcounteren_csr__read__h850619; + 12'd832: data_out__h1020024 = csrf_mscratch_csr; 12'd833: - data_out__h1019990 = + data_out__h1020024 = SEXT__0_CONCAT_IF_csrf_mepcc_reg_data_lat_0_wh_ETC___d16261; - 12'd834: data_out__h1019990 = mcause_csr__read__h850886; - 12'd835: data_out__h1019990 = csrf_mtval_csr; - 12'd836: data_out__h1019990 = mip_csr__read__h851125; - 12'd1952: data_out__h1019990 = csrf_rg_tselect; - 12'd1953: data_out__h1019990 = rg_tdata1__read__h852226; - 12'd1954: data_out__h1019990 = csrf_rg_tdata2; - 12'd1955: data_out__h1019990 = csrf_rg_tdata3; - 12'd1968: data_out__h1019990 = csrf_rg_dcsr; + 12'd834: data_out__h1020024 = mcause_csr__read__h850885; + 12'd835: data_out__h1020024 = csrf_mtval_csr; + 12'd836: data_out__h1020024 = mip_csr__read__h851124; + 12'd1952: data_out__h1020024 = csrf_rg_tselect; + 12'd1953: data_out__h1020024 = rg_tdata1__read__h852225; + 12'd1954: data_out__h1020024 = csrf_rg_tdata2; + 12'd1955: data_out__h1020024 = csrf_rg_tdata3; + 12'd1968: data_out__h1020024 = csrf_rg_dcsr; 12'd1969: - data_out__h1019990 = + data_out__h1020024 = SEXT__0_CONCAT_csrf_rg_dpc_read__6343_BITS_85__ETC___d16367; - 12'd1970: data_out__h1019990 = csrf_rg_dscratch0; - 12'd1971: data_out__h1019990 = csrf_rg_dscratch1; + 12'd1970: data_out__h1020024 = csrf_rg_dscratch0; + 12'd1971: data_out__h1020024 = csrf_rg_dscratch1; 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: - data_out__h1019990 = 64'd0; - 12'd2049: data_out__h1019990 = x_reg_ifc__read__h849324; - 12'd2816, 12'd3072: data_out__h1019990 = csrf_mcycle_ehr_data_rl; - 12'd2818, 12'd3074: data_out__h1019990 = csrf_minstret_ehr_data_rl; - 12'd3008: data_out__h1019990 = { 48'd0, x__h896542 }; - 12'd3073: data_out__h1019990 = csrf_time_reg; - default: data_out__h1019990 = 64'b0; + data_out__h1020024 = 64'd0; + 12'd2049: data_out__h1020024 = x_reg_ifc__read__h849323; + 12'd2816, 12'd3072: data_out__h1020024 = csrf_mcycle_ehr_data_rl; + 12'd2818, 12'd3074: data_out__h1020024 = csrf_minstret_ehr_data_rl; + 12'd3008: data_out__h1020024 = { 48'd0, x__h896540 }; + 12'd3073: data_out__h1020024 = csrf_time_reg; + default: data_out__h1020024 = 64'b0; endcase end always@(coreFix_aluExe_1_dispToRegQ$first or - fflags_csr__read__h849194 or - frm_csr__read__h849205 or - fcsr_csr__read__h849219 or - sstatus_csr__read__h849415 or - sie_csr__read__h849485 or + fflags_csr__read__h849193 or + frm_csr__read__h849204 or + fcsr_csr__read__h849218 or + sstatus_csr__read__h849414 or + sie_csr__read__h849484 or SEXT__0_CONCAT_csrf_stcc_reg_read__6046_BITS_8_ETC___d16070 or - scounteren_csr__read__h849573 or + scounteren_csr__read__h849572 or csrf_sscratch_csr or SEXT__0_CONCAT_IF_csrf_sepcc_reg_data_lat_0_wh_ETC___d16109 or - scause_csr__read__h849713 or + scause_csr__read__h849712 or csrf_stval_csr or - sip_csr__read__h849853 or - satp_csr__read__h849916 or - mstatus_csr__read__h850062 or - medeleg_csr__read__h850223 or - mideleg_csr__read__h850321 or - mie_csr__read__h850448 or + sip_csr__read__h849852 or + satp_csr__read__h849915 or + mstatus_csr__read__h850061 or + medeleg_csr__read__h850222 or + mideleg_csr__read__h850320 or + mie_csr__read__h850447 or SEXT__0_CONCAT_csrf_mtcc_reg_read__6198_BITS_8_ETC___d16222 or - mcounteren_csr__read__h850620 or + mcounteren_csr__read__h850619 or csrf_mscratch_csr or SEXT__0_CONCAT_IF_csrf_mepcc_reg_data_lat_0_wh_ETC___d16261 or - mcause_csr__read__h850886 or + mcause_csr__read__h850885 or csrf_mtval_csr or - mip_csr__read__h851125 or + mip_csr__read__h851124 or csrf_rg_tselect or - rg_tdata1__read__h852226 or + rg_tdata1__read__h852225 or csrf_rg_tdata2 or csrf_rg_tdata3 or csrf_rg_dcsr or SEXT__0_CONCAT_csrf_rg_dpc_read__6343_BITS_85__ETC___d16367 or csrf_rg_dscratch0 or csrf_rg_dscratch1 or - x_reg_ifc__read__h849324 or + x_reg_ifc__read__h849323 or csrf_mcycle_ehr_data_rl or - csrf_minstret_ehr_data_rl or x__h896542 or csrf_time_reg) + csrf_minstret_ehr_data_rl or x__h896540 or csrf_time_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[136:125]) - 12'd1: addr__h843950 = fflags_csr__read__h849194; - 12'd2: addr__h843950 = frm_csr__read__h849205; - 12'd3: addr__h843950 = fcsr_csr__read__h849219; - 12'd256: addr__h843950 = sstatus_csr__read__h849415; - 12'd260: addr__h843950 = sie_csr__read__h849485; + 12'd1: addr__h843948 = fflags_csr__read__h849193; + 12'd2: addr__h843948 = frm_csr__read__h849204; + 12'd3: addr__h843948 = fcsr_csr__read__h849218; + 12'd256: addr__h843948 = sstatus_csr__read__h849414; + 12'd260: addr__h843948 = sie_csr__read__h849484; 12'd261: - addr__h843950 = + addr__h843948 = SEXT__0_CONCAT_csrf_stcc_reg_read__6046_BITS_8_ETC___d16070; - 12'd262: addr__h843950 = scounteren_csr__read__h849573; - 12'd320: addr__h843950 = csrf_sscratch_csr; + 12'd262: addr__h843948 = scounteren_csr__read__h849572; + 12'd320: addr__h843948 = csrf_sscratch_csr; 12'd321: - addr__h843950 = + addr__h843948 = SEXT__0_CONCAT_IF_csrf_sepcc_reg_data_lat_0_wh_ETC___d16109; - 12'd322: addr__h843950 = scause_csr__read__h849713; - 12'd323: addr__h843950 = csrf_stval_csr; - 12'd324: addr__h843950 = sip_csr__read__h849853; - 12'd384: addr__h843950 = satp_csr__read__h849916; - 12'd768: addr__h843950 = mstatus_csr__read__h850062; - 12'd769: addr__h843950 = 64'h800000000014112D; - 12'd770: addr__h843950 = medeleg_csr__read__h850223; - 12'd771: addr__h843950 = mideleg_csr__read__h850321; - 12'd772: addr__h843950 = mie_csr__read__h850448; + 12'd322: addr__h843948 = scause_csr__read__h849712; + 12'd323: addr__h843948 = csrf_stval_csr; + 12'd324: addr__h843948 = sip_csr__read__h849852; + 12'd384: addr__h843948 = satp_csr__read__h849915; + 12'd768: addr__h843948 = mstatus_csr__read__h850061; + 12'd769: addr__h843948 = 64'h800000000014112D; + 12'd770: addr__h843948 = medeleg_csr__read__h850222; + 12'd771: addr__h843948 = mideleg_csr__read__h850320; + 12'd772: addr__h843948 = mie_csr__read__h850447; 12'd773: - addr__h843950 = + addr__h843948 = SEXT__0_CONCAT_csrf_mtcc_reg_read__6198_BITS_8_ETC___d16222; - 12'd774: addr__h843950 = mcounteren_csr__read__h850620; - 12'd832: addr__h843950 = csrf_mscratch_csr; + 12'd774: addr__h843948 = mcounteren_csr__read__h850619; + 12'd832: addr__h843948 = csrf_mscratch_csr; 12'd833: - addr__h843950 = + addr__h843948 = SEXT__0_CONCAT_IF_csrf_mepcc_reg_data_lat_0_wh_ETC___d16261; - 12'd834: addr__h843950 = mcause_csr__read__h850886; - 12'd835: addr__h843950 = csrf_mtval_csr; - 12'd836: addr__h843950 = mip_csr__read__h851125; - 12'd1952: addr__h843950 = csrf_rg_tselect; - 12'd1953: addr__h843950 = rg_tdata1__read__h852226; - 12'd1954: addr__h843950 = csrf_rg_tdata2; - 12'd1955: addr__h843950 = csrf_rg_tdata3; - 12'd1968: addr__h843950 = csrf_rg_dcsr; + 12'd834: addr__h843948 = mcause_csr__read__h850885; + 12'd835: addr__h843948 = csrf_mtval_csr; + 12'd836: addr__h843948 = mip_csr__read__h851124; + 12'd1952: addr__h843948 = csrf_rg_tselect; + 12'd1953: addr__h843948 = rg_tdata1__read__h852225; + 12'd1954: addr__h843948 = csrf_rg_tdata2; + 12'd1955: addr__h843948 = csrf_rg_tdata3; + 12'd1968: addr__h843948 = csrf_rg_dcsr; 12'd1969: - addr__h843950 = + addr__h843948 = SEXT__0_CONCAT_csrf_rg_dpc_read__6343_BITS_85__ETC___d16367; - 12'd1970: addr__h843950 = csrf_rg_dscratch0; - 12'd1971: addr__h843950 = csrf_rg_dscratch1; - 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: addr__h843950 = 64'd0; - 12'd2049: addr__h843950 = x_reg_ifc__read__h849324; - 12'd2816, 12'd3072: addr__h843950 = csrf_mcycle_ehr_data_rl; - 12'd2818, 12'd3074: addr__h843950 = csrf_minstret_ehr_data_rl; - 12'd3008: addr__h843950 = { 48'd0, x__h896542 }; - 12'd3073: addr__h843950 = csrf_time_reg; - default: addr__h843950 = 64'b0; + 12'd1970: addr__h843948 = csrf_rg_dscratch0; + 12'd1971: addr__h843948 = csrf_rg_dscratch1; + 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: addr__h843948 = 64'd0; + 12'd2049: addr__h843948 = x_reg_ifc__read__h849323; + 12'd2816, 12'd3072: addr__h843948 = csrf_mcycle_ehr_data_rl; + 12'd2818, 12'd3074: addr__h843948 = csrf_minstret_ehr_data_rl; + 12'd3008: addr__h843948 = { 48'd0, x__h896540 }; + 12'd3073: addr__h843948 = csrf_time_reg; + default: addr__h843948 = 64'b0; endcase end always@(coreFix_aluExe_0_dispToRegQ$first or - fflags_csr__read__h849194 or - frm_csr__read__h849205 or - fcsr_csr__read__h849219 or - sstatus_csr__read__h849415 or - sie_csr__read__h849485 or + fflags_csr__read__h849193 or + frm_csr__read__h849204 or + fcsr_csr__read__h849218 or + sstatus_csr__read__h849414 or + sie_csr__read__h849484 or SEXT__0_CONCAT_csrf_stcc_reg_read__6046_BITS_8_ETC___d16070 or - scounteren_csr__read__h849573 or + scounteren_csr__read__h849572 or csrf_sscratch_csr or SEXT__0_CONCAT_IF_csrf_sepcc_reg_data_lat_0_wh_ETC___d16109 or - scause_csr__read__h849713 or + scause_csr__read__h849712 or csrf_stval_csr or - sip_csr__read__h849853 or - satp_csr__read__h849916 or - mstatus_csr__read__h850062 or - medeleg_csr__read__h850223 or - mideleg_csr__read__h850321 or - mie_csr__read__h850448 or + sip_csr__read__h849852 or + satp_csr__read__h849915 or + mstatus_csr__read__h850061 or + medeleg_csr__read__h850222 or + mideleg_csr__read__h850320 or + mie_csr__read__h850447 or SEXT__0_CONCAT_csrf_mtcc_reg_read__6198_BITS_8_ETC___d16222 or - mcounteren_csr__read__h850620 or + mcounteren_csr__read__h850619 or csrf_mscratch_csr or SEXT__0_CONCAT_IF_csrf_mepcc_reg_data_lat_0_wh_ETC___d16261 or - mcause_csr__read__h850886 or + mcause_csr__read__h850885 or csrf_mtval_csr or - mip_csr__read__h851125 or + mip_csr__read__h851124 or csrf_rg_tselect or - rg_tdata1__read__h852226 or + rg_tdata1__read__h852225 or csrf_rg_tdata2 or csrf_rg_tdata3 or csrf_rg_dcsr or SEXT__0_CONCAT_csrf_rg_dpc_read__6343_BITS_85__ETC___d16367 or csrf_rg_dscratch0 or csrf_rg_dscratch1 or - x_reg_ifc__read__h849324 or + x_reg_ifc__read__h849323 or csrf_mcycle_ehr_data_rl or - csrf_minstret_ehr_data_rl or x__h896542 or csrf_time_reg) + csrf_minstret_ehr_data_rl or x__h896540 or csrf_time_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[136:125]) - 12'd1: addr__h887459 = fflags_csr__read__h849194; - 12'd2: addr__h887459 = frm_csr__read__h849205; - 12'd3: addr__h887459 = fcsr_csr__read__h849219; - 12'd256: addr__h887459 = sstatus_csr__read__h849415; - 12'd260: addr__h887459 = sie_csr__read__h849485; + 12'd1: addr__h887458 = fflags_csr__read__h849193; + 12'd2: addr__h887458 = frm_csr__read__h849204; + 12'd3: addr__h887458 = fcsr_csr__read__h849218; + 12'd256: addr__h887458 = sstatus_csr__read__h849414; + 12'd260: addr__h887458 = sie_csr__read__h849484; 12'd261: - addr__h887459 = + addr__h887458 = SEXT__0_CONCAT_csrf_stcc_reg_read__6046_BITS_8_ETC___d16070; - 12'd262: addr__h887459 = scounteren_csr__read__h849573; - 12'd320: addr__h887459 = csrf_sscratch_csr; + 12'd262: addr__h887458 = scounteren_csr__read__h849572; + 12'd320: addr__h887458 = csrf_sscratch_csr; 12'd321: - addr__h887459 = + addr__h887458 = SEXT__0_CONCAT_IF_csrf_sepcc_reg_data_lat_0_wh_ETC___d16109; - 12'd322: addr__h887459 = scause_csr__read__h849713; - 12'd323: addr__h887459 = csrf_stval_csr; - 12'd324: addr__h887459 = sip_csr__read__h849853; - 12'd384: addr__h887459 = satp_csr__read__h849916; - 12'd768: addr__h887459 = mstatus_csr__read__h850062; - 12'd769: addr__h887459 = 64'h800000000014112D; - 12'd770: addr__h887459 = medeleg_csr__read__h850223; - 12'd771: addr__h887459 = mideleg_csr__read__h850321; - 12'd772: addr__h887459 = mie_csr__read__h850448; + 12'd322: addr__h887458 = scause_csr__read__h849712; + 12'd323: addr__h887458 = csrf_stval_csr; + 12'd324: addr__h887458 = sip_csr__read__h849852; + 12'd384: addr__h887458 = satp_csr__read__h849915; + 12'd768: addr__h887458 = mstatus_csr__read__h850061; + 12'd769: addr__h887458 = 64'h800000000014112D; + 12'd770: addr__h887458 = medeleg_csr__read__h850222; + 12'd771: addr__h887458 = mideleg_csr__read__h850320; + 12'd772: addr__h887458 = mie_csr__read__h850447; 12'd773: - addr__h887459 = + addr__h887458 = SEXT__0_CONCAT_csrf_mtcc_reg_read__6198_BITS_8_ETC___d16222; - 12'd774: addr__h887459 = mcounteren_csr__read__h850620; - 12'd832: addr__h887459 = csrf_mscratch_csr; + 12'd774: addr__h887458 = mcounteren_csr__read__h850619; + 12'd832: addr__h887458 = csrf_mscratch_csr; 12'd833: - addr__h887459 = + addr__h887458 = SEXT__0_CONCAT_IF_csrf_mepcc_reg_data_lat_0_wh_ETC___d16261; - 12'd834: addr__h887459 = mcause_csr__read__h850886; - 12'd835: addr__h887459 = csrf_mtval_csr; - 12'd836: addr__h887459 = mip_csr__read__h851125; - 12'd1952: addr__h887459 = csrf_rg_tselect; - 12'd1953: addr__h887459 = rg_tdata1__read__h852226; - 12'd1954: addr__h887459 = csrf_rg_tdata2; - 12'd1955: addr__h887459 = csrf_rg_tdata3; - 12'd1968: addr__h887459 = csrf_rg_dcsr; + 12'd834: addr__h887458 = mcause_csr__read__h850885; + 12'd835: addr__h887458 = csrf_mtval_csr; + 12'd836: addr__h887458 = mip_csr__read__h851124; + 12'd1952: addr__h887458 = csrf_rg_tselect; + 12'd1953: addr__h887458 = rg_tdata1__read__h852225; + 12'd1954: addr__h887458 = csrf_rg_tdata2; + 12'd1955: addr__h887458 = csrf_rg_tdata3; + 12'd1968: addr__h887458 = csrf_rg_dcsr; 12'd1969: - addr__h887459 = + addr__h887458 = SEXT__0_CONCAT_csrf_rg_dpc_read__6343_BITS_85__ETC___d16367; - 12'd1970: addr__h887459 = csrf_rg_dscratch0; - 12'd1971: addr__h887459 = csrf_rg_dscratch1; - 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: addr__h887459 = 64'd0; - 12'd2049: addr__h887459 = x_reg_ifc__read__h849324; - 12'd2816, 12'd3072: addr__h887459 = csrf_mcycle_ehr_data_rl; - 12'd2818, 12'd3074: addr__h887459 = csrf_minstret_ehr_data_rl; - 12'd3008: addr__h887459 = { 48'd0, x__h896542 }; - 12'd3073: addr__h887459 = csrf_time_reg; - default: addr__h887459 = 64'b0; + 12'd1970: addr__h887458 = csrf_rg_dscratch0; + 12'd1971: addr__h887458 = csrf_rg_dscratch1; + 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: addr__h887458 = 64'd0; + 12'd2049: addr__h887458 = x_reg_ifc__read__h849323; + 12'd2816, 12'd3072: addr__h887458 = csrf_mcycle_ehr_data_rl; + 12'd2818, 12'd3074: addr__h887458 = csrf_minstret_ehr_data_rl; + 12'd3008: addr__h887458 = { 48'd0, x__h896540 }; + 12'd3073: addr__h887458 = csrf_time_reg; + default: addr__h887458 = 64'b0; endcase end always@(coreFix_aluExe_1_dispToRegQ$first or @@ -46877,17 +46898,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[123:119]) - 5'd1: thin_reserved__h858477 = csrf_ddc_reg[54:53]; - 5'd12: thin_reserved__h858477 = csrf_stcc_reg[54:53]; - 5'd13: thin_reserved__h858477 = csrf_stdc_reg[54:53]; - 5'd14: thin_reserved__h858477 = csrf_sScratchC_reg[54:53]; + 5'd1: thin_reserved__h858476 = csrf_ddc_reg[54:53]; + 5'd12: thin_reserved__h858476 = csrf_stcc_reg[54:53]; + 5'd13: thin_reserved__h858476 = csrf_stdc_reg[54:53]; + 5'd14: thin_reserved__h858476 = csrf_sScratchC_reg[54:53]; 5'd15: - thin_reserved__h858477 = + thin_reserved__h858476 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17176; - 5'd28: thin_reserved__h858477 = csrf_mtcc_reg[54:53]; - 5'd29: thin_reserved__h858477 = csrf_mtdc_reg[54:53]; - 5'd30: thin_reserved__h858477 = csrf_mScratchC_reg[54:53]; - default: thin_reserved__h858477 = + 5'd28: thin_reserved__h858476 = csrf_mtcc_reg[54:53]; + 5'd29: thin_reserved__h858476 = csrf_mtdc_reg[54:53]; + 5'd30: thin_reserved__h858476 = csrf_mScratchC_reg[54:53]; + default: thin_reserved__h858476 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17182; endcase end @@ -46901,17 +46922,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[123:119]) - 5'd1: thin_reserved__h899113 = csrf_ddc_reg[54:53]; - 5'd12: thin_reserved__h899113 = csrf_stcc_reg[54:53]; - 5'd13: thin_reserved__h899113 = csrf_stdc_reg[54:53]; - 5'd14: thin_reserved__h899113 = csrf_sScratchC_reg[54:53]; + 5'd1: thin_reserved__h899111 = csrf_ddc_reg[54:53]; + 5'd12: thin_reserved__h899111 = csrf_stcc_reg[54:53]; + 5'd13: thin_reserved__h899111 = csrf_stdc_reg[54:53]; + 5'd14: thin_reserved__h899111 = csrf_sScratchC_reg[54:53]; 5'd15: - thin_reserved__h899113 = + thin_reserved__h899111 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17176; - 5'd28: thin_reserved__h899113 = csrf_mtcc_reg[54:53]; - 5'd29: thin_reserved__h899113 = csrf_mtdc_reg[54:53]; - 5'd30: thin_reserved__h899113 = csrf_mScratchC_reg[54:53]; - default: thin_reserved__h899113 = + 5'd28: thin_reserved__h899111 = csrf_mtcc_reg[54:53]; + 5'd29: thin_reserved__h899111 = csrf_mtdc_reg[54:53]; + 5'd30: thin_reserved__h899111 = csrf_mScratchC_reg[54:53]; + default: thin_reserved__h899111 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17182; endcase end @@ -46925,17 +46946,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[123:119]) - 5'd1: thin_perms_soft__h858713 = csrf_ddc_reg[71:68]; - 5'd12: thin_perms_soft__h858713 = csrf_stcc_reg[71:68]; - 5'd13: thin_perms_soft__h858713 = csrf_stdc_reg[71:68]; - 5'd14: thin_perms_soft__h858713 = csrf_sScratchC_reg[71:68]; + 5'd1: thin_perms_soft__h858712 = csrf_ddc_reg[71:68]; + 5'd12: thin_perms_soft__h858712 = csrf_stcc_reg[71:68]; + 5'd13: thin_perms_soft__h858712 = csrf_stdc_reg[71:68]; + 5'd14: thin_perms_soft__h858712 = csrf_sScratchC_reg[71:68]; 5'd15: - thin_perms_soft__h858713 = + thin_perms_soft__h858712 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16862; - 5'd28: thin_perms_soft__h858713 = csrf_mtcc_reg[71:68]; - 5'd29: thin_perms_soft__h858713 = csrf_mtdc_reg[71:68]; - 5'd30: thin_perms_soft__h858713 = csrf_mScratchC_reg[71:68]; - default: thin_perms_soft__h858713 = + 5'd28: thin_perms_soft__h858712 = csrf_mtcc_reg[71:68]; + 5'd29: thin_perms_soft__h858712 = csrf_mtdc_reg[71:68]; + 5'd30: thin_perms_soft__h858712 = csrf_mScratchC_reg[71:68]; + default: thin_perms_soft__h858712 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16868; endcase end @@ -46949,17 +46970,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[123:119]) - 5'd1: thin_perms_soft__h899289 = csrf_ddc_reg[71:68]; - 5'd12: thin_perms_soft__h899289 = csrf_stcc_reg[71:68]; - 5'd13: thin_perms_soft__h899289 = csrf_stdc_reg[71:68]; - 5'd14: thin_perms_soft__h899289 = csrf_sScratchC_reg[71:68]; + 5'd1: thin_perms_soft__h899287 = csrf_ddc_reg[71:68]; + 5'd12: thin_perms_soft__h899287 = csrf_stcc_reg[71:68]; + 5'd13: thin_perms_soft__h899287 = csrf_stdc_reg[71:68]; + 5'd14: thin_perms_soft__h899287 = csrf_sScratchC_reg[71:68]; 5'd15: - thin_perms_soft__h899289 = + thin_perms_soft__h899287 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16862; - 5'd28: thin_perms_soft__h899289 = csrf_mtcc_reg[71:68]; - 5'd29: thin_perms_soft__h899289 = csrf_mtdc_reg[71:68]; - 5'd30: thin_perms_soft__h899289 = csrf_mScratchC_reg[71:68]; - default: thin_perms_soft__h899289 = + 5'd28: thin_perms_soft__h899287 = csrf_mtcc_reg[71:68]; + 5'd29: thin_perms_soft__h899287 = csrf_mtdc_reg[71:68]; + 5'd30: thin_perms_soft__h899287 = csrf_mScratchC_reg[71:68]; + default: thin_perms_soft__h899287 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16868; endcase end @@ -46973,17 +46994,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[123:119]) - 5'd1: thin_bounds_topBits__h860421 = csrf_ddc_reg[27:14]; - 5'd12: thin_bounds_topBits__h860421 = csrf_stcc_reg[27:14]; - 5'd13: thin_bounds_topBits__h860421 = csrf_stdc_reg[27:14]; - 5'd14: thin_bounds_topBits__h860421 = csrf_sScratchC_reg[27:14]; + 5'd1: thin_bounds_topBits__h860420 = csrf_ddc_reg[27:14]; + 5'd12: thin_bounds_topBits__h860420 = csrf_stcc_reg[27:14]; + 5'd13: thin_bounds_topBits__h860420 = csrf_stdc_reg[27:14]; + 5'd14: thin_bounds_topBits__h860420 = csrf_sScratchC_reg[27:14]; 5'd15: - thin_bounds_topBits__h860421 = + thin_bounds_topBits__h860420 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17285; - 5'd28: thin_bounds_topBits__h860421 = csrf_mtcc_reg[27:14]; - 5'd29: thin_bounds_topBits__h860421 = csrf_mtdc_reg[27:14]; - 5'd30: thin_bounds_topBits__h860421 = csrf_mScratchC_reg[27:14]; - default: thin_bounds_topBits__h860421 = + 5'd28: thin_bounds_topBits__h860420 = csrf_mtcc_reg[27:14]; + 5'd29: thin_bounds_topBits__h860420 = csrf_mtdc_reg[27:14]; + 5'd30: thin_bounds_topBits__h860420 = csrf_mScratchC_reg[27:14]; + default: thin_bounds_topBits__h860420 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17291; endcase end @@ -46997,17 +47018,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[123:119]) - 5'd1: thin_bounds_topBits__h900515 = csrf_ddc_reg[27:14]; - 5'd12: thin_bounds_topBits__h900515 = csrf_stcc_reg[27:14]; - 5'd13: thin_bounds_topBits__h900515 = csrf_stdc_reg[27:14]; - 5'd14: thin_bounds_topBits__h900515 = csrf_sScratchC_reg[27:14]; + 5'd1: thin_bounds_topBits__h900513 = csrf_ddc_reg[27:14]; + 5'd12: thin_bounds_topBits__h900513 = csrf_stcc_reg[27:14]; + 5'd13: thin_bounds_topBits__h900513 = csrf_stdc_reg[27:14]; + 5'd14: thin_bounds_topBits__h900513 = csrf_sScratchC_reg[27:14]; 5'd15: - thin_bounds_topBits__h900515 = + thin_bounds_topBits__h900513 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17285; - 5'd28: thin_bounds_topBits__h900515 = csrf_mtcc_reg[27:14]; - 5'd29: thin_bounds_topBits__h900515 = csrf_mtdc_reg[27:14]; - 5'd30: thin_bounds_topBits__h900515 = csrf_mScratchC_reg[27:14]; - default: thin_bounds_topBits__h900515 = + 5'd28: thin_bounds_topBits__h900513 = csrf_mtcc_reg[27:14]; + 5'd29: thin_bounds_topBits__h900513 = csrf_mtdc_reg[27:14]; + 5'd30: thin_bounds_topBits__h900513 = csrf_mScratchC_reg[27:14]; + default: thin_bounds_topBits__h900513 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17291; endcase end @@ -47163,44 +47184,6 @@ module mkCore(CLK, IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16934; endcase end - always@(coreFix_aluExe_0_dispToRegQ$first or - IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16956 or - csrf_ddc_reg or - csrf_stcc_reg or - csrf_stdc_reg or - csrf_sScratchC_reg or - IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16950 or - csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) - begin - case (coreFix_aluExe_0_dispToRegQ$first[123:119]) - 5'd1: - IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19267 = - csrf_ddc_reg[64]; - 5'd12: - IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19267 = - csrf_stcc_reg[64]; - 5'd13: - IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19267 = - csrf_stdc_reg[64]; - 5'd14: - IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19267 = - csrf_sScratchC_reg[64]; - 5'd15: - IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19267 = - IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16950; - 5'd28: - IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19267 = - csrf_mtcc_reg[64]; - 5'd29: - IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19267 = - csrf_mtdc_reg[64]; - 5'd30: - IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19267 = - csrf_mScratchC_reg[64]; - default: IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19267 = - IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16956; - endcase - end always@(coreFix_aluExe_0_dispToRegQ$first or IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16978 or csrf_ddc_reg or @@ -47239,6 +47222,44 @@ module mkCore(CLK, IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16978; endcase end + always@(coreFix_aluExe_0_dispToRegQ$first or + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16956 or + csrf_ddc_reg or + csrf_stcc_reg or + csrf_stdc_reg or + csrf_sScratchC_reg or + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16950 or + csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) + begin + case (coreFix_aluExe_0_dispToRegQ$first[123:119]) + 5'd1: + IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19267 = + csrf_ddc_reg[64]; + 5'd12: + IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19267 = + csrf_stcc_reg[64]; + 5'd13: + IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19267 = + csrf_stdc_reg[64]; + 5'd14: + IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19267 = + csrf_sScratchC_reg[64]; + 5'd15: + IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19267 = + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16950; + 5'd28: + IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19267 = + csrf_mtcc_reg[64]; + 5'd29: + IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19267 = + csrf_mtdc_reg[64]; + 5'd30: + IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19267 = + csrf_mScratchC_reg[64]; + default: IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19267 = + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16956; + endcase + end always@(coreFix_aluExe_0_dispToRegQ$first or IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17000 or csrf_ddc_reg or @@ -47353,44 +47374,6 @@ module mkCore(CLK, IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17044; endcase end - always@(coreFix_aluExe_0_dispToRegQ$first or - IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17088 or - csrf_ddc_reg or - csrf_stcc_reg or - csrf_stdc_reg or - csrf_sScratchC_reg or - IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17082 or - csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) - begin - case (coreFix_aluExe_0_dispToRegQ$first[123:119]) - 5'd1: - IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19321 = - csrf_ddc_reg[58]; - 5'd12: - IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19321 = - csrf_stcc_reg[58]; - 5'd13: - IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19321 = - csrf_stdc_reg[58]; - 5'd14: - IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19321 = - csrf_sScratchC_reg[58]; - 5'd15: - IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19321 = - IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17082; - 5'd28: - IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19321 = - csrf_mtcc_reg[58]; - 5'd29: - IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19321 = - csrf_mtdc_reg[58]; - 5'd30: - IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19321 = - csrf_mScratchC_reg[58]; - default: IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19321 = - IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17088; - endcase - end always@(coreFix_aluExe_0_dispToRegQ$first or IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17066 or csrf_ddc_reg or @@ -47430,41 +47413,41 @@ module mkCore(CLK, endcase end always@(coreFix_aluExe_0_dispToRegQ$first or - IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17110 or + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17088 or csrf_ddc_reg or csrf_stcc_reg or csrf_stdc_reg or csrf_sScratchC_reg or - IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17104 or + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17082 or csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[123:119]) 5'd1: - IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19330 = - csrf_ddc_reg[57]; + IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19321 = + csrf_ddc_reg[58]; 5'd12: - IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19330 = - csrf_stcc_reg[57]; + IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19321 = + csrf_stcc_reg[58]; 5'd13: - IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19330 = - csrf_stdc_reg[57]; + IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19321 = + csrf_stdc_reg[58]; 5'd14: - IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19330 = - csrf_sScratchC_reg[57]; + IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19321 = + csrf_sScratchC_reg[58]; 5'd15: - IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19330 = - IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17104; + IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19321 = + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17082; 5'd28: - IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19330 = - csrf_mtcc_reg[57]; + IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19321 = + csrf_mtcc_reg[58]; 5'd29: - IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19330 = - csrf_mtdc_reg[57]; + IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19321 = + csrf_mtdc_reg[58]; 5'd30: - IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19330 = - csrf_mScratchC_reg[57]; - default: IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19330 = - IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17110; + IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19321 = + csrf_mScratchC_reg[58]; + default: IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19321 = + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17088; endcase end always@(coreFix_aluExe_0_dispToRegQ$first or @@ -47505,6 +47488,44 @@ module mkCore(CLK, IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17132; endcase end + always@(coreFix_aluExe_0_dispToRegQ$first or + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17110 or + csrf_ddc_reg or + csrf_stcc_reg or + csrf_stdc_reg or + csrf_sScratchC_reg or + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17104 or + csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) + begin + case (coreFix_aluExe_0_dispToRegQ$first[123:119]) + 5'd1: + IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19330 = + csrf_ddc_reg[57]; + 5'd12: + IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19330 = + csrf_stcc_reg[57]; + 5'd13: + IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19330 = + csrf_stdc_reg[57]; + 5'd14: + IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19330 = + csrf_sScratchC_reg[57]; + 5'd15: + IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19330 = + IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17104; + 5'd28: + IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19330 = + csrf_mtcc_reg[57]; + 5'd29: + IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19330 = + csrf_mtdc_reg[57]; + 5'd30: + IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19330 = + csrf_mScratchC_reg[57]; + default: IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19330 = + IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17110; + endcase + end always@(coreFix_aluExe_0_dispToRegQ$first or IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17160 or csrf_ddc_reg or @@ -47591,17 +47612,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[123:119]) - 5'd1: thin_otype__h858478 = csrf_ddc_reg[52:35]; - 5'd12: thin_otype__h858478 = csrf_stcc_reg[52:35]; - 5'd13: thin_otype__h858478 = csrf_stdc_reg[52:35]; - 5'd14: thin_otype__h858478 = csrf_sScratchC_reg[52:35]; + 5'd1: thin_otype__h858477 = csrf_ddc_reg[52:35]; + 5'd12: thin_otype__h858477 = csrf_stcc_reg[52:35]; + 5'd13: thin_otype__h858477 = csrf_stdc_reg[52:35]; + 5'd14: thin_otype__h858477 = csrf_sScratchC_reg[52:35]; 5'd15: - thin_otype__h858478 = + thin_otype__h858477 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17198; - 5'd28: thin_otype__h858478 = csrf_mtcc_reg[52:35]; - 5'd29: thin_otype__h858478 = csrf_mtdc_reg[52:35]; - 5'd30: thin_otype__h858478 = csrf_mScratchC_reg[52:35]; - default: thin_otype__h858478 = + 5'd28: thin_otype__h858477 = csrf_mtcc_reg[52:35]; + 5'd29: thin_otype__h858477 = csrf_mtdc_reg[52:35]; + 5'd30: thin_otype__h858477 = csrf_mScratchC_reg[52:35]; + default: thin_otype__h858477 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17204; endcase end @@ -47615,17 +47636,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[123:119]) - 5'd1: thin_otype__h899114 = csrf_ddc_reg[52:35]; - 5'd12: thin_otype__h899114 = csrf_stcc_reg[52:35]; - 5'd13: thin_otype__h899114 = csrf_stdc_reg[52:35]; - 5'd14: thin_otype__h899114 = csrf_sScratchC_reg[52:35]; + 5'd1: thin_otype__h899112 = csrf_ddc_reg[52:35]; + 5'd12: thin_otype__h899112 = csrf_stcc_reg[52:35]; + 5'd13: thin_otype__h899112 = csrf_stdc_reg[52:35]; + 5'd14: thin_otype__h899112 = csrf_sScratchC_reg[52:35]; 5'd15: - thin_otype__h899114 = + thin_otype__h899112 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17198; - 5'd28: thin_otype__h899114 = csrf_mtcc_reg[52:35]; - 5'd29: thin_otype__h899114 = csrf_mtdc_reg[52:35]; - 5'd30: thin_otype__h899114 = csrf_mScratchC_reg[52:35]; - default: thin_otype__h899114 = + 5'd28: thin_otype__h899112 = csrf_mtcc_reg[52:35]; + 5'd29: thin_otype__h899112 = csrf_mtdc_reg[52:35]; + 5'd30: thin_otype__h899112 = csrf_mScratchC_reg[52:35]; + default: thin_otype__h899112 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17204; endcase end @@ -47709,10 +47730,10 @@ module mkCore(CLK, begin case (mmio_dataReqQ_data_0[150:149]) 2'd0, 2'd1, 2'd2: - CASE_mmio_dataReqQ_data_0_BITS_150_TO_149_0_mm_ETC__q331 = + CASE_mmio_dataReqQ_data_0_BITS_150_TO_149_0_mm_ETC__q333 = mmio_dataReqQ_data_0[150:145]; 2'd3: - CASE_mmio_dataReqQ_data_0_BITS_150_TO_149_0_mm_ETC__q331 = + CASE_mmio_dataReqQ_data_0_BITS_150_TO_149_0_mm_ETC__q333 = { 2'd3, mmio_dataReqQ_data_0[148:145] }; endcase end @@ -47720,9 +47741,9 @@ module mkCore(CLK, begin case (coreFix_memExe_lsq$firstSt[3:0]) 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: - CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q332 = + CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q334 = coreFix_memExe_lsq$firstSt[3:0]; - default: CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q332 = + default: CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q334 = 4'd15; endcase end @@ -47752,9 +47773,9 @@ module mkCore(CLK, 5'd24, 5'd25, 5'd26: - CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q333 = + CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q335 = coreFix_memExe_lsq$firstSt[4:0]; - default: CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q333 = + default: CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q335 = 5'd27; endcase end @@ -47775,40 +47796,40 @@ module mkCore(CLK, 5'd12, 5'd13, 5'd15: - CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q334 = + CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q336 = coreFix_memExe_lsq$firstSt[4:0]; - default: CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q334 = + default: CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q336 = 5'd28; endcase end always@(coreFix_memExe_lsq$firstSt or - CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q332 or - CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q333 or - CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q334) + CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q334 or + CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q335 or + CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q336) begin case (coreFix_memExe_lsq$firstSt[12:11]) 2'd0: - CASE_coreFix_memExe_lsqfirstSt_BITS_12_TO_11__ETC__q335 = + CASE_coreFix_memExe_lsqfirstSt_BITS_12_TO_11__ETC__q337 = { 2'd0, coreFix_memExe_lsq$firstSt[10:5], - CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q333 }; + CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q335 }; 2'd1: - CASE_coreFix_memExe_lsqfirstSt_BITS_12_TO_11__ETC__q335 = + CASE_coreFix_memExe_lsqfirstSt_BITS_12_TO_11__ETC__q337 = { coreFix_memExe_lsq$firstSt[12:11], 6'h2A, - CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q334 }; - default: CASE_coreFix_memExe_lsqfirstSt_BITS_12_TO_11__ETC__q335 = + CASE_coreFix_memExe_lsqfirstSt_BITS_4_TO_0_0__ETC__q336 }; + default: CASE_coreFix_memExe_lsqfirstSt_BITS_12_TO_11__ETC__q337 = { 9'd298, - CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q332 }; + CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q334 }; endcase end always@(coreFix_memExe_lsq$firstLd) begin case (coreFix_memExe_lsq$firstLd[6:3]) 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: - CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q336 = + CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q338 = coreFix_memExe_lsq$firstLd[6:3]; - default: CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q336 = + default: CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q338 = 4'd15; endcase end @@ -47838,9 +47859,9 @@ module mkCore(CLK, 5'd24, 5'd25, 5'd26: - CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q337 = + CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q339 = coreFix_memExe_lsq$firstLd[7:3]; - default: CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q337 = + default: CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q339 = 5'd27; endcase end @@ -47861,41 +47882,41 @@ module mkCore(CLK, 5'd12, 5'd13, 5'd15: - CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q338 = + CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q340 = coreFix_memExe_lsq$firstLd[7:3]; - default: CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q338 = + default: CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q340 = 5'd28; endcase end always@(coreFix_memExe_lsq$firstLd or - CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q336 or - CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q337 or - CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q338) + CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q338 or + CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q339 or + CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q340) begin case (coreFix_memExe_lsq$firstLd[15:14]) 2'd0: - CASE_coreFix_memExe_lsqfirstLd_BITS_15_TO_14__ETC__q339 = + CASE_coreFix_memExe_lsqfirstLd_BITS_15_TO_14__ETC__q341 = { 2'd0, coreFix_memExe_lsq$firstLd[13:8], - CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q337 }; + CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q339 }; 2'd1: - CASE_coreFix_memExe_lsqfirstLd_BITS_15_TO_14__ETC__q339 = + CASE_coreFix_memExe_lsqfirstLd_BITS_15_TO_14__ETC__q341 = { coreFix_memExe_lsq$firstLd[15:14], 6'h2A, - CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q338 }; - default: CASE_coreFix_memExe_lsqfirstLd_BITS_15_TO_14__ETC__q339 = + CASE_coreFix_memExe_lsqfirstLd_BITS_7_TO_3_0__ETC__q340 }; + default: CASE_coreFix_memExe_lsqfirstLd_BITS_15_TO_14__ETC__q341 = { 9'd298, - CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q336 }; + CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q338 }; endcase end always@(mmioToPlatform_pRq_enq_x) begin case (mmioToPlatform_pRq_enq_x[37:36]) 2'd0, 2'd1, 2'd2: - CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q340 = + CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q342 = mmioToPlatform_pRq_enq_x[37:32]; 2'd3: - CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q340 = + CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q342 = { 2'd3, mmioToPlatform_pRq_enq_x[35:32] }; endcase end @@ -47903,26 +47924,26 @@ module mkCore(CLK, begin case (coreFix_aluExe_0_rsAlu$dispatchData[203:201]) 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q341 = + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q343 = coreFix_aluExe_0_rsAlu$dispatchData[203:201]; - default: CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q341 = 3'd7; + default: CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q343 = 3'd7; endcase end always@(coreFix_aluExe_0_rsAlu$dispatchData or - CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q341) + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q343) begin case (coreFix_aluExe_0_rsAlu$dispatchData[229:227]) 3'd0, 3'd1, 3'd2, 3'd3: - CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q342 = + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q344 = coreFix_aluExe_0_rsAlu$dispatchData[229:200]; 3'd4: - CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q342 = + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q344 = { coreFix_aluExe_0_rsAlu$dispatchData[229:227], 18'h2AAAA, coreFix_aluExe_0_rsAlu$dispatchData[208:204], - CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q341, + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q343, coreFix_aluExe_0_rsAlu$dispatchData[200] }; - default: CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q342 = + default: CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q344 = 30'd715827882; endcase end @@ -47931,13 +47952,13 @@ module mkCore(CLK, begin case (coreFix_aluExe_0_rsAlu$dispatchData[199:198]) 2'd0: - CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q343 = + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q345 = coreFix_aluExe_0_rsAlu$dispatchData[199:189]; 2'd1: - CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q343 = + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q345 = { coreFix_aluExe_0_rsAlu$dispatchData[199:198], IF_coreFix_aluExe_0_rsAlu_dispatchData__8084_B_ETC___d18225 }; - default: CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q343 = + default: CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q345 = 11'd1194; endcase end @@ -47990,9 +48011,9 @@ module mkCore(CLK, 12'd3858, 12'd3859, 12'd3860: - CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q344 = + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q346 = coreFix_aluExe_0_rsAlu$dispatchData[140:129]; - default: CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q344 = + default: CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q346 = 12'd2303; endcase end @@ -48000,9 +48021,9 @@ module mkCore(CLK, begin case (coreFix_aluExe_0_rsAlu$dispatchData[127:123]) 5'd0, 5'd1, 5'd12, 5'd13, 5'd14, 5'd15, 5'd28, 5'd29, 5'd30, 5'd31: - CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q345 = + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q347 = coreFix_aluExe_0_rsAlu$dispatchData[127:123]; - default: CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q345 = + default: CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q347 = 5'd10; endcase end @@ -48032,9 +48053,9 @@ module mkCore(CLK, 5'd24, 5'd25, 5'd26: - CASE_basicExec_9859_BITS_270_TO_266_0_basicExe_ETC__q346 = + CASE_basicExec_9859_BITS_270_TO_266_0_basicExe_ETC__q348 = basicExec___d19859[270:266]; - default: CASE_basicExec_9859_BITS_270_TO_266_0_basicExe_ETC__q346 = + default: CASE_basicExec_9859_BITS_270_TO_266_0_basicExe_ETC__q348 = 5'd27; endcase end @@ -48042,26 +48063,26 @@ module mkCore(CLK, begin case (coreFix_aluExe_0_dispToRegQ$first[199:197]) 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_19_ETC__q347 = + CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_19_ETC__q349 = coreFix_aluExe_0_dispToRegQ$first[199:197]; - default: CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_19_ETC__q347 = 3'd7; + default: CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_19_ETC__q349 = 3'd7; endcase end always@(coreFix_aluExe_0_dispToRegQ$first or - CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_19_ETC__q347) + CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_19_ETC__q349) begin case (coreFix_aluExe_0_dispToRegQ$first[225:223]) 3'd0, 3'd1, 3'd2, 3'd3: - CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_22_ETC__q348 = + CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_22_ETC__q350 = coreFix_aluExe_0_dispToRegQ$first[225:196]; 3'd4: - CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_22_ETC__q348 = + CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_22_ETC__q350 = { coreFix_aluExe_0_dispToRegQ$first[225:223], 18'h2AAAA, coreFix_aluExe_0_dispToRegQ$first[204:200], - CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_19_ETC__q347, + CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_19_ETC__q349, coreFix_aluExe_0_dispToRegQ$first[196] }; - default: CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_22_ETC__q348 = + default: CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_22_ETC__q350 = 30'd715827882; endcase end @@ -48070,13 +48091,13 @@ module mkCore(CLK, begin case (coreFix_aluExe_0_dispToRegQ$first[195:194]) 2'd0: - CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_19_ETC__q349 = + CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_19_ETC__q351 = coreFix_aluExe_0_dispToRegQ$first[195:185]; 2'd1: - CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_19_ETC__q349 = + CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_19_ETC__q351 = { coreFix_aluExe_0_dispToRegQ$first[195:194], IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d18609 }; - default: CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_19_ETC__q349 = + default: CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_19_ETC__q351 = 11'd1194; endcase end @@ -48129,9 +48150,9 @@ module mkCore(CLK, 12'd3858, 12'd3859, 12'd3860: - CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q350 = + CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q352 = coreFix_aluExe_0_dispToRegQ$first[136:125]; - default: CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q350 = + default: CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q352 = 12'd2303; endcase end @@ -48139,9 +48160,9 @@ module mkCore(CLK, begin case (coreFix_aluExe_0_dispToRegQ$first[123:119]) 5'd0, 5'd1, 5'd12, 5'd13, 5'd14, 5'd15, 5'd28, 5'd29, 5'd30, 5'd31: - CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_12_ETC__q351 = + CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_12_ETC__q353 = coreFix_aluExe_0_dispToRegQ$first[123:119]; - default: CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_12_ETC__q351 = + default: CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_12_ETC__q353 = 5'd10; endcase end @@ -48149,26 +48170,26 @@ module mkCore(CLK, begin case (coreFix_aluExe_1_rsAlu$dispatchData[203:201]) 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q352 = + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q354 = coreFix_aluExe_1_rsAlu$dispatchData[203:201]; - default: CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q352 = 3'd7; + default: CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q354 = 3'd7; endcase end always@(coreFix_aluExe_1_rsAlu$dispatchData or - CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q352) + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q354) begin case (coreFix_aluExe_1_rsAlu$dispatchData[229:227]) 3'd0, 3'd1, 3'd2, 3'd3: - CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q353 = + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q355 = coreFix_aluExe_1_rsAlu$dispatchData[229:200]; 3'd4: - CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q353 = + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q355 = { coreFix_aluExe_1_rsAlu$dispatchData[229:227], 18'h2AAAA, coreFix_aluExe_1_rsAlu$dispatchData[208:204], - CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q352, + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q354, coreFix_aluExe_1_rsAlu$dispatchData[200] }; - default: CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q353 = + default: CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q355 = 30'd715827882; endcase end @@ -48177,13 +48198,13 @@ module mkCore(CLK, begin case (coreFix_aluExe_1_rsAlu$dispatchData[199:198]) 2'd0: - CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q354 = + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q356 = coreFix_aluExe_1_rsAlu$dispatchData[199:189]; 2'd1: - CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q354 = + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q356 = { coreFix_aluExe_1_rsAlu$dispatchData[199:198], IF_coreFix_aluExe_1_rsAlu_dispatchData__5318_B_ETC___d15461 }; - default: CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q354 = + default: CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q356 = 11'd1194; endcase end @@ -48236,9 +48257,9 @@ module mkCore(CLK, 12'd3858, 12'd3859, 12'd3860: - CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q355 = + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q357 = coreFix_aluExe_1_rsAlu$dispatchData[140:129]; - default: CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q355 = + default: CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q357 = 12'd2303; endcase end @@ -48246,9 +48267,9 @@ module mkCore(CLK, begin case (coreFix_aluExe_1_rsAlu$dispatchData[127:123]) 5'd0, 5'd1, 5'd12, 5'd13, 5'd14, 5'd15, 5'd28, 5'd29, 5'd30, 5'd31: - CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q356 = + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q358 = coreFix_aluExe_1_rsAlu$dispatchData[127:123]; - default: CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q356 = + default: CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q358 = 5'd10; endcase end @@ -48278,9 +48299,9 @@ module mkCore(CLK, 5'd24, 5'd25, 5'd26: - CASE_basicExec_7743_BITS_270_TO_266_0_basicExe_ETC__q357 = + CASE_basicExec_7743_BITS_270_TO_266_0_basicExe_ETC__q359 = basicExec___d17743[270:266]; - default: CASE_basicExec_7743_BITS_270_TO_266_0_basicExe_ETC__q357 = + default: CASE_basicExec_7743_BITS_270_TO_266_0_basicExe_ETC__q359 = 5'd27; endcase end @@ -48288,26 +48309,26 @@ module mkCore(CLK, begin case (coreFix_aluExe_1_dispToRegQ$first[199:197]) 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_19_ETC__q358 = + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_19_ETC__q360 = coreFix_aluExe_1_dispToRegQ$first[199:197]; - default: CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_19_ETC__q358 = 3'd7; + default: CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_19_ETC__q360 = 3'd7; endcase end always@(coreFix_aluExe_1_dispToRegQ$first or - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_19_ETC__q358) + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_19_ETC__q360) begin case (coreFix_aluExe_1_dispToRegQ$first[225:223]) 3'd0, 3'd1, 3'd2, 3'd3: - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_22_ETC__q359 = + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_22_ETC__q361 = coreFix_aluExe_1_dispToRegQ$first[225:196]; 3'd4: - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_22_ETC__q359 = + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_22_ETC__q361 = { coreFix_aluExe_1_dispToRegQ$first[225:223], 18'h2AAAA, coreFix_aluExe_1_dispToRegQ$first[204:200], - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_19_ETC__q358, + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_19_ETC__q360, coreFix_aluExe_1_dispToRegQ$first[196] }; - default: CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_22_ETC__q359 = + default: CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_22_ETC__q361 = 30'd715827882; endcase end @@ -48316,13 +48337,13 @@ module mkCore(CLK, begin case (coreFix_aluExe_1_dispToRegQ$first[195:194]) 2'd0: - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_19_ETC__q360 = + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_19_ETC__q362 = coreFix_aluExe_1_dispToRegQ$first[195:185]; 2'd1: - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_19_ETC__q360 = + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_19_ETC__q362 = { coreFix_aluExe_1_dispToRegQ$first[195:194], IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d15846 }; - default: CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_19_ETC__q360 = + default: CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_19_ETC__q362 = 11'd1194; endcase end @@ -48375,9 +48396,9 @@ module mkCore(CLK, 12'd3858, 12'd3859, 12'd3860: - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q361 = + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q363 = coreFix_aluExe_1_dispToRegQ$first[136:125]; - default: CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q361 = + default: CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q363 = 12'd2303; endcase end @@ -48385,9 +48406,9 @@ module mkCore(CLK, begin case (coreFix_aluExe_1_dispToRegQ$first[123:119]) 5'd0, 5'd1, 5'd12, 5'd13, 5'd14, 5'd15, 5'd28, 5'd29, 5'd30, 5'd31: - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_12_ETC__q362 = + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_12_ETC__q364 = coreFix_aluExe_1_dispToRegQ$first[123:119]; - default: CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_12_ETC__q362 = + default: CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_12_ETC__q364 = 5'd10; endcase end @@ -48395,26 +48416,26 @@ module mkCore(CLK, begin case (coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[69:67]) 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q363 = + CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q365 = coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[69:67]; - default: CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q363 = 3'd7; + default: CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q365 = 3'd7; endcase end always@(coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData or - CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q363) + CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q365) begin case (coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[95:93]) 3'd0, 3'd1, 3'd2, 3'd3: - CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q364 = + CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q366 = coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[95:66]; 3'd4: - CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q364 = + CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q366 = { coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[95:93], 18'h2AAAA, coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[74:70], - CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q363, + CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q365, coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[66] }; - default: CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q364 = + default: CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q366 = 30'd715827882; endcase end @@ -48426,16 +48447,16 @@ module mkCore(CLK, begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229]) 5'd0: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q365 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q367 = IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14805; 5'd1: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q365 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q367 = coreFix_fpuMulDivExe_0_regToExeQ$first[225] ? { !coreFix_fpuMulDivExe_0_regToExeQ$first[139], coreFix_fpuMulDivExe_0_regToExeQ$first[138:76] } : { IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14858, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14803 }; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q365 = + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q367 = IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d13325; endcase end @@ -48444,9 +48465,9 @@ module mkCore(CLK, begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229]) 5'd0, 5'd1: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q366 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q368 = 64'h3FF0000000000000; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q366 = + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q368 = IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14805; endcase end @@ -48454,26 +48475,26 @@ module mkCore(CLK, begin case (coreFix_fpuMulDivExe_0_dispToRegQ$first[60:58]) 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q367 = + CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q369 = coreFix_fpuMulDivExe_0_dispToRegQ$first[60:58]; - default: CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q367 = 3'd7; + default: CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q369 = 3'd7; endcase end always@(coreFix_fpuMulDivExe_0_dispToRegQ$first or - CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q367) + CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q369) begin case (coreFix_fpuMulDivExe_0_dispToRegQ$first[86:84]) 3'd0, 3'd1, 3'd2, 3'd3: - CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q368 = + CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q370 = coreFix_fpuMulDivExe_0_dispToRegQ$first[86:57]; 3'd4: - CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q368 = + CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q370 = { coreFix_fpuMulDivExe_0_dispToRegQ$first[86:84], 18'h2AAAA, coreFix_fpuMulDivExe_0_dispToRegQ$first[65:61], - CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q367, + CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q369, coreFix_fpuMulDivExe_0_dispToRegQ$first[57] }; - default: CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q368 = + default: CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q370 = 30'd715827882; endcase end @@ -48483,10 +48504,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q369 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q371 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[1:0]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q369 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q371 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[1:0]; endcase end @@ -48497,12 +48518,12 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_processAmo[7:6]) 2'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q370 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q372 = SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4867; 2'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q370 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q372 = SEXT_SEL_ARR_SEL_ARR_coreFix_memExe_dMem_cache_ETC___d4881[63:0]; - default: CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q370 = + default: CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q372 = SEXT_SEL_ARR_SEL_ARR_coreFix_memExe_dMem_cache_ETC___d4889[63:0]; endcase end @@ -48513,12 +48534,12 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_processAmo[7:6]) 2'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q371 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q373 = SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4861; 2'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q371 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q373 = SEXT_SEL_ARR_SEL_ARR_coreFix_memExe_dMem_cache_ETC___d4881[127:64]; - default: CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q371 = + default: CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q373 = SEXT_SEL_ARR_SEL_ARR_coreFix_memExe_dMem_cache_ETC___d4889[127:64]; endcase end @@ -53572,12 +53593,12 @@ module mkCore(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo) $write("'h%h", - CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q370, + CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q372, " "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo) $write("'h%h", - CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q371, + CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q373, " "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo) @@ -53886,7 +53907,7 @@ module mkCore(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[469:465] == 5'd17 && - IF_rob_deqPort_0_deq_data__2261_BIT_288_2918_T_ETC___d23012 == 6'd6) + IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd6) $display("[Terminate CSR] being written (val = %x), ", "send terminate signal to host", rob$deqPort_0_deq_data[95:32]); @@ -54024,7 +54045,7 @@ module mkCore(CLK, rob$deqPort_1_deq_data[469:465] != 5'd25) $write("instret:%0d PC:0x%0h instr:0x%08h", commitStage_rg_serial_num + - IF_rob_deqPort_0_canDeq__3598_THEN_IF_NOT_rob__ETC___d23719, + IF_rob_deqPort_0_canDeq__3600_THEN_IF_NOT_rob__ETC___d23721, rob$deqPort_1_deq_data[630:502], rob$deqPort_1_deq_data[501:470], " iType:"); @@ -56715,17 +56736,17 @@ module mkCore(CLK, if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) $write(" o: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) - $write("'h%h", value__h254475); + $write("'h%h", value__h254472); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) $write(" b: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) - $write("'h%h", value__h254639); + $write("'h%h", value__h254636); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) $write(" t: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) - $write("'h%h", x__h254751[64:0]); + $write("'h%h", x__h254748[64:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) $write(" sp: "); if (RST_N != `BSV_RESET_VALUE) @@ -58519,14 +58540,14 @@ module mkCore(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem) begin - v__h213413 = $time; + v__h213411 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem) - $write("%t : ", v__h213413, "[doRespLdMem]", " "); + $write("%t : ", v__h213411, "[doRespLdMem]", " "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem) $write("'h%h", t__h212841); + if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem) $write("'h%h", t__h212839); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem) $write("; "); if (RST_N != `BSV_RESET_VALUE) @@ -58665,15 +58686,15 @@ module mkCore(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward) begin - v__h215682 = $time; + v__h215680 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward) - $write("%t : ", v__h215682, "[doRespLdForward]", " "); + $write("%t : ", v__h215680, "[doRespLdForward]", " "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward) - $write("'h%h", t__h215127); + $write("'h%h", t__h215125); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward) $write("; "); if (RST_N != `BSV_RESET_VALUE) @@ -58898,17 +58919,17 @@ module mkCore(CLK, if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" o: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) - $write("'h%h", value__h239694); + $write("'h%h", value__h239691); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" b: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) - $write("'h%h", value__h239858); + $write("'h%h", value__h239855); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" t: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) - $write("'h%h", x__h239970[64:0]); + $write("'h%h", x__h239967[64:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" sp: "); if (RST_N != `BSV_RESET_VALUE) @@ -58948,17 +58969,17 @@ module mkCore(CLK, if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" o: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) - $write("'h%h", value__h240851); + $write("'h%h", value__h240848); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" b: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) - $write("'h%h", value__h241015); + $write("'h%h", value__h241012); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" t: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) - $write("'h%h", x__h241127[64:0]); + $write("'h%h", x__h241124[64:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" sp: "); if (RST_N != `BSV_RESET_VALUE) @@ -67191,14 +67212,14 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5591) begin - v__h271939 = $time; + v__h271938 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5591) - $write("%t : [Ld resp] ", v__h271939); + $write("%t : [Ld resp] ", v__h271938); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && @@ -68838,13 +68859,13 @@ module mkCore(CLK, if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5595) begin - v__h347457 = $time; + v__h347456 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5595) - $write("%t : [Ld resp] ", v__h347457); + $write("%t : [Ld resp] ", v__h347456); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5595) @@ -70718,7 +70739,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == 3'd0) begin - v__h423783 = $time; + v__h423782 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) @@ -70726,7 +70747,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == 3'd0) - $write("%t : [Ld resp] ", v__h423783); + $write("%t : [Ld resp] ", v__h423782); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && @@ -73130,7 +73151,7 @@ module mkCore(CLK, $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas && - v__h836642 == 2'd0) + v__h836639 == 2'd0) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); end // synopsys translate_on diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkCoreW.v b/src_SSITH_P3/xilinx_ip/hdl/mkCoreW.v index b86c663..2cee937 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkCoreW.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkCoreW.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jul 1 17:07:45 BST 2020 +// On Thu Jul 2 02:59:17 BST 2020 // // // Ports: @@ -783,7 +783,7 @@ module mkCoreW(RST_N_dm_power_on_reset, ifcs_1_1_noRoute_currentReq$port1__read, ifcs_1_noRoute_inner_currentReq$port1__read, msNoSynth_1_arNoSynth_buffer_enqw$wget, - msNoSynth_1_awNoSynth_snk_putWire$wget; + msNoSynth_1_awNoSynth_buffer_enqw$wget; wire [74 : 0] tagController_tmp_shimSlave_wff_rv$port0__write_1, tagController_tmp_shimSlave_wff_rv$port1__read, tagController_tmp_shimSlave_wff_rv$port2__read, @@ -3313,12 +3313,12 @@ module mkCoreW(RST_N_dm_power_on_reset, MUX_flitToSink_2$wset_1__SEL_1, MUX_flitToSink_2$wset_1__SEL_3, MUX_ifcs_0_1_state_1$write_1__SEL_1, - MUX_ifcs_0_state$write_1__PSEL_3, + MUX_ifcs_0_state$write_1__PSEL_1, MUX_ifcs_0_state$write_1__SEL_1, MUX_ifcs_0_state$write_1__SEL_2, MUX_ifcs_0_state$write_1__SEL_3, MUX_ifcs_1_1_state_1$write_1__SEL_1, - MUX_ifcs_1_state$write_1__PSEL_3, + MUX_ifcs_1_state$write_1__PSEL_1, MUX_ifcs_1_state$write_1__SEL_1, MUX_ifcs_1_state$write_1__SEL_2, MUX_ifcs_1_state$write_1__SEL_3, @@ -5303,22 +5303,22 @@ module mkCoreW(RST_N_dm_power_on_reset, // rule RL_rl_dm_hart0_reset_wait assign CAN_FIRE_RL_rl_dm_hart0_reset_wait = (rg_hart0_reset_delay != 8'd1 || - proc$RDY_start && - debug_module$RDY_hart0_reset_client_response_put) && + debug_module$RDY_hart0_reset_client_response_put && + proc$RDY_start) && rg_hart0_reset_delay != 8'd0 ; assign WILL_FIRE_RL_rl_dm_hart0_reset_wait = CAN_FIRE_RL_rl_dm_hart0_reset_wait && !EN_start ; // rule RL_ClientServerRequest assign CAN_FIRE_RL_ClientServerRequest = - proc$RDY_hart0_run_halt_server_request_put && - debug_module$RDY_hart0_client_run_halt_request_get ; + debug_module$RDY_hart0_client_run_halt_request_get && + proc$RDY_hart0_run_halt_server_request_put ; assign WILL_FIRE_RL_ClientServerRequest = CAN_FIRE_RL_ClientServerRequest ; // rule RL_ClientServerResponse assign CAN_FIRE_RL_ClientServerResponse = - proc$RDY_hart0_run_halt_server_response_get && - debug_module$RDY_hart0_client_run_halt_response_put ; + debug_module$RDY_hart0_client_run_halt_response_put && + proc$RDY_hart0_run_halt_server_response_get ; assign WILL_FIRE_RL_ClientServerResponse = CAN_FIRE_RL_ClientServerResponse ; @@ -5330,15 +5330,15 @@ module mkCoreW(RST_N_dm_power_on_reset, // rule RL_ClientServerResponse_1 assign CAN_FIRE_RL_ClientServerResponse_1 = - proc$RDY_hart0_gpr_mem_server_response_get && - debug_module$RDY_hart0_gpr_mem_client_response_put ; + debug_module$RDY_hart0_gpr_mem_client_response_put && + proc$RDY_hart0_gpr_mem_server_response_get ; assign WILL_FIRE_RL_ClientServerResponse_1 = CAN_FIRE_RL_ClientServerResponse_1 ; // rule RL_ClientServerResponse_2 assign CAN_FIRE_RL_ClientServerResponse_2 = - proc$RDY_hart0_csr_mem_server_response_get && - debug_module$RDY_hart0_csr_mem_client_response_put ; + debug_module$RDY_hart0_csr_mem_client_response_put && + proc$RDY_hart0_csr_mem_server_response_get ; assign WILL_FIRE_RL_ClientServerResponse_2 = CAN_FIRE_RL_ClientServerResponse_2 ; @@ -7758,15 +7758,15 @@ module mkCoreW(RST_N_dm_power_on_reset, // rule RL_ClientServerRequest_1 assign CAN_FIRE_RL_ClientServerRequest_1 = - proc$RDY_hart0_gpr_mem_server_request_put && - debug_module$RDY_hart0_gpr_mem_client_request_get ; + debug_module$RDY_hart0_gpr_mem_client_request_get && + proc$RDY_hart0_gpr_mem_server_request_put ; assign WILL_FIRE_RL_ClientServerRequest_1 = CAN_FIRE_RL_ClientServerRequest_1 ; // rule RL_ClientServerRequest_2 assign CAN_FIRE_RL_ClientServerRequest_2 = - proc$RDY_hart0_csr_mem_server_request_put && - debug_module$RDY_hart0_csr_mem_client_request_get ; + debug_module$RDY_hart0_csr_mem_client_request_get && + proc$RDY_hart0_csr_mem_server_request_put ; assign WILL_FIRE_RL_ClientServerRequest_2 = CAN_FIRE_RL_ClientServerRequest_2 ; @@ -8623,33 +8623,33 @@ module mkCoreW(RST_N_dm_power_on_reset, assign MUX_ifcs_0_1_state_1$write_1__SEL_1 = WILL_FIRE_RL_ifcs_0_1_followFlits_1 && ssNoSynth_0_rNoSynth_buffer_ff$D_OUT[1] ; - assign MUX_ifcs_0_state$write_1__SEL_1 = - WILL_FIRE_RL_ifcs_0_firstFlit && - IF_merged_0_outflit_whas__501_THEN_NOT_merged__ETC___d1556 ; - assign MUX_ifcs_0_state$write_1__SEL_2 = - WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp && - IF_merged_0_outflit_whas__501_THEN_NOT_merged__ETC___d1556 ; - assign MUX_ifcs_0_state$write_1__PSEL_3 = + assign MUX_ifcs_0_state$write_1__PSEL_1 = WILL_FIRE_RL_ifcs_0_drainFlits || WILL_FIRE_RL_ifcs_0_followFlits ; - assign MUX_ifcs_0_state$write_1__SEL_3 = - MUX_ifcs_0_state$write_1__PSEL_3 && + assign MUX_ifcs_0_state$write_1__SEL_1 = + MUX_ifcs_0_state$write_1__PSEL_1 && IF_merged_0_outflit_whas__501_THEN_merged_0_ou_ETC___d1561 ; + assign MUX_ifcs_0_state$write_1__SEL_2 = + WILL_FIRE_RL_ifcs_0_firstFlit && + IF_merged_0_outflit_whas__501_THEN_NOT_merged__ETC___d1556 ; + assign MUX_ifcs_0_state$write_1__SEL_3 = + WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp && + IF_merged_0_outflit_whas__501_THEN_NOT_merged__ETC___d1556 ; assign MUX_ifcs_1_1_state_1$write_1__SEL_1 = WILL_FIRE_RL_ifcs_1_1_followFlits_1 && ssNoSynth_1_rNoSynth_buffer_ff$D_OUT[1] ; - assign MUX_ifcs_1_state$write_1__SEL_1 = - WILL_FIRE_RL_ifcs_1_firstFlit && - IF_merged_1_outflit_whas__601_THEN_NOT_merged__ETC___d1650 ; - assign MUX_ifcs_1_state$write_1__SEL_2 = - WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp && - IF_merged_1_outflit_whas__601_THEN_NOT_merged__ETC___d1650 ; - assign MUX_ifcs_1_state$write_1__PSEL_3 = + assign MUX_ifcs_1_state$write_1__PSEL_1 = WILL_FIRE_RL_ifcs_1_drainFlits || WILL_FIRE_RL_ifcs_1_followFlits ; - assign MUX_ifcs_1_state$write_1__SEL_3 = - MUX_ifcs_1_state$write_1__PSEL_3 && + assign MUX_ifcs_1_state$write_1__SEL_1 = + MUX_ifcs_1_state$write_1__PSEL_1 && IF_merged_1_outflit_whas__601_THEN_merged_1_ou_ETC___d1655 ; + assign MUX_ifcs_1_state$write_1__SEL_2 = + WILL_FIRE_RL_ifcs_1_firstFlit && + IF_merged_1_outflit_whas__601_THEN_NOT_merged__ETC___d1650 ; + assign MUX_ifcs_1_state$write_1__SEL_3 = + WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp && + IF_merged_1_outflit_whas__601_THEN_NOT_merged__ETC___d1650 ; assign MUX_ifcs_2_1_state$write_1__SEL_1 = WILL_FIRE_RL_ifcs_2_1_followFlits && ssNoSynth_2_rNoSynth_buffer_ff$D_OUT[1] ; @@ -8917,7 +8917,7 @@ module mkCoreW(RST_N_dm_power_on_reset, WILL_FIRE_RL_sinks_1_1_0_doPut ? MUX_ifcs_0_1_snk_putWire$wset_1__VAL_1 : ifcs_0_1_noRouteRsp$D_OUT ; - assign msNoSynth_1_awNoSynth_snk_putWire$wget = + assign msNoSynth_1_awNoSynth_buffer_enqw$wget = { debug_module$master_awid, debug_module$master_awaddr, debug_module$master_awlen, @@ -9706,20 +9706,20 @@ module mkCoreW(RST_N_dm_power_on_reset, MUX_ifcs_0_state$write_1__SEL_2 or MUX_ifcs_0_state$write_1__SEL_3) begin case (1'b1) // synopsys parallel_case - MUX_ifcs_0_state$write_1__SEL_1: ifcs_0_state$D_IN = 2'd1; - MUX_ifcs_0_state$write_1__SEL_2: ifcs_0_state$D_IN = 2'd2; - MUX_ifcs_0_state$write_1__SEL_3: ifcs_0_state$D_IN = 2'd0; + MUX_ifcs_0_state$write_1__SEL_1: ifcs_0_state$D_IN = 2'd0; + MUX_ifcs_0_state$write_1__SEL_2: ifcs_0_state$D_IN = 2'd1; + MUX_ifcs_0_state$write_1__SEL_3: ifcs_0_state$D_IN = 2'd2; default: ifcs_0_state$D_IN = 2'b10 /* unspecified value */ ; endcase end assign ifcs_0_state$EN = + (WILL_FIRE_RL_ifcs_0_drainFlits || + WILL_FIRE_RL_ifcs_0_followFlits) && + IF_merged_0_outflit_whas__501_THEN_merged_0_ou_ETC___d1561 || WILL_FIRE_RL_ifcs_0_firstFlit && IF_merged_0_outflit_whas__501_THEN_NOT_merged__ETC___d1556 || WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp && - IF_merged_0_outflit_whas__501_THEN_NOT_merged__ETC___d1556 || - (WILL_FIRE_RL_ifcs_0_drainFlits || - WILL_FIRE_RL_ifcs_0_followFlits) && - IF_merged_0_outflit_whas__501_THEN_merged_0_ou_ETC___d1561 ; + IF_merged_0_outflit_whas__501_THEN_NOT_merged__ETC___d1556 ; // register ifcs_0_state_1 assign ifcs_0_state_1$D_IN = 1'd0 ; @@ -9764,20 +9764,20 @@ module mkCoreW(RST_N_dm_power_on_reset, MUX_ifcs_1_state$write_1__SEL_2 or MUX_ifcs_1_state$write_1__SEL_3) begin case (1'b1) // synopsys parallel_case - MUX_ifcs_1_state$write_1__SEL_1: ifcs_1_state$D_IN = 2'd1; - MUX_ifcs_1_state$write_1__SEL_2: ifcs_1_state$D_IN = 2'd2; - MUX_ifcs_1_state$write_1__SEL_3: ifcs_1_state$D_IN = 2'd0; + MUX_ifcs_1_state$write_1__SEL_1: ifcs_1_state$D_IN = 2'd0; + MUX_ifcs_1_state$write_1__SEL_2: ifcs_1_state$D_IN = 2'd1; + MUX_ifcs_1_state$write_1__SEL_3: ifcs_1_state$D_IN = 2'd2; default: ifcs_1_state$D_IN = 2'b10 /* unspecified value */ ; endcase end assign ifcs_1_state$EN = + (WILL_FIRE_RL_ifcs_1_drainFlits || + WILL_FIRE_RL_ifcs_1_followFlits) && + IF_merged_1_outflit_whas__601_THEN_merged_1_ou_ETC___d1655 || WILL_FIRE_RL_ifcs_1_firstFlit && IF_merged_1_outflit_whas__601_THEN_NOT_merged__ETC___d1650 || WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp && - IF_merged_1_outflit_whas__601_THEN_NOT_merged__ETC___d1650 || - (WILL_FIRE_RL_ifcs_1_drainFlits || - WILL_FIRE_RL_ifcs_1_followFlits) && - IF_merged_1_outflit_whas__601_THEN_merged_1_ou_ETC___d1655 ; + IF_merged_1_outflit_whas__601_THEN_NOT_merged__ETC___d1650 ; // register ifcs_1_state_1 assign ifcs_1_state_1$D_IN = 1'd0 ; @@ -10332,7 +10332,7 @@ module mkCoreW(RST_N_dm_power_on_reset, assign merged_1_awff$D_IN = msNoSynth_1_awNoSynth_buffer_ff$EMPTY_N ? msNoSynth_1_awNoSynth_buffer_ff$D_OUT : - msNoSynth_1_awNoSynth_snk_putWire$wget ; + msNoSynth_1_awNoSynth_buffer_enqw$wget ; assign merged_1_awff$ENQ = CAN_FIRE_RL_merged_1_awFlit ; assign merged_1_awff$DEQ = CAN_FIRE_RL_merged_1_genFirst ; assign merged_1_awff$CLR = 1'b0 ; @@ -10432,7 +10432,7 @@ module mkCoreW(RST_N_dm_power_on_reset, // submodule msNoSynth_1_awNoSynth_buffer_ff assign msNoSynth_1_awNoSynth_buffer_ff$D_IN = - msNoSynth_1_awNoSynth_snk_putWire$wget ; + msNoSynth_1_awNoSynth_buffer_enqw$wget ; assign msNoSynth_1_awNoSynth_buffer_ff$ENQ = CAN_FIRE_RL_msNoSynth_1_awNoSynth_buffer_enqueue ; assign msNoSynth_1_awNoSynth_buffer_ff$DEQ = diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDCRqMshrWrapper.v b/src_SSITH_P3/xilinx_ip/hdl/mkDCRqMshrWrapper.v index d8f0756..8863dc3 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDCRqMshrWrapper.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDCRqMshrWrapper.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:52:01 BST 2020 +// On Thu Jul 2 02:53:53 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDM_Abstract_Commands.v b/src_SSITH_P3/xilinx_ip/hdl/mkDM_Abstract_Commands.v index a5ea406..8a66c6a 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDM_Abstract_Commands.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDM_Abstract_Commands.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 24 20:23:59 BST 2020 +// On Thu Jul 2 02:46:44 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDM_Run_Control.v b/src_SSITH_P3/xilinx_ip/hdl/mkDM_Run_Control.v index 52cd854..2cdae8a 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDM_Run_Control.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDM_Run_Control.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 24 20:23:58 BST 2020 +// On Thu Jul 2 02:46:43 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDM_System_Bus.v b/src_SSITH_P3/xilinx_ip/hdl/mkDM_System_Bus.v index 87ed61e..45cb1e9 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDM_System_Bus.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDM_System_Bus.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:45:18 BST 2020 +// On Thu Jul 2 02:46:59 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDPRqMshrWrapper.v b/src_SSITH_P3/xilinx_ip/hdl/mkDPRqMshrWrapper.v index 3a1285e..091e4a5 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDPRqMshrWrapper.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDPRqMshrWrapper.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:52:02 BST 2020 +// On Thu Jul 2 02:53:54 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDPipeline.v b/src_SSITH_P3/xilinx_ip/hdl/mkDPipeline.v index 02b27ea..52b9305 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDPipeline.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDPipeline.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:52:05 BST 2020 +// On Thu Jul 2 02:53:57 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDTlbSynth.v b/src_SSITH_P3/xilinx_ip/hdl/mkDTlbSynth.v index d47a114..3b4ce0f 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDTlbSynth.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDTlbSynth.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:52:32 BST 2020 +// On Thu Jul 2 02:54:27 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDebug_Module.v b/src_SSITH_P3/xilinx_ip/hdl/mkDebug_Module.v index 63c5137..11e425d 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDebug_Module.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDebug_Module.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:45:19 BST 2020 +// On Thu Jul 2 02:47:00 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDirPredictor.v b/src_SSITH_P3/xilinx_ip/hdl/mkDirPredictor.v index ea4c12d..2b0072b 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDirPredictor.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDirPredictor.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:53:56 BST 2020 +// On Thu Jul 2 02:56:45 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDivExecQ.v b/src_SSITH_P3/xilinx_ip/hdl/mkDivExecQ.v index 26bed02..aa37e9d 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDivExecQ.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDivExecQ.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:53:50 BST 2020 +// On Thu Jul 2 02:55:48 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDoubleDiv.v b/src_SSITH_P3/xilinx_ip/hdl/mkDoubleDiv.v index a9fc74d..67af9a1 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDoubleDiv.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDoubleDiv.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:53:30 BST 2020 +// On Thu Jul 2 02:55:27 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDoubleFMA.v b/src_SSITH_P3/xilinx_ip/hdl/mkDoubleFMA.v index 22e646b..b276d98 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDoubleFMA.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDoubleFMA.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:53:36 BST 2020 +// On Thu Jul 2 02:55:33 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDoubleSqrt.v b/src_SSITH_P3/xilinx_ip/hdl/mkDoubleSqrt.v index a38d838..39ac50d 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDoubleSqrt.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDoubleSqrt.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:53:33 BST 2020 +// On Thu Jul 2 02:55:30 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDummyStoreBuffer.v b/src_SSITH_P3/xilinx_ip/hdl/mkDummyStoreBuffer.v index 4674119..8a46fff 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDummyStoreBuffer.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDummyStoreBuffer.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:46:05 BST 2020 +// On Thu Jul 2 02:47:51 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkEpochManager.v b/src_SSITH_P3/xilinx_ip/hdl/mkEpochManager.v index 5eff025..409e367 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkEpochManager.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkEpochManager.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:45:54 BST 2020 +// On Thu Jul 2 02:47:40 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkFetchStage.v b/src_SSITH_P3/xilinx_ip/hdl/mkFetchStage.v index 93dfe52..d32e3f0 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkFetchStage.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkFetchStage.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:54:10 BST 2020 +// On Thu Jul 2 02:56:59 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkFmaExecQ.v b/src_SSITH_P3/xilinx_ip/hdl/mkFmaExecQ.v index 30f6e60..8a2f5d7 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkFmaExecQ.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkFmaExecQ.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:53:38 BST 2020 +// On Thu Jul 2 02:55:35 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkFpuMulDivDispToRegFifo.v b/src_SSITH_P3/xilinx_ip/hdl/mkFpuMulDivDispToRegFifo.v index 4283b86..a6aee6c 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkFpuMulDivDispToRegFifo.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkFpuMulDivDispToRegFifo.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:53:51 BST 2020 +// On Thu Jul 2 02:55:49 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkFpuMulDivRegToExeFifo.v b/src_SSITH_P3/xilinx_ip/hdl/mkFpuMulDivRegToExeFifo.v index 1d123cf..21640fd 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkFpuMulDivRegToExeFifo.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkFpuMulDivRegToExeFifo.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:53:52 BST 2020 +// On Thu Jul 2 02:55:49 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkGSelectGHistReg.v b/src_SSITH_P3/xilinx_ip/hdl/mkGSelectGHistReg.v index 52b5d00..49613ec 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkGSelectGHistReg.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkGSelectGHistReg.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:53:52 BST 2020 +// On Thu Jul 2 02:56:42 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkGSelectPred.v b/src_SSITH_P3/xilinx_ip/hdl/mkGSelectPred.v index f8bdbef..158aded 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkGSelectPred.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkGSelectPred.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:53:53 BST 2020 +// On Thu Jul 2 02:56:42 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkGShareGHistReg.v b/src_SSITH_P3/xilinx_ip/hdl/mkGShareGHistReg.v index b294278..a5c42dc 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkGShareGHistReg.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkGShareGHistReg.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:53:53 BST 2020 +// On Thu Jul 2 02:56:43 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkGSharePred.v b/src_SSITH_P3/xilinx_ip/hdl/mkGSharePred.v index 15c3761..3a02e80 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkGSharePred.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkGSharePred.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:53:53 BST 2020 +// On Thu Jul 2 02:56:43 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkIBankWrapper.v b/src_SSITH_P3/xilinx_ip/hdl/mkIBankWrapper.v index 578f452..a4dcf1d 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkIBankWrapper.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkIBankWrapper.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:52:11 BST 2020 +// On Thu Jul 2 02:54:04 BST 2020 // // // Ports: @@ -585,7 +585,7 @@ module mkIBankWrapper(CLK, SEL_ARR_m_fromPQ_data_0_13_BITS_65_TO_2_22_m_f_ETC___d425, addr__h42425; reg [31 : 0] CASE_m_cRqMshrpipelineResp_getRq_BITS_5_TO_2__ETC__q37, - CASE_sel1069_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36; + CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36; reg [2 : 0] CASE_m_rqToPQ_deqP_0_m_rqToPQ_data_0_BITS_2_TO_ETC__q31, x__h45568; reg [1 : 0] CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_1_TO_ETC__q38, @@ -616,7 +616,7 @@ module mkIBankWrapper(CLK, IF_m_pipeline_first__47_BITS_518_TO_516_52_EQ__ETC___d595; wire [5 : 0] IF_m_pipeline_first__47_BITS_521_TO_520_58_EQ__ETC___d600, SEL_ARR_m_rqToPQ_data_0_84_BITS_5_TO_4_94_m_rq_ETC___d806; - wire [3 : 0] sel__h51069; + wire [3 : 0] sel__h51068; wire [2 : 0] IF_m_cRqMshr_pipelineResp_searchEndOfChain_m_c_ETC___d615, SEL_ARR_m_fromPQ_data_0_13_BIT_518_49_m_fromPQ_ETC___d461, SEL_ARR_m_rsToPQ_data_0_10_BIT_515_27_m_rsToPQ_ETC___d739, @@ -1055,7 +1055,7 @@ module mkIBankWrapper(CLK, WILL_FIRE_RL_m_pipelineResp_pRq && !m_pipeline$first[575] ; assign MUX_m_cRqMshr$pipelineResp_setResult_2__VAL_1 = { 4'd15 - m_cRqMshr$pipelineResp_getRq[5:2] != 4'd0, - CASE_sel1069_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36, + CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36, 1'd1, CASE_m_cRqMshrpipelineResp_getRq_BITS_5_TO_2__ETC__q37 } ; assign MUX_m_cRqMshr$pipelineResp_setStateSlot_2__VAL_2 = @@ -1714,7 +1714,7 @@ module mkIBankWrapper(CLK, assign resp_addr__h45726 = { m_cRqMshr$sendRsToP_cRq_getSlot[53:1], m_cRqMshr$sendRsToP_cRq_getRq[10:0] } ; - assign sel__h51069 = m_cRqMshr$pipelineResp_getRq[5:2] + 4'd1 ; + assign sel__h51068 = m_cRqMshr$pipelineResp_getRq[5:2] + 4'd1 ; assign v__h10212 = IF_m_rsToPQ_enqReq_lat_1_whas__1_THEN_m_rsToPQ_ETC___d40 ? v__h10363 : @@ -2150,56 +2150,56 @@ module mkIBankWrapper(CLK, m_fromPQ_data_1[586]; endcase end - always@(sel__h51069 or m_pipeline$first) + always@(sel__h51068 or m_pipeline$first) begin - case (sel__h51069) + case (sel__h51068) 4'd0: - CASE_sel1069_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[31:0]; 4'd1: - CASE_sel1069_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[63:32]; 4'd2: - CASE_sel1069_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[95:64]; 4'd3: - CASE_sel1069_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[127:96]; 4'd4: - CASE_sel1069_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[159:128]; 4'd5: - CASE_sel1069_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[191:160]; 4'd6: - CASE_sel1069_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[223:192]; 4'd7: - CASE_sel1069_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[255:224]; 4'd8: - CASE_sel1069_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[287:256]; 4'd9: - CASE_sel1069_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[319:288]; 4'd10: - CASE_sel1069_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[351:320]; 4'd11: - CASE_sel1069_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[383:352]; 4'd12: - CASE_sel1069_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[415:384]; 4'd13: - CASE_sel1069_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[447:416]; 4'd14: - CASE_sel1069_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[479:448]; 4'd15: - CASE_sel1069_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = + CASE_sel1068_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 = m_pipeline$first[511:480]; endcase end diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkICRqMshrWrapper.v b/src_SSITH_P3/xilinx_ip/hdl/mkICRqMshrWrapper.v index 2222c94..c39a248 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkICRqMshrWrapper.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkICRqMshrWrapper.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:52:06 BST 2020 +// On Thu Jul 2 02:53:58 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkICoCache.v b/src_SSITH_P3/xilinx_ip/hdl/mkICoCache.v index e422da8..959f31b 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkICoCache.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkICoCache.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:52:12 BST 2020 +// On Thu Jul 2 02:54:04 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkIPRqMshrWrapper.v b/src_SSITH_P3/xilinx_ip/hdl/mkIPRqMshrWrapper.v index ac14188..7ead3ba 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkIPRqMshrWrapper.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkIPRqMshrWrapper.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:52:07 BST 2020 +// On Thu Jul 2 02:53:59 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkIPipeline.v b/src_SSITH_P3/xilinx_ip/hdl/mkIPipeline.v index 10408d7..dc3c7c5 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkIPipeline.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkIPipeline.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:52:09 BST 2020 +// On Thu Jul 2 02:54:02 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkITlb.v b/src_SSITH_P3/xilinx_ip/hdl/mkITlb.v index 3710d77..d0227f6 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkITlb.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkITlb.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:45:53 BST 2020 +// On Thu Jul 2 02:47:39 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkJtagTap.v b/src_SSITH_P3/xilinx_ip/hdl/mkJtagTap.v index 45ffba2..322715f 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkJtagTap.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkJtagTap.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 24 20:23:27 BST 2020 +// On Thu Jul 2 02:46:12 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkL2Tlb.v b/src_SSITH_P3/xilinx_ip/hdl/mkL2Tlb.v index 3233cfd..ca3cbd1 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkL2Tlb.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkL2Tlb.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:51:44 BST 2020 +// On Thu Jul 2 02:53:30 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkLLCache.v b/src_SSITH_P3/xilinx_ip/hdl/mkLLCache.v index 5507f55..b288a89 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkLLCache.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkLLCache.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:53:24 BST 2020 +// On Thu Jul 2 02:55:19 BST 2020 // // // Ports: @@ -1617,7 +1617,7 @@ module mkLLCache(CLK, cache_cRqMshrpipelineResp_getData_BITS_447_TO_ETC__q119, cache_cRqMshrpipelineResp_getData_BITS_511_TO_ETC__q120, cache_cRqMshrpipelineResp_getData_BITS_63_TO_0__q126, - rqAddr__h296735, + rqAddr__h296734, x_addr__h12321, x_addr__h74358; wire [62 : 0] IF_IF_SEL_ARR_cache_pipeline_first__466_BITS_5_ETC___d3416, @@ -2902,7 +2902,7 @@ module mkLLCache(CLK, cache_cRqMshr$sendRsToDmaC_getRq[2:0] } ; assign MUX_cache_toCQ_enqReq_lat_0$wset_1__VAL_2 = { 522'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, - rqAddr__h296735, + rqAddr__h296734, IF_SEL_ARR_cache_cRqMshr_sendRqToC_getSlot_IF__ETC___d2438, child__h296070 } ; assign MUX_cache_toMInfoQ$enq_1__VAL_1 = @@ -6125,7 +6125,7 @@ module mkLLCache(CLK, cache_rsToCIndexQ_deqP + 4'd1 ; assign next_deqP___1__h38335 = cache_toCQ_deqP + 1'd1 ; assign next_deqP___1__h4227 = cache_rqFromCQ_deqP + 1'd1 ; - assign rqAddr__h296735 = + assign rqAddr__h296734 = (cache_cRqMshr$sendRqToC_getState == 3'd3) ? cache_cRqMshr$sendRqToC_getRq[139:76] : { cache_cRqMshr$sendRqToC_getSlot[58:9], diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkLLPipeline.v b/src_SSITH_P3/xilinx_ip/hdl/mkLLPipeline.v index 83ecca8..6c7184a 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkLLPipeline.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkLLPipeline.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:53:12 BST 2020 +// On Thu Jul 2 02:55:08 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkLSQIssueLdQ.v b/src_SSITH_P3/xilinx_ip/hdl/mkLSQIssueLdQ.v index db276a1..8fc44de 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkLSQIssueLdQ.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkLSQIssueLdQ.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:50:07 BST 2020 +// On Thu Jul 2 02:51:56 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkLastLvCRqMshr.v b/src_SSITH_P3/xilinx_ip/hdl/mkLastLvCRqMshr.v index f45df3f..eb4b242 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkLastLvCRqMshr.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkLastLvCRqMshr.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:53:04 BST 2020 +// On Thu Jul 2 02:55:00 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkMMIOInst.v b/src_SSITH_P3/xilinx_ip/hdl/mkMMIOInst.v index 06e42bf..104987e 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkMMIOInst.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkMMIOInst.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:45:43 BST 2020 +// On Thu Jul 2 02:47:28 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkMemDispToRegFifo.v b/src_SSITH_P3/xilinx_ip/hdl/mkMemDispToRegFifo.v index e24d405..8a70870 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkMemDispToRegFifo.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkMemDispToRegFifo.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:52:24 BST 2020 +// On Thu Jul 2 02:54:18 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkMemLoader.v b/src_SSITH_P3/xilinx_ip/hdl/mkMemLoader.v index 29a9fce..ef6f348 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkMemLoader.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkMemLoader.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:52:39 BST 2020 +// On Thu Jul 2 02:54:36 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkMemRegToExeFifo.v b/src_SSITH_P3/xilinx_ip/hdl/mkMemRegToExeFifo.v index 1eddd77..592ff26 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkMemRegToExeFifo.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkMemRegToExeFifo.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:52:24 BST 2020 +// On Thu Jul 2 02:54:18 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkMinimumExecQ.v b/src_SSITH_P3/xilinx_ip/hdl/mkMinimumExecQ.v index 73c279c..77e09f9 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkMinimumExecQ.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkMinimumExecQ.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:53:38 BST 2020 +// On Thu Jul 2 02:55:35 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkMulExecQ.v b/src_SSITH_P3/xilinx_ip/hdl/mkMulExecQ.v index 083fbf2..1a460bb 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkMulExecQ.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkMulExecQ.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:53:50 BST 2020 +// On Thu Jul 2 02:55:47 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkNullTransCache.v b/src_SSITH_P3/xilinx_ip/hdl/mkNullTransCache.v index a4f6259..8625c0c 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkNullTransCache.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkNullTransCache.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:45:40 BST 2020 +// On Thu Jul 2 02:47:23 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkP3_Core.v b/src_SSITH_P3/xilinx_ip/hdl/mkP3_Core.v index ba7fb28..757a589 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkP3_Core.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkP3_Core.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jul 1 17:07:56 BST 2020 +// On Thu Jul 2 02:59:27 BST 2020 // // // Ports: @@ -1350,7 +1350,7 @@ module mkP3_Core(CLK, // rule RL_rl_ndm_reset_wait assign CAN_FIRE_RL_rl_ndm_reset_wait = (rg_ndm_reset_delay != 8'd1 || - corew$RDY_start && corew$RDY_ndm_reset_client_response_put) && + corew$RDY_ndm_reset_client_response_put && corew$RDY_start) && rg_ndm_reset_delay != 8'd0 ; assign WILL_FIRE_RL_rl_ndm_reset_wait = CAN_FIRE_RL_rl_ndm_reset_wait ; diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkPLIC_16_2_7.v b/src_SSITH_P3/xilinx_ip/hdl/mkPLIC_16_2_7.v index 6551d17..627cd77 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkPLIC_16_2_7.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkPLIC_16_2_7.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:45:12 BST 2020 +// On Thu Jul 2 02:46:53 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkPowerOnReset.v b/src_SSITH_P3/xilinx_ip/hdl/mkPowerOnReset.v index 1b21cdd..6dbfc0e 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkPowerOnReset.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkPowerOnReset.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 24 20:23:22 BST 2020 +// On Thu Jul 2 02:46:08 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkProc.v b/src_SSITH_P3/xilinx_ip/hdl/mkProc.v index 8129743..4eb9c68 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkProc.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkProc.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jul 1 17:07:33 BST 2020 +// On Thu Jul 2 02:59:06 BST 2020 // // // Ports: @@ -2005,7 +2005,7 @@ module mkProc(CLK, CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q24, CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q25, CASE_x22858_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q29, - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1970, + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1971, dword__h150359, ld_data__h188181, v_wdata__h215359, @@ -2034,9 +2034,9 @@ module mkProc(CLK, wire [519 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__561_THE_ETC___d1830; wire [517 : 0] IF_enqDst_1_0_lat_1_whas__634_THEN_enqDst_1_0__ETC___d1680; wire [515 : 0] IF_enqDst_1_0_lat_0_whas__637_THEN_enqDst_1_0__ETC___d1672, - IF_llc_axi4_adapter_rg_rd_rsp_beat_243_BIT_0_2_ETC___d2285, + IF_llc_axi4_adapter_rg_rd_rsp_beat_245_BIT_0_2_ETC___d2287, SEL_ARR_IF_propDstData_1_0_lat_0_whas__561_THE_ETC___d1825; - wire [383 : 0] IF_llc_mem_server_axi4_slave_xactor_shim_awff__ETC___d2018, + wire [383 : 0] IF_llc_mem_server_axi4_slave_xactor_shim_awff__ETC___d2019, SEL_ARR_IF_propDstData_1_0_lat_0_whas__561_THE_ETC___d1807; wire [129 : 0] IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_ETC___d1111, IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_ETC___d1164; @@ -2056,7 +2056,7 @@ module mkProc(CLK, wire [66 : 0] IF_NOT_core_0_mmioToPlatform_cRq_first__21_BIT_ETC___d546, IF_core_0_mmioToPlatform_cRq_first__21_BITS_21_ETC___d544; wire [65 : 0] mmio_axi4_adapter_f_rsps_to_core_first__291_BI_ETC___d1392; - wire [64 : 0] IF_llc_mem_server_propDstData_0_lat_0_whas__10_ETC___d2107; + wire [64 : 0] IF_llc_mem_server_propDstData_0_lat_0_whas__10_ETC___d2108; wire [63 : 0] IF_enqDst_1_0_lat_0_whas__637_THEN_enqDst_1_0__ETC___d1652, IF_mmioPlatform_fromHostQ_empty_80_OR_mmioPlat_ETC___d1159, IF_mmioPlatform_fromHostQ_empty_80_THEN_0_ELSE_ETC___d1157, @@ -2096,10 +2096,10 @@ module mkProc(CLK, IF_mmioPlatform_fetchingWay_363_THEN_mmioPlatf_ETC___d1389, amo_req_data__h39114, lower_data__h44520, - mmioPlatform_mtime_BITS_31_TO_0__q6, - mmioPlatform_mtime_BITS_63_TO_32__q5, - mmioPlatform_mtimecmp_0_BITS_31_TO_0__q8, - mmioPlatform_mtimecmp_0_BITS_63_TO_32__q7, + mmioPlatform_mtime_BITS_31_TO_0__q8, + mmioPlatform_mtime_BITS_63_TO_32__q7, + mmioPlatform_mtimecmp_0_BITS_31_TO_0__q6, + mmioPlatform_mtimecmp_0_BITS_63_TO_32__q5, upper_data__h44521, v__h44376, v__h44413, @@ -2153,8 +2153,8 @@ module mkProc(CLK, IF_enqDst_1_0_lat_0_whas__637_THEN_enqDst_1_0__ETC___d1642, IF_enqDst_1_0_lat_0_whas__637_THEN_enqDst_1_0__ETC___d1662, IF_enqDst_1_0_lat_0_whas__637_THEN_enqDst_1_0__ETC___d1678, - IF_llc_mem_server_enqDst_0_lat_0_whas__112_THE_ETC___d2117, - IF_llc_mem_server_propDstIdx_0_lat_0_whas__097_ETC___d2100, + IF_llc_mem_server_enqDst_0_lat_0_whas__113_THE_ETC___d2118, + IF_llc_mem_server_propDstIdx_0_lat_0_whas__098_ETC___d2101, IF_mmioPlatform_mtimecmp_0_99_ULE_IF_NOT_mmioP_ETC___d1038, IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_ETC___d819, IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_2_ETC___d1100, @@ -2174,9 +2174,9 @@ module mkProc(CLK, IF_propDstIdx_1_lat_0_whas__420_THEN_propDstId_ETC___d1423, NOT_enqDst_0_rl_445_BIT_73_446_451_AND_SEL_ARR_ETC___d1539, NOT_enqDst_1_0_rl_640_BIT_584_641_646_AND_SEL__ETC___d1836, - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239, - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2318, - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2321, + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241, + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2320, + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2323, NOT_mmioPlatform_curReq_97_BITS_66_TO_64_98_EQ_ETC___d1194, NOT_mmioPlatform_curReq_97_BITS_66_TO_64_98_EQ_ETC___d1289, NOT_mmioPlatform_curReq_97_BITS_66_TO_64_98_EQ_ETC___d1300, @@ -2191,6 +2191,7 @@ module mkProc(CLK, NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d993, SEL_ARR_IF_propDstIdx_0_lat_0_whas__413_THEN_p_ETC___d1481, SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__546_THEN_ETC___d1714, + _dand1mmio_axi4_adapter_f_reqs_from_core$EN_deq, _theResult____h13492, core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d523, core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d525, @@ -2203,9 +2204,9 @@ module mkProc(CLK, core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d781, core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d788, core_0_mmioToPlatform_cRq_notEmpty__07_AND_cor_ETC___d764, - llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2250, - llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2036, - llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1935, + llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2252, + llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2037, + llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1936, mmioPlatform_amoWaitWriteResp_304_OR_core_0_RD_ETC___d1307, mmioPlatform_cycle_90_ULT_99___d491, mmioPlatform_fetchingWay_363_ULT_mmioPlatform__ETC___d1372, @@ -2230,6 +2231,7 @@ module mkProc(CLK, mmio_axi4_adapter_f_reqs_from_core_i_notEmpty__ETC___d8, mmio_axi4_adapter_read_req_addr_79_BIT_3_80_PL_ETC___d181, mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ax_ETC___d217, + whichHalf___1__h15055, x__h100756, x__h10399, x__h116294, @@ -3001,36 +3003,32 @@ module mkProc(CLK, // rule RL_sendPRq assign CAN_FIRE_RL_sendPRq = + llc$RDY_to_child_toC_first && llc$RDY_to_child_toC_deq && core_0$RDY_dCacheToParent_fromP_enq && - llc$RDY_to_child_toC_deq && - llc$RDY_to_child_toC_first && !llc$to_child_toC_first[587] && !llc$to_child_toC_first[0] ; assign WILL_FIRE_RL_sendPRq = CAN_FIRE_RL_sendPRq ; // rule RL_sendPRs assign CAN_FIRE_RL_sendPRs = + llc$RDY_to_child_toC_first && llc$RDY_to_child_toC_deq && core_0$RDY_dCacheToParent_fromP_enq && - llc$RDY_to_child_toC_deq && - llc$RDY_to_child_toC_first && llc$to_child_toC_first[587] && !llc$to_child_toC_first[520] ; assign WILL_FIRE_RL_sendPRs = CAN_FIRE_RL_sendPRs ; // rule RL_sendPRq_1 assign CAN_FIRE_RL_sendPRq_1 = + llc$RDY_to_child_toC_first && llc$RDY_to_child_toC_deq && core_0$RDY_iCacheToParent_fromP_enq && - llc$RDY_to_child_toC_deq && - llc$RDY_to_child_toC_first && !llc$to_child_toC_first[587] && llc$to_child_toC_first[0] ; assign WILL_FIRE_RL_sendPRq_1 = CAN_FIRE_RL_sendPRq_1 ; // rule RL_sendPRs_1 assign CAN_FIRE_RL_sendPRs_1 = + llc$RDY_to_child_toC_first && llc$RDY_to_child_toC_deq && core_0$RDY_iCacheToParent_fromP_enq && - llc$RDY_to_child_toC_deq && - llc$RDY_to_child_toC_first && llc$to_child_toC_first[587] && llc$to_child_toC_first[520] ; assign WILL_FIRE_RL_sendPRs_1 = CAN_FIRE_RL_sendPRs_1 ; @@ -3370,7 +3368,7 @@ module mkProc(CLK, // rule RL_llc_mem_server_rl_cacheline_cache_writeback_finish assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish = - llc$RDY_dma_respSt_deq && llc$RDY_dma_respSt_first && + llc$RDY_dma_respSt_first && llc$RDY_dma_respSt_deq && !llc$dma_respSt_first[4] && llc_mem_server_rg_cacheline_cache_state == 3'd1 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish = @@ -3378,7 +3376,7 @@ module mkProc(CLK, // rule RL_llc_mem_server_rl_cacheline_cache_reload_finish assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish = - llc$RDY_dma_respLd_deq && llc$RDY_dma_respLd_first && + llc$RDY_dma_respLd_first && llc$RDY_dma_respLd_deq && !llc$dma_respLd_first[4] && llc_mem_server_rg_cacheline_cache_state == 3'd2 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish = @@ -3399,21 +3397,21 @@ module mkProc(CLK, // rule RL_llc_mem_server_doEnq assign CAN_FIRE_RL_llc_mem_server_doEnq = llc_mem_server_tlbQ$FULL_N && - IF_llc_mem_server_enqDst_0_lat_0_whas__112_THE_ETC___d2117 ; + IF_llc_mem_server_enqDst_0_lat_0_whas__113_THE_ETC___d2118 ; assign WILL_FIRE_RL_llc_mem_server_doEnq = CAN_FIRE_RL_llc_mem_server_doEnq ; // rule RL_llc_mem_server_sendLdRespToTlb assign CAN_FIRE_RL_llc_mem_server_sendLdRespToTlb = - core_0$RDY_tlbToMem_respLd_enq && llc$RDY_dma_respLd_deq && - llc$RDY_dma_respLd_first && + llc$RDY_dma_respLd_first && llc$RDY_dma_respLd_deq && + core_0$RDY_tlbToMem_respLd_enq && llc$dma_respLd_first[4] ; assign WILL_FIRE_RL_llc_mem_server_sendLdRespToTlb = CAN_FIRE_RL_llc_mem_server_sendLdRespToTlb ; // rule RL_llc_mem_server_sendStRespToTlb assign CAN_FIRE_RL_llc_mem_server_sendStRespToTlb = - llc$RDY_dma_respSt_deq && llc$RDY_dma_respSt_first && + llc$RDY_dma_respSt_first && llc$RDY_dma_respSt_deq && llc$dma_respSt_first[4] ; assign WILL_FIRE_RL_llc_mem_server_sendStRespToTlb = CAN_FIRE_RL_llc_mem_server_sendStRespToTlb ; @@ -3467,7 +3465,7 @@ module mkProc(CLK, !llc_mem_server_axi4_slave_xactor_shim_rff_rv[73] && (llc_mem_server_rg_cacheline_cache_state == 3'd3 || llc_mem_server_rg_cacheline_cache_state == 3'd4) && - llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2036 ; + llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2037 ; assign WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req = CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req ; @@ -3479,7 +3477,7 @@ module mkProc(CLK, !llc_mem_server_axi4_slave_xactor_shim_bff_rv[7] && (llc_mem_server_rg_cacheline_cache_state == 3'd3 || llc_mem_server_rg_cacheline_cache_state == 3'd4) && - llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1935 ; + llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1936 ; assign WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req = CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req && !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged ; @@ -3498,7 +3496,7 @@ module mkProc(CLK, !llc_mem_server_axi4_slave_xactor_clearing && llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[98] && llc_mem_server_rg_cacheline_cache_state == 3'd4 && - !llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1935 ; + !llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1936 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss && !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged ; @@ -3509,7 +3507,7 @@ module mkProc(CLK, !llc_mem_server_axi4_slave_xactor_clearing && llc_mem_server_axi4_slave_xactor_shim_arff_rv$port1__read[98] && llc_mem_server_rg_cacheline_cache_state == 3'd4 && - !llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2036 ; + !llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2037 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss && !WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req && @@ -3522,7 +3520,7 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[98] && llc$RDY_dma_memReq_enq && llc_mem_server_rg_cacheline_cache_state == 3'd3 && - !llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1935 ; + !llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1936 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ; @@ -3532,7 +3530,7 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_shim_arff_rv$port1__read[98] && llc$RDY_dma_memReq_enq && llc_mem_server_rg_cacheline_cache_state == 3'd3 && - !llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2036 ; + !llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2037 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld && !WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req && @@ -3623,8 +3621,8 @@ module mkProc(CLK, // rule RL_llc_axi4_adapter_rl_handle_read_req assign CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req = !llc_axi4_adapter_master_xactor_clearing && - llc$RDY_to_mem_toM_deq && llc$RDY_to_mem_toM_first && + llc$RDY_to_mem_toM_deq && !llc_axi4_adapter_master_xactor_shim_arff_rv[98] && llc_axi4_adapter_f_pending_reads$FULL_N && !llc$to_mem_toM_first[644] && @@ -3731,7 +3729,7 @@ module mkProc(CLK, // rule RL_llc_axi4_adapter_rl_handle_read_rsps assign CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps = !llc_axi4_adapter_master_xactor_clearing && - llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2250 ; + llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2252 ; assign WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps ; @@ -3925,7 +3923,7 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:33] != 2'd0 && llc_mem_server_rg_cacheline_cache_data[512], - IF_llc_mem_server_axi4_slave_xactor_shim_awff__ETC___d2018, + IF_llc_mem_server_axi4_slave_xactor_shim_awff__ETC___d2019, (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32] == 3'd1) ? data__h140632 : @@ -4128,10 +4126,10 @@ module mkProc(CLK, !llc_mem_server_axi4_slave_xactor_shim_arff_rv[98] ; assign llc_mem_server_propDstIdx_0_lat_1$whas = !llc_mem_server_enqDst_0_rl[65] && - IF_llc_mem_server_propDstIdx_0_lat_0_whas__097_ETC___d2100 ; + IF_llc_mem_server_propDstIdx_0_lat_0_whas__098_ETC___d2101 ; assign llc_mem_server_enqDst_0_lat_0$wget = { 1'd1, - IF_llc_mem_server_propDstData_0_lat_0_whas__10_ETC___d2107 } ; + IF_llc_mem_server_propDstData_0_lat_0_whas__10_ETC___d2108 } ; assign llc_axi4_adapter_master_xactor_master_bSynth_snk_putWire$wget = { master0_bid, master0_bresp } ; assign llc_axi4_adapter_master_xactor_master_bSynth_snk_putWire$whas = @@ -4346,7 +4344,7 @@ module mkProc(CLK, EN_hart0_put_other_req_put ? hart0_put_other_req_put : set_verbosity_verbosity ; - assign cfg_verbosity$EN = EN_hart0_put_other_req_put || EN_set_verbosity ; + assign cfg_verbosity$EN = EN_set_verbosity || EN_hart0_put_other_req_put ; // register enqDst_0_rl assign enqDst_0_rl$D_IN = @@ -4407,7 +4405,7 @@ module mkProc(CLK, // register llc_axi4_adapter_rg_cline assign llc_axi4_adapter_rg_cline$D_IN = - IF_llc_axi4_adapter_rg_rd_rsp_beat_243_BIT_0_2_ETC___d2285 ; + IF_llc_axi4_adapter_rg_rd_rsp_beat_245_BIT_0_2_ETC___d2287 ; assign llc_axi4_adapter_rg_cline$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps ; @@ -4456,7 +4454,7 @@ module mkProc(CLK, // register llc_mem_server_enqDst_0_rl assign llc_mem_server_enqDst_0_rl$D_IN = { !CAN_FIRE_RL_llc_mem_server_doEnq && - IF_llc_mem_server_enqDst_0_lat_0_whas__112_THE_ETC___d2117, + IF_llc_mem_server_enqDst_0_lat_0_whas__113_THE_ETC___d2118, CAN_FIRE_RL_llc_mem_server_doEnq ? 65'h0AAAAAAAAAAAAAAAA : (llc_mem_server_propDstIdx_0_lat_1$whas ? @@ -4466,13 +4464,13 @@ module mkProc(CLK, // register llc_mem_server_propDstData_0_rl assign llc_mem_server_propDstData_0_rl$D_IN = - IF_llc_mem_server_propDstData_0_lat_0_whas__10_ETC___d2107 ; + IF_llc_mem_server_propDstData_0_lat_0_whas__10_ETC___d2108 ; assign llc_mem_server_propDstData_0_rl$EN = 1'd1 ; // register llc_mem_server_propDstIdx_0_rl assign llc_mem_server_propDstIdx_0_rl$D_IN = !llc_mem_server_propDstIdx_0_lat_1$whas && - IF_llc_mem_server_propDstIdx_0_lat_0_whas__097_ETC___d2100 ; + IF_llc_mem_server_propDstIdx_0_lat_0_whas__098_ETC___d2101 ; assign llc_mem_server_propDstIdx_0_rl$EN = 1'd1 ; // register llc_mem_server_rg_cacheline_cache_addr @@ -4859,7 +4857,7 @@ module mkProc(CLK, // register mmio_axi4_adapter_rg_wr_req_beat assign mmio_axi4_adapter_rg_wr_req_beat$D_IN = - mmio_axi4_adapter_f_reqs_from_core$D_OUT[136:129] != 8'd0 && + !whichHalf___1__h15055 && mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] != 8'd0 && !mmio_axi4_adapter_rg_wr_req_beat && x__h17610 ; @@ -5190,7 +5188,7 @@ module mkProc(CLK, IF_enqDst_1_0_lat_0_whas__637_THEN_enqDst_1_0__ETC___d1672, IF_enqDst_1_0_lat_0_whas__637_THEN_enqDst_1_0__ETC___d1678 } ; assign llc$to_mem_rsFromM_enq_x = - { IF_llc_axi4_adapter_rg_rd_rsp_beat_243_BIT_0_2_ETC___d2285, + { IF_llc_axi4_adapter_rg_rd_rsp_beat_245_BIT_0_2_ETC___d2287, llc_axi4_adapter_f_pending_reads$D_OUT[4:0] } ; assign llc$EN_to_child_rsFromC_enq = CAN_FIRE_RL_doEnq_1 ; assign llc$EN_to_child_rqFromC_enq = CAN_FIRE_RL_doEnq ; @@ -5283,11 +5281,7 @@ module mkProc(CLK, WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req || WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req ; assign mmio_axi4_adapter_f_reqs_from_core$DEQ = - WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && - (mmio_axi4_adapter_f_reqs_from_core$D_OUT[136:129] == 8'd0 || - mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] == 8'd0 || - mmio_axi4_adapter_rg_wr_req_beat || - !mmio_axi4_adapter_soc_map$m_is_IO_addr) || + _dand1mmio_axi4_adapter_f_reqs_from_core$EN_deq || WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St || WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req ; assign mmio_axi4_adapter_f_reqs_from_core$CLR = 1'b0 ; @@ -5370,7 +5364,7 @@ module mkProc(CLK, assign mmio_axi4_adapter_master_shim_wff$D_IN = { wflit_wdata__h17678, wflit_wstrb__h17679, - mmio_axi4_adapter_f_reqs_from_core$D_OUT[136:129] == 8'd0 || + whichHalf___1__h15055 || mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] == 8'd0 || mmio_axi4_adapter_rg_wr_req_beat, 1'd0 } ; @@ -5611,14 +5605,14 @@ module mkProc(CLK, 2'b10 : IF_enqDst_1_0_lat_0_whas__637_THEN_enqDst_1_0__ETC___d1657, IF_enqDst_1_0_lat_1_whas__634_THEN_enqDst_1_0__ETC___d1680 } ; - assign IF_llc_axi4_adapter_rg_rd_rsp_beat_243_BIT_0_2_ETC___d2285 = + assign IF_llc_axi4_adapter_rg_rd_rsp_beat_245_BIT_0_2_ETC___d2287 = { llc_axi4_adapter_rg_rd_rsp_beat[0] ? llc_axi4_adapter_rg_cline[515:512] : { llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[0], llc_axi4_adapter_rg_cline[515:513] }, llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[67:4], llc_axi4_adapter_rg_cline[511:64] } ; - assign IF_llc_mem_server_axi4_slave_xactor_shim_awff__ETC___d2018 = + assign IF_llc_mem_server_axi4_slave_xactor_shim_awff__ETC___d2019 = { (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32] == 3'd7) ? data__h140632 : @@ -5643,15 +5637,15 @@ module mkProc(CLK, 3'd2) ? data__h140632 : llc_mem_server_rg_cacheline_cache_data[191:128] } ; - assign IF_llc_mem_server_enqDst_0_lat_0_whas__112_THE_ETC___d2117 = + assign IF_llc_mem_server_enqDst_0_lat_0_whas__113_THE_ETC___d2118 = llc_mem_server_propDstIdx_0_lat_1$whas ? llc_mem_server_enqDst_0_lat_0$wget[65] : llc_mem_server_enqDst_0_rl[65] ; - assign IF_llc_mem_server_propDstData_0_lat_0_whas__10_ETC___d2107 = + assign IF_llc_mem_server_propDstData_0_lat_0_whas__10_ETC___d2108 = CAN_FIRE_RL_llc_mem_server_srcPropose ? core_0$tlbToMem_memReq_first : llc_mem_server_propDstData_0_rl ; - assign IF_llc_mem_server_propDstIdx_0_lat_0_whas__097_ETC___d2100 = + assign IF_llc_mem_server_propDstIdx_0_lat_0_whas__098_ETC___d2101 = CAN_FIRE_RL_llc_mem_server_srcPropose || llc_mem_server_propDstIdx_0_rl ; assign IF_mmioPlatform_fetchingWay_363_THEN_mmioPlatf_ETC___d1389 = @@ -5696,16 +5690,16 @@ module mkProc(CLK, mmioPlatform_reqData[63:0]) ; assign IF_mmioPlatform_reqBE_05_BIT_4_06_THEN_SEXT_mm_ETC___d1054 = mmioPlatform_reqBE[4] ? - { {32{mmioPlatform_mtime_BITS_63_TO_32__q5[31]}}, - mmioPlatform_mtime_BITS_63_TO_32__q5 } : - { {32{mmioPlatform_mtime_BITS_31_TO_0__q6[31]}}, - mmioPlatform_mtime_BITS_31_TO_0__q6 } ; + { {32{mmioPlatform_mtime_BITS_63_TO_32__q7[31]}}, + mmioPlatform_mtime_BITS_63_TO_32__q7 } : + { {32{mmioPlatform_mtime_BITS_31_TO_0__q8[31]}}, + mmioPlatform_mtime_BITS_31_TO_0__q8 } ; assign IF_mmioPlatform_reqBE_05_BIT_4_06_THEN_SEXT_mm_ETC___d981 = mmioPlatform_reqBE[4] ? - { {32{mmioPlatform_mtimecmp_0_BITS_63_TO_32__q7[31]}}, - mmioPlatform_mtimecmp_0_BITS_63_TO_32__q7 } : - { {32{mmioPlatform_mtimecmp_0_BITS_31_TO_0__q8[31]}}, - mmioPlatform_mtimecmp_0_BITS_31_TO_0__q8 } ; + { {32{mmioPlatform_mtimecmp_0_BITS_63_TO_32__q5[31]}}, + mmioPlatform_mtimecmp_0_BITS_63_TO_32__q5 } : + { {32{mmioPlatform_mtimecmp_0_BITS_31_TO_0__q6[31]}}, + mmioPlatform_mtimecmp_0_BITS_31_TO_0__q6 } ; assign IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_ETC___d1111 = (mmioPlatform_reqFunc[5:4] == 2'd0) ? 130'h2AAAAAAAAAAAAAAA955555554AAAAAAAA : @@ -5782,7 +5776,7 @@ module mkProc(CLK, assign IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d206 = mmio_axi4_adapter_soc_map$m_is_IO_addr ? mmio_axi4_adapter_master_shim_wff$FULL_N && - (mmio_axi4_adapter_f_reqs_from_core$D_OUT[136:129] != 8'd0 && + (!whichHalf___1__h15055 && mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] != 8'd0 && mmio_axi4_adapter_rg_wr_req_beat || mmio_axi4_adapter_master_shim_awff$FULL_N) : @@ -5835,15 +5829,15 @@ module mkProc(CLK, (SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__546_THEN_ETC___d1710 ? !srcRR_1_0 : IF_propDstIdx_1_0_lat_0_whas__546_THEN_propDst_ETC___d1549) ; - assign NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239 = + assign NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241 = llc_axi4_adapter_cfg_verbosity > 4'd1 ; - assign NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2318 = - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239 && + assign NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2320 = + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241 && (llc_axi4_adapter_rg_rd_rsp_beat[0] ? !llc_axi4_adapter_rg_cline[515] : !llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[0]) ; - assign NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2321 = - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239 && + assign NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2323 = + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241 && (llc_axi4_adapter_rg_rd_rsp_beat[0] ? llc_axi4_adapter_rg_cline[515] : llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[0]) ; @@ -5997,12 +5991,18 @@ module mkProc(CLK, (IF_propDstIdx_1_0_lat_0_whas__546_THEN_NOT_pro_ETC___d1712 ? IF_propDstIdx_1_1_lat_0_whas__553_THEN_propDst_ETC___d1556 : IF_propDstIdx_1_0_lat_0_whas__546_THEN_propDst_ETC___d1549) ; + assign _dand1mmio_axi4_adapter_f_reqs_from_core$EN_deq = + WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && + (whichHalf___1__h15055 || + mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] == 8'd0 || + mmio_axi4_adapter_rg_wr_req_beat || + !mmio_axi4_adapter_soc_map$m_is_IO_addr) ; assign _theResult_____1_awsize_val__h17116 = (x__h15143 + y__h15144 <= 5'd4) ? 3'b010 : 3'b011 ; assign _theResult____h13492 = - (mmio_axi4_adapter_f_reqs_from_core$D_OUT[136:129] == 8'd0 || + (whichHalf___1__h15055 || mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] == 8'd0) ? - mmio_axi4_adapter_f_reqs_from_core$D_OUT[136:129] == 8'd0 : + whichHalf___1__h15055 : mmio_axi4_adapter_rg_wr_req_beat ; assign addr1__h90533 = { mmioPlatform_curReq[63:3], 3'b0 } ; assign amo_req_data__h39114 = @@ -6077,28 +6077,28 @@ module mkProc(CLK, assign data__h140632 = { llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[9] ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[73:66] : - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1970[63:56], + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1971[63:56], llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[8] ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[65:58] : - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1970[55:48], + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1971[55:48], llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[7] ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[57:50] : - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1970[47:40], + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1971[47:40], llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[6] ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[49:42] : - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1970[39:32], + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1971[39:32], llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[5] ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[41:34] : - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1970[31:24], + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1971[31:24], llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[4] ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[33:26] : - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1970[23:16], + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1971[23:16], llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[3] ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[25:18] : - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1970[15:8], + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1971[15:8], llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[2] ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[17:10] : - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1970[7:0] } ; + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1971[7:0] } ; assign failed_testnum__h223734 = { 1'd0, mmioPlatform_toHostQ_data_0[63:1] } ; assign line_addr__h140065 = @@ -6112,16 +6112,16 @@ module mkProc(CLK, llc_axi4_adapter_master_xactor_shim_arff_rv$port1__read[97:0] ; assign llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q32 = llc_axi4_adapter_master_xactor_shim_awff_rv$port1__read[97:0] ; - assign llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2250 = + assign llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2252 = llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[73] && (llc_axi4_adapter_rg_rd_rsp_beat != 3'd7 || llc$RDY_to_mem_rsFromM_enq && llc_axi4_adapter_f_pending_reads$EMPTY_N) ; assign llc_axi4_adapter_master_xactor_shim_wff_rvpor_ETC__q33 = llc_axi4_adapter_master_xactor_shim_wff_rv$port1__read[73:0] ; - assign llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2036 = + assign llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2037 = line_addr__h150176 == llc_mem_server_rg_cacheline_cache_addr ; - assign llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1935 = + assign llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1936 = line_addr__h140065 == llc_mem_server_rg_cacheline_cache_addr ; assign llc_mem_server_axi4_slave_xactor_shim_bff_rvp_ETC__q30 = llc_mem_server_axi4_slave_xactor_shim_bff_rv$port1__read[6:0] ; @@ -6130,7 +6130,7 @@ module mkProc(CLK, assign lower_data__h44520 = mmioPlatform_waitLowerMSIPCRs ? v__h44413 : 32'd0 ; assign mem_req_rd_addr_arlen__h5411 = - (mmio_axi4_adapter_f_reqs_from_core$D_OUT[136:129] != 8'd0 && + (!whichHalf___1__h15055 && mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] != 8'd0) ? 8'd1 : 8'd0 ; @@ -6142,16 +6142,16 @@ module mkProc(CLK, assign mmioPlatform_cycle_90_ULT_99___d491 = mmioPlatform_cycle < 7'd99 ; assign mmioPlatform_fetchingWay_363_ULT_mmioPlatform__ETC___d1372 = mmioPlatform_fetchingWay < mmioPlatform_reqFunc[0] ; - assign mmioPlatform_mtime_BITS_31_TO_0__q6 = mmioPlatform_mtime[31:0] ; - assign mmioPlatform_mtime_BITS_63_TO_32__q5 = mmioPlatform_mtime[63:32] ; + assign mmioPlatform_mtime_BITS_31_TO_0__q8 = mmioPlatform_mtime[31:0] ; + assign mmioPlatform_mtime_BITS_63_TO_32__q7 = mmioPlatform_mtime[63:32] ; assign mmioPlatform_mtime__h59831 = mmioPlatform_mtime ; assign mmioPlatform_mtimecmp_0_99_ULE_IF_NOT_mmioPlat_ETC___d1029 = mmioPlatform_mtimecmp_0 <= newData__h53320 ; assign mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500 = mmioPlatform_mtimecmp_0 <= mmioPlatform_mtime ; - assign mmioPlatform_mtimecmp_0_BITS_31_TO_0__q8 = + assign mmioPlatform_mtimecmp_0_BITS_31_TO_0__q6 = mmioPlatform_mtimecmp_0[31:0] ; - assign mmioPlatform_mtimecmp_0_BITS_63_TO_32__q7 = + assign mmioPlatform_mtimecmp_0_BITS_63_TO_32__q5 = mmioPlatform_mtimecmp_0[63:32] ; assign mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d584 = (mmioPlatform_mtip_0 || @@ -6275,12 +6275,12 @@ module mkProc(CLK, (IF_NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03__ETC___d957 || !mmioPlatform_mtip_0) ; assign mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253 = - (mmio_axi4_adapter_f_reqs_from_core$D_OUT[136:129] == 8'd0 || + (whichHalf___1__h15055 || mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] == 8'd0 || !mmio_axi4_adapter_rg_wr_req_beat) && mmio_axi4_adapter_cfg_verbosity != 4'd0 ; assign mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d259 = - (mmio_axi4_adapter_f_reqs_from_core$D_OUT[136:129] == 8'd0 || + (whichHalf___1__h15055 || mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] == 8'd0 || !mmio_axi4_adapter_rg_wr_req_beat) && mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15 ; @@ -6310,7 +6310,7 @@ module mkProc(CLK, mmio_axi4_adapter_master_shim_rff$D_OUT[67:4] } } ; assign mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ax_ETC___d217 = mmio_axi4_adapter_soc_map$m_is_IO_addr && - (mmio_axi4_adapter_f_reqs_from_core$D_OUT[136:129] == 8'd0 || + (whichHalf___1__h15055 || mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] == 8'd0 || !mmio_axi4_adapter_rg_wr_req_beat) ; assign newData__h45219 = @@ -6331,6 +6331,8 @@ module mkProc(CLK, assign v__h44413 = { 31'd0, core_0$mmioToPlatform_cRs_first } ; assign v_awaddr__h214948 = { llc$to_mem_toM_first[643:586], 6'h0 } ; assign value__h61538 = mmioPlatform_mtimecmp_0 ; + assign whichHalf___1__h15055 = + mmio_axi4_adapter_f_reqs_from_core$D_OUT[136:129] == 8'd0 ; assign x__h100756 = SEL_ARR_IF_propDstIdx_0_lat_0_whas__413_THEN_p_ETC___d1477 ? srcRR_0 : @@ -7061,28 +7063,28 @@ module mkProc(CLK, begin case (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32]) 3'd0: - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1970 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1971 = llc_mem_server_rg_cacheline_cache_data[63:0]; 3'd1: - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1970 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1971 = llc_mem_server_rg_cacheline_cache_data[127:64]; 3'd2: - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1970 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1971 = llc_mem_server_rg_cacheline_cache_data[191:128]; 3'd3: - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1970 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1971 = llc_mem_server_rg_cacheline_cache_data[255:192]; 3'd4: - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1970 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1971 = llc_mem_server_rg_cacheline_cache_data[319:256]; 3'd5: - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1970 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1971 = llc_mem_server_rg_cacheline_cache_data[383:320]; 3'd6: - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1970 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1971 = llc_mem_server_rg_cacheline_cache_data[447:384]; 3'd7: - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1970 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1971 = llc_mem_server_rg_cacheline_cache_data[511:448]; endcase end @@ -8348,7 +8350,7 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0 && - mmio_axi4_adapter_f_reqs_from_core$D_OUT[136:129] != 8'd0 && + !whichHalf___1__h15055 && mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] != 8'd0 && !mmio_axi4_adapter_rg_wr_req_beat) $write("False"); @@ -8356,7 +8358,7 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0 && - (mmio_axi4_adapter_f_reqs_from_core$D_OUT[136:129] == 8'd0 || + (whichHalf___1__h15055 || mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] == 8'd0 || mmio_axi4_adapter_rg_wr_req_beat)) $write("True"); @@ -8375,10 +8377,10 @@ module mkProc(CLK, mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) $write("first: %d, last: %d, whichHalf: %d", - mmio_axi4_adapter_f_reqs_from_core$D_OUT[136:129] == 8'd0 || + whichHalf___1__h15055 || mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] == 8'd0 || !mmio_axi4_adapter_rg_wr_req_beat, - mmio_axi4_adapter_f_reqs_from_core$D_OUT[136:129] == 8'd0 || + whichHalf___1__h15055 || mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] == 8'd0 || mmio_axi4_adapter_rg_wr_req_beat, _theResult____h13492, @@ -13393,103 +13395,103 @@ module mkProc(CLK, $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write("AXI4_ARFlit { ", "arid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write("'h%h", 5'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write(", ", "araddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write("'h%h", line_addr__h193455); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write(", ", "arlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write("'h%h", 8'd7); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write(", ", "arsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write("AXI4_Size { ", "val: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write("'h%h", 3'b011, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write(", ", "arburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write("INCR"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write(", ", "arlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write("NORMAL"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write(", ", "arcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write("'h%h", 4'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write(", ", "arprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write("'h%h", 3'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write(", ", "arqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write(", ", "arregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write(", ", "aruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_awSynth_src_warnDoDrop) @@ -13570,7 +13572,7 @@ module mkProc(CLK, $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) begin v__h193908 = $stime; #0; @@ -13578,54 +13580,54 @@ module mkProc(CLK, v__h193902 = v__h193908 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsps: beat %0d ", v__h193902, llc_axi4_adapter_rg_rd_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write("AXI4_RFlit { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write("'h%h", llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[72:68]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write("'h%h", llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[67:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239 && + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241 && llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] == 2'd0) $write("OKAY"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239 && + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241 && llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] == 2'd1) $write("EXOKAY"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239 && + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241 && llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] == 2'd2) $write("SLVERR"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239 && + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241 && llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != 2'd0 && llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != @@ -13634,31 +13636,31 @@ module mkProc(CLK, $write("DECERR"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239 && + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241 && llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239 && + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241 && !llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write("'h%h", llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[0], " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && @@ -13752,27 +13754,27 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write(" Response to LLC: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write("MemRsMsg { ", "data: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write("CLine { ", "tag: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write(", ", "data: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write(" >"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write(" }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write(", ", "child: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write(", ", "id: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write("LdMemRqId { ", "refill: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239 && + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241 && llc_axi4_adapter_f_pending_reads$D_OUT[4]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239 && + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241 && !llc_axi4_adapter_f_pending_reads$D_OUT[4]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write(", ", "mshrIdx: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write("'h%h", llc_axi4_adapter_f_pending_reads$D_OUT[3:0], " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write(" }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__224_U_ETC___d2239) + NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) $write("\n"); end // synopsys translate_on diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkRFileSynth.v b/src_SSITH_P3/xilinx_ip/hdl/mkRFileSynth.v index 1a008f5..14f529a 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkRFileSynth.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkRFileSynth.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:48:58 BST 2020 +// On Thu Jul 2 02:50:45 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkRas.v b/src_SSITH_P3/xilinx_ip/hdl/mkRas.v index b6d433b..b82bda2 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkRas.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkRas.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:50:02 BST 2020 +// On Thu Jul 2 02:51:50 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkRegRenamingTable.v b/src_SSITH_P3/xilinx_ip/hdl/mkRegRenamingTable.v index eff8e9c..28f6fa9 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkRegRenamingTable.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkRegRenamingTable.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:46:31 BST 2020 +// On Thu Jul 2 02:48:17 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkReorderBufferSynth.v b/src_SSITH_P3/xilinx_ip/hdl/mkReorderBufferSynth.v index c74409b..985acb0 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkReorderBufferSynth.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkReorderBufferSynth.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:49:39 BST 2020 +// On Thu Jul 2 02:51:26 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkReservationStationAlu.v b/src_SSITH_P3/xilinx_ip/hdl/mkReservationStationAlu.v index a13a7e4..b7407ae 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkReservationStationAlu.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkReservationStationAlu.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:54:23 BST 2020 +// On Thu Jul 2 02:57:11 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkReservationStationFpuMulDiv.v b/src_SSITH_P3/xilinx_ip/hdl/mkReservationStationFpuMulDiv.v index 80c922e..83272b2 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkReservationStationFpuMulDiv.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkReservationStationFpuMulDiv.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:49:52 BST 2020 +// On Thu Jul 2 02:51:40 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkReservationStationMem.v b/src_SSITH_P3/xilinx_ip/hdl/mkReservationStationMem.v index f9b935e..633751c 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkReservationStationMem.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkReservationStationMem.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:49:47 BST 2020 +// On Thu Jul 2 02:51:35 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkRobRowSynth.v b/src_SSITH_P3/xilinx_ip/hdl/mkRobRowSynth.v index b94cd19..a72426d 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkRobRowSynth.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkRobRowSynth.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:49:08 BST 2020 +// On Thu Jul 2 02:50:55 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkScoreboardAggr.v b/src_SSITH_P3/xilinx_ip/hdl/mkScoreboardAggr.v index f3160ac..c357f95 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkScoreboardAggr.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkScoreboardAggr.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jul 1 17:05:30 BST 2020 +// On Thu Jul 2 02:53:09 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkScoreboardCons.v b/src_SSITH_P3/xilinx_ip/hdl/mkScoreboardCons.v index 0161f17..9ad03e7 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkScoreboardCons.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkScoreboardCons.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jul 1 17:05:23 BST 2020 +// On Thu Jul 2 02:53:02 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkSimpleRespQ.v b/src_SSITH_P3/xilinx_ip/hdl/mkSimpleRespQ.v index 731cdc5..b36ae0d 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkSimpleRespQ.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkSimpleRespQ.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:53:38 BST 2020 +// On Thu Jul 2 02:55:35 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkSoC_Map.v b/src_SSITH_P3/xilinx_ip/hdl/mkSoC_Map.v index aff3d1b..cbc1583 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkSoC_Map.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkSoC_Map.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:45:07 BST 2020 +// On Thu Jul 2 02:46:48 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkSpecTagManager.v b/src_SSITH_P3/xilinx_ip/hdl/mkSpecTagManager.v index 2118078..36346da 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkSpecTagManager.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkSpecTagManager.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:48:49 BST 2020 +// On Thu Jul 2 02:50:35 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkSplitLSQ.v b/src_SSITH_P3/xilinx_ip/hdl/mkSplitLSQ.v index e135a28..bdfba73 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkSplitLSQ.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkSplitLSQ.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:50:45 BST 2020 +// On Thu Jul 2 02:52:33 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkSplitTransCache.v b/src_SSITH_P3/xilinx_ip/hdl/mkSplitTransCache.v index 077739d..e5190dc 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkSplitTransCache.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkSplitTransCache.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:45:39 BST 2020 +// On Thu Jul 2 02:47:22 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkStoreBufferEhr.v b/src_SSITH_P3/xilinx_ip/hdl/mkStoreBufferEhr.v index da5e7b0..fa7c126 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkStoreBufferEhr.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkStoreBufferEhr.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:46:04 BST 2020 +// On Thu Jul 2 02:47:50 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkSyncBramFifo_w36_d512.v b/src_SSITH_P3/xilinx_ip/hdl/mkSyncBramFifo_w36_d512.v index 3570f20..89d0978 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkSyncBramFifo_w36_d512.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkSyncBramFifo_w36_d512.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 24 20:31:55 BST 2020 +// On Thu Jul 2 02:54:30 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkSyncFifo_w32_d16.v b/src_SSITH_P3/xilinx_ip/hdl/mkSyncFifo_w32_d16.v index 1a41439..903e663 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkSyncFifo_w32_d16.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkSyncFifo_w32_d16.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 24 20:31:55 BST 2020 +// On Thu Jul 2 02:54:30 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkTagController.v b/src_SSITH_P3/xilinx_ip/hdl/mkTagController.v index 8ec3206..6db409c 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkTagController.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkTagController.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 24 20:34:04 BST 2020 +// On Thu Jul 2 02:56:37 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkTourGHistReg.v b/src_SSITH_P3/xilinx_ip/hdl/mkTourGHistReg.v index c9315a3..77d6b46 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkTourGHistReg.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkTourGHistReg.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:53:54 BST 2020 +// On Thu Jul 2 02:56:43 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkTourPred.v b/src_SSITH_P3/xilinx_ip/hdl/mkTourPred.v index fa6b54e..edd6088 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkTourPred.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkTourPred.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:53:54 BST 2020 +// On Thu Jul 2 02:56:44 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkTourPredSecure.v b/src_SSITH_P3/xilinx_ip/hdl/mkTourPredSecure.v index 52c8769..1b82c22 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkTourPredSecure.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkTourPredSecure.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:53:55 BST 2020 +// On Thu Jul 2 02:56:44 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpDiv.v b/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpDiv.v index 6ccee51..ce2bbdf 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpDiv.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpDiv.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 24 20:32:50 BST 2020 +// On Thu Jul 2 02:55:23 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpDivIP.v b/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpDivIP.v index cae3995..81f24da 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpDivIP.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpDivIP.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 24 20:32:50 BST 2020 +// On Thu Jul 2 02:55:23 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpDivSim.v b/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpDivSim.v index bdc6945..a51d531 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpDivSim.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpDivSim.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 24 20:32:50 BST 2020 +// On Thu Jul 2 02:55:23 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpFma.v b/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpFma.v index c118fe7..e0abe15 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpFma.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpFma.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 24 20:32:50 BST 2020 +// On Thu Jul 2 02:55:23 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpFmaIP.v b/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpFmaIP.v index b2c85cf..71c0bd2 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpFmaIP.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpFmaIP.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 24 20:32:50 BST 2020 +// On Thu Jul 2 02:55:23 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpFmaSim.v b/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpFmaSim.v index 3b0d41f..86a3886 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpFmaSim.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpFmaSim.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 24 20:32:50 BST 2020 +// On Thu Jul 2 02:55:23 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpSqrt.v b/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpSqrt.v index c8f3301..23e5d8a 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpSqrt.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpSqrt.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 24 20:32:50 BST 2020 +// On Thu Jul 2 02:55:23 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpSqrtIP.v b/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpSqrtIP.v index 2c53437..72fa192 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpSqrtIP.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpSqrtIP.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 24 20:32:50 BST 2020 +// On Thu Jul 2 02:55:23 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpSqrtSim.v b/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpSqrtSim.v index 89c5e28..37fdff6 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpSqrtSim.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkXilinxFpSqrtSim.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Wed Jun 24 20:32:50 BST 2020 +// On Thu Jul 2 02:55:23 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/module_alu.v b/src_SSITH_P3/xilinx_ip/hdl/module_alu.v index a9f9800..69b174e 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/module_alu.v +++ b/src_SSITH_P3/xilinx_ip/hdl/module_alu.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:45:25 BST 2020 +// On Thu Jul 2 02:47:07 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/module_aluBr.v b/src_SSITH_P3/xilinx_ip/hdl/module_aluBr.v index c8bd44b..518a50c 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/module_aluBr.v +++ b/src_SSITH_P3/xilinx_ip/hdl/module_aluBr.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:45:27 BST 2020 +// On Thu Jul 2 02:47:09 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/module_amoExec.v b/src_SSITH_P3/xilinx_ip/hdl/module_amoExec.v index f0e0b02..24cc5e3 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/module_amoExec.v +++ b/src_SSITH_P3/xilinx_ip/hdl/module_amoExec.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:45:06 BST 2020 +// On Thu Jul 2 02:46:45 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/module_basicExec.v b/src_SSITH_P3/xilinx_ip/hdl/module_basicExec.v index 756ad26..b31032f 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/module_basicExec.v +++ b/src_SSITH_P3/xilinx_ip/hdl/module_basicExec.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:45:28 BST 2020 +// On Thu Jul 2 02:47:10 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/module_brAddrCalc.v b/src_SSITH_P3/xilinx_ip/hdl/module_brAddrCalc.v index 20fa1f2..b6aa6b5 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/module_brAddrCalc.v +++ b/src_SSITH_P3/xilinx_ip/hdl/module_brAddrCalc.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:45:27 BST 2020 +// On Thu Jul 2 02:47:09 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/module_capChecks.v b/src_SSITH_P3/xilinx_ip/hdl/module_capChecks.v index 7e7e1b1..4ce00f1 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/module_capChecks.v +++ b/src_SSITH_P3/xilinx_ip/hdl/module_capChecks.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:45:24 BST 2020 +// On Thu Jul 2 02:47:06 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/module_capInspect.v b/src_SSITH_P3/xilinx_ip/hdl/module_capInspect.v index d6e32bc..887e628 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/module_capInspect.v +++ b/src_SSITH_P3/xilinx_ip/hdl/module_capInspect.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:45:27 BST 2020 +// On Thu Jul 2 02:47:09 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/module_capModify.v b/src_SSITH_P3/xilinx_ip/hdl/module_capModify.v index 21db3a4..39de667 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/module_capModify.v +++ b/src_SSITH_P3/xilinx_ip/hdl/module_capModify.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:45:27 BST 2020 +// On Thu Jul 2 02:47:09 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/module_checkForException.v b/src_SSITH_P3/xilinx_ip/hdl/module_checkForException.v index 5f3e268..88d46e5 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/module_checkForException.v +++ b/src_SSITH_P3/xilinx_ip/hdl/module_checkForException.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:45:29 BST 2020 +// On Thu Jul 2 02:47:11 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/module_decode.v b/src_SSITH_P3/xilinx_ip/hdl/module_decode.v index f4a5472..aef0a68 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/module_decode.v +++ b/src_SSITH_P3/xilinx_ip/hdl/module_decode.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:49:58 BST 2020 +// On Thu Jul 2 02:51:46 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/module_decodeBrPred.v b/src_SSITH_P3/xilinx_ip/hdl/module_decodeBrPred.v index 51876d2..c692635 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/module_decodeBrPred.v +++ b/src_SSITH_P3/xilinx_ip/hdl/module_decodeBrPred.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:49:54 BST 2020 +// On Thu Jul 2 02:51:43 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/module_execFpuSimple.v b/src_SSITH_P3/xilinx_ip/hdl/module_execFpuSimple.v index 59badfc..395bb44 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/module_execFpuSimple.v +++ b/src_SSITH_P3/xilinx_ip/hdl/module_execFpuSimple.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:53:45 BST 2020 +// On Thu Jul 2 02:55:42 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/module_prepareBoundsCheck.v b/src_SSITH_P3/xilinx_ip/hdl/module_prepareBoundsCheck.v index 1100df8..e5808b1 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/module_prepareBoundsCheck.v +++ b/src_SSITH_P3/xilinx_ip/hdl/module_prepareBoundsCheck.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:45:25 BST 2020 +// On Thu Jul 2 02:47:07 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/module_setBoundsALU.v b/src_SSITH_P3/xilinx_ip/hdl/module_setBoundsALU.v index 907c720..753ab1d 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/module_setBoundsALU.v +++ b/src_SSITH_P3/xilinx_ip/hdl/module_setBoundsALU.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:45:25 BST 2020 +// On Thu Jul 2 02:47:07 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/module_specialRWALU.v b/src_SSITH_P3/xilinx_ip/hdl/module_specialRWALU.v index 0397d99..aa771f7 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/module_specialRWALU.v +++ b/src_SSITH_P3/xilinx_ip/hdl/module_specialRWALU.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Mon Jun 29 23:45:27 BST 2020 +// On Thu Jul 2 02:47:09 BST 2020 // // // Ports: