From 81a12b89cb9c524242bb858aa290e5a73aeda8a0 Mon Sep 17 00:00:00 2001 From: Jonathan Woodruff Date: Thu, 7 Oct 2021 16:28:57 +0000 Subject: [PATCH 1/2] Move to NonPipelinedSquareRooter to hopefully fit more deterministically. We're still waiting for a fixed NonPipelinedDivider. --- src_Core/RISCY_OOO/procs/lib/Fpu.bsv | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/src_Core/RISCY_OOO/procs/lib/Fpu.bsv b/src_Core/RISCY_OOO/procs/lib/Fpu.bsv index f3e2a3b..b3894c4 100644 --- a/src_Core/RISCY_OOO/procs/lib/Fpu.bsv +++ b/src_Core/RISCY_OOO/procs/lib/Fpu.bsv @@ -106,7 +106,7 @@ module mkDoubleSqrt(Server#(Tuple2#(Double, FpuRoundMode), Tuple2#(Double, FpuEx `ifdef USE_XILINX_FPU let fpu <- mkXilinxFpSqrt; `else - let int_sqrt <- mkSquareRooter(1); // [sizhuo] size in RVFpu: 3 + let int_sqrt <- mkNonPipelinedSquareRooter(3); // [sizhuo] size in RVFpu: 3 let fpu <- mkFloatingPointSquareRooter(int_sqrt); `endif return fpu; @@ -344,7 +344,7 @@ function Tuple2#(Bit#(64), FpuException) float_to_int( // necessary for rounding and overflow detection. Bit#(TAdd#(66,m)) int_val = {64'b1, in.sfd, 2'b0}; // this is 2**m times larger than it should be - we will shift this to correct for that int_val = saturating_shift_right(int_val, fromInteger(valueOf(m)) + bias_exp - in_exp); - + // do rounding // 00 : exact // 01 : < 0.5 @@ -963,4 +963,3 @@ module mkFpuExecPipeline(FpuExec); sqrtQ.specUpdate )); endmodule - From 3d0aee0af4d7931bcfc063bb87d6af77b9a47752 Mon Sep 17 00:00:00 2001 From: Jonathan Woodruff Date: Thu, 7 Oct 2021 16:30:32 +0000 Subject: [PATCH 2/2] Remove some verbosity from the committed state. --- src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv | 4 ++-- src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv index 8b59771..b39fc2c 100755 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv @@ -226,7 +226,7 @@ interface AluExePipeline; endinterface module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline); - Bool verbose = True; + Bool verbose = False; Integer verbosity = 0; // alu reservation station @@ -323,7 +323,7 @@ module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline); end end - + else if(x.dInst.iType == CJALR || x.dInst.iType == Jr) begin let res_targets = inIfc.checkTarget(ppc); diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv index 2b76ca7..d671913 100644 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv @@ -252,7 +252,7 @@ interface MemExePipeline; endinterface module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline); - Bool verbose = True; + Bool verbose = False; // we change cache request in case of single core, becaues our MSI protocol // is not good with single core