From 4c194d4e82794edc9ff4c0a190533eac7658e8eb Mon Sep 17 00:00:00 2001 From: Franz Fuchs Date: Thu, 23 Sep 2021 14:36:50 +0100 Subject: [PATCH 1/3] integrated new version of RISCV_HPM_Events done by Jess --- builds/Resources/Include_Common.mk | 6 +++--- libs/RISCV_HPM_Events | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/builds/Resources/Include_Common.mk b/builds/Resources/Include_Common.mk index 6772ce0..1a51f0e 100644 --- a/builds/Resources/Include_Common.mk +++ b/builds/Resources/Include_Common.mk @@ -144,7 +144,7 @@ TagTableStructure.bsv: $(REPO)/libs/TagController/tagsparams.py generate_hpm_vector: GenerateHPMVector.bsv GenerateHPMVector.bsv: $(RISCV_HPM_Events_DIR)/parse_counters.py @echo "INFO: Re-generating GenerateHPMVector bluespec file" - $^ $(RISCV_HPM_Events_DIR)/counters.yaml Toooba -b $@ + $^ $(RISCV_HPM_Events_DIR)/counters.yaml -m ProcTypes -b $@ @echo "INFO: Re-generated GenerateHPMVector bluespec file" @@ -152,7 +152,7 @@ GenerateHPMVector.bsv: $(RISCV_HPM_Events_DIR)/parse_counters.py stat_counters: StatCounters.bsv StatCounters.bsv: $(RISCV_HPM_Events_DIR)/parse_counters.py @echo "INFO: Re-generating HPM events struct bluepsec file" - $^ $(RISCV_HPM_Events_DIR)/counters.yaml Toooba -s $@ + $^ $(RISCV_HPM_Events_DIR)/counters.yaml -m ProcTypes -s $@ @echo "INFO: Re-generated HPM events struct bluespec file" compile: tagsparams #stat_counters generate_hpm_vector @@ -166,6 +166,6 @@ clean: .PHONY: full_clean full_clean: clean rm -r -f $(SIM_EXE_FILE)* *.log *.vcd *.hex Logs/ - rm -f TagTableStructure.bsv GenerateHPMVector.bsv .depends.mk + rm -f TagTableStructure.bsv StatCounters.bsv GenerateHPMVector.bsv .depends.mk # ================================================================ diff --git a/libs/RISCV_HPM_Events b/libs/RISCV_HPM_Events index e3a1281..bf5107c 160000 --- a/libs/RISCV_HPM_Events +++ b/libs/RISCV_HPM_Events @@ -1 +1 @@ -Subproject commit e3a12815d2f680cf28c8a87e368e72955fe2611e +Subproject commit bf5107c39ce7e59c21d4372a2c349a25b0145cc4 From 4cfac08bcadcbbab69781338044d410bd19bd844 Mon Sep 17 00:00:00 2001 From: Franz Fuchs Date: Thu, 23 Sep 2021 15:25:46 +0100 Subject: [PATCH 2/3] Bumped BlueStuff and made necessary adaptations --- libs/BlueStuff | 2 +- src_Core/Core/CoreW.bsv | 8 ++++---- src_Core/Core/CoreW_IFC.bsv | 4 ++-- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/libs/BlueStuff b/libs/BlueStuff index a8d270d..df2529d 160000 --- a/libs/BlueStuff +++ b/libs/BlueStuff @@ -1 +1 @@ -Subproject commit a8d270d79ae4e4b7c7035337ebad887813a3aaab +Subproject commit df2529dd4298fe77cfba638001f4a960f82fbe02 diff --git a/src_Core/Core/CoreW.bsv b/src_Core/Core/CoreW.bsv index 0b00cc6..b3bfd94 100644 --- a/src_Core/Core/CoreW.bsv +++ b/src_Core/Core/CoreW.bsv @@ -499,13 +499,13 @@ endmodule: mkCoreW module mkCoreW_Synth #(Reset dm_power_on_reset) (CoreW_IFC_Synth #(N_External_Interrupt_Sources)); let core <- mkCoreW (dm_power_on_reset); - let cpu_imem_master_synth <- toAXI4_Master_Synth (core.cpu_imem_master); - let cpu_dmem_master_synth <- toAXI4_Master_Synth (core.cpu_dmem_master); + let cpu_imem_master_sig <- toAXI4_Master_Sig (core.cpu_imem_master); + let cpu_dmem_master_sig <- toAXI4_Master_Sig (core.cpu_dmem_master); method set_verbosity = core.set_verbosity; method start = core.start; - interface cpu_imem_master = cpu_imem_master_synth; - interface cpu_dmem_master = cpu_dmem_master_synth; + interface cpu_imem_master = cpu_imem_master_sig; + interface cpu_dmem_master = cpu_dmem_master_sig; interface core_external_interrupt_sources = core.core_external_interrupt_sources; method nmi_req = core.nmi_req; `ifdef RVFI_DII diff --git a/src_Core/Core/CoreW_IFC.bsv b/src_Core/Core/CoreW_IFC.bsv index 2bb5a6e..ff6a4c3 100644 --- a/src_Core/Core/CoreW_IFC.bsv +++ b/src_Core/Core/CoreW_IFC.bsv @@ -150,11 +150,11 @@ interface CoreW_IFC_Synth #(numeric type t_n_interrupt_sources); // AXI4 Fabric interfaces // CPU IMem to Fabric master interface - interface AXI4_Master_Synth #(TAdd#(Wd_MId,1), Wd_Addr, Wd_Data, + interface AXI4_Master_Sig #(TAdd#(Wd_MId,1), Wd_Addr, Wd_Data, 0, 0, 0, 0, 0) cpu_imem_master; // CPU DMem to Fabric master interface - interface AXI4_Master_Synth #(TAdd#(Wd_MId,1), Wd_Addr, Wd_Data, + interface AXI4_Master_Sig #(TAdd#(Wd_MId,1), Wd_Addr, Wd_Data, 0, 0, 0, 0, 0) cpu_dmem_master; // ---------------------------------------------------------------- From db9b5c7f5424825199c58f07ef3daab2521515d2 Mon Sep 17 00:00:00 2001 From: Franz Fuchs Date: Fri, 24 Sep 2021 11:39:23 +0100 Subject: [PATCH 3/3] re-integrated TagController --- libs/RISCV_HPM_Events | 2 +- libs/TagController | 2 +- src_Core/CPU/Core.bsv | 8 ++++---- src_Core/CPU/Proc.bsv | 2 +- src_Core/CPU/Proc_IFC.bsv | 2 +- src_Core/Core/CoreW.bsv | 13 ++++++++++++- 6 files changed, 20 insertions(+), 9 deletions(-) diff --git a/libs/RISCV_HPM_Events b/libs/RISCV_HPM_Events index bf5107c..9e345b2 160000 --- a/libs/RISCV_HPM_Events +++ b/libs/RISCV_HPM_Events @@ -1 +1 @@ -Subproject commit bf5107c39ce7e59c21d4372a2c349a25b0145cc4 +Subproject commit 9e345b27e848adbc979abd08f2b8ccdc24845a0e diff --git a/libs/TagController b/libs/TagController index 7c9ac94..99c43e8 160000 --- a/libs/TagController +++ b/libs/TagController @@ -1 +1 @@ -Subproject commit 7c9ac94d1d93ea4086ac9320c560cb262432dfc5 +Subproject commit 99c43e81384741ae11e098a63514a78bd43637e2 diff --git a/src_Core/CPU/Core.bsv b/src_Core/CPU/Core.bsv index d40ef31..ad6562a 100644 --- a/src_Core/CPU/Core.bsv +++ b/src_Core/CPU/Core.bsv @@ -212,7 +212,7 @@ interface Core; `ifdef PERFORMANCE_MONITORING method Action events_llc(EventsLL events); - method Action events_tgc(EventsCacheCore events); + method Action events_tgc(EventsTGC events); `endif endinterface @@ -1150,7 +1150,7 @@ module mkCore#(CoreId coreId)(Core); // different fields than the TLB, which makes it safe to combine them Reg#(EventsLL) events_llc_reg <- mkRegU; - Reg#(EventsCacheCore) events_tgc_reg <- mkRegU; + Reg#(EventsTGC) events_tgc_reg <- mkRegU; rule report_events; EventsCore events = unpack(pack(commitStage.events)); events.evt_REDIRECT = zeroExtend(pack(fetchStage.redirect_evt)); @@ -1160,7 +1160,7 @@ module mkCore#(CoreId coreId)(Core); EventsCore core_evts = unpack(pack(coreFix.memExeIfc.events) | pack(hpm_core_events[0])); EventsL1I imem_evts = unpack(pack(iMem.events) | pack(iTlb.events)); EventsL1D dmem_evts = unpack(pack(dMem.events) | pack(dTlb.events)); - EventsCacheCore tgc_evts = events_tgc_reg; + EventsTGC tgc_evts = events_tgc_reg; EventsLL llmem_evts = unpack(pack(events_llc_reg) | pack(l2Tlb.events)); Maybe#(EventsTransExe) mab_trans_exe = tagged Invalid; @@ -1182,7 +1182,7 @@ module mkCore#(CoreId coreId)(Core); let ev_struct = HPMEvents{mab_EventsCore: tagged Valid core_evts, mab_EventsL1I: tagged Valid imem_evts, mab_EventsL1D: tagged Valid dmem_evts, mab_EventsLL: tagged Valid llmem_evts, - mab_EventsCacheCore: tagged Valid tgc_evts, mab_EventsTransExe: mab_trans_exe, + mab_EventsTGC: tagged Valid tgc_evts, mab_EventsTransExe: mab_trans_exe, mab_AXI4_Slave_Events: tagged Invalid, mab_AXI4_Master_Events: tagged Invalid}; let events = generateHPMVector(ev_struct); diff --git a/src_Core/CPU/Proc.bsv b/src_Core/CPU/Proc.bsv index 8355804..243896f 100644 --- a/src_Core/CPU/Proc.bsv +++ b/src_Core/CPU/Proc.bsv @@ -179,7 +179,7 @@ module mkProc (Proc_IFC); endrule `ifdef PERFORMANCE_MONITORING - Reg#(EventsCacheCore) events_tgc_reg <- mkRegU; + Reg#(EventsTGC) events_tgc_reg <- mkRegU; rule broadcastPerfEvents; for(Integer j = 0; j < valueof(CoreNum); j = j+1) begin core[j].events_llc(llc.events); diff --git a/src_Core/CPU/Proc_IFC.bsv b/src_Core/CPU/Proc_IFC.bsv index db83ac1..0cc77ee 100644 --- a/src_Core/CPU/Proc_IFC.bsv +++ b/src_Core/CPU/Proc_IFC.bsv @@ -130,7 +130,7 @@ interface Proc_IFC; `endif `ifdef PERFORMANCE_MONITORING - method Action events_tgc(EventsCacheCore events); + method Action events_tgc(EventsTGC events); `endif endinterface diff --git a/src_Core/Core/CoreW.bsv b/src_Core/Core/CoreW.bsv index b3bfd94..a77b60b 100644 --- a/src_Core/Core/CoreW.bsv +++ b/src_Core/Core/CoreW.bsv @@ -60,6 +60,7 @@ import GetPut_Aux :: *; import Routable :: *; import AXI4 :: *; import TagControllerAXI :: *; +import CacheCore :: *; // ================================================================ // Project imports @@ -178,7 +179,17 @@ module mkCoreW #(Reset dm_power_on_reset) mkConnection(proc.master0, tagController.slave, reset_by all_harts_reset); `ifdef PERFORMANCE_MONITORING rule report_tagController_events; - EventsCacheCore evts = tagController.events; + EventsCacheCore cache_core_evts = tagController.events; + EventsTGC evts = unpack(0); + evts.evt_WRITE = zeroExtend(pack(cache_core_evts.evt_WRITE)); + evts.evt_WRITE_MISS = zeroExtend(pack(cache_core_evts.evt_WRITE_MISS)); + evts.evt_READ = zeroExtend(pack(cache_core_evts.evt_READ)); + evts.evt_READ_MISS = zeroExtend(pack(cache_core_evts.evt_READ_MISS)); + evts.evt_EVICT = zeroExtend(pack(cache_core_evts.evt_EVICT)); +`ifdef USECAP + evts.evt_SET_TAG_WRITE = zeroExtend(pack(cache_core_evts.evt_SET_TAG_WRITE)); + evts.evt_SET_TAG_READ = zeroExtend(pack(cache_core_evts.evt_SET_TAG_READ)); +`endif proc.events_tgc(evts); endrule `endif