Cheri-research/Toooba
1
0
Fork 0
Code Issues 1 Pull Requests Actions Packages Projects Releases Wiki Activity

Tidy section formatting so that it better exports to asciidoctor.

Browse Source
This commit is contained in:
Simon Moore
2023-08-30 18:26:47 +01:00
committed by GitHub
parent da473192c7
commit d04c8ea3a9
1 changed files with 4 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
README.md
View File

@@ -3,8 +3,7 @@
This is a prototype of an out-of-order core that implements hardware capabilities (see [CHERI](https://www.cl.cam.ac.uk/research/security/ctsrd/cheri/) for details). This is a prototype of an out-of-order core that implements hardware capabilities (see [CHERI](https://www.cl.cam.ac.uk/research/security/ctsrd/cheri/) for details).
It is based off of [Bluespec's Toooba](https://github.com/bluespec/Toooba), which is a slight variation of [MIT's RisyOO core](https://github.com/csail-csg/riscy-OOO). It is based off of [Bluespec's Toooba](https://github.com/bluespec/Toooba), which is a slight variation of [MIT's RisyOO core](https://github.com/csail-csg/riscy-OOO).
---------------------------------------------------------------- ## Note re. distribution of MIT RISCY-OOO sources.
### Note re. distribution of MIT RISCY-OOO sources.
The directory `src_Core/RISCY_OOO` contains sources copied from MIT's The directory `src_Core/RISCY_OOO` contains sources copied from MIT's
`riscy-OOO` repository. See `LICENSE_RISCY-OOO` for MIT's license. `riscy-OOO` repository. See `LICENSE_RISCY-OOO` for MIT's license.
@@ -19,8 +18,7 @@ small and mostly additive:
The University of Cambridge made changes to RiscyOO to add support for [CHERI capabilities](https://www.cl.cam.ac.uk/techreports/UCAM-CL-TR-941.pdf). For details on what CHERI instructions do, please see the [Instruction Set Architecture document](https://www.cl.cam.ac.uk/techreports/UCAM-CL-TR-951.pdf). The University of Cambridge made changes to RiscyOO to add support for [CHERI capabilities](https://www.cl.cam.ac.uk/techreports/UCAM-CL-TR-941.pdf). For details on what CHERI instructions do, please see the [Instruction Set Architecture document](https://www.cl.cam.ac.uk/techreports/UCAM-CL-TR-951.pdf).
---------------------------------------------------------------- ## About the source codes (in BSV and Verilog)
### About the source codes (in BSV and Verilog)
The BSV source code in this repository, from which the synthesizable The BSV source code in this repository, from which the synthesizable
Verilog RTL in this repository is generated, is highly parameterized Verilog RTL in this repository is generated, is highly parameterized
@@ -46,7 +44,7 @@ repository are for one specific configuration:
If you want to generate other Verilog variants, you'll need a Bluespec If you want to generate other Verilog variants, you'll need a Bluespec
`bsc` compiler, which is open source and can be found in [this repository](https://github.com/B-Lang-org/bsc). `bsc` compiler, which is open source and can be found in [this repository](https://github.com/B-Lang-org/bsc).
### Testbench included ## Testbench included
This repository contains a simple testbench (a small SoC) with which This repository contains a simple testbench (a small SoC) with which
one can run RISC-V binaries in simulation by loading standard mem hex one can run RISC-V binaries in simulation by loading standard mem hex
@@ -63,11 +61,10 @@ an RV64ACDFIMSUxCHERI simulator, using Bluesim and Verilog simulation.
There are also RVFI-DII variants of these to be used with [TestRIG](https://github.com/CTSRD-CHERI/TestRIG). There are also RVFI-DII variants of these to be used with [TestRIG](https://github.com/CTSRD-CHERI/TestRIG).
The generated Verilog is synthesizable. The generated Verilog is synthesizable.
#### Simulation ## Simulation
We currently only support Bluesim and Verilator simulation. There is also some code related to simulation on iVerilog, but this is currently not working and not being maintained. We currently only support Bluesim and Verilator simulation. There is also some code related to simulation on iVerilog, but this is currently not working and not being maintained.
----------------------------------------------------------------
## Source codes ## Source codes
This repository contains two levels of source code: Verilog and BSV. This repository contains two levels of source code: Verilog and BSV.
@@ -124,7 +121,6 @@ instruction-by-instruction trace that can be checked for correctness
against a RISC-V Golden Reference Model. Please contact Bluespec, against a RISC-V Golden Reference Model. Please contact Bluespec,
Inc. for more information. Inc. for more information.
----------------------------------------------------------------
## Build Instructions ## Build Instructions
First clone this repository and then inside the repository initialize the submodules: First clone this repository and then inside the repository initialize the submodules:
@@ -182,5 +178,3 @@ In the corresponding build directory:
all the standard RISC-V ISA tests relevant for RV64ACDFIMSU (regression testing). all the standard RISC-V ISA tests relevant for RV64ACDFIMSU (regression testing).
This uses the Python script `Tests/Run_regression.py`. This uses the Python script `Tests/Run_regression.py`.
Please see the documentation at the top of that program for details. Please see the documentation at the top of that program for details.
----------------------------------------------------------------