diff --git a/src_SSITH_P3/src_BSV/P3_Core.bsv b/src_SSITH_P3/src_BSV/P3_Core.bsv
index b5145d1..136ba87 100644
--- a/src_SSITH_P3/src_BSV/P3_Core.bsv
+++ b/src_SSITH_P3/src_BSV/P3_Core.bsv
@@ -137,6 +137,7 @@ module mkDelayShim #(Bit#(16) delay) (AXI4_Shim#(id_, addr_, data_, awuser_, wus
       interface ar = toSink(arff);
       interface r = toSource(rff);
    endinterface
+   interface clear = error("clear not supported");
 endmodule
 
 (* synthesize *)