From d17d3135bbd5cd65b55b07132b7caa46ae34aef6 Mon Sep 17 00:00:00 2001
From: Peter Rugg <pdr32@cam.ac.uk>
Date: Wed, 12 Jul 2023 15:34:12 +0100
Subject: [PATCH] Add error clear implementation for delayShim

---
 src_SSITH_P3/src_BSV/P3_Core.bsv | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src_SSITH_P3/src_BSV/P3_Core.bsv b/src_SSITH_P3/src_BSV/P3_Core.bsv
index b5145d1..136ba87 100644
--- a/src_SSITH_P3/src_BSV/P3_Core.bsv
+++ b/src_SSITH_P3/src_BSV/P3_Core.bsv
@@ -137,6 +137,7 @@ module mkDelayShim #(Bit#(16) delay) (AXI4_Shim#(id_, addr_, data_, awuser_, wus
       interface ar = toSink(arff);
       interface r = toSource(rff);
    endinterface
+   interface clear = error("clear not supported");
 endmodule
 
 (* synthesize *)