From d29bdf0a81f4fd91feba10acd0673eeb10ca8a5e Mon Sep 17 00:00:00 2001
From: Jonathan Woodruff <jdw57@cam.ac.uk>
Date: Wed, 17 May 2023 16:50:42 +0000
Subject: [PATCH] Default to Data Cache Stride 2 prefetcher, and no Instruction
 Cache prefetcher.

---
 builds/Resources/Include_RISCY_Config.mk | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/builds/Resources/Include_RISCY_Config.mk b/builds/Resources/Include_RISCY_Config.mk
index 039e954..fb4de9a 100644
--- a/builds/Resources/Include_RISCY_Config.mk
+++ b/builds/Resources/Include_RISCY_Config.mk
@@ -45,10 +45,10 @@ SIM_LLC_ARBITER_LAT ?=
 # default check cache deadlock and rename error
 CHECK_DEADLOCK ?= true
 RENAME_DEBUG ?= false
-INSTR_PREFETCHER_LOCATION ?= L1
+INSTR_PREFETCHER_LOCATION ?= NONE
 INSTR_PREFETCHER_TYPE ?= SINGLE_WINDOW_TARGET
 DATA_PREFETCHER_LOCATION ?= L1
-DATA_PREFETCHER_TYPE ?= MARKOV_ON_HIT_2
+DATA_PREFETCHER_TYPE ?= STRIDE
 
 # clk frequency depends on core size
 ifneq (,$(filter $(CORE_SIZE),TINY SMALL BOOM MEDIUM))