From d2b41c852d7ae23bcb152bba55fe3636de58dcf9 Mon Sep 17 00:00:00 2001
From: Karlis Susters <ks980@cam.ac.uk>
Date: Wed, 12 Apr 2023 21:55:13 +0300
Subject: [PATCH] Added prefetcher port to ICrqmshr and retired prefetchRqDone

---
 src_Core/RISCY_OOO/coherence/src/IBank.bsv    |  8 +---
 src_Core/RISCY_OOO/coherence/src/ICRqMshr.bsv | 38 ++++++++++++++++---
 2 files changed, 34 insertions(+), 12 deletions(-)

diff --git a/src_Core/RISCY_OOO/coherence/src/IBank.bsv b/src_Core/RISCY_OOO/coherence/src/IBank.bsv
index e6728fb..44b60d3 100644
--- a/src_Core/RISCY_OOO/coherence/src/IBank.bsv
+++ b/src_Core/RISCY_OOO/coherence/src/IBank.bsv
@@ -168,7 +168,6 @@ module mkIBank#(
     FIFO#(cRqIdxT) cRqIndexQ <- mkSizedFIFO(valueof(cRqNum));
     FIFO#(cRqIdxT) prefetchIndexQ <- mkSizedFIFO(valueof(cRqNum));
     Vector#(cRqNum, Reg#(Bool)) cRqIsPrefetch <- replicateM(mkReg(?));
-    Vector#(cRqNum, Reg#(Bool)) prefetchRqDone <- replicateM(mkReg(?));
 
     let prefetcher <- mkL1IPrefetcher;
     let llcPrefetcher <- mkLLIPrefetcherInL1I;
@@ -323,7 +322,6 @@ module mkIBank#(
         // enq to indexQ for in order resp
         prefetchIndexQ.enq(n);
         cRqIsPrefetch[n] <= True;
-        prefetchRqDone[n] <= False;
         addedCRqs.incr(1);
         // performance counter: cRq type
         //incrReqCnt; TODO make separate counter for prefetch requests
@@ -536,7 +534,6 @@ module mkIBank#(
             prefetcher.reportAccess(req.addr, HIT);
             llcPrefetcher.reportAccess(req.addr, HIT);
         end
-        prefetchRqDone[n] <= True;
         // process req to get superscalar inst read results
         // set MSHR entry as Done & save inst results
         let instResult = readInst(ram.line, req.addr);
@@ -773,11 +770,10 @@ module mkIBank#(
     endrule
     
     rule discardPrefetchRqResult(
-            //cRqMshr.sendRsToC.getResult(prefetchIndexQ.first) matches tagged Valid .inst);
-            prefetchRqDone[prefetchIndexQ.first]);
+            cRqMshr.prefetcher.getResult(prefetchIndexQ.first) matches tagged Valid .inst);
         prefetchIndexQ.deq;
         removedCRqs.incr(1);
-        cRqMshr.sendRsToC.releaseEntry(prefetchIndexQ.first); // release MSHR entry
+        cRqMshr.prefetcher.releaseEntry(prefetchIndexQ.first); // release MSHR entry
         if (verbose)
         $display("%t I %m discardPrefetchRqResult: ", $time,
             fshow(prefetchIndexQ.first)
diff --git a/src_Core/RISCY_OOO/coherence/src/ICRqMshr.bsv b/src_Core/RISCY_OOO/coherence/src/ICRqMshr.bsv
index b6c815f..7db5c5a 100644
--- a/src_Core/RISCY_OOO/coherence/src/ICRqMshr.bsv
+++ b/src_Core/RISCY_OOO/coherence/src/ICRqMshr.bsv
@@ -143,6 +143,14 @@ interface ICRqMshr_sendRsToC#(
     method Maybe#(resultT) getResult(Bit#(TLog#(cRqNum)) n);
 endinterface
 
+interface ICRqMshr_prefetcher#(
+    numeric type cRqNum,
+    type resultT
+);
+    method Action releaseEntry(Bit#(TLog#(cRqNum)) n);
+    method Maybe#(resultT) getResult(Bit#(TLog#(cRqNum)) n);
+endinterface
+
 interface ICRqMshr#(
     numeric type cRqNum, 
     type wayT,
@@ -156,6 +164,9 @@ interface ICRqMshr#(
     // port for sendRsToC
     interface ICRqMshr_sendRsToC#(cRqNum, resultT) sendRsToC;
 
+    // port for prefetcher
+    interface ICRqMshr_prefetcher#(cRqNum, resultT) prefetcher;
+
     // port for sendRsToP_cRq
     interface ICRqMshr_sendRsToP_cRq#(cRqNum, wayT, tagT, reqT) sendRsToP_cRq;
 
@@ -192,7 +203,8 @@ module mkICRqMshrSafe#(
 
     // EHR ports
     // We put pipelineResp < transfer to cater for deq < enq of cache pipeline
-    Integer cRqTransfer_port = 2;
+    Integer cRqTransfer_port = 3;
+    Integer prefetcher_port = 2;
     Integer sendRsToC_port = 1; // create a bypass behavior from pipelineResp to sendRsToC (to save a cycle)
     Integer pipelineResp_port = 0;
     Integer sendRqToP_port = 0; // sendRqToP is read only
@@ -200,15 +212,15 @@ module mkICRqMshrSafe#(
     Integer flush_port = 0; // flush port is read only
 
     // MSHR entry state
-    Vector#(cRqNum, Ehr#(3, ICRqState)) stateVec <- replicateM(mkEhr(Empty));
+    Vector#(cRqNum, Ehr#(4, ICRqState)) stateVec <- replicateM(mkEhr(Empty));
     // cRq req contents
-    Vector#(cRqNum, Ehr#(3, reqT)) reqVec <- replicateM(mkEhr(?));
+    Vector#(cRqNum, Ehr#(4, reqT)) reqVec <- replicateM(mkEhr(?));
     // cRq mshr slots
-    Vector#(cRqNum, Ehr#(3, slotT)) slotVec <- replicateM(mkEhr(defaultValue));
+    Vector#(cRqNum, Ehr#(4, slotT)) slotVec <- replicateM(mkEhr(defaultValue));
     // result
-    Vector#(cRqNum, Ehr#(3, Maybe#(resultT))) resultVec <- replicateM(mkEhr(Invalid));
+    Vector#(cRqNum, Ehr#(4, Maybe#(resultT))) resultVec <- replicateM(mkEhr(Invalid));
     // successor valid bit
-    Vector#(cRqNum, Ehr#(3, Bool)) succValidVec <- replicateM(mkEhr(False));
+    Vector#(cRqNum, Ehr#(4, Bool)) succValidVec <- replicateM(mkEhr(False));
     // successor MSHR index
     RegFile#(cRqIndexT, cRqIndexT) succFile <- mkRegFile(0, fromInteger(valueOf(cRqNum) - 1));
     // empty entry FIFO
@@ -273,6 +285,20 @@ module mkICRqMshrSafe#(
         endmethod
     endinterface
 
+    interface ICRqMshr_prefetcher prefetcher;
+        method Action releaseEntry(cRqIndexT n) if(inited);
+            emptyEntryQ.enq(n);
+            stateVec[n][prefetcher_port] <= Empty;
+`ifdef CHECK_DEADLOCK
+            checker.releaseEntry(n);
+`endif
+        endmethod
+
+        method Maybe#(resultT) getResult(Bit#(TLog#(cRqNum)) n);
+            return resultVec[n][prefetcher_port];
+        endmethod
+    endinterface
+
     interface ICRqMshr_sendRsToP_cRq sendRsToP_cRq;
         method reqT getRq(cRqIndexT n);
             return reqVec[n][sendRsToP_cRq_port];