diff --git a/src_Core/Core/CoreW.bsv b/src_Core/Core/CoreW.bsv
index bd622dd..7e75669 100644
--- a/src_Core/Core/CoreW.bsv
+++ b/src_Core/Core/CoreW.bsv
@@ -163,7 +163,7 @@ module mkCoreW #(Reset dm_power_on_reset)
    SoC_Map_IFC  soc_map  <- mkSoC_Map;
 
    // RISCY-OOO processor
-   // TODO (when we do multicore): need resets for each core.
+   // TODO: could have separate resets for each core.
    Proc_IFC proc <- mkProc (reset_by all_harts_reset);
 
    // handle uncached interface
diff --git a/src_Core/Debug_Module/DM_Abstract_Commands.bsv b/src_Core/Debug_Module/DM_Abstract_Commands.bsv
index b4d9b89..88fffb9 100644
--- a/src_Core/Debug_Module/DM_Abstract_Commands.bsv
+++ b/src_Core/Debug_Module/DM_Abstract_Commands.bsv
@@ -284,7 +284,7 @@ module mkDM_Abstract_Commands (DM_Abstract_Commands_IFC);
 	 rg_start_reg_access <= False;
 
 	 if (verbosity != 0)
-	    $display ("%0d: DM_Abstract_Commands.rl_csr_write_start hart %i: ", cur_cycle, core, fshow (req));
+	    $display ("%0d: DM_Abstract_Commands.rl_csr_write_start hart %0d: ", cur_cycle, core, fshow (req));
       endrule
 
       // ----------------
@@ -296,7 +296,7 @@ module mkDM_Abstract_Commands (DM_Abstract_Commands_IFC);
 				   && is_csr);
 	       let rsp <- pop (f_harts_csr_rsps[core]);
 	       if (verbosity != 0)
-		  $display ("%0d: DM_Abstract_Commands.rl_csr_write_finish hart %i: ", cur_cycle, core, fshow (rsp));
+		  $display ("%0d: DM_Abstract_Commands.rl_csr_write_finish hart %0d: ", cur_cycle, core, fshow (rsp));
 
 	       rg_abstractcs_cmderr <= (rsp.ok ? DM_ABSTRACTCS_CMDERR_NONE : DM_ABSTRACTCS_CMDERR_HALT_RESUME);
 	       rg_abstractcs_busy   <= False;
@@ -318,7 +318,7 @@ module mkDM_Abstract_Commands (DM_Abstract_Commands_IFC);
 	 rg_start_reg_access <= False;
 
 	 if (verbosity != 0)
-	    $display ("%0d: DM_Abstract_Commands.rl_csr_read_start hart %i: ", cur_cycle, core, fshow (req));
+	    $display ("%0d: DM_Abstract_Commands.rl_csr_read_start hart %0d: ", cur_cycle, core, fshow (req));
       endrule
 
       // ----------------
@@ -330,7 +330,7 @@ module mkDM_Abstract_Commands (DM_Abstract_Commands_IFC);
 				     && is_csr);
 	       let rsp <- pop (f_harts_csr_rsps[core]);
 	       if (verbosity != 0)
-		  $display ("%0d: DM_Abstract_Commands.rl_csr_read_finish hart %i: ", cur_cycle, core, fshow (rsp));
+		  $display ("%0d: DM_Abstract_Commands.rl_csr_read_finish hart %0d: ", cur_cycle, core, fshow (rsp));
 
 	       rg_abstractcs_cmderr <= (rsp.ok ? DM_ABSTRACTCS_CMDERR_NONE : DM_ABSTRACTCS_CMDERR_HALT_RESUME);
 `ifdef RV32
@@ -365,7 +365,7 @@ module mkDM_Abstract_Commands (DM_Abstract_Commands_IFC);
 	 f_harts_gpr_reqs[core].enq (req);
 	 rg_start_reg_access <= False;
 	 if (verbosity != 0)
-	    $display ("%0d: DM_Abstract_Commands.rl_gpr_write_start hart %i: ", cur_cycle, core, fshow (req));
+	    $display ("%0d: DM_Abstract_Commands.rl_gpr_write_start hart %0d: ", cur_cycle, core, fshow (req));
       endrule
 
       // ----------------
@@ -377,7 +377,7 @@ module mkDM_Abstract_Commands (DM_Abstract_Commands_IFC);
 				      && is_gpr);
 	       let rsp <- pop (f_harts_gpr_rsps[core]);
 	       if (verbosity != 0)
-		  $display ("%0d: DM_Abstract_Commands.rl_gpr_write_finish hart %i: ", cur_cycle, core, fshow (rsp));
+		  $display ("%0d: DM_Abstract_Commands.rl_gpr_write_finish hart %0d: ", cur_cycle, core, fshow (rsp));
 
 	       rg_abstractcs_cmderr <= (rsp.ok ? DM_ABSTRACTCS_CMDERR_NONE : DM_ABSTRACTCS_CMDERR_HALT_RESUME);
 	       rg_abstractcs_busy   <= False;
@@ -399,7 +399,7 @@ module mkDM_Abstract_Commands (DM_Abstract_Commands_IFC);
 	 rg_start_reg_access <= False;
 
 	 if (verbosity != 0)
-	    $display ("%0d: DM_Abstract_Commands.rl_gpr_read_start hart %i: ", cur_cycle, core, fshow (req));
+	    $display ("%0d: DM_Abstract_Commands.rl_gpr_read_start hart %0d: ", cur_cycle, core, fshow (req));
       endrule
 
       // ----------------
@@ -411,7 +411,7 @@ module mkDM_Abstract_Commands (DM_Abstract_Commands_IFC);
 				     && is_gpr);
 	       let rsp <- pop (f_harts_gpr_rsps[core]);
 	       if (verbosity != 0)
-		  $display ("%0d: DM_Abstract_Commands.rl_gpr_read_finish hart %i: ", cur_cycle, core, fshow (rsp));
+		  $display ("%0d: DM_Abstract_Commands.rl_gpr_read_finish hart %0d: ", cur_cycle, core, fshow (rsp));
 
 `ifdef RV32
 	       rg_data0 <= rsp.data;
@@ -448,7 +448,7 @@ module mkDM_Abstract_Commands (DM_Abstract_Commands_IFC);
 	 f_harts_fpr_reqs[core].enq (req);
 	 rg_start_reg_access <= False;
 	 if (verbosity != 0)
-	    $display ("%0d: DM_Abstract_Commands.rl_fpr_write_start hart %i: ", cur_cycle, core, fshow (req));
+	    $display ("%0d: DM_Abstract_Commands.rl_fpr_write_start hart %0d: ", cur_cycle, core, fshow (req));
       endrule
 
       // ----------------
@@ -460,7 +460,7 @@ module mkDM_Abstract_Commands (DM_Abstract_Commands_IFC);
 				      && is_fpr);
 	       let rsp <- pop (f_harts_fpr_rsps[core]);
 	       if (verbosity != 0)
-		  $display ("%0d: DM_Abstract_Commands.rl_fpr_write_finish hart %i: ", cur_cycle, core, fshow (rsp));
+		  $display ("%0d: DM_Abstract_Commands.rl_fpr_write_finish hart %0d: ", cur_cycle, core, fshow (rsp));
 
 	       rg_abstractcs_cmderr <= (rsp.ok ? DM_ABSTRACTCS_CMDERR_NONE : DM_ABSTRACTCS_CMDERR_HALT_RESUME);
 	       rg_abstractcs_busy   <= False;
@@ -482,7 +482,7 @@ module mkDM_Abstract_Commands (DM_Abstract_Commands_IFC);
 	 rg_start_reg_access <= False;
 
 	 if (verbosity != 0)
-	    $display ("%0d: DM_Abstract_Commands.rl_fpr_read_start hart %i: ", cur_cycle, core, fshow (req));
+	    $display ("%0d: DM_Abstract_Commands.rl_fpr_read_start hart %0d: ", cur_cycle, core, fshow (req));
       endrule
 
       // ----------------
@@ -598,8 +598,10 @@ module mkDM_Abstract_Commands (DM_Abstract_Commands_IFC);
 	    rg_dmcontrol_hartsel <= fn_dmcontrol_hartsel(dm_word);
 	    // It is specified that the debugger must not change hartsel while this module is busy.
 	    // If this is done, the debug unit will wedge, so print a warning.
-	    $display ("%0d: DM_Abstract_Commands.write: [", cur_cycle, dm_addr_name,
-		      "] <= 0x%08h: ERROR: must not change hartsel while busy", dm_word);
+	    if (rg_abstractcs_busy) begin
+	       $display ("%0d: DM_Abstract_Commands.write: [", cur_cycle, dm_addr_name,
+			 "] <= 0x%08h: ERROR: must not change hartsel while busy", dm_word);
+	    end
 	 end
 
 	 else if (dm_addr == dm_addr_abstractcs)
diff --git a/src_Core/Debug_Module/DM_Run_Control.bsv b/src_Core/Debug_Module/DM_Run_Control.bsv
index a912d5b..92d3ce0 100644
--- a/src_Core/Debug_Module/DM_Run_Control.bsv
+++ b/src_Core/Debug_Module/DM_Run_Control.bsv
@@ -289,12 +289,12 @@ module mkDM_Run_Control (DM_Run_Control_IFC);
 	    else if (resumereq && (! rg_harts_running[hartsel])) begin
 	       f_harts_run_halt_reqs[hartsel].enq (True);
 	       rg_harts_resumeack[hartsel] <= False;
-	       $display ("%0d: %m.dmcontrol_write: hart %i resume request", cur_cycle, hartsel);
+	       $display ("%0d: %m.dmcontrol_write: hart %0d resume request", cur_cycle, hartsel);
 	    end
 	    // Halt hart(s)
 	    else if (haltreq && rg_harts_running[hartsel]) begin
 	       f_harts_run_halt_reqs[hartsel].enq (False);
-	       $display ("%0d: %m.dmcontrol_write: hart %i halt request", cur_cycle, hartsel);
+	       $display ("%0d: %m.dmcontrol_write: hart %0d halt request", cur_cycle, hartsel);
 	    end
 	 end
       endaction
@@ -326,7 +326,7 @@ module mkDM_Run_Control (DM_Run_Control_IFC);
 	 rg_harts_running[core]  <= running;
 
 	 if (verbosity != 0)
-	    $display ("%0d: %m.rl_harts_reset_rsp: hart %i running = ", cur_cycle, core, fshow (running));
+	    $display ("%0d: %m.rl_harts_reset_rsp: hart %0d running = ", cur_cycle, core, fshow (running));
    endrule
 
    // Response from system for NDM reset
@@ -348,7 +348,7 @@ module mkDM_Run_Control (DM_Run_Control_IFC);
 	    rg_harts_resumeack[core] <= True;
 
       if (verbosity != 0)
-	    $display ("%0d: %m.rl_harts_run_rsp hart: hart %i 'running' = ", cur_cycle, core, fshow (running));
+	    $display ("%0d: %m.rl_harts_run_rsp hart: hart %0d 'running' = ", cur_cycle, core, fshow (running));
    endrule
 
    // ----------------------------------------------------------------