From d509ab0fab8c2c1a48bf725344a36418a94af044 Mon Sep 17 00:00:00 2001
From: Peter Rugg <pdr32@cam.ac.uk>
Date: Wed, 12 Jul 2023 17:06:03 +0100
Subject: [PATCH] Mask off address bits in latency shim

---
 src_SSITH_P3/src_BSV/P3_Core.bsv | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/src_SSITH_P3/src_BSV/P3_Core.bsv b/src_SSITH_P3/src_BSV/P3_Core.bsv
index ecb1f93..94f3caa 100644
--- a/src_SSITH_P3/src_BSV/P3_Core.bsv
+++ b/src_SSITH_P3/src_BSV/P3_Core.bsv
@@ -224,7 +224,8 @@ module mkP3_Core (P3_Core_IFC);
               "\n                     w - ", fshow(wflit));
        let bresp = OKAY;
        let latency = truncate(wflit.wdata);
-       case(awflit.awaddr)
+       Bit#(12) addr = truncate(awflit.awaddr);
+       case(addr)
            0:       latencyCycles0 <= latency;
            64:      latencyCycles1 <= latency;
            default: bresp = SLVERR;
@@ -241,7 +242,7 @@ module mkP3_Core (P3_Core_IFC);
        Bit#(12) addr = truncate(arflit.araddr);
        let rresp = OKAY;
        Bit#(Wd_Data_Periph) rdata = ?;
-       case(arflit.araddr)
+       case(addr)
            0:       rdata = zeroExtend(latencyCycles0);
            64:      rdata = zeroExtend(latencyCycles1);
            default: rresp = SLVERR;