From d5e52a9ecb1e0711479865f1bcf42988de3e8ae6 Mon Sep 17 00:00:00 2001 From: Jonathan Woodruff Date: Fri, 5 Nov 2021 17:42:19 +0000 Subject: [PATCH] Revert to upstream direction predictors to reduce diffs and prepare for improvements that can be upstreamed. Basically, only use addresses in these predictors rather than capabilities, and just pass an address in from the FetchStage. --- src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv | 4 ++-- src_Core/RISCY_OOO/procs/lib/Bht.bsv | 10 ++++------ src_Core/RISCY_OOO/procs/lib/BrPred.bsv | 4 ++-- src_Core/RISCY_OOO/procs/lib/GSelectPred.bsv | 10 ++++------ src_Core/RISCY_OOO/procs/lib/GSharePred.bsv | 10 ++++------ src_Core/RISCY_OOO/procs/lib/TourPred.bsv | 10 ++++------ src_Core/RISCY_OOO/procs/lib/TourPredSecure.bsv | 12 +++++------- 7 files changed, 25 insertions(+), 35 deletions(-) diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv index d26dc78..9851594 100644 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv @@ -700,7 +700,7 @@ module mkFetchStage(FetchStage); // direction predict Bool pred_taken = False; if(dInst.iType == Br) begin - let pred_res <- dirPred.pred[i].pred(pc); + let pred_res <- dirPred.pred[i].pred(getAddr(pc)); pred_taken = pred_res.taken; dp_train = pred_res.train; end @@ -943,7 +943,7 @@ module mkFetchStage(FetchStage); //end if (iType == Br) begin // Train the direction predictor for all branches - dirPred.update(pc, taken, dpTrain, mispred); + dirPred.update(getAddr(pc), taken, dpTrain, mispred); end // train next addr pred when mispred if(mispred) begin diff --git a/src_Core/RISCY_OOO/procs/lib/Bht.bsv b/src_Core/RISCY_OOO/procs/lib/Bht.bsv index 79c1746..e87cb08 100644 --- a/src_Core/RISCY_OOO/procs/lib/Bht.bsv +++ b/src_Core/RISCY_OOO/procs/lib/Bht.bsv @@ -39,8 +39,6 @@ import ProcTypes::*; import RegFile::*; import Vector::*; import BrPred::*; -import CHERICC_Fat::*; -import CHERICap::*; export BhtTrainInfo; export mkBht; @@ -57,14 +55,14 @@ module mkBht(DirPredictor#(BhtTrainInfo)); // mkRegFileWCF is the RegFile version of mkConfigReg RegFile#(BhtIndex, Bit#(2)) hist <- mkRegFileWCF(0,fromInteger(valueOf(BhtEntries)-1)); - function BhtIndex getIndex(CapMem pc); - return truncate(getAddr(pc) >> 2); + function BhtIndex getIndex(Addr pc); + return truncate(pc >> 2); endfunction Vector#(SupSize, DirPred#(BhtTrainInfo)) predIfc; for(Integer i = 0; i < valueof(SupSize); i = i+1) begin predIfc[i] = (interface DirPred; - method ActionValue#(DirPredResult#(BhtTrainInfo)) pred(CapMem pc); + method ActionValue#(DirPredResult#(BhtTrainInfo)) pred(Addr pc); let index = getIndex(pc); Bit#(2) cnt = hist.sub(index); Bool taken = cnt[1] == 1; @@ -78,7 +76,7 @@ module mkBht(DirPredictor#(BhtTrainInfo)); interface pred = predIfc; - method Action update(CapMem pc, Bool taken, BhtTrainInfo train, Bool mispred); + method Action update(Addr pc, Bool taken, BhtTrainInfo train, Bool mispred); let index = getIndex(pc); let current_hist = hist.sub(index); Bit#(2) next_hist; diff --git a/src_Core/RISCY_OOO/procs/lib/BrPred.bsv b/src_Core/RISCY_OOO/procs/lib/BrPred.bsv index 1ac9456..8d074a4 100644 --- a/src_Core/RISCY_OOO/procs/lib/BrPred.bsv +++ b/src_Core/RISCY_OOO/procs/lib/BrPred.bsv @@ -73,12 +73,12 @@ typedef struct { } DirPredResult#(type trainInfoT) deriving(Bits, Eq, FShow); interface DirPred#(type trainInfoT); - method ActionValue#(DirPredResult#(trainInfoT)) pred(CapMem pc); + method ActionValue#(DirPredResult#(trainInfoT)) pred(Addr pc); endinterface interface DirPredictor#(type trainInfoT); interface Vector#(SupSize, DirPred#(trainInfoT)) pred; - method Action update(CapMem pc, Bool taken, trainInfoT train, Bool mispred); + method Action update(Addr pc, Bool taken, trainInfoT train, Bool mispred); method Action flush; method Bool flush_done; endinterface diff --git a/src_Core/RISCY_OOO/procs/lib/GSelectPred.bsv b/src_Core/RISCY_OOO/procs/lib/GSelectPred.bsv index a8eccfb..41b9f12 100644 --- a/src_Core/RISCY_OOO/procs/lib/GSelectPred.bsv +++ b/src_Core/RISCY_OOO/procs/lib/GSelectPred.bsv @@ -41,8 +41,6 @@ import Ehr::*; import Vector::*; import GlobalBrHistReg::*; import BrPred::*; -import CHERICC_Fat::*; -import CHERICap::*; export GSelectGHistSz; export GSelectGHist; @@ -85,8 +83,8 @@ module mkGSelectPred(DirPredictor#(GSelectTrainInfo)); Ehr#(TAdd#(1, SupSize), Bit#(TLog#(TAdd#(SupSize, 1)))) predCnt <- mkEhr(0); Ehr#(TAdd#(1, SupSize), Bit#(SupSize)) predRes <- mkEhr(0); - function BhtIndex getIndex(CapMem pc, GSelectGHist gHist); - Bit#(PCIndexSz) pcIdx = truncate(getAddr(pc) >> 2); + function BhtIndex getIndex(Addr pc, GSelectGHist gHist); + Bit#(PCIndexSz) pcIdx = truncate(pc >> 2); return {gHist, pcIdx}; endfunction @@ -108,7 +106,7 @@ module mkGSelectPred(DirPredictor#(GSelectTrainInfo)); Vector#(SupSize, DirPred#(GSelectTrainInfo)) predIfc; for(Integer i = 0; i < valueof(SupSize); i = i+1) begin predIfc[i] = (interface DirPred; - method ActionValue#(DirPredResult#(GSelectTrainInfo)) pred(CapMem pc); + method ActionValue#(DirPredResult#(GSelectTrainInfo)) pred(Addr pc); // get the global history // all previous branch in this cycle must be not taken // otherwise this branch should be on wrong path @@ -142,7 +140,7 @@ module mkGSelectPred(DirPredictor#(GSelectTrainInfo)); interface pred = predIfc; - method Action update(CapMem pc, Bool taken, GSelectTrainInfo train, Bool mispred); + method Action update(Addr pc, Bool taken, GSelectTrainInfo train, Bool mispred); // update history if mispred if(mispred) begin GSelectGHist newHist = truncate({pack(taken), train.gHist} >> 1); diff --git a/src_Core/RISCY_OOO/procs/lib/GSharePred.bsv b/src_Core/RISCY_OOO/procs/lib/GSharePred.bsv index ce04324..395ba46 100644 --- a/src_Core/RISCY_OOO/procs/lib/GSharePred.bsv +++ b/src_Core/RISCY_OOO/procs/lib/GSharePred.bsv @@ -41,8 +41,6 @@ import Ehr::*; import Vector::*; import GlobalBrHistReg::*; import BrPred::*; -import CHERICC_Fat::*; -import CHERICap::*; export GShareGHistSz; export GShareGHist; @@ -85,8 +83,8 @@ module mkGSharePred(DirPredictor#(GShareTrainInfo)); Ehr#(TAdd#(1, SupSize), Bit#(TLog#(TAdd#(SupSize, 1)))) predCnt <- mkEhr(0); Ehr#(TAdd#(1, SupSize), Bit#(SupSize)) predRes <- mkEhr(0); - function BhtIndex getIndex(CapMem pc, GShareGHist gHist); - Bit#(PCIndexSz) pcIdx = truncate(getAddr(pc) >> 2); + function BhtIndex getIndex(Addr pc, GShareGHist gHist); + Bit#(PCIndexSz) pcIdx = truncate(pc >> 2); return gHist ^ pcIdx; endfunction @@ -108,7 +106,7 @@ module mkGSharePred(DirPredictor#(GShareTrainInfo)); Vector#(SupSize, DirPred#(GShareTrainInfo)) predIfc; for(Integer i = 0; i < valueof(SupSize); i = i+1) begin predIfc[i] = (interface DirPred; - method ActionValue#(DirPredResult#(GShareTrainInfo)) pred(CapMem pc); + method ActionValue#(DirPredResult#(GShareTrainInfo)) pred(Addr pc); // get the global history // all previous branch in this cycle must be not taken // otherwise this branch should be on wrong path @@ -142,7 +140,7 @@ module mkGSharePred(DirPredictor#(GShareTrainInfo)); interface pred = predIfc; - method Action update(CapMem pc, Bool taken, GShareTrainInfo train, Bool mispred); + method Action update(Addr pc, Bool taken, GShareTrainInfo train, Bool mispred); // update history if mispred if(mispred) begin GShareGHist newHist = truncate({pack(taken), train.gHist} >> 1); diff --git a/src_Core/RISCY_OOO/procs/lib/TourPred.bsv b/src_Core/RISCY_OOO/procs/lib/TourPred.bsv index c03cccf..d751f0d 100644 --- a/src_Core/RISCY_OOO/procs/lib/TourPred.bsv +++ b/src_Core/RISCY_OOO/procs/lib/TourPred.bsv @@ -41,8 +41,6 @@ import Ehr::*; import Vector::*; import GlobalBrHistReg::*; import BrPred::*; -import CHERICC_Fat::*; -import CHERICap::*; export TourLocalHistSz; export TourLocalHist; @@ -96,8 +94,8 @@ module mkTourPred(DirPredictor#(TourTrainInfo)); Ehr#(TAdd#(1, SupSize), SupCnt) predCnt <- mkEhr(0); Ehr#(TAdd#(1, SupSize), Bit#(SupSize)) predRes <- mkEhr(0); - function PCIndex getPCIndex(CapMem pc); - return truncate(getAddr(pc) >> 2); + function PCIndex getPCIndex(Addr pc); + return truncate(pc >> 2); endfunction // common sat counter operations @@ -120,7 +118,7 @@ module mkTourPred(DirPredictor#(TourTrainInfo)); Vector#(SupSize, DirPred#(TourTrainInfo)) predIfc; for(Integer i = 0; i < valueof(SupSize); i = i+1) begin predIfc[i] = (interface DirPred; - method ActionValue#(DirPredResult#(TourTrainInfo)) pred(CapMem pc); + method ActionValue#(DirPredResult#(TourTrainInfo)) pred(Addr pc); // get local history & prediction TourLocalHist localHist = localHistTab.sub(getPCIndex(pc)); Bool localTaken = isTaken(localBht.sub(localHist)); @@ -166,7 +164,7 @@ module mkTourPred(DirPredictor#(TourTrainInfo)); interface pred = predIfc; - method Action update(CapMem pc, Bool taken, TourTrainInfo train, Bool mispred); + method Action update(Addr pc, Bool taken, TourTrainInfo train, Bool mispred); // update history if mispred if(mispred) begin TourGlobalHist newHist = truncateLSB({pack(taken), train.globalHist}); diff --git a/src_Core/RISCY_OOO/procs/lib/TourPredSecure.bsv b/src_Core/RISCY_OOO/procs/lib/TourPredSecure.bsv index b18e2a9..747b531 100644 --- a/src_Core/RISCY_OOO/procs/lib/TourPredSecure.bsv +++ b/src_Core/RISCY_OOO/procs/lib/TourPredSecure.bsv @@ -42,8 +42,6 @@ import Vector::*; import GlobalBrHistReg::*; import BrPred::*; import TourPred::*; -import CHERICC_Fat::*; -import CHERICap::*; export mkTourPredSecure; @@ -75,7 +73,7 @@ typedef TExp#(LgGlobalVecSz) GlobalVecSz; typedef Bit#(GlobalVecSz) GlobalVecSelect; typedef struct { - CapMem pc; + Addr pc; Bool taken; TourTrainInfo train; Bool mispred; @@ -105,8 +103,8 @@ module mkTourPredSecure(DirPredictor#(TourTrainInfo)); Reg#(Bool) flushDone <- mkReg(True); Reg#(TabIndex) flushIndex <- mkReg(0); - function Tuple2#(TabIndex, LocalHistVecSelect) getPCIndex(CapMem pc); - PCIndex pcIdx = truncate(getAddr(pc) >> 2); + function Tuple2#(TabIndex, LocalHistVecSelect) getPCIndex(Addr pc); + PCIndex pcIdx = truncate(pc >> 2); TabIndex tabIdx = truncateLSB(pcIdx); LocalHistVecSelect sel = truncate(pcIdx); return tuple2(tabIdx, sel); @@ -144,7 +142,7 @@ module mkTourPredSecure(DirPredictor#(TourTrainInfo)); Vector#(SupSize, DirPred#(TourTrainInfo)) predIfc; for(Integer i = 0; i < valueof(SupSize); i = i+1) begin predIfc[i] = (interface DirPred; - method ActionValue#(DirPredResult#(TourTrainInfo)) pred(CapMem pc); + method ActionValue#(DirPredResult#(TourTrainInfo)) pred(Addr pc); // get local history let {localHistTabIdx, localHistVecSel} = getPCIndex(pc); Vector#(LocalHistVecSz, TourLocalHist) localHistVec = localHistTab.sub(localHistTabIdx); @@ -255,7 +253,7 @@ module mkTourPredSecure(DirPredictor#(TourTrainInfo)); interface pred = predIfc; - method Action update(CapMem pc, Bool taken, TourTrainInfo train, Bool mispred); + method Action update(Addr pc, Bool taken, TourTrainInfo train, Bool mispred); updateEn.wset(TourUpdate {pc: pc, taken: taken, train: train, mispred: mispred}); endmethod