From d7a4d3497b15600525a3d4ec2e429862df0691c7 Mon Sep 17 00:00:00 2001 From: jon Date: Fri, 17 Jul 2020 16:39:13 +0100 Subject: [PATCH] Keep unaligned instruction fetch from breaking DII. --- src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv index df81f33..9ad508c 100644 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv @@ -579,6 +579,9 @@ module mkFetchStage(FetchStage); */ match { .posLastSupX2, .pred_next_pc } <- fav_pred_next_pc (pc); + `ifdef RVFI_DII + posLastSupX2 = 3; + `endif let next_fetch_pc = fromMaybe(addPc(pc, 2 * (fromInteger(posLastSupX2) + 1)), pred_next_pc); pc_reg[pc_fetch1_port] <= next_fetch_pc;