diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkAluDispToRegFifo.v b/src_SSITH_P3_sim/Verilog_RTL/mkAluDispToRegFifo.v index 5328e55..0d0571f 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkAluDispToRegFifo.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkAluDispToRegFifo.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkAluExeToFinFifo.v b/src_SSITH_P3_sim/Verilog_RTL/mkAluExeToFinFifo.v index 8740ef1..ca62b8e 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkAluExeToFinFifo.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkAluExeToFinFifo.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkAluRegToExeFifo.v b/src_SSITH_P3_sim/Verilog_RTL/mkAluRegToExeFifo.v index 797242e..43427ed 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkAluRegToExeFifo.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkAluRegToExeFifo.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkBht.v b/src_SSITH_P3_sim/Verilog_RTL/mkBht.v index f41b4ca..bbc0dff 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkBht.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkBht.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkCore.v b/src_SSITH_P3_sim/Verilog_RTL/mkCore.v index 2fd8385..0882bcc 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkCore.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkCore.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // @@ -86,7 +86,6 @@ // RDY_renameDebug_renameErr_get O 1 const // RDY_setMEIP O 1 const // RDY_setSEIP O 1 const -// RDY_setDEIP O 1 const // RDY_hart0_run_halt_server_request_put O 1 reg // hart0_run_halt_server_response_get O 1 reg // RDY_hart0_run_halt_server_response_get O 1 reg @@ -99,10 +98,6 @@ // RDY_hart0_csr_mem_server_request_put O 1 reg // hart0_csr_mem_server_response_get O 65 reg // RDY_hart0_csr_mem_server_response_get O 1 reg -// v_to_TV_0_get O 320 -// RDY_v_to_TV_0_get O 1 reg -// v_to_TV_1_get O 320 -// RDY_v_to_TV_1_get O 1 reg // CLK I 1 clock // RST_N I 1 reset // coreReq_start_startpc I 64 @@ -119,7 +114,6 @@ // recvDoStats_x I 1 reg // setMEIP_v I 1 // setSEIP_v I 1 -// setDEIP_v I 1 // hart0_run_halt_server_request_put I 1 reg // hart0_gpr_mem_server_request_put I 70 reg // hart0_fpr_mem_server_request_put I 70 reg @@ -144,7 +138,6 @@ // EN_deadlock_checkStarted_get I 1 unused // EN_setMEIP I 1 // EN_setSEIP I 1 -// EN_setDEIP I 1 // EN_hart0_run_halt_server_request_put I 1 // EN_hart0_gpr_mem_server_request_put I 1 // EN_hart0_fpr_mem_server_request_put I 1 @@ -164,8 +157,6 @@ // EN_hart0_gpr_mem_server_response_get I 1 // EN_hart0_fpr_mem_server_response_get I 1 // EN_hart0_csr_mem_server_response_get I 1 -// EN_v_to_TV_0_get I 1 -// EN_v_to_TV_1_get I 1 // // No combinational paths from inputs to outputs // @@ -362,10 +353,6 @@ module mkCore(CLK, EN_setSEIP, RDY_setSEIP, - setDEIP_v, - EN_setDEIP, - RDY_setDEIP, - hart0_run_halt_server_request_put, EN_hart0_run_halt_server_request_put, RDY_hart0_run_halt_server_request_put, @@ -396,15 +383,7 @@ module mkCore(CLK, EN_hart0_csr_mem_server_response_get, hart0_csr_mem_server_response_get, - RDY_hart0_csr_mem_server_response_get, - - EN_v_to_TV_0_get, - v_to_TV_0_get, - RDY_v_to_TV_0_get, - - EN_v_to_TV_1_get, - v_to_TV_1_get, - RDY_v_to_TV_1_get); + RDY_hart0_csr_mem_server_response_get); input CLK; input RST_N; @@ -633,11 +612,6 @@ module mkCore(CLK, input EN_setSEIP; output RDY_setSEIP; - // action method setDEIP - input setDEIP_v; - input EN_setDEIP; - output RDY_setDEIP; - // action method hart0_run_halt_server_request_put input hart0_run_halt_server_request_put; input EN_hart0_run_halt_server_request_put; @@ -678,19 +652,8 @@ module mkCore(CLK, output [64 : 0] hart0_csr_mem_server_response_get; output RDY_hart0_csr_mem_server_response_get; - // actionvalue method v_to_TV_0_get - input EN_v_to_TV_0_get; - output [319 : 0] v_to_TV_0_get; - output RDY_v_to_TV_0_get; - - // actionvalue method v_to_TV_1_get - input EN_v_to_TV_1_get; - output [319 : 0] v_to_TV_1_get; - output RDY_v_to_TV_1_get; - // signals for module outputs wire [578 : 0] dCacheToParent_rsToP_first, iCacheToParent_rsToP_first; - wire [319 : 0] v_to_TV_0_get, v_to_TV_1_get; wire [162 : 0] deadlock_commitInstStuck_get, deadlock_commitUserInstStuck_get; wire [141 : 0] mmioToPlatform_cRq_first; @@ -757,7 +720,6 @@ module mkCore(CLK, RDY_recvDoStats, RDY_renameDebug_renameErr_get, RDY_sendDoStats, - RDY_setDEIP, RDY_setMEIP, RDY_setSEIP, RDY_tlbToMem_memReq_deq, @@ -765,8 +727,6 @@ module mkCore(CLK, RDY_tlbToMem_memReq_notEmpty, RDY_tlbToMem_respLd_enq, RDY_tlbToMem_respLd_notFull, - RDY_v_to_TV_0_get, - RDY_v_to_TV_1_get, dCacheToParent_fromP_notFull, dCacheToParent_rqToP_notEmpty, dCacheToParent_rsToP_notEmpty, @@ -1357,11 +1317,6 @@ module mkCore(CLK, reg csrInstOrInterruptInflight_rl; wire csrInstOrInterruptInflight_rl$D_IN, csrInstOrInterruptInflight_rl$EN; - // register csrf_debug_int_pend - reg csrf_debug_int_pend; - reg csrf_debug_int_pend$D_IN; - wire csrf_debug_int_pend$EN; - // register csrf_external_int_en_vec_0 reg csrf_external_int_en_vec_0; wire csrf_external_int_en_vec_0$D_IN, csrf_external_int_en_vec_0$EN; @@ -1540,7 +1495,7 @@ module mkCore(CLK, // register csrf_prv_reg reg [1 : 0] csrf_prv_reg; - wire [1 : 0] csrf_prv_reg$D_IN; + reg [1 : 0] csrf_prv_reg$D_IN; wire csrf_prv_reg$EN; // register csrf_rg_dcsr @@ -3755,22 +3710,6 @@ module mkCore(CLK, specTagManager$canClaim, specTagManager$specUpdate_incorrectSpeculation_kill_all; - // ports of submodule v_f_to_TV_0 - wire [319 : 0] v_f_to_TV_0$D_IN, v_f_to_TV_0$D_OUT; - wire v_f_to_TV_0$CLR, - v_f_to_TV_0$DEQ, - v_f_to_TV_0$EMPTY_N, - v_f_to_TV_0$ENQ, - v_f_to_TV_0$FULL_N; - - // ports of submodule v_f_to_TV_1 - wire [319 : 0] v_f_to_TV_1$D_IN, v_f_to_TV_1$D_OUT; - wire v_f_to_TV_1$CLR, - v_f_to_TV_1$DEQ, - v_f_to_TV_1$EMPTY_N, - v_f_to_TV_1$ENQ, - v_f_to_TV_1$FULL_N; - // rule scheduling signals wire CAN_FIRE_RL_commitStage_doCommitKilledLd, CAN_FIRE_RL_commitStage_doCommitNormalInst, @@ -4006,13 +3945,10 @@ module mkCore(CLK, CAN_FIRE_recvDoStats, CAN_FIRE_renameDebug_renameErr_get, CAN_FIRE_sendDoStats, - CAN_FIRE_setDEIP, CAN_FIRE_setMEIP, CAN_FIRE_setSEIP, CAN_FIRE_tlbToMem_memReq_deq, CAN_FIRE_tlbToMem_respLd_enq, - CAN_FIRE_v_to_TV_0_get, - CAN_FIRE_v_to_TV_1_get, WILL_FIRE_RL_commitStage_doCommitKilledLd, WILL_FIRE_RL_commitStage_doCommitNormalInst, WILL_FIRE_RL_commitStage_doCommitSystemInst, @@ -4247,13 +4183,10 @@ module mkCore(CLK, WILL_FIRE_recvDoStats, WILL_FIRE_renameDebug_renameErr_get, WILL_FIRE_sendDoStats, - WILL_FIRE_setDEIP, WILL_FIRE_setMEIP, WILL_FIRE_setSEIP, WILL_FIRE_tlbToMem_memReq_deq, - WILL_FIRE_tlbToMem_respLd_enq, - WILL_FIRE_v_to_TV_0_get, - WILL_FIRE_v_to_TV_1_get; + WILL_FIRE_tlbToMem_respLd_enq; // inputs to muxes for submodule ports reg [63 : 0] MUX_coreFix_memExe_lsq$respLd_2__VAL_1, @@ -4272,7 +4205,6 @@ module mkCore(CLK, MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_2, MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_3, MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_4; - wire [319 : 0] MUX_v_f_to_TV_0$enq_1__VAL_1; wire [282 : 0] MUX_rob$enqPort_0_enq_1__VAL_1, MUX_rob$enqPort_0_enq_1__VAL_2, MUX_rob$enqPort_0_enq_1__VAL_3; @@ -4325,6 +4257,8 @@ module mkCore(CLK, MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__VAL_2; wire [57 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_3__VAL_1, MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_3__VAL_2; + wire [48 : 0] MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1, + MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1; wire [29 : 0] MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_1, MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_2; wire [26 : 0] MUX_regRenamingTable$rename_0_getRename_1__VAL_2, @@ -4386,6 +4320,7 @@ module mkCore(CLK, MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__SEL_2, MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__SEL_1, MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__SEL_2, + MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1, MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__SEL_1, MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__SEL_2, MUX_coreFix_memExe_lsq$getHit_1__SEL_1, @@ -4401,12 +4336,12 @@ module mkCore(CLK, MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_1, MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_2, MUX_csrInstOrInterruptInflight_dummy_1_0$wset_1__VAL_1, - MUX_csrf_debug_int_pend$write_1__SEL_1, - MUX_csrf_debug_int_pend$write_1__SEL_2, MUX_csrf_external_int_en_vec_0$write_1__SEL_1, MUX_csrf_external_int_en_vec_3$write_1__SEL_1, MUX_csrf_external_int_pend_vec_0$write_1__SEL_1, MUX_csrf_external_int_pend_vec_0$write_1__SEL_2, + MUX_csrf_external_int_pend_vec_3$write_1__SEL_1, + MUX_csrf_external_int_pend_vec_3$write_1__SEL_2, MUX_csrf_fflags_reg$write_1__SEL_1, MUX_csrf_fflags_reg$write_1__SEL_2, MUX_csrf_fflags_reg$write_1__SEL_3, @@ -4443,8 +4378,10 @@ module mkCore(CLK, MUX_csrf_prev_ie_vec_1$write_1__VAL_1, MUX_csrf_prev_ie_vec_3$write_1__SEL_1, MUX_csrf_prev_ie_vec_3$write_1__VAL_1, + MUX_csrf_prv_reg$write_1__SEL_1, + MUX_csrf_prv_reg$write_1__SEL_2, + MUX_csrf_prv_reg$write_1__SEL_3, MUX_csrf_rg_dcsr$write_1__SEL_1, - MUX_csrf_rg_dcsr$write_1__SEL_3, MUX_csrf_rg_dpc$write_1__SEL_1, MUX_csrf_rg_dpc$write_1__SEL_3, MUX_csrf_rg_dscratch0$write_1__SEL_1, @@ -4465,7 +4402,6 @@ module mkCore(CLK, MUX_csrf_stvec_base_hi_reg$write_1__SEL_1, MUX_epochManager$updatePrevEpoch_0_update_1__SEL_2, MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2, - MUX_fetchStage$redirect_1__SEL_1, MUX_flush_reservation$write_1__SEL_2, MUX_flush_tlbs$write_1__SEL_1, MUX_regRenamingTable$rename_0_getRename_1__SEL_1, @@ -4488,62 +4424,60 @@ module mkCore(CLK, MUX_sbCons$setReady_3_put_1__SEL_1, MUX_sbCons$setReady_3_put_1__SEL_2, MUX_sbCons$setReady_3_put_1__SEL_3, - MUX_started$write_1__SEL_1, - MUX_update_vm_info$write_1__SEL_2, - MUX_v_f_to_TV_0$enq_1__SEL_1; + MUX_started$write_1__SEL_1; // remaining internal signals reg [511 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2528; - reg [63 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q292, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q293, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q23, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q24, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q25, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q254, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q255, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q26, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q27, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q28, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q267, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q245, + reg [63 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q282, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q283, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q15, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q16, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q17, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q18, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q19, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q20, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q244, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q245, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q257, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q237, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q238, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q239, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q240, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q241, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q242, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q246, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q247, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q248, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q249, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q250, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q256, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q257, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q258, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10055, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2968, - addr__h292300, - curData__h193733, - data_out__h727964, - rVal1__h613231, - rVal1__h637895, - trap_val__h708107, - x__h198472; - reg [51 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q20, - CASE_guard05685_0b0_sfdin13905_BITS_56_TO_5_0b_ETC__q217, - CASE_guard05685_0b0_sfdin13905_BITS_56_TO_5_0b_ETC__q218, - CASE_guard14754_0b0_theResult___snd22690_BITS__ETC__q219, - CASE_guard14754_0b0_theResult___snd22690_BITS__ETC__q220, - CASE_guard35226_0b0_theResult___snd43138_BITS__ETC__q205, - CASE_guard35226_0b0_theResult___snd43138_BITS__ETC__q206, - CASE_guard44538_0b0_sfdin52758_BITS_56_TO_5_0b_ETC__q207, - CASE_guard44538_0b0_sfdin52758_BITS_56_TO_5_0b_ETC__q208, - CASE_guard53607_0b0_theResult___snd61543_BITS__ETC__q209, - CASE_guard53607_0b0_theResult___snd61543_BITS__ETC__q210, - CASE_guard74530_0b0_theResult___snd82442_BITS__ETC__q221, - CASE_guard74530_0b0_theResult___snd82442_BITS__ETC__q222, - CASE_guard83842_0b0_sfdin92062_BITS_56_TO_5_0b_ETC__q223, - CASE_guard83842_0b0_sfdin92062_BITS_56_TO_5_0b_ETC__q224, - CASE_guard92911_0b0_theResult___snd00847_BITS__ETC__q225, - CASE_guard92911_0b0_theResult___snd00847_BITS__ETC__q226, - CASE_guard96373_0b0_theResult___snd04285_BITS__ETC__q215, - CASE_guard96373_0b0_theResult___snd04285_BITS__ETC__q216, + addr__h291992, + curData__h193425, + data_out__h723975, + rVal1__h612922, + rVal1__h637560, + trap_val__h706787, + x__h198164; + reg [51 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q10, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q12, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q8, + CASE_guard05376_0b0_sfdin13596_BITS_56_TO_5_0b_ETC__q209, + CASE_guard05376_0b0_sfdin13596_BITS_56_TO_5_0b_ETC__q210, + CASE_guard14445_0b0_theResult___snd22381_BITS__ETC__q211, + CASE_guard14445_0b0_theResult___snd22381_BITS__ETC__q212, + CASE_guard34917_0b0_theResult___snd42829_BITS__ETC__q197, + CASE_guard34917_0b0_theResult___snd42829_BITS__ETC__q198, + CASE_guard44229_0b0_sfdin52449_BITS_56_TO_5_0b_ETC__q199, + CASE_guard44229_0b0_sfdin52449_BITS_56_TO_5_0b_ETC__q200, + CASE_guard53298_0b0_theResult___snd61234_BITS__ETC__q201, + CASE_guard53298_0b0_theResult___snd61234_BITS__ETC__q202, + CASE_guard74221_0b0_theResult___snd82133_BITS__ETC__q213, + CASE_guard74221_0b0_theResult___snd82133_BITS__ETC__q214, + CASE_guard83533_0b0_sfdin91753_BITS_56_TO_5_0b_ETC__q215, + CASE_guard83533_0b0_sfdin91753_BITS_56_TO_5_0b_ETC__q216, + CASE_guard92602_0b0_theResult___snd00538_BITS__ETC__q217, + CASE_guard92602_0b0_theResult___snd00538_BITS__ETC__q218, + CASE_guard96064_0b0_theResult___snd03976_BITS__ETC__q205, + CASE_guard96064_0b0_theResult___snd03976_BITS__ETC__q206, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10710, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10736, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10755, @@ -4555,90 +4489,86 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9985; reg [31 : 0] SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1356, SEL_ARR_mmio_dataRespQ_data_0_109_BITS_31_TO_0_ETC___d1408; - reg [22 : 0] CASE_guard02799_0b0_theResult___snd10798_BITS__ETC__q83, - CASE_guard02799_0b0_theResult___snd10798_BITS__ETC__q84, - CASE_guard11729_0b0_sfdin19951_BITS_56_TO_34_0_ETC__q87, - CASE_guard11729_0b0_sfdin19951_BITS_56_TO_34_0_ETC__q88, - CASE_guard20565_0b0_theResult___snd28588_BITS__ETC__q89, - CASE_guard20565_0b0_theResult___snd28588_BITS__ETC__q90, - CASE_guard39787_0b0_sfdin47880_BITS_56_TO_34_0_ETC__q120, - CASE_guard39787_0b0_sfdin47880_BITS_56_TO_34_0_ETC__q121, - CASE_guard48393_0b0_sfdin56488_BITS_56_TO_34_0_ETC__q50, - CASE_guard48393_0b0_sfdin56488_BITS_56_TO_34_0_ETC__q51, - CASE_guard48494_0b0_theResult___snd56493_BITS__ETC__q118, - CASE_guard48494_0b0_theResult___snd56493_BITS__ETC__q119, - CASE_guard57102_0b0_theResult___snd65101_BITS__ETC__q48, - CASE_guard57102_0b0_theResult___snd65101_BITS__ETC__q49, - CASE_guard57424_0b0_sfdin65646_BITS_56_TO_34_0_ETC__q122, - CASE_guard57424_0b0_sfdin65646_BITS_56_TO_34_0_ETC__q123, - CASE_guard66032_0b0_sfdin74254_BITS_56_TO_34_0_ETC__q52, - CASE_guard66032_0b0_sfdin74254_BITS_56_TO_34_0_ETC__q53, - CASE_guard66260_0b0_theResult___snd74283_BITS__ETC__q125, - CASE_guard66260_0b0_theResult___snd74283_BITS__ETC__q126, - CASE_guard74868_0b0_theResult___snd82891_BITS__ETC__q54, - CASE_guard74868_0b0_theResult___snd82891_BITS__ETC__q55, - CASE_guard94092_0b0_sfdin02185_BITS_56_TO_34_0_ETC__q85, - CASE_guard94092_0b0_sfdin02185_BITS_56_TO_34_0_ETC__q86, - _theResult___fst_sfd__h348366, - _theResult___fst_sfd__h357089, - _theResult___fst_sfd__h365671, - _theResult___fst_sfd__h374855, - _theResult___fst_sfd__h383491, - _theResult___fst_sfd__h394065, - _theResult___fst_sfd__h402786, - _theResult___fst_sfd__h411368, - _theResult___fst_sfd__h420552, - _theResult___fst_sfd__h429188, - _theResult___fst_sfd__h439760, - _theResult___fst_sfd__h448481, - _theResult___fst_sfd__h457063, - _theResult___fst_sfd__h466247, - _theResult___fst_sfd__h474883; - reg [20 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_15_ETC__q282, - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q231, - CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q279, - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_15_ETC__q288, - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q228, - CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q285, - CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q295, - CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q291, - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d13064, - IF_fetchStage_pipelines_1_first__2943_BITS_194_ETC___d13758; + reg [22 : 0] CASE_guard02490_0b0_theResult___snd10489_BITS__ETC__q77, + CASE_guard02490_0b0_theResult___snd10489_BITS__ETC__q78, + CASE_guard11420_0b0_sfdin19642_BITS_56_TO_34_0_ETC__q79, + CASE_guard11420_0b0_sfdin19642_BITS_56_TO_34_0_ETC__q80, + CASE_guard20256_0b0_theResult___snd28279_BITS__ETC__q81, + CASE_guard20256_0b0_theResult___snd28279_BITS__ETC__q82, + CASE_guard39478_0b0_sfdin47571_BITS_56_TO_34_0_ETC__q112, + CASE_guard39478_0b0_sfdin47571_BITS_56_TO_34_0_ETC__q113, + CASE_guard48084_0b0_sfdin56179_BITS_56_TO_34_0_ETC__q40, + CASE_guard48084_0b0_sfdin56179_BITS_56_TO_34_0_ETC__q41, + CASE_guard48185_0b0_theResult___snd56184_BITS__ETC__q110, + CASE_guard48185_0b0_theResult___snd56184_BITS__ETC__q111, + CASE_guard56793_0b0_theResult___snd64792_BITS__ETC__q42, + CASE_guard56793_0b0_theResult___snd64792_BITS__ETC__q43, + CASE_guard57115_0b0_sfdin65337_BITS_56_TO_34_0_ETC__q114, + CASE_guard57115_0b0_sfdin65337_BITS_56_TO_34_0_ETC__q115, + CASE_guard65723_0b0_sfdin73945_BITS_56_TO_34_0_ETC__q44, + CASE_guard65723_0b0_sfdin73945_BITS_56_TO_34_0_ETC__q45, + CASE_guard65951_0b0_theResult___snd73974_BITS__ETC__q116, + CASE_guard65951_0b0_theResult___snd73974_BITS__ETC__q117, + CASE_guard74559_0b0_theResult___snd82582_BITS__ETC__q46, + CASE_guard74559_0b0_theResult___snd82582_BITS__ETC__q47, + CASE_guard93783_0b0_sfdin01876_BITS_56_TO_34_0_ETC__q75, + CASE_guard93783_0b0_sfdin01876_BITS_56_TO_34_0_ETC__q76, + _theResult___fst_sfd__h348057, + _theResult___fst_sfd__h356780, + _theResult___fst_sfd__h365362, + _theResult___fst_sfd__h374546, + _theResult___fst_sfd__h383182, + _theResult___fst_sfd__h393756, + _theResult___fst_sfd__h402477, + _theResult___fst_sfd__h411059, + _theResult___fst_sfd__h420243, + _theResult___fst_sfd__h428879, + _theResult___fst_sfd__h439451, + _theResult___fst_sfd__h448172, + _theResult___fst_sfd__h456754, + _theResult___fst_sfd__h465938, + _theResult___fst_sfd__h474574; + reg [20 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_15_ETC__q272, + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q223, + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q269, + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_15_ETC__q278, + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q220, + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q275, + CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q285, + CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q281, + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d13060, + IF_fetchStage_pipelines_1_first__2940_BITS_194_ETC___d13754; reg [15 : 0] SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1367, SEL_ARR_mmio_dataRespQ_data_0_109_BITS_15_TO_0_ETC___d1417; - reg [11 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q283, - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_394_ETC__q232, - CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q280, - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q289, - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q229, - CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q286, - CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q235, - CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q275, - CASE_robdeqPort_1_deq_data_BITS_180_TO_169_1__ETC__q297, - CASE_v_f_to_TV_0D_OUT_BITS_153_TO_142_1_v_f_t_ETC__q5, - CASE_v_f_to_TV_1D_OUT_BITS_153_TO_142_1_v_f_t_ETC__q1, - IF_fetchStage_pipelines_0_first__2934_BITS_172_ETC___d13146; - reg [10 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q18, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q19, - CASE_guard05685_0b0_theResult___fst_exp13911_0_ETC__q211, - CASE_guard05685_0b0_theResult___fst_exp13911_0_ETC__q212, - CASE_guard14754_0b0_theResult___fst_exp22744_0_ETC__q213, - CASE_guard14754_0b0_theResult___fst_exp22744_0_ETC__q214, - CASE_guard35226_0b0_theResult___fst_exp43187_0_ETC__q183, - CASE_guard35226_0b0_theResult___fst_exp43187_0_ETC__q184, - CASE_guard44538_0b0_theResult___fst_exp52764_0_ETC__q185, - CASE_guard44538_0b0_theResult___fst_exp52764_0_ETC__q186, - CASE_guard53607_0b0_theResult___fst_exp61597_0_ETC__q187, - CASE_guard53607_0b0_theResult___fst_exp61597_0_ETC__q188, - CASE_guard74530_0b0_theResult___fst_exp82491_0_ETC__q160, - CASE_guard74530_0b0_theResult___fst_exp82491_0_ETC__q161, - CASE_guard83842_0b0_theResult___fst_exp92068_0_ETC__q189, - CASE_guard83842_0b0_theResult___fst_exp92068_0_ETC__q190, - CASE_guard92911_0b0_theResult___fst_exp00901_0_ETC__q191, - CASE_guard92911_0b0_theResult___fst_exp00901_0_ETC__q192, - CASE_guard96373_0b0_theResult___fst_exp04334_0_ETC__q143, - CASE_guard96373_0b0_theResult___fst_exp04334_0_ETC__q144, + reg [11 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q273, + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_394_ETC__q224, + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q270, + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q279, + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q221, + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q276, + CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q227, + IF_fetchStage_pipelines_0_first__2931_BITS_172_ETC___d13142; + reg [10 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q11, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q7, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q9, + CASE_guard05376_0b0_theResult___fst_exp13602_0_ETC__q203, + CASE_guard05376_0b0_theResult___fst_exp13602_0_ETC__q204, + CASE_guard14445_0b0_theResult___fst_exp22435_0_ETC__q207, + CASE_guard14445_0b0_theResult___fst_exp22435_0_ETC__q208, + CASE_guard34917_0b0_theResult___fst_exp42878_0_ETC__q175, + CASE_guard34917_0b0_theResult___fst_exp42878_0_ETC__q176, + CASE_guard44229_0b0_theResult___fst_exp52455_0_ETC__q177, + CASE_guard44229_0b0_theResult___fst_exp52455_0_ETC__q178, + CASE_guard53298_0b0_theResult___fst_exp61288_0_ETC__q179, + CASE_guard53298_0b0_theResult___fst_exp61288_0_ETC__q180, + CASE_guard74221_0b0_theResult___fst_exp82182_0_ETC__q152, + CASE_guard74221_0b0_theResult___fst_exp82182_0_ETC__q153, + CASE_guard83533_0b0_theResult___fst_exp91759_0_ETC__q183, + CASE_guard83533_0b0_theResult___fst_exp91759_0_ETC__q184, + CASE_guard92602_0b0_theResult___fst_exp00592_0_ETC__q181, + CASE_guard92602_0b0_theResult___fst_exp00592_0_ETC__q182, + CASE_guard96064_0b0_theResult___fst_exp04025_0_ETC__q135, + CASE_guard96064_0b0_theResult___fst_exp04025_0_ETC__q136, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10615, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10653, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10684, @@ -4648,161 +4578,153 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9845, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9883, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9914; - reg [7 : 0] CASE_guard02799_0b0_theResult___fst_exp10847_0_ETC__q68, - CASE_guard02799_0b0_theResult___fst_exp10847_0_ETC__q69, - CASE_guard11729_0b0_theResult___fst_exp19957_0_ETC__q76, - CASE_guard11729_0b0_theResult___fst_exp19957_0_ETC__q77, - CASE_guard20565_0b0_theResult___fst_exp28642_0_ETC__q81, - CASE_guard20565_0b0_theResult___fst_exp28642_0_ETC__q82, - CASE_guard39787_0b0_theResult___fst_exp47886_0_ETC__q105, - CASE_guard39787_0b0_theResult___fst_exp47886_0_ETC__q106, - CASE_guard48393_0b0_theResult___fst_exp56494_0_ETC__q35, - CASE_guard48393_0b0_theResult___fst_exp56494_0_ETC__q36, - CASE_guard48494_0b0_theResult___fst_exp56542_0_ETC__q103, - CASE_guard48494_0b0_theResult___fst_exp56542_0_ETC__q104, - CASE_guard57102_0b0_theResult___fst_exp65150_0_ETC__q33, - CASE_guard57102_0b0_theResult___fst_exp65150_0_ETC__q34, - CASE_guard57424_0b0_theResult___fst_exp65652_0_ETC__q111, - CASE_guard57424_0b0_theResult___fst_exp65652_0_ETC__q112, - CASE_guard66032_0b0_theResult___fst_exp74260_0_ETC__q41, - CASE_guard66032_0b0_theResult___fst_exp74260_0_ETC__q42, - CASE_guard66260_0b0_theResult___fst_exp74337_0_ETC__q116, - CASE_guard66260_0b0_theResult___fst_exp74337_0_ETC__q117, - CASE_guard74868_0b0_theResult___fst_exp82945_0_ETC__q46, - CASE_guard74868_0b0_theResult___fst_exp82945_0_ETC__q47, - CASE_guard94092_0b0_theResult___fst_exp02191_0_ETC__q70, - CASE_guard94092_0b0_theResult___fst_exp02191_0_ETC__q71, + reg [7 : 0] CASE_guard02490_0b0_theResult___fst_exp10538_0_ETC__q60, + CASE_guard02490_0b0_theResult___fst_exp10538_0_ETC__q61, + CASE_guard11420_0b0_theResult___fst_exp19648_0_ETC__q68, + CASE_guard11420_0b0_theResult___fst_exp19648_0_ETC__q69, + CASE_guard20256_0b0_theResult___fst_exp28333_0_ETC__q73, + CASE_guard20256_0b0_theResult___fst_exp28333_0_ETC__q74, + CASE_guard39478_0b0_theResult___fst_exp47577_0_ETC__q97, + CASE_guard39478_0b0_theResult___fst_exp47577_0_ETC__q98, + CASE_guard48084_0b0_theResult___fst_exp56185_0_ETC__q27, + CASE_guard48084_0b0_theResult___fst_exp56185_0_ETC__q28, + CASE_guard48185_0b0_theResult___fst_exp56233_0_ETC__q95, + CASE_guard48185_0b0_theResult___fst_exp56233_0_ETC__q96, + CASE_guard56793_0b0_theResult___fst_exp64841_0_ETC__q25, + CASE_guard56793_0b0_theResult___fst_exp64841_0_ETC__q26, + CASE_guard57115_0b0_theResult___fst_exp65343_0_ETC__q103, + CASE_guard57115_0b0_theResult___fst_exp65343_0_ETC__q104, + CASE_guard65723_0b0_theResult___fst_exp73951_0_ETC__q33, + CASE_guard65723_0b0_theResult___fst_exp73951_0_ETC__q34, + CASE_guard65951_0b0_theResult___fst_exp74028_0_ETC__q108, + CASE_guard65951_0b0_theResult___fst_exp74028_0_ETC__q109, + CASE_guard74559_0b0_theResult___fst_exp82636_0_ETC__q38, + CASE_guard74559_0b0_theResult___fst_exp82636_0_ETC__q39, + CASE_guard93783_0b0_theResult___fst_exp01882_0_ETC__q62, + CASE_guard93783_0b0_theResult___fst_exp01882_0_ETC__q63, SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1381, SEL_ARR_mmio_dataRespQ_data_0_109_BITS_7_TO_0__ETC___d1430, - _theResult___fst_exp__h348365, - _theResult___fst_exp__h357088, - _theResult___fst_exp__h365670, - _theResult___fst_exp__h374854, - _theResult___fst_exp__h383490, - _theResult___fst_exp__h394064, - _theResult___fst_exp__h402785, - _theResult___fst_exp__h411367, - _theResult___fst_exp__h420551, - _theResult___fst_exp__h429187, - _theResult___fst_exp__h439759, - _theResult___fst_exp__h448480, - _theResult___fst_exp__h457062, - _theResult___fst_exp__h466246, - _theResult___fst_exp__h474882; - reg [5 : 0] CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q277, - CASE_mmio_cRqQ_data_0_BITS_77_TO_76_0_mmio_cRq_ETC__q9, - CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q272, - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989; - reg [4 : 0] IF_fetchStage_pipelines_0_first__2934_BITS_191_ETC___d14310, - IF_fetchStage_pipelines_1_first__2943_BITS_191_ETC___d14474; - reg [3 : 0] CASE_checkForException_3180_BITS_3_TO_0_0_chec_ETC__q234, - CASE_coreFix_memExe_dTlbprocResp_BITS_105_TO__ETC__q21, - CASE_coreFix_memExe_dTlbprocResp_BITS_109_TO__ETC__q22, - CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q274, - CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q273, - CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q251, - CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q252, - CASE_v_f_to_TV_0D_OUT_BITS_139_TO_136_0_v_f_t_ETC__q6, - CASE_v_f_to_TV_0D_OUT_BITS_139_TO_136_0_v_f_t_ETC__q7, - CASE_v_f_to_TV_1D_OUT_BITS_139_TO_136_0_v_f_t_ETC__q2, - CASE_v_f_to_TV_1D_OUT_BITS_139_TO_136_0_v_f_t_ETC__q3, - IF_fetchStage_pipelines_0_first__2934_BITS_191_ETC___d14313, - IF_fetchStage_pipelines_0_first__2934_BIT_68_2_ETC___d13300, - IF_fetchStage_pipelines_1_first__2943_BITS_191_ETC___d14475, - i__h707083, - i__h707243; - reg [2 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q281, - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q230, - CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q278, - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q287, - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q227, - CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q284, - CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q294, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q253, - CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q290, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q266, - CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q233, - CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q236, + _theResult___fst_exp__h348056, + _theResult___fst_exp__h356779, + _theResult___fst_exp__h365361, + _theResult___fst_exp__h374545, + _theResult___fst_exp__h383181, + _theResult___fst_exp__h393755, + _theResult___fst_exp__h402476, + _theResult___fst_exp__h411058, + _theResult___fst_exp__h420242, + _theResult___fst_exp__h428878, + _theResult___fst_exp__h439450, + _theResult___fst_exp__h448171, + _theResult___fst_exp__h456753, + _theResult___fst_exp__h465937, + _theResult___fst_exp__h474573; + reg [5 : 0] CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q267, + CASE_mmio_cRqQ_data_0_BITS_77_TO_76_0_mmio_cRq_ETC__q1, + CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q264, + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931; + reg [4 : 0] IF_fetchStage_pipelines_0_first__2931_BITS_191_ETC___d14306, + IF_fetchStage_pipelines_1_first__2940_BITS_191_ETC___d14470; + reg [3 : 0] CASE_checkForException_3176_BITS_3_TO_0_0_chec_ETC__q226, + CASE_coreFix_memExe_dTlbprocResp_BITS_105_TO__ETC__q13, + CASE_coreFix_memExe_dTlbprocResp_BITS_109_TO__ETC__q14, + CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q266, + CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q265, + CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q261, + CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q262, + IF_fetchStage_pipelines_0_first__2931_BITS_191_ETC___d14309, + IF_fetchStage_pipelines_0_first__2931_BIT_68_2_ETC___d13296, + IF_fetchStage_pipelines_1_first__2940_BITS_191_ETC___d14471, + i__h705763, + i__h705923; + reg [2 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q271, + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q222, + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q268, + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q277, + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q219, + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q274, + CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q284, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q243, + CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q280, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q256, + CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q225, + CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q228, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10828, - x__h288079, - x__h293849; - reg [1 : 0] CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q261, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q296, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q264, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q268, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q259, - CASE_robdeqPort_0_deq_data_BITS_97_TO_96_0_ro_ETC__q276, - CASE_robdeqPort_1_deq_data_BITS_97_TO_96_0_ro_ETC__q298, - CASE_v_f_to_TV_0D_OUT_BITS_71_TO_70_0_v_f_to__ETC__q8, - CASE_v_f_to_TV_1D_OUT_BITS_71_TO_70_0_v_f_to__ETC__q4; - reg CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q146, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q148, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q150, + x__h287771, + x__h293541; + reg [1 : 0] CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q251, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q286, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q254, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q258, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q249; + reg CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q138, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q140, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q142, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q155, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q157, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q159, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q161, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q167, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q169, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q171, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q173, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q186, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q188, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q190, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q192, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q198, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q200, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q204, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q263, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q262, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q269, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q270, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q265, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q260, - CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q243, - CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q244, - CASE_fetchStage_pipelines_0_canDeq__2932_AND_N_ETC__q241, - CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q240, - CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q237, - CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q238, - CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q242, - CASE_guard02799_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q94, - CASE_guard02799_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q93, - CASE_guard05685_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145, - CASE_guard11729_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q96, - CASE_guard11729_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q95, - CASE_guard14754_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149, - CASE_guard20565_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q98, - CASE_guard20565_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q97, - CASE_guard35226_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203, - CASE_guard35226_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193, - CASE_guard39787_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q127, - CASE_guard39787_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q124, - CASE_guard44538_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199, - CASE_guard44538_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197, - CASE_guard48393_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q57, - CASE_guard48393_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q56, - CASE_guard48494_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q129, - CASE_guard48494_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q128, - CASE_guard53607_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201, - CASE_guard53607_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195, - CASE_guard57102_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q59, - CASE_guard57102_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q58, - CASE_guard57424_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q131, - CASE_guard57424_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q130, - CASE_guard66032_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q61, - CASE_guard66032_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q60, - CASE_guard66260_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q133, - CASE_guard66260_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q132, - CASE_guard74530_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172, - CASE_guard74530_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162, - CASE_guard74868_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q63, - CASE_guard74868_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q62, - CASE_guard83842_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168, - CASE_guard83842_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164, - CASE_guard92911_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170, - CASE_guard92911_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166, - CASE_guard94092_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q92, - CASE_guard94092_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q91, - CASE_guard96373_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147, - CASE_k71729_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q253, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q252, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q259, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q260, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q255, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q250, + CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q235, + CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q236, + CASE_fetchStage_pipelines_0_canDeq__2929_AND_N_ETC__q233, + CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q232, + CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q229, + CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q230, + CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q234, + CASE_guard02490_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q86, + CASE_guard02490_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q84, + CASE_guard05376_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139, + CASE_guard11420_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q88, + CASE_guard11420_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q87, + CASE_guard14445_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141, + CASE_guard20256_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q90, + CASE_guard20256_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q89, + CASE_guard34917_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195, + CASE_guard34917_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185, + CASE_guard39478_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q119, + CASE_guard39478_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q118, + CASE_guard44229_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191, + CASE_guard44229_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187, + CASE_guard48084_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49, + CASE_guard48084_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48, + CASE_guard48185_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q121, + CASE_guard48185_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q120, + CASE_guard53298_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193, + CASE_guard53298_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189, + CASE_guard56793_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q51, + CASE_guard56793_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q50, + CASE_guard57115_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q123, + CASE_guard57115_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q122, + CASE_guard65723_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53, + CASE_guard65723_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52, + CASE_guard65951_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q125, + CASE_guard65951_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q124, + CASE_guard74221_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162, + CASE_guard74221_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154, + CASE_guard74559_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q55, + CASE_guard74559_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q54, + CASE_guard83533_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160, + CASE_guard83533_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156, + CASE_guard92602_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164, + CASE_guard92602_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158, + CASE_guard93783_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q85, + CASE_guard93783_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q83, + CASE_guard96064_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137, + CASE_k71393_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q231, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6542, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6555, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6559, @@ -4840,31 +4762,31 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d11133, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d8507, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d8520, - IF_fetchStage_pipelines_0_first__2934_BITS_191_ETC___d13635, - IF_fetchStage_pipelines_0_first__2934_BITS_191_ETC___d13693, - IF_fetchStage_pipelines_0_first__2934_BITS_191_ETC___d14304, - IF_fetchStage_pipelines_0_first__2934_BITS_191_ETC___d14307, - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d13639, - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d13663, - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d13698, - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d14015, - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d14037, - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d14055, - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d14110, - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d14112, - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d14126, - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d14133, - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d14209, - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d14221, - IF_fetchStage_pipelines_1_first__2943_BITS_191_ETC___d14472, - IF_fetchStage_pipelines_1_first__2943_BITS_191_ETC___d14473, - IF_fetchStage_pipelines_1_first__2943_BITS_194_ETC___d14067, - IF_fetchStage_pipelines_1_first__2943_BITS_194_ETC___d14206, - IF_fetchStage_pipelines_1_first__2943_BITS_194_ETC___d14233, - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__361_ETC___d13656, - SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__293_ETC___d14167, - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3613_co_ETC___d13623, - SEL_ARR_fetchStage_pipelines_0_canDeq__2932_AN_ETC___d13937; + IF_fetchStage_pipelines_0_first__2931_BITS_191_ETC___d13631, + IF_fetchStage_pipelines_0_first__2931_BITS_191_ETC___d13689, + IF_fetchStage_pipelines_0_first__2931_BITS_191_ETC___d14300, + IF_fetchStage_pipelines_0_first__2931_BITS_191_ETC___d14303, + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d13635, + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d13659, + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d13694, + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d14011, + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d14033, + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d14051, + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d14106, + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d14108, + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d14122, + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d14129, + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d14205, + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d14217, + IF_fetchStage_pipelines_1_first__2940_BITS_191_ETC___d14468, + IF_fetchStage_pipelines_1_first__2940_BITS_191_ETC___d14469, + IF_fetchStage_pipelines_1_first__2940_BITS_194_ETC___d14063, + IF_fetchStage_pipelines_1_first__2940_BITS_194_ETC___d14202, + IF_fetchStage_pipelines_1_first__2940_BITS_194_ETC___d14229, + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__360_ETC___d13652, + SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__292_ETC___d14163, + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3609_co_ETC___d13619, + SEL_ARR_fetchStage_pipelines_0_canDeq__2929_AN_ETC___d13933; wire [581 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3343; wire [569 : 0] IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2538, IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2549, @@ -4873,33 +4795,33 @@ module mkCore(CLK, wire [517 : 0] SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3038; wire [511 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2236, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3031, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15906; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15752; wire [447 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2033; wire [383 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2231, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3022, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15897; - wire [321 : 0] basicExec___d12107, basicExec___d12781; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15743; + wire [321 : 0] basicExec___d12104, basicExec___d12778; wire [319 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2028; wire [255 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2226, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3013, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15888, + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15734, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d11187, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d11200, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d11193; wire [191 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2023; - wire [127 : 0] b__h605940, b__h606016, b__h606117, b__h606129, x__h606941; + wire [127 : 0] b__h605631, b__h605707, b__h605808, b__h605820, x__h606632; wire [68 : 0] execFpuSimple___d11167; wire [65 : 0] IF_IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_NOT_ETC___d627; wire [64 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2598; wire [63 : 0] IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9284, - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__237_ETC___d12622, - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__237_ETC___d12623, - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__237_ETC___d12631, - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__237_ETC___d12632, - IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11948, - IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11949, - IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11957, - IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11958, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12619, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12620, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12628, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12629, + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11945, + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11946, + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11954, + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11955, IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8453, IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8454, IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8461, @@ -4921,373 +4843,372 @@ module mkCore(CLK, IF_coreFix_memExe_lsq_firstLd__285_BIT_96_350__ETC___d1386, IF_coreFix_memExe_lsq_firstLd__285_BIT_96_350__ETC___d1435, IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8, - _theResult___fst__h606340, - _theResult___snd__h606341, - a___1__h605954, - a___1__h606345, - a__h605792, + IF_rob_deqPort_0_canDeq__5156_THEN_IF_NOT_rob__ETC___d15265, + _theResult___fst__h606031, + _theResult___snd__h606032, + a___1__h605645, + a___1__h606036, + a__h605483, amoExec___d882, - b___1__h605955, - b___1__h606406, - b__h605793, - base__h709686, - base__h709889, + b___1__h605646, + b___1__h606097, + b__h605484, + base__h708366, + base__h708569, coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d11256, coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d11257, - data___1__h477383, - data___1__h478277, - data__h476871, - data__h477765, - fallthrough_pc__h668018, - fallthrough_pc__h683403, - fcsr_csr__read__h613533, - fflags_csr__read__h613508, - frm_csr__read__h613519, - mcause_csr__read__h615180, - mcounteren_csr__read__h614925, - medeleg_csr__read__h614525, - mideleg_csr__read__h614620, - mie_csr__read__h614751, - mip_csr__read__h615420, - mstatus_csr__read__h614377, - mtvec_csr__read__h614833, - n___1__h199875, - n__h195271, - n__read__h615524, - n__read__h615715, - n__read__h6636, - n__read__h719255, - next_pc__h718537, - q___1__h478352, - rVal1__h484562, - rVal2__h484563, - r___1__h478379, - res_data__h340167, - res_data__h340172, - res_data__h385869, - res_data__h385874, - res_data__h431564, - res_data__h431569, - resp_addr__h294277, - rob_deqPort_0_deq_data__4547_BITS_282_TO_219_4_ETC___d15180, - robdeqPort_0_deq_data_BITS_95_TO_32__q271, - satp_csr__read__h614234, - scause_csr__read__h614032, - scounteren_csr__read__h613894, - shiftData__h184066, - sie_csr__read__h613798, - sip_csr__read__h614171, - sstatus_csr__read__h613729, - stvec_csr__read__h613841, - upd__h4024, - upd__h5341, - upd__h6750, - upd__h719366, - v__h612041, - v__h636859, - vaddr__h184061, - x__h155041, - x__h158588, - x__h161402, - x__h163250, - x__h18203, - x__h183973, - x__h183974, - x__h20741, - x__h289524, - x__h291378, - x__h46110, - x__h484468, - x__h484469, - x__h484470, - x__h48646, - x__h606329, - x__h620994, - x__h620995, - x__h643354, - x__h643355, - x__h701106, - x__h722429, - x_addr__h316374, - x_quotient__h477567, - x_reg_ifc__read__h613638, - x_remainder__h477568, - y__h623720, - y__h645787, - y__h722455, - y__h723907, - y_avValue__h183139, - y_avValue__h183820, - y_avValue__h481607, - y_avValue__h482290, - y_avValue__h482967, - y_avValue__h613174, - y_avValue__h619004, - y_avValue__h637840, - y_avValue__h641374, - y_avValue__h707954, - y_avValue__h709723, - y_avValue_snd_snd_snd_snd_snd__h722470, - y_avValue_snd_snd_snd_snd_snd__h723956, - y_avValue_snd_snd_snd_snd_snd__h723985; + data___1__h477074, + data___1__h477968, + data__h476562, + data__h477456, + fallthrough_pc__h667681, + fallthrough_pc__h683049, + fcsr_csr__read__h613224, + fflags_csr__read__h613199, + frm_csr__read__h613210, + mcause_csr__read__h614864, + mcounteren_csr__read__h614609, + medeleg_csr__read__h614216, + mideleg_csr__read__h614311, + mie_csr__read__h614435, + mip_csr__read__h615097, + mstatus_csr__read__h614068, + mtvec_csr__read__h614517, + n___1__h199567, + n__h194963, + n__read__h615201, + n__read__h615392, + n__read__h6329, + n__read__h717124, + next_pc__h716406, + q___1__h478043, + rVal1__h484253, + rVal2__h484254, + r___1__h478070, + res_data__h339858, + res_data__h339863, + res_data__h385560, + res_data__h385565, + res_data__h431255, + res_data__h431260, + resp_addr__h293969, + rob_deqPort_0_deq_data__4542_BITS_282_TO_219_4_ETC___d15122, + robdeqPort_0_deq_data_BITS_95_TO_32__q263, + satp_csr__read__h613925, + scause_csr__read__h613723, + scounteren_csr__read__h613585, + shiftData__h183758, + sie_csr__read__h613489, + sip_csr__read__h613862, + sstatus_csr__read__h613420, + stvec_csr__read__h613532, + upd__h3717, + upd__h5034, + upd__h6443, + upd__h717235, + v__h611732, + v__h636524, + vaddr__h183753, + x__h154732, + x__h158279, + x__h161093, + x__h162941, + x__h17895, + x__h183665, + x__h183666, + x__h20433, + x__h289216, + x__h291070, + x__h45802, + x__h48338, + x__h484159, + x__h484160, + x__h484161, + x__h606020, + x__h620659, + x__h620660, + x__h643018, + x__h643019, + x__h700768, + x_addr__h316066, + x_quotient__h477258, + x_reg_ifc__read__h613329, + x_remainder__h477259, + y__h623385, + y__h645451, + y__h720039, + y_avValue__h182831, + y_avValue__h183512, + y_avValue__h481298, + y_avValue__h481981, + y_avValue__h482658, + y_avValue__h612865, + y_avValue__h618669, + y_avValue__h637505, + y_avValue__h641038, + y_avValue__h706634, + y_avValue__h708403, + y_avValue_snd_snd_snd_snd_snd__h719478, + y_avValue_snd_snd_snd_snd_snd__h720092, + y_avValue_snd_snd_snd_snd_snd__h720121; wire [62 : 0] IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10763, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9993, - r1__read__h616692, - r1__read__h617096, - r1__read__h617626, - r1__read__h617631, - r1__read__h617650, - r1__read__h617903, - r1__read__h618069, - r1__read__h618187, - r1__read__h618192, - r1__read__h618211; - wire [61 : 0] r1__read__h616694, - r1__read__h617098, - r1__read__h617633, - r1__read__h617652, - r1__read__h617905, - r1__read__h618045, - r1__read__h618071, - r1__read__h618194, - r1__read__h618213; - wire [60 : 0] r1__read__h617907, - r1__read__h618047, - r1__read__h618073, - r1__read__h618215; - wire [59 : 0] r1__read__h616696, - r1__read__h617100, - r1__read__h617644, - r1__read__h617654, - r1__read__h617909, - r1__read__h618075, - r1__read__h618205, - r1__read__h618217; - wire [58 : 0] r1__read__h616698, - r1__read__h617102, - r1__read__h617656, - r1__read__h617911, - r1__read__h618077, - r1__read__h618219; + r1__read__h616369, + r1__read__h616773, + r1__read__h617303, + r1__read__h617308, + r1__read__h617327, + r1__read__h617580, + r1__read__h617746, + r1__read__h617857, + r1__read__h617862, + r1__read__h617881; + wire [61 : 0] r1__read__h616371, + r1__read__h616775, + r1__read__h617310, + r1__read__h617329, + r1__read__h617582, + r1__read__h617722, + r1__read__h617748, + r1__read__h617864, + r1__read__h617883; + wire [60 : 0] r1__read__h617584, + r1__read__h617724, + r1__read__h617750, + r1__read__h617885; + wire [59 : 0] r1__read__h616373, + r1__read__h616777, + r1__read__h617321, + r1__read__h617331, + r1__read__h617586, + r1__read__h617752, + r1__read__h617875, + r1__read__h617887; + wire [58 : 0] r1__read__h616375, + r1__read__h616779, + r1__read__h617333, + r1__read__h617588, + r1__read__h617754, + r1__read__h617889; wire [57 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2578, IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3108, IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2787, - r1__read__h616700, - r1__read__h617104, - r1__read__h617658, - r1__read__h617913, - r1__read__h618049, - r1__read__h618079, - r1__read__h618221, - y__h256430; - wire [56 : 0] IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q29, - IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q64, - IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q99, - IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q138, - IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q155, - IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q178, - IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q109, - IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q39, - IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q74, - IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q134, - IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q141, - IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q151, - IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q158, - IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q174, - IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q181, - IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q101, - IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q114, - IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q31, - IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q44, - IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q66, - IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q79, + r1__read__h616377, + r1__read__h616781, + r1__read__h617335, + r1__read__h617590, + r1__read__h617726, + r1__read__h617756, + r1__read__h617891, + y__h256122; + wire [56 : 0] IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q21, + IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q56, + IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q91, + IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q130, + IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q147, + IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q170, + IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q101, + IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q31, + IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q66, + IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q126, + IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q133, + IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q143, + IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q150, + IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q166, + IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q173, + IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q106, + IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q23, + IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q36, + IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q58, + IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q71, + IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q93, _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d10249, _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d8764, _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d9479, _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4654, _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d6046, _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7438, - _theResult____h348383, - _theResult____h366022, - _theResult____h394082, - _theResult____h411719, - _theResult____h439777, - _theResult____h457414, - _theResult____h505675, - _theResult____h544528, - _theResult____h583832, - _theResult___snd__h356505, - _theResult___snd__h356516, - _theResult___snd__h356518, - _theResult___snd__h356528, - _theResult___snd__h356534, - _theResult___snd__h356557, - _theResult___snd__h365101, - _theResult___snd__h365103, - _theResult___snd__h365110, - _theResult___snd__h365116, - _theResult___snd__h365139, - _theResult___snd__h374271, - _theResult___snd__h374282, - _theResult___snd__h374284, - _theResult___snd__h374294, - _theResult___snd__h374300, - _theResult___snd__h374323, - _theResult___snd__h382891, - _theResult___snd__h382905, - _theResult___snd__h382911, - _theResult___snd__h382929, - _theResult___snd__h402202, - _theResult___snd__h402213, - _theResult___snd__h402215, - _theResult___snd__h402225, - _theResult___snd__h402231, - _theResult___snd__h402254, - _theResult___snd__h410798, - _theResult___snd__h410800, - _theResult___snd__h410807, - _theResult___snd__h410813, - _theResult___snd__h410836, - _theResult___snd__h419968, - _theResult___snd__h419979, - _theResult___snd__h419981, - _theResult___snd__h419991, - _theResult___snd__h419997, - _theResult___snd__h420020, - _theResult___snd__h428588, - _theResult___snd__h428602, - _theResult___snd__h428608, - _theResult___snd__h428626, - _theResult___snd__h447897, - _theResult___snd__h447908, - _theResult___snd__h447910, - _theResult___snd__h447920, - _theResult___snd__h447926, - _theResult___snd__h447949, - _theResult___snd__h456493, - _theResult___snd__h456495, - _theResult___snd__h456502, - _theResult___snd__h456508, - _theResult___snd__h456531, - _theResult___snd__h465663, - _theResult___snd__h465674, - _theResult___snd__h465676, - _theResult___snd__h465686, - _theResult___snd__h465692, - _theResult___snd__h465715, - _theResult___snd__h474283, - _theResult___snd__h474297, - _theResult___snd__h474303, - _theResult___snd__h474321, - _theResult___snd__h504285, - _theResult___snd__h504287, - _theResult___snd__h504294, - _theResult___snd__h504300, - _theResult___snd__h504323, - _theResult___snd__h513922, - _theResult___snd__h513933, - _theResult___snd__h513935, - _theResult___snd__h513945, - _theResult___snd__h513951, - _theResult___snd__h513974, - _theResult___snd__h522690, - _theResult___snd__h522704, - _theResult___snd__h522710, - _theResult___snd__h522728, - _theResult___snd__h543138, - _theResult___snd__h543140, - _theResult___snd__h543147, - _theResult___snd__h543153, - _theResult___snd__h543176, - _theResult___snd__h552775, - _theResult___snd__h552786, - _theResult___snd__h552788, - _theResult___snd__h552798, - _theResult___snd__h552804, - _theResult___snd__h552827, - _theResult___snd__h561543, - _theResult___snd__h561557, - _theResult___snd__h561563, - _theResult___snd__h561581, - _theResult___snd__h582442, - _theResult___snd__h582444, - _theResult___snd__h582451, - _theResult___snd__h582457, - _theResult___snd__h582480, - _theResult___snd__h592079, - _theResult___snd__h592090, - _theResult___snd__h592092, - _theResult___snd__h592102, - _theResult___snd__h592108, - _theResult___snd__h592131, - _theResult___snd__h600847, - _theResult___snd__h600861, - _theResult___snd__h600867, - _theResult___snd__h600885, - r1__read__h617915, - r1__read__h618051, - r1__read__h618081, - r1__read__h618223, - result__h366635, - result__h412332, - result__h458027, - result__h506288, - result__h545141, - result__h584445, - sfd__h340778, - sfd__h386480, - sfd__h432175, - sfd__h485308, - sfd__h524302, - sfd__h563606, - sfdin__h356488, - sfdin__h374254, - sfdin__h402185, - sfdin__h419951, - sfdin__h447880, - sfdin__h465646, - sfdin__h513905, - sfdin__h552758, - sfdin__h592062, - x__h366732, - x__h412429, - x__h458124, - x__h506383, - x__h545236, - x__h584540; - wire [55 : 0] r1__read__h616702, - r1__read__h617106, - r1__read__h617660, - r1__read__h617917, - r1__read__h618083, - r1__read__h618225; - wire [54 : 0] r1__read__h616704, - r1__read__h617108, - r1__read__h617662, - r1__read__h617919, - r1__read__h618085, - r1__read__h618227; - wire [53 : 0] r1__read__h618028, - r1__read__h618053, - r1__read__h618087, - r1__read__h618229, - sfd__h504352, - sfd__h514003, - sfd__h522763, - sfd__h543205, - sfd__h552856, - sfd__h561616, - sfd__h582509, - sfd__h592160, - sfd__h600920, - value__h349005, - value__h394702, - value__h440397; - wire [52 : 0] r1__read__h617921, - r1__read__h618030, - r1__read__h618055, - r1__read__h618089, - r1__read__h618231; + _theResult____h348074, + _theResult____h365713, + _theResult____h393773, + _theResult____h411410, + _theResult____h439468, + _theResult____h457105, + _theResult____h505366, + _theResult____h544219, + _theResult____h583523, + _theResult___snd__h356196, + _theResult___snd__h356207, + _theResult___snd__h356209, + _theResult___snd__h356219, + _theResult___snd__h356225, + _theResult___snd__h356248, + _theResult___snd__h364792, + _theResult___snd__h364794, + _theResult___snd__h364801, + _theResult___snd__h364807, + _theResult___snd__h364830, + _theResult___snd__h373962, + _theResult___snd__h373973, + _theResult___snd__h373975, + _theResult___snd__h373985, + _theResult___snd__h373991, + _theResult___snd__h374014, + _theResult___snd__h382582, + _theResult___snd__h382596, + _theResult___snd__h382602, + _theResult___snd__h382620, + _theResult___snd__h401893, + _theResult___snd__h401904, + _theResult___snd__h401906, + _theResult___snd__h401916, + _theResult___snd__h401922, + _theResult___snd__h401945, + _theResult___snd__h410489, + _theResult___snd__h410491, + _theResult___snd__h410498, + _theResult___snd__h410504, + _theResult___snd__h410527, + _theResult___snd__h419659, + _theResult___snd__h419670, + _theResult___snd__h419672, + _theResult___snd__h419682, + _theResult___snd__h419688, + _theResult___snd__h419711, + _theResult___snd__h428279, + _theResult___snd__h428293, + _theResult___snd__h428299, + _theResult___snd__h428317, + _theResult___snd__h447588, + _theResult___snd__h447599, + _theResult___snd__h447601, + _theResult___snd__h447611, + _theResult___snd__h447617, + _theResult___snd__h447640, + _theResult___snd__h456184, + _theResult___snd__h456186, + _theResult___snd__h456193, + _theResult___snd__h456199, + _theResult___snd__h456222, + _theResult___snd__h465354, + _theResult___snd__h465365, + _theResult___snd__h465367, + _theResult___snd__h465377, + _theResult___snd__h465383, + _theResult___snd__h465406, + _theResult___snd__h473974, + _theResult___snd__h473988, + _theResult___snd__h473994, + _theResult___snd__h474012, + _theResult___snd__h503976, + _theResult___snd__h503978, + _theResult___snd__h503985, + _theResult___snd__h503991, + _theResult___snd__h504014, + _theResult___snd__h513613, + _theResult___snd__h513624, + _theResult___snd__h513626, + _theResult___snd__h513636, + _theResult___snd__h513642, + _theResult___snd__h513665, + _theResult___snd__h522381, + _theResult___snd__h522395, + _theResult___snd__h522401, + _theResult___snd__h522419, + _theResult___snd__h542829, + _theResult___snd__h542831, + _theResult___snd__h542838, + _theResult___snd__h542844, + _theResult___snd__h542867, + _theResult___snd__h552466, + _theResult___snd__h552477, + _theResult___snd__h552479, + _theResult___snd__h552489, + _theResult___snd__h552495, + _theResult___snd__h552518, + _theResult___snd__h561234, + _theResult___snd__h561248, + _theResult___snd__h561254, + _theResult___snd__h561272, + _theResult___snd__h582133, + _theResult___snd__h582135, + _theResult___snd__h582142, + _theResult___snd__h582148, + _theResult___snd__h582171, + _theResult___snd__h591770, + _theResult___snd__h591781, + _theResult___snd__h591783, + _theResult___snd__h591793, + _theResult___snd__h591799, + _theResult___snd__h591822, + _theResult___snd__h600538, + _theResult___snd__h600552, + _theResult___snd__h600558, + _theResult___snd__h600576, + r1__read__h617592, + r1__read__h617728, + r1__read__h617758, + r1__read__h617893, + result__h366326, + result__h412023, + result__h457718, + result__h505979, + result__h544832, + result__h584136, + sfd__h340469, + sfd__h386171, + sfd__h431866, + sfd__h484999, + sfd__h523993, + sfd__h563297, + sfdin__h356179, + sfdin__h373945, + sfdin__h401876, + sfdin__h419642, + sfdin__h447571, + sfdin__h465337, + sfdin__h513596, + sfdin__h552449, + sfdin__h591753, + x__h366423, + x__h412120, + x__h457815, + x__h506074, + x__h544927, + x__h584231; + wire [55 : 0] r1__read__h616379, + r1__read__h616783, + r1__read__h617337, + r1__read__h617594, + r1__read__h617760, + r1__read__h617895; + wire [54 : 0] r1__read__h616381, + r1__read__h616785, + r1__read__h617339, + r1__read__h617596, + r1__read__h617762, + r1__read__h617897; + wire [53 : 0] r1__read__h617705, + r1__read__h617730, + r1__read__h617764, + r1__read__h617899, + sfd__h504043, + sfd__h513694, + sfd__h522454, + sfd__h542896, + sfd__h552547, + sfd__h561307, + sfd__h582200, + sfd__h591851, + sfd__h600611, + value__h348696, + value__h394393, + value__h440088; + wire [52 : 0] r1__read__h617598, + r1__read__h617707, + r1__read__h617732, + r1__read__h617766, + r1__read__h617901; wire [51 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10730, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10732, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9251, @@ -5309,110 +5230,109 @@ module mkCore(CLK, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10762, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9283, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9992, - _theResult___fst_sfd__h489262, - _theResult___fst_sfd__h505090, - _theResult___fst_sfd__h505093, - _theResult___fst_sfd__h514741, - _theResult___fst_sfd__h514744, - _theResult___fst_sfd__h523525, - _theResult___fst_sfd__h523528, - _theResult___fst_sfd__h523537, - _theResult___fst_sfd__h523543, - _theResult___fst_sfd__h528115, - _theResult___fst_sfd__h543943, - _theResult___fst_sfd__h543946, - _theResult___fst_sfd__h553594, - _theResult___fst_sfd__h553597, - _theResult___fst_sfd__h562378, - _theResult___fst_sfd__h562381, - _theResult___fst_sfd__h562390, - _theResult___fst_sfd__h562396, - _theResult___fst_sfd__h567419, - _theResult___fst_sfd__h583247, - _theResult___fst_sfd__h583250, - _theResult___fst_sfd__h592898, - _theResult___fst_sfd__h592901, - _theResult___fst_sfd__h601682, - _theResult___fst_sfd__h601685, - _theResult___fst_sfd__h601694, - _theResult___fst_sfd__h601700, - _theResult___sfd__h504990, - _theResult___sfd__h514641, - _theResult___sfd__h523425, - _theResult___sfd__h543843, - _theResult___sfd__h553494, - _theResult___sfd__h562278, - _theResult___sfd__h583147, - _theResult___sfd__h592798, - _theResult___sfd__h601582, - _theResult___snd_fst_sfd__h485262, - _theResult___snd_fst_sfd__h505096, - _theResult___snd_fst_sfd__h523531, - _theResult___snd_fst_sfd__h524256, - _theResult___snd_fst_sfd__h543949, - _theResult___snd_fst_sfd__h562384, - _theResult___snd_fst_sfd__h563560, - _theResult___snd_fst_sfd__h583253, - _theResult___snd_fst_sfd__h601688, - out___1_sfd__h485010, - out___1_sfd__h524004, - out___1_sfd__h563308, - out_sfd__h504993, - out_sfd__h514644, - out_sfd__h523428, - out_sfd__h543846, - out_sfd__h553497, - out_sfd__h562281, - out_sfd__h583150, - out_sfd__h592801, - out_sfd__h601585, - r1__read__h618233; - wire [50 : 0] r1__read__h616706, r1__read__h617923; - wire [49 : 0] r1__read__h618032, r1__read__h618235; - wire [48 : 0] r1__read__h616708, r1__read__h617925, r1__read__h618034; - wire [46 : 0] r1__read__h616710, r1__read__h617927; - wire [45 : 0] r1__read__h616712, r1__read__h617929; - wire [44 : 0] r1__read__h616714, r1__read__h617931; - wire [43 : 0] r1__read__h616716, r1__read__h617933; - wire [42 : 0] r1__read__h617935; - wire [41 : 0] r1__read__h617937; - wire [40 : 0] r1__read__h617939; - wire [37 : 0] IF_fetchStage_pipelines_0_first__2934_BIT_160__ETC___d14316, - IF_fetchStage_pipelines_1_first__2943_BIT_160__ETC___d14478; - wire [31 : 0] coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q12, - coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q11, - coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q13, - data76871_BITS_31_TO_0__q10, - data77765_BITS_31_TO_0__q14, - imm__h659224, - r1__read__h616718, - r1__read__h617941, - x__h194496, - x__h340182, - x__h385884, - x__h431579, - x__h76055, - x_data__h65904, - x_data_imm__h678959, - x_data_imm__h694502; - wire [29 : 0] r1__read__h616720, r1__read__h617943; - wire [27 : 0] r1__read__h617945; - wire [24 : 0] NOT_fetchStage_pipelines_0_first__2934_BITS_19_ETC___d14362, - sfd__h356586, - sfd__h365168, - sfd__h374352, - sfd__h382964, - sfd__h402283, - sfd__h410865, - sfd__h420049, - sfd__h428661, - sfd__h447978, - sfd__h456560, - sfd__h465744, - sfd__h474356, - value__h489891, - value__h528744, - value__h568048; + _theResult___fst_sfd__h488953, + _theResult___fst_sfd__h504781, + _theResult___fst_sfd__h504784, + _theResult___fst_sfd__h514432, + _theResult___fst_sfd__h514435, + _theResult___fst_sfd__h523216, + _theResult___fst_sfd__h523219, + _theResult___fst_sfd__h523228, + _theResult___fst_sfd__h523234, + _theResult___fst_sfd__h527806, + _theResult___fst_sfd__h543634, + _theResult___fst_sfd__h543637, + _theResult___fst_sfd__h553285, + _theResult___fst_sfd__h553288, + _theResult___fst_sfd__h562069, + _theResult___fst_sfd__h562072, + _theResult___fst_sfd__h562081, + _theResult___fst_sfd__h562087, + _theResult___fst_sfd__h567110, + _theResult___fst_sfd__h582938, + _theResult___fst_sfd__h582941, + _theResult___fst_sfd__h592589, + _theResult___fst_sfd__h592592, + _theResult___fst_sfd__h601373, + _theResult___fst_sfd__h601376, + _theResult___fst_sfd__h601385, + _theResult___fst_sfd__h601391, + _theResult___sfd__h504681, + _theResult___sfd__h514332, + _theResult___sfd__h523116, + _theResult___sfd__h543534, + _theResult___sfd__h553185, + _theResult___sfd__h561969, + _theResult___sfd__h582838, + _theResult___sfd__h592489, + _theResult___sfd__h601273, + _theResult___snd_fst_sfd__h484953, + _theResult___snd_fst_sfd__h504787, + _theResult___snd_fst_sfd__h523222, + _theResult___snd_fst_sfd__h523947, + _theResult___snd_fst_sfd__h543640, + _theResult___snd_fst_sfd__h562075, + _theResult___snd_fst_sfd__h563251, + _theResult___snd_fst_sfd__h582944, + _theResult___snd_fst_sfd__h601379, + out___1_sfd__h484701, + out___1_sfd__h523695, + out___1_sfd__h562999, + out_sfd__h504684, + out_sfd__h514335, + out_sfd__h523119, + out_sfd__h543537, + out_sfd__h553188, + out_sfd__h561972, + out_sfd__h582841, + out_sfd__h592492, + out_sfd__h601276; + wire [50 : 0] r1__read__h616383, r1__read__h617600; + wire [49 : 0] r1__read__h617709; + wire [48 : 0] r1__read__h616385, r1__read__h617602, r1__read__h617711; + wire [46 : 0] r1__read__h616387, r1__read__h617604; + wire [45 : 0] r1__read__h616389, r1__read__h617606; + wire [44 : 0] r1__read__h616391, r1__read__h617608; + wire [43 : 0] r1__read__h616393, r1__read__h617610; + wire [42 : 0] r1__read__h617612; + wire [41 : 0] r1__read__h617614; + wire [40 : 0] r1__read__h617616; + wire [37 : 0] IF_fetchStage_pipelines_0_first__2931_BIT_160__ETC___d14312, + IF_fetchStage_pipelines_1_first__2940_BIT_160__ETC___d14474; + wire [31 : 0] coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q4, + coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q3, + coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q5, + data76562_BITS_31_TO_0__q2, + data77456_BITS_31_TO_0__q6, + imm__h658888, + r1__read__h616395, + r1__read__h617618, + x__h194188, + x__h339873, + x__h385575, + x__h431270, + x__h75747, + x_data__h65596, + x_data_imm__h678623, + x_data_imm__h694166; + wire [29 : 0] r1__read__h616397, r1__read__h617620; + wire [27 : 0] r1__read__h617622; + wire [24 : 0] NOT_fetchStage_pipelines_0_first__2931_BITS_19_ETC___d14358, + sfd__h356277, + sfd__h364859, + sfd__h374043, + sfd__h382655, + sfd__h401974, + sfd__h410556, + sfd__h419740, + sfd__h428352, + sfd__h447669, + sfd__h456251, + sfd__h465435, + sfd__h474047, + value__h489582, + value__h528435, + value__h567739; wire [22 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5053, IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5055, IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6445, @@ -5437,93 +5357,93 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7858, IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7902, IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7904, - _theResult___fst_sfd__h357092, - _theResult___fst_sfd__h365674, - _theResult___fst_sfd__h374858, - _theResult___fst_sfd__h383494, - _theResult___fst_sfd__h383503, - _theResult___fst_sfd__h383509, - _theResult___fst_sfd__h402789, - _theResult___fst_sfd__h411371, - _theResult___fst_sfd__h420555, - _theResult___fst_sfd__h429191, - _theResult___fst_sfd__h429200, - _theResult___fst_sfd__h429206, - _theResult___fst_sfd__h448484, - _theResult___fst_sfd__h457066, - _theResult___fst_sfd__h466250, - _theResult___fst_sfd__h474886, - _theResult___fst_sfd__h474895, - _theResult___fst_sfd__h474901, - _theResult___sfd__h357011, - _theResult___sfd__h365593, - _theResult___sfd__h374777, - _theResult___sfd__h383413, - _theResult___sfd__h383515, - _theResult___sfd__h402708, - _theResult___sfd__h411290, - _theResult___sfd__h420474, - _theResult___sfd__h429110, - _theResult___sfd__h429212, - _theResult___sfd__h448403, - _theResult___sfd__h456985, - _theResult___sfd__h466169, - _theResult___sfd__h474805, - _theResult___sfd__h474907, - _theResult___snd_fst_sfd__h340728, - _theResult___snd_fst_sfd__h365677, - _theResult___snd_fst_sfd__h383497, - _theResult___snd_fst_sfd__h386430, - _theResult___snd_fst_sfd__h411374, - _theResult___snd_fst_sfd__h429194, - _theResult___snd_fst_sfd__h432125, - _theResult___snd_fst_sfd__h457069, - _theResult___snd_fst_sfd__h474889, - f1_sfd__h484947, - f2_sfd__h523941, - f3_sfd__h563245, - out_f_sfd__h383792, - out_f_sfd__h429489, - out_f_sfd__h475184, - out_sfd__h357014, - out_sfd__h365596, - out_sfd__h374780, - out_sfd__h383416, - out_sfd__h402711, - out_sfd__h411293, - out_sfd__h420477, - out_sfd__h429113, - out_sfd__h448406, - out_sfd__h456988, - out_sfd__h466172, - out_sfd__h474808; - wire [19 : 0] r1__read__h617880; - wire [15 : 0] IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005, - _theResult____h655044, - enabled_ints___1__h655569, - enabled_ints__h655616, - pend_ints__h655042, - y__h655581; - wire [13 : 0] r1__read_BITS_13_TO_0___h655592; - wire [12 : 0] fetchStage_pipelines_1_first__2943_BIT_173_375_ETC___d13842; + _theResult___fst_sfd__h356783, + _theResult___fst_sfd__h365365, + _theResult___fst_sfd__h374549, + _theResult___fst_sfd__h383185, + _theResult___fst_sfd__h383194, + _theResult___fst_sfd__h383200, + _theResult___fst_sfd__h402480, + _theResult___fst_sfd__h411062, + _theResult___fst_sfd__h420246, + _theResult___fst_sfd__h428882, + _theResult___fst_sfd__h428891, + _theResult___fst_sfd__h428897, + _theResult___fst_sfd__h448175, + _theResult___fst_sfd__h456757, + _theResult___fst_sfd__h465941, + _theResult___fst_sfd__h474577, + _theResult___fst_sfd__h474586, + _theResult___fst_sfd__h474592, + _theResult___sfd__h356702, + _theResult___sfd__h365284, + _theResult___sfd__h374468, + _theResult___sfd__h383104, + _theResult___sfd__h383206, + _theResult___sfd__h402399, + _theResult___sfd__h410981, + _theResult___sfd__h420165, + _theResult___sfd__h428801, + _theResult___sfd__h428903, + _theResult___sfd__h448094, + _theResult___sfd__h456676, + _theResult___sfd__h465860, + _theResult___sfd__h474496, + _theResult___sfd__h474598, + _theResult___snd_fst_sfd__h340419, + _theResult___snd_fst_sfd__h365368, + _theResult___snd_fst_sfd__h383188, + _theResult___snd_fst_sfd__h386121, + _theResult___snd_fst_sfd__h411065, + _theResult___snd_fst_sfd__h428885, + _theResult___snd_fst_sfd__h431816, + _theResult___snd_fst_sfd__h456760, + _theResult___snd_fst_sfd__h474580, + f1_sfd__h484638, + f2_sfd__h523632, + f3_sfd__h562936, + out_f_sfd__h383483, + out_f_sfd__h429180, + out_f_sfd__h474875, + out_sfd__h356705, + out_sfd__h365287, + out_sfd__h374471, + out_sfd__h383107, + out_sfd__h402402, + out_sfd__h410984, + out_sfd__h420168, + out_sfd__h428804, + out_sfd__h448097, + out_sfd__h456679, + out_sfd__h465863, + out_sfd__h474499; + wire [19 : 0] r1__read__h617557; + wire [15 : 0] IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001, + _theResult____h654708, + enabled_ints___1__h655233, + enabled_ints__h655280, + pend_ints__h654706, + y__h655245; + wire [13 : 0] r1__read_BITS_13_TO_0___h655256; + wire [12 : 0] fetchStage_pipelines_1_first__2940_BIT_173_375_ETC___d13838; wire [11 : 0] IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10542, IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9057, IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9772, - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12875, - IF_fetchStage_pipelines_0_first__2934_BIT_173__ETC___d13207, + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12872, + IF_fetchStage_pipelines_0_first__2931_BIT_173__ETC___d13203, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10242, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8757, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9472, - SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137, - SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q154, - SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q177, + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q129, + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q146, + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q169, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6039, - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q73, + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q65, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4647, - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q38, + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q30, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7431, - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q108, - _0_CONCAT_csrf_debug_int_pend_read__1882_CONCAT_ETC___d12978, + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q100, + _0_CONCAT_csrf_external_int_en_vec_3_read__1850_ETC___d12974, _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4107, _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5499, _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6891, @@ -5536,24 +5456,24 @@ module mkCore(CLK, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4650, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d6042, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7434, - renaming_spec_bits__h686832, - result__h650621, - result__h650672, - spec_bits__h689959, - w__h650616, - x__h366765, - x__h412462, - x__h458157, - x__h506416, - x__h545269, - x__h584573, - x__h650620, - x__h650671, - y__h650650, - y__h689972, - y_avValue_fst__h683232, - y_avValue_fst__h683261, - y_avValue_fst__h683295; + renaming_spec_bits__h686496, + result__h650285, + result__h650336, + spec_bits__h689623, + w__h650280, + x__h366456, + x__h412153, + x__h457848, + x__h506107, + x__h544960, + x__h584264, + x__h650284, + x__h650335, + y__h650314, + y__h689636, + y_avValue_fst__h682896, + y_avValue_snd_fst__h683178, + y_avValue_snd_fst__h683220; wire [10 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10647, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10649, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9167, @@ -5572,105 +5492,105 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9841, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9908, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9910, - SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q140, - SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q157, - SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q180, - _theResult___exp__h504989, - _theResult___exp__h514640, - _theResult___exp__h523424, - _theResult___exp__h543842, - _theResult___exp__h553493, - _theResult___exp__h562277, - _theResult___exp__h583146, - _theResult___exp__h592797, - _theResult___exp__h601581, - _theResult___fst_exp__h489261, - _theResult___fst_exp__h504325, - _theResult___fst_exp__h504331, - _theResult___fst_exp__h504334, - _theResult___fst_exp__h505089, - _theResult___fst_exp__h505092, - _theResult___fst_exp__h513911, - _theResult___fst_exp__h513976, - _theResult___fst_exp__h513982, - _theResult___fst_exp__h513985, - _theResult___fst_exp__h514740, - _theResult___fst_exp__h514743, - _theResult___fst_exp__h522696, - _theResult___fst_exp__h522735, - _theResult___fst_exp__h522741, - _theResult___fst_exp__h522744, - _theResult___fst_exp__h523524, - _theResult___fst_exp__h523527, - _theResult___fst_exp__h523536, - _theResult___fst_exp__h523539, - _theResult___fst_exp__h528114, - _theResult___fst_exp__h543178, - _theResult___fst_exp__h543184, - _theResult___fst_exp__h543187, - _theResult___fst_exp__h543942, - _theResult___fst_exp__h543945, - _theResult___fst_exp__h552764, - _theResult___fst_exp__h552829, - _theResult___fst_exp__h552835, - _theResult___fst_exp__h552838, - _theResult___fst_exp__h553593, - _theResult___fst_exp__h553596, - _theResult___fst_exp__h561549, - _theResult___fst_exp__h561588, - _theResult___fst_exp__h561594, - _theResult___fst_exp__h561597, - _theResult___fst_exp__h562377, - _theResult___fst_exp__h562380, - _theResult___fst_exp__h562389, - _theResult___fst_exp__h562392, - _theResult___fst_exp__h567418, - _theResult___fst_exp__h582482, - _theResult___fst_exp__h582488, - _theResult___fst_exp__h582491, - _theResult___fst_exp__h583246, - _theResult___fst_exp__h583249, - _theResult___fst_exp__h592068, - _theResult___fst_exp__h592133, - _theResult___fst_exp__h592139, - _theResult___fst_exp__h592142, - _theResult___fst_exp__h592897, - _theResult___fst_exp__h592900, - _theResult___fst_exp__h600853, - _theResult___fst_exp__h600892, - _theResult___fst_exp__h600898, - _theResult___fst_exp__h600901, - _theResult___fst_exp__h601681, - _theResult___fst_exp__h601684, - _theResult___fst_exp__h601693, - _theResult___fst_exp__h601696, - _theResult___snd_fst_exp__h505095, - _theResult___snd_fst_exp__h523530, - _theResult___snd_fst_exp__h543948, - _theResult___snd_fst_exp__h562383, - _theResult___snd_fst_exp__h583252, - _theResult___snd_fst_exp__h601687, - coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q72, - coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q37, - coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q107, - din_inc___2_exp__h523584, - din_inc___2_exp__h523619, - din_inc___2_exp__h523645, - din_inc___2_exp__h562437, - din_inc___2_exp__h562472, - din_inc___2_exp__h562498, - din_inc___2_exp__h601741, - din_inc___2_exp__h601776, - din_inc___2_exp__h601802, - out_exp__h504992, - out_exp__h514643, - out_exp__h523427, - out_exp__h543845, - out_exp__h553496, - out_exp__h562280, - out_exp__h583149, - out_exp__h592800, - out_exp__h601584; + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q132, + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q149, + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q172, + _theResult___exp__h504680, + _theResult___exp__h514331, + _theResult___exp__h523115, + _theResult___exp__h543533, + _theResult___exp__h553184, + _theResult___exp__h561968, + _theResult___exp__h582837, + _theResult___exp__h592488, + _theResult___exp__h601272, + _theResult___fst_exp__h488952, + _theResult___fst_exp__h504016, + _theResult___fst_exp__h504022, + _theResult___fst_exp__h504025, + _theResult___fst_exp__h504780, + _theResult___fst_exp__h504783, + _theResult___fst_exp__h513602, + _theResult___fst_exp__h513667, + _theResult___fst_exp__h513673, + _theResult___fst_exp__h513676, + _theResult___fst_exp__h514431, + _theResult___fst_exp__h514434, + _theResult___fst_exp__h522387, + _theResult___fst_exp__h522426, + _theResult___fst_exp__h522432, + _theResult___fst_exp__h522435, + _theResult___fst_exp__h523215, + _theResult___fst_exp__h523218, + _theResult___fst_exp__h523227, + _theResult___fst_exp__h523230, + _theResult___fst_exp__h527805, + _theResult___fst_exp__h542869, + _theResult___fst_exp__h542875, + _theResult___fst_exp__h542878, + _theResult___fst_exp__h543633, + _theResult___fst_exp__h543636, + _theResult___fst_exp__h552455, + _theResult___fst_exp__h552520, + _theResult___fst_exp__h552526, + _theResult___fst_exp__h552529, + _theResult___fst_exp__h553284, + _theResult___fst_exp__h553287, + _theResult___fst_exp__h561240, + _theResult___fst_exp__h561279, + _theResult___fst_exp__h561285, + _theResult___fst_exp__h561288, + _theResult___fst_exp__h562068, + _theResult___fst_exp__h562071, + _theResult___fst_exp__h562080, + _theResult___fst_exp__h562083, + _theResult___fst_exp__h567109, + _theResult___fst_exp__h582173, + _theResult___fst_exp__h582179, + _theResult___fst_exp__h582182, + _theResult___fst_exp__h582937, + _theResult___fst_exp__h582940, + _theResult___fst_exp__h591759, + _theResult___fst_exp__h591824, + _theResult___fst_exp__h591830, + _theResult___fst_exp__h591833, + _theResult___fst_exp__h592588, + _theResult___fst_exp__h592591, + _theResult___fst_exp__h600544, + _theResult___fst_exp__h600583, + _theResult___fst_exp__h600589, + _theResult___fst_exp__h600592, + _theResult___fst_exp__h601372, + _theResult___fst_exp__h601375, + _theResult___fst_exp__h601384, + _theResult___fst_exp__h601387, + _theResult___snd_fst_exp__h504786, + _theResult___snd_fst_exp__h523221, + _theResult___snd_fst_exp__h543639, + _theResult___snd_fst_exp__h562074, + _theResult___snd_fst_exp__h582943, + _theResult___snd_fst_exp__h601378, + coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q64, + coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q29, + coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q99, + din_inc___2_exp__h523275, + din_inc___2_exp__h523310, + din_inc___2_exp__h523336, + din_inc___2_exp__h562128, + din_inc___2_exp__h562163, + din_inc___2_exp__h562189, + din_inc___2_exp__h601432, + din_inc___2_exp__h601467, + din_inc___2_exp__h601493, + out_exp__h504683, + out_exp__h514334, + out_exp__h523118, + out_exp__h543536, + out_exp__h553187, + out_exp__h561971, + out_exp__h582840, + out_exp__h592491, + out_exp__h601275; wire [8 : 0] IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4968, IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6360, IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7752; @@ -5698,128 +5618,128 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7414, IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7806, IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7808, - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q78, - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q43, - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q113, - _0_CONCAT_csrf_debug_int_pend_read__1882_CONCAT_ETC___d12973, - _theResult___exp__h357010, - _theResult___exp__h365592, - _theResult___exp__h374776, - _theResult___exp__h383412, - _theResult___exp__h383514, - _theResult___exp__h402707, - _theResult___exp__h411289, - _theResult___exp__h420473, - _theResult___exp__h429109, - _theResult___exp__h429211, - _theResult___exp__h448402, - _theResult___exp__h456984, - _theResult___exp__h466168, - _theResult___exp__h474804, - _theResult___exp__h474906, - _theResult___fst_exp__h356494, - _theResult___fst_exp__h356559, - _theResult___fst_exp__h356565, - _theResult___fst_exp__h356568, - _theResult___fst_exp__h357091, - _theResult___fst_exp__h365141, - _theResult___fst_exp__h365147, - _theResult___fst_exp__h365150, - _theResult___fst_exp__h365673, - _theResult___fst_exp__h374260, - _theResult___fst_exp__h374325, - _theResult___fst_exp__h374331, - _theResult___fst_exp__h374334, - _theResult___fst_exp__h374857, - _theResult___fst_exp__h382897, - _theResult___fst_exp__h382936, - _theResult___fst_exp__h382942, - _theResult___fst_exp__h382945, - _theResult___fst_exp__h383493, - _theResult___fst_exp__h383502, - _theResult___fst_exp__h383505, - _theResult___fst_exp__h402191, - _theResult___fst_exp__h402256, - _theResult___fst_exp__h402262, - _theResult___fst_exp__h402265, - _theResult___fst_exp__h402788, - _theResult___fst_exp__h410838, - _theResult___fst_exp__h410844, - _theResult___fst_exp__h410847, - _theResult___fst_exp__h411370, - _theResult___fst_exp__h419957, - _theResult___fst_exp__h420022, - _theResult___fst_exp__h420028, - _theResult___fst_exp__h420031, - _theResult___fst_exp__h420554, - _theResult___fst_exp__h428594, - _theResult___fst_exp__h428633, - _theResult___fst_exp__h428639, - _theResult___fst_exp__h428642, - _theResult___fst_exp__h429190, - _theResult___fst_exp__h429199, - _theResult___fst_exp__h429202, - _theResult___fst_exp__h447886, - _theResult___fst_exp__h447951, - _theResult___fst_exp__h447957, - _theResult___fst_exp__h447960, - _theResult___fst_exp__h448483, - _theResult___fst_exp__h456533, - _theResult___fst_exp__h456539, - _theResult___fst_exp__h456542, - _theResult___fst_exp__h457065, - _theResult___fst_exp__h465652, - _theResult___fst_exp__h465717, - _theResult___fst_exp__h465723, - _theResult___fst_exp__h465726, - _theResult___fst_exp__h466249, - _theResult___fst_exp__h474289, - _theResult___fst_exp__h474328, - _theResult___fst_exp__h474334, - _theResult___fst_exp__h474337, - _theResult___fst_exp__h474885, - _theResult___fst_exp__h474894, - _theResult___fst_exp__h474897, - _theResult___snd_fst_exp__h365676, - _theResult___snd_fst_exp__h383496, - _theResult___snd_fst_exp__h411373, - _theResult___snd_fst_exp__h429193, - _theResult___snd_fst_exp__h457068, - _theResult___snd_fst_exp__h474888, - din_inc___2_exp__h383527, - din_inc___2_exp__h383551, - din_inc___2_exp__h383581, - din_inc___2_exp__h383605, - din_inc___2_exp__h429224, - din_inc___2_exp__h429248, - din_inc___2_exp__h429278, - din_inc___2_exp__h429302, - din_inc___2_exp__h474919, - din_inc___2_exp__h474943, - din_inc___2_exp__h474973, - din_inc___2_exp__h474997, - f1_exp84946_MINUS_127__q136, - f1_exp__h484946, - f2_exp23940_MINUS_127__q176, - f2_exp__h523940, - f3_exp63244_MINUS_127__q153, - f3_exp__h563244, - out_exp__h357013, - out_exp__h365595, - out_exp__h374779, - out_exp__h383415, - out_exp__h402710, - out_exp__h411292, - out_exp__h420476, - out_exp__h429112, - out_exp__h448405, - out_exp__h456987, - out_exp__h466171, - out_exp__h474807, - out_f_exp__h383791, - out_f_exp__h429488, - out_f_exp__h475183, - x__h616677; + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q70, + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q35, + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q105, + _0_CONCAT_csrf_external_int_en_vec_3_read__1850_ETC___d12969, + _theResult___exp__h356701, + _theResult___exp__h365283, + _theResult___exp__h374467, + _theResult___exp__h383103, + _theResult___exp__h383205, + _theResult___exp__h402398, + _theResult___exp__h410980, + _theResult___exp__h420164, + _theResult___exp__h428800, + _theResult___exp__h428902, + _theResult___exp__h448093, + _theResult___exp__h456675, + _theResult___exp__h465859, + _theResult___exp__h474495, + _theResult___exp__h474597, + _theResult___fst_exp__h356185, + _theResult___fst_exp__h356250, + _theResult___fst_exp__h356256, + _theResult___fst_exp__h356259, + _theResult___fst_exp__h356782, + _theResult___fst_exp__h364832, + _theResult___fst_exp__h364838, + _theResult___fst_exp__h364841, + _theResult___fst_exp__h365364, + _theResult___fst_exp__h373951, + _theResult___fst_exp__h374016, + _theResult___fst_exp__h374022, + _theResult___fst_exp__h374025, + _theResult___fst_exp__h374548, + _theResult___fst_exp__h382588, + _theResult___fst_exp__h382627, + _theResult___fst_exp__h382633, + _theResult___fst_exp__h382636, + _theResult___fst_exp__h383184, + _theResult___fst_exp__h383193, + _theResult___fst_exp__h383196, + _theResult___fst_exp__h401882, + _theResult___fst_exp__h401947, + _theResult___fst_exp__h401953, + _theResult___fst_exp__h401956, + _theResult___fst_exp__h402479, + _theResult___fst_exp__h410529, + _theResult___fst_exp__h410535, + _theResult___fst_exp__h410538, + _theResult___fst_exp__h411061, + _theResult___fst_exp__h419648, + _theResult___fst_exp__h419713, + _theResult___fst_exp__h419719, + _theResult___fst_exp__h419722, + _theResult___fst_exp__h420245, + _theResult___fst_exp__h428285, + _theResult___fst_exp__h428324, + _theResult___fst_exp__h428330, + _theResult___fst_exp__h428333, + _theResult___fst_exp__h428881, + _theResult___fst_exp__h428890, + _theResult___fst_exp__h428893, + _theResult___fst_exp__h447577, + _theResult___fst_exp__h447642, + _theResult___fst_exp__h447648, + _theResult___fst_exp__h447651, + _theResult___fst_exp__h448174, + _theResult___fst_exp__h456224, + _theResult___fst_exp__h456230, + _theResult___fst_exp__h456233, + _theResult___fst_exp__h456756, + _theResult___fst_exp__h465343, + _theResult___fst_exp__h465408, + _theResult___fst_exp__h465414, + _theResult___fst_exp__h465417, + _theResult___fst_exp__h465940, + _theResult___fst_exp__h473980, + _theResult___fst_exp__h474019, + _theResult___fst_exp__h474025, + _theResult___fst_exp__h474028, + _theResult___fst_exp__h474576, + _theResult___fst_exp__h474585, + _theResult___fst_exp__h474588, + _theResult___snd_fst_exp__h365367, + _theResult___snd_fst_exp__h383187, + _theResult___snd_fst_exp__h411064, + _theResult___snd_fst_exp__h428884, + _theResult___snd_fst_exp__h456759, + _theResult___snd_fst_exp__h474579, + din_inc___2_exp__h383218, + din_inc___2_exp__h383242, + din_inc___2_exp__h383272, + din_inc___2_exp__h383296, + din_inc___2_exp__h428915, + din_inc___2_exp__h428939, + din_inc___2_exp__h428969, + din_inc___2_exp__h428993, + din_inc___2_exp__h474610, + din_inc___2_exp__h474634, + din_inc___2_exp__h474664, + din_inc___2_exp__h474688, + f1_exp84637_MINUS_127__q128, + f1_exp__h484637, + f2_exp23631_MINUS_127__q168, + f2_exp__h523631, + f3_exp62935_MINUS_127__q145, + f3_exp__h562935, + out_exp__h356704, + out_exp__h365286, + out_exp__h374470, + out_exp__h383106, + out_exp__h402401, + out_exp__h410983, + out_exp__h420167, + out_exp__h428803, + out_exp__h448096, + out_exp__h456678, + out_exp__h465862, + out_exp__h474498, + out_f_exp__h383482, + out_f_exp__h429179, + out_f_exp__h474874, + x__h616354; wire [5 : 0] IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4343, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5735, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7127, @@ -5839,11 +5759,11 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4574, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7358, IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2172, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d15932, - x__h184195, - x__h709701; - wire [4 : 0] IF_fetchStage_pipelines_1_first__2943_BITS_194_ETC___d14531, - IF_rob_deqPort_0_canDeq__5214_THEN_IF_NOT_rob__ETC___d15509, + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d15778, + x__h183887, + x__h708381; + wire [4 : 0] IF_fetchStage_pipelines_1_first__2940_BITS_194_ETC___d14527, + IF_rob_deqPort_0_canDeq__5156_THEN_IF_NOT_rob__ETC___d15354, _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5265, _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6657, _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d8049, @@ -5859,116 +5779,115 @@ module mkCore(CLK, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5277, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6669, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d8061, - checkForException___d13180, - checkForException___d13863, - fflags__h723884, - res_fflags__h340168, - res_fflags__h385870, - res_fflags__h431565, - rob_deqPort_0_deq_data__4547_BIT_166_4563_CONC_ETC___d14612, - rs1__h659223, - x__h155035, - x__h158582, - x__h161398, - x__h289512, - y_avValue_fst__h722016, - y_avValue_fst__h723799, - y_avValue_fst__h723827; + checkForException___d13176, + checkForException___d13859, + fflags__h720016, + res_fflags__h339859, + res_fflags__h385561, + res_fflags__h431256, + rs1__h658887, + x__h154726, + x__h158273, + x__h161089, + x__h289204, + y_avValue_snd_fst__h719462, + y_avValue_snd_fst__h720076, + y_avValue_snd_fst__h720105; wire [3 : 0] IF_IF_coreFix_memExe_dTlb_procResp__740_BIT_11_ETC___d1875, IF_IF_coreFix_memExe_dTlb_procResp__740_BIT_11_ETC___d1877, IF_IF_coreFix_memExe_dTlb_procResp__740_BIT_11_ETC___d1879, IF_IF_coreFix_memExe_dTlb_procResp__740_BIT_11_ETC___d1881, IF_IF_coreFix_memExe_dTlb_procResp__740_BIT_11_ETC___d1883, IF_IF_coreFix_memExe_dTlb_procResp__740_BIT_11_ETC___d1885, - IF_IF_fetchStage_pipelines_0_first__2934_BIT_6_ETC___d13368, - IF_IF_fetchStage_pipelines_0_first__2934_BIT_6_ETC___d13369, - IF_IF_fetchStage_pipelines_0_first__2934_BIT_6_ETC___d13370, - IF_IF_fetchStage_pipelines_0_first__2934_BIT_6_ETC___d13371, - IF_IF_fetchStage_pipelines_0_first__2934_BIT_6_ETC___d13372, - IF_IF_fetchStage_pipelines_0_first__2934_BIT_6_ETC___d13373, - IF_IF_fetchStage_pipelines_0_first__2934_BIT_6_ETC___d13374, - IF_IF_fetchStage_pipelines_0_first__2934_BIT_6_ETC___d13375, - IF_IF_fetchStage_pipelines_0_first__2934_BIT_6_ETC___d13376, - IF_IF_fetchStage_pipelines_0_first__2934_BIT_6_ETC___d13377, - IF_IF_fetchStage_pipelines_0_first__2934_BIT_6_ETC___d13378, - IF_IF_fetchStage_pipelines_0_first__2934_BIT_6_ETC___d13379, - IF_IF_fetchStage_pipelines_0_first__2934_BIT_6_ETC___d13380, - IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3__ETC___d13413, + IF_IF_fetchStage_pipelines_0_first__2931_BIT_6_ETC___d13364, + IF_IF_fetchStage_pipelines_0_first__2931_BIT_6_ETC___d13365, + IF_IF_fetchStage_pipelines_0_first__2931_BIT_6_ETC___d13366, + IF_IF_fetchStage_pipelines_0_first__2931_BIT_6_ETC___d13367, + IF_IF_fetchStage_pipelines_0_first__2931_BIT_6_ETC___d13368, + IF_IF_fetchStage_pipelines_0_first__2931_BIT_6_ETC___d13369, + IF_IF_fetchStage_pipelines_0_first__2931_BIT_6_ETC___d13370, + IF_IF_fetchStage_pipelines_0_first__2931_BIT_6_ETC___d13371, + IF_IF_fetchStage_pipelines_0_first__2931_BIT_6_ETC___d13372, + IF_IF_fetchStage_pipelines_0_first__2931_BIT_6_ETC___d13373, + IF_IF_fetchStage_pipelines_0_first__2931_BIT_6_ETC___d13374, + IF_IF_fetchStage_pipelines_0_first__2931_BIT_6_ETC___d13375, + IF_IF_fetchStage_pipelines_0_first__2931_BIT_6_ETC___d13376, + IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3__ETC___d13409, IF_NOT_coreFix_memExe_dTlb_procResp__740_BIT_1_ETC___d1819, - IF_NOT_renameStage_rg_m_halt_req_2961_BIT_4_29_ETC___d13453, - IF_checkForException_3180_BIT_4_3181_THEN_IF_c_ETC___d13329, + IF_NOT_renameStage_rg_m_halt_req_2958_BIT_4_29_ETC___d13449, + IF_checkForException_3176_BIT_4_3177_THEN_IF_c_ETC___d13325, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2929, IF_coreFix_memExe_dTlb_procResp__740_BITS_105__ETC___d1820, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1263, - cause_code__h707068, - vm_mode_reg__read__h617886; + cause_code__h705748, + vm_mode_reg__read__h617563; wire [2 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2567, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2886, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1220, - _theResult_____2__h298821, - dcsr_cause__h706588, - next_deqP___1__h299100, - v__h298241, - v__h298472, - x__h304451, - x_decodeInfo_frm__h658907; + _theResult_____2__h298513, + dcsr_cause__h705268, + next_deqP___1__h298792, + v__h297933, + v__h298164, + x__h304143, + x_decodeInfo_frm__h658571; wire [1 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2882, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1216, - IF_rob_deqPort_0_canDeq__5214_THEN_IF_NOT_rob__ETC___d15530, - IF_sfdin02185_BIT_33_THEN_2_ELSE_0__q65, - IF_sfdin13905_BIT_4_THEN_2_ELSE_0__q139, - IF_sfdin19951_BIT_33_THEN_2_ELSE_0__q75, - IF_sfdin47880_BIT_33_THEN_2_ELSE_0__q100, - IF_sfdin52758_BIT_4_THEN_2_ELSE_0__q179, - IF_sfdin56488_BIT_33_THEN_2_ELSE_0__q30, - IF_sfdin65646_BIT_33_THEN_2_ELSE_0__q110, - IF_sfdin74254_BIT_33_THEN_2_ELSE_0__q40, - IF_sfdin92062_BIT_4_THEN_2_ELSE_0__q156, - IF_theResult___snd00847_BIT_4_THEN_2_ELSE_0__q159, - IF_theResult___snd04285_BIT_4_THEN_2_ELSE_0__q135, - IF_theResult___snd10798_BIT_33_THEN_2_ELSE_0__q67, - IF_theResult___snd22690_BIT_4_THEN_2_ELSE_0__q142, - IF_theResult___snd28588_BIT_33_THEN_2_ELSE_0__q80, - IF_theResult___snd43138_BIT_4_THEN_2_ELSE_0__q175, - IF_theResult___snd56493_BIT_33_THEN_2_ELSE_0__q102, - IF_theResult___snd61543_BIT_4_THEN_2_ELSE_0__q182, - IF_theResult___snd65101_BIT_33_THEN_2_ELSE_0__q32, - IF_theResult___snd74283_BIT_33_THEN_2_ELSE_0__q115, - IF_theResult___snd82442_BIT_4_THEN_2_ELSE_0__q152, - IF_theResult___snd82891_BIT_33_THEN_2_ELSE_0__q45, - guard__h348393, - guard__h357102, - guard__h366032, - guard__h374868, - guard__h394092, - guard__h402799, - guard__h411729, - guard__h420565, - guard__h439787, - guard__h448494, - guard__h457424, - guard__h466260, - guard__h496373, - guard__h505685, - guard__h514754, - guard__h535226, - guard__h544538, - guard__h553607, - guard__h574530, - guard__h583842, - guard__h592911, - prv__h725519, - prv__h725563, - r1__read_BITS_13_TO_12___h659092, - sbIdx__h158461, - v__h607011, - v__h607021, - v__h608052, - x__h718668, - x__h724126, - y_avValue_snd_snd_snd_fst__h722464, - y_avValue_snd_snd_snd_fst__h723950, - y_avValue_snd_snd_snd_fst__h723979; + IF_rob_deqPort_0_canDeq__5156_THEN_IF_NOT_rob__ETC___d15375, + IF_sfdin01876_BIT_33_THEN_2_ELSE_0__q57, + IF_sfdin13596_BIT_4_THEN_2_ELSE_0__q131, + IF_sfdin19642_BIT_33_THEN_2_ELSE_0__q67, + IF_sfdin47571_BIT_33_THEN_2_ELSE_0__q92, + IF_sfdin52449_BIT_4_THEN_2_ELSE_0__q171, + IF_sfdin56179_BIT_33_THEN_2_ELSE_0__q22, + IF_sfdin65337_BIT_33_THEN_2_ELSE_0__q102, + IF_sfdin73945_BIT_33_THEN_2_ELSE_0__q32, + IF_sfdin91753_BIT_4_THEN_2_ELSE_0__q148, + IF_theResult___snd00538_BIT_4_THEN_2_ELSE_0__q151, + IF_theResult___snd03976_BIT_4_THEN_2_ELSE_0__q127, + IF_theResult___snd10489_BIT_33_THEN_2_ELSE_0__q59, + IF_theResult___snd22381_BIT_4_THEN_2_ELSE_0__q134, + IF_theResult___snd28279_BIT_33_THEN_2_ELSE_0__q72, + IF_theResult___snd42829_BIT_4_THEN_2_ELSE_0__q167, + IF_theResult___snd56184_BIT_33_THEN_2_ELSE_0__q94, + IF_theResult___snd61234_BIT_4_THEN_2_ELSE_0__q174, + IF_theResult___snd64792_BIT_33_THEN_2_ELSE_0__q24, + IF_theResult___snd73974_BIT_33_THEN_2_ELSE_0__q107, + IF_theResult___snd82133_BIT_4_THEN_2_ELSE_0__q144, + IF_theResult___snd82582_BIT_33_THEN_2_ELSE_0__q37, + guard__h348084, + guard__h356793, + guard__h365723, + guard__h374559, + guard__h393783, + guard__h402490, + guard__h411420, + guard__h420256, + guard__h439478, + guard__h448185, + guard__h457115, + guard__h465951, + guard__h496064, + guard__h505376, + guard__h514445, + guard__h534917, + guard__h544229, + guard__h553298, + guard__h574221, + guard__h583533, + guard__h592602, + prv__h721530, + prv__h721574, + r1__read_BITS_13_TO_12___h658756, + sbIdx__h158152, + v__h606702, + v__h606712, + v__h607743, + x__h716537, + x__h720263, + y_avValue_snd_snd_snd_fst__h719472, + y_avValue_snd_snd_snd_fst__h720086, + y_avValue_snd_snd_snd_fst__h720115; wire IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5165, IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5215, IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6557, @@ -5987,9 +5906,9 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10814, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9096, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9811, - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13222, - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13921, - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13958, + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13218, + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13917, + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13954, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10048, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10049, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10585, @@ -6015,12 +5934,12 @@ module mkCore(CLK, IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d10240, IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d8755, IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d9470, - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__237_ETC___d12407, - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__237_ETC___d12408, - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__237_ETC___d12409, - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__237_ETC___d12434, - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__237_ETC___d12435, - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__237_ETC___d12436, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12404, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12405, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12406, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12431, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12432, + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12433, IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11545, IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11546, IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11547, @@ -6044,11 +5963,11 @@ module mkCore(CLK, IF_NOT_coreFix_memExe_bypassWire_0_whas__584_5_ETC___d1647, IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2114, IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2131, - IF_NOT_fetchStage_pipelines_0_canDeq__2932_293_ETC___d14073, - IF_NOT_fetchStage_pipelines_0_canDeq__2932_293_ETC___d14081, - IF_NOT_fetchStage_pipelines_1_first__2943_BITS_ETC___d13996, - IF_NOT_fetchStage_pipelines_1_first__2943_BITS_ETC___d14080, - IF_NOT_rob_deqPort_1_deq_data__5222_BIT_25_522_ETC___d15521, + IF_NOT_fetchStage_pipelines_0_canDeq__2929_293_ETC___d14069, + IF_NOT_fetchStage_pipelines_0_canDeq__2929_293_ETC___d14077, + IF_NOT_fetchStage_pipelines_1_first__2940_BITS_ETC___d13992, + IF_NOT_fetchStage_pipelines_1_first__2940_BITS_ETC___d14076, + IF_NOT_rob_deqPort_1_deq_data__5163_BIT_25_516_ETC___d15366, IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10047, IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10583, IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10816, @@ -6078,8 +5997,8 @@ module mkCore(CLK, IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8107, IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8120, IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8133, - IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2350_ETC___d12383, - IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2350_ETC___d12419, + IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2347_ETC___d12380, + IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2347_ETC___d12416, IF_coreFix_aluExe_1_dispToRegQ_RDY_first__1488_ETC___d11521, IF_coreFix_aluExe_1_dispToRegQ_RDY_first__1488_ETC___d11557, IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8311, @@ -6160,28 +6079,28 @@ module mkCore(CLK, IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d3745, IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3730, IF_coreFix_memExe_respLrScAmoQ_enqReq_lat_1_wh_ETC___d3654, - IF_fetchStage_RDY_pipelines_0_first__2931_AND__ETC___d13610, - IF_fetchStage_RDY_pipelines_1_first__2942_AND__ETC___d13998, - IF_fetchStage_RDY_pipelines_1_first__2942_AND__ETC___d14070, - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d14119, - IF_fetchStage_pipelines_1_first__2943_BITS_194_ETC___d14249, + IF_fetchStage_RDY_pipelines_0_first__2928_AND__ETC___d13606, + IF_fetchStage_RDY_pipelines_1_first__2939_AND__ETC___d13994, + IF_fetchStage_RDY_pipelines_1_first__2939_AND__ETC___d14066, + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d14115, + IF_fetchStage_pipelines_1_first__2940_BITS_194_ETC___d14245, IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmio_c_ETC___d339, IF_mmio_cRsQ_enqReq_lat_1_whas__74_THEN_mmio_c_ETC___d783, IF_mmio_dataReqQ_enqReq_lat_1_whas__7_THEN_mmi_ETC___d46, IF_mmio_dataRespQ_enqReq_lat_1_whas__92_THEN_m_ETC___d201, IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmio_p_ETC___d642, IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_mmio_p_ETC___d491, - IF_rob_deqPort_1_canDeq__5219_THEN_IF_NOT_rob__ETC___d15522, + IF_rob_deqPort_1_canDeq__5160_THEN_IF_NOT_rob__ETC___d15367, NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5317, NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5345, NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d6709, NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d6737, NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d8101, NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d8129, - NOT_IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_296_ETC___d13510, - NOT_IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_296_ETC___d13597, - NOT_IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_296_ETC___d13890, - NOT_IF_NOT_rob_deqPort_0_canDeq__5214_5215_OR__ETC___d15527, + NOT_IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_296_ETC___d13506, + NOT_IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_296_ETC___d13593, + NOT_IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_296_ETC___d13886, + NOT_IF_NOT_rob_deqPort_0_canDeq__5156_5157_OR__ETC___d15372, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10167, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10876, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10918, @@ -6195,13 +6114,13 @@ module mkCore(CLK, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11117, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8667, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9397, - NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13658, - NOT_commitStage_commitTrap_4555_BIT_4_4779_478_ETC___d14814, - NOT_commitStage_commitTrap_4555_BIT_4_4779_478_ETC___d14821, - NOT_commitStage_commitTrap_4555_BIT_4_4779_478_ETC___d14881, - NOT_commitStage_rg_run_state_4553_4554_AND_NOT_ETC___d15010, - NOT_coreFix_aluExe_0_bypassWire_0_whas__2372_2_ETC___d12399, - NOT_coreFix_aluExe_0_bypassWire_0_whas__2372_2_ETC___d12429, + NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13654, + NOT_commitStage_commitTrap_4549_BIT_4_4679_468_ETC___d14714, + NOT_commitStage_commitTrap_4549_BIT_4_4679_468_ETC___d14721, + NOT_commitStage_commitTrap_4549_BIT_4_4679_468_ETC___d14781, + NOT_commitStage_rg_run_state_4547_4548_AND_NOT_ETC___d14951, + NOT_coreFix_aluExe_0_bypassWire_0_whas__2369_2_ETC___d12396, + NOT_coreFix_aluExe_0_bypassWire_0_whas__2369_2_ETC___d12426, NOT_coreFix_aluExe_1_bypassWire_0_whas__1510_1_ETC___d11537, NOT_coreFix_aluExe_1_bypassWire_0_whas__1510_1_ETC___d11567, NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8327, @@ -6256,41 +6175,41 @@ module mkCore(CLK, NOT_coreFix_memExe_respLrScAmoQ_clearReq_dummy_ETC___d3643, NOT_coreFix_memExe_respLrScAmoQ_enqReq_dummy2__ETC___d3685, NOT_coreFix_memExe_respLrScAmoQ_full_977_978_A_ETC___d2110, - NOT_csrf_fs_reg_read__1726_EQ_0_3169_3170_OR_N_ETC___d13503, - NOT_csrf_fs_reg_read__1726_EQ_0_3169_3170_OR_N_ETC___d13595, - NOT_csrf_fs_reg_read__1726_EQ_0_3169_3170_OR_N_ETC___d13888, - NOT_csrf_prv_reg_read__2964_ULE_1_4882_4923_OR_ETC___d14927, - NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d13701, - NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d13935, - NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d13979, - NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d14034, - NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d14052, - NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d14201, - NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d14255, - NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d14383, - NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d14388, - NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d14390, - NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d14402, - NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d14438, - NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d14458, - NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d14465, - NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d14466, - NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d14510, - NOT_fetchStage_pipelines_0_first__2934_BITS_19_ETC___d13499, - NOT_fetchStage_pipelines_0_first__2934_BITS_19_ETC___d13640, - NOT_fetchStage_pipelines_0_first__2934_BITS_19_ETC___d13911, - NOT_fetchStage_pipelines_0_first__2934_BITS_19_ETC___d13917, - NOT_fetchStage_pipelines_0_first__2934_BITS_19_ETC___d14078, - NOT_fetchStage_pipelines_0_first__2934_BITS_19_ETC___d14262, - NOT_fetchStage_pipelines_0_first__2934_BITS_32_ETC___d14286, - NOT_fetchStage_pipelines_0_first__2934_BIT_68__ETC___d13651, - NOT_fetchStage_pipelines_1_canDeq__2940_2941_O_ETC___d12949, - NOT_fetchStage_pipelines_1_first__2943_BITS_19_ETC___d13674, - NOT_fetchStage_pipelines_1_first__2943_BITS_19_ETC___d13904, - NOT_fetchStage_pipelines_1_first__2943_BITS_19_ETC___d14021, - NOT_fetchStage_pipelines_1_first__2943_BITS_19_ETC___d14399, - NOT_fetchStage_pipelines_1_first__2943_BITS_32_ETC___d14453, - NOT_fetchStage_pipelines_1_first__2943_BIT_68__ETC___d14396, + NOT_csrf_fs_reg_read__1726_EQ_0_3165_3166_OR_N_ETC___d13499, + NOT_csrf_fs_reg_read__1726_EQ_0_3165_3166_OR_N_ETC___d13591, + NOT_csrf_fs_reg_read__1726_EQ_0_3165_3166_OR_N_ETC___d13884, + NOT_csrf_prv_reg_read__2961_ULE_1_4782_4823_OR_ETC___d14827, + NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d13697, + NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d13931, + NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d13975, + NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d14030, + NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d14048, + NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d14197, + NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d14251, + NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d14379, + NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d14384, + NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d14386, + NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d14398, + NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d14434, + NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d14454, + NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d14461, + NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d14462, + NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d14506, + NOT_fetchStage_pipelines_0_first__2931_BITS_19_ETC___d13495, + NOT_fetchStage_pipelines_0_first__2931_BITS_19_ETC___d13636, + NOT_fetchStage_pipelines_0_first__2931_BITS_19_ETC___d13907, + NOT_fetchStage_pipelines_0_first__2931_BITS_19_ETC___d13913, + NOT_fetchStage_pipelines_0_first__2931_BITS_19_ETC___d14074, + NOT_fetchStage_pipelines_0_first__2931_BITS_19_ETC___d14258, + NOT_fetchStage_pipelines_0_first__2931_BITS_32_ETC___d14282, + NOT_fetchStage_pipelines_0_first__2931_BIT_68__ETC___d13647, + NOT_fetchStage_pipelines_1_canDeq__2937_2938_O_ETC___d12946, + NOT_fetchStage_pipelines_1_first__2940_BITS_19_ETC___d13670, + NOT_fetchStage_pipelines_1_first__2940_BITS_19_ETC___d13900, + NOT_fetchStage_pipelines_1_first__2940_BITS_19_ETC___d14017, + NOT_fetchStage_pipelines_1_first__2940_BITS_19_ETC___d14395, + NOT_fetchStage_pipelines_1_first__2940_BITS_32_ETC___d14449, + NOT_fetchStage_pipelines_1_first__2940_BIT_68__ETC___d14392, NOT_mmio_cRqQ_clearReq_dummy2_1_read__26_27_OR_ETC___d431, NOT_mmio_cRqQ_enqReq_dummy2_2_read__32_47_OR_I_ETC___d452, NOT_mmio_cRsQ_clearReq_dummy2_1_read__18_19_OR_ETC___d823, @@ -6306,21 +6225,21 @@ module mkCore(CLK, NOT_mmio_pRqQ_enqReq_dummy2_2_read__35_50_OR_I_ETC___d755, NOT_mmio_pRsQ_clearReq_dummy2_1_read__88_89_OR_ETC___d593, NOT_mmio_pRsQ_enqReq_dummy2_2_read__94_09_OR_I_ETC___d614, - NOT_regRenamingTable_rename_0_canRename__3582__ETC___d13926, - NOT_regRenamingTable_rename_0_canRename__3582__ETC___d14002, - NOT_regRenamingTable_rename_0_canRename__3582__ETC___d14378, - NOT_regRenamingTable_rename_1_canRename__3704__ETC___d13966, - NOT_renameStage_rg_m_halt_req_2961_BIT_4_2962__ETC___d13272, - NOT_renameStage_rg_m_halt_req_2961_BIT_4_2962__ETC___d13602, - NOT_renameStage_rg_m_halt_req_2961_BIT_4_2962__ETC___d13901, - NOT_renameStage_rg_m_halt_req_2961_BIT_4_2962__ETC___d14043, - NOT_renameStage_rg_m_halt_req_2961_BIT_4_2962__ETC___d14061, - NOT_rob_deqPort_0_canDeq__5214_5215_OR_rob_RDY_ETC___d15256, - NOT_rob_deqPort_0_canDeq__5214_5215_OR_rob_deq_ETC___d15503, - NOT_rob_deqPort_0_deq_data__4547_BITS_186_TO_1_ETC___d14999, - NOT_rob_deqPort_1_deq_data__5222_BIT_25_5223_5_ETC___d15253, - NOT_specTagManager_canClaim__3580_3666_OR_NOT__ETC___d14172, - NOT_specTagManager_canClaim__3580_3666_OR_NOT__ETC___d14239, + NOT_regRenamingTable_rename_0_canRename__3578__ETC___d13922, + NOT_regRenamingTable_rename_0_canRename__3578__ETC___d13998, + NOT_regRenamingTable_rename_0_canRename__3578__ETC___d14374, + NOT_regRenamingTable_rename_1_canRename__3700__ETC___d13962, + NOT_renameStage_rg_m_halt_req_2958_BIT_4_2959__ETC___d13268, + NOT_renameStage_rg_m_halt_req_2958_BIT_4_2959__ETC___d13598, + NOT_renameStage_rg_m_halt_req_2958_BIT_4_2959__ETC___d13897, + NOT_renameStage_rg_m_halt_req_2958_BIT_4_2959__ETC___d14039, + NOT_renameStage_rg_m_halt_req_2958_BIT_4_2959__ETC___d14057, + NOT_rob_deqPort_0_canDeq__5156_5157_OR_rob_RDY_ETC___d15195, + NOT_rob_deqPort_0_canDeq__5156_5157_OR_rob_deq_ETC___d15348, + NOT_rob_deqPort_0_deq_data__4542_BITS_186_TO_1_ETC___d14941, + NOT_rob_deqPort_1_deq_data__5163_BIT_25_5164_5_ETC___d15192, + NOT_specTagManager_canClaim__3576_3662_OR_NOT__ETC___d14168, + NOT_specTagManager_canClaim__3576_3662_OR_NOT__ETC___d14235, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10243, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10244, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8758, @@ -6354,11 +6273,11 @@ module mkCore(CLK, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6361, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7360, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7753, - _0_OR_NOT_fetchStage_pipelines_0_first__2934_BI_ETC___d14093, - _0_OR_NOT_fetchStage_pipelines_1_first__2943_BI_ETC___d13994, - _0_OR_NOT_fetchStage_pipelines_1_first__2943_BI_ETC___d14185, - _0b0_CONCAT_csrf_medeleg_15_reg_read__1831_1832_ETC___d14902, - _0b0_CONCAT_csrf_mideleg_11_reg_read__1839_1840_ETC___d14884, + _0_OR_NOT_fetchStage_pipelines_0_first__2931_BI_ETC___d14089, + _0_OR_NOT_fetchStage_pipelines_1_first__2940_BI_ETC___d13990, + _0_OR_NOT_fetchStage_pipelines_1_first__2940_BI_ETC___d14181, + _0b0_CONCAT_csrf_medeleg_15_reg_read__1831_1832_ETC___d14802, + _0b0_CONCAT_csrf_mideleg_11_reg_read__1839_1840_ETC___d14784, _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4108, _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4109, _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5280, @@ -6386,7 +6305,8 @@ module mkCore(CLK, _dfoo2, _dfoo20, _dfoo24, - _dfoo30, + _dfoo26, + _dfoo32, _dfoo7, _dor1coreFix_aluExe_0_bypassWire_2$EN_wset, _dor1coreFix_aluExe_0_bypassWire_3$EN_wset, @@ -6412,24 +6332,24 @@ module mkCore(CLK, _dor1sbAggr$EN_setReady_3_put, _dor1sbCons$EN_setReady_0_put, _dor1sbCons$EN_setReady_1_put, - _theResult_____2__h306817, - _theResult_____2__h312811, - _theResult_____2__h320665, - _theResult_____2__h331009, - _theResult_____2__h334234, - commitStage_commitTrap_4555_BIT_4_4779_AND_com_ETC___d14844, - commitStage_commitTrap_4555_BIT_4_4779_AND_com_ETC___d14845, - coreFix_aluExe_0_bypassWire_0_wget__2373_BITS__ETC___d12375, - coreFix_aluExe_0_bypassWire_0_wget__2373_BITS__ETC___d12416, - coreFix_aluExe_0_bypassWire_1_wget__2386_BITS__ETC___d12388, - coreFix_aluExe_0_bypassWire_1_wget__2386_BITS__ETC___d12422, - coreFix_aluExe_0_bypassWire_2_wget__2394_BITS__ETC___d12396, - coreFix_aluExe_0_bypassWire_2_wget__2394_BITS__ETC___d12426, - coreFix_aluExe_0_bypassWire_3_wget__2401_BITS__ETC___d12403, - coreFix_aluExe_0_bypassWire_3_wget__2401_BITS__ETC___d12430, - coreFix_aluExe_0_dispToRegQ_RDY_first__2350_AN_ETC___d12441, - coreFix_aluExe_0_exeToFinQ_RDY_first__2817_AND_ETC___d12857, - coreFix_aluExe_0_rsAlu_approximateCount__3617__ETC___d13619, + _theResult_____2__h306509, + _theResult_____2__h312503, + _theResult_____2__h320357, + _theResult_____2__h330701, + _theResult_____2__h333926, + commitStage_commitTrap_4549_BIT_4_4679_AND_com_ETC___d14744, + commitStage_commitTrap_4549_BIT_4_4679_AND_com_ETC___d14745, + coreFix_aluExe_0_bypassWire_0_wget__2370_BITS__ETC___d12372, + coreFix_aluExe_0_bypassWire_0_wget__2370_BITS__ETC___d12413, + coreFix_aluExe_0_bypassWire_1_wget__2383_BITS__ETC___d12385, + coreFix_aluExe_0_bypassWire_1_wget__2383_BITS__ETC___d12419, + coreFix_aluExe_0_bypassWire_2_wget__2391_BITS__ETC___d12393, + coreFix_aluExe_0_bypassWire_2_wget__2391_BITS__ETC___d12423, + coreFix_aluExe_0_bypassWire_3_wget__2398_BITS__ETC___d12400, + coreFix_aluExe_0_bypassWire_3_wget__2398_BITS__ETC___d12427, + coreFix_aluExe_0_dispToRegQ_RDY_first__2347_AN_ETC___d12438, + coreFix_aluExe_0_exeToFinQ_RDY_first__2814_AND_ETC___d12854, + coreFix_aluExe_0_rsAlu_approximateCount__3613__ETC___d13615, coreFix_aluExe_1_bypassWire_0_wget__1511_BITS__ETC___d11513, coreFix_aluExe_1_bypassWire_0_wget__1511_BITS__ETC___d11554, coreFix_aluExe_1_bypassWire_1_wget__1524_BITS__ETC___d11526, @@ -6439,7 +6359,7 @@ module mkCore(CLK, coreFix_aluExe_1_bypassWire_3_wget__1539_BITS__ETC___d11541, coreFix_aluExe_1_bypassWire_3_wget__1539_BITS__ETC___d11568, coreFix_aluExe_1_dispToRegQ_RDY_first__1488_AN_ETC___d11579, - coreFix_aluExe_1_exeToFinQ_RDY_first__2143_AND_ETC___d12184, + coreFix_aluExe_1_exeToFinQ_RDY_first__2140_AND_ETC___d12181, coreFix_fpuMulDivExe_0_bypassWire_0_wget__301__ETC___d8303, coreFix_fpuMulDivExe_0_bypassWire_0_wget__301__ETC___d8343, coreFix_fpuMulDivExe_0_bypassWire_0_wget__301__ETC___d8369, @@ -6463,7 +6383,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ_first__482_BI_ETC___d11047, coreFix_fpuMulDivExe_0_regToExeQ_first__482_BI_ETC___d11089, coreFix_fpuMulDivExe_0_regToExeQ_first__482_BI_ETC___d11131, - coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__40_ETC___d14192, + coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__40_ETC___d14188, coreFix_memExe_bypassWire_0_wget__585_BITS_70__ETC___d1587, coreFix_memExe_bypassWire_0_wget__585_BITS_70__ETC___d1627, coreFix_memExe_bypassWire_1_wget__598_BITS_70__ETC___d1600, @@ -6533,110 +6453,112 @@ module mkCore(CLK, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1271, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1275, coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2_re_ETC___d3670, - csrf_fs_reg_read__1726_EQ_0_3169_AND_fetchStag_ETC___d13215, - csrf_fs_reg_read__1726_EQ_0_3169_AND_fetchStag_ETC___d13676, - csrf_fs_reg_read__1726_EQ_0_3169_AND_fetchStag_ETC___d13956, - csrf_prv_reg_read__2964_ULE_1_4882_AND_IF_comm_ETC___d14904, - csrf_prv_reg_read__2964_ULE_1___d14882, - csrf_prv_reg_read__2964_ULT_IF_fetchStage_pipe_ETC___d13212, - csrf_rg_dcsr_read__1902_BIT_2_3232_OR_NOT_fetc_ETC___d13672, - epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13899, - epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d14041, - epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d14059, - f_csr_rsps_i_notFull__5637_AND_f_csr_reqs_firs_ETC___d15732, - fetchStage_RDY_pipelines_1_deq__2946_AND_NOT_f_ETC___d14243, - fetchStage_pipelines_0_canDeq__2932_AND_NOT_fe_ETC___d14183, - fetchStage_pipelines_0_canDeq__2932_AND_NOT_fe_ETC___d14265, - fetchStage_pipelines_0_canDeq__2932_AND_NOT_fe_ETC___d14370, - fetchStage_pipelines_0_canDeq__2932_AND_fetchS_ETC___d14253, - fetchStage_pipelines_0_canDeq__2932_AND_regRen_ETC___d14189, - fetchStage_pipelines_0_canDeq__2932_AND_regRen_ETC___d14196, - fetchStage_pipelines_0_canDeq__2932_AND_regRen_ETC___d14218, - fetchStage_pipelines_0_canDeq__2932_AND_regRen_ETC___d14230, - fetchStage_pipelines_0_canDeq__2932_AND_regRen_ETC___d14521, - fetchStage_pipelines_0_canDeq__2932_AND_specTa_ETC___d14348, - fetchStage_pipelines_0_first__2934_BITS_194_TO_ETC___d13210, - fetchStage_pipelines_0_first__2934_BITS_194_TO_ETC___d13910, - fetchStage_pipelines_0_first__2934_BITS_194_TO_ETC___d14009, - fetchStage_pipelines_0_first__2934_BITS_194_TO_ETC___d14121, - fetchStage_pipelines_0_first__2934_BITS_194_TO_ETC___d14127, - fetchStage_pipelines_0_first__2934_BITS_194_TO_ETC___d14144, - fetchStage_pipelines_0_first__2934_BITS_194_TO_ETC___d14156, - fetchStage_pipelines_0_first__2934_BITS_194_TO_ETC___d14163, - fetchStage_pipelines_0_first__2934_BITS_194_TO_ETC___d14179, - fetchStage_pipelines_0_first__2934_BITS_199_TO_ETC___d13683, - fetchStage_pipelines_0_first__2934_BIT_68_2963_ETC___d14000, - fetchStage_pipelines_1_first__2943_BITS_194_TO_ETC___d14138, - fetchStage_pipelines_1_first__2943_BITS_199_TO_ETC___d14150, - guard__h366630, - guard__h412327, - guard__h458022, - guard__h506283, - guard__h545136, - guard__h584440, - idx__h686963, - k__h671729, + coreFix_memExe_stb_isEmpty__011_AND_coreFix_me_ETC___d14946, + csrf_fs_reg_read__1726_EQ_0_3165_AND_fetchStag_ETC___d13211, + csrf_fs_reg_read__1726_EQ_0_3165_AND_fetchStag_ETC___d13672, + csrf_fs_reg_read__1726_EQ_0_3165_AND_fetchStag_ETC___d13952, + csrf_prv_reg_read__2961_ULE_1_4782_AND_IF_comm_ETC___d14804, + csrf_prv_reg_read__2961_ULE_1___d14782, + csrf_prv_reg_read__2961_ULT_IF_fetchStage_pipe_ETC___d13208, + csrf_rg_dcsr_read__1899_BIT_2_3228_OR_NOT_fetc_ETC___d13668, + epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13895, + epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d14037, + epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d14055, + f_csr_rsps_i_notFull__5482_AND_f_csr_reqs_firs_ETC___d15577, + fetchStage_RDY_pipelines_1_deq__2943_AND_NOT_f_ETC___d14239, + fetchStage_pipelines_0_canDeq__2929_AND_NOT_fe_ETC___d14179, + fetchStage_pipelines_0_canDeq__2929_AND_NOT_fe_ETC___d14261, + fetchStage_pipelines_0_canDeq__2929_AND_NOT_fe_ETC___d14366, + fetchStage_pipelines_0_canDeq__2929_AND_fetchS_ETC___d14249, + fetchStage_pipelines_0_canDeq__2929_AND_regRen_ETC___d14185, + fetchStage_pipelines_0_canDeq__2929_AND_regRen_ETC___d14192, + fetchStage_pipelines_0_canDeq__2929_AND_regRen_ETC___d14214, + fetchStage_pipelines_0_canDeq__2929_AND_regRen_ETC___d14226, + fetchStage_pipelines_0_canDeq__2929_AND_regRen_ETC___d14517, + fetchStage_pipelines_0_canDeq__2929_AND_specTa_ETC___d14344, + fetchStage_pipelines_0_first__2931_BITS_194_TO_ETC___d13206, + fetchStage_pipelines_0_first__2931_BITS_194_TO_ETC___d13906, + fetchStage_pipelines_0_first__2931_BITS_194_TO_ETC___d14005, + fetchStage_pipelines_0_first__2931_BITS_194_TO_ETC___d14117, + fetchStage_pipelines_0_first__2931_BITS_194_TO_ETC___d14123, + fetchStage_pipelines_0_first__2931_BITS_194_TO_ETC___d14140, + fetchStage_pipelines_0_first__2931_BITS_194_TO_ETC___d14152, + fetchStage_pipelines_0_first__2931_BITS_194_TO_ETC___d14159, + fetchStage_pipelines_0_first__2931_BITS_194_TO_ETC___d14175, + fetchStage_pipelines_0_first__2931_BITS_199_TO_ETC___d13679, + fetchStage_pipelines_0_first__2931_BIT_68_2960_ETC___d13996, + fetchStage_pipelines_1_first__2940_BITS_194_TO_ETC___d14134, + fetchStage_pipelines_1_first__2940_BITS_199_TO_ETC___d14146, + guard__h366321, + guard__h412018, + guard__h457713, + guard__h505974, + guard__h544827, + guard__h584131, + idx__h686627, + k__h671393, mmio_cRqQ_enqReq_dummy2_2_read__32_AND_IF_mmio_ETC___d444, mmio_cRsQ_enqReq_dummy2_2_read__24_AND_IF_mmio_ETC___d836, mmio_dataPendQ_enqReq_dummy2_2_read__00_AND_IF_ETC___d312, mmio_dataReqQ_enqReq_dummy2_2_read__41_AND_IF__ETC___d153, mmio_dataRespQ_enqReq_dummy2_2_read__42_AND_IF_ETC___d254, - mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13225, - mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13513, - mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13531, - mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14257, - mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14259, + mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13221, + mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13509, + mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13527, + mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14253, + mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14255, mmio_pRqQ_enqReq_dummy2_2_read__35_AND_IF_mmio_ETC___d747, mmio_pRsQ_enqReq_dummy2_2_read__94_AND_IF_mmio_ETC___d606, - msip__h75940, - next_deqP___1__h307096, - next_deqP___1__h313377, - next_deqP___1__h321231, - next_deqP___1__h331288, - next_deqP___1__h334513, - r1__read_BIT_20___h659752, - r__h616724, - regRenamingTable_RDY_rename_0_getRename__3469__ETC___d14106, - regRenamingTable_RDY_rename_1_getRename__4169__ETC___d14187, - regRenamingTable_rename_0_canRename__3582_AND__ETC___d13604, - regRenamingTable_rename_0_canRename__3582_AND__ETC___d13653, - regRenamingTable_rename_0_canRename__3582_AND__ETC___d13667, - regRenamingTable_rename_0_canRename__3582_AND__ETC___d13988, - regRenamingTable_rename_0_canRename__3582_AND__ETC___d14135, - regRenamingTable_rename_0_canRename__3582_AND__ETC___d14277, - regRenamingTable_rename_0_canRename__3582_AND__ETC___d14290, - regRenamingTable_rename_0_canRename__3582_AND__ETC___d14295, - regRenamingTable_rename_0_canRename__3582_AND__ETC___d14300, - regRenamingTable_rename_0_canRename__3582_AND__ETC___d14320, - regRenamingTable_rename_0_canRename__3582_AND__ETC___d14324, - regRenamingTable_rename_0_canRename__3582_AND__ETC___d14330, - regRenamingTable_rename_0_canRename__3582_AND__ETC___d14334, - regRenamingTable_rename_0_canRename__3582_AND__ETC___d14342, - regRenamingTable_rename_0_canRename__3582_AND__ETC___d14519, - regRenamingTable_rename_1_canRename__3704_AND__ETC___d13903, - regRenamingTable_rename_1_canRename__3704_AND__ETC___d14045, - regRenamingTable_rename_1_canRename__3704_AND__ETC___d14063, - regRenamingTable_rename_1_canRename__3704_AND__ETC___d14398, - renameStage_rg_m_halt_req_2961_BIT_4_2962_OR_N_ETC___d13238, - renameStage_rg_m_halt_req_2961_BIT_4_2962_OR_N_ETC___d13467, - renameStage_rg_m_halt_req_2961_BIT_4_2962_OR_f_ETC___d13924, - renameStage_rg_m_halt_req_2961_BIT_4_2962_OR_f_ETC___d13964, - renameStage_rg_m_halt_req_2961_BIT_4_2962_OR_f_ETC___d14005, - renameStage_rg_m_halt_req_2961_BIT_4_2962_OR_f_ETC___d14085, - rg_core_run_state_read__3228_EQ_2_3229_AND_NOT_ETC___d15576, - rob_RDY_deqPort_0_deq_data__4544_AND_rob_RDY_d_ETC___d15004, - rob_RDY_enqPort_0_enq__2956_AND_regRenamingTab_ETC___d13477, - v__h301586, - v__h302104, - v__h312100, - v__h312331, - v__h315976, - v__h316207, - v__h330577, - v__h330808, - v__h333802, - v__h334033, - x__h606355; + msip__h75632, + next_deqP___1__h306788, + next_deqP___1__h313069, + next_deqP___1__h320923, + next_deqP___1__h330980, + next_deqP___1__h334205, + r1__read_BIT_20___h659416, + r__h616401, + regRenamingTable_RDY_rename_0_getRename__3465__ETC___d14102, + regRenamingTable_RDY_rename_1_getRename__4165__ETC___d14183, + regRenamingTable_rename_0_canRename__3578_AND__ETC___d13600, + regRenamingTable_rename_0_canRename__3578_AND__ETC___d13649, + regRenamingTable_rename_0_canRename__3578_AND__ETC___d13663, + regRenamingTable_rename_0_canRename__3578_AND__ETC___d13984, + regRenamingTable_rename_0_canRename__3578_AND__ETC___d14131, + regRenamingTable_rename_0_canRename__3578_AND__ETC___d14273, + regRenamingTable_rename_0_canRename__3578_AND__ETC___d14286, + regRenamingTable_rename_0_canRename__3578_AND__ETC___d14291, + regRenamingTable_rename_0_canRename__3578_AND__ETC___d14296, + regRenamingTable_rename_0_canRename__3578_AND__ETC___d14316, + regRenamingTable_rename_0_canRename__3578_AND__ETC___d14320, + regRenamingTable_rename_0_canRename__3578_AND__ETC___d14326, + regRenamingTable_rename_0_canRename__3578_AND__ETC___d14330, + regRenamingTable_rename_0_canRename__3578_AND__ETC___d14338, + regRenamingTable_rename_0_canRename__3578_AND__ETC___d14515, + regRenamingTable_rename_1_canRename__3700_AND__ETC___d13899, + regRenamingTable_rename_1_canRename__3700_AND__ETC___d14041, + regRenamingTable_rename_1_canRename__3700_AND__ETC___d14059, + regRenamingTable_rename_1_canRename__3700_AND__ETC___d14394, + renameStage_rg_m_halt_req_2958_BIT_4_2959_OR_N_ETC___d13234, + renameStage_rg_m_halt_req_2958_BIT_4_2959_OR_N_ETC___d13463, + renameStage_rg_m_halt_req_2958_BIT_4_2959_OR_f_ETC___d13920, + renameStage_rg_m_halt_req_2958_BIT_4_2959_OR_f_ETC___d13960, + renameStage_rg_m_halt_req_2958_BIT_4_2959_OR_f_ETC___d14001, + renameStage_rg_m_halt_req_2958_BIT_4_2959_OR_f_ETC___d14081, + rg_core_run_state_read__3224_EQ_2_3225_AND_NOT_ETC___d15421, + rob_RDY_enqPort_0_enq__2953_AND_regRenamingTab_ETC___d13473, + v__h301278, + v__h301796, + v__h311792, + v__h312023, + v__h315668, + v__h315899, + v__h330269, + v__h330500, + v__h333494, + v__h333725, + value_BIT_52___h357451, + value_BIT_52___h448843, + x__h606046; // action method coreReq_start assign RDY_coreReq_start = 1'd1 ; @@ -6674,10 +6596,10 @@ module mkCore(CLK, // value method dCacheToParent_rsToP_first assign dCacheToParent_rsToP_first = - { CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q258, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q259, - !CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q260, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15906 } ; + { CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q248, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q249, + !CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q250, + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15752 } ; assign RDY_dCacheToParent_rsToP_first = !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty ; @@ -6695,9 +6617,9 @@ module mkCore(CLK, // value method dCacheToParent_rqToP_first assign dCacheToParent_rqToP_first = - { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q267, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q268, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d15932 } ; + { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q257, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q258, + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d15778 } ; assign RDY_dCacheToParent_rqToP_first = !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty ; @@ -6795,7 +6717,7 @@ module mkCore(CLK, // value method mmioToPlatform_cRq_first assign mmioToPlatform_cRq_first = { mmio_cRqQ_data_0[141:78], - CASE_mmio_cRqQ_data_0_BITS_77_TO_76_0_mmio_cRq_ETC__q9, + CASE_mmio_cRqQ_data_0_BITS_77_TO_76_0_mmio_cRq_ETC__q1, mmio_cRqQ_data_0[71:0] } ; assign RDY_mmioToPlatform_cRq_first = !mmio_cRqQ_empty ; @@ -6929,11 +6851,6 @@ module mkCore(CLK, assign CAN_FIRE_setSEIP = 1'd1 ; assign WILL_FIRE_setSEIP = EN_setSEIP ; - // action method setDEIP - assign RDY_setDEIP = 1'd1 ; - assign CAN_FIRE_setDEIP = 1'd1 ; - assign WILL_FIRE_setDEIP = EN_setDEIP ; - // action method hart0_run_halt_server_request_put assign RDY_hart0_run_halt_server_request_put = f_run_halt_reqs$FULL_N ; assign CAN_FIRE_hart0_run_halt_server_request_put = f_run_halt_reqs$FULL_N ; @@ -6987,36 +6904,6 @@ module mkCore(CLK, assign WILL_FIRE_hart0_csr_mem_server_response_get = EN_hart0_csr_mem_server_response_get ; - // actionvalue method v_to_TV_0_get - assign v_to_TV_0_get = - { v_f_to_TV_0$D_OUT[319:154], - CASE_v_f_to_TV_0D_OUT_BITS_153_TO_142_1_v_f_t_ETC__q5, - v_f_to_TV_0$D_OUT[141:140], - v_f_to_TV_0$D_OUT[140] ? - CASE_v_f_to_TV_0D_OUT_BITS_139_TO_136_0_v_f_t_ETC__q6 : - CASE_v_f_to_TV_0D_OUT_BITS_139_TO_136_0_v_f_t_ETC__q7, - v_f_to_TV_0$D_OUT[135:72], - CASE_v_f_to_TV_0D_OUT_BITS_71_TO_70_0_v_f_to__ETC__q8, - v_f_to_TV_0$D_OUT[69:0] } ; - assign RDY_v_to_TV_0_get = v_f_to_TV_0$EMPTY_N ; - assign CAN_FIRE_v_to_TV_0_get = v_f_to_TV_0$EMPTY_N ; - assign WILL_FIRE_v_to_TV_0_get = EN_v_to_TV_0_get ; - - // actionvalue method v_to_TV_1_get - assign v_to_TV_1_get = - { v_f_to_TV_1$D_OUT[319:154], - CASE_v_f_to_TV_1D_OUT_BITS_153_TO_142_1_v_f_t_ETC__q1, - v_f_to_TV_1$D_OUT[141:140], - v_f_to_TV_1$D_OUT[140] ? - CASE_v_f_to_TV_1D_OUT_BITS_139_TO_136_0_v_f_t_ETC__q2 : - CASE_v_f_to_TV_1D_OUT_BITS_139_TO_136_0_v_f_t_ETC__q3, - v_f_to_TV_1$D_OUT[135:72], - CASE_v_f_to_TV_1D_OUT_BITS_71_TO_70_0_v_f_to__ETC__q4, - v_f_to_TV_1$D_OUT[69:0] } ; - assign RDY_v_to_TV_1_get = v_f_to_TV_1$EMPTY_N ; - assign CAN_FIRE_v_to_TV_1_get = v_f_to_TV_1$EMPTY_N ; - assign WILL_FIRE_v_to_TV_1_get = EN_v_to_TV_1_get ; - // submodule coreFix_aluExe_0_dispToRegQ mkAluDispToRegFifo coreFix_aluExe_0_dispToRegQ(.CLK(CLK), .RST_N(RST_N), @@ -9786,28 +9673,6 @@ module mkCore(CLK, .isFull_ehrPort0(), .RDY_isFull_ehrPort0()); - // submodule v_f_to_TV_0 - FIFO2 #(.width(32'd320), .guarded(32'd1)) v_f_to_TV_0(.RST(RST_N), - .CLK(CLK), - .D_IN(v_f_to_TV_0$D_IN), - .ENQ(v_f_to_TV_0$ENQ), - .DEQ(v_f_to_TV_0$DEQ), - .CLR(v_f_to_TV_0$CLR), - .D_OUT(v_f_to_TV_0$D_OUT), - .FULL_N(v_f_to_TV_0$FULL_N), - .EMPTY_N(v_f_to_TV_0$EMPTY_N)); - - // submodule v_f_to_TV_1 - FIFO2 #(.width(32'd320), .guarded(32'd1)) v_f_to_TV_1(.RST(RST_N), - .CLK(CLK), - .D_IN(v_f_to_TV_1$D_IN), - .ENQ(v_f_to_TV_1$ENQ), - .DEQ(v_f_to_TV_1$DEQ), - .CLR(v_f_to_TV_1$CLR), - .D_OUT(v_f_to_TV_1$D_OUT), - .FULL_N(v_f_to_TV_1$FULL_N), - .EMPTY_N(v_f_to_TV_1$EMPTY_N)); - // rule RL_rl_outOfReset assign CAN_FIRE_RL_rl_outOfReset = !outOfReset ; assign WILL_FIRE_RL_rl_outOfReset = CAN_FIRE_RL_rl_outOfReset ; @@ -9881,7 +9746,7 @@ module mkCore(CLK, // rule RL_readyToFetch assign CAN_FIRE_RL_readyToFetch = fetchStage$RDY_done_flushing && - rg_core_run_state_read__3228_EQ_2_3229_AND_NOT_ETC___d15576 && + rg_core_run_state_read__3224_EQ_2_3225_AND_NOT_ETC___d15421 && !flush_brpred && fetchStage$iMemIfc_flush_done && fetchStage$flush_predictors_done ; @@ -9952,10 +9817,6 @@ module mkCore(CLK, f_run_halt_rsps$FULL_N && rg_core_run_state == 2'd0 ; assign WILL_FIRE_RL_rl_debug_halted = CAN_FIRE_RL_rl_debug_halted ; - // rule RL_rl_debug_resume - assign CAN_FIRE_RL_rl_debug_resume = MUX_started$write_1__SEL_1 ; - assign WILL_FIRE_RL_rl_debug_resume = MUX_started$write_1__SEL_1 ; - // rule RL_rl_debug_run_redundant assign CAN_FIRE_RL_rl_debug_run_redundant = f_run_halt_reqs$EMPTY_N && f_run_halt_rsps$FULL_N && @@ -9982,7 +9843,7 @@ module mkCore(CLK, // rule RL_rl_debug_csr_write assign CAN_FIRE_RL_rl_debug_csr_write = f_csr_reqs$EMPTY_N && - f_csr_rsps_i_notFull__5637_AND_f_csr_reqs_firs_ETC___d15732 && + f_csr_rsps_i_notFull__5482_AND_f_csr_reqs_firs_ETC___d15577 && rg_core_run_state == 2'd1 && f_csr_reqs$D_OUT[76] ; assign WILL_FIRE_RL_rl_debug_csr_write = CAN_FIRE_RL_rl_debug_csr_write ; @@ -10297,7 +10158,7 @@ module mkCore(CLK, (!fetchStage$pipelines_0_canDeq || epochManager$checkEpoch_0_check || fetchStage$RDY_pipelines_0_deq) && - NOT_fetchStage_pipelines_1_canDeq__2940_2941_O_ETC___d12949 && + NOT_fetchStage_pipelines_1_canDeq__2937_2938_O_ETC___d12946 && !epochManager$checkEpoch_0_check ; assign WILL_FIRE_RL_renameStage_doRenaming_wrongPath = CAN_FIRE_RL_renameStage_doRenaming_wrongPath ; @@ -10305,7 +10166,6 @@ module mkCore(CLK, // rule RL_commitStage_doCommitTrap_flush assign CAN_FIRE_RL_commitStage_doCommitTrap_flush = rob$RDY_deqPort_0_deq_data && rob$RDY_deqPort_0_deq && - v_f_to_TV_0$FULL_N && (rob$deqPort_0_deq_data[12] || epochManager$RDY_incrementEpoch) && !commitStage_rg_run_state && @@ -10317,13 +10177,13 @@ module mkCore(CLK, !WILL_FIRE_RL_renameStage_doRenaming_SystemInst && !WILL_FIRE_RL_renameStage_doRenaming_Trap && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F && + !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && - !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple && !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && @@ -10341,16 +10201,16 @@ module mkCore(CLK, // rule RL_commitStage_doCommitTrap_handle assign CAN_FIRE_RL_commitStage_doCommitTrap_handle = - NOT_commitStage_commitTrap_4555_BIT_4_4779_478_ETC___d14821 && - commitStage_commitTrap_4555_BIT_4_4779_AND_com_ETC___d14845 && + NOT_commitStage_commitTrap_4549_BIT_4_4679_468_ETC___d14721 && + commitStage_commitTrap_4549_BIT_4_4679_AND_com_ETC___d14745 && !commitStage_rg_run_state && commitStage_commitTrap[133] ; assign WILL_FIRE_RL_commitStage_doCommitTrap_handle = CAN_FIRE_RL_commitStage_doCommitTrap_handle && !WILL_FIRE_RL_renameStage_doRenaming_SystemInst && !WILL_FIRE_RL_renameStage_doRenaming_Trap && - !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && + !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && !WILL_FIRE_RL_prepareCachesAndTlbs ; // rule RL_commitStage_doCommitKilledLd @@ -10367,13 +10227,13 @@ module mkCore(CLK, !WILL_FIRE_RL_renameStage_doRenaming_SystemInst && !WILL_FIRE_RL_renameStage_doRenaming_Trap && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F && + !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && - !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple && !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && @@ -10391,9 +10251,8 @@ module mkCore(CLK, // rule RL_commitStage_doCommitSystemInst assign CAN_FIRE_RL_commitStage_doCommitSystemInst = - coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty && - rob_RDY_deqPort_0_deq_data__4544_AND_rob_RDY_d_ETC___d15004 && - NOT_commitStage_rg_run_state_4553_4554_AND_NOT_ETC___d15010 && + coreFix_memExe_stb_isEmpty__011_AND_coreFix_me_ETC___d14946 && + NOT_commitStage_rg_run_state_4547_4548_AND_NOT_ETC___d14951 && (rob$deqPort_0_deq_data[186:182] == 5'd0 || rob$deqPort_0_deq_data[186:182] == 5'd21 || rob$deqPort_0_deq_data[186:182] == 5'd17 || @@ -10407,8 +10266,8 @@ module mkCore(CLK, CAN_FIRE_RL_commitStage_doCommitSystemInst && !WILL_FIRE_RL_renameStage_doRenaming_SystemInst && !WILL_FIRE_RL_renameStage_doRenaming_Trap && - !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && + !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && !WILL_FIRE_RL_rl_debug_csr_write && !WILL_FIRE_RL_prepareCachesAndTlbs ; @@ -10435,8 +10294,8 @@ module mkCore(CLK, // rule RL_commitStage_doCommitNormalInst assign CAN_FIRE_RL_commitStage_doCommitNormalInst = rob$RDY_deqPort_0_deq_data && - NOT_rob_deqPort_0_canDeq__5214_5215_OR_rob_RDY_ETC___d15256 && - NOT_commitStage_rg_run_state_4553_4554_AND_NOT_ETC___d15010 && + NOT_rob_deqPort_0_canDeq__5156_5157_OR_rob_RDY_ETC___d15195 && + NOT_commitStage_rg_run_state_4547_4548_AND_NOT_ETC___d14951 && rob$deqPort_0_deq_data[186:182] != 5'd0 && rob$deqPort_0_deq_data[186:182] != 5'd21 && rob$deqPort_0_deq_data[186:182] != 5'd17 && @@ -10463,11 +10322,10 @@ module mkCore(CLK, coreFix_trainBPQ_1$FULL_N ; assign WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T = CAN_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && - !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple && !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && @@ -10494,10 +10352,12 @@ module mkCore(CLK, coreFix_trainBPQ_0$FULL_N ; assign WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T = CAN_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && + !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F && + !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple && !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && @@ -10518,7 +10378,7 @@ module mkCore(CLK, assign CAN_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F = !coreFix_aluExe_0_exeToFinQ$first[17] && coreFix_aluExe_0_exeToFinQ$RDY_deq && - coreFix_aluExe_0_exeToFinQ_RDY_first__2817_AND_ETC___d12857 ; + coreFix_aluExe_0_exeToFinQ_RDY_first__2814_AND_ETC___d12854 ; assign WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F = CAN_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; @@ -10527,10 +10387,9 @@ module mkCore(CLK, assign CAN_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F = !coreFix_aluExe_1_exeToFinQ$first[17] && coreFix_aluExe_1_exeToFinQ$RDY_deq && - coreFix_aluExe_1_exeToFinQ_RDY_first__2143_AND_ETC___d12184 ; + coreFix_aluExe_1_exeToFinQ_RDY_first__2140_AND_ETC___d12181 ; assign WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F = - CAN_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F && - !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ; + CAN_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F ; // rule RL_coreFix_aluExe_1_doExeAlu assign CAN_FIRE_RL_coreFix_aluExe_1_doExeAlu = @@ -10541,8 +10400,8 @@ module mkCore(CLK, CAN_FIRE_RL_coreFix_aluExe_1_doExeAlu && !WILL_FIRE_RL_commitStage_doCommitKilledLd && !WILL_FIRE_RL_commitStage_doCommitTrap_flush && - !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && - !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ; + !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && + !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; // rule RL_coreFix_aluExe_0_doExeAlu assign CAN_FIRE_RL_coreFix_aluExe_0_doExeAlu = @@ -10553,8 +10412,8 @@ module mkCore(CLK, CAN_FIRE_RL_coreFix_aluExe_0_doExeAlu && !WILL_FIRE_RL_commitStage_doCommitKilledLd && !WILL_FIRE_RL_commitStage_doCommitTrap_flush && - !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && - !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ; + !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && + !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; // rule RL_coreFix_aluExe_1_doRegReadAlu assign CAN_FIRE_RL_coreFix_aluExe_1_doRegReadAlu = @@ -10565,20 +10424,20 @@ module mkCore(CLK, CAN_FIRE_RL_coreFix_aluExe_1_doRegReadAlu && !WILL_FIRE_RL_commitStage_doCommitKilledLd && !WILL_FIRE_RL_commitStage_doCommitTrap_flush && - !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && - !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ; + !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && + !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; // rule RL_coreFix_aluExe_0_doRegReadAlu assign CAN_FIRE_RL_coreFix_aluExe_0_doRegReadAlu = coreFix_aluExe_0_dispToRegQ$RDY_deq && coreFix_aluExe_0_regToExeQ$RDY_enq && - coreFix_aluExe_0_dispToRegQ_RDY_first__2350_AN_ETC___d12441 ; + coreFix_aluExe_0_dispToRegQ_RDY_first__2347_AN_ETC___d12438 ; assign WILL_FIRE_RL_coreFix_aluExe_0_doRegReadAlu = CAN_FIRE_RL_coreFix_aluExe_0_doRegReadAlu && !WILL_FIRE_RL_commitStage_doCommitKilledLd && !WILL_FIRE_RL_commitStage_doCommitTrap_flush && - !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && - !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ; + !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && + !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; // rule RL_coreFix_aluExe_0_doDispatchAlu assign CAN_FIRE_RL_coreFix_aluExe_0_doDispatchAlu = @@ -10589,8 +10448,8 @@ module mkCore(CLK, CAN_FIRE_RL_coreFix_aluExe_0_doDispatchAlu && !WILL_FIRE_RL_commitStage_doCommitKilledLd && !WILL_FIRE_RL_commitStage_doCommitTrap_flush && - !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && - !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ; + !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && + !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; // rule RL_coreFix_aluExe_1_doDispatchAlu assign CAN_FIRE_RL_coreFix_aluExe_1_doDispatchAlu = @@ -10601,8 +10460,8 @@ module mkCore(CLK, CAN_FIRE_RL_coreFix_aluExe_1_doDispatchAlu && !WILL_FIRE_RL_commitStage_doCommitKilledLd && !WILL_FIRE_RL_commitStage_doCommitTrap_flush && - !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && - !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ; + !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && + !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; // rule RL_coreFix_fpuMulDivExe_0_doFinishFpSimple assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple = @@ -10626,6 +10485,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_divQ_RDY_first__ETC___d5368 ; assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv = CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple ; @@ -10636,6 +10496,7 @@ module mkCore(CLK, assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt = CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple ; @@ -10645,8 +10506,6 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_mulDivExec_mulQ_RDY_fir_ETC___d8152 ; assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul = CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple ; @@ -10662,9 +10521,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$EMPTY_N ; assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv = CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple ; @@ -10750,8 +10609,8 @@ module mkCore(CLK, CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue && !WILL_FIRE_RL_commitStage_doCommitKilledLd && !WILL_FIRE_RL_commitStage_doCommitTrap_flush && - !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && + !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue ; @@ -10769,8 +10628,8 @@ module mkCore(CLK, CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue && !WILL_FIRE_RL_commitStage_doCommitKilledLd && !WILL_FIRE_RL_commitStage_doCommitTrap_flush && - !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && + !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue ; @@ -10819,8 +10678,8 @@ module mkCore(CLK, CAN_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && !WILL_FIRE_RL_commitStage_doCommitKilledLd && !WILL_FIRE_RL_commitStage_doCommitTrap_flush && - !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && + !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && !WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ; @@ -10834,8 +10693,8 @@ module mkCore(CLK, CAN_FIRE_RL_coreFix_memExe_doDeqStQ_fault && !WILL_FIRE_RL_commitStage_doCommitKilledLd && !WILL_FIRE_RL_commitStage_doCommitTrap_flush && - !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && + !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && !WILL_FIRE_RL_coreFix_memExe_doFinishMem && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && @@ -10855,8 +10714,8 @@ module mkCore(CLK, CAN_FIRE_RL_coreFix_memExe_doDeqStQ_Fence && !WILL_FIRE_RL_commitStage_doCommitKilledLd && !WILL_FIRE_RL_commitStage_doCommitTrap_flush && - !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && + !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && !WILL_FIRE_RL_coreFix_memExe_doFinishMem && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && @@ -10864,29 +10723,6 @@ module mkCore(CLK, !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ; - // rule RL_coreFix_memExe_doDeqStQ_ScAmo_deq - assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq = - !coreFix_memExe_respLrScAmoQ_empty && - rob$RDY_setExecuted_deqLSQ && - coreFix_memExe_lsq$RDY_deqSt && - coreFix_memExe_lsq$RDY_firstSt && - coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd2 ; - assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq = - CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && - !WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence && - !WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && - !WILL_FIRE_RL_commitStage_doCommitKilledLd && - !WILL_FIRE_RL_commitStage_doCommitTrap_flush && - !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && - !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && - !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && - !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && - !WILL_FIRE_RL_coreFix_memExe_doFinishMem && - !WILL_FIRE_RL_coreFix_memExe_doRespLdForward && - !WILL_FIRE_RL_coreFix_memExe_doRespLdMem && - !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem && - !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ; - // rule RL_coreFix_memExe_doDeqStQ_MMIO_deq assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq = !mmio_dataRespQ_empty && @@ -10902,8 +10738,31 @@ module mkCore(CLK, !WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && !WILL_FIRE_RL_commitStage_doCommitKilledLd && !WILL_FIRE_RL_commitStage_doCommitTrap_flush && - !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && + !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && + !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && + !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && + !WILL_FIRE_RL_coreFix_memExe_doFinishMem && + !WILL_FIRE_RL_coreFix_memExe_doRespLdForward && + !WILL_FIRE_RL_coreFix_memExe_doRespLdMem && + !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem && + !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ; + + // rule RL_coreFix_memExe_doDeqStQ_ScAmo_deq + assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq = + !coreFix_memExe_respLrScAmoQ_empty && + rob$RDY_setExecuted_deqLSQ && + coreFix_memExe_lsq$RDY_deqSt && + coreFix_memExe_lsq$RDY_firstSt && + coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd2 ; + assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq = + CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + !WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence && + !WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && + !WILL_FIRE_RL_commitStage_doCommitKilledLd && + !WILL_FIRE_RL_commitStage_doCommitTrap_flush && + !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && + !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && !WILL_FIRE_RL_coreFix_memExe_doFinishMem && @@ -10927,8 +10786,8 @@ module mkCore(CLK, !WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && !WILL_FIRE_RL_commitStage_doCommitKilledLd && !WILL_FIRE_RL_commitStage_doCommitTrap_flush && - !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && + !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && !WILL_FIRE_RL_coreFix_memExe_doFinishMem && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ; @@ -11029,8 +10888,8 @@ module mkCore(CLK, !WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && !WILL_FIRE_RL_commitStage_doCommitKilledLd && !WILL_FIRE_RL_commitStage_doCommitTrap_flush && - !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && - !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ; + !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && + !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; // rule RL_coreFix_memExe_doRespLdMem assign CAN_FIRE_RL_coreFix_memExe_doRespLdMem = @@ -11083,6 +10942,19 @@ module mkCore(CLK, assign WILL_FIRE_RL_prepareCachesAndTlbs = CAN_FIRE_RL_prepareCachesAndTlbs ; + // rule RL_rl_debug_resume + assign CAN_FIRE_RL_rl_debug_resume = + commitStage_rg_run_state && coreFix_memExe_dTlb$RDY_flush && + fetchStage$RDY_iTlbIfc_flush && + f_run_halt_reqs$EMPTY_N && + f_run_halt_rsps$FULL_N && + rg_core_run_state == 2'd1 && + f_run_halt_reqs$D_OUT && + !f_gpr_reqs$EMPTY_N && + !f_fpr_reqs$EMPTY_N && + !f_csr_reqs$EMPTY_N ; + assign WILL_FIRE_RL_rl_debug_resume = MUX_started$write_1__SEL_1 ; + // rule RL_coreFix_memExe_doRegReadMem assign CAN_FIRE_RL_coreFix_memExe_doRegReadMem = coreFix_memExe_dispToRegQ$RDY_deq && @@ -11091,8 +10963,8 @@ module mkCore(CLK, CAN_FIRE_RL_coreFix_memExe_doRegReadMem && !WILL_FIRE_RL_commitStage_doCommitKilledLd && !WILL_FIRE_RL_commitStage_doCommitTrap_flush && - !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && - !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ; + !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && + !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; // rule RL_coreFix_memExe_doDispatchMem assign CAN_FIRE_RL_coreFix_memExe_doDispatchMem = @@ -11103,15 +10975,15 @@ module mkCore(CLK, CAN_FIRE_RL_coreFix_memExe_doDispatchMem && !WILL_FIRE_RL_commitStage_doCommitKilledLd && !WILL_FIRE_RL_commitStage_doCommitTrap_flush && - !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && - !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ; + !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && + !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; // rule RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer = !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty && coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_send && coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_getEmptyEntryInit && - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q269 ; + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q259 ; assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer = CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer ; @@ -11142,7 +11014,7 @@ module mkCore(CLK, assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer = !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty && coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_send && - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q270 ; + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q260 ; assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer = CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer ; @@ -11212,16 +11084,16 @@ module mkCore(CLK, assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_canon = 1'd1 ; + // rule RL_coreFix_memExe_respLrScAmoQ_canonicalize + assign CAN_FIRE_RL_coreFix_memExe_respLrScAmoQ_canonicalize = 1'd1 ; + assign WILL_FIRE_RL_coreFix_memExe_respLrScAmoQ_canonicalize = 1'd1 ; + // rule RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_canon assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_canon = 1'd1 ; assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_canon = 1'd1 ; - // rule RL_coreFix_memExe_respLrScAmoQ_canonicalize - assign CAN_FIRE_RL_coreFix_memExe_respLrScAmoQ_canonicalize = 1'd1 ; - assign WILL_FIRE_RL_coreFix_memExe_respLrScAmoQ_canonicalize = 1'd1 ; - // rule RL_coreFix_memExe_respLrScAmoQ_clearReq_canon assign CAN_FIRE_RL_coreFix_memExe_respLrScAmoQ_clearReq_canon = 1'd1 ; assign WILL_FIRE_RL_coreFix_memExe_respLrScAmoQ_clearReq_canon = 1'd1 ; @@ -11234,6 +11106,10 @@ module mkCore(CLK, assign CAN_FIRE_RL_coreFix_memExe_respLrScAmoQ_enqReq_canon = 1'd1 ; assign WILL_FIRE_RL_coreFix_memExe_respLrScAmoQ_enqReq_canon = 1'd1 ; + // rule RL_coreFix_memExe_forwardQ_canonicalize + assign CAN_FIRE_RL_coreFix_memExe_forwardQ_canonicalize = 1'd1 ; + assign WILL_FIRE_RL_coreFix_memExe_forwardQ_canonicalize = 1'd1 ; + // rule RL_coreFix_memExe_memRespLdQ_canonicalize assign CAN_FIRE_RL_coreFix_memExe_memRespLdQ_canonicalize = 1'd1 ; assign WILL_FIRE_RL_coreFix_memExe_memRespLdQ_canonicalize = 1'd1 ; @@ -11250,10 +11126,6 @@ module mkCore(CLK, assign CAN_FIRE_RL_coreFix_memExe_memRespLdQ_enqReq_canon = 1'd1 ; assign WILL_FIRE_RL_coreFix_memExe_memRespLdQ_enqReq_canon = 1'd1 ; - // rule RL_coreFix_memExe_forwardQ_canonicalize - assign CAN_FIRE_RL_coreFix_memExe_forwardQ_canonicalize = 1'd1 ; - assign WILL_FIRE_RL_coreFix_memExe_forwardQ_canonicalize = 1'd1 ; - // rule RL_coreFix_memExe_forwardQ_clearReq_canon assign CAN_FIRE_RL_coreFix_memExe_forwardQ_clearReq_canon = 1'd1 ; assign WILL_FIRE_RL_coreFix_memExe_forwardQ_clearReq_canon = 1'd1 ; @@ -11270,14 +11142,14 @@ module mkCore(CLK, assign CAN_FIRE_RL_coreFix_memExe_reqStQ_full_canon = 1'd1 ; assign WILL_FIRE_RL_coreFix_memExe_reqStQ_full_canon = 1'd1 ; - // rule RL_coreFix_memExe_reqLrScAmoQ_empty_canon - assign CAN_FIRE_RL_coreFix_memExe_reqLrScAmoQ_empty_canon = 1'd1 ; - assign WILL_FIRE_RL_coreFix_memExe_reqLrScAmoQ_empty_canon = 1'd1 ; - // rule RL_coreFix_memExe_reqStQ_empty_canon assign CAN_FIRE_RL_coreFix_memExe_reqStQ_empty_canon = 1'd1 ; assign WILL_FIRE_RL_coreFix_memExe_reqStQ_empty_canon = 1'd1 ; + // rule RL_coreFix_memExe_reqLrScAmoQ_data_0_canon + assign CAN_FIRE_RL_coreFix_memExe_reqLrScAmoQ_data_0_canon = 1'd1 ; + assign WILL_FIRE_RL_coreFix_memExe_reqLrScAmoQ_data_0_canon = 1'd1 ; + // rule RL_coreFix_memExe_reqStQ_data_0_canon assign CAN_FIRE_RL_coreFix_memExe_reqStQ_data_0_canon = 1'd1 ; assign WILL_FIRE_RL_coreFix_memExe_reqStQ_data_0_canon = 1'd1 ; @@ -11286,9 +11158,9 @@ module mkCore(CLK, assign CAN_FIRE_RL_coreFix_memExe_reqLrScAmoQ_full_canon = 1'd1 ; assign WILL_FIRE_RL_coreFix_memExe_reqLrScAmoQ_full_canon = 1'd1 ; - // rule RL_coreFix_memExe_reqLrScAmoQ_data_0_canon - assign CAN_FIRE_RL_coreFix_memExe_reqLrScAmoQ_data_0_canon = 1'd1 ; - assign WILL_FIRE_RL_coreFix_memExe_reqLrScAmoQ_data_0_canon = 1'd1 ; + // rule RL_coreFix_memExe_reqLrScAmoQ_empty_canon + assign CAN_FIRE_RL_coreFix_memExe_reqLrScAmoQ_empty_canon = 1'd1 ; + assign WILL_FIRE_RL_coreFix_memExe_reqLrScAmoQ_empty_canon = 1'd1 ; // rule RL_coreFix_memExe_reqLdQ_full_canon assign CAN_FIRE_RL_coreFix_memExe_reqLdQ_full_canon = 1'd1 ; @@ -11311,8 +11183,8 @@ module mkCore(CLK, CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && !WILL_FIRE_RL_commitStage_doCommitKilledLd && !WILL_FIRE_RL_commitStage_doCommitTrap_flush && - !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && - !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ; + !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && + !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; // rule RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv = @@ -11323,8 +11195,8 @@ module mkCore(CLK, CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv && !WILL_FIRE_RL_commitStage_doCommitKilledLd && !WILL_FIRE_RL_commitStage_doCommitTrap_flush && - !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && - !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ; + !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && + !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; // rule RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv = @@ -11335,8 +11207,8 @@ module mkCore(CLK, CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv && !WILL_FIRE_RL_commitStage_doCommitKilledLd && !WILL_FIRE_RL_commitStage_doCommitTrap_flush && - !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && - !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ; + !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && + !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; // rule RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_doInit assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_doInit = @@ -11377,25 +11249,25 @@ module mkCore(CLK, epochManager$RDY_incrementEpoch && rob$RDY_enqPort_0_enq && fetchStage$RDY_pipelines_0_first && fetchStage$RDY_pipelines_0_deq && - mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13225 && + mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13221 && rob$isEmpty && rg_core_run_state == 2'd2 ; assign WILL_FIRE_RL_renameStage_doRenaming_Trap = CAN_FIRE_RL_renameStage_doRenaming_Trap && - !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && + !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && !WILL_FIRE_RL_rl_debug_halt_req ; // rule RL_renameStage_doRenaming_SystemInst assign CAN_FIRE_RL_renameStage_doRenaming_SystemInst = epochManager$RDY_incrementEpoch && - rob_RDY_enqPort_0_enq__2956_AND_regRenamingTab_ETC___d13477 && - mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13531 && + rob_RDY_enqPort_0_enq__2953_AND_regRenamingTab_ETC___d13473 && + mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13527 && rg_core_run_state == 2'd2 ; assign WILL_FIRE_RL_renameStage_doRenaming_SystemInst = CAN_FIRE_RL_renameStage_doRenaming_SystemInst && - !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && + !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && !WILL_FIRE_RL_rl_debug_halt_req ; // rule RL_csrInstOrInterruptInflight_canon @@ -11432,15 +11304,15 @@ module mkCore(CLK, // rule RL_renameStage_doRenaming assign CAN_FIRE_RL_renameStage_doRenaming = (!fetchStage$pipelines_0_canDeq || - IF_fetchStage_RDY_pipelines_0_first__2931_AND__ETC___d13610) && - IF_NOT_fetchStage_pipelines_0_canDeq__2932_293_ETC___d14073 && - IF_NOT_fetchStage_pipelines_0_canDeq__2932_293_ETC___d14081 && - NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d14255 && - mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14259 ; + IF_fetchStage_RDY_pipelines_0_first__2928_AND__ETC___d13606) && + IF_NOT_fetchStage_pipelines_0_canDeq__2929_293_ETC___d14069 && + IF_NOT_fetchStage_pipelines_0_canDeq__2929_293_ETC___d14077 && + NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d14251 && + mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14255 ; assign WILL_FIRE_RL_renameStage_doRenaming = CAN_FIRE_RL_renameStage_doRenaming && - !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && + !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && !WILL_FIRE_RL_rl_debug_halt_req ; // rule RL_mmio_pRqQ_canonicalize @@ -11475,7 +11347,7 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_fpr_read ; assign MUX_commitStage_rg_run_state$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap_4555_BIT_4_4779_AND_com_ETC___d14844 ; + commitStage_commitTrap_4549_BIT_4_4679_AND_com_ETC___d14744 ; assign MUX_commitStage_setLSQAtCommit_0$wset_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitNormalInst && rob$deqPort_0_canDeq && @@ -11597,6 +11469,8 @@ module mkCore(CLK, WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] && NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqMsh_ETC___d2730 ; + assign MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1 = + WILL_FIRE_RL_prepareCachesAndTlbs && update_vm_info ; assign MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__SEL_1 = WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && coreFix_memExe_lsq$issueLd[74:73] != 2'd0 && @@ -11662,20 +11536,12 @@ module mkCore(CLK, WILL_FIRE_RL_commitStage_doCommitTrap_handle && (commitStage_commitTrap[4] || commitStage_commitTrap[3:0] == 4'd3) ; - assign MUX_csrf_debug_int_pend$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == - 6'd29 ; - assign MUX_csrf_debug_int_pend$write_1__SEL_2 = - WILL_FIRE_RL_rl_debug_csr_write && - f_csr_reqs$D_OUT[75:64] == 12'd836 ; assign MUX_csrf_external_int_en_vec_0$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + (IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd9 || - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd22) ; assign MUX_csrf_external_int_en_vec_3$write_1__SEL_1 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11683,23 +11549,31 @@ module mkCore(CLK, assign MUX_csrf_external_int_pend_vec_0$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + (IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd16 || - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd29) ; assign MUX_csrf_external_int_pend_vec_0$write_1__SEL_2 = WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd324 || f_csr_reqs$D_OUT[75:64] == 12'd836) ; + assign MUX_csrf_external_int_pend_vec_3$write_1__SEL_1 = + WILL_FIRE_RL_commitStage_doCommitSystemInst && + rob$deqPort_0_deq_data[186:182] == 5'd13 && + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == + 6'd29 ; + assign MUX_csrf_external_int_pend_vec_3$write_1__SEL_2 = + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd836 ; assign MUX_csrf_fflags_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitNormalInst && - NOT_IF_NOT_rob_deqPort_0_canDeq__5214_5215_OR__ETC___d15527 ; + NOT_IF_NOT_rob_deqPort_0_canDeq__5156_5157_OR__ETC___d15372 ; assign MUX_csrf_fflags_reg$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + (IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd0 || - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd2) ; assign MUX_csrf_fflags_reg$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11708,22 +11582,22 @@ module mkCore(CLK, assign MUX_csrf_frm_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + (IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd1 || - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd2) ; assign MUX_csrf_fs_reg$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + (IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd0 || - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd1 || - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd2 || - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd8 || - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd18) ; assign MUX_csrf_fs_reg$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11735,33 +11609,33 @@ module mkCore(CLK, assign MUX_csrf_ie_vec_0$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + (IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd8 || - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd18) ; assign MUX_csrf_ie_vec_0$write_1__SEL_2 = WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd256 || f_csr_reqs$D_OUT[75:64] == 12'd768) ; assign MUX_csrf_ie_vec_1$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo30 ; + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 ; assign MUX_csrf_ie_vec_1$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4555_BIT_4_4779_478_ETC___d14881 && - csrf_prv_reg_read__2964_ULE_1_4882_AND_IF_comm_ETC___d14904 ; + NOT_commitStage_commitTrap_4549_BIT_4_4679_468_ETC___d14781 && + csrf_prv_reg_read__2961_ULE_1_4782_AND_IF_comm_ETC___d14804 ; assign MUX_csrf_ie_vec_3$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo24 ; + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; assign MUX_csrf_ie_vec_3$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4555_BIT_4_4779_478_ETC___d14881 && - NOT_csrf_prv_reg_read__2964_ULE_1_4882_4923_OR_ETC___d14927 ; + NOT_commitStage_commitTrap_4549_BIT_4_4679_468_ETC___d14781 && + NOT_csrf_prv_reg_read__2961_ULE_1_4782_4823_OR_ETC___d14827 ; assign MUX_csrf_ie_vec_3$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd768 ; assign MUX_csrf_mcause_code_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd27 ; assign MUX_csrf_mcause_code_reg$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11775,7 +11649,7 @@ module mkCore(CLK, assign MUX_csrf_mcycle_ehr_data_dummy2_0$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd30 ; assign MUX_csrf_medeleg_13_11_reg$write_1__SEL_1 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11783,7 +11657,7 @@ module mkCore(CLK, assign MUX_csrf_mepc_csr$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd26 ; assign MUX_csrf_mepc_csr$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11797,17 +11671,17 @@ module mkCore(CLK, assign MUX_csrf_minstret_ehr_data_dummy2_0$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd31 ; assign MUX_csrf_mpp_reg$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo24 ; + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; assign MUX_csrf_mscratch_csr$write_1__SEL_1 = WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd832 ; assign MUX_csrf_mtval_csr$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd28 ; assign MUX_csrf_mtval_csr$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11819,21 +11693,26 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd384 ; assign MUX_csrf_prev_ie_vec_1$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo30 ; + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 ; assign MUX_csrf_prev_ie_vec_3$write_1__SEL_1 = + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; + assign MUX_csrf_prv_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo24 ; + assign MUX_csrf_prv_reg$write_1__SEL_2 = + WILL_FIRE_RL_commitStage_doCommitTrap_handle && + NOT_commitStage_commitTrap_4549_BIT_4_4679_468_ETC___d14781 ; + assign MUX_csrf_prv_reg$write_1__SEL_3 = + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd1968 ; assign MUX_csrf_rg_dcsr$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd36 ; - assign MUX_csrf_rg_dcsr$write_1__SEL_3 = - WILL_FIRE_RL_rl_debug_csr_write && - f_csr_reqs$D_OUT[75:64] == 12'd1968 ; assign MUX_csrf_rg_dpc$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd37 ; assign MUX_csrf_rg_dpc$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11847,7 +11726,7 @@ module mkCore(CLK, assign MUX_csrf_scause_code_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd14 ; assign MUX_csrf_scause_code_reg$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11858,7 +11737,7 @@ module mkCore(CLK, assign MUX_csrf_sepc_csr$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd13 ; assign MUX_csrf_sepc_csr$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11868,7 +11747,7 @@ module mkCore(CLK, mmio_pRqQ_data_0[37:36] != 2'd0 && mmio_pRqQ_data_0[37:36] != 2'd1 ; assign MUX_csrf_spp_reg$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo30 ; + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 ; assign MUX_csrf_sscratch_csr$write_1__SEL_1 = WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd320 ; @@ -11878,7 +11757,7 @@ module mkCore(CLK, assign MUX_csrf_stval_csr$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd15 ; assign MUX_csrf_stval_csr$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11889,16 +11768,13 @@ module mkCore(CLK, assign MUX_epochManager$updatePrevEpoch_0_update_1__SEL_2 = WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2934_BITS_19_ETC___d14262 && - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d13663 ; + NOT_fetchStage_pipelines_0_first__2931_BITS_19_ETC___d14258 && + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d13659 ; assign MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2 = WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d14388 && - NOT_fetchStage_pipelines_1_first__2943_BITS_19_ETC___d14399 && - IF_fetchStage_pipelines_1_first__2943_BITS_194_ETC___d14067 ; - assign MUX_fetchStage$redirect_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4555_BIT_4_4779_478_ETC___d14881 ; + NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d14384 && + NOT_fetchStage_pipelines_1_first__2940_BITS_19_ETC___d14395 && + IF_fetchStage_pipelines_1_first__2940_BITS_194_ETC___d14063 ; assign MUX_flush_reservation$write_1__SEL_2 = WILL_FIRE_RL_prepareCachesAndTlbs && flush_reservation ; assign MUX_flush_tlbs$write_1__SEL_1 = @@ -11911,7 +11787,7 @@ module mkCore(CLK, csrf_rg_dcsr[2] ; assign MUX_renameStage_rg_m_halt_req$write_1__SEL_2 = WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d14388 && + NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d14384 && csrf_rg_dcsr[2] ; assign MUX_rf$write_3_wr_1__PSEL_1 = WILL_FIRE_RL_coreFix_memExe_doRespLdForward || @@ -11953,18 +11829,8 @@ module mkCore(CLK, MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 && coreFix_memExe_lsq$firstLd[89] ; assign MUX_started$write_1__SEL_1 = - commitStage_rg_run_state && f_run_halt_reqs$EMPTY_N && - f_run_halt_rsps$FULL_N && - rg_core_run_state == 2'd1 && - f_run_halt_reqs$D_OUT && - !f_gpr_reqs$EMPTY_N && - !f_fpr_reqs$EMPTY_N && - !f_csr_reqs$EMPTY_N ; - assign MUX_update_vm_info$write_1__SEL_2 = - WILL_FIRE_RL_prepareCachesAndTlbs && update_vm_info ; - assign MUX_v_f_to_TV_0$enq_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitNormalInst && - rob$deqPort_0_canDeq ; + CAN_FIRE_RL_rl_debug_resume && + !WILL_FIRE_RL_prepareCachesAndTlbs ; assign MUX_regRenamingTable$rename_0_getRename_1__VAL_2 = { 2'd2, f_gpr_reqs$D_OUT[68:64], 20'd345386 } ; assign MUX_regRenamingTable$rename_0_getRename_1__VAL_3 = @@ -11972,19 +11838,22 @@ module mkCore(CLK, assign MUX_commitStage_commitTrap$write_1__VAL_2 = { 1'd1, rob$deqPort_0_deq_data[282:219], - x__h701106, - rob_deqPort_0_deq_data__4547_BIT_166_4563_CONC_ETC___d14612 } ; + x__h700768, + rob$deqPort_0_deq_data[166], + rob$deqPort_0_deq_data[166] ? + CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q261 : + CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q262 } ; assign MUX_commitStage_rg_serialnum$write_1__VAL_1 = commitStage_rg_serialnum + 64'd1 ; assign MUX_commitStage_rg_serialnum$write_1__VAL_2 = - commitStage_rg_serialnum + y__h723907 ; + commitStage_rg_serialnum + y__h720039 ; assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_1 = - (k__h671729 == 1'd0 && - fetchStage_pipelines_0_canDeq__2932_AND_NOT_fe_ETC___d14265) ? + (k__h671393 == 1'd0 && + fetchStage_pipelines_0_canDeq__2929_AND_NOT_fe_ETC___d14261) ? { fetchStage$pipelines_0_first[199:195], - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d13064, + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d13060, fetchStage$pipelines_0_first[173], - IF_fetchStage_pipelines_0_first__2934_BITS_172_ETC___d13146, + IF_fetchStage_pipelines_0_first__2931_BITS_172_ETC___d13142, fetchStage$pipelines_0_first[160:128], fetchStage$pipelines_0_first[255:232], regRenamingTable$rename_0_getRename, @@ -11994,21 +11863,21 @@ module mkCore(CLK, specTagManager$nextSpecTag, sbAggr$eagerLookup_0_get } : { fetchStage$pipelines_1_first[199:195], - IF_fetchStage_pipelines_1_first__2943_BITS_194_ETC___d13758, - fetchStage_pipelines_1_first__2943_BIT_173_375_ETC___d13842, + IF_fetchStage_pipelines_1_first__2940_BITS_194_ETC___d13754, + fetchStage_pipelines_1_first__2940_BIT_173_375_ETC___d13838, fetchStage$pipelines_1_first[160:128], fetchStage$pipelines_1_first[255:232], regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h686832, + renaming_spec_bits__h686496, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_2 = { fetchStage$pipelines_0_first[199:195], - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d13064, + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d13060, fetchStage$pipelines_0_first[173], - IF_fetchStage_pipelines_0_first__2934_BITS_172_ETC___d13146, + IF_fetchStage_pipelines_0_first__2931_BITS_172_ETC___d13142, fetchStage$pipelines_0_first[160:128], fetchStage$pipelines_0_first[255:232], regRenamingTable$rename_0_getRename, @@ -12103,7 +11972,7 @@ module mkCore(CLK, IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2033, (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd0) ? - n__h195271 : + n__h194963 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0] } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_4 = { IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2787, @@ -12117,10 +11986,10 @@ module mkCore(CLK, assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_1 = { 517'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq[147:84], - x__h288079 } ; + x__h287771 } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_2 = { 517'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, - x__h289524, + x__h289216, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_3 = { 518'h1AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, @@ -12128,7 +11997,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_4 = { 2'd2, - addr__h292300, + addr__h291992, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3038 } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_1 = { 1'd1, @@ -12141,12 +12010,12 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_1 = - { x__h155035, x__h155041, 84'h82AAAAAAAAAAAAAAAAAAA } ; + { x__h154726, x__h154732, 84'h82AAAAAAAAAAAAAAAAAAA } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_2 = - { x__h158582, x__h158588, 84'hCAAAAAAAAAAAAAAAAAAAA } ; + { x__h158273, x__h158279, 84'hCAAAAAAAAAAAAAAAAAAAA } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_3 = - { x__h161398, - x__h161402, + { x__h161089, + x__h161093, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1216, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1220, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1224, @@ -12157,7 +12026,7 @@ module mkCore(CLK, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1246, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1250, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1255, - x__h163250, + x__h162941, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1263, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1267, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1271, @@ -12170,13 +12039,19 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_1 = { 1'd1, - resp_addr__h294277, + resp_addr__h293969, 2'd0, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getData } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_2 = { 1'd1, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getRq, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getData } ; + assign MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1 = + { prv__h721574, + prv__h721574 != 2'd3 && csrf_vm_mode_sv39_reg, + csrf_mxr_reg, + csrf_sum_reg, + csrf_ppn_reg } ; assign MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__VAL_1 = { 1'd1, coreFix_memExe_lsq$getIssueLd[76:72], @@ -12250,7 +12125,7 @@ module mkCore(CLK, assign MUX_coreFix_memExe_memRespLdQ_enqReq_lat_0$wset_1__VAL_1 = { 1'd1, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[152:148], - x__h198472 } ; + x__h198164 } ; assign MUX_coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wset_1__VAL_1 = { 5'd0, coreFix_memExe_lsq$firstSt[141:78], @@ -12285,8 +12160,8 @@ module mkCore(CLK, assign MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_3 = { 1'd1, coreFix_memExe_dMem_cache_m_banks_0_processAmo[6] ? - curData__h193733 : - { {32{x__h194496[31]}}, x__h194496 } } ; + curData__h193425 : + { {32{x__h194188[31]}}, x__h194188 } } ; assign MUX_coreFix_trainBPQ_0$enq_1__VAL_1 = { coreFix_aluExe_0_exeToFinQ$first[146:19], coreFix_aluExe_0_exeToFinQ$first[326:322], @@ -12319,23 +12194,23 @@ module mkCore(CLK, MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_1 || MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_2 ; assign MUX_csrf_fflags_reg$write_1__VAL_1 = - csrf_fflags_reg | fflags__h723884 ; + csrf_fflags_reg | fflags__h720016 ; assign MUX_csrf_frm_reg$write_1__VAL_1 = - (IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + (IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd1) ? - robdeqPort_0_deq_data_BITS_95_TO_32__q271[2:0] : - robdeqPort_0_deq_data_BITS_95_TO_32__q271[7:5] ; + robdeqPort_0_deq_data_BITS_95_TO_32__q263[2:0] : + robdeqPort_0_deq_data_BITS_95_TO_32__q263[7:5] ; assign MUX_csrf_frm_reg$write_1__VAL_2 = (f_csr_reqs$D_OUT[75:64] == 12'd2) ? f_csr_reqs$D_OUT[2:0] : f_csr_reqs$D_OUT[7:5] ; - always@(IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 or - robdeqPort_0_deq_data_BITS_95_TO_32__q271) + always@(IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 or + robdeqPort_0_deq_data_BITS_95_TO_32__q263) begin - case (IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989) + case (IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931) 6'd0, 6'd1, 6'd2: MUX_csrf_fs_reg$write_1__VAL_2 = 2'b11; default: MUX_csrf_fs_reg$write_1__VAL_2 = - robdeqPort_0_deq_data_BITS_95_TO_32__q271[14:13]; + robdeqPort_0_deq_data_BITS_95_TO_32__q263[14:13]; endcase end always@(f_csr_reqs$D_OUT) @@ -12347,57 +12222,61 @@ module mkCore(CLK, end assign MUX_csrf_ie_vec_1$write_1__VAL_1 = (rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + (IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd8 || - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd18)) ? - robdeqPort_0_deq_data_BITS_95_TO_32__q271[1] : + robdeqPort_0_deq_data_BITS_95_TO_32__q263[1] : csrf_prev_ie_vec_1 ; assign MUX_csrf_ie_vec_3$write_1__VAL_1 = (rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd18) ? - robdeqPort_0_deq_data_BITS_95_TO_32__q271[3] : + robdeqPort_0_deq_data_BITS_95_TO_32__q263[3] : csrf_prev_ie_vec_3 ; assign MUX_csrf_minstret_ehr_data_lat_0$wset_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ; assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1 = - n__read__h719255 + 64'd1 ; + n__read__h717124 + 64'd1 ; assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2 = - n__read__h719255 + { 62'd0, x__h724126 } ; + n__read__h717124 + { 62'd0, x__h720263 } ; assign MUX_csrf_mpp_reg$write_1__VAL_1 = (rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd18) ? MUX_csrf_minstret_ehr_data_lat_0$wset_1__VAL_2[12:11] : 2'd0 ; assign MUX_csrf_mtval_csr$write_1__VAL_1 = rob$deqPort_0_deq_data[95:32] ; assign MUX_csrf_mtval_csr$write_1__VAL_2 = - commitStage_commitTrap[4] ? 64'd0 : trap_val__h708107 ; + commitStage_commitTrap[4] ? 64'd0 : trap_val__h706787 ; assign MUX_csrf_prev_ie_vec_1$write_1__VAL_1 = rob$deqPort_0_deq_data[186:182] != 5'd13 || - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 != + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 != 6'd8 && - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 != + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 != 6'd18 || MUX_csrf_mtval_csr$write_1__VAL_1[5] ; assign MUX_csrf_prev_ie_vec_3$write_1__VAL_1 = rob$deqPort_0_deq_data[186:182] != 5'd13 || - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 != + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 != 6'd18 || MUX_csrf_mtval_csr$write_1__VAL_1[7] ; assign MUX_csrf_prv_reg$write_1__VAL_1 = - csrf_prv_reg_read__2964_ULE_1_4882_AND_IF_comm_ETC___d14904 ? + (rob$deqPort_0_deq_data[186:182] == 5'd13 && + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == + 6'd36) ? + MUX_csrf_mtval_csr$write_1__VAL_1[1:0] : + ((rob$deqPort_0_deq_data[186:182] == 5'd19) ? + x__h716537 : + csrf_mpp_reg) ; + assign MUX_csrf_prv_reg$write_1__VAL_2 = + csrf_prv_reg_read__2961_ULE_1_4782_AND_IF_comm_ETC___d14804 ? 2'd1 : 2'd3 ; - assign MUX_csrf_prv_reg$write_1__VAL_2 = - (rob$deqPort_0_deq_data[186:182] == 5'd19) ? - x__h718668 : - csrf_mpp_reg ; assign MUX_csrf_rg_dcsr$write_1__VAL_2 = { 32'b0, csrf_rg_dcsr[31:9], - dcsr_cause__h706588, + dcsr_cause__h705268, csrf_rg_dcsr[5:2], csrf_prv_reg } ; assign MUX_csrf_sepc_csr$write_1__VAL_1 = rob$deqPort_0_deq_data[95:32] ; @@ -12407,25 +12286,31 @@ module mkCore(CLK, amoExec___d882[0] ; assign MUX_csrf_spp_reg$write_1__VAL_1 = rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + (IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd8 || - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd18) && MUX_csrf_sepc_csr$write_1__VAL_1[8] ; assign MUX_csrf_stval_csr$write_1__VAL_1 = rob$deqPort_0_deq_data[95:32] ; - assign MUX_f_csr_rsps$enq_1__VAL_3 = { 1'd1, data_out__h727964 } ; + assign MUX_f_csr_rsps$enq_1__VAL_3 = { 1'd1, data_out__h723975 } ; assign MUX_f_fpr_rsps$enq_1__VAL_3 = { 1'd1, rf$read_4_rd1 } ; + assign MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 = + { csrf_prv_reg, + csrf_prv_reg != 2'd3 && csrf_vm_mode_sv39_reg, + csrf_mxr_reg, + csrf_sum_reg, + csrf_ppn_reg } ; assign MUX_fetchStage$redirect_1__VAL_1 = - csrf_prv_reg_read__2964_ULE_1_4882_AND_IF_comm_ETC___d14904 ? - y_avValue__h707954 : - y_avValue__h709723 ; + csrf_prv_reg_read__2961_ULE_1_4782_AND_IF_comm_ETC___d14804 ? + y_avValue__h706634 : + y_avValue__h708403 ; always@(rob$deqPort_0_deq_data or - next_pc__h718537 or csrf_sepc_csr or csrf_mepc_csr) + next_pc__h716406 or csrf_sepc_csr or csrf_mepc_csr) begin case (rob$deqPort_0_deq_data[186:182]) 5'd19: MUX_fetchStage$redirect_1__VAL_6 = csrf_sepc_csr; 5'd20: MUX_fetchStage$redirect_1__VAL_6 = csrf_mepc_csr; - default: MUX_fetchStage$redirect_1__VAL_6 = next_pc__h718537; + default: MUX_fetchStage$redirect_1__VAL_6 = next_pc__h716406; endcase end assign MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_1 = @@ -12437,7 +12322,7 @@ module mkCore(CLK, assign MUX_mmio_cRqQ_enqReq_lat_0$wset_1__VAL_1 = { 1'd1, mmio_dataReqQ_data_0[141:78], - CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q272, + CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q264, mmio_dataReqQ_data_0[71:0] } ; assign MUX_mmio_cRqQ_enqReq_lat_0$wset_1__VAL_2 = { 1'd1, @@ -12460,24 +12345,24 @@ module mkCore(CLK, 56'hAAAAAAAAAAAAAA } ; assign MUX_rf$write_2_wr_2__VAL_2 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[39] ? - res_data__h340172 : - res_data__h340167 ; + res_data__h339863 : + res_data__h339858 ; assign MUX_rf$write_2_wr_2__VAL_3 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[39] ? - res_data__h385874 : - res_data__h385869 ; + res_data__h385565 : + res_data__h385560 ; assign MUX_rf$write_2_wr_2__VAL_4 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[39] ? - res_data__h431569 : - res_data__h431564 ; + res_data__h431260 : + res_data__h431255 ; assign MUX_rf$write_2_wr_2__VAL_5 = coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[33] ? - data___1__h477383 : - data__h476871 ; + data___1__h477074 : + data__h476562 ; assign MUX_rf$write_2_wr_2__VAL_6 = coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[33] ? - data___1__h478277 : - data__h477765 ; + data___1__h477968 : + data__h477456 ; assign MUX_rf$write_3_wr_2__VAL_4 = coreFix_memExe_lsq$firstLd[100] ? coreFix_memExe_respLrScAmoQ_data_0 : @@ -12491,7 +12376,7 @@ module mkCore(CLK, fetchStage$pipelines_0_first[127:96], fetchStage$pipelines_0_first[199:195], fetchStage$pipelines_0_first[173], - IF_fetchStage_pipelines_0_first__2934_BITS_172_ETC___d13146, + IF_fetchStage_pipelines_0_first__2931_BITS_172_ETC___d13142, 73'h1280000000000000000, fetchStage$pipelines_0_first[323:260], 5'd0, @@ -12502,16 +12387,16 @@ module mkCore(CLK, fetchStage$pipelines_0_first[194:192] != 3'd2 && fetchStage$pipelines_0_first[194:192] != 3'd3 && fetchStage$pipelines_0_first[194:192] != 3'd4, - NOT_fetchStage_pipelines_0_first__2934_BITS_19_ETC___d14362 } ; + NOT_fetchStage_pipelines_0_first__2931_BITS_19_ETC___d14358 } ; assign MUX_rob$enqPort_0_enq_1__VAL_2 = { fetchStage$pipelines_0_first[387:324], fetchStage$pipelines_0_first[127:96], fetchStage$pipelines_0_first[199:195], fetchStage$pipelines_0_first[173], - IF_fetchStage_pipelines_0_first__2934_BITS_172_ETC___d13146, + IF_fetchStage_pipelines_0_first__2931_BITS_172_ETC___d13142, 2'd1, - renameStage_rg_m_halt_req_2961_BIT_4_2962_OR_N_ETC___d13238, - IF_NOT_renameStage_rg_m_halt_req_2961_BIT_4_29_ETC___d13453, + renameStage_rg_m_halt_req_2958_BIT_4_2959_OR_N_ETC___d13234, + IF_NOT_renameStage_rg_m_halt_req_2958_BIT_4_29_ETC___d13449, fetchStage$pipelines_0_first[63:0], 2'd0, fetchStage$pipelines_0_first[323:260], @@ -12522,7 +12407,7 @@ module mkCore(CLK, fetchStage$pipelines_0_first[127:96], fetchStage$pipelines_0_first[199:195], fetchStage$pipelines_0_first[173], - IF_fetchStage_pipelines_0_first__2934_BITS_172_ETC___d13146, + IF_fetchStage_pipelines_0_first__2931_BITS_172_ETC___d13142, 73'h1280000000000000000, fetchStage$pipelines_0_first[323:260], 5'd0, @@ -12533,31 +12418,22 @@ module mkCore(CLK, specTagManager$currentSpecBits } ; assign MUX_rob$setExecuted_deqLSQ_2__VAL_2 = { 1'd1, - CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q273 } ; + CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q265 } ; assign MUX_rob$setExecuted_deqLSQ_2__VAL_6 = { 1'd1, - CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q274 } ; + CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q266 } ; assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_2 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[4:0] : - res_fflags__h340168 ; + res_fflags__h339859 ; assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_3 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[4:0] : - res_fflags__h385870 ; + res_fflags__h385561 ; assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_4 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[4:0] : - res_fflags__h431565 ; - assign MUX_v_f_to_TV_0$enq_1__VAL_1 = - { commitStage_rg_serialnum, - rob$deqPort_0_deq_data[282:181], - CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q275, - rob$deqPort_0_deq_data[167], - rob_deqPort_0_deq_data__4547_BIT_166_4563_CONC_ETC___d14612, - rob$deqPort_0_deq_data[161:98], - CASE_robdeqPort_0_deq_data_BITS_97_TO_96_0_ro_ETC__q276, - rob$deqPort_0_deq_data[95:26] } ; + res_fflags__h431256 ; // inlined wires assign csrf_minstret_ehr_data_lat_0$whas = @@ -12576,7 +12452,7 @@ module mkCore(CLK, WILL_FIRE_RL_renameStage_doRenaming_SystemInst && fetchStage$pipelines_0_first[199:195] == 5'd13 || WILL_FIRE_RL_renameStage_doRenaming_Trap && - renameStage_rg_m_halt_req_2961_BIT_4_2962_OR_N_ETC___d13467 ; + renameStage_rg_m_halt_req_2958_BIT_4_2959_OR_N_ETC___d13463 ; assign mmio_dataReqQ_enqReq_lat_0$wget = WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue ? MUX_mmio_dataReqQ_enqReq_lat_0$wset_1__VAL_1 : @@ -12606,7 +12482,7 @@ module mkCore(CLK, assign mmio_pRqQ_enqReq_lat_0$wget = { 1'd1, mmioToPlatform_pRq_enq_x[38], - CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q277, + CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q267, mmioToPlatform_pRq_enq_x[31:0] } ; assign mmio_cRsQ_enqReq_lat_0$wget = { 1'd1, csrf_software_int_pend_vec_3 } ; @@ -12618,13 +12494,13 @@ module mkCore(CLK, coreFix_aluExe_1_exeToFinQ$first[16] ; assign coreFix_aluExe_0_bypassWire_0$wget = { coreFix_aluExe_0_regToExeQ$first[348:342], - basicExec___d12781[321:258] } ; + basicExec___d12778[321:258] } ; assign coreFix_aluExe_0_bypassWire_0$whas = WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu && coreFix_aluExe_0_regToExeQ$first[349] ; assign coreFix_aluExe_0_bypassWire_1$wget = { coreFix_aluExe_1_regToExeQ$first[348:342], - basicExec___d12107[321:258] } ; + basicExec___d12104[321:258] } ; assign coreFix_aluExe_0_bypassWire_1$whas = WILL_FIRE_RL_coreFix_aluExe_1_doExeAlu && coreFix_aluExe_1_regToExeQ$first[349] ; @@ -12863,7 +12739,7 @@ module mkCore(CLK, MUX_commitStage_rg_run_state$write_1__SEL_1 ; assign commitStage_rg_run_state$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap_4555_BIT_4_4779_AND_com_ETC___d14844 || + commitStage_commitTrap_4549_BIT_4_4679_AND_com_ETC___d14744 || WILL_FIRE_RL_rl_debug_resume ; // register commitStage_rg_serialnum @@ -12896,8 +12772,8 @@ module mkCore(CLK, // register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$D_IN = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas ? - v__h608052 : - v__h607011 ; + v__h607743 : + v__h606702 ; assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$EN = 1'd1 ; // register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_0 @@ -13043,7 +12919,7 @@ module mkCore(CLK, (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT && coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl) ? 3'd0 : - _theResult_____2__h298821 ; + _theResult_____2__h298513 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl @@ -13065,7 +12941,7 @@ module mkCore(CLK, (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT && coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl) ? 3'd0 : - v__h298241 ; + v__h297933 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl @@ -13111,7 +12987,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3223 && - _theResult_____2__h306817 ; + _theResult_____2__h306509 ; assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl @@ -13129,7 +13005,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3223 && - v__h301586 ; + v__h301278 ; assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl @@ -13229,7 +13105,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3394 && - _theResult_____2__h312811 ; + _theResult_____2__h312503 ; assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl @@ -13247,7 +13123,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3394 && - v__h312100 ; + v__h311792 ; assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl @@ -13268,7 +13144,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$D_IN = - { x_addr__h316374, + { x_addr__h316066, coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[514:513] : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[514:513], @@ -13298,7 +13174,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3490 && - _theResult_____2__h320665 ; + _theResult_____2__h320357 ; assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl @@ -13316,7 +13192,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3490 && - v__h315976 ; + v__h315668 ; assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl @@ -13393,7 +13269,7 @@ module mkCore(CLK, // register coreFix_memExe_forwardQ_deqP assign coreFix_memExe_forwardQ_deqP$D_IN = NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3813 && - _theResult_____2__h334234 ; + _theResult_____2__h333926 ; assign coreFix_memExe_forwardQ_deqP$EN = 1'd1 ; // register coreFix_memExe_forwardQ_deqReq_rl @@ -13411,7 +13287,7 @@ module mkCore(CLK, // register coreFix_memExe_forwardQ_enqP assign coreFix_memExe_forwardQ_enqP$D_IN = NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3813 && - v__h333802 ; + v__h333494 ; assign coreFix_memExe_forwardQ_enqP$EN = 1'd1 ; // register coreFix_memExe_forwardQ_enqReq_rl @@ -13454,7 +13330,7 @@ module mkCore(CLK, // register coreFix_memExe_memRespLdQ_deqP assign coreFix_memExe_memRespLdQ_deqP$D_IN = NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3719 && - _theResult_____2__h331009 ; + _theResult_____2__h330701 ; assign coreFix_memExe_memRespLdQ_deqP$EN = 1'd1 ; // register coreFix_memExe_memRespLdQ_deqReq_rl @@ -13472,7 +13348,7 @@ module mkCore(CLK, // register coreFix_memExe_memRespLdQ_enqP assign coreFix_memExe_memRespLdQ_enqP$D_IN = NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3719 && - v__h330577 ; + v__h330269 ; assign coreFix_memExe_memRespLdQ_enqP$EN = 1'd1 ; // register coreFix_memExe_memRespLdQ_enqReq_rl @@ -13627,28 +13503,6 @@ module mkCore(CLK, csrInstOrInterruptInflight_rl) ; assign csrInstOrInterruptInflight_rl$EN = 1'd1 ; - // register csrf_debug_int_pend - always@(MUX_csrf_debug_int_pend$write_1__SEL_1 or - MUX_csrf_stval_csr$write_1__VAL_1 or - MUX_csrf_debug_int_pend$write_1__SEL_2 or - f_csr_reqs$D_OUT or EN_setDEIP or setDEIP_v) - case (1'b1) - MUX_csrf_debug_int_pend$write_1__SEL_1: - csrf_debug_int_pend$D_IN = MUX_csrf_stval_csr$write_1__VAL_1[14]; - MUX_csrf_debug_int_pend$write_1__SEL_2: - csrf_debug_int_pend$D_IN = f_csr_reqs$D_OUT[14]; - EN_setDEIP: csrf_debug_int_pend$D_IN = setDEIP_v; - default: csrf_debug_int_pend$D_IN = 1'b0 /* unspecified value */ ; - endcase - assign csrf_debug_int_pend$EN = - WILL_FIRE_RL_rl_debug_csr_write && - f_csr_reqs$D_OUT[75:64] == 12'd836 || - WILL_FIRE_RL_commitStage_doCommitSystemInst && - rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == - 6'd29 || - EN_setDEIP ; - // register csrf_external_int_en_vec_0 assign csrf_external_int_en_vec_0$D_IN = MUX_csrf_external_int_en_vec_0$write_1__SEL_1 ? @@ -13681,7 +13535,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd772 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd22 ; // register csrf_external_int_pend_vec_0 @@ -13718,15 +13572,15 @@ module mkCore(CLK, EN_setSEIP ; // register csrf_external_int_pend_vec_3 - always@(MUX_csrf_debug_int_pend$write_1__SEL_1 or + always@(MUX_csrf_external_int_pend_vec_3$write_1__SEL_1 or MUX_csrf_stval_csr$write_1__VAL_1 or - MUX_csrf_debug_int_pend$write_1__SEL_2 or + MUX_csrf_external_int_pend_vec_3$write_1__SEL_2 or f_csr_reqs$D_OUT or EN_setMEIP or setMEIP_v) case (1'b1) - MUX_csrf_debug_int_pend$write_1__SEL_1: + MUX_csrf_external_int_pend_vec_3$write_1__SEL_1: csrf_external_int_pend_vec_3$D_IN = MUX_csrf_stval_csr$write_1__VAL_1[11]; - MUX_csrf_debug_int_pend$write_1__SEL_2: + MUX_csrf_external_int_pend_vec_3$write_1__SEL_2: csrf_external_int_pend_vec_3$D_IN = f_csr_reqs$D_OUT[11]; EN_setMEIP: csrf_external_int_pend_vec_3$D_IN = setMEIP_v; default: csrf_external_int_pend_vec_3$D_IN = @@ -13737,7 +13591,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd836 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd29 || EN_setMEIP ; @@ -13759,12 +13613,12 @@ module mkCore(CLK, assign csrf_fflags_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + (IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd0 || - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd2) || WILL_FIRE_RL_commitStage_doCommitNormalInst && - NOT_IF_NOT_rob_deqPort_0_canDeq__5214_5215_OR__ETC___d15527 || + NOT_IF_NOT_rob_deqPort_0_canDeq__5156_5157_OR__ETC___d15372 || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd1 || f_csr_reqs$D_OUT[75:64] == 12'd3) ; @@ -13777,9 +13631,9 @@ module mkCore(CLK, assign csrf_frm_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + (IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd1 || - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd2) || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd2 || @@ -13801,7 +13655,7 @@ module mkCore(CLK, assign csrf_fs_reg$EN = MUX_csrf_fs_reg$write_1__SEL_2 || WILL_FIRE_RL_commitStage_doCommitNormalInst && - NOT_IF_NOT_rob_deqPort_0_canDeq__5214_5215_OR__ETC___d15527 || + NOT_IF_NOT_rob_deqPort_0_canDeq__5156_5157_OR__ETC___d15372 || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd1 || f_csr_reqs$D_OUT[75:64] == 12'd2 || @@ -13834,10 +13688,10 @@ module mkCore(CLK, default: csrf_ie_vec_1$D_IN = 1'b0 /* unspecified value */ ; endcase assign csrf_ie_vec_1$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo30 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4555_BIT_4_4779_478_ETC___d14881 && - csrf_prv_reg_read__2964_ULE_1_4882_AND_IF_comm_ETC___d14904 || + NOT_commitStage_commitTrap_4549_BIT_4_4679_468_ETC___d14781 && + csrf_prv_reg_read__2961_ULE_1_4782_AND_IF_comm_ETC___d14804 || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd256 || f_csr_reqs$D_OUT[75:64] == 12'd768) ; @@ -13856,24 +13710,24 @@ module mkCore(CLK, default: csrf_ie_vec_3$D_IN = 1'b0 /* unspecified value */ ; endcase assign csrf_ie_vec_3$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo24 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 || WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4555_BIT_4_4779_478_ETC___d14881 && - NOT_csrf_prv_reg_read__2964_ULE_1_4882_4923_OR_ETC___d14927 ; + NOT_commitStage_commitTrap_4549_BIT_4_4679_468_ETC___d14781 && + NOT_csrf_prv_reg_read__2961_ULE_1_4782_4823_OR_ETC___d14827 ; // register csrf_mcause_code_reg always@(MUX_csrf_mcause_code_reg$write_1__SEL_1 or MUX_csrf_stval_csr$write_1__VAL_1 or MUX_csrf_ie_vec_3$write_1__SEL_2 or - cause_code__h707068 or + cause_code__h705748 or MUX_csrf_mcause_code_reg$write_1__SEL_3 or f_csr_reqs$D_OUT) case (1'b1) MUX_csrf_mcause_code_reg$write_1__SEL_1: csrf_mcause_code_reg$D_IN = MUX_csrf_stval_csr$write_1__VAL_1[3:0]; MUX_csrf_ie_vec_3$write_1__SEL_2: - csrf_mcause_code_reg$D_IN = cause_code__h707068; + csrf_mcause_code_reg$D_IN = cause_code__h705748; MUX_csrf_mcause_code_reg$write_1__SEL_3: csrf_mcause_code_reg$D_IN = f_csr_reqs$D_OUT[3:0]; default: csrf_mcause_code_reg$D_IN = 4'b1010 /* unspecified value */ ; @@ -13882,11 +13736,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd834 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4555_BIT_4_4779_478_ETC___d14881 && - NOT_csrf_prv_reg_read__2964_ULE_1_4882_4923_OR_ETC___d14927 || + NOT_commitStage_commitTrap_4549_BIT_4_4679_468_ETC___d14781 && + NOT_csrf_prv_reg_read__2961_ULE_1_4782_4823_OR_ETC___d14827 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd27 ; // register csrf_mcause_interrupt_reg @@ -13909,11 +13763,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd834 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4555_BIT_4_4779_478_ETC___d14881 && - NOT_csrf_prv_reg_read__2964_ULE_1_4882_4923_OR_ETC___d14927 || + NOT_commitStage_commitTrap_4549_BIT_4_4679_468_ETC___d14781 && + NOT_csrf_prv_reg_read__2961_ULE_1_4782_4823_OR_ETC___d14827 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd27 ; // register csrf_mcounteren_cy_reg @@ -13926,7 +13780,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd774 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd24 ; // register csrf_mcounteren_ir_reg @@ -13939,7 +13793,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd774 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd24 ; // register csrf_mcounteren_tm_reg @@ -13952,11 +13806,11 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd774 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd24 ; // register csrf_mcycle_ehr_data_rl - assign csrf_mcycle_ehr_data_rl$D_IN = upd__h5341 ; + assign csrf_mcycle_ehr_data_rl$D_IN = upd__h5034 ; assign csrf_mcycle_ehr_data_rl$EN = 1'd1 ; // register csrf_medeleg_13_11_reg @@ -13969,7 +13823,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd770 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd20 ; // register csrf_medeleg_15_reg @@ -13982,7 +13836,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd770 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd20 ; // register csrf_medeleg_9_0_reg @@ -13995,7 +13849,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd770 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd20 ; // register csrf_mepc_csr @@ -14018,11 +13872,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd833 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4555_BIT_4_4779_478_ETC___d14881 && - NOT_csrf_prv_reg_read__2964_ULE_1_4882_4923_OR_ETC___d14927 || + NOT_commitStage_commitTrap_4549_BIT_4_4679_468_ETC___d14781 && + NOT_csrf_prv_reg_read__2961_ULE_1_4782_4823_OR_ETC___d14827 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd26 ; // register csrf_mideleg_11_reg @@ -14035,7 +13889,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd771 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd21 ; // register csrf_mideleg_1_0_reg @@ -14048,7 +13902,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd771 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd21 ; // register csrf_mideleg_5_3_reg @@ -14061,7 +13915,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd771 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd21 ; // register csrf_mideleg_9_7_reg @@ -14074,13 +13928,13 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd771 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd21 ; // register csrf_minstret_ehr_data_rl assign csrf_minstret_ehr_data_rl$D_IN = csrf_minstret_ehr_data_lat_1$whas ? - upd__h4024 : + upd__h3717 : IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8 ; assign csrf_minstret_ehr_data_rl$EN = 1'd1 ; @@ -14099,12 +13953,12 @@ module mkCore(CLK, default: csrf_mpp_reg$D_IN = 2'b10 /* unspecified value */ ; endcase assign csrf_mpp_reg$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo24 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 || WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4555_BIT_4_4779_478_ETC___d14881 && - NOT_csrf_prv_reg_read__2964_ULE_1_4882_4923_OR_ETC___d14927 ; + NOT_commitStage_commitTrap_4549_BIT_4_4679_468_ETC___d14781 && + NOT_csrf_prv_reg_read__2961_ULE_1_4782_4823_OR_ETC___d14827 ; // register csrf_mprv_reg assign csrf_mprv_reg$D_IN = @@ -14116,7 +13970,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd18 ; // register csrf_mscratch_csr @@ -14129,7 +13983,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd832 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd25 ; // register csrf_mtval_csr @@ -14152,11 +14006,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd835 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4555_BIT_4_4779_478_ETC___d14881 && - NOT_csrf_prv_reg_read__2964_ULE_1_4882_4923_OR_ETC___d14927 || + NOT_commitStage_commitTrap_4549_BIT_4_4679_468_ETC___d14781 && + NOT_csrf_prv_reg_read__2961_ULE_1_4782_4823_OR_ETC___d14827 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd28 ; // register csrf_mtvec_base_hi_reg @@ -14169,7 +14023,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd773 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd23 ; // register csrf_mtvec_mode_low_reg @@ -14182,7 +14036,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd773 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd23 ; // register csrf_mxr_reg @@ -14206,7 +14060,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd384 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd17 ; // register csrf_prev_ie_vec_0 @@ -14235,10 +14089,10 @@ module mkCore(CLK, default: csrf_prev_ie_vec_1$D_IN = 1'b0 /* unspecified value */ ; endcase assign csrf_prev_ie_vec_1$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo30 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4555_BIT_4_4779_478_ETC___d14881 && - csrf_prv_reg_read__2964_ULE_1_4882_AND_IF_comm_ETC___d14904 || + NOT_commitStage_commitTrap_4549_BIT_4_4679_468_ETC___d14781 && + csrf_prv_reg_read__2961_ULE_1_4782_AND_IF_comm_ETC___d14804 || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd256 || f_csr_reqs$D_OUT[75:64] == 12'd768) ; @@ -14258,49 +14112,59 @@ module mkCore(CLK, default: csrf_prev_ie_vec_3$D_IN = 1'b0 /* unspecified value */ ; endcase assign csrf_prev_ie_vec_3$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo24 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 || WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4555_BIT_4_4779_478_ETC___d14881 && - NOT_csrf_prv_reg_read__2964_ULE_1_4882_4923_OR_ETC___d14927 ; + NOT_commitStage_commitTrap_4549_BIT_4_4679_468_ETC___d14781 && + NOT_csrf_prv_reg_read__2961_ULE_1_4782_4823_OR_ETC___d14827 ; // register csrf_prv_reg - assign csrf_prv_reg$D_IN = - MUX_fetchStage$redirect_1__SEL_1 ? - MUX_csrf_prv_reg$write_1__VAL_1 : - MUX_csrf_prv_reg$write_1__VAL_2 ; + always@(MUX_csrf_prv_reg$write_1__SEL_1 or + MUX_csrf_prv_reg$write_1__VAL_1 or + MUX_csrf_prv_reg$write_1__SEL_2 or + MUX_csrf_prv_reg$write_1__VAL_2 or + MUX_csrf_prv_reg$write_1__SEL_3 or f_csr_reqs$D_OUT) + case (1'b1) + MUX_csrf_prv_reg$write_1__SEL_1: + csrf_prv_reg$D_IN = MUX_csrf_prv_reg$write_1__VAL_1; + MUX_csrf_prv_reg$write_1__SEL_2: + csrf_prv_reg$D_IN = MUX_csrf_prv_reg$write_1__VAL_2; + MUX_csrf_prv_reg$write_1__SEL_3: + csrf_prv_reg$D_IN = f_csr_reqs$D_OUT[1:0]; + default: csrf_prv_reg$D_IN = 2'b10 /* unspecified value */ ; + endcase assign csrf_prv_reg$EN = + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo24 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4555_BIT_4_4779_478_ETC___d14881 || - WILL_FIRE_RL_commitStage_doCommitSystemInst && - (rob$deqPort_0_deq_data[186:182] == 5'd19 || - rob$deqPort_0_deq_data[186:182] == 5'd20) ; + NOT_commitStage_commitTrap_4549_BIT_4_4679_468_ETC___d14781 || + WILL_FIRE_RL_rl_debug_csr_write && + f_csr_reqs$D_OUT[75:64] == 12'd1968 ; // register csrf_rg_dcsr always@(MUX_csrf_rg_dcsr$write_1__SEL_1 or rob$deqPort_0_deq_data or MUX_commitStage_rg_run_state$write_1__SEL_1 or MUX_csrf_rg_dcsr$write_1__VAL_2 or - MUX_csrf_rg_dcsr$write_1__SEL_3 or f_csr_reqs$D_OUT) + MUX_csrf_prv_reg$write_1__SEL_3 or f_csr_reqs$D_OUT) case (1'b1) MUX_csrf_rg_dcsr$write_1__SEL_1: csrf_rg_dcsr$D_IN = rob$deqPort_0_deq_data[95:32]; MUX_commitStage_rg_run_state$write_1__SEL_1: csrf_rg_dcsr$D_IN = MUX_csrf_rg_dcsr$write_1__VAL_2; - MUX_csrf_rg_dcsr$write_1__SEL_3: + MUX_csrf_prv_reg$write_1__SEL_3: csrf_rg_dcsr$D_IN = f_csr_reqs$D_OUT[63:0]; default: csrf_rg_dcsr$D_IN = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase assign csrf_rg_dcsr$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap_4555_BIT_4_4779_AND_com_ETC___d14844 || + commitStage_commitTrap_4549_BIT_4_4679_AND_com_ETC___d14744 || WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd1968 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd36 ; // register csrf_rg_dpc @@ -14319,12 +14183,12 @@ module mkCore(CLK, endcase assign csrf_rg_dpc$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap_4555_BIT_4_4779_AND_com_ETC___d14844 || + commitStage_commitTrap_4549_BIT_4_4679_AND_com_ETC___d14744 || WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd1969 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd37 ; // register csrf_rg_dscratch0 @@ -14337,7 +14201,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1970 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd38 ; // register csrf_rg_dscratch1 @@ -14350,20 +14214,20 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1971 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd39 ; // register csrf_scause_code_reg always@(MUX_csrf_scause_code_reg$write_1__SEL_1 or MUX_csrf_stval_csr$write_1__VAL_1 or MUX_csrf_ie_vec_1$write_1__SEL_2 or - cause_code__h707068 or + cause_code__h705748 or MUX_csrf_scause_code_reg$write_1__SEL_3 or f_csr_reqs$D_OUT) case (1'b1) MUX_csrf_scause_code_reg$write_1__SEL_1: csrf_scause_code_reg$D_IN = MUX_csrf_stval_csr$write_1__VAL_1[3:0]; MUX_csrf_ie_vec_1$write_1__SEL_2: - csrf_scause_code_reg$D_IN = cause_code__h707068; + csrf_scause_code_reg$D_IN = cause_code__h705748; MUX_csrf_scause_code_reg$write_1__SEL_3: csrf_scause_code_reg$D_IN = f_csr_reqs$D_OUT[3:0]; default: csrf_scause_code_reg$D_IN = 4'b1010 /* unspecified value */ ; @@ -14372,11 +14236,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd322 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4555_BIT_4_4779_478_ETC___d14881 && - csrf_prv_reg_read__2964_ULE_1_4882_AND_IF_comm_ETC___d14904 || + NOT_commitStage_commitTrap_4549_BIT_4_4679_468_ETC___d14781 && + csrf_prv_reg_read__2961_ULE_1_4782_AND_IF_comm_ETC___d14804 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd14 ; // register csrf_scause_interrupt_reg @@ -14399,11 +14263,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd322 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4555_BIT_4_4779_478_ETC___d14881 && - csrf_prv_reg_read__2964_ULE_1_4882_AND_IF_comm_ETC___d14904 || + NOT_commitStage_commitTrap_4549_BIT_4_4679_468_ETC___d14781 && + csrf_prv_reg_read__2961_ULE_1_4782_AND_IF_comm_ETC___d14804 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd14 ; // register csrf_scounteren_cy_reg @@ -14416,7 +14280,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd262 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd11 ; // register csrf_scounteren_ir_reg @@ -14429,7 +14293,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd262 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd11 ; // register csrf_scounteren_tm_reg @@ -14442,7 +14306,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd262 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd11 ; // register csrf_sepc_csr @@ -14465,11 +14329,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd321 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4555_BIT_4_4779_478_ETC___d14881 && - csrf_prv_reg_read__2964_ULE_1_4882_AND_IF_comm_ETC___d14904 || + NOT_commitStage_commitTrap_4549_BIT_4_4679_468_ETC___d14781 && + csrf_prv_reg_read__2961_ULE_1_4782_AND_IF_comm_ETC___d14804 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd13 ; // register csrf_software_int_en_vec_0 @@ -14504,7 +14368,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd772 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd22 ; // register csrf_software_int_pend_vec_0 @@ -14530,19 +14394,19 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd836) ; // register csrf_software_int_pend_vec_3 - always@(MUX_csrf_debug_int_pend$write_1__SEL_1 or + always@(MUX_csrf_external_int_pend_vec_3$write_1__SEL_1 or MUX_csrf_stval_csr$write_1__VAL_1 or MUX_csrf_software_int_pend_vec_3$write_1__SEL_2 or MUX_csrf_software_int_pend_vec_3$write_1__VAL_2 or - MUX_csrf_debug_int_pend$write_1__SEL_2 or f_csr_reqs$D_OUT) + MUX_csrf_external_int_pend_vec_3$write_1__SEL_2 or f_csr_reqs$D_OUT) case (1'b1) - MUX_csrf_debug_int_pend$write_1__SEL_1: + MUX_csrf_external_int_pend_vec_3$write_1__SEL_1: csrf_software_int_pend_vec_3$D_IN = MUX_csrf_stval_csr$write_1__VAL_1[3]; MUX_csrf_software_int_pend_vec_3$write_1__SEL_2: csrf_software_int_pend_vec_3$D_IN = MUX_csrf_software_int_pend_vec_3$write_1__VAL_2; - MUX_csrf_debug_int_pend$write_1__SEL_2: + MUX_csrf_external_int_pend_vec_3$write_1__SEL_2: csrf_software_int_pend_vec_3$D_IN = f_csr_reqs$D_OUT[3]; default: csrf_software_int_pend_vec_3$D_IN = 1'b0 /* unspecified value */ ; @@ -14555,7 +14419,7 @@ module mkCore(CLK, mmio_pRqQ_data_0[37:36] != 2'd1 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd29 ; // register csrf_spp_reg @@ -14572,10 +14436,10 @@ module mkCore(CLK, default: csrf_spp_reg$D_IN = 1'b0 /* unspecified value */ ; endcase assign csrf_spp_reg$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo30 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4555_BIT_4_4779_478_ETC___d14881 && - csrf_prv_reg_read__2964_ULE_1_4882_AND_IF_comm_ETC___d14904 || + NOT_commitStage_commitTrap_4549_BIT_4_4679_468_ETC___d14781 && + csrf_prv_reg_read__2961_ULE_1_4782_AND_IF_comm_ETC___d14804 || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd256 || f_csr_reqs$D_OUT[75:64] == 12'd768) ; @@ -14590,7 +14454,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd320 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd12 ; // register csrf_stats_module_doStats @@ -14617,11 +14481,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd323 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4555_BIT_4_4779_478_ETC___d14881 && - csrf_prv_reg_read__2964_ULE_1_4882_AND_IF_comm_ETC___d14904 || + NOT_commitStage_commitTrap_4549_BIT_4_4679_468_ETC___d14781 && + csrf_prv_reg_read__2961_ULE_1_4782_AND_IF_comm_ETC___d14804 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd15 ; // register csrf_stvec_base_hi_reg @@ -14634,7 +14498,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd261 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd10 ; // register csrf_stvec_mode_low_reg @@ -14647,7 +14511,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd261 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd10 ; // register csrf_sum_reg @@ -14697,7 +14561,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd772 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd22 ; // register csrf_timer_int_pend_vec_0 @@ -14738,7 +14602,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd18 ; // register csrf_tvm_reg @@ -14751,7 +14615,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd18 ; // register csrf_tw_reg @@ -14764,7 +14628,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd18 ; // register csrf_vm_mode_sv39_reg @@ -14777,21 +14641,21 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd384 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd17 ; // register flush_brpred assign flush_brpred$D_IN = MUX_commitStage_rg_run_state$write_1__SEL_1 ; assign flush_brpred$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap_4555_BIT_4_4779_AND_com_ETC___d14844 || + commitStage_commitTrap_4549_BIT_4_4679_AND_com_ETC___d14744 || WILL_FIRE_RL_flushBrPred ; // register flush_caches assign flush_caches$D_IN = MUX_commitStage_rg_run_state$write_1__SEL_1 ; assign flush_caches$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap_4555_BIT_4_4779_AND_com_ETC___d14844 || + commitStage_commitTrap_4549_BIT_4_4679_AND_com_ETC___d14744 || WILL_FIRE_RL_flushCaches ; // register flush_reservation @@ -14806,11 +14670,11 @@ module mkCore(CLK, assign flush_tlbs$EN = WILL_FIRE_RL_prepareCachesAndTlbs && flush_tlbs || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap_4555_BIT_4_4779_AND_com_ETC___d14844 || + commitStage_commitTrap_4549_BIT_4_4679_AND_com_ETC___d14744 || WILL_FIRE_RL_commitStage_doCommitSystemInst && (rob$deqPort_0_deq_data[186:182] == 5'd16 || rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd17) ; // register mmio_cRqQ_clearReq_rl @@ -14819,7 +14683,7 @@ module mkCore(CLK, // register mmio_cRqQ_data_0 assign mmio_cRqQ_data_0$D_IN = - { x__h46110, + { x__h45802, (mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[77:76] == 2'd0 : mmio_cRqQ_enqReq_rl[77:76] == 2'd0) ? @@ -14831,7 +14695,7 @@ module mkCore(CLK, mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[71:64] : mmio_cRqQ_enqReq_rl[71:64], - x__h48646 } ; + x__h48338 } ; assign mmio_cRqQ_data_0$EN = NOT_mmio_cRqQ_clearReq_dummy2_1_read__26_27_OR_ETC___d431 && mmio_cRqQ_enqReq_dummy2_2$Q_OUT && @@ -14924,7 +14788,7 @@ module mkCore(CLK, // register mmio_dataReqQ_data_0 assign mmio_dataReqQ_data_0$D_IN = - { x__h18203, + { x__h17895, (mmio_dataReqQ_enqReq_lat_0$whas ? mmio_dataReqQ_enqReq_lat_0$wget[77:76] == 2'd0 : mmio_dataReqQ_enqReq_rl[77:76] == 2'd0) ? @@ -14936,7 +14800,7 @@ module mkCore(CLK, mmio_dataReqQ_enqReq_lat_0$whas ? mmio_dataReqQ_enqReq_lat_0$wget[71:64] : mmio_dataReqQ_enqReq_rl[71:64], - x__h20741 } ; + x__h20433 } ; assign mmio_dataReqQ_data_0$EN = NOT_mmio_dataReqQ_clearReq_dummy2_1_read__35_3_ETC___d140 && mmio_dataReqQ_enqReq_dummy2_2$Q_OUT && @@ -15020,7 +14884,7 @@ module mkCore(CLK, mmio_pRqQ_enqReq_lat_0$wget[32] : mmio_pRqQ_enqReq_rl[32] } : IF_IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmi_ETC___d766, - x_data__h65904 } ; + x_data__h65596 } ; assign mmio_pRqQ_data_0$EN = NOT_mmio_pRqQ_clearReq_dummy2_1_read__29_30_OR_ETC___d734 && mmio_pRqQ_enqReq_dummy2_2$Q_OUT && @@ -15110,7 +14974,7 @@ module mkCore(CLK, WILL_FIRE_RL_renameStage_doRenaming_Trap) && csrf_rg_dcsr[2] || WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d14388 && + NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d14384 && csrf_rg_dcsr[2] || WILL_FIRE_RL_rl_debug_resume || WILL_FIRE_RL_rl_debug_halt_req ; @@ -15140,7 +15004,8 @@ module mkCore(CLK, EN_coreReq_start ; // register update_vm_info - assign update_vm_info$D_IN = !MUX_update_vm_info$write_1__SEL_2 ; + assign update_vm_info$D_IN = + !MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1 ; assign update_vm_info$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && _dfoo20 || WILL_FIRE_RL_prepareCachesAndTlbs && update_vm_info || @@ -15149,16 +15014,16 @@ module mkCore(CLK, // submodule coreFix_aluExe_0_dispToRegQ assign coreFix_aluExe_0_dispToRegQ$enq_x = { coreFix_aluExe_0_rsAlu$dispatchData[161:157], - CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q279, + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q269, coreFix_aluExe_0_rsAlu$dispatchData[135], - CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q280, + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q270, coreFix_aluExe_0_rsAlu$dispatchData[122:90], coreFix_aluExe_0_rsAlu$dispatchData[65:21], coreFix_aluExe_0_rsAlu$dispatchData[89:66], coreFix_aluExe_0_rsAlu$dispatchData[8:4], coreFix_aluExe_0_rsAlu$dispatchData[20:9] } ; assign coreFix_aluExe_0_dispToRegQ$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12875 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12872 ; assign coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all = !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ; @@ -15198,13 +15063,13 @@ module mkCore(CLK, { coreFix_aluExe_0_regToExeQ$first[421:417], coreFix_aluExe_0_regToExeQ$first[349:305], coreFix_aluExe_0_regToExeQ$first[18:17] != 2'b11, - basicExec___d12781[321:258], + basicExec___d12778[321:258], coreFix_aluExe_0_regToExeQ$first[395], - basicExec___d12781[257:194], - basicExec___d12781[129:0], + basicExec___d12778[257:194], + basicExec___d12778[129:0], coreFix_aluExe_0_regToExeQ$first[16:0] } ; assign coreFix_aluExe_0_exeToFinQ$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12875 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12872 ; assign coreFix_aluExe_0_exeToFinQ$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -15242,19 +15107,19 @@ module mkCore(CLK, // submodule coreFix_aluExe_0_regToExeQ assign coreFix_aluExe_0_regToExeQ$enq_x = { coreFix_aluExe_0_dispToRegQ$first[157:153], - CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_15_ETC__q282, + CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_15_ETC__q272, coreFix_aluExe_0_dispToRegQ$first[131], - CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q283, + CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q273, coreFix_aluExe_0_dispToRegQ$first[118:86], coreFix_aluExe_0_dispToRegQ$first[61:17], - x__h643354, - x__h643355, + x__h643018, + x__h643019, rob$getOrigPC_0_get, rob$getOrigPredPC_0_get, rob$getOrig_Inst_0_get, coreFix_aluExe_0_dispToRegQ$first[16:0] } ; assign coreFix_aluExe_0_regToExeQ$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12875 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12872 ; assign coreFix_aluExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -15362,7 +15227,7 @@ module mkCore(CLK, end assign coreFix_aluExe_0_rsAlu$setRobEnqTime_t = rob$getEnqTime ; assign coreFix_aluExe_0_rsAlu$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12875 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12872 ; assign coreFix_aluExe_0_rsAlu$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -15441,16 +15306,16 @@ module mkCore(CLK, // submodule coreFix_aluExe_1_dispToRegQ assign coreFix_aluExe_1_dispToRegQ$enq_x = { coreFix_aluExe_1_rsAlu$dispatchData[161:157], - CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q285, + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q275, coreFix_aluExe_1_rsAlu$dispatchData[135], - CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q286, + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q276, coreFix_aluExe_1_rsAlu$dispatchData[122:90], coreFix_aluExe_1_rsAlu$dispatchData[65:21], coreFix_aluExe_1_rsAlu$dispatchData[89:66], coreFix_aluExe_1_rsAlu$dispatchData[8:4], coreFix_aluExe_1_rsAlu$dispatchData[20:9] } ; assign coreFix_aluExe_1_dispToRegQ$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12875 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12872 ; assign coreFix_aluExe_1_dispToRegQ$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -15489,13 +15354,13 @@ module mkCore(CLK, { coreFix_aluExe_1_regToExeQ$first[421:417], coreFix_aluExe_1_regToExeQ$first[349:305], coreFix_aluExe_1_regToExeQ$first[18:17] != 2'b11, - basicExec___d12107[321:258], + basicExec___d12104[321:258], coreFix_aluExe_1_regToExeQ$first[395], - basicExec___d12107[257:194], - basicExec___d12107[129:0], + basicExec___d12104[257:194], + basicExec___d12104[129:0], coreFix_aluExe_1_regToExeQ$first[16:0] } ; assign coreFix_aluExe_1_exeToFinQ$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12875 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12872 ; assign coreFix_aluExe_1_exeToFinQ$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -15533,19 +15398,19 @@ module mkCore(CLK, // submodule coreFix_aluExe_1_regToExeQ assign coreFix_aluExe_1_regToExeQ$enq_x = { coreFix_aluExe_1_dispToRegQ$first[157:153], - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_15_ETC__q288, + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_15_ETC__q278, coreFix_aluExe_1_dispToRegQ$first[131], - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q289, + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q279, coreFix_aluExe_1_dispToRegQ$first[118:86], coreFix_aluExe_1_dispToRegQ$first[61:17], - x__h620994, - x__h620995, + x__h620659, + x__h620660, rob$getOrigPC_1_get, rob$getOrigPredPC_1_get, rob$getOrig_Inst_1_get, coreFix_aluExe_1_dispToRegQ$first[16:0] } ; assign coreFix_aluExe_1_regToExeQ$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12875 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12872 ; assign coreFix_aluExe_1_regToExeQ$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -15581,12 +15446,12 @@ module mkCore(CLK, // submodule coreFix_aluExe_1_rsAlu assign coreFix_aluExe_1_rsAlu$enq_x = - (k__h671729 == 1'd1 && - fetchStage_pipelines_0_canDeq__2932_AND_NOT_fe_ETC___d14265) ? + (k__h671393 == 1'd1 && + fetchStage_pipelines_0_canDeq__2929_AND_NOT_fe_ETC___d14261) ? { fetchStage$pipelines_0_first[199:195], - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d13064, + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d13060, fetchStage$pipelines_0_first[173], - IF_fetchStage_pipelines_0_first__2934_BITS_172_ETC___d13146, + IF_fetchStage_pipelines_0_first__2931_BITS_172_ETC___d13142, fetchStage$pipelines_0_first[160:128], fetchStage$pipelines_0_first[255:232], regRenamingTable$rename_0_getRename, @@ -15596,13 +15461,13 @@ module mkCore(CLK, specTagManager$nextSpecTag, sbAggr$eagerLookup_0_get } : { fetchStage$pipelines_1_first[199:195], - IF_fetchStage_pipelines_1_first__2943_BITS_194_ETC___d13758, - fetchStage_pipelines_1_first__2943_BIT_173_375_ETC___d13842, + IF_fetchStage_pipelines_1_first__2940_BITS_194_ETC___d13754, + fetchStage_pipelines_1_first__2940_BIT_173_375_ETC___d13838, fetchStage$pipelines_1_first[160:128], fetchStage$pipelines_1_first[255:232], regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h686832, + renaming_spec_bits__h686496, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -15675,7 +15540,7 @@ module mkCore(CLK, end assign coreFix_aluExe_1_rsAlu$setRobEnqTime_t = rob$getEnqTime ; assign coreFix_aluExe_1_rsAlu$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12875 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12872 ; assign coreFix_aluExe_1_rsAlu$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -15751,10 +15616,10 @@ module mkCore(CLK, // submodule coreFix_fpuMulDivExe_0_dispToRegQ assign coreFix_fpuMulDivExe_0_dispToRegQ$enq_x = - { CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q291, + { CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q281, coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[65:9] } ; assign coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12875 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12872 ; assign coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -15808,7 +15673,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[224:204], coreFix_fpuMulDivExe_0_regToExeQ$first[11:0] } ; assign coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12875 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12872 ; assign coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -15863,8 +15728,8 @@ module mkCore(CLK, assign coreFix_fpuMulDivExe_0_fpuExec_double_fma$request_put = { coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd2, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10055, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q292, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q293, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q282, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q283, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10828 } ; assign coreFix_fpuMulDivExe_0_fpuExec_double_fma$EN_request_put = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && @@ -15896,7 +15761,7 @@ module mkCore(CLK, assign coreFix_fpuMulDivExe_0_fpuExec_fmaQ$enq_x = coreFix_fpuMulDivExe_0_fpuExec_divQ$enq_x ; assign coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12875 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12872 ; assign coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -15946,7 +15811,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[224:204], coreFix_fpuMulDivExe_0_regToExeQ$first[11:0] } ; assign coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12875 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12872 ; assign coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -15995,7 +15860,7 @@ module mkCore(CLK, assign coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$enq_x = coreFix_fpuMulDivExe_0_fpuExec_divQ$enq_x ; assign coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12875 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12872 ; assign coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -16039,7 +15904,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[224:204], coreFix_fpuMulDivExe_0_regToExeQ$first[11:0] } ; assign coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12875 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12872 ; assign coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -16080,12 +15945,12 @@ module mkCore(CLK, // submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$D_IN = - { x__h606329, - b__h605793 == 64'd0, - a__h605792, + { x__h606020, + b__h605484 == 64'd0, + a__h605483, coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0, - x__h606355, - a__h605792[63], + x__h606046, + a__h605483[63], 8'd0 } ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$ENQ = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && @@ -16100,8 +15965,8 @@ module mkCore(CLK, // submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$D_IN = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? - _theResult___snd__h606341 : - b__h605793 ; + _theResult___snd__h606032 : + b__h605484 ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$ENQ = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd3 && @@ -16114,7 +15979,7 @@ module mkCore(CLK, // submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_IN = - { x__h606941, + { x__h606632, coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$D_OUT[75:0] } ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$ENQ = CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_compute ; @@ -16129,7 +15994,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[224:204], coreFix_fpuMulDivExe_0_regToExeQ$first[11:0] } ; assign coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12875 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12872 ; assign coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -16193,14 +16058,14 @@ module mkCore(CLK, // submodule coreFix_fpuMulDivExe_0_regToExeQ assign coreFix_fpuMulDivExe_0_regToExeQ$enq_x = - { CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q295, + { CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q285, coreFix_fpuMulDivExe_0_dispToRegQ$first[32:12], - x__h484468, - x__h484469, - x__h484470, + x__h484159, + x__h484160, + x__h484161, coreFix_fpuMulDivExe_0_dispToRegQ$first[11:0] } ; assign coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12875 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12872 ; assign coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -16238,18 +16103,18 @@ module mkCore(CLK, // submodule coreFix_fpuMulDivExe_0_rsFpuMulDiv assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$enq_x = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3582_AND__ETC___d14277) ? - { IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d13064, + regRenamingTable_rename_0_canRename__3578_AND__ETC___d14273) ? + { IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d13060, regRenamingTable$rename_0_getRename, rob$enqPort_0_getEnqInstTag, specTagManager$currentSpecBits, fetchStage$pipelines_0_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_0_get } : - { IF_fetchStage_pipelines_1_first__2943_BITS_194_ETC___d13758, + { IF_fetchStage_pipelines_1_first__2940_BITS_194_ETC___d13754, regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h686832, + renaming_spec_bits__h686496, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -16322,7 +16187,7 @@ module mkCore(CLK, end assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRobEnqTime_t = rob$getEnqTime ; assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12875 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12872 ; assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -16348,12 +16213,12 @@ module mkCore(CLK, assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_enq = WILL_FIRE_RL_renameStage_doRenaming && (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3582_AND__ETC___d14277 || - NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d14388 && - regRenamingTable_rename_1_canRename__3704_AND__ETC___d14398 && + regRenamingTable_rename_0_canRename__3578_AND__ETC___d14273 || + NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d14384 && + regRenamingTable_rename_1_canRename__3700_AND__ETC___d14394 && (fetchStage$pipelines_1_first[194:192] == 3'd3 || fetchStage$pipelines_1_first[194:192] == 3'd4) && - NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d14438 && + NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d14434 && coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) ; assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRobEnqTime = 1'd1 ; assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_doDispatch = @@ -16407,8 +16272,8 @@ module mkCore(CLK, // submodule coreFix_memExe_dMem_cache_m_banks_0_cRqMshr assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit_r = - { x__h289512, - x__h289524, + { x__h289204, + x__h289216, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2882, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2886, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2890, @@ -16419,13 +16284,13 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2912, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2916, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2921, - x__h291378, + x__h291070, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2929, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2933, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2937, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2941 } ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq_n = - x__h288079 ; + x__h287771 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n = (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[578:577] == 2'd0) ? @@ -16653,7 +16518,7 @@ module mkCore(CLK, // submodule coreFix_memExe_dMem_cache_m_banks_0_pRqMshr assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit_r = { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2968, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q296 } ; + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q286 } ; assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq_n = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[575:574] ; assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getState_n = @@ -17062,16 +16927,16 @@ module mkCore(CLK, assign coreFix_memExe_dTlb$procReq_req = { coreFix_memExe_regToExeQ$first[192:190], coreFix_memExe_regToExeQ$first[157:140], - coreFix_memExe_lsq$getOrigBE << vaddr__h184061[2:0], - vaddr__h184061, + coreFix_memExe_lsq$getOrigBE << vaddr__h183753[2:0], + vaddr__h183753, coreFix_memExe_lsq$getOrigBE[7] ? - vaddr__h184061[2:0] != 3'd0 : + vaddr__h183753[2:0] != 3'd0 : (coreFix_memExe_lsq$getOrigBE[3] ? - vaddr__h184061[1:0] != 2'd0 : - coreFix_memExe_lsq$getOrigBE[1] && vaddr__h184061[0]), + vaddr__h183753[1:0] != 2'd0 : + coreFix_memExe_lsq$getOrigBE[1] && vaddr__h183753[0]), coreFix_memExe_regToExeQ$first[11:0] } ; assign coreFix_memExe_dTlb$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12875 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12872 ; assign coreFix_memExe_dTlb$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -17098,14 +16963,15 @@ module mkCore(CLK, { l2Tlb$toChildren_rsToC_first[80:0], l2Tlb$toChildren_rsToC_first[82:81] } ; assign coreFix_memExe_dTlb$updateVMInfo_vm = - { prv__h725563, - prv__h725563 != 2'd3 && csrf_vm_mode_sv39_reg, - csrf_mxr_reg, - csrf_sum_reg, - csrf_ppn_reg } ; - assign coreFix_memExe_dTlb$EN_flush = MUX_flush_tlbs$write_1__SEL_1 ; + MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1 ? + MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1 : + MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1 ; + assign coreFix_memExe_dTlb$EN_flush = + WILL_FIRE_RL_prepareCachesAndTlbs && flush_tlbs || + WILL_FIRE_RL_rl_debug_resume ; assign coreFix_memExe_dTlb$EN_updateVMInfo = - MUX_update_vm_info$write_1__SEL_2 ; + WILL_FIRE_RL_prepareCachesAndTlbs && update_vm_info || + WILL_FIRE_RL_rl_debug_resume ; assign coreFix_memExe_dTlb$EN_procReq = CAN_FIRE_RL_coreFix_memExe_doExeMem ; assign coreFix_memExe_dTlb$EN_deqProcResp = @@ -17134,7 +17000,7 @@ module mkCore(CLK, coreFix_memExe_rsMem$dispatchData[71:66], coreFix_memExe_rsMem$dispatchData[20:9] } ; assign coreFix_memExe_dispToRegQ$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12875 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12872 ; assign coreFix_memExe_dispToRegQ$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -17207,44 +17073,44 @@ module mkCore(CLK, // submodule coreFix_memExe_lsq assign coreFix_memExe_lsq$enqLd_dst = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3582_AND__ETC___d14334) ? + regRenamingTable_rename_0_canRename__3578_AND__ETC___d14330) ? regRenamingTable$rename_0_getRename[8:0] : regRenamingTable$rename_1_getRename[8:0] ; assign coreFix_memExe_lsq$enqLd_inst_tag = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3582_AND__ETC___d14334) ? + regRenamingTable_rename_0_canRename__3578_AND__ETC___d14330) ? rob$enqPort_0_getEnqInstTag : rob$enqPort_1_getEnqInstTag ; assign coreFix_memExe_lsq$enqLd_mem_inst = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3582_AND__ETC___d14334) ? + regRenamingTable_rename_0_canRename__3578_AND__ETC___d14330) ? fetchStage$pipelines_0_first[191:174] : fetchStage$pipelines_1_first[191:174] ; assign coreFix_memExe_lsq$enqLd_spec_bits = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3582_AND__ETC___d14334) ? + regRenamingTable_rename_0_canRename__3578_AND__ETC___d14330) ? specTagManager$currentSpecBits : - renaming_spec_bits__h686832 ; + renaming_spec_bits__h686496 ; assign coreFix_memExe_lsq$enqSt_dst = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3582_AND__ETC___d14342) ? + regRenamingTable_rename_0_canRename__3578_AND__ETC___d14338) ? regRenamingTable$rename_0_getRename[8:0] : regRenamingTable$rename_1_getRename[8:0] ; assign coreFix_memExe_lsq$enqSt_inst_tag = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3582_AND__ETC___d14342) ? + regRenamingTable_rename_0_canRename__3578_AND__ETC___d14338) ? rob$enqPort_0_getEnqInstTag : rob$enqPort_1_getEnqInstTag ; assign coreFix_memExe_lsq$enqSt_mem_inst = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3582_AND__ETC___d14342) ? + regRenamingTable_rename_0_canRename__3578_AND__ETC___d14338) ? fetchStage$pipelines_0_first[191:174] : fetchStage$pipelines_1_first[191:174] ; assign coreFix_memExe_lsq$enqSt_spec_bits = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3582_AND__ETC___d14342) ? + regRenamingTable_rename_0_canRename__3578_AND__ETC___d14338) ? specTagManager$currentSpecBits : - renaming_spec_bits__h686832 ; + renaming_spec_bits__h686496 ; assign coreFix_memExe_lsq$getHit_t = MUX_coreFix_memExe_lsq$getHit_1__SEL_1 ? MUX_coreFix_memExe_lsq$getHit_1__VAL_1 : @@ -17280,7 +17146,7 @@ module mkCore(CLK, assign coreFix_memExe_lsq$setAtCommit_1_put = rob$deqPort_1_deq_data[24:19] ; assign coreFix_memExe_lsq$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12875 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12872 ; assign coreFix_memExe_lsq$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -17324,7 +17190,7 @@ module mkCore(CLK, assign coreFix_memExe_lsq$updateData_d = (coreFix_memExe_regToExeQ$first[192:190] == 3'd4) ? coreFix_memExe_regToExeQ$first[75:12] : - shiftData__h184066 ; + shiftData__h183758 ; assign coreFix_memExe_lsq$updateData_t = coreFix_memExe_regToExeQ$first[143:140] ; assign coreFix_memExe_lsq$wakeupLdStalledBySB_sbIdx = @@ -17424,11 +17290,11 @@ module mkCore(CLK, assign coreFix_memExe_regToExeQ$enq_x = { coreFix_memExe_dispToRegQ$first[97:63], coreFix_memExe_dispToRegQ$first[29:12], - x__h183973, - x__h183974, + x__h183665, + x__h183666, coreFix_memExe_dispToRegQ$first[11:0] } ; assign coreFix_memExe_regToExeQ$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12875 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12872 ; assign coreFix_memExe_regToExeQ$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -17676,9 +17542,9 @@ module mkCore(CLK, // submodule coreFix_memExe_rsMem assign coreFix_memExe_rsMem$enq_x = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3582_AND__ETC___d14300) ? + regRenamingTable_rename_0_canRename__3578_AND__ETC___d14296) ? { fetchStage$pipelines_0_first[191:189], - IF_fetchStage_pipelines_0_first__2934_BIT_160__ETC___d14316, + IF_fetchStage_pipelines_0_first__2931_BIT_160__ETC___d14312, regRenamingTable$rename_0_getRename, rob$enqPort_0_getEnqInstTag, specTagManager$currentSpecBits, @@ -17686,10 +17552,10 @@ module mkCore(CLK, specTagManager$nextSpecTag, sbAggr$eagerLookup_0_get } : { fetchStage$pipelines_1_first[191:189], - IF_fetchStage_pipelines_1_first__2943_BIT_160__ETC___d14478, + IF_fetchStage_pipelines_1_first__2940_BIT_160__ETC___d14474, regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h686832, + renaming_spec_bits__h686496, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -17762,7 +17628,7 @@ module mkCore(CLK, end assign coreFix_memExe_rsMem$setRobEnqTime_t = rob$getEnqTime ; assign coreFix_memExe_rsMem$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12875 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12872 ; assign coreFix_memExe_rsMem$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -17917,7 +17783,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd2816 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd30 ; // submodule csrf_mcycle_ehr_data_dummy2_1 @@ -17931,7 +17797,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd2818 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd31 ; // submodule csrf_minstret_ehr_data_dummy2_1 @@ -17949,7 +17815,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd2049 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd7 ; assign csrf_stats_module_writeQ$DEQ = EN_sendDoStats ; assign csrf_stats_module_writeQ$CLR = 1'b0 ; @@ -17960,7 +17826,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd2048 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd6 ; assign csrf_terminate_module_terminateQ$DEQ = EN_coreIndInv_terminate ; assign csrf_terminate_module_terminateQ$CLR = 1'b0 ; @@ -17979,8 +17845,8 @@ module mkCore(CLK, fetchStage$pipelines_0_canDeq || WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2934_BITS_19_ETC___d14262 && - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d13663 || + NOT_fetchStage_pipelines_0_first__2931_BITS_19_ETC___d14258 && + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d13659 || WILL_FIRE_RL_renameStage_doRenaming_SystemInst || WILL_FIRE_RL_renameStage_doRenaming_Trap ; assign epochManager$EN_updatePrevEpoch_1_update = @@ -17988,9 +17854,9 @@ module mkCore(CLK, fetchStage$pipelines_1_canDeq && !epochManager$checkEpoch_1_check || WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d14388 && - NOT_fetchStage_pipelines_1_first__2943_BITS_19_ETC___d14399 && - IF_fetchStage_pipelines_1_first__2943_BITS_194_ETC___d14067 ; + NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d14384 && + NOT_fetchStage_pipelines_1_first__2940_BITS_19_ETC___d14395 && + IF_fetchStage_pipelines_1_first__2940_BITS_194_ETC___d14063 ; assign epochManager$EN_incrementEpoch = WILL_FIRE_RL_commitStage_doCommitTrap_flush && !rob$deqPort_0_deq_data[12] || @@ -18127,18 +17993,16 @@ module mkCore(CLK, l2Tlb$toChildren_rsToC_first[80:0] ; assign fetchStage$iTlbIfc_to_proc_request_put = 64'h0 ; assign fetchStage$iTlbIfc_updateVMInfo_vm = - { csrf_prv_reg, - csrf_prv_reg != 2'd3 && csrf_vm_mode_sv39_reg, - csrf_mxr_reg, - csrf_sum_reg, - csrf_ppn_reg } ; + MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1 ? + MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 : + MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 ; assign fetchStage$mmioIfc_instResp_enq_x = mmio_pRsQ_data_0[65:0] ; assign fetchStage$mmioIfc_setHtifAddrs_fromHost = coreReq_start_fromHostAddr ; assign fetchStage$mmioIfc_setHtifAddrs_toHost = coreReq_start_toHostAddr ; assign fetchStage$perf_req_r = 2'h0 ; assign fetchStage$perf_setStatus_doStats = 1'b0 ; - always@(MUX_fetchStage$redirect_1__SEL_1 or + always@(MUX_csrf_prv_reg$write_1__SEL_2 or MUX_fetchStage$redirect_1__VAL_1 or WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or coreFix_aluExe_1_exeToFinQ$first or @@ -18152,7 +18016,7 @@ module mkCore(CLK, MUX_fetchStage$redirect_1__VAL_6) begin case (1'b1) // synopsys parallel_case - MUX_fetchStage$redirect_1__SEL_1: + MUX_csrf_prv_reg$write_1__SEL_2: fetchStage$redirect_pc = MUX_fetchStage$redirect_1__VAL_1; WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T: fetchStage$redirect_pc = coreFix_aluExe_1_exeToFinQ$first[82:19]; @@ -18201,8 +18065,8 @@ module mkCore(CLK, fetchStage$pipelines_0_canDeq || WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2934_BITS_19_ETC___d14262 && - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d13663 || + NOT_fetchStage_pipelines_0_first__2931_BITS_19_ETC___d14258 && + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d13659 || WILL_FIRE_RL_renameStage_doRenaming_SystemInst || WILL_FIRE_RL_renameStage_doRenaming_Trap ; assign fetchStage$EN_pipelines_1_deq = @@ -18210,12 +18074,15 @@ module mkCore(CLK, fetchStage$pipelines_1_canDeq && !epochManager$checkEpoch_1_check || WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d14388 && - NOT_fetchStage_pipelines_1_first__2943_BITS_19_ETC___d14399 && - IF_fetchStage_pipelines_1_first__2943_BITS_194_ETC___d14067 ; - assign fetchStage$EN_iTlbIfc_flush = MUX_flush_tlbs$write_1__SEL_1 ; + NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d14384 && + NOT_fetchStage_pipelines_1_first__2940_BITS_19_ETC___d14395 && + IF_fetchStage_pipelines_1_first__2940_BITS_194_ETC___d14063 ; + assign fetchStage$EN_iTlbIfc_flush = + WILL_FIRE_RL_prepareCachesAndTlbs && flush_tlbs || + WILL_FIRE_RL_rl_debug_resume ; assign fetchStage$EN_iTlbIfc_updateVMInfo = - MUX_update_vm_info$write_1__SEL_2 ; + WILL_FIRE_RL_prepareCachesAndTlbs && update_vm_info || + WILL_FIRE_RL_rl_debug_resume ; assign fetchStage$EN_iTlbIfc_to_proc_request_put = 1'b0 ; assign fetchStage$EN_iTlbIfc_to_proc_response_get = 1'b0 ; assign fetchStage$EN_iTlbIfc_toParent_rqToP_deq = WILL_FIRE_RL_sendITlbReq ; @@ -18249,14 +18116,14 @@ module mkCore(CLK, assign fetchStage$EN_stop = 1'b0 ; assign fetchStage$EN_setWaitRedirect = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap_4555_BIT_4_4779_AND_com_ETC___d14844 || + commitStage_commitTrap_4549_BIT_4_4679_AND_com_ETC___d14744 || WILL_FIRE_RL_commitStage_doCommitTrap_flush && !rob$deqPort_0_deq_data[12] || WILL_FIRE_RL_renameStage_doRenaming_SystemInst || WILL_FIRE_RL_renameStage_doRenaming_Trap ; assign fetchStage$EN_redirect = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4555_BIT_4_4779_478_ETC___d14881 || + NOT_commitStage_commitTrap_4549_BIT_4_4679_468_ETC___d14781 || WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T || WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T || WILL_FIRE_RL_commitStage_doCommitKilledLd || @@ -18281,9 +18148,17 @@ module mkCore(CLK, MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_1 : MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_2 ; assign l2Tlb$toMem_respLd_enq_x = tlbToMem_respLd_enq_x ; - assign l2Tlb$updateVMInfo_vmD = coreFix_memExe_dTlb$updateVMInfo_vm ; - assign l2Tlb$updateVMInfo_vmI = fetchStage$iTlbIfc_updateVMInfo_vm ; - assign l2Tlb$EN_updateVMInfo = MUX_update_vm_info$write_1__SEL_2 ; + assign l2Tlb$updateVMInfo_vmD = + MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1 ? + MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1 : + MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1 ; + assign l2Tlb$updateVMInfo_vmI = + MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1 ? + MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 : + MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 ; + assign l2Tlb$EN_updateVMInfo = + WILL_FIRE_RL_prepareCachesAndTlbs && update_vm_info || + WILL_FIRE_RL_rl_debug_resume ; assign l2Tlb$EN_toChildren_rqFromC_put = WILL_FIRE_RL_sendDTlbReq || WILL_FIRE_RL_sendITlbReq ; assign l2Tlb$EN_toChildren_rsToC_deq = @@ -18562,11 +18437,11 @@ module mkCore(CLK, assign regRenamingTable$rename_1_claimRename_r = fetchStage$pipelines_1_first[95:69] ; assign regRenamingTable$rename_1_claimRename_sb = - renaming_spec_bits__h686832 ; + renaming_spec_bits__h686496 ; assign regRenamingTable$rename_1_getRename_r = fetchStage$pipelines_1_first[95:69] ; assign regRenamingTable$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12875 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12872 ; assign regRenamingTable$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -18592,8 +18467,8 @@ module mkCore(CLK, assign regRenamingTable$EN_rename_0_claimRename = WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2934_BITS_19_ETC___d14262 && - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d13663 || + NOT_fetchStage_pipelines_0_first__2931_BITS_19_ETC___d14258 && + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d13659 || WILL_FIRE_RL_renameStage_doRenaming_SystemInst ; assign regRenamingTable$EN_rename_1_claimRename = MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2 ; @@ -18816,7 +18691,7 @@ module mkCore(CLK, { fetchStage$pipelines_1_first[387:324], fetchStage$pipelines_1_first[127:96], fetchStage$pipelines_1_first[199:195], - fetchStage_pipelines_1_first__2943_BIT_173_375_ETC___d13842, + fetchStage_pipelines_1_first__2940_BIT_173_375_ETC___d13838, 73'h1280000000000000000, fetchStage$pipelines_1_first[323:260], 5'd0, @@ -18828,11 +18703,11 @@ module mkCore(CLK, fetchStage$pipelines_1_first[194:192] != 3'd3 && fetchStage$pipelines_1_first[194:192] != 3'd4, fetchStage$pipelines_1_first[194:192] != 3'd2 || - fetchStage_pipelines_0_canDeq__2932_AND_regRen_ETC___d14521 || - IF_fetchStage_pipelines_1_first__2943_BITS_191_ETC___d14472, - IF_fetchStage_pipelines_1_first__2943_BITS_194_ETC___d14531, + fetchStage_pipelines_0_canDeq__2929_AND_regRen_ETC___d14517 || + IF_fetchStage_pipelines_1_first__2940_BITS_191_ETC___d14468, + IF_fetchStage_pipelines_1_first__2940_BITS_194_ETC___d14527, 7'd32, - renaming_spec_bits__h686832 } ; + renaming_spec_bits__h686496 } ; assign rob$getOrigPC_0_get_x = coreFix_aluExe_0_dispToRegQ$first[52:41] ; assign rob$getOrigPC_1_get_x = coreFix_aluExe_1_dispToRegQ$first[52:41] ; assign rob$getOrigPC_2_get_x = 12'h0 ; @@ -18975,7 +18850,7 @@ module mkCore(CLK, coreFix_memExe_dTlb$procResp[102:91] ; assign rob$setLSQAtCommitNotified_x = rob$deqPort_0_getDeqInstTag ; assign rob$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12875 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12872 ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or coreFix_aluExe_1_exeToFinQ$first or WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or @@ -19021,8 +18896,8 @@ module mkCore(CLK, assign rob$EN_enqPort_0_enq = WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2934_BITS_19_ETC___d14262 && - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d13663 || + NOT_fetchStage_pipelines_0_first__2931_BITS_19_ETC___d14258 && + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d13659 || WILL_FIRE_RL_renameStage_doRenaming_Trap || WILL_FIRE_RL_renameStage_doRenaming_SystemInst ; assign rob$EN_enqPort_1_enq = @@ -19147,8 +19022,8 @@ module mkCore(CLK, assign sbAggr$EN_setBusy_0_set = WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2934_BITS_19_ETC___d14262 && - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d13663 || + NOT_fetchStage_pipelines_0_first__2931_BITS_19_ETC___d14258 && + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d13659 || WILL_FIRE_RL_renameStage_doRenaming_SystemInst ; assign sbAggr$EN_setBusy_1_set = MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2 ; @@ -19262,8 +19137,8 @@ module mkCore(CLK, assign sbCons$EN_setBusy_0_set = WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2934_BITS_19_ETC___d14262 && - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d13663 || + NOT_fetchStage_pipelines_0_first__2931_BITS_19_ETC___d14258 && + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d13659 || WILL_FIRE_RL_renameStage_doRenaming_SystemInst ; assign sbCons$EN_setBusy_1_set = MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2 ; @@ -19300,7 +19175,7 @@ module mkCore(CLK, // submodule specTagManager assign specTagManager$specUpdate_correctSpeculation_mask = - IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12875 ; + IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12872 ; assign specTagManager$specUpdate_incorrectSpeculation_kill_all = coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ; always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or @@ -19325,9 +19200,9 @@ module mkCore(CLK, end assign specTagManager$EN_claimSpecTag = WILL_FIRE_RL_renameStage_doRenaming && - (fetchStage_pipelines_0_canDeq__2932_AND_specTa_ETC___d14348 || - NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d14388 && - NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d14510) ; + (fetchStage_pipelines_0_canDeq__2929_AND_specTa_ETC___d14344 || + NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d14384 && + NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d14506) ; assign specTagManager$EN_specUpdate_incorrectSpeculation = WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T || WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T || @@ -19335,63 +19210,23 @@ module mkCore(CLK, WILL_FIRE_RL_commitStage_doCommitTrap_flush ; assign specTagManager$EN_specUpdate_correctSpeculation = 1'd1 ; - // submodule v_f_to_TV_0 - assign v_f_to_TV_0$D_IN = - MUX_v_f_to_TV_0$enq_1__SEL_1 ? - MUX_v_f_to_TV_0$enq_1__VAL_1 : - MUX_v_f_to_TV_0$enq_1__VAL_1 ; - assign v_f_to_TV_0$ENQ = - WILL_FIRE_RL_commitStage_doCommitNormalInst && - rob$deqPort_0_canDeq || - WILL_FIRE_RL_commitStage_doCommitTrap_flush || - WILL_FIRE_RL_commitStage_doCommitSystemInst ; - assign v_f_to_TV_0$DEQ = EN_v_to_TV_0_get ; - assign v_f_to_TV_0$CLR = 1'b0 ; - - // submodule v_f_to_TV_1 - assign v_f_to_TV_1$D_IN = - { x__h722429, - rob$deqPort_1_deq_data[282:181], - CASE_robdeqPort_1_deq_data_BITS_180_TO_169_1__ETC__q297, - 6'd10, - rob$deqPort_1_deq_data[161:98], - CASE_robdeqPort_1_deq_data_BITS_97_TO_96_0_ro_ETC__q298, - rob$deqPort_1_deq_data[95:26] } ; - assign v_f_to_TV_1$ENQ = - WILL_FIRE_RL_commitStage_doCommitNormalInst && - rob$deqPort_1_canDeq && - rob$deqPort_1_deq_data[25] && - !rob$deqPort_1_deq_data[18] && - !rob$deqPort_1_deq_data[167] && - rob$deqPort_1_deq_data[186:182] != 5'd0 && - rob$deqPort_1_deq_data[186:182] != 5'd21 && - rob$deqPort_1_deq_data[186:182] != 5'd17 && - rob$deqPort_1_deq_data[186:182] != 5'd18 && - rob$deqPort_1_deq_data[186:182] != 5'd13 && - rob$deqPort_1_deq_data[186:182] != 5'd16 && - rob$deqPort_1_deq_data[186:182] != 5'd15 && - rob$deqPort_1_deq_data[186:182] != 5'd19 && - rob$deqPort_1_deq_data[186:182] != 5'd20 ; - assign v_f_to_TV_1$DEQ = EN_v_to_TV_1_get ; - assign v_f_to_TV_1$CLR = 1'b0 ; - // remaining internal signals module_amoExec instance_amoExec_2(.amoExec_amo_inst(coreFix_memExe_dMem_cache_m_banks_0_processAmo[10:4]), - .amoExec_current_data(curData__h193733), + .amoExec_current_data(curData__h193425), .amoExec_in_data(coreFix_memExe_dMem_cache_m_banks_0_processAmo[74:11]), .amoExec_upper_32_bits(coreFix_memExe_dMem_cache_m_banks_0_processAmo[90]), - .amoExec(n__h195271)); + .amoExec(n__h194963)); module_amoExec instance_amoExec_3(.amoExec_amo_inst({ mmio_pRqQ_data_0[35:32], 3'd0 }), .amoExec_current_data({ 63'd0, - msip__h75940 }), - .amoExec_in_data({ 32'd0, x__h76055 }), + msip__h75632 }), + .amoExec_in_data({ 32'd0, x__h75747 }), .amoExec_upper_32_bits(1'd0), .amoExec(amoExec___d882)); module_basicExec instance_basicExec_6(.basicExec_dInst({ coreFix_aluExe_1_regToExeQ$first[421:417], - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q228, + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q220, { coreFix_aluExe_1_regToExeQ$first[395], - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q229, + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q221, coreFix_aluExe_1_regToExeQ$first[382], coreFix_aluExe_1_regToExeQ$first[381:350] } }), .basicExec_rVal1(coreFix_aluExe_1_regToExeQ$first[304:241]), @@ -19399,11 +19234,11 @@ module mkCore(CLK, .basicExec_pc(coreFix_aluExe_1_regToExeQ$first[176:113]), .basicExec_ppc(coreFix_aluExe_1_regToExeQ$first[112:49]), .basicExec_orig_inst(coreFix_aluExe_1_regToExeQ$first[48:17]), - .basicExec(basicExec___d12107)); + .basicExec(basicExec___d12104)); module_basicExec instance_basicExec_5(.basicExec_dInst({ coreFix_aluExe_0_regToExeQ$first[421:417], - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q231, + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q223, { coreFix_aluExe_0_regToExeQ$first[395], - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_394_ETC__q232, + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_394_ETC__q224, coreFix_aluExe_0_regToExeQ$first[382], coreFix_aluExe_0_regToExeQ$first[381:350] } }), .basicExec_rVal1(coreFix_aluExe_0_regToExeQ$first[304:241]), @@ -19411,13 +19246,13 @@ module mkCore(CLK, .basicExec_pc(coreFix_aluExe_0_regToExeQ$first[176:113]), .basicExec_ppc(coreFix_aluExe_0_regToExeQ$first[112:49]), .basicExec_orig_inst(coreFix_aluExe_0_regToExeQ$first[48:17]), - .basicExec(basicExec___d12781)); + .basicExec(basicExec___d12778)); module_checkForException instance_checkForException_0(.checkForException_dInst({ fetchStage$pipelines_0_first[199:195], - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d13064, + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d13060, { { fetchStage$pipelines_0_first[173], - IF_fetchStage_pipelines_0_first__2934_BITS_172_ETC___d13146 }, + IF_fetchStage_pipelines_0_first__2931_BITS_172_ETC___d13142 }, fetchStage$pipelines_0_first[160], - x_data_imm__h678959 } }), + x_data_imm__h678623 } }), .checkForException_regs({ fetchStage$pipelines_0_first[95], fetchStage$pipelines_0_first[94:89], { fetchStage$pipelines_0_first[88], @@ -19426,12 +19261,12 @@ module mkCore(CLK, fetchStage$pipelines_0_first[80:76], fetchStage$pipelines_0_first[75], fetchStage$pipelines_0_first[74:69] } }), - .checkForException_csrState({ x_decodeInfo_frm__h658907, - r1__read_BITS_13_TO_12___h659092 != + .checkForException_csrState({ x_decodeInfo_frm__h658571, + r1__read_BITS_13_TO_12___h658756 != 2'd0, - { prv__h725519, + { prv__h721530, csrf_tvm_reg, - { r1__read_BIT_20___h659752, + { r1__read_BIT_20___h659416, csrf_tsr_reg, { csrf_mcounteren_cy_reg, csrf_mcounteren_cy_reg && @@ -19442,12 +19277,12 @@ module mkCore(CLK, { csrf_mcounteren_tm_reg, csrf_mcounteren_tm_reg && csrf_scounteren_tm_reg } } } } } }), - .checkForException(checkForException___d13180)); + .checkForException(checkForException___d13176)); module_checkForException instance_checkForException_1(.checkForException_dInst({ fetchStage$pipelines_1_first[199:195], - IF_fetchStage_pipelines_1_first__2943_BITS_194_ETC___d13758, - { fetchStage_pipelines_1_first__2943_BIT_173_375_ETC___d13842, + IF_fetchStage_pipelines_1_first__2940_BITS_194_ETC___d13754, + { fetchStage_pipelines_1_first__2940_BIT_173_375_ETC___d13838, fetchStage$pipelines_1_first[160], - x_data_imm__h694502 } }), + x_data_imm__h694166 } }), .checkForException_regs({ fetchStage$pipelines_1_first[95], fetchStage$pipelines_1_first[94:89], { fetchStage$pipelines_1_first[88], @@ -19456,12 +19291,12 @@ module mkCore(CLK, fetchStage$pipelines_1_first[80:76], fetchStage$pipelines_1_first[75], fetchStage$pipelines_1_first[74:69] } }), - .checkForException_csrState({ x_decodeInfo_frm__h658907, - r1__read_BITS_13_TO_12___h659092 != + .checkForException_csrState({ x_decodeInfo_frm__h658571, + r1__read_BITS_13_TO_12___h658756 != 2'd0, - { prv__h725519, + { prv__h721530, csrf_tvm_reg, - { r1__read_BIT_20___h659752, + { r1__read_BIT_20___h659416, csrf_tsr_reg, { csrf_mcounteren_cy_reg, csrf_mcounteren_cy_reg && @@ -19472,1200 +19307,1200 @@ module mkCore(CLK, { csrf_mcounteren_tm_reg, csrf_mcounteren_tm_reg && csrf_scounteren_tm_reg } } } } } }), - .checkForException(checkForException___d13863)); + .checkForException(checkForException___d13859)); module_execFpuSimple instance_execFpuSimple_4(.execFpuSimple_fpu_inst({ coreFix_fpuMulDivExe_0_regToExeQ$first[233:229], - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q253, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q243, coreFix_fpuMulDivExe_0_regToExeQ$first[225] }), - .execFpuSimple_rVal1(rVal1__h484562), - .execFpuSimple_rVal2(rVal2__h484563), + .execFpuSimple_rVal1(rVal1__h484253), + .execFpuSimple_rVal2(rVal2__h484254), .execFpuSimple(execFpuSimple___d11167)); - assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q29 = + assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q21 = _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d4345 ? - _theResult___snd__h356557 : - _theResult____h348383 ; - assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q64 = + _theResult___snd__h356248 : + _theResult____h348074 ; + assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q56 = _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5737 ? - _theResult___snd__h402254 : - _theResult____h394082 ; - assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q99 = + _theResult___snd__h401945 : + _theResult____h393773 ; + assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q91 = _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7129 ? - _theResult___snd__h447949 : - _theResult____h439777 ; - assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q138 = + _theResult___snd__h447640 : + _theResult____h439468 ; + assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q130 = _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d9008 ? - _theResult___snd__h513974 : - _theResult____h505675 ; - assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q155 = + _theResult___snd__h513665 : + _theResult____h505366 ; + assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q147 = _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d9723 ? - _theResult___snd__h592131 : - _theResult____h583832 ; - assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q178 = + _theResult___snd__h591822 : + _theResult____h583523 ; + assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q170 = _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10493 ? - _theResult___snd__h552827 : - _theResult____h544528 ; - assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q109 = + _theResult___snd__h552518 : + _theResult____h544219 ; + assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q101 = _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7680 ? - _theResult___snd__h465715 : - _theResult____h457414 ; - assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q39 = + _theResult___snd__h465406 : + _theResult____h457105 ; + assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q31 = _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d4896 ? - _theResult___snd__h374323 : - _theResult____h366022 ; - assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q74 = + _theResult___snd__h374014 : + _theResult____h365713 ; + assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q66 = _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6288 ? - _theResult___snd__h420020 : - _theResult____h411719 ; - assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q134 = + _theResult___snd__h419711 : + _theResult____h411410 ; + assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q126 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8696 ? - _theResult___snd__h504323 : + _theResult___snd__h504014 : 57'd0 ; - assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q141 = + assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q133 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9058 ? - _theResult___snd__h504323 : - _theResult___snd__h522728 ; - assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q151 = + _theResult___snd__h504014 : + _theResult___snd__h522419 ; + assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q143 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9426 ? - _theResult___snd__h582480 : + _theResult___snd__h582171 : 57'd0 ; - assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q158 = + assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q150 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9773 ? - _theResult___snd__h582480 : - _theResult___snd__h600885 ; - assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q174 = + _theResult___snd__h582171 : + _theResult___snd__h600576 ; + assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q166 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10196 ? - _theResult___snd__h543176 : + _theResult___snd__h542867 : 57'd0 ; - assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q181 = + assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q173 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10543 ? - _theResult___snd__h543176 : - _theResult___snd__h561581 ; - assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q101 = - _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7360 ? - _theResult___snd__h456531 : - 57'd0 ; - assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q114 = + _theResult___snd__h542867 : + _theResult___snd__h561272 ; + assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q106 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7753 ? - _theResult___snd__h456531 : - _theResult___snd__h474321 ; - assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q31 = + _theResult___snd__h456222 : + _theResult___snd__h474012 ; + assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q23 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4576 ? - _theResult___snd__h365139 : + _theResult___snd__h364830 : 57'd0 ; - assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q44 = + assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q36 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4969 ? - _theResult___snd__h365139 : - _theResult___snd__h382929 ; - assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q66 = + _theResult___snd__h364830 : + _theResult___snd__h382620 ; + assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q58 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5968 ? - _theResult___snd__h410836 : + _theResult___snd__h410527 : 57'd0 ; - assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q79 = + assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q71 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6361 ? - _theResult___snd__h410836 : - _theResult___snd__h428626 ; + _theResult___snd__h410527 : + _theResult___snd__h428317 ; + assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q93 = + _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7360 ? + _theResult___snd__h456222 : + 57'd0 ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5165 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4109 ? - ((_theResult___fst_exp__h356494 == 8'd255) ? + ((_theResult___fst_exp__h356185 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5150) : - ((_theResult___fst_exp__h365150 == 8'd255) ? + ((_theResult___fst_exp__h364841 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5163) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5215 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4109 ? - ((_theResult___fst_exp__h356494 == 8'd255) ? + ((_theResult___fst_exp__h356185 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5206) : - ((_theResult___fst_exp__h365150 == 8'd255) ? + ((_theResult___fst_exp__h364841 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5213) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6557 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5501 ? - ((_theResult___fst_exp__h402191 == 8'd255) ? + ((_theResult___fst_exp__h401882 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6542) : - ((_theResult___fst_exp__h410847 == 8'd255) ? + ((_theResult___fst_exp__h410538 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6555) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6607 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5501 ? - ((_theResult___fst_exp__h402191 == 8'd255) ? + ((_theResult___fst_exp__h401882 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6598) : - ((_theResult___fst_exp__h410847 == 8'd255) ? + ((_theResult___fst_exp__h410538 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6605) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7949 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6893 ? - ((_theResult___fst_exp__h447886 == 8'd255) ? + ((_theResult___fst_exp__h447577 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7934) : - ((_theResult___fst_exp__h456542 == 8'd255) ? + ((_theResult___fst_exp__h456233 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7947) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7999 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6893 ? - ((_theResult___fst_exp__h447886 == 8'd255) ? + ((_theResult___fst_exp__h447577 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7990) : - ((_theResult___fst_exp__h456542 == 8'd255) ? + ((_theResult___fst_exp__h456233 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7997) ; assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4343 = - (_theResult____h348383[56] ? + (_theResult____h348074[56] ? 6'd0 : - (_theResult____h348383[55] ? + (_theResult____h348074[55] ? 6'd1 : - (_theResult____h348383[54] ? + (_theResult____h348074[54] ? 6'd2 : - (_theResult____h348383[53] ? + (_theResult____h348074[53] ? 6'd3 : - (_theResult____h348383[52] ? + (_theResult____h348074[52] ? 6'd4 : - (_theResult____h348383[51] ? + (_theResult____h348074[51] ? 6'd5 : - (_theResult____h348383[50] ? + (_theResult____h348074[50] ? 6'd6 : - (_theResult____h348383[49] ? + (_theResult____h348074[49] ? 6'd7 : - (_theResult____h348383[48] ? + (_theResult____h348074[48] ? 6'd8 : - (_theResult____h348383[47] ? + (_theResult____h348074[47] ? 6'd9 : - (_theResult____h348383[46] ? + (_theResult____h348074[46] ? 6'd10 : - (_theResult____h348383[45] ? + (_theResult____h348074[45] ? 6'd11 : - (_theResult____h348383[44] ? + (_theResult____h348074[44] ? 6'd12 : - (_theResult____h348383[43] ? + (_theResult____h348074[43] ? 6'd13 : - (_theResult____h348383[42] ? + (_theResult____h348074[42] ? 6'd14 : - (_theResult____h348383[41] ? + (_theResult____h348074[41] ? 6'd15 : - (_theResult____h348383[40] ? + (_theResult____h348074[40] ? 6'd16 : - (_theResult____h348383[39] ? + (_theResult____h348074[39] ? 6'd17 : - (_theResult____h348383[38] ? + (_theResult____h348074[38] ? 6'd18 : - (_theResult____h348383[37] ? + (_theResult____h348074[37] ? 6'd19 : - (_theResult____h348383[36] ? + (_theResult____h348074[36] ? 6'd20 : - (_theResult____h348383[35] ? + (_theResult____h348074[35] ? 6'd21 : - (_theResult____h348383[34] ? + (_theResult____h348074[34] ? 6'd22 : - (_theResult____h348383[33] ? + (_theResult____h348074[33] ? 6'd23 : - (_theResult____h348383[32] ? + (_theResult____h348074[32] ? 6'd24 : - (_theResult____h348383[31] ? + (_theResult____h348074[31] ? 6'd25 : - (_theResult____h348383[30] ? + (_theResult____h348074[30] ? 6'd26 : - (_theResult____h348383[29] ? + (_theResult____h348074[29] ? 6'd27 : - (_theResult____h348383[28] ? + (_theResult____h348074[28] ? 6'd28 : - (_theResult____h348383[27] ? + (_theResult____h348074[27] ? 6'd29 : - (_theResult____h348383[26] ? + (_theResult____h348074[26] ? 6'd30 : - (_theResult____h348383[25] ? + (_theResult____h348074[25] ? 6'd31 : - (_theResult____h348383[24] ? + (_theResult____h348074[24] ? 6'd32 : - (_theResult____h348383[23] ? + (_theResult____h348074[23] ? 6'd33 : - (_theResult____h348383[22] ? + (_theResult____h348074[22] ? 6'd34 : - (_theResult____h348383[21] ? + (_theResult____h348074[21] ? 6'd35 : - (_theResult____h348383[20] ? + (_theResult____h348074[20] ? 6'd36 : - (_theResult____h348383[19] ? + (_theResult____h348074[19] ? 6'd37 : - (_theResult____h348383[18] ? + (_theResult____h348074[18] ? 6'd38 : - (_theResult____h348383[17] ? + (_theResult____h348074[17] ? 6'd39 : - (_theResult____h348383[16] ? + (_theResult____h348074[16] ? 6'd40 : - (_theResult____h348383[15] ? + (_theResult____h348074[15] ? 6'd41 : - (_theResult____h348383[14] ? + (_theResult____h348074[14] ? 6'd42 : - (_theResult____h348383[13] ? + (_theResult____h348074[13] ? 6'd43 : - (_theResult____h348383[12] ? + (_theResult____h348074[12] ? 6'd44 : - (_theResult____h348383[11] ? + (_theResult____h348074[11] ? 6'd45 : - (_theResult____h348383[10] ? + (_theResult____h348074[10] ? 6'd46 : - (_theResult____h348383[9] ? + (_theResult____h348074[9] ? 6'd47 : - (_theResult____h348383[8] ? + (_theResult____h348074[8] ? 6'd48 : - (_theResult____h348383[7] ? + (_theResult____h348074[7] ? 6'd49 : - (_theResult____h348383[6] ? + (_theResult____h348074[6] ? 6'd50 : - (_theResult____h348383[5] ? + (_theResult____h348074[5] ? 6'd51 : - (_theResult____h348383[4] ? + (_theResult____h348074[4] ? 6'd52 : - (_theResult____h348383[3] ? + (_theResult____h348074[3] ? 6'd53 : - (_theResult____h348383[2] ? + (_theResult____h348074[2] ? 6'd54 : - (_theResult____h348383[1] ? + (_theResult____h348074[1] ? 6'd55 : - (_theResult____h348383[0] ? + (_theResult____h348074[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5735 = - (_theResult____h394082[56] ? + (_theResult____h393773[56] ? 6'd0 : - (_theResult____h394082[55] ? + (_theResult____h393773[55] ? 6'd1 : - (_theResult____h394082[54] ? + (_theResult____h393773[54] ? 6'd2 : - (_theResult____h394082[53] ? + (_theResult____h393773[53] ? 6'd3 : - (_theResult____h394082[52] ? + (_theResult____h393773[52] ? 6'd4 : - (_theResult____h394082[51] ? + (_theResult____h393773[51] ? 6'd5 : - (_theResult____h394082[50] ? + (_theResult____h393773[50] ? 6'd6 : - (_theResult____h394082[49] ? + (_theResult____h393773[49] ? 6'd7 : - (_theResult____h394082[48] ? + (_theResult____h393773[48] ? 6'd8 : - (_theResult____h394082[47] ? + (_theResult____h393773[47] ? 6'd9 : - (_theResult____h394082[46] ? + (_theResult____h393773[46] ? 6'd10 : - (_theResult____h394082[45] ? + (_theResult____h393773[45] ? 6'd11 : - (_theResult____h394082[44] ? + (_theResult____h393773[44] ? 6'd12 : - (_theResult____h394082[43] ? + (_theResult____h393773[43] ? 6'd13 : - (_theResult____h394082[42] ? + (_theResult____h393773[42] ? 6'd14 : - (_theResult____h394082[41] ? + (_theResult____h393773[41] ? 6'd15 : - (_theResult____h394082[40] ? + (_theResult____h393773[40] ? 6'd16 : - (_theResult____h394082[39] ? + (_theResult____h393773[39] ? 6'd17 : - (_theResult____h394082[38] ? + (_theResult____h393773[38] ? 6'd18 : - (_theResult____h394082[37] ? + (_theResult____h393773[37] ? 6'd19 : - (_theResult____h394082[36] ? + (_theResult____h393773[36] ? 6'd20 : - (_theResult____h394082[35] ? + (_theResult____h393773[35] ? 6'd21 : - (_theResult____h394082[34] ? + (_theResult____h393773[34] ? 6'd22 : - (_theResult____h394082[33] ? + (_theResult____h393773[33] ? 6'd23 : - (_theResult____h394082[32] ? + (_theResult____h393773[32] ? 6'd24 : - (_theResult____h394082[31] ? + (_theResult____h393773[31] ? 6'd25 : - (_theResult____h394082[30] ? + (_theResult____h393773[30] ? 6'd26 : - (_theResult____h394082[29] ? + (_theResult____h393773[29] ? 6'd27 : - (_theResult____h394082[28] ? + (_theResult____h393773[28] ? 6'd28 : - (_theResult____h394082[27] ? + (_theResult____h393773[27] ? 6'd29 : - (_theResult____h394082[26] ? + (_theResult____h393773[26] ? 6'd30 : - (_theResult____h394082[25] ? + (_theResult____h393773[25] ? 6'd31 : - (_theResult____h394082[24] ? + (_theResult____h393773[24] ? 6'd32 : - (_theResult____h394082[23] ? + (_theResult____h393773[23] ? 6'd33 : - (_theResult____h394082[22] ? + (_theResult____h393773[22] ? 6'd34 : - (_theResult____h394082[21] ? + (_theResult____h393773[21] ? 6'd35 : - (_theResult____h394082[20] ? + (_theResult____h393773[20] ? 6'd36 : - (_theResult____h394082[19] ? + (_theResult____h393773[19] ? 6'd37 : - (_theResult____h394082[18] ? + (_theResult____h393773[18] ? 6'd38 : - (_theResult____h394082[17] ? + (_theResult____h393773[17] ? 6'd39 : - (_theResult____h394082[16] ? + (_theResult____h393773[16] ? 6'd40 : - (_theResult____h394082[15] ? + (_theResult____h393773[15] ? 6'd41 : - (_theResult____h394082[14] ? + (_theResult____h393773[14] ? 6'd42 : - (_theResult____h394082[13] ? + (_theResult____h393773[13] ? 6'd43 : - (_theResult____h394082[12] ? + (_theResult____h393773[12] ? 6'd44 : - (_theResult____h394082[11] ? + (_theResult____h393773[11] ? 6'd45 : - (_theResult____h394082[10] ? + (_theResult____h393773[10] ? 6'd46 : - (_theResult____h394082[9] ? + (_theResult____h393773[9] ? 6'd47 : - (_theResult____h394082[8] ? + (_theResult____h393773[8] ? 6'd48 : - (_theResult____h394082[7] ? + (_theResult____h393773[7] ? 6'd49 : - (_theResult____h394082[6] ? + (_theResult____h393773[6] ? 6'd50 : - (_theResult____h394082[5] ? + (_theResult____h393773[5] ? 6'd51 : - (_theResult____h394082[4] ? + (_theResult____h393773[4] ? 6'd52 : - (_theResult____h394082[3] ? + (_theResult____h393773[3] ? 6'd53 : - (_theResult____h394082[2] ? + (_theResult____h393773[2] ? 6'd54 : - (_theResult____h394082[1] ? + (_theResult____h393773[1] ? 6'd55 : - (_theResult____h394082[0] ? + (_theResult____h393773[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7127 = - (_theResult____h439777[56] ? + (_theResult____h439468[56] ? 6'd0 : - (_theResult____h439777[55] ? + (_theResult____h439468[55] ? 6'd1 : - (_theResult____h439777[54] ? + (_theResult____h439468[54] ? 6'd2 : - (_theResult____h439777[53] ? + (_theResult____h439468[53] ? 6'd3 : - (_theResult____h439777[52] ? + (_theResult____h439468[52] ? 6'd4 : - (_theResult____h439777[51] ? + (_theResult____h439468[51] ? 6'd5 : - (_theResult____h439777[50] ? + (_theResult____h439468[50] ? 6'd6 : - (_theResult____h439777[49] ? + (_theResult____h439468[49] ? 6'd7 : - (_theResult____h439777[48] ? + (_theResult____h439468[48] ? 6'd8 : - (_theResult____h439777[47] ? + (_theResult____h439468[47] ? 6'd9 : - (_theResult____h439777[46] ? + (_theResult____h439468[46] ? 6'd10 : - (_theResult____h439777[45] ? + (_theResult____h439468[45] ? 6'd11 : - (_theResult____h439777[44] ? + (_theResult____h439468[44] ? 6'd12 : - (_theResult____h439777[43] ? + (_theResult____h439468[43] ? 6'd13 : - (_theResult____h439777[42] ? + (_theResult____h439468[42] ? 6'd14 : - (_theResult____h439777[41] ? + (_theResult____h439468[41] ? 6'd15 : - (_theResult____h439777[40] ? + (_theResult____h439468[40] ? 6'd16 : - (_theResult____h439777[39] ? + (_theResult____h439468[39] ? 6'd17 : - (_theResult____h439777[38] ? + (_theResult____h439468[38] ? 6'd18 : - (_theResult____h439777[37] ? + (_theResult____h439468[37] ? 6'd19 : - (_theResult____h439777[36] ? + (_theResult____h439468[36] ? 6'd20 : - (_theResult____h439777[35] ? + (_theResult____h439468[35] ? 6'd21 : - (_theResult____h439777[34] ? + (_theResult____h439468[34] ? 6'd22 : - (_theResult____h439777[33] ? + (_theResult____h439468[33] ? 6'd23 : - (_theResult____h439777[32] ? + (_theResult____h439468[32] ? 6'd24 : - (_theResult____h439777[31] ? + (_theResult____h439468[31] ? 6'd25 : - (_theResult____h439777[30] ? + (_theResult____h439468[30] ? 6'd26 : - (_theResult____h439777[29] ? + (_theResult____h439468[29] ? 6'd27 : - (_theResult____h439777[28] ? + (_theResult____h439468[28] ? 6'd28 : - (_theResult____h439777[27] ? + (_theResult____h439468[27] ? 6'd29 : - (_theResult____h439777[26] ? + (_theResult____h439468[26] ? 6'd30 : - (_theResult____h439777[25] ? + (_theResult____h439468[25] ? 6'd31 : - (_theResult____h439777[24] ? + (_theResult____h439468[24] ? 6'd32 : - (_theResult____h439777[23] ? + (_theResult____h439468[23] ? 6'd33 : - (_theResult____h439777[22] ? + (_theResult____h439468[22] ? 6'd34 : - (_theResult____h439777[21] ? + (_theResult____h439468[21] ? 6'd35 : - (_theResult____h439777[20] ? + (_theResult____h439468[20] ? 6'd36 : - (_theResult____h439777[19] ? + (_theResult____h439468[19] ? 6'd37 : - (_theResult____h439777[18] ? + (_theResult____h439468[18] ? 6'd38 : - (_theResult____h439777[17] ? + (_theResult____h439468[17] ? 6'd39 : - (_theResult____h439777[16] ? + (_theResult____h439468[16] ? 6'd40 : - (_theResult____h439777[15] ? + (_theResult____h439468[15] ? 6'd41 : - (_theResult____h439777[14] ? + (_theResult____h439468[14] ? 6'd42 : - (_theResult____h439777[13] ? + (_theResult____h439468[13] ? 6'd43 : - (_theResult____h439777[12] ? + (_theResult____h439468[12] ? 6'd44 : - (_theResult____h439777[11] ? + (_theResult____h439468[11] ? 6'd45 : - (_theResult____h439777[10] ? + (_theResult____h439468[10] ? 6'd46 : - (_theResult____h439777[9] ? + (_theResult____h439468[9] ? 6'd47 : - (_theResult____h439777[8] ? + (_theResult____h439468[8] ? 6'd48 : - (_theResult____h439777[7] ? + (_theResult____h439468[7] ? 6'd49 : - (_theResult____h439777[6] ? + (_theResult____h439468[6] ? 6'd50 : - (_theResult____h439777[5] ? + (_theResult____h439468[5] ? 6'd51 : - (_theResult____h439777[4] ? + (_theResult____h439468[4] ? 6'd52 : - (_theResult____h439777[3] ? + (_theResult____h439468[3] ? 6'd53 : - (_theResult____h439777[2] ? + (_theResult____h439468[2] ? 6'd54 : - (_theResult____h439777[1] ? + (_theResult____h439468[1] ? 6'd55 : - (_theResult____h439777[0] ? + (_theResult____h439468[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10491 = - (_theResult____h544528[56] ? + (_theResult____h544219[56] ? 6'd0 : - (_theResult____h544528[55] ? + (_theResult____h544219[55] ? 6'd1 : - (_theResult____h544528[54] ? + (_theResult____h544219[54] ? 6'd2 : - (_theResult____h544528[53] ? + (_theResult____h544219[53] ? 6'd3 : - (_theResult____h544528[52] ? + (_theResult____h544219[52] ? 6'd4 : - (_theResult____h544528[51] ? + (_theResult____h544219[51] ? 6'd5 : - (_theResult____h544528[50] ? + (_theResult____h544219[50] ? 6'd6 : - (_theResult____h544528[49] ? + (_theResult____h544219[49] ? 6'd7 : - (_theResult____h544528[48] ? + (_theResult____h544219[48] ? 6'd8 : - (_theResult____h544528[47] ? + (_theResult____h544219[47] ? 6'd9 : - (_theResult____h544528[46] ? + (_theResult____h544219[46] ? 6'd10 : - (_theResult____h544528[45] ? + (_theResult____h544219[45] ? 6'd11 : - (_theResult____h544528[44] ? + (_theResult____h544219[44] ? 6'd12 : - (_theResult____h544528[43] ? + (_theResult____h544219[43] ? 6'd13 : - (_theResult____h544528[42] ? + (_theResult____h544219[42] ? 6'd14 : - (_theResult____h544528[41] ? + (_theResult____h544219[41] ? 6'd15 : - (_theResult____h544528[40] ? + (_theResult____h544219[40] ? 6'd16 : - (_theResult____h544528[39] ? + (_theResult____h544219[39] ? 6'd17 : - (_theResult____h544528[38] ? + (_theResult____h544219[38] ? 6'd18 : - (_theResult____h544528[37] ? + (_theResult____h544219[37] ? 6'd19 : - (_theResult____h544528[36] ? + (_theResult____h544219[36] ? 6'd20 : - (_theResult____h544528[35] ? + (_theResult____h544219[35] ? 6'd21 : - (_theResult____h544528[34] ? + (_theResult____h544219[34] ? 6'd22 : - (_theResult____h544528[33] ? + (_theResult____h544219[33] ? 6'd23 : - (_theResult____h544528[32] ? + (_theResult____h544219[32] ? 6'd24 : - (_theResult____h544528[31] ? + (_theResult____h544219[31] ? 6'd25 : - (_theResult____h544528[30] ? + (_theResult____h544219[30] ? 6'd26 : - (_theResult____h544528[29] ? + (_theResult____h544219[29] ? 6'd27 : - (_theResult____h544528[28] ? + (_theResult____h544219[28] ? 6'd28 : - (_theResult____h544528[27] ? + (_theResult____h544219[27] ? 6'd29 : - (_theResult____h544528[26] ? + (_theResult____h544219[26] ? 6'd30 : - (_theResult____h544528[25] ? + (_theResult____h544219[25] ? 6'd31 : - (_theResult____h544528[24] ? + (_theResult____h544219[24] ? 6'd32 : - (_theResult____h544528[23] ? + (_theResult____h544219[23] ? 6'd33 : - (_theResult____h544528[22] ? + (_theResult____h544219[22] ? 6'd34 : - (_theResult____h544528[21] ? + (_theResult____h544219[21] ? 6'd35 : - (_theResult____h544528[20] ? + (_theResult____h544219[20] ? 6'd36 : - (_theResult____h544528[19] ? + (_theResult____h544219[19] ? 6'd37 : - (_theResult____h544528[18] ? + (_theResult____h544219[18] ? 6'd38 : - (_theResult____h544528[17] ? + (_theResult____h544219[17] ? 6'd39 : - (_theResult____h544528[16] ? + (_theResult____h544219[16] ? 6'd40 : - (_theResult____h544528[15] ? + (_theResult____h544219[15] ? 6'd41 : - (_theResult____h544528[14] ? + (_theResult____h544219[14] ? 6'd42 : - (_theResult____h544528[13] ? + (_theResult____h544219[13] ? 6'd43 : - (_theResult____h544528[12] ? + (_theResult____h544219[12] ? 6'd44 : - (_theResult____h544528[11] ? + (_theResult____h544219[11] ? 6'd45 : - (_theResult____h544528[10] ? + (_theResult____h544219[10] ? 6'd46 : - (_theResult____h544528[9] ? + (_theResult____h544219[9] ? 6'd47 : - (_theResult____h544528[8] ? + (_theResult____h544219[8] ? 6'd48 : - (_theResult____h544528[7] ? + (_theResult____h544219[7] ? 6'd49 : - (_theResult____h544528[6] ? + (_theResult____h544219[6] ? 6'd50 : - (_theResult____h544528[5] ? + (_theResult____h544219[5] ? 6'd51 : - (_theResult____h544528[4] ? + (_theResult____h544219[4] ? 6'd52 : - (_theResult____h544528[3] ? + (_theResult____h544219[3] ? 6'd53 : - (_theResult____h544528[2] ? + (_theResult____h544219[2] ? 6'd54 : - (_theResult____h544528[1] ? + (_theResult____h544219[1] ? 6'd55 : - (_theResult____h544528[0] ? + (_theResult____h544219[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9006 = - (_theResult____h505675[56] ? + (_theResult____h505366[56] ? 6'd0 : - (_theResult____h505675[55] ? + (_theResult____h505366[55] ? 6'd1 : - (_theResult____h505675[54] ? + (_theResult____h505366[54] ? 6'd2 : - (_theResult____h505675[53] ? + (_theResult____h505366[53] ? 6'd3 : - (_theResult____h505675[52] ? + (_theResult____h505366[52] ? 6'd4 : - (_theResult____h505675[51] ? + (_theResult____h505366[51] ? 6'd5 : - (_theResult____h505675[50] ? + (_theResult____h505366[50] ? 6'd6 : - (_theResult____h505675[49] ? + (_theResult____h505366[49] ? 6'd7 : - (_theResult____h505675[48] ? + (_theResult____h505366[48] ? 6'd8 : - (_theResult____h505675[47] ? + (_theResult____h505366[47] ? 6'd9 : - (_theResult____h505675[46] ? + (_theResult____h505366[46] ? 6'd10 : - (_theResult____h505675[45] ? + (_theResult____h505366[45] ? 6'd11 : - (_theResult____h505675[44] ? + (_theResult____h505366[44] ? 6'd12 : - (_theResult____h505675[43] ? + (_theResult____h505366[43] ? 6'd13 : - (_theResult____h505675[42] ? + (_theResult____h505366[42] ? 6'd14 : - (_theResult____h505675[41] ? + (_theResult____h505366[41] ? 6'd15 : - (_theResult____h505675[40] ? + (_theResult____h505366[40] ? 6'd16 : - (_theResult____h505675[39] ? + (_theResult____h505366[39] ? 6'd17 : - (_theResult____h505675[38] ? + (_theResult____h505366[38] ? 6'd18 : - (_theResult____h505675[37] ? + (_theResult____h505366[37] ? 6'd19 : - (_theResult____h505675[36] ? + (_theResult____h505366[36] ? 6'd20 : - (_theResult____h505675[35] ? + (_theResult____h505366[35] ? 6'd21 : - (_theResult____h505675[34] ? + (_theResult____h505366[34] ? 6'd22 : - (_theResult____h505675[33] ? + (_theResult____h505366[33] ? 6'd23 : - (_theResult____h505675[32] ? + (_theResult____h505366[32] ? 6'd24 : - (_theResult____h505675[31] ? + (_theResult____h505366[31] ? 6'd25 : - (_theResult____h505675[30] ? + (_theResult____h505366[30] ? 6'd26 : - (_theResult____h505675[29] ? + (_theResult____h505366[29] ? 6'd27 : - (_theResult____h505675[28] ? + (_theResult____h505366[28] ? 6'd28 : - (_theResult____h505675[27] ? + (_theResult____h505366[27] ? 6'd29 : - (_theResult____h505675[26] ? + (_theResult____h505366[26] ? 6'd30 : - (_theResult____h505675[25] ? + (_theResult____h505366[25] ? 6'd31 : - (_theResult____h505675[24] ? + (_theResult____h505366[24] ? 6'd32 : - (_theResult____h505675[23] ? + (_theResult____h505366[23] ? 6'd33 : - (_theResult____h505675[22] ? + (_theResult____h505366[22] ? 6'd34 : - (_theResult____h505675[21] ? + (_theResult____h505366[21] ? 6'd35 : - (_theResult____h505675[20] ? + (_theResult____h505366[20] ? 6'd36 : - (_theResult____h505675[19] ? + (_theResult____h505366[19] ? 6'd37 : - (_theResult____h505675[18] ? + (_theResult____h505366[18] ? 6'd38 : - (_theResult____h505675[17] ? + (_theResult____h505366[17] ? 6'd39 : - (_theResult____h505675[16] ? + (_theResult____h505366[16] ? 6'd40 : - (_theResult____h505675[15] ? + (_theResult____h505366[15] ? 6'd41 : - (_theResult____h505675[14] ? + (_theResult____h505366[14] ? 6'd42 : - (_theResult____h505675[13] ? + (_theResult____h505366[13] ? 6'd43 : - (_theResult____h505675[12] ? + (_theResult____h505366[12] ? 6'd44 : - (_theResult____h505675[11] ? + (_theResult____h505366[11] ? 6'd45 : - (_theResult____h505675[10] ? + (_theResult____h505366[10] ? 6'd46 : - (_theResult____h505675[9] ? + (_theResult____h505366[9] ? 6'd47 : - (_theResult____h505675[8] ? + (_theResult____h505366[8] ? 6'd48 : - (_theResult____h505675[7] ? + (_theResult____h505366[7] ? 6'd49 : - (_theResult____h505675[6] ? + (_theResult____h505366[6] ? 6'd50 : - (_theResult____h505675[5] ? + (_theResult____h505366[5] ? 6'd51 : - (_theResult____h505675[4] ? + (_theResult____h505366[4] ? 6'd52 : - (_theResult____h505675[3] ? + (_theResult____h505366[3] ? 6'd53 : - (_theResult____h505675[2] ? + (_theResult____h505366[2] ? 6'd54 : - (_theResult____h505675[1] ? + (_theResult____h505366[1] ? 6'd55 : - (_theResult____h505675[0] ? + (_theResult____h505366[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9721 = - (_theResult____h583832[56] ? + (_theResult____h583523[56] ? 6'd0 : - (_theResult____h583832[55] ? + (_theResult____h583523[55] ? 6'd1 : - (_theResult____h583832[54] ? + (_theResult____h583523[54] ? 6'd2 : - (_theResult____h583832[53] ? + (_theResult____h583523[53] ? 6'd3 : - (_theResult____h583832[52] ? + (_theResult____h583523[52] ? 6'd4 : - (_theResult____h583832[51] ? + (_theResult____h583523[51] ? 6'd5 : - (_theResult____h583832[50] ? + (_theResult____h583523[50] ? 6'd6 : - (_theResult____h583832[49] ? + (_theResult____h583523[49] ? 6'd7 : - (_theResult____h583832[48] ? + (_theResult____h583523[48] ? 6'd8 : - (_theResult____h583832[47] ? + (_theResult____h583523[47] ? 6'd9 : - (_theResult____h583832[46] ? + (_theResult____h583523[46] ? 6'd10 : - (_theResult____h583832[45] ? + (_theResult____h583523[45] ? 6'd11 : - (_theResult____h583832[44] ? + (_theResult____h583523[44] ? 6'd12 : - (_theResult____h583832[43] ? + (_theResult____h583523[43] ? 6'd13 : - (_theResult____h583832[42] ? + (_theResult____h583523[42] ? 6'd14 : - (_theResult____h583832[41] ? + (_theResult____h583523[41] ? 6'd15 : - (_theResult____h583832[40] ? + (_theResult____h583523[40] ? 6'd16 : - (_theResult____h583832[39] ? + (_theResult____h583523[39] ? 6'd17 : - (_theResult____h583832[38] ? + (_theResult____h583523[38] ? 6'd18 : - (_theResult____h583832[37] ? + (_theResult____h583523[37] ? 6'd19 : - (_theResult____h583832[36] ? + (_theResult____h583523[36] ? 6'd20 : - (_theResult____h583832[35] ? + (_theResult____h583523[35] ? 6'd21 : - (_theResult____h583832[34] ? + (_theResult____h583523[34] ? 6'd22 : - (_theResult____h583832[33] ? + (_theResult____h583523[33] ? 6'd23 : - (_theResult____h583832[32] ? + (_theResult____h583523[32] ? 6'd24 : - (_theResult____h583832[31] ? + (_theResult____h583523[31] ? 6'd25 : - (_theResult____h583832[30] ? + (_theResult____h583523[30] ? 6'd26 : - (_theResult____h583832[29] ? + (_theResult____h583523[29] ? 6'd27 : - (_theResult____h583832[28] ? + (_theResult____h583523[28] ? 6'd28 : - (_theResult____h583832[27] ? + (_theResult____h583523[27] ? 6'd29 : - (_theResult____h583832[26] ? + (_theResult____h583523[26] ? 6'd30 : - (_theResult____h583832[25] ? + (_theResult____h583523[25] ? 6'd31 : - (_theResult____h583832[24] ? + (_theResult____h583523[24] ? 6'd32 : - (_theResult____h583832[23] ? + (_theResult____h583523[23] ? 6'd33 : - (_theResult____h583832[22] ? + (_theResult____h583523[22] ? 6'd34 : - (_theResult____h583832[21] ? + (_theResult____h583523[21] ? 6'd35 : - (_theResult____h583832[20] ? + (_theResult____h583523[20] ? 6'd36 : - (_theResult____h583832[19] ? + (_theResult____h583523[19] ? 6'd37 : - (_theResult____h583832[18] ? + (_theResult____h583523[18] ? 6'd38 : - (_theResult____h583832[17] ? + (_theResult____h583523[17] ? 6'd39 : - (_theResult____h583832[16] ? + (_theResult____h583523[16] ? 6'd40 : - (_theResult____h583832[15] ? + (_theResult____h583523[15] ? 6'd41 : - (_theResult____h583832[14] ? + (_theResult____h583523[14] ? 6'd42 : - (_theResult____h583832[13] ? + (_theResult____h583523[13] ? 6'd43 : - (_theResult____h583832[12] ? + (_theResult____h583523[12] ? 6'd44 : - (_theResult____h583832[11] ? + (_theResult____h583523[11] ? 6'd45 : - (_theResult____h583832[10] ? + (_theResult____h583523[10] ? 6'd46 : - (_theResult____h583832[9] ? + (_theResult____h583523[9] ? 6'd47 : - (_theResult____h583832[8] ? + (_theResult____h583523[8] ? 6'd48 : - (_theResult____h583832[7] ? + (_theResult____h583523[7] ? 6'd49 : - (_theResult____h583832[6] ? + (_theResult____h583523[6] ? 6'd50 : - (_theResult____h583832[5] ? + (_theResult____h583523[5] ? 6'd51 : - (_theResult____h583832[4] ? + (_theResult____h583523[4] ? 6'd52 : - (_theResult____h583832[3] ? + (_theResult____h583523[3] ? 6'd53 : - (_theResult____h583832[2] ? + (_theResult____h583523[2] ? 6'd54 : - (_theResult____h583832[1] ? + (_theResult____h583523[1] ? 6'd55 : - (_theResult____h583832[0] ? + (_theResult____h583523[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4894 = - (_theResult____h366022[56] ? + (_theResult____h365713[56] ? 6'd0 : - (_theResult____h366022[55] ? + (_theResult____h365713[55] ? 6'd1 : - (_theResult____h366022[54] ? + (_theResult____h365713[54] ? 6'd2 : - (_theResult____h366022[53] ? + (_theResult____h365713[53] ? 6'd3 : - (_theResult____h366022[52] ? + (_theResult____h365713[52] ? 6'd4 : - (_theResult____h366022[51] ? + (_theResult____h365713[51] ? 6'd5 : - (_theResult____h366022[50] ? + (_theResult____h365713[50] ? 6'd6 : - (_theResult____h366022[49] ? + (_theResult____h365713[49] ? 6'd7 : - (_theResult____h366022[48] ? + (_theResult____h365713[48] ? 6'd8 : - (_theResult____h366022[47] ? + (_theResult____h365713[47] ? 6'd9 : - (_theResult____h366022[46] ? + (_theResult____h365713[46] ? 6'd10 : - (_theResult____h366022[45] ? + (_theResult____h365713[45] ? 6'd11 : - (_theResult____h366022[44] ? + (_theResult____h365713[44] ? 6'd12 : - (_theResult____h366022[43] ? + (_theResult____h365713[43] ? 6'd13 : - (_theResult____h366022[42] ? + (_theResult____h365713[42] ? 6'd14 : - (_theResult____h366022[41] ? + (_theResult____h365713[41] ? 6'd15 : - (_theResult____h366022[40] ? + (_theResult____h365713[40] ? 6'd16 : - (_theResult____h366022[39] ? + (_theResult____h365713[39] ? 6'd17 : - (_theResult____h366022[38] ? + (_theResult____h365713[38] ? 6'd18 : - (_theResult____h366022[37] ? + (_theResult____h365713[37] ? 6'd19 : - (_theResult____h366022[36] ? + (_theResult____h365713[36] ? 6'd20 : - (_theResult____h366022[35] ? + (_theResult____h365713[35] ? 6'd21 : - (_theResult____h366022[34] ? + (_theResult____h365713[34] ? 6'd22 : - (_theResult____h366022[33] ? + (_theResult____h365713[33] ? 6'd23 : - (_theResult____h366022[32] ? + (_theResult____h365713[32] ? 6'd24 : - (_theResult____h366022[31] ? + (_theResult____h365713[31] ? 6'd25 : - (_theResult____h366022[30] ? + (_theResult____h365713[30] ? 6'd26 : - (_theResult____h366022[29] ? + (_theResult____h365713[29] ? 6'd27 : - (_theResult____h366022[28] ? + (_theResult____h365713[28] ? 6'd28 : - (_theResult____h366022[27] ? + (_theResult____h365713[27] ? 6'd29 : - (_theResult____h366022[26] ? + (_theResult____h365713[26] ? 6'd30 : - (_theResult____h366022[25] ? + (_theResult____h365713[25] ? 6'd31 : - (_theResult____h366022[24] ? + (_theResult____h365713[24] ? 6'd32 : - (_theResult____h366022[23] ? + (_theResult____h365713[23] ? 6'd33 : - (_theResult____h366022[22] ? + (_theResult____h365713[22] ? 6'd34 : - (_theResult____h366022[21] ? + (_theResult____h365713[21] ? 6'd35 : - (_theResult____h366022[20] ? + (_theResult____h365713[20] ? 6'd36 : - (_theResult____h366022[19] ? + (_theResult____h365713[19] ? 6'd37 : - (_theResult____h366022[18] ? + (_theResult____h365713[18] ? 6'd38 : - (_theResult____h366022[17] ? + (_theResult____h365713[17] ? 6'd39 : - (_theResult____h366022[16] ? + (_theResult____h365713[16] ? 6'd40 : - (_theResult____h366022[15] ? + (_theResult____h365713[15] ? 6'd41 : - (_theResult____h366022[14] ? + (_theResult____h365713[14] ? 6'd42 : - (_theResult____h366022[13] ? + (_theResult____h365713[13] ? 6'd43 : - (_theResult____h366022[12] ? + (_theResult____h365713[12] ? 6'd44 : - (_theResult____h366022[11] ? + (_theResult____h365713[11] ? 6'd45 : - (_theResult____h366022[10] ? + (_theResult____h365713[10] ? 6'd46 : - (_theResult____h366022[9] ? + (_theResult____h365713[9] ? 6'd47 : - (_theResult____h366022[8] ? + (_theResult____h365713[8] ? 6'd48 : - (_theResult____h366022[7] ? + (_theResult____h365713[7] ? 6'd49 : - (_theResult____h366022[6] ? + (_theResult____h365713[6] ? 6'd50 : - (_theResult____h366022[5] ? + (_theResult____h365713[5] ? 6'd51 : - (_theResult____h366022[4] ? + (_theResult____h365713[4] ? 6'd52 : - (_theResult____h366022[3] ? + (_theResult____h365713[3] ? 6'd53 : - (_theResult____h366022[2] ? + (_theResult____h365713[2] ? 6'd54 : - (_theResult____h366022[1] ? + (_theResult____h365713[1] ? 6'd55 : - (_theResult____h366022[0] ? + (_theResult____h365713[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6286 = - (_theResult____h411719[56] ? + (_theResult____h411410[56] ? 6'd0 : - (_theResult____h411719[55] ? + (_theResult____h411410[55] ? 6'd1 : - (_theResult____h411719[54] ? + (_theResult____h411410[54] ? 6'd2 : - (_theResult____h411719[53] ? + (_theResult____h411410[53] ? 6'd3 : - (_theResult____h411719[52] ? + (_theResult____h411410[52] ? 6'd4 : - (_theResult____h411719[51] ? + (_theResult____h411410[51] ? 6'd5 : - (_theResult____h411719[50] ? + (_theResult____h411410[50] ? 6'd6 : - (_theResult____h411719[49] ? + (_theResult____h411410[49] ? 6'd7 : - (_theResult____h411719[48] ? + (_theResult____h411410[48] ? 6'd8 : - (_theResult____h411719[47] ? + (_theResult____h411410[47] ? 6'd9 : - (_theResult____h411719[46] ? + (_theResult____h411410[46] ? 6'd10 : - (_theResult____h411719[45] ? + (_theResult____h411410[45] ? 6'd11 : - (_theResult____h411719[44] ? + (_theResult____h411410[44] ? 6'd12 : - (_theResult____h411719[43] ? + (_theResult____h411410[43] ? 6'd13 : - (_theResult____h411719[42] ? + (_theResult____h411410[42] ? 6'd14 : - (_theResult____h411719[41] ? + (_theResult____h411410[41] ? 6'd15 : - (_theResult____h411719[40] ? + (_theResult____h411410[40] ? 6'd16 : - (_theResult____h411719[39] ? + (_theResult____h411410[39] ? 6'd17 : - (_theResult____h411719[38] ? + (_theResult____h411410[38] ? 6'd18 : - (_theResult____h411719[37] ? + (_theResult____h411410[37] ? 6'd19 : - (_theResult____h411719[36] ? + (_theResult____h411410[36] ? 6'd20 : - (_theResult____h411719[35] ? + (_theResult____h411410[35] ? 6'd21 : - (_theResult____h411719[34] ? + (_theResult____h411410[34] ? 6'd22 : - (_theResult____h411719[33] ? + (_theResult____h411410[33] ? 6'd23 : - (_theResult____h411719[32] ? + (_theResult____h411410[32] ? 6'd24 : - (_theResult____h411719[31] ? + (_theResult____h411410[31] ? 6'd25 : - (_theResult____h411719[30] ? + (_theResult____h411410[30] ? 6'd26 : - (_theResult____h411719[29] ? + (_theResult____h411410[29] ? 6'd27 : - (_theResult____h411719[28] ? + (_theResult____h411410[28] ? 6'd28 : - (_theResult____h411719[27] ? + (_theResult____h411410[27] ? 6'd29 : - (_theResult____h411719[26] ? + (_theResult____h411410[26] ? 6'd30 : - (_theResult____h411719[25] ? + (_theResult____h411410[25] ? 6'd31 : - (_theResult____h411719[24] ? + (_theResult____h411410[24] ? 6'd32 : - (_theResult____h411719[23] ? + (_theResult____h411410[23] ? 6'd33 : - (_theResult____h411719[22] ? + (_theResult____h411410[22] ? 6'd34 : - (_theResult____h411719[21] ? + (_theResult____h411410[21] ? 6'd35 : - (_theResult____h411719[20] ? + (_theResult____h411410[20] ? 6'd36 : - (_theResult____h411719[19] ? + (_theResult____h411410[19] ? 6'd37 : - (_theResult____h411719[18] ? + (_theResult____h411410[18] ? 6'd38 : - (_theResult____h411719[17] ? + (_theResult____h411410[17] ? 6'd39 : - (_theResult____h411719[16] ? + (_theResult____h411410[16] ? 6'd40 : - (_theResult____h411719[15] ? + (_theResult____h411410[15] ? 6'd41 : - (_theResult____h411719[14] ? + (_theResult____h411410[14] ? 6'd42 : - (_theResult____h411719[13] ? + (_theResult____h411410[13] ? 6'd43 : - (_theResult____h411719[12] ? + (_theResult____h411410[12] ? 6'd44 : - (_theResult____h411719[11] ? + (_theResult____h411410[11] ? 6'd45 : - (_theResult____h411719[10] ? + (_theResult____h411410[10] ? 6'd46 : - (_theResult____h411719[9] ? + (_theResult____h411410[9] ? 6'd47 : - (_theResult____h411719[8] ? + (_theResult____h411410[8] ? 6'd48 : - (_theResult____h411719[7] ? + (_theResult____h411410[7] ? 6'd49 : - (_theResult____h411719[6] ? + (_theResult____h411410[6] ? 6'd50 : - (_theResult____h411719[5] ? + (_theResult____h411410[5] ? 6'd51 : - (_theResult____h411719[4] ? + (_theResult____h411410[4] ? 6'd52 : - (_theResult____h411719[3] ? + (_theResult____h411410[3] ? 6'd53 : - (_theResult____h411719[2] ? + (_theResult____h411410[2] ? 6'd54 : - (_theResult____h411719[1] ? + (_theResult____h411410[1] ? 6'd55 : - (_theResult____h411719[0] ? + (_theResult____h411410[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7678 = - (_theResult____h457414[56] ? + (_theResult____h457105[56] ? 6'd0 : - (_theResult____h457414[55] ? + (_theResult____h457105[55] ? 6'd1 : - (_theResult____h457414[54] ? + (_theResult____h457105[54] ? 6'd2 : - (_theResult____h457414[53] ? + (_theResult____h457105[53] ? 6'd3 : - (_theResult____h457414[52] ? + (_theResult____h457105[52] ? 6'd4 : - (_theResult____h457414[51] ? + (_theResult____h457105[51] ? 6'd5 : - (_theResult____h457414[50] ? + (_theResult____h457105[50] ? 6'd6 : - (_theResult____h457414[49] ? + (_theResult____h457105[49] ? 6'd7 : - (_theResult____h457414[48] ? + (_theResult____h457105[48] ? 6'd8 : - (_theResult____h457414[47] ? + (_theResult____h457105[47] ? 6'd9 : - (_theResult____h457414[46] ? + (_theResult____h457105[46] ? 6'd10 : - (_theResult____h457414[45] ? + (_theResult____h457105[45] ? 6'd11 : - (_theResult____h457414[44] ? + (_theResult____h457105[44] ? 6'd12 : - (_theResult____h457414[43] ? + (_theResult____h457105[43] ? 6'd13 : - (_theResult____h457414[42] ? + (_theResult____h457105[42] ? 6'd14 : - (_theResult____h457414[41] ? + (_theResult____h457105[41] ? 6'd15 : - (_theResult____h457414[40] ? + (_theResult____h457105[40] ? 6'd16 : - (_theResult____h457414[39] ? + (_theResult____h457105[39] ? 6'd17 : - (_theResult____h457414[38] ? + (_theResult____h457105[38] ? 6'd18 : - (_theResult____h457414[37] ? + (_theResult____h457105[37] ? 6'd19 : - (_theResult____h457414[36] ? + (_theResult____h457105[36] ? 6'd20 : - (_theResult____h457414[35] ? + (_theResult____h457105[35] ? 6'd21 : - (_theResult____h457414[34] ? + (_theResult____h457105[34] ? 6'd22 : - (_theResult____h457414[33] ? + (_theResult____h457105[33] ? 6'd23 : - (_theResult____h457414[32] ? + (_theResult____h457105[32] ? 6'd24 : - (_theResult____h457414[31] ? + (_theResult____h457105[31] ? 6'd25 : - (_theResult____h457414[30] ? + (_theResult____h457105[30] ? 6'd26 : - (_theResult____h457414[29] ? + (_theResult____h457105[29] ? 6'd27 : - (_theResult____h457414[28] ? + (_theResult____h457105[28] ? 6'd28 : - (_theResult____h457414[27] ? + (_theResult____h457105[27] ? 6'd29 : - (_theResult____h457414[26] ? + (_theResult____h457105[26] ? 6'd30 : - (_theResult____h457414[25] ? + (_theResult____h457105[25] ? 6'd31 : - (_theResult____h457414[24] ? + (_theResult____h457105[24] ? 6'd32 : - (_theResult____h457414[23] ? + (_theResult____h457105[23] ? 6'd33 : - (_theResult____h457414[22] ? + (_theResult____h457105[22] ? 6'd34 : - (_theResult____h457414[21] ? + (_theResult____h457105[21] ? 6'd35 : - (_theResult____h457414[20] ? + (_theResult____h457105[20] ? 6'd36 : - (_theResult____h457414[19] ? + (_theResult____h457105[19] ? 6'd37 : - (_theResult____h457414[18] ? + (_theResult____h457105[18] ? 6'd38 : - (_theResult____h457414[17] ? + (_theResult____h457105[17] ? 6'd39 : - (_theResult____h457414[16] ? + (_theResult____h457105[16] ? 6'd40 : - (_theResult____h457414[15] ? + (_theResult____h457105[15] ? 6'd41 : - (_theResult____h457414[14] ? + (_theResult____h457105[14] ? 6'd42 : - (_theResult____h457414[13] ? + (_theResult____h457105[13] ? 6'd43 : - (_theResult____h457414[12] ? + (_theResult____h457105[12] ? 6'd44 : - (_theResult____h457414[11] ? + (_theResult____h457105[11] ? 6'd45 : - (_theResult____h457414[10] ? + (_theResult____h457105[10] ? 6'd46 : - (_theResult____h457414[9] ? + (_theResult____h457105[9] ? 6'd47 : - (_theResult____h457414[8] ? + (_theResult____h457105[8] ? 6'd48 : - (_theResult____h457414[7] ? + (_theResult____h457105[7] ? 6'd49 : - (_theResult____h457414[6] ? + (_theResult____h457105[6] ? 6'd50 : - (_theResult____h457414[5] ? + (_theResult____h457105[5] ? 6'd51 : - (_theResult____h457414[4] ? + (_theResult____h457105[4] ? 6'd52 : - (_theResult____h457414[3] ? + (_theResult____h457105[3] ? 6'd53 : - (_theResult____h457414[2] ? + (_theResult____h457105[2] ? 6'd54 : - (_theResult____h457414[1] ? + (_theResult____h457105[1] ? 6'd55 : - (_theResult____h457414[0] ? + (_theResult____h457105[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d10033 = - (_theResult___fst_exp__h592068 == 11'd2047) ? + (_theResult___fst_exp__h591759 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -20673,10 +20508,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard83842_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q169) ; + CASE_guard83533_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q161) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d10535 = - (_theResult___fst_exp__h552764 == 11'd2047) ? + (_theResult___fst_exp__h552455 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -20684,10 +20519,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard44538_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q198) ; + CASE_guard44229_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q188) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d10802 = - (_theResult___fst_exp__h552764 == 11'd2047) ? + (_theResult___fst_exp__h552455 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -20695,10 +20530,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard44538_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q200) ; + CASE_guard44229_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q192) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d9050 = - (_theResult___fst_exp__h513911 == 11'd2047) ? + (_theResult___fst_exp__h513602 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : @@ -20706,10 +20541,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard05685_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q146) ; + CASE_guard05376_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q140) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d9765 = - (_theResult___fst_exp__h592068 == 11'd2047) ? + (_theResult___fst_exp__h591759 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -20717,538 +20552,538 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard83842_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165) ; + CASE_guard83533_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q157) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4406 = - (guard__h348393 == 2'b0 || + (guard__h348084 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h356494 : - _theResult___exp__h357010 ; + _theResult___fst_exp__h356185 : + _theResult___exp__h356701 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4409 = - (guard__h348393 == 2'b0) ? - _theResult___fst_exp__h356494 : + (guard__h348084 == 2'b0) ? + _theResult___fst_exp__h356185 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h357010 : - _theResult___fst_exp__h356494) ; + _theResult___exp__h356701 : + _theResult___fst_exp__h356185) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5053 = - (guard__h348393 == 2'b0 || + (guard__h348084 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - sfdin__h356488[56:34] : - _theResult___sfd__h357011 ; + sfdin__h356179[56:34] : + _theResult___sfd__h356702 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5055 = - (guard__h348393 == 2'b0) ? - sfdin__h356488[56:34] : + (guard__h348084 == 2'b0) ? + sfdin__h356179[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h357011 : - sfdin__h356488[56:34]) ; + _theResult___sfd__h356702 : + sfdin__h356179[56:34]) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5798 = - (guard__h394092 == 2'b0 || + (guard__h393783 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h402191 : - _theResult___exp__h402707 ; + _theResult___fst_exp__h401882 : + _theResult___exp__h402398 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5801 = - (guard__h394092 == 2'b0) ? - _theResult___fst_exp__h402191 : + (guard__h393783 == 2'b0) ? + _theResult___fst_exp__h401882 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h402707 : - _theResult___fst_exp__h402191) ; + _theResult___exp__h402398 : + _theResult___fst_exp__h401882) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6445 = - (guard__h394092 == 2'b0 || + (guard__h393783 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - sfdin__h402185[56:34] : - _theResult___sfd__h402708 ; + sfdin__h401876[56:34] : + _theResult___sfd__h402399 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6447 = - (guard__h394092 == 2'b0) ? - sfdin__h402185[56:34] : + (guard__h393783 == 2'b0) ? + sfdin__h401876[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h402708 : - sfdin__h402185[56:34]) ; + _theResult___sfd__h402399 : + sfdin__h401876[56:34]) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7190 = - (guard__h439787 == 2'b0 || + (guard__h439478 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h447886 : - _theResult___exp__h448402 ; + _theResult___fst_exp__h447577 : + _theResult___exp__h448093 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7193 = - (guard__h439787 == 2'b0) ? - _theResult___fst_exp__h447886 : + (guard__h439478 == 2'b0) ? + _theResult___fst_exp__h447577 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h448402 : - _theResult___fst_exp__h447886) ; + _theResult___exp__h448093 : + _theResult___fst_exp__h447577) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7837 = - (guard__h439787 == 2'b0 || + (guard__h439478 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - sfdin__h447880[56:34] : - _theResult___sfd__h448403 ; + sfdin__h447571[56:34] : + _theResult___sfd__h448094 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7839 = - (guard__h439787 == 2'b0) ? - sfdin__h447880[56:34] : + (guard__h439478 == 2'b0) ? + sfdin__h447571[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h448403 : - sfdin__h447880[56:34]) ; + _theResult___sfd__h448094 : + sfdin__h447571[56:34]) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10647 = - (guard__h544538 == 2'b0 || + (guard__h544229 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___fst_exp__h552764 : - _theResult___exp__h553493 ; + _theResult___fst_exp__h552455 : + _theResult___exp__h553184 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10649 = - (guard__h544538 == 2'b0) ? - _theResult___fst_exp__h552764 : + (guard__h544229 == 2'b0) ? + _theResult___fst_exp__h552455 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___exp__h553493 : - _theResult___fst_exp__h552764) ; + _theResult___exp__h553184 : + _theResult___fst_exp__h552455) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10730 = - (guard__h544538 == 2'b0 || + (guard__h544229 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - sfdin__h552758[56:5] : - _theResult___sfd__h553494 ; + sfdin__h552449[56:5] : + _theResult___sfd__h553185 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10732 = - (guard__h544538 == 2'b0) ? - sfdin__h552758[56:5] : + (guard__h544229 == 2'b0) ? + sfdin__h552449[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___sfd__h553494 : - sfdin__h552758[56:5]) ; + _theResult___sfd__h553185 : + sfdin__h552449[56:5]) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9167 = - (guard__h505685 == 2'b0 || + (guard__h505376 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___fst_exp__h513911 : - _theResult___exp__h514640 ; + _theResult___fst_exp__h513602 : + _theResult___exp__h514331 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9169 = - (guard__h505685 == 2'b0) ? - _theResult___fst_exp__h513911 : + (guard__h505376 == 2'b0) ? + _theResult___fst_exp__h513602 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___exp__h514640 : - _theResult___fst_exp__h513911) ; + _theResult___exp__h514331 : + _theResult___fst_exp__h513602) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9251 = - (guard__h505685 == 2'b0 || + (guard__h505376 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - sfdin__h513905[56:5] : - _theResult___sfd__h514641 ; + sfdin__h513596[56:5] : + _theResult___sfd__h514332 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9253 = - (guard__h505685 == 2'b0) ? - sfdin__h513905[56:5] : + (guard__h505376 == 2'b0) ? + sfdin__h513596[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___sfd__h514641 : - sfdin__h513905[56:5]) ; + _theResult___sfd__h514332 : + sfdin__h513596[56:5]) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9877 = - (guard__h583842 == 2'b0 || + (guard__h583533 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___fst_exp__h592068 : - _theResult___exp__h592797 ; + _theResult___fst_exp__h591759 : + _theResult___exp__h592488 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9879 = - (guard__h583842 == 2'b0) ? - _theResult___fst_exp__h592068 : + (guard__h583533 == 2'b0) ? + _theResult___fst_exp__h591759 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___exp__h592797 : - _theResult___fst_exp__h592068) ; + _theResult___exp__h592488 : + _theResult___fst_exp__h591759) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9960 = - (guard__h583842 == 2'b0 || + (guard__h583533 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - sfdin__h592062[56:5] : - _theResult___sfd__h592798 ; + sfdin__h591753[56:5] : + _theResult___sfd__h592489 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9962 = - (guard__h583842 == 2'b0) ? - sfdin__h592062[56:5] : + (guard__h583533 == 2'b0) ? + sfdin__h591753[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___sfd__h592798 : - sfdin__h592062[56:5]) ; + _theResult___sfd__h592489 : + sfdin__h591753[56:5]) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4953 = - (guard__h366032 == 2'b0 || + (guard__h365723 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h374260 : - _theResult___exp__h374776 ; + _theResult___fst_exp__h373951 : + _theResult___exp__h374467 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4955 = - (guard__h366032 == 2'b0) ? - _theResult___fst_exp__h374260 : + (guard__h365723 == 2'b0) ? + _theResult___fst_exp__h373951 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h374776 : - _theResult___fst_exp__h374260) ; + _theResult___exp__h374467 : + _theResult___fst_exp__h373951) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5099 = - (guard__h366032 == 2'b0 || + (guard__h365723 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - sfdin__h374254[56:34] : - _theResult___sfd__h374777 ; + sfdin__h373945[56:34] : + _theResult___sfd__h374468 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5101 = - (guard__h366032 == 2'b0) ? - sfdin__h374254[56:34] : + (guard__h365723 == 2'b0) ? + sfdin__h373945[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h374777 : - sfdin__h374254[56:34]) ; + _theResult___sfd__h374468 : + sfdin__h373945[56:34]) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6345 = - (guard__h411729 == 2'b0 || + (guard__h411420 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h419957 : - _theResult___exp__h420473 ; + _theResult___fst_exp__h419648 : + _theResult___exp__h420164 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6347 = - (guard__h411729 == 2'b0) ? - _theResult___fst_exp__h419957 : + (guard__h411420 == 2'b0) ? + _theResult___fst_exp__h419648 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h420473 : - _theResult___fst_exp__h419957) ; + _theResult___exp__h420164 : + _theResult___fst_exp__h419648) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6491 = - (guard__h411729 == 2'b0 || + (guard__h411420 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - sfdin__h419951[56:34] : - _theResult___sfd__h420474 ; + sfdin__h419642[56:34] : + _theResult___sfd__h420165 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6493 = - (guard__h411729 == 2'b0) ? - sfdin__h419951[56:34] : + (guard__h411420 == 2'b0) ? + sfdin__h419642[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h420474 : - sfdin__h419951[56:34]) ; + _theResult___sfd__h420165 : + sfdin__h419642[56:34]) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7737 = - (guard__h457424 == 2'b0 || + (guard__h457115 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h465652 : - _theResult___exp__h466168 ; + _theResult___fst_exp__h465343 : + _theResult___exp__h465859 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7739 = - (guard__h457424 == 2'b0) ? - _theResult___fst_exp__h465652 : + (guard__h457115 == 2'b0) ? + _theResult___fst_exp__h465343 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h466168 : - _theResult___fst_exp__h465652) ; + _theResult___exp__h465859 : + _theResult___fst_exp__h465343) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7883 = - (guard__h457424 == 2'b0 || + (guard__h457115 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - sfdin__h465646[56:34] : - _theResult___sfd__h466169 ; + sfdin__h465337[56:34] : + _theResult___sfd__h465860 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7885 = - (guard__h457424 == 2'b0) ? - sfdin__h465646[56:34] : + (guard__h457115 == 2'b0) ? + sfdin__h465337[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h466169 : - sfdin__h465646[56:34]) ; + _theResult___sfd__h465860 : + sfdin__h465337[56:34]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10609 = - (guard__h535226 == 2'b0 || + (guard__h534917 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___fst_exp__h543187 : - _theResult___exp__h543842 ; + _theResult___fst_exp__h542878 : + _theResult___exp__h543533 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10611 = - (guard__h535226 == 2'b0) ? - _theResult___fst_exp__h543187 : + (guard__h534917 == 2'b0) ? + _theResult___fst_exp__h542878 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___exp__h543842 : - _theResult___fst_exp__h543187) ; + _theResult___exp__h543533 : + _theResult___fst_exp__h542878) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10678 = - (guard__h553607 == 2'b0 || + (guard__h553298 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___fst_exp__h561597 : - _theResult___exp__h562277 ; + _theResult___fst_exp__h561288 : + _theResult___exp__h561968 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10680 = - (guard__h553607 == 2'b0) ? - _theResult___fst_exp__h561597 : + (guard__h553298 == 2'b0) ? + _theResult___fst_exp__h561288 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___exp__h562277 : - _theResult___fst_exp__h561597) ; + _theResult___exp__h561968 : + _theResult___fst_exp__h561288) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10704 = - (guard__h535226 == 2'b0 || + (guard__h534917 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___snd__h543138[56:5] : - _theResult___sfd__h543843 ; + _theResult___snd__h542829[56:5] : + _theResult___sfd__h543534 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10706 = - (guard__h535226 == 2'b0) ? - _theResult___snd__h543138[56:5] : + (guard__h534917 == 2'b0) ? + _theResult___snd__h542829[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___sfd__h543843 : - _theResult___snd__h543138[56:5]) ; + _theResult___sfd__h543534 : + _theResult___snd__h542829[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10749 = - (guard__h553607 == 2'b0 || + (guard__h553298 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___snd__h561543[56:5] : - _theResult___sfd__h562278 ; + _theResult___snd__h561234[56:5] : + _theResult___sfd__h561969 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10751 = - (guard__h553607 == 2'b0) ? - _theResult___snd__h561543[56:5] : + (guard__h553298 == 2'b0) ? + _theResult___snd__h561234[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___sfd__h562278 : - _theResult___snd__h561543[56:5]) ; + _theResult___sfd__h561969 : + _theResult___snd__h561234[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9124 = - (guard__h496373 == 2'b0 || + (guard__h496064 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___fst_exp__h504334 : - _theResult___exp__h504989 ; + _theResult___fst_exp__h504025 : + _theResult___exp__h504680 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9126 = - (guard__h496373 == 2'b0) ? - _theResult___fst_exp__h504334 : + (guard__h496064 == 2'b0) ? + _theResult___fst_exp__h504025 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___exp__h504989 : - _theResult___fst_exp__h504334) ; + _theResult___exp__h504680 : + _theResult___fst_exp__h504025) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9198 = - (guard__h514754 == 2'b0 || + (guard__h514445 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___fst_exp__h522744 : - _theResult___exp__h523424 ; + _theResult___fst_exp__h522435 : + _theResult___exp__h523115 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9200 = - (guard__h514754 == 2'b0) ? - _theResult___fst_exp__h522744 : + (guard__h514445 == 2'b0) ? + _theResult___fst_exp__h522435 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___exp__h523424 : - _theResult___fst_exp__h522744) ; + _theResult___exp__h523115 : + _theResult___fst_exp__h522435) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9224 = - (guard__h496373 == 2'b0 || + (guard__h496064 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___snd__h504285[56:5] : - _theResult___sfd__h504990 ; + _theResult___snd__h503976[56:5] : + _theResult___sfd__h504681 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9226 = - (guard__h496373 == 2'b0) ? - _theResult___snd__h504285[56:5] : + (guard__h496064 == 2'b0) ? + _theResult___snd__h503976[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___sfd__h504990 : - _theResult___snd__h504285[56:5]) ; + _theResult___sfd__h504681 : + _theResult___snd__h503976[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9270 = - (guard__h514754 == 2'b0 || + (guard__h514445 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___snd__h522690[56:5] : - _theResult___sfd__h523425 ; + _theResult___snd__h522381[56:5] : + _theResult___sfd__h523116 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9272 = - (guard__h514754 == 2'b0) ? - _theResult___snd__h522690[56:5] : + (guard__h514445 == 2'b0) ? + _theResult___snd__h522381[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___sfd__h523425 : - _theResult___snd__h522690[56:5]) ; + _theResult___sfd__h523116 : + _theResult___snd__h522381[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9839 = - (guard__h574530 == 2'b0 || + (guard__h574221 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___fst_exp__h582491 : - _theResult___exp__h583146 ; + _theResult___fst_exp__h582182 : + _theResult___exp__h582837 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9841 = - (guard__h574530 == 2'b0) ? - _theResult___fst_exp__h582491 : + (guard__h574221 == 2'b0) ? + _theResult___fst_exp__h582182 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___exp__h583146 : - _theResult___fst_exp__h582491) ; + _theResult___exp__h582837 : + _theResult___fst_exp__h582182) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9908 = - (guard__h592911 == 2'b0 || + (guard__h592602 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___fst_exp__h600901 : - _theResult___exp__h601581 ; + _theResult___fst_exp__h600592 : + _theResult___exp__h601272 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9910 = - (guard__h592911 == 2'b0) ? - _theResult___fst_exp__h600901 : + (guard__h592602 == 2'b0) ? + _theResult___fst_exp__h600592 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___exp__h601581 : - _theResult___fst_exp__h600901) ; + _theResult___exp__h601272 : + _theResult___fst_exp__h600592) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9934 = - (guard__h574530 == 2'b0 || + (guard__h574221 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___snd__h582442[56:5] : - _theResult___sfd__h583147 ; + _theResult___snd__h582133[56:5] : + _theResult___sfd__h582838 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9936 = - (guard__h574530 == 2'b0) ? - _theResult___snd__h582442[56:5] : + (guard__h574221 == 2'b0) ? + _theResult___snd__h582133[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___sfd__h583147 : - _theResult___snd__h582442[56:5]) ; + _theResult___sfd__h582838 : + _theResult___snd__h582133[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9979 = - (guard__h592911 == 2'b0 || + (guard__h592602 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___snd__h600847[56:5] : - _theResult___sfd__h601582 ; + _theResult___snd__h600538[56:5] : + _theResult___sfd__h601273 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9981 = - (guard__h592911 == 2'b0) ? - _theResult___snd__h600847[56:5] : + (guard__h592602 == 2'b0) ? + _theResult___snd__h600538[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___sfd__h601582 : - _theResult___snd__h600847[56:5]) ; + _theResult___sfd__h601273 : + _theResult___snd__h600538[56:5]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4628 = - (guard__h357102 == 2'b0 || + (guard__h356793 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h365150 : - _theResult___exp__h365592 ; + _theResult___fst_exp__h364841 : + _theResult___exp__h365283 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4630 = - (guard__h357102 == 2'b0) ? - _theResult___fst_exp__h365150 : + (guard__h356793 == 2'b0) ? + _theResult___fst_exp__h364841 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h365592 : - _theResult___fst_exp__h365150) ; + _theResult___exp__h365283 : + _theResult___fst_exp__h364841) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5022 = - (guard__h374868 == 2'b0 || + (guard__h374559 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h382945 : - _theResult___exp__h383412 ; + _theResult___fst_exp__h382636 : + _theResult___exp__h383103 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5024 = - (guard__h374868 == 2'b0) ? - _theResult___fst_exp__h382945 : + (guard__h374559 == 2'b0) ? + _theResult___fst_exp__h382636 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h383412 : - _theResult___fst_exp__h382945) ; + _theResult___exp__h383103 : + _theResult___fst_exp__h382636) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5072 = - (guard__h357102 == 2'b0 || + (guard__h356793 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___snd__h365101[56:34] : - _theResult___sfd__h365593 ; + _theResult___snd__h364792[56:34] : + _theResult___sfd__h365284 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5074 = - (guard__h357102 == 2'b0) ? - _theResult___snd__h365101[56:34] : + (guard__h356793 == 2'b0) ? + _theResult___snd__h364792[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h365593 : - _theResult___snd__h365101[56:34]) ; + _theResult___sfd__h365284 : + _theResult___snd__h364792[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5118 = - (guard__h374868 == 2'b0 || + (guard__h374559 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___snd__h382891[56:34] : - _theResult___sfd__h383413 ; + _theResult___snd__h382582[56:34] : + _theResult___sfd__h383104 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5120 = - (guard__h374868 == 2'b0) ? - _theResult___snd__h382891[56:34] : + (guard__h374559 == 2'b0) ? + _theResult___snd__h382582[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h383413 : - _theResult___snd__h382891[56:34]) ; + _theResult___sfd__h383104 : + _theResult___snd__h382582[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6020 = - (guard__h402799 == 2'b0 || + (guard__h402490 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h410847 : - _theResult___exp__h411289 ; + _theResult___fst_exp__h410538 : + _theResult___exp__h410980 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6022 = - (guard__h402799 == 2'b0) ? - _theResult___fst_exp__h410847 : + (guard__h402490 == 2'b0) ? + _theResult___fst_exp__h410538 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h411289 : - _theResult___fst_exp__h410847) ; + _theResult___exp__h410980 : + _theResult___fst_exp__h410538) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6414 = - (guard__h420565 == 2'b0 || + (guard__h420256 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h428642 : - _theResult___exp__h429109 ; + _theResult___fst_exp__h428333 : + _theResult___exp__h428800 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6416 = - (guard__h420565 == 2'b0) ? - _theResult___fst_exp__h428642 : + (guard__h420256 == 2'b0) ? + _theResult___fst_exp__h428333 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h429109 : - _theResult___fst_exp__h428642) ; + _theResult___exp__h428800 : + _theResult___fst_exp__h428333) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6464 = - (guard__h402799 == 2'b0 || + (guard__h402490 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___snd__h410798[56:34] : - _theResult___sfd__h411290 ; + _theResult___snd__h410489[56:34] : + _theResult___sfd__h410981 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6466 = - (guard__h402799 == 2'b0) ? - _theResult___snd__h410798[56:34] : + (guard__h402490 == 2'b0) ? + _theResult___snd__h410489[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h411290 : - _theResult___snd__h410798[56:34]) ; + _theResult___sfd__h410981 : + _theResult___snd__h410489[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6510 = - (guard__h420565 == 2'b0 || + (guard__h420256 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___snd__h428588[56:34] : - _theResult___sfd__h429110 ; + _theResult___snd__h428279[56:34] : + _theResult___sfd__h428801 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6512 = - (guard__h420565 == 2'b0) ? - _theResult___snd__h428588[56:34] : + (guard__h420256 == 2'b0) ? + _theResult___snd__h428279[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h429110 : - _theResult___snd__h428588[56:34]) ; + _theResult___sfd__h428801 : + _theResult___snd__h428279[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7412 = - (guard__h448494 == 2'b0 || + (guard__h448185 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h456542 : - _theResult___exp__h456984 ; + _theResult___fst_exp__h456233 : + _theResult___exp__h456675 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7414 = - (guard__h448494 == 2'b0) ? - _theResult___fst_exp__h456542 : + (guard__h448185 == 2'b0) ? + _theResult___fst_exp__h456233 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h456984 : - _theResult___fst_exp__h456542) ; + _theResult___exp__h456675 : + _theResult___fst_exp__h456233) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7806 = - (guard__h466260 == 2'b0 || + (guard__h465951 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h474337 : - _theResult___exp__h474804 ; + _theResult___fst_exp__h474028 : + _theResult___exp__h474495 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7808 = - (guard__h466260 == 2'b0) ? - _theResult___fst_exp__h474337 : + (guard__h465951 == 2'b0) ? + _theResult___fst_exp__h474028 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h474804 : - _theResult___fst_exp__h474337) ; + _theResult___exp__h474495 : + _theResult___fst_exp__h474028) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7856 = - (guard__h448494 == 2'b0 || + (guard__h448185 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___snd__h456493[56:34] : - _theResult___sfd__h456985 ; + _theResult___snd__h456184[56:34] : + _theResult___sfd__h456676 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7858 = - (guard__h448494 == 2'b0) ? - _theResult___snd__h456493[56:34] : + (guard__h448185 == 2'b0) ? + _theResult___snd__h456184[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h456985 : - _theResult___snd__h456493[56:34]) ; + _theResult___sfd__h456676 : + _theResult___snd__h456184[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7902 = - (guard__h466260 == 2'b0 || + (guard__h465951 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___snd__h474283[56:34] : - _theResult___sfd__h474805 ; + _theResult___snd__h473974[56:34] : + _theResult___sfd__h474496 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7904 = - (guard__h466260 == 2'b0) ? - _theResult___snd__h474283[56:34] : + (guard__h465951 == 2'b0) ? + _theResult___snd__h473974[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h474805 : - _theResult___snd__h474283[56:34]) ; + _theResult___sfd__h474496 : + _theResult___snd__h473974[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10018 = - (_theResult___fst_exp__h582491 == 11'd2047) ? + (_theResult___fst_exp__h582182 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -21256,10 +21091,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard74530_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q173) ; + CASE_guard74221_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10045 = - (_theResult___fst_exp__h600901 == 11'd2047) ? + (_theResult___fst_exp__h600592 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -21267,10 +21102,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard92911_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q171) ; + CASE_guard92602_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10581 = - (_theResult___fst_exp__h561597 == 11'd2047) ? + (_theResult___fst_exp__h561288 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -21278,10 +21113,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard53607_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196) ; + CASE_guard53298_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q190) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10787 = - (_theResult___fst_exp__h543187 == 11'd2047) ? + (_theResult___fst_exp__h542878 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -21289,10 +21124,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard35226_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q204) ; + CASE_guard34917_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10814 = - (_theResult___fst_exp__h561597 == 11'd2047) ? + (_theResult___fst_exp__h561288 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -21300,10 +21135,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard53607_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202) ; + CASE_guard53298_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9096 = - (_theResult___fst_exp__h522744 == 11'd2047) ? + (_theResult___fst_exp__h522435 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : @@ -21311,10 +21146,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard14754_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q150) ; + CASE_guard14445_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q142) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9811 = - (_theResult___fst_exp__h600901 == 11'd2047) ? + (_theResult___fst_exp__h600592 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -21322,76 +21157,76 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard92911_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q167) ; - assign IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005 = - (_theResult____h655044 == 16'd0 && + CASE_guard92602_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q159) ; + assign IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001 = + (_theResult____h654708 == 16'd0 && (csrf_prv_reg == 2'd0 || csrf_prv_reg == 2'd1 && csrf_ie_vec_1)) ? - enabled_ints__h655616 : - _theResult____h655044 ; - assign IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13222 = - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[0] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[1] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[2] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[3] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[4] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[5] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[6] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[7] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[8] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[9] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[10] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[11] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[12] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[13] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[14] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[15] || - checkForException___d13180[4] || - csrf_fs_reg_read__1726_EQ_0_3169_AND_fetchStag_ETC___d13215 || + enabled_ints__h655280 : + _theResult____h654708 ; + assign IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13218 = + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[0] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[1] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[2] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[3] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[4] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[5] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[6] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[7] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[8] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[9] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[10] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[11] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[12] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[13] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[14] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[15] || + checkForException___d13176[4] || + csrf_fs_reg_read__1726_EQ_0_3165_AND_fetchStag_ETC___d13211 || fetchStage$pipelines_0_first[231:200] == 32'h10500073 && csrf_tw_reg && csrf_prv_reg != 2'd3 ; - assign IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13921 = - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[0] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[1] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[2] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[3] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[4] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[5] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[6] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[7] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[8] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[9] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[10] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[11] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[12] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[13] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[14] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[15] || - checkForException___d13180[4] || - csrf_fs_reg_read__1726_EQ_0_3169_AND_fetchStag_ETC___d13676 ; - assign IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13958 = - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[0] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[1] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[2] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[3] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[4] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[5] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[6] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[7] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[8] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[9] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[10] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[11] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[12] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[13] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[14] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[15] || - checkForException___d13863[4] || - csrf_fs_reg_read__1726_EQ_0_3169_AND_fetchStag_ETC___d13956 ; + assign IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13917 = + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[0] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[1] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[2] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[3] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[4] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[5] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[6] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[7] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[8] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[9] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[10] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[11] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[12] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[13] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[14] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[15] || + checkForException___d13176[4] || + csrf_fs_reg_read__1726_EQ_0_3165_AND_fetchStag_ETC___d13672 ; + assign IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13954 = + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[0] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[1] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[2] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[3] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[4] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[5] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[6] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[7] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[8] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[9] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[10] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[11] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[12] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[13] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[14] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[15] || + checkForException___d13859[4] || + csrf_fs_reg_read__1726_EQ_0_3165_AND_fetchStag_ETC___d13952 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10048 = - (f3_exp__h563244 == 8'd0) ? + (f3_exp__h562935 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9351 ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9353 ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != @@ -21401,85 +21236,85 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10020) : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10047 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10049 = - (f3_exp__h563244 == 8'd255 && f3_sfd__h563245 != 23'd0 || - (f3_exp__h563244 == 8'd255 || f3_exp__h563244 == 8'd0) && - f3_sfd__h563245 == 23'd0) ? + (f3_exp__h562935 == 8'd255 && f3_sfd__h562936 != 23'd0 || + (f3_exp__h562935 == 8'd255 || f3_exp__h562935 == 8'd0) && + f3_sfd__h562936 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10048 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10194 = - ((f2_exp__h523940 == 8'd0) ? - (f2_sfd__h523941[22] ? + ((f2_exp__h523631 == 8'd0) ? + (f2_sfd__h523632[22] ? 6'd2 : - (f2_sfd__h523941[21] ? + (f2_sfd__h523632[21] ? 6'd3 : - (f2_sfd__h523941[20] ? + (f2_sfd__h523632[20] ? 6'd4 : - (f2_sfd__h523941[19] ? + (f2_sfd__h523632[19] ? 6'd5 : - (f2_sfd__h523941[18] ? + (f2_sfd__h523632[18] ? 6'd6 : - (f2_sfd__h523941[17] ? + (f2_sfd__h523632[17] ? 6'd7 : - (f2_sfd__h523941[16] ? + (f2_sfd__h523632[16] ? 6'd8 : - (f2_sfd__h523941[15] ? + (f2_sfd__h523632[15] ? 6'd9 : - (f2_sfd__h523941[14] ? + (f2_sfd__h523632[14] ? 6'd10 : - (f2_sfd__h523941[13] ? + (f2_sfd__h523632[13] ? 6'd11 : - (f2_sfd__h523941[12] ? + (f2_sfd__h523632[12] ? 6'd12 : - (f2_sfd__h523941[11] ? + (f2_sfd__h523632[11] ? 6'd13 : - (f2_sfd__h523941[10] ? + (f2_sfd__h523632[10] ? 6'd14 : - (f2_sfd__h523941[9] ? + (f2_sfd__h523632[9] ? 6'd15 : - (f2_sfd__h523941[8] ? + (f2_sfd__h523632[8] ? 6'd16 : - (f2_sfd__h523941[7] ? + (f2_sfd__h523632[7] ? 6'd17 : - (f2_sfd__h523941[6] ? + (f2_sfd__h523632[6] ? 6'd18 : - (f2_sfd__h523941[5] ? + (f2_sfd__h523632[5] ? 6'd19 : - (f2_sfd__h523941[4] ? + (f2_sfd__h523632[4] ? 6'd20 : - (f2_sfd__h523941[3] ? + (f2_sfd__h523632[3] ? 6'd21 : - (f2_sfd__h523941[2] ? + (f2_sfd__h523632[2] ? 6'd22 : - (f2_sfd__h523941[1] ? + (f2_sfd__h523632[1] ? 6'd23 : - (f2_sfd__h523941[0] ? + (f2_sfd__h523632[0] ? 6'd24 : 6'd57))))))))))))))))))))))) : 6'd1) - 6'd1 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10585 = - (f2_exp__h523940 == 8'd255 && f2_sfd__h523941 != 23'd0 || - (f2_exp__h523940 == 8'd255 || f2_exp__h523940 == 8'd0) && - f2_sfd__h523941 == 23'd0) ? + (f2_exp__h523631 == 8'd255 && f2_sfd__h523632 != 23'd0 || + (f2_exp__h523631 == 8'd255 || f2_exp__h523631 == 8'd0) && + f2_sfd__h523632 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - ((f2_exp__h523940 == 8'd0) ? + ((f2_exp__h523631 == 8'd0) ? IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d10240 : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10583) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10762 = - (f2_exp__h523940 == 8'd255 && f2_sfd__h523941 != 23'd0) ? - _theResult___snd_fst_sfd__h524256 : - _theResult___fst_sfd__h562396 ; + (f2_exp__h523631 == 8'd255 && f2_sfd__h523632 != 23'd0) ? + _theResult___snd_fst_sfd__h523947 : + _theResult___fst_sfd__h562087 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10763 = - { (f2_exp__h523940 == 8'd255) ? + { (f2_exp__h523631 == 8'd255) ? 11'd2047 : - _theResult___fst_exp__h562392, + _theResult___fst_exp__h562083, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10762 } ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10817 = - (f2_exp__h523940 == 8'd0) ? + (f2_exp__h523631 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10121 ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10123 ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != @@ -21489,15 +21324,15 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10789) : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10816 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10818 = - (f2_exp__h523940 == 8'd255 && f2_sfd__h523941 != 23'd0 || - (f2_exp__h523940 == 8'd255 || f2_exp__h523940 == 8'd0) && - f2_sfd__h523941 == 23'd0) ? + (f2_exp__h523631 == 8'd255 && f2_sfd__h523632 != 23'd0 || + (f2_exp__h523631 == 8'd255 || f2_exp__h523631 == 8'd0) && + f2_sfd__h523632 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10817 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10873 = - (f1_exp__h484946 == 8'd0) ? + (f1_exp__h484637 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8621 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8623 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10852[4] : @@ -21505,7 +21340,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8759 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10869[4] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10914 = - (f2_exp__h523940 == 8'd0) ? + (f2_exp__h523631 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10121 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10123 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10893[4] : @@ -21513,7 +21348,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10244 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10910[4] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10958 = - (f3_exp__h563244 == 8'd0) ? + (f3_exp__h562935 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9351 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9353 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10937[4] : @@ -21521,7 +21356,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9474 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10954[4] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10973 = - (f1_exp__h484946 == 8'd0) ? + (f1_exp__h484637 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8621 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8623 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10852[3] : @@ -21529,7 +21364,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8759 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10869[3] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10983 = - (f2_exp__h523940 == 8'd0) ? + (f2_exp__h523631 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10121 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10123 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10893[3] : @@ -21537,7 +21372,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10244 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10910[3] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10994 = - (f3_exp__h563244 == 8'd0) ? + (f3_exp__h562935 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9351 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9353 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10937[3] : @@ -21545,208 +21380,208 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9474 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10954[3] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11013 = - (f1_exp__h484946 == 8'd0) ? + (f1_exp__h484637 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8621 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8623 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10852[2] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8758 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11011 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11027 = - (f2_exp__h523940 == 8'd0) ? + (f2_exp__h523631 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10121 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10123 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10893[2] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10243 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11025 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11042 = - (f3_exp__h563244 == 8'd0) ? + (f3_exp__h562935 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9351 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9353 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10937[2] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9473 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11040 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11059 = - (f1_exp__h484946 == 8'd0) ? + (f1_exp__h484637 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8621 && (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8623 || _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10852[1]) : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8758 && IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11057 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11071 = - (f2_exp__h523940 == 8'd0) ? + (f2_exp__h523631 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10121 && (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10123 || _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10893[1]) : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10243 && IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11069 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11084 = - (f3_exp__h563244 == 8'd0) ? + (f3_exp__h562935 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9351 && (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9353 || _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10937[1]) : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9473 && IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11082 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11101 = - (f1_exp__h484946 == 8'd0) ? + (f1_exp__h484637 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8621 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8623 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10852[0] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8758 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11099 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11113 = - (f2_exp__h523940 == 8'd0) ? + (f2_exp__h523631 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10121 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10123 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10893[0] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10243 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11111 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11126 = - (f3_exp__h563244 == 8'd0) ? + (f3_exp__h562935 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9351 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9353 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10937[0] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9473 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11124 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8694 = - ((f1_exp__h484946 == 8'd0) ? - (f1_sfd__h484947[22] ? + ((f1_exp__h484637 == 8'd0) ? + (f1_sfd__h484638[22] ? 6'd2 : - (f1_sfd__h484947[21] ? + (f1_sfd__h484638[21] ? 6'd3 : - (f1_sfd__h484947[20] ? + (f1_sfd__h484638[20] ? 6'd4 : - (f1_sfd__h484947[19] ? + (f1_sfd__h484638[19] ? 6'd5 : - (f1_sfd__h484947[18] ? + (f1_sfd__h484638[18] ? 6'd6 : - (f1_sfd__h484947[17] ? + (f1_sfd__h484638[17] ? 6'd7 : - (f1_sfd__h484947[16] ? + (f1_sfd__h484638[16] ? 6'd8 : - (f1_sfd__h484947[15] ? + (f1_sfd__h484638[15] ? 6'd9 : - (f1_sfd__h484947[14] ? + (f1_sfd__h484638[14] ? 6'd10 : - (f1_sfd__h484947[13] ? + (f1_sfd__h484638[13] ? 6'd11 : - (f1_sfd__h484947[12] ? + (f1_sfd__h484638[12] ? 6'd12 : - (f1_sfd__h484947[11] ? + (f1_sfd__h484638[11] ? 6'd13 : - (f1_sfd__h484947[10] ? + (f1_sfd__h484638[10] ? 6'd14 : - (f1_sfd__h484947[9] ? + (f1_sfd__h484638[9] ? 6'd15 : - (f1_sfd__h484947[8] ? + (f1_sfd__h484638[8] ? 6'd16 : - (f1_sfd__h484947[7] ? + (f1_sfd__h484638[7] ? 6'd17 : - (f1_sfd__h484947[6] ? + (f1_sfd__h484638[6] ? 6'd18 : - (f1_sfd__h484947[5] ? + (f1_sfd__h484638[5] ? 6'd19 : - (f1_sfd__h484947[4] ? + (f1_sfd__h484638[4] ? 6'd20 : - (f1_sfd__h484947[3] ? + (f1_sfd__h484638[3] ? 6'd21 : - (f1_sfd__h484947[2] ? + (f1_sfd__h484638[2] ? 6'd22 : - (f1_sfd__h484947[1] ? + (f1_sfd__h484638[1] ? 6'd23 : - (f1_sfd__h484947[0] ? + (f1_sfd__h484638[0] ? 6'd24 : 6'd57))))))))))))))))))))))) : 6'd1) - 6'd1 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9100 = - (f1_exp__h484946 == 8'd255 && f1_sfd__h484947 != 23'd0 || - (f1_exp__h484946 == 8'd255 || f1_exp__h484946 == 8'd0) && - f1_sfd__h484947 == 23'd0) ? + (f1_exp__h484637 == 8'd255 && f1_sfd__h484638 != 23'd0 || + (f1_exp__h484637 == 8'd255 || f1_exp__h484637 == 8'd0) && + f1_sfd__h484638 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - ((f1_exp__h484946 == 8'd0) ? + ((f1_exp__h484637 == 8'd0) ? IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d8755 : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9098) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9283 = - (f1_exp__h484946 == 8'd255 && f1_sfd__h484947 != 23'd0) ? - _theResult___snd_fst_sfd__h485262 : - _theResult___fst_sfd__h523543 ; + (f1_exp__h484637 == 8'd255 && f1_sfd__h484638 != 23'd0) ? + _theResult___snd_fst_sfd__h484953 : + _theResult___fst_sfd__h523234 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9284 = { IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9100, - (f1_exp__h484946 == 8'd255) ? + (f1_exp__h484637 == 8'd255) ? 11'd2047 : - _theResult___fst_exp__h523539, + _theResult___fst_exp__h523230, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9283 } ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9424 = - ((f3_exp__h563244 == 8'd0) ? - (f3_sfd__h563245[22] ? + ((f3_exp__h562935 == 8'd0) ? + (f3_sfd__h562936[22] ? 6'd2 : - (f3_sfd__h563245[21] ? + (f3_sfd__h562936[21] ? 6'd3 : - (f3_sfd__h563245[20] ? + (f3_sfd__h562936[20] ? 6'd4 : - (f3_sfd__h563245[19] ? + (f3_sfd__h562936[19] ? 6'd5 : - (f3_sfd__h563245[18] ? + (f3_sfd__h562936[18] ? 6'd6 : - (f3_sfd__h563245[17] ? + (f3_sfd__h562936[17] ? 6'd7 : - (f3_sfd__h563245[16] ? + (f3_sfd__h562936[16] ? 6'd8 : - (f3_sfd__h563245[15] ? + (f3_sfd__h562936[15] ? 6'd9 : - (f3_sfd__h563245[14] ? + (f3_sfd__h562936[14] ? 6'd10 : - (f3_sfd__h563245[13] ? + (f3_sfd__h562936[13] ? 6'd11 : - (f3_sfd__h563245[12] ? + (f3_sfd__h562936[12] ? 6'd12 : - (f3_sfd__h563245[11] ? + (f3_sfd__h562936[11] ? 6'd13 : - (f3_sfd__h563245[10] ? + (f3_sfd__h562936[10] ? 6'd14 : - (f3_sfd__h563245[9] ? + (f3_sfd__h562936[9] ? 6'd15 : - (f3_sfd__h563245[8] ? + (f3_sfd__h562936[8] ? 6'd16 : - (f3_sfd__h563245[7] ? + (f3_sfd__h562936[7] ? 6'd17 : - (f3_sfd__h563245[6] ? + (f3_sfd__h562936[6] ? 6'd18 : - (f3_sfd__h563245[5] ? + (f3_sfd__h562936[5] ? 6'd19 : - (f3_sfd__h563245[4] ? + (f3_sfd__h562936[4] ? 6'd20 : - (f3_sfd__h563245[3] ? + (f3_sfd__h562936[3] ? 6'd21 : - (f3_sfd__h563245[2] ? + (f3_sfd__h562936[2] ? 6'd22 : - (f3_sfd__h563245[1] ? + (f3_sfd__h562936[1] ? 6'd23 : - (f3_sfd__h563245[0] ? + (f3_sfd__h562936[0] ? 6'd24 : 6'd57))))))))))))))))))))))) : 6'd1) - 6'd1 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9815 = - (f3_exp__h563244 == 8'd255 && f3_sfd__h563245 != 23'd0 || - (f3_exp__h563244 == 8'd255 || f3_exp__h563244 == 8'd0) && - f3_sfd__h563245 == 23'd0) ? + (f3_exp__h562935 == 8'd255 && f3_sfd__h562936 != 23'd0 || + (f3_exp__h562935 == 8'd255 || f3_exp__h562935 == 8'd0) && + f3_sfd__h562936 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - ((f3_exp__h563244 == 8'd0) ? + ((f3_exp__h562935 == 8'd0) ? IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d9470 : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9813) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9992 = - (f3_exp__h563244 == 8'd255 && f3_sfd__h563245 != 23'd0) ? - _theResult___snd_fst_sfd__h563560 : - _theResult___fst_sfd__h601700 ; + (f3_exp__h562935 == 8'd255 && f3_sfd__h562936 != 23'd0) ? + _theResult___snd_fst_sfd__h563251 : + _theResult___fst_sfd__h601391 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9993 = - { (f3_exp__h563244 == 8'd255) ? + { (f3_exp__h562935 == 8'd255) ? 11'd2047 : - _theResult___fst_exp__h601696, + _theResult___fst_exp__h601387, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9992 } ; assign IF_IF_coreFix_memExe_dTlb_procResp__740_BIT_11_ETC___d1875 = IF_coreFix_memExe_dTlb_procResp__740_BIT_110_7_ETC___d1864 ? @@ -21786,110 +21621,110 @@ module mkCore(CLK, (IF_coreFix_memExe_dTlb_procResp__740_BIT_110_7_ETC___d1828 ? 4'd1 : IF_IF_coreFix_memExe_dTlb_procResp__740_BIT_11_ETC___d1883) ; - assign IF_IF_fetchStage_pipelines_0_first__2934_BIT_6_ETC___d13368 = + assign IF_IF_fetchStage_pipelines_0_first__2931_BIT_6_ETC___d13364 = (fetchStage$pipelines_0_first[68] ? - IF_fetchStage_pipelines_0_first__2934_BIT_68_2_ETC___d13300 == + IF_fetchStage_pipelines_0_first__2931_BIT_68_2_ETC___d13296 == 4'd12 : - IF_checkForException_3180_BIT_4_3181_THEN_IF_c_ETC___d13329 == + IF_checkForException_3176_BIT_4_3177_THEN_IF_c_ETC___d13325 == 4'd12) ? 4'd13 : 4'd15 ; - assign IF_IF_fetchStage_pipelines_0_first__2934_BIT_6_ETC___d13369 = + assign IF_IF_fetchStage_pipelines_0_first__2931_BIT_6_ETC___d13365 = (fetchStage$pipelines_0_first[68] ? - IF_fetchStage_pipelines_0_first__2934_BIT_68_2_ETC___d13300 == + IF_fetchStage_pipelines_0_first__2931_BIT_68_2_ETC___d13296 == 4'd11 : - IF_checkForException_3180_BIT_4_3181_THEN_IF_c_ETC___d13329 == + IF_checkForException_3176_BIT_4_3177_THEN_IF_c_ETC___d13325 == 4'd11) ? 4'd12 : - IF_IF_fetchStage_pipelines_0_first__2934_BIT_6_ETC___d13368 ; - assign IF_IF_fetchStage_pipelines_0_first__2934_BIT_6_ETC___d13370 = + IF_IF_fetchStage_pipelines_0_first__2931_BIT_6_ETC___d13364 ; + assign IF_IF_fetchStage_pipelines_0_first__2931_BIT_6_ETC___d13366 = (fetchStage$pipelines_0_first[68] ? - IF_fetchStage_pipelines_0_first__2934_BIT_68_2_ETC___d13300 == + IF_fetchStage_pipelines_0_first__2931_BIT_68_2_ETC___d13296 == 4'd10 : - IF_checkForException_3180_BIT_4_3181_THEN_IF_c_ETC___d13329 == + IF_checkForException_3176_BIT_4_3177_THEN_IF_c_ETC___d13325 == 4'd10) ? 4'd11 : - IF_IF_fetchStage_pipelines_0_first__2934_BIT_6_ETC___d13369 ; - assign IF_IF_fetchStage_pipelines_0_first__2934_BIT_6_ETC___d13371 = + IF_IF_fetchStage_pipelines_0_first__2931_BIT_6_ETC___d13365 ; + assign IF_IF_fetchStage_pipelines_0_first__2931_BIT_6_ETC___d13367 = (fetchStage$pipelines_0_first[68] ? - IF_fetchStage_pipelines_0_first__2934_BIT_68_2_ETC___d13300 == + IF_fetchStage_pipelines_0_first__2931_BIT_68_2_ETC___d13296 == 4'd9 : - IF_checkForException_3180_BIT_4_3181_THEN_IF_c_ETC___d13329 == + IF_checkForException_3176_BIT_4_3177_THEN_IF_c_ETC___d13325 == 4'd9) ? 4'd9 : - IF_IF_fetchStage_pipelines_0_first__2934_BIT_6_ETC___d13370 ; - assign IF_IF_fetchStage_pipelines_0_first__2934_BIT_6_ETC___d13372 = + IF_IF_fetchStage_pipelines_0_first__2931_BIT_6_ETC___d13366 ; + assign IF_IF_fetchStage_pipelines_0_first__2931_BIT_6_ETC___d13368 = (fetchStage$pipelines_0_first[68] ? - IF_fetchStage_pipelines_0_first__2934_BIT_68_2_ETC___d13300 == + IF_fetchStage_pipelines_0_first__2931_BIT_68_2_ETC___d13296 == 4'd8 : - IF_checkForException_3180_BIT_4_3181_THEN_IF_c_ETC___d13329 == + IF_checkForException_3176_BIT_4_3177_THEN_IF_c_ETC___d13325 == 4'd8) ? 4'd8 : - IF_IF_fetchStage_pipelines_0_first__2934_BIT_6_ETC___d13371 ; - assign IF_IF_fetchStage_pipelines_0_first__2934_BIT_6_ETC___d13373 = + IF_IF_fetchStage_pipelines_0_first__2931_BIT_6_ETC___d13367 ; + assign IF_IF_fetchStage_pipelines_0_first__2931_BIT_6_ETC___d13369 = (fetchStage$pipelines_0_first[68] ? - IF_fetchStage_pipelines_0_first__2934_BIT_68_2_ETC___d13300 == + IF_fetchStage_pipelines_0_first__2931_BIT_68_2_ETC___d13296 == 4'd7 : - IF_checkForException_3180_BIT_4_3181_THEN_IF_c_ETC___d13329 == + IF_checkForException_3176_BIT_4_3177_THEN_IF_c_ETC___d13325 == 4'd7) ? 4'd7 : - IF_IF_fetchStage_pipelines_0_first__2934_BIT_6_ETC___d13372 ; - assign IF_IF_fetchStage_pipelines_0_first__2934_BIT_6_ETC___d13374 = + IF_IF_fetchStage_pipelines_0_first__2931_BIT_6_ETC___d13368 ; + assign IF_IF_fetchStage_pipelines_0_first__2931_BIT_6_ETC___d13370 = (fetchStage$pipelines_0_first[68] ? - IF_fetchStage_pipelines_0_first__2934_BIT_68_2_ETC___d13300 == + IF_fetchStage_pipelines_0_first__2931_BIT_68_2_ETC___d13296 == 4'd6 : - IF_checkForException_3180_BIT_4_3181_THEN_IF_c_ETC___d13329 == + IF_checkForException_3176_BIT_4_3177_THEN_IF_c_ETC___d13325 == 4'd6) ? 4'd6 : - IF_IF_fetchStage_pipelines_0_first__2934_BIT_6_ETC___d13373 ; - assign IF_IF_fetchStage_pipelines_0_first__2934_BIT_6_ETC___d13375 = + IF_IF_fetchStage_pipelines_0_first__2931_BIT_6_ETC___d13369 ; + assign IF_IF_fetchStage_pipelines_0_first__2931_BIT_6_ETC___d13371 = (fetchStage$pipelines_0_first[68] ? - IF_fetchStage_pipelines_0_first__2934_BIT_68_2_ETC___d13300 == + IF_fetchStage_pipelines_0_first__2931_BIT_68_2_ETC___d13296 == 4'd5 : - IF_checkForException_3180_BIT_4_3181_THEN_IF_c_ETC___d13329 == + IF_checkForException_3176_BIT_4_3177_THEN_IF_c_ETC___d13325 == 4'd5) ? 4'd5 : - IF_IF_fetchStage_pipelines_0_first__2934_BIT_6_ETC___d13374 ; - assign IF_IF_fetchStage_pipelines_0_first__2934_BIT_6_ETC___d13376 = + IF_IF_fetchStage_pipelines_0_first__2931_BIT_6_ETC___d13370 ; + assign IF_IF_fetchStage_pipelines_0_first__2931_BIT_6_ETC___d13372 = (fetchStage$pipelines_0_first[68] ? - IF_fetchStage_pipelines_0_first__2934_BIT_68_2_ETC___d13300 == + IF_fetchStage_pipelines_0_first__2931_BIT_68_2_ETC___d13296 == 4'd4 : - IF_checkForException_3180_BIT_4_3181_THEN_IF_c_ETC___d13329 == + IF_checkForException_3176_BIT_4_3177_THEN_IF_c_ETC___d13325 == 4'd4) ? 4'd4 : - IF_IF_fetchStage_pipelines_0_first__2934_BIT_6_ETC___d13375 ; - assign IF_IF_fetchStage_pipelines_0_first__2934_BIT_6_ETC___d13377 = + IF_IF_fetchStage_pipelines_0_first__2931_BIT_6_ETC___d13371 ; + assign IF_IF_fetchStage_pipelines_0_first__2931_BIT_6_ETC___d13373 = (fetchStage$pipelines_0_first[68] ? - IF_fetchStage_pipelines_0_first__2934_BIT_68_2_ETC___d13300 == + IF_fetchStage_pipelines_0_first__2931_BIT_68_2_ETC___d13296 == 4'd3 : - IF_checkForException_3180_BIT_4_3181_THEN_IF_c_ETC___d13329 == + IF_checkForException_3176_BIT_4_3177_THEN_IF_c_ETC___d13325 == 4'd3) ? 4'd3 : - IF_IF_fetchStage_pipelines_0_first__2934_BIT_6_ETC___d13376 ; - assign IF_IF_fetchStage_pipelines_0_first__2934_BIT_6_ETC___d13378 = + IF_IF_fetchStage_pipelines_0_first__2931_BIT_6_ETC___d13372 ; + assign IF_IF_fetchStage_pipelines_0_first__2931_BIT_6_ETC___d13374 = (fetchStage$pipelines_0_first[68] ? - IF_fetchStage_pipelines_0_first__2934_BIT_68_2_ETC___d13300 == + IF_fetchStage_pipelines_0_first__2931_BIT_68_2_ETC___d13296 == 4'd2 : - IF_checkForException_3180_BIT_4_3181_THEN_IF_c_ETC___d13329 == + IF_checkForException_3176_BIT_4_3177_THEN_IF_c_ETC___d13325 == 4'd2) ? 4'd2 : - IF_IF_fetchStage_pipelines_0_first__2934_BIT_6_ETC___d13377 ; - assign IF_IF_fetchStage_pipelines_0_first__2934_BIT_6_ETC___d13379 = + IF_IF_fetchStage_pipelines_0_first__2931_BIT_6_ETC___d13373 ; + assign IF_IF_fetchStage_pipelines_0_first__2931_BIT_6_ETC___d13375 = (fetchStage$pipelines_0_first[68] ? - IF_fetchStage_pipelines_0_first__2934_BIT_68_2_ETC___d13300 == + IF_fetchStage_pipelines_0_first__2931_BIT_68_2_ETC___d13296 == 4'd1 : - IF_checkForException_3180_BIT_4_3181_THEN_IF_c_ETC___d13329 == + IF_checkForException_3176_BIT_4_3177_THEN_IF_c_ETC___d13325 == 4'd1) ? 4'd1 : - IF_IF_fetchStage_pipelines_0_first__2934_BIT_6_ETC___d13378 ; - assign IF_IF_fetchStage_pipelines_0_first__2934_BIT_6_ETC___d13380 = + IF_IF_fetchStage_pipelines_0_first__2931_BIT_6_ETC___d13374 ; + assign IF_IF_fetchStage_pipelines_0_first__2931_BIT_6_ETC___d13376 = (fetchStage$pipelines_0_first[68] ? - IF_fetchStage_pipelines_0_first__2934_BIT_68_2_ETC___d13300 == + IF_fetchStage_pipelines_0_first__2931_BIT_68_2_ETC___d13296 == 4'd0 : - IF_checkForException_3180_BIT_4_3181_THEN_IF_c_ETC___d13329 == + IF_checkForException_3176_BIT_4_3177_THEN_IF_c_ETC___d13325 == 4'd0) ? 4'd0 : - IF_IF_fetchStage_pipelines_0_first__2934_BIT_6_ETC___d13379 ; + IF_IF_fetchStage_pipelines_0_first__2931_BIT_6_ETC___d13375 ; assign IF_IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmi_ETC___d463 = { (mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[77:76] == 2'd1 : @@ -21952,7 +21787,7 @@ module mkCore(CLK, assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d10240 = (!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10121 || _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10123 || - _theResult___fst_exp__h543187 == 11'd2047) ? + _theResult___fst_exp__h542878 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -21960,12 +21795,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard35226_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194) ; + CASE_guard34917_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q186) ; assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d8755 = (!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8621 || _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8623 || - _theResult___fst_exp__h504334 == 11'd2047) ? + _theResult___fst_exp__h504025 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : @@ -21973,12 +21808,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard96373_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q148) ; + CASE_guard96064_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q138) ; assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d9470 = (!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9351 || _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9353 || - _theResult___fst_exp__h582491 == 11'd2047) ? + _theResult___fst_exp__h582182 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -21986,137 +21821,137 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard74530_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163) ; - assign IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3__ETC___d13413 = - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[0] ? + CASE_guard74221_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q155) ; + assign IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3__ETC___d13409 = + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[0] ? 4'd0 : - (IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[1] ? + (IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[1] ? 4'd1 : - ((IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[3] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[2]) ? + ((IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[3] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[2]) ? 4'd2 : - ((IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[4] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[2] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[3]) ? + ((IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[4] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[2] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[3]) ? 4'd3 : - ((IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[5] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[2] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[3] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[4]) ? + ((IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[5] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[2] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[3] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[4]) ? 4'd4 : - ((IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[7] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[2] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[3] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[4] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[5] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[6]) ? + ((IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[7] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[2] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[3] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[4] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[5] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[6]) ? 4'd5 : - ((IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[8] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[2] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[3] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[4] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[5] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[6] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[7]) ? + ((IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[8] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[2] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[3] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[4] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[5] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[6] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[7]) ? 4'd6 : - ((IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[9] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[2] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[3] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[4] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[5] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[6] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[7] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[8]) ? + ((IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[9] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[2] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[3] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[4] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[5] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[6] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[7] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[8]) ? 4'd7 : - ((IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[11] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[2] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[3] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[4] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[5] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[6] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[7] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[8] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[9] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[10]) ? + ((IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[11] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[2] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[3] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[4] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[5] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[6] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[7] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[8] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[9] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[10]) ? 4'd8 : - ((IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[14] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[2] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[3] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[4] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[5] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[6] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[7] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[8] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[9] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[10] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[11] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[12] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[13]) ? + ((IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[14] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[2] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[3] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[4] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[5] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[6] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[7] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[8] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[9] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[10] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[11] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[12] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[13]) ? 4'd9 : 4'd10))))))))) ; - assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__237_ETC___d12407 = + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12404 = (!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_aluExe_0_bypassWire_0_wget__2373_BITS__ETC___d12375) ? + !coreFix_aluExe_0_bypassWire_0_wget__2370_BITS__ETC___d12372) ? coreFix_aluExe_0_bypassWire_1$whas && - coreFix_aluExe_0_bypassWire_1_wget__2386_BITS__ETC___d12388 : + coreFix_aluExe_0_bypassWire_1_wget__2383_BITS__ETC___d12385 : coreFix_aluExe_0_bypassWire_0$whas ; - assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__237_ETC___d12408 = + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12405 = ((!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_aluExe_0_bypassWire_0_wget__2373_BITS__ETC___d12375) && + !coreFix_aluExe_0_bypassWire_0_wget__2370_BITS__ETC___d12372) && (!coreFix_aluExe_0_bypassWire_1$whas || - !coreFix_aluExe_0_bypassWire_1_wget__2386_BITS__ETC___d12388)) ? + !coreFix_aluExe_0_bypassWire_1_wget__2383_BITS__ETC___d12385)) ? coreFix_aluExe_0_bypassWire_2$whas && - coreFix_aluExe_0_bypassWire_2_wget__2394_BITS__ETC___d12396 : - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__237_ETC___d12407 ; - assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__237_ETC___d12409 = - NOT_coreFix_aluExe_0_bypassWire_0_whas__2372_2_ETC___d12399 ? + coreFix_aluExe_0_bypassWire_2_wget__2391_BITS__ETC___d12393 : + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12404 ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12406 = + NOT_coreFix_aluExe_0_bypassWire_0_whas__2369_2_ETC___d12396 ? coreFix_aluExe_0_bypassWire_3$whas && - coreFix_aluExe_0_bypassWire_3_wget__2401_BITS__ETC___d12403 : - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__237_ETC___d12408 ; - assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__237_ETC___d12434 = + coreFix_aluExe_0_bypassWire_3_wget__2398_BITS__ETC___d12400 : + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12405 ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12431 = (!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_aluExe_0_bypassWire_0_wget__2373_BITS__ETC___d12416) ? + !coreFix_aluExe_0_bypassWire_0_wget__2370_BITS__ETC___d12413) ? coreFix_aluExe_0_bypassWire_1$whas && - coreFix_aluExe_0_bypassWire_1_wget__2386_BITS__ETC___d12422 : + coreFix_aluExe_0_bypassWire_1_wget__2383_BITS__ETC___d12419 : coreFix_aluExe_0_bypassWire_0$whas ; - assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__237_ETC___d12435 = + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12432 = ((!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_aluExe_0_bypassWire_0_wget__2373_BITS__ETC___d12416) && + !coreFix_aluExe_0_bypassWire_0_wget__2370_BITS__ETC___d12413) && (!coreFix_aluExe_0_bypassWire_1$whas || - !coreFix_aluExe_0_bypassWire_1_wget__2386_BITS__ETC___d12422)) ? + !coreFix_aluExe_0_bypassWire_1_wget__2383_BITS__ETC___d12419)) ? coreFix_aluExe_0_bypassWire_2$whas && - coreFix_aluExe_0_bypassWire_2_wget__2394_BITS__ETC___d12426 : - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__237_ETC___d12434 ; - assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__237_ETC___d12436 = - NOT_coreFix_aluExe_0_bypassWire_0_whas__2372_2_ETC___d12429 ? + coreFix_aluExe_0_bypassWire_2_wget__2391_BITS__ETC___d12423 : + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12431 ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12433 = + NOT_coreFix_aluExe_0_bypassWire_0_whas__2369_2_ETC___d12426 ? coreFix_aluExe_0_bypassWire_3$whas && - coreFix_aluExe_0_bypassWire_3_wget__2401_BITS__ETC___d12430 : - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__237_ETC___d12435 ; - assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__237_ETC___d12622 = + coreFix_aluExe_0_bypassWire_3_wget__2398_BITS__ETC___d12427 : + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12432 ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12619 = (!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_aluExe_0_bypassWire_0_wget__2373_BITS__ETC___d12375) ? + !coreFix_aluExe_0_bypassWire_0_wget__2370_BITS__ETC___d12372) ? coreFix_aluExe_0_bypassWire_1$wget[63:0] : coreFix_aluExe_0_bypassWire_0$wget[63:0] ; - assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__237_ETC___d12623 = + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12620 = ((!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_aluExe_0_bypassWire_0_wget__2373_BITS__ETC___d12375) && + !coreFix_aluExe_0_bypassWire_0_wget__2370_BITS__ETC___d12372) && (!coreFix_aluExe_0_bypassWire_1$whas || - !coreFix_aluExe_0_bypassWire_1_wget__2386_BITS__ETC___d12388)) ? + !coreFix_aluExe_0_bypassWire_1_wget__2383_BITS__ETC___d12385)) ? coreFix_aluExe_0_bypassWire_2$wget[63:0] : - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__237_ETC___d12622 ; - assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__237_ETC___d12631 = + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12619 ; + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12628 = (!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_aluExe_0_bypassWire_0_wget__2373_BITS__ETC___d12416) ? + !coreFix_aluExe_0_bypassWire_0_wget__2370_BITS__ETC___d12413) ? coreFix_aluExe_0_bypassWire_1$wget[63:0] : coreFix_aluExe_0_bypassWire_0$wget[63:0] ; - assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__237_ETC___d12632 = + assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12629 = ((!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_aluExe_0_bypassWire_0_wget__2373_BITS__ETC___d12416) && + !coreFix_aluExe_0_bypassWire_0_wget__2370_BITS__ETC___d12413) && (!coreFix_aluExe_0_bypassWire_1$whas || - !coreFix_aluExe_0_bypassWire_1_wget__2386_BITS__ETC___d12422)) ? + !coreFix_aluExe_0_bypassWire_1_wget__2383_BITS__ETC___d12419)) ? coreFix_aluExe_0_bypassWire_2$wget[63:0] : - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__237_ETC___d12631 ; + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12628 ; assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11545 = (!coreFix_aluExe_0_bypassWire_0$whas || !coreFix_aluExe_1_bypassWire_0_wget__1511_BITS__ETC___d11513) ? @@ -22155,30 +21990,30 @@ module mkCore(CLK, coreFix_aluExe_1_bypassWire_3$whas && coreFix_aluExe_1_bypassWire_3_wget__1539_BITS__ETC___d11568 : IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11573 ; - assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11948 = + assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11945 = (!coreFix_aluExe_0_bypassWire_0$whas || !coreFix_aluExe_1_bypassWire_0_wget__1511_BITS__ETC___d11513) ? coreFix_aluExe_0_bypassWire_1$wget[63:0] : coreFix_aluExe_0_bypassWire_0$wget[63:0] ; - assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11949 = + assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11946 = ((!coreFix_aluExe_0_bypassWire_0$whas || !coreFix_aluExe_1_bypassWire_0_wget__1511_BITS__ETC___d11513) && (!coreFix_aluExe_0_bypassWire_1$whas || !coreFix_aluExe_1_bypassWire_1_wget__1524_BITS__ETC___d11526)) ? coreFix_aluExe_0_bypassWire_2$wget[63:0] : - IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11948 ; - assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11957 = + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11945 ; + assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11954 = (!coreFix_aluExe_0_bypassWire_0$whas || !coreFix_aluExe_1_bypassWire_0_wget__1511_BITS__ETC___d11554) ? coreFix_aluExe_0_bypassWire_1$wget[63:0] : coreFix_aluExe_0_bypassWire_0$wget[63:0] ; - assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11958 = + assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11955 = ((!coreFix_aluExe_0_bypassWire_0$whas || !coreFix_aluExe_1_bypassWire_0_wget__1511_BITS__ETC___d11554) && (!coreFix_aluExe_0_bypassWire_1$whas || !coreFix_aluExe_1_bypassWire_1_wget__1524_BITS__ETC___d11560)) ? coreFix_aluExe_0_bypassWire_2$wget[63:0] : - IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11957 ; + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11954 ; assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8335 = (!coreFix_aluExe_0_bypassWire_0$whas || !coreFix_fpuMulDivExe_0_bypassWire_0_wget__301__ETC___d8303) ? @@ -22365,104 +22200,104 @@ module mkCore(CLK, assign IF_NOT_coreFix_memExe_dTlb_procResp__740_BIT_1_ETC___d1819 = (!coreFix_memExe_dTlb$procResp[110] && coreFix_memExe_dTlb$procResp[12]) ? - CASE_coreFix_memExe_dTlbprocResp_BITS_105_TO__ETC__q21 : - CASE_coreFix_memExe_dTlbprocResp_BITS_109_TO__ETC__q22 ; - assign IF_NOT_fetchStage_pipelines_0_canDeq__2932_293_ETC___d14073 = + CASE_coreFix_memExe_dTlbprocResp_BITS_105_TO__ETC__q13 : + CASE_coreFix_memExe_dTlbprocResp_BITS_109_TO__ETC__q14 ; + assign IF_NOT_fetchStage_pipelines_0_canDeq__2929_293_ETC___d14069 = ((!fetchStage$pipelines_0_canDeq || - NOT_fetchStage_pipelines_0_first__2934_BITS_19_ETC___d13640) && + NOT_fetchStage_pipelines_0_first__2931_BITS_19_ETC___d13636) && fetchStage$pipelines_1_canDeq) ? fetchStage$RDY_pipelines_1_first && (fetchStage$pipelines_1_first[194:192] != 3'd1 || !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first) && - IF_fetchStage_RDY_pipelines_1_first__2942_AND__ETC___d14070 : + IF_fetchStage_RDY_pipelines_1_first__2939_AND__ETC___d14066 : !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first ; - assign IF_NOT_fetchStage_pipelines_0_canDeq__2932_293_ETC___d14081 = + assign IF_NOT_fetchStage_pipelines_0_canDeq__2929_293_ETC___d14077 = ((!fetchStage$pipelines_0_canDeq || - NOT_fetchStage_pipelines_0_first__2934_BITS_19_ETC___d13640) && + NOT_fetchStage_pipelines_0_first__2931_BITS_19_ETC___d13636) && fetchStage$pipelines_1_canDeq) ? - IF_NOT_fetchStage_pipelines_1_first__2943_BITS_ETC___d14080 : + IF_NOT_fetchStage_pipelines_1_first__2940_BITS_ETC___d14076 : fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2934_BITS_19_ETC___d14078 ; - assign IF_NOT_fetchStage_pipelines_1_first__2943_BITS_ETC___d13996 = + NOT_fetchStage_pipelines_0_first__2931_BITS_19_ETC___d14074 ; + assign IF_NOT_fetchStage_pipelines_1_first__2940_BITS_ETC___d13992 = (fetchStage$pipelines_1_first[194:192] == 3'd3 || fetchStage$pipelines_1_first[194:192] == 3'd4) ? - NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d13979 : + NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d13975 : ((fetchStage$pipelines_1_first[194:192] == 3'd2) ? (!fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first) && - (regRenamingTable_rename_0_canRename__3582_AND__ETC___d13988 || - NOT_regRenamingTable_rename_1_canRename__3704__ETC___d13966) : - _0_OR_NOT_fetchStage_pipelines_1_first__2943_BI_ETC___d13994) ; - assign IF_NOT_fetchStage_pipelines_1_first__2943_BITS_ETC___d14080 = - NOT_fetchStage_pipelines_1_first__2943_BITS_19_ETC___d13904 ? - IF_fetchStage_pipelines_1_first__2943_BITS_194_ETC___d14067 || + (regRenamingTable_rename_0_canRename__3578_AND__ETC___d13984 || + NOT_regRenamingTable_rename_1_canRename__3700__ETC___d13962) : + _0_OR_NOT_fetchStage_pipelines_1_first__2940_BI_ETC___d13990) ; + assign IF_NOT_fetchStage_pipelines_1_first__2940_BITS_ETC___d14076 = + NOT_fetchStage_pipelines_1_first__2940_BITS_19_ETC___d13900 ? + IF_fetchStage_pipelines_1_first__2940_BITS_194_ETC___d14063 || fetchStage$pipelines_0_canDeq && (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3582_AND__ETC___d13653 && - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d13663 : + regRenamingTable_rename_0_canRename__3578_AND__ETC___d13649 && + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d13659 : fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2934_BITS_19_ETC___d14078 ; - assign IF_NOT_renameStage_rg_m_halt_req_2961_BIT_4_29_ETC___d13453 = - NOT_renameStage_rg_m_halt_req_2961_BIT_4_2962__ETC___d13272 ? - IF_IF_fetchStage_pipelines_0_first__2934_BIT_6_ETC___d13380 : + NOT_fetchStage_pipelines_0_first__2931_BITS_19_ETC___d14074 ; + assign IF_NOT_renameStage_rg_m_halt_req_2958_BIT_4_29_ETC___d13449 = + NOT_renameStage_rg_m_halt_req_2958_BIT_4_2959__ETC___d13268 ? + IF_IF_fetchStage_pipelines_0_first__2931_BIT_6_ETC___d13376 : ((renameStage_rg_m_halt_req[4] ? renameStage_rg_m_halt_req[3:0] == 4'd0 : - IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3__ETC___d13413 == + IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3__ETC___d13409 == 4'd0) ? 4'd0 : ((renameStage_rg_m_halt_req[4] ? renameStage_rg_m_halt_req[3:0] == 4'd1 : - IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3__ETC___d13413 == + IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3__ETC___d13409 == 4'd1) ? 4'd1 : ((renameStage_rg_m_halt_req[4] ? renameStage_rg_m_halt_req[3:0] == 4'd3 : - IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3__ETC___d13413 == + IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3__ETC___d13409 == 4'd2) ? 4'd3 : ((renameStage_rg_m_halt_req[4] ? renameStage_rg_m_halt_req[3:0] == 4'd4 : - IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3__ETC___d13413 == + IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3__ETC___d13409 == 4'd3) ? 4'd4 : ((renameStage_rg_m_halt_req[4] ? renameStage_rg_m_halt_req[3:0] == 4'd5 : - IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3__ETC___d13413 == + IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3__ETC___d13409 == 4'd4) ? 4'd5 : ((renameStage_rg_m_halt_req[4] ? renameStage_rg_m_halt_req[3:0] == 4'd7 : - IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3__ETC___d13413 == + IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3__ETC___d13409 == 4'd5) ? 4'd7 : ((renameStage_rg_m_halt_req[4] ? renameStage_rg_m_halt_req[3:0] == 4'd8 : - IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3__ETC___d13413 == + IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3__ETC___d13409 == 4'd6) ? 4'd8 : ((renameStage_rg_m_halt_req[4] ? renameStage_rg_m_halt_req[3:0] == 4'd9 : - IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3__ETC___d13413 == + IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3__ETC___d13409 == 4'd7) ? 4'd9 : ((renameStage_rg_m_halt_req[4] ? renameStage_rg_m_halt_req[3:0] == 4'd11 : - IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3__ETC___d13413 == + IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3__ETC___d13409 == 4'd8) ? 4'd11 : ((renameStage_rg_m_halt_req[4] ? renameStage_rg_m_halt_req[3:0] == 4'd14 : - IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3__ETC___d13413 == + IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3__ETC___d13409 == 4'd9) ? 4'd14 : 4'd15)))))))))) ; - assign IF_NOT_rob_deqPort_1_deq_data__5222_BIT_25_522_ETC___d15521 = + assign IF_NOT_rob_deqPort_1_deq_data__5163_BIT_25_516_ETC___d15366 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[186:182] == 5'd0 || @@ -22484,11 +22319,11 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10045) : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10020 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10542 = - ((SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q177[10:0] == + ((SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q169[10:0] == 11'd0) ? 12'd3074 : - { SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q180[10], - SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q180 }) - + { SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q172[10], + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q172 }) - 12'd3074 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10583 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10243 ? @@ -22507,54 +22342,54 @@ module mkCore(CLK, assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11011 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8759 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10869[2] : - _theResult___fst_exp__h523527 == 11'd2047 && - _theResult___fst_sfd__h523528 == 52'd0 ; + _theResult___fst_exp__h523218 == 11'd2047 && + _theResult___fst_sfd__h523219 == 52'd0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11025 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10244 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10910[2] : - _theResult___fst_exp__h562380 == 11'd2047 && - _theResult___fst_sfd__h562381 == 52'd0 ; + _theResult___fst_exp__h562071 == 11'd2047 && + _theResult___fst_sfd__h562072 == 52'd0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11040 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9474 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10954[2] : - _theResult___fst_exp__h601684 == 11'd2047 && - _theResult___fst_sfd__h601685 == 52'd0 ; + _theResult___fst_exp__h601375 == 11'd2047 && + _theResult___fst_sfd__h601376 == 52'd0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11057 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8759 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10869[1] : - _theResult___fst_exp__h522744 == 11'd0 && - guard__h514754 != 2'b0 ; + _theResult___fst_exp__h522435 == 11'd0 && + guard__h514445 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11069 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10244 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10910[1] : - _theResult___fst_exp__h561597 == 11'd0 && - guard__h553607 != 2'b0 ; + _theResult___fst_exp__h561288 == 11'd0 && + guard__h553298 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11082 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9474 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10954[1] : - _theResult___fst_exp__h600901 == 11'd0 && - guard__h592911 != 2'b0 ; + _theResult___fst_exp__h600592 == 11'd0 && + guard__h592602 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11099 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8759 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10869[0] : - _theResult___fst_exp__h522744 != 11'd2047 && - guard__h514754 != 2'b0 ; + _theResult___fst_exp__h522435 != 11'd2047 && + guard__h514445 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11111 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10244 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10910[0] : - _theResult___fst_exp__h561597 != 11'd2047 && - guard__h553607 != 2'b0 ; + _theResult___fst_exp__h561288 != 11'd2047 && + guard__h553298 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11124 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9474 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10954[0] : - _theResult___fst_exp__h600901 != 11'd2047 && - guard__h592911 != 2'b0 ; + _theResult___fst_exp__h600592 != 11'd2047 && + guard__h592602 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9057 = - ((SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137[10:0] == + ((SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q129[10:0] == 11'd0) ? 12'd3074 : - { SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q140[10], - SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q140 }) - + { SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q132[10], + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q132 }) - 12'd3074 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9098 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8758 ? @@ -22565,11 +22400,11 @@ module mkCore(CLK, 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9772 = - ((SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q154[10:0] == + ((SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q146[10:0] == 11'd0) ? 12'd3074 : - { SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q157[10], - SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q157 }) - + { SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q149[10], + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q149 }) - 12'd3074 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9813 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9473 ? @@ -22580,135 +22415,135 @@ module mkCore(CLK, 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4968 = - ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q38[7:0] == + ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q30[7:0] == 8'd0) ? 9'd386 : - { SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q43[7], - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q43 }) - + { SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q35[7], + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q35 }) - 9'd386 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5195 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4649 ? - ((_theResult___fst_exp__h374260 == 8'd255) ? + ((_theResult___fst_exp__h373951 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5180) : - ((_theResult___fst_exp__h382945 == 8'd255) ? + ((_theResult___fst_exp__h382636 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5193) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5232 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4649 ? - ((_theResult___fst_exp__h374260 == 8'd255) ? + ((_theResult___fst_exp__h373951 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5223) : - ((_theResult___fst_exp__h382945 == 8'd255) ? + ((_theResult___fst_exp__h382636 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5230) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5323 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4649 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5294[2] : - _theResult___fst_exp__h383493 == 8'd255 && - _theResult___fst_sfd__h383494 == 23'd0 ; + _theResult___fst_exp__h383184 == 8'd255 && + _theResult___fst_sfd__h383185 == 23'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5336 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4649 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5294[1] : - _theResult___fst_exp__h382945 == 8'd0 && - guard__h374868 != 2'b0 ; + _theResult___fst_exp__h382636 == 8'd0 && + guard__h374559 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5349 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4649 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5294[0] : - _theResult___fst_exp__h382945 != 8'd255 && - guard__h374868 != 2'b0 ; + _theResult___fst_exp__h382636 != 8'd255 && + guard__h374559 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6360 = - ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q73[7:0] == + ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q65[7:0] == 8'd0) ? 9'd386 : - { SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q78[7], - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q78 }) - + { SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q70[7], + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q70 }) - 9'd386 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6587 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6041 ? - ((_theResult___fst_exp__h419957 == 8'd255) ? + ((_theResult___fst_exp__h419648 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6572) : - ((_theResult___fst_exp__h428642 == 8'd255) ? + ((_theResult___fst_exp__h428333 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6585) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6624 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6041 ? - ((_theResult___fst_exp__h419957 == 8'd255) ? + ((_theResult___fst_exp__h419648 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6615) : - ((_theResult___fst_exp__h428642 == 8'd255) ? + ((_theResult___fst_exp__h428333 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6622) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6715 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6041 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6686[2] : - _theResult___fst_exp__h429190 == 8'd255 && - _theResult___fst_sfd__h429191 == 23'd0 ; + _theResult___fst_exp__h428881 == 8'd255 && + _theResult___fst_sfd__h428882 == 23'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6728 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6041 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6686[1] : - _theResult___fst_exp__h428642 == 8'd0 && - guard__h420565 != 2'b0 ; + _theResult___fst_exp__h428333 == 8'd0 && + guard__h420256 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6741 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6041 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6686[0] : - _theResult___fst_exp__h428642 != 8'd255 && - guard__h420565 != 2'b0 ; + _theResult___fst_exp__h428333 != 8'd255 && + guard__h420256 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7752 = - ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q108[7:0] == + ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q100[7:0] == 8'd0) ? 9'd386 : - { SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q113[7], - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q113 }) - + { SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q105[7], + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q105 }) - 9'd386 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7979 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7433 ? - ((_theResult___fst_exp__h465652 == 8'd255) ? + ((_theResult___fst_exp__h465343 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7964) : - ((_theResult___fst_exp__h474337 == 8'd255) ? + ((_theResult___fst_exp__h474028 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7977) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8016 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7433 ? - ((_theResult___fst_exp__h465652 == 8'd255) ? + ((_theResult___fst_exp__h465343 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8007) : - ((_theResult___fst_exp__h474337 == 8'd255) ? + ((_theResult___fst_exp__h474028 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8014) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8107 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7433 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d8078[2] : - _theResult___fst_exp__h474885 == 8'd255 && - _theResult___fst_sfd__h474886 == 23'd0 ; + _theResult___fst_exp__h474576 == 8'd255 && + _theResult___fst_sfd__h474577 == 23'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8120 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7433 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d8078[1] : - _theResult___fst_exp__h474337 == 8'd0 && - guard__h466260 != 2'b0 ; + _theResult___fst_exp__h474028 == 8'd0 && + guard__h465951 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8133 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7433 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d8078[0] : - _theResult___fst_exp__h474337 != 8'd255 && - guard__h466260 != 2'b0 ; - assign IF_checkForException_3180_BIT_4_3181_THEN_IF_c_ETC___d13329 = - checkForException___d13180[4] ? - CASE_checkForException_3180_BITS_3_TO_0_0_chec_ETC__q234 : + _theResult___fst_exp__h474028 != 8'd255 && + guard__h465951 != 2'b0 ; + assign IF_checkForException_3176_BIT_4_3177_THEN_IF_c_ETC___d13325 = + checkForException___d13176[4] ? + CASE_checkForException_3176_BITS_3_TO_0_0_chec_ETC__q226 : 4'd2 ; - assign IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2350_ETC___d12383 = + assign IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2347_ETC___d12380 = (coreFix_aluExe_0_dispToRegQ$RDY_first && coreFix_aluExe_0_bypassWire_0$whas && - coreFix_aluExe_0_bypassWire_0_wget__2373_BITS__ETC___d12375) ? + coreFix_aluExe_0_bypassWire_0_wget__2370_BITS__ETC___d12372) ? !coreFix_aluExe_0_bypassWire_0$whas || coreFix_aluExe_0_dispToRegQ$RDY_first : !coreFix_aluExe_0_bypassWire_1$whas || coreFix_aluExe_0_dispToRegQ$RDY_first ; - assign IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2350_ETC___d12419 = + assign IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2347_ETC___d12416 = (coreFix_aluExe_0_dispToRegQ$RDY_first && coreFix_aluExe_0_bypassWire_0$whas && - coreFix_aluExe_0_bypassWire_0_wget__2373_BITS__ETC___d12416) ? + coreFix_aluExe_0_bypassWire_0_wget__2370_BITS__ETC___d12413) ? !coreFix_aluExe_0_bypassWire_0$whas || coreFix_aluExe_0_dispToRegQ$RDY_first : !coreFix_aluExe_0_bypassWire_1$whas || @@ -23348,10 +23183,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[75:12] : { IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9815, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9993 } ; - assign IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12875 = + assign IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12872 = coreFix_globalSpecUpdate_correctSpecTag_1$whas ? - result__h650621 : - w__h650616 ; + result__h650285 : + w__h650280 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2112 = (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == 3'd3 && @@ -23373,39 +23208,39 @@ module mkCore(CLK, assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2226 = { (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd7) ? - n___1__h199875 : + n___1__h199567 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd6) ? - n___1__h199875 : + n___1__h199567 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd5) ? - n___1__h199875 : + n___1__h199567 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd4) ? - n___1__h199875 : + n___1__h199567 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2231 = { IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2226, (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd3) ? - n___1__h199875 : + n___1__h199567 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd2) ? - n___1__h199875 : + n___1__h199567 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2236 = { IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2231, (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd1) ? - n___1__h199875 : + n___1__h199567 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd0) ? - n___1__h199875 : + n___1__h199567 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2549 = (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == @@ -23458,7 +23293,7 @@ module mkCore(CLK, assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2595 = (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == 3'd2) ? - x__h198472 : + x__h198164 : (coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2178 ? 64'd0 : 64'd1) ; @@ -23470,7 +23305,7 @@ module mkCore(CLK, WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry || coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3154 = - _theResult_____2__h298821 == v__h298241 ; + _theResult_____2__h298513 == v__h297933 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3234 = EN_dCacheToParent_fromP_enq ? coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[583] : @@ -23479,7 +23314,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_lat_0$whas || coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3256 = - _theResult_____2__h306817 == v__h301586 ; + _theResult_____2__h306509 == v__h301278 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3276 = EN_dCacheToParent_fromP_enq ? !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[583] : @@ -23508,7 +23343,7 @@ module mkCore(CLK, EN_dCacheToParent_fromP_enq ? coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[514:3] : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[514:3], - x__h304451 } ; + x__h304143 } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3100 = !MUX_flush_reservation$write_1__SEL_2 && (coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$whas ? @@ -23606,35 +23441,35 @@ module mkCore(CLK, assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2023 = { (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd7) ? - n__h195271 : + n__h194963 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448], (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd6) ? - n__h195271 : + n__h194963 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384], (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd5) ? - n__h195271 : + n__h194963 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2028 = { IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2023, (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd4) ? - n__h195271 : + n__h194963 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256], (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd3) ? - n__h195271 : + n__h194963 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2033 = { IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2028, (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd2) ? - n__h195271 : + n__h194963 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128], (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd1) ? - n__h195271 : + n__h194963 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2882 = coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? @@ -23662,7 +23497,7 @@ module mkCore(CLK, EN_dCacheToParent_rqToP_deq || coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3428 = - _theResult_____2__h312811 == v__h312100 ; + _theResult_____2__h312503 == v__h311792 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3501 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[579] : @@ -23671,7 +23506,7 @@ module mkCore(CLK, EN_dCacheToParent_rsToP_deq || coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3524 = - _theResult_____2__h320665 == v__h315976 ; + _theResult_____2__h320357 == v__h315668 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3543 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[579] : @@ -23823,7 +23658,7 @@ module mkCore(CLK, !coreFix_aluExe_0_bypassWire_1$whas || coreFix_memExe_dispToRegQ$RDY_first ; assign IF_coreFix_memExe_forwardQ_deqReq_dummy2_2_rea_ETC___d3846 = - _theResult_____2__h334234 == v__h333802 ; + _theResult_____2__h333926 == v__h333494 ; assign IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d3839 = WILL_FIRE_RL_coreFix_memExe_doRespLdForward || coreFix_memExe_forwardQ_deqReq_rl ; @@ -23872,7 +23707,7 @@ module mkCore(CLK, SEL_ARR_mmio_dataRespQ_data_0_109_BITS_31_TO_0_ETC___d1408 }) : IF_coreFix_memExe_lsq_firstLd__285_BIT_94_360__ETC___d1434 ; assign IF_coreFix_memExe_memRespLdQ_deqReq_dummy2_2_r_ETC___d3752 = - _theResult_____2__h331009 == v__h330577 ; + _theResult_____2__h330701 == v__h330269 ; assign IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d3745 = WILL_FIRE_RL_coreFix_memExe_doRespLdMem || coreFix_memExe_memRespLdQ_deqReq_rl ; @@ -23904,79 +23739,79 @@ module mkCore(CLK, coreFix_memExe_respLrScAmoQ_enqReq_rl[64] ; assign IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8 = csrf_minstret_ehr_data_lat_0$whas ? - upd__h719366 : + upd__h717235 : csrf_minstret_ehr_data_rl ; - assign IF_fetchStage_RDY_pipelines_0_first__2931_AND__ETC___d13610 = + assign IF_fetchStage_RDY_pipelines_0_first__2928_AND__ETC___d13606 = (fetchStage$RDY_pipelines_0_first && (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3582_AND__ETC___d13604) ? + regRenamingTable_rename_0_canRename__3578_AND__ETC___d13600) ? fetchStage$RDY_pipelines_0_first : !regRenamingTable$rename_0_canRename || fetchStage$RDY_pipelines_0_first ; - assign IF_fetchStage_RDY_pipelines_1_first__2942_AND__ETC___d13998 = + assign IF_fetchStage_RDY_pipelines_1_first__2939_AND__ETC___d13994 = (fetchStage$RDY_pipelines_1_first && (fetchStage$pipelines_1_first[194:192] == 3'd0 || fetchStage$pipelines_1_first[194:192] == 3'd1)) ? (!fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first) && - (SEL_ARR_fetchStage_pipelines_0_canDeq__2932_AN_ETC___d13937 || + (SEL_ARR_fetchStage_pipelines_0_canDeq__2929_AN_ETC___d13933 || fetchStage$pipelines_1_first[194:192] == 3'd1 && - regRenamingTable_rename_0_canRename__3582_AND__ETC___d13667 || - NOT_regRenamingTable_rename_1_canRename__3704__ETC___d13966) : + regRenamingTable_rename_0_canRename__3578_AND__ETC___d13663 || + NOT_regRenamingTable_rename_1_canRename__3700__ETC___d13962) : fetchStage$RDY_pipelines_1_first && - IF_NOT_fetchStage_pipelines_1_first__2943_BITS_ETC___d13996 ; - assign IF_fetchStage_RDY_pipelines_1_first__2942_AND__ETC___d14070 = + IF_NOT_fetchStage_pipelines_1_first__2940_BITS_ETC___d13992 ; + assign IF_fetchStage_RDY_pipelines_1_first__2939_AND__ETC___d14066 = (fetchStage$RDY_pipelines_1_first && - NOT_fetchStage_pipelines_1_first__2943_BITS_19_ETC___d13674 && - NOT_fetchStage_pipelines_1_first__2943_BITS_19_ETC___d13904) ? - IF_fetchStage_RDY_pipelines_1_first__2942_AND__ETC___d13998 && - (IF_fetchStage_pipelines_1_first__2943_BITS_194_ETC___d14067 || + NOT_fetchStage_pipelines_1_first__2940_BITS_19_ETC___d13670 && + NOT_fetchStage_pipelines_1_first__2940_BITS_19_ETC___d13900) ? + IF_fetchStage_RDY_pipelines_1_first__2939_AND__ETC___d13994 && + (IF_fetchStage_pipelines_1_first__2940_BITS_194_ETC___d14063 || !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first) : !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first ; - assign IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d14119 = - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d14112 || + assign IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d14115 = + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d14108 || rob$RDY_enqPort_0_enq && regRenamingTable$RDY_rename_0_claimRename && regRenamingTable$RDY_rename_0_getRename && fetchStage$RDY_pipelines_0_deq && (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$RDY_claimSpecTag) ; - assign IF_fetchStage_pipelines_0_first__2934_BIT_160__ETC___d14316 = + assign IF_fetchStage_pipelines_0_first__2931_BIT_160__ETC___d14312 = { fetchStage$pipelines_0_first[159:128], - IF_fetchStage_pipelines_0_first__2934_BITS_191_ETC___d14304, - IF_fetchStage_pipelines_0_first__2934_BITS_191_ETC___d14307 ? - IF_fetchStage_pipelines_0_first__2934_BITS_191_ETC___d14310 : + IF_fetchStage_pipelines_0_first__2931_BITS_191_ETC___d14300, + IF_fetchStage_pipelines_0_first__2931_BITS_191_ETC___d14303 ? + IF_fetchStage_pipelines_0_first__2931_BITS_191_ETC___d14306 : { 1'h0, - IF_fetchStage_pipelines_0_first__2934_BITS_191_ETC___d14313 } } ; - assign IF_fetchStage_pipelines_0_first__2934_BIT_173__ETC___d13207 = + IF_fetchStage_pipelines_0_first__2931_BITS_191_ETC___d14309 } } ; + assign IF_fetchStage_pipelines_0_first__2931_BIT_173__ETC___d13203 = fetchStage$pipelines_0_first[173] ? - IF_fetchStage_pipelines_0_first__2934_BITS_172_ETC___d13146 : + IF_fetchStage_pipelines_0_first__2931_BITS_172_ETC___d13142 : 12'hCFF ; - assign IF_fetchStage_pipelines_1_first__2943_BITS_194_ETC___d14249 = - IF_fetchStage_pipelines_1_first__2943_BITS_194_ETC___d14206 && - IF_fetchStage_RDY_pipelines_1_first__2942_AND__ETC___d13998 && - (IF_fetchStage_pipelines_1_first__2943_BITS_194_ETC___d14233 || + assign IF_fetchStage_pipelines_1_first__2940_BITS_194_ETC___d14245 = + IF_fetchStage_pipelines_1_first__2940_BITS_194_ETC___d14202 && + IF_fetchStage_RDY_pipelines_1_first__2939_AND__ETC___d13994 && + (IF_fetchStage_pipelines_1_first__2940_BITS_194_ETC___d14229 || rob$RDY_enqPort_1_enq && regRenamingTable$RDY_rename_1_claimRename && regRenamingTable$RDY_rename_1_getRename && - fetchStage_RDY_pipelines_1_deq__2946_AND_NOT_f_ETC___d14243) ; - assign IF_fetchStage_pipelines_1_first__2943_BITS_194_ETC___d14531 = + fetchStage_RDY_pipelines_1_deq__2943_AND_NOT_f_ETC___d14239) ; + assign IF_fetchStage_pipelines_1_first__2940_BITS_194_ETC___d14527 = (fetchStage$pipelines_1_first[194:192] == 3'd2 && - NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d14466 && - IF_fetchStage_pipelines_1_first__2943_BITS_191_ETC___d14473) ? - IF_fetchStage_pipelines_1_first__2943_BITS_191_ETC___d14474 : + NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d14462 && + IF_fetchStage_pipelines_1_first__2940_BITS_191_ETC___d14469) ? + IF_fetchStage_pipelines_1_first__2940_BITS_191_ETC___d14470 : { 1'h0, - IF_fetchStage_pipelines_1_first__2943_BITS_191_ETC___d14475 } ; - assign IF_fetchStage_pipelines_1_first__2943_BIT_160__ETC___d14478 = + IF_fetchStage_pipelines_1_first__2940_BITS_191_ETC___d14471 } ; + assign IF_fetchStage_pipelines_1_first__2940_BIT_160__ETC___d14474 = { fetchStage$pipelines_1_first[159:128], - IF_fetchStage_pipelines_1_first__2943_BITS_191_ETC___d14472, - IF_fetchStage_pipelines_1_first__2943_BITS_191_ETC___d14473 ? - IF_fetchStage_pipelines_1_first__2943_BITS_191_ETC___d14474 : + IF_fetchStage_pipelines_1_first__2940_BITS_191_ETC___d14468, + IF_fetchStage_pipelines_1_first__2940_BITS_191_ETC___d14469 ? + IF_fetchStage_pipelines_1_first__2940_BITS_191_ETC___d14470 : { 1'h0, - IF_fetchStage_pipelines_1_first__2943_BITS_191_ETC___d14475 } } ; + IF_fetchStage_pipelines_1_first__2940_BITS_191_ETC___d14471 } } ; assign IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmio_c_ETC___d339 = mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[142] : @@ -24001,58 +23836,62 @@ module mkCore(CLK, EN_mmioToPlatform_pRs_enq ? mmio_pRsQ_enqReq_lat_0$wget[67] : mmio_pRsQ_enqReq_rl[67] ; - assign IF_rob_deqPort_0_canDeq__5214_THEN_IF_NOT_rob__ETC___d15509 = - rob$deqPort_0_canDeq ? y_avValue_fst__h722016 : 5'd0 ; - assign IF_rob_deqPort_0_canDeq__5214_THEN_IF_NOT_rob__ETC___d15530 = + assign IF_rob_deqPort_0_canDeq__5156_THEN_IF_NOT_rob__ETC___d15265 = rob$deqPort_0_canDeq ? - y_avValue_snd_snd_snd_fst__h722464 : + y_avValue_snd_snd_snd_snd_snd__h719478 : + 64'd0 ; + assign IF_rob_deqPort_0_canDeq__5156_THEN_IF_NOT_rob__ETC___d15354 = + rob$deqPort_0_canDeq ? y_avValue_snd_fst__h719462 : 5'd0 ; + assign IF_rob_deqPort_0_canDeq__5156_THEN_IF_NOT_rob__ETC___d15375 = + rob$deqPort_0_canDeq ? + y_avValue_snd_snd_snd_fst__h719472 : 2'd0 ; - assign IF_rob_deqPort_1_canDeq__5219_THEN_IF_NOT_rob__ETC___d15522 = + assign IF_rob_deqPort_1_canDeq__5160_THEN_IF_NOT_rob__ETC___d15367 = rob$deqPort_1_canDeq ? - IF_NOT_rob_deqPort_1_deq_data__5222_BIT_25_522_ETC___d15521 : + IF_NOT_rob_deqPort_1_deq_data__5163_BIT_25_516_ETC___d15366 : rob$deqPort_0_canDeq && rob$deqPort_0_deq_data[26] ; - assign IF_sfdin02185_BIT_33_THEN_2_ELSE_0__q65 = - sfdin__h402185[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin13905_BIT_4_THEN_2_ELSE_0__q139 = - sfdin__h513905[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin19951_BIT_33_THEN_2_ELSE_0__q75 = - sfdin__h419951[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin47880_BIT_33_THEN_2_ELSE_0__q100 = - sfdin__h447880[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin52758_BIT_4_THEN_2_ELSE_0__q179 = - sfdin__h552758[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin56488_BIT_33_THEN_2_ELSE_0__q30 = - sfdin__h356488[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin65646_BIT_33_THEN_2_ELSE_0__q110 = - sfdin__h465646[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin74254_BIT_33_THEN_2_ELSE_0__q40 = - sfdin__h374254[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin92062_BIT_4_THEN_2_ELSE_0__q156 = - sfdin__h592062[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd00847_BIT_4_THEN_2_ELSE_0__q159 = - _theResult___snd__h600847[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd04285_BIT_4_THEN_2_ELSE_0__q135 = - _theResult___snd__h504285[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd10798_BIT_33_THEN_2_ELSE_0__q67 = - _theResult___snd__h410798[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd22690_BIT_4_THEN_2_ELSE_0__q142 = - _theResult___snd__h522690[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd28588_BIT_33_THEN_2_ELSE_0__q80 = - _theResult___snd__h428588[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd43138_BIT_4_THEN_2_ELSE_0__q175 = - _theResult___snd__h543138[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd56493_BIT_33_THEN_2_ELSE_0__q102 = - _theResult___snd__h456493[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd61543_BIT_4_THEN_2_ELSE_0__q182 = - _theResult___snd__h561543[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd65101_BIT_33_THEN_2_ELSE_0__q32 = - _theResult___snd__h365101[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd74283_BIT_33_THEN_2_ELSE_0__q115 = - _theResult___snd__h474283[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd82442_BIT_4_THEN_2_ELSE_0__q152 = - _theResult___snd__h582442[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd82891_BIT_33_THEN_2_ELSE_0__q45 = - _theResult___snd__h382891[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin01876_BIT_33_THEN_2_ELSE_0__q57 = + sfdin__h401876[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin13596_BIT_4_THEN_2_ELSE_0__q131 = + sfdin__h513596[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin19642_BIT_33_THEN_2_ELSE_0__q67 = + sfdin__h419642[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin47571_BIT_33_THEN_2_ELSE_0__q92 = + sfdin__h447571[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin52449_BIT_4_THEN_2_ELSE_0__q171 = + sfdin__h552449[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin56179_BIT_33_THEN_2_ELSE_0__q22 = + sfdin__h356179[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin65337_BIT_33_THEN_2_ELSE_0__q102 = + sfdin__h465337[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin73945_BIT_33_THEN_2_ELSE_0__q32 = + sfdin__h373945[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin91753_BIT_4_THEN_2_ELSE_0__q148 = + sfdin__h591753[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd00538_BIT_4_THEN_2_ELSE_0__q151 = + _theResult___snd__h600538[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd03976_BIT_4_THEN_2_ELSE_0__q127 = + _theResult___snd__h503976[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd10489_BIT_33_THEN_2_ELSE_0__q59 = + _theResult___snd__h410489[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd22381_BIT_4_THEN_2_ELSE_0__q134 = + _theResult___snd__h522381[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd28279_BIT_33_THEN_2_ELSE_0__q72 = + _theResult___snd__h428279[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd42829_BIT_4_THEN_2_ELSE_0__q167 = + _theResult___snd__h542829[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd56184_BIT_33_THEN_2_ELSE_0__q94 = + _theResult___snd__h456184[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd61234_BIT_4_THEN_2_ELSE_0__q174 = + _theResult___snd__h561234[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd64792_BIT_33_THEN_2_ELSE_0__q24 = + _theResult___snd__h364792[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd73974_BIT_33_THEN_2_ELSE_0__q107 = + _theResult___snd__h473974[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd82133_BIT_4_THEN_2_ELSE_0__q144 = + _theResult___snd__h582133[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd82582_BIT_33_THEN_2_ELSE_0__q37 = + _theResult___snd__h382582[33] ? 2'd2 : 2'd0 ; assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5317 = !_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4108 || (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4109 ? @@ -24083,198 +23922,198 @@ module mkCore(CLK, (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6893 ? _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d8049[0] : _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d8061[0]) ; - assign NOT_IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_296_ETC___d13510 = - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[0] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[1] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[2] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[3] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[4] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[5] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[6] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[7] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[8] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[9] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[10] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[11] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[12] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[13] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[14] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[15] && - !checkForException___d13180[4] && - NOT_csrf_fs_reg_read__1726_EQ_0_3169_3170_OR_N_ETC___d13503 && + assign NOT_IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_296_ETC___d13506 = + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[0] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[1] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[2] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[3] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[4] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[5] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[6] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[7] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[8] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[9] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[10] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[11] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[12] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[13] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[14] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[15] && + !checkForException___d13176[4] && + NOT_csrf_fs_reg_read__1726_EQ_0_3165_3166_OR_N_ETC___d13499 && (fetchStage$pipelines_0_first[231:200] != 32'h10500073 || !csrf_tw_reg || csrf_prv_reg == 2'd3) ; - assign NOT_IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_296_ETC___d13597 = - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[0] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[1] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[2] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[3] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[4] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[5] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[6] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[7] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[8] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[9] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[10] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[11] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[12] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[13] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[14] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[15] && - !checkForException___d13180[4] && - NOT_csrf_fs_reg_read__1726_EQ_0_3169_3170_OR_N_ETC___d13595 ; - assign NOT_IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_296_ETC___d13890 = - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[0] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[1] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[2] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[3] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[4] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[5] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[6] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[7] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[8] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[9] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[10] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[11] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[12] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[13] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[14] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[15] && - !checkForException___d13863[4] && - NOT_csrf_fs_reg_read__1726_EQ_0_3169_3170_OR_N_ETC___d13888 ; - assign NOT_IF_NOT_rob_deqPort_0_canDeq__5214_5215_OR__ETC___d15527 = - (fflags__h723884 & csrf_fflags_reg) != fflags__h723884 || - !r__h616724 && - (IF_rob_deqPort_1_canDeq__5219_THEN_IF_NOT_rob__ETC___d15522 || - fflags__h723884 != 5'd0) ; + assign NOT_IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_296_ETC___d13593 = + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[0] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[1] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[2] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[3] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[4] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[5] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[6] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[7] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[8] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[9] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[10] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[11] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[12] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[13] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[14] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[15] && + !checkForException___d13176[4] && + NOT_csrf_fs_reg_read__1726_EQ_0_3165_3166_OR_N_ETC___d13591 ; + assign NOT_IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_296_ETC___d13886 = + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[0] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[1] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[2] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[3] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[4] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[5] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[6] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[7] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[8] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[9] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[10] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[11] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[12] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[13] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[14] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[15] && + !checkForException___d13859[4] && + NOT_csrf_fs_reg_read__1726_EQ_0_3165_3166_OR_N_ETC___d13884 ; + assign NOT_IF_NOT_rob_deqPort_0_canDeq__5156_5157_OR__ETC___d15372 = + (fflags__h720016 & csrf_fflags_reg) != fflags__h720016 || + !r__h616401 && + (IF_rob_deqPort_1_canDeq__5160_THEN_IF_NOT_rob__ETC___d15367 || + fflags__h720016 != 5'd0) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10167 = - !f2_sfd__h523941[21] && !f2_sfd__h523941[20] && - !f2_sfd__h523941[19] && - !f2_sfd__h523941[18] && - !f2_sfd__h523941[17] && - !f2_sfd__h523941[16] && - !f2_sfd__h523941[15] && - !f2_sfd__h523941[14] && - !f2_sfd__h523941[13] && - !f2_sfd__h523941[12] && - !f2_sfd__h523941[11] && - !f2_sfd__h523941[10] && - !f2_sfd__h523941[9] && - !f2_sfd__h523941[8] && - !f2_sfd__h523941[7] && - !f2_sfd__h523941[6] && - !f2_sfd__h523941[5] && - !f2_sfd__h523941[4] && - !f2_sfd__h523941[3] && - !f2_sfd__h523941[2] && - !f2_sfd__h523941[1] && - !f2_sfd__h523941[0] ; + !f2_sfd__h523632[21] && !f2_sfd__h523632[20] && + !f2_sfd__h523632[19] && + !f2_sfd__h523632[18] && + !f2_sfd__h523632[17] && + !f2_sfd__h523632[16] && + !f2_sfd__h523632[15] && + !f2_sfd__h523632[14] && + !f2_sfd__h523632[13] && + !f2_sfd__h523632[12] && + !f2_sfd__h523632[11] && + !f2_sfd__h523632[10] && + !f2_sfd__h523632[9] && + !f2_sfd__h523632[8] && + !f2_sfd__h523632[7] && + !f2_sfd__h523632[6] && + !f2_sfd__h523632[5] && + !f2_sfd__h523632[4] && + !f2_sfd__h523632[3] && + !f2_sfd__h523632[2] && + !f2_sfd__h523632[1] && + !f2_sfd__h523632[0] ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10876 = - (f1_exp__h484946 != 8'd255 || f1_sfd__h484947 == 23'd0) && - (f1_exp__h484946 != 8'd255 || f1_sfd__h484947 != 23'd0) && - (f1_exp__h484946 != 8'd0 || f1_sfd__h484947 != 23'd0) && + (f1_exp__h484637 != 8'd255 || f1_sfd__h484638 == 23'd0) && + (f1_exp__h484637 != 8'd255 || f1_sfd__h484638 != 23'd0) && + (f1_exp__h484637 != 8'd0 || f1_sfd__h484638 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10873 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10918 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10876 | - ((f2_exp__h523940 != 8'd255 || f2_sfd__h523941 == 23'd0) && - (f2_exp__h523940 != 8'd255 || f2_sfd__h523941 != 23'd0) && - (f2_exp__h523940 != 8'd0 || f2_sfd__h523941 != 23'd0) && + ((f2_exp__h523631 != 8'd255 || f2_sfd__h523632 == 23'd0) && + (f2_exp__h523631 != 8'd255 || f2_sfd__h523632 != 23'd0) && + (f2_exp__h523631 != 8'd0 || f2_sfd__h523632 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10914) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10976 = - (f1_exp__h484946 != 8'd255 || f1_sfd__h484947 == 23'd0) && - (f1_exp__h484946 != 8'd255 || f1_sfd__h484947 != 23'd0) && - (f1_exp__h484946 != 8'd0 || f1_sfd__h484947 != 23'd0) && + (f1_exp__h484637 != 8'd255 || f1_sfd__h484638 == 23'd0) && + (f1_exp__h484637 != 8'd255 || f1_sfd__h484638 != 23'd0) && + (f1_exp__h484637 != 8'd0 || f1_sfd__h484638 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10973 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10987 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10976 | - ((f2_exp__h523940 != 8'd255 || f2_sfd__h523941 == 23'd0) && - (f2_exp__h523940 != 8'd255 || f2_sfd__h523941 != 23'd0) && - (f2_exp__h523940 != 8'd0 || f2_sfd__h523941 != 23'd0) && + ((f2_exp__h523631 != 8'd255 || f2_sfd__h523632 == 23'd0) && + (f2_exp__h523631 != 8'd255 || f2_sfd__h523632 != 23'd0) && + (f2_exp__h523631 != 8'd0 || f2_sfd__h523632 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10983) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11016 = - (f1_exp__h484946 != 8'd255 || f1_sfd__h484947 == 23'd0) && - (f1_exp__h484946 != 8'd255 || f1_sfd__h484947 != 23'd0) && - (f1_exp__h484946 != 8'd0 || f1_sfd__h484947 != 23'd0) && + (f1_exp__h484637 != 8'd255 || f1_sfd__h484638 == 23'd0) && + (f1_exp__h484637 != 8'd255 || f1_sfd__h484638 != 23'd0) && + (f1_exp__h484637 != 8'd0 || f1_sfd__h484638 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11013 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11031 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11016 | - ((f2_exp__h523940 != 8'd255 || f2_sfd__h523941 == 23'd0) && - (f2_exp__h523940 != 8'd255 || f2_sfd__h523941 != 23'd0) && - (f2_exp__h523940 != 8'd0 || f2_sfd__h523941 != 23'd0) && + ((f2_exp__h523631 != 8'd255 || f2_sfd__h523632 == 23'd0) && + (f2_exp__h523631 != 8'd255 || f2_sfd__h523632 != 23'd0) && + (f2_exp__h523631 != 8'd0 || f2_sfd__h523632 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11027) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11062 = - (f1_exp__h484946 != 8'd255 || f1_sfd__h484947 == 23'd0) && - (f1_exp__h484946 != 8'd255 || f1_sfd__h484947 != 23'd0) && - (f1_exp__h484946 != 8'd0 || f1_sfd__h484947 != 23'd0) && + (f1_exp__h484637 != 8'd255 || f1_sfd__h484638 == 23'd0) && + (f1_exp__h484637 != 8'd255 || f1_sfd__h484638 != 23'd0) && + (f1_exp__h484637 != 8'd0 || f1_sfd__h484638 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11059 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11075 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11062 | - ((f2_exp__h523940 != 8'd255 || f2_sfd__h523941 == 23'd0) && - (f2_exp__h523940 != 8'd255 || f2_sfd__h523941 != 23'd0) && - (f2_exp__h523940 != 8'd0 || f2_sfd__h523941 != 23'd0) && + ((f2_exp__h523631 != 8'd255 || f2_sfd__h523632 == 23'd0) && + (f2_exp__h523631 != 8'd255 || f2_sfd__h523632 != 23'd0) && + (f2_exp__h523631 != 8'd0 || f2_sfd__h523632 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11071) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11104 = - (f1_exp__h484946 != 8'd255 || f1_sfd__h484947 == 23'd0) && - (f1_exp__h484946 != 8'd255 || f1_sfd__h484947 != 23'd0) && - (f1_exp__h484946 != 8'd0 || f1_sfd__h484947 != 23'd0) && + (f1_exp__h484637 != 8'd255 || f1_sfd__h484638 == 23'd0) && + (f1_exp__h484637 != 8'd255 || f1_sfd__h484638 != 23'd0) && + (f1_exp__h484637 != 8'd0 || f1_sfd__h484638 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11101 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11117 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11104 | - ((f2_exp__h523940 != 8'd255 || f2_sfd__h523941 == 23'd0) && - (f2_exp__h523940 != 8'd255 || f2_sfd__h523941 != 23'd0) && - (f2_exp__h523940 != 8'd0 || f2_sfd__h523941 != 23'd0) && + ((f2_exp__h523631 != 8'd255 || f2_sfd__h523632 == 23'd0) && + (f2_exp__h523631 != 8'd255 || f2_sfd__h523632 != 23'd0) && + (f2_exp__h523631 != 8'd0 || f2_sfd__h523632 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11113) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8667 = - !f1_sfd__h484947[21] && !f1_sfd__h484947[20] && - !f1_sfd__h484947[19] && - !f1_sfd__h484947[18] && - !f1_sfd__h484947[17] && - !f1_sfd__h484947[16] && - !f1_sfd__h484947[15] && - !f1_sfd__h484947[14] && - !f1_sfd__h484947[13] && - !f1_sfd__h484947[12] && - !f1_sfd__h484947[11] && - !f1_sfd__h484947[10] && - !f1_sfd__h484947[9] && - !f1_sfd__h484947[8] && - !f1_sfd__h484947[7] && - !f1_sfd__h484947[6] && - !f1_sfd__h484947[5] && - !f1_sfd__h484947[4] && - !f1_sfd__h484947[3] && - !f1_sfd__h484947[2] && - !f1_sfd__h484947[1] && - !f1_sfd__h484947[0] ; + !f1_sfd__h484638[21] && !f1_sfd__h484638[20] && + !f1_sfd__h484638[19] && + !f1_sfd__h484638[18] && + !f1_sfd__h484638[17] && + !f1_sfd__h484638[16] && + !f1_sfd__h484638[15] && + !f1_sfd__h484638[14] && + !f1_sfd__h484638[13] && + !f1_sfd__h484638[12] && + !f1_sfd__h484638[11] && + !f1_sfd__h484638[10] && + !f1_sfd__h484638[9] && + !f1_sfd__h484638[8] && + !f1_sfd__h484638[7] && + !f1_sfd__h484638[6] && + !f1_sfd__h484638[5] && + !f1_sfd__h484638[4] && + !f1_sfd__h484638[3] && + !f1_sfd__h484638[2] && + !f1_sfd__h484638[1] && + !f1_sfd__h484638[0] ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9397 = - !f3_sfd__h563245[21] && !f3_sfd__h563245[20] && - !f3_sfd__h563245[19] && - !f3_sfd__h563245[18] && - !f3_sfd__h563245[17] && - !f3_sfd__h563245[16] && - !f3_sfd__h563245[15] && - !f3_sfd__h563245[14] && - !f3_sfd__h563245[13] && - !f3_sfd__h563245[12] && - !f3_sfd__h563245[11] && - !f3_sfd__h563245[10] && - !f3_sfd__h563245[9] && - !f3_sfd__h563245[8] && - !f3_sfd__h563245[7] && - !f3_sfd__h563245[6] && - !f3_sfd__h563245[5] && - !f3_sfd__h563245[4] && - !f3_sfd__h563245[3] && - !f3_sfd__h563245[2] && - !f3_sfd__h563245[1] && - !f3_sfd__h563245[0] ; - assign NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13658 = - !SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__361_ETC___d13656 && + !f3_sfd__h562936[21] && !f3_sfd__h562936[20] && + !f3_sfd__h562936[19] && + !f3_sfd__h562936[18] && + !f3_sfd__h562936[17] && + !f3_sfd__h562936[16] && + !f3_sfd__h562936[15] && + !f3_sfd__h562936[14] && + !f3_sfd__h562936[13] && + !f3_sfd__h562936[12] && + !f3_sfd__h562936[11] && + !f3_sfd__h562936[10] && + !f3_sfd__h562936[9] && + !f3_sfd__h562936[8] && + !f3_sfd__h562936[7] && + !f3_sfd__h562936[6] && + !f3_sfd__h562936[5] && + !f3_sfd__h562936[4] && + !f3_sfd__h562936[3] && + !f3_sfd__h562936[2] && + !f3_sfd__h562936[1] && + !f3_sfd__h562936[0] ; + assign NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13654 = + !SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__360_ETC___d13652 && (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3582_AND__ETC___d13604 ; - assign NOT_commitStage_commitTrap_4555_BIT_4_4779_478_ETC___d14814 = + regRenamingTable_rename_0_canRename__3578_AND__ETC___d13600 ; + assign NOT_commitStage_commitTrap_4549_BIT_4_4679_468_ETC___d14714 = (!commitStage_commitTrap[4] || commitStage_commitTrap[3:0] == 4'd0 || commitStage_commitTrap[3:0] == 4'd1 || @@ -24287,13 +24126,13 @@ module mkCore(CLK, commitStage_commitTrap[3:0] == 4'd11) && (commitStage_commitTrap[4] || commitStage_commitTrap[3:0] != 4'd3 || - CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q243) ; - assign NOT_commitStage_commitTrap_4555_BIT_4_4779_478_ETC___d14821 = - NOT_commitStage_commitTrap_4555_BIT_4_4779_478_ETC___d14814 || + CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q235) ; + assign NOT_commitStage_commitTrap_4549_BIT_4_4679_468_ETC___d14721 = + NOT_commitStage_commitTrap_4549_BIT_4_4679_468_ETC___d14714 || coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty && fetchStage$iTlbIfc_noPendingReq && coreFix_memExe_dTlb$noPendingReq ; - assign NOT_commitStage_commitTrap_4555_BIT_4_4779_478_ETC___d14881 = + assign NOT_commitStage_commitTrap_4549_BIT_4_4679_468_ETC___d14781 = (!commitStage_commitTrap[4] || commitStage_commitTrap[3:0] != 4'd14) && (!commitStage_commitTrap[4] || @@ -24309,26 +24148,26 @@ module mkCore(CLK, commitStage_commitTrap[3:0] == 4'd14) && (commitStage_commitTrap[4] || commitStage_commitTrap[3:0] != 4'd3 || - CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q243) ; - assign NOT_commitStage_rg_run_state_4553_4554_AND_NOT_ETC___d15010 = + CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q235) ; + assign NOT_commitStage_rg_run_state_4547_4548_AND_NOT_ETC___d14951 = !commitStage_rg_run_state && !commitStage_commitTrap[133] && !rob$deqPort_0_deq_data[167] && !rob$deqPort_0_deq_data[18] && rob$deqPort_0_deq_data[25] ; - assign NOT_coreFix_aluExe_0_bypassWire_0_whas__2372_2_ETC___d12399 = + assign NOT_coreFix_aluExe_0_bypassWire_0_whas__2369_2_ETC___d12396 = (!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_aluExe_0_bypassWire_0_wget__2373_BITS__ETC___d12375) && + !coreFix_aluExe_0_bypassWire_0_wget__2370_BITS__ETC___d12372) && (!coreFix_aluExe_0_bypassWire_1$whas || - !coreFix_aluExe_0_bypassWire_1_wget__2386_BITS__ETC___d12388) && + !coreFix_aluExe_0_bypassWire_1_wget__2383_BITS__ETC___d12385) && (!coreFix_aluExe_0_bypassWire_2$whas || - !coreFix_aluExe_0_bypassWire_2_wget__2394_BITS__ETC___d12396) ; - assign NOT_coreFix_aluExe_0_bypassWire_0_whas__2372_2_ETC___d12429 = + !coreFix_aluExe_0_bypassWire_2_wget__2391_BITS__ETC___d12393) ; + assign NOT_coreFix_aluExe_0_bypassWire_0_whas__2369_2_ETC___d12426 = (!coreFix_aluExe_0_bypassWire_0$whas || - !coreFix_aluExe_0_bypassWire_0_wget__2373_BITS__ETC___d12416) && + !coreFix_aluExe_0_bypassWire_0_wget__2370_BITS__ETC___d12413) && (!coreFix_aluExe_0_bypassWire_1$whas || - !coreFix_aluExe_0_bypassWire_1_wget__2386_BITS__ETC___d12422) && + !coreFix_aluExe_0_bypassWire_1_wget__2383_BITS__ETC___d12419) && (!coreFix_aluExe_0_bypassWire_2$whas || - !coreFix_aluExe_0_bypassWire_2_wget__2394_BITS__ETC___d12426) ; + !coreFix_aluExe_0_bypassWire_2_wget__2391_BITS__ETC___d12423) ; assign NOT_coreFix_aluExe_1_bypassWire_0_whas__1510_1_ETC___d11537 = (!coreFix_aluExe_0_bypassWire_0$whas || !coreFix_aluExe_1_bypassWire_0_wget__1511_BITS__ETC___d11513) && @@ -24525,7 +24364,7 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[5] ; assign NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__48_ETC___d8540 = coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] != 3'd3 || - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q263 ; + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q253 ; assign NOT_coreFix_memExe_bypassWire_0_whas__584_590__ETC___d1611 = (!coreFix_aluExe_0_bypassWire_0$whas || !coreFix_memExe_bypassWire_0_wget__585_BITS_70__ETC___d1587) && @@ -24842,7 +24681,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_pipelineResp_releaseEntry && (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc[3] || !coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full) ; - assign NOT_csrf_fs_reg_read__1726_EQ_0_3169_3170_OR_N_ETC___d13503 = + assign NOT_csrf_fs_reg_read__1726_EQ_0_3165_3166_OR_N_ETC___d13499 = (csrf_fs_reg != 2'd0 || (!fetchStage$pipelines_0_first[95] || !fetchStage$pipelines_0_first[94]) && @@ -24852,9 +24691,9 @@ module mkCore(CLK, (!fetchStage$pipelines_0_first[75] || !fetchStage$pipelines_0_first[74])) && (fetchStage$pipelines_0_first[199:195] != 5'd13 || - NOT_fetchStage_pipelines_0_first__2934_BITS_19_ETC___d13499 && - !csrf_prv_reg_read__2964_ULT_IF_fetchStage_pipe_ETC___d13212) ; - assign NOT_csrf_fs_reg_read__1726_EQ_0_3169_3170_OR_N_ETC___d13595 = + NOT_fetchStage_pipelines_0_first__2931_BITS_19_ETC___d13495 && + !csrf_prv_reg_read__2961_ULT_IF_fetchStage_pipe_ETC___d13208) ; + assign NOT_csrf_fs_reg_read__1726_EQ_0_3165_3166_OR_N_ETC___d13591 = (csrf_fs_reg != 2'd0 || (!fetchStage$pipelines_0_first[95] || !fetchStage$pipelines_0_first[94]) && @@ -24866,7 +24705,7 @@ module mkCore(CLK, (fetchStage$pipelines_0_first[231:200] != 32'h10500073 || !csrf_tw_reg || csrf_prv_reg == 2'd3) ; - assign NOT_csrf_fs_reg_read__1726_EQ_0_3169_3170_OR_N_ETC___d13888 = + assign NOT_csrf_fs_reg_read__1726_EQ_0_3165_3166_OR_N_ETC___d13884 = (csrf_fs_reg != 2'd0 || (!fetchStage$pipelines_1_first[95] || !fetchStage$pipelines_1_first[94]) && @@ -24878,215 +24717,215 @@ module mkCore(CLK, (fetchStage$pipelines_1_first[231:200] != 32'h10500073 || !csrf_tw_reg || csrf_prv_reg == 2'd3) ; - assign NOT_csrf_prv_reg_read__2964_ULE_1_4882_4923_OR_ETC___d14927 = - !csrf_prv_reg_read__2964_ULE_1___d14882 || + assign NOT_csrf_prv_reg_read__2961_ULE_1_4782_4823_OR_ETC___d14827 = + !csrf_prv_reg_read__2961_ULE_1___d14782 || (commitStage_commitTrap[4] ? - !_0b0_CONCAT_csrf_mideleg_11_reg_read__1839_1840_ETC___d14884 : - !_0b0_CONCAT_csrf_medeleg_15_reg_read__1831_1832_ETC___d14902) ; - assign NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d13701 = + !_0b0_CONCAT_csrf_mideleg_11_reg_read__1839_1840_ETC___d14784 : + !_0b0_CONCAT_csrf_medeleg_15_reg_read__1831_1832_ETC___d14802) ; + assign NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d13697 = !fetchStage$pipelines_0_canDeq || !regRenamingTable$rename_0_canRename || - fetchStage_pipelines_0_first__2934_BITS_199_TO_ETC___d13683 || - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d13698 || + fetchStage_pipelines_0_first__2931_BITS_199_TO_ETC___d13679 || + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d13694 || fetchStage$pipelines_0_first[194:192] != 3'd1 ; - assign NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d13935 = + assign NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d13931 = (!fetchStage$pipelines_0_canDeq || fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || - NOT_regRenamingTable_rename_0_canRename__3582__ETC___d13926 || + NOT_regRenamingTable_rename_0_canRename__3578__ETC___d13922 || fetchStage$pipelines_0_first[194:192] != 3'd0 && fetchStage$pipelines_0_first[194:192] != 3'd1 || - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3613_co_ETC___d13623) && + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3609_co_ETC___d13619) && coreFix_aluExe_1_rsAlu$canEnq && - !coreFix_aluExe_0_rsAlu_approximateCount__3617__ETC___d13619 ; - assign NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d13979 = + !coreFix_aluExe_0_rsAlu_approximateCount__3613__ETC___d13615 ; + assign NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d13975 = (!fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first) && - (regRenamingTable_rename_0_canRename__3582_AND__ETC___d13653 && + (regRenamingTable_rename_0_canRename__3578_AND__ETC___d13649 && (fetchStage$pipelines_0_first[194:192] == 3'd3 || fetchStage$pipelines_0_first[194:192] == 3'd4) || !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq || - NOT_regRenamingTable_rename_1_canRename__3704__ETC___d13966) ; - assign NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d14034 = + NOT_regRenamingTable_rename_1_canRename__3700__ETC___d13962) ; + assign NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d14030 = !fetchStage$pipelines_0_canDeq || !regRenamingTable$rename_0_canRename || - fetchStage_pipelines_0_first__2934_BITS_199_TO_ETC___d13683 || + fetchStage_pipelines_0_first__2931_BITS_199_TO_ETC___d13679 || fetchStage$pipelines_0_first[194:192] != 3'd3 && fetchStage$pipelines_0_first[194:192] != 3'd4 ; - assign NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d14052 = + assign NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d14048 = (!fetchStage$pipelines_0_canDeq || - NOT_regRenamingTable_rename_0_canRename__3582__ETC___d14002 || + NOT_regRenamingTable_rename_0_canRename__3578__ETC___d13998 || fetchStage$pipelines_0_first[194:192] != 3'd2 || - IF_fetchStage_pipelines_0_first__2934_BITS_191_ETC___d13693) && + IF_fetchStage_pipelines_0_first__2931_BITS_191_ETC___d13689) && coreFix_memExe_rsMem$canEnq && - CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q238 ; - assign NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d14201 = + CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q230 ; + assign NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d14197 = (!fetchStage$pipelines_0_canDeq || - NOT_specTagManager_canClaim__3580_3666_OR_NOT__ETC___d14172) && - CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q242 && + NOT_specTagManager_canClaim__3576_3662_OR_NOT__ETC___d14168) && + CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q234 && (fetchStage$pipelines_1_first[199:195] == 5'd14 || coreFix_memExe_rsMem$RDY_enq) ; - assign NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d14255 = + assign NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d14251 = (!fetchStage$pipelines_0_canDeq || - fetchStage_pipelines_0_first__2934_BITS_194_TO_ETC___d14121 && - IF_fetchStage_RDY_pipelines_0_first__2931_AND__ETC___d13610) && + fetchStage_pipelines_0_first__2931_BITS_194_TO_ETC___d14117 && + IF_fetchStage_RDY_pipelines_0_first__2928_AND__ETC___d13606) && fetchStage$RDY_pipelines_0_first && - fetchStage_pipelines_0_canDeq__2932_AND_fetchS_ETC___d14253 ; - assign NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d14383 = + fetchStage_pipelines_0_canDeq__2929_AND_fetchS_ETC___d14249 ; + assign NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d14379 = (!fetchStage$pipelines_0_canDeq || fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || - NOT_regRenamingTable_rename_0_canRename__3582__ETC___d14378 || + NOT_regRenamingTable_rename_0_canRename__3578__ETC___d14374 || fetchStage$pipelines_0_first[194:192] != 3'd0 && fetchStage$pipelines_0_first[194:192] != 3'd1 || - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3613_co_ETC___d13623) && + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3609_co_ETC___d13619) && coreFix_aluExe_1_rsAlu$canEnq && - !coreFix_aluExe_0_rsAlu_approximateCount__3617__ETC___d13619 ; - assign NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d14388 = + !coreFix_aluExe_0_rsAlu_approximateCount__3613__ETC___d13615 ; + assign NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d14384 = (!fetchStage$pipelines_0_canDeq || - NOT_fetchStage_pipelines_0_first__2934_BITS_19_ETC___d14262 && - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d13639) && + NOT_fetchStage_pipelines_0_first__2931_BITS_19_ETC___d14258 && + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d13635) && fetchStage$pipelines_1_canDeq ; - assign NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d14390 = + assign NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d14386 = !fetchStage$pipelines_0_canDeq || !regRenamingTable$rename_0_canRename || - renameStage_rg_m_halt_req_2961_BIT_4_2962_OR_f_ETC___d14085 || - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d13698 || + renameStage_rg_m_halt_req_2958_BIT_4_2959_OR_f_ETC___d14081 || + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d13694 || fetchStage$pipelines_0_first[194:192] != 3'd1 ; - assign NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d14402 = - NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d14388 && - NOT_fetchStage_pipelines_1_first__2943_BITS_19_ETC___d14399 && + assign NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d14398 = + NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d14384 && + NOT_fetchStage_pipelines_1_first__2940_BITS_19_ETC___d14395 && (fetchStage$pipelines_1_first[194:192] == 3'd0 || fetchStage$pipelines_1_first[194:192] == 3'd1) && - SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__293_ETC___d14167 ; - assign NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d14438 = + SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__292_ETC___d14163 ; + assign NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d14434 = !fetchStage$pipelines_0_canDeq || !regRenamingTable$rename_0_canRename || - renameStage_rg_m_halt_req_2961_BIT_4_2962_OR_f_ETC___d14085 || + renameStage_rg_m_halt_req_2958_BIT_4_2959_OR_f_ETC___d14081 || fetchStage$pipelines_0_first[194:192] != 3'd3 && fetchStage$pipelines_0_first[194:192] != 3'd4 ; - assign NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d14458 = - NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d14388 && - regRenamingTable_rename_1_canRename__3704_AND__ETC___d14398 && + assign NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d14454 = + NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d14384 && + regRenamingTable_rename_1_canRename__3700_AND__ETC___d14394 && (fetchStage$pipelines_1_first[194:192] == 3'd3 || fetchStage$pipelines_1_first[194:192] == 3'd4) && - NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d14438 && + NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d14434 && coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq && - NOT_fetchStage_pipelines_1_first__2943_BITS_32_ETC___d14453 ; - assign NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d14465 = + NOT_fetchStage_pipelines_1_first__2940_BITS_32_ETC___d14449 ; + assign NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d14461 = !fetchStage$pipelines_0_canDeq || !regRenamingTable$rename_0_canRename || - renameStage_rg_m_halt_req_2961_BIT_4_2962_OR_f_ETC___d14085 || + renameStage_rg_m_halt_req_2958_BIT_4_2959_OR_f_ETC___d14081 || fetchStage$pipelines_0_first[194:192] != 3'd2 || - IF_fetchStage_pipelines_0_first__2934_BITS_191_ETC___d13693 ; - assign NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d14466 = - NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d14465 && + IF_fetchStage_pipelines_0_first__2931_BITS_191_ETC___d13689 ; + assign NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d14462 = + NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d14461 && coreFix_memExe_rsMem$canEnq && - CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q238 ; - assign NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d14510 = - NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d14390 && + CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q230 ; + assign NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d14506 = + NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d14386 && specTagManager$canClaim && - regRenamingTable_rename_1_canRename__3704_AND__ETC___d14398 && - IF_fetchStage_pipelines_1_first__2943_BITS_194_ETC___d14067 && + regRenamingTable_rename_1_canRename__3700_AND__ETC___d14394 && + IF_fetchStage_pipelines_1_first__2940_BITS_194_ETC___d14063 && fetchStage$pipelines_1_first[194:192] == 3'd1 ; - assign NOT_fetchStage_pipelines_0_first__2934_BITS_19_ETC___d13499 = + assign NOT_fetchStage_pipelines_0_first__2931_BITS_19_ETC___d13495 = (fetchStage$pipelines_0_first[194:192] != 3'd0 || fetchStage$pipelines_0_first[178:174] != 5'd15) && - rs1__h659223 == 5'd0 && - imm__h659224 == 32'd0 || - IF_fetchStage_pipelines_0_first__2934_BIT_173__ETC___d13207[11:10] != + rs1__h658887 == 5'd0 && + imm__h658888 == 32'd0 || + IF_fetchStage_pipelines_0_first__2931_BIT_173__ETC___d13203[11:10] != 2'b11 ; - assign NOT_fetchStage_pipelines_0_first__2934_BITS_19_ETC___d13640 = + assign NOT_fetchStage_pipelines_0_first__2931_BITS_19_ETC___d13636 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3582_AND__ETC___d13604 && - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d13639 ; - assign NOT_fetchStage_pipelines_0_first__2934_BITS_19_ETC___d13911 = + regRenamingTable_rename_0_canRename__3578_AND__ETC___d13600 && + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d13635 ; + assign NOT_fetchStage_pipelines_0_first__2931_BITS_19_ETC___d13907 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3582_AND__ETC___d13604 && - fetchStage_pipelines_0_first__2934_BITS_194_TO_ETC___d13910 ; - assign NOT_fetchStage_pipelines_0_first__2934_BITS_19_ETC___d13917 = + regRenamingTable_rename_0_canRename__3578_AND__ETC___d13600 && + fetchStage_pipelines_0_first__2931_BITS_194_TO_ETC___d13906 ; + assign NOT_fetchStage_pipelines_0_first__2931_BITS_19_ETC___d13913 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3582_AND__ETC___d13604 && + regRenamingTable_rename_0_canRename__3578_AND__ETC___d13600 && (fetchStage$pipelines_0_first[194:192] == 3'd0 || fetchStage$pipelines_0_first[194:192] == 3'd1) && - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3613_co_ETC___d13623 && + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3609_co_ETC___d13619 && (!coreFix_aluExe_0_rsAlu$canEnq || - !coreFix_aluExe_0_rsAlu_approximateCount__3617__ETC___d13619) ; - assign NOT_fetchStage_pipelines_0_first__2934_BITS_19_ETC___d14078 = + !coreFix_aluExe_0_rsAlu_approximateCount__3613__ETC___d13615) ; + assign NOT_fetchStage_pipelines_0_first__2931_BITS_19_ETC___d14074 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3582_AND__ETC___d13604 && - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d13663 ; - assign NOT_fetchStage_pipelines_0_first__2934_BITS_19_ETC___d14262 = + regRenamingTable_rename_0_canRename__3578_AND__ETC___d13600 && + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d13659 ; + assign NOT_fetchStage_pipelines_0_first__2931_BITS_19_ETC___d14258 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && regRenamingTable$rename_0_canRename && - !checkForException___d13180[4] && + !checkForException___d13176[4] && rob$enqPort_0_canEnq ; - assign NOT_fetchStage_pipelines_0_first__2934_BITS_19_ETC___d14362 = + assign NOT_fetchStage_pipelines_0_first__2931_BITS_19_ETC___d14358 = { fetchStage$pipelines_0_first[194:192] != 3'd2 || !coreFix_memExe_rsMem$canEnq || - IF_fetchStage_pipelines_0_first__2934_BITS_191_ETC___d13693 || - IF_fetchStage_pipelines_0_first__2934_BITS_191_ETC___d14304, + IF_fetchStage_pipelines_0_first__2931_BITS_191_ETC___d13689 || + IF_fetchStage_pipelines_0_first__2931_BITS_191_ETC___d14300, (fetchStage$pipelines_0_first[194:192] == 3'd2 && coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2934_BITS_191_ETC___d13635 && - IF_fetchStage_pipelines_0_first__2934_BITS_191_ETC___d14307) ? - IF_fetchStage_pipelines_0_first__2934_BITS_191_ETC___d14310 : + IF_fetchStage_pipelines_0_first__2931_BITS_191_ETC___d13631 && + IF_fetchStage_pipelines_0_first__2931_BITS_191_ETC___d14303) ? + IF_fetchStage_pipelines_0_first__2931_BITS_191_ETC___d14306 : { 1'h0, - IF_fetchStage_pipelines_0_first__2934_BITS_191_ETC___d14313 }, + IF_fetchStage_pipelines_0_first__2931_BITS_191_ETC___d14309 }, 7'd32, specTagManager$currentSpecBits } ; - assign NOT_fetchStage_pipelines_0_first__2934_BITS_32_ETC___d14286 = + assign NOT_fetchStage_pipelines_0_first__2931_BITS_32_ETC___d14282 = fetchStage$pipelines_0_first[323:260] != - fallthrough_pc__h668018 ; - assign NOT_fetchStage_pipelines_0_first__2934_BIT_68__ETC___d13651 = + fallthrough_pc__h667681 ; + assign NOT_fetchStage_pipelines_0_first__2931_BIT_68__ETC___d13647 = !fetchStage$pipelines_0_first[68] && - !checkForException___d13180[4] && - NOT_csrf_fs_reg_read__1726_EQ_0_3169_3170_OR_N_ETC___d13595 && + !checkForException___d13176[4] && + NOT_csrf_fs_reg_read__1726_EQ_0_3165_3166_OR_N_ETC___d13591 && rob$enqPort_0_canEnq && epochManager$checkEpoch_0_check ; - assign NOT_fetchStage_pipelines_1_canDeq__2940_2941_O_ETC___d12949 = + assign NOT_fetchStage_pipelines_1_canDeq__2937_2938_O_ETC___d12946 = !fetchStage$pipelines_1_canDeq || fetchStage$RDY_pipelines_1_first && (epochManager$checkEpoch_1_check || fetchStage$RDY_pipelines_1_deq) ; - assign NOT_fetchStage_pipelines_1_first__2943_BITS_19_ETC___d13674 = + assign NOT_fetchStage_pipelines_1_first__2940_BITS_19_ETC___d13670 = (fetchStage$pipelines_1_first[194:192] != 3'd1 || !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first) && (fetchStage$RDY_pipelines_0_first && fetchStage$pipelines_1_first[194:192] == 3'd1 && - regRenamingTable_rename_0_canRename__3582_AND__ETC___d13667 || - csrf_rg_dcsr_read__1902_BIT_2_3232_OR_NOT_fetc_ETC___d13672) ; - assign NOT_fetchStage_pipelines_1_first__2943_BITS_19_ETC___d13904 = + regRenamingTable_rename_0_canRename__3578_AND__ETC___d13663 || + csrf_rg_dcsr_read__1899_BIT_2_3228_OR_NOT_fetc_ETC___d13668) ; + assign NOT_fetchStage_pipelines_1_first__2940_BITS_19_ETC___d13900 = (fetchStage$pipelines_1_first[194:192] != 3'd1 || - NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d13701 && + NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d13697 && specTagManager$canClaim) && - regRenamingTable_rename_1_canRename__3704_AND__ETC___d13903 ; - assign NOT_fetchStage_pipelines_1_first__2943_BITS_19_ETC___d14021 = + regRenamingTable_rename_1_canRename__3700_AND__ETC___d13899 ; + assign NOT_fetchStage_pipelines_1_first__2940_BITS_19_ETC___d14017 = (fetchStage$pipelines_1_first[194:192] != 3'd1 || (!fetchStage$pipelines_0_canDeq || - NOT_regRenamingTable_rename_0_canRename__3582__ETC___d14002 || - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d14015 || + NOT_regRenamingTable_rename_0_canRename__3578__ETC___d13998 || + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d14011 || fetchStage$pipelines_0_first[194:192] != 3'd1) && specTagManager$canClaim) && - regRenamingTable_rename_1_canRename__3704_AND__ETC___d13903 ; - assign NOT_fetchStage_pipelines_1_first__2943_BITS_19_ETC___d14399 = + regRenamingTable_rename_1_canRename__3700_AND__ETC___d13899 ; + assign NOT_fetchStage_pipelines_1_first__2940_BITS_19_ETC___d14395 = (fetchStage$pipelines_1_first[194:192] != 3'd1 || - NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d14390 && + NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d14386 && specTagManager$canClaim) && - regRenamingTable_rename_1_canRename__3704_AND__ETC___d14398 ; - assign NOT_fetchStage_pipelines_1_first__2943_BITS_32_ETC___d14453 = + regRenamingTable_rename_1_canRename__3700_AND__ETC___d14394 ; + assign NOT_fetchStage_pipelines_1_first__2940_BITS_32_ETC___d14449 = fetchStage$pipelines_1_first[323:260] != - fallthrough_pc__h683403 ; - assign NOT_fetchStage_pipelines_1_first__2943_BIT_68__ETC___d14396 = + fallthrough_pc__h683049 ; + assign NOT_fetchStage_pipelines_1_first__2940_BIT_68__ETC___d14392 = !fetchStage$pipelines_1_first[68] && - !checkForException___d13863[4] && - NOT_csrf_fs_reg_read__1726_EQ_0_3169_3170_OR_N_ETC___d13888 && + !checkForException___d13859[4] && + NOT_csrf_fs_reg_read__1726_EQ_0_3165_3166_OR_N_ETC___d13884 && rob$enqPort_1_canEnq && epochManager$checkEpoch_1_check && !csrf_rg_dcsr[2] ; @@ -25169,7 +25008,7 @@ module mkCore(CLK, (mmio_pRsQ_deqReq_dummy2_2$Q_OUT && (mmio_pRsQ_deqReq_lat_0$whas || mmio_pRsQ_deqReq_rl) || mmio_pRsQ_empty) ; - assign NOT_regRenamingTable_rename_0_canRename__3582__ETC___d13926 = + assign NOT_regRenamingTable_rename_0_canRename__3578__ETC___d13922 = !regRenamingTable$rename_0_canRename || fetchStage$pipelines_0_first[199:195] == 5'd0 || fetchStage$pipelines_0_first[199:195] == 5'd21 || @@ -25180,8 +25019,8 @@ module mkCore(CLK, fetchStage$pipelines_0_first[199:195] == 5'd15 || fetchStage$pipelines_0_first[199:195] == 5'd19 || fetchStage$pipelines_0_first[199:195] == 5'd20 || - renameStage_rg_m_halt_req_2961_BIT_4_2962_OR_f_ETC___d13924 ; - assign NOT_regRenamingTable_rename_0_canRename__3582__ETC___d14002 = + renameStage_rg_m_halt_req_2958_BIT_4_2959_OR_f_ETC___d13920 ; + assign NOT_regRenamingTable_rename_0_canRename__3578__ETC___d13998 = !regRenamingTable$rename_0_canRename || fetchStage$pipelines_0_first[199:195] == 5'd0 || fetchStage$pipelines_0_first[199:195] == 5'd21 || @@ -25192,14 +25031,14 @@ module mkCore(CLK, fetchStage$pipelines_0_first[199:195] == 5'd15 || fetchStage$pipelines_0_first[199:195] == 5'd19 || fetchStage$pipelines_0_first[199:195] == 5'd20 || - fetchStage_pipelines_0_first__2934_BIT_68_2963_ETC___d14000 ; - assign NOT_regRenamingTable_rename_0_canRename__3582__ETC___d14378 = + fetchStage_pipelines_0_first__2931_BIT_68_2960_ETC___d13996 ; + assign NOT_regRenamingTable_rename_0_canRename__3578__ETC___d14374 = !regRenamingTable$rename_0_canRename || renameStage_rg_m_halt_req[4] || fetchStage$pipelines_0_first[68] || - checkForException___d13180[4] || + checkForException___d13176[4] || !rob$enqPort_0_canEnq ; - assign NOT_regRenamingTable_rename_1_canRename__3704__ETC___d13966 = + assign NOT_regRenamingTable_rename_1_canRename__3700__ETC___d13962 = !regRenamingTable$rename_1_canRename || fetchStage$pipelines_1_first[199:195] == 5'd0 || fetchStage$pipelines_1_first[199:195] == 5'd21 || @@ -25210,58 +25049,58 @@ module mkCore(CLK, fetchStage$pipelines_1_first[199:195] == 5'd15 || fetchStage$pipelines_1_first[199:195] == 5'd19 || fetchStage$pipelines_1_first[199:195] == 5'd20 || - renameStage_rg_m_halt_req_2961_BIT_4_2962_OR_f_ETC___d13964 ; - assign NOT_renameStage_rg_m_halt_req_2961_BIT_4_2962__ETC___d13272 = + renameStage_rg_m_halt_req_2958_BIT_4_2959_OR_f_ETC___d13960 ; + assign NOT_renameStage_rg_m_halt_req_2958_BIT_4_2959__ETC___d13268 = !renameStage_rg_m_halt_req[4] && (fetchStage$pipelines_0_first[68] || - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[0] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[1] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[2] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[3] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[4] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[5] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[6] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[7] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[8] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[9] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[10] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[11] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[12] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[13] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[14] && - !IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[15]) ; - assign NOT_renameStage_rg_m_halt_req_2961_BIT_4_2962__ETC___d13602 = + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[0] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[1] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[2] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[3] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[4] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[5] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[6] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[7] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[8] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[9] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[10] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[11] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[12] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[13] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[14] && + !IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[15]) ; + assign NOT_renameStage_rg_m_halt_req_2958_BIT_4_2959__ETC___d13598 = !renameStage_rg_m_halt_req[4] && !fetchStage$pipelines_0_first[68] && - NOT_IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_296_ETC___d13597 && + NOT_IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_296_ETC___d13593 && rob$enqPort_0_canEnq && epochManager$checkEpoch_0_check ; - assign NOT_renameStage_rg_m_halt_req_2961_BIT_4_2962__ETC___d13901 = + assign NOT_renameStage_rg_m_halt_req_2958_BIT_4_2959__ETC___d13897 = !renameStage_rg_m_halt_req[4] && !fetchStage$pipelines_1_first[68] && - NOT_IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_296_ETC___d13890 && + NOT_IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_296_ETC___d13886 && rob$enqPort_1_canEnq && - epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13899 ; - assign NOT_renameStage_rg_m_halt_req_2961_BIT_4_2962__ETC___d14043 = + epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13895 ; + assign NOT_renameStage_rg_m_halt_req_2958_BIT_4_2959__ETC___d14039 = !renameStage_rg_m_halt_req[4] && !fetchStage$pipelines_1_first[68] && - NOT_IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_296_ETC___d13890 && + NOT_IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_296_ETC___d13886 && rob$enqPort_1_canEnq && - epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d14041 ; - assign NOT_renameStage_rg_m_halt_req_2961_BIT_4_2962__ETC___d14061 = + epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d14037 ; + assign NOT_renameStage_rg_m_halt_req_2958_BIT_4_2959__ETC___d14057 = !renameStage_rg_m_halt_req[4] && !fetchStage$pipelines_1_first[68] && - NOT_IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_296_ETC___d13890 && + NOT_IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_296_ETC___d13886 && rob$enqPort_1_canEnq && - epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d14059 ; - assign NOT_rob_deqPort_0_canDeq__5214_5215_OR_rob_RDY_ETC___d15256 = + epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d14055 ; + assign NOT_rob_deqPort_0_canDeq__5156_5157_OR_rob_RDY_ETC___d15195 = (!rob$deqPort_0_canDeq || - rob$RDY_deqPort_0_deq && regRenamingTable$RDY_commit_0_commit && - v_f_to_TV_0$FULL_N) && + rob$RDY_deqPort_0_deq && + regRenamingTable$RDY_commit_0_commit) && (!rob$deqPort_1_canDeq || rob$RDY_deqPort_1_deq_data && - NOT_rob_deqPort_1_deq_data__5222_BIT_25_5223_5_ETC___d15253) ; - assign NOT_rob_deqPort_0_canDeq__5214_5215_OR_rob_deq_ETC___d15503 = + NOT_rob_deqPort_1_deq_data__5163_BIT_25_5164_5_ETC___d15192) ; + assign NOT_rob_deqPort_0_canDeq__5156_5157_OR_rob_deq_ETC___d15348 = (!rob$deqPort_0_canDeq || rob$deqPort_0_deq_data[25] && !rob$deqPort_0_deq_data[18] && !rob$deqPort_0_deq_data[167] && @@ -25275,15 +25114,15 @@ module mkCore(CLK, rob$deqPort_0_deq_data[186:182] != 5'd19 && rob$deqPort_0_deq_data[186:182] != 5'd20) && rob$deqPort_1_canDeq ; - assign NOT_rob_deqPort_0_deq_data__4547_BITS_186_TO_1_ETC___d14999 = + assign NOT_rob_deqPort_0_deq_data__4542_BITS_186_TO_1_ETC___d14941 = rob$deqPort_0_deq_data[186:182] != 5'd13 || - (IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 != + (IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 != 6'd7 || csrf_stats_module_writeQ$FULL_N) && - (IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 != + (IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 != 6'd6 || csrf_terminate_module_terminateQ$FULL_N) ; - assign NOT_rob_deqPort_1_deq_data__5222_BIT_25_5223_5_ETC___d15253 = + assign NOT_rob_deqPort_1_deq_data__5163_BIT_25_5164_5_ETC___d15192 = !rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[186:182] == 5'd0 || @@ -25295,60 +25134,59 @@ module mkCore(CLK, rob$deqPort_1_deq_data[186:182] == 5'd15 || rob$deqPort_1_deq_data[186:182] == 5'd19 || rob$deqPort_1_deq_data[186:182] == 5'd20 || - rob$RDY_deqPort_1_deq && regRenamingTable$RDY_commit_1_commit && - v_f_to_TV_1$FULL_N ; - assign NOT_specTagManager_canClaim__3580_3666_OR_NOT__ETC___d14172 = + rob$RDY_deqPort_1_deq && regRenamingTable$RDY_commit_1_commit ; + assign NOT_specTagManager_canClaim__3576_3662_OR_NOT__ETC___d14168 = !specTagManager$canClaim || !regRenamingTable$rename_0_canRename || - fetchStage_pipelines_0_first__2934_BITS_199_TO_ETC___d13683 || - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d14112 || + fetchStage_pipelines_0_first__2931_BITS_199_TO_ETC___d13679 || + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d14108 || fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$RDY_nextSpecTag ; - assign NOT_specTagManager_canClaim__3580_3666_OR_NOT__ETC___d14239 = + assign NOT_specTagManager_canClaim__3576_3662_OR_NOT__ETC___d14235 = !specTagManager$canClaim || !regRenamingTable$rename_0_canRename || - renameStage_rg_m_halt_req_2961_BIT_4_2962_OR_f_ETC___d14085 || - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d14112 || + renameStage_rg_m_halt_req_2958_BIT_4_2959_OR_f_ETC___d14081 || + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d14108 || fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$RDY_nextSpecTag ; assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3013 = - { CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q23, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q24, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q25, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q26 } ; + { CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q15, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q16, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q17, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q18 } ; assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3022 = { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3013, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q27, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q28 } ; + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q19, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q20 } ; assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3031 = { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3022, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q254, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q255 } ; + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q244, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q245 } ; assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3038 = - { CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q261, - !CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q262, + { CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q251, + !CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q252, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3031, - x__h293849 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d15932 = - { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q264, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q265, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q266 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15888 = - { CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q245, + x__h293541 } ; + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d15778 = + { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q254, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q255, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q256 } ; + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15734 = + { CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q237, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q238, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q239, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q240 } ; + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15743 = + { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15734, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q241, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q242 } ; + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15752 = + { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15743, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q246, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q247, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q248 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15897 = - { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15888, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q249, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q250 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15906 = - { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15897, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q256, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q257 } ; + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q247 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10242 = - { {4{f2_exp23940_MINUS_127__q176[7]}}, - f2_exp23940_MINUS_127__q176 } ; + { {4{f2_exp23631_MINUS_127__q168[7]}}, + f2_exp23631_MINUS_127__q168 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10243 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10242 ^ 12'h800) <= @@ -25358,12 +25196,12 @@ module mkCore(CLK, 12'h800) < 12'd1026 ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d11187 = - b__h605940 * b__h606016 ; + b__h605631 * b__h605707 ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d11200 = - b__h605940 * b__h606129 ; + b__h605631 * b__h605820 ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8757 = - { {4{f1_exp84946_MINUS_127__q136[7]}}, - f1_exp84946_MINUS_127__q136 } ; + { {4{f1_exp84637_MINUS_127__q128[7]}}, + f1_exp84637_MINUS_127__q128 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8758 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8757 ^ 12'h800) <= @@ -25373,8 +25211,8 @@ module mkCore(CLK, 12'h800) < 12'd1026 ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9472 = - { {4{f3_exp63244_MINUS_127__q153[7]}}, - f3_exp63244_MINUS_127__q153 } ; + { {4{f3_exp62935_MINUS_127__q145[7]}}, + f3_exp62935_MINUS_127__q145 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9473 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9472 ^ 12'h800) <= @@ -25383,27 +25221,27 @@ module mkCore(CLK, (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9472 ^ 12'h800) < 12'd1026 ; - assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137 = + assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q129 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8757 + 12'd1023 ; - assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q140 = - SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137[10:0] - + assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q132 = + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q129[10:0] - 11'd1023 ; - assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q154 = + assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q146 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9472 + 12'd1023 ; - assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q157 = - SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q154[10:0] - + assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q149 = + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q146[10:0] - 11'd1023 ; - assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q177 = + assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q169 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10242 + 12'd1023 ; - assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q180 = - SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q177[10:0] - + assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q172 = + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q169[10:0] - 11'd1023 ; assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6039 = - { coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q72[10], - coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q72 } ; + { coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q64[10], + coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q64 } ; assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6040 = (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6039 ^ 12'h800) <= @@ -25412,15 +25250,15 @@ module mkCore(CLK, (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6039 ^ 12'h800) < 12'd1922 ; - assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q73 = + assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q65 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6039 + 12'd127 ; - assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q78 = - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q73[7:0] - + assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q70 = + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q65[7:0] - 8'd127 ; assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4647 = - { coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q37[10], - coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q37 } ; + { coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q29[10], + coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q29 } ; assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4648 = (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4647 ^ 12'h800) <= @@ -25429,15 +25267,15 @@ module mkCore(CLK, (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4647 ^ 12'h800) < 12'd1922 ; - assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q38 = + assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q30 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4647 + 12'd127 ; - assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q43 = - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q38[7:0] - + assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q35 = + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q30[7:0] - 8'd127 ; assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7431 = - { coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q107[10], - coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q107 } ; + { coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q99[10], + coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q99 } ; assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7432 = (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7431 ^ 12'h800) <= @@ -25446,11 +25284,11 @@ module mkCore(CLK, (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7431 ^ 12'h800) < 12'd1922 ; - assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q108 = + assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q100 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7431 + 12'd127 ; - assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q113 = - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q108[7:0] - + assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q105 = + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q100[7:0] - 8'd127 ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d4345 = ({ 3'd0, @@ -25459,15 +25297,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5265 = { 3'd0, - _theResult___fst_exp__h356494 == 8'd0 && - (sfdin__h356488[56:34] == 23'd0 || guard__h348393 != 2'b0), + _theResult___fst_exp__h356185 == 8'd0 && + (sfdin__h356179[56:34] == 23'd0 || guard__h348084 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h357091 == 8'd255 && - _theResult___fst_sfd__h357092 == 23'd0, + _theResult___fst_exp__h356782 == 8'd255 && + _theResult___fst_sfd__h356783 == 23'd0, 1'd0, - _theResult___fst_exp__h356494 != 8'd255 && - guard__h348393 != 2'b0 } ; + _theResult___fst_exp__h356185 != 8'd255 && + guard__h348084 != 2'b0 } ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5737 = ({ 3'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5735 } ^ @@ -25475,15 +25313,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6657 = { 3'd0, - _theResult___fst_exp__h402191 == 8'd0 && - (sfdin__h402185[56:34] == 23'd0 || guard__h394092 != 2'b0), + _theResult___fst_exp__h401882 == 8'd0 && + (sfdin__h401876[56:34] == 23'd0 || guard__h393783 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h402788 == 8'd255 && - _theResult___fst_sfd__h402789 == 23'd0, + _theResult___fst_exp__h402479 == 8'd255 && + _theResult___fst_sfd__h402480 == 23'd0, 1'd0, - _theResult___fst_exp__h402191 != 8'd255 && - guard__h394092 != 2'b0 } ; + _theResult___fst_exp__h401882 != 8'd255 && + guard__h393783 != 2'b0 } ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7129 = ({ 3'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7127 } ^ @@ -25491,15 +25329,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d8049 = { 3'd0, - _theResult___fst_exp__h447886 == 8'd0 && - (sfdin__h447880[56:34] == 23'd0 || guard__h439787 != 2'b0), + _theResult___fst_exp__h447577 == 8'd0 && + (sfdin__h447571[56:34] == 23'd0 || guard__h439478 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h448483 == 8'd255 && - _theResult___fst_sfd__h448484 == 23'd0, + _theResult___fst_exp__h448174 == 8'd255 && + _theResult___fst_sfd__h448175 == 23'd0, 1'd0, - _theResult___fst_exp__h447886 != 8'd255 && - guard__h439787 != 2'b0 } ; + _theResult___fst_exp__h447577 != 8'd255 && + guard__h439478 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10493 = ({ 6'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10491 } ^ @@ -25507,37 +25345,37 @@ module mkCore(CLK, 12'd2048 ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10869 = { 3'd0, - _theResult___fst_exp__h513911 == 11'd0 && - (sfdin__h513905[56:5] == 52'd0 || guard__h505685 != 2'b0), + _theResult___fst_exp__h513602 == 11'd0 && + (sfdin__h513596[56:5] == 52'd0 || guard__h505376 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h514743 == 11'd2047 && - _theResult___fst_sfd__h514744 == 52'd0, + _theResult___fst_exp__h514434 == 11'd2047 && + _theResult___fst_sfd__h514435 == 52'd0, 1'd0, - _theResult___fst_exp__h513911 != 11'd2047 && - guard__h505685 != 2'b0 } ; + _theResult___fst_exp__h513602 != 11'd2047 && + guard__h505376 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10910 = { 3'd0, - _theResult___fst_exp__h552764 == 11'd0 && - (sfdin__h552758[56:5] == 52'd0 || guard__h544538 != 2'b0), + _theResult___fst_exp__h552455 == 11'd0 && + (sfdin__h552449[56:5] == 52'd0 || guard__h544229 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h553596 == 11'd2047 && - _theResult___fst_sfd__h553597 == 52'd0, + _theResult___fst_exp__h553287 == 11'd2047 && + _theResult___fst_sfd__h553288 == 52'd0, 1'd0, - _theResult___fst_exp__h552764 != 11'd2047 && - guard__h544538 != 2'b0 } ; + _theResult___fst_exp__h552455 != 11'd2047 && + guard__h544229 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10954 = { 3'd0, - _theResult___fst_exp__h592068 == 11'd0 && - (sfdin__h592062[56:5] == 52'd0 || guard__h583842 != 2'b0), + _theResult___fst_exp__h591759 == 11'd0 && + (sfdin__h591753[56:5] == 52'd0 || guard__h583533 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h592900 == 11'd2047 && - _theResult___fst_sfd__h592901 == 52'd0, + _theResult___fst_exp__h592591 == 11'd2047 && + _theResult___fst_sfd__h592592 == 52'd0, 1'd0, - _theResult___fst_exp__h592068 != 11'd2047 && - guard__h583842 != 2'b0 } ; + _theResult___fst_exp__h591759 != 11'd2047 && + guard__h583533 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d9008 = ({ 6'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9006 } ^ @@ -25555,15 +25393,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5294 = { 3'd0, - _theResult___fst_exp__h374260 == 8'd0 && - (sfdin__h374254[56:34] == 23'd0 || guard__h366032 != 2'b0), + _theResult___fst_exp__h373951 == 8'd0 && + (sfdin__h373945[56:34] == 23'd0 || guard__h365723 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h374857 == 8'd255 && - _theResult___fst_sfd__h374858 == 23'd0, + _theResult___fst_exp__h374548 == 8'd255 && + _theResult___fst_sfd__h374549 == 23'd0, 1'd0, - _theResult___fst_exp__h374260 != 8'd255 && - guard__h366032 != 2'b0 } ; + _theResult___fst_exp__h373951 != 8'd255 && + guard__h365723 != 2'b0 } ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6288 = ({ 3'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6286 } ^ @@ -25571,15 +25409,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6686 = { 3'd0, - _theResult___fst_exp__h419957 == 8'd0 && - (sfdin__h419951[56:34] == 23'd0 || guard__h411729 != 2'b0), + _theResult___fst_exp__h419648 == 8'd0 && + (sfdin__h419642[56:34] == 23'd0 || guard__h411420 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h420554 == 8'd255 && - _theResult___fst_sfd__h420555 == 23'd0, + _theResult___fst_exp__h420245 == 8'd255 && + _theResult___fst_sfd__h420246 == 23'd0, 1'd0, - _theResult___fst_exp__h419957 != 8'd255 && - guard__h411729 != 2'b0 } ; + _theResult___fst_exp__h419648 != 8'd255 && + guard__h411420 != 2'b0 } ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7680 = ({ 3'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7678 } ^ @@ -25587,15 +25425,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d8078 = { 3'd0, - _theResult___fst_exp__h465652 == 8'd0 && - (sfdin__h465646[56:34] == 23'd0 || guard__h457424 != 2'b0), + _theResult___fst_exp__h465343 == 8'd0 && + (sfdin__h465337[56:34] == 23'd0 || guard__h457115 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h466249 == 8'd255 && - _theResult___fst_sfd__h466250 == 23'd0, + _theResult___fst_exp__h465940 == 8'd255 && + _theResult___fst_sfd__h465941 == 23'd0, 1'd0, - _theResult___fst_exp__h465652 != 8'd255 && - guard__h457424 != 2'b0 } ; + _theResult___fst_exp__h465343 != 8'd255 && + guard__h457115 != 2'b0 } ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10196 = ({ 6'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10194 } ^ @@ -25609,37 +25447,37 @@ module mkCore(CLK, 12'h800) ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10852 = { 3'd0, - _theResult___fst_exp__h504334 == 11'd0 && - guard__h496373 != 2'b0, + _theResult___fst_exp__h504025 == 11'd0 && + guard__h496064 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h505092 == 11'd2047 && - _theResult___fst_sfd__h505093 == 52'd0, + _theResult___fst_exp__h504783 == 11'd2047 && + _theResult___fst_sfd__h504784 == 52'd0, 1'd0, - _theResult___fst_exp__h504334 != 11'd2047 && - guard__h496373 != 2'b0 } ; + _theResult___fst_exp__h504025 != 11'd2047 && + guard__h496064 != 2'b0 } ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10893 = { 3'd0, - _theResult___fst_exp__h543187 == 11'd0 && - guard__h535226 != 2'b0, + _theResult___fst_exp__h542878 == 11'd0 && + guard__h534917 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h543945 == 11'd2047 && - _theResult___fst_sfd__h543946 == 52'd0, + _theResult___fst_exp__h543636 == 11'd2047 && + _theResult___fst_sfd__h543637 == 52'd0, 1'd0, - _theResult___fst_exp__h543187 != 11'd2047 && - guard__h535226 != 2'b0 } ; + _theResult___fst_exp__h542878 != 11'd2047 && + guard__h534917 != 2'b0 } ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10937 = { 3'd0, - _theResult___fst_exp__h582491 == 11'd0 && - guard__h574530 != 2'b0, + _theResult___fst_exp__h582182 == 11'd0 && + guard__h574221 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h583249 == 11'd2047 && - _theResult___fst_sfd__h583250 == 52'd0, + _theResult___fst_exp__h582940 == 11'd2047 && + _theResult___fst_sfd__h582941 == 52'd0, 1'd0, - _theResult___fst_exp__h582491 != 11'd2047 && - guard__h574530 != 2'b0 } ; + _theResult___fst_exp__h582182 != 11'd2047 && + guard__h574221 != 2'b0 } ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8696 = ({ 6'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8694 } ^ @@ -25675,15 +25513,15 @@ module mkCore(CLK, 9'h100) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5277 = { 3'd0, - _theResult___fst_exp__h365150 == 8'd0 && - guard__h357102 != 2'b0, + _theResult___fst_exp__h364841 == 8'd0 && + guard__h356793 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h365673 == 8'd255 && - _theResult___fst_sfd__h365674 == 23'd0, + _theResult___fst_exp__h365364 == 8'd255 && + _theResult___fst_sfd__h365365 == 23'd0, 1'd0, - _theResult___fst_exp__h365150 != 8'd255 && - guard__h357102 != 2'b0 } ; + _theResult___fst_exp__h364841 != 8'd255 && + guard__h356793 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5968 = ({ 3'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5966 } ^ @@ -25697,15 +25535,15 @@ module mkCore(CLK, 9'h100) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6669 = { 3'd0, - _theResult___fst_exp__h410847 == 8'd0 && - guard__h402799 != 2'b0, + _theResult___fst_exp__h410538 == 8'd0 && + guard__h402490 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h411370 == 8'd255 && - _theResult___fst_sfd__h411371 == 23'd0, + _theResult___fst_exp__h411061 == 8'd255 && + _theResult___fst_sfd__h411062 == 23'd0, 1'd0, - _theResult___fst_exp__h410847 != 8'd255 && - guard__h402799 != 2'b0 } ; + _theResult___fst_exp__h410538 != 8'd255 && + guard__h402490 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7360 = ({ 3'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7358 } ^ @@ -25719,75 +25557,73 @@ module mkCore(CLK, 9'h100) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d8061 = { 3'd0, - _theResult___fst_exp__h456542 == 8'd0 && - guard__h448494 != 2'b0, + _theResult___fst_exp__h456233 == 8'd0 && + guard__h448185 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h457065 == 8'd255 && - _theResult___fst_sfd__h457066 == 23'd0, + _theResult___fst_exp__h456756 == 8'd255 && + _theResult___fst_sfd__h456757 == 23'd0, 1'd0, - _theResult___fst_exp__h456542 != 8'd255 && - guard__h448494 != 2'b0 } ; + _theResult___fst_exp__h456233 != 8'd255 && + guard__h448185 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d11193 = - b__h606117 * b__h606129 ; - assign _0_CONCAT_csrf_debug_int_pend_read__1882_CONCAT_ETC___d12973 = - { 1'd0, - csrf_debug_int_pend, - 2'b0, + b__h605808 * b__h605820 ; + assign _0_CONCAT_csrf_external_int_en_vec_3_read__1850_ETC___d12969 = + { 4'd0, csrf_external_int_en_vec_3 & csrf_external_int_pend_vec_3, 1'd0, csrf_external_int_en_vec_1 & csrf_external_int_pend_vec_1, csrf_external_int_en_vec_0 & csrf_external_int_pend_vec_0 } ; - assign _0_CONCAT_csrf_debug_int_pend_read__1882_CONCAT_ETC___d12978 = - { _0_CONCAT_csrf_debug_int_pend_read__1882_CONCAT_ETC___d12973, + assign _0_CONCAT_csrf_external_int_en_vec_3_read__1850_ETC___d12974 = + { _0_CONCAT_csrf_external_int_en_vec_3_read__1850_ETC___d12969, csrf_timer_int_en_vec_3 & csrf_timer_int_pend_vec_3, 1'd0, csrf_timer_int_en_vec_1 & csrf_timer_int_pend_vec_1, csrf_timer_int_en_vec_0 & csrf_timer_int_pend_vec_0 } ; - assign _0_OR_NOT_fetchStage_pipelines_0_first__2934_BI_ETC___d14093 = + assign _0_OR_NOT_fetchStage_pipelines_0_first__2931_BI_ETC___d14089 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$RDY_nextSpecTag) && - CASE_k71729_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239 ; - assign _0_OR_NOT_fetchStage_pipelines_1_first__2943_BI_ETC___d13994 = + CASE_k71393_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q231 ; + assign _0_OR_NOT_fetchStage_pipelines_1_first__2940_BI_ETC___d13990 = (fetchStage$pipelines_1_first[194:192] != 3'd1 || !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first) && (fetchStage$RDY_pipelines_0_first && fetchStage$pipelines_1_first[194:192] == 3'd1 && - regRenamingTable_rename_0_canRename__3582_AND__ETC___d13667 || - NOT_regRenamingTable_rename_1_canRename__3704__ETC___d13966) ; - assign _0_OR_NOT_fetchStage_pipelines_1_first__2943_BI_ETC___d14185 = + regRenamingTable_rename_0_canRename__3578_AND__ETC___d13663 || + NOT_regRenamingTable_rename_1_canRename__3700__ETC___d13962) ; + assign _0_OR_NOT_fetchStage_pipelines_1_first__2940_BI_ETC___d14181 = (fetchStage$pipelines_1_first[194:192] != 3'd1 || specTagManager$RDY_nextSpecTag) && - CASE_fetchStage_pipelines_0_canDeq__2932_AND_N_ETC__q241 ; + CASE_fetchStage_pipelines_0_canDeq__2929_AND_N_ETC__q233 ; assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d10249 = - sfd__h524302 >> + sfd__h523993 >> _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d10245 ; assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d8764 = - sfd__h485308 >> + sfd__h484999 >> _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d8760 ; assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d9479 = - sfd__h563606 >> + sfd__h563297 >> _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d9475 ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4654 = - sfd__h340778 >> + sfd__h340469 >> (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4650[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4650) ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d6046 = - sfd__h386480 >> + sfd__h386171 >> (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d6042[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d6042) ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7438 = - sfd__h432175 >> + sfd__h431866 >> (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7434[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7434) ; - assign _0b0_CONCAT_csrf_medeleg_15_reg_read__1831_1832_ETC___d14902 = - medeleg_csr__read__h614525[i__h707083] ; - assign _0b0_CONCAT_csrf_mideleg_11_reg_read__1839_1840_ETC___d14884 = - mideleg_csr__read__h614620[i__h707243] ; + assign _0b0_CONCAT_csrf_medeleg_15_reg_read__1831_1832_ETC___d14802 = + medeleg_csr__read__h614216[i__h705763] ; + assign _0b0_CONCAT_csrf_mideleg_11_reg_read__1839_1840_ETC___d14784 = + mideleg_csr__read__h614311[i__h705923] ; assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4107 = 12'd3074 - { 6'd0, @@ -26193,51 +26029,51 @@ module mkCore(CLK, assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10120 = 12'd3970 - { 7'd0, - f2_sfd__h523941[22] ? + f2_sfd__h523632[22] ? 5'd0 : - (f2_sfd__h523941[21] ? + (f2_sfd__h523632[21] ? 5'd1 : - (f2_sfd__h523941[20] ? + (f2_sfd__h523632[20] ? 5'd2 : - (f2_sfd__h523941[19] ? + (f2_sfd__h523632[19] ? 5'd3 : - (f2_sfd__h523941[18] ? + (f2_sfd__h523632[18] ? 5'd4 : - (f2_sfd__h523941[17] ? + (f2_sfd__h523632[17] ? 5'd5 : - (f2_sfd__h523941[16] ? + (f2_sfd__h523632[16] ? 5'd6 : - (f2_sfd__h523941[15] ? + (f2_sfd__h523632[15] ? 5'd7 : - (f2_sfd__h523941[14] ? + (f2_sfd__h523632[14] ? 5'd8 : - (f2_sfd__h523941[13] ? + (f2_sfd__h523632[13] ? 5'd9 : - (f2_sfd__h523941[12] ? + (f2_sfd__h523632[12] ? 5'd10 : - (f2_sfd__h523941[11] ? + (f2_sfd__h523632[11] ? 5'd11 : - (f2_sfd__h523941[10] ? + (f2_sfd__h523632[10] ? 5'd12 : - (f2_sfd__h523941[9] ? + (f2_sfd__h523632[9] ? 5'd13 : - (f2_sfd__h523941[8] ? + (f2_sfd__h523632[8] ? 5'd14 : - (f2_sfd__h523941[7] ? + (f2_sfd__h523632[7] ? 5'd15 : - (f2_sfd__h523941[6] ? + (f2_sfd__h523632[6] ? 5'd16 : - (f2_sfd__h523941[5] ? + (f2_sfd__h523632[5] ? 5'd17 : - (f2_sfd__h523941[4] ? + (f2_sfd__h523632[4] ? 5'd18 : - (f2_sfd__h523941[3] ? + (f2_sfd__h523632[3] ? 5'd19 : - (f2_sfd__h523941[2] ? + (f2_sfd__h523632[2] ? 5'd20 : - (f2_sfd__h523941[1] ? + (f2_sfd__h523632[1] ? 5'd21 : - (f2_sfd__h523941[0] ? + (f2_sfd__h523632[0] ? 5'd22 : 5'd23)))))))))))))))))))))) } ; assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10121 = @@ -26251,51 +26087,51 @@ module mkCore(CLK, assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8620 = 12'd3970 - { 7'd0, - f1_sfd__h484947[22] ? + f1_sfd__h484638[22] ? 5'd0 : - (f1_sfd__h484947[21] ? + (f1_sfd__h484638[21] ? 5'd1 : - (f1_sfd__h484947[20] ? + (f1_sfd__h484638[20] ? 5'd2 : - (f1_sfd__h484947[19] ? + (f1_sfd__h484638[19] ? 5'd3 : - (f1_sfd__h484947[18] ? + (f1_sfd__h484638[18] ? 5'd4 : - (f1_sfd__h484947[17] ? + (f1_sfd__h484638[17] ? 5'd5 : - (f1_sfd__h484947[16] ? + (f1_sfd__h484638[16] ? 5'd6 : - (f1_sfd__h484947[15] ? + (f1_sfd__h484638[15] ? 5'd7 : - (f1_sfd__h484947[14] ? + (f1_sfd__h484638[14] ? 5'd8 : - (f1_sfd__h484947[13] ? + (f1_sfd__h484638[13] ? 5'd9 : - (f1_sfd__h484947[12] ? + (f1_sfd__h484638[12] ? 5'd10 : - (f1_sfd__h484947[11] ? + (f1_sfd__h484638[11] ? 5'd11 : - (f1_sfd__h484947[10] ? + (f1_sfd__h484638[10] ? 5'd12 : - (f1_sfd__h484947[9] ? + (f1_sfd__h484638[9] ? 5'd13 : - (f1_sfd__h484947[8] ? + (f1_sfd__h484638[8] ? 5'd14 : - (f1_sfd__h484947[7] ? + (f1_sfd__h484638[7] ? 5'd15 : - (f1_sfd__h484947[6] ? + (f1_sfd__h484638[6] ? 5'd16 : - (f1_sfd__h484947[5] ? + (f1_sfd__h484638[5] ? 5'd17 : - (f1_sfd__h484947[4] ? + (f1_sfd__h484638[4] ? 5'd18 : - (f1_sfd__h484947[3] ? + (f1_sfd__h484638[3] ? 5'd19 : - (f1_sfd__h484947[2] ? + (f1_sfd__h484638[2] ? 5'd20 : - (f1_sfd__h484947[1] ? + (f1_sfd__h484638[1] ? 5'd21 : - (f1_sfd__h484947[0] ? + (f1_sfd__h484638[0] ? 5'd22 : 5'd23)))))))))))))))))))))) } ; assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8621 = @@ -26309,51 +26145,51 @@ module mkCore(CLK, assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9350 = 12'd3970 - { 7'd0, - f3_sfd__h563245[22] ? + f3_sfd__h562936[22] ? 5'd0 : - (f3_sfd__h563245[21] ? + (f3_sfd__h562936[21] ? 5'd1 : - (f3_sfd__h563245[20] ? + (f3_sfd__h562936[20] ? 5'd2 : - (f3_sfd__h563245[19] ? + (f3_sfd__h562936[19] ? 5'd3 : - (f3_sfd__h563245[18] ? + (f3_sfd__h562936[18] ? 5'd4 : - (f3_sfd__h563245[17] ? + (f3_sfd__h562936[17] ? 5'd5 : - (f3_sfd__h563245[16] ? + (f3_sfd__h562936[16] ? 5'd6 : - (f3_sfd__h563245[15] ? + (f3_sfd__h562936[15] ? 5'd7 : - (f3_sfd__h563245[14] ? + (f3_sfd__h562936[14] ? 5'd8 : - (f3_sfd__h563245[13] ? + (f3_sfd__h562936[13] ? 5'd9 : - (f3_sfd__h563245[12] ? + (f3_sfd__h562936[12] ? 5'd10 : - (f3_sfd__h563245[11] ? + (f3_sfd__h562936[11] ? 5'd11 : - (f3_sfd__h563245[10] ? + (f3_sfd__h562936[10] ? 5'd12 : - (f3_sfd__h563245[9] ? + (f3_sfd__h562936[9] ? 5'd13 : - (f3_sfd__h563245[8] ? + (f3_sfd__h562936[8] ? 5'd14 : - (f3_sfd__h563245[7] ? + (f3_sfd__h562936[7] ? 5'd15 : - (f3_sfd__h563245[6] ? + (f3_sfd__h562936[6] ? 5'd16 : - (f3_sfd__h563245[5] ? + (f3_sfd__h562936[5] ? 5'd17 : - (f3_sfd__h563245[4] ? + (f3_sfd__h562936[4] ? 5'd18 : - (f3_sfd__h563245[3] ? + (f3_sfd__h562936[3] ? 5'd19 : - (f3_sfd__h563245[2] ? + (f3_sfd__h562936[2] ? 5'd20 : - (f3_sfd__h563245[1] ? + (f3_sfd__h562936[1] ? 5'd21 : - (f3_sfd__h563245[0] ? + (f3_sfd__h562936[0] ? 5'd22 : 5'd23)))))))))))))))))))))) } ; assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9351 = @@ -26375,57 +26211,63 @@ module mkCore(CLK, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7431 ; assign _dfoo12 = fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3582_AND__ETC___d14300 || - NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d14388 && - regRenamingTable_rename_1_canRename__3704_AND__ETC___d14398 && + regRenamingTable_rename_0_canRename__3578_AND__ETC___d14296 || + NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d14384 && + regRenamingTable_rename_1_canRename__3700_AND__ETC___d14394 && fetchStage$pipelines_1_first[194:192] == 3'd2 && - NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d14466 && + NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d14462 && fetchStage$pipelines_1_first[199:195] != 5'd14 ; assign _dfoo16 = - k__h671729 == 1'd1 && - fetchStage_pipelines_0_canDeq__2932_AND_NOT_fe_ETC___d14265 || - (fetchStage_pipelines_0_canDeq__2932_AND_NOT_fe_ETC___d14370 || - NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d14383) == + k__h671393 == 1'd1 && + fetchStage_pipelines_0_canDeq__2929_AND_NOT_fe_ETC___d14261 || + (fetchStage_pipelines_0_canDeq__2929_AND_NOT_fe_ETC___d14366 || + NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d14379) == 1'd1 && - NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d14402 ; + NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d14398 ; assign _dfoo18 = - k__h671729 == 1'd0 && - fetchStage_pipelines_0_canDeq__2932_AND_NOT_fe_ETC___d14265 || - (fetchStage_pipelines_0_canDeq__2932_AND_NOT_fe_ETC___d14370 || - NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d14383) == + k__h671393 == 1'd0 && + fetchStage_pipelines_0_canDeq__2929_AND_NOT_fe_ETC___d14261 || + (fetchStage_pipelines_0_canDeq__2929_AND_NOT_fe_ETC___d14366 || + NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d14379) == 1'd0 && - NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d14402 ; + NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d14398 ; assign _dfoo2 = fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3582_AND__ETC___d14342 || - NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d14388 && - regRenamingTable_rename_1_canRename__3704_AND__ETC___d14398 && + regRenamingTable_rename_0_canRename__3578_AND__ETC___d14338 || + NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d14384 && + regRenamingTable_rename_1_canRename__3700_AND__ETC___d14394 && fetchStage$pipelines_1_first[194:192] == 3'd2 && - NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d14466 && + NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d14462 && fetchStage$pipelines_1_first[191:189] != 3'd0 && fetchStage$pipelines_1_first[191:189] != 3'd2 ; assign _dfoo20 = - commitStage_commitTrap_4555_BIT_4_4779_AND_com_ETC___d14844 || - NOT_commitStage_commitTrap_4555_BIT_4_4779_478_ETC___d14881 ; + commitStage_commitTrap_4549_BIT_4_4679_AND_com_ETC___d14744 || + NOT_commitStage_commitTrap_4549_BIT_4_4679_468_ETC___d14781 ; assign _dfoo24 = rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == + 6'd36 || + rob$deqPort_0_deq_data[186:182] == 5'd19 || + rob$deqPort_0_deq_data[186:182] == 5'd20 ; + assign _dfoo26 = + rob$deqPort_0_deq_data[186:182] == 5'd13 && + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd18 || rob$deqPort_0_deq_data[186:182] == 5'd20 ; - assign _dfoo30 = + assign _dfoo32 = rob$deqPort_0_deq_data[186:182] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + (IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd8 || - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd18) || rob$deqPort_0_deq_data[186:182] == 5'd19 ; assign _dfoo7 = fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3582_AND__ETC___d14334 || - NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d14388 && - regRenamingTable_rename_1_canRename__3704_AND__ETC___d14398 && + regRenamingTable_rename_0_canRename__3578_AND__ETC___d14330 || + NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d14384 && + regRenamingTable_rename_1_canRename__3700_AND__ETC___d14394 && fetchStage$pipelines_1_first[194:192] == 3'd2 && - NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d14466 && + NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d14462 && (fetchStage$pipelines_1_first[191:189] == 3'd0 || fetchStage$pipelines_1_first[191:189] == 3'd2) ; assign _dor1coreFix_aluExe_0_bypassWire_2$EN_wset = @@ -26500,1421 +26342,1421 @@ module mkCore(CLK, assign _dor1sbCons$EN_setReady_1_put = WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F || WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; - assign _theResult_____2__h298821 = + assign _theResult_____2__h298513 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3142) ? - next_deqP___1__h299100 : + next_deqP___1__h298792 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP ; - assign _theResult_____2__h306817 = + assign _theResult_____2__h306509 = (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3249) ? - next_deqP___1__h307096 : + next_deqP___1__h306788 : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP ; - assign _theResult_____2__h312811 = + assign _theResult_____2__h312503 = (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3420) ? - next_deqP___1__h313377 : + next_deqP___1__h313069 : coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP ; - assign _theResult_____2__h320665 = + assign _theResult_____2__h320357 = (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3516) ? - next_deqP___1__h321231 : + next_deqP___1__h320923 : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP ; - assign _theResult_____2__h331009 = + assign _theResult_____2__h330701 = (coreFix_memExe_memRespLdQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d3745) ? - next_deqP___1__h331288 : + next_deqP___1__h330980 : coreFix_memExe_memRespLdQ_deqP ; - assign _theResult_____2__h334234 = + assign _theResult_____2__h333926 = (coreFix_memExe_forwardQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d3839) ? - next_deqP___1__h334513 : + next_deqP___1__h334205 : coreFix_memExe_forwardQ_deqP ; - assign _theResult____h348383 = - (value__h349005 == 54'd0) ? sfd__h340778 : 57'd1 ; - assign _theResult____h366022 = + assign _theResult____h348074 = + (value__h348696 == 54'd0) ? sfd__h340469 : 57'd1 ; + assign _theResult____h365713 = ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4650 ^ 12'h800) < 12'd2105) ? - result__h366635 : - _theResult____h348383 ; - assign _theResult____h394082 = - (value__h394702 == 54'd0) ? sfd__h386480 : 57'd1 ; - assign _theResult____h411719 = + result__h366326 : + _theResult____h348074 ; + assign _theResult____h393773 = + (value__h394393 == 54'd0) ? sfd__h386171 : 57'd1 ; + assign _theResult____h411410 = ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d6042 ^ 12'h800) < 12'd2105) ? - result__h412332 : - _theResult____h394082 ; - assign _theResult____h439777 = - (value__h440397 == 54'd0) ? sfd__h432175 : 57'd1 ; - assign _theResult____h457414 = + result__h412023 : + _theResult____h393773 ; + assign _theResult____h439468 = + (value__h440088 == 54'd0) ? sfd__h431866 : 57'd1 ; + assign _theResult____h457105 = ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7434 ^ 12'h800) < 12'd2105) ? - result__h458027 : - _theResult____h439777 ; - assign _theResult____h505675 = + result__h457718 : + _theResult____h439468 ; + assign _theResult____h505366 = ((_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d8760 ^ 12'h800) < 12'd2105) ? - result__h506288 : - ((value__h489891 == 25'd0) ? sfd__h485308 : 57'd1) ; - assign _theResult____h544528 = + result__h505979 : + ((value__h489582 == 25'd0) ? sfd__h484999 : 57'd1) ; + assign _theResult____h544219 = ((_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d10245 ^ 12'h800) < 12'd2105) ? - result__h545141 : - ((value__h528744 == 25'd0) ? sfd__h524302 : 57'd1) ; - assign _theResult____h583832 = + result__h544832 : + ((value__h528435 == 25'd0) ? sfd__h523993 : 57'd1) ; + assign _theResult____h583523 = ((_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d9475 ^ 12'h800) < 12'd2105) ? - result__h584445 : - ((value__h568048 == 25'd0) ? sfd__h563606 : 57'd1) ; - assign _theResult____h655044 = + result__h584136 : + ((value__h567739 == 25'd0) ? sfd__h563297 : 57'd1) ; + assign _theResult____h654708 = (csrf_prv_reg != 2'd3 || csrf_ie_vec_3) ? - enabled_ints___1__h655569 : + enabled_ints___1__h655233 : 16'd0 ; - assign _theResult___exp__h357010 = - sfd__h356586[24] ? - ((_theResult___fst_exp__h356494 == 8'd254) ? + assign _theResult___exp__h356701 = + sfd__h356277[24] ? + ((_theResult___fst_exp__h356185 == 8'd254) ? 8'd255 : - din_inc___2_exp__h383527) : - ((_theResult___fst_exp__h356494 == 8'd0 && - sfd__h356586[24:23] == 2'b01) ? + din_inc___2_exp__h383218) : + ((_theResult___fst_exp__h356185 == 8'd0 && + sfd__h356277[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h356494) ; - assign _theResult___exp__h365592 = - sfd__h365168[24] ? - ((_theResult___fst_exp__h365150 == 8'd254) ? + _theResult___fst_exp__h356185) ; + assign _theResult___exp__h365283 = + sfd__h364859[24] ? + ((_theResult___fst_exp__h364841 == 8'd254) ? 8'd255 : - din_inc___2_exp__h383551) : - ((_theResult___fst_exp__h365150 == 8'd0 && - sfd__h365168[24:23] == 2'b01) ? + din_inc___2_exp__h383242) : + ((_theResult___fst_exp__h364841 == 8'd0 && + sfd__h364859[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h365150) ; - assign _theResult___exp__h374776 = - sfd__h374352[24] ? - ((_theResult___fst_exp__h374260 == 8'd254) ? + _theResult___fst_exp__h364841) ; + assign _theResult___exp__h374467 = + sfd__h374043[24] ? + ((_theResult___fst_exp__h373951 == 8'd254) ? 8'd255 : - din_inc___2_exp__h383581) : - ((_theResult___fst_exp__h374260 == 8'd0 && - sfd__h374352[24:23] == 2'b01) ? + din_inc___2_exp__h383272) : + ((_theResult___fst_exp__h373951 == 8'd0 && + sfd__h374043[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h374260) ; - assign _theResult___exp__h383412 = - sfd__h382964[24] ? - ((_theResult___fst_exp__h382945 == 8'd254) ? + _theResult___fst_exp__h373951) ; + assign _theResult___exp__h383103 = + sfd__h382655[24] ? + ((_theResult___fst_exp__h382636 == 8'd254) ? 8'd255 : - din_inc___2_exp__h383605) : - ((_theResult___fst_exp__h382945 == 8'd0 && - sfd__h382964[24:23] == 2'b01) ? + din_inc___2_exp__h383296) : + ((_theResult___fst_exp__h382636 == 8'd0 && + sfd__h382655[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h382945) ; - assign _theResult___exp__h383514 = + _theResult___fst_exp__h382636) ; + assign _theResult___exp__h383205 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h383505 ; - assign _theResult___exp__h402707 = - sfd__h402283[24] ? - ((_theResult___fst_exp__h402191 == 8'd254) ? + _theResult___fst_exp__h383196 ; + assign _theResult___exp__h402398 = + sfd__h401974[24] ? + ((_theResult___fst_exp__h401882 == 8'd254) ? 8'd255 : - din_inc___2_exp__h429224) : - ((_theResult___fst_exp__h402191 == 8'd0 && - sfd__h402283[24:23] == 2'b01) ? + din_inc___2_exp__h428915) : + ((_theResult___fst_exp__h401882 == 8'd0 && + sfd__h401974[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h402191) ; - assign _theResult___exp__h411289 = - sfd__h410865[24] ? - ((_theResult___fst_exp__h410847 == 8'd254) ? + _theResult___fst_exp__h401882) ; + assign _theResult___exp__h410980 = + sfd__h410556[24] ? + ((_theResult___fst_exp__h410538 == 8'd254) ? 8'd255 : - din_inc___2_exp__h429248) : - ((_theResult___fst_exp__h410847 == 8'd0 && - sfd__h410865[24:23] == 2'b01) ? + din_inc___2_exp__h428939) : + ((_theResult___fst_exp__h410538 == 8'd0 && + sfd__h410556[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h410847) ; - assign _theResult___exp__h420473 = - sfd__h420049[24] ? - ((_theResult___fst_exp__h419957 == 8'd254) ? + _theResult___fst_exp__h410538) ; + assign _theResult___exp__h420164 = + sfd__h419740[24] ? + ((_theResult___fst_exp__h419648 == 8'd254) ? 8'd255 : - din_inc___2_exp__h429278) : - ((_theResult___fst_exp__h419957 == 8'd0 && - sfd__h420049[24:23] == 2'b01) ? + din_inc___2_exp__h428969) : + ((_theResult___fst_exp__h419648 == 8'd0 && + sfd__h419740[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h419957) ; - assign _theResult___exp__h429109 = - sfd__h428661[24] ? - ((_theResult___fst_exp__h428642 == 8'd254) ? + _theResult___fst_exp__h419648) ; + assign _theResult___exp__h428800 = + sfd__h428352[24] ? + ((_theResult___fst_exp__h428333 == 8'd254) ? 8'd255 : - din_inc___2_exp__h429302) : - ((_theResult___fst_exp__h428642 == 8'd0 && - sfd__h428661[24:23] == 2'b01) ? + din_inc___2_exp__h428993) : + ((_theResult___fst_exp__h428333 == 8'd0 && + sfd__h428352[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h428642) ; - assign _theResult___exp__h429211 = + _theResult___fst_exp__h428333) ; + assign _theResult___exp__h428902 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h429202 ; - assign _theResult___exp__h448402 = - sfd__h447978[24] ? - ((_theResult___fst_exp__h447886 == 8'd254) ? + _theResult___fst_exp__h428893 ; + assign _theResult___exp__h448093 = + sfd__h447669[24] ? + ((_theResult___fst_exp__h447577 == 8'd254) ? 8'd255 : - din_inc___2_exp__h474919) : - ((_theResult___fst_exp__h447886 == 8'd0 && - sfd__h447978[24:23] == 2'b01) ? + din_inc___2_exp__h474610) : + ((_theResult___fst_exp__h447577 == 8'd0 && + sfd__h447669[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h447886) ; - assign _theResult___exp__h456984 = - sfd__h456560[24] ? - ((_theResult___fst_exp__h456542 == 8'd254) ? + _theResult___fst_exp__h447577) ; + assign _theResult___exp__h456675 = + sfd__h456251[24] ? + ((_theResult___fst_exp__h456233 == 8'd254) ? 8'd255 : - din_inc___2_exp__h474943) : - ((_theResult___fst_exp__h456542 == 8'd0 && - sfd__h456560[24:23] == 2'b01) ? + din_inc___2_exp__h474634) : + ((_theResult___fst_exp__h456233 == 8'd0 && + sfd__h456251[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h456542) ; - assign _theResult___exp__h466168 = - sfd__h465744[24] ? - ((_theResult___fst_exp__h465652 == 8'd254) ? + _theResult___fst_exp__h456233) ; + assign _theResult___exp__h465859 = + sfd__h465435[24] ? + ((_theResult___fst_exp__h465343 == 8'd254) ? 8'd255 : - din_inc___2_exp__h474973) : - ((_theResult___fst_exp__h465652 == 8'd0 && - sfd__h465744[24:23] == 2'b01) ? + din_inc___2_exp__h474664) : + ((_theResult___fst_exp__h465343 == 8'd0 && + sfd__h465435[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h465652) ; - assign _theResult___exp__h474804 = - sfd__h474356[24] ? - ((_theResult___fst_exp__h474337 == 8'd254) ? + _theResult___fst_exp__h465343) ; + assign _theResult___exp__h474495 = + sfd__h474047[24] ? + ((_theResult___fst_exp__h474028 == 8'd254) ? 8'd255 : - din_inc___2_exp__h474997) : - ((_theResult___fst_exp__h474337 == 8'd0 && - sfd__h474356[24:23] == 2'b01) ? + din_inc___2_exp__h474688) : + ((_theResult___fst_exp__h474028 == 8'd0 && + sfd__h474047[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h474337) ; - assign _theResult___exp__h474906 = + _theResult___fst_exp__h474028) ; + assign _theResult___exp__h474597 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h474897 ; - assign _theResult___exp__h504989 = - sfd__h504352[53] ? - ((_theResult___fst_exp__h504334 == 11'd2046) ? + _theResult___fst_exp__h474588 ; + assign _theResult___exp__h504680 = + sfd__h504043[53] ? + ((_theResult___fst_exp__h504025 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h523584) : - ((_theResult___fst_exp__h504334 == 11'd0 && - sfd__h504352[53:52] == 2'b01) ? + din_inc___2_exp__h523275) : + ((_theResult___fst_exp__h504025 == 11'd0 && + sfd__h504043[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h504334) ; - assign _theResult___exp__h514640 = - sfd__h514003[53] ? - ((_theResult___fst_exp__h513911 == 11'd2046) ? + _theResult___fst_exp__h504025) ; + assign _theResult___exp__h514331 = + sfd__h513694[53] ? + ((_theResult___fst_exp__h513602 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h523619) : - ((_theResult___fst_exp__h513911 == 11'd0 && - sfd__h514003[53:52] == 2'b01) ? + din_inc___2_exp__h523310) : + ((_theResult___fst_exp__h513602 == 11'd0 && + sfd__h513694[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h513911) ; - assign _theResult___exp__h523424 = - sfd__h522763[53] ? - ((_theResult___fst_exp__h522744 == 11'd2046) ? + _theResult___fst_exp__h513602) ; + assign _theResult___exp__h523115 = + sfd__h522454[53] ? + ((_theResult___fst_exp__h522435 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h523645) : - ((_theResult___fst_exp__h522744 == 11'd0 && - sfd__h522763[53:52] == 2'b01) ? + din_inc___2_exp__h523336) : + ((_theResult___fst_exp__h522435 == 11'd0 && + sfd__h522454[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h522744) ; - assign _theResult___exp__h543842 = - sfd__h543205[53] ? - ((_theResult___fst_exp__h543187 == 11'd2046) ? + _theResult___fst_exp__h522435) ; + assign _theResult___exp__h543533 = + sfd__h542896[53] ? + ((_theResult___fst_exp__h542878 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h562437) : - ((_theResult___fst_exp__h543187 == 11'd0 && - sfd__h543205[53:52] == 2'b01) ? + din_inc___2_exp__h562128) : + ((_theResult___fst_exp__h542878 == 11'd0 && + sfd__h542896[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h543187) ; - assign _theResult___exp__h553493 = - sfd__h552856[53] ? - ((_theResult___fst_exp__h552764 == 11'd2046) ? + _theResult___fst_exp__h542878) ; + assign _theResult___exp__h553184 = + sfd__h552547[53] ? + ((_theResult___fst_exp__h552455 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h562472) : - ((_theResult___fst_exp__h552764 == 11'd0 && - sfd__h552856[53:52] == 2'b01) ? + din_inc___2_exp__h562163) : + ((_theResult___fst_exp__h552455 == 11'd0 && + sfd__h552547[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h552764) ; - assign _theResult___exp__h562277 = - sfd__h561616[53] ? - ((_theResult___fst_exp__h561597 == 11'd2046) ? + _theResult___fst_exp__h552455) ; + assign _theResult___exp__h561968 = + sfd__h561307[53] ? + ((_theResult___fst_exp__h561288 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h562498) : - ((_theResult___fst_exp__h561597 == 11'd0 && - sfd__h561616[53:52] == 2'b01) ? + din_inc___2_exp__h562189) : + ((_theResult___fst_exp__h561288 == 11'd0 && + sfd__h561307[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h561597) ; - assign _theResult___exp__h583146 = - sfd__h582509[53] ? - ((_theResult___fst_exp__h582491 == 11'd2046) ? + _theResult___fst_exp__h561288) ; + assign _theResult___exp__h582837 = + sfd__h582200[53] ? + ((_theResult___fst_exp__h582182 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h601741) : - ((_theResult___fst_exp__h582491 == 11'd0 && - sfd__h582509[53:52] == 2'b01) ? + din_inc___2_exp__h601432) : + ((_theResult___fst_exp__h582182 == 11'd0 && + sfd__h582200[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h582491) ; - assign _theResult___exp__h592797 = - sfd__h592160[53] ? - ((_theResult___fst_exp__h592068 == 11'd2046) ? + _theResult___fst_exp__h582182) ; + assign _theResult___exp__h592488 = + sfd__h591851[53] ? + ((_theResult___fst_exp__h591759 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h601776) : - ((_theResult___fst_exp__h592068 == 11'd0 && - sfd__h592160[53:52] == 2'b01) ? + din_inc___2_exp__h601467) : + ((_theResult___fst_exp__h591759 == 11'd0 && + sfd__h591851[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h592068) ; - assign _theResult___exp__h601581 = - sfd__h600920[53] ? - ((_theResult___fst_exp__h600901 == 11'd2046) ? + _theResult___fst_exp__h591759) ; + assign _theResult___exp__h601272 = + sfd__h600611[53] ? + ((_theResult___fst_exp__h600592 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h601802) : - ((_theResult___fst_exp__h600901 == 11'd0 && - sfd__h600920[53:52] == 2'b01) ? + din_inc___2_exp__h601493) : + ((_theResult___fst_exp__h600592 == 11'd0 && + sfd__h600611[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h600901) ; - assign _theResult___fst__h606340 = - a__h605792[63] ? a___1__h606345 : a__h605792 ; - assign _theResult___fst_exp__h356494 = - _theResult____h348383[56] ? + _theResult___fst_exp__h600592) ; + assign _theResult___fst__h606031 = + a__h605483[63] ? a___1__h606036 : a__h605483 ; + assign _theResult___fst_exp__h356185 = + _theResult____h348074[56] ? 8'd2 : - _theResult___fst_exp__h356568 ; - assign _theResult___fst_exp__h356559 = + _theResult___fst_exp__h356259 ; + assign _theResult___fst_exp__h356250 = 8'd0 - { 2'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4343 } ; - assign _theResult___fst_exp__h356565 = - (!_theResult____h348383[56] && !_theResult____h348383[55] && - !_theResult____h348383[54] && - !_theResult____h348383[53] && - !_theResult____h348383[52] && - !_theResult____h348383[51] && - !_theResult____h348383[50] && - !_theResult____h348383[49] && - !_theResult____h348383[48] && - !_theResult____h348383[47] && - !_theResult____h348383[46] && - !_theResult____h348383[45] && - !_theResult____h348383[44] && - !_theResult____h348383[43] && - !_theResult____h348383[42] && - !_theResult____h348383[41] && - !_theResult____h348383[40] && - !_theResult____h348383[39] && - !_theResult____h348383[38] && - !_theResult____h348383[37] && - !_theResult____h348383[36] && - !_theResult____h348383[35] && - !_theResult____h348383[34] && - !_theResult____h348383[33] && - !_theResult____h348383[32] && - !_theResult____h348383[31] && - !_theResult____h348383[30] && - !_theResult____h348383[29] && - !_theResult____h348383[28] && - !_theResult____h348383[27] && - !_theResult____h348383[26] && - !_theResult____h348383[25] && - !_theResult____h348383[24] && - !_theResult____h348383[23] && - !_theResult____h348383[22] && - !_theResult____h348383[21] && - !_theResult____h348383[20] && - !_theResult____h348383[19] && - !_theResult____h348383[18] && - !_theResult____h348383[17] && - !_theResult____h348383[16] && - !_theResult____h348383[15] && - !_theResult____h348383[14] && - !_theResult____h348383[13] && - !_theResult____h348383[12] && - !_theResult____h348383[11] && - !_theResult____h348383[10] && - !_theResult____h348383[9] && - !_theResult____h348383[8] && - !_theResult____h348383[7] && - !_theResult____h348383[6] && - !_theResult____h348383[5] && - !_theResult____h348383[4] && - !_theResult____h348383[3] && - !_theResult____h348383[2] && - !_theResult____h348383[1] && - !_theResult____h348383[0] || + assign _theResult___fst_exp__h356256 = + (!_theResult____h348074[56] && !_theResult____h348074[55] && + !_theResult____h348074[54] && + !_theResult____h348074[53] && + !_theResult____h348074[52] && + !_theResult____h348074[51] && + !_theResult____h348074[50] && + !_theResult____h348074[49] && + !_theResult____h348074[48] && + !_theResult____h348074[47] && + !_theResult____h348074[46] && + !_theResult____h348074[45] && + !_theResult____h348074[44] && + !_theResult____h348074[43] && + !_theResult____h348074[42] && + !_theResult____h348074[41] && + !_theResult____h348074[40] && + !_theResult____h348074[39] && + !_theResult____h348074[38] && + !_theResult____h348074[37] && + !_theResult____h348074[36] && + !_theResult____h348074[35] && + !_theResult____h348074[34] && + !_theResult____h348074[33] && + !_theResult____h348074[32] && + !_theResult____h348074[31] && + !_theResult____h348074[30] && + !_theResult____h348074[29] && + !_theResult____h348074[28] && + !_theResult____h348074[27] && + !_theResult____h348074[26] && + !_theResult____h348074[25] && + !_theResult____h348074[24] && + !_theResult____h348074[23] && + !_theResult____h348074[22] && + !_theResult____h348074[21] && + !_theResult____h348074[20] && + !_theResult____h348074[19] && + !_theResult____h348074[18] && + !_theResult____h348074[17] && + !_theResult____h348074[16] && + !_theResult____h348074[15] && + !_theResult____h348074[14] && + !_theResult____h348074[13] && + !_theResult____h348074[12] && + !_theResult____h348074[11] && + !_theResult____h348074[10] && + !_theResult____h348074[9] && + !_theResult____h348074[8] && + !_theResult____h348074[7] && + !_theResult____h348074[6] && + !_theResult____h348074[5] && + !_theResult____h348074[4] && + !_theResult____h348074[3] && + !_theResult____h348074[2] && + !_theResult____h348074[1] && + !_theResult____h348074[0] || !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d4345) ? 8'd0 : - _theResult___fst_exp__h356559 ; - assign _theResult___fst_exp__h356568 = - (!_theResult____h348383[56] && _theResult____h348383[55]) ? + _theResult___fst_exp__h356250 ; + assign _theResult___fst_exp__h356259 = + (!_theResult____h348074[56] && _theResult____h348074[55]) ? 8'd1 : - _theResult___fst_exp__h356565 ; - assign _theResult___fst_exp__h357091 = - (_theResult___fst_exp__h356494 == 8'd255) ? - _theResult___fst_exp__h356494 : - _theResult___fst_exp__h357088 ; - assign _theResult___fst_exp__h365141 = + _theResult___fst_exp__h356256 ; + assign _theResult___fst_exp__h356782 = + (_theResult___fst_exp__h356185 == 8'd255) ? + _theResult___fst_exp__h356185 : + _theResult___fst_exp__h356779 ; + assign _theResult___fst_exp__h364832 = 8'd129 - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4574 } ; - assign _theResult___fst_exp__h365147 = + assign _theResult___fst_exp__h364838 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4519 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4576) ? 8'd0 : - _theResult___fst_exp__h365141 ; - assign _theResult___fst_exp__h365150 = + _theResult___fst_exp__h364832 ; + assign _theResult___fst_exp__h364841 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h365147 : + _theResult___fst_exp__h364838 : 8'd129 ; - assign _theResult___fst_exp__h365673 = - (_theResult___fst_exp__h365150 == 8'd255) ? - _theResult___fst_exp__h365150 : - _theResult___fst_exp__h365670 ; - assign _theResult___fst_exp__h374260 = - _theResult____h366022[56] ? + assign _theResult___fst_exp__h365364 = + (_theResult___fst_exp__h364841 == 8'd255) ? + _theResult___fst_exp__h364841 : + _theResult___fst_exp__h365361 ; + assign _theResult___fst_exp__h373951 = + _theResult____h365713[56] ? 8'd2 : - _theResult___fst_exp__h374334 ; - assign _theResult___fst_exp__h374325 = + _theResult___fst_exp__h374025 ; + assign _theResult___fst_exp__h374016 = 8'd0 - { 2'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4894 } ; - assign _theResult___fst_exp__h374331 = - (!_theResult____h366022[56] && !_theResult____h366022[55] && - !_theResult____h366022[54] && - !_theResult____h366022[53] && - !_theResult____h366022[52] && - !_theResult____h366022[51] && - !_theResult____h366022[50] && - !_theResult____h366022[49] && - !_theResult____h366022[48] && - !_theResult____h366022[47] && - !_theResult____h366022[46] && - !_theResult____h366022[45] && - !_theResult____h366022[44] && - !_theResult____h366022[43] && - !_theResult____h366022[42] && - !_theResult____h366022[41] && - !_theResult____h366022[40] && - !_theResult____h366022[39] && - !_theResult____h366022[38] && - !_theResult____h366022[37] && - !_theResult____h366022[36] && - !_theResult____h366022[35] && - !_theResult____h366022[34] && - !_theResult____h366022[33] && - !_theResult____h366022[32] && - !_theResult____h366022[31] && - !_theResult____h366022[30] && - !_theResult____h366022[29] && - !_theResult____h366022[28] && - !_theResult____h366022[27] && - !_theResult____h366022[26] && - !_theResult____h366022[25] && - !_theResult____h366022[24] && - !_theResult____h366022[23] && - !_theResult____h366022[22] && - !_theResult____h366022[21] && - !_theResult____h366022[20] && - !_theResult____h366022[19] && - !_theResult____h366022[18] && - !_theResult____h366022[17] && - !_theResult____h366022[16] && - !_theResult____h366022[15] && - !_theResult____h366022[14] && - !_theResult____h366022[13] && - !_theResult____h366022[12] && - !_theResult____h366022[11] && - !_theResult____h366022[10] && - !_theResult____h366022[9] && - !_theResult____h366022[8] && - !_theResult____h366022[7] && - !_theResult____h366022[6] && - !_theResult____h366022[5] && - !_theResult____h366022[4] && - !_theResult____h366022[3] && - !_theResult____h366022[2] && - !_theResult____h366022[1] && - !_theResult____h366022[0] || + assign _theResult___fst_exp__h374022 = + (!_theResult____h365713[56] && !_theResult____h365713[55] && + !_theResult____h365713[54] && + !_theResult____h365713[53] && + !_theResult____h365713[52] && + !_theResult____h365713[51] && + !_theResult____h365713[50] && + !_theResult____h365713[49] && + !_theResult____h365713[48] && + !_theResult____h365713[47] && + !_theResult____h365713[46] && + !_theResult____h365713[45] && + !_theResult____h365713[44] && + !_theResult____h365713[43] && + !_theResult____h365713[42] && + !_theResult____h365713[41] && + !_theResult____h365713[40] && + !_theResult____h365713[39] && + !_theResult____h365713[38] && + !_theResult____h365713[37] && + !_theResult____h365713[36] && + !_theResult____h365713[35] && + !_theResult____h365713[34] && + !_theResult____h365713[33] && + !_theResult____h365713[32] && + !_theResult____h365713[31] && + !_theResult____h365713[30] && + !_theResult____h365713[29] && + !_theResult____h365713[28] && + !_theResult____h365713[27] && + !_theResult____h365713[26] && + !_theResult____h365713[25] && + !_theResult____h365713[24] && + !_theResult____h365713[23] && + !_theResult____h365713[22] && + !_theResult____h365713[21] && + !_theResult____h365713[20] && + !_theResult____h365713[19] && + !_theResult____h365713[18] && + !_theResult____h365713[17] && + !_theResult____h365713[16] && + !_theResult____h365713[15] && + !_theResult____h365713[14] && + !_theResult____h365713[13] && + !_theResult____h365713[12] && + !_theResult____h365713[11] && + !_theResult____h365713[10] && + !_theResult____h365713[9] && + !_theResult____h365713[8] && + !_theResult____h365713[7] && + !_theResult____h365713[6] && + !_theResult____h365713[5] && + !_theResult____h365713[4] && + !_theResult____h365713[3] && + !_theResult____h365713[2] && + !_theResult____h365713[1] && + !_theResult____h365713[0] || !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d4896) ? 8'd0 : - _theResult___fst_exp__h374325 ; - assign _theResult___fst_exp__h374334 = - (!_theResult____h366022[56] && _theResult____h366022[55]) ? + _theResult___fst_exp__h374016 ; + assign _theResult___fst_exp__h374025 = + (!_theResult____h365713[56] && _theResult____h365713[55]) ? 8'd1 : - _theResult___fst_exp__h374331 ; - assign _theResult___fst_exp__h374857 = - (_theResult___fst_exp__h374260 == 8'd255) ? - _theResult___fst_exp__h374260 : - _theResult___fst_exp__h374854 ; - assign _theResult___fst_exp__h382897 = - (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q38[7:0] == + _theResult___fst_exp__h374022 ; + assign _theResult___fst_exp__h374548 = + (_theResult___fst_exp__h373951 == 8'd255) ? + _theResult___fst_exp__h373951 : + _theResult___fst_exp__h374545 ; + assign _theResult___fst_exp__h382588 = + (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q30[7:0] == 8'd0) ? 8'd1 : - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q38[7:0] ; - assign _theResult___fst_exp__h382936 = - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q38[7:0] - + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q30[7:0] ; + assign _theResult___fst_exp__h382627 = + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q30[7:0] - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4574 } ; - assign _theResult___fst_exp__h382942 = + assign _theResult___fst_exp__h382633 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4519 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4969) ? 8'd0 : - _theResult___fst_exp__h382936 ; - assign _theResult___fst_exp__h382945 = + _theResult___fst_exp__h382627 ; + assign _theResult___fst_exp__h382636 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h382942 : - _theResult___fst_exp__h382897 ; - assign _theResult___fst_exp__h383493 = - (_theResult___fst_exp__h382945 == 8'd255) ? - _theResult___fst_exp__h382945 : - _theResult___fst_exp__h383490 ; - assign _theResult___fst_exp__h383502 = + _theResult___fst_exp__h382633 : + _theResult___fst_exp__h382588 ; + assign _theResult___fst_exp__h383184 = + (_theResult___fst_exp__h382636 == 8'd255) ? + _theResult___fst_exp__h382636 : + _theResult___fst_exp__h383181 ; + assign _theResult___fst_exp__h383193 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4108 ? - _theResult___snd_fst_exp__h365676 : - _theResult___fst_exp__h348365) : + _theResult___snd_fst_exp__h365367 : + _theResult___fst_exp__h348056) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4648 ? - _theResult___snd_fst_exp__h383496 : - _theResult___fst_exp__h348365) ; - assign _theResult___fst_exp__h383505 = + _theResult___snd_fst_exp__h383187 : + _theResult___fst_exp__h348056) ; + assign _theResult___fst_exp__h383196 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == 52'd0) ? 8'd0 : - _theResult___fst_exp__h383502 ; - assign _theResult___fst_exp__h402191 = - _theResult____h394082[56] ? + _theResult___fst_exp__h383193 ; + assign _theResult___fst_exp__h401882 = + _theResult____h393773[56] ? 8'd2 : - _theResult___fst_exp__h402265 ; - assign _theResult___fst_exp__h402256 = + _theResult___fst_exp__h401956 ; + assign _theResult___fst_exp__h401947 = 8'd0 - { 2'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5735 } ; - assign _theResult___fst_exp__h402262 = - (!_theResult____h394082[56] && !_theResult____h394082[55] && - !_theResult____h394082[54] && - !_theResult____h394082[53] && - !_theResult____h394082[52] && - !_theResult____h394082[51] && - !_theResult____h394082[50] && - !_theResult____h394082[49] && - !_theResult____h394082[48] && - !_theResult____h394082[47] && - !_theResult____h394082[46] && - !_theResult____h394082[45] && - !_theResult____h394082[44] && - !_theResult____h394082[43] && - !_theResult____h394082[42] && - !_theResult____h394082[41] && - !_theResult____h394082[40] && - !_theResult____h394082[39] && - !_theResult____h394082[38] && - !_theResult____h394082[37] && - !_theResult____h394082[36] && - !_theResult____h394082[35] && - !_theResult____h394082[34] && - !_theResult____h394082[33] && - !_theResult____h394082[32] && - !_theResult____h394082[31] && - !_theResult____h394082[30] && - !_theResult____h394082[29] && - !_theResult____h394082[28] && - !_theResult____h394082[27] && - !_theResult____h394082[26] && - !_theResult____h394082[25] && - !_theResult____h394082[24] && - !_theResult____h394082[23] && - !_theResult____h394082[22] && - !_theResult____h394082[21] && - !_theResult____h394082[20] && - !_theResult____h394082[19] && - !_theResult____h394082[18] && - !_theResult____h394082[17] && - !_theResult____h394082[16] && - !_theResult____h394082[15] && - !_theResult____h394082[14] && - !_theResult____h394082[13] && - !_theResult____h394082[12] && - !_theResult____h394082[11] && - !_theResult____h394082[10] && - !_theResult____h394082[9] && - !_theResult____h394082[8] && - !_theResult____h394082[7] && - !_theResult____h394082[6] && - !_theResult____h394082[5] && - !_theResult____h394082[4] && - !_theResult____h394082[3] && - !_theResult____h394082[2] && - !_theResult____h394082[1] && - !_theResult____h394082[0] || + assign _theResult___fst_exp__h401953 = + (!_theResult____h393773[56] && !_theResult____h393773[55] && + !_theResult____h393773[54] && + !_theResult____h393773[53] && + !_theResult____h393773[52] && + !_theResult____h393773[51] && + !_theResult____h393773[50] && + !_theResult____h393773[49] && + !_theResult____h393773[48] && + !_theResult____h393773[47] && + !_theResult____h393773[46] && + !_theResult____h393773[45] && + !_theResult____h393773[44] && + !_theResult____h393773[43] && + !_theResult____h393773[42] && + !_theResult____h393773[41] && + !_theResult____h393773[40] && + !_theResult____h393773[39] && + !_theResult____h393773[38] && + !_theResult____h393773[37] && + !_theResult____h393773[36] && + !_theResult____h393773[35] && + !_theResult____h393773[34] && + !_theResult____h393773[33] && + !_theResult____h393773[32] && + !_theResult____h393773[31] && + !_theResult____h393773[30] && + !_theResult____h393773[29] && + !_theResult____h393773[28] && + !_theResult____h393773[27] && + !_theResult____h393773[26] && + !_theResult____h393773[25] && + !_theResult____h393773[24] && + !_theResult____h393773[23] && + !_theResult____h393773[22] && + !_theResult____h393773[21] && + !_theResult____h393773[20] && + !_theResult____h393773[19] && + !_theResult____h393773[18] && + !_theResult____h393773[17] && + !_theResult____h393773[16] && + !_theResult____h393773[15] && + !_theResult____h393773[14] && + !_theResult____h393773[13] && + !_theResult____h393773[12] && + !_theResult____h393773[11] && + !_theResult____h393773[10] && + !_theResult____h393773[9] && + !_theResult____h393773[8] && + !_theResult____h393773[7] && + !_theResult____h393773[6] && + !_theResult____h393773[5] && + !_theResult____h393773[4] && + !_theResult____h393773[3] && + !_theResult____h393773[2] && + !_theResult____h393773[1] && + !_theResult____h393773[0] || !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5737) ? 8'd0 : - _theResult___fst_exp__h402256 ; - assign _theResult___fst_exp__h402265 = - (!_theResult____h394082[56] && _theResult____h394082[55]) ? + _theResult___fst_exp__h401947 ; + assign _theResult___fst_exp__h401956 = + (!_theResult____h393773[56] && _theResult____h393773[55]) ? 8'd1 : - _theResult___fst_exp__h402262 ; - assign _theResult___fst_exp__h402788 = - (_theResult___fst_exp__h402191 == 8'd255) ? - _theResult___fst_exp__h402191 : - _theResult___fst_exp__h402785 ; - assign _theResult___fst_exp__h410838 = + _theResult___fst_exp__h401953 ; + assign _theResult___fst_exp__h402479 = + (_theResult___fst_exp__h401882 == 8'd255) ? + _theResult___fst_exp__h401882 : + _theResult___fst_exp__h402476 ; + assign _theResult___fst_exp__h410529 = 8'd129 - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5966 } ; - assign _theResult___fst_exp__h410844 = + assign _theResult___fst_exp__h410535 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5911 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5968) ? 8'd0 : - _theResult___fst_exp__h410838 ; - assign _theResult___fst_exp__h410847 = + _theResult___fst_exp__h410529 ; + assign _theResult___fst_exp__h410538 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h410844 : + _theResult___fst_exp__h410535 : 8'd129 ; - assign _theResult___fst_exp__h411370 = - (_theResult___fst_exp__h410847 == 8'd255) ? - _theResult___fst_exp__h410847 : - _theResult___fst_exp__h411367 ; - assign _theResult___fst_exp__h419957 = - _theResult____h411719[56] ? + assign _theResult___fst_exp__h411061 = + (_theResult___fst_exp__h410538 == 8'd255) ? + _theResult___fst_exp__h410538 : + _theResult___fst_exp__h411058 ; + assign _theResult___fst_exp__h419648 = + _theResult____h411410[56] ? 8'd2 : - _theResult___fst_exp__h420031 ; - assign _theResult___fst_exp__h420022 = + _theResult___fst_exp__h419722 ; + assign _theResult___fst_exp__h419713 = 8'd0 - { 2'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6286 } ; - assign _theResult___fst_exp__h420028 = - (!_theResult____h411719[56] && !_theResult____h411719[55] && - !_theResult____h411719[54] && - !_theResult____h411719[53] && - !_theResult____h411719[52] && - !_theResult____h411719[51] && - !_theResult____h411719[50] && - !_theResult____h411719[49] && - !_theResult____h411719[48] && - !_theResult____h411719[47] && - !_theResult____h411719[46] && - !_theResult____h411719[45] && - !_theResult____h411719[44] && - !_theResult____h411719[43] && - !_theResult____h411719[42] && - !_theResult____h411719[41] && - !_theResult____h411719[40] && - !_theResult____h411719[39] && - !_theResult____h411719[38] && - !_theResult____h411719[37] && - !_theResult____h411719[36] && - !_theResult____h411719[35] && - !_theResult____h411719[34] && - !_theResult____h411719[33] && - !_theResult____h411719[32] && - !_theResult____h411719[31] && - !_theResult____h411719[30] && - !_theResult____h411719[29] && - !_theResult____h411719[28] && - !_theResult____h411719[27] && - !_theResult____h411719[26] && - !_theResult____h411719[25] && - !_theResult____h411719[24] && - !_theResult____h411719[23] && - !_theResult____h411719[22] && - !_theResult____h411719[21] && - !_theResult____h411719[20] && - !_theResult____h411719[19] && - !_theResult____h411719[18] && - !_theResult____h411719[17] && - !_theResult____h411719[16] && - !_theResult____h411719[15] && - !_theResult____h411719[14] && - !_theResult____h411719[13] && - !_theResult____h411719[12] && - !_theResult____h411719[11] && - !_theResult____h411719[10] && - !_theResult____h411719[9] && - !_theResult____h411719[8] && - !_theResult____h411719[7] && - !_theResult____h411719[6] && - !_theResult____h411719[5] && - !_theResult____h411719[4] && - !_theResult____h411719[3] && - !_theResult____h411719[2] && - !_theResult____h411719[1] && - !_theResult____h411719[0] || + assign _theResult___fst_exp__h419719 = + (!_theResult____h411410[56] && !_theResult____h411410[55] && + !_theResult____h411410[54] && + !_theResult____h411410[53] && + !_theResult____h411410[52] && + !_theResult____h411410[51] && + !_theResult____h411410[50] && + !_theResult____h411410[49] && + !_theResult____h411410[48] && + !_theResult____h411410[47] && + !_theResult____h411410[46] && + !_theResult____h411410[45] && + !_theResult____h411410[44] && + !_theResult____h411410[43] && + !_theResult____h411410[42] && + !_theResult____h411410[41] && + !_theResult____h411410[40] && + !_theResult____h411410[39] && + !_theResult____h411410[38] && + !_theResult____h411410[37] && + !_theResult____h411410[36] && + !_theResult____h411410[35] && + !_theResult____h411410[34] && + !_theResult____h411410[33] && + !_theResult____h411410[32] && + !_theResult____h411410[31] && + !_theResult____h411410[30] && + !_theResult____h411410[29] && + !_theResult____h411410[28] && + !_theResult____h411410[27] && + !_theResult____h411410[26] && + !_theResult____h411410[25] && + !_theResult____h411410[24] && + !_theResult____h411410[23] && + !_theResult____h411410[22] && + !_theResult____h411410[21] && + !_theResult____h411410[20] && + !_theResult____h411410[19] && + !_theResult____h411410[18] && + !_theResult____h411410[17] && + !_theResult____h411410[16] && + !_theResult____h411410[15] && + !_theResult____h411410[14] && + !_theResult____h411410[13] && + !_theResult____h411410[12] && + !_theResult____h411410[11] && + !_theResult____h411410[10] && + !_theResult____h411410[9] && + !_theResult____h411410[8] && + !_theResult____h411410[7] && + !_theResult____h411410[6] && + !_theResult____h411410[5] && + !_theResult____h411410[4] && + !_theResult____h411410[3] && + !_theResult____h411410[2] && + !_theResult____h411410[1] && + !_theResult____h411410[0] || !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6288) ? 8'd0 : - _theResult___fst_exp__h420022 ; - assign _theResult___fst_exp__h420031 = - (!_theResult____h411719[56] && _theResult____h411719[55]) ? + _theResult___fst_exp__h419713 ; + assign _theResult___fst_exp__h419722 = + (!_theResult____h411410[56] && _theResult____h411410[55]) ? 8'd1 : - _theResult___fst_exp__h420028 ; - assign _theResult___fst_exp__h420554 = - (_theResult___fst_exp__h419957 == 8'd255) ? - _theResult___fst_exp__h419957 : - _theResult___fst_exp__h420551 ; - assign _theResult___fst_exp__h428594 = - (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q73[7:0] == + _theResult___fst_exp__h419719 ; + assign _theResult___fst_exp__h420245 = + (_theResult___fst_exp__h419648 == 8'd255) ? + _theResult___fst_exp__h419648 : + _theResult___fst_exp__h420242 ; + assign _theResult___fst_exp__h428285 = + (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q65[7:0] == 8'd0) ? 8'd1 : - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q73[7:0] ; - assign _theResult___fst_exp__h428633 = - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q73[7:0] - + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q65[7:0] ; + assign _theResult___fst_exp__h428324 = + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q65[7:0] - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5966 } ; - assign _theResult___fst_exp__h428639 = + assign _theResult___fst_exp__h428330 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5911 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6361) ? 8'd0 : - _theResult___fst_exp__h428633 ; - assign _theResult___fst_exp__h428642 = + _theResult___fst_exp__h428324 ; + assign _theResult___fst_exp__h428333 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h428639 : - _theResult___fst_exp__h428594 ; - assign _theResult___fst_exp__h429190 = - (_theResult___fst_exp__h428642 == 8'd255) ? - _theResult___fst_exp__h428642 : - _theResult___fst_exp__h429187 ; - assign _theResult___fst_exp__h429199 = + _theResult___fst_exp__h428330 : + _theResult___fst_exp__h428285 ; + assign _theResult___fst_exp__h428881 = + (_theResult___fst_exp__h428333 == 8'd255) ? + _theResult___fst_exp__h428333 : + _theResult___fst_exp__h428878 ; + assign _theResult___fst_exp__h428890 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5500 ? - _theResult___snd_fst_exp__h411373 : - _theResult___fst_exp__h394064) : + _theResult___snd_fst_exp__h411064 : + _theResult___fst_exp__h393755) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6040 ? - _theResult___snd_fst_exp__h429193 : - _theResult___fst_exp__h394064) ; - assign _theResult___fst_exp__h429202 = + _theResult___snd_fst_exp__h428884 : + _theResult___fst_exp__h393755) ; + assign _theResult___fst_exp__h428893 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == 52'd0) ? 8'd0 : - _theResult___fst_exp__h429199 ; - assign _theResult___fst_exp__h447886 = - _theResult____h439777[56] ? + _theResult___fst_exp__h428890 ; + assign _theResult___fst_exp__h447577 = + _theResult____h439468[56] ? 8'd2 : - _theResult___fst_exp__h447960 ; - assign _theResult___fst_exp__h447951 = + _theResult___fst_exp__h447651 ; + assign _theResult___fst_exp__h447642 = 8'd0 - { 2'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7127 } ; - assign _theResult___fst_exp__h447957 = - (!_theResult____h439777[56] && !_theResult____h439777[55] && - !_theResult____h439777[54] && - !_theResult____h439777[53] && - !_theResult____h439777[52] && - !_theResult____h439777[51] && - !_theResult____h439777[50] && - !_theResult____h439777[49] && - !_theResult____h439777[48] && - !_theResult____h439777[47] && - !_theResult____h439777[46] && - !_theResult____h439777[45] && - !_theResult____h439777[44] && - !_theResult____h439777[43] && - !_theResult____h439777[42] && - !_theResult____h439777[41] && - !_theResult____h439777[40] && - !_theResult____h439777[39] && - !_theResult____h439777[38] && - !_theResult____h439777[37] && - !_theResult____h439777[36] && - !_theResult____h439777[35] && - !_theResult____h439777[34] && - !_theResult____h439777[33] && - !_theResult____h439777[32] && - !_theResult____h439777[31] && - !_theResult____h439777[30] && - !_theResult____h439777[29] && - !_theResult____h439777[28] && - !_theResult____h439777[27] && - !_theResult____h439777[26] && - !_theResult____h439777[25] && - !_theResult____h439777[24] && - !_theResult____h439777[23] && - !_theResult____h439777[22] && - !_theResult____h439777[21] && - !_theResult____h439777[20] && - !_theResult____h439777[19] && - !_theResult____h439777[18] && - !_theResult____h439777[17] && - !_theResult____h439777[16] && - !_theResult____h439777[15] && - !_theResult____h439777[14] && - !_theResult____h439777[13] && - !_theResult____h439777[12] && - !_theResult____h439777[11] && - !_theResult____h439777[10] && - !_theResult____h439777[9] && - !_theResult____h439777[8] && - !_theResult____h439777[7] && - !_theResult____h439777[6] && - !_theResult____h439777[5] && - !_theResult____h439777[4] && - !_theResult____h439777[3] && - !_theResult____h439777[2] && - !_theResult____h439777[1] && - !_theResult____h439777[0] || + assign _theResult___fst_exp__h447648 = + (!_theResult____h439468[56] && !_theResult____h439468[55] && + !_theResult____h439468[54] && + !_theResult____h439468[53] && + !_theResult____h439468[52] && + !_theResult____h439468[51] && + !_theResult____h439468[50] && + !_theResult____h439468[49] && + !_theResult____h439468[48] && + !_theResult____h439468[47] && + !_theResult____h439468[46] && + !_theResult____h439468[45] && + !_theResult____h439468[44] && + !_theResult____h439468[43] && + !_theResult____h439468[42] && + !_theResult____h439468[41] && + !_theResult____h439468[40] && + !_theResult____h439468[39] && + !_theResult____h439468[38] && + !_theResult____h439468[37] && + !_theResult____h439468[36] && + !_theResult____h439468[35] && + !_theResult____h439468[34] && + !_theResult____h439468[33] && + !_theResult____h439468[32] && + !_theResult____h439468[31] && + !_theResult____h439468[30] && + !_theResult____h439468[29] && + !_theResult____h439468[28] && + !_theResult____h439468[27] && + !_theResult____h439468[26] && + !_theResult____h439468[25] && + !_theResult____h439468[24] && + !_theResult____h439468[23] && + !_theResult____h439468[22] && + !_theResult____h439468[21] && + !_theResult____h439468[20] && + !_theResult____h439468[19] && + !_theResult____h439468[18] && + !_theResult____h439468[17] && + !_theResult____h439468[16] && + !_theResult____h439468[15] && + !_theResult____h439468[14] && + !_theResult____h439468[13] && + !_theResult____h439468[12] && + !_theResult____h439468[11] && + !_theResult____h439468[10] && + !_theResult____h439468[9] && + !_theResult____h439468[8] && + !_theResult____h439468[7] && + !_theResult____h439468[6] && + !_theResult____h439468[5] && + !_theResult____h439468[4] && + !_theResult____h439468[3] && + !_theResult____h439468[2] && + !_theResult____h439468[1] && + !_theResult____h439468[0] || !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7129) ? 8'd0 : - _theResult___fst_exp__h447951 ; - assign _theResult___fst_exp__h447960 = - (!_theResult____h439777[56] && _theResult____h439777[55]) ? + _theResult___fst_exp__h447642 ; + assign _theResult___fst_exp__h447651 = + (!_theResult____h439468[56] && _theResult____h439468[55]) ? 8'd1 : - _theResult___fst_exp__h447957 ; - assign _theResult___fst_exp__h448483 = - (_theResult___fst_exp__h447886 == 8'd255) ? - _theResult___fst_exp__h447886 : - _theResult___fst_exp__h448480 ; - assign _theResult___fst_exp__h456533 = + _theResult___fst_exp__h447648 ; + assign _theResult___fst_exp__h448174 = + (_theResult___fst_exp__h447577 == 8'd255) ? + _theResult___fst_exp__h447577 : + _theResult___fst_exp__h448171 ; + assign _theResult___fst_exp__h456224 = 8'd129 - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7358 } ; - assign _theResult___fst_exp__h456539 = + assign _theResult___fst_exp__h456230 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7303 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7360) ? 8'd0 : - _theResult___fst_exp__h456533 ; - assign _theResult___fst_exp__h456542 = + _theResult___fst_exp__h456224 ; + assign _theResult___fst_exp__h456233 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h456539 : + _theResult___fst_exp__h456230 : 8'd129 ; - assign _theResult___fst_exp__h457065 = - (_theResult___fst_exp__h456542 == 8'd255) ? - _theResult___fst_exp__h456542 : - _theResult___fst_exp__h457062 ; - assign _theResult___fst_exp__h465652 = - _theResult____h457414[56] ? + assign _theResult___fst_exp__h456756 = + (_theResult___fst_exp__h456233 == 8'd255) ? + _theResult___fst_exp__h456233 : + _theResult___fst_exp__h456753 ; + assign _theResult___fst_exp__h465343 = + _theResult____h457105[56] ? 8'd2 : - _theResult___fst_exp__h465726 ; - assign _theResult___fst_exp__h465717 = + _theResult___fst_exp__h465417 ; + assign _theResult___fst_exp__h465408 = 8'd0 - { 2'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7678 } ; - assign _theResult___fst_exp__h465723 = - (!_theResult____h457414[56] && !_theResult____h457414[55] && - !_theResult____h457414[54] && - !_theResult____h457414[53] && - !_theResult____h457414[52] && - !_theResult____h457414[51] && - !_theResult____h457414[50] && - !_theResult____h457414[49] && - !_theResult____h457414[48] && - !_theResult____h457414[47] && - !_theResult____h457414[46] && - !_theResult____h457414[45] && - !_theResult____h457414[44] && - !_theResult____h457414[43] && - !_theResult____h457414[42] && - !_theResult____h457414[41] && - !_theResult____h457414[40] && - !_theResult____h457414[39] && - !_theResult____h457414[38] && - !_theResult____h457414[37] && - !_theResult____h457414[36] && - !_theResult____h457414[35] && - !_theResult____h457414[34] && - !_theResult____h457414[33] && - !_theResult____h457414[32] && - !_theResult____h457414[31] && - !_theResult____h457414[30] && - !_theResult____h457414[29] && - !_theResult____h457414[28] && - !_theResult____h457414[27] && - !_theResult____h457414[26] && - !_theResult____h457414[25] && - !_theResult____h457414[24] && - !_theResult____h457414[23] && - !_theResult____h457414[22] && - !_theResult____h457414[21] && - !_theResult____h457414[20] && - !_theResult____h457414[19] && - !_theResult____h457414[18] && - !_theResult____h457414[17] && - !_theResult____h457414[16] && - !_theResult____h457414[15] && - !_theResult____h457414[14] && - !_theResult____h457414[13] && - !_theResult____h457414[12] && - !_theResult____h457414[11] && - !_theResult____h457414[10] && - !_theResult____h457414[9] && - !_theResult____h457414[8] && - !_theResult____h457414[7] && - !_theResult____h457414[6] && - !_theResult____h457414[5] && - !_theResult____h457414[4] && - !_theResult____h457414[3] && - !_theResult____h457414[2] && - !_theResult____h457414[1] && - !_theResult____h457414[0] || + assign _theResult___fst_exp__h465414 = + (!_theResult____h457105[56] && !_theResult____h457105[55] && + !_theResult____h457105[54] && + !_theResult____h457105[53] && + !_theResult____h457105[52] && + !_theResult____h457105[51] && + !_theResult____h457105[50] && + !_theResult____h457105[49] && + !_theResult____h457105[48] && + !_theResult____h457105[47] && + !_theResult____h457105[46] && + !_theResult____h457105[45] && + !_theResult____h457105[44] && + !_theResult____h457105[43] && + !_theResult____h457105[42] && + !_theResult____h457105[41] && + !_theResult____h457105[40] && + !_theResult____h457105[39] && + !_theResult____h457105[38] && + !_theResult____h457105[37] && + !_theResult____h457105[36] && + !_theResult____h457105[35] && + !_theResult____h457105[34] && + !_theResult____h457105[33] && + !_theResult____h457105[32] && + !_theResult____h457105[31] && + !_theResult____h457105[30] && + !_theResult____h457105[29] && + !_theResult____h457105[28] && + !_theResult____h457105[27] && + !_theResult____h457105[26] && + !_theResult____h457105[25] && + !_theResult____h457105[24] && + !_theResult____h457105[23] && + !_theResult____h457105[22] && + !_theResult____h457105[21] && + !_theResult____h457105[20] && + !_theResult____h457105[19] && + !_theResult____h457105[18] && + !_theResult____h457105[17] && + !_theResult____h457105[16] && + !_theResult____h457105[15] && + !_theResult____h457105[14] && + !_theResult____h457105[13] && + !_theResult____h457105[12] && + !_theResult____h457105[11] && + !_theResult____h457105[10] && + !_theResult____h457105[9] && + !_theResult____h457105[8] && + !_theResult____h457105[7] && + !_theResult____h457105[6] && + !_theResult____h457105[5] && + !_theResult____h457105[4] && + !_theResult____h457105[3] && + !_theResult____h457105[2] && + !_theResult____h457105[1] && + !_theResult____h457105[0] || !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7680) ? 8'd0 : - _theResult___fst_exp__h465717 ; - assign _theResult___fst_exp__h465726 = - (!_theResult____h457414[56] && _theResult____h457414[55]) ? + _theResult___fst_exp__h465408 ; + assign _theResult___fst_exp__h465417 = + (!_theResult____h457105[56] && _theResult____h457105[55]) ? 8'd1 : - _theResult___fst_exp__h465723 ; - assign _theResult___fst_exp__h466249 = - (_theResult___fst_exp__h465652 == 8'd255) ? - _theResult___fst_exp__h465652 : - _theResult___fst_exp__h466246 ; - assign _theResult___fst_exp__h474289 = - (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q108[7:0] == + _theResult___fst_exp__h465414 ; + assign _theResult___fst_exp__h465940 = + (_theResult___fst_exp__h465343 == 8'd255) ? + _theResult___fst_exp__h465343 : + _theResult___fst_exp__h465937 ; + assign _theResult___fst_exp__h473980 = + (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q100[7:0] == 8'd0) ? 8'd1 : - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q108[7:0] ; - assign _theResult___fst_exp__h474328 = - SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q108[7:0] - + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q100[7:0] ; + assign _theResult___fst_exp__h474019 = + SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q100[7:0] - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7358 } ; - assign _theResult___fst_exp__h474334 = + assign _theResult___fst_exp__h474025 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7303 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7753) ? 8'd0 : - _theResult___fst_exp__h474328 ; - assign _theResult___fst_exp__h474337 = + _theResult___fst_exp__h474019 ; + assign _theResult___fst_exp__h474028 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h474334 : - _theResult___fst_exp__h474289 ; - assign _theResult___fst_exp__h474885 = - (_theResult___fst_exp__h474337 == 8'd255) ? - _theResult___fst_exp__h474337 : - _theResult___fst_exp__h474882 ; - assign _theResult___fst_exp__h474894 = + _theResult___fst_exp__h474025 : + _theResult___fst_exp__h473980 ; + assign _theResult___fst_exp__h474576 = + (_theResult___fst_exp__h474028 == 8'd255) ? + _theResult___fst_exp__h474028 : + _theResult___fst_exp__h474573 ; + assign _theResult___fst_exp__h474585 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6892 ? - _theResult___snd_fst_exp__h457068 : - _theResult___fst_exp__h439759) : + _theResult___snd_fst_exp__h456759 : + _theResult___fst_exp__h439450) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7432 ? - _theResult___snd_fst_exp__h474888 : - _theResult___fst_exp__h439759) ; - assign _theResult___fst_exp__h474897 = + _theResult___snd_fst_exp__h474579 : + _theResult___fst_exp__h439450) ; + assign _theResult___fst_exp__h474588 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == 52'd0) ? 8'd0 : - _theResult___fst_exp__h474894 ; - assign _theResult___fst_exp__h489261 = + _theResult___fst_exp__h474585 ; + assign _theResult___fst_exp__h488952 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 ; - assign _theResult___fst_exp__h504325 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q7 ; + assign _theResult___fst_exp__h504016 = 11'd897 - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8694 } ; - assign _theResult___fst_exp__h504331 = - (f1_exp__h484946 == 8'd0 && !f1_sfd__h484947[22] && + assign _theResult___fst_exp__h504022 = + (f1_exp__h484637 == 8'd0 && !f1_sfd__h484638[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8667 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8696) ? 11'd0 : - _theResult___fst_exp__h504325 ; - assign _theResult___fst_exp__h504334 = - (f1_exp__h484946 == 8'd0) ? - _theResult___fst_exp__h504331 : + _theResult___fst_exp__h504016 ; + assign _theResult___fst_exp__h504025 = + (f1_exp__h484637 == 8'd0) ? + _theResult___fst_exp__h504022 : 11'd897 ; - assign _theResult___fst_exp__h505089 = + assign _theResult___fst_exp__h504780 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard96373_0b0_theResult___fst_exp04334_0_ETC__q144 : + CASE_guard96064_0b0_theResult___fst_exp04025_0_ETC__q136 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9130 ; - assign _theResult___fst_exp__h505092 = - (_theResult___fst_exp__h504334 == 11'd2047) ? - _theResult___fst_exp__h504334 : - _theResult___fst_exp__h505089 ; - assign _theResult___fst_exp__h513911 = - _theResult____h505675[56] ? + assign _theResult___fst_exp__h504783 = + (_theResult___fst_exp__h504025 == 11'd2047) ? + _theResult___fst_exp__h504025 : + _theResult___fst_exp__h504780 ; + assign _theResult___fst_exp__h513602 = + _theResult____h505366[56] ? 11'd2 : - _theResult___fst_exp__h513985 ; - assign _theResult___fst_exp__h513976 = + _theResult___fst_exp__h513676 ; + assign _theResult___fst_exp__h513667 = 11'd0 - { 5'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9006 } ; - assign _theResult___fst_exp__h513982 = - (!_theResult____h505675[56] && !_theResult____h505675[55] && - !_theResult____h505675[54] && - !_theResult____h505675[53] && - !_theResult____h505675[52] && - !_theResult____h505675[51] && - !_theResult____h505675[50] && - !_theResult____h505675[49] && - !_theResult____h505675[48] && - !_theResult____h505675[47] && - !_theResult____h505675[46] && - !_theResult____h505675[45] && - !_theResult____h505675[44] && - !_theResult____h505675[43] && - !_theResult____h505675[42] && - !_theResult____h505675[41] && - !_theResult____h505675[40] && - !_theResult____h505675[39] && - !_theResult____h505675[38] && - !_theResult____h505675[37] && - !_theResult____h505675[36] && - !_theResult____h505675[35] && - !_theResult____h505675[34] && - !_theResult____h505675[33] && - !_theResult____h505675[32] && - !_theResult____h505675[31] && - !_theResult____h505675[30] && - !_theResult____h505675[29] && - !_theResult____h505675[28] && - !_theResult____h505675[27] && - !_theResult____h505675[26] && - !_theResult____h505675[25] && - !_theResult____h505675[24] && - !_theResult____h505675[23] && - !_theResult____h505675[22] && - !_theResult____h505675[21] && - !_theResult____h505675[20] && - !_theResult____h505675[19] && - !_theResult____h505675[18] && - !_theResult____h505675[17] && - !_theResult____h505675[16] && - !_theResult____h505675[15] && - !_theResult____h505675[14] && - !_theResult____h505675[13] && - !_theResult____h505675[12] && - !_theResult____h505675[11] && - !_theResult____h505675[10] && - !_theResult____h505675[9] && - !_theResult____h505675[8] && - !_theResult____h505675[7] && - !_theResult____h505675[6] && - !_theResult____h505675[5] && - !_theResult____h505675[4] && - !_theResult____h505675[3] && - !_theResult____h505675[2] && - !_theResult____h505675[1] && - !_theResult____h505675[0] || + assign _theResult___fst_exp__h513673 = + (!_theResult____h505366[56] && !_theResult____h505366[55] && + !_theResult____h505366[54] && + !_theResult____h505366[53] && + !_theResult____h505366[52] && + !_theResult____h505366[51] && + !_theResult____h505366[50] && + !_theResult____h505366[49] && + !_theResult____h505366[48] && + !_theResult____h505366[47] && + !_theResult____h505366[46] && + !_theResult____h505366[45] && + !_theResult____h505366[44] && + !_theResult____h505366[43] && + !_theResult____h505366[42] && + !_theResult____h505366[41] && + !_theResult____h505366[40] && + !_theResult____h505366[39] && + !_theResult____h505366[38] && + !_theResult____h505366[37] && + !_theResult____h505366[36] && + !_theResult____h505366[35] && + !_theResult____h505366[34] && + !_theResult____h505366[33] && + !_theResult____h505366[32] && + !_theResult____h505366[31] && + !_theResult____h505366[30] && + !_theResult____h505366[29] && + !_theResult____h505366[28] && + !_theResult____h505366[27] && + !_theResult____h505366[26] && + !_theResult____h505366[25] && + !_theResult____h505366[24] && + !_theResult____h505366[23] && + !_theResult____h505366[22] && + !_theResult____h505366[21] && + !_theResult____h505366[20] && + !_theResult____h505366[19] && + !_theResult____h505366[18] && + !_theResult____h505366[17] && + !_theResult____h505366[16] && + !_theResult____h505366[15] && + !_theResult____h505366[14] && + !_theResult____h505366[13] && + !_theResult____h505366[12] && + !_theResult____h505366[11] && + !_theResult____h505366[10] && + !_theResult____h505366[9] && + !_theResult____h505366[8] && + !_theResult____h505366[7] && + !_theResult____h505366[6] && + !_theResult____h505366[5] && + !_theResult____h505366[4] && + !_theResult____h505366[3] && + !_theResult____h505366[2] && + !_theResult____h505366[1] && + !_theResult____h505366[0] || !_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d9008) ? 11'd0 : - _theResult___fst_exp__h513976 ; - assign _theResult___fst_exp__h513985 = - (!_theResult____h505675[56] && _theResult____h505675[55]) ? + _theResult___fst_exp__h513667 ; + assign _theResult___fst_exp__h513676 = + (!_theResult____h505366[56] && _theResult____h505366[55]) ? 11'd1 : - _theResult___fst_exp__h513982 ; - assign _theResult___fst_exp__h514740 = + _theResult___fst_exp__h513673 ; + assign _theResult___fst_exp__h514431 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard05685_0b0_theResult___fst_exp13911_0_ETC__q212 : + CASE_guard05376_0b0_theResult___fst_exp13602_0_ETC__q204 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9173 ; - assign _theResult___fst_exp__h514743 = - (_theResult___fst_exp__h513911 == 11'd2047) ? - _theResult___fst_exp__h513911 : - _theResult___fst_exp__h514740 ; - assign _theResult___fst_exp__h522696 = - (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137[10:0] == + assign _theResult___fst_exp__h514434 = + (_theResult___fst_exp__h513602 == 11'd2047) ? + _theResult___fst_exp__h513602 : + _theResult___fst_exp__h514431 ; + assign _theResult___fst_exp__h522387 = + (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q129[10:0] == 11'd0) ? 11'd1 : - SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137[10:0] ; - assign _theResult___fst_exp__h522735 = - SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137[10:0] - + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q129[10:0] ; + assign _theResult___fst_exp__h522426 = + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q129[10:0] - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8694 } ; - assign _theResult___fst_exp__h522741 = - (f1_exp__h484946 == 8'd0 && !f1_sfd__h484947[22] && + assign _theResult___fst_exp__h522432 = + (f1_exp__h484637 == 8'd0 && !f1_sfd__h484638[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8667 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9058) ? 11'd0 : - _theResult___fst_exp__h522735 ; - assign _theResult___fst_exp__h522744 = - (f1_exp__h484946 == 8'd0) ? - _theResult___fst_exp__h522741 : - _theResult___fst_exp__h522696 ; - assign _theResult___fst_exp__h523524 = + _theResult___fst_exp__h522426 ; + assign _theResult___fst_exp__h522435 = + (f1_exp__h484637 == 8'd0) ? + _theResult___fst_exp__h522432 : + _theResult___fst_exp__h522387 ; + assign _theResult___fst_exp__h523215 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard14754_0b0_theResult___fst_exp22744_0_ETC__q214 : + CASE_guard14445_0b0_theResult___fst_exp22435_0_ETC__q208 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9204 ; - assign _theResult___fst_exp__h523527 = - (_theResult___fst_exp__h522744 == 11'd2047) ? - _theResult___fst_exp__h522744 : - _theResult___fst_exp__h523524 ; - assign _theResult___fst_exp__h523536 = - (f1_exp__h484946 == 8'd0) ? + assign _theResult___fst_exp__h523218 = + (_theResult___fst_exp__h522435 == 11'd2047) ? + _theResult___fst_exp__h522435 : + _theResult___fst_exp__h523215 ; + assign _theResult___fst_exp__h523227 = + (f1_exp__h484637 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8621 ? - _theResult___snd_fst_exp__h505095 : - _theResult___fst_exp__h489261) : + _theResult___snd_fst_exp__h504786 : + _theResult___fst_exp__h488952) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8758 ? - _theResult___snd_fst_exp__h523530 : - _theResult___fst_exp__h489261) ; - assign _theResult___fst_exp__h523539 = - (f1_exp__h484946 == 8'd0 && f1_sfd__h484947 == 23'd0) ? + _theResult___snd_fst_exp__h523221 : + _theResult___fst_exp__h488952) ; + assign _theResult___fst_exp__h523230 = + (f1_exp__h484637 == 8'd0 && f1_sfd__h484638 == 23'd0) ? 11'd0 : - _theResult___fst_exp__h523536 ; - assign _theResult___fst_exp__h528114 = + _theResult___fst_exp__h523227 ; + assign _theResult___fst_exp__h527805 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q18 ; - assign _theResult___fst_exp__h543178 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q9 ; + assign _theResult___fst_exp__h542869 = 11'd897 - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10194 } ; - assign _theResult___fst_exp__h543184 = - (f2_exp__h523940 == 8'd0 && !f2_sfd__h523941[22] && + assign _theResult___fst_exp__h542875 = + (f2_exp__h523631 == 8'd0 && !f2_sfd__h523632[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10167 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10196) ? 11'd0 : - _theResult___fst_exp__h543178 ; - assign _theResult___fst_exp__h543187 = - (f2_exp__h523940 == 8'd0) ? - _theResult___fst_exp__h543184 : + _theResult___fst_exp__h542869 ; + assign _theResult___fst_exp__h542878 = + (f2_exp__h523631 == 8'd0) ? + _theResult___fst_exp__h542875 : 11'd897 ; - assign _theResult___fst_exp__h543942 = + assign _theResult___fst_exp__h543633 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard35226_0b0_theResult___fst_exp43187_0_ETC__q184 : + CASE_guard34917_0b0_theResult___fst_exp42878_0_ETC__q176 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10615 ; - assign _theResult___fst_exp__h543945 = - (_theResult___fst_exp__h543187 == 11'd2047) ? - _theResult___fst_exp__h543187 : - _theResult___fst_exp__h543942 ; - assign _theResult___fst_exp__h552764 = - _theResult____h544528[56] ? + assign _theResult___fst_exp__h543636 = + (_theResult___fst_exp__h542878 == 11'd2047) ? + _theResult___fst_exp__h542878 : + _theResult___fst_exp__h543633 ; + assign _theResult___fst_exp__h552455 = + _theResult____h544219[56] ? 11'd2 : - _theResult___fst_exp__h552838 ; - assign _theResult___fst_exp__h552829 = + _theResult___fst_exp__h552529 ; + assign _theResult___fst_exp__h552520 = 11'd0 - { 5'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10491 } ; - assign _theResult___fst_exp__h552835 = - (!_theResult____h544528[56] && !_theResult____h544528[55] && - !_theResult____h544528[54] && - !_theResult____h544528[53] && - !_theResult____h544528[52] && - !_theResult____h544528[51] && - !_theResult____h544528[50] && - !_theResult____h544528[49] && - !_theResult____h544528[48] && - !_theResult____h544528[47] && - !_theResult____h544528[46] && - !_theResult____h544528[45] && - !_theResult____h544528[44] && - !_theResult____h544528[43] && - !_theResult____h544528[42] && - !_theResult____h544528[41] && - !_theResult____h544528[40] && - !_theResult____h544528[39] && - !_theResult____h544528[38] && - !_theResult____h544528[37] && - !_theResult____h544528[36] && - !_theResult____h544528[35] && - !_theResult____h544528[34] && - !_theResult____h544528[33] && - !_theResult____h544528[32] && - !_theResult____h544528[31] && - !_theResult____h544528[30] && - !_theResult____h544528[29] && - !_theResult____h544528[28] && - !_theResult____h544528[27] && - !_theResult____h544528[26] && - !_theResult____h544528[25] && - !_theResult____h544528[24] && - !_theResult____h544528[23] && - !_theResult____h544528[22] && - !_theResult____h544528[21] && - !_theResult____h544528[20] && - !_theResult____h544528[19] && - !_theResult____h544528[18] && - !_theResult____h544528[17] && - !_theResult____h544528[16] && - !_theResult____h544528[15] && - !_theResult____h544528[14] && - !_theResult____h544528[13] && - !_theResult____h544528[12] && - !_theResult____h544528[11] && - !_theResult____h544528[10] && - !_theResult____h544528[9] && - !_theResult____h544528[8] && - !_theResult____h544528[7] && - !_theResult____h544528[6] && - !_theResult____h544528[5] && - !_theResult____h544528[4] && - !_theResult____h544528[3] && - !_theResult____h544528[2] && - !_theResult____h544528[1] && - !_theResult____h544528[0] || + assign _theResult___fst_exp__h552526 = + (!_theResult____h544219[56] && !_theResult____h544219[55] && + !_theResult____h544219[54] && + !_theResult____h544219[53] && + !_theResult____h544219[52] && + !_theResult____h544219[51] && + !_theResult____h544219[50] && + !_theResult____h544219[49] && + !_theResult____h544219[48] && + !_theResult____h544219[47] && + !_theResult____h544219[46] && + !_theResult____h544219[45] && + !_theResult____h544219[44] && + !_theResult____h544219[43] && + !_theResult____h544219[42] && + !_theResult____h544219[41] && + !_theResult____h544219[40] && + !_theResult____h544219[39] && + !_theResult____h544219[38] && + !_theResult____h544219[37] && + !_theResult____h544219[36] && + !_theResult____h544219[35] && + !_theResult____h544219[34] && + !_theResult____h544219[33] && + !_theResult____h544219[32] && + !_theResult____h544219[31] && + !_theResult____h544219[30] && + !_theResult____h544219[29] && + !_theResult____h544219[28] && + !_theResult____h544219[27] && + !_theResult____h544219[26] && + !_theResult____h544219[25] && + !_theResult____h544219[24] && + !_theResult____h544219[23] && + !_theResult____h544219[22] && + !_theResult____h544219[21] && + !_theResult____h544219[20] && + !_theResult____h544219[19] && + !_theResult____h544219[18] && + !_theResult____h544219[17] && + !_theResult____h544219[16] && + !_theResult____h544219[15] && + !_theResult____h544219[14] && + !_theResult____h544219[13] && + !_theResult____h544219[12] && + !_theResult____h544219[11] && + !_theResult____h544219[10] && + !_theResult____h544219[9] && + !_theResult____h544219[8] && + !_theResult____h544219[7] && + !_theResult____h544219[6] && + !_theResult____h544219[5] && + !_theResult____h544219[4] && + !_theResult____h544219[3] && + !_theResult____h544219[2] && + !_theResult____h544219[1] && + !_theResult____h544219[0] || !_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10493) ? 11'd0 : - _theResult___fst_exp__h552829 ; - assign _theResult___fst_exp__h552838 = - (!_theResult____h544528[56] && _theResult____h544528[55]) ? + _theResult___fst_exp__h552520 ; + assign _theResult___fst_exp__h552529 = + (!_theResult____h544219[56] && _theResult____h544219[55]) ? 11'd1 : - _theResult___fst_exp__h552835 ; - assign _theResult___fst_exp__h553593 = + _theResult___fst_exp__h552526 ; + assign _theResult___fst_exp__h553284 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard44538_0b0_theResult___fst_exp52764_0_ETC__q186 : + CASE_guard44229_0b0_theResult___fst_exp52455_0_ETC__q178 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10653 ; - assign _theResult___fst_exp__h553596 = - (_theResult___fst_exp__h552764 == 11'd2047) ? - _theResult___fst_exp__h552764 : - _theResult___fst_exp__h553593 ; - assign _theResult___fst_exp__h561549 = - (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q177[10:0] == + assign _theResult___fst_exp__h553287 = + (_theResult___fst_exp__h552455 == 11'd2047) ? + _theResult___fst_exp__h552455 : + _theResult___fst_exp__h553284 ; + assign _theResult___fst_exp__h561240 = + (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q169[10:0] == 11'd0) ? 11'd1 : - SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q177[10:0] ; - assign _theResult___fst_exp__h561588 = - SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q177[10:0] - + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q169[10:0] ; + assign _theResult___fst_exp__h561279 = + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q169[10:0] - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10194 } ; - assign _theResult___fst_exp__h561594 = - (f2_exp__h523940 == 8'd0 && !f2_sfd__h523941[22] && + assign _theResult___fst_exp__h561285 = + (f2_exp__h523631 == 8'd0 && !f2_sfd__h523632[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10167 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10543) ? 11'd0 : - _theResult___fst_exp__h561588 ; - assign _theResult___fst_exp__h561597 = - (f2_exp__h523940 == 8'd0) ? - _theResult___fst_exp__h561594 : - _theResult___fst_exp__h561549 ; - assign _theResult___fst_exp__h562377 = + _theResult___fst_exp__h561279 ; + assign _theResult___fst_exp__h561288 = + (f2_exp__h523631 == 8'd0) ? + _theResult___fst_exp__h561285 : + _theResult___fst_exp__h561240 ; + assign _theResult___fst_exp__h562068 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard53607_0b0_theResult___fst_exp61597_0_ETC__q188 : + CASE_guard53298_0b0_theResult___fst_exp61288_0_ETC__q180 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10684 ; - assign _theResult___fst_exp__h562380 = - (_theResult___fst_exp__h561597 == 11'd2047) ? - _theResult___fst_exp__h561597 : - _theResult___fst_exp__h562377 ; - assign _theResult___fst_exp__h562389 = - (f2_exp__h523940 == 8'd0) ? + assign _theResult___fst_exp__h562071 = + (_theResult___fst_exp__h561288 == 11'd2047) ? + _theResult___fst_exp__h561288 : + _theResult___fst_exp__h562068 ; + assign _theResult___fst_exp__h562080 = + (f2_exp__h523631 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10121 ? - _theResult___snd_fst_exp__h543948 : - _theResult___fst_exp__h528114) : + _theResult___snd_fst_exp__h543639 : + _theResult___fst_exp__h527805) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10243 ? - _theResult___snd_fst_exp__h562383 : - _theResult___fst_exp__h528114) ; - assign _theResult___fst_exp__h562392 = - (f2_exp__h523940 == 8'd0 && f2_sfd__h523941 == 23'd0) ? + _theResult___snd_fst_exp__h562074 : + _theResult___fst_exp__h527805) ; + assign _theResult___fst_exp__h562083 = + (f2_exp__h523631 == 8'd0 && f2_sfd__h523632 == 23'd0) ? 11'd0 : - _theResult___fst_exp__h562389 ; - assign _theResult___fst_exp__h567418 = + _theResult___fst_exp__h562080 ; + assign _theResult___fst_exp__h567109 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q19 ; - assign _theResult___fst_exp__h582482 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q11 ; + assign _theResult___fst_exp__h582173 = 11'd897 - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9424 } ; - assign _theResult___fst_exp__h582488 = - (f3_exp__h563244 == 8'd0 && !f3_sfd__h563245[22] && + assign _theResult___fst_exp__h582179 = + (f3_exp__h562935 == 8'd0 && !f3_sfd__h562936[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9397 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9426) ? 11'd0 : - _theResult___fst_exp__h582482 ; - assign _theResult___fst_exp__h582491 = - (f3_exp__h563244 == 8'd0) ? - _theResult___fst_exp__h582488 : + _theResult___fst_exp__h582173 ; + assign _theResult___fst_exp__h582182 = + (f3_exp__h562935 == 8'd0) ? + _theResult___fst_exp__h582179 : 11'd897 ; - assign _theResult___fst_exp__h583246 = + assign _theResult___fst_exp__h582937 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard74530_0b0_theResult___fst_exp82491_0_ETC__q161 : + CASE_guard74221_0b0_theResult___fst_exp82182_0_ETC__q153 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9845 ; - assign _theResult___fst_exp__h583249 = - (_theResult___fst_exp__h582491 == 11'd2047) ? - _theResult___fst_exp__h582491 : - _theResult___fst_exp__h583246 ; - assign _theResult___fst_exp__h592068 = - _theResult____h583832[56] ? + assign _theResult___fst_exp__h582940 = + (_theResult___fst_exp__h582182 == 11'd2047) ? + _theResult___fst_exp__h582182 : + _theResult___fst_exp__h582937 ; + assign _theResult___fst_exp__h591759 = + _theResult____h583523[56] ? 11'd2 : - _theResult___fst_exp__h592142 ; - assign _theResult___fst_exp__h592133 = + _theResult___fst_exp__h591833 ; + assign _theResult___fst_exp__h591824 = 11'd0 - { 5'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9721 } ; - assign _theResult___fst_exp__h592139 = - (!_theResult____h583832[56] && !_theResult____h583832[55] && - !_theResult____h583832[54] && - !_theResult____h583832[53] && - !_theResult____h583832[52] && - !_theResult____h583832[51] && - !_theResult____h583832[50] && - !_theResult____h583832[49] && - !_theResult____h583832[48] && - !_theResult____h583832[47] && - !_theResult____h583832[46] && - !_theResult____h583832[45] && - !_theResult____h583832[44] && - !_theResult____h583832[43] && - !_theResult____h583832[42] && - !_theResult____h583832[41] && - !_theResult____h583832[40] && - !_theResult____h583832[39] && - !_theResult____h583832[38] && - !_theResult____h583832[37] && - !_theResult____h583832[36] && - !_theResult____h583832[35] && - !_theResult____h583832[34] && - !_theResult____h583832[33] && - !_theResult____h583832[32] && - !_theResult____h583832[31] && - !_theResult____h583832[30] && - !_theResult____h583832[29] && - !_theResult____h583832[28] && - !_theResult____h583832[27] && - !_theResult____h583832[26] && - !_theResult____h583832[25] && - !_theResult____h583832[24] && - !_theResult____h583832[23] && - !_theResult____h583832[22] && - !_theResult____h583832[21] && - !_theResult____h583832[20] && - !_theResult____h583832[19] && - !_theResult____h583832[18] && - !_theResult____h583832[17] && - !_theResult____h583832[16] && - !_theResult____h583832[15] && - !_theResult____h583832[14] && - !_theResult____h583832[13] && - !_theResult____h583832[12] && - !_theResult____h583832[11] && - !_theResult____h583832[10] && - !_theResult____h583832[9] && - !_theResult____h583832[8] && - !_theResult____h583832[7] && - !_theResult____h583832[6] && - !_theResult____h583832[5] && - !_theResult____h583832[4] && - !_theResult____h583832[3] && - !_theResult____h583832[2] && - !_theResult____h583832[1] && - !_theResult____h583832[0] || + assign _theResult___fst_exp__h591830 = + (!_theResult____h583523[56] && !_theResult____h583523[55] && + !_theResult____h583523[54] && + !_theResult____h583523[53] && + !_theResult____h583523[52] && + !_theResult____h583523[51] && + !_theResult____h583523[50] && + !_theResult____h583523[49] && + !_theResult____h583523[48] && + !_theResult____h583523[47] && + !_theResult____h583523[46] && + !_theResult____h583523[45] && + !_theResult____h583523[44] && + !_theResult____h583523[43] && + !_theResult____h583523[42] && + !_theResult____h583523[41] && + !_theResult____h583523[40] && + !_theResult____h583523[39] && + !_theResult____h583523[38] && + !_theResult____h583523[37] && + !_theResult____h583523[36] && + !_theResult____h583523[35] && + !_theResult____h583523[34] && + !_theResult____h583523[33] && + !_theResult____h583523[32] && + !_theResult____h583523[31] && + !_theResult____h583523[30] && + !_theResult____h583523[29] && + !_theResult____h583523[28] && + !_theResult____h583523[27] && + !_theResult____h583523[26] && + !_theResult____h583523[25] && + !_theResult____h583523[24] && + !_theResult____h583523[23] && + !_theResult____h583523[22] && + !_theResult____h583523[21] && + !_theResult____h583523[20] && + !_theResult____h583523[19] && + !_theResult____h583523[18] && + !_theResult____h583523[17] && + !_theResult____h583523[16] && + !_theResult____h583523[15] && + !_theResult____h583523[14] && + !_theResult____h583523[13] && + !_theResult____h583523[12] && + !_theResult____h583523[11] && + !_theResult____h583523[10] && + !_theResult____h583523[9] && + !_theResult____h583523[8] && + !_theResult____h583523[7] && + !_theResult____h583523[6] && + !_theResult____h583523[5] && + !_theResult____h583523[4] && + !_theResult____h583523[3] && + !_theResult____h583523[2] && + !_theResult____h583523[1] && + !_theResult____h583523[0] || !_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d9723) ? 11'd0 : - _theResult___fst_exp__h592133 ; - assign _theResult___fst_exp__h592142 = - (!_theResult____h583832[56] && _theResult____h583832[55]) ? + _theResult___fst_exp__h591824 ; + assign _theResult___fst_exp__h591833 = + (!_theResult____h583523[56] && _theResult____h583523[55]) ? 11'd1 : - _theResult___fst_exp__h592139 ; - assign _theResult___fst_exp__h592897 = + _theResult___fst_exp__h591830 ; + assign _theResult___fst_exp__h592588 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard83842_0b0_theResult___fst_exp92068_0_ETC__q190 : + CASE_guard83533_0b0_theResult___fst_exp91759_0_ETC__q184 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9883 ; - assign _theResult___fst_exp__h592900 = - (_theResult___fst_exp__h592068 == 11'd2047) ? - _theResult___fst_exp__h592068 : - _theResult___fst_exp__h592897 ; - assign _theResult___fst_exp__h600853 = - (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q154[10:0] == + assign _theResult___fst_exp__h592591 = + (_theResult___fst_exp__h591759 == 11'd2047) ? + _theResult___fst_exp__h591759 : + _theResult___fst_exp__h592588 ; + assign _theResult___fst_exp__h600544 = + (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q146[10:0] == 11'd0) ? 11'd1 : - SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q154[10:0] ; - assign _theResult___fst_exp__h600892 = - SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q154[10:0] - + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q146[10:0] ; + assign _theResult___fst_exp__h600583 = + SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q146[10:0] - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9424 } ; - assign _theResult___fst_exp__h600898 = - (f3_exp__h563244 == 8'd0 && !f3_sfd__h563245[22] && + assign _theResult___fst_exp__h600589 = + (f3_exp__h562935 == 8'd0 && !f3_sfd__h562936[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9397 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9773) ? 11'd0 : - _theResult___fst_exp__h600892 ; - assign _theResult___fst_exp__h600901 = - (f3_exp__h563244 == 8'd0) ? - _theResult___fst_exp__h600898 : - _theResult___fst_exp__h600853 ; - assign _theResult___fst_exp__h601681 = + _theResult___fst_exp__h600583 ; + assign _theResult___fst_exp__h600592 = + (f3_exp__h562935 == 8'd0) ? + _theResult___fst_exp__h600589 : + _theResult___fst_exp__h600544 ; + assign _theResult___fst_exp__h601372 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard92911_0b0_theResult___fst_exp00901_0_ETC__q192 : + CASE_guard92602_0b0_theResult___fst_exp00592_0_ETC__q182 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9914 ; - assign _theResult___fst_exp__h601684 = - (_theResult___fst_exp__h600901 == 11'd2047) ? - _theResult___fst_exp__h600901 : - _theResult___fst_exp__h601681 ; - assign _theResult___fst_exp__h601693 = - (f3_exp__h563244 == 8'd0) ? + assign _theResult___fst_exp__h601375 = + (_theResult___fst_exp__h600592 == 11'd2047) ? + _theResult___fst_exp__h600592 : + _theResult___fst_exp__h601372 ; + assign _theResult___fst_exp__h601384 = + (f3_exp__h562935 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9351 ? - _theResult___snd_fst_exp__h583252 : - _theResult___fst_exp__h567418) : + _theResult___snd_fst_exp__h582943 : + _theResult___fst_exp__h567109) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9473 ? - _theResult___snd_fst_exp__h601687 : - _theResult___fst_exp__h567418) ; - assign _theResult___fst_exp__h601696 = - (f3_exp__h563244 == 8'd0 && f3_sfd__h563245 == 23'd0) ? + _theResult___snd_fst_exp__h601378 : + _theResult___fst_exp__h567109) ; + assign _theResult___fst_exp__h601387 = + (f3_exp__h562935 == 8'd0 && f3_sfd__h562936 == 23'd0) ? 11'd0 : - _theResult___fst_exp__h601693 ; - assign _theResult___fst_sfd__h357092 = - (_theResult___fst_exp__h356494 == 8'd255) ? - sfdin__h356488[56:34] : - _theResult___fst_sfd__h357089 ; - assign _theResult___fst_sfd__h365674 = - (_theResult___fst_exp__h365150 == 8'd255) ? - _theResult___snd__h365101[56:34] : - _theResult___fst_sfd__h365671 ; - assign _theResult___fst_sfd__h374858 = - (_theResult___fst_exp__h374260 == 8'd255) ? - sfdin__h374254[56:34] : - _theResult___fst_sfd__h374855 ; - assign _theResult___fst_sfd__h383494 = - (_theResult___fst_exp__h382945 == 8'd255) ? - _theResult___snd__h382891[56:34] : - _theResult___fst_sfd__h383491 ; - assign _theResult___fst_sfd__h383503 = + _theResult___fst_exp__h601384 ; + assign _theResult___fst_sfd__h356783 = + (_theResult___fst_exp__h356185 == 8'd255) ? + sfdin__h356179[56:34] : + _theResult___fst_sfd__h356780 ; + assign _theResult___fst_sfd__h365365 = + (_theResult___fst_exp__h364841 == 8'd255) ? + _theResult___snd__h364792[56:34] : + _theResult___fst_sfd__h365362 ; + assign _theResult___fst_sfd__h374549 = + (_theResult___fst_exp__h373951 == 8'd255) ? + sfdin__h373945[56:34] : + _theResult___fst_sfd__h374546 ; + assign _theResult___fst_sfd__h383185 = + (_theResult___fst_exp__h382636 == 8'd255) ? + _theResult___snd__h382582[56:34] : + _theResult___fst_sfd__h383182 ; + assign _theResult___fst_sfd__h383194 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4108 ? - _theResult___snd_fst_sfd__h365677 : - _theResult___fst_sfd__h348366) : + _theResult___snd_fst_sfd__h365368 : + _theResult___fst_sfd__h348057) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4648 ? - _theResult___snd_fst_sfd__h383497 : - _theResult___fst_sfd__h348366) ; - assign _theResult___fst_sfd__h383509 = + _theResult___snd_fst_sfd__h383188 : + _theResult___fst_sfd__h348057) ; + assign _theResult___fst_sfd__h383200 = ((coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == @@ -27922,33 +27764,33 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == 52'd0) ? 23'd0 : - _theResult___fst_sfd__h383503 ; - assign _theResult___fst_sfd__h402789 = - (_theResult___fst_exp__h402191 == 8'd255) ? - sfdin__h402185[56:34] : - _theResult___fst_sfd__h402786 ; - assign _theResult___fst_sfd__h411371 = - (_theResult___fst_exp__h410847 == 8'd255) ? - _theResult___snd__h410798[56:34] : - _theResult___fst_sfd__h411368 ; - assign _theResult___fst_sfd__h420555 = - (_theResult___fst_exp__h419957 == 8'd255) ? - sfdin__h419951[56:34] : - _theResult___fst_sfd__h420552 ; - assign _theResult___fst_sfd__h429191 = - (_theResult___fst_exp__h428642 == 8'd255) ? - _theResult___snd__h428588[56:34] : - _theResult___fst_sfd__h429188 ; - assign _theResult___fst_sfd__h429200 = + _theResult___fst_sfd__h383194 ; + assign _theResult___fst_sfd__h402480 = + (_theResult___fst_exp__h401882 == 8'd255) ? + sfdin__h401876[56:34] : + _theResult___fst_sfd__h402477 ; + assign _theResult___fst_sfd__h411062 = + (_theResult___fst_exp__h410538 == 8'd255) ? + _theResult___snd__h410489[56:34] : + _theResult___fst_sfd__h411059 ; + assign _theResult___fst_sfd__h420246 = + (_theResult___fst_exp__h419648 == 8'd255) ? + sfdin__h419642[56:34] : + _theResult___fst_sfd__h420243 ; + assign _theResult___fst_sfd__h428882 = + (_theResult___fst_exp__h428333 == 8'd255) ? + _theResult___snd__h428279[56:34] : + _theResult___fst_sfd__h428879 ; + assign _theResult___fst_sfd__h428891 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5500 ? - _theResult___snd_fst_sfd__h411374 : - _theResult___fst_sfd__h394065) : + _theResult___snd_fst_sfd__h411065 : + _theResult___fst_sfd__h393756) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6040 ? - _theResult___snd_fst_sfd__h429194 : - _theResult___fst_sfd__h394065) ; - assign _theResult___fst_sfd__h429206 = + _theResult___snd_fst_sfd__h428885 : + _theResult___fst_sfd__h393756) ; + assign _theResult___fst_sfd__h428897 = ((coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == @@ -27956,33 +27798,33 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == 52'd0) ? 23'd0 : - _theResult___fst_sfd__h429200 ; - assign _theResult___fst_sfd__h448484 = - (_theResult___fst_exp__h447886 == 8'd255) ? - sfdin__h447880[56:34] : - _theResult___fst_sfd__h448481 ; - assign _theResult___fst_sfd__h457066 = - (_theResult___fst_exp__h456542 == 8'd255) ? - _theResult___snd__h456493[56:34] : - _theResult___fst_sfd__h457063 ; - assign _theResult___fst_sfd__h466250 = - (_theResult___fst_exp__h465652 == 8'd255) ? - sfdin__h465646[56:34] : - _theResult___fst_sfd__h466247 ; - assign _theResult___fst_sfd__h474886 = - (_theResult___fst_exp__h474337 == 8'd255) ? - _theResult___snd__h474283[56:34] : - _theResult___fst_sfd__h474883 ; - assign _theResult___fst_sfd__h474895 = + _theResult___fst_sfd__h428891 ; + assign _theResult___fst_sfd__h448175 = + (_theResult___fst_exp__h447577 == 8'd255) ? + sfdin__h447571[56:34] : + _theResult___fst_sfd__h448172 ; + assign _theResult___fst_sfd__h456757 = + (_theResult___fst_exp__h456233 == 8'd255) ? + _theResult___snd__h456184[56:34] : + _theResult___fst_sfd__h456754 ; + assign _theResult___fst_sfd__h465941 = + (_theResult___fst_exp__h465343 == 8'd255) ? + sfdin__h465337[56:34] : + _theResult___fst_sfd__h465938 ; + assign _theResult___fst_sfd__h474577 = + (_theResult___fst_exp__h474028 == 8'd255) ? + _theResult___snd__h473974[56:34] : + _theResult___fst_sfd__h474574 ; + assign _theResult___fst_sfd__h474586 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6892 ? - _theResult___snd_fst_sfd__h457069 : - _theResult___fst_sfd__h439760) : + _theResult___snd_fst_sfd__h456760 : + _theResult___fst_sfd__h439451) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7432 ? - _theResult___snd_fst_sfd__h474889 : - _theResult___fst_sfd__h439760) ; - assign _theResult___fst_sfd__h474901 = + _theResult___snd_fst_sfd__h474580 : + _theResult___fst_sfd__h439451) ; + assign _theResult___fst_sfd__h474592 = ((coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == @@ -27990,1313 +27832,1313 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == 52'd0) ? 23'd0 : - _theResult___fst_sfd__h474895 ; - assign _theResult___fst_sfd__h489262 = + _theResult___fst_sfd__h474586 ; + assign _theResult___fst_sfd__h488953 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17 ; - assign _theResult___fst_sfd__h505090 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q8 ; + assign _theResult___fst_sfd__h504781 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard96373_0b0_theResult___snd04285_BITS__ETC__q216 : + CASE_guard96064_0b0_theResult___snd03976_BITS__ETC__q206 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9230 ; - assign _theResult___fst_sfd__h505093 = - (_theResult___fst_exp__h504334 == 11'd2047) ? - _theResult___snd__h504285[56:5] : - _theResult___fst_sfd__h505090 ; - assign _theResult___fst_sfd__h514741 = + assign _theResult___fst_sfd__h504784 = + (_theResult___fst_exp__h504025 == 11'd2047) ? + _theResult___snd__h503976[56:5] : + _theResult___fst_sfd__h504781 ; + assign _theResult___fst_sfd__h514432 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard05685_0b0_sfdin13905_BITS_56_TO_5_0b_ETC__q218 : + CASE_guard05376_0b0_sfdin13596_BITS_56_TO_5_0b_ETC__q210 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9257 ; - assign _theResult___fst_sfd__h514744 = - (_theResult___fst_exp__h513911 == 11'd2047) ? - sfdin__h513905[56:5] : - _theResult___fst_sfd__h514741 ; - assign _theResult___fst_sfd__h523525 = + assign _theResult___fst_sfd__h514435 = + (_theResult___fst_exp__h513602 == 11'd2047) ? + sfdin__h513596[56:5] : + _theResult___fst_sfd__h514432 ; + assign _theResult___fst_sfd__h523216 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard14754_0b0_theResult___snd22690_BITS__ETC__q220 : + CASE_guard14445_0b0_theResult___snd22381_BITS__ETC__q212 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9276 ; - assign _theResult___fst_sfd__h523528 = - (_theResult___fst_exp__h522744 == 11'd2047) ? - _theResult___snd__h522690[56:5] : - _theResult___fst_sfd__h523525 ; - assign _theResult___fst_sfd__h523537 = - (f1_exp__h484946 == 8'd0) ? + assign _theResult___fst_sfd__h523219 = + (_theResult___fst_exp__h522435 == 11'd2047) ? + _theResult___snd__h522381[56:5] : + _theResult___fst_sfd__h523216 ; + assign _theResult___fst_sfd__h523228 = + (f1_exp__h484637 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8621 ? - _theResult___snd_fst_sfd__h505096 : - _theResult___fst_sfd__h489262) : + _theResult___snd_fst_sfd__h504787 : + _theResult___fst_sfd__h488953) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8758 ? - _theResult___snd_fst_sfd__h523531 : - _theResult___fst_sfd__h489262) ; - assign _theResult___fst_sfd__h523543 = - ((f1_exp__h484946 == 8'd255 || f1_exp__h484946 == 8'd0) && - f1_sfd__h484947 == 23'd0) ? + _theResult___snd_fst_sfd__h523222 : + _theResult___fst_sfd__h488953) ; + assign _theResult___fst_sfd__h523234 = + ((f1_exp__h484637 == 8'd255 || f1_exp__h484637 == 8'd0) && + f1_sfd__h484638 == 23'd0) ? 52'd0 : - _theResult___fst_sfd__h523537 ; - assign _theResult___fst_sfd__h528115 = + _theResult___fst_sfd__h523228 ; + assign _theResult___fst_sfd__h527806 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 ; - assign _theResult___fst_sfd__h543943 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q10 ; + assign _theResult___fst_sfd__h543634 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard35226_0b0_theResult___snd43138_BITS__ETC__q206 : + CASE_guard34917_0b0_theResult___snd42829_BITS__ETC__q198 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10710 ; - assign _theResult___fst_sfd__h543946 = - (_theResult___fst_exp__h543187 == 11'd2047) ? - _theResult___snd__h543138[56:5] : - _theResult___fst_sfd__h543943 ; - assign _theResult___fst_sfd__h553594 = + assign _theResult___fst_sfd__h543637 = + (_theResult___fst_exp__h542878 == 11'd2047) ? + _theResult___snd__h542829[56:5] : + _theResult___fst_sfd__h543634 ; + assign _theResult___fst_sfd__h553285 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard44538_0b0_sfdin52758_BITS_56_TO_5_0b_ETC__q208 : + CASE_guard44229_0b0_sfdin52449_BITS_56_TO_5_0b_ETC__q200 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10736 ; - assign _theResult___fst_sfd__h553597 = - (_theResult___fst_exp__h552764 == 11'd2047) ? - sfdin__h552758[56:5] : - _theResult___fst_sfd__h553594 ; - assign _theResult___fst_sfd__h562378 = + assign _theResult___fst_sfd__h553288 = + (_theResult___fst_exp__h552455 == 11'd2047) ? + sfdin__h552449[56:5] : + _theResult___fst_sfd__h553285 ; + assign _theResult___fst_sfd__h562069 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard53607_0b0_theResult___snd61543_BITS__ETC__q210 : + CASE_guard53298_0b0_theResult___snd61234_BITS__ETC__q202 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10755 ; - assign _theResult___fst_sfd__h562381 = - (_theResult___fst_exp__h561597 == 11'd2047) ? - _theResult___snd__h561543[56:5] : - _theResult___fst_sfd__h562378 ; - assign _theResult___fst_sfd__h562390 = - (f2_exp__h523940 == 8'd0) ? + assign _theResult___fst_sfd__h562072 = + (_theResult___fst_exp__h561288 == 11'd2047) ? + _theResult___snd__h561234[56:5] : + _theResult___fst_sfd__h562069 ; + assign _theResult___fst_sfd__h562081 = + (f2_exp__h523631 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10121 ? - _theResult___snd_fst_sfd__h543949 : - _theResult___fst_sfd__h528115) : + _theResult___snd_fst_sfd__h543640 : + _theResult___fst_sfd__h527806) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10243 ? - _theResult___snd_fst_sfd__h562384 : - _theResult___fst_sfd__h528115) ; - assign _theResult___fst_sfd__h562396 = - ((f2_exp__h523940 == 8'd255 || f2_exp__h523940 == 8'd0) && - f2_sfd__h523941 == 23'd0) ? + _theResult___snd_fst_sfd__h562075 : + _theResult___fst_sfd__h527806) ; + assign _theResult___fst_sfd__h562087 = + ((f2_exp__h523631 == 8'd255 || f2_exp__h523631 == 8'd0) && + f2_sfd__h523632 == 23'd0) ? 52'd0 : - _theResult___fst_sfd__h562390 ; - assign _theResult___fst_sfd__h567419 = + _theResult___fst_sfd__h562081 ; + assign _theResult___fst_sfd__h567110 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q20 ; - assign _theResult___fst_sfd__h583247 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q12 ; + assign _theResult___fst_sfd__h582938 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard74530_0b0_theResult___snd82442_BITS__ETC__q222 : + CASE_guard74221_0b0_theResult___snd82133_BITS__ETC__q214 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9940 ; - assign _theResult___fst_sfd__h583250 = - (_theResult___fst_exp__h582491 == 11'd2047) ? - _theResult___snd__h582442[56:5] : - _theResult___fst_sfd__h583247 ; - assign _theResult___fst_sfd__h592898 = + assign _theResult___fst_sfd__h582941 = + (_theResult___fst_exp__h582182 == 11'd2047) ? + _theResult___snd__h582133[56:5] : + _theResult___fst_sfd__h582938 ; + assign _theResult___fst_sfd__h592589 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard83842_0b0_sfdin92062_BITS_56_TO_5_0b_ETC__q224 : + CASE_guard83533_0b0_sfdin91753_BITS_56_TO_5_0b_ETC__q216 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9966 ; - assign _theResult___fst_sfd__h592901 = - (_theResult___fst_exp__h592068 == 11'd2047) ? - sfdin__h592062[56:5] : - _theResult___fst_sfd__h592898 ; - assign _theResult___fst_sfd__h601682 = + assign _theResult___fst_sfd__h592592 = + (_theResult___fst_exp__h591759 == 11'd2047) ? + sfdin__h591753[56:5] : + _theResult___fst_sfd__h592589 ; + assign _theResult___fst_sfd__h601373 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard92911_0b0_theResult___snd00847_BITS__ETC__q226 : + CASE_guard92602_0b0_theResult___snd00538_BITS__ETC__q218 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9985 ; - assign _theResult___fst_sfd__h601685 = - (_theResult___fst_exp__h600901 == 11'd2047) ? - _theResult___snd__h600847[56:5] : - _theResult___fst_sfd__h601682 ; - assign _theResult___fst_sfd__h601694 = - (f3_exp__h563244 == 8'd0) ? + assign _theResult___fst_sfd__h601376 = + (_theResult___fst_exp__h600592 == 11'd2047) ? + _theResult___snd__h600538[56:5] : + _theResult___fst_sfd__h601373 ; + assign _theResult___fst_sfd__h601385 = + (f3_exp__h562935 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9351 ? - _theResult___snd_fst_sfd__h583253 : - _theResult___fst_sfd__h567419) : + _theResult___snd_fst_sfd__h582944 : + _theResult___fst_sfd__h567110) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9473 ? - _theResult___snd_fst_sfd__h601688 : - _theResult___fst_sfd__h567419) ; - assign _theResult___fst_sfd__h601700 = - ((f3_exp__h563244 == 8'd255 || f3_exp__h563244 == 8'd0) && - f3_sfd__h563245 == 23'd0) ? + _theResult___snd_fst_sfd__h601379 : + _theResult___fst_sfd__h567110) ; + assign _theResult___fst_sfd__h601391 = + ((f3_exp__h562935 == 8'd255 || f3_exp__h562935 == 8'd0) && + f3_sfd__h562936 == 23'd0) ? 52'd0 : - _theResult___fst_sfd__h601694 ; - assign _theResult___sfd__h357011 = - sfd__h356586[24] ? - ((_theResult___fst_exp__h356494 == 8'd254) ? + _theResult___fst_sfd__h601385 ; + assign _theResult___sfd__h356702 = + sfd__h356277[24] ? + ((_theResult___fst_exp__h356185 == 8'd254) ? 23'd0 : - sfd__h356586[23:1]) : - sfd__h356586[22:0] ; - assign _theResult___sfd__h365593 = - sfd__h365168[24] ? - ((_theResult___fst_exp__h365150 == 8'd254) ? + sfd__h356277[23:1]) : + sfd__h356277[22:0] ; + assign _theResult___sfd__h365284 = + sfd__h364859[24] ? + ((_theResult___fst_exp__h364841 == 8'd254) ? 23'd0 : - sfd__h365168[23:1]) : - sfd__h365168[22:0] ; - assign _theResult___sfd__h374777 = - sfd__h374352[24] ? - ((_theResult___fst_exp__h374260 == 8'd254) ? + sfd__h364859[23:1]) : + sfd__h364859[22:0] ; + assign _theResult___sfd__h374468 = + sfd__h374043[24] ? + ((_theResult___fst_exp__h373951 == 8'd254) ? 23'd0 : - sfd__h374352[23:1]) : - sfd__h374352[22:0] ; - assign _theResult___sfd__h383413 = - sfd__h382964[24] ? - ((_theResult___fst_exp__h382945 == 8'd254) ? + sfd__h374043[23:1]) : + sfd__h374043[22:0] ; + assign _theResult___sfd__h383104 = + sfd__h382655[24] ? + ((_theResult___fst_exp__h382636 == 8'd254) ? 23'd0 : - sfd__h382964[23:1]) : - sfd__h382964[22:0] ; - assign _theResult___sfd__h383515 = + sfd__h382655[23:1]) : + sfd__h382655[22:0] ; + assign _theResult___sfd__h383206 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h340728 : - _theResult___fst_sfd__h383509 ; - assign _theResult___sfd__h402708 = - sfd__h402283[24] ? - ((_theResult___fst_exp__h402191 == 8'd254) ? + _theResult___snd_fst_sfd__h340419 : + _theResult___fst_sfd__h383200 ; + assign _theResult___sfd__h402399 = + sfd__h401974[24] ? + ((_theResult___fst_exp__h401882 == 8'd254) ? 23'd0 : - sfd__h402283[23:1]) : - sfd__h402283[22:0] ; - assign _theResult___sfd__h411290 = - sfd__h410865[24] ? - ((_theResult___fst_exp__h410847 == 8'd254) ? + sfd__h401974[23:1]) : + sfd__h401974[22:0] ; + assign _theResult___sfd__h410981 = + sfd__h410556[24] ? + ((_theResult___fst_exp__h410538 == 8'd254) ? 23'd0 : - sfd__h410865[23:1]) : - sfd__h410865[22:0] ; - assign _theResult___sfd__h420474 = - sfd__h420049[24] ? - ((_theResult___fst_exp__h419957 == 8'd254) ? + sfd__h410556[23:1]) : + sfd__h410556[22:0] ; + assign _theResult___sfd__h420165 = + sfd__h419740[24] ? + ((_theResult___fst_exp__h419648 == 8'd254) ? 23'd0 : - sfd__h420049[23:1]) : - sfd__h420049[22:0] ; - assign _theResult___sfd__h429110 = - sfd__h428661[24] ? - ((_theResult___fst_exp__h428642 == 8'd254) ? + sfd__h419740[23:1]) : + sfd__h419740[22:0] ; + assign _theResult___sfd__h428801 = + sfd__h428352[24] ? + ((_theResult___fst_exp__h428333 == 8'd254) ? 23'd0 : - sfd__h428661[23:1]) : - sfd__h428661[22:0] ; - assign _theResult___sfd__h429212 = + sfd__h428352[23:1]) : + sfd__h428352[22:0] ; + assign _theResult___sfd__h428903 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h386430 : - _theResult___fst_sfd__h429206 ; - assign _theResult___sfd__h448403 = - sfd__h447978[24] ? - ((_theResult___fst_exp__h447886 == 8'd254) ? + _theResult___snd_fst_sfd__h386121 : + _theResult___fst_sfd__h428897 ; + assign _theResult___sfd__h448094 = + sfd__h447669[24] ? + ((_theResult___fst_exp__h447577 == 8'd254) ? 23'd0 : - sfd__h447978[23:1]) : - sfd__h447978[22:0] ; - assign _theResult___sfd__h456985 = - sfd__h456560[24] ? - ((_theResult___fst_exp__h456542 == 8'd254) ? + sfd__h447669[23:1]) : + sfd__h447669[22:0] ; + assign _theResult___sfd__h456676 = + sfd__h456251[24] ? + ((_theResult___fst_exp__h456233 == 8'd254) ? 23'd0 : - sfd__h456560[23:1]) : - sfd__h456560[22:0] ; - assign _theResult___sfd__h466169 = - sfd__h465744[24] ? - ((_theResult___fst_exp__h465652 == 8'd254) ? + sfd__h456251[23:1]) : + sfd__h456251[22:0] ; + assign _theResult___sfd__h465860 = + sfd__h465435[24] ? + ((_theResult___fst_exp__h465343 == 8'd254) ? 23'd0 : - sfd__h465744[23:1]) : - sfd__h465744[22:0] ; - assign _theResult___sfd__h474805 = - sfd__h474356[24] ? - ((_theResult___fst_exp__h474337 == 8'd254) ? + sfd__h465435[23:1]) : + sfd__h465435[22:0] ; + assign _theResult___sfd__h474496 = + sfd__h474047[24] ? + ((_theResult___fst_exp__h474028 == 8'd254) ? 23'd0 : - sfd__h474356[23:1]) : - sfd__h474356[22:0] ; - assign _theResult___sfd__h474907 = + sfd__h474047[23:1]) : + sfd__h474047[22:0] ; + assign _theResult___sfd__h474598 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h432125 : - _theResult___fst_sfd__h474901 ; - assign _theResult___sfd__h504990 = - sfd__h504352[53] ? - ((_theResult___fst_exp__h504334 == 11'd2046) ? + _theResult___snd_fst_sfd__h431816 : + _theResult___fst_sfd__h474592 ; + assign _theResult___sfd__h504681 = + sfd__h504043[53] ? + ((_theResult___fst_exp__h504025 == 11'd2046) ? 52'd0 : - sfd__h504352[52:1]) : - sfd__h504352[51:0] ; - assign _theResult___sfd__h514641 = - sfd__h514003[53] ? - ((_theResult___fst_exp__h513911 == 11'd2046) ? + sfd__h504043[52:1]) : + sfd__h504043[51:0] ; + assign _theResult___sfd__h514332 = + sfd__h513694[53] ? + ((_theResult___fst_exp__h513602 == 11'd2046) ? 52'd0 : - sfd__h514003[52:1]) : - sfd__h514003[51:0] ; - assign _theResult___sfd__h523425 = - sfd__h522763[53] ? - ((_theResult___fst_exp__h522744 == 11'd2046) ? + sfd__h513694[52:1]) : + sfd__h513694[51:0] ; + assign _theResult___sfd__h523116 = + sfd__h522454[53] ? + ((_theResult___fst_exp__h522435 == 11'd2046) ? 52'd0 : - sfd__h522763[52:1]) : - sfd__h522763[51:0] ; - assign _theResult___sfd__h543843 = - sfd__h543205[53] ? - ((_theResult___fst_exp__h543187 == 11'd2046) ? + sfd__h522454[52:1]) : + sfd__h522454[51:0] ; + assign _theResult___sfd__h543534 = + sfd__h542896[53] ? + ((_theResult___fst_exp__h542878 == 11'd2046) ? 52'd0 : - sfd__h543205[52:1]) : - sfd__h543205[51:0] ; - assign _theResult___sfd__h553494 = - sfd__h552856[53] ? - ((_theResult___fst_exp__h552764 == 11'd2046) ? + sfd__h542896[52:1]) : + sfd__h542896[51:0] ; + assign _theResult___sfd__h553185 = + sfd__h552547[53] ? + ((_theResult___fst_exp__h552455 == 11'd2046) ? 52'd0 : - sfd__h552856[52:1]) : - sfd__h552856[51:0] ; - assign _theResult___sfd__h562278 = - sfd__h561616[53] ? - ((_theResult___fst_exp__h561597 == 11'd2046) ? + sfd__h552547[52:1]) : + sfd__h552547[51:0] ; + assign _theResult___sfd__h561969 = + sfd__h561307[53] ? + ((_theResult___fst_exp__h561288 == 11'd2046) ? 52'd0 : - sfd__h561616[52:1]) : - sfd__h561616[51:0] ; - assign _theResult___sfd__h583147 = - sfd__h582509[53] ? - ((_theResult___fst_exp__h582491 == 11'd2046) ? + sfd__h561307[52:1]) : + sfd__h561307[51:0] ; + assign _theResult___sfd__h582838 = + sfd__h582200[53] ? + ((_theResult___fst_exp__h582182 == 11'd2046) ? 52'd0 : - sfd__h582509[52:1]) : - sfd__h582509[51:0] ; - assign _theResult___sfd__h592798 = - sfd__h592160[53] ? - ((_theResult___fst_exp__h592068 == 11'd2046) ? + sfd__h582200[52:1]) : + sfd__h582200[51:0] ; + assign _theResult___sfd__h592489 = + sfd__h591851[53] ? + ((_theResult___fst_exp__h591759 == 11'd2046) ? 52'd0 : - sfd__h592160[52:1]) : - sfd__h592160[51:0] ; - assign _theResult___sfd__h601582 = - sfd__h600920[53] ? - ((_theResult___fst_exp__h600901 == 11'd2046) ? + sfd__h591851[52:1]) : + sfd__h591851[51:0] ; + assign _theResult___sfd__h601273 = + sfd__h600611[53] ? + ((_theResult___fst_exp__h600592 == 11'd2046) ? 52'd0 : - sfd__h600920[52:1]) : - sfd__h600920[51:0] ; - assign _theResult___snd__h356505 = { _theResult____h348383[55:0], 1'd0 } ; - assign _theResult___snd__h356516 = - (!_theResult____h348383[56] && _theResult____h348383[55]) ? - _theResult___snd__h356518 : - _theResult___snd__h356528 ; - assign _theResult___snd__h356518 = { _theResult____h348383[54:0], 2'd0 } ; - assign _theResult___snd__h356528 = - (!_theResult____h348383[56] && !_theResult____h348383[55] && - !_theResult____h348383[54] && - !_theResult____h348383[53] && - !_theResult____h348383[52] && - !_theResult____h348383[51] && - !_theResult____h348383[50] && - !_theResult____h348383[49] && - !_theResult____h348383[48] && - !_theResult____h348383[47] && - !_theResult____h348383[46] && - !_theResult____h348383[45] && - !_theResult____h348383[44] && - !_theResult____h348383[43] && - !_theResult____h348383[42] && - !_theResult____h348383[41] && - !_theResult____h348383[40] && - !_theResult____h348383[39] && - !_theResult____h348383[38] && - !_theResult____h348383[37] && - !_theResult____h348383[36] && - !_theResult____h348383[35] && - !_theResult____h348383[34] && - !_theResult____h348383[33] && - !_theResult____h348383[32] && - !_theResult____h348383[31] && - !_theResult____h348383[30] && - !_theResult____h348383[29] && - !_theResult____h348383[28] && - !_theResult____h348383[27] && - !_theResult____h348383[26] && - !_theResult____h348383[25] && - !_theResult____h348383[24] && - !_theResult____h348383[23] && - !_theResult____h348383[22] && - !_theResult____h348383[21] && - !_theResult____h348383[20] && - !_theResult____h348383[19] && - !_theResult____h348383[18] && - !_theResult____h348383[17] && - !_theResult____h348383[16] && - !_theResult____h348383[15] && - !_theResult____h348383[14] && - !_theResult____h348383[13] && - !_theResult____h348383[12] && - !_theResult____h348383[11] && - !_theResult____h348383[10] && - !_theResult____h348383[9] && - !_theResult____h348383[8] && - !_theResult____h348383[7] && - !_theResult____h348383[6] && - !_theResult____h348383[5] && - !_theResult____h348383[4] && - !_theResult____h348383[3] && - !_theResult____h348383[2] && - !_theResult____h348383[1] && - !_theResult____h348383[0]) ? - _theResult____h348383 : - _theResult___snd__h356534 ; - assign _theResult___snd__h356534 = - { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q29[54:0], + sfd__h600611[52:1]) : + sfd__h600611[51:0] ; + assign _theResult___snd__h356196 = { _theResult____h348074[55:0], 1'd0 } ; + assign _theResult___snd__h356207 = + (!_theResult____h348074[56] && _theResult____h348074[55]) ? + _theResult___snd__h356209 : + _theResult___snd__h356219 ; + assign _theResult___snd__h356209 = { _theResult____h348074[54:0], 2'd0 } ; + assign _theResult___snd__h356219 = + (!_theResult____h348074[56] && !_theResult____h348074[55] && + !_theResult____h348074[54] && + !_theResult____h348074[53] && + !_theResult____h348074[52] && + !_theResult____h348074[51] && + !_theResult____h348074[50] && + !_theResult____h348074[49] && + !_theResult____h348074[48] && + !_theResult____h348074[47] && + !_theResult____h348074[46] && + !_theResult____h348074[45] && + !_theResult____h348074[44] && + !_theResult____h348074[43] && + !_theResult____h348074[42] && + !_theResult____h348074[41] && + !_theResult____h348074[40] && + !_theResult____h348074[39] && + !_theResult____h348074[38] && + !_theResult____h348074[37] && + !_theResult____h348074[36] && + !_theResult____h348074[35] && + !_theResult____h348074[34] && + !_theResult____h348074[33] && + !_theResult____h348074[32] && + !_theResult____h348074[31] && + !_theResult____h348074[30] && + !_theResult____h348074[29] && + !_theResult____h348074[28] && + !_theResult____h348074[27] && + !_theResult____h348074[26] && + !_theResult____h348074[25] && + !_theResult____h348074[24] && + !_theResult____h348074[23] && + !_theResult____h348074[22] && + !_theResult____h348074[21] && + !_theResult____h348074[20] && + !_theResult____h348074[19] && + !_theResult____h348074[18] && + !_theResult____h348074[17] && + !_theResult____h348074[16] && + !_theResult____h348074[15] && + !_theResult____h348074[14] && + !_theResult____h348074[13] && + !_theResult____h348074[12] && + !_theResult____h348074[11] && + !_theResult____h348074[10] && + !_theResult____h348074[9] && + !_theResult____h348074[8] && + !_theResult____h348074[7] && + !_theResult____h348074[6] && + !_theResult____h348074[5] && + !_theResult____h348074[4] && + !_theResult____h348074[3] && + !_theResult____h348074[2] && + !_theResult____h348074[1] && + !_theResult____h348074[0]) ? + _theResult____h348074 : + _theResult___snd__h356225 ; + assign _theResult___snd__h356225 = + { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q21[54:0], 2'd0 } ; - assign _theResult___snd__h356557 = - _theResult____h348383 << + assign _theResult___snd__h356248 = + _theResult____h348074 << IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4343 ; - assign _theResult___snd__h365101 = + assign _theResult___snd__h364792 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___snd__h365110 : - _theResult___snd__h365103 ; - assign _theResult___snd__h365103 = + _theResult___snd__h364801 : + _theResult___snd__h364794 ; + assign _theResult___snd__h364794 = { coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5], 5'd0 } ; - assign _theResult___snd__h365110 = + assign _theResult___snd__h364801 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4519) ? - sfd__h340778 : - _theResult___snd__h365116 ; - assign _theResult___snd__h365116 = - { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q31[54:0], + sfd__h340469 : + _theResult___snd__h364807 ; + assign _theResult___snd__h364807 = + { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q23[54:0], 2'd0 } ; - assign _theResult___snd__h365139 = - sfd__h340778 << + assign _theResult___snd__h364830 = + sfd__h340469 << IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4574 ; - assign _theResult___snd__h374271 = { _theResult____h366022[55:0], 1'd0 } ; - assign _theResult___snd__h374282 = - (!_theResult____h366022[56] && _theResult____h366022[55]) ? - _theResult___snd__h374284 : - _theResult___snd__h374294 ; - assign _theResult___snd__h374284 = { _theResult____h366022[54:0], 2'd0 } ; - assign _theResult___snd__h374294 = - (!_theResult____h366022[56] && !_theResult____h366022[55] && - !_theResult____h366022[54] && - !_theResult____h366022[53] && - !_theResult____h366022[52] && - !_theResult____h366022[51] && - !_theResult____h366022[50] && - !_theResult____h366022[49] && - !_theResult____h366022[48] && - !_theResult____h366022[47] && - !_theResult____h366022[46] && - !_theResult____h366022[45] && - !_theResult____h366022[44] && - !_theResult____h366022[43] && - !_theResult____h366022[42] && - !_theResult____h366022[41] && - !_theResult____h366022[40] && - !_theResult____h366022[39] && - !_theResult____h366022[38] && - !_theResult____h366022[37] && - !_theResult____h366022[36] && - !_theResult____h366022[35] && - !_theResult____h366022[34] && - !_theResult____h366022[33] && - !_theResult____h366022[32] && - !_theResult____h366022[31] && - !_theResult____h366022[30] && - !_theResult____h366022[29] && - !_theResult____h366022[28] && - !_theResult____h366022[27] && - !_theResult____h366022[26] && - !_theResult____h366022[25] && - !_theResult____h366022[24] && - !_theResult____h366022[23] && - !_theResult____h366022[22] && - !_theResult____h366022[21] && - !_theResult____h366022[20] && - !_theResult____h366022[19] && - !_theResult____h366022[18] && - !_theResult____h366022[17] && - !_theResult____h366022[16] && - !_theResult____h366022[15] && - !_theResult____h366022[14] && - !_theResult____h366022[13] && - !_theResult____h366022[12] && - !_theResult____h366022[11] && - !_theResult____h366022[10] && - !_theResult____h366022[9] && - !_theResult____h366022[8] && - !_theResult____h366022[7] && - !_theResult____h366022[6] && - !_theResult____h366022[5] && - !_theResult____h366022[4] && - !_theResult____h366022[3] && - !_theResult____h366022[2] && - !_theResult____h366022[1] && - !_theResult____h366022[0]) ? - _theResult____h366022 : - _theResult___snd__h374300 ; - assign _theResult___snd__h374300 = - { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q39[54:0], + assign _theResult___snd__h373962 = { _theResult____h365713[55:0], 1'd0 } ; + assign _theResult___snd__h373973 = + (!_theResult____h365713[56] && _theResult____h365713[55]) ? + _theResult___snd__h373975 : + _theResult___snd__h373985 ; + assign _theResult___snd__h373975 = { _theResult____h365713[54:0], 2'd0 } ; + assign _theResult___snd__h373985 = + (!_theResult____h365713[56] && !_theResult____h365713[55] && + !_theResult____h365713[54] && + !_theResult____h365713[53] && + !_theResult____h365713[52] && + !_theResult____h365713[51] && + !_theResult____h365713[50] && + !_theResult____h365713[49] && + !_theResult____h365713[48] && + !_theResult____h365713[47] && + !_theResult____h365713[46] && + !_theResult____h365713[45] && + !_theResult____h365713[44] && + !_theResult____h365713[43] && + !_theResult____h365713[42] && + !_theResult____h365713[41] && + !_theResult____h365713[40] && + !_theResult____h365713[39] && + !_theResult____h365713[38] && + !_theResult____h365713[37] && + !_theResult____h365713[36] && + !_theResult____h365713[35] && + !_theResult____h365713[34] && + !_theResult____h365713[33] && + !_theResult____h365713[32] && + !_theResult____h365713[31] && + !_theResult____h365713[30] && + !_theResult____h365713[29] && + !_theResult____h365713[28] && + !_theResult____h365713[27] && + !_theResult____h365713[26] && + !_theResult____h365713[25] && + !_theResult____h365713[24] && + !_theResult____h365713[23] && + !_theResult____h365713[22] && + !_theResult____h365713[21] && + !_theResult____h365713[20] && + !_theResult____h365713[19] && + !_theResult____h365713[18] && + !_theResult____h365713[17] && + !_theResult____h365713[16] && + !_theResult____h365713[15] && + !_theResult____h365713[14] && + !_theResult____h365713[13] && + !_theResult____h365713[12] && + !_theResult____h365713[11] && + !_theResult____h365713[10] && + !_theResult____h365713[9] && + !_theResult____h365713[8] && + !_theResult____h365713[7] && + !_theResult____h365713[6] && + !_theResult____h365713[5] && + !_theResult____h365713[4] && + !_theResult____h365713[3] && + !_theResult____h365713[2] && + !_theResult____h365713[1] && + !_theResult____h365713[0]) ? + _theResult____h365713 : + _theResult___snd__h373991 ; + assign _theResult___snd__h373991 = + { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q31[54:0], 2'd0 } ; - assign _theResult___snd__h374323 = - _theResult____h366022 << + assign _theResult___snd__h374014 = + _theResult____h365713 << IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4894 ; - assign _theResult___snd__h382891 = + assign _theResult___snd__h382582 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___snd__h382905 : - _theResult___snd__h365103 ; - assign _theResult___snd__h382905 = + _theResult___snd__h382596 : + _theResult___snd__h364794 ; + assign _theResult___snd__h382596 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4519) ? - sfd__h340778 : - _theResult___snd__h382911 ; - assign _theResult___snd__h382911 = - { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q44[54:0], + sfd__h340469 : + _theResult___snd__h382602 ; + assign _theResult___snd__h382602 = + { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q36[54:0], 2'd0 } ; - assign _theResult___snd__h382929 = - sfd__h340778 << + assign _theResult___snd__h382620 = + sfd__h340469 << (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4968[8] ? 9'h0AA : IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4968) ; - assign _theResult___snd__h402202 = { _theResult____h394082[55:0], 1'd0 } ; - assign _theResult___snd__h402213 = - (!_theResult____h394082[56] && _theResult____h394082[55]) ? - _theResult___snd__h402215 : - _theResult___snd__h402225 ; - assign _theResult___snd__h402215 = { _theResult____h394082[54:0], 2'd0 } ; - assign _theResult___snd__h402225 = - (!_theResult____h394082[56] && !_theResult____h394082[55] && - !_theResult____h394082[54] && - !_theResult____h394082[53] && - !_theResult____h394082[52] && - !_theResult____h394082[51] && - !_theResult____h394082[50] && - !_theResult____h394082[49] && - !_theResult____h394082[48] && - !_theResult____h394082[47] && - !_theResult____h394082[46] && - !_theResult____h394082[45] && - !_theResult____h394082[44] && - !_theResult____h394082[43] && - !_theResult____h394082[42] && - !_theResult____h394082[41] && - !_theResult____h394082[40] && - !_theResult____h394082[39] && - !_theResult____h394082[38] && - !_theResult____h394082[37] && - !_theResult____h394082[36] && - !_theResult____h394082[35] && - !_theResult____h394082[34] && - !_theResult____h394082[33] && - !_theResult____h394082[32] && - !_theResult____h394082[31] && - !_theResult____h394082[30] && - !_theResult____h394082[29] && - !_theResult____h394082[28] && - !_theResult____h394082[27] && - !_theResult____h394082[26] && - !_theResult____h394082[25] && - !_theResult____h394082[24] && - !_theResult____h394082[23] && - !_theResult____h394082[22] && - !_theResult____h394082[21] && - !_theResult____h394082[20] && - !_theResult____h394082[19] && - !_theResult____h394082[18] && - !_theResult____h394082[17] && - !_theResult____h394082[16] && - !_theResult____h394082[15] && - !_theResult____h394082[14] && - !_theResult____h394082[13] && - !_theResult____h394082[12] && - !_theResult____h394082[11] && - !_theResult____h394082[10] && - !_theResult____h394082[9] && - !_theResult____h394082[8] && - !_theResult____h394082[7] && - !_theResult____h394082[6] && - !_theResult____h394082[5] && - !_theResult____h394082[4] && - !_theResult____h394082[3] && - !_theResult____h394082[2] && - !_theResult____h394082[1] && - !_theResult____h394082[0]) ? - _theResult____h394082 : - _theResult___snd__h402231 ; - assign _theResult___snd__h402231 = - { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q64[54:0], + assign _theResult___snd__h401893 = { _theResult____h393773[55:0], 1'd0 } ; + assign _theResult___snd__h401904 = + (!_theResult____h393773[56] && _theResult____h393773[55]) ? + _theResult___snd__h401906 : + _theResult___snd__h401916 ; + assign _theResult___snd__h401906 = { _theResult____h393773[54:0], 2'd0 } ; + assign _theResult___snd__h401916 = + (!_theResult____h393773[56] && !_theResult____h393773[55] && + !_theResult____h393773[54] && + !_theResult____h393773[53] && + !_theResult____h393773[52] && + !_theResult____h393773[51] && + !_theResult____h393773[50] && + !_theResult____h393773[49] && + !_theResult____h393773[48] && + !_theResult____h393773[47] && + !_theResult____h393773[46] && + !_theResult____h393773[45] && + !_theResult____h393773[44] && + !_theResult____h393773[43] && + !_theResult____h393773[42] && + !_theResult____h393773[41] && + !_theResult____h393773[40] && + !_theResult____h393773[39] && + !_theResult____h393773[38] && + !_theResult____h393773[37] && + !_theResult____h393773[36] && + !_theResult____h393773[35] && + !_theResult____h393773[34] && + !_theResult____h393773[33] && + !_theResult____h393773[32] && + !_theResult____h393773[31] && + !_theResult____h393773[30] && + !_theResult____h393773[29] && + !_theResult____h393773[28] && + !_theResult____h393773[27] && + !_theResult____h393773[26] && + !_theResult____h393773[25] && + !_theResult____h393773[24] && + !_theResult____h393773[23] && + !_theResult____h393773[22] && + !_theResult____h393773[21] && + !_theResult____h393773[20] && + !_theResult____h393773[19] && + !_theResult____h393773[18] && + !_theResult____h393773[17] && + !_theResult____h393773[16] && + !_theResult____h393773[15] && + !_theResult____h393773[14] && + !_theResult____h393773[13] && + !_theResult____h393773[12] && + !_theResult____h393773[11] && + !_theResult____h393773[10] && + !_theResult____h393773[9] && + !_theResult____h393773[8] && + !_theResult____h393773[7] && + !_theResult____h393773[6] && + !_theResult____h393773[5] && + !_theResult____h393773[4] && + !_theResult____h393773[3] && + !_theResult____h393773[2] && + !_theResult____h393773[1] && + !_theResult____h393773[0]) ? + _theResult____h393773 : + _theResult___snd__h401922 ; + assign _theResult___snd__h401922 = + { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q56[54:0], 2'd0 } ; - assign _theResult___snd__h402254 = - _theResult____h394082 << + assign _theResult___snd__h401945 = + _theResult____h393773 << IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5735 ; - assign _theResult___snd__h410798 = + assign _theResult___snd__h410489 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___snd__h410807 : - _theResult___snd__h410800 ; - assign _theResult___snd__h410800 = + _theResult___snd__h410498 : + _theResult___snd__h410491 ; + assign _theResult___snd__h410491 = { coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5], 5'd0 } ; - assign _theResult___snd__h410807 = + assign _theResult___snd__h410498 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5911) ? - sfd__h386480 : - _theResult___snd__h410813 ; - assign _theResult___snd__h410813 = - { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q66[54:0], + sfd__h386171 : + _theResult___snd__h410504 ; + assign _theResult___snd__h410504 = + { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q58[54:0], 2'd0 } ; - assign _theResult___snd__h410836 = - sfd__h386480 << + assign _theResult___snd__h410527 = + sfd__h386171 << IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5966 ; - assign _theResult___snd__h419968 = { _theResult____h411719[55:0], 1'd0 } ; - assign _theResult___snd__h419979 = - (!_theResult____h411719[56] && _theResult____h411719[55]) ? - _theResult___snd__h419981 : - _theResult___snd__h419991 ; - assign _theResult___snd__h419981 = { _theResult____h411719[54:0], 2'd0 } ; - assign _theResult___snd__h419991 = - (!_theResult____h411719[56] && !_theResult____h411719[55] && - !_theResult____h411719[54] && - !_theResult____h411719[53] && - !_theResult____h411719[52] && - !_theResult____h411719[51] && - !_theResult____h411719[50] && - !_theResult____h411719[49] && - !_theResult____h411719[48] && - !_theResult____h411719[47] && - !_theResult____h411719[46] && - !_theResult____h411719[45] && - !_theResult____h411719[44] && - !_theResult____h411719[43] && - !_theResult____h411719[42] && - !_theResult____h411719[41] && - !_theResult____h411719[40] && - !_theResult____h411719[39] && - !_theResult____h411719[38] && - !_theResult____h411719[37] && - !_theResult____h411719[36] && - !_theResult____h411719[35] && - !_theResult____h411719[34] && - !_theResult____h411719[33] && - !_theResult____h411719[32] && - !_theResult____h411719[31] && - !_theResult____h411719[30] && - !_theResult____h411719[29] && - !_theResult____h411719[28] && - !_theResult____h411719[27] && - !_theResult____h411719[26] && - !_theResult____h411719[25] && - !_theResult____h411719[24] && - !_theResult____h411719[23] && - !_theResult____h411719[22] && - !_theResult____h411719[21] && - !_theResult____h411719[20] && - !_theResult____h411719[19] && - !_theResult____h411719[18] && - !_theResult____h411719[17] && - !_theResult____h411719[16] && - !_theResult____h411719[15] && - !_theResult____h411719[14] && - !_theResult____h411719[13] && - !_theResult____h411719[12] && - !_theResult____h411719[11] && - !_theResult____h411719[10] && - !_theResult____h411719[9] && - !_theResult____h411719[8] && - !_theResult____h411719[7] && - !_theResult____h411719[6] && - !_theResult____h411719[5] && - !_theResult____h411719[4] && - !_theResult____h411719[3] && - !_theResult____h411719[2] && - !_theResult____h411719[1] && - !_theResult____h411719[0]) ? - _theResult____h411719 : - _theResult___snd__h419997 ; - assign _theResult___snd__h419997 = - { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q74[54:0], + assign _theResult___snd__h419659 = { _theResult____h411410[55:0], 1'd0 } ; + assign _theResult___snd__h419670 = + (!_theResult____h411410[56] && _theResult____h411410[55]) ? + _theResult___snd__h419672 : + _theResult___snd__h419682 ; + assign _theResult___snd__h419672 = { _theResult____h411410[54:0], 2'd0 } ; + assign _theResult___snd__h419682 = + (!_theResult____h411410[56] && !_theResult____h411410[55] && + !_theResult____h411410[54] && + !_theResult____h411410[53] && + !_theResult____h411410[52] && + !_theResult____h411410[51] && + !_theResult____h411410[50] && + !_theResult____h411410[49] && + !_theResult____h411410[48] && + !_theResult____h411410[47] && + !_theResult____h411410[46] && + !_theResult____h411410[45] && + !_theResult____h411410[44] && + !_theResult____h411410[43] && + !_theResult____h411410[42] && + !_theResult____h411410[41] && + !_theResult____h411410[40] && + !_theResult____h411410[39] && + !_theResult____h411410[38] && + !_theResult____h411410[37] && + !_theResult____h411410[36] && + !_theResult____h411410[35] && + !_theResult____h411410[34] && + !_theResult____h411410[33] && + !_theResult____h411410[32] && + !_theResult____h411410[31] && + !_theResult____h411410[30] && + !_theResult____h411410[29] && + !_theResult____h411410[28] && + !_theResult____h411410[27] && + !_theResult____h411410[26] && + !_theResult____h411410[25] && + !_theResult____h411410[24] && + !_theResult____h411410[23] && + !_theResult____h411410[22] && + !_theResult____h411410[21] && + !_theResult____h411410[20] && + !_theResult____h411410[19] && + !_theResult____h411410[18] && + !_theResult____h411410[17] && + !_theResult____h411410[16] && + !_theResult____h411410[15] && + !_theResult____h411410[14] && + !_theResult____h411410[13] && + !_theResult____h411410[12] && + !_theResult____h411410[11] && + !_theResult____h411410[10] && + !_theResult____h411410[9] && + !_theResult____h411410[8] && + !_theResult____h411410[7] && + !_theResult____h411410[6] && + !_theResult____h411410[5] && + !_theResult____h411410[4] && + !_theResult____h411410[3] && + !_theResult____h411410[2] && + !_theResult____h411410[1] && + !_theResult____h411410[0]) ? + _theResult____h411410 : + _theResult___snd__h419688 ; + assign _theResult___snd__h419688 = + { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q66[54:0], 2'd0 } ; - assign _theResult___snd__h420020 = - _theResult____h411719 << + assign _theResult___snd__h419711 = + _theResult____h411410 << IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6286 ; - assign _theResult___snd__h428588 = + assign _theResult___snd__h428279 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___snd__h428602 : - _theResult___snd__h410800 ; - assign _theResult___snd__h428602 = + _theResult___snd__h428293 : + _theResult___snd__h410491 ; + assign _theResult___snd__h428293 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5911) ? - sfd__h386480 : - _theResult___snd__h428608 ; - assign _theResult___snd__h428608 = - { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q79[54:0], + sfd__h386171 : + _theResult___snd__h428299 ; + assign _theResult___snd__h428299 = + { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q71[54:0], 2'd0 } ; - assign _theResult___snd__h428626 = - sfd__h386480 << + assign _theResult___snd__h428317 = + sfd__h386171 << (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6360[8] ? 9'h0AA : IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6360) ; - assign _theResult___snd__h447897 = { _theResult____h439777[55:0], 1'd0 } ; - assign _theResult___snd__h447908 = - (!_theResult____h439777[56] && _theResult____h439777[55]) ? - _theResult___snd__h447910 : - _theResult___snd__h447920 ; - assign _theResult___snd__h447910 = { _theResult____h439777[54:0], 2'd0 } ; - assign _theResult___snd__h447920 = - (!_theResult____h439777[56] && !_theResult____h439777[55] && - !_theResult____h439777[54] && - !_theResult____h439777[53] && - !_theResult____h439777[52] && - !_theResult____h439777[51] && - !_theResult____h439777[50] && - !_theResult____h439777[49] && - !_theResult____h439777[48] && - !_theResult____h439777[47] && - !_theResult____h439777[46] && - !_theResult____h439777[45] && - !_theResult____h439777[44] && - !_theResult____h439777[43] && - !_theResult____h439777[42] && - !_theResult____h439777[41] && - !_theResult____h439777[40] && - !_theResult____h439777[39] && - !_theResult____h439777[38] && - !_theResult____h439777[37] && - !_theResult____h439777[36] && - !_theResult____h439777[35] && - !_theResult____h439777[34] && - !_theResult____h439777[33] && - !_theResult____h439777[32] && - !_theResult____h439777[31] && - !_theResult____h439777[30] && - !_theResult____h439777[29] && - !_theResult____h439777[28] && - !_theResult____h439777[27] && - !_theResult____h439777[26] && - !_theResult____h439777[25] && - !_theResult____h439777[24] && - !_theResult____h439777[23] && - !_theResult____h439777[22] && - !_theResult____h439777[21] && - !_theResult____h439777[20] && - !_theResult____h439777[19] && - !_theResult____h439777[18] && - !_theResult____h439777[17] && - !_theResult____h439777[16] && - !_theResult____h439777[15] && - !_theResult____h439777[14] && - !_theResult____h439777[13] && - !_theResult____h439777[12] && - !_theResult____h439777[11] && - !_theResult____h439777[10] && - !_theResult____h439777[9] && - !_theResult____h439777[8] && - !_theResult____h439777[7] && - !_theResult____h439777[6] && - !_theResult____h439777[5] && - !_theResult____h439777[4] && - !_theResult____h439777[3] && - !_theResult____h439777[2] && - !_theResult____h439777[1] && - !_theResult____h439777[0]) ? - _theResult____h439777 : - _theResult___snd__h447926 ; - assign _theResult___snd__h447926 = - { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q99[54:0], + assign _theResult___snd__h447588 = { _theResult____h439468[55:0], 1'd0 } ; + assign _theResult___snd__h447599 = + (!_theResult____h439468[56] && _theResult____h439468[55]) ? + _theResult___snd__h447601 : + _theResult___snd__h447611 ; + assign _theResult___snd__h447601 = { _theResult____h439468[54:0], 2'd0 } ; + assign _theResult___snd__h447611 = + (!_theResult____h439468[56] && !_theResult____h439468[55] && + !_theResult____h439468[54] && + !_theResult____h439468[53] && + !_theResult____h439468[52] && + !_theResult____h439468[51] && + !_theResult____h439468[50] && + !_theResult____h439468[49] && + !_theResult____h439468[48] && + !_theResult____h439468[47] && + !_theResult____h439468[46] && + !_theResult____h439468[45] && + !_theResult____h439468[44] && + !_theResult____h439468[43] && + !_theResult____h439468[42] && + !_theResult____h439468[41] && + !_theResult____h439468[40] && + !_theResult____h439468[39] && + !_theResult____h439468[38] && + !_theResult____h439468[37] && + !_theResult____h439468[36] && + !_theResult____h439468[35] && + !_theResult____h439468[34] && + !_theResult____h439468[33] && + !_theResult____h439468[32] && + !_theResult____h439468[31] && + !_theResult____h439468[30] && + !_theResult____h439468[29] && + !_theResult____h439468[28] && + !_theResult____h439468[27] && + !_theResult____h439468[26] && + !_theResult____h439468[25] && + !_theResult____h439468[24] && + !_theResult____h439468[23] && + !_theResult____h439468[22] && + !_theResult____h439468[21] && + !_theResult____h439468[20] && + !_theResult____h439468[19] && + !_theResult____h439468[18] && + !_theResult____h439468[17] && + !_theResult____h439468[16] && + !_theResult____h439468[15] && + !_theResult____h439468[14] && + !_theResult____h439468[13] && + !_theResult____h439468[12] && + !_theResult____h439468[11] && + !_theResult____h439468[10] && + !_theResult____h439468[9] && + !_theResult____h439468[8] && + !_theResult____h439468[7] && + !_theResult____h439468[6] && + !_theResult____h439468[5] && + !_theResult____h439468[4] && + !_theResult____h439468[3] && + !_theResult____h439468[2] && + !_theResult____h439468[1] && + !_theResult____h439468[0]) ? + _theResult____h439468 : + _theResult___snd__h447617 ; + assign _theResult___snd__h447617 = + { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q91[54:0], 2'd0 } ; - assign _theResult___snd__h447949 = - _theResult____h439777 << + assign _theResult___snd__h447640 = + _theResult____h439468 << IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7127 ; - assign _theResult___snd__h456493 = + assign _theResult___snd__h456184 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___snd__h456502 : - _theResult___snd__h456495 ; - assign _theResult___snd__h456495 = + _theResult___snd__h456193 : + _theResult___snd__h456186 ; + assign _theResult___snd__h456186 = { coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5], 5'd0 } ; - assign _theResult___snd__h456502 = + assign _theResult___snd__h456193 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7303) ? - sfd__h432175 : - _theResult___snd__h456508 ; - assign _theResult___snd__h456508 = - { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q101[54:0], + sfd__h431866 : + _theResult___snd__h456199 ; + assign _theResult___snd__h456199 = + { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q93[54:0], 2'd0 } ; - assign _theResult___snd__h456531 = - sfd__h432175 << + assign _theResult___snd__h456222 = + sfd__h431866 << IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7358 ; - assign _theResult___snd__h465663 = { _theResult____h457414[55:0], 1'd0 } ; - assign _theResult___snd__h465674 = - (!_theResult____h457414[56] && _theResult____h457414[55]) ? - _theResult___snd__h465676 : - _theResult___snd__h465686 ; - assign _theResult___snd__h465676 = { _theResult____h457414[54:0], 2'd0 } ; - assign _theResult___snd__h465686 = - (!_theResult____h457414[56] && !_theResult____h457414[55] && - !_theResult____h457414[54] && - !_theResult____h457414[53] && - !_theResult____h457414[52] && - !_theResult____h457414[51] && - !_theResult____h457414[50] && - !_theResult____h457414[49] && - !_theResult____h457414[48] && - !_theResult____h457414[47] && - !_theResult____h457414[46] && - !_theResult____h457414[45] && - !_theResult____h457414[44] && - !_theResult____h457414[43] && - !_theResult____h457414[42] && - !_theResult____h457414[41] && - !_theResult____h457414[40] && - !_theResult____h457414[39] && - !_theResult____h457414[38] && - !_theResult____h457414[37] && - !_theResult____h457414[36] && - !_theResult____h457414[35] && - !_theResult____h457414[34] && - !_theResult____h457414[33] && - !_theResult____h457414[32] && - !_theResult____h457414[31] && - !_theResult____h457414[30] && - !_theResult____h457414[29] && - !_theResult____h457414[28] && - !_theResult____h457414[27] && - !_theResult____h457414[26] && - !_theResult____h457414[25] && - !_theResult____h457414[24] && - !_theResult____h457414[23] && - !_theResult____h457414[22] && - !_theResult____h457414[21] && - !_theResult____h457414[20] && - !_theResult____h457414[19] && - !_theResult____h457414[18] && - !_theResult____h457414[17] && - !_theResult____h457414[16] && - !_theResult____h457414[15] && - !_theResult____h457414[14] && - !_theResult____h457414[13] && - !_theResult____h457414[12] && - !_theResult____h457414[11] && - !_theResult____h457414[10] && - !_theResult____h457414[9] && - !_theResult____h457414[8] && - !_theResult____h457414[7] && - !_theResult____h457414[6] && - !_theResult____h457414[5] && - !_theResult____h457414[4] && - !_theResult____h457414[3] && - !_theResult____h457414[2] && - !_theResult____h457414[1] && - !_theResult____h457414[0]) ? - _theResult____h457414 : - _theResult___snd__h465692 ; - assign _theResult___snd__h465692 = - { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q109[54:0], + assign _theResult___snd__h465354 = { _theResult____h457105[55:0], 1'd0 } ; + assign _theResult___snd__h465365 = + (!_theResult____h457105[56] && _theResult____h457105[55]) ? + _theResult___snd__h465367 : + _theResult___snd__h465377 ; + assign _theResult___snd__h465367 = { _theResult____h457105[54:0], 2'd0 } ; + assign _theResult___snd__h465377 = + (!_theResult____h457105[56] && !_theResult____h457105[55] && + !_theResult____h457105[54] && + !_theResult____h457105[53] && + !_theResult____h457105[52] && + !_theResult____h457105[51] && + !_theResult____h457105[50] && + !_theResult____h457105[49] && + !_theResult____h457105[48] && + !_theResult____h457105[47] && + !_theResult____h457105[46] && + !_theResult____h457105[45] && + !_theResult____h457105[44] && + !_theResult____h457105[43] && + !_theResult____h457105[42] && + !_theResult____h457105[41] && + !_theResult____h457105[40] && + !_theResult____h457105[39] && + !_theResult____h457105[38] && + !_theResult____h457105[37] && + !_theResult____h457105[36] && + !_theResult____h457105[35] && + !_theResult____h457105[34] && + !_theResult____h457105[33] && + !_theResult____h457105[32] && + !_theResult____h457105[31] && + !_theResult____h457105[30] && + !_theResult____h457105[29] && + !_theResult____h457105[28] && + !_theResult____h457105[27] && + !_theResult____h457105[26] && + !_theResult____h457105[25] && + !_theResult____h457105[24] && + !_theResult____h457105[23] && + !_theResult____h457105[22] && + !_theResult____h457105[21] && + !_theResult____h457105[20] && + !_theResult____h457105[19] && + !_theResult____h457105[18] && + !_theResult____h457105[17] && + !_theResult____h457105[16] && + !_theResult____h457105[15] && + !_theResult____h457105[14] && + !_theResult____h457105[13] && + !_theResult____h457105[12] && + !_theResult____h457105[11] && + !_theResult____h457105[10] && + !_theResult____h457105[9] && + !_theResult____h457105[8] && + !_theResult____h457105[7] && + !_theResult____h457105[6] && + !_theResult____h457105[5] && + !_theResult____h457105[4] && + !_theResult____h457105[3] && + !_theResult____h457105[2] && + !_theResult____h457105[1] && + !_theResult____h457105[0]) ? + _theResult____h457105 : + _theResult___snd__h465383 ; + assign _theResult___snd__h465383 = + { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q101[54:0], 2'd0 } ; - assign _theResult___snd__h465715 = - _theResult____h457414 << + assign _theResult___snd__h465406 = + _theResult____h457105 << IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7678 ; - assign _theResult___snd__h474283 = + assign _theResult___snd__h473974 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___snd__h474297 : - _theResult___snd__h456495 ; - assign _theResult___snd__h474297 = + _theResult___snd__h473988 : + _theResult___snd__h456186 ; + assign _theResult___snd__h473988 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7303) ? - sfd__h432175 : - _theResult___snd__h474303 ; - assign _theResult___snd__h474303 = - { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q114[54:0], + sfd__h431866 : + _theResult___snd__h473994 ; + assign _theResult___snd__h473994 = + { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q106[54:0], 2'd0 } ; - assign _theResult___snd__h474321 = - sfd__h432175 << + assign _theResult___snd__h474012 = + sfd__h431866 << (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7752[8] ? 9'h0AA : IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7752) ; - assign _theResult___snd__h504285 = - (f1_exp__h484946 == 8'd0) ? - _theResult___snd__h504294 : - _theResult___snd__h504287 ; - assign _theResult___snd__h504287 = { f1_sfd__h484947, 34'd0 } ; - assign _theResult___snd__h504294 = - (f1_exp__h484946 == 8'd0 && !f1_sfd__h484947[22] && + assign _theResult___snd__h503976 = + (f1_exp__h484637 == 8'd0) ? + _theResult___snd__h503985 : + _theResult___snd__h503978 ; + assign _theResult___snd__h503978 = { f1_sfd__h484638, 34'd0 } ; + assign _theResult___snd__h503985 = + (f1_exp__h484637 == 8'd0 && !f1_sfd__h484638[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8667) ? - sfd__h485308 : - _theResult___snd__h504300 ; - assign _theResult___snd__h504300 = - { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q134[54:0], + sfd__h484999 : + _theResult___snd__h503991 ; + assign _theResult___snd__h503991 = + { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q126[54:0], 2'd0 } ; - assign _theResult___snd__h504323 = - sfd__h485308 << + assign _theResult___snd__h504014 = + sfd__h484999 << IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8694 ; - assign _theResult___snd__h513922 = { _theResult____h505675[55:0], 1'd0 } ; - assign _theResult___snd__h513933 = - (!_theResult____h505675[56] && _theResult____h505675[55]) ? - _theResult___snd__h513935 : - _theResult___snd__h513945 ; - assign _theResult___snd__h513935 = { _theResult____h505675[54:0], 2'd0 } ; - assign _theResult___snd__h513945 = - (!_theResult____h505675[56] && !_theResult____h505675[55] && - !_theResult____h505675[54] && - !_theResult____h505675[53] && - !_theResult____h505675[52] && - !_theResult____h505675[51] && - !_theResult____h505675[50] && - !_theResult____h505675[49] && - !_theResult____h505675[48] && - !_theResult____h505675[47] && - !_theResult____h505675[46] && - !_theResult____h505675[45] && - !_theResult____h505675[44] && - !_theResult____h505675[43] && - !_theResult____h505675[42] && - !_theResult____h505675[41] && - !_theResult____h505675[40] && - !_theResult____h505675[39] && - !_theResult____h505675[38] && - !_theResult____h505675[37] && - !_theResult____h505675[36] && - !_theResult____h505675[35] && - !_theResult____h505675[34] && - !_theResult____h505675[33] && - !_theResult____h505675[32] && - !_theResult____h505675[31] && - !_theResult____h505675[30] && - !_theResult____h505675[29] && - !_theResult____h505675[28] && - !_theResult____h505675[27] && - !_theResult____h505675[26] && - !_theResult____h505675[25] && - !_theResult____h505675[24] && - !_theResult____h505675[23] && - !_theResult____h505675[22] && - !_theResult____h505675[21] && - !_theResult____h505675[20] && - !_theResult____h505675[19] && - !_theResult____h505675[18] && - !_theResult____h505675[17] && - !_theResult____h505675[16] && - !_theResult____h505675[15] && - !_theResult____h505675[14] && - !_theResult____h505675[13] && - !_theResult____h505675[12] && - !_theResult____h505675[11] && - !_theResult____h505675[10] && - !_theResult____h505675[9] && - !_theResult____h505675[8] && - !_theResult____h505675[7] && - !_theResult____h505675[6] && - !_theResult____h505675[5] && - !_theResult____h505675[4] && - !_theResult____h505675[3] && - !_theResult____h505675[2] && - !_theResult____h505675[1] && - !_theResult____h505675[0]) ? - _theResult____h505675 : - _theResult___snd__h513951 ; - assign _theResult___snd__h513951 = - { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q138[54:0], + assign _theResult___snd__h513613 = { _theResult____h505366[55:0], 1'd0 } ; + assign _theResult___snd__h513624 = + (!_theResult____h505366[56] && _theResult____h505366[55]) ? + _theResult___snd__h513626 : + _theResult___snd__h513636 ; + assign _theResult___snd__h513626 = { _theResult____h505366[54:0], 2'd0 } ; + assign _theResult___snd__h513636 = + (!_theResult____h505366[56] && !_theResult____h505366[55] && + !_theResult____h505366[54] && + !_theResult____h505366[53] && + !_theResult____h505366[52] && + !_theResult____h505366[51] && + !_theResult____h505366[50] && + !_theResult____h505366[49] && + !_theResult____h505366[48] && + !_theResult____h505366[47] && + !_theResult____h505366[46] && + !_theResult____h505366[45] && + !_theResult____h505366[44] && + !_theResult____h505366[43] && + !_theResult____h505366[42] && + !_theResult____h505366[41] && + !_theResult____h505366[40] && + !_theResult____h505366[39] && + !_theResult____h505366[38] && + !_theResult____h505366[37] && + !_theResult____h505366[36] && + !_theResult____h505366[35] && + !_theResult____h505366[34] && + !_theResult____h505366[33] && + !_theResult____h505366[32] && + !_theResult____h505366[31] && + !_theResult____h505366[30] && + !_theResult____h505366[29] && + !_theResult____h505366[28] && + !_theResult____h505366[27] && + !_theResult____h505366[26] && + !_theResult____h505366[25] && + !_theResult____h505366[24] && + !_theResult____h505366[23] && + !_theResult____h505366[22] && + !_theResult____h505366[21] && + !_theResult____h505366[20] && + !_theResult____h505366[19] && + !_theResult____h505366[18] && + !_theResult____h505366[17] && + !_theResult____h505366[16] && + !_theResult____h505366[15] && + !_theResult____h505366[14] && + !_theResult____h505366[13] && + !_theResult____h505366[12] && + !_theResult____h505366[11] && + !_theResult____h505366[10] && + !_theResult____h505366[9] && + !_theResult____h505366[8] && + !_theResult____h505366[7] && + !_theResult____h505366[6] && + !_theResult____h505366[5] && + !_theResult____h505366[4] && + !_theResult____h505366[3] && + !_theResult____h505366[2] && + !_theResult____h505366[1] && + !_theResult____h505366[0]) ? + _theResult____h505366 : + _theResult___snd__h513642 ; + assign _theResult___snd__h513642 = + { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q130[54:0], 2'd0 } ; - assign _theResult___snd__h513974 = - _theResult____h505675 << + assign _theResult___snd__h513665 = + _theResult____h505366 << IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9006 ; - assign _theResult___snd__h522690 = - (f1_exp__h484946 == 8'd0) ? - _theResult___snd__h522704 : - _theResult___snd__h504287 ; - assign _theResult___snd__h522704 = - (f1_exp__h484946 == 8'd0 && !f1_sfd__h484947[22] && + assign _theResult___snd__h522381 = + (f1_exp__h484637 == 8'd0) ? + _theResult___snd__h522395 : + _theResult___snd__h503978 ; + assign _theResult___snd__h522395 = + (f1_exp__h484637 == 8'd0 && !f1_sfd__h484638[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8667) ? - sfd__h485308 : - _theResult___snd__h522710 ; - assign _theResult___snd__h522710 = - { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q141[54:0], + sfd__h484999 : + _theResult___snd__h522401 ; + assign _theResult___snd__h522401 = + { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q133[54:0], 2'd0 } ; - assign _theResult___snd__h522728 = - sfd__h485308 << + assign _theResult___snd__h522419 = + sfd__h484999 << IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9057 ; - assign _theResult___snd__h543138 = - (f2_exp__h523940 == 8'd0) ? - _theResult___snd__h543147 : - _theResult___snd__h543140 ; - assign _theResult___snd__h543140 = { f2_sfd__h523941, 34'd0 } ; - assign _theResult___snd__h543147 = - (f2_exp__h523940 == 8'd0 && !f2_sfd__h523941[22] && + assign _theResult___snd__h542829 = + (f2_exp__h523631 == 8'd0) ? + _theResult___snd__h542838 : + _theResult___snd__h542831 ; + assign _theResult___snd__h542831 = { f2_sfd__h523632, 34'd0 } ; + assign _theResult___snd__h542838 = + (f2_exp__h523631 == 8'd0 && !f2_sfd__h523632[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10167) ? - sfd__h524302 : - _theResult___snd__h543153 ; - assign _theResult___snd__h543153 = - { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q174[54:0], + sfd__h523993 : + _theResult___snd__h542844 ; + assign _theResult___snd__h542844 = + { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q166[54:0], 2'd0 } ; - assign _theResult___snd__h543176 = - sfd__h524302 << + assign _theResult___snd__h542867 = + sfd__h523993 << IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10194 ; - assign _theResult___snd__h552775 = { _theResult____h544528[55:0], 1'd0 } ; - assign _theResult___snd__h552786 = - (!_theResult____h544528[56] && _theResult____h544528[55]) ? - _theResult___snd__h552788 : - _theResult___snd__h552798 ; - assign _theResult___snd__h552788 = { _theResult____h544528[54:0], 2'd0 } ; - assign _theResult___snd__h552798 = - (!_theResult____h544528[56] && !_theResult____h544528[55] && - !_theResult____h544528[54] && - !_theResult____h544528[53] && - !_theResult____h544528[52] && - !_theResult____h544528[51] && - !_theResult____h544528[50] && - !_theResult____h544528[49] && - !_theResult____h544528[48] && - !_theResult____h544528[47] && - !_theResult____h544528[46] && - !_theResult____h544528[45] && - !_theResult____h544528[44] && - !_theResult____h544528[43] && - !_theResult____h544528[42] && - !_theResult____h544528[41] && - !_theResult____h544528[40] && - !_theResult____h544528[39] && - !_theResult____h544528[38] && - !_theResult____h544528[37] && - !_theResult____h544528[36] && - !_theResult____h544528[35] && - !_theResult____h544528[34] && - !_theResult____h544528[33] && - !_theResult____h544528[32] && - !_theResult____h544528[31] && - !_theResult____h544528[30] && - !_theResult____h544528[29] && - !_theResult____h544528[28] && - !_theResult____h544528[27] && - !_theResult____h544528[26] && - !_theResult____h544528[25] && - !_theResult____h544528[24] && - !_theResult____h544528[23] && - !_theResult____h544528[22] && - !_theResult____h544528[21] && - !_theResult____h544528[20] && - !_theResult____h544528[19] && - !_theResult____h544528[18] && - !_theResult____h544528[17] && - !_theResult____h544528[16] && - !_theResult____h544528[15] && - !_theResult____h544528[14] && - !_theResult____h544528[13] && - !_theResult____h544528[12] && - !_theResult____h544528[11] && - !_theResult____h544528[10] && - !_theResult____h544528[9] && - !_theResult____h544528[8] && - !_theResult____h544528[7] && - !_theResult____h544528[6] && - !_theResult____h544528[5] && - !_theResult____h544528[4] && - !_theResult____h544528[3] && - !_theResult____h544528[2] && - !_theResult____h544528[1] && - !_theResult____h544528[0]) ? - _theResult____h544528 : - _theResult___snd__h552804 ; - assign _theResult___snd__h552804 = - { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q178[54:0], + assign _theResult___snd__h552466 = { _theResult____h544219[55:0], 1'd0 } ; + assign _theResult___snd__h552477 = + (!_theResult____h544219[56] && _theResult____h544219[55]) ? + _theResult___snd__h552479 : + _theResult___snd__h552489 ; + assign _theResult___snd__h552479 = { _theResult____h544219[54:0], 2'd0 } ; + assign _theResult___snd__h552489 = + (!_theResult____h544219[56] && !_theResult____h544219[55] && + !_theResult____h544219[54] && + !_theResult____h544219[53] && + !_theResult____h544219[52] && + !_theResult____h544219[51] && + !_theResult____h544219[50] && + !_theResult____h544219[49] && + !_theResult____h544219[48] && + !_theResult____h544219[47] && + !_theResult____h544219[46] && + !_theResult____h544219[45] && + !_theResult____h544219[44] && + !_theResult____h544219[43] && + !_theResult____h544219[42] && + !_theResult____h544219[41] && + !_theResult____h544219[40] && + !_theResult____h544219[39] && + !_theResult____h544219[38] && + !_theResult____h544219[37] && + !_theResult____h544219[36] && + !_theResult____h544219[35] && + !_theResult____h544219[34] && + !_theResult____h544219[33] && + !_theResult____h544219[32] && + !_theResult____h544219[31] && + !_theResult____h544219[30] && + !_theResult____h544219[29] && + !_theResult____h544219[28] && + !_theResult____h544219[27] && + !_theResult____h544219[26] && + !_theResult____h544219[25] && + !_theResult____h544219[24] && + !_theResult____h544219[23] && + !_theResult____h544219[22] && + !_theResult____h544219[21] && + !_theResult____h544219[20] && + !_theResult____h544219[19] && + !_theResult____h544219[18] && + !_theResult____h544219[17] && + !_theResult____h544219[16] && + !_theResult____h544219[15] && + !_theResult____h544219[14] && + !_theResult____h544219[13] && + !_theResult____h544219[12] && + !_theResult____h544219[11] && + !_theResult____h544219[10] && + !_theResult____h544219[9] && + !_theResult____h544219[8] && + !_theResult____h544219[7] && + !_theResult____h544219[6] && + !_theResult____h544219[5] && + !_theResult____h544219[4] && + !_theResult____h544219[3] && + !_theResult____h544219[2] && + !_theResult____h544219[1] && + !_theResult____h544219[0]) ? + _theResult____h544219 : + _theResult___snd__h552495 ; + assign _theResult___snd__h552495 = + { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q170[54:0], 2'd0 } ; - assign _theResult___snd__h552827 = - _theResult____h544528 << + assign _theResult___snd__h552518 = + _theResult____h544219 << IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10491 ; - assign _theResult___snd__h561543 = - (f2_exp__h523940 == 8'd0) ? - _theResult___snd__h561557 : - _theResult___snd__h543140 ; - assign _theResult___snd__h561557 = - (f2_exp__h523940 == 8'd0 && !f2_sfd__h523941[22] && + assign _theResult___snd__h561234 = + (f2_exp__h523631 == 8'd0) ? + _theResult___snd__h561248 : + _theResult___snd__h542831 ; + assign _theResult___snd__h561248 = + (f2_exp__h523631 == 8'd0 && !f2_sfd__h523632[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10167) ? - sfd__h524302 : - _theResult___snd__h561563 ; - assign _theResult___snd__h561563 = - { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q181[54:0], + sfd__h523993 : + _theResult___snd__h561254 ; + assign _theResult___snd__h561254 = + { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q173[54:0], 2'd0 } ; - assign _theResult___snd__h561581 = - sfd__h524302 << + assign _theResult___snd__h561272 = + sfd__h523993 << IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10542 ; - assign _theResult___snd__h582442 = - (f3_exp__h563244 == 8'd0) ? - _theResult___snd__h582451 : - _theResult___snd__h582444 ; - assign _theResult___snd__h582444 = { f3_sfd__h563245, 34'd0 } ; - assign _theResult___snd__h582451 = - (f3_exp__h563244 == 8'd0 && !f3_sfd__h563245[22] && + assign _theResult___snd__h582133 = + (f3_exp__h562935 == 8'd0) ? + _theResult___snd__h582142 : + _theResult___snd__h582135 ; + assign _theResult___snd__h582135 = { f3_sfd__h562936, 34'd0 } ; + assign _theResult___snd__h582142 = + (f3_exp__h562935 == 8'd0 && !f3_sfd__h562936[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9397) ? - sfd__h563606 : - _theResult___snd__h582457 ; - assign _theResult___snd__h582457 = - { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q151[54:0], + sfd__h563297 : + _theResult___snd__h582148 ; + assign _theResult___snd__h582148 = + { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q143[54:0], 2'd0 } ; - assign _theResult___snd__h582480 = - sfd__h563606 << + assign _theResult___snd__h582171 = + sfd__h563297 << IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9424 ; - assign _theResult___snd__h592079 = { _theResult____h583832[55:0], 1'd0 } ; - assign _theResult___snd__h592090 = - (!_theResult____h583832[56] && _theResult____h583832[55]) ? - _theResult___snd__h592092 : - _theResult___snd__h592102 ; - assign _theResult___snd__h592092 = { _theResult____h583832[54:0], 2'd0 } ; - assign _theResult___snd__h592102 = - (!_theResult____h583832[56] && !_theResult____h583832[55] && - !_theResult____h583832[54] && - !_theResult____h583832[53] && - !_theResult____h583832[52] && - !_theResult____h583832[51] && - !_theResult____h583832[50] && - !_theResult____h583832[49] && - !_theResult____h583832[48] && - !_theResult____h583832[47] && - !_theResult____h583832[46] && - !_theResult____h583832[45] && - !_theResult____h583832[44] && - !_theResult____h583832[43] && - !_theResult____h583832[42] && - !_theResult____h583832[41] && - !_theResult____h583832[40] && - !_theResult____h583832[39] && - !_theResult____h583832[38] && - !_theResult____h583832[37] && - !_theResult____h583832[36] && - !_theResult____h583832[35] && - !_theResult____h583832[34] && - !_theResult____h583832[33] && - !_theResult____h583832[32] && - !_theResult____h583832[31] && - !_theResult____h583832[30] && - !_theResult____h583832[29] && - !_theResult____h583832[28] && - !_theResult____h583832[27] && - !_theResult____h583832[26] && - !_theResult____h583832[25] && - !_theResult____h583832[24] && - !_theResult____h583832[23] && - !_theResult____h583832[22] && - !_theResult____h583832[21] && - !_theResult____h583832[20] && - !_theResult____h583832[19] && - !_theResult____h583832[18] && - !_theResult____h583832[17] && - !_theResult____h583832[16] && - !_theResult____h583832[15] && - !_theResult____h583832[14] && - !_theResult____h583832[13] && - !_theResult____h583832[12] && - !_theResult____h583832[11] && - !_theResult____h583832[10] && - !_theResult____h583832[9] && - !_theResult____h583832[8] && - !_theResult____h583832[7] && - !_theResult____h583832[6] && - !_theResult____h583832[5] && - !_theResult____h583832[4] && - !_theResult____h583832[3] && - !_theResult____h583832[2] && - !_theResult____h583832[1] && - !_theResult____h583832[0]) ? - _theResult____h583832 : - _theResult___snd__h592108 ; - assign _theResult___snd__h592108 = - { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q155[54:0], + assign _theResult___snd__h591770 = { _theResult____h583523[55:0], 1'd0 } ; + assign _theResult___snd__h591781 = + (!_theResult____h583523[56] && _theResult____h583523[55]) ? + _theResult___snd__h591783 : + _theResult___snd__h591793 ; + assign _theResult___snd__h591783 = { _theResult____h583523[54:0], 2'd0 } ; + assign _theResult___snd__h591793 = + (!_theResult____h583523[56] && !_theResult____h583523[55] && + !_theResult____h583523[54] && + !_theResult____h583523[53] && + !_theResult____h583523[52] && + !_theResult____h583523[51] && + !_theResult____h583523[50] && + !_theResult____h583523[49] && + !_theResult____h583523[48] && + !_theResult____h583523[47] && + !_theResult____h583523[46] && + !_theResult____h583523[45] && + !_theResult____h583523[44] && + !_theResult____h583523[43] && + !_theResult____h583523[42] && + !_theResult____h583523[41] && + !_theResult____h583523[40] && + !_theResult____h583523[39] && + !_theResult____h583523[38] && + !_theResult____h583523[37] && + !_theResult____h583523[36] && + !_theResult____h583523[35] && + !_theResult____h583523[34] && + !_theResult____h583523[33] && + !_theResult____h583523[32] && + !_theResult____h583523[31] && + !_theResult____h583523[30] && + !_theResult____h583523[29] && + !_theResult____h583523[28] && + !_theResult____h583523[27] && + !_theResult____h583523[26] && + !_theResult____h583523[25] && + !_theResult____h583523[24] && + !_theResult____h583523[23] && + !_theResult____h583523[22] && + !_theResult____h583523[21] && + !_theResult____h583523[20] && + !_theResult____h583523[19] && + !_theResult____h583523[18] && + !_theResult____h583523[17] && + !_theResult____h583523[16] && + !_theResult____h583523[15] && + !_theResult____h583523[14] && + !_theResult____h583523[13] && + !_theResult____h583523[12] && + !_theResult____h583523[11] && + !_theResult____h583523[10] && + !_theResult____h583523[9] && + !_theResult____h583523[8] && + !_theResult____h583523[7] && + !_theResult____h583523[6] && + !_theResult____h583523[5] && + !_theResult____h583523[4] && + !_theResult____h583523[3] && + !_theResult____h583523[2] && + !_theResult____h583523[1] && + !_theResult____h583523[0]) ? + _theResult____h583523 : + _theResult___snd__h591799 ; + assign _theResult___snd__h591799 = + { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q147[54:0], 2'd0 } ; - assign _theResult___snd__h592131 = - _theResult____h583832 << + assign _theResult___snd__h591822 = + _theResult____h583523 << IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9721 ; - assign _theResult___snd__h600847 = - (f3_exp__h563244 == 8'd0) ? - _theResult___snd__h600861 : - _theResult___snd__h582444 ; - assign _theResult___snd__h600861 = - (f3_exp__h563244 == 8'd0 && !f3_sfd__h563245[22] && + assign _theResult___snd__h600538 = + (f3_exp__h562935 == 8'd0) ? + _theResult___snd__h600552 : + _theResult___snd__h582135 ; + assign _theResult___snd__h600552 = + (f3_exp__h562935 == 8'd0 && !f3_sfd__h562936[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9397) ? - sfd__h563606 : - _theResult___snd__h600867 ; - assign _theResult___snd__h600867 = - { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q158[54:0], + sfd__h563297 : + _theResult___snd__h600558 ; + assign _theResult___snd__h600558 = + { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q150[54:0], 2'd0 } ; - assign _theResult___snd__h600885 = - sfd__h563606 << + assign _theResult___snd__h600576 = + sfd__h563297 << IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9772 ; - assign _theResult___snd__h606341 = - b__h605793[63] ? b___1__h606406 : b__h605793 ; - assign _theResult___snd_fst_exp__h365676 = + assign _theResult___snd__h606032 = + b__h605484[63] ? b___1__h606097 : b__h605484 ; + assign _theResult___snd_fst_exp__h365367 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4109 ? - _theResult___fst_exp__h357091 : - _theResult___fst_exp__h365673 ; - assign _theResult___snd_fst_exp__h383496 = + _theResult___fst_exp__h356782 : + _theResult___fst_exp__h365364 ; + assign _theResult___snd_fst_exp__h383187 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4649 ? - _theResult___fst_exp__h374857 : - _theResult___fst_exp__h383493 ; - assign _theResult___snd_fst_exp__h411373 = + _theResult___fst_exp__h374548 : + _theResult___fst_exp__h383184 ; + assign _theResult___snd_fst_exp__h411064 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5501 ? - _theResult___fst_exp__h402788 : - _theResult___fst_exp__h411370 ; - assign _theResult___snd_fst_exp__h429193 = + _theResult___fst_exp__h402479 : + _theResult___fst_exp__h411061 ; + assign _theResult___snd_fst_exp__h428884 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6041 ? - _theResult___fst_exp__h420554 : - _theResult___fst_exp__h429190 ; - assign _theResult___snd_fst_exp__h457068 = + _theResult___fst_exp__h420245 : + _theResult___fst_exp__h428881 ; + assign _theResult___snd_fst_exp__h456759 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6893 ? - _theResult___fst_exp__h448483 : - _theResult___fst_exp__h457065 ; - assign _theResult___snd_fst_exp__h474888 = + _theResult___fst_exp__h448174 : + _theResult___fst_exp__h456756 ; + assign _theResult___snd_fst_exp__h474579 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7433 ? - _theResult___fst_exp__h466249 : - _theResult___fst_exp__h474885 ; - assign _theResult___snd_fst_exp__h505095 = + _theResult___fst_exp__h465940 : + _theResult___fst_exp__h474576 ; + assign _theResult___snd_fst_exp__h504786 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8623 ? 11'd0 : - _theResult___fst_exp__h505092 ; - assign _theResult___snd_fst_exp__h523530 = + _theResult___fst_exp__h504783 ; + assign _theResult___snd_fst_exp__h523221 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8759 ? - _theResult___fst_exp__h514743 : - _theResult___fst_exp__h523527 ; - assign _theResult___snd_fst_exp__h543948 = + _theResult___fst_exp__h514434 : + _theResult___fst_exp__h523218 ; + assign _theResult___snd_fst_exp__h543639 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10123 ? 11'd0 : - _theResult___fst_exp__h543945 ; - assign _theResult___snd_fst_exp__h562383 = + _theResult___fst_exp__h543636 ; + assign _theResult___snd_fst_exp__h562074 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10244 ? - _theResult___fst_exp__h553596 : - _theResult___fst_exp__h562380 ; - assign _theResult___snd_fst_exp__h583252 = + _theResult___fst_exp__h553287 : + _theResult___fst_exp__h562071 ; + assign _theResult___snd_fst_exp__h582943 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9353 ? 11'd0 : - _theResult___fst_exp__h583249 ; - assign _theResult___snd_fst_exp__h601687 = + _theResult___fst_exp__h582940 ; + assign _theResult___snd_fst_exp__h601378 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9474 ? - _theResult___fst_exp__h592900 : - _theResult___fst_exp__h601684 ; - assign _theResult___snd_fst_sfd__h340728 = + _theResult___fst_exp__h592591 : + _theResult___fst_exp__h601375 ; + assign _theResult___snd_fst_sfd__h340419 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:34] == 23'd0) ? 23'd2097152 : coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:34] ; - assign _theResult___snd_fst_sfd__h365677 = + assign _theResult___snd_fst_sfd__h365368 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4109 ? - _theResult___fst_sfd__h357092 : - _theResult___fst_sfd__h365674 ; - assign _theResult___snd_fst_sfd__h383497 = + _theResult___fst_sfd__h356783 : + _theResult___fst_sfd__h365365 ; + assign _theResult___snd_fst_sfd__h383188 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4649 ? - _theResult___fst_sfd__h374858 : - _theResult___fst_sfd__h383494 ; - assign _theResult___snd_fst_sfd__h386430 = + _theResult___fst_sfd__h374549 : + _theResult___fst_sfd__h383185 ; + assign _theResult___snd_fst_sfd__h386121 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:34] == 23'd0) ? 23'd2097152 : coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:34] ; - assign _theResult___snd_fst_sfd__h411374 = + assign _theResult___snd_fst_sfd__h411065 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5501 ? - _theResult___fst_sfd__h402789 : - _theResult___fst_sfd__h411371 ; - assign _theResult___snd_fst_sfd__h429194 = + _theResult___fst_sfd__h402480 : + _theResult___fst_sfd__h411062 ; + assign _theResult___snd_fst_sfd__h428885 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6041 ? - _theResult___fst_sfd__h420555 : - _theResult___fst_sfd__h429191 ; - assign _theResult___snd_fst_sfd__h432125 = + _theResult___fst_sfd__h420246 : + _theResult___fst_sfd__h428882 ; + assign _theResult___snd_fst_sfd__h431816 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:34] == 23'd0) ? 23'd2097152 : coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:34] ; - assign _theResult___snd_fst_sfd__h457069 = + assign _theResult___snd_fst_sfd__h456760 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6893 ? - _theResult___fst_sfd__h448484 : - _theResult___fst_sfd__h457066 ; - assign _theResult___snd_fst_sfd__h474889 = + _theResult___fst_sfd__h448175 : + _theResult___fst_sfd__h456757 ; + assign _theResult___snd_fst_sfd__h474580 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7433 ? - _theResult___fst_sfd__h466250 : - _theResult___fst_sfd__h474886 ; - assign _theResult___snd_fst_sfd__h485262 = - (f1_sfd__h484947 == 23'd0) ? + _theResult___fst_sfd__h465941 : + _theResult___fst_sfd__h474577 ; + assign _theResult___snd_fst_sfd__h484953 = + (f1_sfd__h484638 == 23'd0) ? 52'h4000000000000 : - out___1_sfd__h485010 ; - assign _theResult___snd_fst_sfd__h505096 = + out___1_sfd__h484701 ; + assign _theResult___snd_fst_sfd__h504787 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8623 ? 52'd0 : - _theResult___fst_sfd__h505093 ; - assign _theResult___snd_fst_sfd__h523531 = + _theResult___fst_sfd__h504784 ; + assign _theResult___snd_fst_sfd__h523222 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8759 ? - _theResult___fst_sfd__h514744 : - _theResult___fst_sfd__h523528 ; - assign _theResult___snd_fst_sfd__h524256 = - (f2_sfd__h523941 == 23'd0) ? + _theResult___fst_sfd__h514435 : + _theResult___fst_sfd__h523219 ; + assign _theResult___snd_fst_sfd__h523947 = + (f2_sfd__h523632 == 23'd0) ? 52'h4000000000000 : - out___1_sfd__h524004 ; - assign _theResult___snd_fst_sfd__h543949 = + out___1_sfd__h523695 ; + assign _theResult___snd_fst_sfd__h543640 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10123 ? 52'd0 : - _theResult___fst_sfd__h543946 ; - assign _theResult___snd_fst_sfd__h562384 = + _theResult___fst_sfd__h543637 ; + assign _theResult___snd_fst_sfd__h562075 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10244 ? - _theResult___fst_sfd__h553597 : - _theResult___fst_sfd__h562381 ; - assign _theResult___snd_fst_sfd__h563560 = - (f3_sfd__h563245 == 23'd0) ? + _theResult___fst_sfd__h553288 : + _theResult___fst_sfd__h562072 ; + assign _theResult___snd_fst_sfd__h563251 = + (f3_sfd__h562936 == 23'd0) ? 52'h4000000000000 : - out___1_sfd__h563308 ; - assign _theResult___snd_fst_sfd__h583253 = + out___1_sfd__h562999 ; + assign _theResult___snd_fst_sfd__h582944 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9353 ? 52'd0 : - _theResult___fst_sfd__h583250 ; - assign _theResult___snd_fst_sfd__h601688 = + _theResult___fst_sfd__h582941 ; + assign _theResult___snd_fst_sfd__h601379 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9474 ? - _theResult___fst_sfd__h592901 : - _theResult___fst_sfd__h601685 ; - assign a___1__h605954 = + _theResult___fst_sfd__h592592 : + _theResult___fst_sfd__h601376 ; + assign a___1__h605645 = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd1) ? { 32'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[171:140] } : - { {32{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q11[31]}}, - coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q11 } ; - assign a___1__h606345 = 64'd0 - a__h605792 ; - assign a__h605792 = + { {32{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q3[31]}}, + coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q3 } ; + assign a___1__h606036 = 64'd0 - a__h605483 ; + assign a__h605483 = coreFix_fpuMulDivExe_0_regToExeQ$first[227] ? - a___1__h605954 : + a___1__h605645 : coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; - assign b___1__h605955 = + assign b___1__h605646 = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? - { {32{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q12[31]}}, - coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q12 } : + { {32{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q4[31]}}, + coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q4 } : { 32'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[107:76] } ; - assign b___1__h606406 = 64'd0 - b__h605793 ; - assign b__h605793 = + assign b___1__h606097 = 64'd0 - b__h605484 ; + assign b__h605484 = coreFix_fpuMulDivExe_0_regToExeQ$first[227] ? - b___1__h605955 : + b___1__h605646 : coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; - assign b__h605940 = { {64{a__h605792[63]}}, a__h605792 } ; - assign b__h606016 = { {64{b__h605793[63]}}, b__h605793 } ; - assign b__h606117 = { 64'd0, a__h605792 } ; - assign b__h606129 = { 64'd0, b__h605793 } ; - assign base__h709686 = { csrf_stvec_base_hi_reg, 2'b0 } ; - assign base__h709889 = { csrf_mtvec_base_hi_reg, 2'b0 } ; - assign cause_code__h707068 = - commitStage_commitTrap[4] ? i__h707243 : i__h707083 ; - assign commitStage_commitTrap_4555_BIT_4_4779_AND_com_ETC___d14844 = + assign b__h605631 = { {64{a__h605483[63]}}, a__h605483 } ; + assign b__h605707 = { {64{b__h605484[63]}}, b__h605484 } ; + assign b__h605808 = { 64'd0, a__h605483 } ; + assign b__h605820 = { 64'd0, b__h605484 } ; + assign base__h708366 = { csrf_stvec_base_hi_reg, 2'b0 } ; + assign base__h708569 = { csrf_mtvec_base_hi_reg, 2'b0 } ; + assign cause_code__h705748 = + commitStage_commitTrap[4] ? i__h705923 : i__h705763 ; + assign commitStage_commitTrap_4549_BIT_4_4679_AND_com_ETC___d14744 = commitStage_commitTrap[4] && commitStage_commitTrap[3:0] != 4'd0 && commitStage_commitTrap[3:0] != 4'd1 && @@ -29309,54 +29151,54 @@ module mkCore(CLK, commitStage_commitTrap[3:0] != 4'd11 || !commitStage_commitTrap[4] && commitStage_commitTrap[3:0] == 4'd3 && - CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q244 ; - assign commitStage_commitTrap_4555_BIT_4_4779_AND_com_ETC___d14845 = - commitStage_commitTrap_4555_BIT_4_4779_AND_com_ETC___d14844 || + CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q236 ; + assign commitStage_commitTrap_4549_BIT_4_4679_AND_com_ETC___d14745 = + commitStage_commitTrap_4549_BIT_4_4679_AND_com_ETC___d14744 || coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty && fetchStage$iTlbIfc_noPendingReq && coreFix_memExe_dTlb$noPendingReq ; - assign coreFix_aluExe_0_bypassWire_0_wget__2373_BITS__ETC___d12375 = + assign coreFix_aluExe_0_bypassWire_0_wget__2370_BITS__ETC___d12372 = coreFix_aluExe_0_bypassWire_0$wget[70:64] == coreFix_aluExe_0_dispToRegQ$first[84:78] ; - assign coreFix_aluExe_0_bypassWire_0_wget__2373_BITS__ETC___d12416 = + assign coreFix_aluExe_0_bypassWire_0_wget__2370_BITS__ETC___d12413 = coreFix_aluExe_0_bypassWire_0$wget[70:64] == coreFix_aluExe_0_dispToRegQ$first[76:70] ; - assign coreFix_aluExe_0_bypassWire_1_wget__2386_BITS__ETC___d12388 = + assign coreFix_aluExe_0_bypassWire_1_wget__2383_BITS__ETC___d12385 = coreFix_aluExe_0_bypassWire_1$wget[70:64] == coreFix_aluExe_0_dispToRegQ$first[84:78] ; - assign coreFix_aluExe_0_bypassWire_1_wget__2386_BITS__ETC___d12422 = + assign coreFix_aluExe_0_bypassWire_1_wget__2383_BITS__ETC___d12419 = coreFix_aluExe_0_bypassWire_1$wget[70:64] == coreFix_aluExe_0_dispToRegQ$first[76:70] ; - assign coreFix_aluExe_0_bypassWire_2_wget__2394_BITS__ETC___d12396 = + assign coreFix_aluExe_0_bypassWire_2_wget__2391_BITS__ETC___d12393 = coreFix_aluExe_0_bypassWire_2$wget[70:64] == coreFix_aluExe_0_dispToRegQ$first[84:78] ; - assign coreFix_aluExe_0_bypassWire_2_wget__2394_BITS__ETC___d12426 = + assign coreFix_aluExe_0_bypassWire_2_wget__2391_BITS__ETC___d12423 = coreFix_aluExe_0_bypassWire_2$wget[70:64] == coreFix_aluExe_0_dispToRegQ$first[76:70] ; - assign coreFix_aluExe_0_bypassWire_3_wget__2401_BITS__ETC___d12403 = + assign coreFix_aluExe_0_bypassWire_3_wget__2398_BITS__ETC___d12400 = coreFix_aluExe_0_bypassWire_3$wget[70:64] == coreFix_aluExe_0_dispToRegQ$first[84:78] ; - assign coreFix_aluExe_0_bypassWire_3_wget__2401_BITS__ETC___d12430 = + assign coreFix_aluExe_0_bypassWire_3_wget__2398_BITS__ETC___d12427 = coreFix_aluExe_0_bypassWire_3$wget[70:64] == coreFix_aluExe_0_dispToRegQ$first[76:70] ; - assign coreFix_aluExe_0_dispToRegQ_RDY_first__2350_AN_ETC___d12441 = + assign coreFix_aluExe_0_dispToRegQ_RDY_first__2347_AN_ETC___d12438 = coreFix_aluExe_0_dispToRegQ$RDY_first && (coreFix_aluExe_0_dispToRegQ$first[131] || !coreFix_aluExe_0_dispToRegQ$first[85] || sbCons$lazyLookup_0_get[3] || - IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2350_ETC___d12383 && - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__237_ETC___d12409) && + IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2347_ETC___d12380 && + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12406) && (!coreFix_aluExe_0_dispToRegQ$first[77] || sbCons$lazyLookup_0_get[2] || - IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2350_ETC___d12419 && - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__237_ETC___d12436) ; - assign coreFix_aluExe_0_exeToFinQ_RDY_first__2817_AND_ETC___d12857 = + IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2347_ETC___d12416 && + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12433) ; + assign coreFix_aluExe_0_exeToFinQ_RDY_first__2814_AND_ETC___d12854 = coreFix_aluExe_0_exeToFinQ$RDY_first && rob$RDY_setExecuted_doFinishAlu_0_set && (coreFix_aluExe_0_exeToFinQ$first[326:322] != 5'd9 && coreFix_aluExe_0_exeToFinQ$first[326:322] != 5'd10 || coreFix_trainBPQ_0$FULL_N) ; - assign coreFix_aluExe_0_rsAlu_approximateCount__3617__ETC___d13619 = + assign coreFix_aluExe_0_rsAlu_approximateCount__3613__ETC___d13615 = coreFix_aluExe_0_rsAlu$approximateCount < coreFix_aluExe_1_rsAlu$approximateCount ; assign coreFix_aluExe_1_bypassWire_0_wget__1511_BITS__ETC___d11513 = @@ -29394,7 +29236,7 @@ module mkCore(CLK, sbCons$lazyLookup_1_get[2] || IF_coreFix_aluExe_1_dispToRegQ_RDY_first__1488_ETC___d11557 && IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11574) ; - assign coreFix_aluExe_1_exeToFinQ_RDY_first__2143_AND_ETC___d12184 = + assign coreFix_aluExe_1_exeToFinQ_RDY_first__2140_AND_ETC___d12181 = coreFix_aluExe_1_exeToFinQ$RDY_first && rob$RDY_setExecuted_doFinishAlu_1_set && (coreFix_aluExe_1_exeToFinQ$first[326:322] != 5'd9 && @@ -29456,13 +29298,13 @@ module mkCore(CLK, rob$RDY_setExecuted_doFinishFpuMulDiv_0_set && coreFix_fpuMulDivExe_0_fpuExec_double_div$RDY_response_get && coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_first_data ; - assign coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q72 = + assign coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q64 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] - 11'd1023 ; - assign coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q37 = + assign coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q29 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] - 11'd1023 ; - assign coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q107 = + assign coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q99 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] - 11'd1023 ; assign coreFix_fpuMulDivExe_0_fpuExec_fmaQ_RDY_first__ETC___d3976 = @@ -29501,9 +29343,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10918 | - ((f3_exp__h563244 != 8'd255 || f3_sfd__h563245 == 23'd0) && - (f3_exp__h563244 != 8'd255 || f3_sfd__h563245 != 23'd0) && - (f3_exp__h563244 != 8'd0 || f3_sfd__h563245 != 23'd0) && + ((f3_exp__h562935 != 8'd255 || f3_sfd__h562936 == 23'd0) && + (f3_exp__h562935 != 8'd255 || f3_sfd__h562936 != 23'd0) && + (f3_exp__h562935 != 8'd0 || f3_sfd__h562936 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10958) ; assign coreFix_fpuMulDivExe_0_regToExeQ_first__482_BI_ETC___d10999 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || @@ -29511,9 +29353,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10987 | - ((f3_exp__h563244 != 8'd255 || f3_sfd__h563245 == 23'd0) && - (f3_exp__h563244 != 8'd255 || f3_sfd__h563245 != 23'd0) && - (f3_exp__h563244 != 8'd0 || f3_sfd__h563245 != 23'd0) && + ((f3_exp__h562935 != 8'd255 || f3_sfd__h562936 == 23'd0) && + (f3_exp__h562935 != 8'd255 || f3_sfd__h562936 != 23'd0) && + (f3_exp__h562935 != 8'd0 || f3_sfd__h562936 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10994) ; assign coreFix_fpuMulDivExe_0_regToExeQ_first__482_BI_ETC___d11047 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || @@ -29521,9 +29363,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11031 | - ((f3_exp__h563244 != 8'd255 || f3_sfd__h563245 == 23'd0) && - (f3_exp__h563244 != 8'd255 || f3_sfd__h563245 != 23'd0) && - (f3_exp__h563244 != 8'd0 || f3_sfd__h563245 != 23'd0) && + ((f3_exp__h562935 != 8'd255 || f3_sfd__h562936 == 23'd0) && + (f3_exp__h562935 != 8'd255 || f3_sfd__h562936 != 23'd0) && + (f3_exp__h562935 != 8'd0 || f3_sfd__h562936 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11042) ; assign coreFix_fpuMulDivExe_0_regToExeQ_first__482_BI_ETC___d11089 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || @@ -29531,9 +29373,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11075 | - ((f3_exp__h563244 != 8'd255 || f3_sfd__h563245 == 23'd0) && - (f3_exp__h563244 != 8'd255 || f3_sfd__h563245 != 23'd0) && - (f3_exp__h563244 != 8'd0 || f3_sfd__h563245 != 23'd0) && + ((f3_exp__h562935 != 8'd255 || f3_sfd__h562936 == 23'd0) && + (f3_exp__h562935 != 8'd255 || f3_sfd__h562936 != 23'd0) && + (f3_exp__h562935 != 8'd0 || f3_sfd__h562936 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11084) ; assign coreFix_fpuMulDivExe_0_regToExeQ_first__482_BI_ETC___d11131 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || @@ -29541,19 +29383,19 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11117 | - ((f3_exp__h563244 != 8'd255 || f3_sfd__h563245 == 23'd0) && - (f3_exp__h563244 != 8'd255 || f3_sfd__h563245 != 23'd0) && - (f3_exp__h563244 != 8'd0 || f3_sfd__h563245 != 23'd0) && + ((f3_exp__h562935 != 8'd255 || f3_sfd__h562936 == 23'd0) && + (f3_exp__h562935 != 8'd255 || f3_sfd__h562936 != 23'd0) && + (f3_exp__h562935 != 8'd0 || f3_sfd__h562936 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11126) ; - assign coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q12 = + assign coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q4 = coreFix_fpuMulDivExe_0_regToExeQ$first[107:76] ; - assign coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q11 = + assign coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q3 = coreFix_fpuMulDivExe_0_regToExeQ$first[171:140] ; - assign coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__40_ETC___d14192 = + assign coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__40_ETC___d14188 = coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_enq && regRenamingTable$RDY_rename_1_getRename && (!fetchStage$pipelines_0_canDeq || - NOT_specTagManager_canClaim__3580_3666_OR_NOT__ETC___d14172) ; + NOT_specTagManager_canClaim__3576_3662_OR_NOT__ETC___d14168) ; assign coreFix_memExe_bypassWire_0_wget__585_BITS_70__ETC___d1587 = coreFix_aluExe_0_bypassWire_0$wget[70:64] == coreFix_memExe_dispToRegQ$first[61:55] ; @@ -29589,7 +29431,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$Q_OUT && coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58] && coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[57:0] == - y__h256430 ; + y__h256122 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIn_ETC___d3163 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3127 || @@ -29862,7 +29704,7 @@ module mkCore(CLK, sbCons$lazyLookup_3_get[2] || IF_coreFix_memExe_dispToRegQ_RDY_first__564_AN_ETC___d1630 && IF_NOT_coreFix_memExe_bypassWire_0_whas__584_5_ETC___d1647) ; - assign coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q13 = + assign coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q5 = coreFix_memExe_regToExeQ$first[189:158] ; assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1224 = coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT && @@ -29926,7 +29768,15 @@ module mkCore(CLK, !coreFix_memExe_respLrScAmoQ_deqReq_lat_0$whas && !coreFix_memExe_respLrScAmoQ_deqReq_rl) && coreFix_memExe_respLrScAmoQ_full ; - assign csrf_fs_reg_read__1726_EQ_0_3169_AND_fetchStag_ETC___d13215 = + assign coreFix_memExe_stb_isEmpty__011_AND_coreFix_me_ETC___d14946 = + coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty && + rob$RDY_deqPort_0_deq_data && + rob$RDY_deqPort_0_deq && + regRenamingTable$RDY_commit_0_commit && + fetchStage$iTlbIfc_noPendingReq && + coreFix_memExe_dTlb$noPendingReq && + NOT_rob_deqPort_0_deq_data__4542_BITS_186_TO_1_ETC___d14941 ; + assign csrf_fs_reg_read__1726_EQ_0_3165_AND_fetchStag_ETC___d13211 = csrf_fs_reg == 2'd0 && (fetchStage$pipelines_0_first[95] && fetchStage$pipelines_0_first[94] || @@ -29936,9 +29786,9 @@ module mkCore(CLK, fetchStage$pipelines_0_first[75] && fetchStage$pipelines_0_first[74]) || fetchStage$pipelines_0_first[199:195] == 5'd13 && - (fetchStage_pipelines_0_first__2934_BITS_194_TO_ETC___d13210 || - csrf_prv_reg_read__2964_ULT_IF_fetchStage_pipe_ETC___d13212) ; - assign csrf_fs_reg_read__1726_EQ_0_3169_AND_fetchStag_ETC___d13676 = + (fetchStage_pipelines_0_first__2931_BITS_194_TO_ETC___d13206 || + csrf_prv_reg_read__2961_ULT_IF_fetchStage_pipe_ETC___d13208) ; + assign csrf_fs_reg_read__1726_EQ_0_3165_AND_fetchStag_ETC___d13672 = csrf_fs_reg == 2'd0 && (fetchStage$pipelines_0_first[95] && fetchStage$pipelines_0_first[94] || @@ -29950,7 +29800,7 @@ module mkCore(CLK, fetchStage$pipelines_0_first[231:200] == 32'h10500073 && csrf_tw_reg && csrf_prv_reg != 2'd3 ; - assign csrf_fs_reg_read__1726_EQ_0_3169_AND_fetchStag_ETC___d13956 = + assign csrf_fs_reg_read__1726_EQ_0_3165_AND_fetchStag_ETC___d13952 = csrf_fs_reg == 2'd0 && (fetchStage$pipelines_1_first[95] && fetchStage$pipelines_1_first[94] || @@ -29962,38 +29812,38 @@ module mkCore(CLK, fetchStage$pipelines_1_first[231:200] == 32'h10500073 && csrf_tw_reg && csrf_prv_reg != 2'd3 ; - assign csrf_prv_reg_read__2964_ULE_1_4882_AND_IF_comm_ETC___d14904 = - csrf_prv_reg_read__2964_ULE_1___d14882 && + assign csrf_prv_reg_read__2961_ULE_1_4782_AND_IF_comm_ETC___d14804 = + csrf_prv_reg_read__2961_ULE_1___d14782 && (commitStage_commitTrap[4] ? - _0b0_CONCAT_csrf_mideleg_11_reg_read__1839_1840_ETC___d14884 : - _0b0_CONCAT_csrf_medeleg_15_reg_read__1831_1832_ETC___d14902) ; - assign csrf_prv_reg_read__2964_ULE_1___d14882 = csrf_prv_reg <= 2'd1 ; - assign csrf_prv_reg_read__2964_ULT_IF_fetchStage_pipe_ETC___d13212 = + _0b0_CONCAT_csrf_mideleg_11_reg_read__1839_1840_ETC___d14784 : + _0b0_CONCAT_csrf_medeleg_15_reg_read__1831_1832_ETC___d14802) ; + assign csrf_prv_reg_read__2961_ULE_1___d14782 = csrf_prv_reg <= 2'd1 ; + assign csrf_prv_reg_read__2961_ULT_IF_fetchStage_pipe_ETC___d13208 = csrf_prv_reg < - IF_fetchStage_pipelines_0_first__2934_BIT_173__ETC___d13207[9:8] ; - assign csrf_rg_dcsr_read__1902_BIT_2_3232_OR_NOT_fetc_ETC___d13672 = + IF_fetchStage_pipelines_0_first__2931_BIT_173__ETC___d13203[9:8] ; + assign csrf_rg_dcsr_read__1899_BIT_2_3228_OR_NOT_fetc_ETC___d13668 = csrf_rg_dcsr[2] || !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first && - IF_fetchStage_RDY_pipelines_0_first__2931_AND__ETC___d13610 ; - assign data76871_BITS_31_TO_0__q10 = data__h476871[31:0] ; - assign data77765_BITS_31_TO_0__q14 = data__h477765[31:0] ; - assign data___1__h477383 = - { {32{data76871_BITS_31_TO_0__q10[31]}}, - data76871_BITS_31_TO_0__q10 } ; - assign data___1__h478277 = - { {32{data77765_BITS_31_TO_0__q14[31]}}, - data77765_BITS_31_TO_0__q14 } ; - assign data__h476871 = + IF_fetchStage_RDY_pipelines_0_first__2928_AND__ETC___d13606 ; + assign data76562_BITS_31_TO_0__q2 = data__h476562[31:0] ; + assign data77456_BITS_31_TO_0__q6 = data__h477456[31:0] ; + assign data___1__h477074 = + { {32{data76562_BITS_31_TO_0__q2[31]}}, + data76562_BITS_31_TO_0__q2 } ; + assign data___1__h477968 = + { {32{data77456_BITS_31_TO_0__q6[31]}}, + data77456_BITS_31_TO_0__q6 } ; + assign data__h476562 = (coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[35:34] == 2'd0) ? coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_OUT[63:0] : coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_OUT[127:64] ; - assign data__h477765 = + assign data__h477456 = (coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[35:34] == 2'd2) ? - x_quotient__h477567 : - x_remainder__h477568 ; - assign dcsr_cause__h706588 = + x_quotient__h477258 : + x_remainder__h477259 ; + assign dcsr_cause__h705268 = (commitStage_commitTrap[4] && commitStage_commitTrap[3:0] == 4'd14) ? 3'd3 : @@ -30010,240 +29860,240 @@ module mkCore(CLK, commitStage_commitTrap[3:0] != 4'd14) ? 3'd4 : 3'd1) ; - assign din_inc___2_exp__h383527 = _theResult___fst_exp__h356494 + 8'd1 ; - assign din_inc___2_exp__h383551 = _theResult___fst_exp__h365150 + 8'd1 ; - assign din_inc___2_exp__h383581 = _theResult___fst_exp__h374260 + 8'd1 ; - assign din_inc___2_exp__h383605 = _theResult___fst_exp__h382945 + 8'd1 ; - assign din_inc___2_exp__h429224 = _theResult___fst_exp__h402191 + 8'd1 ; - assign din_inc___2_exp__h429248 = _theResult___fst_exp__h410847 + 8'd1 ; - assign din_inc___2_exp__h429278 = _theResult___fst_exp__h419957 + 8'd1 ; - assign din_inc___2_exp__h429302 = _theResult___fst_exp__h428642 + 8'd1 ; - assign din_inc___2_exp__h474919 = _theResult___fst_exp__h447886 + 8'd1 ; - assign din_inc___2_exp__h474943 = _theResult___fst_exp__h456542 + 8'd1 ; - assign din_inc___2_exp__h474973 = _theResult___fst_exp__h465652 + 8'd1 ; - assign din_inc___2_exp__h474997 = _theResult___fst_exp__h474337 + 8'd1 ; - assign din_inc___2_exp__h523584 = _theResult___fst_exp__h504334 + 11'd1 ; - assign din_inc___2_exp__h523619 = _theResult___fst_exp__h513911 + 11'd1 ; - assign din_inc___2_exp__h523645 = _theResult___fst_exp__h522744 + 11'd1 ; - assign din_inc___2_exp__h562437 = _theResult___fst_exp__h543187 + 11'd1 ; - assign din_inc___2_exp__h562472 = _theResult___fst_exp__h552764 + 11'd1 ; - assign din_inc___2_exp__h562498 = _theResult___fst_exp__h561597 + 11'd1 ; - assign din_inc___2_exp__h601741 = _theResult___fst_exp__h582491 + 11'd1 ; - assign din_inc___2_exp__h601776 = _theResult___fst_exp__h592068 + 11'd1 ; - assign din_inc___2_exp__h601802 = _theResult___fst_exp__h600901 + 11'd1 ; - assign enabled_ints___1__h655569 = pend_ints__h655042 & y__h655581 ; - assign enabled_ints__h655616 = - pend_ints__h655042 & - { r1__read_BITS_13_TO_0___h655592, csrf_mideleg_1_0_reg } ; - assign epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13899 = + assign din_inc___2_exp__h383218 = _theResult___fst_exp__h356185 + 8'd1 ; + assign din_inc___2_exp__h383242 = _theResult___fst_exp__h364841 + 8'd1 ; + assign din_inc___2_exp__h383272 = _theResult___fst_exp__h373951 + 8'd1 ; + assign din_inc___2_exp__h383296 = _theResult___fst_exp__h382636 + 8'd1 ; + assign din_inc___2_exp__h428915 = _theResult___fst_exp__h401882 + 8'd1 ; + assign din_inc___2_exp__h428939 = _theResult___fst_exp__h410538 + 8'd1 ; + assign din_inc___2_exp__h428969 = _theResult___fst_exp__h419648 + 8'd1 ; + assign din_inc___2_exp__h428993 = _theResult___fst_exp__h428333 + 8'd1 ; + assign din_inc___2_exp__h474610 = _theResult___fst_exp__h447577 + 8'd1 ; + assign din_inc___2_exp__h474634 = _theResult___fst_exp__h456233 + 8'd1 ; + assign din_inc___2_exp__h474664 = _theResult___fst_exp__h465343 + 8'd1 ; + assign din_inc___2_exp__h474688 = _theResult___fst_exp__h474028 + 8'd1 ; + assign din_inc___2_exp__h523275 = _theResult___fst_exp__h504025 + 11'd1 ; + assign din_inc___2_exp__h523310 = _theResult___fst_exp__h513602 + 11'd1 ; + assign din_inc___2_exp__h523336 = _theResult___fst_exp__h522435 + 11'd1 ; + assign din_inc___2_exp__h562128 = _theResult___fst_exp__h542878 + 11'd1 ; + assign din_inc___2_exp__h562163 = _theResult___fst_exp__h552455 + 11'd1 ; + assign din_inc___2_exp__h562189 = _theResult___fst_exp__h561288 + 11'd1 ; + assign din_inc___2_exp__h601432 = _theResult___fst_exp__h582182 + 11'd1 ; + assign din_inc___2_exp__h601467 = _theResult___fst_exp__h591759 + 11'd1 ; + assign din_inc___2_exp__h601493 = _theResult___fst_exp__h600592 + 11'd1 ; + assign enabled_ints___1__h655233 = pend_ints__h654706 & y__h655245 ; + assign enabled_ints__h655280 = + pend_ints__h654706 & + { r1__read_BITS_13_TO_0___h655256, csrf_mideleg_1_0_reg } ; + assign epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13895 = epochManager$checkEpoch_1_check && !csrf_rg_dcsr[2] && (!fetchStage$pipelines_0_canDeq || (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3582_AND__ETC___d13653 && - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d13639) ; - assign epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d14041 = + regRenamingTable_rename_0_canRename__3578_AND__ETC___d13649 && + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d13635) ; + assign epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d14037 = epochManager$checkEpoch_1_check && !csrf_rg_dcsr[2] && (!fetchStage$pipelines_0_canDeq || (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3582_AND__ETC___d13653 && - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d14037) ; - assign epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d14059 = + regRenamingTable_rename_0_canRename__3578_AND__ETC___d13649 && + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d14033) ; + assign epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d14055 = epochManager$checkEpoch_1_check && !csrf_rg_dcsr[2] && (!fetchStage$pipelines_0_canDeq || (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3582_AND__ETC___d13653 && - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d14055) ; - assign f1_exp84946_MINUS_127__q136 = f1_exp__h484946 - 8'd127 ; - assign f1_exp__h484946 = + regRenamingTable_rename_0_canRename__3578_AND__ETC___d13649 && + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d14051) ; + assign f1_exp84637_MINUS_127__q128 = f1_exp__h484637 - 8'd127 ; + assign f1_exp__h484637 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] : 8'd255 ; - assign f1_sfd__h484947 = + assign f1_sfd__h484638 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] : 23'd4194304 ; - assign f2_exp23940_MINUS_127__q176 = f2_exp__h523940 - 8'd127 ; - assign f2_exp__h523940 = + assign f2_exp23631_MINUS_127__q168 = f2_exp__h523631 - 8'd127 ; + assign f2_exp__h523631 = (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] : 8'd255 ; - assign f2_sfd__h523941 = + assign f2_sfd__h523632 = (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] : 23'd4194304 ; - assign f3_exp63244_MINUS_127__q153 = f3_exp__h563244 - 8'd127 ; - assign f3_exp__h563244 = + assign f3_exp62935_MINUS_127__q145 = f3_exp__h562935 - 8'd127 ; + assign f3_exp__h562935 = (coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] : 8'd255 ; - assign f3_sfd__h563245 = + assign f3_sfd__h562936 = (coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] : 23'd4194304 ; - assign f_csr_rsps_i_notFull__5637_AND_f_csr_reqs_firs_ETC___d15732 = + assign f_csr_rsps_i_notFull__5482_AND_f_csr_reqs_firs_ETC___d15577 = f_csr_rsps$FULL_N && (f_csr_reqs$D_OUT[75:64] != 12'd2049 || csrf_stats_module_writeQ$FULL_N) && (f_csr_reqs$D_OUT[75:64] != 12'd2048 || csrf_terminate_module_terminateQ$FULL_N) ; - assign fallthrough_pc__h668018 = + assign fallthrough_pc__h667681 = (fetchStage$pipelines_0_first[97:96] == 2'b11) ? fetchStage$pipelines_0_first[387:324] + 64'd4 : fetchStage$pipelines_0_first[387:324] + 64'd2 ; - assign fallthrough_pc__h683403 = + assign fallthrough_pc__h683049 = (fetchStage$pipelines_1_first[97:96] == 2'b11) ? fetchStage$pipelines_1_first[387:324] + 64'd4 : fetchStage$pipelines_1_first[387:324] + 64'd2 ; - assign fcsr_csr__read__h613533 = { 56'd0, x__h616677 } ; - assign fetchStage_RDY_pipelines_1_deq__2946_AND_NOT_f_ETC___d14243 = + assign fcsr_csr__read__h613224 = { 56'd0, x__h616354 } ; + assign fetchStage_RDY_pipelines_1_deq__2943_AND_NOT_f_ETC___d14239 = fetchStage$RDY_pipelines_1_deq && (!fetchStage$pipelines_0_canDeq || - NOT_specTagManager_canClaim__3580_3666_OR_NOT__ETC___d14239) && + NOT_specTagManager_canClaim__3576_3662_OR_NOT__ETC___d14235) && (fetchStage$pipelines_1_first[194:192] != 3'd1 || specTagManager$RDY_claimSpecTag) ; - assign fetchStage_pipelines_0_canDeq__2932_AND_NOT_fe_ETC___d14183 = + assign fetchStage_pipelines_0_canDeq__2929_AND_NOT_fe_ETC___d14179 = fetchStage$pipelines_0_canDeq && (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3582_AND__ETC___d13653 && - fetchStage_pipelines_0_first__2934_BITS_194_TO_ETC___d13910 || + regRenamingTable_rename_0_canRename__3578_AND__ETC___d13649 && + fetchStage_pipelines_0_first__2931_BITS_194_TO_ETC___d13906 || !coreFix_aluExe_0_rsAlu$canEnq || (!fetchStage$pipelines_0_canDeq || - fetchStage_pipelines_0_first__2934_BITS_194_TO_ETC___d14179) && + fetchStage_pipelines_0_first__2931_BITS_194_TO_ETC___d14175) && coreFix_aluExe_1_rsAlu$canEnq && - !coreFix_aluExe_0_rsAlu_approximateCount__3617__ETC___d13619 ; - assign fetchStage_pipelines_0_canDeq__2932_AND_NOT_fe_ETC___d14265 = + !coreFix_aluExe_0_rsAlu_approximateCount__3613__ETC___d13615 ; + assign fetchStage_pipelines_0_canDeq__2929_AND_NOT_fe_ETC___d14261 = fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2934_BITS_19_ETC___d14262 && + NOT_fetchStage_pipelines_0_first__2931_BITS_19_ETC___d14258 && (fetchStage$pipelines_0_first[194:192] == 3'd0 || fetchStage$pipelines_0_first[194:192] == 3'd1) && - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3613_co_ETC___d13623 ; - assign fetchStage_pipelines_0_canDeq__2932_AND_NOT_fe_ETC___d14370 = + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3609_co_ETC___d13619 ; + assign fetchStage_pipelines_0_canDeq__2929_AND_NOT_fe_ETC___d14366 = fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2934_BITS_19_ETC___d14262 && - fetchStage_pipelines_0_first__2934_BITS_194_TO_ETC___d13910 || + NOT_fetchStage_pipelines_0_first__2931_BITS_19_ETC___d14258 && + fetchStage_pipelines_0_first__2931_BITS_194_TO_ETC___d13906 || !coreFix_aluExe_0_rsAlu$canEnq ; - assign fetchStage_pipelines_0_canDeq__2932_AND_fetchS_ETC___d14253 = + assign fetchStage_pipelines_0_canDeq__2929_AND_fetchS_ETC___d14249 = fetchStage$pipelines_0_canDeq && - fetchStage_pipelines_0_first__2934_BITS_194_TO_ETC___d14127 || + fetchStage_pipelines_0_first__2931_BITS_194_TO_ETC___d14123 || !fetchStage$pipelines_1_canDeq || fetchStage$RDY_pipelines_1_first && - (fetchStage_pipelines_1_first__2943_BITS_194_TO_ETC___d14138 || + (fetchStage_pipelines_1_first__2940_BITS_194_TO_ETC___d14134 || !regRenamingTable$rename_1_canRename || - fetchStage_pipelines_1_first__2943_BITS_199_TO_ETC___d14150 || - IF_fetchStage_pipelines_1_first__2943_BITS_194_ETC___d14249) && - IF_fetchStage_RDY_pipelines_1_first__2942_AND__ETC___d14070 ; - assign fetchStage_pipelines_0_canDeq__2932_AND_regRen_ETC___d14189 = + fetchStage_pipelines_1_first__2940_BITS_199_TO_ETC___d14146 || + IF_fetchStage_pipelines_1_first__2940_BITS_194_ETC___d14245) && + IF_fetchStage_RDY_pipelines_1_first__2939_AND__ETC___d14066 ; + assign fetchStage_pipelines_0_canDeq__2929_AND_regRen_ETC___d14185 = fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3582_AND__ETC___d13653 && + regRenamingTable_rename_0_canRename__3578_AND__ETC___d13649 && (fetchStage$pipelines_0_first[194:192] == 3'd3 || fetchStage$pipelines_0_first[194:192] == 3'd4) ; - assign fetchStage_pipelines_0_canDeq__2932_AND_regRen_ETC___d14196 = + assign fetchStage_pipelines_0_canDeq__2929_AND_regRen_ETC___d14192 = fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3582_AND__ETC___d13653 && + regRenamingTable_rename_0_canRename__3578_AND__ETC___d13649 && fetchStage$pipelines_0_first[194:192] == 3'd2 && - IF_fetchStage_pipelines_0_first__2934_BITS_191_ETC___d13635 || + IF_fetchStage_pipelines_0_first__2931_BITS_191_ETC___d13631 || !coreFix_memExe_rsMem$canEnq || - CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q237 ; - assign fetchStage_pipelines_0_canDeq__2932_AND_regRen_ETC___d14218 = - fetchStage_pipelines_0_canDeq__2932_AND_regRen_ETC___d14189 || + CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q229 ; + assign fetchStage_pipelines_0_canDeq__2929_AND_regRen_ETC___d14214 = + fetchStage_pipelines_0_canDeq__2929_AND_regRen_ETC___d14185 || !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq || fetchStage$pipelines_0_canDeq && (fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || - NOT_regRenamingTable_rename_0_canRename__3582__ETC___d14002 || - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d14209) ; - assign fetchStage_pipelines_0_canDeq__2932_AND_regRen_ETC___d14230 = - fetchStage_pipelines_0_canDeq__2932_AND_regRen_ETC___d14196 || + NOT_regRenamingTable_rename_0_canRename__3578__ETC___d13998 || + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d14205) ; + assign fetchStage_pipelines_0_canDeq__2929_AND_regRen_ETC___d14226 = + fetchStage_pipelines_0_canDeq__2929_AND_regRen_ETC___d14192 || fetchStage$pipelines_0_canDeq && (fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || - NOT_regRenamingTable_rename_0_canRename__3582__ETC___d14002 || - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d14221) ; - assign fetchStage_pipelines_0_canDeq__2932_AND_regRen_ETC___d14521 = + NOT_regRenamingTable_rename_0_canRename__3578__ETC___d13998 || + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d14217) ; + assign fetchStage_pipelines_0_canDeq__2929_AND_regRen_ETC___d14517 = fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3582_AND__ETC___d14519 || + regRenamingTable_rename_0_canRename__3578_AND__ETC___d14515 || !coreFix_memExe_rsMem$canEnq || - CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q237 ; - assign fetchStage_pipelines_0_canDeq__2932_AND_specTa_ETC___d14348 = + CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q229 ; + assign fetchStage_pipelines_0_canDeq__2929_AND_specTa_ETC___d14344 = fetchStage$pipelines_0_canDeq && specTagManager$canClaim && regRenamingTable$rename_0_canRename && - !checkForException___d13180[4] && + !checkForException___d13176[4] && rob$enqPort_0_canEnq && - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d13663 && + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d13659 && fetchStage$pipelines_0_first[194:192] == 3'd1 ; - assign fetchStage_pipelines_0_first__2934_BITS_194_TO_ETC___d13210 = + assign fetchStage_pipelines_0_first__2931_BITS_194_TO_ETC___d13206 = (fetchStage$pipelines_0_first[194:192] == 3'd0 && fetchStage$pipelines_0_first[178:174] == 5'd15 || - rs1__h659223 != 5'd0 || - imm__h659224 != 32'd0) && - IF_fetchStage_pipelines_0_first__2934_BIT_173__ETC___d13207[11:10] == + rs1__h658887 != 5'd0 || + imm__h658888 != 32'd0) && + IF_fetchStage_pipelines_0_first__2931_BIT_173__ETC___d13203[11:10] == 2'b11 ; - assign fetchStage_pipelines_0_first__2934_BITS_194_TO_ETC___d13910 = + assign fetchStage_pipelines_0_first__2931_BITS_194_TO_ETC___d13906 = (fetchStage$pipelines_0_first[194:192] == 3'd0 || fetchStage$pipelines_0_first[194:192] == 3'd1) && - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3613_co_ETC___d13623 && + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3609_co_ETC___d13619 && (!coreFix_aluExe_1_rsAlu$canEnq || - coreFix_aluExe_0_rsAlu_approximateCount__3617__ETC___d13619) ; - assign fetchStage_pipelines_0_first__2934_BITS_194_TO_ETC___d14009 = + coreFix_aluExe_0_rsAlu_approximateCount__3613__ETC___d13615) ; + assign fetchStage_pipelines_0_first__2931_BITS_194_TO_ETC___d14005 = fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || - renameStage_rg_m_halt_req_2961_BIT_4_2962_OR_f_ETC___d14005 ; - assign fetchStage_pipelines_0_first__2934_BITS_194_TO_ETC___d14121 = + renameStage_rg_m_halt_req_2958_BIT_4_2959_OR_f_ETC___d14001 ; + assign fetchStage_pipelines_0_first__2931_BITS_194_TO_ETC___d14117 = fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || !regRenamingTable$rename_0_canRename || - renameStage_rg_m_halt_req_2961_BIT_4_2962_OR_f_ETC___d14085 || - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d14110 && - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d14119 ; - assign fetchStage_pipelines_0_first__2934_BITS_194_TO_ETC___d14127 = + renameStage_rg_m_halt_req_2958_BIT_4_2959_OR_f_ETC___d14081 || + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d14106 && + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d14115 ; + assign fetchStage_pipelines_0_first__2931_BITS_194_TO_ETC___d14123 = fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || !regRenamingTable$rename_0_canRename || - renameStage_rg_m_halt_req_2961_BIT_4_2962_OR_f_ETC___d14085 || - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d14126 ; - assign fetchStage_pipelines_0_first__2934_BITS_194_TO_ETC___d14144 = + renameStage_rg_m_halt_req_2958_BIT_4_2959_OR_f_ETC___d14081 || + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d14122 ; + assign fetchStage_pipelines_0_first__2931_BITS_194_TO_ETC___d14140 = fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || !regRenamingTable$rename_0_canRename || fetchStage$pipelines_0_first[68] || - checkForException___d13180[4] || + checkForException___d13176[4] || !rob$enqPort_0_canEnq || - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d14126 ; - assign fetchStage_pipelines_0_first__2934_BITS_194_TO_ETC___d14156 = + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d14122 ; + assign fetchStage_pipelines_0_first__2931_BITS_194_TO_ETC___d14152 = fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || - NOT_regRenamingTable_rename_0_canRename__3582__ETC___d13926 || + NOT_regRenamingTable_rename_0_canRename__3578__ETC___d13922 || fetchStage$pipelines_0_first[194:192] != 3'd0 && fetchStage$pipelines_0_first[194:192] != 3'd1 || - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3613_co_ETC___d13623 || + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3609_co_ETC___d13619 || coreFix_aluExe_1_rsAlu$canEnq && - !coreFix_aluExe_0_rsAlu_approximateCount__3617__ETC___d13619 ; - assign fetchStage_pipelines_0_first__2934_BITS_194_TO_ETC___d14163 = + !coreFix_aluExe_0_rsAlu_approximateCount__3613__ETC___d13615 ; + assign fetchStage_pipelines_0_first__2931_BITS_194_TO_ETC___d14159 = fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || - NOT_regRenamingTable_rename_0_canRename__3582__ETC___d13926 || + NOT_regRenamingTable_rename_0_canRename__3578__ETC___d13922 || fetchStage$pipelines_0_first[194:192] != 3'd0 && fetchStage$pipelines_0_first[194:192] != 3'd1 || - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3613_co_ETC___d13623 || + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3609_co_ETC___d13619 || coreFix_aluExe_0_rsAlu$canEnq && - coreFix_aluExe_0_rsAlu_approximateCount__3617__ETC___d13619 ; - assign fetchStage_pipelines_0_first__2934_BITS_194_TO_ETC___d14179 = + coreFix_aluExe_0_rsAlu_approximateCount__3613__ETC___d13615 ; + assign fetchStage_pipelines_0_first__2931_BITS_194_TO_ETC___d14175 = fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || !regRenamingTable$rename_0_canRename || - fetchStage_pipelines_0_first__2934_BITS_199_TO_ETC___d13683 || + fetchStage_pipelines_0_first__2931_BITS_199_TO_ETC___d13679 || fetchStage$pipelines_0_first[194:192] != 3'd0 && fetchStage$pipelines_0_first[194:192] != 3'd1 || - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3613_co_ETC___d13623 ; - assign fetchStage_pipelines_0_first__2934_BITS_199_TO_ETC___d13683 = + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3609_co_ETC___d13619 ; + assign fetchStage_pipelines_0_first__2931_BITS_199_TO_ETC___d13679 = fetchStage$pipelines_0_first[199:195] == 5'd0 || fetchStage$pipelines_0_first[199:195] == 5'd21 || fetchStage$pipelines_0_first[199:195] == 5'd17 || @@ -30255,22 +30105,22 @@ module mkCore(CLK, fetchStage$pipelines_0_first[199:195] == 5'd20 || renameStage_rg_m_halt_req[4] || fetchStage$pipelines_0_first[68] || - checkForException___d13180[4] || - csrf_fs_reg_read__1726_EQ_0_3169_AND_fetchStag_ETC___d13676 || + checkForException___d13176[4] || + csrf_fs_reg_read__1726_EQ_0_3165_AND_fetchStag_ETC___d13672 || !rob$enqPort_0_canEnq || !epochManager$checkEpoch_0_check ; - assign fetchStage_pipelines_0_first__2934_BIT_68_2963_ETC___d14000 = + assign fetchStage_pipelines_0_first__2931_BIT_68_2960_ETC___d13996 = fetchStage$pipelines_0_first[68] || - checkForException___d13180[4] || - csrf_fs_reg_read__1726_EQ_0_3169_AND_fetchStag_ETC___d13676 || + checkForException___d13176[4] || + csrf_fs_reg_read__1726_EQ_0_3165_AND_fetchStag_ETC___d13672 || !rob$enqPort_0_canEnq || !epochManager$checkEpoch_0_check ; - assign fetchStage_pipelines_1_first__2943_BITS_194_TO_ETC___d14138 = + assign fetchStage_pipelines_1_first__2940_BITS_194_TO_ETC___d14134 = fetchStage$pipelines_1_first[194:192] == 3'd1 && (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3582_AND__ETC___d14135 || + regRenamingTable_rename_0_canRename__3578_AND__ETC___d14131 || !specTagManager$canClaim) ; - assign fetchStage_pipelines_1_first__2943_BITS_199_TO_ETC___d14150 = + assign fetchStage_pipelines_1_first__2940_BITS_199_TO_ETC___d14146 = fetchStage$pipelines_1_first[199:195] == 5'd0 || fetchStage$pipelines_1_first[199:195] == 5'd21 || fetchStage$pipelines_1_first[199:195] == 5'd17 || @@ -30282,116 +30132,116 @@ module mkCore(CLK, fetchStage$pipelines_1_first[199:195] == 5'd20 || renameStage_rg_m_halt_req[4] || fetchStage$pipelines_1_first[68] || - checkForException___d13863[4] || - csrf_fs_reg_read__1726_EQ_0_3169_AND_fetchStag_ETC___d13956 || + checkForException___d13859[4] || + csrf_fs_reg_read__1726_EQ_0_3165_AND_fetchStag_ETC___d13952 || !rob$enqPort_1_canEnq || !epochManager$checkEpoch_1_check || csrf_rg_dcsr[2] || fetchStage$pipelines_0_canDeq && - fetchStage_pipelines_0_first__2934_BITS_194_TO_ETC___d14144 ; - assign fetchStage_pipelines_1_first__2943_BIT_173_375_ETC___d13842 = + fetchStage_pipelines_0_first__2931_BITS_194_TO_ETC___d14140 ; + assign fetchStage_pipelines_1_first__2940_BIT_173_375_ETC___d13838 = { fetchStage$pipelines_1_first[173], - CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q235 } ; - assign fflags__h723884 = - NOT_rob_deqPort_0_canDeq__5214_5215_OR_rob_deq_ETC___d15503 ? - y_avValue_fst__h723827 : - IF_rob_deqPort_0_canDeq__5214_THEN_IF_NOT_rob__ETC___d15509 ; - assign fflags_csr__read__h613508 = { 59'd0, csrf_fflags_reg } ; - assign frm_csr__read__h613519 = { 61'd0, csrf_frm_reg } ; - assign guard__h348393 = - { IF_sfdin56488_BIT_33_THEN_2_ELSE_0__q30[1], - { sfdin__h356488[32:0], 23'd0 } != 56'd0 } ; - assign guard__h357102 = - { IF_theResult___snd65101_BIT_33_THEN_2_ELSE_0__q32[1], - { _theResult___snd__h365101[32:0], 23'd0 } != 56'd0 } ; - assign guard__h366032 = - { IF_sfdin74254_BIT_33_THEN_2_ELSE_0__q40[1], - { sfdin__h374254[32:0], 23'd0 } != 56'd0 } ; - assign guard__h366630 = x__h366732 != 57'd0 ; - assign guard__h374868 = - { IF_theResult___snd82891_BIT_33_THEN_2_ELSE_0__q45[1], - { _theResult___snd__h382891[32:0], 23'd0 } != 56'd0 } ; - assign guard__h394092 = - { IF_sfdin02185_BIT_33_THEN_2_ELSE_0__q65[1], - { sfdin__h402185[32:0], 23'd0 } != 56'd0 } ; - assign guard__h402799 = - { IF_theResult___snd10798_BIT_33_THEN_2_ELSE_0__q67[1], - { _theResult___snd__h410798[32:0], 23'd0 } != 56'd0 } ; - assign guard__h411729 = - { IF_sfdin19951_BIT_33_THEN_2_ELSE_0__q75[1], - { sfdin__h419951[32:0], 23'd0 } != 56'd0 } ; - assign guard__h412327 = x__h412429 != 57'd0 ; - assign guard__h420565 = - { IF_theResult___snd28588_BIT_33_THEN_2_ELSE_0__q80[1], - { _theResult___snd__h428588[32:0], 23'd0 } != 56'd0 } ; - assign guard__h439787 = - { IF_sfdin47880_BIT_33_THEN_2_ELSE_0__q100[1], - { sfdin__h447880[32:0], 23'd0 } != 56'd0 } ; - assign guard__h448494 = - { IF_theResult___snd56493_BIT_33_THEN_2_ELSE_0__q102[1], - { _theResult___snd__h456493[32:0], 23'd0 } != 56'd0 } ; - assign guard__h457424 = - { IF_sfdin65646_BIT_33_THEN_2_ELSE_0__q110[1], - { sfdin__h465646[32:0], 23'd0 } != 56'd0 } ; - assign guard__h458022 = x__h458124 != 57'd0 ; - assign guard__h466260 = - { IF_theResult___snd74283_BIT_33_THEN_2_ELSE_0__q115[1], - { _theResult___snd__h474283[32:0], 23'd0 } != 56'd0 } ; - assign guard__h496373 = - { IF_theResult___snd04285_BIT_4_THEN_2_ELSE_0__q135[1], - { _theResult___snd__h504285[3:0], 52'd0 } != 56'd0 } ; - assign guard__h505685 = - { IF_sfdin13905_BIT_4_THEN_2_ELSE_0__q139[1], - { sfdin__h513905[3:0], 52'd0 } != 56'd0 } ; - assign guard__h506283 = x__h506383 != 57'd0 ; - assign guard__h514754 = - { IF_theResult___snd22690_BIT_4_THEN_2_ELSE_0__q142[1], - { _theResult___snd__h522690[3:0], 52'd0 } != 56'd0 } ; - assign guard__h535226 = - { IF_theResult___snd43138_BIT_4_THEN_2_ELSE_0__q175[1], - { _theResult___snd__h543138[3:0], 52'd0 } != 56'd0 } ; - assign guard__h544538 = - { IF_sfdin52758_BIT_4_THEN_2_ELSE_0__q179[1], - { sfdin__h552758[3:0], 52'd0 } != 56'd0 } ; - assign guard__h545136 = x__h545236 != 57'd0 ; - assign guard__h553607 = - { IF_theResult___snd61543_BIT_4_THEN_2_ELSE_0__q182[1], - { _theResult___snd__h561543[3:0], 52'd0 } != 56'd0 } ; - assign guard__h574530 = - { IF_theResult___snd82442_BIT_4_THEN_2_ELSE_0__q152[1], - { _theResult___snd__h582442[3:0], 52'd0 } != 56'd0 } ; - assign guard__h583842 = - { IF_sfdin92062_BIT_4_THEN_2_ELSE_0__q156[1], - { sfdin__h592062[3:0], 52'd0 } != 56'd0 } ; - assign guard__h584440 = x__h584540 != 57'd0 ; - assign guard__h592911 = - { IF_theResult___snd00847_BIT_4_THEN_2_ELSE_0__q159[1], - { _theResult___snd__h600847[3:0], 52'd0 } != 56'd0 } ; - assign idx__h686963 = + CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q227 } ; + assign fflags__h720016 = + NOT_rob_deqPort_0_canDeq__5156_5157_OR_rob_deq_ETC___d15348 ? + y_avValue_snd_fst__h720076 : + IF_rob_deqPort_0_canDeq__5156_THEN_IF_NOT_rob__ETC___d15354 ; + assign fflags_csr__read__h613199 = { 59'd0, csrf_fflags_reg } ; + assign frm_csr__read__h613210 = { 61'd0, csrf_frm_reg } ; + assign guard__h348084 = + { IF_sfdin56179_BIT_33_THEN_2_ELSE_0__q22[1], + { sfdin__h356179[32:0], 23'd0 } != 56'd0 } ; + assign guard__h356793 = + { IF_theResult___snd64792_BIT_33_THEN_2_ELSE_0__q24[1], + { _theResult___snd__h364792[32:0], 23'd0 } != 56'd0 } ; + assign guard__h365723 = + { IF_sfdin73945_BIT_33_THEN_2_ELSE_0__q32[1], + { sfdin__h373945[32:0], 23'd0 } != 56'd0 } ; + assign guard__h366321 = x__h366423 != 57'd0 ; + assign guard__h374559 = + { IF_theResult___snd82582_BIT_33_THEN_2_ELSE_0__q37[1], + { _theResult___snd__h382582[32:0], 23'd0 } != 56'd0 } ; + assign guard__h393783 = + { IF_sfdin01876_BIT_33_THEN_2_ELSE_0__q57[1], + { sfdin__h401876[32:0], 23'd0 } != 56'd0 } ; + assign guard__h402490 = + { IF_theResult___snd10489_BIT_33_THEN_2_ELSE_0__q59[1], + { _theResult___snd__h410489[32:0], 23'd0 } != 56'd0 } ; + assign guard__h411420 = + { IF_sfdin19642_BIT_33_THEN_2_ELSE_0__q67[1], + { sfdin__h419642[32:0], 23'd0 } != 56'd0 } ; + assign guard__h412018 = x__h412120 != 57'd0 ; + assign guard__h420256 = + { IF_theResult___snd28279_BIT_33_THEN_2_ELSE_0__q72[1], + { _theResult___snd__h428279[32:0], 23'd0 } != 56'd0 } ; + assign guard__h439478 = + { IF_sfdin47571_BIT_33_THEN_2_ELSE_0__q92[1], + { sfdin__h447571[32:0], 23'd0 } != 56'd0 } ; + assign guard__h448185 = + { IF_theResult___snd56184_BIT_33_THEN_2_ELSE_0__q94[1], + { _theResult___snd__h456184[32:0], 23'd0 } != 56'd0 } ; + assign guard__h457115 = + { IF_sfdin65337_BIT_33_THEN_2_ELSE_0__q102[1], + { sfdin__h465337[32:0], 23'd0 } != 56'd0 } ; + assign guard__h457713 = x__h457815 != 57'd0 ; + assign guard__h465951 = + { IF_theResult___snd73974_BIT_33_THEN_2_ELSE_0__q107[1], + { _theResult___snd__h473974[32:0], 23'd0 } != 56'd0 } ; + assign guard__h496064 = + { IF_theResult___snd03976_BIT_4_THEN_2_ELSE_0__q127[1], + { _theResult___snd__h503976[3:0], 52'd0 } != 56'd0 } ; + assign guard__h505376 = + { IF_sfdin13596_BIT_4_THEN_2_ELSE_0__q131[1], + { sfdin__h513596[3:0], 52'd0 } != 56'd0 } ; + assign guard__h505974 = x__h506074 != 57'd0 ; + assign guard__h514445 = + { IF_theResult___snd22381_BIT_4_THEN_2_ELSE_0__q134[1], + { _theResult___snd__h522381[3:0], 52'd0 } != 56'd0 } ; + assign guard__h534917 = + { IF_theResult___snd42829_BIT_4_THEN_2_ELSE_0__q167[1], + { _theResult___snd__h542829[3:0], 52'd0 } != 56'd0 } ; + assign guard__h544229 = + { IF_sfdin52449_BIT_4_THEN_2_ELSE_0__q171[1], + { sfdin__h552449[3:0], 52'd0 } != 56'd0 } ; + assign guard__h544827 = x__h544927 != 57'd0 ; + assign guard__h553298 = + { IF_theResult___snd61234_BIT_4_THEN_2_ELSE_0__q174[1], + { _theResult___snd__h561234[3:0], 52'd0 } != 56'd0 } ; + assign guard__h574221 = + { IF_theResult___snd82133_BIT_4_THEN_2_ELSE_0__q144[1], + { _theResult___snd__h582133[3:0], 52'd0 } != 56'd0 } ; + assign guard__h583533 = + { IF_sfdin91753_BIT_4_THEN_2_ELSE_0__q148[1], + { sfdin__h591753[3:0], 52'd0 } != 56'd0 } ; + assign guard__h584131 = x__h584231 != 57'd0 ; + assign guard__h592602 = + { IF_theResult___snd00538_BIT_4_THEN_2_ELSE_0__q151[1], + { _theResult___snd__h600538[3:0], 52'd0 } != 56'd0 } ; + assign idx__h686627 = fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2934_BITS_19_ETC___d13911 || + NOT_fetchStage_pipelines_0_first__2931_BITS_19_ETC___d13907 || !coreFix_aluExe_0_rsAlu$canEnq || - NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d13935 ; - assign imm__h659224 = + NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d13931 ; + assign imm__h658888 = fetchStage$pipelines_0_first[160] ? fetchStage$pipelines_0_first[159:128] : 32'd0 ; - assign k__h671729 = + assign k__h671393 = !coreFix_aluExe_0_rsAlu$canEnq || coreFix_aluExe_1_rsAlu$canEnq && - !coreFix_aluExe_0_rsAlu_approximateCount__3617__ETC___d13619 ; - assign mcause_csr__read__h615180 = - { r1__read__h618205, csrf_mcause_code_reg } ; - assign mcounteren_csr__read__h614925 = - { r1__read__h618192, csrf_mcounteren_cy_reg } ; - assign medeleg_csr__read__h614525 = - { r1__read__h618028, csrf_medeleg_9_0_reg } ; - assign mideleg_csr__read__h614620 = - { r1__read__h618045, csrf_mideleg_1_0_reg } ; - assign mie_csr__read__h614751 = - { r1__read__h618069, csrf_software_int_en_vec_0 } ; - assign mip_csr__read__h615420 = - { r1__read__h618211, csrf_software_int_pend_vec_0 } ; + !coreFix_aluExe_0_rsAlu_approximateCount__3613__ETC___d13615 ; + assign mcause_csr__read__h614864 = + { r1__read__h617875, csrf_mcause_code_reg } ; + assign mcounteren_csr__read__h614609 = + { r1__read__h617862, csrf_mcounteren_cy_reg } ; + assign medeleg_csr__read__h614216 = + { r1__read__h617705, csrf_medeleg_9_0_reg } ; + assign mideleg_csr__read__h614311 = + { r1__read__h617722, csrf_mideleg_1_0_reg } ; + assign mie_csr__read__h614435 = + { r1__read__h617746, csrf_software_int_en_vec_0 } ; + assign mip_csr__read__h615097 = + { r1__read__h617881, csrf_software_int_pend_vec_0 } ; assign mmio_cRqQ_enqReq_dummy2_2_read__32_AND_IF_mmio_ETC___d444 = mmio_cRqQ_enqReq_dummy2_2$Q_OUT && IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmio_c_ETC___d339 || @@ -30424,18 +30274,18 @@ module mkCore(CLK, !mmio_dataRespQ_deqReq_lat_0$whas && !mmio_dataRespQ_deqReq_rl) && mmio_dataRespQ_full ; - assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13225 = + assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13221 = mmio_pRqQ_empty && epochManager$checkEpoch_0_check && (renameStage_rg_m_halt_req[4] || fetchStage$pipelines_0_first[68] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13222) ; - assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13513 = + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13218) ; + assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13509 = mmio_pRqQ_empty && epochManager$checkEpoch_0_check && !renameStage_rg_m_halt_req[4] && !fetchStage$pipelines_0_first[68] && - NOT_IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_296_ETC___d13510 ; - assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13531 = - mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13513 && + NOT_IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_296_ETC___d13506 ; + assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13527 = + mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13509 && (fetchStage$pipelines_0_first[199:195] == 5'd0 || fetchStage$pipelines_0_first[199:195] == 5'd21 || fetchStage$pipelines_0_first[199:195] == 5'd17 || @@ -30446,13 +30296,13 @@ module mkCore(CLK, fetchStage$pipelines_0_first[199:195] == 5'd19 || fetchStage$pipelines_0_first[199:195] == 5'd20) && rob$isEmpty ; - assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14257 = + assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14253 = mmio_pRqQ_empty && epochManager$checkEpoch_0_check && !renameStage_rg_m_halt_req[4] && !fetchStage$pipelines_0_first[68] && - NOT_IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_296_ETC___d13597 ; - assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14259 = - mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14257 && + NOT_IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_296_ETC___d13593 ; + assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14255 = + mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14253 && fetchStage$pipelines_0_first[199:195] != 5'd0 && fetchStage$pipelines_0_first[199:195] != 5'd21 && fetchStage$pipelines_0_first[199:195] != 5'd17 && @@ -30475,292 +30325,292 @@ module mkCore(CLK, (!mmio_pRsQ_deqReq_dummy2_2$Q_OUT || !mmio_pRsQ_deqReq_lat_0$whas && !mmio_pRsQ_deqReq_rl) && mmio_pRsQ_full ; - assign msip__h75940 = csrf_software_int_pend_vec_3 ; - assign mstatus_csr__read__h614377 = { r1__read__h617903, csrf_ie_vec_0 } ; - assign mtvec_csr__read__h614833 = - { r1__read__h618187, csrf_mtvec_mode_low_reg } ; - assign n___1__h199875 = + assign msip__h75632 = csrf_software_int_pend_vec_3 ; + assign mstatus_csr__read__h614068 = { r1__read__h617580, csrf_ie_vec_0 } ; + assign mtvec_csr__read__h614517 = + { r1__read__h617857, csrf_mtvec_mode_low_reg } ; + assign n___1__h199567 = { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[78] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[70:63] : - x__h198472[63:56], + x__h198164[63:56], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[77] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[62:55] : - x__h198472[55:48], + x__h198164[55:48], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[76] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[54:47] : - x__h198472[47:40], + x__h198164[47:40], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[75] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[46:39] : - x__h198472[39:32], + x__h198164[39:32], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[74] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[38:31] : - x__h198472[31:24], + x__h198164[31:24], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[73] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[30:23] : - x__h198472[23:16], + x__h198164[23:16], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[72] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[22:15] : - x__h198472[15:8], + x__h198164[15:8], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[71] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[14:7] : - x__h198472[7:0] } ; - assign n__read__h615524 = + x__h198164[7:0] } ; + assign n__read__h615201 = (csrf_mcycle_ehr_data_dummy2_0$Q_OUT && csrf_mcycle_ehr_data_dummy2_1$Q_OUT) ? csrf_mcycle_ehr_data_rl : 64'd0 ; - assign n__read__h615715 = + assign n__read__h615392 = (csrf_minstret_ehr_data_dummy2_0$Q_OUT && csrf_minstret_ehr_data_dummy2_1$Q_OUT) ? csrf_minstret_ehr_data_rl : 64'd0 ; - assign n__read__h6636 = + assign n__read__h6329 = csrf_mcycle_ehr_data_dummy2_1$Q_OUT ? (csrf_mcycle_ehr_data_lat_0$whas ? - upd__h6750 : + upd__h6443 : csrf_mcycle_ehr_data_rl) : 64'd0 ; - assign n__read__h719255 = + assign n__read__h717124 = csrf_minstret_ehr_data_dummy2_1$Q_OUT ? IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8 : 64'd0 ; - assign next_deqP___1__h299100 = + assign next_deqP___1__h298792 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP == 3'd7) ? 3'd0 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP + 3'd1 ; - assign next_deqP___1__h307096 = + assign next_deqP___1__h306788 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP + 1'd1 ; - assign next_deqP___1__h313377 = + assign next_deqP___1__h313069 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP + 1'd1 ; - assign next_deqP___1__h321231 = + assign next_deqP___1__h320923 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP + 1'd1 ; - assign next_deqP___1__h331288 = coreFix_memExe_memRespLdQ_deqP + 1'd1 ; - assign next_deqP___1__h334513 = coreFix_memExe_forwardQ_deqP + 1'd1 ; - assign next_pc__h718537 = + assign next_deqP___1__h330980 = coreFix_memExe_memRespLdQ_deqP + 1'd1 ; + assign next_deqP___1__h334205 = coreFix_memExe_forwardQ_deqP + 1'd1 ; + assign next_pc__h716406 = (rob$deqPort_0_deq_data[97:96] == 2'd0) ? rob$deqPort_0_deq_data[95:32] : - rob_deqPort_0_deq_data__4547_BITS_282_TO_219_4_ETC___d15180 ; - assign out___1_sfd__h485010 = { f1_sfd__h484947, 29'd0 } ; - assign out___1_sfd__h524004 = { f2_sfd__h523941, 29'd0 } ; - assign out___1_sfd__h563308 = { f3_sfd__h563245, 29'd0 } ; - assign out_exp__h357013 = - sfdin__h356488[34] ? - _theResult___exp__h357010 : - _theResult___fst_exp__h356494 ; - assign out_exp__h365595 = - _theResult___snd__h365101[34] ? - _theResult___exp__h365592 : - _theResult___fst_exp__h365150 ; - assign out_exp__h374779 = - sfdin__h374254[34] ? - _theResult___exp__h374776 : - _theResult___fst_exp__h374260 ; - assign out_exp__h383415 = - _theResult___snd__h382891[34] ? - _theResult___exp__h383412 : - _theResult___fst_exp__h382945 ; - assign out_exp__h402710 = - sfdin__h402185[34] ? - _theResult___exp__h402707 : - _theResult___fst_exp__h402191 ; - assign out_exp__h411292 = - _theResult___snd__h410798[34] ? - _theResult___exp__h411289 : - _theResult___fst_exp__h410847 ; - assign out_exp__h420476 = - sfdin__h419951[34] ? - _theResult___exp__h420473 : - _theResult___fst_exp__h419957 ; - assign out_exp__h429112 = - _theResult___snd__h428588[34] ? - _theResult___exp__h429109 : - _theResult___fst_exp__h428642 ; - assign out_exp__h448405 = - sfdin__h447880[34] ? - _theResult___exp__h448402 : - _theResult___fst_exp__h447886 ; - assign out_exp__h456987 = - _theResult___snd__h456493[34] ? - _theResult___exp__h456984 : - _theResult___fst_exp__h456542 ; - assign out_exp__h466171 = - sfdin__h465646[34] ? - _theResult___exp__h466168 : - _theResult___fst_exp__h465652 ; - assign out_exp__h474807 = - _theResult___snd__h474283[34] ? - _theResult___exp__h474804 : - _theResult___fst_exp__h474337 ; - assign out_exp__h504992 = - _theResult___snd__h504285[5] ? - _theResult___exp__h504989 : - _theResult___fst_exp__h504334 ; - assign out_exp__h514643 = - sfdin__h513905[5] ? - _theResult___exp__h514640 : - _theResult___fst_exp__h513911 ; - assign out_exp__h523427 = - _theResult___snd__h522690[5] ? - _theResult___exp__h523424 : - _theResult___fst_exp__h522744 ; - assign out_exp__h543845 = - _theResult___snd__h543138[5] ? - _theResult___exp__h543842 : - _theResult___fst_exp__h543187 ; - assign out_exp__h553496 = - sfdin__h552758[5] ? - _theResult___exp__h553493 : - _theResult___fst_exp__h552764 ; - assign out_exp__h562280 = - _theResult___snd__h561543[5] ? - _theResult___exp__h562277 : - _theResult___fst_exp__h561597 ; - assign out_exp__h583149 = - _theResult___snd__h582442[5] ? - _theResult___exp__h583146 : - _theResult___fst_exp__h582491 ; - assign out_exp__h592800 = - sfdin__h592062[5] ? - _theResult___exp__h592797 : - _theResult___fst_exp__h592068 ; - assign out_exp__h601584 = - _theResult___snd__h600847[5] ? - _theResult___exp__h601581 : - _theResult___fst_exp__h600901 ; - assign out_f_exp__h383791 = - (_theResult___exp__h383514 == 8'd255 && - _theResult___sfd__h383515 != 23'd0 || + rob_deqPort_0_deq_data__4542_BITS_282_TO_219_4_ETC___d15122 ; + assign out___1_sfd__h484701 = { f1_sfd__h484638, 29'd0 } ; + assign out___1_sfd__h523695 = { f2_sfd__h523632, 29'd0 } ; + assign out___1_sfd__h562999 = { f3_sfd__h562936, 29'd0 } ; + assign out_exp__h356704 = + sfdin__h356179[34] ? + _theResult___exp__h356701 : + _theResult___fst_exp__h356185 ; + assign out_exp__h365286 = + _theResult___snd__h364792[34] ? + _theResult___exp__h365283 : + _theResult___fst_exp__h364841 ; + assign out_exp__h374470 = + sfdin__h373945[34] ? + _theResult___exp__h374467 : + _theResult___fst_exp__h373951 ; + assign out_exp__h383106 = + _theResult___snd__h382582[34] ? + _theResult___exp__h383103 : + _theResult___fst_exp__h382636 ; + assign out_exp__h402401 = + sfdin__h401876[34] ? + _theResult___exp__h402398 : + _theResult___fst_exp__h401882 ; + assign out_exp__h410983 = + _theResult___snd__h410489[34] ? + _theResult___exp__h410980 : + _theResult___fst_exp__h410538 ; + assign out_exp__h420167 = + sfdin__h419642[34] ? + _theResult___exp__h420164 : + _theResult___fst_exp__h419648 ; + assign out_exp__h428803 = + _theResult___snd__h428279[34] ? + _theResult___exp__h428800 : + _theResult___fst_exp__h428333 ; + assign out_exp__h448096 = + sfdin__h447571[34] ? + _theResult___exp__h448093 : + _theResult___fst_exp__h447577 ; + assign out_exp__h456678 = + _theResult___snd__h456184[34] ? + _theResult___exp__h456675 : + _theResult___fst_exp__h456233 ; + assign out_exp__h465862 = + sfdin__h465337[34] ? + _theResult___exp__h465859 : + _theResult___fst_exp__h465343 ; + assign out_exp__h474498 = + _theResult___snd__h473974[34] ? + _theResult___exp__h474495 : + _theResult___fst_exp__h474028 ; + assign out_exp__h504683 = + _theResult___snd__h503976[5] ? + _theResult___exp__h504680 : + _theResult___fst_exp__h504025 ; + assign out_exp__h514334 = + sfdin__h513596[5] ? + _theResult___exp__h514331 : + _theResult___fst_exp__h513602 ; + assign out_exp__h523118 = + _theResult___snd__h522381[5] ? + _theResult___exp__h523115 : + _theResult___fst_exp__h522435 ; + assign out_exp__h543536 = + _theResult___snd__h542829[5] ? + _theResult___exp__h543533 : + _theResult___fst_exp__h542878 ; + assign out_exp__h553187 = + sfdin__h552449[5] ? + _theResult___exp__h553184 : + _theResult___fst_exp__h552455 ; + assign out_exp__h561971 = + _theResult___snd__h561234[5] ? + _theResult___exp__h561968 : + _theResult___fst_exp__h561288 ; + assign out_exp__h582840 = + _theResult___snd__h582133[5] ? + _theResult___exp__h582837 : + _theResult___fst_exp__h582182 ; + assign out_exp__h592491 = + sfdin__h591753[5] ? + _theResult___exp__h592488 : + _theResult___fst_exp__h591759 ; + assign out_exp__h601275 = + _theResult___snd__h600538[5] ? + _theResult___exp__h601272 : + _theResult___fst_exp__h600592 ; + assign out_f_exp__h383482 = + (_theResult___exp__h383205 == 8'd255 && + _theResult___sfd__h383206 != 23'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h383505 ; - assign out_f_exp__h429488 = - (_theResult___exp__h429211 == 8'd255 && - _theResult___sfd__h429212 != 23'd0 || + _theResult___fst_exp__h383196 ; + assign out_f_exp__h429179 = + (_theResult___exp__h428902 == 8'd255 && + _theResult___sfd__h428903 != 23'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h429202 ; - assign out_f_exp__h475183 = - (_theResult___exp__h474906 == 8'd255 && - _theResult___sfd__h474907 != 23'd0 || + _theResult___fst_exp__h428893 ; + assign out_f_exp__h474874 = + (_theResult___exp__h474597 == 8'd255 && + _theResult___sfd__h474598 != 23'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h474897 ; - assign out_f_sfd__h383792 = - (_theResult___exp__h383514 == 8'd255 && - _theResult___sfd__h383515 != 23'd0) ? + _theResult___fst_exp__h474588 ; + assign out_f_sfd__h383483 = + (_theResult___exp__h383205 == 8'd255 && + _theResult___sfd__h383206 != 23'd0) ? 23'd4194304 : - _theResult___sfd__h383515 ; - assign out_f_sfd__h429489 = - (_theResult___exp__h429211 == 8'd255 && - _theResult___sfd__h429212 != 23'd0) ? + _theResult___sfd__h383206 ; + assign out_f_sfd__h429180 = + (_theResult___exp__h428902 == 8'd255 && + _theResult___sfd__h428903 != 23'd0) ? 23'd4194304 : - _theResult___sfd__h429212 ; - assign out_f_sfd__h475184 = - (_theResult___exp__h474906 == 8'd255 && - _theResult___sfd__h474907 != 23'd0) ? + _theResult___sfd__h428903 ; + assign out_f_sfd__h474875 = + (_theResult___exp__h474597 == 8'd255 && + _theResult___sfd__h474598 != 23'd0) ? 23'd4194304 : - _theResult___sfd__h474907 ; - assign out_sfd__h357014 = - sfdin__h356488[34] ? - _theResult___sfd__h357011 : - sfdin__h356488[56:34] ; - assign out_sfd__h365596 = - _theResult___snd__h365101[34] ? - _theResult___sfd__h365593 : - _theResult___snd__h365101[56:34] ; - assign out_sfd__h374780 = - sfdin__h374254[34] ? - _theResult___sfd__h374777 : - sfdin__h374254[56:34] ; - assign out_sfd__h383416 = - _theResult___snd__h382891[34] ? - _theResult___sfd__h383413 : - _theResult___snd__h382891[56:34] ; - assign out_sfd__h402711 = - sfdin__h402185[34] ? - _theResult___sfd__h402708 : - sfdin__h402185[56:34] ; - assign out_sfd__h411293 = - _theResult___snd__h410798[34] ? - _theResult___sfd__h411290 : - _theResult___snd__h410798[56:34] ; - assign out_sfd__h420477 = - sfdin__h419951[34] ? - _theResult___sfd__h420474 : - sfdin__h419951[56:34] ; - assign out_sfd__h429113 = - _theResult___snd__h428588[34] ? - _theResult___sfd__h429110 : - _theResult___snd__h428588[56:34] ; - assign out_sfd__h448406 = - sfdin__h447880[34] ? - _theResult___sfd__h448403 : - sfdin__h447880[56:34] ; - assign out_sfd__h456988 = - _theResult___snd__h456493[34] ? - _theResult___sfd__h456985 : - _theResult___snd__h456493[56:34] ; - assign out_sfd__h466172 = - sfdin__h465646[34] ? - _theResult___sfd__h466169 : - sfdin__h465646[56:34] ; - assign out_sfd__h474808 = - _theResult___snd__h474283[34] ? - _theResult___sfd__h474805 : - _theResult___snd__h474283[56:34] ; - assign out_sfd__h504993 = - _theResult___snd__h504285[5] ? - _theResult___sfd__h504990 : - _theResult___snd__h504285[56:5] ; - assign out_sfd__h514644 = - sfdin__h513905[5] ? - _theResult___sfd__h514641 : - sfdin__h513905[56:5] ; - assign out_sfd__h523428 = - _theResult___snd__h522690[5] ? - _theResult___sfd__h523425 : - _theResult___snd__h522690[56:5] ; - assign out_sfd__h543846 = - _theResult___snd__h543138[5] ? - _theResult___sfd__h543843 : - _theResult___snd__h543138[56:5] ; - assign out_sfd__h553497 = - sfdin__h552758[5] ? - _theResult___sfd__h553494 : - sfdin__h552758[56:5] ; - assign out_sfd__h562281 = - _theResult___snd__h561543[5] ? - _theResult___sfd__h562278 : - _theResult___snd__h561543[56:5] ; - assign out_sfd__h583150 = - _theResult___snd__h582442[5] ? - _theResult___sfd__h583147 : - _theResult___snd__h582442[56:5] ; - assign out_sfd__h592801 = - sfdin__h592062[5] ? - _theResult___sfd__h592798 : - sfdin__h592062[56:5] ; - assign out_sfd__h601585 = - _theResult___snd__h600847[5] ? - _theResult___sfd__h601582 : - _theResult___snd__h600847[56:5] ; - assign pend_ints__h655042 = - { _0_CONCAT_csrf_debug_int_pend_read__1882_CONCAT_ETC___d12978, + _theResult___sfd__h474598 ; + assign out_sfd__h356705 = + sfdin__h356179[34] ? + _theResult___sfd__h356702 : + sfdin__h356179[56:34] ; + assign out_sfd__h365287 = + _theResult___snd__h364792[34] ? + _theResult___sfd__h365284 : + _theResult___snd__h364792[56:34] ; + assign out_sfd__h374471 = + sfdin__h373945[34] ? + _theResult___sfd__h374468 : + sfdin__h373945[56:34] ; + assign out_sfd__h383107 = + _theResult___snd__h382582[34] ? + _theResult___sfd__h383104 : + _theResult___snd__h382582[56:34] ; + assign out_sfd__h402402 = + sfdin__h401876[34] ? + _theResult___sfd__h402399 : + sfdin__h401876[56:34] ; + assign out_sfd__h410984 = + _theResult___snd__h410489[34] ? + _theResult___sfd__h410981 : + _theResult___snd__h410489[56:34] ; + assign out_sfd__h420168 = + sfdin__h419642[34] ? + _theResult___sfd__h420165 : + sfdin__h419642[56:34] ; + assign out_sfd__h428804 = + _theResult___snd__h428279[34] ? + _theResult___sfd__h428801 : + _theResult___snd__h428279[56:34] ; + assign out_sfd__h448097 = + sfdin__h447571[34] ? + _theResult___sfd__h448094 : + sfdin__h447571[56:34] ; + assign out_sfd__h456679 = + _theResult___snd__h456184[34] ? + _theResult___sfd__h456676 : + _theResult___snd__h456184[56:34] ; + assign out_sfd__h465863 = + sfdin__h465337[34] ? + _theResult___sfd__h465860 : + sfdin__h465337[56:34] ; + assign out_sfd__h474499 = + _theResult___snd__h473974[34] ? + _theResult___sfd__h474496 : + _theResult___snd__h473974[56:34] ; + assign out_sfd__h504684 = + _theResult___snd__h503976[5] ? + _theResult___sfd__h504681 : + _theResult___snd__h503976[56:5] ; + assign out_sfd__h514335 = + sfdin__h513596[5] ? + _theResult___sfd__h514332 : + sfdin__h513596[56:5] ; + assign out_sfd__h523119 = + _theResult___snd__h522381[5] ? + _theResult___sfd__h523116 : + _theResult___snd__h522381[56:5] ; + assign out_sfd__h543537 = + _theResult___snd__h542829[5] ? + _theResult___sfd__h543534 : + _theResult___snd__h542829[56:5] ; + assign out_sfd__h553188 = + sfdin__h552449[5] ? + _theResult___sfd__h553185 : + sfdin__h552449[56:5] ; + assign out_sfd__h561972 = + _theResult___snd__h561234[5] ? + _theResult___sfd__h561969 : + _theResult___snd__h561234[56:5] ; + assign out_sfd__h582841 = + _theResult___snd__h582133[5] ? + _theResult___sfd__h582838 : + _theResult___snd__h582133[56:5] ; + assign out_sfd__h592492 = + sfdin__h591753[5] ? + _theResult___sfd__h592489 : + sfdin__h591753[56:5] ; + assign out_sfd__h601276 = + _theResult___snd__h600538[5] ? + _theResult___sfd__h601273 : + _theResult___snd__h600538[56:5] ; + assign pend_ints__h654706 = + { _0_CONCAT_csrf_external_int_en_vec_3_read__1850_ETC___d12974, csrf_software_int_en_vec_3 & csrf_software_int_pend_vec_3, 1'd0, csrf_software_int_en_vec_1 & csrf_software_int_pend_vec_1, csrf_software_int_en_vec_0 & csrf_software_int_pend_vec_0 } ; - assign prv__h725519 = csrf_prv_reg ; - assign prv__h725563 = csrf_mprv_reg ? csrf_mpp_reg : csrf_prv_reg ; - assign q___1__h478352 = + assign prv__h721530 = csrf_prv_reg ; + assign prv__h721574 = csrf_mprv_reg ? csrf_mpp_reg : csrf_prv_reg ; + assign q___1__h478043 = 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[203:140] ; - assign r1__read_BITS_13_TO_0___h655592 = + assign r1__read_BITS_13_TO_0___h655256 = { 4'd0, csrf_mideleg_11_reg, 1'b0, @@ -30768,137 +30618,134 @@ module mkCore(CLK, 1'b0, csrf_mideleg_5_3_reg, 1'b0 } ; - assign r1__read_BITS_13_TO_12___h659092 = csrf_fs_reg ; - assign r1__read_BIT_20___h659752 = csrf_tw_reg ; - assign r1__read__h616692 = { r1__read__h616694, csrf_ie_vec_1 } ; - assign r1__read__h616694 = { r1__read__h616696, 2'b0 } ; - assign r1__read__h616696 = { r1__read__h616698, csrf_prev_ie_vec_0 } ; - assign r1__read__h616698 = { r1__read__h616700, csrf_prev_ie_vec_1 } ; - assign r1__read__h616700 = { r1__read__h616702, 2'b0 } ; - assign r1__read__h616702 = { r1__read__h616704, csrf_spp_reg } ; - assign r1__read__h616704 = { r1__read__h616706, 4'b0 } ; - assign r1__read__h616706 = { r1__read__h616708, csrf_fs_reg } ; - assign r1__read__h616708 = { r1__read__h616710, 2'd0 } ; - assign r1__read__h616710 = { r1__read__h616712, 1'b0 } ; - assign r1__read__h616712 = { r1__read__h616714, csrf_sum_reg } ; - assign r1__read__h616714 = { r1__read__h616716, csrf_mxr_reg } ; - assign r1__read__h616716 = { r1__read__h616718, 12'b0 } ; - assign r1__read__h616718 = { r1__read__h616720, 2'b10 } ; - assign r1__read__h616720 = { r__h616724, 29'b0 } ; - assign r1__read__h617096 = - { r1__read__h617098, csrf_software_int_en_vec_1 } ; - assign r1__read__h617098 = { r1__read__h617100, 2'b0 } ; - assign r1__read__h617100 = { r1__read__h617102, csrf_timer_int_en_vec_0 } ; - assign r1__read__h617102 = { r1__read__h617104, csrf_timer_int_en_vec_1 } ; - assign r1__read__h617104 = { r1__read__h617106, 2'b0 } ; - assign r1__read__h617106 = - { r1__read__h617108, csrf_external_int_en_vec_0 } ; - assign r1__read__h617108 = { 54'b0, csrf_external_int_en_vec_1 } ; - assign r1__read__h617626 = { csrf_stvec_base_hi_reg, 1'b0 } ; - assign r1__read__h617631 = { r1__read__h617633, csrf_scounteren_tm_reg } ; - assign r1__read__h617633 = { 61'd0, csrf_scounteren_ir_reg } ; - assign r1__read__h617644 = { csrf_scause_interrupt_reg, 59'b0 } ; - assign r1__read__h617650 = - { r1__read__h617652, csrf_software_int_pend_vec_1 } ; - assign r1__read__h617652 = { r1__read__h617654, 2'b0 } ; - assign r1__read__h617654 = - { r1__read__h617656, csrf_timer_int_pend_vec_0 } ; - assign r1__read__h617656 = - { r1__read__h617658, csrf_timer_int_pend_vec_1 } ; - assign r1__read__h617658 = { r1__read__h617660, 2'b0 } ; - assign r1__read__h617660 = - { r1__read__h617662, csrf_external_int_pend_vec_0 } ; - assign r1__read__h617662 = { 54'b0, csrf_external_int_pend_vec_1 } ; - assign r1__read__h617880 = { vm_mode_reg__read__h617886, 16'd0 } ; - assign r1__read__h617903 = { r1__read__h617905, csrf_ie_vec_1 } ; - assign r1__read__h617905 = { r1__read__h617907, 1'b0 } ; - assign r1__read__h617907 = { r1__read__h617909, csrf_ie_vec_3 } ; - assign r1__read__h617909 = { r1__read__h617911, csrf_prev_ie_vec_0 } ; - assign r1__read__h617911 = { r1__read__h617913, csrf_prev_ie_vec_1 } ; - assign r1__read__h617913 = { r1__read__h617915, 1'b0 } ; - assign r1__read__h617915 = { r1__read__h617917, csrf_prev_ie_vec_3 } ; - assign r1__read__h617917 = { r1__read__h617919, csrf_spp_reg } ; - assign r1__read__h617919 = { r1__read__h617921, 2'b0 } ; - assign r1__read__h617921 = { r1__read__h617923, csrf_mpp_reg } ; - assign r1__read__h617923 = { r1__read__h617925, csrf_fs_reg } ; - assign r1__read__h617925 = { r1__read__h617927, 2'd0 } ; - assign r1__read__h617927 = { r1__read__h617929, csrf_mprv_reg } ; - assign r1__read__h617929 = { r1__read__h617931, csrf_sum_reg } ; - assign r1__read__h617931 = { r1__read__h617933, csrf_mxr_reg } ; - assign r1__read__h617933 = { r1__read__h617935, csrf_tvm_reg } ; - assign r1__read__h617935 = { r1__read__h617937, csrf_tw_reg } ; - assign r1__read__h617937 = { r1__read__h617939, csrf_tsr_reg } ; - assign r1__read__h617939 = { r1__read__h617941, 9'b0 } ; - assign r1__read__h617941 = { r1__read__h617943, 2'b10 } ; - assign r1__read__h617943 = { r1__read__h617945, 2'b10 } ; - assign r1__read__h617945 = { r__h616724, 27'b0 } ; - assign r1__read__h618028 = { r1__read__h618030, 1'b0 } ; - assign r1__read__h618030 = { r1__read__h618032, csrf_medeleg_13_11_reg } ; - assign r1__read__h618032 = { r1__read__h618034, 1'b0 } ; - assign r1__read__h618034 = { 48'b0, csrf_medeleg_15_reg } ; - assign r1__read__h618045 = { r1__read__h618047, 1'b0 } ; - assign r1__read__h618047 = { r1__read__h618049, csrf_mideleg_5_3_reg } ; - assign r1__read__h618049 = { r1__read__h618051, 1'b0 } ; - assign r1__read__h618051 = { r1__read__h618053, csrf_mideleg_9_7_reg } ; - assign r1__read__h618053 = { r1__read__h618055, 1'b0 } ; - assign r1__read__h618055 = { 52'b0, csrf_mideleg_11_reg } ; - assign r1__read__h618069 = - { r1__read__h618071, csrf_software_int_en_vec_1 } ; - assign r1__read__h618071 = { r1__read__h618073, 1'b0 } ; - assign r1__read__h618073 = - { r1__read__h618075, csrf_software_int_en_vec_3 } ; - assign r1__read__h618075 = { r1__read__h618077, csrf_timer_int_en_vec_0 } ; - assign r1__read__h618077 = { r1__read__h618079, csrf_timer_int_en_vec_1 } ; - assign r1__read__h618079 = { r1__read__h618081, 1'b0 } ; - assign r1__read__h618081 = { r1__read__h618083, csrf_timer_int_en_vec_3 } ; - assign r1__read__h618083 = - { r1__read__h618085, csrf_external_int_en_vec_0 } ; - assign r1__read__h618085 = - { r1__read__h618087, csrf_external_int_en_vec_1 } ; - assign r1__read__h618087 = { r1__read__h618089, 1'b0 } ; - assign r1__read__h618089 = { 52'd4, csrf_external_int_en_vec_3 } ; - assign r1__read__h618187 = { csrf_mtvec_base_hi_reg, 1'b0 } ; - assign r1__read__h618192 = { r1__read__h618194, csrf_mcounteren_tm_reg } ; - assign r1__read__h618194 = { 61'd0, csrf_mcounteren_ir_reg } ; - assign r1__read__h618205 = { csrf_mcause_interrupt_reg, 59'b0 } ; - assign r1__read__h618211 = - { r1__read__h618213, csrf_software_int_pend_vec_1 } ; - assign r1__read__h618213 = { r1__read__h618215, 1'b0 } ; - assign r1__read__h618215 = - { r1__read__h618217, csrf_software_int_pend_vec_3 } ; - assign r1__read__h618217 = - { r1__read__h618219, csrf_timer_int_pend_vec_0 } ; - assign r1__read__h618219 = - { r1__read__h618221, csrf_timer_int_pend_vec_1 } ; - assign r1__read__h618221 = { r1__read__h618223, 1'b0 } ; - assign r1__read__h618223 = - { r1__read__h618225, csrf_timer_int_pend_vec_3 } ; - assign r1__read__h618225 = - { r1__read__h618227, csrf_external_int_pend_vec_0 } ; - assign r1__read__h618227 = - { r1__read__h618229, csrf_external_int_pend_vec_1 } ; - assign r1__read__h618229 = { r1__read__h618231, 1'b0 } ; - assign r1__read__h618231 = - { r1__read__h618233, csrf_external_int_pend_vec_3 } ; - assign r1__read__h618233 = { r1__read__h618235, 2'b0 } ; - assign r1__read__h618235 = { 49'b0, csrf_debug_int_pend } ; - assign rVal1__h484562 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; - assign rVal2__h484563 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; - assign r___1__h478379 = + assign r1__read_BITS_13_TO_12___h658756 = csrf_fs_reg ; + assign r1__read_BIT_20___h659416 = csrf_tw_reg ; + assign r1__read__h616369 = { r1__read__h616371, csrf_ie_vec_1 } ; + assign r1__read__h616371 = { r1__read__h616373, 2'b0 } ; + assign r1__read__h616373 = { r1__read__h616375, csrf_prev_ie_vec_0 } ; + assign r1__read__h616375 = { r1__read__h616377, csrf_prev_ie_vec_1 } ; + assign r1__read__h616377 = { r1__read__h616379, 2'b0 } ; + assign r1__read__h616379 = { r1__read__h616381, csrf_spp_reg } ; + assign r1__read__h616381 = { r1__read__h616383, 4'b0 } ; + assign r1__read__h616383 = { r1__read__h616385, csrf_fs_reg } ; + assign r1__read__h616385 = { r1__read__h616387, 2'd0 } ; + assign r1__read__h616387 = { r1__read__h616389, 1'b0 } ; + assign r1__read__h616389 = { r1__read__h616391, csrf_sum_reg } ; + assign r1__read__h616391 = { r1__read__h616393, csrf_mxr_reg } ; + assign r1__read__h616393 = { r1__read__h616395, 12'b0 } ; + assign r1__read__h616395 = { r1__read__h616397, 2'b10 } ; + assign r1__read__h616397 = { r__h616401, 29'b0 } ; + assign r1__read__h616773 = + { r1__read__h616775, csrf_software_int_en_vec_1 } ; + assign r1__read__h616775 = { r1__read__h616777, 2'b0 } ; + assign r1__read__h616777 = { r1__read__h616779, csrf_timer_int_en_vec_0 } ; + assign r1__read__h616779 = { r1__read__h616781, csrf_timer_int_en_vec_1 } ; + assign r1__read__h616781 = { r1__read__h616783, 2'b0 } ; + assign r1__read__h616783 = + { r1__read__h616785, csrf_external_int_en_vec_0 } ; + assign r1__read__h616785 = { 54'b0, csrf_external_int_en_vec_1 } ; + assign r1__read__h617303 = { csrf_stvec_base_hi_reg, 1'b0 } ; + assign r1__read__h617308 = { r1__read__h617310, csrf_scounteren_tm_reg } ; + assign r1__read__h617310 = { 61'd0, csrf_scounteren_ir_reg } ; + assign r1__read__h617321 = { csrf_scause_interrupt_reg, 59'b0 } ; + assign r1__read__h617327 = + { r1__read__h617329, csrf_software_int_pend_vec_1 } ; + assign r1__read__h617329 = { r1__read__h617331, 2'b0 } ; + assign r1__read__h617331 = + { r1__read__h617333, csrf_timer_int_pend_vec_0 } ; + assign r1__read__h617333 = + { r1__read__h617335, csrf_timer_int_pend_vec_1 } ; + assign r1__read__h617335 = { r1__read__h617337, 2'b0 } ; + assign r1__read__h617337 = + { r1__read__h617339, csrf_external_int_pend_vec_0 } ; + assign r1__read__h617339 = { 54'b0, csrf_external_int_pend_vec_1 } ; + assign r1__read__h617557 = { vm_mode_reg__read__h617563, 16'd0 } ; + assign r1__read__h617580 = { r1__read__h617582, csrf_ie_vec_1 } ; + assign r1__read__h617582 = { r1__read__h617584, 1'b0 } ; + assign r1__read__h617584 = { r1__read__h617586, csrf_ie_vec_3 } ; + assign r1__read__h617586 = { r1__read__h617588, csrf_prev_ie_vec_0 } ; + assign r1__read__h617588 = { r1__read__h617590, csrf_prev_ie_vec_1 } ; + assign r1__read__h617590 = { r1__read__h617592, 1'b0 } ; + assign r1__read__h617592 = { r1__read__h617594, csrf_prev_ie_vec_3 } ; + assign r1__read__h617594 = { r1__read__h617596, csrf_spp_reg } ; + assign r1__read__h617596 = { r1__read__h617598, 2'b0 } ; + assign r1__read__h617598 = { r1__read__h617600, csrf_mpp_reg } ; + assign r1__read__h617600 = { r1__read__h617602, csrf_fs_reg } ; + assign r1__read__h617602 = { r1__read__h617604, 2'd0 } ; + assign r1__read__h617604 = { r1__read__h617606, csrf_mprv_reg } ; + assign r1__read__h617606 = { r1__read__h617608, csrf_sum_reg } ; + assign r1__read__h617608 = { r1__read__h617610, csrf_mxr_reg } ; + assign r1__read__h617610 = { r1__read__h617612, csrf_tvm_reg } ; + assign r1__read__h617612 = { r1__read__h617614, csrf_tw_reg } ; + assign r1__read__h617614 = { r1__read__h617616, csrf_tsr_reg } ; + assign r1__read__h617616 = { r1__read__h617618, 9'b0 } ; + assign r1__read__h617618 = { r1__read__h617620, 2'b10 } ; + assign r1__read__h617620 = { r1__read__h617622, 2'b10 } ; + assign r1__read__h617622 = { r__h616401, 27'b0 } ; + assign r1__read__h617705 = { r1__read__h617707, 1'b0 } ; + assign r1__read__h617707 = { r1__read__h617709, csrf_medeleg_13_11_reg } ; + assign r1__read__h617709 = { r1__read__h617711, 1'b0 } ; + assign r1__read__h617711 = { 48'b0, csrf_medeleg_15_reg } ; + assign r1__read__h617722 = { r1__read__h617724, 1'b0 } ; + assign r1__read__h617724 = { r1__read__h617726, csrf_mideleg_5_3_reg } ; + assign r1__read__h617726 = { r1__read__h617728, 1'b0 } ; + assign r1__read__h617728 = { r1__read__h617730, csrf_mideleg_9_7_reg } ; + assign r1__read__h617730 = { r1__read__h617732, 1'b0 } ; + assign r1__read__h617732 = { 52'b0, csrf_mideleg_11_reg } ; + assign r1__read__h617746 = + { r1__read__h617748, csrf_software_int_en_vec_1 } ; + assign r1__read__h617748 = { r1__read__h617750, 1'b0 } ; + assign r1__read__h617750 = + { r1__read__h617752, csrf_software_int_en_vec_3 } ; + assign r1__read__h617752 = { r1__read__h617754, csrf_timer_int_en_vec_0 } ; + assign r1__read__h617754 = { r1__read__h617756, csrf_timer_int_en_vec_1 } ; + assign r1__read__h617756 = { r1__read__h617758, 1'b0 } ; + assign r1__read__h617758 = { r1__read__h617760, csrf_timer_int_en_vec_3 } ; + assign r1__read__h617760 = + { r1__read__h617762, csrf_external_int_en_vec_0 } ; + assign r1__read__h617762 = + { r1__read__h617764, csrf_external_int_en_vec_1 } ; + assign r1__read__h617764 = { r1__read__h617766, 1'b0 } ; + assign r1__read__h617766 = { 52'b0, csrf_external_int_en_vec_3 } ; + assign r1__read__h617857 = { csrf_mtvec_base_hi_reg, 1'b0 } ; + assign r1__read__h617862 = { r1__read__h617864, csrf_mcounteren_tm_reg } ; + assign r1__read__h617864 = { 61'd0, csrf_mcounteren_ir_reg } ; + assign r1__read__h617875 = { csrf_mcause_interrupt_reg, 59'b0 } ; + assign r1__read__h617881 = + { r1__read__h617883, csrf_software_int_pend_vec_1 } ; + assign r1__read__h617883 = { r1__read__h617885, 1'b0 } ; + assign r1__read__h617885 = + { r1__read__h617887, csrf_software_int_pend_vec_3 } ; + assign r1__read__h617887 = + { r1__read__h617889, csrf_timer_int_pend_vec_0 } ; + assign r1__read__h617889 = + { r1__read__h617891, csrf_timer_int_pend_vec_1 } ; + assign r1__read__h617891 = { r1__read__h617893, 1'b0 } ; + assign r1__read__h617893 = + { r1__read__h617895, csrf_timer_int_pend_vec_3 } ; + assign r1__read__h617895 = + { r1__read__h617897, csrf_external_int_pend_vec_0 } ; + assign r1__read__h617897 = + { r1__read__h617899, csrf_external_int_pend_vec_1 } ; + assign r1__read__h617899 = { r1__read__h617901, 1'b0 } ; + assign r1__read__h617901 = { 52'b0, csrf_external_int_pend_vec_3 } ; + assign rVal1__h484253 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; + assign rVal2__h484254 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; + assign r___1__h478070 = 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[139:76] ; - assign r__h616724 = csrf_fs_reg == 2'b11 ; - assign regRenamingTable_RDY_rename_0_getRename__3469__ETC___d14106 = + assign r__h616401 = csrf_fs_reg == 2'b11 ; + assign regRenamingTable_RDY_rename_0_getRename__3465__ETC___d14102 = regRenamingTable$RDY_rename_0_getRename && - CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q240 && + CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q232 && (fetchStage$pipelines_0_first[199:195] == 5'd14 || coreFix_memExe_rsMem$RDY_enq) ; - assign regRenamingTable_RDY_rename_1_getRename__4169__ETC___d14187 = + assign regRenamingTable_RDY_rename_1_getRename__4165__ETC___d14183 = regRenamingTable$RDY_rename_1_getRename && (!fetchStage$pipelines_0_canDeq || - NOT_specTagManager_canClaim__3580_3666_OR_NOT__ETC___d14172) && - _0_OR_NOT_fetchStage_pipelines_1_first__2943_BI_ETC___d14185 ; - assign regRenamingTable_rename_0_canRename__3582_AND__ETC___d13604 = + NOT_specTagManager_canClaim__3576_3662_OR_NOT__ETC___d14168) && + _0_OR_NOT_fetchStage_pipelines_1_first__2940_BI_ETC___d14181 ; + assign regRenamingTable_rename_0_canRename__3578_AND__ETC___d13600 = regRenamingTable$rename_0_canRename && fetchStage$pipelines_0_first[199:195] != 5'd0 && fetchStage$pipelines_0_first[199:195] != 5'd21 && @@ -30909,8 +30756,8 @@ module mkCore(CLK, fetchStage$pipelines_0_first[199:195] != 5'd15 && fetchStage$pipelines_0_first[199:195] != 5'd19 && fetchStage$pipelines_0_first[199:195] != 5'd20 && - NOT_renameStage_rg_m_halt_req_2961_BIT_4_2962__ETC___d13602 ; - assign regRenamingTable_rename_0_canRename__3582_AND__ETC___d13653 = + NOT_renameStage_rg_m_halt_req_2958_BIT_4_2959__ETC___d13598 ; + assign regRenamingTable_rename_0_canRename__3578_AND__ETC___d13649 = regRenamingTable$rename_0_canRename && fetchStage$pipelines_0_first[199:195] != 5'd0 && fetchStage$pipelines_0_first[199:195] != 5'd21 && @@ -30921,105 +30768,105 @@ module mkCore(CLK, fetchStage$pipelines_0_first[199:195] != 5'd15 && fetchStage$pipelines_0_first[199:195] != 5'd19 && fetchStage$pipelines_0_first[199:195] != 5'd20 && - NOT_fetchStage_pipelines_0_first__2934_BIT_68__ETC___d13651 ; - assign regRenamingTable_rename_0_canRename__3582_AND__ETC___d13667 = - regRenamingTable_rename_0_canRename__3582_AND__ETC___d13653 && - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d13663 && + NOT_fetchStage_pipelines_0_first__2931_BIT_68__ETC___d13647 ; + assign regRenamingTable_rename_0_canRename__3578_AND__ETC___d13663 = + regRenamingTable_rename_0_canRename__3578_AND__ETC___d13649 && + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d13659 && fetchStage$pipelines_0_first[194:192] == 3'd1 || !specTagManager$canClaim ; - assign regRenamingTable_rename_0_canRename__3582_AND__ETC___d13988 = - regRenamingTable_rename_0_canRename__3582_AND__ETC___d13653 && + assign regRenamingTable_rename_0_canRename__3578_AND__ETC___d13984 = + regRenamingTable_rename_0_canRename__3578_AND__ETC___d13649 && fetchStage$pipelines_0_first[194:192] == 3'd2 && - IF_fetchStage_pipelines_0_first__2934_BITS_191_ETC___d13635 || + IF_fetchStage_pipelines_0_first__2931_BITS_191_ETC___d13631 || !coreFix_memExe_rsMem$canEnq || - CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q237 ; - assign regRenamingTable_rename_0_canRename__3582_AND__ETC___d14135 = + CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q229 ; + assign regRenamingTable_rename_0_canRename__3578_AND__ETC___d14131 = regRenamingTable$rename_0_canRename && - !checkForException___d13180[4] && + !checkForException___d13176[4] && rob$enqPort_0_canEnq && - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d14133 && + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d14129 && fetchStage$pipelines_0_first[194:192] == 3'd1 ; - assign regRenamingTable_rename_0_canRename__3582_AND__ETC___d14277 = + assign regRenamingTable_rename_0_canRename__3578_AND__ETC___d14273 = regRenamingTable$rename_0_canRename && - !checkForException___d13180[4] && + !checkForException___d13176[4] && rob$enqPort_0_canEnq && (fetchStage$pipelines_0_first[194:192] == 3'd3 || fetchStage$pipelines_0_first[194:192] == 3'd4) && coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq ; - assign regRenamingTable_rename_0_canRename__3582_AND__ETC___d14290 = + assign regRenamingTable_rename_0_canRename__3578_AND__ETC___d14286 = regRenamingTable$rename_0_canRename && - !checkForException___d13180[4] && + !checkForException___d13176[4] && rob$enqPort_0_canEnq && (fetchStage$pipelines_0_first[194:192] == 3'd3 || fetchStage$pipelines_0_first[194:192] == 3'd4) && coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq && - NOT_fetchStage_pipelines_0_first__2934_BITS_32_ETC___d14286 ; - assign regRenamingTable_rename_0_canRename__3582_AND__ETC___d14295 = + NOT_fetchStage_pipelines_0_first__2931_BITS_32_ETC___d14282 ; + assign regRenamingTable_rename_0_canRename__3578_AND__ETC___d14291 = regRenamingTable$rename_0_canRename && - !checkForException___d13180[4] && + !checkForException___d13176[4] && rob$enqPort_0_canEnq && (fetchStage$pipelines_0_first[194:192] == 3'd3 || fetchStage$pipelines_0_first[194:192] == 3'd4) && coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq && fetchStage$pipelines_0_first[173] ; - assign regRenamingTable_rename_0_canRename__3582_AND__ETC___d14300 = + assign regRenamingTable_rename_0_canRename__3578_AND__ETC___d14296 = regRenamingTable$rename_0_canRename && - !checkForException___d13180[4] && + !checkForException___d13176[4] && rob$enqPort_0_canEnq && fetchStage$pipelines_0_first[194:192] == 3'd2 && coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2934_BITS_191_ETC___d13635 && + IF_fetchStage_pipelines_0_first__2931_BITS_191_ETC___d13631 && fetchStage$pipelines_0_first[199:195] != 5'd14 ; - assign regRenamingTable_rename_0_canRename__3582_AND__ETC___d14320 = + assign regRenamingTable_rename_0_canRename__3578_AND__ETC___d14316 = regRenamingTable$rename_0_canRename && - !checkForException___d13180[4] && + !checkForException___d13176[4] && rob$enqPort_0_canEnq && fetchStage$pipelines_0_first[194:192] == 3'd2 && coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2934_BITS_191_ETC___d13635 && - NOT_fetchStage_pipelines_0_first__2934_BITS_32_ETC___d14286 ; - assign regRenamingTable_rename_0_canRename__3582_AND__ETC___d14324 = + IF_fetchStage_pipelines_0_first__2931_BITS_191_ETC___d13631 && + NOT_fetchStage_pipelines_0_first__2931_BITS_32_ETC___d14282 ; + assign regRenamingTable_rename_0_canRename__3578_AND__ETC___d14320 = regRenamingTable$rename_0_canRename && - !checkForException___d13180[4] && + !checkForException___d13176[4] && rob$enqPort_0_canEnq && fetchStage$pipelines_0_first[194:192] == 3'd2 && coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2934_BITS_191_ETC___d13635 && + IF_fetchStage_pipelines_0_first__2931_BITS_191_ETC___d13631 && fetchStage$pipelines_0_first[173] ; - assign regRenamingTable_rename_0_canRename__3582_AND__ETC___d14330 = + assign regRenamingTable_rename_0_canRename__3578_AND__ETC___d14326 = regRenamingTable$rename_0_canRename && - !checkForException___d13180[4] && + !checkForException___d13176[4] && rob$enqPort_0_canEnq && fetchStage$pipelines_0_first[194:192] == 3'd2 && coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2934_BITS_191_ETC___d13635 && + IF_fetchStage_pipelines_0_first__2931_BITS_191_ETC___d13631 && (fetchStage$pipelines_0_first[199:195] != 5'd14) != fetchStage$pipelines_0_first[160] ; - assign regRenamingTable_rename_0_canRename__3582_AND__ETC___d14334 = + assign regRenamingTable_rename_0_canRename__3578_AND__ETC___d14330 = regRenamingTable$rename_0_canRename && - !checkForException___d13180[4] && + !checkForException___d13176[4] && rob$enqPort_0_canEnq && fetchStage$pipelines_0_first[194:192] == 3'd2 && coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2934_BITS_191_ETC___d13635 && + IF_fetchStage_pipelines_0_first__2931_BITS_191_ETC___d13631 && (fetchStage$pipelines_0_first[191:189] == 3'd0 || fetchStage$pipelines_0_first[191:189] == 3'd2) ; - assign regRenamingTable_rename_0_canRename__3582_AND__ETC___d14342 = + assign regRenamingTable_rename_0_canRename__3578_AND__ETC___d14338 = regRenamingTable$rename_0_canRename && - !checkForException___d13180[4] && + !checkForException___d13176[4] && rob$enqPort_0_canEnq && fetchStage$pipelines_0_first[194:192] == 3'd2 && coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2934_BITS_191_ETC___d13635 && + IF_fetchStage_pipelines_0_first__2931_BITS_191_ETC___d13631 && fetchStage$pipelines_0_first[191:189] != 3'd0 && fetchStage$pipelines_0_first[191:189] != 3'd2 ; - assign regRenamingTable_rename_0_canRename__3582_AND__ETC___d14519 = + assign regRenamingTable_rename_0_canRename__3578_AND__ETC___d14515 = regRenamingTable$rename_0_canRename && - !checkForException___d13180[4] && + !checkForException___d13176[4] && rob$enqPort_0_canEnq && fetchStage$pipelines_0_first[194:192] == 3'd2 && - IF_fetchStage_pipelines_0_first__2934_BITS_191_ETC___d13635 ; - assign regRenamingTable_rename_1_canRename__3704_AND__ETC___d13903 = + IF_fetchStage_pipelines_0_first__2931_BITS_191_ETC___d13631 ; + assign regRenamingTable_rename_1_canRename__3700_AND__ETC___d13899 = regRenamingTable$rename_1_canRename && fetchStage$pipelines_1_first[199:195] != 5'd0 && fetchStage$pipelines_1_first[199:195] != 5'd21 && @@ -31030,8 +30877,8 @@ module mkCore(CLK, fetchStage$pipelines_1_first[199:195] != 5'd15 && fetchStage$pipelines_1_first[199:195] != 5'd19 && fetchStage$pipelines_1_first[199:195] != 5'd20 && - NOT_renameStage_rg_m_halt_req_2961_BIT_4_2962__ETC___d13901 ; - assign regRenamingTable_rename_1_canRename__3704_AND__ETC___d14045 = + NOT_renameStage_rg_m_halt_req_2958_BIT_4_2959__ETC___d13897 ; + assign regRenamingTable_rename_1_canRename__3700_AND__ETC___d14041 = regRenamingTable$rename_1_canRename && fetchStage$pipelines_1_first[199:195] != 5'd0 && fetchStage$pipelines_1_first[199:195] != 5'd21 && @@ -31042,8 +30889,8 @@ module mkCore(CLK, fetchStage$pipelines_1_first[199:195] != 5'd15 && fetchStage$pipelines_1_first[199:195] != 5'd19 && fetchStage$pipelines_1_first[199:195] != 5'd20 && - NOT_renameStage_rg_m_halt_req_2961_BIT_4_2962__ETC___d14043 ; - assign regRenamingTable_rename_1_canRename__3704_AND__ETC___d14063 = + NOT_renameStage_rg_m_halt_req_2958_BIT_4_2959__ETC___d14039 ; + assign regRenamingTable_rename_1_canRename__3700_AND__ETC___d14059 = regRenamingTable$rename_1_canRename && fetchStage$pipelines_1_first[199:195] != 5'd0 && fetchStage$pipelines_1_first[199:195] != 5'd21 && @@ -31054,8 +30901,8 @@ module mkCore(CLK, fetchStage$pipelines_1_first[199:195] != 5'd15 && fetchStage$pipelines_1_first[199:195] != 5'd19 && fetchStage$pipelines_1_first[199:195] != 5'd20 && - NOT_renameStage_rg_m_halt_req_2961_BIT_4_2962__ETC___d14061 ; - assign regRenamingTable_rename_1_canRename__3704_AND__ETC___d14398 = + NOT_renameStage_rg_m_halt_req_2958_BIT_4_2959__ETC___d14057 ; + assign regRenamingTable_rename_1_canRename__3700_AND__ETC___d14394 = regRenamingTable$rename_1_canRename && fetchStage$pipelines_1_first[199:195] != 5'd0 && fetchStage$pipelines_1_first[199:195] != 5'd21 && @@ -31066,75 +30913,75 @@ module mkCore(CLK, fetchStage$pipelines_1_first[199:195] != 5'd15 && fetchStage$pipelines_1_first[199:195] != 5'd19 && fetchStage$pipelines_1_first[199:195] != 5'd20 && - NOT_fetchStage_pipelines_1_first__2943_BIT_68__ETC___d14396 ; - assign renameStage_rg_m_halt_req_2961_BIT_4_2962_OR_N_ETC___d13238 = + NOT_fetchStage_pipelines_1_first__2940_BIT_68__ETC___d14392 ; + assign renameStage_rg_m_halt_req_2958_BIT_4_2959_OR_N_ETC___d13234 = renameStage_rg_m_halt_req[4] || !fetchStage$pipelines_0_first[68] && - (IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[0] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[1] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[2] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[3] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[4] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[5] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[6] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[7] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[8] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[9] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[10] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[11] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[12] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[13] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[14] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[15]) ; - assign renameStage_rg_m_halt_req_2961_BIT_4_2962_OR_N_ETC___d13467 = - renameStage_rg_m_halt_req_2961_BIT_4_2962_OR_N_ETC___d13238 || + (IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[0] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[1] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[2] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[3] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[4] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[5] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[6] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[7] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[8] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[9] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[10] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[11] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[12] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[13] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[14] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[15]) ; + assign renameStage_rg_m_halt_req_2958_BIT_4_2959_OR_N_ETC___d13463 = + renameStage_rg_m_halt_req_2958_BIT_4_2959_OR_N_ETC___d13234 || (fetchStage$pipelines_0_first[68] ? - IF_fetchStage_pipelines_0_first__2934_BIT_68_2_ETC___d13300 : - IF_checkForException_3180_BIT_4_3181_THEN_IF_c_ETC___d13329) == + IF_fetchStage_pipelines_0_first__2931_BIT_68_2_ETC___d13296 : + IF_checkForException_3176_BIT_4_3177_THEN_IF_c_ETC___d13325) == 4'd3 ; - assign renameStage_rg_m_halt_req_2961_BIT_4_2962_OR_f_ETC___d13924 = + assign renameStage_rg_m_halt_req_2958_BIT_4_2959_OR_f_ETC___d13920 = renameStage_rg_m_halt_req[4] || fetchStage$pipelines_0_first[68] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13921 || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13917 || !rob$enqPort_0_canEnq || !epochManager$checkEpoch_0_check ; - assign renameStage_rg_m_halt_req_2961_BIT_4_2962_OR_f_ETC___d13964 = + assign renameStage_rg_m_halt_req_2958_BIT_4_2959_OR_f_ETC___d13960 = renameStage_rg_m_halt_req[4] || fetchStage$pipelines_1_first[68] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13958 || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13954 || !rob$enqPort_1_canEnq || !epochManager$checkEpoch_1_check || - csrf_rg_dcsr_read__1902_BIT_2_3232_OR_NOT_fetc_ETC___d13672 ; - assign renameStage_rg_m_halt_req_2961_BIT_4_2962_OR_f_ETC___d14005 = + csrf_rg_dcsr_read__1899_BIT_2_3228_OR_NOT_fetc_ETC___d13668 ; + assign renameStage_rg_m_halt_req_2958_BIT_4_2959_OR_f_ETC___d14001 = renameStage_rg_m_halt_req[4] || fetchStage$pipelines_0_first[68] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[0] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[1] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[2] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[3] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[4] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[5] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[6] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[7] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[8] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[9] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[10] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[11] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[12] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[13] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[14] || - IF_IF_NOT_csrf_prv_reg_read__2964_EQ_3_2965_29_ETC___d13005[15] ; - assign renameStage_rg_m_halt_req_2961_BIT_4_2962_OR_f_ETC___d14085 = + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[0] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[1] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[2] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[3] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[4] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[5] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[6] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[7] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[8] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[9] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[10] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[11] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[12] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[13] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[14] || + IF_IF_NOT_csrf_prv_reg_read__2961_EQ_3_2962_29_ETC___d13001[15] ; + assign renameStage_rg_m_halt_req_2958_BIT_4_2959_OR_f_ETC___d14081 = renameStage_rg_m_halt_req[4] || fetchStage$pipelines_0_first[68] || - checkForException___d13180[4] || + checkForException___d13176[4] || !rob$enqPort_0_canEnq ; - assign renaming_spec_bits__h686832 = + assign renaming_spec_bits__h686496 = fetchStage$pipelines_0_canDeq ? - y_avValue_fst__h683295 : + y_avValue_snd_fst__h683178 : specTagManager$currentSpecBits ; - assign res_data__h340167 = { 32'hFFFFFFFF, x__h340182 } ; - assign res_data__h340172 = + assign res_data__h339858 = { 32'hFFFFFFFF, x__h339873 } ; + assign res_data__h339863 = { (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == @@ -31147,8 +30994,8 @@ module mkCore(CLK, 52'd0) ? 63'h7FF8000000000000 : coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:5] } ; - assign res_data__h385869 = { 32'hFFFFFFFF, x__h385884 } ; - assign res_data__h385874 = + assign res_data__h385560 = { 32'hFFFFFFFF, x__h385575 } ; + assign res_data__h385565 = { (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == @@ -31161,8 +31008,8 @@ module mkCore(CLK, 52'd0) ? 63'h7FF8000000000000 : coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:5] } ; - assign res_data__h431564 = { 32'hFFFFFFFF, x__h431579 } ; - assign res_data__h431569 = + assign res_data__h431255 = { 32'hFFFFFFFF, x__h431270 } ; + assign res_data__h431260 = { (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == @@ -31175,7 +31022,7 @@ module mkCore(CLK, 52'd0) ? 63'h7FF8000000000000 : coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:5] } ; - assign res_fflags__h340168 = + assign res_fflags__h339859 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[38:34] | coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[4:0] | { (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != @@ -31186,8 +31033,7 @@ module mkCore(CLK, 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] != 52'd0) && - (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != - 11'd0 || + (value_BIT_52___h357451 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5298, @@ -31199,8 +31045,7 @@ module mkCore(CLK, 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] != 52'd0) && - (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != - 11'd0 || + (value_BIT_52___h357451 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5309, @@ -31212,8 +31057,7 @@ module mkCore(CLK, 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] != 52'd0) && - (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != - 11'd0 || + (value_BIT_52___h357451 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5325, @@ -31225,8 +31069,7 @@ module mkCore(CLK, 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] != 52'd0) && - (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != - 11'd0 || + (value_BIT_52___h357451 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5338, @@ -31238,12 +31081,11 @@ module mkCore(CLK, 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] != 52'd0) && - (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != - 11'd0 || + (value_BIT_52___h357451 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5351 } ; - assign res_fflags__h385870 = + assign res_fflags__h385561 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[38:34] | coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[4:0] | { (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != @@ -31311,7 +31153,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6743 } ; - assign res_fflags__h431565 = + assign res_fflags__h431256 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[38:34] | coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[4:0] | { (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != @@ -31322,8 +31164,7 @@ module mkCore(CLK, 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && - (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != - 11'd0 || + (value_BIT_52___h448843 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8082, @@ -31335,8 +31176,7 @@ module mkCore(CLK, 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && - (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != - 11'd0 || + (value_BIT_52___h448843 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8093, @@ -31348,8 +31188,7 @@ module mkCore(CLK, 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && - (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != - 11'd0 || + (value_BIT_52___h448843 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8109, @@ -31361,8 +31200,7 @@ module mkCore(CLK, 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && - (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != - 11'd0 || + (value_BIT_52___h448843 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8122, @@ -31374,54 +31212,46 @@ module mkCore(CLK, 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && - (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != - 11'd0 || + (value_BIT_52___h448843 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8135 } ; - assign resp_addr__h294277 = + assign resp_addr__h293969 = { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot[52:1], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getRq[95:84] } ; - assign result__h366635 = + assign result__h366326 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4654[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4654[0] | - guard__h366630 } ; - assign result__h412332 = + guard__h366321 } ; + assign result__h412023 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d6046[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d6046[0] | - guard__h412327 } ; - assign result__h458027 = + guard__h412018 } ; + assign result__h457718 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7438[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7438[0] | - guard__h458022 } ; - assign result__h506288 = + guard__h457713 } ; + assign result__h505979 = { _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d8764[56:1], _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d8764[0] | - guard__h506283 } ; - assign result__h545141 = + guard__h505974 } ; + assign result__h544832 = { _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d10249[56:1], _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d10249[0] | - guard__h545136 } ; - assign result__h584445 = + guard__h544827 } ; + assign result__h584136 = { _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d9479[56:1], _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d9479[0] | - guard__h584440 } ; - assign result__h650621 = w__h650616 & y__h650650 ; - assign result__h650672 = ~x__h650671 ; - assign rg_core_run_state_read__3228_EQ_2_3229_AND_NOT_ETC___d15576 = + guard__h584131 } ; + assign result__h650285 = w__h650280 & y__h650314 ; + assign result__h650336 = ~x__h650335 ; + assign rg_core_run_state_read__3224_EQ_2_3225_AND_NOT_ETC___d15421 = rg_core_run_state == 2'd2 && !flush_reservation && !flush_tlbs && !update_vm_info && fetchStage$iTlbIfc_flush_done && coreFix_memExe_dTlb$flush_done && !flush_caches ; - assign rob_RDY_deqPort_0_deq_data__4544_AND_rob_RDY_d_ETC___d15004 = - rob$RDY_deqPort_0_deq_data && rob$RDY_deqPort_0_deq && - regRenamingTable$RDY_commit_0_commit && - v_f_to_TV_0$FULL_N && - fetchStage$iTlbIfc_noPendingReq && - coreFix_memExe_dTlb$noPendingReq && - NOT_rob_deqPort_0_deq_data__4547_BITS_186_TO_1_ETC___d14999 ; - assign rob_RDY_enqPort_0_enq__2956_AND_regRenamingTab_ETC___d13477 = + assign rob_RDY_enqPort_0_enq__2953_AND_regRenamingTab_ETC___d13473 = rob$RDY_enqPort_0_enq && regRenamingTable$RDY_rename_0_claimRename && regRenamingTable$RDY_rename_0_getRename && @@ -31429,489 +31259,487 @@ module mkCore(CLK, fetchStage$RDY_pipelines_0_deq && (fetchStage$pipelines_0_first[194:192] != 3'd0 || coreFix_aluExe_0_rsAlu$RDY_enq) ; - assign rob_deqPort_0_deq_data__4547_BITS_282_TO_219_4_ETC___d15180 = + assign rob_deqPort_0_deq_data__4542_BITS_282_TO_219_4_ETC___d15122 = rob$deqPort_0_deq_data[282:219] + 64'd4 ; - assign rob_deqPort_0_deq_data__4547_BIT_166_4563_CONC_ETC___d14612 = - { rob$deqPort_0_deq_data[166], - rob$deqPort_0_deq_data[166] ? - CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q251 : - CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q252 } ; - assign robdeqPort_0_deq_data_BITS_95_TO_32__q271 = + assign robdeqPort_0_deq_data_BITS_95_TO_32__q263 = rob$deqPort_0_deq_data[95:32] ; - assign rs1__h659223 = + assign rs1__h658887 = (fetchStage$pipelines_0_first[88] && !fetchStage$pipelines_0_first[87]) ? fetchStage$pipelines_0_first[86:82] : 5'd0 ; - assign satp_csr__read__h614234 = { r1__read__h617880, csrf_ppn_reg } ; - assign sbIdx__h158461 = + assign satp_csr__read__h613925 = { r1__read__h617557, csrf_ppn_reg } ; + assign sbIdx__h158152 = coreFix_memExe_reqStQ_data_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_coreFix_memExe_doIssueSB ? coreFix_memExe_reqStQ_data_0_lat_0$wget[65:64] : coreFix_memExe_reqStQ_data_0_rl[65:64]) : 2'd0 ; - assign scause_csr__read__h614032 = - { r1__read__h617644, csrf_scause_code_reg } ; - assign scounteren_csr__read__h613894 = - { r1__read__h617631, csrf_scounteren_cy_reg } ; - assign sfd__h340778 = { value__h349005, 3'd0 } ; - assign sfd__h356586 = + assign scause_csr__read__h613723 = + { r1__read__h617321, csrf_scause_code_reg } ; + assign scounteren_csr__read__h613585 = + { r1__read__h617308, csrf_scounteren_cy_reg } ; + assign sfd__h340469 = { value__h348696, 3'd0 } ; + assign sfd__h356277 = { 1'b0, - _theResult___fst_exp__h356494 != 8'd0, - sfdin__h356488[56:34] } + + _theResult___fst_exp__h356185 != 8'd0, + sfdin__h356179[56:34] } + 25'd1 ; - assign sfd__h365168 = + assign sfd__h364859 = { 1'b0, - _theResult___fst_exp__h365150 != 8'd0, - _theResult___snd__h365101[56:34] } + + _theResult___fst_exp__h364841 != 8'd0, + _theResult___snd__h364792[56:34] } + 25'd1 ; - assign sfd__h374352 = + assign sfd__h374043 = { 1'b0, - _theResult___fst_exp__h374260 != 8'd0, - sfdin__h374254[56:34] } + + _theResult___fst_exp__h373951 != 8'd0, + sfdin__h373945[56:34] } + 25'd1 ; - assign sfd__h382964 = + assign sfd__h382655 = { 1'b0, - _theResult___fst_exp__h382945 != 8'd0, - _theResult___snd__h382891[56:34] } + + _theResult___fst_exp__h382636 != 8'd0, + _theResult___snd__h382582[56:34] } + 25'd1 ; - assign sfd__h386480 = { value__h394702, 3'd0 } ; - assign sfd__h402283 = + assign sfd__h386171 = { value__h394393, 3'd0 } ; + assign sfd__h401974 = { 1'b0, - _theResult___fst_exp__h402191 != 8'd0, - sfdin__h402185[56:34] } + + _theResult___fst_exp__h401882 != 8'd0, + sfdin__h401876[56:34] } + 25'd1 ; - assign sfd__h410865 = + assign sfd__h410556 = { 1'b0, - _theResult___fst_exp__h410847 != 8'd0, - _theResult___snd__h410798[56:34] } + + _theResult___fst_exp__h410538 != 8'd0, + _theResult___snd__h410489[56:34] } + 25'd1 ; - assign sfd__h420049 = + assign sfd__h419740 = { 1'b0, - _theResult___fst_exp__h419957 != 8'd0, - sfdin__h419951[56:34] } + + _theResult___fst_exp__h419648 != 8'd0, + sfdin__h419642[56:34] } + 25'd1 ; - assign sfd__h428661 = + assign sfd__h428352 = { 1'b0, - _theResult___fst_exp__h428642 != 8'd0, - _theResult___snd__h428588[56:34] } + + _theResult___fst_exp__h428333 != 8'd0, + _theResult___snd__h428279[56:34] } + 25'd1 ; - assign sfd__h432175 = { value__h440397, 3'd0 } ; - assign sfd__h447978 = + assign sfd__h431866 = { value__h440088, 3'd0 } ; + assign sfd__h447669 = { 1'b0, - _theResult___fst_exp__h447886 != 8'd0, - sfdin__h447880[56:34] } + + _theResult___fst_exp__h447577 != 8'd0, + sfdin__h447571[56:34] } + 25'd1 ; - assign sfd__h456560 = + assign sfd__h456251 = { 1'b0, - _theResult___fst_exp__h456542 != 8'd0, - _theResult___snd__h456493[56:34] } + + _theResult___fst_exp__h456233 != 8'd0, + _theResult___snd__h456184[56:34] } + 25'd1 ; - assign sfd__h465744 = + assign sfd__h465435 = { 1'b0, - _theResult___fst_exp__h465652 != 8'd0, - sfdin__h465646[56:34] } + + _theResult___fst_exp__h465343 != 8'd0, + sfdin__h465337[56:34] } + 25'd1 ; - assign sfd__h474356 = + assign sfd__h474047 = { 1'b0, - _theResult___fst_exp__h474337 != 8'd0, - _theResult___snd__h474283[56:34] } + + _theResult___fst_exp__h474028 != 8'd0, + _theResult___snd__h473974[56:34] } + 25'd1 ; - assign sfd__h485308 = { value__h489891, 32'd0 } ; - assign sfd__h504352 = + assign sfd__h484999 = { value__h489582, 32'd0 } ; + assign sfd__h504043 = { 1'b0, - _theResult___fst_exp__h504334 != 11'd0, - _theResult___snd__h504285[56:5] } + + _theResult___fst_exp__h504025 != 11'd0, + _theResult___snd__h503976[56:5] } + 54'd1 ; - assign sfd__h514003 = + assign sfd__h513694 = { 1'b0, - _theResult___fst_exp__h513911 != 11'd0, - sfdin__h513905[56:5] } + + _theResult___fst_exp__h513602 != 11'd0, + sfdin__h513596[56:5] } + 54'd1 ; - assign sfd__h522763 = + assign sfd__h522454 = { 1'b0, - _theResult___fst_exp__h522744 != 11'd0, - _theResult___snd__h522690[56:5] } + + _theResult___fst_exp__h522435 != 11'd0, + _theResult___snd__h522381[56:5] } + 54'd1 ; - assign sfd__h524302 = { value__h528744, 32'd0 } ; - assign sfd__h543205 = + assign sfd__h523993 = { value__h528435, 32'd0 } ; + assign sfd__h542896 = { 1'b0, - _theResult___fst_exp__h543187 != 11'd0, - _theResult___snd__h543138[56:5] } + + _theResult___fst_exp__h542878 != 11'd0, + _theResult___snd__h542829[56:5] } + 54'd1 ; - assign sfd__h552856 = + assign sfd__h552547 = { 1'b0, - _theResult___fst_exp__h552764 != 11'd0, - sfdin__h552758[56:5] } + + _theResult___fst_exp__h552455 != 11'd0, + sfdin__h552449[56:5] } + 54'd1 ; - assign sfd__h561616 = + assign sfd__h561307 = { 1'b0, - _theResult___fst_exp__h561597 != 11'd0, - _theResult___snd__h561543[56:5] } + + _theResult___fst_exp__h561288 != 11'd0, + _theResult___snd__h561234[56:5] } + 54'd1 ; - assign sfd__h563606 = { value__h568048, 32'd0 } ; - assign sfd__h582509 = + assign sfd__h563297 = { value__h567739, 32'd0 } ; + assign sfd__h582200 = { 1'b0, - _theResult___fst_exp__h582491 != 11'd0, - _theResult___snd__h582442[56:5] } + + _theResult___fst_exp__h582182 != 11'd0, + _theResult___snd__h582133[56:5] } + 54'd1 ; - assign sfd__h592160 = + assign sfd__h591851 = { 1'b0, - _theResult___fst_exp__h592068 != 11'd0, - sfdin__h592062[56:5] } + + _theResult___fst_exp__h591759 != 11'd0, + sfdin__h591753[56:5] } + 54'd1 ; - assign sfd__h600920 = + assign sfd__h600611 = { 1'b0, - _theResult___fst_exp__h600901 != 11'd0, - _theResult___snd__h600847[56:5] } + + _theResult___fst_exp__h600592 != 11'd0, + _theResult___snd__h600538[56:5] } + 54'd1 ; - assign sfdin__h356488 = - _theResult____h348383[56] ? - _theResult___snd__h356505 : - _theResult___snd__h356516 ; - assign sfdin__h374254 = - _theResult____h366022[56] ? - _theResult___snd__h374271 : - _theResult___snd__h374282 ; - assign sfdin__h402185 = - _theResult____h394082[56] ? - _theResult___snd__h402202 : - _theResult___snd__h402213 ; - assign sfdin__h419951 = - _theResult____h411719[56] ? - _theResult___snd__h419968 : - _theResult___snd__h419979 ; - assign sfdin__h447880 = - _theResult____h439777[56] ? - _theResult___snd__h447897 : - _theResult___snd__h447908 ; - assign sfdin__h465646 = - _theResult____h457414[56] ? - _theResult___snd__h465663 : - _theResult___snd__h465674 ; - assign sfdin__h513905 = - _theResult____h505675[56] ? - _theResult___snd__h513922 : - _theResult___snd__h513933 ; - assign sfdin__h552758 = - _theResult____h544528[56] ? - _theResult___snd__h552775 : - _theResult___snd__h552786 ; - assign sfdin__h592062 = - _theResult____h583832[56] ? - _theResult___snd__h592079 : - _theResult___snd__h592090 ; - assign shiftData__h184066 = - coreFix_memExe_regToExeQ$first[75:12] << x__h184195 ; - assign sie_csr__read__h613798 = - { r1__read__h617096, csrf_software_int_en_vec_0 } ; - assign sip_csr__read__h614171 = - { r1__read__h617650, csrf_software_int_pend_vec_0 } ; - assign spec_bits__h689959 = specTagManager$currentSpecBits | y__h689972 ; - assign sstatus_csr__read__h613729 = { r1__read__h616692, csrf_ie_vec_0 } ; - assign stvec_csr__read__h613841 = - { r1__read__h617626, csrf_stvec_mode_low_reg } ; - assign upd__h4024 = + assign sfdin__h356179 = + _theResult____h348074[56] ? + _theResult___snd__h356196 : + _theResult___snd__h356207 ; + assign sfdin__h373945 = + _theResult____h365713[56] ? + _theResult___snd__h373962 : + _theResult___snd__h373973 ; + assign sfdin__h401876 = + _theResult____h393773[56] ? + _theResult___snd__h401893 : + _theResult___snd__h401904 ; + assign sfdin__h419642 = + _theResult____h411410[56] ? + _theResult___snd__h419659 : + _theResult___snd__h419670 ; + assign sfdin__h447571 = + _theResult____h439468[56] ? + _theResult___snd__h447588 : + _theResult___snd__h447599 ; + assign sfdin__h465337 = + _theResult____h457105[56] ? + _theResult___snd__h465354 : + _theResult___snd__h465365 ; + assign sfdin__h513596 = + _theResult____h505366[56] ? + _theResult___snd__h513613 : + _theResult___snd__h513624 ; + assign sfdin__h552449 = + _theResult____h544219[56] ? + _theResult___snd__h552466 : + _theResult___snd__h552477 ; + assign sfdin__h591753 = + _theResult____h583523[56] ? + _theResult___snd__h591770 : + _theResult___snd__h591781 ; + assign shiftData__h183758 = + coreFix_memExe_regToExeQ$first[75:12] << x__h183887 ; + assign sie_csr__read__h613489 = + { r1__read__h616773, csrf_software_int_en_vec_0 } ; + assign sip_csr__read__h613862 = + { r1__read__h617327, csrf_software_int_pend_vec_0 } ; + assign spec_bits__h689623 = specTagManager$currentSpecBits | y__h689636 ; + assign sstatus_csr__read__h613420 = { r1__read__h616369, csrf_ie_vec_0 } ; + assign stvec_csr__read__h613532 = + { r1__read__h617303, csrf_stvec_mode_low_reg } ; + assign upd__h3717 = WILL_FIRE_RL_commitStage_doCommitSystemInst ? MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1 : MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2 ; - assign upd__h5341 = n__read__h6636 + 64'd1 ; - assign upd__h6750 = + assign upd__h5034 = n__read__h6329 + 64'd1 ; + assign upd__h6443 = MUX_csrf_mcycle_ehr_data_dummy2_0$write_1__SEL_1 ? f_csr_reqs$D_OUT[63:0] : rob$deqPort_0_deq_data[95:32] ; - assign upd__h719366 = + assign upd__h717235 = MUX_csrf_minstret_ehr_data_dummy2_0$write_1__SEL_1 ? f_csr_reqs$D_OUT[63:0] : rob$deqPort_0_deq_data[95:32] ; - assign v__h298241 = + assign v__h297933 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3127) ? - v__h298472 : + v__h298164 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ; - assign v__h298472 = + assign v__h298164 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd7) ? 3'd0 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP + 3'd1 ; - assign v__h301586 = + assign v__h301278 = (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3234) ? - v__h302104 : + v__h301796 : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP ; - assign v__h302104 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP + 1'd1 ; - assign v__h312100 = + assign v__h301796 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP + 1'd1 ; + assign v__h311792 = (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3405) ? - v__h312331 : + v__h312023 : coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP ; - assign v__h312331 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP + 1'd1 ; - assign v__h315976 = + assign v__h312023 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP + 1'd1 ; + assign v__h315668 = (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3501) ? - v__h316207 : + v__h315899 : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP ; - assign v__h316207 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP + 1'd1 ; - assign v__h330577 = + assign v__h315899 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP + 1'd1 ; + assign v__h330269 = (coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3730) ? - v__h330808 : + v__h330500 : coreFix_memExe_memRespLdQ_enqP ; - assign v__h330808 = coreFix_memExe_memRespLdQ_enqP + 1'd1 ; - assign v__h333802 = + assign v__h330500 = coreFix_memExe_memRespLdQ_enqP + 1'd1 ; + assign v__h333494 = (coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d3824) ? - v__h334033 : + v__h333725 : coreFix_memExe_forwardQ_enqP ; - assign v__h334033 = coreFix_memExe_forwardQ_enqP + 1'd1 ; - assign v__h607011 = + assign v__h333725 = coreFix_memExe_forwardQ_enqP + 1'd1 ; + assign v__h606702 = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_deqEn$whas ? - v__h607021 : + v__h606712 : coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit ; - assign v__h607021 = + assign v__h606712 = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit + 2'd1 ; - assign v__h608052 = v__h607011 - 2'd1 ; - assign v__h612041 = - sbCons$lazyLookup_1_get[3] ? rf$read_1_rd1 : y_avValue__h613174 ; - assign v__h636859 = - sbCons$lazyLookup_0_get[3] ? rf$read_0_rd1 : y_avValue__h637840 ; - assign vaddr__h184061 = + assign v__h607743 = v__h606702 - 2'd1 ; + assign v__h611732 = + sbCons$lazyLookup_1_get[3] ? rf$read_1_rd1 : y_avValue__h612865 ; + assign v__h636524 = + sbCons$lazyLookup_0_get[3] ? rf$read_0_rd1 : y_avValue__h637505 ; + assign vaddr__h183753 = coreFix_memExe_regToExeQ$first[139:76] + - { {32{coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q13[31]}}, - coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q13 } ; - assign value__h349005 = + { {32{coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q5[31]}}, + coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q5 } ; + assign value_BIT_52___h357451 = + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != + 11'd0 ; + assign value_BIT_52___h448843 = + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != + 11'd0 ; + assign value__h348696 = { 1'b0, - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != - 11'd0, + value_BIT_52___h357451, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] } ; - assign value__h394702 = + assign value__h394393 = { 1'b0, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != 11'd0, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] } ; - assign value__h440397 = + assign value__h440088 = { 1'b0, - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != - 11'd0, + value_BIT_52___h448843, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] } ; - assign value__h489891 = { 1'b0, f1_exp__h484946 != 8'd0, f1_sfd__h484947 } ; - assign value__h528744 = { 1'b0, f2_exp__h523940 != 8'd0, f2_sfd__h523941 } ; - assign value__h568048 = { 1'b0, f3_exp__h563244 != 8'd0, f3_sfd__h563245 } ; - assign vm_mode_reg__read__h617886 = { csrf_vm_mode_sv39_reg, 3'b0 } ; - assign w__h650616 = + assign value__h489582 = { 1'b0, f1_exp__h484637 != 8'd0, f1_sfd__h484638 } ; + assign value__h528435 = { 1'b0, f2_exp__h523631 != 8'd0, f2_sfd__h523632 } ; + assign value__h567739 = { 1'b0, f3_exp__h562935 != 8'd0, f3_sfd__h562936 } ; + assign vm_mode_reg__read__h617563 = { csrf_vm_mode_sv39_reg, 3'b0 } ; + assign w__h650280 = coreFix_globalSpecUpdate_correctSpecTag_0$whas ? - result__h650672 : + result__h650336 : 12'd4095 ; - assign x__h155035 = + assign x__h154726 = coreFix_memExe_reqLdQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLdQ_data_0_lat_0$whas ? coreFix_memExe_reqLdQ_data_0_lat_0$wget[68:64] : coreFix_memExe_reqLdQ_data_0_rl[68:64]) : 5'd0 ; - assign x__h155041 = + assign x__h154732 = coreFix_memExe_reqLdQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLdQ_data_0_lat_0$whas ? coreFix_memExe_reqLdQ_data_0_lat_0$wget[63:0] : coreFix_memExe_reqLdQ_data_0_rl[63:0]) : 64'd0 ; - assign x__h158582 = { 3'd0, sbIdx__h158461 } ; - assign x__h158588 = + assign x__h158273 = { 3'd0, sbIdx__h158152 } ; + assign x__h158279 = coreFix_memExe_reqStQ_data_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_coreFix_memExe_doIssueSB ? coreFix_memExe_reqStQ_data_0_lat_0$wget[63:0] : coreFix_memExe_reqStQ_data_0_rl[63:0]) : 64'd0 ; - assign x__h161398 = + assign x__h161089 = coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ? coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[152:148] : coreFix_memExe_reqLrScAmoQ_data_0_rl[152:148]) : 5'd0 ; - assign x__h161402 = + assign x__h161093 = coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ? coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[147:84] : coreFix_memExe_reqLrScAmoQ_data_0_rl[147:84]) : 64'd0 ; - assign x__h163250 = + assign x__h162941 = coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ? coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[70:7] : coreFix_memExe_reqLrScAmoQ_data_0_rl[70:7]) : 64'd0 ; - assign x__h18203 = + assign x__h17895 = mmio_dataReqQ_enqReq_lat_0$whas ? mmio_dataReqQ_enqReq_lat_0$wget[141:78] : mmio_dataReqQ_enqReq_rl[141:78] ; - assign x__h183973 = - sbCons$lazyLookup_3_get[3] ? rf$read_3_rd1 : y_avValue__h183139 ; - assign x__h183974 = - sbCons$lazyLookup_3_get[2] ? rf$read_3_rd2 : y_avValue__h183820 ; - assign x__h184195 = { vaddr__h184061[2:0], 3'b0 } ; - assign x__h194496 = + assign x__h183665 = + sbCons$lazyLookup_3_get[3] ? rf$read_3_rd1 : y_avValue__h182831 ; + assign x__h183666 = + sbCons$lazyLookup_3_get[2] ? rf$read_3_rd2 : y_avValue__h183512 ; + assign x__h183887 = { vaddr__h183753[2:0], 3'b0 } ; + assign x__h194188 = coreFix_memExe_dMem_cache_m_banks_0_processAmo[90] ? - curData__h193733[63:32] : - curData__h193733[31:0] ; - assign x__h20741 = + curData__h193425[63:32] : + curData__h193425[31:0] ; + assign x__h20433 = mmio_dataReqQ_enqReq_lat_0$whas ? mmio_dataReqQ_enqReq_lat_0$wget[63:0] : mmio_dataReqQ_enqReq_rl[63:0] ; - assign x__h289512 = + assign x__h289204 = coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[152:148] : coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[152:148]) : 5'd0 ; - assign x__h289524 = + assign x__h289216 = coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[147:84] : coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[147:84]) : 64'd0 ; - assign x__h291378 = + assign x__h291070 = coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[70:7] : coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[70:7]) : 64'd0 ; - assign x__h304451 = + assign x__h304143 = EN_dCacheToParent_fromP_enq ? coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[2:0] : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[2:0] ; - assign x__h340182 = - { (_theResult___exp__h383514 != 8'd255 || - _theResult___sfd__h383515 == 23'd0) && + assign x__h339873 = + { (_theResult___exp__h383205 != 8'd255 || + _theResult___sfd__h383206 == 23'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5236, - out_f_exp__h383791, - out_f_sfd__h383792 } ; - assign x__h366732 = - sfd__h340778 << (x__h366765[11] ? 12'hAAA : x__h366765) ; - assign x__h366765 = + out_f_exp__h383482, + out_f_sfd__h383483 } ; + assign x__h366423 = + sfd__h340469 << (x__h366456[11] ? 12'hAAA : x__h366456) ; + assign x__h366456 = 12'd57 - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4650 ; - assign x__h385884 = - { (_theResult___exp__h429211 != 8'd255 || - _theResult___sfd__h429212 == 23'd0) && + assign x__h385575 = + { (_theResult___exp__h428902 != 8'd255 || + _theResult___sfd__h428903 == 23'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6628, - out_f_exp__h429488, - out_f_sfd__h429489 } ; - assign x__h412429 = - sfd__h386480 << (x__h412462[11] ? 12'hAAA : x__h412462) ; - assign x__h412462 = + out_f_exp__h429179, + out_f_sfd__h429180 } ; + assign x__h412120 = + sfd__h386171 << (x__h412153[11] ? 12'hAAA : x__h412153) ; + assign x__h412153 = 12'd57 - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d6042 ; - assign x__h431579 = - { (_theResult___exp__h474906 != 8'd255 || - _theResult___sfd__h474907 == 23'd0) && + assign x__h431270 = + { (_theResult___exp__h474597 != 8'd255 || + _theResult___sfd__h474598 == 23'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8020, - out_f_exp__h475183, - out_f_sfd__h475184 } ; - assign x__h458124 = - sfd__h432175 << (x__h458157[11] ? 12'hAAA : x__h458157) ; - assign x__h458157 = + out_f_exp__h474874, + out_f_sfd__h474875 } ; + assign x__h457815 = + sfd__h431866 << (x__h457848[11] ? 12'hAAA : x__h457848) ; + assign x__h457848 = 12'd57 - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7434 ; - assign x__h46110 = + assign x__h45802 = mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[141:78] : mmio_cRqQ_enqReq_rl[141:78] ; - assign x__h484468 = - sbCons$lazyLookup_2_get[3] ? rf$read_2_rd1 : y_avValue__h481607 ; - assign x__h484469 = - sbCons$lazyLookup_2_get[2] ? rf$read_2_rd2 : y_avValue__h482290 ; - assign x__h484470 = - sbCons$lazyLookup_2_get[1] ? rf$read_2_rd3 : y_avValue__h482967 ; - assign x__h48646 = + assign x__h48338 = mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[63:0] : mmio_cRqQ_enqReq_rl[63:0] ; - assign x__h506383 = sfd__h485308 << x__h506416 ; - assign x__h506416 = + assign x__h484159 = + sbCons$lazyLookup_2_get[3] ? rf$read_2_rd1 : y_avValue__h481298 ; + assign x__h484160 = + sbCons$lazyLookup_2_get[2] ? rf$read_2_rd2 : y_avValue__h481981 ; + assign x__h484161 = + sbCons$lazyLookup_2_get[1] ? rf$read_2_rd3 : y_avValue__h482658 ; + assign x__h506074 = sfd__h484999 << x__h506107 ; + assign x__h506107 = 12'd57 - _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d8760 ; - assign x__h545236 = sfd__h524302 << x__h545269 ; - assign x__h545269 = + assign x__h544927 = sfd__h523993 << x__h544960 ; + assign x__h544960 = 12'd57 - _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d10245 ; - assign x__h584540 = sfd__h563606 << x__h584573 ; - assign x__h584573 = + assign x__h584231 = sfd__h563297 << x__h584264 ; + assign x__h584264 = 12'd57 - _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d9475 ; - assign x__h606329 = + assign x__h606020 = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? - _theResult___fst__h606340 : - a__h605792 ; - assign x__h606355 = a__h605792[63] ^ b__h605793[63] ; - assign x__h606941 = + _theResult___fst__h606031 : + a__h605483 ; + assign x__h606046 = a__h605483[63] ^ b__h605484[63] ; + assign x__h606632 = (coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$D_OUT == 64'd0) ? { 64'hFFFFFFFFFFFFFFFF, coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$D_OUT[139:76] } : { coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d11256, coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d11257 } ; - assign x__h616677 = { csrf_frm_reg, csrf_fflags_reg } ; - assign x__h620994 = + assign x__h616354 = { csrf_frm_reg, csrf_fflags_reg } ; + assign x__h620659 = coreFix_aluExe_1_dispToRegQ$first[131] ? - rVal1__h613231 : - v__h612041 ; - assign x__h620995 = - sbCons$lazyLookup_1_get[2] ? rf$read_1_rd2 : y_avValue__h619004 ; - assign x__h643354 = + rVal1__h612922 : + v__h611732 ; + assign x__h620660 = + sbCons$lazyLookup_1_get[2] ? rf$read_1_rd2 : y_avValue__h618669 ; + assign x__h643018 = coreFix_aluExe_0_dispToRegQ$first[131] ? - rVal1__h637895 : - v__h636859 ; - assign x__h643355 = - sbCons$lazyLookup_0_get[2] ? rf$read_0_rd2 : y_avValue__h641374 ; - assign x__h650620 = 12'd1 << coreFix_aluExe_1_exeToFinQ$first[15:12] ; - assign x__h650671 = 12'd1 << coreFix_aluExe_0_exeToFinQ$first[15:12] ; - assign x__h701106 = + rVal1__h637560 : + v__h636524 ; + assign x__h643019 = + sbCons$lazyLookup_0_get[2] ? rf$read_0_rd2 : y_avValue__h641038 ; + assign x__h650284 = 12'd1 << coreFix_aluExe_1_exeToFinQ$first[15:12] ; + assign x__h650335 = 12'd1 << coreFix_aluExe_0_exeToFinQ$first[15:12] ; + assign x__h700768 = (!rob$deqPort_0_deq_data[166] && (rob$deqPort_0_deq_data[165:162] == 4'd1 || rob$deqPort_0_deq_data[165:162] == 4'd12)) ? rob$deqPort_0_deq_data[161:98] : rob$deqPort_0_deq_data[95:32] ; - assign x__h709701 = { cause_code__h707068, 2'b0 } ; - assign x__h718668 = { 1'b0, csrf_spp_reg } ; - assign x__h722429 = commitStage_rg_serialnum + y__h722455 ; - assign x__h724126 = - NOT_rob_deqPort_0_canDeq__5214_5215_OR_rob_deq_ETC___d15503 ? - y_avValue_snd_snd_snd_fst__h723950 : - IF_rob_deqPort_0_canDeq__5214_THEN_IF_NOT_rob__ETC___d15530 ; - assign x__h76055 = mmio_pRqQ_data_0[31:0] ; - assign x_addr__h316374 = + assign x__h708381 = { cause_code__h705748, 2'b0 } ; + assign x__h716537 = { 1'b0, csrf_spp_reg } ; + assign x__h720263 = + NOT_rob_deqPort_0_canDeq__5156_5157_OR_rob_deq_ETC___d15348 ? + y_avValue_snd_snd_snd_fst__h720086 : + IF_rob_deqPort_0_canDeq__5156_THEN_IF_NOT_rob__ETC___d15375 ; + assign x__h75747 = mmio_pRqQ_data_0[31:0] ; + assign x_addr__h316066 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[578:515] : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[578:515] ; - assign x_data__h65904 = + assign x_data__h65596 = EN_mmioToPlatform_pRq_enq ? mmio_pRqQ_enqReq_lat_0$wget[31:0] : mmio_pRqQ_enqReq_rl[31:0] ; - assign x_data_imm__h678959 = fetchStage$pipelines_0_first[159:128] ; - assign x_data_imm__h694502 = fetchStage$pipelines_1_first[159:128] ; - assign x_decodeInfo_frm__h658907 = csrf_frm_reg ; - assign x_quotient__h477567 = + assign x_data_imm__h678623 = fetchStage$pipelines_0_first[159:128] ; + assign x_data_imm__h694166 = fetchStage$pipelines_1_first[159:128] ; + assign x_decodeInfo_frm__h658571 = csrf_frm_reg ; + assign x_quotient__h477258 = coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[75] ? 64'hFFFFFFFFFFFFFFFF : ((coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[10] && coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[9]) ? - q___1__h478352 : + q___1__h478043 : coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[203:140]) ; - assign x_reg_ifc__read__h613638 = { 63'd0, csrf_stats_module_doStats } ; - assign x_remainder__h477568 = + assign x_reg_ifc__read__h613329 = { 63'd0, csrf_stats_module_doStats } ; + assign x_remainder__h477259 = coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[75] ? coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[74:11] : ((coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[10] && coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[8]) ? - r___1__h478379 : + r___1__h478070 : coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[139:76]) ; - assign y__h256430 = + assign y__h256122 = { coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:518], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[95:90] } ; - assign y__h623720 = coreFix_aluExe_1_regToExeQ$first[176:113] + 64'd4 ; - assign y__h645787 = coreFix_aluExe_0_regToExeQ$first[176:113] + 64'd4 ; - assign y__h650650 = ~x__h650620 ; - assign y__h655581 = + assign y__h623385 = coreFix_aluExe_1_regToExeQ$first[176:113] + 64'd4 ; + assign y__h645451 = coreFix_aluExe_0_regToExeQ$first[176:113] + 64'd4 ; + assign y__h650314 = ~x__h650284 ; + assign y__h655245 = { 4'd15, ~csrf_mideleg_11_reg, 1'd1, @@ -31920,74 +31748,70 @@ module mkCore(CLK, ~csrf_mideleg_5_3_reg, 1'd1, ~csrf_mideleg_1_0_reg } ; - assign y__h689972 = 12'd1 << specTagManager$nextSpecTag ; - assign y__h722455 = - rob$deqPort_0_canDeq ? - y_avValue_snd_snd_snd_snd_snd__h722470 : - 64'd0 ; - assign y__h723907 = - NOT_rob_deqPort_0_canDeq__5214_5215_OR_rob_deq_ETC___d15503 ? - y_avValue_snd_snd_snd_snd_snd__h723956 : - y__h722455 ; - assign y_avValue__h183139 = + assign y__h689636 = 12'd1 << specTagManager$nextSpecTag ; + assign y__h720039 = + NOT_rob_deqPort_0_canDeq__5156_5157_OR_rob_deq_ETC___d15348 ? + y_avValue_snd_snd_snd_snd_snd__h720092 : + IF_rob_deqPort_0_canDeq__5156_THEN_IF_NOT_rob__ETC___d15265 ; + assign y_avValue__h182831 = NOT_coreFix_memExe_bypassWire_0_whas__584_590__ETC___d1611 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_memExe_bypassWire_0_whas__584_5_ETC___d1679 ; - assign y_avValue__h183820 = + assign y_avValue__h183512 = NOT_coreFix_memExe_bypassWire_0_whas__584_590__ETC___d1640 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_memExe_bypassWire_0_whas__584_5_ETC___d1687 ; - assign y_avValue__h481607 = + assign y_avValue__h481298 = NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8327 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8454 ; - assign y_avValue__h482290 = + assign y_avValue__h481981 = NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8356 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8462 ; - assign y_avValue__h482967 = + assign y_avValue__h482658 = NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8382 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8470 ; - assign y_avValue__h613174 = + assign y_avValue__h612865 = NOT_coreFix_aluExe_1_bypassWire_0_whas__1510_1_ETC___d11537 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : - IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11949 ; - assign y_avValue__h619004 = + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11946 ; + assign y_avValue__h618669 = NOT_coreFix_aluExe_1_bypassWire_0_whas__1510_1_ETC___d11567 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : - IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11958 ; - assign y_avValue__h637840 = - NOT_coreFix_aluExe_0_bypassWire_0_whas__2372_2_ETC___d12399 ? + IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11955 ; + assign y_avValue__h637505 = + NOT_coreFix_aluExe_0_bypassWire_0_whas__2369_2_ETC___d12396 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__237_ETC___d12623 ; - assign y_avValue__h641374 = - NOT_coreFix_aluExe_0_bypassWire_0_whas__2372_2_ETC___d12429 ? + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12620 ; + assign y_avValue__h641038 = + NOT_coreFix_aluExe_0_bypassWire_0_whas__2369_2_ETC___d12426 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__237_ETC___d12632 ; - assign y_avValue__h707954 = + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12629 ; + assign y_avValue__h706634 = (csrf_stvec_mode_low_reg && commitStage_commitTrap[4]) ? - base__h709686 + { 58'd0, x__h709701 } : - base__h709686 ; - assign y_avValue__h709723 = + base__h708366 + { 58'd0, x__h708381 } : + base__h708366 ; + assign y_avValue__h708403 = (csrf_mtvec_mode_low_reg && commitStage_commitTrap[4]) ? - base__h709889 + { 58'd0, x__h709701 } : - base__h709889 ; - assign y_avValue_fst__h683232 = + base__h708569 + { 58'd0, x__h708381 } : + base__h708569 ; + assign y_avValue_fst__h682896 = (fetchStage$pipelines_0_first[194:192] == 3'd1) ? - spec_bits__h689959 : + spec_bits__h689623 : specTagManager$currentSpecBits ; - assign y_avValue_fst__h683261 = - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d13663 ? - y_avValue_fst__h683232 : - specTagManager$currentSpecBits ; - assign y_avValue_fst__h683295 = + assign y_avValue_snd_fst__h683178 = ((fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3582_AND__ETC___d13604) ? - y_avValue_fst__h683261 : + regRenamingTable_rename_0_canRename__3578_AND__ETC___d13600) ? + y_avValue_snd_fst__h683220 : specTagManager$currentSpecBits ; - assign y_avValue_fst__h722016 = + assign y_avValue_snd_fst__h683220 = + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d13659 ? + y_avValue_fst__h682896 : + specTagManager$currentSpecBits ; + assign y_avValue_snd_fst__h719462 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[167] || rob$deqPort_0_deq_data[186:182] == 5'd0 || @@ -32001,10 +31825,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[186:182] == 5'd20) ? 5'd0 : rob$deqPort_0_deq_data[31:27] ; - assign y_avValue_fst__h723799 = - IF_rob_deqPort_0_canDeq__5214_THEN_IF_NOT_rob__ETC___d15509 | - rob$deqPort_1_deq_data[31:27] ; - assign y_avValue_fst__h723827 = + assign y_avValue_snd_fst__h720076 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[186:182] == 5'd0 || @@ -32016,9 +31837,12 @@ module mkCore(CLK, rob$deqPort_1_deq_data[186:182] == 5'd15 || rob$deqPort_1_deq_data[186:182] == 5'd19 || rob$deqPort_1_deq_data[186:182] == 5'd20) ? - IF_rob_deqPort_0_canDeq__5214_THEN_IF_NOT_rob__ETC___d15509 : - y_avValue_fst__h723799 ; - assign y_avValue_snd_snd_snd_fst__h722464 = + IF_rob_deqPort_0_canDeq__5156_THEN_IF_NOT_rob__ETC___d15354 : + y_avValue_snd_fst__h720105 ; + assign y_avValue_snd_fst__h720105 = + IF_rob_deqPort_0_canDeq__5156_THEN_IF_NOT_rob__ETC___d15354 | + rob$deqPort_1_deq_data[31:27] ; + assign y_avValue_snd_snd_snd_fst__h719472 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[167] || rob$deqPort_0_deq_data[186:182] == 5'd0 || @@ -32032,7 +31856,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[186:182] == 5'd20) ? 2'd0 : 2'd1 ; - assign y_avValue_snd_snd_snd_fst__h723950 = + assign y_avValue_snd_snd_snd_fst__h720086 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[186:182] == 5'd0 || @@ -32044,12 +31868,12 @@ module mkCore(CLK, rob$deqPort_1_deq_data[186:182] == 5'd15 || rob$deqPort_1_deq_data[186:182] == 5'd19 || rob$deqPort_1_deq_data[186:182] == 5'd20) ? - IF_rob_deqPort_0_canDeq__5214_THEN_IF_NOT_rob__ETC___d15530 : - y_avValue_snd_snd_snd_fst__h723979 ; - assign y_avValue_snd_snd_snd_fst__h723979 = - IF_rob_deqPort_0_canDeq__5214_THEN_IF_NOT_rob__ETC___d15530 + + IF_rob_deqPort_0_canDeq__5156_THEN_IF_NOT_rob__ETC___d15375 : + y_avValue_snd_snd_snd_fst__h720115 ; + assign y_avValue_snd_snd_snd_fst__h720115 = + IF_rob_deqPort_0_canDeq__5156_THEN_IF_NOT_rob__ETC___d15375 + 2'd1 ; - assign y_avValue_snd_snd_snd_snd_snd__h722470 = + assign y_avValue_snd_snd_snd_snd_snd__h719478 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[167] || rob$deqPort_0_deq_data[186:182] == 5'd0 || @@ -32063,7 +31887,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[186:182] == 5'd20) ? 64'd0 : 64'd1 ; - assign y_avValue_snd_snd_snd_snd_snd__h723956 = + assign y_avValue_snd_snd_snd_snd_snd__h720092 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[186:182] == 5'd0 || @@ -32075,193 +31899,19 @@ module mkCore(CLK, rob$deqPort_1_deq_data[186:182] == 5'd15 || rob$deqPort_1_deq_data[186:182] == 5'd19 || rob$deqPort_1_deq_data[186:182] == 5'd20) ? - y__h722455 : - y_avValue_snd_snd_snd_snd_snd__h723985 ; - assign y_avValue_snd_snd_snd_snd_snd__h723985 = y__h722455 + 64'd1 ; - always@(v_f_to_TV_1$D_OUT) - begin - case (v_f_to_TV_1$D_OUT[153:142]) - 12'd1, - 12'd2, - 12'd3, - 12'd256, - 12'd260, - 12'd261, - 12'd262, - 12'd320, - 12'd321, - 12'd322, - 12'd323, - 12'd324, - 12'd384, - 12'd768, - 12'd769, - 12'd770, - 12'd771, - 12'd772, - 12'd773, - 12'd774, - 12'd832, - 12'd833, - 12'd834, - 12'd835, - 12'd836, - 12'd1968, - 12'd1969, - 12'd1970, - 12'd1971, - 12'd2048, - 12'd2049, - 12'd2816, - 12'd2818, - 12'd3072, - 12'd3073, - 12'd3074, - 12'd3857, - 12'd3858, - 12'd3859, - 12'd3860: - CASE_v_f_to_TV_1D_OUT_BITS_153_TO_142_1_v_f_t_ETC__q1 = - v_f_to_TV_1$D_OUT[153:142]; - default: CASE_v_f_to_TV_1D_OUT_BITS_153_TO_142_1_v_f_t_ETC__q1 = - 12'd2303; - endcase - end - always@(v_f_to_TV_1$D_OUT) - begin - case (v_f_to_TV_1$D_OUT[139:136]) - 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: - CASE_v_f_to_TV_1D_OUT_BITS_139_TO_136_0_v_f_t_ETC__q2 = - v_f_to_TV_1$D_OUT[139:136]; - default: CASE_v_f_to_TV_1D_OUT_BITS_139_TO_136_0_v_f_t_ETC__q2 = 4'd15; - endcase - end - always@(v_f_to_TV_1$D_OUT) - begin - case (v_f_to_TV_1$D_OUT[139:136]) - 4'd0, - 4'd1, - 4'd2, - 4'd3, - 4'd4, - 4'd5, - 4'd6, - 4'd7, - 4'd8, - 4'd9, - 4'd11, - 4'd12, - 4'd13: - CASE_v_f_to_TV_1D_OUT_BITS_139_TO_136_0_v_f_t_ETC__q3 = - v_f_to_TV_1$D_OUT[139:136]; - default: CASE_v_f_to_TV_1D_OUT_BITS_139_TO_136_0_v_f_t_ETC__q3 = 4'd15; - endcase - end - always@(v_f_to_TV_1$D_OUT) - begin - case (v_f_to_TV_1$D_OUT[71:70]) - 2'd0, 2'd1: - CASE_v_f_to_TV_1D_OUT_BITS_71_TO_70_0_v_f_to__ETC__q4 = - v_f_to_TV_1$D_OUT[71:70]; - default: CASE_v_f_to_TV_1D_OUT_BITS_71_TO_70_0_v_f_to__ETC__q4 = 2'd2; - endcase - end - always@(v_f_to_TV_0$D_OUT) - begin - case (v_f_to_TV_0$D_OUT[153:142]) - 12'd1, - 12'd2, - 12'd3, - 12'd256, - 12'd260, - 12'd261, - 12'd262, - 12'd320, - 12'd321, - 12'd322, - 12'd323, - 12'd324, - 12'd384, - 12'd768, - 12'd769, - 12'd770, - 12'd771, - 12'd772, - 12'd773, - 12'd774, - 12'd832, - 12'd833, - 12'd834, - 12'd835, - 12'd836, - 12'd1968, - 12'd1969, - 12'd1970, - 12'd1971, - 12'd2048, - 12'd2049, - 12'd2816, - 12'd2818, - 12'd3072, - 12'd3073, - 12'd3074, - 12'd3857, - 12'd3858, - 12'd3859, - 12'd3860: - CASE_v_f_to_TV_0D_OUT_BITS_153_TO_142_1_v_f_t_ETC__q5 = - v_f_to_TV_0$D_OUT[153:142]; - default: CASE_v_f_to_TV_0D_OUT_BITS_153_TO_142_1_v_f_t_ETC__q5 = - 12'd2303; - endcase - end - always@(v_f_to_TV_0$D_OUT) - begin - case (v_f_to_TV_0$D_OUT[139:136]) - 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: - CASE_v_f_to_TV_0D_OUT_BITS_139_TO_136_0_v_f_t_ETC__q6 = - v_f_to_TV_0$D_OUT[139:136]; - default: CASE_v_f_to_TV_0D_OUT_BITS_139_TO_136_0_v_f_t_ETC__q6 = 4'd15; - endcase - end - always@(v_f_to_TV_0$D_OUT) - begin - case (v_f_to_TV_0$D_OUT[139:136]) - 4'd0, - 4'd1, - 4'd2, - 4'd3, - 4'd4, - 4'd5, - 4'd6, - 4'd7, - 4'd8, - 4'd9, - 4'd11, - 4'd12, - 4'd13: - CASE_v_f_to_TV_0D_OUT_BITS_139_TO_136_0_v_f_t_ETC__q7 = - v_f_to_TV_0$D_OUT[139:136]; - default: CASE_v_f_to_TV_0D_OUT_BITS_139_TO_136_0_v_f_t_ETC__q7 = 4'd15; - endcase - end - always@(v_f_to_TV_0$D_OUT) - begin - case (v_f_to_TV_0$D_OUT[71:70]) - 2'd0, 2'd1: - CASE_v_f_to_TV_0D_OUT_BITS_71_TO_70_0_v_f_to__ETC__q8 = - v_f_to_TV_0$D_OUT[71:70]; - default: CASE_v_f_to_TV_0D_OUT_BITS_71_TO_70_0_v_f_to__ETC__q8 = 2'd2; - endcase - end + IF_rob_deqPort_0_canDeq__5156_THEN_IF_NOT_rob__ETC___d15265 : + y_avValue_snd_snd_snd_snd_snd__h720121 ; + assign y_avValue_snd_snd_snd_snd_snd__h720121 = + IF_rob_deqPort_0_canDeq__5156_THEN_IF_NOT_rob__ETC___d15265 + + 64'd1 ; always@(mmio_cRqQ_data_0) begin case (mmio_cRqQ_data_0[77:76]) 2'd0, 2'd1, 2'd2: - CASE_mmio_cRqQ_data_0_BITS_77_TO_76_0_mmio_cRq_ETC__q9 = + CASE_mmio_cRqQ_data_0_BITS_77_TO_76_0_mmio_cRq_ETC__q1 = mmio_cRqQ_data_0[77:72]; 2'd3: - CASE_mmio_cRqQ_data_0_BITS_77_TO_76_0_mmio_cRq_ETC__q9 = + CASE_mmio_cRqQ_data_0_BITS_77_TO_76_0_mmio_cRq_ETC__q1 = { 2'd3, mmio_cRqQ_data_0[75:72] }; endcase end @@ -32270,28 +31920,28 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87]) 3'd0: - x__h198472 = + x__h198164 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0]; 3'd1: - x__h198472 = + x__h198164 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64]; 3'd2: - x__h198472 = + x__h198164 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128]; 3'd3: - x__h198472 = + x__h198164 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192]; 3'd4: - x__h198472 = + x__h198164 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256]; 3'd5: - x__h198472 = + x__h198164 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320]; 3'd6: - x__h198472 = + x__h198164 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384]; 3'd7: - x__h198472 = + x__h198164 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448]; endcase end @@ -32307,28 +31957,28 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP) 3'd0: - x__h288079 = + x__h287771 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0; 3'd1: - x__h288079 = + x__h287771 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1; 3'd2: - x__h288079 = + x__h287771 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2; 3'd3: - x__h288079 = + x__h287771 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3; 3'd4: - x__h288079 = + x__h287771 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4; 3'd5: - x__h288079 = + x__h287771 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5; 3'd6: - x__h288079 = + x__h287771 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6; 3'd7: - x__h288079 = + x__h287771 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7; endcase end @@ -32338,10 +31988,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - addr__h292300 = + addr__h291992 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[581:518]; 1'd1: - addr__h292300 = + addr__h291992 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[581:518]; endcase end @@ -32350,36 +32000,36 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91]) 3'd0: - curData__h193733 = + curData__h193425 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0]; 3'd1: - curData__h193733 = + curData__h193425 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64]; 3'd2: - curData__h193733 = + curData__h193425 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128]; 3'd3: - curData__h193733 = + curData__h193425 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192]; 3'd4: - curData__h193733 = + curData__h193425 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256]; 3'd5: - curData__h193733 = + curData__h193425 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320]; 3'd6: - curData__h193733 = + curData__h193425 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384]; 3'd7: - curData__h193733 = + curData__h193425 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448]; endcase end always@(commitStage_commitTrap) begin case (commitStage_commitTrap[3:0]) - 4'd0, 4'd3: trap_val__h708107 = commitStage_commitTrap[132:69]; - default: trap_val__h708107 = + 4'd0, 4'd3: trap_val__h706787 = commitStage_commitTrap[132:69]; + default: trap_val__h706787 = (commitStage_commitTrap[3:0] != 4'd2 && commitStage_commitTrap[3:0] != 4'd8 && commitStage_commitTrap[3:0] != 4'd9 && @@ -32394,468 +32044,468 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - x__h293849 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[2:0]; + x__h293541 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[2:0]; 1'd1: - x__h293849 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[2:0]; + x__h293541 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[2:0]; endcase end always@(f_csr_reqs$D_OUT or - fflags_csr__read__h613508 or - frm_csr__read__h613519 or - fcsr_csr__read__h613533 or - sstatus_csr__read__h613729 or - sie_csr__read__h613798 or - stvec_csr__read__h613841 or - scounteren_csr__read__h613894 or + fflags_csr__read__h613199 or + frm_csr__read__h613210 or + fcsr_csr__read__h613224 or + sstatus_csr__read__h613420 or + sie_csr__read__h613489 or + stvec_csr__read__h613532 or + scounteren_csr__read__h613585 or csrf_sscratch_csr or csrf_sepc_csr or - scause_csr__read__h614032 or + scause_csr__read__h613723 or csrf_stval_csr or - sip_csr__read__h614171 or - satp_csr__read__h614234 or - mstatus_csr__read__h614377 or - medeleg_csr__read__h614525 or - mideleg_csr__read__h614620 or - mie_csr__read__h614751 or - mtvec_csr__read__h614833 or - mcounteren_csr__read__h614925 or + sip_csr__read__h613862 or + satp_csr__read__h613925 or + mstatus_csr__read__h614068 or + medeleg_csr__read__h614216 or + mideleg_csr__read__h614311 or + mie_csr__read__h614435 or + mtvec_csr__read__h614517 or + mcounteren_csr__read__h614609 or csrf_mscratch_csr or csrf_mepc_csr or - mcause_csr__read__h615180 or + mcause_csr__read__h614864 or csrf_mtval_csr or - mip_csr__read__h615420 or + mip_csr__read__h615097 or csrf_rg_dcsr or csrf_rg_dpc or csrf_rg_dscratch0 or csrf_rg_dscratch1 or - x_reg_ifc__read__h613638 or - n__read__h615524 or n__read__h615715 or csrf_time_reg) + x_reg_ifc__read__h613329 or + n__read__h615201 or n__read__h615392 or csrf_time_reg) begin case (f_csr_reqs$D_OUT[75:64]) - 12'd1: data_out__h727964 = fflags_csr__read__h613508; - 12'd2: data_out__h727964 = frm_csr__read__h613519; - 12'd3: data_out__h727964 = fcsr_csr__read__h613533; - 12'd256: data_out__h727964 = sstatus_csr__read__h613729; - 12'd260: data_out__h727964 = sie_csr__read__h613798; - 12'd261: data_out__h727964 = stvec_csr__read__h613841; - 12'd262: data_out__h727964 = scounteren_csr__read__h613894; - 12'd320: data_out__h727964 = csrf_sscratch_csr; - 12'd321: data_out__h727964 = csrf_sepc_csr; - 12'd322: data_out__h727964 = scause_csr__read__h614032; - 12'd323: data_out__h727964 = csrf_stval_csr; - 12'd324: data_out__h727964 = sip_csr__read__h614171; - 12'd384: data_out__h727964 = satp_csr__read__h614234; - 12'd768: data_out__h727964 = mstatus_csr__read__h614377; - 12'd769: data_out__h727964 = 64'h800000000014112D; - 12'd770: data_out__h727964 = medeleg_csr__read__h614525; - 12'd771: data_out__h727964 = mideleg_csr__read__h614620; - 12'd772: data_out__h727964 = mie_csr__read__h614751; - 12'd773: data_out__h727964 = mtvec_csr__read__h614833; - 12'd774: data_out__h727964 = mcounteren_csr__read__h614925; - 12'd832: data_out__h727964 = csrf_mscratch_csr; - 12'd833: data_out__h727964 = csrf_mepc_csr; - 12'd834: data_out__h727964 = mcause_csr__read__h615180; - 12'd835: data_out__h727964 = csrf_mtval_csr; - 12'd836: data_out__h727964 = mip_csr__read__h615420; - 12'd1968: data_out__h727964 = csrf_rg_dcsr; - 12'd1969: data_out__h727964 = csrf_rg_dpc; - 12'd1970: data_out__h727964 = csrf_rg_dscratch0; - 12'd1971: data_out__h727964 = csrf_rg_dscratch1; + 12'd1: data_out__h723975 = fflags_csr__read__h613199; + 12'd2: data_out__h723975 = frm_csr__read__h613210; + 12'd3: data_out__h723975 = fcsr_csr__read__h613224; + 12'd256: data_out__h723975 = sstatus_csr__read__h613420; + 12'd260: data_out__h723975 = sie_csr__read__h613489; + 12'd261: data_out__h723975 = stvec_csr__read__h613532; + 12'd262: data_out__h723975 = scounteren_csr__read__h613585; + 12'd320: data_out__h723975 = csrf_sscratch_csr; + 12'd321: data_out__h723975 = csrf_sepc_csr; + 12'd322: data_out__h723975 = scause_csr__read__h613723; + 12'd323: data_out__h723975 = csrf_stval_csr; + 12'd324: data_out__h723975 = sip_csr__read__h613862; + 12'd384: data_out__h723975 = satp_csr__read__h613925; + 12'd768: data_out__h723975 = mstatus_csr__read__h614068; + 12'd769: data_out__h723975 = 64'h800000000014112D; + 12'd770: data_out__h723975 = medeleg_csr__read__h614216; + 12'd771: data_out__h723975 = mideleg_csr__read__h614311; + 12'd772: data_out__h723975 = mie_csr__read__h614435; + 12'd773: data_out__h723975 = mtvec_csr__read__h614517; + 12'd774: data_out__h723975 = mcounteren_csr__read__h614609; + 12'd832: data_out__h723975 = csrf_mscratch_csr; + 12'd833: data_out__h723975 = csrf_mepc_csr; + 12'd834: data_out__h723975 = mcause_csr__read__h614864; + 12'd835: data_out__h723975 = csrf_mtval_csr; + 12'd836: data_out__h723975 = mip_csr__read__h615097; + 12'd1968: data_out__h723975 = csrf_rg_dcsr; + 12'd1969: data_out__h723975 = csrf_rg_dpc; + 12'd1970: data_out__h723975 = csrf_rg_dscratch0; + 12'd1971: data_out__h723975 = csrf_rg_dscratch1; 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: - data_out__h727964 = 64'd0; - 12'd2049: data_out__h727964 = x_reg_ifc__read__h613638; - 12'd2816, 12'd3072: data_out__h727964 = n__read__h615524; - 12'd2818, 12'd3074: data_out__h727964 = n__read__h615715; - 12'd3073: data_out__h727964 = csrf_time_reg; - default: data_out__h727964 = 64'b0; + data_out__h723975 = 64'd0; + 12'd2049: data_out__h723975 = x_reg_ifc__read__h613329; + 12'd2816, 12'd3072: data_out__h723975 = n__read__h615201; + 12'd2818, 12'd3074: data_out__h723975 = n__read__h615392; + 12'd3073: data_out__h723975 = csrf_time_reg; + default: data_out__h723975 = 64'b0; endcase end always@(coreFix_aluExe_1_dispToRegQ$first or - fflags_csr__read__h613508 or - frm_csr__read__h613519 or - fcsr_csr__read__h613533 or - sstatus_csr__read__h613729 or - sie_csr__read__h613798 or - stvec_csr__read__h613841 or - scounteren_csr__read__h613894 or + fflags_csr__read__h613199 or + frm_csr__read__h613210 or + fcsr_csr__read__h613224 or + sstatus_csr__read__h613420 or + sie_csr__read__h613489 or + stvec_csr__read__h613532 or + scounteren_csr__read__h613585 or csrf_sscratch_csr or csrf_sepc_csr or - scause_csr__read__h614032 or + scause_csr__read__h613723 or csrf_stval_csr or - sip_csr__read__h614171 or - satp_csr__read__h614234 or - mstatus_csr__read__h614377 or - medeleg_csr__read__h614525 or - mideleg_csr__read__h614620 or - mie_csr__read__h614751 or - mtvec_csr__read__h614833 or - mcounteren_csr__read__h614925 or + sip_csr__read__h613862 or + satp_csr__read__h613925 or + mstatus_csr__read__h614068 or + medeleg_csr__read__h614216 or + mideleg_csr__read__h614311 or + mie_csr__read__h614435 or + mtvec_csr__read__h614517 or + mcounteren_csr__read__h614609 or csrf_mscratch_csr or csrf_mepc_csr or - mcause_csr__read__h615180 or + mcause_csr__read__h614864 or csrf_mtval_csr or - mip_csr__read__h615420 or + mip_csr__read__h615097 or csrf_rg_dcsr or csrf_rg_dpc or csrf_rg_dscratch0 or csrf_rg_dscratch1 or - x_reg_ifc__read__h613638 or - n__read__h615524 or n__read__h615715 or csrf_time_reg) + x_reg_ifc__read__h613329 or + n__read__h615201 or n__read__h615392 or csrf_time_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[130:119]) - 12'd1: rVal1__h613231 = fflags_csr__read__h613508; - 12'd2: rVal1__h613231 = frm_csr__read__h613519; - 12'd3: rVal1__h613231 = fcsr_csr__read__h613533; - 12'd256: rVal1__h613231 = sstatus_csr__read__h613729; - 12'd260: rVal1__h613231 = sie_csr__read__h613798; - 12'd261: rVal1__h613231 = stvec_csr__read__h613841; - 12'd262: rVal1__h613231 = scounteren_csr__read__h613894; - 12'd320: rVal1__h613231 = csrf_sscratch_csr; - 12'd321: rVal1__h613231 = csrf_sepc_csr; - 12'd322: rVal1__h613231 = scause_csr__read__h614032; - 12'd323: rVal1__h613231 = csrf_stval_csr; - 12'd324: rVal1__h613231 = sip_csr__read__h614171; - 12'd384: rVal1__h613231 = satp_csr__read__h614234; - 12'd768: rVal1__h613231 = mstatus_csr__read__h614377; - 12'd769: rVal1__h613231 = 64'h800000000014112D; - 12'd770: rVal1__h613231 = medeleg_csr__read__h614525; - 12'd771: rVal1__h613231 = mideleg_csr__read__h614620; - 12'd772: rVal1__h613231 = mie_csr__read__h614751; - 12'd773: rVal1__h613231 = mtvec_csr__read__h614833; - 12'd774: rVal1__h613231 = mcounteren_csr__read__h614925; - 12'd832: rVal1__h613231 = csrf_mscratch_csr; - 12'd833: rVal1__h613231 = csrf_mepc_csr; - 12'd834: rVal1__h613231 = mcause_csr__read__h615180; - 12'd835: rVal1__h613231 = csrf_mtval_csr; - 12'd836: rVal1__h613231 = mip_csr__read__h615420; - 12'd1968: rVal1__h613231 = csrf_rg_dcsr; - 12'd1969: rVal1__h613231 = csrf_rg_dpc; - 12'd1970: rVal1__h613231 = csrf_rg_dscratch0; - 12'd1971: rVal1__h613231 = csrf_rg_dscratch1; + 12'd1: rVal1__h612922 = fflags_csr__read__h613199; + 12'd2: rVal1__h612922 = frm_csr__read__h613210; + 12'd3: rVal1__h612922 = fcsr_csr__read__h613224; + 12'd256: rVal1__h612922 = sstatus_csr__read__h613420; + 12'd260: rVal1__h612922 = sie_csr__read__h613489; + 12'd261: rVal1__h612922 = stvec_csr__read__h613532; + 12'd262: rVal1__h612922 = scounteren_csr__read__h613585; + 12'd320: rVal1__h612922 = csrf_sscratch_csr; + 12'd321: rVal1__h612922 = csrf_sepc_csr; + 12'd322: rVal1__h612922 = scause_csr__read__h613723; + 12'd323: rVal1__h612922 = csrf_stval_csr; + 12'd324: rVal1__h612922 = sip_csr__read__h613862; + 12'd384: rVal1__h612922 = satp_csr__read__h613925; + 12'd768: rVal1__h612922 = mstatus_csr__read__h614068; + 12'd769: rVal1__h612922 = 64'h800000000014112D; + 12'd770: rVal1__h612922 = medeleg_csr__read__h614216; + 12'd771: rVal1__h612922 = mideleg_csr__read__h614311; + 12'd772: rVal1__h612922 = mie_csr__read__h614435; + 12'd773: rVal1__h612922 = mtvec_csr__read__h614517; + 12'd774: rVal1__h612922 = mcounteren_csr__read__h614609; + 12'd832: rVal1__h612922 = csrf_mscratch_csr; + 12'd833: rVal1__h612922 = csrf_mepc_csr; + 12'd834: rVal1__h612922 = mcause_csr__read__h614864; + 12'd835: rVal1__h612922 = csrf_mtval_csr; + 12'd836: rVal1__h612922 = mip_csr__read__h615097; + 12'd1968: rVal1__h612922 = csrf_rg_dcsr; + 12'd1969: rVal1__h612922 = csrf_rg_dpc; + 12'd1970: rVal1__h612922 = csrf_rg_dscratch0; + 12'd1971: rVal1__h612922 = csrf_rg_dscratch1; 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: - rVal1__h613231 = 64'd0; - 12'd2049: rVal1__h613231 = x_reg_ifc__read__h613638; - 12'd2816, 12'd3072: rVal1__h613231 = n__read__h615524; - 12'd2818, 12'd3074: rVal1__h613231 = n__read__h615715; - 12'd3073: rVal1__h613231 = csrf_time_reg; - default: rVal1__h613231 = 64'b0; + rVal1__h612922 = 64'd0; + 12'd2049: rVal1__h612922 = x_reg_ifc__read__h613329; + 12'd2816, 12'd3072: rVal1__h612922 = n__read__h615201; + 12'd2818, 12'd3074: rVal1__h612922 = n__read__h615392; + 12'd3073: rVal1__h612922 = csrf_time_reg; + default: rVal1__h612922 = 64'b0; endcase end always@(coreFix_aluExe_0_dispToRegQ$first or - fflags_csr__read__h613508 or - frm_csr__read__h613519 or - fcsr_csr__read__h613533 or - sstatus_csr__read__h613729 or - sie_csr__read__h613798 or - stvec_csr__read__h613841 or - scounteren_csr__read__h613894 or + fflags_csr__read__h613199 or + frm_csr__read__h613210 or + fcsr_csr__read__h613224 or + sstatus_csr__read__h613420 or + sie_csr__read__h613489 or + stvec_csr__read__h613532 or + scounteren_csr__read__h613585 or csrf_sscratch_csr or csrf_sepc_csr or - scause_csr__read__h614032 or + scause_csr__read__h613723 or csrf_stval_csr or - sip_csr__read__h614171 or - satp_csr__read__h614234 or - mstatus_csr__read__h614377 or - medeleg_csr__read__h614525 or - mideleg_csr__read__h614620 or - mie_csr__read__h614751 or - mtvec_csr__read__h614833 or - mcounteren_csr__read__h614925 or + sip_csr__read__h613862 or + satp_csr__read__h613925 or + mstatus_csr__read__h614068 or + medeleg_csr__read__h614216 or + mideleg_csr__read__h614311 or + mie_csr__read__h614435 or + mtvec_csr__read__h614517 or + mcounteren_csr__read__h614609 or csrf_mscratch_csr or csrf_mepc_csr or - mcause_csr__read__h615180 or + mcause_csr__read__h614864 or csrf_mtval_csr or - mip_csr__read__h615420 or + mip_csr__read__h615097 or csrf_rg_dcsr or csrf_rg_dpc or csrf_rg_dscratch0 or csrf_rg_dscratch1 or - x_reg_ifc__read__h613638 or - n__read__h615524 or n__read__h615715 or csrf_time_reg) + x_reg_ifc__read__h613329 or + n__read__h615201 or n__read__h615392 or csrf_time_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[130:119]) - 12'd1: rVal1__h637895 = fflags_csr__read__h613508; - 12'd2: rVal1__h637895 = frm_csr__read__h613519; - 12'd3: rVal1__h637895 = fcsr_csr__read__h613533; - 12'd256: rVal1__h637895 = sstatus_csr__read__h613729; - 12'd260: rVal1__h637895 = sie_csr__read__h613798; - 12'd261: rVal1__h637895 = stvec_csr__read__h613841; - 12'd262: rVal1__h637895 = scounteren_csr__read__h613894; - 12'd320: rVal1__h637895 = csrf_sscratch_csr; - 12'd321: rVal1__h637895 = csrf_sepc_csr; - 12'd322: rVal1__h637895 = scause_csr__read__h614032; - 12'd323: rVal1__h637895 = csrf_stval_csr; - 12'd324: rVal1__h637895 = sip_csr__read__h614171; - 12'd384: rVal1__h637895 = satp_csr__read__h614234; - 12'd768: rVal1__h637895 = mstatus_csr__read__h614377; - 12'd769: rVal1__h637895 = 64'h800000000014112D; - 12'd770: rVal1__h637895 = medeleg_csr__read__h614525; - 12'd771: rVal1__h637895 = mideleg_csr__read__h614620; - 12'd772: rVal1__h637895 = mie_csr__read__h614751; - 12'd773: rVal1__h637895 = mtvec_csr__read__h614833; - 12'd774: rVal1__h637895 = mcounteren_csr__read__h614925; - 12'd832: rVal1__h637895 = csrf_mscratch_csr; - 12'd833: rVal1__h637895 = csrf_mepc_csr; - 12'd834: rVal1__h637895 = mcause_csr__read__h615180; - 12'd835: rVal1__h637895 = csrf_mtval_csr; - 12'd836: rVal1__h637895 = mip_csr__read__h615420; - 12'd1968: rVal1__h637895 = csrf_rg_dcsr; - 12'd1969: rVal1__h637895 = csrf_rg_dpc; - 12'd1970: rVal1__h637895 = csrf_rg_dscratch0; - 12'd1971: rVal1__h637895 = csrf_rg_dscratch1; + 12'd1: rVal1__h637560 = fflags_csr__read__h613199; + 12'd2: rVal1__h637560 = frm_csr__read__h613210; + 12'd3: rVal1__h637560 = fcsr_csr__read__h613224; + 12'd256: rVal1__h637560 = sstatus_csr__read__h613420; + 12'd260: rVal1__h637560 = sie_csr__read__h613489; + 12'd261: rVal1__h637560 = stvec_csr__read__h613532; + 12'd262: rVal1__h637560 = scounteren_csr__read__h613585; + 12'd320: rVal1__h637560 = csrf_sscratch_csr; + 12'd321: rVal1__h637560 = csrf_sepc_csr; + 12'd322: rVal1__h637560 = scause_csr__read__h613723; + 12'd323: rVal1__h637560 = csrf_stval_csr; + 12'd324: rVal1__h637560 = sip_csr__read__h613862; + 12'd384: rVal1__h637560 = satp_csr__read__h613925; + 12'd768: rVal1__h637560 = mstatus_csr__read__h614068; + 12'd769: rVal1__h637560 = 64'h800000000014112D; + 12'd770: rVal1__h637560 = medeleg_csr__read__h614216; + 12'd771: rVal1__h637560 = mideleg_csr__read__h614311; + 12'd772: rVal1__h637560 = mie_csr__read__h614435; + 12'd773: rVal1__h637560 = mtvec_csr__read__h614517; + 12'd774: rVal1__h637560 = mcounteren_csr__read__h614609; + 12'd832: rVal1__h637560 = csrf_mscratch_csr; + 12'd833: rVal1__h637560 = csrf_mepc_csr; + 12'd834: rVal1__h637560 = mcause_csr__read__h614864; + 12'd835: rVal1__h637560 = csrf_mtval_csr; + 12'd836: rVal1__h637560 = mip_csr__read__h615097; + 12'd1968: rVal1__h637560 = csrf_rg_dcsr; + 12'd1969: rVal1__h637560 = csrf_rg_dpc; + 12'd1970: rVal1__h637560 = csrf_rg_dscratch0; + 12'd1971: rVal1__h637560 = csrf_rg_dscratch1; 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: - rVal1__h637895 = 64'd0; - 12'd2049: rVal1__h637895 = x_reg_ifc__read__h613638; - 12'd2816, 12'd3072: rVal1__h637895 = n__read__h615524; - 12'd2818, 12'd3074: rVal1__h637895 = n__read__h615715; - 12'd3073: rVal1__h637895 = csrf_time_reg; - default: rVal1__h637895 = 64'b0; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd1: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 = - 52'hFFFFFFFFFFFFF; - 3'd2: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - 52'd0 : - 52'hFFFFFFFFFFFFF; - 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - 52'hFFFFFFFFFFFFF : - 52'd0; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 = 52'd0; + rVal1__h637560 = 64'd0; + 12'd2049: rVal1__h637560 = x_reg_ifc__read__h613329; + 12'd2816, 12'd3072: rVal1__h637560 = n__read__h615201; + 12'd2818, 12'd3074: rVal1__h637560 = n__read__h615392; + 12'd3073: rVal1__h637560 = csrf_time_reg; + default: rVal1__h637560 = 64'b0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h348365 = 8'd255; + 3'd0, 3'd1: _theResult___fst_exp__h348056 = 8'd255; 3'd2: - _theResult___fst_exp__h348365 = + _theResult___fst_exp__h348056 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 8'd254 : 8'd255; 3'd3: - _theResult___fst_exp__h348365 = + _theResult___fst_exp__h348056 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 8'd255 : 8'd254; - 3'd4: _theResult___fst_exp__h348365 = 8'd254; - default: _theResult___fst_exp__h348365 = 8'd0; + 3'd4: _theResult___fst_exp__h348056 = 8'd254; + default: _theResult___fst_exp__h348056 = 8'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_sfd__h348366 = 23'd0; + 3'd0, 3'd1: _theResult___fst_sfd__h348057 = 23'd0; 3'd2: - _theResult___fst_sfd__h348366 = + _theResult___fst_sfd__h348057 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 23'd8388607 : 23'd0; 3'd3: - _theResult___fst_sfd__h348366 = + _theResult___fst_sfd__h348057 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 23'd0 : 23'd8388607; - 3'd4: _theResult___fst_sfd__h348366 = 23'd8388607; - default: _theResult___fst_sfd__h348366 = 23'd0; + 3'd4: _theResult___fst_sfd__h348057 = 23'd8388607; + default: _theResult___fst_sfd__h348057 = 23'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h394064 = 8'd255; + 3'd0, 3'd1: _theResult___fst_exp__h393755 = 8'd255; 3'd2: - _theResult___fst_exp__h394064 = + _theResult___fst_exp__h393755 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 8'd254 : 8'd255; 3'd3: - _theResult___fst_exp__h394064 = + _theResult___fst_exp__h393755 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 8'd255 : 8'd254; - 3'd4: _theResult___fst_exp__h394064 = 8'd254; - default: _theResult___fst_exp__h394064 = 8'd0; + 3'd4: _theResult___fst_exp__h393755 = 8'd254; + default: _theResult___fst_exp__h393755 = 8'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_sfd__h394065 = 23'd0; + 3'd0, 3'd1: _theResult___fst_sfd__h393756 = 23'd0; 3'd2: - _theResult___fst_sfd__h394065 = + _theResult___fst_sfd__h393756 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 23'd8388607 : 23'd0; 3'd3: - _theResult___fst_sfd__h394065 = + _theResult___fst_sfd__h393756 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 23'd0 : 23'd8388607; - 3'd4: _theResult___fst_sfd__h394065 = 23'd8388607; - default: _theResult___fst_sfd__h394065 = 23'd0; + 3'd4: _theResult___fst_sfd__h393756 = 23'd8388607; + default: _theResult___fst_sfd__h393756 = 23'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h439759 = 8'd255; + 3'd0, 3'd1: _theResult___fst_exp__h439450 = 8'd255; 3'd2: - _theResult___fst_exp__h439759 = + _theResult___fst_exp__h439450 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 8'd254 : 8'd255; 3'd3: - _theResult___fst_exp__h439759 = + _theResult___fst_exp__h439450 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 8'd255 : 8'd254; - 3'd4: _theResult___fst_exp__h439759 = 8'd254; - default: _theResult___fst_exp__h439759 = 8'd0; + 3'd4: _theResult___fst_exp__h439450 = 8'd254; + default: _theResult___fst_exp__h439450 = 8'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_sfd__h439760 = 23'd0; + 3'd0, 3'd1: _theResult___fst_sfd__h439451 = 23'd0; 3'd2: - _theResult___fst_sfd__h439760 = + _theResult___fst_sfd__h439451 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 23'd8388607 : 23'd0; 3'd3: - _theResult___fst_sfd__h439760 = + _theResult___fst_sfd__h439451 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 23'd0 : 23'd8388607; - 3'd4: _theResult___fst_sfd__h439760 = 23'd8388607; - default: _theResult___fst_sfd__h439760 = 23'd0; + 3'd4: _theResult___fst_sfd__h439451 = 23'd8388607; + default: _theResult___fst_sfd__h439451 = 23'd0; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd1: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = 11'd2046; + 3'd1: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q7 = 11'd2046; 3'd2: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q7 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? 11'd2047 : 11'd2046; 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q7 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? 11'd2046 : 11'd2047; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = 11'd0; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q7 = 11'd0; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q8 = 52'hFFFFFFFFFFFFF; 3'd2: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q8 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? 52'd0 : 52'hFFFFFFFFFFFFF; 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q8 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? 52'hFFFFFFFFFFFFF : 52'd0; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17 = 52'd0; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q8 = 52'd0; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd1: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q18 = 11'd2046; + 3'd1: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q9 = 11'd2046; 3'd2: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q18 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q9 = (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? 11'd2047 : 11'd2046; 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q18 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q9 = (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? 11'd2046 : 11'd2047; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q18 = 11'd0; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd1: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q19 = 11'd2046; - 3'd2: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q19 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - 11'd2047 : - 11'd2046; - 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q19 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - 11'd2046 : - 11'd2047; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q19 = 11'd0; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q9 = 11'd0; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q20 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q10 = 52'hFFFFFFFFFFFFF; 3'd2: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q20 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q10 = + (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? + 52'd0 : + 52'hFFFFFFFFFFFFF; + 3'd3: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q10 = + (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? + 52'hFFFFFFFFFFFFF : + 52'd0; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q10 = 52'd0; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd1: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q11 = 11'd2046; + 3'd2: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q11 = + (coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? + 11'd2047 : + 11'd2046; + 3'd3: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q11 = + (coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? + 11'd2046 : + 11'd2047; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q11 = 11'd0; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd1: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q12 = + 52'hFFFFFFFFFFFFF; + 3'd2: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q12 = (coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? 52'd0 : 52'hFFFFFFFFFFFFF; 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q20 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q12 = (coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? 52'hFFFFFFFFFFFFF : 52'd0; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q20 = 52'd0; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q12 = 52'd0; endcase end always@(commitStage_commitTrap) @@ -32874,16 +32524,16 @@ module mkCore(CLK, 4'd11, 4'd12, 4'd13: - i__h707083 = commitStage_commitTrap[3:0]; - default: i__h707083 = 4'd15; + i__h705763 = commitStage_commitTrap[3:0]; + default: i__h705763 = 4'd15; endcase end always@(commitStage_commitTrap) begin case (commitStage_commitTrap[3:0]) 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: - i__h707243 = commitStage_commitTrap[3:0]; - default: i__h707243 = 4'd15; + i__h705923 = commitStage_commitTrap[3:0]; + default: i__h705923 = 4'd15; endcase end always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) @@ -32898,23 +32548,6 @@ module mkCore(CLK, endcase end always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) - begin - case (coreFix_memExe_lsq$firstLd[19:18]) - 2'd0: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1367 = - coreFix_memExe_respLrScAmoQ_data_0[15:0]; - 2'd1: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1367 = - coreFix_memExe_respLrScAmoQ_data_0[31:16]; - 2'd2: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1367 = - coreFix_memExe_respLrScAmoQ_data_0[47:32]; - 2'd3: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1367 = - coreFix_memExe_respLrScAmoQ_data_0[63:48]; - endcase - end - always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) begin case (coreFix_memExe_lsq$firstLd[19:17]) 3'd0: @@ -32943,6 +32576,34 @@ module mkCore(CLK, coreFix_memExe_respLrScAmoQ_data_0[63:56]; endcase end + always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) + begin + case (coreFix_memExe_lsq$firstLd[19:18]) + 2'd0: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1367 = + coreFix_memExe_respLrScAmoQ_data_0[15:0]; + 2'd1: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1367 = + coreFix_memExe_respLrScAmoQ_data_0[31:16]; + 2'd2: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1367 = + coreFix_memExe_respLrScAmoQ_data_0[47:32]; + 2'd3: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1367 = + coreFix_memExe_respLrScAmoQ_data_0[63:48]; + endcase + end + always@(coreFix_memExe_lsq$firstLd or mmio_dataRespQ_data_0) + begin + case (coreFix_memExe_lsq$firstLd[19]) + 1'd0: + SEL_ARR_mmio_dataRespQ_data_0_109_BITS_31_TO_0_ETC___d1408 = + mmio_dataRespQ_data_0[31:0]; + 1'd1: + SEL_ARR_mmio_dataRespQ_data_0_109_BITS_31_TO_0_ETC___d1408 = + mmio_dataRespQ_data_0[63:32]; + endcase + end always@(coreFix_memExe_lsq$firstLd or mmio_dataRespQ_data_0) begin case (coreFix_memExe_lsq$firstLd[19:18]) @@ -32961,17 +32622,6 @@ module mkCore(CLK, endcase end always@(coreFix_memExe_lsq$firstLd or mmio_dataRespQ_data_0) - begin - case (coreFix_memExe_lsq$firstLd[19]) - 1'd0: - SEL_ARR_mmio_dataRespQ_data_0_109_BITS_31_TO_0_ETC___d1408 = - mmio_dataRespQ_data_0[31:0]; - 1'd1: - SEL_ARR_mmio_dataRespQ_data_0_109_BITS_31_TO_0_ETC___d1408 = - mmio_dataRespQ_data_0[63:32]; - endcase - end - always@(coreFix_memExe_lsq$firstLd or mmio_dataRespQ_data_0) begin case (coreFix_memExe_lsq$firstLd[19:17]) 3'd0: @@ -33004,20 +32654,20 @@ module mkCore(CLK, begin case (coreFix_memExe_dTlb$procResp[105:103]) 3'd0, 3'd2: - CASE_coreFix_memExe_dTlbprocResp_BITS_105_TO__ETC__q21 = 4'd4; - default: CASE_coreFix_memExe_dTlbprocResp_BITS_105_TO__ETC__q21 = 4'd6; + CASE_coreFix_memExe_dTlbprocResp_BITS_105_TO__ETC__q13 = 4'd4; + default: CASE_coreFix_memExe_dTlbprocResp_BITS_105_TO__ETC__q13 = 4'd6; endcase end always@(coreFix_memExe_dTlb$procResp) begin case (coreFix_memExe_dTlb$procResp[109:106]) 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: - CASE_coreFix_memExe_dTlbprocResp_BITS_109_TO__ETC__q22 = + CASE_coreFix_memExe_dTlbprocResp_BITS_109_TO__ETC__q14 = coreFix_memExe_dTlb$procResp[109:106]; - 4'd11: CASE_coreFix_memExe_dTlbprocResp_BITS_109_TO__ETC__q22 = 4'd10; - 4'd12: CASE_coreFix_memExe_dTlbprocResp_BITS_109_TO__ETC__q22 = 4'd11; - 4'd13: CASE_coreFix_memExe_dTlbprocResp_BITS_109_TO__ETC__q22 = 4'd12; - default: CASE_coreFix_memExe_dTlbprocResp_BITS_109_TO__ETC__q22 = 4'd13; + 4'd11: CASE_coreFix_memExe_dTlbprocResp_BITS_109_TO__ETC__q14 = 4'd10; + 4'd12: CASE_coreFix_memExe_dTlbprocResp_BITS_109_TO__ETC__q14 = 4'd11; + 4'd13: CASE_coreFix_memExe_dTlbprocResp_BITS_109_TO__ETC__q14 = 4'd12; + default: CASE_coreFix_memExe_dTlbprocResp_BITS_109_TO__ETC__q14 = 4'd13; endcase end always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or @@ -33039,10 +32689,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q23 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q15 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[514:451]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q23 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q15 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[514:451]; endcase end @@ -33052,10 +32702,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q24 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q16 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[450:387]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q24 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q16 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[450:387]; endcase end @@ -33065,10 +32715,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q25 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q17 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[386:323]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q25 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q17 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[386:323]; endcase end @@ -33078,10 +32728,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q26 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q18 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[322:259]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q26 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q18 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[322:259]; endcase end @@ -33091,10 +32741,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q27 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q19 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[258:195]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q27 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q19 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[258:195]; endcase end @@ -33104,453 +32754,453 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q28 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q20 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[194:131]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q28 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q20 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[194:131]; endcase end - always@(guard__h357102 or - _theResult___fst_exp__h365150 or - out_exp__h365595 or _theResult___exp__h365592) + always@(guard__h356793 or + _theResult___fst_exp__h364841 or + out_exp__h365286 or _theResult___exp__h365283) begin - case (guard__h357102) + case (guard__h356793) 2'b0, 2'b01: - CASE_guard57102_0b0_theResult___fst_exp65150_0_ETC__q33 = - _theResult___fst_exp__h365150; + CASE_guard56793_0b0_theResult___fst_exp64841_0_ETC__q25 = + _theResult___fst_exp__h364841; 2'b10: - CASE_guard57102_0b0_theResult___fst_exp65150_0_ETC__q33 = - out_exp__h365595; + CASE_guard56793_0b0_theResult___fst_exp64841_0_ETC__q25 = + out_exp__h365286; 2'b11: - CASE_guard57102_0b0_theResult___fst_exp65150_0_ETC__q33 = - _theResult___exp__h365592; + CASE_guard56793_0b0_theResult___fst_exp64841_0_ETC__q25 = + _theResult___exp__h365283; endcase end - always@(guard__h357102 or - _theResult___fst_exp__h365150 or _theResult___exp__h365592) + always@(guard__h356793 or + _theResult___fst_exp__h364841 or _theResult___exp__h365283) begin - case (guard__h357102) + case (guard__h356793) 2'b0: - CASE_guard57102_0b0_theResult___fst_exp65150_0_ETC__q34 = - _theResult___fst_exp__h365150; + CASE_guard56793_0b0_theResult___fst_exp64841_0_ETC__q26 = + _theResult___fst_exp__h364841; 2'b01, 2'b10, 2'b11: - CASE_guard57102_0b0_theResult___fst_exp65150_0_ETC__q34 = - _theResult___exp__h365592; + CASE_guard56793_0b0_theResult___fst_exp64841_0_ETC__q26 = + _theResult___exp__h365283; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard57102_0b0_theResult___fst_exp65150_0_ETC__q33 or - CASE_guard57102_0b0_theResult___fst_exp65150_0_ETC__q34 or + CASE_guard56793_0b0_theResult___fst_exp64841_0_ETC__q25 or + CASE_guard56793_0b0_theResult___fst_exp64841_0_ETC__q26 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4628 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4630 or - _theResult___fst_exp__h365150) + _theResult___fst_exp__h364841) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h365670 = - CASE_guard57102_0b0_theResult___fst_exp65150_0_ETC__q33; + _theResult___fst_exp__h365361 = + CASE_guard56793_0b0_theResult___fst_exp64841_0_ETC__q25; 3'd1: - _theResult___fst_exp__h365670 = - CASE_guard57102_0b0_theResult___fst_exp65150_0_ETC__q34; + _theResult___fst_exp__h365361 = + CASE_guard56793_0b0_theResult___fst_exp64841_0_ETC__q26; 3'd2: - _theResult___fst_exp__h365670 = + _theResult___fst_exp__h365361 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4628; 3'd3: - _theResult___fst_exp__h365670 = + _theResult___fst_exp__h365361 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4630; - 3'd4: _theResult___fst_exp__h365670 = _theResult___fst_exp__h365150; - default: _theResult___fst_exp__h365670 = 8'd0; + 3'd4: _theResult___fst_exp__h365361 = _theResult___fst_exp__h364841; + default: _theResult___fst_exp__h365361 = 8'd0; endcase end - always@(guard__h348393 or - _theResult___fst_exp__h356494 or - out_exp__h357013 or _theResult___exp__h357010) + always@(guard__h348084 or + _theResult___fst_exp__h356185 or + out_exp__h356704 or _theResult___exp__h356701) begin - case (guard__h348393) + case (guard__h348084) 2'b0, 2'b01: - CASE_guard48393_0b0_theResult___fst_exp56494_0_ETC__q35 = - _theResult___fst_exp__h356494; + CASE_guard48084_0b0_theResult___fst_exp56185_0_ETC__q27 = + _theResult___fst_exp__h356185; 2'b10: - CASE_guard48393_0b0_theResult___fst_exp56494_0_ETC__q35 = - out_exp__h357013; + CASE_guard48084_0b0_theResult___fst_exp56185_0_ETC__q27 = + out_exp__h356704; 2'b11: - CASE_guard48393_0b0_theResult___fst_exp56494_0_ETC__q35 = - _theResult___exp__h357010; + CASE_guard48084_0b0_theResult___fst_exp56185_0_ETC__q27 = + _theResult___exp__h356701; endcase end - always@(guard__h348393 or - _theResult___fst_exp__h356494 or _theResult___exp__h357010) + always@(guard__h348084 or + _theResult___fst_exp__h356185 or _theResult___exp__h356701) begin - case (guard__h348393) + case (guard__h348084) 2'b0: - CASE_guard48393_0b0_theResult___fst_exp56494_0_ETC__q36 = - _theResult___fst_exp__h356494; + CASE_guard48084_0b0_theResult___fst_exp56185_0_ETC__q28 = + _theResult___fst_exp__h356185; 2'b01, 2'b10, 2'b11: - CASE_guard48393_0b0_theResult___fst_exp56494_0_ETC__q36 = - _theResult___exp__h357010; + CASE_guard48084_0b0_theResult___fst_exp56185_0_ETC__q28 = + _theResult___exp__h356701; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard48393_0b0_theResult___fst_exp56494_0_ETC__q35 or - CASE_guard48393_0b0_theResult___fst_exp56494_0_ETC__q36 or + CASE_guard48084_0b0_theResult___fst_exp56185_0_ETC__q27 or + CASE_guard48084_0b0_theResult___fst_exp56185_0_ETC__q28 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4406 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4409 or - _theResult___fst_exp__h356494) + _theResult___fst_exp__h356185) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h357088 = - CASE_guard48393_0b0_theResult___fst_exp56494_0_ETC__q35; + _theResult___fst_exp__h356779 = + CASE_guard48084_0b0_theResult___fst_exp56185_0_ETC__q27; 3'd1: - _theResult___fst_exp__h357088 = - CASE_guard48393_0b0_theResult___fst_exp56494_0_ETC__q36; + _theResult___fst_exp__h356779 = + CASE_guard48084_0b0_theResult___fst_exp56185_0_ETC__q28; 3'd2: - _theResult___fst_exp__h357088 = + _theResult___fst_exp__h356779 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4406; 3'd3: - _theResult___fst_exp__h357088 = + _theResult___fst_exp__h356779 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4409; - 3'd4: _theResult___fst_exp__h357088 = _theResult___fst_exp__h356494; - default: _theResult___fst_exp__h357088 = 8'd0; + 3'd4: _theResult___fst_exp__h356779 = _theResult___fst_exp__h356185; + default: _theResult___fst_exp__h356779 = 8'd0; endcase end - always@(guard__h366032 or - _theResult___fst_exp__h374260 or - out_exp__h374779 or _theResult___exp__h374776) + always@(guard__h365723 or + _theResult___fst_exp__h373951 or + out_exp__h374470 or _theResult___exp__h374467) begin - case (guard__h366032) + case (guard__h365723) 2'b0, 2'b01: - CASE_guard66032_0b0_theResult___fst_exp74260_0_ETC__q41 = - _theResult___fst_exp__h374260; + CASE_guard65723_0b0_theResult___fst_exp73951_0_ETC__q33 = + _theResult___fst_exp__h373951; 2'b10: - CASE_guard66032_0b0_theResult___fst_exp74260_0_ETC__q41 = - out_exp__h374779; + CASE_guard65723_0b0_theResult___fst_exp73951_0_ETC__q33 = + out_exp__h374470; 2'b11: - CASE_guard66032_0b0_theResult___fst_exp74260_0_ETC__q41 = - _theResult___exp__h374776; + CASE_guard65723_0b0_theResult___fst_exp73951_0_ETC__q33 = + _theResult___exp__h374467; endcase end - always@(guard__h366032 or - _theResult___fst_exp__h374260 or _theResult___exp__h374776) + always@(guard__h365723 or + _theResult___fst_exp__h373951 or _theResult___exp__h374467) begin - case (guard__h366032) + case (guard__h365723) 2'b0: - CASE_guard66032_0b0_theResult___fst_exp74260_0_ETC__q42 = - _theResult___fst_exp__h374260; + CASE_guard65723_0b0_theResult___fst_exp73951_0_ETC__q34 = + _theResult___fst_exp__h373951; 2'b01, 2'b10, 2'b11: - CASE_guard66032_0b0_theResult___fst_exp74260_0_ETC__q42 = - _theResult___exp__h374776; + CASE_guard65723_0b0_theResult___fst_exp73951_0_ETC__q34 = + _theResult___exp__h374467; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard66032_0b0_theResult___fst_exp74260_0_ETC__q41 or - CASE_guard66032_0b0_theResult___fst_exp74260_0_ETC__q42 or + CASE_guard65723_0b0_theResult___fst_exp73951_0_ETC__q33 or + CASE_guard65723_0b0_theResult___fst_exp73951_0_ETC__q34 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4953 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4955 or - _theResult___fst_exp__h374260) + _theResult___fst_exp__h373951) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h374854 = - CASE_guard66032_0b0_theResult___fst_exp74260_0_ETC__q41; + _theResult___fst_exp__h374545 = + CASE_guard65723_0b0_theResult___fst_exp73951_0_ETC__q33; 3'd1: - _theResult___fst_exp__h374854 = - CASE_guard66032_0b0_theResult___fst_exp74260_0_ETC__q42; + _theResult___fst_exp__h374545 = + CASE_guard65723_0b0_theResult___fst_exp73951_0_ETC__q34; 3'd2: - _theResult___fst_exp__h374854 = + _theResult___fst_exp__h374545 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4953; 3'd3: - _theResult___fst_exp__h374854 = + _theResult___fst_exp__h374545 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4955; - 3'd4: _theResult___fst_exp__h374854 = _theResult___fst_exp__h374260; - default: _theResult___fst_exp__h374854 = 8'd0; + 3'd4: _theResult___fst_exp__h374545 = _theResult___fst_exp__h373951; + default: _theResult___fst_exp__h374545 = 8'd0; endcase end - always@(guard__h374868 or - _theResult___fst_exp__h382945 or - out_exp__h383415 or _theResult___exp__h383412) + always@(guard__h374559 or + _theResult___fst_exp__h382636 or + out_exp__h383106 or _theResult___exp__h383103) begin - case (guard__h374868) + case (guard__h374559) 2'b0, 2'b01: - CASE_guard74868_0b0_theResult___fst_exp82945_0_ETC__q46 = - _theResult___fst_exp__h382945; + CASE_guard74559_0b0_theResult___fst_exp82636_0_ETC__q38 = + _theResult___fst_exp__h382636; 2'b10: - CASE_guard74868_0b0_theResult___fst_exp82945_0_ETC__q46 = - out_exp__h383415; + CASE_guard74559_0b0_theResult___fst_exp82636_0_ETC__q38 = + out_exp__h383106; 2'b11: - CASE_guard74868_0b0_theResult___fst_exp82945_0_ETC__q46 = - _theResult___exp__h383412; + CASE_guard74559_0b0_theResult___fst_exp82636_0_ETC__q38 = + _theResult___exp__h383103; endcase end - always@(guard__h374868 or - _theResult___fst_exp__h382945 or _theResult___exp__h383412) + always@(guard__h374559 or + _theResult___fst_exp__h382636 or _theResult___exp__h383103) begin - case (guard__h374868) + case (guard__h374559) 2'b0: - CASE_guard74868_0b0_theResult___fst_exp82945_0_ETC__q47 = - _theResult___fst_exp__h382945; + CASE_guard74559_0b0_theResult___fst_exp82636_0_ETC__q39 = + _theResult___fst_exp__h382636; 2'b01, 2'b10, 2'b11: - CASE_guard74868_0b0_theResult___fst_exp82945_0_ETC__q47 = - _theResult___exp__h383412; + CASE_guard74559_0b0_theResult___fst_exp82636_0_ETC__q39 = + _theResult___exp__h383103; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard74868_0b0_theResult___fst_exp82945_0_ETC__q46 or - CASE_guard74868_0b0_theResult___fst_exp82945_0_ETC__q47 or + CASE_guard74559_0b0_theResult___fst_exp82636_0_ETC__q38 or + CASE_guard74559_0b0_theResult___fst_exp82636_0_ETC__q39 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5022 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5024 or - _theResult___fst_exp__h382945) + _theResult___fst_exp__h382636) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h383490 = - CASE_guard74868_0b0_theResult___fst_exp82945_0_ETC__q46; + _theResult___fst_exp__h383181 = + CASE_guard74559_0b0_theResult___fst_exp82636_0_ETC__q38; 3'd1: - _theResult___fst_exp__h383490 = - CASE_guard74868_0b0_theResult___fst_exp82945_0_ETC__q47; + _theResult___fst_exp__h383181 = + CASE_guard74559_0b0_theResult___fst_exp82636_0_ETC__q39; 3'd2: - _theResult___fst_exp__h383490 = + _theResult___fst_exp__h383181 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5022; 3'd3: - _theResult___fst_exp__h383490 = + _theResult___fst_exp__h383181 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5024; - 3'd4: _theResult___fst_exp__h383490 = _theResult___fst_exp__h382945; - default: _theResult___fst_exp__h383490 = 8'd0; + 3'd4: _theResult___fst_exp__h383181 = _theResult___fst_exp__h382636; + default: _theResult___fst_exp__h383181 = 8'd0; endcase end - always@(guard__h357102 or - _theResult___snd__h365101 or - out_sfd__h365596 or _theResult___sfd__h365593) + always@(guard__h348084 or + sfdin__h356179 or out_sfd__h356705 or _theResult___sfd__h356702) begin - case (guard__h357102) + case (guard__h348084) 2'b0, 2'b01: - CASE_guard57102_0b0_theResult___snd65101_BITS__ETC__q48 = - _theResult___snd__h365101[56:34]; + CASE_guard48084_0b0_sfdin56179_BITS_56_TO_34_0_ETC__q40 = + sfdin__h356179[56:34]; 2'b10: - CASE_guard57102_0b0_theResult___snd65101_BITS__ETC__q48 = - out_sfd__h365596; + CASE_guard48084_0b0_sfdin56179_BITS_56_TO_34_0_ETC__q40 = + out_sfd__h356705; 2'b11: - CASE_guard57102_0b0_theResult___snd65101_BITS__ETC__q48 = - _theResult___sfd__h365593; + CASE_guard48084_0b0_sfdin56179_BITS_56_TO_34_0_ETC__q40 = + _theResult___sfd__h356702; endcase end - always@(guard__h357102 or - _theResult___snd__h365101 or _theResult___sfd__h365593) + always@(guard__h348084 or sfdin__h356179 or _theResult___sfd__h356702) begin - case (guard__h357102) + case (guard__h348084) 2'b0: - CASE_guard57102_0b0_theResult___snd65101_BITS__ETC__q49 = - _theResult___snd__h365101[56:34]; + CASE_guard48084_0b0_sfdin56179_BITS_56_TO_34_0_ETC__q41 = + sfdin__h356179[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard57102_0b0_theResult___snd65101_BITS__ETC__q49 = - _theResult___sfd__h365593; + CASE_guard48084_0b0_sfdin56179_BITS_56_TO_34_0_ETC__q41 = + _theResult___sfd__h356702; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard57102_0b0_theResult___snd65101_BITS__ETC__q48 or - CASE_guard57102_0b0_theResult___snd65101_BITS__ETC__q49 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5072 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5074 or - _theResult___snd__h365101) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0: - _theResult___fst_sfd__h365671 = - CASE_guard57102_0b0_theResult___snd65101_BITS__ETC__q48; - 3'd1: - _theResult___fst_sfd__h365671 = - CASE_guard57102_0b0_theResult___snd65101_BITS__ETC__q49; - 3'd2: - _theResult___fst_sfd__h365671 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5072; - 3'd3: - _theResult___fst_sfd__h365671 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5074; - 3'd4: _theResult___fst_sfd__h365671 = _theResult___snd__h365101[56:34]; - default: _theResult___fst_sfd__h365671 = 23'd0; - endcase - end - always@(guard__h348393 or - sfdin__h356488 or out_sfd__h357014 or _theResult___sfd__h357011) - begin - case (guard__h348393) - 2'b0, 2'b01: - CASE_guard48393_0b0_sfdin56488_BITS_56_TO_34_0_ETC__q50 = - sfdin__h356488[56:34]; - 2'b10: - CASE_guard48393_0b0_sfdin56488_BITS_56_TO_34_0_ETC__q50 = - out_sfd__h357014; - 2'b11: - CASE_guard48393_0b0_sfdin56488_BITS_56_TO_34_0_ETC__q50 = - _theResult___sfd__h357011; - endcase - end - always@(guard__h348393 or sfdin__h356488 or _theResult___sfd__h357011) - begin - case (guard__h348393) - 2'b0: - CASE_guard48393_0b0_sfdin56488_BITS_56_TO_34_0_ETC__q51 = - sfdin__h356488[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard48393_0b0_sfdin56488_BITS_56_TO_34_0_ETC__q51 = - _theResult___sfd__h357011; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard48393_0b0_sfdin56488_BITS_56_TO_34_0_ETC__q50 or - CASE_guard48393_0b0_sfdin56488_BITS_56_TO_34_0_ETC__q51 or + CASE_guard48084_0b0_sfdin56179_BITS_56_TO_34_0_ETC__q40 or + CASE_guard48084_0b0_sfdin56179_BITS_56_TO_34_0_ETC__q41 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5053 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5055 or - sfdin__h356488) + sfdin__h356179) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h357089 = - CASE_guard48393_0b0_sfdin56488_BITS_56_TO_34_0_ETC__q50; + _theResult___fst_sfd__h356780 = + CASE_guard48084_0b0_sfdin56179_BITS_56_TO_34_0_ETC__q40; 3'd1: - _theResult___fst_sfd__h357089 = - CASE_guard48393_0b0_sfdin56488_BITS_56_TO_34_0_ETC__q51; + _theResult___fst_sfd__h356780 = + CASE_guard48084_0b0_sfdin56179_BITS_56_TO_34_0_ETC__q41; 3'd2: - _theResult___fst_sfd__h357089 = + _theResult___fst_sfd__h356780 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5053; 3'd3: - _theResult___fst_sfd__h357089 = + _theResult___fst_sfd__h356780 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5055; - 3'd4: _theResult___fst_sfd__h357089 = sfdin__h356488[56:34]; - default: _theResult___fst_sfd__h357089 = 23'd0; + 3'd4: _theResult___fst_sfd__h356780 = sfdin__h356179[56:34]; + default: _theResult___fst_sfd__h356780 = 23'd0; endcase end - always@(guard__h366032 or - sfdin__h374254 or out_sfd__h374780 or _theResult___sfd__h374777) + always@(guard__h356793 or + _theResult___snd__h364792 or + out_sfd__h365287 or _theResult___sfd__h365284) begin - case (guard__h366032) + case (guard__h356793) 2'b0, 2'b01: - CASE_guard66032_0b0_sfdin74254_BITS_56_TO_34_0_ETC__q52 = - sfdin__h374254[56:34]; + CASE_guard56793_0b0_theResult___snd64792_BITS__ETC__q42 = + _theResult___snd__h364792[56:34]; 2'b10: - CASE_guard66032_0b0_sfdin74254_BITS_56_TO_34_0_ETC__q52 = - out_sfd__h374780; + CASE_guard56793_0b0_theResult___snd64792_BITS__ETC__q42 = + out_sfd__h365287; 2'b11: - CASE_guard66032_0b0_sfdin74254_BITS_56_TO_34_0_ETC__q52 = - _theResult___sfd__h374777; + CASE_guard56793_0b0_theResult___snd64792_BITS__ETC__q42 = + _theResult___sfd__h365284; endcase end - always@(guard__h366032 or sfdin__h374254 or _theResult___sfd__h374777) + always@(guard__h356793 or + _theResult___snd__h364792 or _theResult___sfd__h365284) begin - case (guard__h366032) + case (guard__h356793) 2'b0: - CASE_guard66032_0b0_sfdin74254_BITS_56_TO_34_0_ETC__q53 = - sfdin__h374254[56:34]; + CASE_guard56793_0b0_theResult___snd64792_BITS__ETC__q43 = + _theResult___snd__h364792[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard66032_0b0_sfdin74254_BITS_56_TO_34_0_ETC__q53 = - _theResult___sfd__h374777; + CASE_guard56793_0b0_theResult___snd64792_BITS__ETC__q43 = + _theResult___sfd__h365284; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard66032_0b0_sfdin74254_BITS_56_TO_34_0_ETC__q52 or - CASE_guard66032_0b0_sfdin74254_BITS_56_TO_34_0_ETC__q53 or + CASE_guard56793_0b0_theResult___snd64792_BITS__ETC__q42 or + CASE_guard56793_0b0_theResult___snd64792_BITS__ETC__q43 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5072 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5074 or + _theResult___snd__h364792) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) + 3'd0: + _theResult___fst_sfd__h365362 = + CASE_guard56793_0b0_theResult___snd64792_BITS__ETC__q42; + 3'd1: + _theResult___fst_sfd__h365362 = + CASE_guard56793_0b0_theResult___snd64792_BITS__ETC__q43; + 3'd2: + _theResult___fst_sfd__h365362 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5072; + 3'd3: + _theResult___fst_sfd__h365362 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5074; + 3'd4: _theResult___fst_sfd__h365362 = _theResult___snd__h364792[56:34]; + default: _theResult___fst_sfd__h365362 = 23'd0; + endcase + end + always@(guard__h365723 or + sfdin__h373945 or out_sfd__h374471 or _theResult___sfd__h374468) + begin + case (guard__h365723) + 2'b0, 2'b01: + CASE_guard65723_0b0_sfdin73945_BITS_56_TO_34_0_ETC__q44 = + sfdin__h373945[56:34]; + 2'b10: + CASE_guard65723_0b0_sfdin73945_BITS_56_TO_34_0_ETC__q44 = + out_sfd__h374471; + 2'b11: + CASE_guard65723_0b0_sfdin73945_BITS_56_TO_34_0_ETC__q44 = + _theResult___sfd__h374468; + endcase + end + always@(guard__h365723 or sfdin__h373945 or _theResult___sfd__h374468) + begin + case (guard__h365723) + 2'b0: + CASE_guard65723_0b0_sfdin73945_BITS_56_TO_34_0_ETC__q45 = + sfdin__h373945[56:34]; + 2'b01, 2'b10, 2'b11: + CASE_guard65723_0b0_sfdin73945_BITS_56_TO_34_0_ETC__q45 = + _theResult___sfd__h374468; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or + CASE_guard65723_0b0_sfdin73945_BITS_56_TO_34_0_ETC__q44 or + CASE_guard65723_0b0_sfdin73945_BITS_56_TO_34_0_ETC__q45 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5099 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5101 or - sfdin__h374254) + sfdin__h373945) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h374855 = - CASE_guard66032_0b0_sfdin74254_BITS_56_TO_34_0_ETC__q52; + _theResult___fst_sfd__h374546 = + CASE_guard65723_0b0_sfdin73945_BITS_56_TO_34_0_ETC__q44; 3'd1: - _theResult___fst_sfd__h374855 = - CASE_guard66032_0b0_sfdin74254_BITS_56_TO_34_0_ETC__q53; + _theResult___fst_sfd__h374546 = + CASE_guard65723_0b0_sfdin73945_BITS_56_TO_34_0_ETC__q45; 3'd2: - _theResult___fst_sfd__h374855 = + _theResult___fst_sfd__h374546 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5099; 3'd3: - _theResult___fst_sfd__h374855 = + _theResult___fst_sfd__h374546 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5101; - 3'd4: _theResult___fst_sfd__h374855 = sfdin__h374254[56:34]; - default: _theResult___fst_sfd__h374855 = 23'd0; + 3'd4: _theResult___fst_sfd__h374546 = sfdin__h373945[56:34]; + default: _theResult___fst_sfd__h374546 = 23'd0; endcase end - always@(guard__h374868 or - _theResult___snd__h382891 or - out_sfd__h383416 or _theResult___sfd__h383413) + always@(guard__h374559 or + _theResult___snd__h382582 or + out_sfd__h383107 or _theResult___sfd__h383104) begin - case (guard__h374868) + case (guard__h374559) 2'b0, 2'b01: - CASE_guard74868_0b0_theResult___snd82891_BITS__ETC__q54 = - _theResult___snd__h382891[56:34]; + CASE_guard74559_0b0_theResult___snd82582_BITS__ETC__q46 = + _theResult___snd__h382582[56:34]; 2'b10: - CASE_guard74868_0b0_theResult___snd82891_BITS__ETC__q54 = - out_sfd__h383416; + CASE_guard74559_0b0_theResult___snd82582_BITS__ETC__q46 = + out_sfd__h383107; 2'b11: - CASE_guard74868_0b0_theResult___snd82891_BITS__ETC__q54 = - _theResult___sfd__h383413; + CASE_guard74559_0b0_theResult___snd82582_BITS__ETC__q46 = + _theResult___sfd__h383104; endcase end - always@(guard__h374868 or - _theResult___snd__h382891 or _theResult___sfd__h383413) + always@(guard__h374559 or + _theResult___snd__h382582 or _theResult___sfd__h383104) begin - case (guard__h374868) + case (guard__h374559) 2'b0: - CASE_guard74868_0b0_theResult___snd82891_BITS__ETC__q55 = - _theResult___snd__h382891[56:34]; + CASE_guard74559_0b0_theResult___snd82582_BITS__ETC__q47 = + _theResult___snd__h382582[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard74868_0b0_theResult___snd82891_BITS__ETC__q55 = - _theResult___sfd__h383413; + CASE_guard74559_0b0_theResult___snd82582_BITS__ETC__q47 = + _theResult___sfd__h383104; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard74868_0b0_theResult___snd82891_BITS__ETC__q54 or - CASE_guard74868_0b0_theResult___snd82891_BITS__ETC__q55 or + CASE_guard74559_0b0_theResult___snd82582_BITS__ETC__q46 or + CASE_guard74559_0b0_theResult___snd82582_BITS__ETC__q47 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5118 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5120 or - _theResult___snd__h382891) + _theResult___snd__h382582) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h383491 = - CASE_guard74868_0b0_theResult___snd82891_BITS__ETC__q54; + _theResult___fst_sfd__h383182 = + CASE_guard74559_0b0_theResult___snd82582_BITS__ETC__q46; 3'd1: - _theResult___fst_sfd__h383491 = - CASE_guard74868_0b0_theResult___snd82891_BITS__ETC__q55; + _theResult___fst_sfd__h383182 = + CASE_guard74559_0b0_theResult___snd82582_BITS__ETC__q47; 3'd2: - _theResult___fst_sfd__h383491 = + _theResult___fst_sfd__h383182 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5118; 3'd3: - _theResult___fst_sfd__h383491 = + _theResult___fst_sfd__h383182 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5120; - 3'd4: _theResult___fst_sfd__h383491 = _theResult___snd__h382891[56:34]; - default: _theResult___fst_sfd__h383491 = 23'd0; + 3'd4: _theResult___fst_sfd__h383182 = _theResult___snd__h382582[56:34]; + default: _theResult___fst_sfd__h383182 = 23'd0; endcase end - always@(guard__h348393 or + always@(guard__h348084 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h348393) + case (guard__h348084) 2'b0, 2'b01, 2'b10: - CASE_guard48393_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q56 = + CASE_guard48084_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard48393_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q56 = - guard__h348393 == 2'b11 && + CASE_guard48084_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48 = + guard__h348084 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard48393_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q56 or - guard__h348393) + CASE_guard48084_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48 or + guard__h348084) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5206 = - CASE_guard48393_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q56; + CASE_guard48084_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5206 = - (guard__h348393 == 2'b0) ? + (guard__h348084 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h348393 == 2'b01 || guard__h348393 == 2'b10 || - guard__h348393 == 2'b11) && + (guard__h348084 == 2'b01 || guard__h348084 == 2'b10 || + guard__h348084 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5206 = @@ -33561,34 +33211,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h348393 or + always@(guard__h348084 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h348393) + case (guard__h348084) 2'b0, 2'b01, 2'b10: - CASE_guard48393_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q57 = + CASE_guard48084_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard48393_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q57 = - guard__h348393 != 2'b11 || + CASE_guard48084_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49 = + guard__h348084 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard48393_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q57 or - guard__h348393) + CASE_guard48084_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49 or + guard__h348084) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5150 = - CASE_guard48393_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q57; + CASE_guard48084_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5150 = - (guard__h348393 == 2'b0) ? + (guard__h348084 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h348393 != 2'b01 && guard__h348393 != 2'b10 && - guard__h348393 != 2'b11 || + guard__h348084 != 2'b01 && guard__h348084 != 2'b10 && + guard__h348084 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5150 = @@ -33599,34 +33249,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h357102 or + always@(guard__h356793 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h357102) + case (guard__h356793) 2'b0, 2'b01, 2'b10: - CASE_guard57102_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q58 = + CASE_guard56793_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q50 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard57102_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q58 = - guard__h357102 == 2'b11 && + CASE_guard56793_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q50 = + guard__h356793 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard57102_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q58 or - guard__h357102) + CASE_guard56793_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q50 or + guard__h356793) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5213 = - CASE_guard57102_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q58; + CASE_guard56793_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q50; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5213 = - (guard__h357102 == 2'b0) ? + (guard__h356793 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h357102 == 2'b01 || guard__h357102 == 2'b10 || - guard__h357102 == 2'b11) && + (guard__h356793 == 2'b01 || guard__h356793 == 2'b10 || + guard__h356793 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5213 = @@ -33637,34 +33287,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h357102 or + always@(guard__h356793 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h357102) + case (guard__h356793) 2'b0, 2'b01, 2'b10: - CASE_guard57102_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q59 = + CASE_guard56793_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q51 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard57102_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q59 = - guard__h357102 != 2'b11 || + CASE_guard56793_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q51 = + guard__h356793 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard57102_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q59 or - guard__h357102) + CASE_guard56793_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q51 or + guard__h356793) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5163 = - CASE_guard57102_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q59; + CASE_guard56793_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q51; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5163 = - (guard__h357102 == 2'b0) ? + (guard__h356793 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h357102 != 2'b01 && guard__h357102 != 2'b10 && - guard__h357102 != 2'b11 || + guard__h356793 != 2'b01 && guard__h356793 != 2'b10 && + guard__h356793 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5163 = @@ -33675,34 +33325,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h366032 or + always@(guard__h365723 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h366032) + case (guard__h365723) 2'b0, 2'b01, 2'b10: - CASE_guard66032_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q60 = + CASE_guard65723_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard66032_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q60 = - guard__h366032 == 2'b11 && + CASE_guard65723_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52 = + guard__h365723 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard66032_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q60 or - guard__h366032) + CASE_guard65723_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52 or + guard__h365723) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5223 = - CASE_guard66032_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q60; + CASE_guard65723_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5223 = - (guard__h366032 == 2'b0) ? + (guard__h365723 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h366032 == 2'b01 || guard__h366032 == 2'b10 || - guard__h366032 == 2'b11) && + (guard__h365723 == 2'b01 || guard__h365723 == 2'b10 || + guard__h365723 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5223 = @@ -33713,34 +33363,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h366032 or + always@(guard__h365723 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h366032) + case (guard__h365723) 2'b0, 2'b01, 2'b10: - CASE_guard66032_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q61 = + CASE_guard65723_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard66032_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q61 = - guard__h366032 != 2'b11 || + CASE_guard65723_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53 = + guard__h365723 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard66032_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q61 or - guard__h366032) + CASE_guard65723_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53 or + guard__h365723) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5180 = - CASE_guard66032_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q61; + CASE_guard65723_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5180 = - (guard__h366032 == 2'b0) ? + (guard__h365723 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h366032 != 2'b01 && guard__h366032 != 2'b10 && - guard__h366032 != 2'b11 || + guard__h365723 != 2'b01 && guard__h365723 != 2'b10 && + guard__h365723 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5180 = @@ -33751,34 +33401,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h374868 or + always@(guard__h374559 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h374868) + case (guard__h374559) 2'b0, 2'b01, 2'b10: - CASE_guard74868_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q62 = + CASE_guard74559_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q54 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard74868_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q62 = - guard__h374868 == 2'b11 && + CASE_guard74559_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q54 = + guard__h374559 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard74868_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q62 or - guard__h374868) + CASE_guard74559_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q54 or + guard__h374559) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5230 = - CASE_guard74868_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q62; + CASE_guard74559_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q54; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5230 = - (guard__h374868 == 2'b0) ? + (guard__h374559 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h374868 == 2'b01 || guard__h374868 == 2'b10 || - guard__h374868 == 2'b11) && + (guard__h374559 == 2'b01 || guard__h374559 == 2'b10 || + guard__h374559 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5230 = @@ -33789,34 +33439,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h374868 or + always@(guard__h374559 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h374868) + case (guard__h374559) 2'b0, 2'b01, 2'b10: - CASE_guard74868_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q63 = + CASE_guard74559_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q55 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard74868_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q63 = - guard__h374868 != 2'b11 || + CASE_guard74559_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q55 = + guard__h374559 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard74868_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q63 or - guard__h374868) + CASE_guard74559_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q55 or + guard__h374559) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5193 = - CASE_guard74868_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q63; + CASE_guard74559_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q55; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5193 = - (guard__h374868 == 2'b0) ? + (guard__h374559 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h374868 != 2'b01 && guard__h374868 != 2'b10 && - guard__h374868 != 2'b11 || + guard__h374559 != 2'b01 && guard__h374559 != 2'b10 && + guard__h374559 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5193 = @@ -33853,446 +33503,446 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h402799 or - _theResult___fst_exp__h410847 or - out_exp__h411292 or _theResult___exp__h411289) + always@(guard__h402490 or + _theResult___fst_exp__h410538 or + out_exp__h410983 or _theResult___exp__h410980) begin - case (guard__h402799) + case (guard__h402490) 2'b0, 2'b01: - CASE_guard02799_0b0_theResult___fst_exp10847_0_ETC__q68 = - _theResult___fst_exp__h410847; + CASE_guard02490_0b0_theResult___fst_exp10538_0_ETC__q60 = + _theResult___fst_exp__h410538; 2'b10: - CASE_guard02799_0b0_theResult___fst_exp10847_0_ETC__q68 = - out_exp__h411292; + CASE_guard02490_0b0_theResult___fst_exp10538_0_ETC__q60 = + out_exp__h410983; 2'b11: - CASE_guard02799_0b0_theResult___fst_exp10847_0_ETC__q68 = - _theResult___exp__h411289; + CASE_guard02490_0b0_theResult___fst_exp10538_0_ETC__q60 = + _theResult___exp__h410980; endcase end - always@(guard__h402799 or - _theResult___fst_exp__h410847 or _theResult___exp__h411289) + always@(guard__h402490 or + _theResult___fst_exp__h410538 or _theResult___exp__h410980) begin - case (guard__h402799) + case (guard__h402490) 2'b0: - CASE_guard02799_0b0_theResult___fst_exp10847_0_ETC__q69 = - _theResult___fst_exp__h410847; + CASE_guard02490_0b0_theResult___fst_exp10538_0_ETC__q61 = + _theResult___fst_exp__h410538; 2'b01, 2'b10, 2'b11: - CASE_guard02799_0b0_theResult___fst_exp10847_0_ETC__q69 = - _theResult___exp__h411289; + CASE_guard02490_0b0_theResult___fst_exp10538_0_ETC__q61 = + _theResult___exp__h410980; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard02799_0b0_theResult___fst_exp10847_0_ETC__q68 or - CASE_guard02799_0b0_theResult___fst_exp10847_0_ETC__q69 or + CASE_guard02490_0b0_theResult___fst_exp10538_0_ETC__q60 or + CASE_guard02490_0b0_theResult___fst_exp10538_0_ETC__q61 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6020 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6022 or - _theResult___fst_exp__h410847) + _theResult___fst_exp__h410538) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h411367 = - CASE_guard02799_0b0_theResult___fst_exp10847_0_ETC__q68; + _theResult___fst_exp__h411058 = + CASE_guard02490_0b0_theResult___fst_exp10538_0_ETC__q60; 3'd1: - _theResult___fst_exp__h411367 = - CASE_guard02799_0b0_theResult___fst_exp10847_0_ETC__q69; + _theResult___fst_exp__h411058 = + CASE_guard02490_0b0_theResult___fst_exp10538_0_ETC__q61; 3'd2: - _theResult___fst_exp__h411367 = + _theResult___fst_exp__h411058 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6020; 3'd3: - _theResult___fst_exp__h411367 = + _theResult___fst_exp__h411058 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6022; - 3'd4: _theResult___fst_exp__h411367 = _theResult___fst_exp__h410847; - default: _theResult___fst_exp__h411367 = 8'd0; + 3'd4: _theResult___fst_exp__h411058 = _theResult___fst_exp__h410538; + default: _theResult___fst_exp__h411058 = 8'd0; endcase end - always@(guard__h394092 or - _theResult___fst_exp__h402191 or - out_exp__h402710 or _theResult___exp__h402707) + always@(guard__h393783 or + _theResult___fst_exp__h401882 or + out_exp__h402401 or _theResult___exp__h402398) begin - case (guard__h394092) + case (guard__h393783) 2'b0, 2'b01: - CASE_guard94092_0b0_theResult___fst_exp02191_0_ETC__q70 = - _theResult___fst_exp__h402191; + CASE_guard93783_0b0_theResult___fst_exp01882_0_ETC__q62 = + _theResult___fst_exp__h401882; 2'b10: - CASE_guard94092_0b0_theResult___fst_exp02191_0_ETC__q70 = - out_exp__h402710; + CASE_guard93783_0b0_theResult___fst_exp01882_0_ETC__q62 = + out_exp__h402401; 2'b11: - CASE_guard94092_0b0_theResult___fst_exp02191_0_ETC__q70 = - _theResult___exp__h402707; + CASE_guard93783_0b0_theResult___fst_exp01882_0_ETC__q62 = + _theResult___exp__h402398; endcase end - always@(guard__h394092 or - _theResult___fst_exp__h402191 or _theResult___exp__h402707) + always@(guard__h393783 or + _theResult___fst_exp__h401882 or _theResult___exp__h402398) begin - case (guard__h394092) + case (guard__h393783) 2'b0: - CASE_guard94092_0b0_theResult___fst_exp02191_0_ETC__q71 = - _theResult___fst_exp__h402191; + CASE_guard93783_0b0_theResult___fst_exp01882_0_ETC__q63 = + _theResult___fst_exp__h401882; 2'b01, 2'b10, 2'b11: - CASE_guard94092_0b0_theResult___fst_exp02191_0_ETC__q71 = - _theResult___exp__h402707; + CASE_guard93783_0b0_theResult___fst_exp01882_0_ETC__q63 = + _theResult___exp__h402398; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard94092_0b0_theResult___fst_exp02191_0_ETC__q70 or - CASE_guard94092_0b0_theResult___fst_exp02191_0_ETC__q71 or + CASE_guard93783_0b0_theResult___fst_exp01882_0_ETC__q62 or + CASE_guard93783_0b0_theResult___fst_exp01882_0_ETC__q63 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5798 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5801 or - _theResult___fst_exp__h402191) + _theResult___fst_exp__h401882) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h402785 = - CASE_guard94092_0b0_theResult___fst_exp02191_0_ETC__q70; + _theResult___fst_exp__h402476 = + CASE_guard93783_0b0_theResult___fst_exp01882_0_ETC__q62; 3'd1: - _theResult___fst_exp__h402785 = - CASE_guard94092_0b0_theResult___fst_exp02191_0_ETC__q71; + _theResult___fst_exp__h402476 = + CASE_guard93783_0b0_theResult___fst_exp01882_0_ETC__q63; 3'd2: - _theResult___fst_exp__h402785 = + _theResult___fst_exp__h402476 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5798; 3'd3: - _theResult___fst_exp__h402785 = + _theResult___fst_exp__h402476 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5801; - 3'd4: _theResult___fst_exp__h402785 = _theResult___fst_exp__h402191; - default: _theResult___fst_exp__h402785 = 8'd0; + 3'd4: _theResult___fst_exp__h402476 = _theResult___fst_exp__h401882; + default: _theResult___fst_exp__h402476 = 8'd0; endcase end - always@(guard__h411729 or - _theResult___fst_exp__h419957 or - out_exp__h420476 or _theResult___exp__h420473) + always@(guard__h411420 or + _theResult___fst_exp__h419648 or + out_exp__h420167 or _theResult___exp__h420164) begin - case (guard__h411729) + case (guard__h411420) 2'b0, 2'b01: - CASE_guard11729_0b0_theResult___fst_exp19957_0_ETC__q76 = - _theResult___fst_exp__h419957; + CASE_guard11420_0b0_theResult___fst_exp19648_0_ETC__q68 = + _theResult___fst_exp__h419648; 2'b10: - CASE_guard11729_0b0_theResult___fst_exp19957_0_ETC__q76 = - out_exp__h420476; + CASE_guard11420_0b0_theResult___fst_exp19648_0_ETC__q68 = + out_exp__h420167; 2'b11: - CASE_guard11729_0b0_theResult___fst_exp19957_0_ETC__q76 = - _theResult___exp__h420473; + CASE_guard11420_0b0_theResult___fst_exp19648_0_ETC__q68 = + _theResult___exp__h420164; endcase end - always@(guard__h411729 or - _theResult___fst_exp__h419957 or _theResult___exp__h420473) + always@(guard__h411420 or + _theResult___fst_exp__h419648 or _theResult___exp__h420164) begin - case (guard__h411729) + case (guard__h411420) 2'b0: - CASE_guard11729_0b0_theResult___fst_exp19957_0_ETC__q77 = - _theResult___fst_exp__h419957; + CASE_guard11420_0b0_theResult___fst_exp19648_0_ETC__q69 = + _theResult___fst_exp__h419648; 2'b01, 2'b10, 2'b11: - CASE_guard11729_0b0_theResult___fst_exp19957_0_ETC__q77 = - _theResult___exp__h420473; + CASE_guard11420_0b0_theResult___fst_exp19648_0_ETC__q69 = + _theResult___exp__h420164; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard11729_0b0_theResult___fst_exp19957_0_ETC__q76 or - CASE_guard11729_0b0_theResult___fst_exp19957_0_ETC__q77 or + CASE_guard11420_0b0_theResult___fst_exp19648_0_ETC__q68 or + CASE_guard11420_0b0_theResult___fst_exp19648_0_ETC__q69 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6345 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6347 or - _theResult___fst_exp__h419957) + _theResult___fst_exp__h419648) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h420551 = - CASE_guard11729_0b0_theResult___fst_exp19957_0_ETC__q76; + _theResult___fst_exp__h420242 = + CASE_guard11420_0b0_theResult___fst_exp19648_0_ETC__q68; 3'd1: - _theResult___fst_exp__h420551 = - CASE_guard11729_0b0_theResult___fst_exp19957_0_ETC__q77; + _theResult___fst_exp__h420242 = + CASE_guard11420_0b0_theResult___fst_exp19648_0_ETC__q69; 3'd2: - _theResult___fst_exp__h420551 = + _theResult___fst_exp__h420242 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6345; 3'd3: - _theResult___fst_exp__h420551 = + _theResult___fst_exp__h420242 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6347; - 3'd4: _theResult___fst_exp__h420551 = _theResult___fst_exp__h419957; - default: _theResult___fst_exp__h420551 = 8'd0; + 3'd4: _theResult___fst_exp__h420242 = _theResult___fst_exp__h419648; + default: _theResult___fst_exp__h420242 = 8'd0; endcase end - always@(guard__h420565 or - _theResult___fst_exp__h428642 or - out_exp__h429112 or _theResult___exp__h429109) + always@(guard__h420256 or + _theResult___fst_exp__h428333 or + out_exp__h428803 or _theResult___exp__h428800) begin - case (guard__h420565) + case (guard__h420256) 2'b0, 2'b01: - CASE_guard20565_0b0_theResult___fst_exp28642_0_ETC__q81 = - _theResult___fst_exp__h428642; + CASE_guard20256_0b0_theResult___fst_exp28333_0_ETC__q73 = + _theResult___fst_exp__h428333; 2'b10: - CASE_guard20565_0b0_theResult___fst_exp28642_0_ETC__q81 = - out_exp__h429112; + CASE_guard20256_0b0_theResult___fst_exp28333_0_ETC__q73 = + out_exp__h428803; 2'b11: - CASE_guard20565_0b0_theResult___fst_exp28642_0_ETC__q81 = - _theResult___exp__h429109; + CASE_guard20256_0b0_theResult___fst_exp28333_0_ETC__q73 = + _theResult___exp__h428800; endcase end - always@(guard__h420565 or - _theResult___fst_exp__h428642 or _theResult___exp__h429109) + always@(guard__h420256 or + _theResult___fst_exp__h428333 or _theResult___exp__h428800) begin - case (guard__h420565) + case (guard__h420256) 2'b0: - CASE_guard20565_0b0_theResult___fst_exp28642_0_ETC__q82 = - _theResult___fst_exp__h428642; + CASE_guard20256_0b0_theResult___fst_exp28333_0_ETC__q74 = + _theResult___fst_exp__h428333; 2'b01, 2'b10, 2'b11: - CASE_guard20565_0b0_theResult___fst_exp28642_0_ETC__q82 = - _theResult___exp__h429109; + CASE_guard20256_0b0_theResult___fst_exp28333_0_ETC__q74 = + _theResult___exp__h428800; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard20565_0b0_theResult___fst_exp28642_0_ETC__q81 or - CASE_guard20565_0b0_theResult___fst_exp28642_0_ETC__q82 or + CASE_guard20256_0b0_theResult___fst_exp28333_0_ETC__q73 or + CASE_guard20256_0b0_theResult___fst_exp28333_0_ETC__q74 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6414 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6416 or - _theResult___fst_exp__h428642) + _theResult___fst_exp__h428333) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h429187 = - CASE_guard20565_0b0_theResult___fst_exp28642_0_ETC__q81; + _theResult___fst_exp__h428878 = + CASE_guard20256_0b0_theResult___fst_exp28333_0_ETC__q73; 3'd1: - _theResult___fst_exp__h429187 = - CASE_guard20565_0b0_theResult___fst_exp28642_0_ETC__q82; + _theResult___fst_exp__h428878 = + CASE_guard20256_0b0_theResult___fst_exp28333_0_ETC__q74; 3'd2: - _theResult___fst_exp__h429187 = + _theResult___fst_exp__h428878 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6414; 3'd3: - _theResult___fst_exp__h429187 = + _theResult___fst_exp__h428878 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6416; - 3'd4: _theResult___fst_exp__h429187 = _theResult___fst_exp__h428642; - default: _theResult___fst_exp__h429187 = 8'd0; + 3'd4: _theResult___fst_exp__h428878 = _theResult___fst_exp__h428333; + default: _theResult___fst_exp__h428878 = 8'd0; endcase end - always@(guard__h402799 or - _theResult___snd__h410798 or - out_sfd__h411293 or _theResult___sfd__h411290) + always@(guard__h393783 or + sfdin__h401876 or out_sfd__h402402 or _theResult___sfd__h402399) begin - case (guard__h402799) + case (guard__h393783) 2'b0, 2'b01: - CASE_guard02799_0b0_theResult___snd10798_BITS__ETC__q83 = - _theResult___snd__h410798[56:34]; + CASE_guard93783_0b0_sfdin01876_BITS_56_TO_34_0_ETC__q75 = + sfdin__h401876[56:34]; 2'b10: - CASE_guard02799_0b0_theResult___snd10798_BITS__ETC__q83 = - out_sfd__h411293; + CASE_guard93783_0b0_sfdin01876_BITS_56_TO_34_0_ETC__q75 = + out_sfd__h402402; 2'b11: - CASE_guard02799_0b0_theResult___snd10798_BITS__ETC__q83 = - _theResult___sfd__h411290; + CASE_guard93783_0b0_sfdin01876_BITS_56_TO_34_0_ETC__q75 = + _theResult___sfd__h402399; endcase end - always@(guard__h402799 or - _theResult___snd__h410798 or _theResult___sfd__h411290) + always@(guard__h393783 or sfdin__h401876 or _theResult___sfd__h402399) begin - case (guard__h402799) + case (guard__h393783) 2'b0: - CASE_guard02799_0b0_theResult___snd10798_BITS__ETC__q84 = - _theResult___snd__h410798[56:34]; + CASE_guard93783_0b0_sfdin01876_BITS_56_TO_34_0_ETC__q76 = + sfdin__h401876[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard02799_0b0_theResult___snd10798_BITS__ETC__q84 = - _theResult___sfd__h411290; + CASE_guard93783_0b0_sfdin01876_BITS_56_TO_34_0_ETC__q76 = + _theResult___sfd__h402399; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard02799_0b0_theResult___snd10798_BITS__ETC__q83 or - CASE_guard02799_0b0_theResult___snd10798_BITS__ETC__q84 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6464 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6466 or - _theResult___snd__h410798) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0: - _theResult___fst_sfd__h411368 = - CASE_guard02799_0b0_theResult___snd10798_BITS__ETC__q83; - 3'd1: - _theResult___fst_sfd__h411368 = - CASE_guard02799_0b0_theResult___snd10798_BITS__ETC__q84; - 3'd2: - _theResult___fst_sfd__h411368 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6464; - 3'd3: - _theResult___fst_sfd__h411368 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6466; - 3'd4: _theResult___fst_sfd__h411368 = _theResult___snd__h410798[56:34]; - default: _theResult___fst_sfd__h411368 = 23'd0; - endcase - end - always@(guard__h394092 or - sfdin__h402185 or out_sfd__h402711 or _theResult___sfd__h402708) - begin - case (guard__h394092) - 2'b0, 2'b01: - CASE_guard94092_0b0_sfdin02185_BITS_56_TO_34_0_ETC__q85 = - sfdin__h402185[56:34]; - 2'b10: - CASE_guard94092_0b0_sfdin02185_BITS_56_TO_34_0_ETC__q85 = - out_sfd__h402711; - 2'b11: - CASE_guard94092_0b0_sfdin02185_BITS_56_TO_34_0_ETC__q85 = - _theResult___sfd__h402708; - endcase - end - always@(guard__h394092 or sfdin__h402185 or _theResult___sfd__h402708) - begin - case (guard__h394092) - 2'b0: - CASE_guard94092_0b0_sfdin02185_BITS_56_TO_34_0_ETC__q86 = - sfdin__h402185[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard94092_0b0_sfdin02185_BITS_56_TO_34_0_ETC__q86 = - _theResult___sfd__h402708; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard94092_0b0_sfdin02185_BITS_56_TO_34_0_ETC__q85 or - CASE_guard94092_0b0_sfdin02185_BITS_56_TO_34_0_ETC__q86 or + CASE_guard93783_0b0_sfdin01876_BITS_56_TO_34_0_ETC__q75 or + CASE_guard93783_0b0_sfdin01876_BITS_56_TO_34_0_ETC__q76 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6445 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6447 or - sfdin__h402185) + sfdin__h401876) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h402786 = - CASE_guard94092_0b0_sfdin02185_BITS_56_TO_34_0_ETC__q85; + _theResult___fst_sfd__h402477 = + CASE_guard93783_0b0_sfdin01876_BITS_56_TO_34_0_ETC__q75; 3'd1: - _theResult___fst_sfd__h402786 = - CASE_guard94092_0b0_sfdin02185_BITS_56_TO_34_0_ETC__q86; + _theResult___fst_sfd__h402477 = + CASE_guard93783_0b0_sfdin01876_BITS_56_TO_34_0_ETC__q76; 3'd2: - _theResult___fst_sfd__h402786 = + _theResult___fst_sfd__h402477 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6445; 3'd3: - _theResult___fst_sfd__h402786 = + _theResult___fst_sfd__h402477 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6447; - 3'd4: _theResult___fst_sfd__h402786 = sfdin__h402185[56:34]; - default: _theResult___fst_sfd__h402786 = 23'd0; + 3'd4: _theResult___fst_sfd__h402477 = sfdin__h401876[56:34]; + default: _theResult___fst_sfd__h402477 = 23'd0; endcase end - always@(guard__h411729 or - sfdin__h419951 or out_sfd__h420477 or _theResult___sfd__h420474) + always@(guard__h402490 or + _theResult___snd__h410489 or + out_sfd__h410984 or _theResult___sfd__h410981) begin - case (guard__h411729) + case (guard__h402490) 2'b0, 2'b01: - CASE_guard11729_0b0_sfdin19951_BITS_56_TO_34_0_ETC__q87 = - sfdin__h419951[56:34]; + CASE_guard02490_0b0_theResult___snd10489_BITS__ETC__q77 = + _theResult___snd__h410489[56:34]; 2'b10: - CASE_guard11729_0b0_sfdin19951_BITS_56_TO_34_0_ETC__q87 = - out_sfd__h420477; + CASE_guard02490_0b0_theResult___snd10489_BITS__ETC__q77 = + out_sfd__h410984; 2'b11: - CASE_guard11729_0b0_sfdin19951_BITS_56_TO_34_0_ETC__q87 = - _theResult___sfd__h420474; + CASE_guard02490_0b0_theResult___snd10489_BITS__ETC__q77 = + _theResult___sfd__h410981; endcase end - always@(guard__h411729 or sfdin__h419951 or _theResult___sfd__h420474) + always@(guard__h402490 or + _theResult___snd__h410489 or _theResult___sfd__h410981) begin - case (guard__h411729) + case (guard__h402490) 2'b0: - CASE_guard11729_0b0_sfdin19951_BITS_56_TO_34_0_ETC__q88 = - sfdin__h419951[56:34]; + CASE_guard02490_0b0_theResult___snd10489_BITS__ETC__q78 = + _theResult___snd__h410489[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard11729_0b0_sfdin19951_BITS_56_TO_34_0_ETC__q88 = - _theResult___sfd__h420474; + CASE_guard02490_0b0_theResult___snd10489_BITS__ETC__q78 = + _theResult___sfd__h410981; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard11729_0b0_sfdin19951_BITS_56_TO_34_0_ETC__q87 or - CASE_guard11729_0b0_sfdin19951_BITS_56_TO_34_0_ETC__q88 or + CASE_guard02490_0b0_theResult___snd10489_BITS__ETC__q77 or + CASE_guard02490_0b0_theResult___snd10489_BITS__ETC__q78 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6464 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6466 or + _theResult___snd__h410489) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) + 3'd0: + _theResult___fst_sfd__h411059 = + CASE_guard02490_0b0_theResult___snd10489_BITS__ETC__q77; + 3'd1: + _theResult___fst_sfd__h411059 = + CASE_guard02490_0b0_theResult___snd10489_BITS__ETC__q78; + 3'd2: + _theResult___fst_sfd__h411059 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6464; + 3'd3: + _theResult___fst_sfd__h411059 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6466; + 3'd4: _theResult___fst_sfd__h411059 = _theResult___snd__h410489[56:34]; + default: _theResult___fst_sfd__h411059 = 23'd0; + endcase + end + always@(guard__h411420 or + sfdin__h419642 or out_sfd__h420168 or _theResult___sfd__h420165) + begin + case (guard__h411420) + 2'b0, 2'b01: + CASE_guard11420_0b0_sfdin19642_BITS_56_TO_34_0_ETC__q79 = + sfdin__h419642[56:34]; + 2'b10: + CASE_guard11420_0b0_sfdin19642_BITS_56_TO_34_0_ETC__q79 = + out_sfd__h420168; + 2'b11: + CASE_guard11420_0b0_sfdin19642_BITS_56_TO_34_0_ETC__q79 = + _theResult___sfd__h420165; + endcase + end + always@(guard__h411420 or sfdin__h419642 or _theResult___sfd__h420165) + begin + case (guard__h411420) + 2'b0: + CASE_guard11420_0b0_sfdin19642_BITS_56_TO_34_0_ETC__q80 = + sfdin__h419642[56:34]; + 2'b01, 2'b10, 2'b11: + CASE_guard11420_0b0_sfdin19642_BITS_56_TO_34_0_ETC__q80 = + _theResult___sfd__h420165; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or + CASE_guard11420_0b0_sfdin19642_BITS_56_TO_34_0_ETC__q79 or + CASE_guard11420_0b0_sfdin19642_BITS_56_TO_34_0_ETC__q80 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6491 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6493 or - sfdin__h419951) + sfdin__h419642) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h420552 = - CASE_guard11729_0b0_sfdin19951_BITS_56_TO_34_0_ETC__q87; + _theResult___fst_sfd__h420243 = + CASE_guard11420_0b0_sfdin19642_BITS_56_TO_34_0_ETC__q79; 3'd1: - _theResult___fst_sfd__h420552 = - CASE_guard11729_0b0_sfdin19951_BITS_56_TO_34_0_ETC__q88; + _theResult___fst_sfd__h420243 = + CASE_guard11420_0b0_sfdin19642_BITS_56_TO_34_0_ETC__q80; 3'd2: - _theResult___fst_sfd__h420552 = + _theResult___fst_sfd__h420243 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6491; 3'd3: - _theResult___fst_sfd__h420552 = + _theResult___fst_sfd__h420243 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6493; - 3'd4: _theResult___fst_sfd__h420552 = sfdin__h419951[56:34]; - default: _theResult___fst_sfd__h420552 = 23'd0; + 3'd4: _theResult___fst_sfd__h420243 = sfdin__h419642[56:34]; + default: _theResult___fst_sfd__h420243 = 23'd0; endcase end - always@(guard__h420565 or - _theResult___snd__h428588 or - out_sfd__h429113 or _theResult___sfd__h429110) + always@(guard__h420256 or + _theResult___snd__h428279 or + out_sfd__h428804 or _theResult___sfd__h428801) begin - case (guard__h420565) + case (guard__h420256) 2'b0, 2'b01: - CASE_guard20565_0b0_theResult___snd28588_BITS__ETC__q89 = - _theResult___snd__h428588[56:34]; + CASE_guard20256_0b0_theResult___snd28279_BITS__ETC__q81 = + _theResult___snd__h428279[56:34]; 2'b10: - CASE_guard20565_0b0_theResult___snd28588_BITS__ETC__q89 = - out_sfd__h429113; + CASE_guard20256_0b0_theResult___snd28279_BITS__ETC__q81 = + out_sfd__h428804; 2'b11: - CASE_guard20565_0b0_theResult___snd28588_BITS__ETC__q89 = - _theResult___sfd__h429110; + CASE_guard20256_0b0_theResult___snd28279_BITS__ETC__q81 = + _theResult___sfd__h428801; endcase end - always@(guard__h420565 or - _theResult___snd__h428588 or _theResult___sfd__h429110) + always@(guard__h420256 or + _theResult___snd__h428279 or _theResult___sfd__h428801) begin - case (guard__h420565) + case (guard__h420256) 2'b0: - CASE_guard20565_0b0_theResult___snd28588_BITS__ETC__q90 = - _theResult___snd__h428588[56:34]; + CASE_guard20256_0b0_theResult___snd28279_BITS__ETC__q82 = + _theResult___snd__h428279[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard20565_0b0_theResult___snd28588_BITS__ETC__q90 = - _theResult___sfd__h429110; + CASE_guard20256_0b0_theResult___snd28279_BITS__ETC__q82 = + _theResult___sfd__h428801; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard20565_0b0_theResult___snd28588_BITS__ETC__q89 or - CASE_guard20565_0b0_theResult___snd28588_BITS__ETC__q90 or + CASE_guard20256_0b0_theResult___snd28279_BITS__ETC__q81 or + CASE_guard20256_0b0_theResult___snd28279_BITS__ETC__q82 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6510 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6512 or - _theResult___snd__h428588) + _theResult___snd__h428279) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h429188 = - CASE_guard20565_0b0_theResult___snd28588_BITS__ETC__q89; + _theResult___fst_sfd__h428879 = + CASE_guard20256_0b0_theResult___snd28279_BITS__ETC__q81; 3'd1: - _theResult___fst_sfd__h429188 = - CASE_guard20565_0b0_theResult___snd28588_BITS__ETC__q90; + _theResult___fst_sfd__h428879 = + CASE_guard20256_0b0_theResult___snd28279_BITS__ETC__q82; 3'd2: - _theResult___fst_sfd__h429188 = + _theResult___fst_sfd__h428879 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6510; 3'd3: - _theResult___fst_sfd__h429188 = + _theResult___fst_sfd__h428879 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6512; - 3'd4: _theResult___fst_sfd__h429188 = _theResult___snd__h428588[56:34]; - default: _theResult___fst_sfd__h429188 = 23'd0; + 3'd4: _theResult___fst_sfd__h428879 = _theResult___snd__h428279[56:34]; + default: _theResult___fst_sfd__h428879 = 23'd0; endcase end - always@(guard__h394092 or + always@(guard__h393783 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h394092) + case (guard__h393783) 2'b0, 2'b01, 2'b10: - CASE_guard94092_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q91 = + CASE_guard93783_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q83 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard94092_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q91 = - guard__h394092 == 2'b11 && + CASE_guard93783_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q83 = + guard__h393783 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard94092_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q91 or - guard__h394092) + CASE_guard93783_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q83 or + guard__h393783) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6598 = - CASE_guard94092_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q91; + CASE_guard93783_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q83; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6598 = - (guard__h394092 == 2'b0) ? + (guard__h393783 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h394092 == 2'b01 || guard__h394092 == 2'b10 || - guard__h394092 == 2'b11) && + (guard__h393783 == 2'b01 || guard__h393783 == 2'b10 || + guard__h393783 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6598 = @@ -34303,72 +33953,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h394092 or + always@(guard__h402490 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h394092) + case (guard__h402490) 2'b0, 2'b01, 2'b10: - CASE_guard94092_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q92 = - !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; - 2'd3: - CASE_guard94092_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q92 = - guard__h394092 != 2'b11 || - !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard94092_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q92 or - guard__h394092) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0: - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6542 = - CASE_guard94092_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q92; - 3'd1: - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6542 = - (guard__h394092 == 2'b0) ? - !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h394092 != 2'b01 && guard__h394092 != 2'b10 && - guard__h394092 != 2'b11 || - !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; - 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6542 = - !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6542 = - coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] != - 3'd4 || - !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; - endcase - end - always@(guard__h402799 or - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) - begin - case (guard__h402799) - 2'b0, 2'b01, 2'b10: - CASE_guard02799_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q93 = + CASE_guard02490_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q84 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard02799_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q93 = - guard__h402799 == 2'b11 && + CASE_guard02490_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q84 = + guard__h402490 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard02799_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q93 or - guard__h402799) + CASE_guard02490_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q84 or + guard__h402490) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6605 = - CASE_guard02799_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q93; + CASE_guard02490_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q84; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6605 = - (guard__h402799 == 2'b0) ? + (guard__h402490 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h402799 == 2'b01 || guard__h402799 == 2'b10 || - guard__h402799 == 2'b11) && + (guard__h402490 == 2'b01 || guard__h402490 == 2'b10 || + guard__h402490 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6605 = @@ -34379,34 +33991,72 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h402799 or + always@(guard__h393783 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h402799) + case (guard__h393783) 2'b0, 2'b01, 2'b10: - CASE_guard02799_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q94 = + CASE_guard93783_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q85 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard02799_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q94 = - guard__h402799 != 2'b11 || + CASE_guard93783_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q85 = + guard__h393783 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard02799_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q94 or - guard__h402799) + CASE_guard93783_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q85 or + guard__h393783) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) + 3'd0: + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6542 = + CASE_guard93783_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q85; + 3'd1: + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6542 = + (guard__h393783 == 2'b0) ? + !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : + guard__h393783 != 2'b01 && guard__h393783 != 2'b10 && + guard__h393783 != 2'b11 || + !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; + 3'd2, 3'd3: + IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6542 = + !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; + default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6542 = + coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] != + 3'd4 || + !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; + endcase + end + always@(guard__h402490 or + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) + begin + case (guard__h402490) + 2'b0, 2'b01, 2'b10: + CASE_guard02490_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q86 = + !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; + 2'd3: + CASE_guard02490_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q86 = + guard__h402490 != 2'b11 || + !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or + CASE_guard02490_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q86 or + guard__h402490) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6555 = - CASE_guard02799_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q94; + CASE_guard02490_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q86; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6555 = - (guard__h402799 == 2'b0) ? + (guard__h402490 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h402799 != 2'b01 && guard__h402799 != 2'b10 && - guard__h402799 != 2'b11 || + guard__h402490 != 2'b01 && guard__h402490 != 2'b10 && + guard__h402490 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6555 = @@ -34417,34 +34067,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h411729 or + always@(guard__h411420 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h411729) + case (guard__h411420) 2'b0, 2'b01, 2'b10: - CASE_guard11729_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q95 = + CASE_guard11420_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q87 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard11729_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q95 = - guard__h411729 == 2'b11 && + CASE_guard11420_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q87 = + guard__h411420 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard11729_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q95 or - guard__h411729) + CASE_guard11420_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q87 or + guard__h411420) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6615 = - CASE_guard11729_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q95; + CASE_guard11420_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q87; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6615 = - (guard__h411729 == 2'b0) ? + (guard__h411420 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h411729 == 2'b01 || guard__h411729 == 2'b10 || - guard__h411729 == 2'b11) && + (guard__h411420 == 2'b01 || guard__h411420 == 2'b10 || + guard__h411420 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6615 = @@ -34455,34 +34105,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h411729 or + always@(guard__h411420 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h411729) + case (guard__h411420) 2'b0, 2'b01, 2'b10: - CASE_guard11729_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q96 = + CASE_guard11420_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q88 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard11729_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q96 = - guard__h411729 != 2'b11 || + CASE_guard11420_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q88 = + guard__h411420 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard11729_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q96 or - guard__h411729) + CASE_guard11420_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q88 or + guard__h411420) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6572 = - CASE_guard11729_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q96; + CASE_guard11420_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q88; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6572 = - (guard__h411729 == 2'b0) ? + (guard__h411420 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h411729 != 2'b01 && guard__h411729 != 2'b10 && - guard__h411729 != 2'b11 || + guard__h411420 != 2'b01 && guard__h411420 != 2'b10 && + guard__h411420 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6572 = @@ -34493,34 +34143,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h420565 or + always@(guard__h420256 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h420565) + case (guard__h420256) 2'b0, 2'b01, 2'b10: - CASE_guard20565_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q97 = + CASE_guard20256_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q89 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard20565_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q97 = - guard__h420565 == 2'b11 && + CASE_guard20256_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q89 = + guard__h420256 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard20565_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q97 or - guard__h420565) + CASE_guard20256_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q89 or + guard__h420256) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6622 = - CASE_guard20565_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q97; + CASE_guard20256_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q89; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6622 = - (guard__h420565 == 2'b0) ? + (guard__h420256 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h420565 == 2'b01 || guard__h420565 == 2'b10 || - guard__h420565 == 2'b11) && + (guard__h420256 == 2'b01 || guard__h420256 == 2'b10 || + guard__h420256 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6622 = @@ -34531,34 +34181,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h420565 or + always@(guard__h420256 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h420565) + case (guard__h420256) 2'b0, 2'b01, 2'b10: - CASE_guard20565_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q98 = + CASE_guard20256_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q90 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard20565_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q98 = - guard__h420565 != 2'b11 || + CASE_guard20256_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q90 = + guard__h420256 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard20565_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q98 or - guard__h420565) + CASE_guard20256_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q90 or + guard__h420256) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6585 = - CASE_guard20565_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q98; + CASE_guard20256_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q90; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6585 = - (guard__h420565 == 2'b0) ? + (guard__h420256 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h420565 != 2'b01 && guard__h420565 != 2'b10 && - guard__h420565 != 2'b11 || + guard__h420256 != 2'b01 && guard__h420256 != 2'b10 && + guard__h420256 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6585 = @@ -34595,394 +34245,446 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h448494 or - _theResult___fst_exp__h456542 or - out_exp__h456987 or _theResult___exp__h456984) + always@(guard__h448185 or + _theResult___fst_exp__h456233 or + out_exp__h456678 or _theResult___exp__h456675) begin - case (guard__h448494) + case (guard__h448185) 2'b0, 2'b01: - CASE_guard48494_0b0_theResult___fst_exp56542_0_ETC__q103 = - _theResult___fst_exp__h456542; + CASE_guard48185_0b0_theResult___fst_exp56233_0_ETC__q95 = + _theResult___fst_exp__h456233; 2'b10: - CASE_guard48494_0b0_theResult___fst_exp56542_0_ETC__q103 = - out_exp__h456987; + CASE_guard48185_0b0_theResult___fst_exp56233_0_ETC__q95 = + out_exp__h456678; 2'b11: - CASE_guard48494_0b0_theResult___fst_exp56542_0_ETC__q103 = - _theResult___exp__h456984; + CASE_guard48185_0b0_theResult___fst_exp56233_0_ETC__q95 = + _theResult___exp__h456675; endcase end - always@(guard__h448494 or - _theResult___fst_exp__h456542 or _theResult___exp__h456984) + always@(guard__h448185 or + _theResult___fst_exp__h456233 or _theResult___exp__h456675) begin - case (guard__h448494) + case (guard__h448185) 2'b0: - CASE_guard48494_0b0_theResult___fst_exp56542_0_ETC__q104 = - _theResult___fst_exp__h456542; + CASE_guard48185_0b0_theResult___fst_exp56233_0_ETC__q96 = + _theResult___fst_exp__h456233; 2'b01, 2'b10, 2'b11: - CASE_guard48494_0b0_theResult___fst_exp56542_0_ETC__q104 = - _theResult___exp__h456984; + CASE_guard48185_0b0_theResult___fst_exp56233_0_ETC__q96 = + _theResult___exp__h456675; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard48494_0b0_theResult___fst_exp56542_0_ETC__q103 or - CASE_guard48494_0b0_theResult___fst_exp56542_0_ETC__q104 or + CASE_guard48185_0b0_theResult___fst_exp56233_0_ETC__q95 or + CASE_guard48185_0b0_theResult___fst_exp56233_0_ETC__q96 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7412 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7414 or - _theResult___fst_exp__h456542) + _theResult___fst_exp__h456233) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h457062 = - CASE_guard48494_0b0_theResult___fst_exp56542_0_ETC__q103; + _theResult___fst_exp__h456753 = + CASE_guard48185_0b0_theResult___fst_exp56233_0_ETC__q95; 3'd1: - _theResult___fst_exp__h457062 = - CASE_guard48494_0b0_theResult___fst_exp56542_0_ETC__q104; + _theResult___fst_exp__h456753 = + CASE_guard48185_0b0_theResult___fst_exp56233_0_ETC__q96; 3'd2: - _theResult___fst_exp__h457062 = + _theResult___fst_exp__h456753 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7412; 3'd3: - _theResult___fst_exp__h457062 = + _theResult___fst_exp__h456753 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7414; - 3'd4: _theResult___fst_exp__h457062 = _theResult___fst_exp__h456542; - default: _theResult___fst_exp__h457062 = 8'd0; + 3'd4: _theResult___fst_exp__h456753 = _theResult___fst_exp__h456233; + default: _theResult___fst_exp__h456753 = 8'd0; endcase end - always@(guard__h439787 or - _theResult___fst_exp__h447886 or - out_exp__h448405 or _theResult___exp__h448402) + always@(guard__h439478 or + _theResult___fst_exp__h447577 or + out_exp__h448096 or _theResult___exp__h448093) begin - case (guard__h439787) + case (guard__h439478) 2'b0, 2'b01: - CASE_guard39787_0b0_theResult___fst_exp47886_0_ETC__q105 = - _theResult___fst_exp__h447886; + CASE_guard39478_0b0_theResult___fst_exp47577_0_ETC__q97 = + _theResult___fst_exp__h447577; 2'b10: - CASE_guard39787_0b0_theResult___fst_exp47886_0_ETC__q105 = - out_exp__h448405; + CASE_guard39478_0b0_theResult___fst_exp47577_0_ETC__q97 = + out_exp__h448096; 2'b11: - CASE_guard39787_0b0_theResult___fst_exp47886_0_ETC__q105 = - _theResult___exp__h448402; + CASE_guard39478_0b0_theResult___fst_exp47577_0_ETC__q97 = + _theResult___exp__h448093; endcase end - always@(guard__h439787 or - _theResult___fst_exp__h447886 or _theResult___exp__h448402) + always@(guard__h439478 or + _theResult___fst_exp__h447577 or _theResult___exp__h448093) begin - case (guard__h439787) + case (guard__h439478) 2'b0: - CASE_guard39787_0b0_theResult___fst_exp47886_0_ETC__q106 = - _theResult___fst_exp__h447886; + CASE_guard39478_0b0_theResult___fst_exp47577_0_ETC__q98 = + _theResult___fst_exp__h447577; 2'b01, 2'b10, 2'b11: - CASE_guard39787_0b0_theResult___fst_exp47886_0_ETC__q106 = - _theResult___exp__h448402; + CASE_guard39478_0b0_theResult___fst_exp47577_0_ETC__q98 = + _theResult___exp__h448093; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard39787_0b0_theResult___fst_exp47886_0_ETC__q105 or - CASE_guard39787_0b0_theResult___fst_exp47886_0_ETC__q106 or + CASE_guard39478_0b0_theResult___fst_exp47577_0_ETC__q97 or + CASE_guard39478_0b0_theResult___fst_exp47577_0_ETC__q98 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7190 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7193 or - _theResult___fst_exp__h447886) + _theResult___fst_exp__h447577) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h448480 = - CASE_guard39787_0b0_theResult___fst_exp47886_0_ETC__q105; + _theResult___fst_exp__h448171 = + CASE_guard39478_0b0_theResult___fst_exp47577_0_ETC__q97; 3'd1: - _theResult___fst_exp__h448480 = - CASE_guard39787_0b0_theResult___fst_exp47886_0_ETC__q106; + _theResult___fst_exp__h448171 = + CASE_guard39478_0b0_theResult___fst_exp47577_0_ETC__q98; 3'd2: - _theResult___fst_exp__h448480 = + _theResult___fst_exp__h448171 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7190; 3'd3: - _theResult___fst_exp__h448480 = + _theResult___fst_exp__h448171 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7193; - 3'd4: _theResult___fst_exp__h448480 = _theResult___fst_exp__h447886; - default: _theResult___fst_exp__h448480 = 8'd0; + 3'd4: _theResult___fst_exp__h448171 = _theResult___fst_exp__h447577; + default: _theResult___fst_exp__h448171 = 8'd0; endcase end - always@(guard__h457424 or - _theResult___fst_exp__h465652 or - out_exp__h466171 or _theResult___exp__h466168) + always@(guard__h457115 or + _theResult___fst_exp__h465343 or + out_exp__h465862 or _theResult___exp__h465859) begin - case (guard__h457424) + case (guard__h457115) 2'b0, 2'b01: - CASE_guard57424_0b0_theResult___fst_exp65652_0_ETC__q111 = - _theResult___fst_exp__h465652; + CASE_guard57115_0b0_theResult___fst_exp65343_0_ETC__q103 = + _theResult___fst_exp__h465343; 2'b10: - CASE_guard57424_0b0_theResult___fst_exp65652_0_ETC__q111 = - out_exp__h466171; + CASE_guard57115_0b0_theResult___fst_exp65343_0_ETC__q103 = + out_exp__h465862; 2'b11: - CASE_guard57424_0b0_theResult___fst_exp65652_0_ETC__q111 = - _theResult___exp__h466168; + CASE_guard57115_0b0_theResult___fst_exp65343_0_ETC__q103 = + _theResult___exp__h465859; endcase end - always@(guard__h457424 or - _theResult___fst_exp__h465652 or _theResult___exp__h466168) + always@(guard__h457115 or + _theResult___fst_exp__h465343 or _theResult___exp__h465859) begin - case (guard__h457424) + case (guard__h457115) 2'b0: - CASE_guard57424_0b0_theResult___fst_exp65652_0_ETC__q112 = - _theResult___fst_exp__h465652; + CASE_guard57115_0b0_theResult___fst_exp65343_0_ETC__q104 = + _theResult___fst_exp__h465343; 2'b01, 2'b10, 2'b11: - CASE_guard57424_0b0_theResult___fst_exp65652_0_ETC__q112 = - _theResult___exp__h466168; + CASE_guard57115_0b0_theResult___fst_exp65343_0_ETC__q104 = + _theResult___exp__h465859; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard57424_0b0_theResult___fst_exp65652_0_ETC__q111 or - CASE_guard57424_0b0_theResult___fst_exp65652_0_ETC__q112 or + CASE_guard57115_0b0_theResult___fst_exp65343_0_ETC__q103 or + CASE_guard57115_0b0_theResult___fst_exp65343_0_ETC__q104 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7737 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7739 or - _theResult___fst_exp__h465652) + _theResult___fst_exp__h465343) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h466246 = - CASE_guard57424_0b0_theResult___fst_exp65652_0_ETC__q111; + _theResult___fst_exp__h465937 = + CASE_guard57115_0b0_theResult___fst_exp65343_0_ETC__q103; 3'd1: - _theResult___fst_exp__h466246 = - CASE_guard57424_0b0_theResult___fst_exp65652_0_ETC__q112; + _theResult___fst_exp__h465937 = + CASE_guard57115_0b0_theResult___fst_exp65343_0_ETC__q104; 3'd2: - _theResult___fst_exp__h466246 = + _theResult___fst_exp__h465937 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7737; 3'd3: - _theResult___fst_exp__h466246 = + _theResult___fst_exp__h465937 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7739; - 3'd4: _theResult___fst_exp__h466246 = _theResult___fst_exp__h465652; - default: _theResult___fst_exp__h466246 = 8'd0; + 3'd4: _theResult___fst_exp__h465937 = _theResult___fst_exp__h465343; + default: _theResult___fst_exp__h465937 = 8'd0; endcase end - always@(guard__h466260 or - _theResult___fst_exp__h474337 or - out_exp__h474807 or _theResult___exp__h474804) + always@(guard__h465951 or + _theResult___fst_exp__h474028 or + out_exp__h474498 or _theResult___exp__h474495) begin - case (guard__h466260) + case (guard__h465951) 2'b0, 2'b01: - CASE_guard66260_0b0_theResult___fst_exp74337_0_ETC__q116 = - _theResult___fst_exp__h474337; + CASE_guard65951_0b0_theResult___fst_exp74028_0_ETC__q108 = + _theResult___fst_exp__h474028; 2'b10: - CASE_guard66260_0b0_theResult___fst_exp74337_0_ETC__q116 = - out_exp__h474807; + CASE_guard65951_0b0_theResult___fst_exp74028_0_ETC__q108 = + out_exp__h474498; 2'b11: - CASE_guard66260_0b0_theResult___fst_exp74337_0_ETC__q116 = - _theResult___exp__h474804; + CASE_guard65951_0b0_theResult___fst_exp74028_0_ETC__q108 = + _theResult___exp__h474495; endcase end - always@(guard__h466260 or - _theResult___fst_exp__h474337 or _theResult___exp__h474804) + always@(guard__h465951 or + _theResult___fst_exp__h474028 or _theResult___exp__h474495) begin - case (guard__h466260) + case (guard__h465951) 2'b0: - CASE_guard66260_0b0_theResult___fst_exp74337_0_ETC__q117 = - _theResult___fst_exp__h474337; + CASE_guard65951_0b0_theResult___fst_exp74028_0_ETC__q109 = + _theResult___fst_exp__h474028; 2'b01, 2'b10, 2'b11: - CASE_guard66260_0b0_theResult___fst_exp74337_0_ETC__q117 = - _theResult___exp__h474804; + CASE_guard65951_0b0_theResult___fst_exp74028_0_ETC__q109 = + _theResult___exp__h474495; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard66260_0b0_theResult___fst_exp74337_0_ETC__q116 or - CASE_guard66260_0b0_theResult___fst_exp74337_0_ETC__q117 or + CASE_guard65951_0b0_theResult___fst_exp74028_0_ETC__q108 or + CASE_guard65951_0b0_theResult___fst_exp74028_0_ETC__q109 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7806 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7808 or - _theResult___fst_exp__h474337) + _theResult___fst_exp__h474028) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h474882 = - CASE_guard66260_0b0_theResult___fst_exp74337_0_ETC__q116; + _theResult___fst_exp__h474573 = + CASE_guard65951_0b0_theResult___fst_exp74028_0_ETC__q108; 3'd1: - _theResult___fst_exp__h474882 = - CASE_guard66260_0b0_theResult___fst_exp74337_0_ETC__q117; + _theResult___fst_exp__h474573 = + CASE_guard65951_0b0_theResult___fst_exp74028_0_ETC__q109; 3'd2: - _theResult___fst_exp__h474882 = + _theResult___fst_exp__h474573 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7806; 3'd3: - _theResult___fst_exp__h474882 = + _theResult___fst_exp__h474573 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7808; - 3'd4: _theResult___fst_exp__h474882 = _theResult___fst_exp__h474337; - default: _theResult___fst_exp__h474882 = 8'd0; + 3'd4: _theResult___fst_exp__h474573 = _theResult___fst_exp__h474028; + default: _theResult___fst_exp__h474573 = 8'd0; endcase end - always@(guard__h448494 or - _theResult___snd__h456493 or - out_sfd__h456988 or _theResult___sfd__h456985) + always@(guard__h448185 or + _theResult___snd__h456184 or + out_sfd__h456679 or _theResult___sfd__h456676) begin - case (guard__h448494) + case (guard__h448185) 2'b0, 2'b01: - CASE_guard48494_0b0_theResult___snd56493_BITS__ETC__q118 = - _theResult___snd__h456493[56:34]; + CASE_guard48185_0b0_theResult___snd56184_BITS__ETC__q110 = + _theResult___snd__h456184[56:34]; 2'b10: - CASE_guard48494_0b0_theResult___snd56493_BITS__ETC__q118 = - out_sfd__h456988; + CASE_guard48185_0b0_theResult___snd56184_BITS__ETC__q110 = + out_sfd__h456679; 2'b11: - CASE_guard48494_0b0_theResult___snd56493_BITS__ETC__q118 = - _theResult___sfd__h456985; + CASE_guard48185_0b0_theResult___snd56184_BITS__ETC__q110 = + _theResult___sfd__h456676; endcase end - always@(guard__h448494 or - _theResult___snd__h456493 or _theResult___sfd__h456985) + always@(guard__h448185 or + _theResult___snd__h456184 or _theResult___sfd__h456676) begin - case (guard__h448494) + case (guard__h448185) 2'b0: - CASE_guard48494_0b0_theResult___snd56493_BITS__ETC__q119 = - _theResult___snd__h456493[56:34]; + CASE_guard48185_0b0_theResult___snd56184_BITS__ETC__q111 = + _theResult___snd__h456184[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard48494_0b0_theResult___snd56493_BITS__ETC__q119 = - _theResult___sfd__h456985; + CASE_guard48185_0b0_theResult___snd56184_BITS__ETC__q111 = + _theResult___sfd__h456676; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard48494_0b0_theResult___snd56493_BITS__ETC__q118 or - CASE_guard48494_0b0_theResult___snd56493_BITS__ETC__q119 or + CASE_guard48185_0b0_theResult___snd56184_BITS__ETC__q110 or + CASE_guard48185_0b0_theResult___snd56184_BITS__ETC__q111 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7856 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7858 or - _theResult___snd__h456493) + _theResult___snd__h456184) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h457063 = - CASE_guard48494_0b0_theResult___snd56493_BITS__ETC__q118; + _theResult___fst_sfd__h456754 = + CASE_guard48185_0b0_theResult___snd56184_BITS__ETC__q110; 3'd1: - _theResult___fst_sfd__h457063 = - CASE_guard48494_0b0_theResult___snd56493_BITS__ETC__q119; + _theResult___fst_sfd__h456754 = + CASE_guard48185_0b0_theResult___snd56184_BITS__ETC__q111; 3'd2: - _theResult___fst_sfd__h457063 = + _theResult___fst_sfd__h456754 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7856; 3'd3: - _theResult___fst_sfd__h457063 = + _theResult___fst_sfd__h456754 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7858; - 3'd4: _theResult___fst_sfd__h457063 = _theResult___snd__h456493[56:34]; - default: _theResult___fst_sfd__h457063 = 23'd0; + 3'd4: _theResult___fst_sfd__h456754 = _theResult___snd__h456184[56:34]; + default: _theResult___fst_sfd__h456754 = 23'd0; endcase end - always@(guard__h439787 or - sfdin__h447880 or out_sfd__h448406 or _theResult___sfd__h448403) + always@(guard__h439478 or + sfdin__h447571 or out_sfd__h448097 or _theResult___sfd__h448094) begin - case (guard__h439787) + case (guard__h439478) 2'b0, 2'b01: - CASE_guard39787_0b0_sfdin47880_BITS_56_TO_34_0_ETC__q120 = - sfdin__h447880[56:34]; + CASE_guard39478_0b0_sfdin47571_BITS_56_TO_34_0_ETC__q112 = + sfdin__h447571[56:34]; 2'b10: - CASE_guard39787_0b0_sfdin47880_BITS_56_TO_34_0_ETC__q120 = - out_sfd__h448406; + CASE_guard39478_0b0_sfdin47571_BITS_56_TO_34_0_ETC__q112 = + out_sfd__h448097; 2'b11: - CASE_guard39787_0b0_sfdin47880_BITS_56_TO_34_0_ETC__q120 = - _theResult___sfd__h448403; + CASE_guard39478_0b0_sfdin47571_BITS_56_TO_34_0_ETC__q112 = + _theResult___sfd__h448094; endcase end - always@(guard__h439787 or sfdin__h447880 or _theResult___sfd__h448403) + always@(guard__h439478 or sfdin__h447571 or _theResult___sfd__h448094) begin - case (guard__h439787) + case (guard__h439478) 2'b0: - CASE_guard39787_0b0_sfdin47880_BITS_56_TO_34_0_ETC__q121 = - sfdin__h447880[56:34]; + CASE_guard39478_0b0_sfdin47571_BITS_56_TO_34_0_ETC__q113 = + sfdin__h447571[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard39787_0b0_sfdin47880_BITS_56_TO_34_0_ETC__q121 = - _theResult___sfd__h448403; + CASE_guard39478_0b0_sfdin47571_BITS_56_TO_34_0_ETC__q113 = + _theResult___sfd__h448094; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard39787_0b0_sfdin47880_BITS_56_TO_34_0_ETC__q120 or - CASE_guard39787_0b0_sfdin47880_BITS_56_TO_34_0_ETC__q121 or + CASE_guard39478_0b0_sfdin47571_BITS_56_TO_34_0_ETC__q112 or + CASE_guard39478_0b0_sfdin47571_BITS_56_TO_34_0_ETC__q113 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7837 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7839 or - sfdin__h447880) + sfdin__h447571) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h448481 = - CASE_guard39787_0b0_sfdin47880_BITS_56_TO_34_0_ETC__q120; + _theResult___fst_sfd__h448172 = + CASE_guard39478_0b0_sfdin47571_BITS_56_TO_34_0_ETC__q112; 3'd1: - _theResult___fst_sfd__h448481 = - CASE_guard39787_0b0_sfdin47880_BITS_56_TO_34_0_ETC__q121; + _theResult___fst_sfd__h448172 = + CASE_guard39478_0b0_sfdin47571_BITS_56_TO_34_0_ETC__q113; 3'd2: - _theResult___fst_sfd__h448481 = + _theResult___fst_sfd__h448172 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7837; 3'd3: - _theResult___fst_sfd__h448481 = + _theResult___fst_sfd__h448172 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7839; - 3'd4: _theResult___fst_sfd__h448481 = sfdin__h447880[56:34]; - default: _theResult___fst_sfd__h448481 = 23'd0; + 3'd4: _theResult___fst_sfd__h448172 = sfdin__h447571[56:34]; + default: _theResult___fst_sfd__h448172 = 23'd0; endcase end - always@(guard__h457424 or - sfdin__h465646 or out_sfd__h466172 or _theResult___sfd__h466169) + always@(guard__h457115 or + sfdin__h465337 or out_sfd__h465863 or _theResult___sfd__h465860) begin - case (guard__h457424) + case (guard__h457115) 2'b0, 2'b01: - CASE_guard57424_0b0_sfdin65646_BITS_56_TO_34_0_ETC__q122 = - sfdin__h465646[56:34]; + CASE_guard57115_0b0_sfdin65337_BITS_56_TO_34_0_ETC__q114 = + sfdin__h465337[56:34]; 2'b10: - CASE_guard57424_0b0_sfdin65646_BITS_56_TO_34_0_ETC__q122 = - out_sfd__h466172; + CASE_guard57115_0b0_sfdin65337_BITS_56_TO_34_0_ETC__q114 = + out_sfd__h465863; 2'b11: - CASE_guard57424_0b0_sfdin65646_BITS_56_TO_34_0_ETC__q122 = - _theResult___sfd__h466169; + CASE_guard57115_0b0_sfdin65337_BITS_56_TO_34_0_ETC__q114 = + _theResult___sfd__h465860; endcase end - always@(guard__h457424 or sfdin__h465646 or _theResult___sfd__h466169) + always@(guard__h457115 or sfdin__h465337 or _theResult___sfd__h465860) begin - case (guard__h457424) + case (guard__h457115) 2'b0: - CASE_guard57424_0b0_sfdin65646_BITS_56_TO_34_0_ETC__q123 = - sfdin__h465646[56:34]; + CASE_guard57115_0b0_sfdin65337_BITS_56_TO_34_0_ETC__q115 = + sfdin__h465337[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard57424_0b0_sfdin65646_BITS_56_TO_34_0_ETC__q123 = - _theResult___sfd__h466169; + CASE_guard57115_0b0_sfdin65337_BITS_56_TO_34_0_ETC__q115 = + _theResult___sfd__h465860; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard57424_0b0_sfdin65646_BITS_56_TO_34_0_ETC__q122 or - CASE_guard57424_0b0_sfdin65646_BITS_56_TO_34_0_ETC__q123 or + CASE_guard57115_0b0_sfdin65337_BITS_56_TO_34_0_ETC__q114 or + CASE_guard57115_0b0_sfdin65337_BITS_56_TO_34_0_ETC__q115 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7883 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7885 or - sfdin__h465646) + sfdin__h465337) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h466247 = - CASE_guard57424_0b0_sfdin65646_BITS_56_TO_34_0_ETC__q122; + _theResult___fst_sfd__h465938 = + CASE_guard57115_0b0_sfdin65337_BITS_56_TO_34_0_ETC__q114; 3'd1: - _theResult___fst_sfd__h466247 = - CASE_guard57424_0b0_sfdin65646_BITS_56_TO_34_0_ETC__q123; + _theResult___fst_sfd__h465938 = + CASE_guard57115_0b0_sfdin65337_BITS_56_TO_34_0_ETC__q115; 3'd2: - _theResult___fst_sfd__h466247 = + _theResult___fst_sfd__h465938 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7883; 3'd3: - _theResult___fst_sfd__h466247 = + _theResult___fst_sfd__h465938 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7885; - 3'd4: _theResult___fst_sfd__h466247 = sfdin__h465646[56:34]; - default: _theResult___fst_sfd__h466247 = 23'd0; + 3'd4: _theResult___fst_sfd__h465938 = sfdin__h465337[56:34]; + default: _theResult___fst_sfd__h465938 = 23'd0; endcase end - always@(guard__h439787 or + always@(guard__h465951 or + _theResult___snd__h473974 or + out_sfd__h474499 or _theResult___sfd__h474496) + begin + case (guard__h465951) + 2'b0, 2'b01: + CASE_guard65951_0b0_theResult___snd73974_BITS__ETC__q116 = + _theResult___snd__h473974[56:34]; + 2'b10: + CASE_guard65951_0b0_theResult___snd73974_BITS__ETC__q116 = + out_sfd__h474499; + 2'b11: + CASE_guard65951_0b0_theResult___snd73974_BITS__ETC__q116 = + _theResult___sfd__h474496; + endcase + end + always@(guard__h465951 or + _theResult___snd__h473974 or _theResult___sfd__h474496) + begin + case (guard__h465951) + 2'b0: + CASE_guard65951_0b0_theResult___snd73974_BITS__ETC__q117 = + _theResult___snd__h473974[56:34]; + 2'b01, 2'b10, 2'b11: + CASE_guard65951_0b0_theResult___snd73974_BITS__ETC__q117 = + _theResult___sfd__h474496; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or + CASE_guard65951_0b0_theResult___snd73974_BITS__ETC__q116 or + CASE_guard65951_0b0_theResult___snd73974_BITS__ETC__q117 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7902 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7904 or + _theResult___snd__h473974) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) + 3'd0: + _theResult___fst_sfd__h474574 = + CASE_guard65951_0b0_theResult___snd73974_BITS__ETC__q116; + 3'd1: + _theResult___fst_sfd__h474574 = + CASE_guard65951_0b0_theResult___snd73974_BITS__ETC__q117; + 3'd2: + _theResult___fst_sfd__h474574 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7902; + 3'd3: + _theResult___fst_sfd__h474574 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7904; + 3'd4: _theResult___fst_sfd__h474574 = _theResult___snd__h473974[56:34]; + default: _theResult___fst_sfd__h474574 = 23'd0; + endcase + end + always@(guard__h439478 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h439787) + case (guard__h439478) 2'b0, 2'b01, 2'b10: - CASE_guard39787_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q124 = + CASE_guard39478_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q118 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard39787_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q124 = - guard__h439787 == 2'b11 && + CASE_guard39478_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q118 = + guard__h439478 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard39787_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q124 or - guard__h439787) + CASE_guard39478_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q118 or + guard__h439478) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7990 = - CASE_guard39787_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q124; + CASE_guard39478_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q118; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7990 = - (guard__h439787 == 2'b0) ? + (guard__h439478 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h439787 == 2'b01 || guard__h439787 == 2'b10 || - guard__h439787 == 2'b11) && + (guard__h439478 == 2'b01 || guard__h439478 == 2'b10 || + guard__h439478 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7990 = @@ -34993,86 +34695,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h466260 or - _theResult___snd__h474283 or - out_sfd__h474808 or _theResult___sfd__h474805) - begin - case (guard__h466260) - 2'b0, 2'b01: - CASE_guard66260_0b0_theResult___snd74283_BITS__ETC__q125 = - _theResult___snd__h474283[56:34]; - 2'b10: - CASE_guard66260_0b0_theResult___snd74283_BITS__ETC__q125 = - out_sfd__h474808; - 2'b11: - CASE_guard66260_0b0_theResult___snd74283_BITS__ETC__q125 = - _theResult___sfd__h474805; - endcase - end - always@(guard__h466260 or - _theResult___snd__h474283 or _theResult___sfd__h474805) - begin - case (guard__h466260) - 2'b0: - CASE_guard66260_0b0_theResult___snd74283_BITS__ETC__q126 = - _theResult___snd__h474283[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard66260_0b0_theResult___snd74283_BITS__ETC__q126 = - _theResult___sfd__h474805; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard66260_0b0_theResult___snd74283_BITS__ETC__q125 or - CASE_guard66260_0b0_theResult___snd74283_BITS__ETC__q126 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7902 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7904 or - _theResult___snd__h474283) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0: - _theResult___fst_sfd__h474883 = - CASE_guard66260_0b0_theResult___snd74283_BITS__ETC__q125; - 3'd1: - _theResult___fst_sfd__h474883 = - CASE_guard66260_0b0_theResult___snd74283_BITS__ETC__q126; - 3'd2: - _theResult___fst_sfd__h474883 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7902; - 3'd3: - _theResult___fst_sfd__h474883 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7904; - 3'd4: _theResult___fst_sfd__h474883 = _theResult___snd__h474283[56:34]; - default: _theResult___fst_sfd__h474883 = 23'd0; - endcase - end - always@(guard__h439787 or + always@(guard__h439478 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h439787) + case (guard__h439478) 2'b0, 2'b01, 2'b10: - CASE_guard39787_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q127 = + CASE_guard39478_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q119 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard39787_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q127 = - guard__h439787 != 2'b11 || + CASE_guard39478_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q119 = + guard__h439478 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard39787_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q127 or - guard__h439787) + CASE_guard39478_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q119 or + guard__h439478) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7934 = - CASE_guard39787_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q127; + CASE_guard39478_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q119; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7934 = - (guard__h439787 == 2'b0) ? + (guard__h439478 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h439787 != 2'b01 && guard__h439787 != 2'b10 && - guard__h439787 != 2'b11 || + guard__h439478 != 2'b01 && guard__h439478 != 2'b10 && + guard__h439478 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7934 = @@ -35083,34 +34733,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h448494 or + always@(guard__h448185 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h448494) + case (guard__h448185) 2'b0, 2'b01, 2'b10: - CASE_guard48494_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q128 = + CASE_guard48185_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q120 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard48494_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q128 = - guard__h448494 == 2'b11 && + CASE_guard48185_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q120 = + guard__h448185 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard48494_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q128 or - guard__h448494) + CASE_guard48185_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q120 or + guard__h448185) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7997 = - CASE_guard48494_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q128; + CASE_guard48185_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q120; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7997 = - (guard__h448494 == 2'b0) ? + (guard__h448185 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h448494 == 2'b01 || guard__h448494 == 2'b10 || - guard__h448494 == 2'b11) && + (guard__h448185 == 2'b01 || guard__h448185 == 2'b10 || + guard__h448185 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7997 = @@ -35121,34 +34771,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h448494 or + always@(guard__h448185 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h448494) + case (guard__h448185) 2'b0, 2'b01, 2'b10: - CASE_guard48494_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q129 = + CASE_guard48185_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q121 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard48494_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q129 = - guard__h448494 != 2'b11 || + CASE_guard48185_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q121 = + guard__h448185 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard48494_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q129 or - guard__h448494) + CASE_guard48185_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q121 or + guard__h448185) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7947 = - CASE_guard48494_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q129; + CASE_guard48185_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q121; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7947 = - (guard__h448494 == 2'b0) ? + (guard__h448185 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h448494 != 2'b01 && guard__h448494 != 2'b10 && - guard__h448494 != 2'b11 || + guard__h448185 != 2'b01 && guard__h448185 != 2'b10 && + guard__h448185 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7947 = @@ -35159,34 +34809,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h457424 or + always@(guard__h457115 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h457424) + case (guard__h457115) 2'b0, 2'b01, 2'b10: - CASE_guard57424_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q130 = + CASE_guard57115_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q122 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard57424_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q130 = - guard__h457424 == 2'b11 && + CASE_guard57115_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q122 = + guard__h457115 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard57424_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q130 or - guard__h457424) + CASE_guard57115_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q122 or + guard__h457115) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8007 = - CASE_guard57424_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q130; + CASE_guard57115_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q122; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8007 = - (guard__h457424 == 2'b0) ? + (guard__h457115 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h457424 == 2'b01 || guard__h457424 == 2'b10 || - guard__h457424 == 2'b11) && + (guard__h457115 == 2'b01 || guard__h457115 == 2'b10 || + guard__h457115 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8007 = @@ -35197,34 +34847,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h457424 or + always@(guard__h457115 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h457424) + case (guard__h457115) 2'b0, 2'b01, 2'b10: - CASE_guard57424_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q131 = + CASE_guard57115_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q123 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard57424_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q131 = - guard__h457424 != 2'b11 || + CASE_guard57115_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q123 = + guard__h457115 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard57424_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q131 or - guard__h457424) + CASE_guard57115_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q123 or + guard__h457115) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7964 = - CASE_guard57424_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q131; + CASE_guard57115_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q123; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7964 = - (guard__h457424 == 2'b0) ? + (guard__h457115 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h457424 != 2'b01 && guard__h457424 != 2'b10 && - guard__h457424 != 2'b11 || + guard__h457115 != 2'b01 && guard__h457115 != 2'b10 && + guard__h457115 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7964 = @@ -35235,34 +34885,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h466260 or + always@(guard__h465951 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h466260) + case (guard__h465951) 2'b0, 2'b01, 2'b10: - CASE_guard66260_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q132 = + CASE_guard65951_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q124 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard66260_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q132 = - guard__h466260 == 2'b11 && + CASE_guard65951_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q124 = + guard__h465951 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard66260_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q132 or - guard__h466260) + CASE_guard65951_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q124 or + guard__h465951) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8014 = - CASE_guard66260_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q132; + CASE_guard65951_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q124; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8014 = - (guard__h466260 == 2'b0) ? + (guard__h465951 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h466260 == 2'b01 || guard__h466260 == 2'b10 || - guard__h466260 == 2'b11) && + (guard__h465951 == 2'b01 || guard__h465951 == 2'b10 || + guard__h465951 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8014 = @@ -35273,34 +34923,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h466260 or + always@(guard__h465951 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h466260) + case (guard__h465951) 2'b0, 2'b01, 2'b10: - CASE_guard66260_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q133 = + CASE_guard65951_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q125 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard66260_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q133 = - guard__h466260 != 2'b11 || + CASE_guard65951_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q125 = + guard__h465951 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard66260_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q133 or - guard__h466260) + CASE_guard65951_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q125 or + guard__h465951) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7977 = - CASE_guard66260_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q133; + CASE_guard65951_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q125; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7977 = - (guard__h466260 == 2'b0) ? + (guard__h465951 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h466260 != 2'b01 && guard__h466260 != 2'b10 && - guard__h466260 != 2'b11 || + guard__h465951 != 2'b01 && guard__h465951 != 2'b10 && + guard__h465951 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7977 = @@ -35357,28 +35007,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_request_put; endcase end - always@(guard__h496373 or - _theResult___fst_exp__h504334 or _theResult___exp__h504989) + always@(guard__h496064 or + _theResult___fst_exp__h504025 or _theResult___exp__h504680) begin - case (guard__h496373) + case (guard__h496064) 2'b0: - CASE_guard96373_0b0_theResult___fst_exp04334_0_ETC__q143 = - _theResult___fst_exp__h504334; + CASE_guard96064_0b0_theResult___fst_exp04025_0_ETC__q135 = + _theResult___fst_exp__h504025; 2'b01, 2'b10, 2'b11: - CASE_guard96373_0b0_theResult___fst_exp04334_0_ETC__q143 = - _theResult___exp__h504989; + CASE_guard96064_0b0_theResult___fst_exp04025_0_ETC__q135 = + _theResult___exp__h504680; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h504334 or + _theResult___fst_exp__h504025 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9126 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9124 or - CASE_guard96373_0b0_theResult___fst_exp04334_0_ETC__q143) + CASE_guard96064_0b0_theResult___fst_exp04025_0_ETC__q135) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9130 = - _theResult___fst_exp__h504334; + _theResult___fst_exp__h504025; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9130 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9126; @@ -35387,175 +35037,175 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9124; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9130 = - CASE_guard96373_0b0_theResult___fst_exp04334_0_ETC__q143; + CASE_guard96064_0b0_theResult___fst_exp04025_0_ETC__q135; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9130 = 11'd0; endcase end - always@(guard__h496373 or - _theResult___fst_exp__h504334 or - out_exp__h504992 or _theResult___exp__h504989) + always@(guard__h496064 or + _theResult___fst_exp__h504025 or + out_exp__h504683 or _theResult___exp__h504680) begin - case (guard__h496373) + case (guard__h496064) 2'b0, 2'b01: - CASE_guard96373_0b0_theResult___fst_exp04334_0_ETC__q144 = - _theResult___fst_exp__h504334; + CASE_guard96064_0b0_theResult___fst_exp04025_0_ETC__q136 = + _theResult___fst_exp__h504025; 2'b10: - CASE_guard96373_0b0_theResult___fst_exp04334_0_ETC__q144 = - out_exp__h504992; + CASE_guard96064_0b0_theResult___fst_exp04025_0_ETC__q136 = + out_exp__h504683; 2'b11: - CASE_guard96373_0b0_theResult___fst_exp04334_0_ETC__q144 = - _theResult___exp__h504989; + CASE_guard96064_0b0_theResult___fst_exp04025_0_ETC__q136 = + _theResult___exp__h504680; endcase end - always@(guard__h505685 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h496064 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h505685) + case (guard__h496064) 2'b0, 2'b01, 2'b10: - CASE_guard05685_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145 = + CASE_guard96064_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard05685_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145 = - guard__h505685 == 2'b11 && + CASE_guard96064_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137 = + guard__h496064 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h505685) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h496064) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q146 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q138 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q146 = - (guard__h505685 == 2'b0) ? + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q138 = + (guard__h496064 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h505685 == 2'b01 || guard__h505685 == 2'b10 || - guard__h505685 == 2'b11) && + (guard__h496064 == 2'b01 || guard__h496064 == 2'b10 || + guard__h496064 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q146 = + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q138 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(guard__h496373 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h505376 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h496373) + case (guard__h505376) 2'b0, 2'b01, 2'b10: - CASE_guard96373_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 = + CASE_guard05376_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard96373_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 = - guard__h496373 == 2'b11 && + CASE_guard05376_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139 = + guard__h505376 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h496373) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h505376) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q148 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q140 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q148 = - (guard__h496373 == 2'b0) ? + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q140 = + (guard__h505376 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h496373 == 2'b01 || guard__h496373 == 2'b10 || - guard__h496373 == 2'b11) && + (guard__h505376 == 2'b01 || guard__h505376 == 2'b10 || + guard__h505376 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q148 = + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q140 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(guard__h514754 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h514445 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h514754) + case (guard__h514445) 2'b0, 2'b01, 2'b10: - CASE_guard14754_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 = + CASE_guard14445_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard14754_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 = - guard__h514754 == 2'b11 && + CASE_guard14445_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141 = + guard__h514445 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h514754) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h514445) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q150 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q142 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q150 = - (guard__h514754 == 2'b0) ? + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q142 = + (guard__h514445 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h514754 == 2'b01 || guard__h514754 == 2'b10 || - guard__h514754 == 2'b11) && + (guard__h514445 == 2'b01 || guard__h514445 == 2'b10 || + guard__h514445 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q150 = + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q142 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(guard__h574530 or - _theResult___fst_exp__h582491 or _theResult___exp__h583146) + always@(guard__h574221 or + _theResult___fst_exp__h582182 or _theResult___exp__h582837) begin - case (guard__h574530) + case (guard__h574221) 2'b0: - CASE_guard74530_0b0_theResult___fst_exp82491_0_ETC__q160 = - _theResult___fst_exp__h582491; + CASE_guard74221_0b0_theResult___fst_exp82182_0_ETC__q152 = + _theResult___fst_exp__h582182; 2'b01, 2'b10, 2'b11: - CASE_guard74530_0b0_theResult___fst_exp82491_0_ETC__q160 = - _theResult___exp__h583146; + CASE_guard74221_0b0_theResult___fst_exp82182_0_ETC__q152 = + _theResult___exp__h582837; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h582491 or + _theResult___fst_exp__h582182 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9841 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9839 or - CASE_guard74530_0b0_theResult___fst_exp82491_0_ETC__q160) + CASE_guard74221_0b0_theResult___fst_exp82182_0_ETC__q152) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9845 = - _theResult___fst_exp__h582491; + _theResult___fst_exp__h582182; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9845 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9841; @@ -35564,283 +35214,283 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9839; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9845 = - CASE_guard74530_0b0_theResult___fst_exp82491_0_ETC__q160; + CASE_guard74221_0b0_theResult___fst_exp82182_0_ETC__q152; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9845 = 11'd0; endcase end - always@(guard__h574530 or - _theResult___fst_exp__h582491 or - out_exp__h583149 or _theResult___exp__h583146) + always@(guard__h574221 or + _theResult___fst_exp__h582182 or + out_exp__h582840 or _theResult___exp__h582837) begin - case (guard__h574530) + case (guard__h574221) 2'b0, 2'b01: - CASE_guard74530_0b0_theResult___fst_exp82491_0_ETC__q161 = - _theResult___fst_exp__h582491; + CASE_guard74221_0b0_theResult___fst_exp82182_0_ETC__q153 = + _theResult___fst_exp__h582182; 2'b10: - CASE_guard74530_0b0_theResult___fst_exp82491_0_ETC__q161 = - out_exp__h583149; + CASE_guard74221_0b0_theResult___fst_exp82182_0_ETC__q153 = + out_exp__h582840; 2'b11: - CASE_guard74530_0b0_theResult___fst_exp82491_0_ETC__q161 = - _theResult___exp__h583146; + CASE_guard74221_0b0_theResult___fst_exp82182_0_ETC__q153 = + _theResult___exp__h582837; endcase end - always@(guard__h574530 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h574221 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h574530) + case (guard__h574221) 2'b0, 2'b01, 2'b10: - CASE_guard74530_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 = + CASE_guard74221_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard74530_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 = - guard__h574530 == 2'b11 && + CASE_guard74221_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 = + guard__h574221 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h574530) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h574221) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd2, 3'd3: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q155 = + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[43]; + 3'd4: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q155 = + (guard__h574221 == 2'b0) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[43] : + (guard__h574221 == 2'b01 || guard__h574221 == 2'b10 || + guard__h574221 == 2'b11) && + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[43]; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q155 = + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[43]; + endcase + end + always@(guard__h583533 or coreFix_fpuMulDivExe_0_regToExeQ$first) + begin + case (guard__h583533) + 2'b0, 2'b01, 2'b10: + CASE_guard83533_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 = + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[43]; + 2'd3: + CASE_guard83533_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 = + guard__h583533 == 2'b11 && + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[43]; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h583533) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd2, 3'd3: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q157 = + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[43]; + 3'd4: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q157 = + (guard__h583533 == 2'b0) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[43] : + (guard__h583533 == 2'b01 || guard__h583533 == 2'b10 || + guard__h583533 == 2'b11) && + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[43]; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q157 = + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[43]; + endcase + end + always@(guard__h592602 or coreFix_fpuMulDivExe_0_regToExeQ$first) + begin + case (guard__h592602) + 2'b0, 2'b01, 2'b10: + CASE_guard92602_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 = + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[43]; + 2'd3: + CASE_guard92602_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 = + guard__h592602 == 2'b11 && + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[43]; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h592602) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd2, 3'd3: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q159 = + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[43]; + 3'd4: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q159 = + (guard__h592602 == 2'b0) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[43] : + (guard__h592602 == 2'b01 || guard__h592602 == 2'b10 || + guard__h592602 == 2'b11) && + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[43]; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q159 = + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[43]; + endcase + end + always@(guard__h583533 or coreFix_fpuMulDivExe_0_regToExeQ$first) + begin + case (guard__h583533) + 2'b0, 2'b01, 2'b10: + CASE_guard83533_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160 = + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; + 2'd3: + CASE_guard83533_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160 = + guard__h583533 != 2'b11 || + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h583533) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd2, 3'd3: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q161 = + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; + 3'd4: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q161 = + (guard__h583533 == 2'b0) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != + 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : + guard__h583533 != 2'b01 && guard__h583533 != 2'b10 && + guard__h583533 != 2'b11 || + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != + 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q161 = + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 || + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != + 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; + endcase + end + always@(guard__h574221 or coreFix_fpuMulDivExe_0_regToExeQ$first) + begin + case (guard__h574221) + 2'b0, 2'b01, 2'b10: + CASE_guard74221_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 = + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; + 2'd3: + CASE_guard74221_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 = + guard__h574221 != 2'b11 || + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h574221) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163 = - coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[43]; + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163 = - (guard__h574530 == 2'b0) ? - coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h574530 == 2'b01 || guard__h574530 == 2'b10 || - guard__h574530 == 2'b11) && - coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[43]; + (guard__h574221 == 2'b0) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != + 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : + guard__h574221 != 2'b01 && guard__h574221 != 2'b10 && + guard__h574221 != 2'b11 || + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != + 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163 = - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && - coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[43]; + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 || + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != + 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h583842 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h592602 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h583842) + case (guard__h592602) 2'b0, 2'b01, 2'b10: - CASE_guard83842_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 = - coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[43]; + CASE_guard92602_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 = + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard83842_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 = - guard__h583842 == 2'b11 && - coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[43]; + CASE_guard92602_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 = + guard__h592602 != 2'b11 || + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h583842) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h592602) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165 = - coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[43]; + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165 = - (guard__h583842 == 2'b0) ? - coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h583842 == 2'b01 || guard__h583842 == 2'b10 || - guard__h583842 == 2'b11) && - coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[43]; + (guard__h592602 == 2'b0) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != + 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : + guard__h592602 != 2'b01 && guard__h592602 != 2'b10 && + guard__h592602 != 2'b11 || + coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != + 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165 = - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && - coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[43]; - endcase - end - always@(guard__h592911 or coreFix_fpuMulDivExe_0_regToExeQ$first) - begin - case (guard__h592911) - 2'b0, 2'b01, 2'b10: - CASE_guard92911_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166 = - coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[43]; - 2'd3: - CASE_guard92911_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166 = - guard__h592911 == 2'b11 && - coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[43]; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h592911) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd2, 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q167 = - coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[43]; - 3'd4: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q167 = - (guard__h592911 == 2'b0) ? - coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h592911 == 2'b01 || guard__h592911 == 2'b10 || - guard__h592911 == 2'b11) && - coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[43]; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q167 = - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && - coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[43]; - endcase - end - always@(guard__h583842 or coreFix_fpuMulDivExe_0_regToExeQ$first) - begin - case (guard__h583842) - 2'b0, 2'b01, 2'b10: - CASE_guard83842_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168 = - coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || - !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; - 2'd3: - CASE_guard83842_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168 = - guard__h583842 != 2'b11 || - coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || - !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h583842) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd2, 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q169 = - coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || - !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; - 3'd4: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q169 = - (guard__h583842 == 2'b0) ? - coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != - 32'hFFFFFFFF || - !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h583842 != 2'b01 && guard__h583842 != 2'b10 && - guard__h583842 != 2'b11 || - coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != - 32'hFFFFFFFF || - !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q169 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h592911 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h534917 or + _theResult___fst_exp__h542878 or _theResult___exp__h543533) begin - case (guard__h592911) - 2'b0, 2'b01, 2'b10: - CASE_guard92911_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 = - coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || - !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; - 2'd3: - CASE_guard92911_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 = - guard__h592911 != 2'b11 || - coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || - !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h592911) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd2, 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q171 = - coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || - !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; - 3'd4: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q171 = - (guard__h592911 == 2'b0) ? - coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != - 32'hFFFFFFFF || - !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h592911 != 2'b01 && guard__h592911 != 2'b10 && - guard__h592911 != 2'b11 || - coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != - 32'hFFFFFFFF || - !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q171 = - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 || - coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != - 32'hFFFFFFFF || - !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; - endcase - end - always@(guard__h574530 or coreFix_fpuMulDivExe_0_regToExeQ$first) - begin - case (guard__h574530) - 2'b0, 2'b01, 2'b10: - CASE_guard74530_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 = - coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || - !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; - 2'd3: - CASE_guard74530_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 = - guard__h574530 != 2'b11 || - coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || - !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h574530) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd2, 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q173 = - coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || - !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; - 3'd4: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q173 = - (guard__h574530 == 2'b0) ? - coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != - 32'hFFFFFFFF || - !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h574530 != 2'b01 && guard__h574530 != 2'b10 && - guard__h574530 != 2'b11 || - coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != - 32'hFFFFFFFF || - !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q173 = - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 || - coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != - 32'hFFFFFFFF || - !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; - endcase - end - always@(guard__h535226 or - _theResult___fst_exp__h543187 or _theResult___exp__h543842) - begin - case (guard__h535226) + case (guard__h534917) 2'b0: - CASE_guard35226_0b0_theResult___fst_exp43187_0_ETC__q183 = - _theResult___fst_exp__h543187; + CASE_guard34917_0b0_theResult___fst_exp42878_0_ETC__q175 = + _theResult___fst_exp__h542878; 2'b01, 2'b10, 2'b11: - CASE_guard35226_0b0_theResult___fst_exp43187_0_ETC__q183 = - _theResult___exp__h543842; + CASE_guard34917_0b0_theResult___fst_exp42878_0_ETC__q175 = + _theResult___exp__h543533; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h543187 or + _theResult___fst_exp__h542878 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10611 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10609 or - CASE_guard35226_0b0_theResult___fst_exp43187_0_ETC__q183) + CASE_guard34917_0b0_theResult___fst_exp42878_0_ETC__q175) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10615 = - _theResult___fst_exp__h543187; + _theResult___fst_exp__h542878; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10615 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10611; @@ -35849,49 +35499,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10609; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10615 = - CASE_guard35226_0b0_theResult___fst_exp43187_0_ETC__q183; + CASE_guard34917_0b0_theResult___fst_exp42878_0_ETC__q175; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10615 = 11'd0; endcase end - always@(guard__h535226 or - _theResult___fst_exp__h543187 or - out_exp__h543845 or _theResult___exp__h543842) + always@(guard__h534917 or + _theResult___fst_exp__h542878 or + out_exp__h543536 or _theResult___exp__h543533) begin - case (guard__h535226) + case (guard__h534917) 2'b0, 2'b01: - CASE_guard35226_0b0_theResult___fst_exp43187_0_ETC__q184 = - _theResult___fst_exp__h543187; + CASE_guard34917_0b0_theResult___fst_exp42878_0_ETC__q176 = + _theResult___fst_exp__h542878; 2'b10: - CASE_guard35226_0b0_theResult___fst_exp43187_0_ETC__q184 = - out_exp__h543845; + CASE_guard34917_0b0_theResult___fst_exp42878_0_ETC__q176 = + out_exp__h543536; 2'b11: - CASE_guard35226_0b0_theResult___fst_exp43187_0_ETC__q184 = - _theResult___exp__h543842; + CASE_guard34917_0b0_theResult___fst_exp42878_0_ETC__q176 = + _theResult___exp__h543533; endcase end - always@(guard__h544538 or - _theResult___fst_exp__h552764 or _theResult___exp__h553493) + always@(guard__h544229 or + _theResult___fst_exp__h552455 or _theResult___exp__h553184) begin - case (guard__h544538) + case (guard__h544229) 2'b0: - CASE_guard44538_0b0_theResult___fst_exp52764_0_ETC__q185 = - _theResult___fst_exp__h552764; + CASE_guard44229_0b0_theResult___fst_exp52455_0_ETC__q177 = + _theResult___fst_exp__h552455; 2'b01, 2'b10, 2'b11: - CASE_guard44538_0b0_theResult___fst_exp52764_0_ETC__q185 = - _theResult___exp__h553493; + CASE_guard44229_0b0_theResult___fst_exp52455_0_ETC__q177 = + _theResult___exp__h553184; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h552764 or + _theResult___fst_exp__h552455 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10649 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10647 or - CASE_guard44538_0b0_theResult___fst_exp52764_0_ETC__q185) + CASE_guard44229_0b0_theResult___fst_exp52455_0_ETC__q177) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10653 = - _theResult___fst_exp__h552764; + _theResult___fst_exp__h552455; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10653 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10649; @@ -35900,49 +35550,49 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10647; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10653 = - CASE_guard44538_0b0_theResult___fst_exp52764_0_ETC__q185; + CASE_guard44229_0b0_theResult___fst_exp52455_0_ETC__q177; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10653 = 11'd0; endcase end - always@(guard__h544538 or - _theResult___fst_exp__h552764 or - out_exp__h553496 or _theResult___exp__h553493) + always@(guard__h544229 or + _theResult___fst_exp__h552455 or + out_exp__h553187 or _theResult___exp__h553184) begin - case (guard__h544538) + case (guard__h544229) 2'b0, 2'b01: - CASE_guard44538_0b0_theResult___fst_exp52764_0_ETC__q186 = - _theResult___fst_exp__h552764; + CASE_guard44229_0b0_theResult___fst_exp52455_0_ETC__q178 = + _theResult___fst_exp__h552455; 2'b10: - CASE_guard44538_0b0_theResult___fst_exp52764_0_ETC__q186 = - out_exp__h553496; + CASE_guard44229_0b0_theResult___fst_exp52455_0_ETC__q178 = + out_exp__h553187; 2'b11: - CASE_guard44538_0b0_theResult___fst_exp52764_0_ETC__q186 = - _theResult___exp__h553493; + CASE_guard44229_0b0_theResult___fst_exp52455_0_ETC__q178 = + _theResult___exp__h553184; endcase end - always@(guard__h553607 or - _theResult___fst_exp__h561597 or _theResult___exp__h562277) + always@(guard__h553298 or + _theResult___fst_exp__h561288 or _theResult___exp__h561968) begin - case (guard__h553607) + case (guard__h553298) 2'b0: - CASE_guard53607_0b0_theResult___fst_exp61597_0_ETC__q187 = - _theResult___fst_exp__h561597; + CASE_guard53298_0b0_theResult___fst_exp61288_0_ETC__q179 = + _theResult___fst_exp__h561288; 2'b01, 2'b10, 2'b11: - CASE_guard53607_0b0_theResult___fst_exp61597_0_ETC__q187 = - _theResult___exp__h562277; + CASE_guard53298_0b0_theResult___fst_exp61288_0_ETC__q179 = + _theResult___exp__h561968; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h561597 or + _theResult___fst_exp__h561288 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10680 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10678 or - CASE_guard53607_0b0_theResult___fst_exp61597_0_ETC__q187) + CASE_guard53298_0b0_theResult___fst_exp61288_0_ETC__q179) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10684 = - _theResult___fst_exp__h561597; + _theResult___fst_exp__h561288; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10684 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10680; @@ -35951,100 +35601,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10678; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10684 = - CASE_guard53607_0b0_theResult___fst_exp61597_0_ETC__q187; + CASE_guard53298_0b0_theResult___fst_exp61288_0_ETC__q179; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10684 = 11'd0; endcase end - always@(guard__h553607 or - _theResult___fst_exp__h561597 or - out_exp__h562280 or _theResult___exp__h562277) + always@(guard__h553298 or + _theResult___fst_exp__h561288 or + out_exp__h561971 or _theResult___exp__h561968) begin - case (guard__h553607) + case (guard__h553298) 2'b0, 2'b01: - CASE_guard53607_0b0_theResult___fst_exp61597_0_ETC__q188 = - _theResult___fst_exp__h561597; + CASE_guard53298_0b0_theResult___fst_exp61288_0_ETC__q180 = + _theResult___fst_exp__h561288; 2'b10: - CASE_guard53607_0b0_theResult___fst_exp61597_0_ETC__q188 = - out_exp__h562280; + CASE_guard53298_0b0_theResult___fst_exp61288_0_ETC__q180 = + out_exp__h561971; 2'b11: - CASE_guard53607_0b0_theResult___fst_exp61597_0_ETC__q188 = - _theResult___exp__h562277; + CASE_guard53298_0b0_theResult___fst_exp61288_0_ETC__q180 = + _theResult___exp__h561968; endcase end - always@(guard__h583842 or - _theResult___fst_exp__h592068 or _theResult___exp__h592797) + always@(guard__h592602 or + _theResult___fst_exp__h600592 or _theResult___exp__h601272) begin - case (guard__h583842) + case (guard__h592602) 2'b0: - CASE_guard83842_0b0_theResult___fst_exp92068_0_ETC__q189 = - _theResult___fst_exp__h592068; + CASE_guard92602_0b0_theResult___fst_exp00592_0_ETC__q181 = + _theResult___fst_exp__h600592; 2'b01, 2'b10, 2'b11: - CASE_guard83842_0b0_theResult___fst_exp92068_0_ETC__q189 = - _theResult___exp__h592797; + CASE_guard92602_0b0_theResult___fst_exp00592_0_ETC__q181 = + _theResult___exp__h601272; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h592068 or - IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9879 or - IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9877 or - CASE_guard83842_0b0_theResult___fst_exp92068_0_ETC__q189) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd1: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9883 = - _theResult___fst_exp__h592068; - 3'd2: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9883 = - IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9879; - 3'd3: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9883 = - IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9877; - 3'd4: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9883 = - CASE_guard83842_0b0_theResult___fst_exp92068_0_ETC__q189; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9883 = - 11'd0; - endcase - end - always@(guard__h583842 or - _theResult___fst_exp__h592068 or - out_exp__h592800 or _theResult___exp__h592797) - begin - case (guard__h583842) - 2'b0, 2'b01: - CASE_guard83842_0b0_theResult___fst_exp92068_0_ETC__q190 = - _theResult___fst_exp__h592068; - 2'b10: - CASE_guard83842_0b0_theResult___fst_exp92068_0_ETC__q190 = - out_exp__h592800; - 2'b11: - CASE_guard83842_0b0_theResult___fst_exp92068_0_ETC__q190 = - _theResult___exp__h592797; - endcase - end - always@(guard__h592911 or - _theResult___fst_exp__h600901 or _theResult___exp__h601581) - begin - case (guard__h592911) - 2'b0: - CASE_guard92911_0b0_theResult___fst_exp00901_0_ETC__q191 = - _theResult___fst_exp__h600901; - 2'b01, 2'b10, 2'b11: - CASE_guard92911_0b0_theResult___fst_exp00901_0_ETC__q191 = - _theResult___exp__h601581; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h600901 or + _theResult___fst_exp__h600592 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9910 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9908 or - CASE_guard92911_0b0_theResult___fst_exp00901_0_ETC__q191) + CASE_guard92602_0b0_theResult___fst_exp00592_0_ETC__q181) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9914 = - _theResult___fst_exp__h600901; + _theResult___fst_exp__h600592; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9914 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9910; @@ -36053,301 +35652,352 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9908; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9914 = - CASE_guard92911_0b0_theResult___fst_exp00901_0_ETC__q191; + CASE_guard92602_0b0_theResult___fst_exp00592_0_ETC__q181; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9914 = 11'd0; endcase end - always@(guard__h592911 or - _theResult___fst_exp__h600901 or - out_exp__h601584 or _theResult___exp__h601581) + always@(guard__h592602 or + _theResult___fst_exp__h600592 or + out_exp__h601275 or _theResult___exp__h601272) begin - case (guard__h592911) + case (guard__h592602) 2'b0, 2'b01: - CASE_guard92911_0b0_theResult___fst_exp00901_0_ETC__q192 = - _theResult___fst_exp__h600901; + CASE_guard92602_0b0_theResult___fst_exp00592_0_ETC__q182 = + _theResult___fst_exp__h600592; 2'b10: - CASE_guard92911_0b0_theResult___fst_exp00901_0_ETC__q192 = - out_exp__h601584; + CASE_guard92602_0b0_theResult___fst_exp00592_0_ETC__q182 = + out_exp__h601275; 2'b11: - CASE_guard92911_0b0_theResult___fst_exp00901_0_ETC__q192 = - _theResult___exp__h601581; + CASE_guard92602_0b0_theResult___fst_exp00592_0_ETC__q182 = + _theResult___exp__h601272; endcase end - always@(guard__h535226 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h583533 or + _theResult___fst_exp__h591759 or _theResult___exp__h592488) begin - case (guard__h535226) - 2'b0, 2'b01, 2'b10: - CASE_guard35226_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 = - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - 2'd3: - CASE_guard35226_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 = - guard__h535226 == 2'b11 && - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h535226) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd2, 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 = - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - 3'd4: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 = - (guard__h535226 == 2'b0) ? - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h535226 == 2'b01 || guard__h535226 == 2'b10 || - guard__h535226 == 2'b11) && - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 = - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - endcase - end - always@(guard__h553607 or coreFix_fpuMulDivExe_0_regToExeQ$first) - begin - case (guard__h553607) - 2'b0, 2'b01, 2'b10: - CASE_guard53607_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 = - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - 2'd3: - CASE_guard53607_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 = - guard__h553607 == 2'b11 && - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h553607) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd2, 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 = - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - 3'd4: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 = - (guard__h553607 == 2'b0) ? - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h553607 == 2'b01 || guard__h553607 == 2'b10 || - guard__h553607 == 2'b11) && - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 = - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - endcase - end - always@(guard__h544538 or coreFix_fpuMulDivExe_0_regToExeQ$first) - begin - case (guard__h544538) - 2'b0, 2'b01, 2'b10: - CASE_guard44538_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197 = - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - 2'd3: - CASE_guard44538_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197 = - guard__h544538 == 2'b11 && - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h544538) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd2, 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q198 = - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - 3'd4: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q198 = - (guard__h544538 == 2'b0) ? - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h544538 == 2'b01 || guard__h544538 == 2'b10 || - guard__h544538 == 2'b11) && - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q198 = - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - endcase - end - always@(guard__h544538 or coreFix_fpuMulDivExe_0_regToExeQ$first) - begin - case (guard__h544538) - 2'b0, 2'b01, 2'b10: - CASE_guard44538_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199 = - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != - 32'hFFFFFFFF || - !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - 2'd3: - CASE_guard44538_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199 = - guard__h544538 != 2'b11 || - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != - 32'hFFFFFFFF || - !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h544538) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd2, 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q200 = - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != - 32'hFFFFFFFF || - !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - 3'd4: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q200 = - (guard__h544538 == 2'b0) ? - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != - 32'hFFFFFFFF || - !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h544538 != 2'b01 && guard__h544538 != 2'b10 && - guard__h544538 != 2'b11 || - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != - 32'hFFFFFFFF || - !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q200 = - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 || - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != - 32'hFFFFFFFF || - !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - endcase - end - always@(guard__h553607 or coreFix_fpuMulDivExe_0_regToExeQ$first) - begin - case (guard__h553607) - 2'b0, 2'b01, 2'b10: - CASE_guard53607_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 = - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != - 32'hFFFFFFFF || - !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - 2'd3: - CASE_guard53607_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 = - guard__h553607 != 2'b11 || - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != - 32'hFFFFFFFF || - !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h553607) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd2, 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202 = - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != - 32'hFFFFFFFF || - !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - 3'd4: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202 = - (guard__h553607 == 2'b0) ? - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != - 32'hFFFFFFFF || - !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h553607 != 2'b01 && guard__h553607 != 2'b10 && - guard__h553607 != 2'b11 || - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != - 32'hFFFFFFFF || - !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202 = - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 || - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != - 32'hFFFFFFFF || - !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - endcase - end - always@(guard__h535226 or coreFix_fpuMulDivExe_0_regToExeQ$first) - begin - case (guard__h535226) - 2'b0, 2'b01, 2'b10: - CASE_guard35226_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 = - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != - 32'hFFFFFFFF || - !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - 2'd3: - CASE_guard35226_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 = - guard__h535226 != 2'b11 || - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != - 32'hFFFFFFFF || - !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h535226) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd2, 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q204 = - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != - 32'hFFFFFFFF || - !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - 3'd4: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q204 = - (guard__h535226 == 2'b0) ? - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != - 32'hFFFFFFFF || - !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h535226 != 2'b01 && guard__h535226 != 2'b10 && - guard__h535226 != 2'b11 || - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != - 32'hFFFFFFFF || - !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q204 = - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 || - coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != - 32'hFFFFFFFF || - !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; - endcase - end - always@(guard__h535226 or - _theResult___snd__h543138 or _theResult___sfd__h543843) - begin - case (guard__h535226) + case (guard__h583533) 2'b0: - CASE_guard35226_0b0_theResult___snd43138_BITS__ETC__q205 = - _theResult___snd__h543138[56:5]; + CASE_guard83533_0b0_theResult___fst_exp91759_0_ETC__q183 = + _theResult___fst_exp__h591759; 2'b01, 2'b10, 2'b11: - CASE_guard35226_0b0_theResult___snd43138_BITS__ETC__q205 = - _theResult___sfd__h543843; + CASE_guard83533_0b0_theResult___fst_exp91759_0_ETC__q183 = + _theResult___exp__h592488; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h543138 or + _theResult___fst_exp__h591759 or + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9879 or + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9877 or + CASE_guard83533_0b0_theResult___fst_exp91759_0_ETC__q183) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd1: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9883 = + _theResult___fst_exp__h591759; + 3'd2: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9883 = + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9879; + 3'd3: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9883 = + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9877; + 3'd4: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9883 = + CASE_guard83533_0b0_theResult___fst_exp91759_0_ETC__q183; + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9883 = + 11'd0; + endcase + end + always@(guard__h583533 or + _theResult___fst_exp__h591759 or + out_exp__h592491 or _theResult___exp__h592488) + begin + case (guard__h583533) + 2'b0, 2'b01: + CASE_guard83533_0b0_theResult___fst_exp91759_0_ETC__q184 = + _theResult___fst_exp__h591759; + 2'b10: + CASE_guard83533_0b0_theResult___fst_exp91759_0_ETC__q184 = + out_exp__h592491; + 2'b11: + CASE_guard83533_0b0_theResult___fst_exp91759_0_ETC__q184 = + _theResult___exp__h592488; + endcase + end + always@(guard__h534917 or coreFix_fpuMulDivExe_0_regToExeQ$first) + begin + case (guard__h534917) + 2'b0, 2'b01, 2'b10: + CASE_guard34917_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185 = + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + 2'd3: + CASE_guard34917_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185 = + guard__h534917 == 2'b11 && + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h534917) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd2, 3'd3: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q186 = + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + 3'd4: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q186 = + (guard__h534917 == 2'b0) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107] : + (guard__h534917 == 2'b01 || guard__h534917 == 2'b10 || + guard__h534917 == 2'b11) && + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q186 = + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + endcase + end + always@(guard__h544229 or coreFix_fpuMulDivExe_0_regToExeQ$first) + begin + case (guard__h544229) + 2'b0, 2'b01, 2'b10: + CASE_guard44229_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187 = + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + 2'd3: + CASE_guard44229_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187 = + guard__h544229 == 2'b11 && + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h544229) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd2, 3'd3: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q188 = + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + 3'd4: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q188 = + (guard__h544229 == 2'b0) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107] : + (guard__h544229 == 2'b01 || guard__h544229 == 2'b10 || + guard__h544229 == 2'b11) && + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q188 = + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + endcase + end + always@(guard__h553298 or coreFix_fpuMulDivExe_0_regToExeQ$first) + begin + case (guard__h553298) + 2'b0, 2'b01, 2'b10: + CASE_guard53298_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189 = + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + 2'd3: + CASE_guard53298_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189 = + guard__h553298 == 2'b11 && + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h553298) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd2, 3'd3: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q190 = + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + 3'd4: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q190 = + (guard__h553298 == 2'b0) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107] : + (guard__h553298 == 2'b01 || guard__h553298 == 2'b10 || + guard__h553298 == 2'b11) && + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q190 = + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + endcase + end + always@(guard__h544229 or coreFix_fpuMulDivExe_0_regToExeQ$first) + begin + case (guard__h544229) + 2'b0, 2'b01, 2'b10: + CASE_guard44229_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191 = + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + 2'd3: + CASE_guard44229_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191 = + guard__h544229 != 2'b11 || + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h544229) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd2, 3'd3: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q192 = + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + 3'd4: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q192 = + (guard__h544229 == 2'b0) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : + guard__h544229 != 2'b01 && guard__h544229 != 2'b10 && + guard__h544229 != 2'b11 || + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q192 = + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 || + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + endcase + end + always@(guard__h553298 or coreFix_fpuMulDivExe_0_regToExeQ$first) + begin + case (guard__h553298) + 2'b0, 2'b01, 2'b10: + CASE_guard53298_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 = + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + 2'd3: + CASE_guard53298_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 = + guard__h553298 != 2'b11 || + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h553298) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd2, 3'd3: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 = + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + 3'd4: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 = + (guard__h553298 == 2'b0) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : + guard__h553298 != 2'b01 && guard__h553298 != 2'b10 && + guard__h553298 != 2'b11 || + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 = + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 || + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + endcase + end + always@(guard__h534917 or coreFix_fpuMulDivExe_0_regToExeQ$first) + begin + case (guard__h534917) + 2'b0, 2'b01, 2'b10: + CASE_guard34917_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 = + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + 2'd3: + CASE_guard34917_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 = + guard__h534917 != 2'b11 || + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h534917) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd2, 3'd3: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 = + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + 3'd4: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 = + (guard__h534917 == 2'b0) ? + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : + guard__h534917 != 2'b01 && guard__h534917 != 2'b10 && + guard__h534917 != 2'b11 || + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 = + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 || + coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != + 32'hFFFFFFFF || + !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; + endcase + end + always@(guard__h534917 or + _theResult___snd__h542829 or _theResult___sfd__h543534) + begin + case (guard__h534917) + 2'b0: + CASE_guard34917_0b0_theResult___snd42829_BITS__ETC__q197 = + _theResult___snd__h542829[56:5]; + 2'b01, 2'b10, 2'b11: + CASE_guard34917_0b0_theResult___snd42829_BITS__ETC__q197 = + _theResult___sfd__h543534; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or + _theResult___snd__h542829 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10706 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10704 or - CASE_guard35226_0b0_theResult___snd43138_BITS__ETC__q205) + CASE_guard34917_0b0_theResult___snd42829_BITS__ETC__q197) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10710 = - _theResult___snd__h543138[56:5]; + _theResult___snd__h542829[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10710 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10706; @@ -36356,48 +36006,48 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10704; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10710 = - CASE_guard35226_0b0_theResult___snd43138_BITS__ETC__q205; + CASE_guard34917_0b0_theResult___snd42829_BITS__ETC__q197; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10710 = 52'd0; endcase end - always@(guard__h535226 or - _theResult___snd__h543138 or - out_sfd__h543846 or _theResult___sfd__h543843) + always@(guard__h534917 or + _theResult___snd__h542829 or + out_sfd__h543537 or _theResult___sfd__h543534) begin - case (guard__h535226) + case (guard__h534917) 2'b0, 2'b01: - CASE_guard35226_0b0_theResult___snd43138_BITS__ETC__q206 = - _theResult___snd__h543138[56:5]; + CASE_guard34917_0b0_theResult___snd42829_BITS__ETC__q198 = + _theResult___snd__h542829[56:5]; 2'b10: - CASE_guard35226_0b0_theResult___snd43138_BITS__ETC__q206 = - out_sfd__h543846; + CASE_guard34917_0b0_theResult___snd42829_BITS__ETC__q198 = + out_sfd__h543537; 2'b11: - CASE_guard35226_0b0_theResult___snd43138_BITS__ETC__q206 = - _theResult___sfd__h543843; + CASE_guard34917_0b0_theResult___snd42829_BITS__ETC__q198 = + _theResult___sfd__h543534; endcase end - always@(guard__h544538 or sfdin__h552758 or _theResult___sfd__h553494) + always@(guard__h544229 or sfdin__h552449 or _theResult___sfd__h553185) begin - case (guard__h544538) + case (guard__h544229) 2'b0: - CASE_guard44538_0b0_sfdin52758_BITS_56_TO_5_0b_ETC__q207 = - sfdin__h552758[56:5]; + CASE_guard44229_0b0_sfdin52449_BITS_56_TO_5_0b_ETC__q199 = + sfdin__h552449[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard44538_0b0_sfdin52758_BITS_56_TO_5_0b_ETC__q207 = - _theResult___sfd__h553494; + CASE_guard44229_0b0_sfdin52449_BITS_56_TO_5_0b_ETC__q199 = + _theResult___sfd__h553185; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h552758 or + sfdin__h552449 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10732 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10730 or - CASE_guard44538_0b0_sfdin52758_BITS_56_TO_5_0b_ETC__q207) + CASE_guard44229_0b0_sfdin52449_BITS_56_TO_5_0b_ETC__q199) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10736 = - sfdin__h552758[56:5]; + sfdin__h552449[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10736 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10732; @@ -36406,48 +36056,48 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10730; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10736 = - CASE_guard44538_0b0_sfdin52758_BITS_56_TO_5_0b_ETC__q207; + CASE_guard44229_0b0_sfdin52449_BITS_56_TO_5_0b_ETC__q199; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10736 = 52'd0; endcase end - always@(guard__h544538 or - sfdin__h552758 or out_sfd__h553497 or _theResult___sfd__h553494) + always@(guard__h544229 or + sfdin__h552449 or out_sfd__h553188 or _theResult___sfd__h553185) begin - case (guard__h544538) + case (guard__h544229) 2'b0, 2'b01: - CASE_guard44538_0b0_sfdin52758_BITS_56_TO_5_0b_ETC__q208 = - sfdin__h552758[56:5]; + CASE_guard44229_0b0_sfdin52449_BITS_56_TO_5_0b_ETC__q200 = + sfdin__h552449[56:5]; 2'b10: - CASE_guard44538_0b0_sfdin52758_BITS_56_TO_5_0b_ETC__q208 = - out_sfd__h553497; + CASE_guard44229_0b0_sfdin52449_BITS_56_TO_5_0b_ETC__q200 = + out_sfd__h553188; 2'b11: - CASE_guard44538_0b0_sfdin52758_BITS_56_TO_5_0b_ETC__q208 = - _theResult___sfd__h553494; + CASE_guard44229_0b0_sfdin52449_BITS_56_TO_5_0b_ETC__q200 = + _theResult___sfd__h553185; endcase end - always@(guard__h553607 or - _theResult___snd__h561543 or _theResult___sfd__h562278) + always@(guard__h553298 or + _theResult___snd__h561234 or _theResult___sfd__h561969) begin - case (guard__h553607) + case (guard__h553298) 2'b0: - CASE_guard53607_0b0_theResult___snd61543_BITS__ETC__q209 = - _theResult___snd__h561543[56:5]; + CASE_guard53298_0b0_theResult___snd61234_BITS__ETC__q201 = + _theResult___snd__h561234[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard53607_0b0_theResult___snd61543_BITS__ETC__q209 = - _theResult___sfd__h562278; + CASE_guard53298_0b0_theResult___snd61234_BITS__ETC__q201 = + _theResult___sfd__h561969; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h561543 or + _theResult___snd__h561234 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10751 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10749 or - CASE_guard53607_0b0_theResult___snd61543_BITS__ETC__q209) + CASE_guard53298_0b0_theResult___snd61234_BITS__ETC__q201) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10755 = - _theResult___snd__h561543[56:5]; + _theResult___snd__h561234[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10755 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10751; @@ -36456,49 +36106,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10749; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10755 = - CASE_guard53607_0b0_theResult___snd61543_BITS__ETC__q209; + CASE_guard53298_0b0_theResult___snd61234_BITS__ETC__q201; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10755 = 52'd0; endcase end - always@(guard__h553607 or - _theResult___snd__h561543 or - out_sfd__h562281 or _theResult___sfd__h562278) + always@(guard__h553298 or + _theResult___snd__h561234 or + out_sfd__h561972 or _theResult___sfd__h561969) begin - case (guard__h553607) + case (guard__h553298) 2'b0, 2'b01: - CASE_guard53607_0b0_theResult___snd61543_BITS__ETC__q210 = - _theResult___snd__h561543[56:5]; + CASE_guard53298_0b0_theResult___snd61234_BITS__ETC__q202 = + _theResult___snd__h561234[56:5]; 2'b10: - CASE_guard53607_0b0_theResult___snd61543_BITS__ETC__q210 = - out_sfd__h562281; + CASE_guard53298_0b0_theResult___snd61234_BITS__ETC__q202 = + out_sfd__h561972; 2'b11: - CASE_guard53607_0b0_theResult___snd61543_BITS__ETC__q210 = - _theResult___sfd__h562278; + CASE_guard53298_0b0_theResult___snd61234_BITS__ETC__q202 = + _theResult___sfd__h561969; endcase end - always@(guard__h505685 or - _theResult___fst_exp__h513911 or _theResult___exp__h514640) + always@(guard__h505376 or + _theResult___fst_exp__h513602 or _theResult___exp__h514331) begin - case (guard__h505685) + case (guard__h505376) 2'b0: - CASE_guard05685_0b0_theResult___fst_exp13911_0_ETC__q211 = - _theResult___fst_exp__h513911; + CASE_guard05376_0b0_theResult___fst_exp13602_0_ETC__q203 = + _theResult___fst_exp__h513602; 2'b01, 2'b10, 2'b11: - CASE_guard05685_0b0_theResult___fst_exp13911_0_ETC__q211 = - _theResult___exp__h514640; + CASE_guard05376_0b0_theResult___fst_exp13602_0_ETC__q203 = + _theResult___exp__h514331; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h513911 or + _theResult___fst_exp__h513602 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9169 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9167 or - CASE_guard05685_0b0_theResult___fst_exp13911_0_ETC__q211) + CASE_guard05376_0b0_theResult___fst_exp13602_0_ETC__q203) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9173 = - _theResult___fst_exp__h513911; + _theResult___fst_exp__h513602; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9173 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9169; @@ -36507,100 +36157,49 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9167; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9173 = - CASE_guard05685_0b0_theResult___fst_exp13911_0_ETC__q211; + CASE_guard05376_0b0_theResult___fst_exp13602_0_ETC__q203; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9173 = 11'd0; endcase end - always@(guard__h505685 or - _theResult___fst_exp__h513911 or - out_exp__h514643 or _theResult___exp__h514640) + always@(guard__h505376 or + _theResult___fst_exp__h513602 or + out_exp__h514334 or _theResult___exp__h514331) begin - case (guard__h505685) + case (guard__h505376) 2'b0, 2'b01: - CASE_guard05685_0b0_theResult___fst_exp13911_0_ETC__q212 = - _theResult___fst_exp__h513911; + CASE_guard05376_0b0_theResult___fst_exp13602_0_ETC__q204 = + _theResult___fst_exp__h513602; 2'b10: - CASE_guard05685_0b0_theResult___fst_exp13911_0_ETC__q212 = - out_exp__h514643; + CASE_guard05376_0b0_theResult___fst_exp13602_0_ETC__q204 = + out_exp__h514334; 2'b11: - CASE_guard05685_0b0_theResult___fst_exp13911_0_ETC__q212 = - _theResult___exp__h514640; + CASE_guard05376_0b0_theResult___fst_exp13602_0_ETC__q204 = + _theResult___exp__h514331; endcase end - always@(guard__h514754 or - _theResult___fst_exp__h522744 or _theResult___exp__h523424) + always@(guard__h496064 or + _theResult___snd__h503976 or _theResult___sfd__h504681) begin - case (guard__h514754) + case (guard__h496064) 2'b0: - CASE_guard14754_0b0_theResult___fst_exp22744_0_ETC__q213 = - _theResult___fst_exp__h522744; + CASE_guard96064_0b0_theResult___snd03976_BITS__ETC__q205 = + _theResult___snd__h503976[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard14754_0b0_theResult___fst_exp22744_0_ETC__q213 = - _theResult___exp__h523424; + CASE_guard96064_0b0_theResult___snd03976_BITS__ETC__q205 = + _theResult___sfd__h504681; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h522744 or - IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9200 or - IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9198 or - CASE_guard14754_0b0_theResult___fst_exp22744_0_ETC__q213) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd1: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9204 = - _theResult___fst_exp__h522744; - 3'd2: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9204 = - IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9200; - 3'd3: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9204 = - IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9198; - 3'd4: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9204 = - CASE_guard14754_0b0_theResult___fst_exp22744_0_ETC__q213; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9204 = - 11'd0; - endcase - end - always@(guard__h514754 or - _theResult___fst_exp__h522744 or - out_exp__h523427 or _theResult___exp__h523424) - begin - case (guard__h514754) - 2'b0, 2'b01: - CASE_guard14754_0b0_theResult___fst_exp22744_0_ETC__q214 = - _theResult___fst_exp__h522744; - 2'b10: - CASE_guard14754_0b0_theResult___fst_exp22744_0_ETC__q214 = - out_exp__h523427; - 2'b11: - CASE_guard14754_0b0_theResult___fst_exp22744_0_ETC__q214 = - _theResult___exp__h523424; - endcase - end - always@(guard__h496373 or - _theResult___snd__h504285 or _theResult___sfd__h504990) - begin - case (guard__h496373) - 2'b0: - CASE_guard96373_0b0_theResult___snd04285_BITS__ETC__q215 = - _theResult___snd__h504285[56:5]; - 2'b01, 2'b10, 2'b11: - CASE_guard96373_0b0_theResult___snd04285_BITS__ETC__q215 = - _theResult___sfd__h504990; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h504285 or + _theResult___snd__h503976 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9226 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9224 or - CASE_guard96373_0b0_theResult___snd04285_BITS__ETC__q215) + CASE_guard96064_0b0_theResult___snd03976_BITS__ETC__q205) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9230 = - _theResult___snd__h504285[56:5]; + _theResult___snd__h503976[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9230 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9226; @@ -36609,48 +36208,99 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9224; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9230 = - CASE_guard96373_0b0_theResult___snd04285_BITS__ETC__q215; + CASE_guard96064_0b0_theResult___snd03976_BITS__ETC__q205; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9230 = 52'd0; endcase end - always@(guard__h496373 or - _theResult___snd__h504285 or - out_sfd__h504993 or _theResult___sfd__h504990) + always@(guard__h496064 or + _theResult___snd__h503976 or + out_sfd__h504684 or _theResult___sfd__h504681) begin - case (guard__h496373) + case (guard__h496064) 2'b0, 2'b01: - CASE_guard96373_0b0_theResult___snd04285_BITS__ETC__q216 = - _theResult___snd__h504285[56:5]; + CASE_guard96064_0b0_theResult___snd03976_BITS__ETC__q206 = + _theResult___snd__h503976[56:5]; 2'b10: - CASE_guard96373_0b0_theResult___snd04285_BITS__ETC__q216 = - out_sfd__h504993; + CASE_guard96064_0b0_theResult___snd03976_BITS__ETC__q206 = + out_sfd__h504684; 2'b11: - CASE_guard96373_0b0_theResult___snd04285_BITS__ETC__q216 = - _theResult___sfd__h504990; + CASE_guard96064_0b0_theResult___snd03976_BITS__ETC__q206 = + _theResult___sfd__h504681; endcase end - always@(guard__h505685 or sfdin__h513905 or _theResult___sfd__h514641) + always@(guard__h514445 or + _theResult___fst_exp__h522435 or _theResult___exp__h523115) begin - case (guard__h505685) + case (guard__h514445) 2'b0: - CASE_guard05685_0b0_sfdin13905_BITS_56_TO_5_0b_ETC__q217 = - sfdin__h513905[56:5]; + CASE_guard14445_0b0_theResult___fst_exp22435_0_ETC__q207 = + _theResult___fst_exp__h522435; 2'b01, 2'b10, 2'b11: - CASE_guard05685_0b0_sfdin13905_BITS_56_TO_5_0b_ETC__q217 = - _theResult___sfd__h514641; + CASE_guard14445_0b0_theResult___fst_exp22435_0_ETC__q207 = + _theResult___exp__h523115; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h513905 or + _theResult___fst_exp__h522435 or + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9200 or + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9198 or + CASE_guard14445_0b0_theResult___fst_exp22435_0_ETC__q207) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd1: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9204 = + _theResult___fst_exp__h522435; + 3'd2: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9204 = + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9200; + 3'd3: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9204 = + IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9198; + 3'd4: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9204 = + CASE_guard14445_0b0_theResult___fst_exp22435_0_ETC__q207; + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9204 = + 11'd0; + endcase + end + always@(guard__h514445 or + _theResult___fst_exp__h522435 or + out_exp__h523118 or _theResult___exp__h523115) + begin + case (guard__h514445) + 2'b0, 2'b01: + CASE_guard14445_0b0_theResult___fst_exp22435_0_ETC__q208 = + _theResult___fst_exp__h522435; + 2'b10: + CASE_guard14445_0b0_theResult___fst_exp22435_0_ETC__q208 = + out_exp__h523118; + 2'b11: + CASE_guard14445_0b0_theResult___fst_exp22435_0_ETC__q208 = + _theResult___exp__h523115; + endcase + end + always@(guard__h505376 or sfdin__h513596 or _theResult___sfd__h514332) + begin + case (guard__h505376) + 2'b0: + CASE_guard05376_0b0_sfdin13596_BITS_56_TO_5_0b_ETC__q209 = + sfdin__h513596[56:5]; + 2'b01, 2'b10, 2'b11: + CASE_guard05376_0b0_sfdin13596_BITS_56_TO_5_0b_ETC__q209 = + _theResult___sfd__h514332; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or + sfdin__h513596 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9253 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9251 or - CASE_guard05685_0b0_sfdin13905_BITS_56_TO_5_0b_ETC__q217) + CASE_guard05376_0b0_sfdin13596_BITS_56_TO_5_0b_ETC__q209) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9257 = - sfdin__h513905[56:5]; + sfdin__h513596[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9257 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9253; @@ -36659,48 +36309,48 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9251; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9257 = - CASE_guard05685_0b0_sfdin13905_BITS_56_TO_5_0b_ETC__q217; + CASE_guard05376_0b0_sfdin13596_BITS_56_TO_5_0b_ETC__q209; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9257 = 52'd0; endcase end - always@(guard__h505685 or - sfdin__h513905 or out_sfd__h514644 or _theResult___sfd__h514641) + always@(guard__h505376 or + sfdin__h513596 or out_sfd__h514335 or _theResult___sfd__h514332) begin - case (guard__h505685) + case (guard__h505376) 2'b0, 2'b01: - CASE_guard05685_0b0_sfdin13905_BITS_56_TO_5_0b_ETC__q218 = - sfdin__h513905[56:5]; + CASE_guard05376_0b0_sfdin13596_BITS_56_TO_5_0b_ETC__q210 = + sfdin__h513596[56:5]; 2'b10: - CASE_guard05685_0b0_sfdin13905_BITS_56_TO_5_0b_ETC__q218 = - out_sfd__h514644; + CASE_guard05376_0b0_sfdin13596_BITS_56_TO_5_0b_ETC__q210 = + out_sfd__h514335; 2'b11: - CASE_guard05685_0b0_sfdin13905_BITS_56_TO_5_0b_ETC__q218 = - _theResult___sfd__h514641; + CASE_guard05376_0b0_sfdin13596_BITS_56_TO_5_0b_ETC__q210 = + _theResult___sfd__h514332; endcase end - always@(guard__h514754 or - _theResult___snd__h522690 or _theResult___sfd__h523425) + always@(guard__h514445 or + _theResult___snd__h522381 or _theResult___sfd__h523116) begin - case (guard__h514754) + case (guard__h514445) 2'b0: - CASE_guard14754_0b0_theResult___snd22690_BITS__ETC__q219 = - _theResult___snd__h522690[56:5]; + CASE_guard14445_0b0_theResult___snd22381_BITS__ETC__q211 = + _theResult___snd__h522381[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard14754_0b0_theResult___snd22690_BITS__ETC__q219 = - _theResult___sfd__h523425; + CASE_guard14445_0b0_theResult___snd22381_BITS__ETC__q211 = + _theResult___sfd__h523116; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h522690 or + _theResult___snd__h522381 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9272 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9270 or - CASE_guard14754_0b0_theResult___snd22690_BITS__ETC__q219) + CASE_guard14445_0b0_theResult___snd22381_BITS__ETC__q211) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9276 = - _theResult___snd__h522690[56:5]; + _theResult___snd__h522381[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9276 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9272; @@ -36709,49 +36359,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9270; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9276 = - CASE_guard14754_0b0_theResult___snd22690_BITS__ETC__q219; + CASE_guard14445_0b0_theResult___snd22381_BITS__ETC__q211; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9276 = 52'd0; endcase end - always@(guard__h514754 or - _theResult___snd__h522690 or - out_sfd__h523428 or _theResult___sfd__h523425) + always@(guard__h514445 or + _theResult___snd__h522381 or + out_sfd__h523119 or _theResult___sfd__h523116) begin - case (guard__h514754) + case (guard__h514445) 2'b0, 2'b01: - CASE_guard14754_0b0_theResult___snd22690_BITS__ETC__q220 = - _theResult___snd__h522690[56:5]; + CASE_guard14445_0b0_theResult___snd22381_BITS__ETC__q212 = + _theResult___snd__h522381[56:5]; 2'b10: - CASE_guard14754_0b0_theResult___snd22690_BITS__ETC__q220 = - out_sfd__h523428; + CASE_guard14445_0b0_theResult___snd22381_BITS__ETC__q212 = + out_sfd__h523119; 2'b11: - CASE_guard14754_0b0_theResult___snd22690_BITS__ETC__q220 = - _theResult___sfd__h523425; + CASE_guard14445_0b0_theResult___snd22381_BITS__ETC__q212 = + _theResult___sfd__h523116; endcase end - always@(guard__h574530 or - _theResult___snd__h582442 or _theResult___sfd__h583147) + always@(guard__h574221 or + _theResult___snd__h582133 or _theResult___sfd__h582838) begin - case (guard__h574530) + case (guard__h574221) 2'b0: - CASE_guard74530_0b0_theResult___snd82442_BITS__ETC__q221 = - _theResult___snd__h582442[56:5]; + CASE_guard74221_0b0_theResult___snd82133_BITS__ETC__q213 = + _theResult___snd__h582133[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard74530_0b0_theResult___snd82442_BITS__ETC__q221 = - _theResult___sfd__h583147; + CASE_guard74221_0b0_theResult___snd82133_BITS__ETC__q213 = + _theResult___sfd__h582838; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h582442 or + _theResult___snd__h582133 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9936 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9934 or - CASE_guard74530_0b0_theResult___snd82442_BITS__ETC__q221) + CASE_guard74221_0b0_theResult___snd82133_BITS__ETC__q213) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9940 = - _theResult___snd__h582442[56:5]; + _theResult___snd__h582133[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9940 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9936; @@ -36760,48 +36410,48 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9934; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9940 = - CASE_guard74530_0b0_theResult___snd82442_BITS__ETC__q221; + CASE_guard74221_0b0_theResult___snd82133_BITS__ETC__q213; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9940 = 52'd0; endcase end - always@(guard__h574530 or - _theResult___snd__h582442 or - out_sfd__h583150 or _theResult___sfd__h583147) + always@(guard__h574221 or + _theResult___snd__h582133 or + out_sfd__h582841 or _theResult___sfd__h582838) begin - case (guard__h574530) + case (guard__h574221) 2'b0, 2'b01: - CASE_guard74530_0b0_theResult___snd82442_BITS__ETC__q222 = - _theResult___snd__h582442[56:5]; + CASE_guard74221_0b0_theResult___snd82133_BITS__ETC__q214 = + _theResult___snd__h582133[56:5]; 2'b10: - CASE_guard74530_0b0_theResult___snd82442_BITS__ETC__q222 = - out_sfd__h583150; + CASE_guard74221_0b0_theResult___snd82133_BITS__ETC__q214 = + out_sfd__h582841; 2'b11: - CASE_guard74530_0b0_theResult___snd82442_BITS__ETC__q222 = - _theResult___sfd__h583147; + CASE_guard74221_0b0_theResult___snd82133_BITS__ETC__q214 = + _theResult___sfd__h582838; endcase end - always@(guard__h583842 or sfdin__h592062 or _theResult___sfd__h592798) + always@(guard__h583533 or sfdin__h591753 or _theResult___sfd__h592489) begin - case (guard__h583842) + case (guard__h583533) 2'b0: - CASE_guard83842_0b0_sfdin92062_BITS_56_TO_5_0b_ETC__q223 = - sfdin__h592062[56:5]; + CASE_guard83533_0b0_sfdin91753_BITS_56_TO_5_0b_ETC__q215 = + sfdin__h591753[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard83842_0b0_sfdin92062_BITS_56_TO_5_0b_ETC__q223 = - _theResult___sfd__h592798; + CASE_guard83533_0b0_sfdin91753_BITS_56_TO_5_0b_ETC__q215 = + _theResult___sfd__h592489; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h592062 or + sfdin__h591753 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9962 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9960 or - CASE_guard83842_0b0_sfdin92062_BITS_56_TO_5_0b_ETC__q223) + CASE_guard83533_0b0_sfdin91753_BITS_56_TO_5_0b_ETC__q215) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9966 = - sfdin__h592062[56:5]; + sfdin__h591753[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9966 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9962; @@ -36810,24 +36460,24 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9960; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9966 = - CASE_guard83842_0b0_sfdin92062_BITS_56_TO_5_0b_ETC__q223; + CASE_guard83533_0b0_sfdin91753_BITS_56_TO_5_0b_ETC__q215; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9966 = 52'd0; endcase end - always@(guard__h583842 or - sfdin__h592062 or out_sfd__h592801 or _theResult___sfd__h592798) + always@(guard__h583533 or + sfdin__h591753 or out_sfd__h592492 or _theResult___sfd__h592489) begin - case (guard__h583842) + case (guard__h583533) 2'b0, 2'b01: - CASE_guard83842_0b0_sfdin92062_BITS_56_TO_5_0b_ETC__q224 = - sfdin__h592062[56:5]; + CASE_guard83533_0b0_sfdin91753_BITS_56_TO_5_0b_ETC__q216 = + sfdin__h591753[56:5]; 2'b10: - CASE_guard83842_0b0_sfdin92062_BITS_56_TO_5_0b_ETC__q224 = - out_sfd__h592801; + CASE_guard83533_0b0_sfdin91753_BITS_56_TO_5_0b_ETC__q216 = + out_sfd__h592492; 2'b11: - CASE_guard83842_0b0_sfdin92062_BITS_56_TO_5_0b_ETC__q224 = - _theResult___sfd__h592798; + CASE_guard83533_0b0_sfdin91753_BITS_56_TO_5_0b_ETC__q216 = + _theResult___sfd__h592489; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or @@ -36862,28 +36512,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ_first__482_BI_ETC___d10963; endcase end - always@(guard__h592911 or - _theResult___snd__h600847 or _theResult___sfd__h601582) + always@(guard__h592602 or + _theResult___snd__h600538 or _theResult___sfd__h601273) begin - case (guard__h592911) + case (guard__h592602) 2'b0: - CASE_guard92911_0b0_theResult___snd00847_BITS__ETC__q225 = - _theResult___snd__h600847[56:5]; + CASE_guard92602_0b0_theResult___snd00538_BITS__ETC__q217 = + _theResult___snd__h600538[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard92911_0b0_theResult___snd00847_BITS__ETC__q225 = - _theResult___sfd__h601582; + CASE_guard92602_0b0_theResult___snd00538_BITS__ETC__q217 = + _theResult___sfd__h601273; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h600847 or + _theResult___snd__h600538 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9981 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9979 or - CASE_guard92911_0b0_theResult___snd00847_BITS__ETC__q225) + CASE_guard92602_0b0_theResult___snd00538_BITS__ETC__q217) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9985 = - _theResult___snd__h600847[56:5]; + _theResult___snd__h600538[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9985 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9981; @@ -36892,25 +36542,25 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9979; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9985 = - CASE_guard92911_0b0_theResult___snd00847_BITS__ETC__q225; + CASE_guard92602_0b0_theResult___snd00538_BITS__ETC__q217; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9985 = 52'd0; endcase end - always@(guard__h592911 or - _theResult___snd__h600847 or - out_sfd__h601585 or _theResult___sfd__h601582) + always@(guard__h592602 or + _theResult___snd__h600538 or + out_sfd__h601276 or _theResult___sfd__h601273) begin - case (guard__h592911) + case (guard__h592602) 2'b0, 2'b01: - CASE_guard92911_0b0_theResult___snd00847_BITS__ETC__q226 = - _theResult___snd__h600847[56:5]; + CASE_guard92602_0b0_theResult___snd00538_BITS__ETC__q218 = + _theResult___snd__h600538[56:5]; 2'b10: - CASE_guard92911_0b0_theResult___snd00847_BITS__ETC__q226 = - out_sfd__h601585; + CASE_guard92602_0b0_theResult___snd00538_BITS__ETC__q218 = + out_sfd__h601276; 2'b11: - CASE_guard92911_0b0_theResult___snd00847_BITS__ETC__q226 = - _theResult___sfd__h601582; + CASE_guard92602_0b0_theResult___snd00538_BITS__ETC__q218 = + _theResult___sfd__h601273; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or @@ -36965,26 +36615,26 @@ module mkCore(CLK, begin case (coreFix_aluExe_1_regToExeQ$first[399:397]) 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q227 = + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q219 = coreFix_aluExe_1_regToExeQ$first[399:397]; - default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q227 = 3'd7; + default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q219 = 3'd7; endcase end always@(coreFix_aluExe_1_regToExeQ$first or - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q227) + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q219) begin case (coreFix_aluExe_1_regToExeQ$first[416:414]) 3'd3, 3'd2, 3'd1, 3'd0: - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q228 = + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q220 = coreFix_aluExe_1_regToExeQ$first[416:396]; 3'd4: - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q228 = + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q220 = { coreFix_aluExe_1_regToExeQ$first[416:414], 9'h0AA, coreFix_aluExe_1_regToExeQ$first[404:400], - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q227, + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q219, coreFix_aluExe_1_regToExeQ$first[396] }; - default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q228 = + default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q220 = { 3'd5, 18'h2AAAA }; endcase end @@ -37031,9 +36681,9 @@ module mkCore(CLK, 12'd3, 12'd2, 12'd1: - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q229 = + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q221 = coreFix_aluExe_1_regToExeQ$first[394:383]; - default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q229 = + default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q221 = 12'd2303; endcase end @@ -37041,26 +36691,26 @@ module mkCore(CLK, begin case (coreFix_aluExe_0_regToExeQ$first[399:397]) 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q230 = + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q222 = coreFix_aluExe_0_regToExeQ$first[399:397]; - default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q230 = 3'd7; + default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q222 = 3'd7; endcase end always@(coreFix_aluExe_0_regToExeQ$first or - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q230) + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q222) begin case (coreFix_aluExe_0_regToExeQ$first[416:414]) 3'd3, 3'd2, 3'd1, 3'd0: - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q231 = + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q223 = coreFix_aluExe_0_regToExeQ$first[416:396]; 3'd4: - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q231 = + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q223 = { coreFix_aluExe_0_regToExeQ$first[416:414], 9'h0AA, coreFix_aluExe_0_regToExeQ$first[404:400], - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q230, + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q222, coreFix_aluExe_0_regToExeQ$first[396] }; - default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q231 = + default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q223 = { 3'd5, 18'h2AAAA }; endcase end @@ -37107,9 +36757,9 @@ module mkCore(CLK, 12'd3, 12'd2, 12'd1: - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_394_ETC__q232 = + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_394_ETC__q224 = coreFix_aluExe_0_regToExeQ$first[394:383]; - default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_394_ETC__q232 = + default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_394_ETC__q224 = 12'd2303; endcase end @@ -37156,9 +36806,9 @@ module mkCore(CLK, 12'd3858, 12'd3859, 12'd3860: - IF_fetchStage_pipelines_0_first__2934_BITS_172_ETC___d13146 = + IF_fetchStage_pipelines_0_first__2931_BITS_172_ETC___d13142 = fetchStage$pipelines_0_first[172:161]; - default: IF_fetchStage_pipelines_0_first__2934_BITS_172_ETC___d13146 = + default: IF_fetchStage_pipelines_0_first__2931_BITS_172_ETC___d13142 = 12'd2303; endcase end @@ -37166,15 +36816,15 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[67:64]) 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: - IF_fetchStage_pipelines_0_first__2934_BIT_68_2_ETC___d13300 = + IF_fetchStage_pipelines_0_first__2931_BIT_68_2_ETC___d13296 = fetchStage$pipelines_0_first[67:64]; 4'd11: - IF_fetchStage_pipelines_0_first__2934_BIT_68_2_ETC___d13300 = 4'd10; + IF_fetchStage_pipelines_0_first__2931_BIT_68_2_ETC___d13296 = 4'd10; 4'd12: - IF_fetchStage_pipelines_0_first__2934_BIT_68_2_ETC___d13300 = 4'd11; + IF_fetchStage_pipelines_0_first__2931_BIT_68_2_ETC___d13296 = 4'd11; 4'd13: - IF_fetchStage_pipelines_0_first__2934_BIT_68_2_ETC___d13300 = 4'd12; - default: IF_fetchStage_pipelines_0_first__2934_BIT_68_2_ETC___d13300 = + IF_fetchStage_pipelines_0_first__2931_BIT_68_2_ETC___d13296 = 4'd12; + default: IF_fetchStage_pipelines_0_first__2931_BIT_68_2_ETC___d13296 = 4'd13; endcase end @@ -37182,51 +36832,51 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[177:175]) 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q233 = + CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q225 = fetchStage$pipelines_0_first[177:175]; - default: CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q233 = 3'd7; + default: CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q225 = 3'd7; endcase end always@(fetchStage$pipelines_0_first or - CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q233) + CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q225) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1, 3'd2, 3'd3: - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d13064 = + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d13060 = fetchStage$pipelines_0_first[194:174]; 3'd4: - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d13064 = + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d13060 = { fetchStage$pipelines_0_first[194:192], 9'h0AA, fetchStage$pipelines_0_first[182:178], - CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q233, + CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q225, fetchStage$pipelines_0_first[174] }; - default: IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d13064 = + default: IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d13060 = 21'd1485482; endcase end - always@(checkForException___d13180) + always@(checkForException___d13176) begin - case (checkForException___d13180[3:0]) + case (checkForException___d13176[3:0]) 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: - CASE_checkForException_3180_BITS_3_TO_0_0_chec_ETC__q234 = - checkForException___d13180[3:0]; - 4'd11: CASE_checkForException_3180_BITS_3_TO_0_0_chec_ETC__q234 = 4'd10; - 4'd12: CASE_checkForException_3180_BITS_3_TO_0_0_chec_ETC__q234 = 4'd11; - 4'd13: CASE_checkForException_3180_BITS_3_TO_0_0_chec_ETC__q234 = 4'd12; - default: CASE_checkForException_3180_BITS_3_TO_0_0_chec_ETC__q234 = + CASE_checkForException_3176_BITS_3_TO_0_0_chec_ETC__q226 = + checkForException___d13176[3:0]; + 4'd11: CASE_checkForException_3176_BITS_3_TO_0_0_chec_ETC__q226 = 4'd10; + 4'd12: CASE_checkForException_3176_BITS_3_TO_0_0_chec_ETC__q226 = 4'd11; + 4'd13: CASE_checkForException_3176_BITS_3_TO_0_0_chec_ETC__q226 = 4'd12; + default: CASE_checkForException_3176_BITS_3_TO_0_0_chec_ETC__q226 = 4'd13; endcase end - always@(k__h671729 or + always@(k__h671393 or coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq) begin - case (k__h671729) + case (k__h671393) 1'd0: - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3613_co_ETC___d13623 = + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3609_co_ETC___d13619 = coreFix_aluExe_0_rsAlu$canEnq; 1'd1: - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3613_co_ETC___d13623 = + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3609_co_ETC___d13619 = coreFix_aluExe_1_rsAlu$canEnq; endcase end @@ -37235,65 +36885,65 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2934_BITS_191_ETC___d13635 = + IF_fetchStage_pipelines_0_first__2931_BITS_191_ETC___d13631 = coreFix_memExe_lsq$enqLdTag[6]; - default: IF_fetchStage_pipelines_0_first__2934_BITS_191_ETC___d13635 = + default: IF_fetchStage_pipelines_0_first__2931_BITS_191_ETC___d13631 = coreFix_memExe_lsq$enqStTag[6]; endcase end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2934_BITS_191_ETC___d13635 or - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3613_co_ETC___d13623 or + IF_fetchStage_pipelines_0_first__2931_BITS_191_ETC___d13631 or + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3609_co_ETC___d13619 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d13639 = - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3613_co_ETC___d13623; + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d13635 = + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3609_co_ETC___d13619; 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d13639 = + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d13635 = coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq; - default: IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d13639 = + default: IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d13635 = fetchStage$pipelines_0_first[194:192] != 3'd2 || coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2934_BITS_191_ETC___d13635; + IF_fetchStage_pipelines_0_first__2931_BITS_191_ETC___d13631; endcase end - always@(k__h671729 or + always@(k__h671393 or coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq) begin - case (k__h671729) + case (k__h671393) 1'd0: - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__361_ETC___d13656 = + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__360_ETC___d13652 = !coreFix_aluExe_0_rsAlu$canEnq; 1'd1: - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__361_ETC___d13656 = + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__360_ETC___d13652 = !coreFix_aluExe_1_rsAlu$canEnq; endcase end always@(fetchStage$pipelines_0_first or - regRenamingTable_rename_0_canRename__3582_AND__ETC___d13604 or - NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13658 or + regRenamingTable_rename_0_canRename__3578_AND__ETC___d13600 or + NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13654 or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2934_BITS_191_ETC___d13635 or + IF_fetchStage_pipelines_0_first__2931_BITS_191_ETC___d13631 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d13663 = - NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13658; + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d13659 = + NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13654; 3'd2: - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d13663 = + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d13659 = coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2934_BITS_191_ETC___d13635 && - regRenamingTable_rename_0_canRename__3582_AND__ETC___d13604; + IF_fetchStage_pipelines_0_first__2931_BITS_191_ETC___d13631 && + regRenamingTable_rename_0_canRename__3578_AND__ETC___d13600; 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d13663 = + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d13659 = coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq && - regRenamingTable_rename_0_canRename__3582_AND__ETC___d13604; - default: IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d13663 = - regRenamingTable_rename_0_canRename__3582_AND__ETC___d13604; + regRenamingTable_rename_0_canRename__3578_AND__ETC___d13600; + default: IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d13659 = + regRenamingTable_rename_0_canRename__3578_AND__ETC___d13600; endcase end always@(fetchStage$pipelines_0_first or @@ -37301,32 +36951,32 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2934_BITS_191_ETC___d13693 = + IF_fetchStage_pipelines_0_first__2931_BITS_191_ETC___d13689 = !coreFix_memExe_lsq$enqLdTag[6]; - default: IF_fetchStage_pipelines_0_first__2934_BITS_191_ETC___d13693 = + default: IF_fetchStage_pipelines_0_first__2931_BITS_191_ETC___d13689 = !coreFix_memExe_lsq$enqStTag[6]; endcase end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2934_BITS_191_ETC___d13693 or - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__361_ETC___d13656 or + IF_fetchStage_pipelines_0_first__2931_BITS_191_ETC___d13689 or + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__360_ETC___d13652 or specTagManager$canClaim or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d13698 = - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__361_ETC___d13656 || + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d13694 = + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__360_ETC___d13652 || fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim; 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d13698 = + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d13694 = !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq; - default: IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d13698 = + default: IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d13694 = fetchStage$pipelines_0_first[194:192] == 3'd2 && (!coreFix_memExe_rsMem$canEnq || - IF_fetchStage_pipelines_0_first__2934_BITS_191_ETC___d13693); + IF_fetchStage_pipelines_0_first__2931_BITS_191_ETC___d13689); endcase end always@(fetchStage$pipelines_1_first) @@ -37372,9 +37022,9 @@ module mkCore(CLK, 12'd3858, 12'd3859, 12'd3860: - CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q235 = + CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q227 = fetchStage$pipelines_1_first[172:161]; - default: CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q235 = + default: CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q227 = 12'd2303; endcase end @@ -37382,46 +37032,46 @@ module mkCore(CLK, begin case (fetchStage$pipelines_1_first[177:175]) 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q236 = + CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q228 = fetchStage$pipelines_1_first[177:175]; - default: CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q236 = 3'd7; + default: CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q228 = 3'd7; endcase end always@(fetchStage$pipelines_1_first or - CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q236) + CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q228) begin case (fetchStage$pipelines_1_first[194:192]) 3'd0, 3'd1, 3'd2, 3'd3: - IF_fetchStage_pipelines_1_first__2943_BITS_194_ETC___d13758 = + IF_fetchStage_pipelines_1_first__2940_BITS_194_ETC___d13754 = fetchStage$pipelines_1_first[194:174]; 3'd4: - IF_fetchStage_pipelines_1_first__2943_BITS_194_ETC___d13758 = + IF_fetchStage_pipelines_1_first__2940_BITS_194_ETC___d13754 = { fetchStage$pipelines_1_first[194:192], 9'h0AA, fetchStage$pipelines_1_first[182:178], - CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q236, + CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q228, fetchStage$pipelines_1_first[174] }; - default: IF_fetchStage_pipelines_1_first__2943_BITS_194_ETC___d13758 = + default: IF_fetchStage_pipelines_1_first__2940_BITS_194_ETC___d13754 = 21'd1485482; endcase end - always@(idx__h686963 or + always@(idx__h686627 or fetchStage$pipelines_0_canDeq or - NOT_fetchStage_pipelines_0_first__2934_BITS_19_ETC___d13911 or + NOT_fetchStage_pipelines_0_first__2931_BITS_19_ETC___d13907 or coreFix_aluExe_0_rsAlu$canEnq or - NOT_fetchStage_pipelines_0_first__2934_BITS_19_ETC___d13917 or + NOT_fetchStage_pipelines_0_first__2931_BITS_19_ETC___d13913 or coreFix_aluExe_1_rsAlu$canEnq) begin - case (idx__h686963) + case (idx__h686627) 1'd0: - SEL_ARR_fetchStage_pipelines_0_canDeq__2932_AN_ETC___d13937 = + SEL_ARR_fetchStage_pipelines_0_canDeq__2929_AN_ETC___d13933 = fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2934_BITS_19_ETC___d13911 || + NOT_fetchStage_pipelines_0_first__2931_BITS_19_ETC___d13907 || !coreFix_aluExe_0_rsAlu$canEnq; 1'd1: - SEL_ARR_fetchStage_pipelines_0_canDeq__2932_AN_ETC___d13937 = + SEL_ARR_fetchStage_pipelines_0_canDeq__2929_AN_ETC___d13933 = fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2934_BITS_19_ETC___d13917 || + NOT_fetchStage_pipelines_0_first__2931_BITS_19_ETC___d13913 || !coreFix_aluExe_1_rsAlu$canEnq; endcase end @@ -37430,68 +37080,68 @@ module mkCore(CLK, begin case (fetchStage$pipelines_1_first[191:189]) 3'd0, 3'd2: - CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q237 = + CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q229 = !coreFix_memExe_lsq$enqLdTag[6]; - default: CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q237 = + default: CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q229 = !coreFix_memExe_lsq$enqStTag[6]; endcase end always@(fetchStage$pipelines_0_first or - renameStage_rg_m_halt_req_2961_BIT_4_2962_OR_f_ETC___d14005 or - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__361_ETC___d13656 or - fetchStage_pipelines_0_first__2934_BITS_194_TO_ETC___d14009 or + renameStage_rg_m_halt_req_2958_BIT_4_2959_OR_f_ETC___d14001 or + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__360_ETC___d13652 or + fetchStage_pipelines_0_first__2931_BITS_194_TO_ETC___d14005 or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2934_BITS_191_ETC___d13693 or + IF_fetchStage_pipelines_0_first__2931_BITS_191_ETC___d13689 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d14015 = - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__361_ETC___d13656 || - fetchStage_pipelines_0_first__2934_BITS_194_TO_ETC___d14009; + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d14011 = + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__360_ETC___d13652 || + fetchStage_pipelines_0_first__2931_BITS_194_TO_ETC___d14005; 3'd2: - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d14015 = + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d14011 = !coreFix_memExe_rsMem$canEnq || - IF_fetchStage_pipelines_0_first__2934_BITS_191_ETC___d13693 || - renameStage_rg_m_halt_req_2961_BIT_4_2962_OR_f_ETC___d14005; + IF_fetchStage_pipelines_0_first__2931_BITS_191_ETC___d13689 || + renameStage_rg_m_halt_req_2958_BIT_4_2959_OR_f_ETC___d14001; 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d14015 = + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d14011 = !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq || - renameStage_rg_m_halt_req_2961_BIT_4_2962_OR_f_ETC___d14005; - default: IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d14015 = - renameStage_rg_m_halt_req_2961_BIT_4_2962_OR_f_ETC___d14005; + renameStage_rg_m_halt_req_2958_BIT_4_2959_OR_f_ETC___d14001; + default: IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d14011 = + renameStage_rg_m_halt_req_2958_BIT_4_2959_OR_f_ETC___d14001; endcase end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2934_BITS_191_ETC___d13635 or - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3613_co_ETC___d13623) + IF_fetchStage_pipelines_0_first__2931_BITS_191_ETC___d13631 or + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3609_co_ETC___d13619) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d14037 = - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3613_co_ETC___d13623; - default: IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d14037 = + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d14033 = + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3609_co_ETC___d13619; + default: IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d14033 = fetchStage$pipelines_0_first[194:192] != 3'd2 || coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2934_BITS_191_ETC___d13635; + IF_fetchStage_pipelines_0_first__2931_BITS_191_ETC___d13631; endcase end always@(fetchStage$pipelines_0_first or - IF_fetchStage_pipelines_0_first__2934_BITS_191_ETC___d13635 or - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3613_co_ETC___d13623 or + IF_fetchStage_pipelines_0_first__2931_BITS_191_ETC___d13631 or + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3609_co_ETC___d13619 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d14055 = - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3613_co_ETC___d13623; + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d14051 = + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3609_co_ETC___d13619; 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d14055 = + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d14051 = coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq; - default: IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d14055 = + default: IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d14051 = fetchStage$pipelines_0_first[194:192] != 3'd2 || - IF_fetchStage_pipelines_0_first__2934_BITS_191_ETC___d13635; + IF_fetchStage_pipelines_0_first__2931_BITS_191_ETC___d13631; endcase end always@(fetchStage$pipelines_1_first or @@ -37499,49 +37149,49 @@ module mkCore(CLK, begin case (fetchStage$pipelines_1_first[191:189]) 3'd0, 3'd2: - CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q238 = + CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q230 = coreFix_memExe_lsq$enqLdTag[6]; - default: CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q238 = + default: CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q230 = coreFix_memExe_lsq$enqStTag[6]; endcase end always@(fetchStage$pipelines_1_first or - regRenamingTable_rename_1_canRename__3704_AND__ETC___d13903 or - SEL_ARR_fetchStage_pipelines_0_canDeq__2932_AN_ETC___d13937 or - NOT_fetchStage_pipelines_1_first__2943_BITS_19_ETC___d14021 or - NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d14052 or - regRenamingTable_rename_1_canRename__3704_AND__ETC___d14063 or - NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d14034 or + regRenamingTable_rename_1_canRename__3700_AND__ETC___d13899 or + SEL_ARR_fetchStage_pipelines_0_canDeq__2929_AN_ETC___d13933 or + NOT_fetchStage_pipelines_1_first__2940_BITS_19_ETC___d14017 or + NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d14048 or + regRenamingTable_rename_1_canRename__3700_AND__ETC___d14059 or + NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d14030 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq or - regRenamingTable_rename_1_canRename__3704_AND__ETC___d14045) + regRenamingTable_rename_1_canRename__3700_AND__ETC___d14041) begin case (fetchStage$pipelines_1_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_1_first__2943_BITS_194_ETC___d14067 = - !SEL_ARR_fetchStage_pipelines_0_canDeq__2932_AN_ETC___d13937 && - NOT_fetchStage_pipelines_1_first__2943_BITS_19_ETC___d14021; + IF_fetchStage_pipelines_1_first__2940_BITS_194_ETC___d14063 = + !SEL_ARR_fetchStage_pipelines_0_canDeq__2929_AN_ETC___d13933 && + NOT_fetchStage_pipelines_1_first__2940_BITS_19_ETC___d14017; 3'd2: - IF_fetchStage_pipelines_1_first__2943_BITS_194_ETC___d14067 = - NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d14052 && - regRenamingTable_rename_1_canRename__3704_AND__ETC___d14063; + IF_fetchStage_pipelines_1_first__2940_BITS_194_ETC___d14063 = + NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d14048 && + regRenamingTable_rename_1_canRename__3700_AND__ETC___d14059; 3'd3, 3'd4: - IF_fetchStage_pipelines_1_first__2943_BITS_194_ETC___d14067 = - NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d14034 && + IF_fetchStage_pipelines_1_first__2940_BITS_194_ETC___d14063 = + NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d14030 && coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq && - regRenamingTable_rename_1_canRename__3704_AND__ETC___d14045; - default: IF_fetchStage_pipelines_1_first__2943_BITS_194_ETC___d14067 = - regRenamingTable_rename_1_canRename__3704_AND__ETC___d13903; + regRenamingTable_rename_1_canRename__3700_AND__ETC___d14041; + default: IF_fetchStage_pipelines_1_first__2940_BITS_194_ETC___d14063 = + regRenamingTable_rename_1_canRename__3700_AND__ETC___d13899; endcase end - always@(k__h671729 or + always@(k__h671393 or coreFix_aluExe_0_rsAlu$RDY_enq or coreFix_aluExe_1_rsAlu$RDY_enq) begin - case (k__h671729) + case (k__h671393) 1'd0: - CASE_k71729_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239 = + CASE_k71393_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q231 = coreFix_aluExe_0_rsAlu$RDY_enq; 1'd1: - CASE_k71729_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239 = + CASE_k71393_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q231 = coreFix_aluExe_1_rsAlu$RDY_enq; endcase end @@ -37550,129 +37200,129 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q240 = + CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q232 = coreFix_memExe_lsq$RDY_enqLd; - default: CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q240 = + default: CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q232 = coreFix_memExe_lsq$RDY_enqSt; endcase end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2934_BITS_191_ETC___d13693 or - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__361_ETC___d13656 or + IF_fetchStage_pipelines_0_first__2931_BITS_191_ETC___d13689 or + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__360_ETC___d13652 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d14112 = - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__361_ETC___d13656; + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d14108 = + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__360_ETC___d13652; 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d14112 = + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d14108 = !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq; - default: IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d14112 = + default: IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d14108 = fetchStage$pipelines_0_first[194:192] == 3'd2 && (!coreFix_memExe_rsMem$canEnq || - IF_fetchStage_pipelines_0_first__2934_BITS_191_ETC___d13693); + IF_fetchStage_pipelines_0_first__2931_BITS_191_ETC___d13689); endcase end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2934_BITS_191_ETC___d13693 or - regRenamingTable_RDY_rename_0_getRename__3469__ETC___d14106 or - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3613_co_ETC___d13623 or + IF_fetchStage_pipelines_0_first__2931_BITS_191_ETC___d13689 or + regRenamingTable_RDY_rename_0_getRename__3465__ETC___d14102 or + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3609_co_ETC___d13619 or regRenamingTable$RDY_rename_0_getRename or - _0_OR_NOT_fetchStage_pipelines_0_first__2934_BI_ETC___d14093 or + _0_OR_NOT_fetchStage_pipelines_0_first__2931_BI_ETC___d14089 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq or coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_enq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d14110 = - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3613_co_ETC___d13623 || + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d14106 = + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3609_co_ETC___d13619 || regRenamingTable$RDY_rename_0_getRename && - _0_OR_NOT_fetchStage_pipelines_0_first__2934_BI_ETC___d14093; + _0_OR_NOT_fetchStage_pipelines_0_first__2931_BI_ETC___d14089; 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d14110 = + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d14106 = !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq || coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_enq && regRenamingTable$RDY_rename_0_getRename; - default: IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d14110 = + default: IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d14106 = fetchStage$pipelines_0_first[194:192] != 3'd2 || !coreFix_memExe_rsMem$canEnq || - IF_fetchStage_pipelines_0_first__2934_BITS_191_ETC___d13693 || - regRenamingTable_RDY_rename_0_getRename__3469__ETC___d14106; + IF_fetchStage_pipelines_0_first__2931_BITS_191_ETC___d13689 || + regRenamingTable_RDY_rename_0_getRename__3465__ETC___d14102; endcase end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2934_BITS_191_ETC___d13693 or - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3613_co_ETC___d13623 or + IF_fetchStage_pipelines_0_first__2931_BITS_191_ETC___d13689 or + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3609_co_ETC___d13619 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d14126 = - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3613_co_ETC___d13623; + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d14122 = + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3609_co_ETC___d13619; 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d14126 = + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d14122 = !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq; - default: IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d14126 = + default: IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d14122 = fetchStage$pipelines_0_first[194:192] == 3'd2 && (!coreFix_memExe_rsMem$canEnq || - IF_fetchStage_pipelines_0_first__2934_BITS_191_ETC___d13693); + IF_fetchStage_pipelines_0_first__2931_BITS_191_ETC___d13689); endcase end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2934_BITS_191_ETC___d13635 or - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__361_ETC___d13656 or + IF_fetchStage_pipelines_0_first__2931_BITS_191_ETC___d13631 or + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__360_ETC___d13652 or specTagManager$canClaim or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d14133 = - !SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__361_ETC___d13656 && + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d14129 = + !SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__360_ETC___d13652 && (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim); 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d14133 = + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d14129 = coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq; - default: IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d14133 = + default: IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d14129 = fetchStage$pipelines_0_first[194:192] != 3'd2 || coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2934_BITS_191_ETC___d13635; + IF_fetchStage_pipelines_0_first__2931_BITS_191_ETC___d13631; endcase end - always@(idx__h686963 or + always@(idx__h686627 or fetchStage$pipelines_0_canDeq or - fetchStage_pipelines_0_first__2934_BITS_194_TO_ETC___d14156 or + fetchStage_pipelines_0_first__2931_BITS_194_TO_ETC___d14152 or coreFix_aluExe_0_rsAlu$canEnq or - fetchStage_pipelines_0_first__2934_BITS_194_TO_ETC___d14163 or + fetchStage_pipelines_0_first__2931_BITS_194_TO_ETC___d14159 or coreFix_aluExe_1_rsAlu$canEnq) begin - case (idx__h686963) + case (idx__h686627) 1'd0: - SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__293_ETC___d14167 = + SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__292_ETC___d14163 = (!fetchStage$pipelines_0_canDeq || - fetchStage_pipelines_0_first__2934_BITS_194_TO_ETC___d14156) && + fetchStage_pipelines_0_first__2931_BITS_194_TO_ETC___d14152) && coreFix_aluExe_0_rsAlu$canEnq; 1'd1: - SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__293_ETC___d14167 = + SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__292_ETC___d14163 = (!fetchStage$pipelines_0_canDeq || - fetchStage_pipelines_0_first__2934_BITS_194_TO_ETC___d14163) && + fetchStage_pipelines_0_first__2931_BITS_194_TO_ETC___d14159) && coreFix_aluExe_1_rsAlu$canEnq; endcase end - always@(fetchStage_pipelines_0_canDeq__2932_AND_NOT_fe_ETC___d14183 or + always@(fetchStage_pipelines_0_canDeq__2929_AND_NOT_fe_ETC___d14179 or coreFix_aluExe_0_rsAlu$RDY_enq or coreFix_aluExe_1_rsAlu$RDY_enq) begin - case (fetchStage_pipelines_0_canDeq__2932_AND_NOT_fe_ETC___d14183) + case (fetchStage_pipelines_0_canDeq__2929_AND_NOT_fe_ETC___d14179) 1'd0: - CASE_fetchStage_pipelines_0_canDeq__2932_AND_N_ETC__q241 = + CASE_fetchStage_pipelines_0_canDeq__2929_AND_N_ETC__q233 = coreFix_aluExe_0_rsAlu$RDY_enq; 1'd1: - CASE_fetchStage_pipelines_0_canDeq__2932_AND_N_ETC__q241 = + CASE_fetchStage_pipelines_0_canDeq__2929_AND_N_ETC__q233 = coreFix_aluExe_1_rsAlu$RDY_enq; endcase end @@ -37681,86 +37331,86 @@ module mkCore(CLK, begin case (fetchStage$pipelines_1_first[191:189]) 3'd0, 3'd2: - CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q242 = + CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q234 = coreFix_memExe_lsq$RDY_enqLd; - default: CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q242 = + default: CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q234 = coreFix_memExe_lsq$RDY_enqSt; endcase end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2934_BITS_191_ETC___d13693 or - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3613_co_ETC___d13623) + IF_fetchStage_pipelines_0_first__2931_BITS_191_ETC___d13689 or + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3609_co_ETC___d13619) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d14209 = - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3613_co_ETC___d13623; - default: IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d14209 = + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d14205 = + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3609_co_ETC___d13619; + default: IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d14205 = fetchStage$pipelines_0_first[194:192] == 3'd2 && (!coreFix_memExe_rsMem$canEnq || - IF_fetchStage_pipelines_0_first__2934_BITS_191_ETC___d13693); + IF_fetchStage_pipelines_0_first__2931_BITS_191_ETC___d13689); endcase end always@(fetchStage$pipelines_0_first or - IF_fetchStage_pipelines_0_first__2934_BITS_191_ETC___d13693 or - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3613_co_ETC___d13623 or + IF_fetchStage_pipelines_0_first__2931_BITS_191_ETC___d13689 or + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3609_co_ETC___d13619 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d14221 = - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3613_co_ETC___d13623; + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d14217 = + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3609_co_ETC___d13619; 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d14221 = + IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d14217 = !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq; - default: IF_fetchStage_pipelines_0_first__2934_BITS_194_ETC___d14221 = + default: IF_fetchStage_pipelines_0_first__2931_BITS_194_ETC___d14217 = fetchStage$pipelines_0_first[194:192] == 3'd2 && - IF_fetchStage_pipelines_0_first__2934_BITS_191_ETC___d13693; + IF_fetchStage_pipelines_0_first__2931_BITS_191_ETC___d13689; endcase end always@(fetchStage$pipelines_1_first or - fetchStage_pipelines_0_canDeq__2932_AND_regRen_ETC___d14230 or - SEL_ARR_fetchStage_pipelines_0_canDeq__2932_AN_ETC___d13937 or - fetchStage_pipelines_0_canDeq__2932_AND_regRen_ETC___d14218) + fetchStage_pipelines_0_canDeq__2929_AND_regRen_ETC___d14226 or + SEL_ARR_fetchStage_pipelines_0_canDeq__2929_AN_ETC___d13933 or + fetchStage_pipelines_0_canDeq__2929_AND_regRen_ETC___d14214) begin case (fetchStage$pipelines_1_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_1_first__2943_BITS_194_ETC___d14233 = - SEL_ARR_fetchStage_pipelines_0_canDeq__2932_AN_ETC___d13937; + IF_fetchStage_pipelines_1_first__2940_BITS_194_ETC___d14229 = + SEL_ARR_fetchStage_pipelines_0_canDeq__2929_AN_ETC___d13933; 3'd3, 3'd4: - IF_fetchStage_pipelines_1_first__2943_BITS_194_ETC___d14233 = - fetchStage_pipelines_0_canDeq__2932_AND_regRen_ETC___d14218; - default: IF_fetchStage_pipelines_1_first__2943_BITS_194_ETC___d14233 = + IF_fetchStage_pipelines_1_first__2940_BITS_194_ETC___d14229 = + fetchStage_pipelines_0_canDeq__2929_AND_regRen_ETC___d14214; + default: IF_fetchStage_pipelines_1_first__2940_BITS_194_ETC___d14229 = fetchStage$pipelines_1_first[194:192] == 3'd2 && - fetchStage_pipelines_0_canDeq__2932_AND_regRen_ETC___d14230; + fetchStage_pipelines_0_canDeq__2929_AND_regRen_ETC___d14226; endcase end always@(fetchStage$pipelines_1_first or - fetchStage_pipelines_0_canDeq__2932_AND_regRen_ETC___d14196 or + fetchStage_pipelines_0_canDeq__2929_AND_regRen_ETC___d14192 or regRenamingTable$RDY_rename_1_getRename or - NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d14201 or - SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__293_ETC___d14167 or - regRenamingTable_RDY_rename_1_getRename__4169__ETC___d14187 or - fetchStage_pipelines_0_canDeq__2932_AND_regRen_ETC___d14189 or + NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d14197 or + SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__292_ETC___d14163 or + regRenamingTable_RDY_rename_1_getRename__4165__ETC___d14183 or + fetchStage_pipelines_0_canDeq__2929_AND_regRen_ETC___d14185 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq or - coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__40_ETC___d14192) + coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__40_ETC___d14188) begin case (fetchStage$pipelines_1_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_1_first__2943_BITS_194_ETC___d14206 = - !SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__293_ETC___d14167 || - regRenamingTable_RDY_rename_1_getRename__4169__ETC___d14187; + IF_fetchStage_pipelines_1_first__2940_BITS_194_ETC___d14202 = + !SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__292_ETC___d14163 || + regRenamingTable_RDY_rename_1_getRename__4165__ETC___d14183; 3'd3, 3'd4: - IF_fetchStage_pipelines_1_first__2943_BITS_194_ETC___d14206 = - fetchStage_pipelines_0_canDeq__2932_AND_regRen_ETC___d14189 || + IF_fetchStage_pipelines_1_first__2940_BITS_194_ETC___d14202 = + fetchStage_pipelines_0_canDeq__2929_AND_regRen_ETC___d14185 || !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq || - coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__40_ETC___d14192; - default: IF_fetchStage_pipelines_1_first__2943_BITS_194_ETC___d14206 = + coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__40_ETC___d14188; + default: IF_fetchStage_pipelines_1_first__2940_BITS_194_ETC___d14202 = fetchStage$pipelines_1_first[194:192] != 3'd2 || - fetchStage_pipelines_0_canDeq__2932_AND_regRen_ETC___d14196 || + fetchStage_pipelines_0_canDeq__2929_AND_regRen_ETC___d14192 || regRenamingTable$RDY_rename_1_getRename && - NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d14201; + NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d14197; endcase end always@(fetchStage$pipelines_0_first or @@ -37768,9 +37418,9 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2934_BITS_191_ETC___d14307 = + IF_fetchStage_pipelines_0_first__2931_BITS_191_ETC___d14303 = !coreFix_memExe_lsq$enqLdTag[5]; - default: IF_fetchStage_pipelines_0_first__2934_BITS_191_ETC___d14307 = + default: IF_fetchStage_pipelines_0_first__2931_BITS_191_ETC___d14303 = !coreFix_memExe_lsq$enqStTag[5]; endcase end @@ -37779,9 +37429,9 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2934_BITS_191_ETC___d14304 = + IF_fetchStage_pipelines_0_first__2931_BITS_191_ETC___d14300 = coreFix_memExe_lsq$enqLdTag[5]; - default: IF_fetchStage_pipelines_0_first__2934_BITS_191_ETC___d14304 = + default: IF_fetchStage_pipelines_0_first__2931_BITS_191_ETC___d14300 = coreFix_memExe_lsq$enqStTag[5]; endcase end @@ -37790,9 +37440,9 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2934_BITS_191_ETC___d14313 = + IF_fetchStage_pipelines_0_first__2931_BITS_191_ETC___d14309 = coreFix_memExe_lsq$enqLdTag[3:0]; - default: IF_fetchStage_pipelines_0_first__2934_BITS_191_ETC___d14313 = + default: IF_fetchStage_pipelines_0_first__2931_BITS_191_ETC___d14309 = coreFix_memExe_lsq$enqStTag[3:0]; endcase end @@ -37801,9 +37451,9 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2934_BITS_191_ETC___d14310 = + IF_fetchStage_pipelines_0_first__2931_BITS_191_ETC___d14306 = coreFix_memExe_lsq$enqLdTag[4:0]; - default: IF_fetchStage_pipelines_0_first__2934_BITS_191_ETC___d14310 = + default: IF_fetchStage_pipelines_0_first__2931_BITS_191_ETC___d14306 = coreFix_memExe_lsq$enqStTag[4:0]; endcase end @@ -37812,9 +37462,9 @@ module mkCore(CLK, begin case (fetchStage$pipelines_1_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_1_first__2943_BITS_191_ETC___d14475 = + IF_fetchStage_pipelines_1_first__2940_BITS_191_ETC___d14471 = coreFix_memExe_lsq$enqLdTag[3:0]; - default: IF_fetchStage_pipelines_1_first__2943_BITS_191_ETC___d14475 = + default: IF_fetchStage_pipelines_1_first__2940_BITS_191_ETC___d14471 = coreFix_memExe_lsq$enqStTag[3:0]; endcase end @@ -37823,9 +37473,9 @@ module mkCore(CLK, begin case (fetchStage$pipelines_1_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_1_first__2943_BITS_191_ETC___d14473 = + IF_fetchStage_pipelines_1_first__2940_BITS_191_ETC___d14469 = !coreFix_memExe_lsq$enqLdTag[5]; - default: IF_fetchStage_pipelines_1_first__2943_BITS_191_ETC___d14473 = + default: IF_fetchStage_pipelines_1_first__2940_BITS_191_ETC___d14469 = !coreFix_memExe_lsq$enqStTag[5]; endcase end @@ -37834,9 +37484,9 @@ module mkCore(CLK, begin case (fetchStage$pipelines_1_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_1_first__2943_BITS_191_ETC___d14472 = + IF_fetchStage_pipelines_1_first__2940_BITS_191_ETC___d14468 = coreFix_memExe_lsq$enqLdTag[5]; - default: IF_fetchStage_pipelines_1_first__2943_BITS_191_ETC___d14472 = + default: IF_fetchStage_pipelines_1_first__2940_BITS_191_ETC___d14468 = coreFix_memExe_lsq$enqStTag[5]; endcase end @@ -37845,9 +37495,9 @@ module mkCore(CLK, begin case (fetchStage$pipelines_1_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_1_first__2943_BITS_191_ETC___d14474 = + IF_fetchStage_pipelines_1_first__2940_BITS_191_ETC___d14470 = coreFix_memExe_lsq$enqLdTag[4:0]; - default: IF_fetchStage_pipelines_1_first__2943_BITS_191_ETC___d14474 = + default: IF_fetchStage_pipelines_1_first__2940_BITS_191_ETC___d14470 = coreFix_memExe_lsq$enqStTag[4:0]; endcase end @@ -37855,12 +37505,12 @@ module mkCore(CLK, begin case (csrf_prv_reg) 2'd1: - CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q243 = + CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q235 = !csrf_rg_dcsr[13]; 2'd3: - CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q243 = + CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q235 = !csrf_rg_dcsr[15]; - default: CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q243 = + default: CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q235 = !csrf_rg_dcsr[12]; endcase end @@ -37868,12 +37518,12 @@ module mkCore(CLK, begin case (csrf_prv_reg) 2'd1: - CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q244 = + CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q236 = csrf_rg_dcsr[13]; 2'd3: - CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q244 = + CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q236 = csrf_rg_dcsr[15]; - default: CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q244 = + default: CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q236 = csrf_rg_dcsr[12]; endcase end @@ -37881,86 +37531,86 @@ module mkCore(CLK, begin case (rob$deqPort_0_deq_data[180:169]) 12'd1: - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 = 6'd0; + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 = 6'd0; 12'd2: - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 = 6'd1; + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 = 6'd1; 12'd3: - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 = 6'd2; + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 = 6'd2; 12'd256: - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 = 6'd8; + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 = 6'd8; 12'd260: - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 = 6'd9; + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 = 6'd9; 12'd261: - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 = 6'd10; + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 = 6'd10; 12'd262: - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 = 6'd11; + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 = 6'd11; 12'd320: - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 = 6'd12; + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 = 6'd12; 12'd321: - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 = 6'd13; + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 = 6'd13; 12'd322: - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 = 6'd14; + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 = 6'd14; 12'd323: - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 = 6'd15; + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 = 6'd15; 12'd324: - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 = 6'd16; + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 = 6'd16; 12'd384: - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 = 6'd17; + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 = 6'd17; 12'd768: - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 = 6'd18; + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 = 6'd18; 12'd769: - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 = 6'd19; + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 = 6'd19; 12'd770: - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 = 6'd20; + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 = 6'd20; 12'd771: - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 = 6'd21; + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 = 6'd21; 12'd772: - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 = 6'd22; + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 = 6'd22; 12'd773: - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 = 6'd23; + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 = 6'd23; 12'd774: - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 = 6'd24; + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 = 6'd24; 12'd832: - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 = 6'd25; + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 = 6'd25; 12'd833: - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 = 6'd26; + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 = 6'd26; 12'd834: - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 = 6'd27; + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 = 6'd27; 12'd835: - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 = 6'd28; + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 = 6'd28; 12'd836: - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 = 6'd29; + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 = 6'd29; 12'd1968: - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 = 6'd36; + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 = 6'd36; 12'd1969: - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 = 6'd37; + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 = 6'd37; 12'd1970: - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 = 6'd38; + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 = 6'd38; 12'd1971: - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 = 6'd39; + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 = 6'd39; 12'd2048: - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 = 6'd6; + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 = 6'd6; 12'd2049: - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 = 6'd7; + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 = 6'd7; 12'd2816: - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 = 6'd30; + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 = 6'd30; 12'd2818: - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 = 6'd31; + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 = 6'd31; 12'd3072: - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 = 6'd3; + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 = 6'd3; 12'd3073: - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 = 6'd4; + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 = 6'd4; 12'd3074: - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 = 6'd5; + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 = 6'd5; 12'd3857: - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 = 6'd32; + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 = 6'd32; 12'd3858: - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 = 6'd33; + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 = 6'd33; 12'd3859: - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 = 6'd34; + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 = 6'd34; 12'd3860: - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 = 6'd35; - default: IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 = + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 = 6'd35; + default: IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 = 6'd40; endcase end @@ -37970,10 +37620,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q245 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q237 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[511:448]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q245 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q237 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[511:448]; endcase end @@ -37983,10 +37633,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q246 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q238 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[447:384]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q246 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q238 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[447:384]; endcase end @@ -37996,10 +37646,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q247 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q239 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[383:320]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q247 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q239 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[383:320]; endcase end @@ -38009,10 +37659,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q248 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q240 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[319:256]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q248 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q240 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[319:256]; endcase end @@ -38022,10 +37672,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q249 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q241 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[255:192]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q249 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q241 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[255:192]; endcase end @@ -38035,45 +37685,13 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q250 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q242 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[191:128]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q250 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q242 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[191:128]; endcase end - always@(rob$deqPort_0_deq_data) - begin - case (rob$deqPort_0_deq_data[165:162]) - 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: - CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q251 = - rob$deqPort_0_deq_data[165:162]; - default: CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q251 = - 4'd15; - endcase - end - always@(rob$deqPort_0_deq_data) - begin - case (rob$deqPort_0_deq_data[165:162]) - 4'd0, - 4'd1, - 4'd2, - 4'd3, - 4'd4, - 4'd5, - 4'd6, - 4'd7, - 4'd8, - 4'd9, - 4'd11, - 4'd12, - 4'd13: - CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q252 = - rob$deqPort_0_deq_data[165:162]; - default: CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q252 = - 4'd15; - endcase - end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) @@ -38309,9 +37927,9 @@ module mkCore(CLK, begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd4, 3'd3, 3'd2, 3'd1, 3'd0: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q253 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q243 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q253 = 3'd7; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q243 = 3'd7; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or @@ -38339,10 +37957,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q254 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q244 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[130:67]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q254 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q244 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[130:67]; endcase end @@ -38352,10 +37970,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q255 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q245 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[66:3]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q255 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q245 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[66:3]; endcase end @@ -38365,10 +37983,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q256 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q246 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[127:64]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q256 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q246 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[127:64]; endcase end @@ -38378,10 +37996,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q257 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q247 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[63:0]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q257 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q247 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[63:0]; endcase end @@ -38391,10 +38009,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q258 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q248 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[578:515]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q258 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q248 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[578:515]; endcase end @@ -38404,10 +38022,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q259 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q249 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[514:513]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q259 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q249 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[514:513]; endcase end @@ -38417,10 +38035,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q260 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q250 = !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[512]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q260 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q250 = !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[512]; endcase end @@ -38430,10 +38048,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q261 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q251 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[517:516]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q261 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q251 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[517:516]; endcase end @@ -38443,10 +38061,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q262 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q252 = !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[515]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q262 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q252 = !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[515]; endcase end @@ -38477,10 +38095,10 @@ module mkCore(CLK, begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[229:228]) 2'd0, 2'd1: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q263 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q253 = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit != 2'd0 && coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_enq; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q263 = + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q253 = coreFix_fpuMulDivExe_0_mulDivExec_divQ_RDY_enq_ETC___d8538; endcase end @@ -38490,10 +38108,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q264 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q254 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[5:4]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q264 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q254 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[5:4]; endcase end @@ -38503,10 +38121,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q265 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q255 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[3]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q265 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q255 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[3]; endcase end @@ -38516,10 +38134,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q266 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q256 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[2:0]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q266 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q256 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[2:0]; endcase end @@ -38529,10 +38147,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q267 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q257 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[71:8]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q267 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q257 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[71:8]; endcase end @@ -38542,10 +38160,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q268 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q258 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[7:6]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q268 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q258 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[7:6]; endcase end @@ -38555,10 +38173,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q269 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q259 = !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[582]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q269 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q259 = !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[582]; endcase end @@ -38568,21 +38186,53 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q270 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q260 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[582]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q270 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q260 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[582]; endcase end + always@(rob$deqPort_0_deq_data) + begin + case (rob$deqPort_0_deq_data[165:162]) + 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: + CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q261 = + rob$deqPort_0_deq_data[165:162]; + default: CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q261 = + 4'd15; + endcase + end + always@(rob$deqPort_0_deq_data) + begin + case (rob$deqPort_0_deq_data[165:162]) + 4'd0, + 4'd1, + 4'd2, + 4'd3, + 4'd4, + 4'd5, + 4'd6, + 4'd7, + 4'd8, + 4'd9, + 4'd11, + 4'd12, + 4'd13: + CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q262 = + rob$deqPort_0_deq_data[165:162]; + default: CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q262 = + 4'd15; + endcase + end always@(mmio_dataReqQ_data_0) begin case (mmio_dataReqQ_data_0[77:76]) 2'd0, 2'd1, 2'd2: - CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q272 = + CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q264 = mmio_dataReqQ_data_0[77:72]; 2'd3: - CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q272 = + CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q264 = { 2'd3, mmio_dataReqQ_data_0[75:72] }; endcase end @@ -38602,9 +38252,9 @@ module mkCore(CLK, 4'd11, 4'd12, 4'd13: - CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q273 = + CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q265 = coreFix_memExe_lsq$firstSt[3:0]; - default: CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q273 = + default: CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q265 = 4'd15; endcase end @@ -38624,78 +38274,20 @@ module mkCore(CLK, 4'd11, 4'd12, 4'd13: - CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q274 = + CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q266 = coreFix_memExe_lsq$firstLd[6:3]; - default: CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q274 = + default: CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q266 = 4'd15; endcase end - always@(rob$deqPort_0_deq_data) - begin - case (rob$deqPort_0_deq_data[180:169]) - 12'd1, - 12'd2, - 12'd3, - 12'd256, - 12'd260, - 12'd261, - 12'd262, - 12'd320, - 12'd321, - 12'd322, - 12'd323, - 12'd324, - 12'd384, - 12'd768, - 12'd769, - 12'd770, - 12'd771, - 12'd772, - 12'd773, - 12'd774, - 12'd832, - 12'd833, - 12'd834, - 12'd835, - 12'd836, - 12'd1968, - 12'd1969, - 12'd1970, - 12'd1971, - 12'd2048, - 12'd2049, - 12'd2816, - 12'd2818, - 12'd3072, - 12'd3073, - 12'd3074, - 12'd3857, - 12'd3858, - 12'd3859, - 12'd3860: - CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q275 = - rob$deqPort_0_deq_data[180:169]; - default: CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q275 = - 12'd2303; - endcase - end - always@(rob$deqPort_0_deq_data) - begin - case (rob$deqPort_0_deq_data[97:96]) - 2'd0, 2'd1: - CASE_robdeqPort_0_deq_data_BITS_97_TO_96_0_ro_ETC__q276 = - rob$deqPort_0_deq_data[97:96]; - default: CASE_robdeqPort_0_deq_data_BITS_97_TO_96_0_ro_ETC__q276 = 2'd2; - endcase - end always@(mmioToPlatform_pRq_enq_x) begin case (mmioToPlatform_pRq_enq_x[37:36]) 2'd0, 2'd1, 2'd2: - CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q277 = + CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q267 = mmioToPlatform_pRq_enq_x[37:32]; 2'd3: - CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q277 = + CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q267 = { 2'd3, mmioToPlatform_pRq_enq_x[35:32] }; endcase end @@ -38703,26 +38295,26 @@ module mkCore(CLK, begin case (coreFix_aluExe_0_rsAlu$dispatchData[139:137]) 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q278 = + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q268 = coreFix_aluExe_0_rsAlu$dispatchData[139:137]; - default: CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q278 = 3'd7; + default: CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q268 = 3'd7; endcase end always@(coreFix_aluExe_0_rsAlu$dispatchData or - CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q278) + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q268) begin case (coreFix_aluExe_0_rsAlu$dispatchData[156:154]) 3'd0, 3'd1, 3'd2, 3'd3: - CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q279 = + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q269 = coreFix_aluExe_0_rsAlu$dispatchData[156:136]; 3'd4: - CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q279 = + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q269 = { coreFix_aluExe_0_rsAlu$dispatchData[156:154], 9'h0AA, coreFix_aluExe_0_rsAlu$dispatchData[144:140], - CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q278, + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q268, coreFix_aluExe_0_rsAlu$dispatchData[136] }; - default: CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q279 = + default: CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q269 = 21'd1485482; endcase end @@ -38769,9 +38361,9 @@ module mkCore(CLK, 12'd3858, 12'd3859, 12'd3860: - CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q280 = + CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q270 = coreFix_aluExe_0_rsAlu$dispatchData[134:123]; - default: CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q280 = + default: CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q270 = 12'd2303; endcase end @@ -38779,26 +38371,26 @@ module mkCore(CLK, begin case (coreFix_aluExe_0_dispToRegQ$first[135:133]) 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q281 = + CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q271 = coreFix_aluExe_0_dispToRegQ$first[135:133]; - default: CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q281 = 3'd7; + default: CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q271 = 3'd7; endcase end always@(coreFix_aluExe_0_dispToRegQ$first or - CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q281) + CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q271) begin case (coreFix_aluExe_0_dispToRegQ$first[152:150]) 3'd0, 3'd1, 3'd2, 3'd3: - CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_15_ETC__q282 = + CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_15_ETC__q272 = coreFix_aluExe_0_dispToRegQ$first[152:132]; 3'd4: - CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_15_ETC__q282 = + CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_15_ETC__q272 = { coreFix_aluExe_0_dispToRegQ$first[152:150], 9'h0AA, coreFix_aluExe_0_dispToRegQ$first[140:136], - CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q281, + CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q271, coreFix_aluExe_0_dispToRegQ$first[132] }; - default: CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_15_ETC__q282 = + default: CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_15_ETC__q272 = 21'd1485482; endcase end @@ -38845,9 +38437,9 @@ module mkCore(CLK, 12'd3858, 12'd3859, 12'd3860: - CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q283 = + CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q273 = coreFix_aluExe_0_dispToRegQ$first[130:119]; - default: CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q283 = + default: CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q273 = 12'd2303; endcase end @@ -38855,26 +38447,26 @@ module mkCore(CLK, begin case (coreFix_aluExe_1_rsAlu$dispatchData[139:137]) 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q284 = + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q274 = coreFix_aluExe_1_rsAlu$dispatchData[139:137]; - default: CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q284 = 3'd7; + default: CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q274 = 3'd7; endcase end always@(coreFix_aluExe_1_rsAlu$dispatchData or - CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q284) + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q274) begin case (coreFix_aluExe_1_rsAlu$dispatchData[156:154]) 3'd0, 3'd1, 3'd2, 3'd3: - CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q285 = + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q275 = coreFix_aluExe_1_rsAlu$dispatchData[156:136]; 3'd4: - CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q285 = + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q275 = { coreFix_aluExe_1_rsAlu$dispatchData[156:154], 9'h0AA, coreFix_aluExe_1_rsAlu$dispatchData[144:140], - CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q284, + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q274, coreFix_aluExe_1_rsAlu$dispatchData[136] }; - default: CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q285 = + default: CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q275 = 21'd1485482; endcase end @@ -38921,9 +38513,9 @@ module mkCore(CLK, 12'd3858, 12'd3859, 12'd3860: - CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q286 = + CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q276 = coreFix_aluExe_1_rsAlu$dispatchData[134:123]; - default: CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q286 = + default: CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q276 = 12'd2303; endcase end @@ -38931,26 +38523,26 @@ module mkCore(CLK, begin case (coreFix_aluExe_1_dispToRegQ$first[135:133]) 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q287 = + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q277 = coreFix_aluExe_1_dispToRegQ$first[135:133]; - default: CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q287 = 3'd7; + default: CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q277 = 3'd7; endcase end always@(coreFix_aluExe_1_dispToRegQ$first or - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q287) + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q277) begin case (coreFix_aluExe_1_dispToRegQ$first[152:150]) 3'd0, 3'd1, 3'd2, 3'd3: - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_15_ETC__q288 = + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_15_ETC__q278 = coreFix_aluExe_1_dispToRegQ$first[152:132]; 3'd4: - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_15_ETC__q288 = + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_15_ETC__q278 = { coreFix_aluExe_1_dispToRegQ$first[152:150], 9'h0AA, coreFix_aluExe_1_dispToRegQ$first[140:136], - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q287, + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q277, coreFix_aluExe_1_dispToRegQ$first[132] }; - default: CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_15_ETC__q288 = + default: CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_15_ETC__q278 = 21'd1485482; endcase end @@ -38997,9 +38589,9 @@ module mkCore(CLK, 12'd3858, 12'd3859, 12'd3860: - CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q289 = + CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q279 = coreFix_aluExe_1_dispToRegQ$first[130:119]; - default: CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q289 = + default: CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q279 = 12'd2303; endcase end @@ -39007,26 +38599,26 @@ module mkCore(CLK, begin case (coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[69:67]) 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q290 = + CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q280 = coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[69:67]; - default: CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q290 = 3'd7; + default: CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q280 = 3'd7; endcase end always@(coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData or - CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q290) + CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q280) begin case (coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[86:84]) 3'd0, 3'd1, 3'd2, 3'd3: - CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q291 = + CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q281 = coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[86:66]; 3'd4: - CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q291 = + CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q281 = { coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[86:84], 9'h0AA, coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[74:70], - CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q290, + CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q280, coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[66] }; - default: CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q291 = + default: CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q281 = 21'd1485482; endcase end @@ -39038,16 +38630,16 @@ module mkCore(CLK, begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229]) 5'd0: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q292 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q282 = IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10765; 5'd1: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q292 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q282 = coreFix_fpuMulDivExe_0_regToExeQ$first[225] ? { !coreFix_fpuMulDivExe_0_regToExeQ$first[139], coreFix_fpuMulDivExe_0_regToExeQ$first[138:76] } : { IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10818, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10763 }; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q292 = + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q282 = IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9285; endcase end @@ -39056,9 +38648,9 @@ module mkCore(CLK, begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229]) 5'd0, 5'd1: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q293 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q283 = 64'h3FF0000000000000; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q293 = + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q283 = IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10765; endcase end @@ -39066,26 +38658,26 @@ module mkCore(CLK, begin case (coreFix_fpuMulDivExe_0_dispToRegQ$first[60:58]) 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q294 = + CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q284 = coreFix_fpuMulDivExe_0_dispToRegQ$first[60:58]; - default: CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q294 = 3'd7; + default: CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q284 = 3'd7; endcase end always@(coreFix_fpuMulDivExe_0_dispToRegQ$first or - CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q294) + CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q284) begin case (coreFix_fpuMulDivExe_0_dispToRegQ$first[77:75]) 3'd0, 3'd1, 3'd2, 3'd3: - CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q295 = + CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q285 = coreFix_fpuMulDivExe_0_dispToRegQ$first[77:57]; 3'd4: - CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q295 = + CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q285 = { coreFix_fpuMulDivExe_0_dispToRegQ$first[77:75], 9'h0AA, coreFix_fpuMulDivExe_0_dispToRegQ$first[65:61], - CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q294, + CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q284, coreFix_fpuMulDivExe_0_dispToRegQ$first[57] }; - default: CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q295 = + default: CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q285 = 21'd1485482; endcase end @@ -39095,71 +38687,13 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q296 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q286 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[1:0]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q296 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q286 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[1:0]; endcase end - always@(rob$deqPort_1_deq_data) - begin - case (rob$deqPort_1_deq_data[180:169]) - 12'd1, - 12'd2, - 12'd3, - 12'd256, - 12'd260, - 12'd261, - 12'd262, - 12'd320, - 12'd321, - 12'd322, - 12'd323, - 12'd324, - 12'd384, - 12'd768, - 12'd769, - 12'd770, - 12'd771, - 12'd772, - 12'd773, - 12'd774, - 12'd832, - 12'd833, - 12'd834, - 12'd835, - 12'd836, - 12'd1968, - 12'd1969, - 12'd1970, - 12'd1971, - 12'd2048, - 12'd2049, - 12'd2816, - 12'd2818, - 12'd3072, - 12'd3073, - 12'd3074, - 12'd3857, - 12'd3858, - 12'd3859, - 12'd3860: - CASE_robdeqPort_1_deq_data_BITS_180_TO_169_1__ETC__q297 = - rob$deqPort_1_deq_data[180:169]; - default: CASE_robdeqPort_1_deq_data_BITS_180_TO_169_1__ETC__q297 = - 12'd2303; - endcase - end - always@(rob$deqPort_1_deq_data) - begin - case (rob$deqPort_1_deq_data[97:96]) - 2'd0, 2'd1: - CASE_robdeqPort_1_deq_data_BITS_97_TO_96_0_ro_ETC__q298 = - rob$deqPort_1_deq_data[97:96]; - default: CASE_robdeqPort_1_deq_data_BITS_97_TO_96_0_ro_ETC__q298 = 2'd2; - endcase - end // handling of inlined registers @@ -39338,7 +38872,6 @@ module mkCore(CLK, coreFix_memExe_respLrScAmoQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0; coreFix_memExe_waitLrScAmoMMIOResp <= `BSV_ASSIGNMENT_DELAY 3'd0; csrInstOrInterruptInflight_rl <= `BSV_ASSIGNMENT_DELAY 1'd0; - csrf_debug_int_pend <= `BSV_ASSIGNMENT_DELAY 1'd0; csrf_external_int_en_vec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0; csrf_external_int_en_vec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; csrf_external_int_en_vec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0; @@ -39781,9 +39314,6 @@ module mkCore(CLK, if (csrInstOrInterruptInflight_rl$EN) csrInstOrInterruptInflight_rl <= `BSV_ASSIGNMENT_DELAY csrInstOrInterruptInflight_rl$D_IN; - if (csrf_debug_int_pend$EN) - csrf_debug_int_pend <= `BSV_ASSIGNMENT_DELAY - csrf_debug_int_pend$D_IN; if (csrf_external_int_en_vec_0$EN) csrf_external_int_en_vec_0 <= `BSV_ASSIGNMENT_DELAY csrf_external_int_en_vec_0$D_IN; @@ -40235,7 +39765,6 @@ module mkCore(CLK, coreFix_memExe_respLrScAmoQ_full = 1'h0; coreFix_memExe_waitLrScAmoMMIOResp = 3'h2; csrInstOrInterruptInflight_rl = 1'h0; - csrf_debug_int_pend = 1'h0; csrf_external_int_en_vec_0 = 1'h0; csrf_external_int_en_vec_1 = 1'h0; csrf_external_int_en_vec_3 = 1'h0; @@ -40685,14 +40214,14 @@ module mkCore(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[186:182] == 5'd13 && - IF_rob_deqPort_0_deq_data__4547_BIT_181_4617_T_ETC___d14989 == 6'd6) + IF_rob_deqPort_0_deq_data__4542_BIT_181_4849_T_ETC___d14931 == 6'd6) $display("[Terminate CSR] being written (val = %x), ", "send terminate signal to host", rob$deqPort_0_deq_data[95:32]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && - next_pc__h718537 != - rob_deqPort_0_deq_data__4547_BITS_282_TO_219_4_ETC___d15180) + next_pc__h716406 != + rob_deqPort_0_deq_data__4542_BITS_282_TO_219_4_ETC___d15122) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && @@ -40829,7 +40358,8 @@ module mkCore(CLK, rob$deqPort_1_deq_data[186:182] != 5'd19 && rob$deqPort_1_deq_data[186:182] != 5'd20) $write("instret:%0d PC:0x%0h instr:0x%08h", - x__h722429, + commitStage_rg_serialnum + + IF_rob_deqPort_0_canDeq__5156_THEN_IF_NOT_rob__ETC___d15265, rob$deqPort_1_deq_data[282:219], rob$deqPort_1_deq_data[218:187], " iType:"); @@ -41025,14 +40555,14 @@ module mkCore(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_aluExe_1_doExeAlu && coreFix_aluExe_1_regToExeQ$first[395] && - basicExec___d12107[0]) + basicExec___d12104[0]) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_aluExe_1_doExeAlu && coreFix_aluExe_1_regToExeQ$first[395] && - (basicExec___d12107[65:2] != + (basicExec___d12104[65:2] != coreFix_aluExe_1_regToExeQ$first[112:49] || - coreFix_aluExe_1_regToExeQ$first[112:49] != y__h623720)) + coreFix_aluExe_1_regToExeQ$first[112:49] != y__h623385)) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu && @@ -41042,14 +40572,14 @@ module mkCore(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu && coreFix_aluExe_0_regToExeQ$first[395] && - basicExec___d12781[0]) + basicExec___d12778[0]) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu && coreFix_aluExe_0_regToExeQ$first[395] && - (basicExec___d12781[65:2] != + (basicExec___d12778[65:2] != coreFix_aluExe_0_regToExeQ$first[112:49] || - coreFix_aluExe_0_regToExeQ$first[112:49] != y__h645787)) + coreFix_aluExe_0_regToExeQ$first[112:49] != y__h645451)) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_aluExe_1_doRegReadAlu && @@ -41075,19 +40605,19 @@ module mkCore(CLK, !coreFix_aluExe_0_dispToRegQ$first[131] && coreFix_aluExe_0_dispToRegQ$first[85] && !sbCons$lazyLookup_0_get[3] && - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__237_ETC___d12409 && - NOT_coreFix_aluExe_0_bypassWire_0_whas__2372_2_ETC___d12399 && + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12406 && + NOT_coreFix_aluExe_0_bypassWire_0_whas__2369_2_ETC___d12396 && (!coreFix_aluExe_0_bypassWire_3$whas || - !coreFix_aluExe_0_bypassWire_3_wget__2401_BITS__ETC___d12403)) + !coreFix_aluExe_0_bypassWire_3_wget__2398_BITS__ETC___d12400)) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_aluExe_0_doRegReadAlu && coreFix_aluExe_0_dispToRegQ$first[77] && !sbCons$lazyLookup_0_get[2] && - IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__237_ETC___d12436 && - NOT_coreFix_aluExe_0_bypassWire_0_whas__2372_2_ETC___d12429 && + IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12433 && + NOT_coreFix_aluExe_0_bypassWire_0_whas__2369_2_ETC___d12426 && (!coreFix_aluExe_0_bypassWire_3$whas || - !coreFix_aluExe_0_bypassWire_3_wget__2401_BITS__ETC___d12430)) + !coreFix_aluExe_0_bypassWire_3_wget__2398_BITS__ETC___d12427)) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul && @@ -41144,6 +40674,15 @@ module mkCore(CLK, coreFix_memExe_lsq$firstSt[158:157] != 2'd0 && coreFix_memExe_lsq$firstSt[158:157] != 2'd2) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[158:157] != 2'd0 && + coreFix_memExe_lsq$firstSt[158:157] != 2'd2) + $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[4]) + $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && (coreFix_memExe_lsq$firstSt[158:157] != 2'd1 && @@ -41154,15 +40693,6 @@ module mkCore(CLK, if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && coreFix_memExe_lsq$firstSt[4]) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && - coreFix_memExe_lsq$firstSt[158:157] != 2'd0 && - coreFix_memExe_lsq$firstSt[158:157] != 2'd2) - $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && - coreFix_memExe_lsq$firstSt[4]) - $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && coreFix_memExe_lsq$firstSt[158:157] != 2'd0 && @@ -41366,7 +40896,7 @@ module mkCore(CLK, $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas && - v__h607011 == 2'd0) + v__h606702 == 2'd0) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming_SystemInst && @@ -41401,66 +40931,66 @@ module mkCore(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3582_AND__ETC___d14290) + regRenamingTable_rename_0_canRename__3578_AND__ETC___d14286) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3582_AND__ETC___d14295) + regRenamingTable_rename_0_canRename__3578_AND__ETC___d14291) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3582_AND__ETC___d14320) + regRenamingTable_rename_0_canRename__3578_AND__ETC___d14316) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3582_AND__ETC___d14324) + regRenamingTable_rename_0_canRename__3578_AND__ETC___d14320) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3582_AND__ETC___d14330) + regRenamingTable_rename_0_canRename__3578_AND__ETC___d14326) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d14458) + NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d14454) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d14388 && - regRenamingTable_rename_1_canRename__3704_AND__ETC___d14398 && + NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d14384 && + regRenamingTable_rename_1_canRename__3700_AND__ETC___d14394 && fetchStage$pipelines_1_first[194:192] != 3'd0 && fetchStage$pipelines_1_first[194:192] != 3'd1 && (fetchStage$pipelines_1_first[194:192] == 3'd3 || fetchStage$pipelines_1_first[194:192] == 3'd4) && - NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d14438 && + NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d14434 && coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq && fetchStage$pipelines_1_first[173]) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d14388 && - regRenamingTable_rename_1_canRename__3704_AND__ETC___d14398 && + NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d14384 && + regRenamingTable_rename_1_canRename__3700_AND__ETC___d14394 && fetchStage$pipelines_1_first[194:192] == 3'd2 && - NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d14466 && - NOT_fetchStage_pipelines_1_first__2943_BITS_32_ETC___d14453) + NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d14462 && + NOT_fetchStage_pipelines_1_first__2940_BITS_32_ETC___d14449) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d14388 && - regRenamingTable_rename_1_canRename__3704_AND__ETC___d14398 && + NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d14384 && + regRenamingTable_rename_1_canRename__3700_AND__ETC___d14394 && fetchStage$pipelines_1_first[194:192] == 3'd2 && - NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d14466 && + NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d14462 && fetchStage$pipelines_1_first[173]) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d14388 && - regRenamingTable_rename_1_canRename__3704_AND__ETC___d14398 && + NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d14384 && + regRenamingTable_rename_1_canRename__3700_AND__ETC___d14394 && fetchStage$pipelines_1_first[194:192] == 3'd2 && - NOT_fetchStage_pipelines_0_canDeq__2932_2933_O_ETC___d14466 && + NOT_fetchStage_pipelines_0_canDeq__2929_2930_O_ETC___d14462 && (fetchStage$pipelines_1_first[199:195] != 5'd14) != fetchStage$pipelines_1_first[160]) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkCoreW.v b/src_SSITH_P3_sim/Verilog_RTL/mkCoreW.v index 7d3a5b9..e6861a1 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkCoreW.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkCoreW.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // @@ -7,9 +7,7 @@ // Ports: // Name I/O size props // RDY_set_verbosity O 1 const -// RDY_set_htif_addrs O 1 const -// RDY_cpu_reset_server_request_put O 1 reg -// RDY_cpu_reset_server_response_get O 1 reg +// RDY_start O 1 // cpu_imem_master_awvalid O 1 // cpu_imem_master_awid O 4 reg // cpu_imem_master_awaddr O 64 reg @@ -22,7 +20,6 @@ // cpu_imem_master_awqos O 4 reg // cpu_imem_master_awregion O 4 reg // cpu_imem_master_wvalid O 1 -// cpu_imem_master_wid O 4 reg // cpu_imem_master_wdata O 64 reg // cpu_imem_master_wstrb O 8 reg // cpu_imem_master_wlast O 1 reg @@ -51,7 +48,6 @@ // cpu_dmem_master_awqos O 4 reg // cpu_dmem_master_awregion O 4 reg // cpu_dmem_master_wvalid O 1 reg -// cpu_dmem_master_wid O 4 reg // cpu_dmem_master_wdata O 64 reg // cpu_dmem_master_wstrb O 8 reg // cpu_dmem_master_wlast O 1 reg @@ -68,19 +64,20 @@ // cpu_dmem_master_arqos O 4 reg // cpu_dmem_master_arregion O 4 reg // cpu_dmem_master_rready O 1 reg -// RDY_dm_dmi_read_addr O 1 -// dm_dmi_read_data O 32 -// RDY_dm_dmi_read_data O 1 -// RDY_dm_dmi_write O 1 -// RDY_dm_ndm_reset_req_get_get O 1 reg -// tv_verifier_info_get_get O 608 reg -// RDY_tv_verifier_info_get_get O 1 reg +// RDY_dmi_read_addr O 1 +// dmi_read_data O 32 +// RDY_dmi_read_data O 1 +// RDY_dmi_write O 1 +// ndm_reset_client_request_get O 1 reg +// RDY_ndm_reset_client_request_get O 1 reg +// RDY_ndm_reset_client_response_put O 1 reg +// RST_N_dm_power_on_reset I 1 reset // CLK I 1 clock // RST_N I 1 reset // set_verbosity_verbosity I 4 // set_verbosity_logdelay I 64 unused -// set_htif_addrs_tohost_addr I 64 reg -// set_htif_addrs_fromhost_addr I 64 reg +// start_tohost_addr I 64 +// start_fromhost_addr I 64 // cpu_imem_master_awready I 1 // cpu_imem_master_wready I 1 // cpu_imem_master_bvalid I 1 @@ -119,26 +116,23 @@ // core_external_interrupt_sources_13_m_interrupt_req_set_not_clear I 1 // core_external_interrupt_sources_14_m_interrupt_req_set_not_clear I 1 // core_external_interrupt_sources_15_m_interrupt_req_set_not_clear I 1 -// debug_external_interrupt_req_set_not_clear I 1 -// dm_dmi_read_addr_dm_addr I 7 -// dm_dmi_write_dm_addr I 7 -// dm_dmi_write_dm_word I 32 +// nmi_req_set_not_clear I 1 unused +// dmi_read_addr_dm_addr I 7 +// dmi_write_dm_addr I 7 +// dmi_write_dm_word I 32 +// ndm_reset_client_response_put I 1 reg // EN_set_verbosity I 1 -// EN_set_htif_addrs I 1 -// EN_cpu_reset_server_request_put I 1 -// EN_cpu_reset_server_response_get I 1 -// EN_dm_dmi_read_addr I 1 -// EN_dm_dmi_write I 1 -// EN_dm_ndm_reset_req_get_get I 1 -// EN_dm_dmi_read_data I 1 -// EN_tv_verifier_info_get_get I 1 +// EN_start I 1 +// EN_dmi_read_addr I 1 +// EN_dmi_write I 1 +// EN_ndm_reset_client_response_put I 1 +// EN_dmi_read_data I 1 +// EN_ndm_reset_client_request_get I 1 // // Combinational paths from inputs to outputs: // (cpu_imem_master_awready, cpu_imem_master_wready) -> cpu_imem_master_bready -// (dm_dmi_read_addr_dm_addr, EN_dm_dmi_read_addr) -> RDY_dm_dmi_read_data -// (dm_dmi_read_addr_dm_addr, -// EN_dm_dmi_read_addr, -// EN_dm_dmi_read_data) -> dm_dmi_read_data +// (dmi_read_addr_dm_addr, EN_dmi_read_addr) -> RDY_dmi_read_data +// (dmi_read_addr_dm_addr, EN_dmi_read_addr, EN_dmi_read_data) -> dmi_read_data // // @@ -155,7 +149,8 @@ `define BSV_RESET_EDGE negedge `endif -module mkCoreW(CLK, +module mkCoreW(RST_N_dm_power_on_reset, + CLK, RST_N, set_verbosity_verbosity, @@ -163,16 +158,10 @@ module mkCoreW(CLK, EN_set_verbosity, RDY_set_verbosity, - set_htif_addrs_tohost_addr, - set_htif_addrs_fromhost_addr, - EN_set_htif_addrs, - RDY_set_htif_addrs, - - EN_cpu_reset_server_request_put, - RDY_cpu_reset_server_request_put, - - EN_cpu_reset_server_response_get, - RDY_cpu_reset_server_response_get, + start_tohost_addr, + start_fromhost_addr, + EN_start, + RDY_start, cpu_imem_master_awvalid, @@ -200,8 +189,6 @@ module mkCoreW(CLK, cpu_imem_master_wvalid, - cpu_imem_master_wid, - cpu_imem_master_wdata, cpu_imem_master_wstrb, @@ -274,8 +261,6 @@ module mkCoreW(CLK, cpu_dmem_master_wvalid, - cpu_dmem_master_wid, - cpu_dmem_master_wdata, cpu_dmem_master_wstrb, @@ -354,27 +339,29 @@ module mkCoreW(CLK, core_external_interrupt_sources_15_m_interrupt_req_set_not_clear, - debug_external_interrupt_req_set_not_clear, + nmi_req_set_not_clear, - dm_dmi_read_addr_dm_addr, - EN_dm_dmi_read_addr, - RDY_dm_dmi_read_addr, + dmi_read_addr_dm_addr, + EN_dmi_read_addr, + RDY_dmi_read_addr, - EN_dm_dmi_read_data, - dm_dmi_read_data, - RDY_dm_dmi_read_data, + EN_dmi_read_data, + dmi_read_data, + RDY_dmi_read_data, - dm_dmi_write_dm_addr, - dm_dmi_write_dm_word, - EN_dm_dmi_write, - RDY_dm_dmi_write, + dmi_write_dm_addr, + dmi_write_dm_word, + EN_dmi_write, + RDY_dmi_write, - EN_dm_ndm_reset_req_get_get, - RDY_dm_ndm_reset_req_get_get, + EN_ndm_reset_client_request_get, + ndm_reset_client_request_get, + RDY_ndm_reset_client_request_get, - EN_tv_verifier_info_get_get, - tv_verifier_info_get_get, - RDY_tv_verifier_info_get_get); + ndm_reset_client_response_put, + EN_ndm_reset_client_response_put, + RDY_ndm_reset_client_response_put); + input RST_N_dm_power_on_reset; input CLK; input RST_N; @@ -384,19 +371,11 @@ module mkCoreW(CLK, input EN_set_verbosity; output RDY_set_verbosity; - // action method set_htif_addrs - input [63 : 0] set_htif_addrs_tohost_addr; - input [63 : 0] set_htif_addrs_fromhost_addr; - input EN_set_htif_addrs; - output RDY_set_htif_addrs; - - // action method cpu_reset_server_request_put - input EN_cpu_reset_server_request_put; - output RDY_cpu_reset_server_request_put; - - // action method cpu_reset_server_response_get - input EN_cpu_reset_server_response_get; - output RDY_cpu_reset_server_response_get; + // action method start + input [63 : 0] start_tohost_addr; + input [63 : 0] start_fromhost_addr; + input EN_start; + output RDY_start; // value method cpu_imem_master_m_awvalid output cpu_imem_master_awvalid; @@ -439,9 +418,6 @@ module mkCoreW(CLK, // value method cpu_imem_master_m_wvalid output cpu_imem_master_wvalid; - // value method cpu_imem_master_m_wid - output [3 : 0] cpu_imem_master_wid; - // value method cpu_imem_master_m_wdata output [63 : 0] cpu_imem_master_wdata; @@ -553,9 +529,6 @@ module mkCoreW(CLK, // value method cpu_dmem_master_m_wvalid output cpu_dmem_master_wvalid; - // value method cpu_dmem_master_m_wid - output [3 : 0] cpu_dmem_master_wid; - // value method cpu_dmem_master_m_wdata output [63 : 0] cpu_dmem_master_wdata; @@ -674,43 +647,43 @@ module mkCoreW(CLK, // action method core_external_interrupt_sources_15_m_interrupt_req input core_external_interrupt_sources_15_m_interrupt_req_set_not_clear; - // action method debug_external_interrupt_req - input debug_external_interrupt_req_set_not_clear; + // action method nmi_req + input nmi_req_set_not_clear; - // action method dm_dmi_read_addr - input [6 : 0] dm_dmi_read_addr_dm_addr; - input EN_dm_dmi_read_addr; - output RDY_dm_dmi_read_addr; + // action method dmi_read_addr + input [6 : 0] dmi_read_addr_dm_addr; + input EN_dmi_read_addr; + output RDY_dmi_read_addr; - // actionvalue method dm_dmi_read_data - input EN_dm_dmi_read_data; - output [31 : 0] dm_dmi_read_data; - output RDY_dm_dmi_read_data; + // actionvalue method dmi_read_data + input EN_dmi_read_data; + output [31 : 0] dmi_read_data; + output RDY_dmi_read_data; - // action method dm_dmi_write - input [6 : 0] dm_dmi_write_dm_addr; - input [31 : 0] dm_dmi_write_dm_word; - input EN_dm_dmi_write; - output RDY_dm_dmi_write; + // action method dmi_write + input [6 : 0] dmi_write_dm_addr; + input [31 : 0] dmi_write_dm_word; + input EN_dmi_write; + output RDY_dmi_write; - // action method dm_ndm_reset_req_get_get - input EN_dm_ndm_reset_req_get_get; - output RDY_dm_ndm_reset_req_get_get; + // actionvalue method ndm_reset_client_request_get + input EN_ndm_reset_client_request_get; + output ndm_reset_client_request_get; + output RDY_ndm_reset_client_request_get; - // actionvalue method tv_verifier_info_get_get - input EN_tv_verifier_info_get_get; - output [607 : 0] tv_verifier_info_get_get; - output RDY_tv_verifier_info_get_get; + // action method ndm_reset_client_response_put + input ndm_reset_client_response_put; + input EN_ndm_reset_client_response_put; + output RDY_ndm_reset_client_response_put; // signals for module outputs - wire [607 : 0] tv_verifier_info_get_get; wire [63 : 0] cpu_dmem_master_araddr, cpu_dmem_master_awaddr, cpu_dmem_master_wdata, cpu_imem_master_araddr, cpu_imem_master_awaddr, cpu_imem_master_wdata; - wire [31 : 0] dm_dmi_read_data; + wire [31 : 0] dmi_read_data; wire [7 : 0] cpu_dmem_master_arlen, cpu_dmem_master_awlen, cpu_dmem_master_wstrb, @@ -725,7 +698,6 @@ module mkCoreW(CLK, cpu_dmem_master_awid, cpu_dmem_master_awqos, cpu_dmem_master_awregion, - cpu_dmem_master_wid, cpu_imem_master_arcache, cpu_imem_master_arid, cpu_imem_master_arqos, @@ -733,8 +705,7 @@ module mkCoreW(CLK, cpu_imem_master_awcache, cpu_imem_master_awid, cpu_imem_master_awqos, - cpu_imem_master_awregion, - cpu_imem_master_wid; + cpu_imem_master_awregion; wire [2 : 0] cpu_dmem_master_arprot, cpu_dmem_master_arsize, cpu_dmem_master_awprot, @@ -747,15 +718,13 @@ module mkCoreW(CLK, cpu_dmem_master_awburst, cpu_imem_master_arburst, cpu_imem_master_awburst; - wire RDY_cpu_reset_server_request_put, - RDY_cpu_reset_server_response_get, - RDY_dm_dmi_read_addr, - RDY_dm_dmi_read_data, - RDY_dm_dmi_write, - RDY_dm_ndm_reset_req_get_get, - RDY_set_htif_addrs, + wire RDY_dmi_read_addr, + RDY_dmi_read_data, + RDY_dmi_write, + RDY_ndm_reset_client_request_get, + RDY_ndm_reset_client_response_put, RDY_set_verbosity, - RDY_tv_verifier_info_get_get, + RDY_start, cpu_dmem_master_arlock, cpu_dmem_master_arvalid, cpu_dmem_master_awlock, @@ -771,13 +740,19 @@ module mkCoreW(CLK, cpu_imem_master_bready, cpu_imem_master_rready, cpu_imem_master_wlast, - cpu_imem_master_wvalid; + cpu_imem_master_wvalid, + ndm_reset_client_request_get; // register rg_fromhost_addr reg [63 : 0] rg_fromhost_addr; wire [63 : 0] rg_fromhost_addr$D_IN; wire rg_fromhost_addr$EN; + // register rg_hart0_reset_delay + reg [7 : 0] rg_hart0_reset_delay; + wire [7 : 0] rg_hart0_reset_delay$D_IN; + wire rg_hart0_reset_delay$EN; + // register rg_tohost_addr reg [63 : 0] rg_tohost_addr; wire [63 : 0] rg_tohost_addr$D_IN; @@ -809,8 +784,7 @@ module mkCoreW(CLK, debug_module$master_awqos, debug_module$master_awregion, debug_module$master_bid, - debug_module$master_rid, - debug_module$master_wid; + debug_module$master_rid; wire [2 : 0] debug_module$master_arprot, debug_module$master_arsize, debug_module$master_awprot, @@ -822,7 +796,6 @@ module mkCoreW(CLK, wire debug_module$EN_dmi_read_addr, debug_module$EN_dmi_read_data, debug_module$EN_dmi_write, - debug_module$EN_get_ndm_reset_req_get, debug_module$EN_hart0_client_run_halt_request_get, debug_module$EN_hart0_client_run_halt_response_put, debug_module$EN_hart0_csr_mem_client_request_get, @@ -830,23 +803,29 @@ module mkCoreW(CLK, debug_module$EN_hart0_fpr_mem_client_request_get, debug_module$EN_hart0_fpr_mem_client_response_put, debug_module$EN_hart0_get_other_req_get, - debug_module$EN_hart0_get_reset_req_get, debug_module$EN_hart0_gpr_mem_client_request_get, debug_module$EN_hart0_gpr_mem_client_response_put, + debug_module$EN_hart0_reset_client_request_get, + debug_module$EN_hart0_reset_client_response_put, + debug_module$EN_ndm_reset_client_request_get, + debug_module$EN_ndm_reset_client_response_put, debug_module$RDY_dmi_read_addr, debug_module$RDY_dmi_read_data, debug_module$RDY_dmi_write, - debug_module$RDY_get_ndm_reset_req_get, debug_module$RDY_hart0_client_run_halt_request_get, debug_module$RDY_hart0_client_run_halt_response_put, debug_module$RDY_hart0_csr_mem_client_request_get, debug_module$RDY_hart0_csr_mem_client_response_put, debug_module$RDY_hart0_get_other_req_get, - debug_module$RDY_hart0_get_reset_req_get, debug_module$RDY_hart0_gpr_mem_client_request_get, debug_module$RDY_hart0_gpr_mem_client_response_put, + debug_module$RDY_hart0_reset_client_request_get, + debug_module$RDY_hart0_reset_client_response_put, + debug_module$RDY_ndm_reset_client_request_get, + debug_module$RDY_ndm_reset_client_response_put, debug_module$hart0_client_run_halt_request_get, debug_module$hart0_client_run_halt_response_put, + debug_module$hart0_reset_client_response_put, debug_module$master_arlock, debug_module$master_arready, debug_module$master_arvalid, @@ -860,148 +839,12 @@ module mkCoreW(CLK, debug_module$master_rvalid, debug_module$master_wlast, debug_module$master_wready, - debug_module$master_wvalid; + debug_module$master_wvalid, + debug_module$ndm_reset_client_request_get, + debug_module$ndm_reset_client_response_put; - // ports of submodule dm_csr_tap - wire [426 : 0] dm_csr_tap$trace_data_out_get; - wire [76 : 0] dm_csr_tap$client_request_get, dm_csr_tap$server_request_put; - wire [64 : 0] dm_csr_tap$client_response_put, - dm_csr_tap$server_response_get; - wire dm_csr_tap$EN_client_request_get, - dm_csr_tap$EN_client_response_put, - dm_csr_tap$EN_server_request_put, - dm_csr_tap$EN_server_response_get, - dm_csr_tap$EN_trace_data_out_get, - dm_csr_tap$RDY_client_request_get, - dm_csr_tap$RDY_client_response_put, - dm_csr_tap$RDY_server_request_put, - dm_csr_tap$RDY_server_response_get, - dm_csr_tap$RDY_trace_data_out_get; - - // ports of submodule dm_gpr_tap_ifc - wire [426 : 0] dm_gpr_tap_ifc$trace_data_out_get; - wire [69 : 0] dm_gpr_tap_ifc$client_request_get, - dm_gpr_tap_ifc$server_request_put; - wire [64 : 0] dm_gpr_tap_ifc$client_response_put, - dm_gpr_tap_ifc$server_response_get; - wire dm_gpr_tap_ifc$EN_client_request_get, - dm_gpr_tap_ifc$EN_client_response_put, - dm_gpr_tap_ifc$EN_server_request_put, - dm_gpr_tap_ifc$EN_server_response_get, - dm_gpr_tap_ifc$EN_trace_data_out_get, - dm_gpr_tap_ifc$RDY_client_request_get, - dm_gpr_tap_ifc$RDY_client_response_put, - dm_gpr_tap_ifc$RDY_server_request_put, - dm_gpr_tap_ifc$RDY_server_response_get, - dm_gpr_tap_ifc$RDY_trace_data_out_get; - - // ports of submodule dm_mem_tap - wire [426 : 0] dm_mem_tap$trace_data_out_get; - wire [63 : 0] dm_mem_tap$master_araddr, - dm_mem_tap$master_awaddr, - dm_mem_tap$master_rdata, - dm_mem_tap$master_wdata, - dm_mem_tap$slave_araddr, - dm_mem_tap$slave_awaddr, - dm_mem_tap$slave_rdata, - dm_mem_tap$slave_wdata; - wire [7 : 0] dm_mem_tap$master_arlen, - dm_mem_tap$master_awlen, - dm_mem_tap$master_wstrb, - dm_mem_tap$slave_arlen, - dm_mem_tap$slave_awlen, - dm_mem_tap$slave_wstrb; - wire [3 : 0] dm_mem_tap$master_arcache, - dm_mem_tap$master_arid, - dm_mem_tap$master_arqos, - dm_mem_tap$master_arregion, - dm_mem_tap$master_awcache, - dm_mem_tap$master_awid, - dm_mem_tap$master_awqos, - dm_mem_tap$master_awregion, - dm_mem_tap$master_bid, - dm_mem_tap$master_rid, - dm_mem_tap$master_wid, - dm_mem_tap$slave_arcache, - dm_mem_tap$slave_arid, - dm_mem_tap$slave_arqos, - dm_mem_tap$slave_arregion, - dm_mem_tap$slave_awcache, - dm_mem_tap$slave_awid, - dm_mem_tap$slave_awqos, - dm_mem_tap$slave_awregion, - dm_mem_tap$slave_bid, - dm_mem_tap$slave_rid, - dm_mem_tap$slave_wid; - wire [2 : 0] dm_mem_tap$master_arprot, - dm_mem_tap$master_arsize, - dm_mem_tap$master_awprot, - dm_mem_tap$master_awsize, - dm_mem_tap$slave_arprot, - dm_mem_tap$slave_arsize, - dm_mem_tap$slave_awprot, - dm_mem_tap$slave_awsize; - wire [1 : 0] dm_mem_tap$master_arburst, - dm_mem_tap$master_awburst, - dm_mem_tap$master_bresp, - dm_mem_tap$master_rresp, - dm_mem_tap$slave_arburst, - dm_mem_tap$slave_awburst, - dm_mem_tap$slave_bresp, - dm_mem_tap$slave_rresp; - wire dm_mem_tap$EN_trace_data_out_get, - dm_mem_tap$RDY_trace_data_out_get, - dm_mem_tap$master_arlock, - dm_mem_tap$master_arready, - dm_mem_tap$master_arvalid, - dm_mem_tap$master_awlock, - dm_mem_tap$master_awready, - dm_mem_tap$master_awvalid, - dm_mem_tap$master_bready, - dm_mem_tap$master_bvalid, - dm_mem_tap$master_rlast, - dm_mem_tap$master_rready, - dm_mem_tap$master_rvalid, - dm_mem_tap$master_wlast, - dm_mem_tap$master_wready, - dm_mem_tap$master_wvalid, - dm_mem_tap$slave_arlock, - dm_mem_tap$slave_arready, - dm_mem_tap$slave_arvalid, - dm_mem_tap$slave_awlock, - dm_mem_tap$slave_awready, - dm_mem_tap$slave_awvalid, - dm_mem_tap$slave_bready, - dm_mem_tap$slave_bvalid, - dm_mem_tap$slave_rlast, - dm_mem_tap$slave_rready, - dm_mem_tap$slave_rvalid, - dm_mem_tap$slave_wlast, - dm_mem_tap$slave_wready, - dm_mem_tap$slave_wvalid; - - // ports of submodule f_reset_reqs - wire f_reset_reqs$CLR, - f_reset_reqs$DEQ, - f_reset_reqs$EMPTY_N, - f_reset_reqs$ENQ, - f_reset_reqs$FULL_N; - - // ports of submodule f_reset_requestor - wire f_reset_requestor$CLR, - f_reset_requestor$DEQ, - f_reset_requestor$D_IN, - f_reset_requestor$D_OUT, - f_reset_requestor$EMPTY_N, - f_reset_requestor$ENQ, - f_reset_requestor$FULL_N; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; + // ports of submodule dm_hart0_reset_controller + wire dm_hart0_reset_controller$ASSERT_IN, dm_hart0_reset_controller$OUT_RST; // ports of submodule fabric_2x3 wire [63 : 0] fabric_2x3$v_from_masters_0_araddr, @@ -1050,7 +893,6 @@ module mkCoreW(CLK, fabric_2x3$v_from_masters_0_awregion, fabric_2x3$v_from_masters_0_bid, fabric_2x3$v_from_masters_0_rid, - fabric_2x3$v_from_masters_0_wid, fabric_2x3$v_from_masters_1_arcache, fabric_2x3$v_from_masters_1_arid, fabric_2x3$v_from_masters_1_arqos, @@ -1061,7 +903,6 @@ module mkCoreW(CLK, fabric_2x3$v_from_masters_1_awregion, fabric_2x3$v_from_masters_1_bid, fabric_2x3$v_from_masters_1_rid, - fabric_2x3$v_from_masters_1_wid, fabric_2x3$v_to_slaves_0_arcache, fabric_2x3$v_to_slaves_0_arid, fabric_2x3$v_to_slaves_0_arqos, @@ -1072,7 +913,6 @@ module mkCoreW(CLK, fabric_2x3$v_to_slaves_0_awregion, fabric_2x3$v_to_slaves_0_bid, fabric_2x3$v_to_slaves_0_rid, - fabric_2x3$v_to_slaves_0_wid, fabric_2x3$v_to_slaves_1_arcache, fabric_2x3$v_to_slaves_1_arid, fabric_2x3$v_to_slaves_1_arqos, @@ -1083,7 +923,6 @@ module mkCoreW(CLK, fabric_2x3$v_to_slaves_1_awregion, fabric_2x3$v_to_slaves_1_bid, fabric_2x3$v_to_slaves_1_rid, - fabric_2x3$v_to_slaves_1_wid, fabric_2x3$v_to_slaves_2_arcache, fabric_2x3$v_to_slaves_2_arid, fabric_2x3$v_to_slaves_2_arqos, @@ -1093,8 +932,7 @@ module mkCoreW(CLK, fabric_2x3$v_to_slaves_2_awqos, fabric_2x3$v_to_slaves_2_awregion, fabric_2x3$v_to_slaves_2_bid, - fabric_2x3$v_to_slaves_2_rid, - fabric_2x3$v_to_slaves_2_wid; + fabric_2x3$v_to_slaves_2_rid; wire [2 : 0] fabric_2x3$v_from_masters_0_arprot, fabric_2x3$v_from_masters_0_arsize, fabric_2x3$v_from_masters_0_awprot, @@ -1137,7 +975,6 @@ module mkCoreW(CLK, fabric_2x3$v_to_slaves_2_rresp; wire fabric_2x3$EN_reset, fabric_2x3$EN_set_verbosity, - fabric_2x3$RDY_reset, fabric_2x3$v_from_masters_0_arlock, fabric_2x3$v_from_masters_0_arready, fabric_2x3$v_from_masters_0_arvalid, @@ -1209,6 +1046,9 @@ module mkCoreW(CLK, fabric_2x3$v_to_slaves_2_wready, fabric_2x3$v_to_slaves_2_wvalid; + // ports of submodule hart0_reset + wire hart0_reset$RST_OUT; + // ports of submodule plic wire [63 : 0] plic$axi4_slave_araddr, plic$axi4_slave_awaddr, @@ -1229,7 +1069,6 @@ module mkCoreW(CLK, plic$axi4_slave_awregion, plic$axi4_slave_bid, plic$axi4_slave_rid, - plic$axi4_slave_wid, plic$set_verbosity_verbosity; wire [2 : 0] plic$axi4_slave_arprot, plic$axi4_slave_arsize, @@ -1244,8 +1083,6 @@ module mkCoreW(CLK, plic$EN_set_addr_map, plic$EN_set_verbosity, plic$EN_show_PLIC_state, - plic$RDY_server_reset_request_put, - plic$RDY_server_reset_response_get, plic$axi4_slave_arlock, plic$axi4_slave_arready, plic$axi4_slave_arvalid, @@ -1280,7 +1117,6 @@ module mkCoreW(CLK, plic$v_targets_1_m_eip; // ports of submodule proc - wire [319 : 0] proc$v_to_TV_0_get, proc$v_to_TV_1_get; wire [76 : 0] proc$hart0_csr_mem_server_request_put; wire [69 : 0] proc$hart0_fpr_mem_server_request_put, proc$hart0_gpr_mem_server_request_put; @@ -1320,7 +1156,6 @@ module mkCoreW(CLK, proc$debug_module_mem_server_awregion, proc$debug_module_mem_server_bid, proc$debug_module_mem_server_rid, - proc$debug_module_mem_server_wid, proc$hart0_put_other_req_put, proc$master0_arcache, proc$master0_arid, @@ -1332,7 +1167,6 @@ module mkCoreW(CLK, proc$master0_awregion, proc$master0_bid, proc$master0_rid, - proc$master0_wid, proc$master1_arcache, proc$master1_arid, proc$master1_arqos, @@ -1343,7 +1177,6 @@ module mkCoreW(CLK, proc$master1_awregion, proc$master1_bid, proc$master1_rid, - proc$master1_wid, proc$set_verbosity_verbosity; wire [2 : 0] proc$debug_module_mem_server_arprot, proc$debug_module_mem_server_arsize, @@ -1378,24 +1211,15 @@ module mkCoreW(CLK, proc$EN_hart0_put_other_req_put, proc$EN_hart0_run_halt_server_request_put, proc$EN_hart0_run_halt_server_response_get, - proc$EN_hart0_server_reset_request_put, - proc$EN_hart0_server_reset_response_get, proc$EN_set_verbosity, proc$EN_start, - proc$EN_v_to_TV_0_get, - proc$EN_v_to_TV_1_get, proc$RDY_hart0_csr_mem_server_request_put, proc$RDY_hart0_csr_mem_server_response_get, proc$RDY_hart0_gpr_mem_server_request_put, proc$RDY_hart0_gpr_mem_server_response_get, proc$RDY_hart0_run_halt_server_request_put, proc$RDY_hart0_run_halt_server_response_get, - proc$RDY_hart0_server_reset_request_put, - proc$RDY_hart0_server_reset_response_get, proc$RDY_start, - proc$RDY_v_to_TV_0_get, - proc$RDY_v_to_TV_1_get, - proc$debug_external_interrupt_req_set_not_clear, proc$debug_module_mem_server_arlock, proc$debug_module_mem_server_arready, proc$debug_module_mem_server_arvalid, @@ -1451,104 +1275,37 @@ module mkCoreW(CLK, soc_map$m_plic_addr_base, soc_map$m_plic_addr_lim; - // ports of submodule tv_encode - reg [426 : 0] tv_encode$dm_in_put; - wire [607 : 0] tv_encode$out_get; - wire [490 : 0] tv_encode$v_cpu_in_0_put, tv_encode$v_cpu_in_1_put; - wire tv_encode$EN_dm_in_put, - tv_encode$EN_out_get, - tv_encode$EN_reset, - tv_encode$EN_v_cpu_in_0_put, - tv_encode$EN_v_cpu_in_1_put, - tv_encode$RDY_dm_in_put, - tv_encode$RDY_out_get, - tv_encode$RDY_reset, - tv_encode$RDY_v_cpu_in_0_put, - tv_encode$RDY_v_cpu_in_1_put; - - // ports of submodule v_td2_to_td_0_f_in - wire [319 : 0] v_td2_to_td_0_f_in$D_IN, v_td2_to_td_0_f_in$D_OUT; - wire v_td2_to_td_0_f_in$CLR, - v_td2_to_td_0_f_in$DEQ, - v_td2_to_td_0_f_in$EMPTY_N, - v_td2_to_td_0_f_in$ENQ, - v_td2_to_td_0_f_in$FULL_N; - - // ports of submodule v_td2_to_td_0_f_out - wire [490 : 0] v_td2_to_td_0_f_out$D_IN, v_td2_to_td_0_f_out$D_OUT; - wire v_td2_to_td_0_f_out$CLR, - v_td2_to_td_0_f_out$DEQ, - v_td2_to_td_0_f_out$EMPTY_N, - v_td2_to_td_0_f_out$ENQ, - v_td2_to_td_0_f_out$FULL_N; - - // ports of submodule v_td2_to_td_1_f_in - wire [319 : 0] v_td2_to_td_1_f_in$D_IN, v_td2_to_td_1_f_in$D_OUT; - wire v_td2_to_td_1_f_in$CLR, - v_td2_to_td_1_f_in$DEQ, - v_td2_to_td_1_f_in$EMPTY_N, - v_td2_to_td_1_f_in$ENQ, - v_td2_to_td_1_f_in$FULL_N; - - // ports of submodule v_td2_to_td_1_f_out - wire [490 : 0] v_td2_to_td_1_f_out$D_IN, v_td2_to_td_1_f_out$D_OUT; - wire v_td2_to_td_1_f_out$CLR, - v_td2_to_td_1_f_out$DEQ, - v_td2_to_td_1_f_out$EMPTY_N, - v_td2_to_td_1_f_out$ENQ, - v_td2_to_td_1_f_out$FULL_N; - // rule scheduling signals wire CAN_FIRE_RL_ClientServerRequest, CAN_FIRE_RL_ClientServerRequest_1, CAN_FIRE_RL_ClientServerRequest_2, - CAN_FIRE_RL_ClientServerRequest_3, - CAN_FIRE_RL_ClientServerRequest_4, CAN_FIRE_RL_ClientServerResponse, CAN_FIRE_RL_ClientServerResponse_1, CAN_FIRE_RL_ClientServerResponse_2, - CAN_FIRE_RL_ClientServerResponse_3, - CAN_FIRE_RL_ClientServerResponse_4, CAN_FIRE_RL_mkConnectionGetPut, - CAN_FIRE_RL_mkConnectionGetPut_1, - CAN_FIRE_RL_mkConnectionGetPut_2, - CAN_FIRE_RL_mkConnectionGetPut_3, - CAN_FIRE_RL_mkConnectionGetPut_4, - CAN_FIRE_RL_rl_cpu_hart0_reset_complete, - CAN_FIRE_RL_rl_cpu_hart0_reset_from_dm_start, - CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start, - CAN_FIRE_RL_rl_merge_dm_csr_trace_data, - CAN_FIRE_RL_rl_merge_dm_gpr_trace_data, - CAN_FIRE_RL_rl_merge_dm_mem_trace_data, + CAN_FIRE_RL_rl_dm_hart0_reset, + CAN_FIRE_RL_rl_dm_hart0_reset_wait, CAN_FIRE_RL_rl_rd_addr_channel, CAN_FIRE_RL_rl_rd_addr_channel_1, CAN_FIRE_RL_rl_rd_addr_channel_2, CAN_FIRE_RL_rl_rd_addr_channel_3, - CAN_FIRE_RL_rl_rd_addr_channel_4, CAN_FIRE_RL_rl_rd_data_channel, CAN_FIRE_RL_rl_rd_data_channel_1, CAN_FIRE_RL_rl_rd_data_channel_2, CAN_FIRE_RL_rl_rd_data_channel_3, - CAN_FIRE_RL_rl_rd_data_channel_4, CAN_FIRE_RL_rl_relay_external_interrupts, - CAN_FIRE_RL_rl_relay_non_maskable_interrupt, CAN_FIRE_RL_rl_wr_addr_channel, CAN_FIRE_RL_rl_wr_addr_channel_1, CAN_FIRE_RL_rl_wr_addr_channel_2, CAN_FIRE_RL_rl_wr_addr_channel_3, - CAN_FIRE_RL_rl_wr_addr_channel_4, CAN_FIRE_RL_rl_wr_data_channel, CAN_FIRE_RL_rl_wr_data_channel_1, CAN_FIRE_RL_rl_wr_data_channel_2, CAN_FIRE_RL_rl_wr_data_channel_3, - CAN_FIRE_RL_rl_wr_data_channel_4, CAN_FIRE_RL_rl_wr_response_channel, CAN_FIRE_RL_rl_wr_response_channel_1, CAN_FIRE_RL_rl_wr_response_channel_2, CAN_FIRE_RL_rl_wr_response_channel_3, - CAN_FIRE_RL_rl_wr_response_channel_4, - CAN_FIRE_RL_v_td2_to_td_0_rl_xform, - CAN_FIRE_RL_v_td2_to_td_1_rl_xform, CAN_FIRE_core_external_interrupt_sources_0_m_interrupt_req, CAN_FIRE_core_external_interrupt_sources_10_m_interrupt_req, CAN_FIRE_core_external_interrupt_sources_11_m_interrupt_req, @@ -1575,66 +1332,44 @@ module mkCoreW(CLK, CAN_FIRE_cpu_imem_master_m_bvalid, CAN_FIRE_cpu_imem_master_m_rvalid, CAN_FIRE_cpu_imem_master_m_wready, - CAN_FIRE_cpu_reset_server_request_put, - CAN_FIRE_cpu_reset_server_response_get, - CAN_FIRE_debug_external_interrupt_req, - CAN_FIRE_dm_dmi_read_addr, - CAN_FIRE_dm_dmi_read_data, - CAN_FIRE_dm_dmi_write, - CAN_FIRE_dm_ndm_reset_req_get_get, - CAN_FIRE_set_htif_addrs, + CAN_FIRE_dmi_read_addr, + CAN_FIRE_dmi_read_data, + CAN_FIRE_dmi_write, + CAN_FIRE_ndm_reset_client_request_get, + CAN_FIRE_ndm_reset_client_response_put, + CAN_FIRE_nmi_req, CAN_FIRE_set_verbosity, - CAN_FIRE_tv_verifier_info_get_get, + CAN_FIRE_start, WILL_FIRE_RL_ClientServerRequest, WILL_FIRE_RL_ClientServerRequest_1, WILL_FIRE_RL_ClientServerRequest_2, - WILL_FIRE_RL_ClientServerRequest_3, - WILL_FIRE_RL_ClientServerRequest_4, WILL_FIRE_RL_ClientServerResponse, WILL_FIRE_RL_ClientServerResponse_1, WILL_FIRE_RL_ClientServerResponse_2, - WILL_FIRE_RL_ClientServerResponse_3, - WILL_FIRE_RL_ClientServerResponse_4, WILL_FIRE_RL_mkConnectionGetPut, - WILL_FIRE_RL_mkConnectionGetPut_1, - WILL_FIRE_RL_mkConnectionGetPut_2, - WILL_FIRE_RL_mkConnectionGetPut_3, - WILL_FIRE_RL_mkConnectionGetPut_4, - WILL_FIRE_RL_rl_cpu_hart0_reset_complete, - WILL_FIRE_RL_rl_cpu_hart0_reset_from_dm_start, - WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start, - WILL_FIRE_RL_rl_merge_dm_csr_trace_data, - WILL_FIRE_RL_rl_merge_dm_gpr_trace_data, - WILL_FIRE_RL_rl_merge_dm_mem_trace_data, + WILL_FIRE_RL_rl_dm_hart0_reset, + WILL_FIRE_RL_rl_dm_hart0_reset_wait, WILL_FIRE_RL_rl_rd_addr_channel, WILL_FIRE_RL_rl_rd_addr_channel_1, WILL_FIRE_RL_rl_rd_addr_channel_2, WILL_FIRE_RL_rl_rd_addr_channel_3, - WILL_FIRE_RL_rl_rd_addr_channel_4, WILL_FIRE_RL_rl_rd_data_channel, WILL_FIRE_RL_rl_rd_data_channel_1, WILL_FIRE_RL_rl_rd_data_channel_2, WILL_FIRE_RL_rl_rd_data_channel_3, - WILL_FIRE_RL_rl_rd_data_channel_4, WILL_FIRE_RL_rl_relay_external_interrupts, - WILL_FIRE_RL_rl_relay_non_maskable_interrupt, WILL_FIRE_RL_rl_wr_addr_channel, WILL_FIRE_RL_rl_wr_addr_channel_1, WILL_FIRE_RL_rl_wr_addr_channel_2, WILL_FIRE_RL_rl_wr_addr_channel_3, - WILL_FIRE_RL_rl_wr_addr_channel_4, WILL_FIRE_RL_rl_wr_data_channel, WILL_FIRE_RL_rl_wr_data_channel_1, WILL_FIRE_RL_rl_wr_data_channel_2, WILL_FIRE_RL_rl_wr_data_channel_3, - WILL_FIRE_RL_rl_wr_data_channel_4, WILL_FIRE_RL_rl_wr_response_channel, WILL_FIRE_RL_rl_wr_response_channel_1, WILL_FIRE_RL_rl_wr_response_channel_2, WILL_FIRE_RL_rl_wr_response_channel_3, - WILL_FIRE_RL_rl_wr_response_channel_4, - WILL_FIRE_RL_v_td2_to_td_0_rl_xform, - WILL_FIRE_RL_v_td2_to_td_1_rl_xform, WILL_FIRE_core_external_interrupt_sources_0_m_interrupt_req, WILL_FIRE_core_external_interrupt_sources_10_m_interrupt_req, WILL_FIRE_core_external_interrupt_sources_11_m_interrupt_req, @@ -1661,63 +1396,38 @@ module mkCoreW(CLK, WILL_FIRE_cpu_imem_master_m_bvalid, WILL_FIRE_cpu_imem_master_m_rvalid, WILL_FIRE_cpu_imem_master_m_wready, - WILL_FIRE_cpu_reset_server_request_put, - WILL_FIRE_cpu_reset_server_response_get, - WILL_FIRE_debug_external_interrupt_req, - WILL_FIRE_dm_dmi_read_addr, - WILL_FIRE_dm_dmi_read_data, - WILL_FIRE_dm_dmi_write, - WILL_FIRE_dm_ndm_reset_req_get_get, - WILL_FIRE_set_htif_addrs, + WILL_FIRE_dmi_read_addr, + WILL_FIRE_dmi_read_data, + WILL_FIRE_dmi_write, + WILL_FIRE_ndm_reset_client_request_get, + WILL_FIRE_ndm_reset_client_response_put, + WILL_FIRE_nmi_req, WILL_FIRE_set_verbosity, - WILL_FIRE_tv_verifier_info_get_get; + WILL_FIRE_start; + + // inputs to muxes for submodule ports + wire [7 : 0] MUX_rg_hart0_reset_delay$write_1__VAL_1; + wire MUX_proc$start_1__SEL_1; // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h7205; - reg [31 : 0] v__h7403; - reg [31 : 0] v__h7674; - reg [31 : 0] v__h7199; - reg [31 : 0] v__h7397; - reg [31 : 0] v__h7668; + reg [31 : 0] v__h4797; + reg [31 : 0] v__h4940; + reg [31 : 0] v__h8302; + reg [31 : 0] v__h4791; + reg [31 : 0] v__h4934; + reg [31 : 0] v__h8296; // synopsys translate_on - // remaining internal signals - reg [63 : 0] x__h5725, x__h6650; - reg [11 : 0] CASE_procv_to_TV_0_get_BITS_153_TO_142_1_proc_ETC__q1, - CASE_procv_to_TV_1_get_BITS_153_TO_142_1_proc_ETC__q5; - reg [4 : 0] CASE_v_td2_to_td_0_f_inD_OUT_BITS_159_TO_155__ETC__q9, - CASE_v_td2_to_td_1_f_inD_OUT_BITS_159_TO_155__ETC__q10, - x1_avValue_rd__h5432, - x1_avValue_rd__h6363; - reg [3 : 0] CASE_procv_to_TV_0_get_BITS_139_TO_136_0_proc_ETC__q2, - CASE_procv_to_TV_0_get_BITS_139_TO_136_0_proc_ETC__q3, - CASE_procv_to_TV_1_get_BITS_139_TO_136_0_proc_ETC__q6, - CASE_procv_to_TV_1_get_BITS_139_TO_136_0_proc_ETC__q7; - reg [1 : 0] CASE_procv_to_TV_0_get_BITS_71_TO_70_0_procv_ETC__q4, - CASE_procv_to_TV_1_get_BITS_71_TO_70_0_procv_ETC__q8; - // action method set_verbosity assign RDY_set_verbosity = 1'd1 ; assign CAN_FIRE_set_verbosity = 1'd1 ; assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - // action method set_htif_addrs - assign RDY_set_htif_addrs = 1'd1 ; - assign CAN_FIRE_set_htif_addrs = 1'd1 ; - assign WILL_FIRE_set_htif_addrs = EN_set_htif_addrs ; - - // action method cpu_reset_server_request_put - assign RDY_cpu_reset_server_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_cpu_reset_server_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_cpu_reset_server_request_put = - EN_cpu_reset_server_request_put ; - - // action method cpu_reset_server_response_get - assign RDY_cpu_reset_server_response_get = f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_cpu_reset_server_response_get = f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_cpu_reset_server_response_get = - EN_cpu_reset_server_response_get ; + // action method start + assign RDY_start = proc$RDY_start ; + assign CAN_FIRE_start = proc$RDY_start ; + assign WILL_FIRE_start = EN_start ; // value method cpu_imem_master_m_awvalid assign cpu_imem_master_awvalid = proc$master0_awvalid ; @@ -1759,9 +1469,6 @@ module mkCoreW(CLK, // value method cpu_imem_master_m_wvalid assign cpu_imem_master_wvalid = proc$master0_wvalid ; - // value method cpu_imem_master_m_wid - assign cpu_imem_master_wid = proc$master0_wid ; - // value method cpu_imem_master_m_wdata assign cpu_imem_master_wdata = proc$master0_wdata ; @@ -1866,9 +1573,6 @@ module mkCoreW(CLK, // value method cpu_dmem_master_m_wvalid assign cpu_dmem_master_wvalid = fabric_2x3$v_to_slaves_0_wvalid ; - // value method cpu_dmem_master_m_wid - assign cpu_dmem_master_wid = fabric_2x3$v_to_slaves_0_wid ; - // value method cpu_dmem_master_m_wdata assign cpu_dmem_master_wdata = fabric_2x3$v_to_slaves_0_wdata ; @@ -1997,42 +1701,47 @@ module mkCoreW(CLK, assign CAN_FIRE_core_external_interrupt_sources_15_m_interrupt_req = 1'd1 ; assign WILL_FIRE_core_external_interrupt_sources_15_m_interrupt_req = 1'd1 ; - // action method debug_external_interrupt_req - assign CAN_FIRE_debug_external_interrupt_req = 1'd1 ; - assign WILL_FIRE_debug_external_interrupt_req = 1'd1 ; + // action method nmi_req + assign CAN_FIRE_nmi_req = 1'd1 ; + assign WILL_FIRE_nmi_req = 1'd1 ; - // action method dm_dmi_read_addr - assign RDY_dm_dmi_read_addr = debug_module$RDY_dmi_read_addr ; - assign CAN_FIRE_dm_dmi_read_addr = debug_module$RDY_dmi_read_addr ; - assign WILL_FIRE_dm_dmi_read_addr = EN_dm_dmi_read_addr ; + // action method dmi_read_addr + assign RDY_dmi_read_addr = debug_module$RDY_dmi_read_addr ; + assign CAN_FIRE_dmi_read_addr = debug_module$RDY_dmi_read_addr ; + assign WILL_FIRE_dmi_read_addr = EN_dmi_read_addr ; - // actionvalue method dm_dmi_read_data - assign dm_dmi_read_data = debug_module$dmi_read_data ; - assign RDY_dm_dmi_read_data = debug_module$RDY_dmi_read_data ; - assign CAN_FIRE_dm_dmi_read_data = debug_module$RDY_dmi_read_data ; - assign WILL_FIRE_dm_dmi_read_data = EN_dm_dmi_read_data ; + // actionvalue method dmi_read_data + assign dmi_read_data = debug_module$dmi_read_data ; + assign RDY_dmi_read_data = debug_module$RDY_dmi_read_data ; + assign CAN_FIRE_dmi_read_data = debug_module$RDY_dmi_read_data ; + assign WILL_FIRE_dmi_read_data = EN_dmi_read_data ; - // action method dm_dmi_write - assign RDY_dm_dmi_write = debug_module$RDY_dmi_write ; - assign CAN_FIRE_dm_dmi_write = debug_module$RDY_dmi_write ; - assign WILL_FIRE_dm_dmi_write = EN_dm_dmi_write ; + // action method dmi_write + assign RDY_dmi_write = debug_module$RDY_dmi_write ; + assign CAN_FIRE_dmi_write = debug_module$RDY_dmi_write ; + assign WILL_FIRE_dmi_write = EN_dmi_write ; - // action method dm_ndm_reset_req_get_get - assign RDY_dm_ndm_reset_req_get_get = - debug_module$RDY_get_ndm_reset_req_get ; - assign CAN_FIRE_dm_ndm_reset_req_get_get = - debug_module$RDY_get_ndm_reset_req_get ; - assign WILL_FIRE_dm_ndm_reset_req_get_get = EN_dm_ndm_reset_req_get_get ; + // actionvalue method ndm_reset_client_request_get + assign ndm_reset_client_request_get = + debug_module$ndm_reset_client_request_get ; + assign RDY_ndm_reset_client_request_get = + debug_module$RDY_ndm_reset_client_request_get ; + assign CAN_FIRE_ndm_reset_client_request_get = + debug_module$RDY_ndm_reset_client_request_get ; + assign WILL_FIRE_ndm_reset_client_request_get = + EN_ndm_reset_client_request_get ; - // actionvalue method tv_verifier_info_get_get - assign tv_verifier_info_get_get = tv_encode$out_get ; - assign RDY_tv_verifier_info_get_get = tv_encode$RDY_out_get ; - assign CAN_FIRE_tv_verifier_info_get_get = tv_encode$RDY_out_get ; - assign WILL_FIRE_tv_verifier_info_get_get = EN_tv_verifier_info_get_get ; + // action method ndm_reset_client_response_put + assign RDY_ndm_reset_client_response_put = + debug_module$RDY_ndm_reset_client_response_put ; + assign CAN_FIRE_ndm_reset_client_response_put = + debug_module$RDY_ndm_reset_client_response_put ; + assign WILL_FIRE_ndm_reset_client_response_put = + EN_ndm_reset_client_response_put ; // submodule debug_module mkDebug_Module debug_module(.CLK(CLK), - .RST_N(RST_N), + .RST_N(RST_N_dm_power_on_reset), .dmi_read_addr_dm_addr(debug_module$dmi_read_addr_dm_addr), .dmi_write_dm_addr(debug_module$dmi_write_dm_addr), .dmi_write_dm_word(debug_module$dmi_write_dm_word), @@ -2040,6 +1749,7 @@ module mkCoreW(CLK, .hart0_csr_mem_client_response_put(debug_module$hart0_csr_mem_client_response_put), .hart0_fpr_mem_client_response_put(debug_module$hart0_fpr_mem_client_response_put), .hart0_gpr_mem_client_response_put(debug_module$hart0_gpr_mem_client_response_put), + .hart0_reset_client_response_put(debug_module$hart0_reset_client_response_put), .master_arready(debug_module$master_arready), .master_awready(debug_module$master_awready), .master_bid(debug_module$master_bid), @@ -2051,10 +1761,12 @@ module mkCoreW(CLK, .master_rresp(debug_module$master_rresp), .master_rvalid(debug_module$master_rvalid), .master_wready(debug_module$master_wready), + .ndm_reset_client_response_put(debug_module$ndm_reset_client_response_put), .EN_dmi_read_addr(debug_module$EN_dmi_read_addr), .EN_dmi_read_data(debug_module$EN_dmi_read_data), .EN_dmi_write(debug_module$EN_dmi_write), - .EN_hart0_get_reset_req_get(debug_module$EN_hart0_get_reset_req_get), + .EN_hart0_reset_client_request_get(debug_module$EN_hart0_reset_client_request_get), + .EN_hart0_reset_client_response_put(debug_module$EN_hart0_reset_client_response_put), .EN_hart0_client_run_halt_request_get(debug_module$EN_hart0_client_run_halt_request_get), .EN_hart0_client_run_halt_response_put(debug_module$EN_hart0_client_run_halt_response_put), .EN_hart0_get_other_req_get(debug_module$EN_hart0_get_other_req_get), @@ -2064,12 +1776,15 @@ module mkCoreW(CLK, .EN_hart0_fpr_mem_client_response_put(debug_module$EN_hart0_fpr_mem_client_response_put), .EN_hart0_csr_mem_client_request_get(debug_module$EN_hart0_csr_mem_client_request_get), .EN_hart0_csr_mem_client_response_put(debug_module$EN_hart0_csr_mem_client_response_put), - .EN_get_ndm_reset_req_get(debug_module$EN_get_ndm_reset_req_get), + .EN_ndm_reset_client_request_get(debug_module$EN_ndm_reset_client_request_get), + .EN_ndm_reset_client_response_put(debug_module$EN_ndm_reset_client_response_put), .RDY_dmi_read_addr(debug_module$RDY_dmi_read_addr), .dmi_read_data(debug_module$dmi_read_data), .RDY_dmi_read_data(debug_module$RDY_dmi_read_data), .RDY_dmi_write(debug_module$RDY_dmi_write), - .RDY_hart0_get_reset_req_get(debug_module$RDY_hart0_get_reset_req_get), + .hart0_reset_client_request_get(), + .RDY_hart0_reset_client_request_get(debug_module$RDY_hart0_reset_client_request_get), + .RDY_hart0_reset_client_response_put(debug_module$RDY_hart0_reset_client_response_put), .hart0_client_run_halt_request_get(debug_module$hart0_client_run_halt_request_get), .RDY_hart0_client_run_halt_request_get(debug_module$RDY_hart0_client_run_halt_request_get), .RDY_hart0_client_run_halt_response_put(debug_module$RDY_hart0_client_run_halt_response_put), @@ -2084,7 +1799,9 @@ module mkCoreW(CLK, .hart0_csr_mem_client_request_get(debug_module$hart0_csr_mem_client_request_get), .RDY_hart0_csr_mem_client_request_get(debug_module$RDY_hart0_csr_mem_client_request_get), .RDY_hart0_csr_mem_client_response_put(debug_module$RDY_hart0_csr_mem_client_response_put), - .RDY_get_ndm_reset_req_get(debug_module$RDY_get_ndm_reset_req_get), + .ndm_reset_client_request_get(debug_module$ndm_reset_client_request_get), + .RDY_ndm_reset_client_request_get(debug_module$RDY_ndm_reset_client_request_get), + .RDY_ndm_reset_client_response_put(debug_module$RDY_ndm_reset_client_response_put), .master_awvalid(debug_module$master_awvalid), .master_awid(debug_module$master_awid), .master_awaddr(debug_module$master_awaddr), @@ -2097,7 +1814,6 @@ module mkCoreW(CLK, .master_awqos(debug_module$master_awqos), .master_awregion(debug_module$master_awregion), .master_wvalid(debug_module$master_wvalid), - .master_wid(debug_module$master_wid), .master_wdata(debug_module$master_wdata), .master_wstrb(debug_module$master_wstrb), .master_wlast(debug_module$master_wlast), @@ -2115,159 +1831,14 @@ module mkCoreW(CLK, .master_arregion(debug_module$master_arregion), .master_rready(debug_module$master_rready)); - // submodule dm_csr_tap - mkDM_CSR_Tap dm_csr_tap(.CLK(CLK), - .RST_N(RST_N), - .client_response_put(dm_csr_tap$client_response_put), - .server_request_put(dm_csr_tap$server_request_put), - .EN_client_request_get(dm_csr_tap$EN_client_request_get), - .EN_client_response_put(dm_csr_tap$EN_client_response_put), - .EN_server_request_put(dm_csr_tap$EN_server_request_put), - .EN_server_response_get(dm_csr_tap$EN_server_response_get), - .EN_trace_data_out_get(dm_csr_tap$EN_trace_data_out_get), - .client_request_get(dm_csr_tap$client_request_get), - .RDY_client_request_get(dm_csr_tap$RDY_client_request_get), - .RDY_client_response_put(dm_csr_tap$RDY_client_response_put), - .RDY_server_request_put(dm_csr_tap$RDY_server_request_put), - .server_response_get(dm_csr_tap$server_response_get), - .RDY_server_response_get(dm_csr_tap$RDY_server_response_get), - .trace_data_out_get(dm_csr_tap$trace_data_out_get), - .RDY_trace_data_out_get(dm_csr_tap$RDY_trace_data_out_get)); - - // submodule dm_gpr_tap_ifc - mkDM_GPR_Tap dm_gpr_tap_ifc(.CLK(CLK), - .RST_N(RST_N), - .client_response_put(dm_gpr_tap_ifc$client_response_put), - .server_request_put(dm_gpr_tap_ifc$server_request_put), - .EN_client_request_get(dm_gpr_tap_ifc$EN_client_request_get), - .EN_client_response_put(dm_gpr_tap_ifc$EN_client_response_put), - .EN_server_request_put(dm_gpr_tap_ifc$EN_server_request_put), - .EN_server_response_get(dm_gpr_tap_ifc$EN_server_response_get), - .EN_trace_data_out_get(dm_gpr_tap_ifc$EN_trace_data_out_get), - .client_request_get(dm_gpr_tap_ifc$client_request_get), - .RDY_client_request_get(dm_gpr_tap_ifc$RDY_client_request_get), - .RDY_client_response_put(dm_gpr_tap_ifc$RDY_client_response_put), - .RDY_server_request_put(dm_gpr_tap_ifc$RDY_server_request_put), - .server_response_get(dm_gpr_tap_ifc$server_response_get), - .RDY_server_response_get(dm_gpr_tap_ifc$RDY_server_response_get), - .trace_data_out_get(dm_gpr_tap_ifc$trace_data_out_get), - .RDY_trace_data_out_get(dm_gpr_tap_ifc$RDY_trace_data_out_get)); - - // submodule dm_mem_tap - mkDM_Mem_Tap dm_mem_tap(.CLK(CLK), - .RST_N(RST_N), - .master_arready(dm_mem_tap$master_arready), - .master_awready(dm_mem_tap$master_awready), - .master_bid(dm_mem_tap$master_bid), - .master_bresp(dm_mem_tap$master_bresp), - .master_bvalid(dm_mem_tap$master_bvalid), - .master_rdata(dm_mem_tap$master_rdata), - .master_rid(dm_mem_tap$master_rid), - .master_rlast(dm_mem_tap$master_rlast), - .master_rresp(dm_mem_tap$master_rresp), - .master_rvalid(dm_mem_tap$master_rvalid), - .master_wready(dm_mem_tap$master_wready), - .slave_araddr(dm_mem_tap$slave_araddr), - .slave_arburst(dm_mem_tap$slave_arburst), - .slave_arcache(dm_mem_tap$slave_arcache), - .slave_arid(dm_mem_tap$slave_arid), - .slave_arlen(dm_mem_tap$slave_arlen), - .slave_arlock(dm_mem_tap$slave_arlock), - .slave_arprot(dm_mem_tap$slave_arprot), - .slave_arqos(dm_mem_tap$slave_arqos), - .slave_arregion(dm_mem_tap$slave_arregion), - .slave_arsize(dm_mem_tap$slave_arsize), - .slave_arvalid(dm_mem_tap$slave_arvalid), - .slave_awaddr(dm_mem_tap$slave_awaddr), - .slave_awburst(dm_mem_tap$slave_awburst), - .slave_awcache(dm_mem_tap$slave_awcache), - .slave_awid(dm_mem_tap$slave_awid), - .slave_awlen(dm_mem_tap$slave_awlen), - .slave_awlock(dm_mem_tap$slave_awlock), - .slave_awprot(dm_mem_tap$slave_awprot), - .slave_awqos(dm_mem_tap$slave_awqos), - .slave_awregion(dm_mem_tap$slave_awregion), - .slave_awsize(dm_mem_tap$slave_awsize), - .slave_awvalid(dm_mem_tap$slave_awvalid), - .slave_bready(dm_mem_tap$slave_bready), - .slave_rready(dm_mem_tap$slave_rready), - .slave_wdata(dm_mem_tap$slave_wdata), - .slave_wid(dm_mem_tap$slave_wid), - .slave_wlast(dm_mem_tap$slave_wlast), - .slave_wstrb(dm_mem_tap$slave_wstrb), - .slave_wvalid(dm_mem_tap$slave_wvalid), - .EN_trace_data_out_get(dm_mem_tap$EN_trace_data_out_get), - .slave_awready(dm_mem_tap$slave_awready), - .slave_wready(dm_mem_tap$slave_wready), - .slave_bvalid(dm_mem_tap$slave_bvalid), - .slave_bid(dm_mem_tap$slave_bid), - .slave_bresp(dm_mem_tap$slave_bresp), - .slave_arready(dm_mem_tap$slave_arready), - .slave_rvalid(dm_mem_tap$slave_rvalid), - .slave_rid(dm_mem_tap$slave_rid), - .slave_rdata(dm_mem_tap$slave_rdata), - .slave_rresp(dm_mem_tap$slave_rresp), - .slave_rlast(dm_mem_tap$slave_rlast), - .master_awvalid(dm_mem_tap$master_awvalid), - .master_awid(dm_mem_tap$master_awid), - .master_awaddr(dm_mem_tap$master_awaddr), - .master_awlen(dm_mem_tap$master_awlen), - .master_awsize(dm_mem_tap$master_awsize), - .master_awburst(dm_mem_tap$master_awburst), - .master_awlock(dm_mem_tap$master_awlock), - .master_awcache(dm_mem_tap$master_awcache), - .master_awprot(dm_mem_tap$master_awprot), - .master_awqos(dm_mem_tap$master_awqos), - .master_awregion(dm_mem_tap$master_awregion), - .master_wvalid(dm_mem_tap$master_wvalid), - .master_wid(dm_mem_tap$master_wid), - .master_wdata(dm_mem_tap$master_wdata), - .master_wstrb(dm_mem_tap$master_wstrb), - .master_wlast(dm_mem_tap$master_wlast), - .master_bready(dm_mem_tap$master_bready), - .master_arvalid(dm_mem_tap$master_arvalid), - .master_arid(dm_mem_tap$master_arid), - .master_araddr(dm_mem_tap$master_araddr), - .master_arlen(dm_mem_tap$master_arlen), - .master_arsize(dm_mem_tap$master_arsize), - .master_arburst(dm_mem_tap$master_arburst), - .master_arlock(dm_mem_tap$master_arlock), - .master_arcache(dm_mem_tap$master_arcache), - .master_arprot(dm_mem_tap$master_arprot), - .master_arqos(dm_mem_tap$master_arqos), - .master_arregion(dm_mem_tap$master_arregion), - .master_rready(dm_mem_tap$master_rready), - .trace_data_out_get(dm_mem_tap$trace_data_out_get), - .RDY_trace_data_out_get(dm_mem_tap$RDY_trace_data_out_get)); - - // submodule f_reset_reqs - FIFO20 #(.guarded(32'd1)) f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_reqs$ENQ), - .DEQ(f_reset_reqs$DEQ), - .CLR(f_reset_reqs$CLR), - .FULL_N(f_reset_reqs$FULL_N), - .EMPTY_N(f_reset_reqs$EMPTY_N)); - - // submodule f_reset_requestor - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_requestor(.RST(RST_N), - .CLK(CLK), - .D_IN(f_reset_requestor$D_IN), - .ENQ(f_reset_requestor$ENQ), - .DEQ(f_reset_requestor$DEQ), - .CLR(f_reset_requestor$CLR), - .D_OUT(f_reset_requestor$D_OUT), - .FULL_N(f_reset_requestor$FULL_N), - .EMPTY_N(f_reset_requestor$EMPTY_N)); - - // submodule f_reset_rsps - FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); + // submodule dm_hart0_reset_controller + MakeResetA #(.RSTDELAY(32'd10), + .init(1'd1)) dm_hart0_reset_controller(.CLK(CLK), + .RST(RST_N), + .DST_CLK(CLK), + .ASSERT_IN(dm_hart0_reset_controller$ASSERT_IN), + .ASSERT_OUT(), + .OUT_RST(dm_hart0_reset_controller$OUT_RST)); // submodule fabric_2x3 mkFabric_2x3 fabric_2x3(.CLK(CLK), @@ -2298,7 +1869,6 @@ module mkCoreW(CLK, .v_from_masters_0_bready(fabric_2x3$v_from_masters_0_bready), .v_from_masters_0_rready(fabric_2x3$v_from_masters_0_rready), .v_from_masters_0_wdata(fabric_2x3$v_from_masters_0_wdata), - .v_from_masters_0_wid(fabric_2x3$v_from_masters_0_wid), .v_from_masters_0_wlast(fabric_2x3$v_from_masters_0_wlast), .v_from_masters_0_wstrb(fabric_2x3$v_from_masters_0_wstrb), .v_from_masters_0_wvalid(fabric_2x3$v_from_masters_0_wvalid), @@ -2327,7 +1897,6 @@ module mkCoreW(CLK, .v_from_masters_1_bready(fabric_2x3$v_from_masters_1_bready), .v_from_masters_1_rready(fabric_2x3$v_from_masters_1_rready), .v_from_masters_1_wdata(fabric_2x3$v_from_masters_1_wdata), - .v_from_masters_1_wid(fabric_2x3$v_from_masters_1_wid), .v_from_masters_1_wlast(fabric_2x3$v_from_masters_1_wlast), .v_from_masters_1_wstrb(fabric_2x3$v_from_masters_1_wstrb), .v_from_masters_1_wvalid(fabric_2x3$v_from_masters_1_wvalid), @@ -2366,7 +1935,7 @@ module mkCoreW(CLK, .v_to_slaves_2_wready(fabric_2x3$v_to_slaves_2_wready), .EN_reset(fabric_2x3$EN_reset), .EN_set_verbosity(fabric_2x3$EN_set_verbosity), - .RDY_reset(fabric_2x3$RDY_reset), + .RDY_reset(), .RDY_set_verbosity(), .v_from_masters_0_awready(fabric_2x3$v_from_masters_0_awready), .v_from_masters_0_wready(fabric_2x3$v_from_masters_0_wready), @@ -2402,7 +1971,6 @@ module mkCoreW(CLK, .v_to_slaves_0_awqos(fabric_2x3$v_to_slaves_0_awqos), .v_to_slaves_0_awregion(fabric_2x3$v_to_slaves_0_awregion), .v_to_slaves_0_wvalid(fabric_2x3$v_to_slaves_0_wvalid), - .v_to_slaves_0_wid(fabric_2x3$v_to_slaves_0_wid), .v_to_slaves_0_wdata(fabric_2x3$v_to_slaves_0_wdata), .v_to_slaves_0_wstrb(fabric_2x3$v_to_slaves_0_wstrb), .v_to_slaves_0_wlast(fabric_2x3$v_to_slaves_0_wlast), @@ -2431,7 +1999,6 @@ module mkCoreW(CLK, .v_to_slaves_1_awqos(fabric_2x3$v_to_slaves_1_awqos), .v_to_slaves_1_awregion(fabric_2x3$v_to_slaves_1_awregion), .v_to_slaves_1_wvalid(fabric_2x3$v_to_slaves_1_wvalid), - .v_to_slaves_1_wid(fabric_2x3$v_to_slaves_1_wid), .v_to_slaves_1_wdata(fabric_2x3$v_to_slaves_1_wdata), .v_to_slaves_1_wstrb(fabric_2x3$v_to_slaves_1_wstrb), .v_to_slaves_1_wlast(fabric_2x3$v_to_slaves_1_wlast), @@ -2460,7 +2027,6 @@ module mkCoreW(CLK, .v_to_slaves_2_awqos(fabric_2x3$v_to_slaves_2_awqos), .v_to_slaves_2_awregion(fabric_2x3$v_to_slaves_2_awregion), .v_to_slaves_2_wvalid(fabric_2x3$v_to_slaves_2_wvalid), - .v_to_slaves_2_wid(fabric_2x3$v_to_slaves_2_wid), .v_to_slaves_2_wdata(fabric_2x3$v_to_slaves_2_wdata), .v_to_slaves_2_wstrb(fabric_2x3$v_to_slaves_2_wstrb), .v_to_slaves_2_wlast(fabric_2x3$v_to_slaves_2_wlast), @@ -2478,6 +2044,11 @@ module mkCoreW(CLK, .v_to_slaves_2_arregion(fabric_2x3$v_to_slaves_2_arregion), .v_to_slaves_2_rready(fabric_2x3$v_to_slaves_2_rready)); + // submodule hart0_reset + ResetEither hart0_reset(.A_RST(RST_N), + .B_RST(dm_hart0_reset_controller$OUT_RST), + .RST_OUT(hart0_reset$RST_OUT)); + // submodule plic mkPLIC_16_2_7 plic(.CLK(CLK), .RST_N(RST_N), @@ -2506,7 +2077,6 @@ module mkCoreW(CLK, .axi4_slave_bready(plic$axi4_slave_bready), .axi4_slave_rready(plic$axi4_slave_rready), .axi4_slave_wdata(plic$axi4_slave_wdata), - .axi4_slave_wid(plic$axi4_slave_wid), .axi4_slave_wlast(plic$axi4_slave_wlast), .axi4_slave_wstrb(plic$axi4_slave_wstrb), .axi4_slave_wvalid(plic$axi4_slave_wvalid), @@ -2536,8 +2106,8 @@ module mkCoreW(CLK, .EN_set_addr_map(plic$EN_set_addr_map), .RDY_set_verbosity(), .RDY_show_PLIC_state(), - .RDY_server_reset_request_put(plic$RDY_server_reset_request_put), - .RDY_server_reset_response_get(plic$RDY_server_reset_response_get), + .RDY_server_reset_request_put(), + .RDY_server_reset_response_get(), .RDY_set_addr_map(), .axi4_slave_awready(plic$axi4_slave_awready), .axi4_slave_wready(plic$axi4_slave_wready), @@ -2555,8 +2125,7 @@ module mkCoreW(CLK, // submodule proc mkProc proc(.CLK(CLK), - .RST_N(RST_N), - .debug_external_interrupt_req_set_not_clear(proc$debug_external_interrupt_req_set_not_clear), + .RST_N(hart0_reset$RST_OUT), .debug_module_mem_server_araddr(proc$debug_module_mem_server_araddr), .debug_module_mem_server_arburst(proc$debug_module_mem_server_arburst), .debug_module_mem_server_arcache(proc$debug_module_mem_server_arcache), @@ -2582,7 +2151,6 @@ module mkCoreW(CLK, .debug_module_mem_server_bready(proc$debug_module_mem_server_bready), .debug_module_mem_server_rready(proc$debug_module_mem_server_rready), .debug_module_mem_server_wdata(proc$debug_module_mem_server_wdata), - .debug_module_mem_server_wid(proc$debug_module_mem_server_wid), .debug_module_mem_server_wlast(proc$debug_module_mem_server_wlast), .debug_module_mem_server_wstrb(proc$debug_module_mem_server_wstrb), .debug_module_mem_server_wvalid(proc$debug_module_mem_server_wvalid), @@ -2620,8 +2188,6 @@ module mkCoreW(CLK, .start_fromhostAddr(proc$start_fromhostAddr), .start_startpc(proc$start_startpc), .start_tohostAddr(proc$start_tohostAddr), - .EN_hart0_server_reset_request_put(proc$EN_hart0_server_reset_request_put), - .EN_hart0_server_reset_response_get(proc$EN_hart0_server_reset_response_get), .EN_start(proc$EN_start), .EN_set_verbosity(proc$EN_set_verbosity), .EN_hart0_run_halt_server_request_put(proc$EN_hart0_run_halt_server_request_put), @@ -2633,10 +2199,6 @@ module mkCoreW(CLK, .EN_hart0_csr_mem_server_request_put(proc$EN_hart0_csr_mem_server_request_put), .EN_hart0_csr_mem_server_response_get(proc$EN_hart0_csr_mem_server_response_get), .EN_hart0_put_other_req_put(proc$EN_hart0_put_other_req_put), - .EN_v_to_TV_0_get(proc$EN_v_to_TV_0_get), - .EN_v_to_TV_1_get(proc$EN_v_to_TV_1_get), - .RDY_hart0_server_reset_request_put(proc$RDY_hart0_server_reset_request_put), - .RDY_hart0_server_reset_response_get(proc$RDY_hart0_server_reset_response_get), .RDY_start(proc$RDY_start), .master0_awvalid(proc$master0_awvalid), .master0_awid(proc$master0_awid), @@ -2650,7 +2212,6 @@ module mkCoreW(CLK, .master0_awqos(proc$master0_awqos), .master0_awregion(proc$master0_awregion), .master0_wvalid(proc$master0_wvalid), - .master0_wid(proc$master0_wid), .master0_wdata(proc$master0_wdata), .master0_wstrb(proc$master0_wstrb), .master0_wlast(proc$master0_wlast), @@ -2679,7 +2240,6 @@ module mkCoreW(CLK, .master1_awqos(proc$master1_awqos), .master1_awregion(proc$master1_awregion), .master1_wvalid(proc$master1_wvalid), - .master1_wid(proc$master1_wid), .master1_wdata(proc$master1_wdata), .master1_wstrb(proc$master1_wstrb), .master1_wlast(proc$master1_wlast), @@ -2720,11 +2280,7 @@ module mkCoreW(CLK, .RDY_hart0_csr_mem_server_request_put(proc$RDY_hart0_csr_mem_server_request_put), .hart0_csr_mem_server_response_get(proc$hart0_csr_mem_server_response_get), .RDY_hart0_csr_mem_server_response_get(proc$RDY_hart0_csr_mem_server_response_get), - .RDY_hart0_put_other_req_put(), - .v_to_TV_0_get(proc$v_to_TV_0_get), - .RDY_v_to_TV_0_get(proc$RDY_v_to_TV_0_get), - .v_to_TV_1_get(proc$v_to_TV_1_get), - .RDY_v_to_TV_1_get(proc$RDY_v_to_TV_1_get)); + .RDY_hart0_put_other_req_put()); // submodule soc_map mkSoC_Map soc_map(.CLK(CLK), @@ -2772,67 +2328,20 @@ module mkCoreW(CLK, .m_mtvec_reset_value(), .m_nmivec_reset_value()); - // submodule tv_encode - mkTV_Encode tv_encode(.CLK(CLK), - .RST_N(RST_N), - .dm_in_put(tv_encode$dm_in_put), - .v_cpu_in_0_put(tv_encode$v_cpu_in_0_put), - .v_cpu_in_1_put(tv_encode$v_cpu_in_1_put), - .EN_reset(tv_encode$EN_reset), - .EN_v_cpu_in_0_put(tv_encode$EN_v_cpu_in_0_put), - .EN_v_cpu_in_1_put(tv_encode$EN_v_cpu_in_1_put), - .EN_dm_in_put(tv_encode$EN_dm_in_put), - .EN_out_get(tv_encode$EN_out_get), - .RDY_reset(tv_encode$RDY_reset), - .RDY_v_cpu_in_0_put(tv_encode$RDY_v_cpu_in_0_put), - .RDY_v_cpu_in_1_put(tv_encode$RDY_v_cpu_in_1_put), - .RDY_dm_in_put(tv_encode$RDY_dm_in_put), - .out_get(tv_encode$out_get), - .RDY_out_get(tv_encode$RDY_out_get)); + // rule RL_rl_dm_hart0_reset + assign CAN_FIRE_RL_rl_dm_hart0_reset = + debug_module$RDY_hart0_reset_client_request_get && + rg_hart0_reset_delay == 8'd0 ; + assign WILL_FIRE_RL_rl_dm_hart0_reset = CAN_FIRE_RL_rl_dm_hart0_reset ; - // submodule v_td2_to_td_0_f_in - FIFO2 #(.width(32'd320), .guarded(32'd1)) v_td2_to_td_0_f_in(.RST(RST_N), - .CLK(CLK), - .D_IN(v_td2_to_td_0_f_in$D_IN), - .ENQ(v_td2_to_td_0_f_in$ENQ), - .DEQ(v_td2_to_td_0_f_in$DEQ), - .CLR(v_td2_to_td_0_f_in$CLR), - .D_OUT(v_td2_to_td_0_f_in$D_OUT), - .FULL_N(v_td2_to_td_0_f_in$FULL_N), - .EMPTY_N(v_td2_to_td_0_f_in$EMPTY_N)); - - // submodule v_td2_to_td_0_f_out - FIFO2 #(.width(32'd491), .guarded(32'd1)) v_td2_to_td_0_f_out(.RST(RST_N), - .CLK(CLK), - .D_IN(v_td2_to_td_0_f_out$D_IN), - .ENQ(v_td2_to_td_0_f_out$ENQ), - .DEQ(v_td2_to_td_0_f_out$DEQ), - .CLR(v_td2_to_td_0_f_out$CLR), - .D_OUT(v_td2_to_td_0_f_out$D_OUT), - .FULL_N(v_td2_to_td_0_f_out$FULL_N), - .EMPTY_N(v_td2_to_td_0_f_out$EMPTY_N)); - - // submodule v_td2_to_td_1_f_in - FIFO2 #(.width(32'd320), .guarded(32'd1)) v_td2_to_td_1_f_in(.RST(RST_N), - .CLK(CLK), - .D_IN(v_td2_to_td_1_f_in$D_IN), - .ENQ(v_td2_to_td_1_f_in$ENQ), - .DEQ(v_td2_to_td_1_f_in$DEQ), - .CLR(v_td2_to_td_1_f_in$CLR), - .D_OUT(v_td2_to_td_1_f_in$D_OUT), - .FULL_N(v_td2_to_td_1_f_in$FULL_N), - .EMPTY_N(v_td2_to_td_1_f_in$EMPTY_N)); - - // submodule v_td2_to_td_1_f_out - FIFO2 #(.width(32'd491), .guarded(32'd1)) v_td2_to_td_1_f_out(.RST(RST_N), - .CLK(CLK), - .D_IN(v_td2_to_td_1_f_out$D_IN), - .ENQ(v_td2_to_td_1_f_out$ENQ), - .DEQ(v_td2_to_td_1_f_out$DEQ), - .CLR(v_td2_to_td_1_f_out$CLR), - .D_OUT(v_td2_to_td_1_f_out$D_OUT), - .FULL_N(v_td2_to_td_1_f_out$FULL_N), - .EMPTY_N(v_td2_to_td_1_f_out$EMPTY_N)); + // rule RL_rl_dm_hart0_reset_wait + assign CAN_FIRE_RL_rl_dm_hart0_reset_wait = + (rg_hart0_reset_delay != 8'd1 || + debug_module$RDY_hart0_reset_client_response_put && + proc$RDY_start) && + rg_hart0_reset_delay != 8'd0 ; + assign WILL_FIRE_RL_rl_dm_hart0_reset_wait = + CAN_FIRE_RL_rl_dm_hart0_reset_wait && !EN_start ; // rule RL_ClientServerRequest assign CAN_FIRE_RL_ClientServerRequest = @@ -2853,29 +2362,19 @@ module mkCoreW(CLK, assign WILL_FIRE_RL_mkConnectionGetPut = debug_module$RDY_hart0_get_other_req_get ; - // rule RL_mkConnectionGetPut_1 - assign CAN_FIRE_RL_mkConnectionGetPut_1 = - proc$RDY_v_to_TV_0_get && v_td2_to_td_0_f_in$FULL_N ; - assign WILL_FIRE_RL_mkConnectionGetPut_1 = - CAN_FIRE_RL_mkConnectionGetPut_1 ; + // rule RL_ClientServerResponse_1 + assign CAN_FIRE_RL_ClientServerResponse_1 = + debug_module$RDY_hart0_gpr_mem_client_response_put && + proc$RDY_hart0_gpr_mem_server_response_get ; + assign WILL_FIRE_RL_ClientServerResponse_1 = + CAN_FIRE_RL_ClientServerResponse_1 ; - // rule RL_mkConnectionGetPut_2 - assign CAN_FIRE_RL_mkConnectionGetPut_2 = - tv_encode$RDY_v_cpu_in_0_put && v_td2_to_td_0_f_out$EMPTY_N ; - assign WILL_FIRE_RL_mkConnectionGetPut_2 = - CAN_FIRE_RL_mkConnectionGetPut_2 ; - - // rule RL_mkConnectionGetPut_3 - assign CAN_FIRE_RL_mkConnectionGetPut_3 = - proc$RDY_v_to_TV_1_get && v_td2_to_td_1_f_in$FULL_N ; - assign WILL_FIRE_RL_mkConnectionGetPut_3 = - CAN_FIRE_RL_mkConnectionGetPut_3 ; - - // rule RL_mkConnectionGetPut_4 - assign CAN_FIRE_RL_mkConnectionGetPut_4 = - tv_encode$RDY_v_cpu_in_1_put && v_td2_to_td_1_f_out$EMPTY_N ; - assign WILL_FIRE_RL_mkConnectionGetPut_4 = - CAN_FIRE_RL_mkConnectionGetPut_4 ; + // rule RL_ClientServerResponse_2 + assign CAN_FIRE_RL_ClientServerResponse_2 = + debug_module$RDY_hart0_csr_mem_client_response_put && + proc$RDY_hart0_csr_mem_server_response_get ; + assign WILL_FIRE_RL_ClientServerResponse_2 = + CAN_FIRE_RL_ClientServerResponse_2 ; // rule RL_rl_wr_addr_channel assign CAN_FIRE_RL_rl_wr_addr_channel = 1'd1 ; @@ -2885,6 +2384,10 @@ module mkCoreW(CLK, assign CAN_FIRE_RL_rl_wr_data_channel = 1'd1 ; assign WILL_FIRE_RL_rl_wr_data_channel = 1'd1 ; + // rule RL_rl_wr_response_channel + assign CAN_FIRE_RL_rl_wr_response_channel = 1'd1 ; + assign WILL_FIRE_RL_rl_wr_response_channel = 1'd1 ; + // rule RL_rl_rd_addr_channel assign CAN_FIRE_RL_rl_rd_addr_channel = 1'd1 ; assign WILL_FIRE_RL_rl_rd_addr_channel = 1'd1 ; @@ -2893,70 +2396,6 @@ module mkCoreW(CLK, assign CAN_FIRE_RL_rl_rd_data_channel = 1'd1 ; assign WILL_FIRE_RL_rl_rd_data_channel = 1'd1 ; - // rule RL_ClientServerRequest_1 - assign CAN_FIRE_RL_ClientServerRequest_1 = - debug_module$RDY_hart0_gpr_mem_client_request_get && - dm_gpr_tap_ifc$RDY_server_request_put ; - assign WILL_FIRE_RL_ClientServerRequest_1 = - CAN_FIRE_RL_ClientServerRequest_1 ; - - // rule RL_ClientServerResponse_1 - assign CAN_FIRE_RL_ClientServerResponse_1 = - debug_module$RDY_hart0_gpr_mem_client_response_put && - dm_gpr_tap_ifc$RDY_server_response_get ; - assign WILL_FIRE_RL_ClientServerResponse_1 = - CAN_FIRE_RL_ClientServerResponse_1 ; - - // rule RL_ClientServerResponse_2 - assign CAN_FIRE_RL_ClientServerResponse_2 = - proc$RDY_hart0_gpr_mem_server_response_get && - dm_gpr_tap_ifc$RDY_client_response_put ; - assign WILL_FIRE_RL_ClientServerResponse_2 = - CAN_FIRE_RL_ClientServerResponse_2 ; - - // rule RL_rl_merge_dm_gpr_trace_data - assign CAN_FIRE_RL_rl_merge_dm_gpr_trace_data = - tv_encode$RDY_dm_in_put && - dm_gpr_tap_ifc$RDY_trace_data_out_get ; - assign WILL_FIRE_RL_rl_merge_dm_gpr_trace_data = - CAN_FIRE_RL_rl_merge_dm_gpr_trace_data ; - - // rule RL_ClientServerRequest_3 - assign CAN_FIRE_RL_ClientServerRequest_3 = - debug_module$RDY_hart0_csr_mem_client_request_get && - dm_csr_tap$RDY_server_request_put ; - assign WILL_FIRE_RL_ClientServerRequest_3 = - CAN_FIRE_RL_ClientServerRequest_3 ; - - // rule RL_ClientServerResponse_3 - assign CAN_FIRE_RL_ClientServerResponse_3 = - debug_module$RDY_hart0_csr_mem_client_response_put && - dm_csr_tap$RDY_server_response_get ; - assign WILL_FIRE_RL_ClientServerResponse_3 = - CAN_FIRE_RL_ClientServerResponse_3 ; - - // rule RL_ClientServerResponse_4 - assign CAN_FIRE_RL_ClientServerResponse_4 = - proc$RDY_hart0_csr_mem_server_response_get && - dm_csr_tap$RDY_client_response_put ; - assign WILL_FIRE_RL_ClientServerResponse_4 = - CAN_FIRE_RL_ClientServerResponse_4 ; - - // rule RL_rl_merge_dm_mem_trace_data - assign CAN_FIRE_RL_rl_merge_dm_mem_trace_data = - tv_encode$RDY_dm_in_put && dm_mem_tap$RDY_trace_data_out_get ; - assign WILL_FIRE_RL_rl_merge_dm_mem_trace_data = - CAN_FIRE_RL_rl_merge_dm_mem_trace_data && - !WILL_FIRE_RL_rl_merge_dm_csr_trace_data && - !WILL_FIRE_RL_rl_merge_dm_gpr_trace_data ; - - // rule RL_rl_merge_dm_csr_trace_data - assign CAN_FIRE_RL_rl_merge_dm_csr_trace_data = - tv_encode$RDY_dm_in_put && dm_csr_tap$RDY_trace_data_out_get ; - assign WILL_FIRE_RL_rl_merge_dm_csr_trace_data = - CAN_FIRE_RL_rl_merge_dm_csr_trace_data && - !WILL_FIRE_RL_rl_merge_dm_gpr_trace_data ; - // rule RL_rl_wr_addr_channel_1 assign CAN_FIRE_RL_rl_wr_addr_channel_1 = 1'd1 ; assign WILL_FIRE_RL_rl_wr_addr_channel_1 = 1'd1 ; @@ -3017,130 +2456,80 @@ module mkCoreW(CLK, assign CAN_FIRE_RL_rl_rd_data_channel_3 = 1'd1 ; assign WILL_FIRE_RL_rl_rd_data_channel_3 = 1'd1 ; - // rule RL_rl_wr_addr_channel_4 - assign CAN_FIRE_RL_rl_wr_addr_channel_4 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_4 = 1'd1 ; - - // rule RL_rl_wr_data_channel_4 - assign CAN_FIRE_RL_rl_wr_data_channel_4 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_4 = 1'd1 ; - - // rule RL_rl_wr_response_channel_4 - assign CAN_FIRE_RL_rl_wr_response_channel_4 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_4 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_4 - assign CAN_FIRE_RL_rl_rd_addr_channel_4 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_4 = 1'd1 ; - - // rule RL_rl_rd_data_channel_4 - assign CAN_FIRE_RL_rl_rd_data_channel_4 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_4 = 1'd1 ; - // rule RL_rl_relay_external_interrupts assign CAN_FIRE_RL_rl_relay_external_interrupts = 1'd1 ; assign WILL_FIRE_RL_rl_relay_external_interrupts = 1'd1 ; - // rule RL_rl_cpu_hart0_reset_from_soc_start - assign CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start = - fabric_2x3$RDY_reset && tv_encode$RDY_reset && - plic$RDY_server_reset_request_put && - proc$RDY_hart0_server_reset_request_put && - f_reset_reqs$EMPTY_N && - f_reset_requestor$FULL_N ; - assign WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start = - CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; - - // rule RL_rl_cpu_hart0_reset_from_dm_start - assign CAN_FIRE_RL_rl_cpu_hart0_reset_from_dm_start = - fabric_2x3$RDY_reset && tv_encode$RDY_reset && - debug_module$RDY_hart0_get_reset_req_get && - plic$RDY_server_reset_request_put && - proc$RDY_hart0_server_reset_request_put && - f_reset_requestor$FULL_N ; - assign WILL_FIRE_RL_rl_cpu_hart0_reset_from_dm_start = - CAN_FIRE_RL_rl_cpu_hart0_reset_from_dm_start && - !WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; - - // rule RL_rl_cpu_hart0_reset_complete - assign CAN_FIRE_RL_rl_cpu_hart0_reset_complete = - plic$RDY_server_reset_response_get && - proc$RDY_hart0_server_reset_response_get && - proc$RDY_start && - f_reset_requestor$EMPTY_N && - (!f_reset_requestor$D_OUT || f_reset_rsps$FULL_N) ; - assign WILL_FIRE_RL_rl_cpu_hart0_reset_complete = - CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; - - // rule RL_rl_wr_response_channel - assign CAN_FIRE_RL_rl_wr_response_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel = 1'd1 ; + // rule RL_ClientServerRequest_1 + assign CAN_FIRE_RL_ClientServerRequest_1 = + debug_module$RDY_hart0_gpr_mem_client_request_get && + proc$RDY_hart0_gpr_mem_server_request_put ; + assign WILL_FIRE_RL_ClientServerRequest_1 = + CAN_FIRE_RL_ClientServerRequest_1 ; // rule RL_ClientServerRequest_2 assign CAN_FIRE_RL_ClientServerRequest_2 = - proc$RDY_hart0_gpr_mem_server_request_put && - dm_gpr_tap_ifc$RDY_client_request_get ; + debug_module$RDY_hart0_csr_mem_client_request_get && + proc$RDY_hart0_csr_mem_server_request_put ; assign WILL_FIRE_RL_ClientServerRequest_2 = CAN_FIRE_RL_ClientServerRequest_2 ; - // rule RL_ClientServerRequest_4 - assign CAN_FIRE_RL_ClientServerRequest_4 = - proc$RDY_hart0_csr_mem_server_request_put && - dm_csr_tap$RDY_client_request_get ; - assign WILL_FIRE_RL_ClientServerRequest_4 = - CAN_FIRE_RL_ClientServerRequest_4 ; - - // rule RL_rl_relay_non_maskable_interrupt - assign CAN_FIRE_RL_rl_relay_non_maskable_interrupt = 1'd1 ; - assign WILL_FIRE_RL_rl_relay_non_maskable_interrupt = 1'd1 ; - - // rule RL_v_td2_to_td_0_rl_xform - assign CAN_FIRE_RL_v_td2_to_td_0_rl_xform = - v_td2_to_td_0_f_in$EMPTY_N && v_td2_to_td_0_f_out$FULL_N ; - assign WILL_FIRE_RL_v_td2_to_td_0_rl_xform = - CAN_FIRE_RL_v_td2_to_td_0_rl_xform ; - - // rule RL_v_td2_to_td_1_rl_xform - assign CAN_FIRE_RL_v_td2_to_td_1_rl_xform = - v_td2_to_td_1_f_in$EMPTY_N && v_td2_to_td_1_f_out$FULL_N ; - assign WILL_FIRE_RL_v_td2_to_td_1_rl_xform = - CAN_FIRE_RL_v_td2_to_td_1_rl_xform ; + // inputs to muxes for submodule ports + assign MUX_proc$start_1__SEL_1 = + WILL_FIRE_RL_rl_dm_hart0_reset_wait && + rg_hart0_reset_delay == 8'd1 ; + assign MUX_rg_hart0_reset_delay$write_1__VAL_1 = + rg_hart0_reset_delay - 8'd1 ; // register rg_fromhost_addr - assign rg_fromhost_addr$D_IN = set_htif_addrs_fromhost_addr ; - assign rg_fromhost_addr$EN = EN_set_htif_addrs ; + assign rg_fromhost_addr$D_IN = start_fromhost_addr ; + assign rg_fromhost_addr$EN = EN_start ; + + // register rg_hart0_reset_delay + assign rg_hart0_reset_delay$D_IN = + WILL_FIRE_RL_rl_dm_hart0_reset_wait ? + MUX_rg_hart0_reset_delay$write_1__VAL_1 : + 8'd210 ; + assign rg_hart0_reset_delay$EN = + WILL_FIRE_RL_rl_dm_hart0_reset_wait || + WILL_FIRE_RL_rl_dm_hart0_reset ; // register rg_tohost_addr - assign rg_tohost_addr$D_IN = set_htif_addrs_tohost_addr ; - assign rg_tohost_addr$EN = EN_set_htif_addrs ; + assign rg_tohost_addr$D_IN = start_tohost_addr ; + assign rg_tohost_addr$EN = EN_start ; // submodule debug_module - assign debug_module$dmi_read_addr_dm_addr = dm_dmi_read_addr_dm_addr ; - assign debug_module$dmi_write_dm_addr = dm_dmi_write_dm_addr ; - assign debug_module$dmi_write_dm_word = dm_dmi_write_dm_word ; + assign debug_module$dmi_read_addr_dm_addr = dmi_read_addr_dm_addr ; + assign debug_module$dmi_write_dm_addr = dmi_write_dm_addr ; + assign debug_module$dmi_write_dm_word = dmi_write_dm_word ; assign debug_module$hart0_client_run_halt_response_put = proc$hart0_run_halt_server_response_get ; assign debug_module$hart0_csr_mem_client_response_put = - dm_csr_tap$server_response_get ; + proc$hart0_csr_mem_server_response_get ; assign debug_module$hart0_fpr_mem_client_response_put = 65'h0 ; assign debug_module$hart0_gpr_mem_client_response_put = - dm_gpr_tap_ifc$server_response_get ; - assign debug_module$master_arready = dm_mem_tap$slave_arready ; - assign debug_module$master_awready = dm_mem_tap$slave_awready ; - assign debug_module$master_bid = dm_mem_tap$slave_bid ; - assign debug_module$master_bresp = dm_mem_tap$slave_bresp ; - assign debug_module$master_bvalid = dm_mem_tap$slave_bvalid ; - assign debug_module$master_rdata = dm_mem_tap$slave_rdata ; - assign debug_module$master_rid = dm_mem_tap$slave_rid ; - assign debug_module$master_rlast = dm_mem_tap$slave_rlast ; - assign debug_module$master_rresp = dm_mem_tap$slave_rresp ; - assign debug_module$master_rvalid = dm_mem_tap$slave_rvalid ; - assign debug_module$master_wready = dm_mem_tap$slave_wready ; - assign debug_module$EN_dmi_read_addr = EN_dm_dmi_read_addr ; - assign debug_module$EN_dmi_read_data = EN_dm_dmi_read_data ; - assign debug_module$EN_dmi_write = EN_dm_dmi_write ; - assign debug_module$EN_hart0_get_reset_req_get = - WILL_FIRE_RL_rl_cpu_hart0_reset_from_dm_start ; + proc$hart0_gpr_mem_server_response_get ; + assign debug_module$hart0_reset_client_response_put = 1'd1 ; + assign debug_module$master_arready = fabric_2x3$v_from_masters_1_arready ; + assign debug_module$master_awready = fabric_2x3$v_from_masters_1_awready ; + assign debug_module$master_bid = fabric_2x3$v_from_masters_1_bid ; + assign debug_module$master_bresp = fabric_2x3$v_from_masters_1_bresp ; + assign debug_module$master_bvalid = fabric_2x3$v_from_masters_1_bvalid ; + assign debug_module$master_rdata = fabric_2x3$v_from_masters_1_rdata ; + assign debug_module$master_rid = fabric_2x3$v_from_masters_1_rid ; + assign debug_module$master_rlast = fabric_2x3$v_from_masters_1_rlast ; + assign debug_module$master_rresp = fabric_2x3$v_from_masters_1_rresp ; + assign debug_module$master_rvalid = fabric_2x3$v_from_masters_1_rvalid ; + assign debug_module$master_wready = fabric_2x3$v_from_masters_1_wready ; + assign debug_module$ndm_reset_client_response_put = + ndm_reset_client_response_put ; + assign debug_module$EN_dmi_read_addr = EN_dmi_read_addr ; + assign debug_module$EN_dmi_read_data = EN_dmi_read_data ; + assign debug_module$EN_dmi_write = EN_dmi_write ; + assign debug_module$EN_hart0_reset_client_request_get = + CAN_FIRE_RL_rl_dm_hart0_reset ; + assign debug_module$EN_hart0_reset_client_response_put = + MUX_proc$start_1__SEL_1 ; assign debug_module$EN_hart0_client_run_halt_request_get = CAN_FIRE_RL_ClientServerRequest ; assign debug_module$EN_hart0_client_run_halt_response_put = @@ -3154,107 +2543,16 @@ module mkCoreW(CLK, assign debug_module$EN_hart0_fpr_mem_client_request_get = 1'b0 ; assign debug_module$EN_hart0_fpr_mem_client_response_put = 1'b0 ; assign debug_module$EN_hart0_csr_mem_client_request_get = - CAN_FIRE_RL_ClientServerRequest_3 ; - assign debug_module$EN_hart0_csr_mem_client_response_put = - CAN_FIRE_RL_ClientServerResponse_3 ; - assign debug_module$EN_get_ndm_reset_req_get = EN_dm_ndm_reset_req_get_get ; - - // submodule dm_csr_tap - assign dm_csr_tap$client_response_put = - proc$hart0_csr_mem_server_response_get ; - assign dm_csr_tap$server_request_put = - debug_module$hart0_csr_mem_client_request_get ; - assign dm_csr_tap$EN_client_request_get = - CAN_FIRE_RL_ClientServerRequest_4 ; - assign dm_csr_tap$EN_client_response_put = - CAN_FIRE_RL_ClientServerResponse_4 ; - assign dm_csr_tap$EN_server_request_put = - CAN_FIRE_RL_ClientServerRequest_3 ; - assign dm_csr_tap$EN_server_response_get = - CAN_FIRE_RL_ClientServerResponse_3 ; - assign dm_csr_tap$EN_trace_data_out_get = - WILL_FIRE_RL_rl_merge_dm_csr_trace_data ; - - // submodule dm_gpr_tap_ifc - assign dm_gpr_tap_ifc$client_response_put = - proc$hart0_gpr_mem_server_response_get ; - assign dm_gpr_tap_ifc$server_request_put = - debug_module$hart0_gpr_mem_client_request_get ; - assign dm_gpr_tap_ifc$EN_client_request_get = CAN_FIRE_RL_ClientServerRequest_2 ; - assign dm_gpr_tap_ifc$EN_client_response_put = + assign debug_module$EN_hart0_csr_mem_client_response_put = CAN_FIRE_RL_ClientServerResponse_2 ; - assign dm_gpr_tap_ifc$EN_server_request_put = - CAN_FIRE_RL_ClientServerRequest_1 ; - assign dm_gpr_tap_ifc$EN_server_response_get = - CAN_FIRE_RL_ClientServerResponse_1 ; - assign dm_gpr_tap_ifc$EN_trace_data_out_get = - CAN_FIRE_RL_rl_merge_dm_gpr_trace_data ; + assign debug_module$EN_ndm_reset_client_request_get = + EN_ndm_reset_client_request_get ; + assign debug_module$EN_ndm_reset_client_response_put = + EN_ndm_reset_client_response_put ; - // submodule dm_mem_tap - assign dm_mem_tap$master_arready = fabric_2x3$v_from_masters_1_arready ; - assign dm_mem_tap$master_awready = fabric_2x3$v_from_masters_1_awready ; - assign dm_mem_tap$master_bid = fabric_2x3$v_from_masters_1_bid ; - assign dm_mem_tap$master_bresp = fabric_2x3$v_from_masters_1_bresp ; - assign dm_mem_tap$master_bvalid = fabric_2x3$v_from_masters_1_bvalid ; - assign dm_mem_tap$master_rdata = fabric_2x3$v_from_masters_1_rdata ; - assign dm_mem_tap$master_rid = fabric_2x3$v_from_masters_1_rid ; - assign dm_mem_tap$master_rlast = fabric_2x3$v_from_masters_1_rlast ; - assign dm_mem_tap$master_rresp = fabric_2x3$v_from_masters_1_rresp ; - assign dm_mem_tap$master_rvalid = fabric_2x3$v_from_masters_1_rvalid ; - assign dm_mem_tap$master_wready = fabric_2x3$v_from_masters_1_wready ; - assign dm_mem_tap$slave_araddr = debug_module$master_araddr ; - assign dm_mem_tap$slave_arburst = debug_module$master_arburst ; - assign dm_mem_tap$slave_arcache = debug_module$master_arcache ; - assign dm_mem_tap$slave_arid = debug_module$master_arid ; - assign dm_mem_tap$slave_arlen = debug_module$master_arlen ; - assign dm_mem_tap$slave_arlock = debug_module$master_arlock ; - assign dm_mem_tap$slave_arprot = debug_module$master_arprot ; - assign dm_mem_tap$slave_arqos = debug_module$master_arqos ; - assign dm_mem_tap$slave_arregion = debug_module$master_arregion ; - assign dm_mem_tap$slave_arsize = debug_module$master_arsize ; - assign dm_mem_tap$slave_arvalid = debug_module$master_arvalid ; - assign dm_mem_tap$slave_awaddr = debug_module$master_awaddr ; - assign dm_mem_tap$slave_awburst = debug_module$master_awburst ; - assign dm_mem_tap$slave_awcache = debug_module$master_awcache ; - assign dm_mem_tap$slave_awid = debug_module$master_awid ; - assign dm_mem_tap$slave_awlen = debug_module$master_awlen ; - assign dm_mem_tap$slave_awlock = debug_module$master_awlock ; - assign dm_mem_tap$slave_awprot = debug_module$master_awprot ; - assign dm_mem_tap$slave_awqos = debug_module$master_awqos ; - assign dm_mem_tap$slave_awregion = debug_module$master_awregion ; - assign dm_mem_tap$slave_awsize = debug_module$master_awsize ; - assign dm_mem_tap$slave_awvalid = debug_module$master_awvalid ; - assign dm_mem_tap$slave_bready = debug_module$master_bready ; - assign dm_mem_tap$slave_rready = debug_module$master_rready ; - assign dm_mem_tap$slave_wdata = debug_module$master_wdata ; - assign dm_mem_tap$slave_wid = debug_module$master_wid ; - assign dm_mem_tap$slave_wlast = debug_module$master_wlast ; - assign dm_mem_tap$slave_wstrb = debug_module$master_wstrb ; - assign dm_mem_tap$slave_wvalid = debug_module$master_wvalid ; - assign dm_mem_tap$EN_trace_data_out_get = - WILL_FIRE_RL_rl_merge_dm_mem_trace_data ; - - // submodule f_reset_reqs - assign f_reset_reqs$ENQ = EN_cpu_reset_server_request_put ; - assign f_reset_reqs$DEQ = CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; - assign f_reset_reqs$CLR = 1'b0 ; - - // submodule f_reset_requestor - assign f_reset_requestor$D_IN = - !WILL_FIRE_RL_rl_cpu_hart0_reset_from_dm_start ; - assign f_reset_requestor$ENQ = - WILL_FIRE_RL_rl_cpu_hart0_reset_from_dm_start || - WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; - assign f_reset_requestor$DEQ = CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; - assign f_reset_requestor$CLR = 1'b0 ; - - // submodule f_reset_rsps - assign f_reset_rsps$ENQ = - WILL_FIRE_RL_rl_cpu_hart0_reset_complete && - f_reset_requestor$D_OUT ; - assign f_reset_rsps$DEQ = EN_cpu_reset_server_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; + // submodule dm_hart0_reset_controller + assign dm_hart0_reset_controller$ASSERT_IN = CAN_FIRE_RL_rl_dm_hart0_reset ; // submodule fabric_2x3 assign fabric_2x3$set_verbosity_verbosity = 4'h0 ; @@ -3283,39 +2581,37 @@ module mkCoreW(CLK, assign fabric_2x3$v_from_masters_0_bready = proc$master1_bready ; assign fabric_2x3$v_from_masters_0_rready = proc$master1_rready ; assign fabric_2x3$v_from_masters_0_wdata = proc$master1_wdata ; - assign fabric_2x3$v_from_masters_0_wid = proc$master1_wid ; assign fabric_2x3$v_from_masters_0_wlast = proc$master1_wlast ; assign fabric_2x3$v_from_masters_0_wstrb = proc$master1_wstrb ; assign fabric_2x3$v_from_masters_0_wvalid = proc$master1_wvalid ; - assign fabric_2x3$v_from_masters_1_araddr = dm_mem_tap$master_araddr ; - assign fabric_2x3$v_from_masters_1_arburst = dm_mem_tap$master_arburst ; - assign fabric_2x3$v_from_masters_1_arcache = dm_mem_tap$master_arcache ; - assign fabric_2x3$v_from_masters_1_arid = dm_mem_tap$master_arid ; - assign fabric_2x3$v_from_masters_1_arlen = dm_mem_tap$master_arlen ; - assign fabric_2x3$v_from_masters_1_arlock = dm_mem_tap$master_arlock ; - assign fabric_2x3$v_from_masters_1_arprot = dm_mem_tap$master_arprot ; - assign fabric_2x3$v_from_masters_1_arqos = dm_mem_tap$master_arqos ; - assign fabric_2x3$v_from_masters_1_arregion = dm_mem_tap$master_arregion ; - assign fabric_2x3$v_from_masters_1_arsize = dm_mem_tap$master_arsize ; - assign fabric_2x3$v_from_masters_1_arvalid = dm_mem_tap$master_arvalid ; - assign fabric_2x3$v_from_masters_1_awaddr = dm_mem_tap$master_awaddr ; - assign fabric_2x3$v_from_masters_1_awburst = dm_mem_tap$master_awburst ; - assign fabric_2x3$v_from_masters_1_awcache = dm_mem_tap$master_awcache ; - assign fabric_2x3$v_from_masters_1_awid = dm_mem_tap$master_awid ; - assign fabric_2x3$v_from_masters_1_awlen = dm_mem_tap$master_awlen ; - assign fabric_2x3$v_from_masters_1_awlock = dm_mem_tap$master_awlock ; - assign fabric_2x3$v_from_masters_1_awprot = dm_mem_tap$master_awprot ; - assign fabric_2x3$v_from_masters_1_awqos = dm_mem_tap$master_awqos ; - assign fabric_2x3$v_from_masters_1_awregion = dm_mem_tap$master_awregion ; - assign fabric_2x3$v_from_masters_1_awsize = dm_mem_tap$master_awsize ; - assign fabric_2x3$v_from_masters_1_awvalid = dm_mem_tap$master_awvalid ; - assign fabric_2x3$v_from_masters_1_bready = dm_mem_tap$master_bready ; - assign fabric_2x3$v_from_masters_1_rready = dm_mem_tap$master_rready ; - assign fabric_2x3$v_from_masters_1_wdata = dm_mem_tap$master_wdata ; - assign fabric_2x3$v_from_masters_1_wid = dm_mem_tap$master_wid ; - assign fabric_2x3$v_from_masters_1_wlast = dm_mem_tap$master_wlast ; - assign fabric_2x3$v_from_masters_1_wstrb = dm_mem_tap$master_wstrb ; - assign fabric_2x3$v_from_masters_1_wvalid = dm_mem_tap$master_wvalid ; + assign fabric_2x3$v_from_masters_1_araddr = debug_module$master_araddr ; + assign fabric_2x3$v_from_masters_1_arburst = debug_module$master_arburst ; + assign fabric_2x3$v_from_masters_1_arcache = debug_module$master_arcache ; + assign fabric_2x3$v_from_masters_1_arid = debug_module$master_arid ; + assign fabric_2x3$v_from_masters_1_arlen = debug_module$master_arlen ; + assign fabric_2x3$v_from_masters_1_arlock = debug_module$master_arlock ; + assign fabric_2x3$v_from_masters_1_arprot = debug_module$master_arprot ; + assign fabric_2x3$v_from_masters_1_arqos = debug_module$master_arqos ; + assign fabric_2x3$v_from_masters_1_arregion = debug_module$master_arregion ; + assign fabric_2x3$v_from_masters_1_arsize = debug_module$master_arsize ; + assign fabric_2x3$v_from_masters_1_arvalid = debug_module$master_arvalid ; + assign fabric_2x3$v_from_masters_1_awaddr = debug_module$master_awaddr ; + assign fabric_2x3$v_from_masters_1_awburst = debug_module$master_awburst ; + assign fabric_2x3$v_from_masters_1_awcache = debug_module$master_awcache ; + assign fabric_2x3$v_from_masters_1_awid = debug_module$master_awid ; + assign fabric_2x3$v_from_masters_1_awlen = debug_module$master_awlen ; + assign fabric_2x3$v_from_masters_1_awlock = debug_module$master_awlock ; + assign fabric_2x3$v_from_masters_1_awprot = debug_module$master_awprot ; + assign fabric_2x3$v_from_masters_1_awqos = debug_module$master_awqos ; + assign fabric_2x3$v_from_masters_1_awregion = debug_module$master_awregion ; + assign fabric_2x3$v_from_masters_1_awsize = debug_module$master_awsize ; + assign fabric_2x3$v_from_masters_1_awvalid = debug_module$master_awvalid ; + assign fabric_2x3$v_from_masters_1_bready = debug_module$master_bready ; + assign fabric_2x3$v_from_masters_1_rready = debug_module$master_rready ; + assign fabric_2x3$v_from_masters_1_wdata = debug_module$master_wdata ; + assign fabric_2x3$v_from_masters_1_wlast = debug_module$master_wlast ; + assign fabric_2x3$v_from_masters_1_wstrb = debug_module$master_wstrb ; + assign fabric_2x3$v_from_masters_1_wvalid = debug_module$master_wvalid ; assign fabric_2x3$v_to_slaves_0_arready = cpu_dmem_master_arready ; assign fabric_2x3$v_to_slaves_0_awready = cpu_dmem_master_awready ; assign fabric_2x3$v_to_slaves_0_bid = cpu_dmem_master_bid ; @@ -3354,9 +2650,7 @@ module mkCoreW(CLK, proc$debug_module_mem_server_rvalid ; assign fabric_2x3$v_to_slaves_2_wready = proc$debug_module_mem_server_wready ; - assign fabric_2x3$EN_reset = - WILL_FIRE_RL_rl_cpu_hart0_reset_from_dm_start || - WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; + assign fabric_2x3$EN_reset = 1'b0 ; assign fabric_2x3$EN_set_verbosity = 1'b0 ; // submodule plic @@ -3385,7 +2679,6 @@ module mkCoreW(CLK, assign plic$axi4_slave_bready = fabric_2x3$v_to_slaves_1_bready ; assign plic$axi4_slave_rready = fabric_2x3$v_to_slaves_1_rready ; assign plic$axi4_slave_wdata = fabric_2x3$v_to_slaves_1_wdata ; - assign plic$axi4_slave_wid = fabric_2x3$v_to_slaves_1_wid ; assign plic$axi4_slave_wlast = fabric_2x3$v_to_slaves_1_wlast ; assign plic$axi4_slave_wstrb = fabric_2x3$v_to_slaves_1_wstrb ; assign plic$axi4_slave_wvalid = fabric_2x3$v_to_slaves_1_wvalid ; @@ -3426,16 +2719,11 @@ module mkCoreW(CLK, core_external_interrupt_sources_9_m_interrupt_req_set_not_clear ; assign plic$EN_set_verbosity = 1'b0 ; assign plic$EN_show_PLIC_state = 1'b0 ; - assign plic$EN_server_reset_request_put = - WILL_FIRE_RL_rl_cpu_hart0_reset_from_dm_start || - WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; - assign plic$EN_server_reset_response_get = - CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; - assign plic$EN_set_addr_map = CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; + assign plic$EN_server_reset_request_put = 1'b0 ; + assign plic$EN_server_reset_response_get = 1'b0 ; + assign plic$EN_set_addr_map = EN_start ; // submodule proc - assign proc$debug_external_interrupt_req_set_not_clear = - debug_external_interrupt_req_set_not_clear ; assign proc$debug_module_mem_server_araddr = fabric_2x3$v_to_slaves_2_araddr ; assign proc$debug_module_mem_server_arburst = @@ -3479,16 +2767,15 @@ module mkCoreW(CLK, assign proc$debug_module_mem_server_rready = fabric_2x3$v_to_slaves_2_rready ; assign proc$debug_module_mem_server_wdata = fabric_2x3$v_to_slaves_2_wdata ; - assign proc$debug_module_mem_server_wid = fabric_2x3$v_to_slaves_2_wid ; assign proc$debug_module_mem_server_wlast = fabric_2x3$v_to_slaves_2_wlast ; assign proc$debug_module_mem_server_wstrb = fabric_2x3$v_to_slaves_2_wstrb ; assign proc$debug_module_mem_server_wvalid = fabric_2x3$v_to_slaves_2_wvalid ; assign proc$hart0_csr_mem_server_request_put = - dm_csr_tap$client_request_get ; + debug_module$hart0_csr_mem_client_request_get ; assign proc$hart0_fpr_mem_server_request_put = 70'h0 ; assign proc$hart0_gpr_mem_server_request_put = - dm_gpr_tap_ifc$client_request_get ; + debug_module$hart0_gpr_mem_client_request_get ; assign proc$hart0_put_other_req_put = debug_module$hart0_get_other_req_get ; assign proc$hart0_run_halt_server_request_put = debug_module$hart0_client_run_halt_request_get ; @@ -3520,370 +2807,40 @@ module mkCoreW(CLK, assign proc$s_external_interrupt_req_set_not_clear = plic$v_targets_1_m_eip ; assign proc$set_verbosity_verbosity = set_verbosity_verbosity ; - assign proc$start_fromhostAddr = rg_fromhost_addr ; + assign proc$start_fromhostAddr = + MUX_proc$start_1__SEL_1 ? + rg_fromhost_addr : + start_fromhost_addr ; assign proc$start_startpc = 64'h0000000070000000 ; - assign proc$start_tohostAddr = rg_tohost_addr ; - assign proc$EN_hart0_server_reset_request_put = - WILL_FIRE_RL_rl_cpu_hart0_reset_from_dm_start || - WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; - assign proc$EN_hart0_server_reset_response_get = - CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; - assign proc$EN_start = CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; + assign proc$start_tohostAddr = + MUX_proc$start_1__SEL_1 ? rg_tohost_addr : start_tohost_addr ; + assign proc$EN_start = + WILL_FIRE_RL_rl_dm_hart0_reset_wait && + rg_hart0_reset_delay == 8'd1 || + EN_start ; assign proc$EN_set_verbosity = EN_set_verbosity ; assign proc$EN_hart0_run_halt_server_request_put = CAN_FIRE_RL_ClientServerRequest ; assign proc$EN_hart0_run_halt_server_response_get = CAN_FIRE_RL_ClientServerResponse ; assign proc$EN_hart0_gpr_mem_server_request_put = - CAN_FIRE_RL_ClientServerRequest_2 ; + CAN_FIRE_RL_ClientServerRequest_1 ; assign proc$EN_hart0_gpr_mem_server_response_get = - CAN_FIRE_RL_ClientServerResponse_2 ; + CAN_FIRE_RL_ClientServerResponse_1 ; assign proc$EN_hart0_fpr_mem_server_request_put = 1'b0 ; assign proc$EN_hart0_fpr_mem_server_response_get = 1'b0 ; assign proc$EN_hart0_csr_mem_server_request_put = - CAN_FIRE_RL_ClientServerRequest_4 ; + CAN_FIRE_RL_ClientServerRequest_2 ; assign proc$EN_hart0_csr_mem_server_response_get = - CAN_FIRE_RL_ClientServerResponse_4 ; + CAN_FIRE_RL_ClientServerResponse_2 ; assign proc$EN_hart0_put_other_req_put = debug_module$RDY_hart0_get_other_req_get ; - assign proc$EN_v_to_TV_0_get = CAN_FIRE_RL_mkConnectionGetPut_1 ; - assign proc$EN_v_to_TV_1_get = CAN_FIRE_RL_mkConnectionGetPut_3 ; // submodule soc_map assign soc_map$m_is_IO_addr_addr = 64'h0 ; assign soc_map$m_is_mem_addr_addr = 64'h0 ; assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - // submodule tv_encode - always@(WILL_FIRE_RL_rl_merge_dm_mem_trace_data or - dm_mem_tap$trace_data_out_get or - WILL_FIRE_RL_rl_merge_dm_gpr_trace_data or - dm_gpr_tap_ifc$trace_data_out_get or - WILL_FIRE_RL_rl_merge_dm_csr_trace_data or - dm_csr_tap$trace_data_out_get) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_rl_merge_dm_mem_trace_data: - tv_encode$dm_in_put = dm_mem_tap$trace_data_out_get; - WILL_FIRE_RL_rl_merge_dm_gpr_trace_data: - tv_encode$dm_in_put = dm_gpr_tap_ifc$trace_data_out_get; - WILL_FIRE_RL_rl_merge_dm_csr_trace_data: - tv_encode$dm_in_put = dm_csr_tap$trace_data_out_get; - default: tv_encode$dm_in_put = - 427'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign tv_encode$v_cpu_in_0_put = v_td2_to_td_0_f_out$D_OUT ; - assign tv_encode$v_cpu_in_1_put = v_td2_to_td_1_f_out$D_OUT ; - assign tv_encode$EN_reset = - WILL_FIRE_RL_rl_cpu_hart0_reset_from_dm_start || - WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; - assign tv_encode$EN_v_cpu_in_0_put = CAN_FIRE_RL_mkConnectionGetPut_2 ; - assign tv_encode$EN_v_cpu_in_1_put = CAN_FIRE_RL_mkConnectionGetPut_4 ; - assign tv_encode$EN_dm_in_put = - WILL_FIRE_RL_rl_merge_dm_mem_trace_data || - WILL_FIRE_RL_rl_merge_dm_gpr_trace_data || - WILL_FIRE_RL_rl_merge_dm_csr_trace_data ; - assign tv_encode$EN_out_get = EN_tv_verifier_info_get_get ; - - // submodule v_td2_to_td_0_f_in - assign v_td2_to_td_0_f_in$D_IN = - { proc$v_to_TV_0_get[319:154], - proc$v_to_TV_0_get[154] ? - CASE_procv_to_TV_0_get_BITS_153_TO_142_1_proc_ETC__q1 : - 12'hAAA, - proc$v_to_TV_0_get[141], - proc$v_to_TV_0_get[141] ? - { proc$v_to_TV_0_get[140], - proc$v_to_TV_0_get[140] ? - CASE_procv_to_TV_0_get_BITS_139_TO_136_0_proc_ETC__q2 : - CASE_procv_to_TV_0_get_BITS_139_TO_136_0_proc_ETC__q3 } : - 5'h0A, - proc$v_to_TV_0_get[135:72], - CASE_procv_to_TV_0_get_BITS_71_TO_70_0_procv_ETC__q4, - proc$v_to_TV_0_get[69:0] } ; - assign v_td2_to_td_0_f_in$ENQ = CAN_FIRE_RL_mkConnectionGetPut_1 ; - assign v_td2_to_td_0_f_in$DEQ = CAN_FIRE_RL_v_td2_to_td_0_rl_xform ; - assign v_td2_to_td_0_f_in$CLR = 1'b0 ; - - // submodule v_td2_to_td_0_f_out - assign v_td2_to_td_0_f_out$D_IN = - { v_td2_to_td_0_f_in$D_OUT[319:256], - CASE_v_td2_to_td_0_f_inD_OUT_BITS_159_TO_155__ETC__q9, - v_td2_to_td_0_f_in$D_OUT[255:192], - v_td2_to_td_0_f_in$D_OUT[161:160] == 2'b11, - v_td2_to_td_0_f_in$D_OUT[191:160], - x1_avValue_rd__h5432, - x__h5725, - 256'h000000000000000000000000000000000000000000000000AAAAAAAAAAAAAAAA } ; - assign v_td2_to_td_0_f_out$ENQ = CAN_FIRE_RL_v_td2_to_td_0_rl_xform ; - assign v_td2_to_td_0_f_out$DEQ = CAN_FIRE_RL_mkConnectionGetPut_2 ; - assign v_td2_to_td_0_f_out$CLR = 1'b0 ; - - // submodule v_td2_to_td_1_f_in - assign v_td2_to_td_1_f_in$D_IN = - { proc$v_to_TV_1_get[319:154], - proc$v_to_TV_1_get[154] ? - CASE_procv_to_TV_1_get_BITS_153_TO_142_1_proc_ETC__q5 : - 12'hAAA, - proc$v_to_TV_1_get[141], - proc$v_to_TV_1_get[141] ? - { proc$v_to_TV_1_get[140], - proc$v_to_TV_1_get[140] ? - CASE_procv_to_TV_1_get_BITS_139_TO_136_0_proc_ETC__q6 : - CASE_procv_to_TV_1_get_BITS_139_TO_136_0_proc_ETC__q7 } : - 5'h0A, - proc$v_to_TV_1_get[135:72], - CASE_procv_to_TV_1_get_BITS_71_TO_70_0_procv_ETC__q8, - proc$v_to_TV_1_get[69:0] } ; - assign v_td2_to_td_1_f_in$ENQ = CAN_FIRE_RL_mkConnectionGetPut_3 ; - assign v_td2_to_td_1_f_in$DEQ = CAN_FIRE_RL_v_td2_to_td_1_rl_xform ; - assign v_td2_to_td_1_f_in$CLR = 1'b0 ; - - // submodule v_td2_to_td_1_f_out - assign v_td2_to_td_1_f_out$D_IN = - { v_td2_to_td_1_f_in$D_OUT[319:256], - CASE_v_td2_to_td_1_f_inD_OUT_BITS_159_TO_155__ETC__q10, - v_td2_to_td_1_f_in$D_OUT[255:192], - v_td2_to_td_1_f_in$D_OUT[161:160] == 2'b11, - v_td2_to_td_1_f_in$D_OUT[191:160], - x1_avValue_rd__h6363, - x__h6650, - 256'h000000000000000000000000000000000000000000000000AAAAAAAAAAAAAAAA } ; - assign v_td2_to_td_1_f_out$ENQ = CAN_FIRE_RL_v_td2_to_td_1_rl_xform ; - assign v_td2_to_td_1_f_out$DEQ = CAN_FIRE_RL_mkConnectionGetPut_4 ; - assign v_td2_to_td_1_f_out$CLR = 1'b0 ; - - // remaining internal signals - always@(v_td2_to_td_0_f_in$D_OUT) - begin - case (v_td2_to_td_0_f_in$D_OUT[159:155]) - 5'd3, 5'd8, 5'd9, 5'd11: x__h5725 = 64'd0; - default: x__h5725 = 64'd0; - endcase - end - always@(v_td2_to_td_0_f_in$D_OUT) - begin - case (v_td2_to_td_0_f_in$D_OUT[159:155]) - 5'd3, 5'd8, 5'd9, 5'd11: x1_avValue_rd__h5432 = 5'd0; - default: x1_avValue_rd__h5432 = 5'd0; - endcase - end - always@(v_td2_to_td_1_f_in$D_OUT) - begin - case (v_td2_to_td_1_f_in$D_OUT[159:155]) - 5'd3, 5'd8, 5'd9, 5'd11: x1_avValue_rd__h6363 = 5'd0; - default: x1_avValue_rd__h6363 = 5'd0; - endcase - end - always@(v_td2_to_td_1_f_in$D_OUT) - begin - case (v_td2_to_td_1_f_in$D_OUT[159:155]) - 5'd3, 5'd8, 5'd9, 5'd11: x__h6650 = 64'd0; - default: x__h6650 = 64'd0; - endcase - end - always@(proc$v_to_TV_0_get) - begin - case (proc$v_to_TV_0_get[153:142]) - 12'd1, - 12'd2, - 12'd3, - 12'd256, - 12'd260, - 12'd261, - 12'd262, - 12'd320, - 12'd321, - 12'd322, - 12'd323, - 12'd324, - 12'd384, - 12'd768, - 12'd769, - 12'd770, - 12'd771, - 12'd772, - 12'd773, - 12'd774, - 12'd832, - 12'd833, - 12'd834, - 12'd835, - 12'd836, - 12'd1968, - 12'd1969, - 12'd1970, - 12'd1971, - 12'd2048, - 12'd2049, - 12'd2816, - 12'd2818, - 12'd3072, - 12'd3073, - 12'd3074, - 12'd3857, - 12'd3858, - 12'd3859, - 12'd3860: - CASE_procv_to_TV_0_get_BITS_153_TO_142_1_proc_ETC__q1 = - proc$v_to_TV_0_get[153:142]; - default: CASE_procv_to_TV_0_get_BITS_153_TO_142_1_proc_ETC__q1 = - 12'd2303; - endcase - end - always@(proc$v_to_TV_0_get) - begin - case (proc$v_to_TV_0_get[139:136]) - 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: - CASE_procv_to_TV_0_get_BITS_139_TO_136_0_proc_ETC__q2 = - proc$v_to_TV_0_get[139:136]; - default: CASE_procv_to_TV_0_get_BITS_139_TO_136_0_proc_ETC__q2 = 4'd15; - endcase - end - always@(proc$v_to_TV_0_get) - begin - case (proc$v_to_TV_0_get[139:136]) - 4'd0, - 4'd1, - 4'd2, - 4'd3, - 4'd4, - 4'd5, - 4'd6, - 4'd7, - 4'd8, - 4'd9, - 4'd11, - 4'd12, - 4'd13: - CASE_procv_to_TV_0_get_BITS_139_TO_136_0_proc_ETC__q3 = - proc$v_to_TV_0_get[139:136]; - default: CASE_procv_to_TV_0_get_BITS_139_TO_136_0_proc_ETC__q3 = 4'd15; - endcase - end - always@(proc$v_to_TV_0_get) - begin - case (proc$v_to_TV_0_get[71:70]) - 2'd0, 2'd1: - CASE_procv_to_TV_0_get_BITS_71_TO_70_0_procv_ETC__q4 = - proc$v_to_TV_0_get[71:70]; - default: CASE_procv_to_TV_0_get_BITS_71_TO_70_0_procv_ETC__q4 = 2'd2; - endcase - end - always@(proc$v_to_TV_1_get) - begin - case (proc$v_to_TV_1_get[153:142]) - 12'd1, - 12'd2, - 12'd3, - 12'd256, - 12'd260, - 12'd261, - 12'd262, - 12'd320, - 12'd321, - 12'd322, - 12'd323, - 12'd324, - 12'd384, - 12'd768, - 12'd769, - 12'd770, - 12'd771, - 12'd772, - 12'd773, - 12'd774, - 12'd832, - 12'd833, - 12'd834, - 12'd835, - 12'd836, - 12'd1968, - 12'd1969, - 12'd1970, - 12'd1971, - 12'd2048, - 12'd2049, - 12'd2816, - 12'd2818, - 12'd3072, - 12'd3073, - 12'd3074, - 12'd3857, - 12'd3858, - 12'd3859, - 12'd3860: - CASE_procv_to_TV_1_get_BITS_153_TO_142_1_proc_ETC__q5 = - proc$v_to_TV_1_get[153:142]; - default: CASE_procv_to_TV_1_get_BITS_153_TO_142_1_proc_ETC__q5 = - 12'd2303; - endcase - end - always@(proc$v_to_TV_1_get) - begin - case (proc$v_to_TV_1_get[139:136]) - 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: - CASE_procv_to_TV_1_get_BITS_139_TO_136_0_proc_ETC__q6 = - proc$v_to_TV_1_get[139:136]; - default: CASE_procv_to_TV_1_get_BITS_139_TO_136_0_proc_ETC__q6 = 4'd15; - endcase - end - always@(proc$v_to_TV_1_get) - begin - case (proc$v_to_TV_1_get[139:136]) - 4'd0, - 4'd1, - 4'd2, - 4'd3, - 4'd4, - 4'd5, - 4'd6, - 4'd7, - 4'd8, - 4'd9, - 4'd11, - 4'd12, - 4'd13: - CASE_procv_to_TV_1_get_BITS_139_TO_136_0_proc_ETC__q7 = - proc$v_to_TV_1_get[139:136]; - default: CASE_procv_to_TV_1_get_BITS_139_TO_136_0_proc_ETC__q7 = 4'd15; - endcase - end - always@(proc$v_to_TV_1_get) - begin - case (proc$v_to_TV_1_get[71:70]) - 2'd0, 2'd1: - CASE_procv_to_TV_1_get_BITS_71_TO_70_0_procv_ETC__q8 = - proc$v_to_TV_1_get[71:70]; - default: CASE_procv_to_TV_1_get_BITS_71_TO_70_0_procv_ETC__q8 = 2'd2; - endcase - end - always@(v_td2_to_td_0_f_in$D_OUT) - begin - case (v_td2_to_td_0_f_in$D_OUT[159:155]) - 5'd2, 5'd6, 5'd7: - CASE_v_td2_to_td_0_f_inD_OUT_BITS_159_TO_155__ETC__q9 = 5'd13; - 5'd3, 5'd8, 5'd9, 5'd11: - CASE_v_td2_to_td_0_f_inD_OUT_BITS_159_TO_155__ETC__q9 = 5'd6; - 5'd10, 5'd14, 5'd15, 5'd16, 5'd17, 5'd18, 5'd19, 5'd20: - CASE_v_td2_to_td_0_f_inD_OUT_BITS_159_TO_155__ETC__q9 = 5'd5; - default: CASE_v_td2_to_td_0_f_inD_OUT_BITS_159_TO_155__ETC__q9 = 5'd6; - endcase - end - always@(v_td2_to_td_1_f_in$D_OUT) - begin - case (v_td2_to_td_1_f_in$D_OUT[159:155]) - 5'd2, 5'd6, 5'd7: - CASE_v_td2_to_td_1_f_inD_OUT_BITS_159_TO_155__ETC__q10 = 5'd13; - 5'd3, 5'd8, 5'd9, 5'd11: - CASE_v_td2_to_td_1_f_inD_OUT_BITS_159_TO_155__ETC__q10 = 5'd6; - 5'd10, 5'd14, 5'd15, 5'd16, 5'd17, 5'd18, 5'd19, 5'd20: - CASE_v_td2_to_td_1_f_inD_OUT_BITS_159_TO_155__ETC__q10 = 5'd5; - default: CASE_v_td2_to_td_1_f_inD_OUT_BITS_159_TO_155__ETC__q10 = 5'd6; - endcase - end - // handling of inlined registers always@(posedge CLK) @@ -3891,12 +2848,16 @@ module mkCoreW(CLK, if (RST_N == `BSV_RESET_VALUE) begin rg_fromhost_addr <= `BSV_ASSIGNMENT_DELAY 64'd0; + rg_hart0_reset_delay <= `BSV_ASSIGNMENT_DELAY 8'd0; rg_tohost_addr <= `BSV_ASSIGNMENT_DELAY 64'd0; end else begin if (rg_fromhost_addr$EN) rg_fromhost_addr <= `BSV_ASSIGNMENT_DELAY rg_fromhost_addr$D_IN; + if (rg_hart0_reset_delay$EN) + rg_hart0_reset_delay <= `BSV_ASSIGNMENT_DELAY + rg_hart0_reset_delay$D_IN; if (rg_tohost_addr$EN) rg_tohost_addr <= `BSV_ASSIGNMENT_DELAY rg_tohost_addr$D_IN; end @@ -3908,6 +2869,7 @@ module mkCoreW(CLK, initial begin rg_fromhost_addr = 64'hAAAAAAAAAAAAAAAA; + rg_hart0_reset_delay = 8'hAA; rg_tohost_addr = 64'hAAAAAAAAAAAAAAAA; end `endif // BSV_NO_INITIAL_BLOCKS @@ -3920,36 +2882,55 @@ module mkCoreW(CLK, begin #0; if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start) - begin - v__h7205 = $stime; - #0; - end - v__h7199 = v__h7205 / 32'd10; + if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_dm_hart0_reset) + begin + v__h4797 = $stime; + #0; + end + v__h4791 = v__h4797 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start) - $display("%0d: Core.rl_cpu_hart0_reset_from_soc_start", v__h7199); + if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_dm_hart0_reset) + $display("%0d: %m.rl_dm_hart0_reset: asserting hart0 reset for %0d cycles", + v__h4791, + $signed(32'd10)); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cpu_hart0_reset_from_dm_start) - begin - v__h7403 = $stime; - #0; - end - v__h7397 = v__h7403 / 32'd10; + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_dm_hart0_reset_wait && + rg_hart0_reset_delay == 8'd1) + begin + v__h4940 = $stime; + #0; + end + v__h4934 = v__h4940 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cpu_hart0_reset_from_dm_start) - $display("%0d: Core.rl_cpu_hart0_reset_from_dm_start", v__h7397); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_dm_hart0_reset_wait && + rg_hart0_reset_delay == 8'd1) + $display("%0d: %m.rl_dm_hart0_reset_wait: proc.start (pc %0h, tohostAddr %0h, fromhostAddr %0h", + v__h4934, + 64'h0000000070000000, + rg_tohost_addr, + rg_fromhost_addr); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cpu_hart0_reset_complete) - begin - v__h7674 = $stime; - #0; - end - v__h7668 = v__h7674 / 32'd10; + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (EN_start) + begin + v__h8302 = $stime; + #0; + end + v__h8296 = v__h8302 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cpu_hart0_reset_complete) - $display("%0d: Core.rl_cpu_hart0_reset_complete; started running proc", - v__h7668); + if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) + if (EN_start) + $display("%0d: %m.method start: proc.start (pc %0h, tohostAddr %0h, fromhostAddr %0h)", + v__h8296, + 64'h0000000070000000, + start_tohost_addr, + start_fromhost_addr); end // synopsys translate_on endmodule // mkCoreW diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkDCRqMshrWrapper.v b/src_SSITH_P3_sim/Verilog_RTL/mkDCRqMshrWrapper.v index 1e80025..532f19a 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkDCRqMshrWrapper.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkDCRqMshrWrapper.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkDM_Abstract_Commands.v b/src_SSITH_P3_sim/Verilog_RTL/mkDM_Abstract_Commands.v index c78345f..218002e 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkDM_Abstract_Commands.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkDM_Abstract_Commands.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // @@ -306,27 +306,27 @@ module mkDM_Abstract_Commands(CLK, // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h2815; - reg [31 : 0] v__h3054; - reg [31 : 0] v__h3179; - reg [31 : 0] v__h3506; - reg [31 : 0] v__h3623; - reg [31 : 0] v__h3336; - reg [31 : 0] v__h4114; - reg [31 : 0] v__h2809; - reg [31 : 0] v__h3048; - reg [31 : 0] v__h3173; - reg [31 : 0] v__h3330; - reg [31 : 0] v__h3500; - reg [31 : 0] v__h3617; - reg [31 : 0] v__h4108; + reg [31 : 0] v__h2853; + reg [31 : 0] v__h3092; + reg [31 : 0] v__h3217; + reg [31 : 0] v__h3544; + reg [31 : 0] v__h3661; + reg [31 : 0] v__h3374; + reg [31 : 0] v__h4152; + reg [31 : 0] v__h2847; + reg [31 : 0] v__h3086; + reg [31 : 0] v__h3211; + reg [31 : 0] v__h3368; + reg [31 : 0] v__h3538; + reg [31 : 0] v__h3655; + reg [31 : 0] v__h4146; // synopsys translate_on // remaining internal signals - wire [63 : 0] req_data__h860; - wire [31 : 0] virt_rg_abstractcs__h706, virt_rg_command__h770; - wire [15 : 0] regno__h2639; - wire [12 : 0] x__h1321, x__h1746; + wire [63 : 0] req_data__h896; + wire [31 : 0] virt_rg_abstractcs__h742, virt_rg_command__h806; + wire [15 : 0] regno__h2677; + wire [12 : 0] x__h1357, x__h1782; wire rg_abstractcs_busy_AND_rg_start_reg_access_AND_ETC___d38, rg_abstractcs_busy_AND_rg_start_reg_access_AND_ETC___d49, rg_abstractcs_busy_AND_rg_start_reg_access_AND_ETC___d61, @@ -352,12 +352,12 @@ module mkDM_Abstract_Commands(CLK, // actionvalue method av_read always@(av_read_dm_addr or rg_data1 or - rg_data0 or virt_rg_abstractcs__h706 or virt_rg_command__h770) + rg_data0 or virt_rg_abstractcs__h742 or virt_rg_command__h806) begin case (av_read_dm_addr) 7'h04: av_read = rg_data0; - 7'h16: av_read = virt_rg_abstractcs__h706; - 7'h17: av_read = virt_rg_command__h770; + 7'h16: av_read = virt_rg_abstractcs__h742; + 7'h17: av_read = virt_rg_command__h806; default: av_read = rg_data1; endcase end @@ -416,7 +416,7 @@ module mkDM_Abstract_Commands(CLK, EN_hart0_csr_mem_client_response_put ; // submodule f_hart0_csr_reqs - FIFO1 #(.width(32'd77), .guarded(32'd1)) f_hart0_csr_reqs(.RST(RST_N), + FIFO2 #(.width(32'd77), .guarded(32'd1)) f_hart0_csr_reqs(.RST(RST_N), .CLK(CLK), .D_IN(f_hart0_csr_reqs$D_IN), .ENQ(f_hart0_csr_reqs$ENQ), @@ -427,7 +427,7 @@ module mkDM_Abstract_Commands(CLK, .EMPTY_N(f_hart0_csr_reqs$EMPTY_N)); // submodule f_hart0_csr_rsps - FIFO1 #(.width(32'd65), .guarded(32'd1)) f_hart0_csr_rsps(.RST(RST_N), + FIFO2 #(.width(32'd65), .guarded(32'd1)) f_hart0_csr_rsps(.RST(RST_N), .CLK(CLK), .D_IN(f_hart0_csr_rsps$D_IN), .ENQ(f_hart0_csr_rsps$ENQ), @@ -438,7 +438,7 @@ module mkDM_Abstract_Commands(CLK, .EMPTY_N(f_hart0_csr_rsps$EMPTY_N)); // submodule f_hart0_fpr_reqs - FIFO1 #(.width(32'd70), .guarded(32'd1)) f_hart0_fpr_reqs(.RST(RST_N), + FIFO2 #(.width(32'd70), .guarded(32'd1)) f_hart0_fpr_reqs(.RST(RST_N), .CLK(CLK), .D_IN(f_hart0_fpr_reqs$D_IN), .ENQ(f_hart0_fpr_reqs$ENQ), @@ -449,7 +449,7 @@ module mkDM_Abstract_Commands(CLK, .EMPTY_N(f_hart0_fpr_reqs$EMPTY_N)); // submodule f_hart0_fpr_rsps - FIFO1 #(.width(32'd65), .guarded(32'd1)) f_hart0_fpr_rsps(.RST(RST_N), + FIFO2 #(.width(32'd65), .guarded(32'd1)) f_hart0_fpr_rsps(.RST(RST_N), .CLK(CLK), .D_IN(f_hart0_fpr_rsps$D_IN), .ENQ(f_hart0_fpr_rsps$ENQ), @@ -460,7 +460,7 @@ module mkDM_Abstract_Commands(CLK, .EMPTY_N(f_hart0_fpr_rsps$EMPTY_N)); // submodule f_hart0_gpr_reqs - FIFO1 #(.width(32'd70), .guarded(32'd1)) f_hart0_gpr_reqs(.RST(RST_N), + FIFO2 #(.width(32'd70), .guarded(32'd1)) f_hart0_gpr_reqs(.RST(RST_N), .CLK(CLK), .D_IN(f_hart0_gpr_reqs$D_IN), .ENQ(f_hart0_gpr_reqs$ENQ), @@ -471,7 +471,7 @@ module mkDM_Abstract_Commands(CLK, .EMPTY_N(f_hart0_gpr_reqs$EMPTY_N)); // submodule f_hart0_gpr_rsps - FIFO1 #(.width(32'd65), .guarded(32'd1)) f_hart0_gpr_rsps(.RST(RST_N), + FIFO2 #(.width(32'd65), .guarded(32'd1)) f_hart0_gpr_rsps(.RST(RST_N), .CLK(CLK), .D_IN(f_hart0_gpr_rsps$D_IN), .ENQ(f_hart0_gpr_rsps$ENQ), @@ -611,19 +611,19 @@ module mkDM_Abstract_Commands(CLK, EN_write && rg_abstractcs_cmderr == 3'd0 && write_dm_addr == 7'h05 ; assign MUX_f_hart0_csr_reqs$enq_1__VAL_1 = - { 1'd1, rg_command_access_reg_regno[11:0], req_data__h860 } ; + { 1'd1, rg_command_access_reg_regno[11:0], req_data__h896 } ; assign MUX_f_hart0_csr_reqs$enq_1__VAL_2 = { 1'd0, rg_command_access_reg_regno[11:0], 64'hAAAAAAAAAAAAAAAA } ; assign MUX_f_hart0_fpr_reqs$enq_1__VAL_1 = - { 1'd1, x__h1746[4:0], req_data__h860 } ; + { 1'd1, x__h1782[4:0], req_data__h896 } ; assign MUX_f_hart0_fpr_reqs$enq_1__VAL_2 = - { 1'd0, x__h1746[4:0], 64'hAAAAAAAAAAAAAAAA } ; + { 1'd0, x__h1782[4:0], 64'hAAAAAAAAAAAAAAAA } ; assign MUX_f_hart0_gpr_reqs$enq_1__VAL_1 = - { 1'd1, x__h1321[4:0], req_data__h860 } ; + { 1'd1, x__h1357[4:0], req_data__h896 } ; assign MUX_f_hart0_gpr_reqs$enq_1__VAL_2 = - { 1'd0, x__h1321[4:0], 64'hAAAAAAAAAAAAAAAA } ; + { 1'd0, x__h1357[4:0], 64'hAAAAAAAAAAAAAAAA } ; assign MUX_rg_abstractcs_cmderr$write_1__VAL_4 = f_hart0_fpr_rsps$D_OUT[64] ? 3'd0 : 3'd4 ; always@(write_dm_addr or rg_abstractcs_busy or write_dm_word) @@ -722,10 +722,10 @@ module mkDM_Abstract_Commands(CLK, assign rg_abstractcs_cmderr$EN = EN_write && write_dm_addr_EQ_0x16_00_AND_rg_abstractcs_bus_ETC___d117 || - WILL_FIRE_RL_rl_gpr_read_finish || - WILL_FIRE_RL_rl_gpr_write_finish || WILL_FIRE_RL_rl_csr_read_finish || WILL_FIRE_RL_rl_csr_write_finish || + WILL_FIRE_RL_rl_gpr_read_finish || + WILL_FIRE_RL_rl_gpr_write_finish || WILL_FIRE_RL_rl_fpr_read_finish || WILL_FIRE_RL_rl_fpr_write_finish || EN_reset || @@ -897,8 +897,8 @@ module mkDM_Abstract_Commands(CLK, assign f_hart0_gpr_rsps$CLR = EN_reset ; // remaining internal signals - assign regno__h2639 = { 3'd0, rg_command_access_reg_regno } ; - assign req_data__h860 = { rg_data1, rg_data0 } ; + assign regno__h2677 = { 3'd0, rg_command_access_reg_regno } ; + assign req_data__h896 = { rg_data1, rg_data0 } ; assign rg_abstractcs_busy_AND_rg_start_reg_access_AND_ETC___d38 = rg_abstractcs_busy && rg_start_reg_access && rg_command_access_reg_write && @@ -938,10 +938,10 @@ module mkDM_Abstract_Commands(CLK, rg_command_access_reg_regno < 13'h1000 ; assign rg_command_access_reg_regno_ULT_0x1020___d57 = rg_command_access_reg_regno < 13'h1020 ; - assign virt_rg_abstractcs__h706 = - { 19'd0, rg_abstractcs_busy, 1'b0, rg_abstractcs_cmderr, 8'd0 } ; - assign virt_rg_command__h770 = - { 15'd17, rg_command_access_reg_write, regno__h2639 } ; + assign virt_rg_abstractcs__h742 = + { 19'd0, rg_abstractcs_busy, 1'b0, rg_abstractcs_cmderr, 8'd2 } ; + assign virt_rg_command__h806 = + { 15'd17, rg_command_access_reg_write, regno__h2677 } ; assign write_dm_addr_EQ_0x16_00_AND_rg_abstractcs_bus_ETC___d117 = write_dm_addr == 7'h16 && (rg_abstractcs_busy || write_dm_word[10:8] != 3'd0) || @@ -975,8 +975,8 @@ module mkDM_Abstract_Commands(CLK, write_dm_word[22:20] != 3'd4 && write_dm_word[22:20] != 3'd5 && write_dm_word[22:20] != 3'd6 ; - assign x__h1321 = rg_command_access_reg_regno - 13'h1000 ; - assign x__h1746 = rg_command_access_reg_regno - 13'h1020 ; + assign x__h1357 = rg_command_access_reg_regno - 13'h1000 ; + assign x__h1782 = rg_command_access_reg_regno - 13'h1020 ; // handling of inlined registers @@ -1031,14 +1031,14 @@ module mkDM_Abstract_Commands(CLK, if (RST_N != `BSV_RESET_VALUE) if (EN_write && write_dm_addr == 7'h16 && rg_abstractcs_busy) begin - v__h2815 = $stime; + v__h2853 = $stime; #0; end - v__h2809 = v__h2815 / 32'd10; + v__h2847 = v__h2853 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_write && write_dm_addr == 7'h16 && rg_abstractcs_busy) $display("%0d: DM_Abstract_Commands.write: [abstractcs] <= 0x%08h: ERROR", - v__h2809, + v__h2847, write_dm_word); if (RST_N != `BSV_RESET_VALUE) if (EN_write && write_dm_addr == 7'h16 && rg_abstractcs_busy) @@ -1048,16 +1048,16 @@ module mkDM_Abstract_Commands(CLK, write_dm_addr == 7'h17 && rg_abstractcs_busy) begin - v__h3054 = $stime; + v__h3092 = $stime; #0; end - v__h3048 = v__h3054 / 32'd10; + v__h3086 = v__h3092 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_write && rg_abstractcs_cmderr == 3'd0 && write_dm_addr == 7'h17 && rg_abstractcs_busy) $display("%0d: DM_Abstract_Commands.write: [command] <= 0x%08h: ERROR", - v__h3048, + v__h3086, write_dm_word); if (RST_N != `BSV_RESET_VALUE) if (EN_write && rg_abstractcs_cmderr == 3'd0 && @@ -1068,15 +1068,15 @@ module mkDM_Abstract_Commands(CLK, if (EN_write && rg_abstractcs_cmderr_1_EQ_0_07_AND_write_dm_ad_ETC___d142) begin - v__h3179 = $stime; + v__h3217 = $stime; #0; end - v__h3173 = v__h3179 / 32'd10; + v__h3211 = v__h3217 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_write && rg_abstractcs_cmderr_1_EQ_0_07_AND_write_dm_ad_ETC___d142) $display("%0d: DM_Abstract_Commands.write: [command] <= 0x%08h: ERROR", - v__h3173, + v__h3211, write_dm_word); if (RST_N != `BSV_RESET_VALUE) if (EN_write && @@ -1094,15 +1094,15 @@ module mkDM_Abstract_Commands(CLK, if (EN_write && rg_abstractcs_cmderr == 3'd0 && write_dm_addr_EQ_0x17_08_AND_NOT_rg_abstractcs_ETC___d149) begin - v__h3506 = $stime; + v__h3544 = $stime; #0; end - v__h3500 = v__h3506 / 32'd10; + v__h3538 = v__h3544 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_write && rg_abstractcs_cmderr == 3'd0 && write_dm_addr_EQ_0x17_08_AND_NOT_rg_abstractcs_ETC___d149) $display("%0d: DM_Abstract_Commands.write: [command] <= 0x%08h: ERROR", - v__h3500, + v__h3538, write_dm_word); if (RST_N != `BSV_RESET_VALUE) if (EN_write && rg_abstractcs_cmderr == 3'd0 && @@ -1112,15 +1112,15 @@ module mkDM_Abstract_Commands(CLK, if (EN_write && rg_abstractcs_cmderr == 3'd0 && write_dm_addr_EQ_0x17_08_AND_NOT_rg_abstractcs_ETC___d167) begin - v__h3623 = $stime; + v__h3661 = $stime; #0; end - v__h3617 = v__h3623 / 32'd10; + v__h3655 = v__h3661 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_write && rg_abstractcs_cmderr == 3'd0 && write_dm_addr_EQ_0x17_08_AND_NOT_rg_abstractcs_ETC___d167) $display("%0d: DM_Abstract_Commands.write: [command] <= 0x%08h: ERROR", - v__h3617, + v__h3655, write_dm_word); if (RST_N != `BSV_RESET_VALUE) if (EN_write && rg_abstractcs_cmderr == 3'd0 && @@ -1130,15 +1130,15 @@ module mkDM_Abstract_Commands(CLK, if (EN_write && rg_abstractcs_cmderr_1_EQ_0_07_AND_write_dm_ad_ETC___d174) begin - v__h3336 = $stime; + v__h3374 = $stime; #0; end - v__h3330 = v__h3336 / 32'd10; + v__h3368 = v__h3374 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_write && rg_abstractcs_cmderr_1_EQ_0_07_AND_write_dm_ad_ETC___d174) $display("%0d: DM_Abstract_Commands.write: [command] <= 0x%08h: ERROR", - v__h3330, + v__h3368, write_dm_word); if (RST_N != `BSV_RESET_VALUE) if (EN_write && @@ -1201,17 +1201,17 @@ module mkDM_Abstract_Commands(CLK, write_dm_addr != 7'h04 && write_dm_addr != 7'h05) begin - v__h4114 = $stime; + v__h4152 = $stime; #0; end - v__h4108 = v__h4114 / 32'd10; + v__h4146 = v__h4152 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_write && write_dm_addr != 7'h16 && rg_abstractcs_cmderr == 3'd0 && write_dm_addr != 7'h17 && write_dm_addr != 7'h04 && write_dm_addr != 7'h05) - $write("%0d: DM_Abstract_Commands.write: [", v__h4108); + $write("%0d: DM_Abstract_Commands.write: [", v__h4146); if (RST_N != `BSV_RESET_VALUE) if (EN_write && rg_abstractcs_cmderr == 3'd0 && write_dm_addr == 7'h10) $write("dm_addr_dmcontrol"); diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkDM_Run_Control.v b/src_SSITH_P3_sim/Verilog_RTL/mkDM_Run_Control.v index 2c47720..67c257c 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkDM_Run_Control.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkDM_Run_Control.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // @@ -12,27 +12,35 @@ // av_read O 32 // RDY_av_read O 1 const // RDY_write O 1 -// RDY_hart0_get_reset_req_get O 1 reg +// hart0_reset_client_request_get O 1 reg +// RDY_hart0_reset_client_request_get O 1 reg +// RDY_hart0_reset_client_response_put O 1 reg // hart0_client_run_halt_request_get O 1 reg // RDY_hart0_client_run_halt_request_get O 1 reg // RDY_hart0_client_run_halt_response_put O 1 reg // hart0_get_other_req_get O 4 reg // RDY_hart0_get_other_req_get O 1 reg -// RDY_get_ndm_reset_req_get O 1 reg +// ndm_reset_client_request_get O 1 reg +// RDY_ndm_reset_client_request_get O 1 reg +// RDY_ndm_reset_client_response_put O 1 reg // CLK I 1 clock // RST_N I 1 reset // av_read_dm_addr I 7 // write_dm_addr I 7 // write_dm_word I 32 +// hart0_reset_client_response_put I 1 reg // hart0_client_run_halt_response_put I 1 reg +// ndm_reset_client_response_put I 1 reg // EN_reset I 1 // EN_write I 1 -// EN_hart0_get_reset_req_get I 1 +// EN_hart0_reset_client_response_put I 1 // EN_hart0_client_run_halt_response_put I 1 -// EN_get_ndm_reset_req_get I 1 +// EN_ndm_reset_client_response_put I 1 // EN_av_read I 1 unused +// EN_hart0_reset_client_request_get I 1 // EN_hart0_client_run_halt_request_get I 1 // EN_hart0_get_other_req_get I 1 +// EN_ndm_reset_client_request_get I 1 // // Combinational paths from inputs to outputs: // av_read_dm_addr -> av_read @@ -71,8 +79,13 @@ module mkDM_Run_Control(CLK, EN_write, RDY_write, - EN_hart0_get_reset_req_get, - RDY_hart0_get_reset_req_get, + EN_hart0_reset_client_request_get, + hart0_reset_client_request_get, + RDY_hart0_reset_client_request_get, + + hart0_reset_client_response_put, + EN_hart0_reset_client_response_put, + RDY_hart0_reset_client_response_put, EN_hart0_client_run_halt_request_get, hart0_client_run_halt_request_get, @@ -86,8 +99,13 @@ module mkDM_Run_Control(CLK, hart0_get_other_req_get, RDY_hart0_get_other_req_get, - EN_get_ndm_reset_req_get, - RDY_get_ndm_reset_req_get); + EN_ndm_reset_client_request_get, + ndm_reset_client_request_get, + RDY_ndm_reset_client_request_get, + + ndm_reset_client_response_put, + EN_ndm_reset_client_response_put, + RDY_ndm_reset_client_response_put); input CLK; input RST_N; @@ -111,9 +129,15 @@ module mkDM_Run_Control(CLK, input EN_write; output RDY_write; - // action method hart0_get_reset_req_get - input EN_hart0_get_reset_req_get; - output RDY_hart0_get_reset_req_get; + // actionvalue method hart0_reset_client_request_get + input EN_hart0_reset_client_request_get; + output hart0_reset_client_request_get; + output RDY_hart0_reset_client_request_get; + + // action method hart0_reset_client_response_put + input hart0_reset_client_response_put; + input EN_hart0_reset_client_response_put; + output RDY_hart0_reset_client_response_put; // actionvalue method hart0_client_run_halt_request_get input EN_hart0_client_run_halt_request_get; @@ -130,24 +154,34 @@ module mkDM_Run_Control(CLK, output [3 : 0] hart0_get_other_req_get; output RDY_hart0_get_other_req_get; - // action method get_ndm_reset_req_get - input EN_get_ndm_reset_req_get; - output RDY_get_ndm_reset_req_get; + // actionvalue method ndm_reset_client_request_get + input EN_ndm_reset_client_request_get; + output ndm_reset_client_request_get; + output RDY_ndm_reset_client_request_get; + + // action method ndm_reset_client_response_put + input ndm_reset_client_response_put; + input EN_ndm_reset_client_response_put; + output RDY_ndm_reset_client_response_put; // signals for module outputs reg [31 : 0] av_read; wire [3 : 0] hart0_get_other_req_get; wire RDY_av_read, RDY_dmactive, - RDY_get_ndm_reset_req_get, RDY_hart0_client_run_halt_request_get, RDY_hart0_client_run_halt_response_put, RDY_hart0_get_other_req_get, - RDY_hart0_get_reset_req_get, + RDY_hart0_reset_client_request_get, + RDY_hart0_reset_client_response_put, + RDY_ndm_reset_client_request_get, + RDY_ndm_reset_client_response_put, RDY_reset, RDY_write, dmactive, - hart0_client_run_halt_request_get; + hart0_client_run_halt_request_get, + hart0_reset_client_request_get, + ndm_reset_client_request_get; // register rg_dmcontrol_dmactive reg rg_dmcontrol_dmactive; @@ -170,6 +204,14 @@ module mkDM_Run_Control(CLK, reg rg_dmstatus_allresumeack$D_IN; wire rg_dmstatus_allresumeack$EN; + // register rg_dmstatus_allunavail + reg rg_dmstatus_allunavail; + wire rg_dmstatus_allunavail$D_IN, rg_dmstatus_allunavail$EN; + + // register rg_hart0_hasreset + reg rg_hart0_hasreset; + wire rg_hart0_hasreset$D_IN, rg_hart0_hasreset$EN; + // register rg_hart0_running reg rg_hart0_running; reg rg_hart0_running$D_IN; @@ -191,10 +233,21 @@ module mkDM_Run_Control(CLK, // ports of submodule f_hart0_reset_reqs wire f_hart0_reset_reqs$CLR, f_hart0_reset_reqs$DEQ, + f_hart0_reset_reqs$D_IN, + f_hart0_reset_reqs$D_OUT, f_hart0_reset_reqs$EMPTY_N, f_hart0_reset_reqs$ENQ, f_hart0_reset_reqs$FULL_N; + // ports of submodule f_hart0_reset_rsps + wire f_hart0_reset_rsps$CLR, + f_hart0_reset_rsps$DEQ, + f_hart0_reset_rsps$D_IN, + f_hart0_reset_rsps$D_OUT, + f_hart0_reset_rsps$EMPTY_N, + f_hart0_reset_rsps$ENQ, + f_hart0_reset_rsps$FULL_N; + // ports of submodule f_hart0_run_halt_reqs wire f_hart0_run_halt_reqs$CLR, f_hart0_run_halt_reqs$DEQ, @@ -216,42 +269,89 @@ module mkDM_Run_Control(CLK, // ports of submodule f_ndm_reset_reqs wire f_ndm_reset_reqs$CLR, f_ndm_reset_reqs$DEQ, + f_ndm_reset_reqs$D_IN, + f_ndm_reset_reqs$D_OUT, f_ndm_reset_reqs$EMPTY_N, f_ndm_reset_reqs$ENQ, f_ndm_reset_reqs$FULL_N; + // ports of submodule f_ndm_reset_rsps + wire f_ndm_reset_rsps$CLR, + f_ndm_reset_rsps$DEQ, + f_ndm_reset_rsps$D_IN, + f_ndm_reset_rsps$D_OUT, + f_ndm_reset_rsps$EMPTY_N, + f_ndm_reset_rsps$ENQ, + f_ndm_reset_rsps$FULL_N; + // rule scheduling signals - wire CAN_FIRE_RL_rl_hart0_run_rsp, + wire CAN_FIRE_RL_rl_hart0_reset_rsp, + CAN_FIRE_RL_rl_hart0_run_rsp, + CAN_FIRE_RL_rl_ndm_reset_rsp, CAN_FIRE_av_read, - CAN_FIRE_get_ndm_reset_req_get, CAN_FIRE_hart0_client_run_halt_request_get, CAN_FIRE_hart0_client_run_halt_response_put, CAN_FIRE_hart0_get_other_req_get, - CAN_FIRE_hart0_get_reset_req_get, + CAN_FIRE_hart0_reset_client_request_get, + CAN_FIRE_hart0_reset_client_response_put, + CAN_FIRE_ndm_reset_client_request_get, + CAN_FIRE_ndm_reset_client_response_put, CAN_FIRE_reset, CAN_FIRE_write, + WILL_FIRE_RL_rl_hart0_reset_rsp, WILL_FIRE_RL_rl_hart0_run_rsp, + WILL_FIRE_RL_rl_ndm_reset_rsp, WILL_FIRE_av_read, - WILL_FIRE_get_ndm_reset_req_get, WILL_FIRE_hart0_client_run_halt_request_get, WILL_FIRE_hart0_client_run_halt_response_put, WILL_FIRE_hart0_get_other_req_get, - WILL_FIRE_hart0_get_reset_req_get, + WILL_FIRE_hart0_reset_client_request_get, + WILL_FIRE_hart0_reset_client_response_put, + WILL_FIRE_ndm_reset_client_request_get, + WILL_FIRE_ndm_reset_client_response_put, WILL_FIRE_reset, WILL_FIRE_write; // inputs to muxes for submodule ports wire MUX_rg_dmstatus_allresumeack$write_1__SEL_2, MUX_rg_dmstatus_allresumeack$write_1__SEL_3, - MUX_rg_hart0_running$write_1__SEL_3, + MUX_rg_dmstatus_allunavail$write_1__SEL_3, + MUX_rg_hart0_hasreset$write_1__SEL_3, MUX_rg_verbosity$write_1__SEL_2; + // declarations used by system tasks + // synopsys translate_off + reg [31 : 0] v__h2225; + reg [31 : 0] v__h2768; + reg [31 : 0] v__h2874; + reg [31 : 0] v__h2989; + reg [31 : 0] v__h3109; + reg [31 : 0] v__h3149; + reg [31 : 0] v__h2186; + reg [31 : 0] v__h1178; + reg [31 : 0] v__h1172; + reg [31 : 0] v__h2180; + reg [31 : 0] v__h2219; + reg [31 : 0] v__h2762; + reg [31 : 0] v__h2868; + reg [31 : 0] v__h2983; + reg [31 : 0] v__h3103; + reg [31 : 0] v__h3143; + // synopsys translate_on + // remaining internal signals - wire [31 : 0] haltsum__h505, - virt_rg_dmcontrol__h670, - virt_rg_dmstatus__h543; - wire write_dm_addr_EQ_0x10_6_AND_write_dm_word_BIT__ETC___d72, - write_dm_addr_EQ_0x10_6_AND_write_dm_word_BIT__ETC___d77; + wire [31 : 0] haltsum__h699, + virt_rg_dmcontrol__h930, + virt_rg_dmstatus__h805; + wire NOT_rg_dmcontrol_ndmreset_6_0_OR_write_dm_word_ETC___d105, + NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d114, + NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d123, + NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d64, + NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d72, + NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d83, + NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d93, + write_dm_addr_EQ_0x10_9_AND_write_dm_word_BIT__ETC___d53, + write_dm_word_BIT_0_3_AND_NOT_rg_dmstatus_allu_ETC___d57; // value method dmactive assign dmactive = rg_dmcontrol_dmactive ; @@ -265,12 +365,12 @@ module mkDM_Run_Control(CLK, // actionvalue method av_read always@(av_read_dm_addr or rg_verbosity or - virt_rg_dmcontrol__h670 or virt_rg_dmstatus__h543 or haltsum__h505) + virt_rg_dmcontrol__h930 or virt_rg_dmstatus__h805 or haltsum__h699) begin case (av_read_dm_addr) - 7'h10: av_read = virt_rg_dmcontrol__h670; - 7'h11: av_read = virt_rg_dmstatus__h543; - 7'h13, 7'h40: av_read = haltsum__h505; + 7'h10: av_read = virt_rg_dmcontrol__h930; + 7'h11: av_read = virt_rg_dmstatus__h805; + 7'h13, 7'h40: av_read = haltsum__h699; default: av_read = { 28'd0, rg_verbosity }; endcase end @@ -280,19 +380,27 @@ module mkDM_Run_Control(CLK, // action method write assign RDY_write = - f_ndm_reset_reqs$FULL_N && f_hart0_reset_reqs$FULL_N && - f_hart0_run_halt_reqs$FULL_N && - f_hart0_other_reqs$FULL_N ; - assign CAN_FIRE_write = - f_ndm_reset_reqs$FULL_N && f_hart0_reset_reqs$FULL_N && - f_hart0_run_halt_reqs$FULL_N && + (rg_dmstatus_allunavail || + f_ndm_reset_reqs$FULL_N && f_hart0_reset_reqs$FULL_N && + f_hart0_run_halt_reqs$FULL_N) && f_hart0_other_reqs$FULL_N ; + assign CAN_FIRE_write = RDY_write ; assign WILL_FIRE_write = EN_write ; - // action method hart0_get_reset_req_get - assign RDY_hart0_get_reset_req_get = f_hart0_reset_reqs$EMPTY_N ; - assign CAN_FIRE_hart0_get_reset_req_get = f_hart0_reset_reqs$EMPTY_N ; - assign WILL_FIRE_hart0_get_reset_req_get = EN_hart0_get_reset_req_get ; + // actionvalue method hart0_reset_client_request_get + assign hart0_reset_client_request_get = f_hart0_reset_reqs$D_OUT ; + assign RDY_hart0_reset_client_request_get = f_hart0_reset_reqs$EMPTY_N ; + assign CAN_FIRE_hart0_reset_client_request_get = + f_hart0_reset_reqs$EMPTY_N ; + assign WILL_FIRE_hart0_reset_client_request_get = + EN_hart0_reset_client_request_get ; + + // action method hart0_reset_client_response_put + assign RDY_hart0_reset_client_response_put = f_hart0_reset_rsps$FULL_N ; + assign CAN_FIRE_hart0_reset_client_response_put = + f_hart0_reset_rsps$FULL_N ; + assign WILL_FIRE_hart0_reset_client_response_put = + EN_hart0_reset_client_response_put ; // actionvalue method hart0_client_run_halt_request_get assign hart0_client_run_halt_request_get = f_hart0_run_halt_reqs$D_OUT ; @@ -317,10 +425,18 @@ module mkDM_Run_Control(CLK, assign CAN_FIRE_hart0_get_other_req_get = f_hart0_other_reqs$EMPTY_N ; assign WILL_FIRE_hart0_get_other_req_get = EN_hart0_get_other_req_get ; - // action method get_ndm_reset_req_get - assign RDY_get_ndm_reset_req_get = f_ndm_reset_reqs$EMPTY_N ; - assign CAN_FIRE_get_ndm_reset_req_get = f_ndm_reset_reqs$EMPTY_N ; - assign WILL_FIRE_get_ndm_reset_req_get = EN_get_ndm_reset_req_get ; + // actionvalue method ndm_reset_client_request_get + assign ndm_reset_client_request_get = f_ndm_reset_reqs$D_OUT ; + assign RDY_ndm_reset_client_request_get = f_ndm_reset_reqs$EMPTY_N ; + assign CAN_FIRE_ndm_reset_client_request_get = f_ndm_reset_reqs$EMPTY_N ; + assign WILL_FIRE_ndm_reset_client_request_get = + EN_ndm_reset_client_request_get ; + + // action method ndm_reset_client_response_put + assign RDY_ndm_reset_client_response_put = f_ndm_reset_rsps$FULL_N ; + assign CAN_FIRE_ndm_reset_client_response_put = f_ndm_reset_rsps$FULL_N ; + assign WILL_FIRE_ndm_reset_client_response_put = + EN_ndm_reset_client_response_put ; // submodule f_hart0_other_reqs FIFO2 #(.width(32'd4), .guarded(32'd1)) f_hart0_other_reqs(.RST(RST_N), @@ -334,13 +450,26 @@ module mkDM_Run_Control(CLK, .EMPTY_N(f_hart0_other_reqs$EMPTY_N)); // submodule f_hart0_reset_reqs - FIFO20 #(.guarded(32'd1)) f_hart0_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(f_hart0_reset_reqs$ENQ), - .DEQ(f_hart0_reset_reqs$DEQ), - .CLR(f_hart0_reset_reqs$CLR), - .FULL_N(f_hart0_reset_reqs$FULL_N), - .EMPTY_N(f_hart0_reset_reqs$EMPTY_N)); + FIFO2 #(.width(32'd1), .guarded(32'd1)) f_hart0_reset_reqs(.RST(RST_N), + .CLK(CLK), + .D_IN(f_hart0_reset_reqs$D_IN), + .ENQ(f_hart0_reset_reqs$ENQ), + .DEQ(f_hart0_reset_reqs$DEQ), + .CLR(f_hart0_reset_reqs$CLR), + .D_OUT(f_hart0_reset_reqs$D_OUT), + .FULL_N(f_hart0_reset_reqs$FULL_N), + .EMPTY_N(f_hart0_reset_reqs$EMPTY_N)); + + // submodule f_hart0_reset_rsps + FIFO2 #(.width(32'd1), .guarded(32'd1)) f_hart0_reset_rsps(.RST(RST_N), + .CLK(CLK), + .D_IN(f_hart0_reset_rsps$D_IN), + .ENQ(f_hart0_reset_rsps$ENQ), + .DEQ(f_hart0_reset_rsps$DEQ), + .CLR(f_hart0_reset_rsps$CLR), + .D_OUT(f_hart0_reset_rsps$D_OUT), + .FULL_N(f_hart0_reset_rsps$FULL_N), + .EMPTY_N(f_hart0_reset_rsps$EMPTY_N)); // submodule f_hart0_run_halt_reqs FIFO2 #(.width(32'd1), .guarded(32'd1)) f_hart0_run_halt_reqs(.RST(RST_N), @@ -365,27 +494,52 @@ module mkDM_Run_Control(CLK, .EMPTY_N(f_hart0_run_halt_rsps$EMPTY_N)); // submodule f_ndm_reset_reqs - FIFO20 #(.guarded(32'd1)) f_ndm_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(f_ndm_reset_reqs$ENQ), - .DEQ(f_ndm_reset_reqs$DEQ), - .CLR(f_ndm_reset_reqs$CLR), - .FULL_N(f_ndm_reset_reqs$FULL_N), - .EMPTY_N(f_ndm_reset_reqs$EMPTY_N)); + FIFO2 #(.width(32'd1), .guarded(32'd1)) f_ndm_reset_reqs(.RST(RST_N), + .CLK(CLK), + .D_IN(f_ndm_reset_reqs$D_IN), + .ENQ(f_ndm_reset_reqs$ENQ), + .DEQ(f_ndm_reset_reqs$DEQ), + .CLR(f_ndm_reset_reqs$CLR), + .D_OUT(f_ndm_reset_reqs$D_OUT), + .FULL_N(f_ndm_reset_reqs$FULL_N), + .EMPTY_N(f_ndm_reset_reqs$EMPTY_N)); + + // submodule f_ndm_reset_rsps + FIFO2 #(.width(32'd1), .guarded(32'd1)) f_ndm_reset_rsps(.RST(RST_N), + .CLK(CLK), + .D_IN(f_ndm_reset_rsps$D_IN), + .ENQ(f_ndm_reset_rsps$ENQ), + .DEQ(f_ndm_reset_rsps$DEQ), + .CLR(f_ndm_reset_rsps$CLR), + .D_OUT(f_ndm_reset_rsps$D_OUT), + .FULL_N(f_ndm_reset_rsps$FULL_N), + .EMPTY_N(f_ndm_reset_rsps$EMPTY_N)); + + // rule RL_rl_hart0_reset_rsp + assign CAN_FIRE_RL_rl_hart0_reset_rsp = f_hart0_reset_rsps$EMPTY_N ; + assign WILL_FIRE_RL_rl_hart0_reset_rsp = f_hart0_reset_rsps$EMPTY_N ; + + // rule RL_rl_ndm_reset_rsp + assign CAN_FIRE_RL_rl_ndm_reset_rsp = f_ndm_reset_rsps$EMPTY_N ; + assign WILL_FIRE_RL_rl_ndm_reset_rsp = f_ndm_reset_rsps$EMPTY_N ; // rule RL_rl_hart0_run_rsp - assign CAN_FIRE_RL_rl_hart0_run_rsp = f_hart0_run_halt_rsps$EMPTY_N ; - assign WILL_FIRE_RL_rl_hart0_run_rsp = f_hart0_run_halt_rsps$EMPTY_N ; + assign CAN_FIRE_RL_rl_hart0_run_rsp = + f_hart0_run_halt_rsps$EMPTY_N && !f_ndm_reset_rsps$EMPTY_N ; + assign WILL_FIRE_RL_rl_hart0_run_rsp = CAN_FIRE_RL_rl_hart0_run_rsp ; // inputs to muxes for submodule ports assign MUX_rg_dmstatus_allresumeack$write_1__SEL_2 = - f_hart0_run_halt_rsps$EMPTY_N && f_hart0_run_halt_rsps$D_OUT ; + WILL_FIRE_RL_rl_hart0_run_rsp && f_hart0_run_halt_rsps$D_OUT ; assign MUX_rg_dmstatus_allresumeack$write_1__SEL_3 = - EN_write && - write_dm_addr_EQ_0x10_6_AND_write_dm_word_BIT__ETC___d77 ; - assign MUX_rg_hart0_running$write_1__SEL_3 = EN_write && write_dm_addr == 7'h10 && write_dm_word[0] && - (write_dm_word[1] || write_dm_word[29]) ; + NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d114 ; + assign MUX_rg_dmstatus_allunavail$write_1__SEL_3 = + EN_write && + write_dm_addr_EQ_0x10_9_AND_write_dm_word_BIT__ETC___d53 ; + assign MUX_rg_hart0_hasreset$write_1__SEL_3 = + EN_write && write_dm_addr == 7'h10 && write_dm_word[0] && + NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d64 ; assign MUX_rg_verbosity$write_1__SEL_2 = EN_write && write_dm_addr == 7'h60 ; @@ -422,26 +576,47 @@ module mkDM_Run_Control(CLK, default: rg_dmstatus_allresumeack$D_IN = 1'b0 /* unspecified value */ ; endcase assign rg_dmstatus_allresumeack$EN = - f_hart0_run_halt_rsps$EMPTY_N && f_hart0_run_halt_rsps$D_OUT || + WILL_FIRE_RL_rl_hart0_run_rsp && f_hart0_run_halt_rsps$D_OUT || + EN_write && write_dm_addr == 7'h10 && write_dm_word[0] && + NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d114 || + EN_reset ; + + // register rg_dmstatus_allunavail + assign rg_dmstatus_allunavail$D_IN = + !EN_reset && !f_ndm_reset_rsps$EMPTY_N ; + assign rg_dmstatus_allunavail$EN = EN_write && - write_dm_addr_EQ_0x10_6_AND_write_dm_word_BIT__ETC___d77 || + write_dm_addr_EQ_0x10_9_AND_write_dm_word_BIT__ETC___d53 || + f_ndm_reset_rsps$EMPTY_N || + EN_reset ; + + // register rg_hart0_hasreset + assign rg_hart0_hasreset$D_IN = !EN_reset && !f_hart0_reset_rsps$EMPTY_N ; + assign rg_hart0_hasreset$EN = + EN_write && write_dm_addr == 7'h10 && write_dm_word[0] && + NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d64 || + f_hart0_reset_rsps$EMPTY_N || EN_reset ; // register rg_hart0_running always@(EN_reset or - f_hart0_run_halt_rsps$EMPTY_N or - f_hart0_run_halt_rsps$D_OUT or MUX_rg_hart0_running$write_1__SEL_3) + WILL_FIRE_RL_rl_hart0_run_rsp or + f_hart0_run_halt_rsps$D_OUT or + f_ndm_reset_rsps$EMPTY_N or + f_ndm_reset_rsps$D_OUT or + f_hart0_reset_rsps$EMPTY_N or f_hart0_reset_rsps$D_OUT) case (1'b1) EN_reset: rg_hart0_running$D_IN = 1'd1; - f_hart0_run_halt_rsps$EMPTY_N: + WILL_FIRE_RL_rl_hart0_run_rsp: rg_hart0_running$D_IN = f_hart0_run_halt_rsps$D_OUT; - MUX_rg_hart0_running$write_1__SEL_3: rg_hart0_running$D_IN = 1'd1; + f_ndm_reset_rsps$EMPTY_N: rg_hart0_running$D_IN = f_ndm_reset_rsps$D_OUT; + f_hart0_reset_rsps$EMPTY_N: + rg_hart0_running$D_IN = f_hart0_reset_rsps$D_OUT; default: rg_hart0_running$D_IN = 1'b0 /* unspecified value */ ; endcase assign rg_hart0_running$EN = - EN_write && write_dm_addr == 7'h10 && write_dm_word[0] && - (write_dm_word[1] || write_dm_word[29]) || - f_hart0_run_halt_rsps$EMPTY_N || + f_ndm_reset_rsps$EMPTY_N || WILL_FIRE_RL_rl_hart0_run_rsp || + f_hart0_reset_rsps$EMPTY_N || EN_reset ; // register rg_verbosity @@ -455,66 +630,123 @@ module mkDM_Run_Control(CLK, assign f_hart0_other_reqs$CLR = 1'b0 ; // submodule f_hart0_reset_reqs - assign f_hart0_reset_reqs$ENQ = - EN_write && write_dm_addr == 7'h10 && write_dm_word[0] && - !write_dm_word[1] && - write_dm_word[29] ; - assign f_hart0_reset_reqs$DEQ = EN_hart0_get_reset_req_get ; + assign f_hart0_reset_reqs$D_IN = !write_dm_word[31] ; + assign f_hart0_reset_reqs$ENQ = MUX_rg_hart0_hasreset$write_1__SEL_3 ; + assign f_hart0_reset_reqs$DEQ = EN_hart0_reset_client_request_get ; assign f_hart0_reset_reqs$CLR = EN_reset ; + // submodule f_hart0_reset_rsps + assign f_hart0_reset_rsps$D_IN = hart0_reset_client_response_put ; + assign f_hart0_reset_rsps$ENQ = EN_hart0_reset_client_response_put ; + assign f_hart0_reset_rsps$DEQ = f_hart0_reset_rsps$EMPTY_N ; + assign f_hart0_reset_rsps$CLR = EN_reset ; + // submodule f_hart0_run_halt_reqs assign f_hart0_run_halt_reqs$D_IN = write_dm_word[30] && !rg_hart0_running ; assign f_hart0_run_halt_reqs$ENQ = - EN_write && - write_dm_addr_EQ_0x10_6_AND_write_dm_word_BIT__ETC___d72 ; + EN_write && write_dm_addr == 7'h10 && write_dm_word[0] && + !rg_dmstatus_allunavail && + (rg_dmcontrol_ndmreset || !write_dm_word[1]) && + NOT_rg_dmcontrol_ndmreset_6_0_OR_write_dm_word_ETC___d105 ; assign f_hart0_run_halt_reqs$DEQ = EN_hart0_client_run_halt_request_get ; assign f_hart0_run_halt_reqs$CLR = EN_reset ; // submodule f_hart0_run_halt_rsps assign f_hart0_run_halt_rsps$D_IN = hart0_client_run_halt_response_put ; assign f_hart0_run_halt_rsps$ENQ = EN_hart0_client_run_halt_response_put ; - assign f_hart0_run_halt_rsps$DEQ = f_hart0_run_halt_rsps$EMPTY_N ; + assign f_hart0_run_halt_rsps$DEQ = CAN_FIRE_RL_rl_hart0_run_rsp ; assign f_hart0_run_halt_rsps$CLR = EN_reset ; // submodule f_ndm_reset_reqs - assign f_ndm_reset_reqs$ENQ = - EN_write && write_dm_addr == 7'h10 && write_dm_word[0] && - write_dm_word[1] ; - assign f_ndm_reset_reqs$DEQ = EN_get_ndm_reset_req_get ; + assign f_ndm_reset_reqs$D_IN = !write_dm_word[31] ; + assign f_ndm_reset_reqs$ENQ = MUX_rg_dmstatus_allunavail$write_1__SEL_3 ; + assign f_ndm_reset_reqs$DEQ = EN_ndm_reset_client_request_get ; assign f_ndm_reset_reqs$CLR = EN_reset ; + // submodule f_ndm_reset_rsps + assign f_ndm_reset_rsps$D_IN = ndm_reset_client_response_put ; + assign f_ndm_reset_rsps$ENQ = EN_ndm_reset_client_response_put ; + assign f_ndm_reset_rsps$DEQ = f_ndm_reset_rsps$EMPTY_N ; + assign f_ndm_reset_rsps$CLR = EN_reset ; + // remaining internal signals - assign haltsum__h505 = { 31'h0, !rg_hart0_running } ; - assign virt_rg_dmcontrol__h670 = + assign NOT_rg_dmcontrol_ndmreset_6_0_OR_write_dm_word_ETC___d105 = + (!rg_dmcontrol_ndmreset || write_dm_word[1]) && + !write_dm_word[29] && + (!write_dm_word[31] || !write_dm_word[30]) && + (write_dm_word[30] && !rg_hart0_running || + write_dm_word[31] && rg_hart0_running) ; + assign NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d114 = + !rg_dmstatus_allunavail && + (rg_dmcontrol_ndmreset || !write_dm_word[1]) && + (!rg_dmcontrol_ndmreset || write_dm_word[1]) && + !write_dm_word[29] && + !write_dm_word[31] && + write_dm_word[30] && + !rg_hart0_running ; + assign NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d123 = + !rg_dmstatus_allunavail && + (rg_dmcontrol_ndmreset || !write_dm_word[1]) && + (!rg_dmcontrol_ndmreset || write_dm_word[1]) && + !write_dm_word[29] && + !write_dm_word[30] && + write_dm_word[31] && + rg_hart0_running ; + assign NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d64 = + !rg_dmstatus_allunavail && + (rg_dmcontrol_ndmreset || !write_dm_word[1]) && + (!rg_dmcontrol_ndmreset || write_dm_word[1]) && + write_dm_word[29] ; + assign NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d72 = + !rg_dmstatus_allunavail && + (rg_dmcontrol_ndmreset || !write_dm_word[1]) && + (!rg_dmcontrol_ndmreset || write_dm_word[1]) && + !write_dm_word[29] && + write_dm_word[26] ; + assign NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d83 = + !rg_dmstatus_allunavail && + (rg_dmcontrol_ndmreset || !write_dm_word[1]) && + (!rg_dmcontrol_ndmreset || write_dm_word[1]) && + !write_dm_word[29] && + write_dm_word[25:16] != 10'd0 ; + assign NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d93 = + !rg_dmstatus_allunavail && + (rg_dmcontrol_ndmreset || !write_dm_word[1]) && + (!rg_dmcontrol_ndmreset || write_dm_word[1]) && + !write_dm_word[29] && + write_dm_word[31] && + write_dm_word[30] ; + assign haltsum__h699 = { 31'h0, !rg_hart0_running } ; + assign virt_rg_dmcontrol__h930 = { 2'b0, rg_dmcontrol_hartreset, 27'd0, rg_dmcontrol_ndmreset, rg_dmcontrol_dmactive } ; - assign virt_rg_dmstatus__h543 = - { 14'b0, + assign virt_rg_dmstatus__h805 = + { 12'd0, + rg_hart0_hasreset, + rg_hart0_hasreset, rg_dmstatus_allresumeack, rg_dmstatus_allresumeack, - 4'd0, + 2'd0, + rg_dmstatus_allunavail, + rg_dmstatus_allunavail, rg_hart0_running, rg_hart0_running, !rg_hart0_running, !rg_hart0_running, 8'd130 } ; - assign write_dm_addr_EQ_0x10_6_AND_write_dm_word_BIT__ETC___d72 = + assign write_dm_addr_EQ_0x10_9_AND_write_dm_word_BIT__ETC___d53 = write_dm_addr == 7'h10 && write_dm_word[0] && + !rg_dmstatus_allunavail && + rg_dmcontrol_ndmreset && + !write_dm_word[1] ; + assign write_dm_word_BIT_0_3_AND_NOT_rg_dmstatus_allu_ETC___d57 = + write_dm_word[0] && !rg_dmstatus_allunavail && + rg_dmcontrol_ndmreset && !write_dm_word[1] && - !write_dm_word[29] && - (!write_dm_word[31] || !write_dm_word[30]) && - (write_dm_word[30] && !rg_hart0_running || - write_dm_word[31] && rg_hart0_running) ; - assign write_dm_addr_EQ_0x10_6_AND_write_dm_word_BIT__ETC___d77 = - write_dm_addr == 7'h10 && write_dm_word[0] && - !write_dm_word[1] && - !write_dm_word[29] && - !write_dm_word[31] && - write_dm_word[30] && - !rg_hart0_running ; + write_dm_word[29] ; // handling of inlined registers @@ -523,12 +755,16 @@ module mkDM_Run_Control(CLK, if (RST_N == `BSV_RESET_VALUE) begin rg_dmcontrol_dmactive <= `BSV_ASSIGNMENT_DELAY 1'd0; + rg_dmstatus_allunavail <= `BSV_ASSIGNMENT_DELAY 1'd0; end else begin if (rg_dmcontrol_dmactive$EN) rg_dmcontrol_dmactive <= `BSV_ASSIGNMENT_DELAY rg_dmcontrol_dmactive$D_IN; + if (rg_dmstatus_allunavail$EN) + rg_dmstatus_allunavail <= `BSV_ASSIGNMENT_DELAY + rg_dmstatus_allunavail$D_IN; end if (rg_dmcontrol_haltreq$EN) rg_dmcontrol_haltreq <= `BSV_ASSIGNMENT_DELAY rg_dmcontrol_haltreq$D_IN; @@ -541,6 +777,8 @@ module mkDM_Run_Control(CLK, if (rg_dmstatus_allresumeack$EN) rg_dmstatus_allresumeack <= `BSV_ASSIGNMENT_DELAY rg_dmstatus_allresumeack$D_IN; + if (rg_hart0_hasreset$EN) + rg_hart0_hasreset <= `BSV_ASSIGNMENT_DELAY rg_hart0_hasreset$D_IN; if (rg_hart0_running$EN) rg_hart0_running <= `BSV_ASSIGNMENT_DELAY rg_hart0_running$D_IN; if (rg_verbosity$EN) @@ -557,6 +795,8 @@ module mkDM_Run_Control(CLK, rg_dmcontrol_hartreset = 1'h0; rg_dmcontrol_ndmreset = 1'h0; rg_dmstatus_allresumeack = 1'h0; + rg_dmstatus_allunavail = 1'h0; + rg_hart0_hasreset = 1'h0; rg_hart0_running = 1'h0; rg_verbosity = 4'hA; end @@ -571,75 +811,117 @@ module mkDM_Run_Control(CLK, #0; if (RST_N != `BSV_RESET_VALUE) if (EN_write && write_dm_addr == 7'h10 && write_dm_word[0] && - write_dm_word[1]) - $display("DM_Run_Control.write: dmcontrol 0x%08h: ndmreset=1: resetting platform", + rg_dmstatus_allunavail) + begin + v__h2225 = $stime; + #0; + end + v__h2219 = v__h2225 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (EN_write && write_dm_addr == 7'h10 && write_dm_word[0] && + rg_dmstatus_allunavail) + $display("%0d: %m.dmcontrol_write 0x%0h: ndm reset in progress; ignoring this write", + v__h2219, write_dm_word); if (RST_N != `BSV_RESET_VALUE) - if (EN_write && write_dm_addr == 7'h10 && write_dm_word[0] && - write_dm_word[1] && - write_dm_word[29]) - $display("DM_Run_Control.write: WARNING: in word written to dmcontrol (0x%08h):", - write_dm_word); + if (EN_write && write_dm_addr == 7'h10 && + write_dm_word_BIT_0_3_AND_NOT_rg_dmstatus_allu_ETC___d57) + $display(" WARNING: %m.dmcontrol_write 0x%08h:", write_dm_word); if (RST_N != `BSV_RESET_VALUE) - if (EN_write && write_dm_addr == 7'h10 && write_dm_word[0] && - write_dm_word[1] && - write_dm_word[29]) - $display(" Both ndmreset (bit 1) and hartreset (bit 29) are asserted"); + if (EN_write && write_dm_addr == 7'h10 && + write_dm_word_BIT_0_3_AND_NOT_rg_dmstatus_allu_ETC___d57) + $display(" Both ndmreset [1] and hartreset [29] are asserted"); if (RST_N != `BSV_RESET_VALUE) - if (EN_write && write_dm_addr == 7'h10 && write_dm_word[0] && - write_dm_word[1] && - write_dm_word[29]) + if (EN_write && write_dm_addr == 7'h10 && + write_dm_word_BIT_0_3_AND_NOT_rg_dmstatus_allu_ETC___d57) $display(" ndmreset has priority; ignoring hartreset"); if (RST_N != `BSV_RESET_VALUE) if (EN_write && write_dm_addr == 7'h10 && write_dm_word[0] && - !write_dm_word[1] && - !write_dm_word[29] && - write_dm_word[26]) - $display("DM_Run_Control.write: ERROR: dmcontrol 0x%08h: 'hasel' is not supported", + NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d72) + begin + v__h2768 = $stime; + #0; + end + v__h2762 = v__h2768 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (EN_write && write_dm_addr == 7'h10 && write_dm_word[0] && + NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d72) + $display("%0d:ERROR: %m.dmcontrol_write 0x%08h: hasel is not supported", + v__h2762, write_dm_word); if (RST_N != `BSV_RESET_VALUE) if (EN_write && write_dm_addr == 7'h10 && write_dm_word[0] && - !write_dm_word[1] && - !write_dm_word[29] && - write_dm_word[25:16] != 10'd0) - $display("DM_Run_Control.write: ERROR: dmcontrol 0x%08h: hartsel 0x%0h not supported", + NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d83) + begin + v__h2874 = $stime; + #0; + end + v__h2868 = v__h2874 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (EN_write && write_dm_addr == 7'h10 && write_dm_word[0] && + NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d83) + $display("%0d:ERROR: %m.dmcontrol_write 0x%08h: hartsel 0x%0h not supported", + v__h2868, write_dm_word, write_dm_word[25:16]); if (RST_N != `BSV_RESET_VALUE) if (EN_write && write_dm_addr == 7'h10 && write_dm_word[0] && - !write_dm_word[1] && - !write_dm_word[29] && - write_dm_word[31] && - write_dm_word[30]) - $display("DM_Run_Control.write: ERROR: dmcontrol 0x%08h: haltreq=1 and resumereq=1", + NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d93) + begin + v__h2989 = $stime; + #0; + end + v__h2983 = v__h2989 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (EN_write && write_dm_addr == 7'h10 && write_dm_word[0] && + NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d93) + $display("%0d:ERROR: %m.dmcontrol_write 0x%08h: haltreq=1 and resumereq=1", + v__h2983, write_dm_word); if (RST_N != `BSV_RESET_VALUE) if (EN_write && write_dm_addr == 7'h10 && write_dm_word[0] && - !write_dm_word[1] && - !write_dm_word[29] && - write_dm_word[31] && - write_dm_word[30]) + NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d93) $display(" This behavior is 'undefined' in the spec; ignoring"); if (RST_N != `BSV_RESET_VALUE) - if (EN_write && - write_dm_addr_EQ_0x10_6_AND_write_dm_word_BIT__ETC___d77) - $display("DM_Run_Control.write: hart0 resume request"); + if (EN_write && write_dm_addr == 7'h10 && write_dm_word[0] && + NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d114) + begin + v__h3109 = $stime; + #0; + end + v__h3103 = v__h3109 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_write && write_dm_addr == 7'h10 && write_dm_word[0] && - !write_dm_word[1] && - !write_dm_word[29] && - !write_dm_word[30] && - write_dm_word[31] && - rg_hart0_running) - $display("DM_Run_Control.write: hart0 halt request"); + NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d114) + $display("%0d: %m.dmcontrol_write: hart0 resume request", v__h3103); + if (RST_N != `BSV_RESET_VALUE) + if (EN_write && write_dm_addr == 7'h10 && write_dm_word[0] && + NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d123) + begin + v__h3149 = $stime; + #0; + end + v__h3143 = v__h3149 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (EN_write && write_dm_addr == 7'h10 && write_dm_word[0] && + NOT_rg_dmstatus_allunavail_2_8_AND_rg_dmcontro_ETC___d123) + $display("%0d: %m.dmcontrol_write: hart0 halt request", v__h3143); if (RST_N != `BSV_RESET_VALUE) if (EN_write && write_dm_addr == 7'h10 && !write_dm_word[0]) - $display("DM_Run_Control.write: dmcontrol 0x%08h (dmactive=0): resetting Debug Module", + begin + v__h2186 = $stime; + #0; + end + v__h2180 = v__h2186 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (EN_write && write_dm_addr == 7'h10 && !write_dm_word[0]) + $display("%0d: %m.dmcontrol_write 0x%08h (dmactive=0): resetting Debug Module", + v__h2180, write_dm_word); if (RST_N != `BSV_RESET_VALUE) if (EN_write && write_dm_addr == 7'h10 && !write_dm_word[0] && write_dm_word[1]) - $display("DM_Run_Control.write: WARNING: in word written to dmcontrol (0x%08h):", + $display(" WARNING: DM_Run_Control: dmcontrol_write 0x%08h:", write_dm_word); if (RST_N != `BSV_RESET_VALUE) if (EN_write && write_dm_addr == 7'h10 && !write_dm_word[0] && @@ -652,7 +934,7 @@ module mkDM_Run_Control(CLK, if (RST_N != `BSV_RESET_VALUE) if (EN_write && write_dm_addr == 7'h10 && !write_dm_word[0] && write_dm_word[29]) - $display("DM_Run_Control.write: WARNING: in word written to dmcontrol (0x%08h):", + $display(" WARNING: DM_Run_Control: dmcontrol_write 0x%08h:", write_dm_word); if (RST_N != `BSV_RESET_VALUE) if (EN_write && write_dm_addr == 7'h10 && !write_dm_word[0] && @@ -663,11 +945,21 @@ module mkDM_Run_Control(CLK, write_dm_word[29]) $display(" dmactive has priority; ignoring hartreset"); if (RST_N != `BSV_RESET_VALUE) - if (f_hart0_run_halt_rsps$EMPTY_N && f_hart0_run_halt_rsps$D_OUT) - $display("DM_Run_Control: hart0 running"); + if (f_ndm_reset_rsps$EMPTY_N) + begin + v__h1178 = $stime; + #0; + end + v__h1172 = v__h1178 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (f_hart0_run_halt_rsps$EMPTY_N && !f_hart0_run_halt_rsps$D_OUT) - $display("DM_Run_Control: hart0 halted"); + if (f_ndm_reset_rsps$EMPTY_N) + $write("%0d: %m.rl_ndm_reset_rsp: hart running = ", v__h1172); + if (RST_N != `BSV_RESET_VALUE) + if (f_ndm_reset_rsps$EMPTY_N && f_ndm_reset_rsps$D_OUT) $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (f_ndm_reset_rsps$EMPTY_N && !f_ndm_reset_rsps$D_OUT) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) if (f_ndm_reset_rsps$EMPTY_N) $write("\n"); end // synopsys translate_on endmodule // mkDM_Run_Control diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkDM_System_Bus.v b/src_SSITH_P3_sim/Verilog_RTL/mkDM_System_Bus.v index 8a04bd0..7a1ddbd 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkDM_System_Bus.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkDM_System_Bus.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // @@ -10,7 +10,7 @@ // av_read O 32 // RDY_av_read O 1 // RDY_write O 1 -// master_awvalid O 1 +// master_awvalid O 1 reg // master_awid O 4 reg // master_awaddr O 64 reg // master_awlen O 8 reg @@ -21,13 +21,12 @@ // master_awprot O 3 reg // master_awqos O 4 reg // master_awregion O 4 reg -// master_wvalid O 1 -// master_wid O 4 reg +// master_wvalid O 1 reg // master_wdata O 64 reg // master_wstrb O 8 reg // master_wlast O 1 reg -// master_bready O 1 const -// master_arvalid O 1 +// master_bready O 1 reg +// master_arvalid O 1 reg // master_arid O 4 reg // master_araddr O 64 reg // master_arlen O 8 reg @@ -38,7 +37,7 @@ // master_arprot O 3 reg // master_arqos O 4 reg // master_arregion O 4 reg -// master_rready O 1 +// master_rready O 1 reg // CLK I 1 clock // RST_N I 1 reset // av_read_dm_addr I 7 @@ -60,9 +59,7 @@ // EN_av_read I 1 // // Combinational paths from inputs to outputs: -// (master_awready, master_wready, master_arready) -> RDY_write -// master_arready -> RDY_av_read -// (master_arready, av_read_dm_addr) -> av_read +// av_read_dm_addr -> av_read // // @@ -121,8 +118,6 @@ module mkDM_System_Bus(CLK, master_wvalid, - master_wid, - master_wdata, master_wstrb, @@ -228,9 +223,6 @@ module mkDM_System_Bus(CLK, // value method master_m_wvalid output master_wvalid; - // value method master_m_wid - output [3 : 0] master_wid; - // value method master_m_wdata output [63 : 0] master_wdata; @@ -312,8 +304,7 @@ module mkDM_System_Bus(CLK, master_awcache, master_awid, master_awqos, - master_awregion, - master_wid; + master_awregion; wire [2 : 0] master_arprot, master_arsize, master_awprot, master_awsize; wire [1 : 0] master_arburst, master_awburst; wire RDY_av_read, @@ -328,66 +319,6 @@ module mkDM_System_Bus(CLK, master_wlast, master_wvalid; - // inlined wires - wire master_xactor_crg_rd_addr_full$EN_port1__write, - master_xactor_crg_rd_addr_full$EN_port2__write, - master_xactor_crg_rd_addr_full$port2__read, - master_xactor_crg_rd_addr_full$port3__read, - master_xactor_crg_rd_data_full$EN_port2__write, - master_xactor_crg_rd_data_full$port2__read, - master_xactor_crg_rd_data_full$port3__read, - master_xactor_crg_wr_addr_full$EN_port1__write, - master_xactor_crg_wr_addr_full$port2__read, - master_xactor_crg_wr_addr_full$port3__read, - master_xactor_crg_wr_data_full$EN_port1__write, - master_xactor_crg_wr_data_full$port2__read, - master_xactor_crg_wr_data_full$port3__read; - - // register master_xactor_crg_rd_addr_full - reg master_xactor_crg_rd_addr_full; - wire master_xactor_crg_rd_addr_full$D_IN, master_xactor_crg_rd_addr_full$EN; - - // register master_xactor_crg_rd_data_full - reg master_xactor_crg_rd_data_full; - wire master_xactor_crg_rd_data_full$D_IN, master_xactor_crg_rd_data_full$EN; - - // register master_xactor_crg_wr_addr_full - reg master_xactor_crg_wr_addr_full; - wire master_xactor_crg_wr_addr_full$D_IN, master_xactor_crg_wr_addr_full$EN; - - // register master_xactor_crg_wr_data_full - reg master_xactor_crg_wr_data_full; - wire master_xactor_crg_wr_data_full$D_IN, master_xactor_crg_wr_data_full$EN; - - // register master_xactor_crg_wr_resp_full - reg master_xactor_crg_wr_resp_full; - wire master_xactor_crg_wr_resp_full$D_IN, master_xactor_crg_wr_resp_full$EN; - - // register master_xactor_rg_rd_addr - reg [96 : 0] master_xactor_rg_rd_addr; - wire [96 : 0] master_xactor_rg_rd_addr$D_IN; - wire master_xactor_rg_rd_addr$EN; - - // register master_xactor_rg_rd_data - reg [70 : 0] master_xactor_rg_rd_data; - wire [70 : 0] master_xactor_rg_rd_data$D_IN; - wire master_xactor_rg_rd_data$EN; - - // register master_xactor_rg_wr_addr - reg [96 : 0] master_xactor_rg_wr_addr; - wire [96 : 0] master_xactor_rg_wr_addr$D_IN; - wire master_xactor_rg_wr_addr$EN; - - // register master_xactor_rg_wr_data - reg [76 : 0] master_xactor_rg_wr_data; - wire [76 : 0] master_xactor_rg_wr_data$D_IN; - wire master_xactor_rg_wr_data$EN; - - // register master_xactor_rg_wr_resp - reg [5 : 0] master_xactor_rg_wr_resp; - wire [5 : 0] master_xactor_rg_wr_resp$D_IN; - wire master_xactor_rg_wr_resp$EN; - // register rg_sb_state reg [1 : 0] rg_sb_state; wire [1 : 0] rg_sb_state$D_IN; @@ -440,6 +371,46 @@ module mkDM_System_Bus(CLK, reg [31 : 0] rg_sbdata0$D_IN; wire rg_sbdata0$EN; + // ports of submodule master_xactor_f_rd_addr + wire [96 : 0] master_xactor_f_rd_addr$D_IN, master_xactor_f_rd_addr$D_OUT; + wire master_xactor_f_rd_addr$CLR, + master_xactor_f_rd_addr$DEQ, + master_xactor_f_rd_addr$EMPTY_N, + master_xactor_f_rd_addr$ENQ, + master_xactor_f_rd_addr$FULL_N; + + // ports of submodule master_xactor_f_rd_data + wire [70 : 0] master_xactor_f_rd_data$D_IN, master_xactor_f_rd_data$D_OUT; + wire master_xactor_f_rd_data$CLR, + master_xactor_f_rd_data$DEQ, + master_xactor_f_rd_data$EMPTY_N, + master_xactor_f_rd_data$ENQ, + master_xactor_f_rd_data$FULL_N; + + // ports of submodule master_xactor_f_wr_addr + wire [96 : 0] master_xactor_f_wr_addr$D_IN, master_xactor_f_wr_addr$D_OUT; + wire master_xactor_f_wr_addr$CLR, + master_xactor_f_wr_addr$DEQ, + master_xactor_f_wr_addr$EMPTY_N, + master_xactor_f_wr_addr$ENQ, + master_xactor_f_wr_addr$FULL_N; + + // ports of submodule master_xactor_f_wr_data + wire [72 : 0] master_xactor_f_wr_data$D_IN, master_xactor_f_wr_data$D_OUT; + wire master_xactor_f_wr_data$CLR, + master_xactor_f_wr_data$DEQ, + master_xactor_f_wr_data$EMPTY_N, + master_xactor_f_wr_data$ENQ, + master_xactor_f_wr_data$FULL_N; + + // ports of submodule master_xactor_f_wr_resp + wire [5 : 0] master_xactor_f_wr_resp$D_IN, master_xactor_f_wr_resp$D_OUT; + wire master_xactor_f_wr_resp$CLR, + master_xactor_f_wr_resp$DEQ, + master_xactor_f_wr_resp$EMPTY_N, + master_xactor_f_wr_resp$ENQ, + master_xactor_f_wr_resp$FULL_N; + // rule scheduling signals wire CAN_FIRE_RL_rl_sb_read_finish, CAN_FIRE_RL_rl_sb_write_response, @@ -466,9 +437,9 @@ module mkDM_System_Bus(CLK, reg [31 : 0] MUX_rg_sbaddress0$write_1__VAL_2, MUX_rg_sbaddress1$write_1__VAL_2; reg [2 : 0] MUX_rg_sbcs_sberror$write_1__VAL_4; - wire [96 : 0] MUX_master_xactor_rg_rd_addr$write_1__VAL_1, - MUX_master_xactor_rg_rd_addr$write_1__VAL_2; - wire MUX_master_xactor_crg_rd_addr_full$port2__write_1__SEL_1, + wire [96 : 0] MUX_master_xactor_f_rd_addr$enq_1__VAL_1, + MUX_master_xactor_f_rd_addr$enq_1__VAL_2; + wire MUX_master_xactor_f_rd_addr$enq_1__SEL_1, MUX_rg_sbaddress0$write_1__SEL_2, MUX_rg_sbaddress0$write_1__SEL_3, MUX_rg_sbaddress1$write_1__SEL_2, @@ -485,45 +456,45 @@ module mkDM_System_Bus(CLK, IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d66, IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d103, IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d79, - wrd_wdata__h5118; - reg [7 : 0] wrd_wstrb__h5119; - reg [2 : 0] x__h3284, x__h4989; - wire [63 : 0] _theResult___fst__h5027, - addr64__h4331, - result__h1836, - result__h1866, - result__h1893, - result__h1920, - result__h1947, - result__h1974, - result__h2001, - result__h2028, - result__h2073, - result__h2100, - result__h2127, - result__h2154, - result__h2195, - result__h2222, + wrd_wdata__h4397; + reg [7 : 0] wrd_wstrb__h4398; + reg [2 : 0] x__h2654, x__h4302; + wire [63 : 0] _theResult___fst__h4340, + addr64__h3701, + result__h1250, + result__h1280, + result__h1307, + result__h1334, + result__h1361, + result__h1388, + result__h1415, + result__h1442, + result__h1487, + result__h1514, + result__h1541, + result__h1568, + result__h1609, + result__h1636, rg_sbaddress1_7_CONCAT_rg_sbaddress0_8_9_PLUS__ETC___d104, - rg_sbaddress1_7_CONCAT_write_dm_word_99_PLUS_I_ETC___d300, - sbaddress__h1228, - word64__h4971; - wire [31 : 0] IF_rg_sbcs_sbreadonaddr_24_THEN_IF_rg_sbcs_sba_ETC___d311, - IF_write_dm_addr_EQ_0x39_59_THEN_rg_sbaddress1_ETC___d302, - v__h2728, - v__h2862; - wire [7 : 0] strobe64__h5026, strobe64__h5029, strobe64__h5032; - wire [5 : 0] shift_bits__h4974; + rg_sbaddress1_7_CONCAT_write_dm_word_98_PLUS_I_ETC___d299, + sbaddress__h638, + word64__h4284; + wire [31 : 0] IF_rg_sbcs_sbreadonaddr_24_THEN_IF_rg_sbcs_sba_ETC___d310, + IF_write_dm_addr_EQ_0x39_58_THEN_rg_sbaddress1_ETC___d301, + v__h2132, + v__h2266; + wire [7 : 0] strobe64__h4339, strobe64__h4342, strobe64__h4345; + wire [5 : 0] shift_bits__h4287; wire rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d110, - rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d317, + rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d316, rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d95, - rg_sbcs_sberror_EQ_0_AND_rg_sbcs_sbreadonaddr__ETC___d292, - write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d257, - write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d266, - write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d272, - write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d274, - write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d279, - write_dm_addr_EQ_0x3C_62_AND_rg_sb_state_EQ_0__ETC___d327; + rg_sbcs_sberror_EQ_0_AND_rg_sbcs_sbreadonaddr__ETC___d291, + write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d256, + write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d265, + write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d271, + write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d273, + write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d278, + write_dm_addr_EQ_0x3C_61_AND_rg_sb_state_EQ_0__ETC___d326; // action method reset assign RDY_reset = 1'd1 ; @@ -532,13 +503,13 @@ module mkDM_System_Bus(CLK, // actionvalue method av_read always@(av_read_dm_addr or - v__h2728 or rg_sbaddress0 or rg_sbaddress1 or v__h2862) + v__h2132 or rg_sbaddress0 or rg_sbaddress1 or v__h2266) begin case (av_read_dm_addr) - 7'h38: av_read = v__h2728; + 7'h38: av_read = v__h2132; 7'h39: av_read = rg_sbaddress0; 7'h3A: av_read = rg_sbaddress1; - 7'h3C: av_read = v__h2862; + 7'h3C: av_read = v__h2266; default: av_read = 32'd0; endcase end @@ -546,7 +517,7 @@ module mkDM_System_Bus(CLK, rg_sb_state == 2'd0 && (rg_sbcs_sbbusyerror || rg_sbcs_sberror != 3'd0 || !rg_sbcs_sbreadondata || - !master_xactor_crg_rd_addr_full$port2__read) ; + master_xactor_f_rd_addr$FULL_N) ; assign CAN_FIRE_av_read = RDY_av_read ; assign WILL_FIRE_av_read = EN_av_read ; @@ -556,64 +527,61 @@ module mkDM_System_Bus(CLK, (rg_sb_state != 2'd0 || rg_sbcs_sbbusyerror || rg_sbcs_sberror != 3'd0 || !rg_sbcs_sbreadonaddr || - !master_xactor_crg_rd_addr_full$port2__read) && + master_xactor_f_rd_addr$FULL_N) && (rg_sb_state != 2'd0 || rg_sbcs_sbbusyerror || rg_sbcs_sberror != 3'd0 || - !master_xactor_crg_wr_addr_full$port2__read && - !master_xactor_crg_wr_data_full$port2__read) ; + master_xactor_f_wr_addr$FULL_N && + master_xactor_f_wr_data$FULL_N) ; assign WILL_FIRE_write = EN_write ; // value method master_m_awvalid - assign master_awvalid = master_xactor_crg_wr_addr_full ; + assign master_awvalid = master_xactor_f_wr_addr$EMPTY_N ; // value method master_m_awid - assign master_awid = master_xactor_rg_wr_addr[96:93] ; + assign master_awid = master_xactor_f_wr_addr$D_OUT[96:93] ; // value method master_m_awaddr - assign master_awaddr = master_xactor_rg_wr_addr[92:29] ; + assign master_awaddr = master_xactor_f_wr_addr$D_OUT[92:29] ; // value method master_m_awlen - assign master_awlen = master_xactor_rg_wr_addr[28:21] ; + assign master_awlen = master_xactor_f_wr_addr$D_OUT[28:21] ; // value method master_m_awsize - assign master_awsize = master_xactor_rg_wr_addr[20:18] ; + assign master_awsize = master_xactor_f_wr_addr$D_OUT[20:18] ; // value method master_m_awburst - assign master_awburst = master_xactor_rg_wr_addr[17:16] ; + assign master_awburst = master_xactor_f_wr_addr$D_OUT[17:16] ; // value method master_m_awlock - assign master_awlock = master_xactor_rg_wr_addr[15] ; + assign master_awlock = master_xactor_f_wr_addr$D_OUT[15] ; // value method master_m_awcache - assign master_awcache = master_xactor_rg_wr_addr[14:11] ; + assign master_awcache = master_xactor_f_wr_addr$D_OUT[14:11] ; // value method master_m_awprot - assign master_awprot = master_xactor_rg_wr_addr[10:8] ; + assign master_awprot = master_xactor_f_wr_addr$D_OUT[10:8] ; // value method master_m_awqos - assign master_awqos = master_xactor_rg_wr_addr[7:4] ; + assign master_awqos = master_xactor_f_wr_addr$D_OUT[7:4] ; // value method master_m_awregion - assign master_awregion = master_xactor_rg_wr_addr[3:0] ; + assign master_awregion = master_xactor_f_wr_addr$D_OUT[3:0] ; // action method master_m_awready assign CAN_FIRE_master_m_awready = 1'd1 ; assign WILL_FIRE_master_m_awready = 1'd1 ; // value method master_m_wvalid - assign master_wvalid = master_xactor_crg_wr_data_full ; - - // value method master_m_wid - assign master_wid = master_xactor_rg_wr_data[76:73] ; + assign master_wvalid = master_xactor_f_wr_data$EMPTY_N ; // value method master_m_wdata - assign master_wdata = master_xactor_rg_wr_data[72:9] ; + assign master_wdata = master_xactor_f_wr_data$D_OUT[72:9] ; // value method master_m_wstrb - assign master_wstrb = master_xactor_rg_wr_data[8:1] ; + assign master_wstrb = master_xactor_f_wr_data$D_OUT[8:1] ; // value method master_m_wlast - assign master_wlast = master_xactor_rg_wr_data[0] ; + assign master_wlast = master_xactor_f_wr_data$D_OUT[0] ; // action method master_m_wready assign CAN_FIRE_master_m_wready = 1'd1 ; @@ -624,40 +592,40 @@ module mkDM_System_Bus(CLK, assign WILL_FIRE_master_m_bvalid = 1'd1 ; // value method master_m_bready - assign master_bready = 1'b1 ; + assign master_bready = master_xactor_f_wr_resp$FULL_N ; // value method master_m_arvalid - assign master_arvalid = master_xactor_crg_rd_addr_full ; + assign master_arvalid = master_xactor_f_rd_addr$EMPTY_N ; // value method master_m_arid - assign master_arid = master_xactor_rg_rd_addr[96:93] ; + assign master_arid = master_xactor_f_rd_addr$D_OUT[96:93] ; // value method master_m_araddr - assign master_araddr = master_xactor_rg_rd_addr[92:29] ; + assign master_araddr = master_xactor_f_rd_addr$D_OUT[92:29] ; // value method master_m_arlen - assign master_arlen = master_xactor_rg_rd_addr[28:21] ; + assign master_arlen = master_xactor_f_rd_addr$D_OUT[28:21] ; // value method master_m_arsize - assign master_arsize = master_xactor_rg_rd_addr[20:18] ; + assign master_arsize = master_xactor_f_rd_addr$D_OUT[20:18] ; // value method master_m_arburst - assign master_arburst = master_xactor_rg_rd_addr[17:16] ; + assign master_arburst = master_xactor_f_rd_addr$D_OUT[17:16] ; // value method master_m_arlock - assign master_arlock = master_xactor_rg_rd_addr[15] ; + assign master_arlock = master_xactor_f_rd_addr$D_OUT[15] ; // value method master_m_arcache - assign master_arcache = master_xactor_rg_rd_addr[14:11] ; + assign master_arcache = master_xactor_f_rd_addr$D_OUT[14:11] ; // value method master_m_arprot - assign master_arprot = master_xactor_rg_rd_addr[10:8] ; + assign master_arprot = master_xactor_f_rd_addr$D_OUT[10:8] ; // value method master_m_arqos - assign master_arqos = master_xactor_rg_rd_addr[7:4] ; + assign master_arqos = master_xactor_f_rd_addr$D_OUT[7:4] ; // value method master_m_arregion - assign master_arregion = master_xactor_rg_rd_addr[3:0] ; + assign master_arregion = master_xactor_f_rd_addr$D_OUT[3:0] ; // action method master_m_arready assign CAN_FIRE_master_m_arready = 1'd1 ; @@ -668,20 +636,79 @@ module mkDM_System_Bus(CLK, assign WILL_FIRE_master_m_rvalid = 1'd1 ; // value method master_m_rready - assign master_rready = !master_xactor_crg_rd_data_full$port2__read ; + assign master_rready = master_xactor_f_rd_data$FULL_N ; + + // submodule master_xactor_f_rd_addr + FIFO2 #(.width(32'd97), + .guarded(32'd1)) master_xactor_f_rd_addr(.RST(RST_N), + .CLK(CLK), + .D_IN(master_xactor_f_rd_addr$D_IN), + .ENQ(master_xactor_f_rd_addr$ENQ), + .DEQ(master_xactor_f_rd_addr$DEQ), + .CLR(master_xactor_f_rd_addr$CLR), + .D_OUT(master_xactor_f_rd_addr$D_OUT), + .FULL_N(master_xactor_f_rd_addr$FULL_N), + .EMPTY_N(master_xactor_f_rd_addr$EMPTY_N)); + + // submodule master_xactor_f_rd_data + FIFO2 #(.width(32'd71), + .guarded(32'd1)) master_xactor_f_rd_data(.RST(RST_N), + .CLK(CLK), + .D_IN(master_xactor_f_rd_data$D_IN), + .ENQ(master_xactor_f_rd_data$ENQ), + .DEQ(master_xactor_f_rd_data$DEQ), + .CLR(master_xactor_f_rd_data$CLR), + .D_OUT(master_xactor_f_rd_data$D_OUT), + .FULL_N(master_xactor_f_rd_data$FULL_N), + .EMPTY_N(master_xactor_f_rd_data$EMPTY_N)); + + // submodule master_xactor_f_wr_addr + FIFO2 #(.width(32'd97), + .guarded(32'd1)) master_xactor_f_wr_addr(.RST(RST_N), + .CLK(CLK), + .D_IN(master_xactor_f_wr_addr$D_IN), + .ENQ(master_xactor_f_wr_addr$ENQ), + .DEQ(master_xactor_f_wr_addr$DEQ), + .CLR(master_xactor_f_wr_addr$CLR), + .D_OUT(master_xactor_f_wr_addr$D_OUT), + .FULL_N(master_xactor_f_wr_addr$FULL_N), + .EMPTY_N(master_xactor_f_wr_addr$EMPTY_N)); + + // submodule master_xactor_f_wr_data + FIFO2 #(.width(32'd73), + .guarded(32'd1)) master_xactor_f_wr_data(.RST(RST_N), + .CLK(CLK), + .D_IN(master_xactor_f_wr_data$D_IN), + .ENQ(master_xactor_f_wr_data$ENQ), + .DEQ(master_xactor_f_wr_data$DEQ), + .CLR(master_xactor_f_wr_data$CLR), + .D_OUT(master_xactor_f_wr_data$D_OUT), + .FULL_N(master_xactor_f_wr_data$FULL_N), + .EMPTY_N(master_xactor_f_wr_data$EMPTY_N)); + + // submodule master_xactor_f_wr_resp + FIFO2 #(.width(32'd6), .guarded(32'd1)) master_xactor_f_wr_resp(.RST(RST_N), + .CLK(CLK), + .D_IN(master_xactor_f_wr_resp$D_IN), + .ENQ(master_xactor_f_wr_resp$ENQ), + .DEQ(master_xactor_f_wr_resp$DEQ), + .CLR(master_xactor_f_wr_resp$CLR), + .D_OUT(master_xactor_f_wr_resp$D_OUT), + .FULL_N(master_xactor_f_wr_resp$FULL_N), + .EMPTY_N(master_xactor_f_wr_resp$EMPTY_N)); // rule RL_rl_sb_read_finish assign CAN_FIRE_RL_rl_sb_read_finish = - master_xactor_crg_rd_data_full && rg_sb_state == 2'd1 && + master_xactor_f_rd_data$EMPTY_N && rg_sb_state == 2'd1 && rg_sbcs_sberror == 3'd0 ; assign WILL_FIRE_RL_rl_sb_read_finish = CAN_FIRE_RL_rl_sb_read_finish ; // rule RL_rl_sb_write_response - assign CAN_FIRE_RL_rl_sb_write_response = master_xactor_crg_wr_resp_full ; - assign WILL_FIRE_RL_rl_sb_write_response = master_xactor_crg_wr_resp_full ; + assign CAN_FIRE_RL_rl_sb_write_response = master_xactor_f_wr_resp$EMPTY_N ; + assign WILL_FIRE_RL_rl_sb_write_response = master_xactor_f_wr_resp$EMPTY_N ; // inputs to muxes for submodule ports - assign MUX_master_xactor_crg_rd_addr_full$port2__write_1__SEL_1 = + assign MUX_master_xactor_f_rd_addr$enq_1__SEL_1 = EN_av_read && av_read_dm_addr == 7'h3C && rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d110 ; assign MUX_rg_sbaddress0$write_1__SEL_2 = @@ -699,50 +726,50 @@ module mkDM_System_Bus(CLK, ((write_dm_addr == 7'h39 || write_dm_addr == 7'h3A) && rg_sb_state == 2'd0 && !rg_sbcs_sbbusyerror && - rg_sbcs_sberror_EQ_0_AND_rg_sbcs_sbreadonaddr__ETC___d292 || + rg_sbcs_sberror_EQ_0_AND_rg_sbcs_sbreadonaddr__ETC___d291 || write_dm_addr == 7'h3C && rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d95) ; assign MUX_rg_sbcs_sbbusyerror$write_1__SEL_2 = EN_write && - write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d266 ; + write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d265 ; assign MUX_rg_sbcs_sbbusyerror$write_1__SEL_3 = EN_av_read && av_read_dm_addr == 7'h3C && rg_sb_state != 2'd0 ; assign MUX_rg_sbcs_sberror$write_1__SEL_1 = - master_xactor_crg_wr_resp_full && - master_xactor_rg_wr_resp[1:0] != 2'b0 ; + master_xactor_f_wr_resp$EMPTY_N && + master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0 ; assign MUX_rg_sbcs_sberror$write_1__SEL_3 = WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0 ; + master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ; assign MUX_rg_sbcs_sberror$write_1__SEL_4 = EN_write && - write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d274 ; + write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d273 ; assign MUX_rg_sbdata0$write_1__SEL_3 = EN_write && - write_dm_addr_EQ_0x3C_62_AND_rg_sb_state_EQ_0__ETC___d327 ; - assign MUX_master_xactor_rg_rd_addr$write_1__VAL_1 = - { 4'd0, sbaddress__h1228, 8'd0, x__h3284, 18'd65536 } ; - assign MUX_master_xactor_rg_rd_addr$write_1__VAL_2 = - { 4'd0, addr64__h4331, 8'd0, x__h3284, 18'd65536 } ; + write_dm_addr_EQ_0x3C_61_AND_rg_sb_state_EQ_0__ETC___d326 ; + assign MUX_master_xactor_f_rd_addr$enq_1__VAL_1 = + { 4'd0, sbaddress__h638, 8'd0, x__h2654, 18'd65536 } ; + assign MUX_master_xactor_f_rd_addr$enq_1__VAL_2 = + { 4'd0, addr64__h3701, 8'd0, x__h2654, 18'd65536 } ; always@(write_dm_addr or rg_sbaddress1_7_CONCAT_rg_sbaddress0_8_9_PLUS__ETC___d104 or - IF_rg_sbcs_sbreadonaddr_24_THEN_IF_rg_sbcs_sba_ETC___d311) + IF_rg_sbcs_sbreadonaddr_24_THEN_IF_rg_sbcs_sba_ETC___d310) begin case (write_dm_addr) 7'h39, 7'h3A: MUX_rg_sbaddress0$write_1__VAL_2 = - IF_rg_sbcs_sbreadonaddr_24_THEN_IF_rg_sbcs_sba_ETC___d311; + IF_rg_sbcs_sbreadonaddr_24_THEN_IF_rg_sbcs_sba_ETC___d310; default: MUX_rg_sbaddress0$write_1__VAL_2 = rg_sbaddress1_7_CONCAT_rg_sbaddress0_8_9_PLUS__ETC___d104[31:0]; endcase end always@(write_dm_addr or rg_sbaddress1_7_CONCAT_rg_sbaddress0_8_9_PLUS__ETC___d104 or - IF_write_dm_addr_EQ_0x39_59_THEN_rg_sbaddress1_ETC___d302) + IF_write_dm_addr_EQ_0x39_58_THEN_rg_sbaddress1_ETC___d301) begin case (write_dm_addr) 7'h39, 7'h3A: MUX_rg_sbaddress1$write_1__VAL_2 = - IF_write_dm_addr_EQ_0x39_59_THEN_rg_sbaddress1_ETC___d302; + IF_write_dm_addr_EQ_0x39_58_THEN_rg_sbaddress1_ETC___d301; default: MUX_rg_sbaddress1$write_1__VAL_2 = rg_sbaddress1_7_CONCAT_rg_sbaddress0_8_9_PLUS__ETC___d104[63:32]; endcase @@ -755,100 +782,6 @@ module mkDM_System_Bus(CLK, endcase end - // inlined wires - assign master_xactor_crg_wr_addr_full$EN_port1__write = - master_xactor_crg_wr_addr_full && master_awready ; - assign master_xactor_crg_wr_addr_full$port2__read = - !master_xactor_crg_wr_addr_full$EN_port1__write && - master_xactor_crg_wr_addr_full ; - assign master_xactor_crg_wr_addr_full$port3__read = - MUX_rg_sbdata0$write_1__SEL_3 || - master_xactor_crg_wr_addr_full$port2__read ; - assign master_xactor_crg_wr_data_full$EN_port1__write = - master_xactor_crg_wr_data_full && master_wready ; - assign master_xactor_crg_wr_data_full$port2__read = - !master_xactor_crg_wr_data_full$EN_port1__write && - master_xactor_crg_wr_data_full ; - assign master_xactor_crg_wr_data_full$port3__read = - MUX_rg_sbdata0$write_1__SEL_3 || - master_xactor_crg_wr_data_full$port2__read ; - assign master_xactor_crg_rd_addr_full$EN_port1__write = - master_xactor_crg_rd_addr_full && master_arready ; - assign master_xactor_crg_rd_addr_full$port2__read = - !master_xactor_crg_rd_addr_full$EN_port1__write && - master_xactor_crg_rd_addr_full ; - assign master_xactor_crg_rd_addr_full$EN_port2__write = - EN_av_read && av_read_dm_addr == 7'h3C && - rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d110 || - EN_write && write_dm_addr == 7'h39 && - rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d317 ; - assign master_xactor_crg_rd_addr_full$port3__read = - master_xactor_crg_rd_addr_full$EN_port2__write ? - 1'd1 : - master_xactor_crg_rd_addr_full$port2__read ; - assign master_xactor_crg_rd_data_full$port2__read = - !CAN_FIRE_RL_rl_sb_read_finish && - master_xactor_crg_rd_data_full ; - assign master_xactor_crg_rd_data_full$EN_port2__write = - master_rvalid && !master_xactor_crg_rd_data_full$port2__read ; - assign master_xactor_crg_rd_data_full$port3__read = - master_xactor_crg_rd_data_full$EN_port2__write || - master_xactor_crg_rd_data_full$port2__read ; - - // register master_xactor_crg_rd_addr_full - assign master_xactor_crg_rd_addr_full$D_IN = - master_xactor_crg_rd_addr_full$port3__read ; - assign master_xactor_crg_rd_addr_full$EN = 1'b1 ; - - // register master_xactor_crg_rd_data_full - assign master_xactor_crg_rd_data_full$D_IN = - master_xactor_crg_rd_data_full$port3__read ; - assign master_xactor_crg_rd_data_full$EN = 1'b1 ; - - // register master_xactor_crg_wr_addr_full - assign master_xactor_crg_wr_addr_full$D_IN = - master_xactor_crg_wr_addr_full$port3__read ; - assign master_xactor_crg_wr_addr_full$EN = 1'b1 ; - - // register master_xactor_crg_wr_data_full - assign master_xactor_crg_wr_data_full$D_IN = - master_xactor_crg_wr_data_full$port3__read ; - assign master_xactor_crg_wr_data_full$EN = 1'b1 ; - - // register master_xactor_crg_wr_resp_full - assign master_xactor_crg_wr_resp_full$D_IN = master_bvalid ; - assign master_xactor_crg_wr_resp_full$EN = 1'b1 ; - - // register master_xactor_rg_rd_addr - assign master_xactor_rg_rd_addr$D_IN = - MUX_master_xactor_crg_rd_addr_full$port2__write_1__SEL_1 ? - MUX_master_xactor_rg_rd_addr$write_1__VAL_1 : - MUX_master_xactor_rg_rd_addr$write_1__VAL_2 ; - assign master_xactor_rg_rd_addr$EN = - EN_av_read && av_read_dm_addr == 7'h3C && - rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d110 || - EN_write && write_dm_addr == 7'h39 && - rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d317 ; - - // register master_xactor_rg_rd_data - assign master_xactor_rg_rd_data$D_IN = - { master_rid, master_rdata, master_rresp, master_rlast } ; - assign master_xactor_rg_rd_data$EN = 1'd1 ; - - // register master_xactor_rg_wr_addr - assign master_xactor_rg_wr_addr$D_IN = - { 4'd0, sbaddress__h1228, 8'd0, x__h4989, 18'd65536 } ; - assign master_xactor_rg_wr_addr$EN = MUX_rg_sbdata0$write_1__SEL_3 ; - - // register master_xactor_rg_wr_data - assign master_xactor_rg_wr_data$D_IN = - { 4'd0, wrd_wdata__h5118, wrd_wstrb__h5119, 1'd1 } ; - assign master_xactor_rg_wr_data$EN = MUX_rg_sbdata0$write_1__SEL_3 ; - - // register master_xactor_rg_wr_resp - assign master_xactor_rg_wr_resp$D_IN = { master_bid, master_bresp } ; - assign master_xactor_rg_wr_resp$EN = master_bvalid ; - // register rg_sb_state assign rg_sb_state$D_IN = (EN_reset || WILL_FIRE_RL_rl_sb_read_finish) ? 2'd0 : 2'd1 ; @@ -856,7 +789,7 @@ module mkDM_System_Bus(CLK, EN_av_read && av_read_dm_addr == 7'h3C && rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d110 || EN_write && write_dm_addr == 7'h39 && - rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d317 || + rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d316 || WILL_FIRE_RL_rl_sb_read_finish || EN_reset ; @@ -904,27 +837,27 @@ module mkDM_System_Bus(CLK, // register rg_sbaddress_reading assign rg_sbaddress_reading$D_IN = - MUX_master_xactor_crg_rd_addr_full$port2__write_1__SEL_1 ? - sbaddress__h1228 : - addr64__h4331 ; + MUX_master_xactor_f_rd_addr$enq_1__SEL_1 ? + sbaddress__h638 : + addr64__h3701 ; assign rg_sbaddress_reading$EN = EN_av_read && av_read_dm_addr == 7'h3C && rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d110 || EN_write && write_dm_addr == 7'h39 && - rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d317 ; + rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d316 ; // register rg_sbcs_sbaccess assign rg_sbcs_sbaccess$D_IN = EN_reset ? 3'd2 : write_dm_word[19:17] ; assign rg_sbcs_sbaccess$EN = EN_write && - write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d257 || + write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d256 || EN_reset ; // register rg_sbcs_sbautoincrement assign rg_sbcs_sbautoincrement$D_IN = !EN_reset && write_dm_word[16] ; assign rg_sbcs_sbautoincrement$EN = EN_write && - write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d257 || + write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d256 || EN_reset ; // register rg_sbcs_sbbusyerror @@ -941,7 +874,7 @@ module mkDM_System_Bus(CLK, assign rg_sbcs_sbbusyerror$EN = EN_av_read && av_read_dm_addr == 7'h3C && rg_sb_state != 2'd0 || EN_write && - write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d266 || + write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d265 || EN_reset ; // register rg_sbcs_sberror @@ -960,25 +893,25 @@ module mkDM_System_Bus(CLK, endcase assign rg_sbcs_sberror$EN = WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0 || - master_xactor_crg_wr_resp_full && - master_xactor_rg_wr_resp[1:0] != 2'b0 || + master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 || + master_xactor_f_wr_resp$EMPTY_N && + master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0 || EN_write && - write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d274 || + write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d273 || EN_reset ; // register rg_sbcs_sbreadonaddr assign rg_sbcs_sbreadonaddr$D_IN = !EN_reset && write_dm_word[20] ; assign rg_sbcs_sbreadonaddr$EN = EN_write && - write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d257 || + write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d256 || EN_reset ; // register rg_sbcs_sbreadondata assign rg_sbcs_sbreadondata$D_IN = !EN_reset && write_dm_word[15] ; assign rg_sbcs_sbreadondata$EN = EN_write && - write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d257 || + write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d256 || EN_reset ; // register rg_sbdata0 @@ -996,42 +929,87 @@ module mkDM_System_Bus(CLK, endcase assign rg_sbdata0$EN = EN_write && - write_dm_addr_EQ_0x3C_62_AND_rg_sb_state_EQ_0__ETC___d327 || + write_dm_addr_EQ_0x3C_61_AND_rg_sb_state_EQ_0__ETC___d326 || WILL_FIRE_RL_rl_sb_read_finish || EN_reset ; + // submodule master_xactor_f_rd_addr + assign master_xactor_f_rd_addr$D_IN = + MUX_master_xactor_f_rd_addr$enq_1__SEL_1 ? + MUX_master_xactor_f_rd_addr$enq_1__VAL_1 : + MUX_master_xactor_f_rd_addr$enq_1__VAL_2 ; + assign master_xactor_f_rd_addr$ENQ = + EN_av_read && av_read_dm_addr == 7'h3C && + rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d110 || + EN_write && write_dm_addr == 7'h39 && + rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d316 ; + assign master_xactor_f_rd_addr$DEQ = + master_xactor_f_rd_addr$EMPTY_N && master_arready ; + assign master_xactor_f_rd_addr$CLR = 1'b0 ; + + // submodule master_xactor_f_rd_data + assign master_xactor_f_rd_data$D_IN = + { master_rid, master_rdata, master_rresp, master_rlast } ; + assign master_xactor_f_rd_data$ENQ = + master_rvalid && master_xactor_f_rd_data$FULL_N ; + assign master_xactor_f_rd_data$DEQ = CAN_FIRE_RL_rl_sb_read_finish ; + assign master_xactor_f_rd_data$CLR = 1'b0 ; + + // submodule master_xactor_f_wr_addr + assign master_xactor_f_wr_addr$D_IN = + { 4'd0, sbaddress__h638, 8'd0, x__h4302, 18'd65536 } ; + assign master_xactor_f_wr_addr$ENQ = MUX_rg_sbdata0$write_1__SEL_3 ; + assign master_xactor_f_wr_addr$DEQ = + master_xactor_f_wr_addr$EMPTY_N && master_awready ; + assign master_xactor_f_wr_addr$CLR = 1'b0 ; + + // submodule master_xactor_f_wr_data + assign master_xactor_f_wr_data$D_IN = + { wrd_wdata__h4397, wrd_wstrb__h4398, 1'd1 } ; + assign master_xactor_f_wr_data$ENQ = MUX_rg_sbdata0$write_1__SEL_3 ; + assign master_xactor_f_wr_data$DEQ = + master_xactor_f_wr_data$EMPTY_N && master_wready ; + assign master_xactor_f_wr_data$CLR = 1'b0 ; + + // submodule master_xactor_f_wr_resp + assign master_xactor_f_wr_resp$D_IN = { master_bid, master_bresp } ; + assign master_xactor_f_wr_resp$ENQ = + master_bvalid && master_xactor_f_wr_resp$FULL_N ; + assign master_xactor_f_wr_resp$DEQ = master_xactor_f_wr_resp$EMPTY_N ; + assign master_xactor_f_wr_resp$CLR = 1'b0 ; + // remaining internal signals - assign IF_rg_sbcs_sbreadonaddr_24_THEN_IF_rg_sbcs_sba_ETC___d311 = + assign IF_rg_sbcs_sbreadonaddr_24_THEN_IF_rg_sbcs_sba_ETC___d310 = rg_sbcs_sbreadonaddr ? (rg_sbcs_sbautoincrement ? - rg_sbaddress1_7_CONCAT_write_dm_word_99_PLUS_I_ETC___d300[31:0] : + rg_sbaddress1_7_CONCAT_write_dm_word_98_PLUS_I_ETC___d299[31:0] : write_dm_word) : write_dm_word ; - assign IF_write_dm_addr_EQ_0x39_59_THEN_rg_sbaddress1_ETC___d302 = + assign IF_write_dm_addr_EQ_0x39_58_THEN_rg_sbaddress1_ETC___d301 = (write_dm_addr == 7'h39) ? - rg_sbaddress1_7_CONCAT_write_dm_word_99_PLUS_I_ETC___d300[63:32] : + rg_sbaddress1_7_CONCAT_write_dm_word_98_PLUS_I_ETC___d299[63:32] : write_dm_word ; - assign _theResult___fst__h5027 = word64__h4971 << shift_bits__h4974 ; - assign addr64__h4331 = { rg_sbaddress1, write_dm_word } ; - assign result__h1836 = { 56'd0, master_xactor_rg_rd_data[10:3] } ; - assign result__h1866 = { 56'd0, master_xactor_rg_rd_data[18:11] } ; - assign result__h1893 = { 56'd0, master_xactor_rg_rd_data[26:19] } ; - assign result__h1920 = { 56'd0, master_xactor_rg_rd_data[34:27] } ; - assign result__h1947 = { 56'd0, master_xactor_rg_rd_data[42:35] } ; - assign result__h1974 = { 56'd0, master_xactor_rg_rd_data[50:43] } ; - assign result__h2001 = { 56'd0, master_xactor_rg_rd_data[58:51] } ; - assign result__h2028 = { 56'd0, master_xactor_rg_rd_data[66:59] } ; - assign result__h2073 = { 48'd0, master_xactor_rg_rd_data[18:3] } ; - assign result__h2100 = { 48'd0, master_xactor_rg_rd_data[34:19] } ; - assign result__h2127 = { 48'd0, master_xactor_rg_rd_data[50:35] } ; - assign result__h2154 = { 48'd0, master_xactor_rg_rd_data[66:51] } ; - assign result__h2195 = { 32'd0, master_xactor_rg_rd_data[34:3] } ; - assign result__h2222 = { 32'd0, master_xactor_rg_rd_data[66:35] } ; + assign _theResult___fst__h4340 = word64__h4284 << shift_bits__h4287 ; + assign addr64__h3701 = { rg_sbaddress1, write_dm_word } ; + assign result__h1250 = { 56'd0, master_xactor_f_rd_data$D_OUT[10:3] } ; + assign result__h1280 = { 56'd0, master_xactor_f_rd_data$D_OUT[18:11] } ; + assign result__h1307 = { 56'd0, master_xactor_f_rd_data$D_OUT[26:19] } ; + assign result__h1334 = { 56'd0, master_xactor_f_rd_data$D_OUT[34:27] } ; + assign result__h1361 = { 56'd0, master_xactor_f_rd_data$D_OUT[42:35] } ; + assign result__h1388 = { 56'd0, master_xactor_f_rd_data$D_OUT[50:43] } ; + assign result__h1415 = { 56'd0, master_xactor_f_rd_data$D_OUT[58:51] } ; + assign result__h1442 = { 56'd0, master_xactor_f_rd_data$D_OUT[66:59] } ; + assign result__h1487 = { 48'd0, master_xactor_f_rd_data$D_OUT[18:3] } ; + assign result__h1514 = { 48'd0, master_xactor_f_rd_data$D_OUT[34:19] } ; + assign result__h1541 = { 48'd0, master_xactor_f_rd_data$D_OUT[50:35] } ; + assign result__h1568 = { 48'd0, master_xactor_f_rd_data$D_OUT[66:51] } ; + assign result__h1609 = { 32'd0, master_xactor_f_rd_data$D_OUT[34:3] } ; + assign result__h1636 = { 32'd0, master_xactor_f_rd_data$D_OUT[66:35] } ; assign rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d110 = rg_sb_state == 2'd0 && !rg_sbcs_sbbusyerror && rg_sbcs_sberror == 3'd0 && rg_sbcs_sbreadondata ; - assign rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d317 = + assign rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d316 = rg_sb_state == 2'd0 && !rg_sbcs_sbbusyerror && rg_sbcs_sberror == 3'd0 && rg_sbcs_sbreadonaddr ; @@ -1040,21 +1018,21 @@ module mkDM_System_Bus(CLK, rg_sbcs_sberror == 3'd0 && rg_sbcs_sbautoincrement ; assign rg_sbaddress1_7_CONCAT_rg_sbaddress0_8_9_PLUS__ETC___d104 = - sbaddress__h1228 + + sbaddress__h638 + IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d103 ; - assign rg_sbaddress1_7_CONCAT_write_dm_word_99_PLUS_I_ETC___d300 = - addr64__h4331 + + assign rg_sbaddress1_7_CONCAT_write_dm_word_98_PLUS_I_ETC___d299 = + addr64__h3701 + IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d103 ; - assign rg_sbcs_sberror_EQ_0_AND_rg_sbcs_sbreadonaddr__ETC___d292 = + assign rg_sbcs_sberror_EQ_0_AND_rg_sbcs_sbreadonaddr__ETC___d291 = rg_sbcs_sberror == 3'd0 && (rg_sbcs_sbreadonaddr && rg_sbcs_sbautoincrement || write_dm_addr != 7'h39) ; - assign sbaddress__h1228 = { rg_sbaddress1, rg_sbaddress0 } ; - assign shift_bits__h4974 = { rg_sbaddress0[2:0], 3'b0 } ; - assign strobe64__h5026 = 8'b00000001 << rg_sbaddress0[2:0] ; - assign strobe64__h5029 = 8'b00000011 << rg_sbaddress0[2:0] ; - assign strobe64__h5032 = 8'b00001111 << rg_sbaddress0[2:0] ; - assign v__h2728 = + assign sbaddress__h638 = { rg_sbaddress1, rg_sbaddress0 } ; + assign shift_bits__h4287 = { rg_sbaddress0[2:0], 3'b0 } ; + assign strobe64__h4339 = 8'b00000001 << rg_sbaddress0[2:0] ; + assign strobe64__h4342 = 8'b00000011 << rg_sbaddress0[2:0] ; + assign strobe64__h4345 = 8'b00001111 << rg_sbaddress0[2:0] ; + assign v__h2132 = { 9'd64, rg_sbcs_sbbusyerror, rg_sb_state != 2'd0, @@ -1064,71 +1042,105 @@ module mkDM_System_Bus(CLK, rg_sbcs_sbreadondata, rg_sbcs_sberror, 12'd2055 } ; - assign v__h2862 = + assign v__h2266 = (rg_sb_state != 2'd0 || rg_sbcs_sbbusyerror || rg_sbcs_sberror != 3'd0) ? 32'd0 : rg_sbdata0 ; - assign word64__h4971 = { 32'd0, write_dm_word } ; - assign write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d257 = + assign word64__h4284 = { 32'd0, write_dm_word } ; + assign write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d256 = write_dm_addr == 7'h38 && (rg_sbcs_sberror == 3'd0 || write_dm_word[14:12] != 3'd0) && (!rg_sbcs_sbbusyerror || write_dm_word[22]) && write_dm_word[19:17] != 3'd4 && write_dm_word[19:17] != 3'd3 ; - assign write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d266 = - write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d257 || + assign write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d265 = + write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d256 || (write_dm_addr == 7'h39 || write_dm_addr == 7'h3A || write_dm_addr == 7'h3C) && rg_sb_state != 2'd0 ; - assign write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d272 = + assign write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d271 = write_dm_addr == 7'h38 && (rg_sbcs_sberror == 3'd0 || write_dm_word[14:12] != 3'd0) && rg_sbcs_sbbusyerror && !write_dm_word[22] ; - assign write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d274 = + assign write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d273 = write_dm_addr == 7'h38 && (rg_sbcs_sberror == 3'd0 || write_dm_word[14:12] != 3'd0) && (!rg_sbcs_sbbusyerror || write_dm_word[22]) ; - assign write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d279 = + assign write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d278 = write_dm_addr == 7'h38 && (rg_sbcs_sberror == 3'd0 || write_dm_word[14:12] != 3'd0) && (!rg_sbcs_sbbusyerror || write_dm_word[22]) && (write_dm_word[19:17] == 3'd4 || write_dm_word[19:17] == 3'd3) ; - assign write_dm_addr_EQ_0x3C_62_AND_rg_sb_state_EQ_0__ETC___d327 = + assign write_dm_addr_EQ_0x3C_61_AND_rg_sb_state_EQ_0__ETC___d326 = write_dm_addr == 7'h3C && rg_sb_state == 2'd0 && !rg_sbcs_sbbusyerror && rg_sbcs_sberror == 3'd0 ; always@(rg_sbcs_sbaccess) begin case (rg_sbcs_sbaccess) - 3'd0, 3'd1, 3'd2: x__h3284 = rg_sbcs_sbaccess; - default: x__h3284 = 3'b011; + 3'd0, 3'd1, 3'd2: x__h2654 = rg_sbcs_sbaccess; + default: x__h2654 = 3'b011; endcase end always@(rg_sbcs_sbaccess) begin case (rg_sbcs_sbaccess) - 3'd0, 3'd1, 3'd2, 3'd3: x__h4989 = rg_sbcs_sbaccess; - default: x__h4989 = 3'b111; + 3'd0, 3'd1, 3'd2, 3'd3: x__h4302 = rg_sbcs_sbaccess; + default: x__h4302 = 3'b111; endcase end always@(rg_sbcs_sbaccess or - strobe64__h5026 or strobe64__h5029 or strobe64__h5032) + strobe64__h4339 or strobe64__h4342 or strobe64__h4345) begin case (rg_sbcs_sbaccess) - 3'd0: wrd_wstrb__h5119 = strobe64__h5026; - 3'd1: wrd_wstrb__h5119 = strobe64__h5029; - 3'd2: wrd_wstrb__h5119 = strobe64__h5032; - 3'd3: wrd_wstrb__h5119 = 8'b11111111; - default: wrd_wstrb__h5119 = 8'd0; + 3'd0: wrd_wstrb__h4398 = strobe64__h4339; + 3'd1: wrd_wstrb__h4398 = strobe64__h4342; + 3'd2: wrd_wstrb__h4398 = strobe64__h4345; + 3'd3: wrd_wstrb__h4398 = 8'b11111111; + default: wrd_wstrb__h4398 = 8'd0; endcase end - always@(rg_sbcs_sbaccess or word64__h4971 or _theResult___fst__h5027) + always@(rg_sbcs_sbaccess or word64__h4284 or _theResult___fst__h4340) begin case (rg_sbcs_sbaccess) - 3'd0, 3'd1, 3'd2: wrd_wdata__h5118 = _theResult___fst__h5027; - default: wrd_wdata__h5118 = word64__h4971; + 3'd0, 3'd1, 3'd2: wrd_wdata__h4397 = _theResult___fst__h4340; + default: wrd_wdata__h4397 = word64__h4284; + endcase + end + always@(rg_sbaddress_reading or + result__h1250 or + result__h1280 or + result__h1307 or + result__h1334 or + result__h1361 or result__h1388 or result__h1415 or result__h1442) + begin + case (rg_sbaddress_reading[2:0]) + 3'h0: + IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 = + result__h1250; + 3'h1: + IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 = + result__h1280; + 3'h2: + IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 = + result__h1307; + 3'h3: + IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 = + result__h1334; + 3'h4: + IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 = + result__h1361; + 3'h5: + IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 = + result__h1388; + 3'h6: + IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 = + result__h1415; + 3'h7: + IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 = + result__h1442; endcase end always@(rg_sbcs_sbaccess) @@ -1143,68 +1155,34 @@ module mkDM_System_Bus(CLK, endcase end always@(rg_sbaddress_reading or - result__h1836 or - result__h1866 or - result__h1893 or - result__h1920 or - result__h1947 or result__h1974 or result__h2001 or result__h2028) - begin - case (rg_sbaddress_reading[2:0]) - 3'h0: - IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 = - result__h1836; - 3'h1: - IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 = - result__h1866; - 3'h2: - IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 = - result__h1893; - 3'h3: - IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 = - result__h1920; - 3'h4: - IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 = - result__h1947; - 3'h5: - IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 = - result__h1974; - 3'h6: - IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 = - result__h2001; - 3'h7: - IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 = - result__h2028; - endcase - end - always@(rg_sbaddress_reading or - result__h2073 or result__h2100 or result__h2127 or result__h2154) + result__h1487 or result__h1514 or result__h1541 or result__h1568) begin case (rg_sbaddress_reading[2:0]) 3'h0: IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d66 = - result__h2073; + result__h1487; 3'h2: IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d66 = - result__h2100; + result__h1514; 3'h4: IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d66 = - result__h2127; + result__h1541; 3'h6: IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d66 = - result__h2154; + result__h1568; default: IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d66 = 64'd0; endcase end - always@(rg_sbaddress_reading or result__h2195 or result__h2222) + always@(rg_sbaddress_reading or result__h1609 or result__h1636) begin case (rg_sbaddress_reading[2:0]) 3'h0: CASE_rg_sbaddress_reading_BITS_2_TO_0_0x0_resu_ETC__q1 = - result__h2195; + result__h1609; 3'h4: CASE_rg_sbaddress_reading_BITS_2_TO_0_0x0_resu_ETC__q1 = - result__h2222; + result__h1636; default: CASE_rg_sbaddress_reading_BITS_2_TO_0_0x0_resu_ETC__q1 = 64'd0; endcase end @@ -1212,7 +1190,7 @@ module mkDM_System_Bus(CLK, IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 or IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d66 or CASE_rg_sbaddress_reading_BITS_2_TO_0_0x0_resu_ETC__q1 or - rg_sbaddress_reading or master_xactor_rg_rd_data) + rg_sbaddress_reading or master_xactor_f_rd_data$D_OUT) begin case (rg_sbcs_sbaccess) 3'd0: @@ -1227,7 +1205,7 @@ module mkDM_System_Bus(CLK, 3'd3: IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d79 = (rg_sbaddress_reading[2:0] == 3'h0) ? - master_xactor_rg_rd_data[66:3] : + master_xactor_f_rd_data$D_OUT[66:3] : 64'd0; default: IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d79 = 64'd0; @@ -1240,51 +1218,16 @@ module mkDM_System_Bus(CLK, begin if (RST_N == `BSV_RESET_VALUE) begin - master_xactor_crg_rd_addr_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - master_xactor_crg_rd_data_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - master_xactor_crg_wr_addr_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - master_xactor_crg_wr_data_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - master_xactor_crg_wr_resp_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_sbaddress0 <= `BSV_ASSIGNMENT_DELAY 32'd0; + rg_sbaddress0 <= `BSV_ASSIGNMENT_DELAY 32'd0; rg_sbaddress1 <= `BSV_ASSIGNMENT_DELAY 32'd0; end else begin - if (master_xactor_crg_rd_addr_full$EN) - master_xactor_crg_rd_addr_full <= `BSV_ASSIGNMENT_DELAY - master_xactor_crg_rd_addr_full$D_IN; - if (master_xactor_crg_rd_data_full$EN) - master_xactor_crg_rd_data_full <= `BSV_ASSIGNMENT_DELAY - master_xactor_crg_rd_data_full$D_IN; - if (master_xactor_crg_wr_addr_full$EN) - master_xactor_crg_wr_addr_full <= `BSV_ASSIGNMENT_DELAY - master_xactor_crg_wr_addr_full$D_IN; - if (master_xactor_crg_wr_data_full$EN) - master_xactor_crg_wr_data_full <= `BSV_ASSIGNMENT_DELAY - master_xactor_crg_wr_data_full$D_IN; - if (master_xactor_crg_wr_resp_full$EN) - master_xactor_crg_wr_resp_full <= `BSV_ASSIGNMENT_DELAY - master_xactor_crg_wr_resp_full$D_IN; - if (rg_sbaddress0$EN) + if (rg_sbaddress0$EN) rg_sbaddress0 <= `BSV_ASSIGNMENT_DELAY rg_sbaddress0$D_IN; if (rg_sbaddress1$EN) rg_sbaddress1 <= `BSV_ASSIGNMENT_DELAY rg_sbaddress1$D_IN; end - if (master_xactor_rg_rd_addr$EN) - master_xactor_rg_rd_addr <= `BSV_ASSIGNMENT_DELAY - master_xactor_rg_rd_addr$D_IN; - if (master_xactor_rg_rd_data$EN) - master_xactor_rg_rd_data <= `BSV_ASSIGNMENT_DELAY - master_xactor_rg_rd_data$D_IN; - if (master_xactor_rg_wr_addr$EN) - master_xactor_rg_wr_addr <= `BSV_ASSIGNMENT_DELAY - master_xactor_rg_wr_addr$D_IN; - if (master_xactor_rg_wr_data$EN) - master_xactor_rg_wr_data <= `BSV_ASSIGNMENT_DELAY - master_xactor_rg_wr_data$D_IN; - if (master_xactor_rg_wr_resp$EN) - master_xactor_rg_wr_resp <= `BSV_ASSIGNMENT_DELAY - master_xactor_rg_wr_resp$D_IN; if (rg_sb_state$EN) rg_sb_state <= `BSV_ASSIGNMENT_DELAY rg_sb_state$D_IN; if (rg_sbaddress_reading$EN) rg_sbaddress_reading <= `BSV_ASSIGNMENT_DELAY rg_sbaddress_reading$D_IN; @@ -1309,16 +1252,6 @@ module mkDM_System_Bus(CLK, `else // not BSV_NO_INITIAL_BLOCKS initial begin - master_xactor_crg_rd_addr_full = 1'h0; - master_xactor_crg_rd_data_full = 1'h0; - master_xactor_crg_wr_addr_full = 1'h0; - master_xactor_crg_wr_data_full = 1'h0; - master_xactor_crg_wr_resp_full = 1'h0; - master_xactor_rg_rd_addr = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; - master_xactor_rg_rd_data = 71'h2AAAAAAAAAAAAAAAAA; - master_xactor_rg_wr_addr = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; - master_xactor_rg_wr_data = 77'h0AAAAAAAAAAAAAAAAAAA; - master_xactor_rg_wr_resp = 6'h2A; rg_sb_state = 2'h2; rg_sbaddress0 = 32'hAAAAAAAA; rg_sbaddress1 = 32'hAAAAAAAA; @@ -1484,24 +1417,24 @@ module mkDM_System_Bus(CLK, $display(" Must be cleared to re-enable system bus access."); if (RST_N != `BSV_RESET_VALUE) if (EN_write && - write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d272) + write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d271) $display("DM_System_Bus.sbcs_write <= 0x%08h: ERROR", write_dm_word); if (RST_N != `BSV_RESET_VALUE) if (EN_write && - write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d272) + write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d271) $display(" ERROR: existing sbbusyerror (%0d) is not being cleared.", rg_sbcs_sbbusyerror); if (RST_N != `BSV_RESET_VALUE) if (EN_write && - write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d272) + write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d271) $display(" Must be cleared to re-enable system bus access."); if (RST_N != `BSV_RESET_VALUE) if (EN_write && - write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d279) + write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d278) $display("DM_System_Bus.sbcs_write <= 0x%08h: ERROR", write_dm_word); if (RST_N != `BSV_RESET_VALUE) if (EN_write && - write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d279) + write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d278) $write(" ERROR: sbaccess "); if (RST_N != `BSV_RESET_VALUE) if (EN_write && write_dm_addr == 7'h38 && @@ -1517,7 +1450,7 @@ module mkDM_System_Bus(CLK, $write("DM_SBACCESS_128_BIT"); if (RST_N != `BSV_RESET_VALUE) if (EN_write && - write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d279) + write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d278) $write(" not supported", "\n"); if (RST_N != `BSV_RESET_VALUE) if (EN_write && write_dm_addr != 7'h38 && @@ -1658,61 +1591,61 @@ module mkDM_System_Bus(CLK, $write("] <= 0x%08h; addr not supported", write_dm_word, "\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0) + master_xactor_f_rd_data$D_OUT[2:1] != 2'b0) $display("DM_System_Bus.rule_sb_read_finish: setting rg_sbcs_sberror to DM_SBERROR_OTHER\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0) + master_xactor_f_rd_data$D_OUT[2:1] != 2'b0) $write(" rdr = "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0) + master_xactor_f_rd_data$D_OUT[2:1] != 2'b0) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0) - $write("'h%h", master_xactor_rg_rd_data[70:67]); + master_xactor_f_rd_data$D_OUT[2:1] != 2'b0) + $write("'h%h", master_xactor_f_rd_data$D_OUT[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0) + master_xactor_f_rd_data$D_OUT[2:1] != 2'b0) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0) - $write("'h%h", master_xactor_rg_rd_data[66:3]); + master_xactor_f_rd_data$D_OUT[2:1] != 2'b0) + $write("'h%h", master_xactor_f_rd_data$D_OUT[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0) + master_xactor_f_rd_data$D_OUT[2:1] != 2'b0) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0) - $write("'h%h", master_xactor_rg_rd_data[2:1]); + master_xactor_f_rd_data$D_OUT[2:1] != 2'b0) + $write("'h%h", master_xactor_f_rd_data$D_OUT[2:1]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0) + master_xactor_f_rd_data$D_OUT[2:1] != 2'b0) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0 && - master_xactor_rg_rd_data[0]) + master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 && + master_xactor_f_rd_data$D_OUT[0]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0 && - !master_xactor_rg_rd_data[0]) + master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 && + !master_xactor_f_rd_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0) + master_xactor_f_rd_data$D_OUT[2:1] != 2'b0) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0) + master_xactor_f_rd_data$D_OUT[2:1] != 2'b0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0) + master_xactor_f_rd_data$D_OUT[2:1] != 2'b0) $write("\n"); end // synopsys translate_on diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkDPRqMshrWrapper.v b/src_SSITH_P3_sim/Verilog_RTL/mkDPRqMshrWrapper.v index 410dac6..659476b 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkDPRqMshrWrapper.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkDPRqMshrWrapper.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkDPipeline.v b/src_SSITH_P3_sim/Verilog_RTL/mkDPipeline.v index 332ab16..969f8c6 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkDPipeline.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkDPipeline.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkDTlbSynth.v b/src_SSITH_P3_sim/Verilog_RTL/mkDTlbSynth.v index 2bb277d..47f254c 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkDTlbSynth.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkDTlbSynth.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkDebug_Module.v b/src_SSITH_P3_sim/Verilog_RTL/mkDebug_Module.v index bcb67ff..e4eae66 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkDebug_Module.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkDebug_Module.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // @@ -10,7 +10,9 @@ // dmi_read_data O 32 // RDY_dmi_read_data O 1 // RDY_dmi_write O 1 -// RDY_hart0_get_reset_req_get O 1 reg +// hart0_reset_client_request_get O 1 reg +// RDY_hart0_reset_client_request_get O 1 reg +// RDY_hart0_reset_client_response_put O 1 reg // hart0_client_run_halt_request_get O 1 reg // RDY_hart0_client_run_halt_request_get O 1 reg // RDY_hart0_client_run_halt_response_put O 1 reg @@ -25,8 +27,10 @@ // hart0_csr_mem_client_request_get O 77 reg // RDY_hart0_csr_mem_client_request_get O 1 reg // RDY_hart0_csr_mem_client_response_put O 1 reg -// RDY_get_ndm_reset_req_get O 1 reg -// master_awvalid O 1 +// ndm_reset_client_request_get O 1 reg +// RDY_ndm_reset_client_request_get O 1 reg +// RDY_ndm_reset_client_response_put O 1 reg +// master_awvalid O 1 reg // master_awid O 4 reg // master_awaddr O 64 reg // master_awlen O 8 reg @@ -37,13 +41,12 @@ // master_awprot O 3 reg // master_awqos O 4 reg // master_awregion O 4 reg -// master_wvalid O 1 -// master_wid O 4 reg +// master_wvalid O 1 reg // master_wdata O 64 reg // master_wstrb O 8 reg // master_wlast O 1 reg -// master_bready O 1 const -// master_arvalid O 1 +// master_bready O 1 reg +// master_arvalid O 1 reg // master_arid O 4 reg // master_araddr O 64 reg // master_arlen O 8 reg @@ -54,16 +57,18 @@ // master_arprot O 3 reg // master_arqos O 4 reg // master_arregion O 4 reg -// master_rready O 1 +// master_rready O 1 reg // CLK I 1 clock // RST_N I 1 reset // dmi_read_addr_dm_addr I 7 // dmi_write_dm_addr I 7 // dmi_write_dm_word I 32 +// hart0_reset_client_response_put I 1 reg // hart0_client_run_halt_response_put I 1 reg // hart0_gpr_mem_client_response_put I 65 reg // hart0_fpr_mem_client_response_put I 65 reg // hart0_csr_mem_client_response_put I 65 reg +// ndm_reset_client_response_put I 1 reg // master_awready I 1 // master_wready I 1 // master_bvalid I 1 @@ -77,28 +82,24 @@ // master_rlast I 1 reg // EN_dmi_read_addr I 1 // EN_dmi_write I 1 -// EN_hart0_get_reset_req_get I 1 +// EN_hart0_reset_client_response_put I 1 // EN_hart0_client_run_halt_response_put I 1 // EN_hart0_gpr_mem_client_response_put I 1 // EN_hart0_fpr_mem_client_response_put I 1 // EN_hart0_csr_mem_client_response_put I 1 -// EN_get_ndm_reset_req_get I 1 +// EN_ndm_reset_client_response_put I 1 // EN_dmi_read_data I 1 +// EN_hart0_reset_client_request_get I 1 // EN_hart0_client_run_halt_request_get I 1 // EN_hart0_get_other_req_get I 1 // EN_hart0_gpr_mem_client_request_get I 1 // EN_hart0_fpr_mem_client_request_get I 1 // EN_hart0_csr_mem_client_request_get I 1 +// EN_ndm_reset_client_request_get I 1 // // Combinational paths from inputs to outputs: -// (dmi_read_addr_dm_addr, -// master_arready, -// EN_dmi_read_addr) -> RDY_dmi_read_data -// (dmi_read_addr_dm_addr, -// master_arready, -// EN_dmi_read_addr, -// EN_dmi_read_data) -> dmi_read_data -// (master_awready, master_wready, master_arready) -> RDY_dmi_write +// (dmi_read_addr_dm_addr, EN_dmi_read_addr) -> RDY_dmi_read_data +// (dmi_read_addr_dm_addr, EN_dmi_read_addr, EN_dmi_read_data) -> dmi_read_data // // @@ -131,8 +132,13 @@ module mkDebug_Module(CLK, EN_dmi_write, RDY_dmi_write, - EN_hart0_get_reset_req_get, - RDY_hart0_get_reset_req_get, + EN_hart0_reset_client_request_get, + hart0_reset_client_request_get, + RDY_hart0_reset_client_request_get, + + hart0_reset_client_response_put, + EN_hart0_reset_client_response_put, + RDY_hart0_reset_client_response_put, EN_hart0_client_run_halt_request_get, hart0_client_run_halt_request_get, @@ -170,8 +176,13 @@ module mkDebug_Module(CLK, EN_hart0_csr_mem_client_response_put, RDY_hart0_csr_mem_client_response_put, - EN_get_ndm_reset_req_get, - RDY_get_ndm_reset_req_get, + EN_ndm_reset_client_request_get, + ndm_reset_client_request_get, + RDY_ndm_reset_client_request_get, + + ndm_reset_client_response_put, + EN_ndm_reset_client_response_put, + RDY_ndm_reset_client_response_put, master_awvalid, @@ -199,8 +210,6 @@ module mkDebug_Module(CLK, master_wvalid, - master_wid, - master_wdata, master_wstrb, @@ -265,9 +274,15 @@ module mkDebug_Module(CLK, input EN_dmi_write; output RDY_dmi_write; - // action method hart0_get_reset_req_get - input EN_hart0_get_reset_req_get; - output RDY_hart0_get_reset_req_get; + // actionvalue method hart0_reset_client_request_get + input EN_hart0_reset_client_request_get; + output hart0_reset_client_request_get; + output RDY_hart0_reset_client_request_get; + + // action method hart0_reset_client_response_put + input hart0_reset_client_response_put; + input EN_hart0_reset_client_response_put; + output RDY_hart0_reset_client_response_put; // actionvalue method hart0_client_run_halt_request_get input EN_hart0_client_run_halt_request_get; @@ -314,9 +329,15 @@ module mkDebug_Module(CLK, input EN_hart0_csr_mem_client_response_put; output RDY_hart0_csr_mem_client_response_put; - // action method get_ndm_reset_req_get - input EN_get_ndm_reset_req_get; - output RDY_get_ndm_reset_req_get; + // actionvalue method ndm_reset_client_request_get + input EN_ndm_reset_client_request_get; + output ndm_reset_client_request_get; + output RDY_ndm_reset_client_request_get; + + // action method ndm_reset_client_response_put + input ndm_reset_client_response_put; + input EN_ndm_reset_client_response_put; + output RDY_ndm_reset_client_response_put; // value method master_m_awvalid output master_awvalid; @@ -359,9 +380,6 @@ module mkDebug_Module(CLK, // value method master_m_wvalid output master_wvalid; - // value method master_m_wid - output [3 : 0] master_wid; - // value method master_m_wdata output [63 : 0] master_wdata; @@ -447,14 +465,12 @@ module mkDebug_Module(CLK, master_awcache, master_awid, master_awqos, - master_awregion, - master_wid; + master_awregion; wire [2 : 0] master_arprot, master_arsize, master_awprot, master_awsize; wire [1 : 0] master_arburst, master_awburst; wire RDY_dmi_read_addr, RDY_dmi_read_data, RDY_dmi_write, - RDY_get_ndm_reset_req_get, RDY_hart0_client_run_halt_request_get, RDY_hart0_client_run_halt_response_put, RDY_hart0_csr_mem_client_request_get, @@ -462,10 +478,14 @@ module mkDebug_Module(CLK, RDY_hart0_fpr_mem_client_request_get, RDY_hart0_fpr_mem_client_response_put, RDY_hart0_get_other_req_get, - RDY_hart0_get_reset_req_get, RDY_hart0_gpr_mem_client_request_get, RDY_hart0_gpr_mem_client_response_put, + RDY_hart0_reset_client_request_get, + RDY_hart0_reset_client_response_put, + RDY_ndm_reset_client_request_get, + RDY_ndm_reset_client_response_put, hart0_client_run_halt_request_get, + hart0_reset_client_request_get, master_arlock, master_arvalid, master_awlock, @@ -473,7 +493,8 @@ module mkDebug_Module(CLK, master_bready, master_rready, master_wlast, - master_wvalid; + master_wvalid, + ndm_reset_client_request_get; // inlined wires wire [7 : 0] f_read_addr_rv$port0__write_1, @@ -517,22 +538,30 @@ module mkDebug_Module(CLK, wire [6 : 0] dm_run_control$av_read_dm_addr, dm_run_control$write_dm_addr; wire [3 : 0] dm_run_control$hart0_get_other_req_get; wire dm_run_control$EN_av_read, - dm_run_control$EN_get_ndm_reset_req_get, dm_run_control$EN_hart0_client_run_halt_request_get, dm_run_control$EN_hart0_client_run_halt_response_put, dm_run_control$EN_hart0_get_other_req_get, - dm_run_control$EN_hart0_get_reset_req_get, + dm_run_control$EN_hart0_reset_client_request_get, + dm_run_control$EN_hart0_reset_client_response_put, + dm_run_control$EN_ndm_reset_client_request_get, + dm_run_control$EN_ndm_reset_client_response_put, dm_run_control$EN_reset, dm_run_control$EN_write, - dm_run_control$RDY_get_ndm_reset_req_get, dm_run_control$RDY_hart0_client_run_halt_request_get, dm_run_control$RDY_hart0_client_run_halt_response_put, dm_run_control$RDY_hart0_get_other_req_get, - dm_run_control$RDY_hart0_get_reset_req_get, + dm_run_control$RDY_hart0_reset_client_request_get, + dm_run_control$RDY_hart0_reset_client_response_put, + dm_run_control$RDY_ndm_reset_client_request_get, + dm_run_control$RDY_ndm_reset_client_response_put, dm_run_control$RDY_write, dm_run_control$dmactive, dm_run_control$hart0_client_run_halt_request_get, - dm_run_control$hart0_client_run_halt_response_put; + dm_run_control$hart0_client_run_halt_response_put, + dm_run_control$hart0_reset_client_request_get, + dm_run_control$hart0_reset_client_response_put, + dm_run_control$ndm_reset_client_request_get, + dm_run_control$ndm_reset_client_response_put; // ports of submodule dm_system_bus wire [63 : 0] dm_system_bus$master_araddr, @@ -553,8 +582,7 @@ module mkDebug_Module(CLK, dm_system_bus$master_awqos, dm_system_bus$master_awregion, dm_system_bus$master_bid, - dm_system_bus$master_rid, - dm_system_bus$master_wid; + dm_system_bus$master_rid; wire [2 : 0] dm_system_bus$master_arprot, dm_system_bus$master_arsize, dm_system_bus$master_awprot, @@ -588,7 +616,6 @@ module mkDebug_Module(CLK, CAN_FIRE_dmi_read_addr, CAN_FIRE_dmi_read_data, CAN_FIRE_dmi_write, - CAN_FIRE_get_ndm_reset_req_get, CAN_FIRE_hart0_client_run_halt_request_get, CAN_FIRE_hart0_client_run_halt_response_put, CAN_FIRE_hart0_csr_mem_client_request_get, @@ -596,19 +623,21 @@ module mkDebug_Module(CLK, CAN_FIRE_hart0_fpr_mem_client_request_get, CAN_FIRE_hart0_fpr_mem_client_response_put, CAN_FIRE_hart0_get_other_req_get, - CAN_FIRE_hart0_get_reset_req_get, CAN_FIRE_hart0_gpr_mem_client_request_get, CAN_FIRE_hart0_gpr_mem_client_response_put, + CAN_FIRE_hart0_reset_client_request_get, + CAN_FIRE_hart0_reset_client_response_put, CAN_FIRE_master_m_arready, CAN_FIRE_master_m_awready, CAN_FIRE_master_m_bvalid, CAN_FIRE_master_m_rvalid, CAN_FIRE_master_m_wready, + CAN_FIRE_ndm_reset_client_request_get, + CAN_FIRE_ndm_reset_client_response_put, WILL_FIRE_RL_rl_reset, WILL_FIRE_dmi_read_addr, WILL_FIRE_dmi_read_data, WILL_FIRE_dmi_write, - WILL_FIRE_get_ndm_reset_req_get, WILL_FIRE_hart0_client_run_halt_request_get, WILL_FIRE_hart0_client_run_halt_response_put, WILL_FIRE_hart0_csr_mem_client_request_get, @@ -616,19 +645,22 @@ module mkDebug_Module(CLK, WILL_FIRE_hart0_fpr_mem_client_request_get, WILL_FIRE_hart0_fpr_mem_client_response_put, WILL_FIRE_hart0_get_other_req_get, - WILL_FIRE_hart0_get_reset_req_get, WILL_FIRE_hart0_gpr_mem_client_request_get, WILL_FIRE_hart0_gpr_mem_client_response_put, + WILL_FIRE_hart0_reset_client_request_get, + WILL_FIRE_hart0_reset_client_response_put, WILL_FIRE_master_m_arready, WILL_FIRE_master_m_awready, WILL_FIRE_master_m_bvalid, WILL_FIRE_master_m_rvalid, - WILL_FIRE_master_m_wready; + WILL_FIRE_master_m_wready, + WILL_FIRE_ndm_reset_client_request_get, + WILL_FIRE_ndm_reset_client_response_put; // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h887; - reg [31 : 0] v__h881; + reg [31 : 0] v__h911; + reg [31 : 0] v__h905; // synopsys translate_on // action method dmi_read_addr @@ -705,12 +737,23 @@ module mkDebug_Module(CLK, dm_run_control$RDY_write && dm_system_bus$RDY_write ; assign WILL_FIRE_dmi_write = EN_dmi_write ; - // action method hart0_get_reset_req_get - assign RDY_hart0_get_reset_req_get = - dm_run_control$RDY_hart0_get_reset_req_get ; - assign CAN_FIRE_hart0_get_reset_req_get = - dm_run_control$RDY_hart0_get_reset_req_get ; - assign WILL_FIRE_hart0_get_reset_req_get = EN_hart0_get_reset_req_get ; + // actionvalue method hart0_reset_client_request_get + assign hart0_reset_client_request_get = + dm_run_control$hart0_reset_client_request_get ; + assign RDY_hart0_reset_client_request_get = + dm_run_control$RDY_hart0_reset_client_request_get ; + assign CAN_FIRE_hart0_reset_client_request_get = + dm_run_control$RDY_hart0_reset_client_request_get ; + assign WILL_FIRE_hart0_reset_client_request_get = + EN_hart0_reset_client_request_get ; + + // action method hart0_reset_client_response_put + assign RDY_hart0_reset_client_response_put = + dm_run_control$RDY_hart0_reset_client_response_put ; + assign CAN_FIRE_hart0_reset_client_response_put = + dm_run_control$RDY_hart0_reset_client_response_put ; + assign WILL_FIRE_hart0_reset_client_response_put = + EN_hart0_reset_client_response_put ; // actionvalue method hart0_client_run_halt_request_get assign hart0_client_run_halt_request_get = @@ -792,12 +835,23 @@ module mkDebug_Module(CLK, assign WILL_FIRE_hart0_csr_mem_client_response_put = EN_hart0_csr_mem_client_response_put ; - // action method get_ndm_reset_req_get - assign RDY_get_ndm_reset_req_get = - dm_run_control$RDY_get_ndm_reset_req_get ; - assign CAN_FIRE_get_ndm_reset_req_get = - dm_run_control$RDY_get_ndm_reset_req_get ; - assign WILL_FIRE_get_ndm_reset_req_get = EN_get_ndm_reset_req_get ; + // actionvalue method ndm_reset_client_request_get + assign ndm_reset_client_request_get = + dm_run_control$ndm_reset_client_request_get ; + assign RDY_ndm_reset_client_request_get = + dm_run_control$RDY_ndm_reset_client_request_get ; + assign CAN_FIRE_ndm_reset_client_request_get = + dm_run_control$RDY_ndm_reset_client_request_get ; + assign WILL_FIRE_ndm_reset_client_request_get = + EN_ndm_reset_client_request_get ; + + // action method ndm_reset_client_response_put + assign RDY_ndm_reset_client_response_put = + dm_run_control$RDY_ndm_reset_client_response_put ; + assign CAN_FIRE_ndm_reset_client_response_put = + dm_run_control$RDY_ndm_reset_client_response_put ; + assign WILL_FIRE_ndm_reset_client_response_put = + EN_ndm_reset_client_response_put ; // value method master_m_awvalid assign master_awvalid = dm_system_bus$master_awvalid ; @@ -839,9 +893,6 @@ module mkDebug_Module(CLK, // value method master_m_wvalid assign master_wvalid = dm_system_bus$master_wvalid ; - // value method master_m_wid - assign master_wid = dm_system_bus$master_wid ; - // value method master_m_wdata assign master_wdata = dm_system_bus$master_wdata ; @@ -943,29 +994,37 @@ module mkDebug_Module(CLK, .RST_N(RST_N), .av_read_dm_addr(dm_run_control$av_read_dm_addr), .hart0_client_run_halt_response_put(dm_run_control$hart0_client_run_halt_response_put), + .hart0_reset_client_response_put(dm_run_control$hart0_reset_client_response_put), + .ndm_reset_client_response_put(dm_run_control$ndm_reset_client_response_put), .write_dm_addr(dm_run_control$write_dm_addr), .write_dm_word(dm_run_control$write_dm_word), .EN_reset(dm_run_control$EN_reset), .EN_av_read(dm_run_control$EN_av_read), .EN_write(dm_run_control$EN_write), - .EN_hart0_get_reset_req_get(dm_run_control$EN_hart0_get_reset_req_get), + .EN_hart0_reset_client_request_get(dm_run_control$EN_hart0_reset_client_request_get), + .EN_hart0_reset_client_response_put(dm_run_control$EN_hart0_reset_client_response_put), .EN_hart0_client_run_halt_request_get(dm_run_control$EN_hart0_client_run_halt_request_get), .EN_hart0_client_run_halt_response_put(dm_run_control$EN_hart0_client_run_halt_response_put), .EN_hart0_get_other_req_get(dm_run_control$EN_hart0_get_other_req_get), - .EN_get_ndm_reset_req_get(dm_run_control$EN_get_ndm_reset_req_get), + .EN_ndm_reset_client_request_get(dm_run_control$EN_ndm_reset_client_request_get), + .EN_ndm_reset_client_response_put(dm_run_control$EN_ndm_reset_client_response_put), .dmactive(dm_run_control$dmactive), .RDY_dmactive(), .RDY_reset(), .av_read(dm_run_control$av_read), .RDY_av_read(), .RDY_write(dm_run_control$RDY_write), - .RDY_hart0_get_reset_req_get(dm_run_control$RDY_hart0_get_reset_req_get), + .hart0_reset_client_request_get(dm_run_control$hart0_reset_client_request_get), + .RDY_hart0_reset_client_request_get(dm_run_control$RDY_hart0_reset_client_request_get), + .RDY_hart0_reset_client_response_put(dm_run_control$RDY_hart0_reset_client_response_put), .hart0_client_run_halt_request_get(dm_run_control$hart0_client_run_halt_request_get), .RDY_hart0_client_run_halt_request_get(dm_run_control$RDY_hart0_client_run_halt_request_get), .RDY_hart0_client_run_halt_response_put(dm_run_control$RDY_hart0_client_run_halt_response_put), .hart0_get_other_req_get(dm_run_control$hart0_get_other_req_get), .RDY_hart0_get_other_req_get(dm_run_control$RDY_hart0_get_other_req_get), - .RDY_get_ndm_reset_req_get(dm_run_control$RDY_get_ndm_reset_req_get)); + .ndm_reset_client_request_get(dm_run_control$ndm_reset_client_request_get), + .RDY_ndm_reset_client_request_get(dm_run_control$RDY_ndm_reset_client_request_get), + .RDY_ndm_reset_client_response_put(dm_run_control$RDY_ndm_reset_client_response_put)); // submodule dm_system_bus mkDM_System_Bus dm_system_bus(.CLK(CLK), @@ -1003,7 +1062,6 @@ module mkDebug_Module(CLK, .master_awqos(dm_system_bus$master_awqos), .master_awregion(dm_system_bus$master_awregion), .master_wvalid(dm_system_bus$master_wvalid), - .master_wid(dm_system_bus$master_wid), .master_wdata(dm_system_bus$master_wdata), .master_wstrb(dm_system_bus$master_wstrb), .master_wlast(dm_system_bus$master_wlast), @@ -1100,6 +1158,10 @@ module mkDebug_Module(CLK, assign dm_run_control$av_read_dm_addr = f_read_addr_rv$port1__read[6:0] ; assign dm_run_control$hart0_client_run_halt_response_put = hart0_client_run_halt_response_put ; + assign dm_run_control$hart0_reset_client_response_put = + hart0_reset_client_response_put ; + assign dm_run_control$ndm_reset_client_response_put = + ndm_reset_client_response_put ; assign dm_run_control$write_dm_addr = dmi_write_dm_addr ; assign dm_run_control$write_dm_word = dmi_write_dm_word ; assign dm_run_control$EN_reset = WILL_FIRE_RL_rl_reset ; @@ -1128,15 +1190,20 @@ module mkDebug_Module(CLK, dmi_write_dm_addr == 7'h40 || dmi_write_dm_addr == 7'h5F || dmi_write_dm_addr == 7'h60) ; - assign dm_run_control$EN_hart0_get_reset_req_get = - EN_hart0_get_reset_req_get ; + assign dm_run_control$EN_hart0_reset_client_request_get = + EN_hart0_reset_client_request_get ; + assign dm_run_control$EN_hart0_reset_client_response_put = + EN_hart0_reset_client_response_put ; assign dm_run_control$EN_hart0_client_run_halt_request_get = EN_hart0_client_run_halt_request_get ; assign dm_run_control$EN_hart0_client_run_halt_response_put = EN_hart0_client_run_halt_response_put ; assign dm_run_control$EN_hart0_get_other_req_get = EN_hart0_get_other_req_get ; - assign dm_run_control$EN_get_ndm_reset_req_get = EN_get_ndm_reset_req_get ; + assign dm_run_control$EN_ndm_reset_client_request_get = + EN_ndm_reset_client_request_get ; + assign dm_run_control$EN_ndm_reset_client_response_put = + EN_ndm_reset_client_response_put ; // submodule dm_system_bus assign dm_system_bus$av_read_dm_addr = f_read_addr_rv$port1__read[6:0] ; @@ -1208,12 +1275,12 @@ module mkDebug_Module(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_reset) begin - v__h887 = $stime; + v__h911 = $stime; #0; end - v__h881 = v__h887 / 32'd10; + v__h905 = v__h911 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset) $display("%0d: Debug_Module reset", v__h881); + if (WILL_FIRE_RL_rl_reset) $display("%0d: Debug_Module reset", v__h905); end // synopsys translate_on endmodule // mkDebug_Module diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkDirPredictor.v b/src_SSITH_P3_sim/Verilog_RTL/mkDirPredictor.v index cafcd0d..7eb91a4 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkDirPredictor.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkDirPredictor.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkDivExecQ.v b/src_SSITH_P3_sim/Verilog_RTL/mkDivExecQ.v index 8c0f2fa..d7ed640 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkDivExecQ.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkDivExecQ.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkDoubleDiv.v b/src_SSITH_P3_sim/Verilog_RTL/mkDoubleDiv.v index bcc0dc5..4465002 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkDoubleDiv.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkDoubleDiv.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkDoubleFMA.v b/src_SSITH_P3_sim/Verilog_RTL/mkDoubleFMA.v index 8fa4092..f127f57 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkDoubleFMA.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkDoubleFMA.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkDoubleSqrt.v b/src_SSITH_P3_sim/Verilog_RTL/mkDoubleSqrt.v index 2fdf4a2..a059588 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkDoubleSqrt.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkDoubleSqrt.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkDummyStoreBuffer.v b/src_SSITH_P3_sim/Verilog_RTL/mkDummyStoreBuffer.v index 2e3bb3a..4dee396 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkDummyStoreBuffer.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkDummyStoreBuffer.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkEpochManager.v b/src_SSITH_P3_sim/Verilog_RTL/mkEpochManager.v index 8c8805a..c0c0da5 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkEpochManager.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkEpochManager.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkFabric_2x3.v b/src_SSITH_P3_sim/Verilog_RTL/mkFabric_2x3.v index fdb8f0f..aec57ab 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkFabric_2x3.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkFabric_2x3.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // @@ -42,7 +42,6 @@ // v_to_slaves_0_awqos O 4 reg // v_to_slaves_0_awregion O 4 reg // v_to_slaves_0_wvalid O 1 reg -// v_to_slaves_0_wid O 4 reg // v_to_slaves_0_wdata O 64 reg // v_to_slaves_0_wstrb O 8 reg // v_to_slaves_0_wlast O 1 reg @@ -71,7 +70,6 @@ // v_to_slaves_1_awqos O 4 reg // v_to_slaves_1_awregion O 4 reg // v_to_slaves_1_wvalid O 1 reg -// v_to_slaves_1_wid O 4 reg // v_to_slaves_1_wdata O 64 reg // v_to_slaves_1_wstrb O 8 reg // v_to_slaves_1_wlast O 1 reg @@ -100,7 +98,6 @@ // v_to_slaves_2_awqos O 4 reg // v_to_slaves_2_awregion O 4 reg // v_to_slaves_2_wvalid O 1 reg -// v_to_slaves_2_wid O 4 reg // v_to_slaves_2_wdata O 64 reg // v_to_slaves_2_wstrb O 8 reg // v_to_slaves_2_wlast O 1 reg @@ -132,7 +129,6 @@ // v_from_masters_0_awqos I 4 reg // v_from_masters_0_awregion I 4 reg // v_from_masters_0_wvalid I 1 -// v_from_masters_0_wid I 4 reg // v_from_masters_0_wdata I 64 reg // v_from_masters_0_wstrb I 8 reg // v_from_masters_0_wlast I 1 reg @@ -161,7 +157,6 @@ // v_from_masters_1_awqos I 4 reg // v_from_masters_1_awregion I 4 reg // v_from_masters_1_wvalid I 1 -// v_from_masters_1_wid I 4 reg // v_from_masters_1_wdata I 64 reg // v_from_masters_1_wstrb I 8 reg // v_from_masters_1_wlast I 1 reg @@ -256,7 +251,6 @@ module mkFabric_2x3(CLK, v_from_masters_0_awready, v_from_masters_0_wvalid, - v_from_masters_0_wid, v_from_masters_0_wdata, v_from_masters_0_wstrb, v_from_masters_0_wlast, @@ -312,7 +306,6 @@ module mkFabric_2x3(CLK, v_from_masters_1_awready, v_from_masters_1_wvalid, - v_from_masters_1_wid, v_from_masters_1_wdata, v_from_masters_1_wstrb, v_from_masters_1_wlast, @@ -379,8 +372,6 @@ module mkFabric_2x3(CLK, v_to_slaves_0_wvalid, - v_to_slaves_0_wid, - v_to_slaves_0_wdata, v_to_slaves_0_wstrb, @@ -453,8 +444,6 @@ module mkFabric_2x3(CLK, v_to_slaves_1_wvalid, - v_to_slaves_1_wid, - v_to_slaves_1_wdata, v_to_slaves_1_wstrb, @@ -527,8 +516,6 @@ module mkFabric_2x3(CLK, v_to_slaves_2_wvalid, - v_to_slaves_2_wid, - v_to_slaves_2_wdata, v_to_slaves_2_wstrb, @@ -604,7 +591,6 @@ module mkFabric_2x3(CLK, // action method v_from_masters_0_m_wvalid input v_from_masters_0_wvalid; - input [3 : 0] v_from_masters_0_wid; input [63 : 0] v_from_masters_0_wdata; input [7 : 0] v_from_masters_0_wstrb; input v_from_masters_0_wlast; @@ -680,7 +666,6 @@ module mkFabric_2x3(CLK, // action method v_from_masters_1_m_wvalid input v_from_masters_1_wvalid; - input [3 : 0] v_from_masters_1_wid; input [63 : 0] v_from_masters_1_wdata; input [7 : 0] v_from_masters_1_wstrb; input v_from_masters_1_wlast; @@ -779,9 +764,6 @@ module mkFabric_2x3(CLK, // value method v_to_slaves_0_m_wvalid output v_to_slaves_0_wvalid; - // value method v_to_slaves_0_m_wid - output [3 : 0] v_to_slaves_0_wid; - // value method v_to_slaves_0_m_wdata output [63 : 0] v_to_slaves_0_wdata; @@ -893,9 +875,6 @@ module mkFabric_2x3(CLK, // value method v_to_slaves_1_m_wvalid output v_to_slaves_1_wvalid; - // value method v_to_slaves_1_m_wid - output [3 : 0] v_to_slaves_1_wid; - // value method v_to_slaves_1_m_wdata output [63 : 0] v_to_slaves_1_wdata; @@ -1007,9 +986,6 @@ module mkFabric_2x3(CLK, // value method v_to_slaves_2_m_wvalid output v_to_slaves_2_wvalid; - // value method v_to_slaves_2_m_wid - output [3 : 0] v_to_slaves_2_wid; - // value method v_to_slaves_2_m_wdata output [63 : 0] v_to_slaves_2_wdata; @@ -1113,7 +1089,6 @@ module mkFabric_2x3(CLK, v_to_slaves_0_awid, v_to_slaves_0_awqos, v_to_slaves_0_awregion, - v_to_slaves_0_wid, v_to_slaves_1_arcache, v_to_slaves_1_arid, v_to_slaves_1_arqos, @@ -1122,7 +1097,6 @@ module mkFabric_2x3(CLK, v_to_slaves_1_awid, v_to_slaves_1_awqos, v_to_slaves_1_awregion, - v_to_slaves_1_wid, v_to_slaves_2_arcache, v_to_slaves_2_arid, v_to_slaves_2_arqos, @@ -1130,8 +1104,7 @@ module mkFabric_2x3(CLK, v_to_slaves_2_awcache, v_to_slaves_2_awid, v_to_slaves_2_awqos, - v_to_slaves_2_awregion, - v_to_slaves_2_wid; + v_to_slaves_2_awregion; wire [2 : 0] v_to_slaves_0_arprot, v_to_slaves_0_arsize, v_to_slaves_0_awprot, @@ -1202,34 +1175,57 @@ module mkFabric_2x3(CLK, reg fabric_rg_reset; wire fabric_rg_reset$D_IN, fabric_rg_reset$EN; - // ports of submodule fabric_v_f_rd_err_id_0 - wire [3 : 0] fabric_v_f_rd_err_id_0$D_IN, fabric_v_f_rd_err_id_0$D_OUT; - wire fabric_v_f_rd_err_id_0$CLR, - fabric_v_f_rd_err_id_0$DEQ, - fabric_v_f_rd_err_id_0$EMPTY_N, - fabric_v_f_rd_err_id_0$ENQ; + // register fabric_v_rg_r_beat_count_0 + reg [7 : 0] fabric_v_rg_r_beat_count_0; + reg [7 : 0] fabric_v_rg_r_beat_count_0$D_IN; + wire fabric_v_rg_r_beat_count_0$EN; - // ports of submodule fabric_v_f_rd_err_id_1 - wire [3 : 0] fabric_v_f_rd_err_id_1$D_IN, fabric_v_f_rd_err_id_1$D_OUT; - wire fabric_v_f_rd_err_id_1$CLR, - fabric_v_f_rd_err_id_1$DEQ, - fabric_v_f_rd_err_id_1$EMPTY_N, - fabric_v_f_rd_err_id_1$ENQ; + // register fabric_v_rg_r_beat_count_1 + reg [7 : 0] fabric_v_rg_r_beat_count_1; + reg [7 : 0] fabric_v_rg_r_beat_count_1$D_IN; + wire fabric_v_rg_r_beat_count_1$EN; - // ports of submodule fabric_v_f_rd_err_user_0 - wire fabric_v_f_rd_err_user_0$CLR, - fabric_v_f_rd_err_user_0$DEQ, - fabric_v_f_rd_err_user_0$EMPTY_N, - fabric_v_f_rd_err_user_0$ENQ; + // register fabric_v_rg_r_beat_count_2 + reg [7 : 0] fabric_v_rg_r_beat_count_2; + reg [7 : 0] fabric_v_rg_r_beat_count_2$D_IN; + wire fabric_v_rg_r_beat_count_2$EN; - // ports of submodule fabric_v_f_rd_err_user_1 - wire fabric_v_f_rd_err_user_1$CLR, - fabric_v_f_rd_err_user_1$DEQ, - fabric_v_f_rd_err_user_1$EMPTY_N, - fabric_v_f_rd_err_user_1$ENQ; + // register fabric_v_rg_r_err_beat_count_0 + reg [7 : 0] fabric_v_rg_r_err_beat_count_0; + wire [7 : 0] fabric_v_rg_r_err_beat_count_0$D_IN; + wire fabric_v_rg_r_err_beat_count_0$EN; + + // register fabric_v_rg_r_err_beat_count_1 + reg [7 : 0] fabric_v_rg_r_err_beat_count_1; + wire [7 : 0] fabric_v_rg_r_err_beat_count_1$D_IN; + wire fabric_v_rg_r_err_beat_count_1$EN; + + // register fabric_v_rg_wd_beat_count_0 + reg [7 : 0] fabric_v_rg_wd_beat_count_0; + wire [7 : 0] fabric_v_rg_wd_beat_count_0$D_IN; + wire fabric_v_rg_wd_beat_count_0$EN; + + // register fabric_v_rg_wd_beat_count_1 + reg [7 : 0] fabric_v_rg_wd_beat_count_1; + wire [7 : 0] fabric_v_rg_wd_beat_count_1$D_IN; + wire fabric_v_rg_wd_beat_count_1$EN; + + // ports of submodule fabric_v_f_rd_err_info_0 + wire [11 : 0] fabric_v_f_rd_err_info_0$D_IN, fabric_v_f_rd_err_info_0$D_OUT; + wire fabric_v_f_rd_err_info_0$CLR, + fabric_v_f_rd_err_info_0$DEQ, + fabric_v_f_rd_err_info_0$EMPTY_N, + fabric_v_f_rd_err_info_0$ENQ; + + // ports of submodule fabric_v_f_rd_err_info_1 + wire [11 : 0] fabric_v_f_rd_err_info_1$D_IN, fabric_v_f_rd_err_info_1$D_OUT; + wire fabric_v_f_rd_err_info_1$CLR, + fabric_v_f_rd_err_info_1$DEQ, + fabric_v_f_rd_err_info_1$EMPTY_N, + fabric_v_f_rd_err_info_1$ENQ; // ports of submodule fabric_v_f_rd_mis_0 - wire [1 : 0] fabric_v_f_rd_mis_0$D_IN, fabric_v_f_rd_mis_0$D_OUT; + wire [8 : 0] fabric_v_f_rd_mis_0$D_IN, fabric_v_f_rd_mis_0$D_OUT; wire fabric_v_f_rd_mis_0$CLR, fabric_v_f_rd_mis_0$DEQ, fabric_v_f_rd_mis_0$EMPTY_N, @@ -1237,7 +1233,7 @@ module mkFabric_2x3(CLK, fabric_v_f_rd_mis_0$FULL_N; // ports of submodule fabric_v_f_rd_mis_1 - wire [1 : 0] fabric_v_f_rd_mis_1$D_IN, fabric_v_f_rd_mis_1$D_OUT; + wire [8 : 0] fabric_v_f_rd_mis_1$D_IN, fabric_v_f_rd_mis_1$D_OUT; wire fabric_v_f_rd_mis_1$CLR, fabric_v_f_rd_mis_1$DEQ, fabric_v_f_rd_mis_1$EMPTY_N, @@ -1245,7 +1241,7 @@ module mkFabric_2x3(CLK, fabric_v_f_rd_mis_1$FULL_N; // ports of submodule fabric_v_f_rd_mis_2 - wire [1 : 0] fabric_v_f_rd_mis_2$D_IN, fabric_v_f_rd_mis_2$D_OUT; + wire [8 : 0] fabric_v_f_rd_mis_2$D_IN, fabric_v_f_rd_mis_2$D_OUT; wire fabric_v_f_rd_mis_2$CLR, fabric_v_f_rd_mis_2$DEQ, fabric_v_f_rd_mis_2$EMPTY_N, @@ -1270,52 +1266,61 @@ module mkFabric_2x3(CLK, fabric_v_f_rd_sjs_1$ENQ, fabric_v_f_rd_sjs_1$FULL_N; - // ports of submodule fabric_v_f_wr_err_id_0 - wire [3 : 0] fabric_v_f_wr_err_id_0$D_IN, fabric_v_f_wr_err_id_0$D_OUT; - wire fabric_v_f_wr_err_id_0$CLR, - fabric_v_f_wr_err_id_0$DEQ, - fabric_v_f_wr_err_id_0$EMPTY_N, - fabric_v_f_wr_err_id_0$ENQ; + // ports of submodule fabric_v_f_wd_tasks_0 + reg [9 : 0] fabric_v_f_wd_tasks_0$D_IN; + wire [9 : 0] fabric_v_f_wd_tasks_0$D_OUT; + wire fabric_v_f_wd_tasks_0$CLR, + fabric_v_f_wd_tasks_0$DEQ, + fabric_v_f_wd_tasks_0$EMPTY_N, + fabric_v_f_wd_tasks_0$ENQ, + fabric_v_f_wd_tasks_0$FULL_N; - // ports of submodule fabric_v_f_wr_err_id_1 - wire [3 : 0] fabric_v_f_wr_err_id_1$D_IN, fabric_v_f_wr_err_id_1$D_OUT; - wire fabric_v_f_wr_err_id_1$CLR, - fabric_v_f_wr_err_id_1$DEQ, - fabric_v_f_wr_err_id_1$EMPTY_N, - fabric_v_f_wr_err_id_1$ENQ; + // ports of submodule fabric_v_f_wd_tasks_1 + reg [9 : 0] fabric_v_f_wd_tasks_1$D_IN; + wire [9 : 0] fabric_v_f_wd_tasks_1$D_OUT; + wire fabric_v_f_wd_tasks_1$CLR, + fabric_v_f_wd_tasks_1$DEQ, + fabric_v_f_wd_tasks_1$EMPTY_N, + fabric_v_f_wd_tasks_1$ENQ, + fabric_v_f_wd_tasks_1$FULL_N; - // ports of submodule fabric_v_f_wr_err_user_0 - wire fabric_v_f_wr_err_user_0$CLR, - fabric_v_f_wr_err_user_0$DEQ, - fabric_v_f_wr_err_user_0$EMPTY_N, - fabric_v_f_wr_err_user_0$ENQ; + // ports of submodule fabric_v_f_wr_err_info_0 + wire [3 : 0] fabric_v_f_wr_err_info_0$D_IN, fabric_v_f_wr_err_info_0$D_OUT; + wire fabric_v_f_wr_err_info_0$CLR, + fabric_v_f_wr_err_info_0$DEQ, + fabric_v_f_wr_err_info_0$EMPTY_N, + fabric_v_f_wr_err_info_0$ENQ; - // ports of submodule fabric_v_f_wr_err_user_1 - wire fabric_v_f_wr_err_user_1$CLR, - fabric_v_f_wr_err_user_1$DEQ, - fabric_v_f_wr_err_user_1$EMPTY_N, - fabric_v_f_wr_err_user_1$ENQ; + // ports of submodule fabric_v_f_wr_err_info_1 + wire [3 : 0] fabric_v_f_wr_err_info_1$D_IN, fabric_v_f_wr_err_info_1$D_OUT; + wire fabric_v_f_wr_err_info_1$CLR, + fabric_v_f_wr_err_info_1$DEQ, + fabric_v_f_wr_err_info_1$EMPTY_N, + fabric_v_f_wr_err_info_1$ENQ; // ports of submodule fabric_v_f_wr_mis_0 - wire [1 : 0] fabric_v_f_wr_mis_0$D_IN, fabric_v_f_wr_mis_0$D_OUT; wire fabric_v_f_wr_mis_0$CLR, fabric_v_f_wr_mis_0$DEQ, + fabric_v_f_wr_mis_0$D_IN, + fabric_v_f_wr_mis_0$D_OUT, fabric_v_f_wr_mis_0$EMPTY_N, fabric_v_f_wr_mis_0$ENQ, fabric_v_f_wr_mis_0$FULL_N; // ports of submodule fabric_v_f_wr_mis_1 - wire [1 : 0] fabric_v_f_wr_mis_1$D_IN, fabric_v_f_wr_mis_1$D_OUT; wire fabric_v_f_wr_mis_1$CLR, fabric_v_f_wr_mis_1$DEQ, + fabric_v_f_wr_mis_1$D_IN, + fabric_v_f_wr_mis_1$D_OUT, fabric_v_f_wr_mis_1$EMPTY_N, fabric_v_f_wr_mis_1$ENQ, fabric_v_f_wr_mis_1$FULL_N; // ports of submodule fabric_v_f_wr_mis_2 - wire [1 : 0] fabric_v_f_wr_mis_2$D_IN, fabric_v_f_wr_mis_2$D_OUT; wire fabric_v_f_wr_mis_2$CLR, fabric_v_f_wr_mis_2$DEQ, + fabric_v_f_wr_mis_2$D_IN, + fabric_v_f_wr_mis_2$D_OUT, fabric_v_f_wr_mis_2$EMPTY_N, fabric_v_f_wr_mis_2$ENQ, fabric_v_f_wr_mis_2$FULL_N; @@ -1366,7 +1371,7 @@ module mkFabric_2x3(CLK, fabric_xactors_from_masters_0_f_wr_addr$FULL_N; // ports of submodule fabric_xactors_from_masters_0_f_wr_data - wire [76 : 0] fabric_xactors_from_masters_0_f_wr_data$D_IN, + wire [72 : 0] fabric_xactors_from_masters_0_f_wr_data$D_IN, fabric_xactors_from_masters_0_f_wr_data$D_OUT; wire fabric_xactors_from_masters_0_f_wr_data$CLR, fabric_xactors_from_masters_0_f_wr_data$DEQ, @@ -1411,7 +1416,7 @@ module mkFabric_2x3(CLK, fabric_xactors_from_masters_1_f_wr_addr$FULL_N; // ports of submodule fabric_xactors_from_masters_1_f_wr_data - wire [76 : 0] fabric_xactors_from_masters_1_f_wr_data$D_IN, + wire [72 : 0] fabric_xactors_from_masters_1_f_wr_data$D_IN, fabric_xactors_from_masters_1_f_wr_data$D_OUT; wire fabric_xactors_from_masters_1_f_wr_data$CLR, fabric_xactors_from_masters_1_f_wr_data$DEQ, @@ -1456,7 +1461,7 @@ module mkFabric_2x3(CLK, fabric_xactors_to_slaves_0_f_wr_addr$FULL_N; // ports of submodule fabric_xactors_to_slaves_0_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_0_f_wr_data$D_IN, + wire [72 : 0] fabric_xactors_to_slaves_0_f_wr_data$D_IN, fabric_xactors_to_slaves_0_f_wr_data$D_OUT; wire fabric_xactors_to_slaves_0_f_wr_data$CLR, fabric_xactors_to_slaves_0_f_wr_data$DEQ, @@ -1501,7 +1506,7 @@ module mkFabric_2x3(CLK, fabric_xactors_to_slaves_1_f_wr_addr$FULL_N; // ports of submodule fabric_xactors_to_slaves_1_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_1_f_wr_data$D_IN, + wire [72 : 0] fabric_xactors_to_slaves_1_f_wr_data$D_IN, fabric_xactors_to_slaves_1_f_wr_data$D_OUT; wire fabric_xactors_to_slaves_1_f_wr_data$CLR, fabric_xactors_to_slaves_1_f_wr_data$DEQ, @@ -1546,7 +1551,7 @@ module mkFabric_2x3(CLK, fabric_xactors_to_slaves_2_f_wr_addr$FULL_N; // ports of submodule fabric_xactors_to_slaves_2_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_2_f_wr_data$D_IN, + wire [72 : 0] fabric_xactors_to_slaves_2_f_wr_data$D_IN, fabric_xactors_to_slaves_2_f_wr_data$D_OUT; wire fabric_xactors_to_slaves_2_f_wr_data$CLR, fabric_xactors_to_slaves_2_f_wr_data$DEQ, @@ -1602,6 +1607,8 @@ module mkFabric_2x3(CLK, CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3, CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4, CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5, + CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data, + CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1, CAN_FIRE_reset, CAN_FIRE_set_verbosity, CAN_FIRE_v_from_masters_0_m_arvalid, @@ -1658,6 +1665,8 @@ module mkFabric_2x3(CLK, WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3, WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4, WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5, + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data, + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1, WILL_FIRE_reset, WILL_FIRE_set_verbosity, WILL_FIRE_v_from_masters_0_m_arvalid, @@ -1687,91 +1696,152 @@ module mkFabric_2x3(CLK, WILL_FIRE_v_to_slaves_2_m_wready; // inputs to muxes for submodule ports - wire [70 : 0] MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4, + wire [70 : 0] MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1, + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2, + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3, + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4, MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4; + wire [9 : 0] MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1, + MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2, + MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3, + MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1, + MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2, + MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3; + wire [8 : 0] MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1, + MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2; + wire [7 : 0] MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2, + MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2, + MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2, + MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2, + MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2; wire [5 : 0] MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4, MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4; + wire MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1, + MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1, + MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1; // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h8376; - reg [31 : 0] v__h8854; - reg [31 : 0] v__h9332; - reg [31 : 0] v__h9903; - reg [31 : 0] v__h10365; - reg [31 : 0] v__h10827; - reg [31 : 0] v__h12052; - reg [31 : 0] v__h12404; - reg [31 : 0] v__h12756; - reg [31 : 0] v__h13171; - reg [31 : 0] v__h13499; - reg [31 : 0] v__h13827; - reg [31 : 0] v__h14823; - reg [31 : 0] v__h15116; - reg [31 : 0] v__h15409; - reg [31 : 0] v__h15715; - reg [31 : 0] v__h15982; - reg [31 : 0] v__h16249; - reg [31 : 0] v__h16556; - reg [31 : 0] v__h16823; - reg [31 : 0] v__h17170; - reg [31 : 0] v__h17493; - reg [31 : 0] v__h17816; - reg [31 : 0] v__h18143; - reg [31 : 0] v__h18429; - reg [31 : 0] v__h18715; - reg [31 : 0] v__h19040; - reg [31 : 0] v__h19314; - reg [31 : 0] v__h5509; - reg [31 : 0] v__h5503; - reg [31 : 0] v__h8370; - reg [31 : 0] v__h8848; - reg [31 : 0] v__h9326; - reg [31 : 0] v__h9897; - reg [31 : 0] v__h10359; - reg [31 : 0] v__h10821; - reg [31 : 0] v__h12046; - reg [31 : 0] v__h12398; - reg [31 : 0] v__h12750; - reg [31 : 0] v__h13165; - reg [31 : 0] v__h13493; - reg [31 : 0] v__h13821; - reg [31 : 0] v__h14817; - reg [31 : 0] v__h15110; - reg [31 : 0] v__h15403; - reg [31 : 0] v__h15709; - reg [31 : 0] v__h15976; - reg [31 : 0] v__h16243; - reg [31 : 0] v__h16550; - reg [31 : 0] v__h16817; - reg [31 : 0] v__h17164; - reg [31 : 0] v__h17487; - reg [31 : 0] v__h17810; - reg [31 : 0] v__h18137; - reg [31 : 0] v__h18423; - reg [31 : 0] v__h18709; - reg [31 : 0] v__h19034; - reg [31 : 0] v__h19308; + reg [31 : 0] v__h8785; + reg [31 : 0] v__h9160; + reg [31 : 0] v__h9535; + reg [31 : 0] v__h9980; + reg [31 : 0] v__h10349; + reg [31 : 0] v__h10718; + reg [31 : 0] v__h11990; + reg [31 : 0] v__h12433; + reg [31 : 0] v__h12808; + reg [31 : 0] v__h13100; + reg [31 : 0] v__h13392; + reg [31 : 0] v__h13695; + reg [31 : 0] v__h13961; + reg [31 : 0] v__h14227; + reg [31 : 0] v__h14491; + reg [31 : 0] v__h14717; + reg [31 : 0] v__h15146; + reg [31 : 0] v__h15502; + reg [31 : 0] v__h15858; + reg [31 : 0] v__h16275; + reg [31 : 0] v__h16607; + reg [31 : 0] v__h16939; + reg [31 : 0] v__h17955; + reg [31 : 0] v__h18206; + reg [31 : 0] v__h18581; + reg [31 : 0] v__h18822; + reg [31 : 0] v__h19197; + reg [31 : 0] v__h19438; + reg [31 : 0] v__h19800; + reg [31 : 0] v__h20051; + reg [31 : 0] v__h20381; + reg [31 : 0] v__h20622; + reg [31 : 0] v__h20952; + reg [31 : 0] v__h21193; + reg [31 : 0] v__h21706; + reg [31 : 0] v__h22107; + reg [31 : 0] v__h5833; + reg [31 : 0] v__h5827; + reg [31 : 0] v__h8779; + reg [31 : 0] v__h9154; + reg [31 : 0] v__h9529; + reg [31 : 0] v__h9974; + reg [31 : 0] v__h10343; + reg [31 : 0] v__h10712; + reg [31 : 0] v__h11984; + reg [31 : 0] v__h12427; + reg [31 : 0] v__h12802; + reg [31 : 0] v__h13094; + reg [31 : 0] v__h13386; + reg [31 : 0] v__h13689; + reg [31 : 0] v__h13955; + reg [31 : 0] v__h14221; + reg [31 : 0] v__h14485; + reg [31 : 0] v__h14711; + reg [31 : 0] v__h15140; + reg [31 : 0] v__h15496; + reg [31 : 0] v__h15852; + reg [31 : 0] v__h16269; + reg [31 : 0] v__h16601; + reg [31 : 0] v__h16933; + reg [31 : 0] v__h17949; + reg [31 : 0] v__h18200; + reg [31 : 0] v__h18575; + reg [31 : 0] v__h18816; + reg [31 : 0] v__h19191; + reg [31 : 0] v__h19432; + reg [31 : 0] v__h19794; + reg [31 : 0] v__h20045; + reg [31 : 0] v__h20375; + reg [31 : 0] v__h20616; + reg [31 : 0] v__h20946; + reg [31 : 0] v__h21187; + reg [31 : 0] v__h21700; + reg [31 : 0] v__h22101; // synopsys translate_on // remaining internal signals - wire NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d150, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d155, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d21, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d199, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d204, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d100, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d95, - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d148, - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d18, - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d197, - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d93, - soc_map_m_plic_addr_base__4_ULE_fabric_xactors_ETC___d153, - soc_map_m_plic_addr_base__4_ULE_fabric_xactors_ETC___d202, - soc_map_m_plic_addr_base__4_ULE_fabric_xactors_ETC___d25, - soc_map_m_plic_addr_base__4_ULE_fabric_xactors_ETC___d98; + reg CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1, + CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2; + wire [7 : 0] x__h11895, + x__h12338, + x__h18092, + x__h18718, + x__h19334, + x__h21638, + x__h22039; + wire [1 : 0] IF_fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_ETC___d396, + IF_fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_ETC___d435, + IF_fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_ETC___d474, + x1_avValue_rresp__h18070, + x1_avValue_rresp__h18696, + x1_avValue_rresp__h19312; + wire _dor1fabric_v_f_rd_mis_0$EN_deq, + _dor1fabric_v_f_rd_mis_1$EN_deq, + _dor1fabric_v_f_rd_mis_2$EN_deq, + fabric_v_f_wd_tasks_0_i_notEmpty__21_AND_fabri_ETC___d130, + fabric_v_f_wd_tasks_1_i_notEmpty__49_AND_fabri_ETC___d155, + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369, + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409, + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448, + fabric_v_rg_r_err_beat_count_0_18_EQ_fabric_v__ETC___d520, + fabric_v_rg_r_err_beat_count_1_36_EQ_fabric_v__ETC___d538, + fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138, + fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163, + fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d275, + fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d280, + fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19, + fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d26, + fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d325, + fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d330, + fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83, + fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88, + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16, + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d273, + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d323, + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d81, + soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d23, + soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d278, + soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d328, + soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d86; // action method reset assign RDY_reset = !fabric_rg_reset ; @@ -1962,10 +2032,6 @@ module mkFabric_2x3(CLK, // value method v_to_slaves_0_m_wvalid assign v_to_slaves_0_wvalid = fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N ; - // value method v_to_slaves_0_m_wid - assign v_to_slaves_0_wid = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[76:73] ; - // value method v_to_slaves_0_m_wdata assign v_to_slaves_0_wdata = fabric_xactors_to_slaves_0_f_wr_data$D_OUT[72:9] ; @@ -2094,10 +2160,6 @@ module mkFabric_2x3(CLK, // value method v_to_slaves_1_m_wvalid assign v_to_slaves_1_wvalid = fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N ; - // value method v_to_slaves_1_m_wid - assign v_to_slaves_1_wid = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[76:73] ; - // value method v_to_slaves_1_m_wdata assign v_to_slaves_1_wdata = fabric_xactors_to_slaves_1_f_wr_data$D_OUT[72:9] ; @@ -2226,10 +2288,6 @@ module mkFabric_2x3(CLK, // value method v_to_slaves_2_m_wvalid assign v_to_slaves_2_wvalid = fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N ; - // value method v_to_slaves_2_m_wid - assign v_to_slaves_2_wid = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[76:73] ; - // value method v_to_slaves_2_m_wdata assign v_to_slaves_2_wdata = fabric_xactors_to_slaves_2_f_wr_data$D_OUT[72:9] ; @@ -2307,58 +2365,36 @@ module mkFabric_2x3(CLK, // value method v_to_slaves_2_m_rready assign v_to_slaves_2_rready = fabric_xactors_to_slaves_2_f_rd_data$FULL_N ; - // submodule fabric_v_f_rd_err_id_0 - SizedFIFO #(.p1width(32'd4), + // submodule fabric_v_f_rd_err_info_0 + SizedFIFO #(.p1width(32'd12), .p2depth(32'd8), .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_err_id_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_err_id_0$D_IN), - .ENQ(fabric_v_f_rd_err_id_0$ENQ), - .DEQ(fabric_v_f_rd_err_id_0$DEQ), - .CLR(fabric_v_f_rd_err_id_0$CLR), - .D_OUT(fabric_v_f_rd_err_id_0$D_OUT), - .FULL_N(), - .EMPTY_N(fabric_v_f_rd_err_id_0$EMPTY_N)); + .guarded(32'd1)) fabric_v_f_rd_err_info_0(.RST(RST_N), + .CLK(CLK), + .D_IN(fabric_v_f_rd_err_info_0$D_IN), + .ENQ(fabric_v_f_rd_err_info_0$ENQ), + .DEQ(fabric_v_f_rd_err_info_0$DEQ), + .CLR(fabric_v_f_rd_err_info_0$CLR), + .D_OUT(fabric_v_f_rd_err_info_0$D_OUT), + .FULL_N(), + .EMPTY_N(fabric_v_f_rd_err_info_0$EMPTY_N)); - // submodule fabric_v_f_rd_err_id_1 - SizedFIFO #(.p1width(32'd4), + // submodule fabric_v_f_rd_err_info_1 + SizedFIFO #(.p1width(32'd12), .p2depth(32'd8), .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_err_id_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_err_id_1$D_IN), - .ENQ(fabric_v_f_rd_err_id_1$ENQ), - .DEQ(fabric_v_f_rd_err_id_1$DEQ), - .CLR(fabric_v_f_rd_err_id_1$CLR), - .D_OUT(fabric_v_f_rd_err_id_1$D_OUT), - .FULL_N(), - .EMPTY_N(fabric_v_f_rd_err_id_1$EMPTY_N)); - - // submodule fabric_v_f_rd_err_user_0 - SizedFIFO0 #(.p1depth(32'd8), - .p2cntr_width(32'd4), - .guarded(32'd1)) fabric_v_f_rd_err_user_0(.RST(RST_N), - .CLK(CLK), - .ENQ(fabric_v_f_rd_err_user_0$ENQ), - .DEQ(fabric_v_f_rd_err_user_0$DEQ), - .CLR(fabric_v_f_rd_err_user_0$CLR), - .FULL_N(), - .EMPTY_N(fabric_v_f_rd_err_user_0$EMPTY_N)); - - // submodule fabric_v_f_rd_err_user_1 - SizedFIFO0 #(.p1depth(32'd8), - .p2cntr_width(32'd4), - .guarded(32'd1)) fabric_v_f_rd_err_user_1(.RST(RST_N), - .CLK(CLK), - .ENQ(fabric_v_f_rd_err_user_1$ENQ), - .DEQ(fabric_v_f_rd_err_user_1$DEQ), - .CLR(fabric_v_f_rd_err_user_1$CLR), - .FULL_N(), - .EMPTY_N(fabric_v_f_rd_err_user_1$EMPTY_N)); + .guarded(32'd1)) fabric_v_f_rd_err_info_1(.RST(RST_N), + .CLK(CLK), + .D_IN(fabric_v_f_rd_err_info_1$D_IN), + .ENQ(fabric_v_f_rd_err_info_1$ENQ), + .DEQ(fabric_v_f_rd_err_info_1$DEQ), + .CLR(fabric_v_f_rd_err_info_1$CLR), + .D_OUT(fabric_v_f_rd_err_info_1$D_OUT), + .FULL_N(), + .EMPTY_N(fabric_v_f_rd_err_info_1$EMPTY_N)); // submodule fabric_v_f_rd_mis_0 - SizedFIFO #(.p1width(32'd2), + SizedFIFO #(.p1width(32'd9), .p2depth(32'd8), .p3cntr_width(32'd3), .guarded(32'd1)) fabric_v_f_rd_mis_0(.RST(RST_N), @@ -2372,7 +2408,7 @@ module mkFabric_2x3(CLK, .EMPTY_N(fabric_v_f_rd_mis_0$EMPTY_N)); // submodule fabric_v_f_rd_mis_1 - SizedFIFO #(.p1width(32'd2), + SizedFIFO #(.p1width(32'd9), .p2depth(32'd8), .p3cntr_width(32'd3), .guarded(32'd1)) fabric_v_f_rd_mis_1(.RST(RST_N), @@ -2386,7 +2422,7 @@ module mkFabric_2x3(CLK, .EMPTY_N(fabric_v_f_rd_mis_1$EMPTY_N)); // submodule fabric_v_f_rd_mis_2 - SizedFIFO #(.p1width(32'd2), + SizedFIFO #(.p1width(32'd9), .p2depth(32'd8), .p3cntr_width(32'd3), .guarded(32'd1)) fabric_v_f_rd_mis_2(.RST(RST_N), @@ -2427,58 +2463,58 @@ module mkFabric_2x3(CLK, .FULL_N(fabric_v_f_rd_sjs_1$FULL_N), .EMPTY_N(fabric_v_f_rd_sjs_1$EMPTY_N)); - // submodule fabric_v_f_wr_err_id_0 + // submodule fabric_v_f_wd_tasks_0 + FIFO2 #(.width(32'd10), .guarded(32'd1)) fabric_v_f_wd_tasks_0(.RST(RST_N), + .CLK(CLK), + .D_IN(fabric_v_f_wd_tasks_0$D_IN), + .ENQ(fabric_v_f_wd_tasks_0$ENQ), + .DEQ(fabric_v_f_wd_tasks_0$DEQ), + .CLR(fabric_v_f_wd_tasks_0$CLR), + .D_OUT(fabric_v_f_wd_tasks_0$D_OUT), + .FULL_N(fabric_v_f_wd_tasks_0$FULL_N), + .EMPTY_N(fabric_v_f_wd_tasks_0$EMPTY_N)); + + // submodule fabric_v_f_wd_tasks_1 + FIFO2 #(.width(32'd10), .guarded(32'd1)) fabric_v_f_wd_tasks_1(.RST(RST_N), + .CLK(CLK), + .D_IN(fabric_v_f_wd_tasks_1$D_IN), + .ENQ(fabric_v_f_wd_tasks_1$ENQ), + .DEQ(fabric_v_f_wd_tasks_1$DEQ), + .CLR(fabric_v_f_wd_tasks_1$CLR), + .D_OUT(fabric_v_f_wd_tasks_1$D_OUT), + .FULL_N(fabric_v_f_wd_tasks_1$FULL_N), + .EMPTY_N(fabric_v_f_wd_tasks_1$EMPTY_N)); + + // submodule fabric_v_f_wr_err_info_0 SizedFIFO #(.p1width(32'd4), .p2depth(32'd8), .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_err_id_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_err_id_0$D_IN), - .ENQ(fabric_v_f_wr_err_id_0$ENQ), - .DEQ(fabric_v_f_wr_err_id_0$DEQ), - .CLR(fabric_v_f_wr_err_id_0$CLR), - .D_OUT(fabric_v_f_wr_err_id_0$D_OUT), - .FULL_N(), - .EMPTY_N(fabric_v_f_wr_err_id_0$EMPTY_N)); + .guarded(32'd1)) fabric_v_f_wr_err_info_0(.RST(RST_N), + .CLK(CLK), + .D_IN(fabric_v_f_wr_err_info_0$D_IN), + .ENQ(fabric_v_f_wr_err_info_0$ENQ), + .DEQ(fabric_v_f_wr_err_info_0$DEQ), + .CLR(fabric_v_f_wr_err_info_0$CLR), + .D_OUT(fabric_v_f_wr_err_info_0$D_OUT), + .FULL_N(), + .EMPTY_N(fabric_v_f_wr_err_info_0$EMPTY_N)); - // submodule fabric_v_f_wr_err_id_1 + // submodule fabric_v_f_wr_err_info_1 SizedFIFO #(.p1width(32'd4), .p2depth(32'd8), .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_err_id_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_err_id_1$D_IN), - .ENQ(fabric_v_f_wr_err_id_1$ENQ), - .DEQ(fabric_v_f_wr_err_id_1$DEQ), - .CLR(fabric_v_f_wr_err_id_1$CLR), - .D_OUT(fabric_v_f_wr_err_id_1$D_OUT), - .FULL_N(), - .EMPTY_N(fabric_v_f_wr_err_id_1$EMPTY_N)); - - // submodule fabric_v_f_wr_err_user_0 - SizedFIFO0 #(.p1depth(32'd8), - .p2cntr_width(32'd4), - .guarded(32'd1)) fabric_v_f_wr_err_user_0(.RST(RST_N), - .CLK(CLK), - .ENQ(fabric_v_f_wr_err_user_0$ENQ), - .DEQ(fabric_v_f_wr_err_user_0$DEQ), - .CLR(fabric_v_f_wr_err_user_0$CLR), - .FULL_N(), - .EMPTY_N(fabric_v_f_wr_err_user_0$EMPTY_N)); - - // submodule fabric_v_f_wr_err_user_1 - SizedFIFO0 #(.p1depth(32'd8), - .p2cntr_width(32'd4), - .guarded(32'd1)) fabric_v_f_wr_err_user_1(.RST(RST_N), - .CLK(CLK), - .ENQ(fabric_v_f_wr_err_user_1$ENQ), - .DEQ(fabric_v_f_wr_err_user_1$DEQ), - .CLR(fabric_v_f_wr_err_user_1$CLR), - .FULL_N(), - .EMPTY_N(fabric_v_f_wr_err_user_1$EMPTY_N)); + .guarded(32'd1)) fabric_v_f_wr_err_info_1(.RST(RST_N), + .CLK(CLK), + .D_IN(fabric_v_f_wr_err_info_1$D_IN), + .ENQ(fabric_v_f_wr_err_info_1$ENQ), + .DEQ(fabric_v_f_wr_err_info_1$DEQ), + .CLR(fabric_v_f_wr_err_info_1$CLR), + .D_OUT(fabric_v_f_wr_err_info_1$D_OUT), + .FULL_N(), + .EMPTY_N(fabric_v_f_wr_err_info_1$EMPTY_N)); // submodule fabric_v_f_wr_mis_0 - SizedFIFO #(.p1width(32'd2), + SizedFIFO #(.p1width(32'd1), .p2depth(32'd8), .p3cntr_width(32'd3), .guarded(32'd1)) fabric_v_f_wr_mis_0(.RST(RST_N), @@ -2492,7 +2528,7 @@ module mkFabric_2x3(CLK, .EMPTY_N(fabric_v_f_wr_mis_0$EMPTY_N)); // submodule fabric_v_f_wr_mis_1 - SizedFIFO #(.p1width(32'd2), + SizedFIFO #(.p1width(32'd1), .p2depth(32'd8), .p3cntr_width(32'd3), .guarded(32'd1)) fabric_v_f_wr_mis_1(.RST(RST_N), @@ -2506,7 +2542,7 @@ module mkFabric_2x3(CLK, .EMPTY_N(fabric_v_f_wr_mis_1$EMPTY_N)); // submodule fabric_v_f_wr_mis_2 - SizedFIFO #(.p1width(32'd2), + SizedFIFO #(.p1width(32'd1), .p2depth(32'd8), .p3cntr_width(32'd3), .guarded(32'd1)) fabric_v_f_wr_mis_2(.RST(RST_N), @@ -2584,7 +2620,7 @@ module mkFabric_2x3(CLK, .EMPTY_N(fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N)); // submodule fabric_xactors_from_masters_0_f_wr_data - FIFO2 #(.width(32'd77), + FIFO2 #(.width(32'd73), .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_data(.RST(RST_N), .CLK(CLK), .D_IN(fabric_xactors_from_masters_0_f_wr_data$D_IN), @@ -2644,7 +2680,7 @@ module mkFabric_2x3(CLK, .EMPTY_N(fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N)); // submodule fabric_xactors_from_masters_1_f_wr_data - FIFO2 #(.width(32'd77), + FIFO2 #(.width(32'd73), .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_data(.RST(RST_N), .CLK(CLK), .D_IN(fabric_xactors_from_masters_1_f_wr_data$D_IN), @@ -2704,7 +2740,7 @@ module mkFabric_2x3(CLK, .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N)); // submodule fabric_xactors_to_slaves_0_f_wr_data - FIFO2 #(.width(32'd77), + FIFO2 #(.width(32'd73), .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_data(.RST(RST_N), .CLK(CLK), .D_IN(fabric_xactors_to_slaves_0_f_wr_data$D_IN), @@ -2764,7 +2800,7 @@ module mkFabric_2x3(CLK, .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N)); // submodule fabric_xactors_to_slaves_1_f_wr_data - FIFO2 #(.width(32'd77), + FIFO2 #(.width(32'd73), .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_data(.RST(RST_N), .CLK(CLK), .D_IN(fabric_xactors_to_slaves_1_f_wr_data$D_IN), @@ -2824,7 +2860,7 @@ module mkFabric_2x3(CLK, .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N)); // submodule fabric_xactors_to_slaves_2_f_wr_data - FIFO2 #(.width(32'd77), + FIFO2 #(.width(32'd73), .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_data(.RST(RST_N), .CLK(CLK), .D_IN(fabric_xactors_to_slaves_2_f_wr_data$D_IN), @@ -2896,58 +2932,54 @@ module mkFabric_2x3(CLK, // rule RL_fabric_rl_wr_xaction_master_to_slave assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave = fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N && fabric_xactors_to_slaves_0_f_wr_addr$FULL_N && - fabric_xactors_to_slaves_0_f_wr_data$FULL_N && + fabric_v_f_wd_tasks_0$FULL_N && fabric_v_f_wr_mis_0$FULL_N && fabric_v_f_wr_sjs_0$FULL_N && - (!soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d18 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d21) && - (!soc_map_m_plic_addr_base__4_ULE_fabric_xactors_ETC___d25 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28) ; + (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 || + !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19) && + (!soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d23 || + !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d26) ; assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave = CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; // rule RL_fabric_rl_wr_xaction_master_to_slave_1 assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 = fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N && + fabric_v_f_wd_tasks_0$FULL_N && fabric_v_f_wr_sjs_0$FULL_N && fabric_xactors_to_slaves_1_f_wr_addr$FULL_N && - fabric_xactors_to_slaves_1_f_wr_data$FULL_N && fabric_v_f_wr_mis_1$FULL_N && - (!soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d18 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d21) && - soc_map_m_plic_addr_base__4_ULE_fabric_xactors_ETC___d25 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28 ; + (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 || + !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19) && + soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d23 && + fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d26 ; assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 = CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; // rule RL_fabric_rl_wr_xaction_master_to_slave_2 assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 = fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N && + fabric_v_f_wd_tasks_0$FULL_N && fabric_v_f_wr_sjs_0$FULL_N && fabric_xactors_to_slaves_2_f_wr_addr$FULL_N && - fabric_xactors_to_slaves_2_f_wr_data$FULL_N && fabric_v_f_wr_mis_2$FULL_N && - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d18 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d21 ; + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 && + fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19 ; assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 = CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; // rule RL_fabric_rl_wr_xaction_master_to_slave_3 assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 = fabric_xactors_to_slaves_0_f_wr_addr$FULL_N && - fabric_xactors_to_slaves_0_f_wr_data$FULL_N && fabric_v_f_wr_mis_0$FULL_N && fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N && + fabric_v_f_wd_tasks_1$FULL_N && fabric_v_f_wr_sjs_1$FULL_N && - (!soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d93 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d95) && - (!soc_map_m_plic_addr_base__4_ULE_fabric_xactors_ETC___d98 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d100) ; + (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d81 || + !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83) && + (!soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d86 || + !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88) ; assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 = CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; @@ -2955,15 +2987,14 @@ module mkFabric_2x3(CLK, // rule RL_fabric_rl_wr_xaction_master_to_slave_4 assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 = fabric_xactors_to_slaves_1_f_wr_addr$FULL_N && - fabric_xactors_to_slaves_1_f_wr_data$FULL_N && fabric_v_f_wr_mis_1$FULL_N && fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N && + fabric_v_f_wd_tasks_1$FULL_N && fabric_v_f_wr_sjs_1$FULL_N && - (!soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d93 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d95) && - soc_map_m_plic_addr_base__4_ULE_fabric_xactors_ETC___d98 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d100 ; + (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d81 || + !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83) && + soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d86 && + fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88 ; assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 = CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; @@ -2971,100 +3002,37 @@ module mkFabric_2x3(CLK, // rule RL_fabric_rl_wr_xaction_master_to_slave_5 assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 = fabric_xactors_to_slaves_2_f_wr_addr$FULL_N && - fabric_xactors_to_slaves_2_f_wr_data$FULL_N && fabric_v_f_wr_mis_2$FULL_N && fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N && + fabric_v_f_wd_tasks_1$FULL_N && fabric_v_f_wr_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d93 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d95 ; + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d81 && + fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83 ; assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 = CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - // rule RL_fabric_rl_rd_xaction_master_to_slave - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_0$FULL_N && - fabric_v_f_rd_sjs_0$FULL_N && - (!soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d148 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d150) && - (!soc_map_m_plic_addr_base__4_ULE_fabric_xactors_ETC___d153 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d155) ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; + // rule RL_fabric_rl_wr_xaction_master_to_slave_data + assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data = + fabric_xactors_from_masters_0_f_wr_data$EMPTY_N && + fabric_v_f_wd_tasks_0_i_notEmpty__21_AND_fabri_ETC___d130 ; + assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data = + CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ; - // rule RL_fabric_rl_rd_xaction_master_to_slave_1 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_0$FULL_N && - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_1$FULL_N && - (!soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d148 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d150) && - soc_map_m_plic_addr_base__4_ULE_fabric_xactors_ETC___d153 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d155 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_2 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_0$FULL_N && - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_2$FULL_N && - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d148 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d150 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_3 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 = - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_0$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - (!soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d197 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d199) && - (!soc_map_m_plic_addr_base__4_ULE_fabric_xactors_ETC___d202 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d204) ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_4 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 = - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_1$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - (!soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d197 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d199) && - soc_map_m_plic_addr_base__4_ULE_fabric_xactors_ETC___d202 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d204 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_5 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 = - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_2$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d197 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d199 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; + // rule RL_fabric_rl_wr_xaction_master_to_slave_data_1 + assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 = + fabric_xactors_from_masters_1_f_wr_data$EMPTY_N && + fabric_v_f_wd_tasks_1_i_notEmpty__49_AND_fabri_ETC___d155 ; + assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 = + CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ; // rule RL_fabric_rl_wr_resp_slave_to_master assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master = fabric_v_f_wr_mis_0$EMPTY_N && fabric_v_f_wr_sjs_0$EMPTY_N && fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N && fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_0$D_OUT == 2'd0 && + !fabric_v_f_wr_mis_0$D_OUT && fabric_v_f_wr_sjs_0$D_OUT == 2'd0 ; assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master = CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; @@ -3075,7 +3043,7 @@ module mkFabric_2x3(CLK, fabric_xactors_from_masters_0_f_wr_resp$FULL_N && fabric_v_f_wr_mis_1$EMPTY_N && fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N && - fabric_v_f_wr_mis_1$D_OUT == 2'd0 && + !fabric_v_f_wr_mis_1$D_OUT && fabric_v_f_wr_sjs_0$D_OUT == 2'd1 ; assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 = CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; @@ -3086,7 +3054,7 @@ module mkFabric_2x3(CLK, fabric_xactors_from_masters_0_f_wr_resp$FULL_N && fabric_v_f_wr_mis_2$EMPTY_N && fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N && - fabric_v_f_wr_mis_2$D_OUT == 2'd0 && + !fabric_v_f_wr_mis_2$D_OUT && fabric_v_f_wr_sjs_0$D_OUT == 2'd2 ; assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 = CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; @@ -3097,7 +3065,7 @@ module mkFabric_2x3(CLK, fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N && fabric_v_f_wr_sjs_1$EMPTY_N && fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_0$D_OUT == 2'd1 && + fabric_v_f_wr_mis_0$D_OUT && fabric_v_f_wr_sjs_1$D_OUT == 2'd0 ; assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 = CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ; @@ -3108,7 +3076,7 @@ module mkFabric_2x3(CLK, fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N && fabric_v_f_wr_sjs_1$EMPTY_N && fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_1$D_OUT == 2'd1 && + fabric_v_f_wr_mis_1$D_OUT && fabric_v_f_wr_sjs_1$D_OUT == 2'd1 ; assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 = CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 ; @@ -3119,7 +3087,7 @@ module mkFabric_2x3(CLK, fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N && fabric_v_f_wr_sjs_1$EMPTY_N && fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_2$D_OUT == 2'd1 && + fabric_v_f_wr_mis_2$D_OUT && fabric_v_f_wr_sjs_1$D_OUT == 2'd2 ; assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 = CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 ; @@ -3128,8 +3096,7 @@ module mkFabric_2x3(CLK, assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master = fabric_v_f_wr_sjs_0$EMPTY_N && fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_err_id_0$EMPTY_N && - fabric_v_f_wr_err_user_0$EMPTY_N && + fabric_v_f_wr_err_info_0$EMPTY_N && fabric_v_f_wr_sjs_0$D_OUT == 2'd3 ; assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master = CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; @@ -3138,40 +3105,123 @@ module mkFabric_2x3(CLK, assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 = fabric_v_f_wr_sjs_1$EMPTY_N && fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_err_id_1$EMPTY_N && - fabric_v_f_wr_err_user_1$EMPTY_N && + fabric_v_f_wr_err_info_1$EMPTY_N && fabric_v_f_wr_sjs_1$D_OUT == 2'd3 ; assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 = CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; + // rule RL_fabric_rl_rd_xaction_master_to_slave + assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave = + fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && + fabric_xactors_to_slaves_0_f_rd_addr$FULL_N && + fabric_v_f_rd_mis_0$FULL_N && + fabric_v_f_rd_sjs_0$FULL_N && + (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d273 || + !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d275) && + (!soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d278 || + !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d280) ; + assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave = + CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; + + // rule RL_fabric_rl_rd_xaction_master_to_slave_1 + assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 = + fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && + fabric_v_f_rd_sjs_0$FULL_N && + fabric_xactors_to_slaves_1_f_rd_addr$FULL_N && + fabric_v_f_rd_mis_1$FULL_N && + (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d273 || + !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d275) && + soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d278 && + fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d280 ; + assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 = + CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; + + // rule RL_fabric_rl_rd_xaction_master_to_slave_2 + assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 = + fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && + fabric_v_f_rd_sjs_0$FULL_N && + fabric_xactors_to_slaves_2_f_rd_addr$FULL_N && + fabric_v_f_rd_mis_2$FULL_N && + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d273 && + fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d275 ; + assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 = + CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; + + // rule RL_fabric_rl_rd_xaction_master_to_slave_3 + assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 = + fabric_xactors_to_slaves_0_f_rd_addr$FULL_N && + fabric_v_f_rd_mis_0$FULL_N && + fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && + fabric_v_f_rd_sjs_1$FULL_N && + (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d323 || + !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d325) && + (!soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d328 || + !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d330) ; + assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 = + CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; + + // rule RL_fabric_rl_rd_xaction_master_to_slave_4 + assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 = + fabric_xactors_to_slaves_1_f_rd_addr$FULL_N && + fabric_v_f_rd_mis_1$FULL_N && + fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && + fabric_v_f_rd_sjs_1$FULL_N && + (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d323 || + !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d325) && + soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d328 && + fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d330 ; + assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 = + CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; + + // rule RL_fabric_rl_rd_xaction_master_to_slave_5 + assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 = + fabric_xactors_to_slaves_2_f_rd_addr$FULL_N && + fabric_v_f_rd_mis_2$FULL_N && + fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && + fabric_v_f_rd_sjs_1$FULL_N && + soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d323 && + fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d325 ; + assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 = + CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; + // rule RL_fabric_rl_rd_resp_slave_to_master assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master = - fabric_v_f_rd_mis_0$EMPTY_N && fabric_v_f_rd_sjs_0$EMPTY_N && + fabric_v_f_rd_mis_0$EMPTY_N && fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N && fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_mis_0$D_OUT == 2'd0 && + (fabric_v_f_rd_mis_0$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && + (!fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 || + fabric_v_f_rd_sjs_0$EMPTY_N) && + !fabric_v_f_rd_mis_0$D_OUT[8] && fabric_v_f_rd_sjs_0$D_OUT == 2'd0 ; assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master = CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; // rule RL_fabric_rl_rd_resp_slave_to_master_1 assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 = - fabric_v_f_rd_sjs_0$EMPTY_N && fabric_xactors_from_masters_0_f_rd_data$FULL_N && fabric_v_f_rd_mis_1$EMPTY_N && fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N && - fabric_v_f_rd_mis_1$D_OUT == 2'd0 && + (fabric_v_f_rd_mis_1$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && + (!fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 || + fabric_v_f_rd_sjs_0$EMPTY_N) && + !fabric_v_f_rd_mis_1$D_OUT[8] && fabric_v_f_rd_sjs_0$D_OUT == 2'd1 ; assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 = CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; // rule RL_fabric_rl_rd_resp_slave_to_master_2 assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 = - fabric_v_f_rd_sjs_0$EMPTY_N && fabric_xactors_from_masters_0_f_rd_data$FULL_N && fabric_v_f_rd_mis_2$EMPTY_N && fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N && - fabric_v_f_rd_mis_2$D_OUT == 2'd0 && + (fabric_v_f_rd_mis_2$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && + (!fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 || + fabric_v_f_rd_sjs_0$EMPTY_N) && + !fabric_v_f_rd_mis_2$D_OUT[8] && fabric_v_f_rd_sjs_0$D_OUT == 2'd2 ; assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 = CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; @@ -3180,9 +3230,9 @@ module mkFabric_2x3(CLK, assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 = fabric_v_f_rd_mis_0$EMPTY_N && fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N && - fabric_v_f_rd_sjs_1$EMPTY_N && fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_mis_0$D_OUT == 2'd1 && + fabric_v_f_rd_sjs_1$EMPTY_N && + fabric_v_f_rd_mis_0$D_OUT[8] && fabric_v_f_rd_sjs_1$D_OUT == 2'd0 ; assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 = CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 ; @@ -3191,9 +3241,9 @@ module mkFabric_2x3(CLK, assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 = fabric_v_f_rd_mis_1$EMPTY_N && fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N && - fabric_v_f_rd_sjs_1$EMPTY_N && fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_mis_1$D_OUT == 2'd1 && + fabric_v_f_rd_sjs_1$EMPTY_N && + fabric_v_f_rd_mis_1$D_OUT[8] && fabric_v_f_rd_sjs_1$D_OUT == 2'd1 ; assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 = CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 ; @@ -3202,9 +3252,9 @@ module mkFabric_2x3(CLK, assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 = fabric_v_f_rd_mis_2$EMPTY_N && fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N && - fabric_v_f_rd_sjs_1$EMPTY_N && fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_mis_2$D_OUT == 2'd1 && + fabric_v_f_rd_sjs_1$EMPTY_N && + fabric_v_f_rd_mis_2$D_OUT[8] && fabric_v_f_rd_sjs_1$D_OUT == 2'd2 ; assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 = CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 ; @@ -3213,8 +3263,7 @@ module mkFabric_2x3(CLK, assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master = fabric_v_f_rd_sjs_0$EMPTY_N && fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_err_id_0$EMPTY_N && - fabric_v_f_rd_err_user_0$EMPTY_N && + fabric_v_f_rd_err_info_0$EMPTY_N && fabric_v_f_rd_sjs_0$D_OUT == 2'd3 ; assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master = CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ; @@ -3223,8 +3272,7 @@ module mkFabric_2x3(CLK, assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 = fabric_v_f_rd_sjs_1$EMPTY_N && fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_err_id_1$EMPTY_N && - fabric_v_f_rd_err_user_1$EMPTY_N && + fabric_v_f_rd_err_info_1$EMPTY_N && fabric_v_f_rd_sjs_1$D_OUT == 2'd3 ; assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 = CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; @@ -3234,14 +3282,75 @@ module mkFabric_2x3(CLK, assign WILL_FIRE_RL_fabric_rl_reset = fabric_rg_reset ; // inputs to muxes for submodule ports + assign MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 = + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 ; + assign MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 = + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 ; + assign MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 = + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 ; + assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 = + { 1'd0, fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21] } ; + assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 = + { 1'd1, fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21] } ; + assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 = + { 2'd0, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; + assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 = + { 2'd1, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; + assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3 = + { 2'd2, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; + assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 = + { 2'd0, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; + assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 = + { 2'd1, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; + assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3 = + { 2'd2, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; + assign MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 = + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 ? + 8'd0 : + x__h18092 ; + assign MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 = + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 ? + 8'd0 : + x__h18718 ; + assign MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 = + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 ? + 8'd0 : + x__h19334 ; + assign MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 = + fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 ? + 8'd0 : + x__h11895 ; + assign MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 = + fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 ? + 8'd0 : + x__h12338 ; + assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 = + { fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:3], + IF_fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_ETC___d474, + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0] } ; + assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 = + { fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:3], + IF_fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_ETC___d396, + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0] } ; + assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 = + { fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:3], + IF_fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_ETC___d435, + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0] } ; assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4 = - { fabric_v_f_rd_err_id_0$D_OUT, 67'd7 } ; + { fabric_v_f_rd_err_info_0$D_OUT[3:0], + 66'd3, + fabric_v_rg_r_err_beat_count_0_18_EQ_fabric_v__ETC___d520 } ; assign MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4 = - { fabric_v_f_wr_err_id_0$D_OUT, 2'b11 } ; + { fabric_v_f_wr_err_info_0$D_OUT, 2'd3 } ; assign MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4 = - { fabric_v_f_rd_err_id_1$D_OUT, 67'd7 } ; + { fabric_v_f_rd_err_info_1$D_OUT[3:0], + 66'd3, + fabric_v_rg_r_err_beat_count_1_36_EQ_fabric_v__ETC___d538 } ; assign MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4 = - { fabric_v_f_wr_err_id_1$D_OUT, 2'b11 } ; + { fabric_v_f_wr_err_info_1$D_OUT, 2'd3 } ; // register fabric_cfg_verbosity assign fabric_cfg_verbosity$D_IN = set_verbosity_verbosity ; @@ -3251,67 +3360,156 @@ module mkFabric_2x3(CLK, assign fabric_rg_reset$D_IN = !fabric_rg_reset ; assign fabric_rg_reset$EN = fabric_rg_reset || EN_reset ; - // submodule fabric_v_f_rd_err_id_0 - assign fabric_v_f_rd_err_id_0$D_IN = 4'h0 ; - assign fabric_v_f_rd_err_id_0$ENQ = 1'b0 ; - assign fabric_v_f_rd_err_id_0$DEQ = + // register fabric_v_rg_r_beat_count_0 + always@(fabric_rg_reset or + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or + MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 or + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master) + case (1'b1) + fabric_rg_reset: fabric_v_rg_r_beat_count_0$D_IN = 8'd0; + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3: + fabric_v_rg_r_beat_count_0$D_IN = + MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2; + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master: + fabric_v_rg_r_beat_count_0$D_IN = + MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2; + default: fabric_v_rg_r_beat_count_0$D_IN = + 8'b10101010 /* unspecified value */ ; + endcase + assign fabric_v_rg_r_beat_count_0$EN = + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master || + fabric_rg_reset ; + + // register fabric_v_rg_r_beat_count_1 + always@(fabric_rg_reset or + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or + MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 or + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1) + case (1'b1) + fabric_rg_reset: fabric_v_rg_r_beat_count_1$D_IN = 8'd0; + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4: + fabric_v_rg_r_beat_count_1$D_IN = + MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2; + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1: + fabric_v_rg_r_beat_count_1$D_IN = + MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2; + default: fabric_v_rg_r_beat_count_1$D_IN = + 8'b10101010 /* unspecified value */ ; + endcase + assign fabric_v_rg_r_beat_count_1$EN = + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || + fabric_rg_reset ; + + // register fabric_v_rg_r_beat_count_2 + always@(fabric_rg_reset or + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or + MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 or + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2) + case (1'b1) + fabric_rg_reset: fabric_v_rg_r_beat_count_2$D_IN = 8'd0; + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: + fabric_v_rg_r_beat_count_2$D_IN = + MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2; + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: + fabric_v_rg_r_beat_count_2$D_IN = + MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2; + default: fabric_v_rg_r_beat_count_2$D_IN = + 8'b10101010 /* unspecified value */ ; + endcase + assign fabric_v_rg_r_beat_count_2$EN = + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || + fabric_rg_reset ; + + // register fabric_v_rg_r_err_beat_count_0 + assign fabric_v_rg_r_err_beat_count_0$D_IN = + fabric_v_rg_r_err_beat_count_0_18_EQ_fabric_v__ETC___d520 ? + 8'd0 : + x__h21638 ; + assign fabric_v_rg_r_err_beat_count_0$EN = CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - assign fabric_v_f_rd_err_id_0$CLR = fabric_rg_reset ; - // submodule fabric_v_f_rd_err_id_1 - assign fabric_v_f_rd_err_id_1$D_IN = 4'h0 ; - assign fabric_v_f_rd_err_id_1$ENQ = 1'b0 ; - assign fabric_v_f_rd_err_id_1$DEQ = + // register fabric_v_rg_r_err_beat_count_1 + assign fabric_v_rg_r_err_beat_count_1$D_IN = + fabric_v_rg_r_err_beat_count_1_36_EQ_fabric_v__ETC___d538 ? + 8'd0 : + x__h22039 ; + assign fabric_v_rg_r_err_beat_count_1$EN = CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - assign fabric_v_f_rd_err_id_1$CLR = fabric_rg_reset ; - // submodule fabric_v_f_rd_err_user_0 - assign fabric_v_f_rd_err_user_0$ENQ = 1'b0 ; - assign fabric_v_f_rd_err_user_0$DEQ = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - assign fabric_v_f_rd_err_user_0$CLR = fabric_rg_reset ; + // register fabric_v_rg_wd_beat_count_0 + assign fabric_v_rg_wd_beat_count_0$D_IN = + fabric_rg_reset ? + 8'd0 : + MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 ; + assign fabric_v_rg_wd_beat_count_0$EN = + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data || + fabric_rg_reset ; - // submodule fabric_v_f_rd_err_user_1 - assign fabric_v_f_rd_err_user_1$ENQ = 1'b0 ; - assign fabric_v_f_rd_err_user_1$DEQ = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - assign fabric_v_f_rd_err_user_1$CLR = fabric_rg_reset ; + // register fabric_v_rg_wd_beat_count_1 + assign fabric_v_rg_wd_beat_count_1$D_IN = + fabric_rg_reset ? + 8'd0 : + MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 ; + assign fabric_v_rg_wd_beat_count_1$EN = + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 || + fabric_rg_reset ; + + // submodule fabric_v_f_rd_err_info_0 + assign fabric_v_f_rd_err_info_0$D_IN = 12'h0 ; + assign fabric_v_f_rd_err_info_0$ENQ = 1'b0 ; + assign fabric_v_f_rd_err_info_0$DEQ = + WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && + fabric_v_rg_r_err_beat_count_0_18_EQ_fabric_v__ETC___d520 ; + assign fabric_v_f_rd_err_info_0$CLR = fabric_rg_reset ; + + // submodule fabric_v_f_rd_err_info_1 + assign fabric_v_f_rd_err_info_1$D_IN = 12'h0 ; + assign fabric_v_f_rd_err_info_1$ENQ = 1'b0 ; + assign fabric_v_f_rd_err_info_1$DEQ = + WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && + fabric_v_rg_r_err_beat_count_1_36_EQ_fabric_v__ETC___d538 ; + assign fabric_v_f_rd_err_info_1$CLR = fabric_rg_reset ; // submodule fabric_v_f_rd_mis_0 assign fabric_v_f_rd_mis_0$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ? 2'd0 : 2'd1 ; + WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ? + MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : + MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; assign fabric_v_f_rd_mis_0$ENQ = WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; assign fabric_v_f_rd_mis_0$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; + _dor1fabric_v_f_rd_mis_0$EN_deq && + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 ; assign fabric_v_f_rd_mis_0$CLR = fabric_rg_reset ; // submodule fabric_v_f_rd_mis_1 assign fabric_v_f_rd_mis_1$D_IN = WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ? - 2'd0 : - 2'd1 ; + MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : + MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; assign fabric_v_f_rd_mis_1$ENQ = WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ; assign fabric_v_f_rd_mis_1$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; + _dor1fabric_v_f_rd_mis_1$EN_deq && + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 ; assign fabric_v_f_rd_mis_1$CLR = fabric_rg_reset ; // submodule fabric_v_f_rd_mis_2 assign fabric_v_f_rd_mis_2$D_IN = WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ? - 2'd0 : - 2'd1 ; + MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : + MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; assign fabric_v_f_rd_mis_2$ENQ = WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ; assign fabric_v_f_rd_mis_2$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; + _dor1fabric_v_f_rd_mis_2$EN_deq && + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 ; assign fabric_v_f_rd_mis_2$CLR = fabric_rg_reset ; // submodule fabric_v_f_rd_sjs_0 @@ -3334,10 +3532,14 @@ module mkFabric_2x3(CLK, WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; assign fabric_v_f_rd_sjs_0$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 || + WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && + fabric_v_rg_r_err_beat_count_0_18_EQ_fabric_v__ETC___d520 ; assign fabric_v_f_rd_sjs_0$CLR = fabric_rg_reset ; // submodule fabric_v_f_rd_sjs_1 @@ -3360,41 +3562,89 @@ module mkFabric_2x3(CLK, WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 || WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ; assign fabric_v_f_rd_sjs_1$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 ; + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 || + WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && + fabric_v_rg_r_err_beat_count_1_36_EQ_fabric_v__ETC___d538 ; assign fabric_v_f_rd_sjs_1$CLR = fabric_rg_reset ; - // submodule fabric_v_f_wr_err_id_0 - assign fabric_v_f_wr_err_id_0$D_IN = 4'h0 ; - assign fabric_v_f_wr_err_id_0$ENQ = 1'b0 ; - assign fabric_v_f_wr_err_id_0$DEQ = + // submodule fabric_v_f_wd_tasks_0 + always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or + MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 or + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or + MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 or + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 or + MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave: + fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1; + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1: + fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2; + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2: + fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3; + default: fabric_v_f_wd_tasks_0$D_IN = + 10'b1010101010 /* unspecified value */ ; + endcase + end + assign fabric_v_f_wd_tasks_0$ENQ = + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; + assign fabric_v_f_wd_tasks_0$DEQ = + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 ; + assign fabric_v_f_wd_tasks_0$CLR = fabric_rg_reset ; + + // submodule fabric_v_f_wd_tasks_1 + always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 or + MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 or + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 or + MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 or + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 or + MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3: + fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1; + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4: + fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2; + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5: + fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3; + default: fabric_v_f_wd_tasks_1$D_IN = + 10'b1010101010 /* unspecified value */ ; + endcase + end + assign fabric_v_f_wd_tasks_1$ENQ = + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 || + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; + assign fabric_v_f_wd_tasks_1$DEQ = + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 ; + assign fabric_v_f_wd_tasks_1$CLR = fabric_rg_reset ; + + // submodule fabric_v_f_wr_err_info_0 + assign fabric_v_f_wr_err_info_0$D_IN = 4'h0 ; + assign fabric_v_f_wr_err_info_0$ENQ = 1'b0 ; + assign fabric_v_f_wr_err_info_0$DEQ = CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - assign fabric_v_f_wr_err_id_0$CLR = fabric_rg_reset ; + assign fabric_v_f_wr_err_info_0$CLR = fabric_rg_reset ; - // submodule fabric_v_f_wr_err_id_1 - assign fabric_v_f_wr_err_id_1$D_IN = 4'h0 ; - assign fabric_v_f_wr_err_id_1$ENQ = 1'b0 ; - assign fabric_v_f_wr_err_id_1$DEQ = + // submodule fabric_v_f_wr_err_info_1 + assign fabric_v_f_wr_err_info_1$D_IN = 4'h0 ; + assign fabric_v_f_wr_err_info_1$ENQ = 1'b0 ; + assign fabric_v_f_wr_err_info_1$DEQ = CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - assign fabric_v_f_wr_err_id_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_err_user_0 - assign fabric_v_f_wr_err_user_0$ENQ = 1'b0 ; - assign fabric_v_f_wr_err_user_0$DEQ = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - assign fabric_v_f_wr_err_user_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_err_user_1 - assign fabric_v_f_wr_err_user_1$ENQ = 1'b0 ; - assign fabric_v_f_wr_err_user_1$DEQ = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - assign fabric_v_f_wr_err_user_1$CLR = fabric_rg_reset ; + assign fabric_v_f_wr_err_info_1$CLR = fabric_rg_reset ; // submodule fabric_v_f_wr_mis_0 assign fabric_v_f_wr_mis_0$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ? 2'd0 : 2'd1 ; + !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; assign fabric_v_f_wr_mis_0$ENQ = WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; @@ -3405,9 +3655,7 @@ module mkFabric_2x3(CLK, // submodule fabric_v_f_wr_mis_1 assign fabric_v_f_wr_mis_1$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ? - 2'd0 : - 2'd1 ; + !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; assign fabric_v_f_wr_mis_1$ENQ = WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ; @@ -3418,9 +3666,7 @@ module mkFabric_2x3(CLK, // submodule fabric_v_f_wr_mis_2 assign fabric_v_f_wr_mis_2$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ? - 2'd0 : - 2'd1 ; + !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; assign fabric_v_f_wr_mis_2$ENQ = WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; @@ -3503,25 +3749,25 @@ module mkFabric_2x3(CLK, assign fabric_xactors_from_masters_0_f_rd_addr$CLR = fabric_rg_reset ; // submodule fabric_xactors_from_masters_0_f_rd_data - always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master or - fabric_xactors_to_slaves_0_f_rd_data$D_OUT or + always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 or + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master or + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 or - fabric_xactors_to_slaves_1_f_rd_data$D_OUT or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 or - fabric_xactors_to_slaves_2_f_rd_data$D_OUT or + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master or MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - fabric_xactors_to_slaves_0_f_rd_data$D_OUT; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - fabric_xactors_to_slaves_1_f_rd_data$D_OUT; WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: fabric_xactors_from_masters_0_f_rd_data$D_IN = - fabric_xactors_to_slaves_2_f_rd_data$D_OUT; + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master: + fabric_xactors_from_masters_0_f_rd_data$D_IN = + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1: + fabric_xactors_from_masters_0_f_rd_data$D_IN = + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master: fabric_xactors_from_masters_0_f_rd_data$D_IN = MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4; @@ -3530,9 +3776,9 @@ module mkFabric_2x3(CLK, endcase end assign fabric_xactors_from_masters_0_f_rd_data$ENQ = + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master || WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master ; assign fabric_xactors_from_masters_0_f_rd_data$DEQ = v_from_masters_0_rready && @@ -3562,17 +3808,14 @@ module mkFabric_2x3(CLK, // submodule fabric_xactors_from_masters_0_f_wr_data assign fabric_xactors_from_masters_0_f_wr_data$D_IN = - { v_from_masters_0_wid, - v_from_masters_0_wdata, + { v_from_masters_0_wdata, v_from_masters_0_wstrb, v_from_masters_0_wlast } ; assign fabric_xactors_from_masters_0_f_wr_data$ENQ = v_from_masters_0_wvalid && fabric_xactors_from_masters_0_f_wr_data$FULL_N ; assign fabric_xactors_from_masters_0_f_wr_data$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; + CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ; assign fabric_xactors_from_masters_0_f_wr_data$CLR = fabric_rg_reset ; // submodule fabric_xactors_from_masters_0_f_wr_resp @@ -3634,25 +3877,25 @@ module mkFabric_2x3(CLK, assign fabric_xactors_from_masters_1_f_rd_addr$CLR = fabric_rg_reset ; // submodule fabric_xactors_from_masters_1_f_rd_data - always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or - fabric_xactors_to_slaves_0_f_rd_data$D_OUT or + always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or - fabric_xactors_to_slaves_1_f_rd_data$D_OUT or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or - fabric_xactors_to_slaves_2_f_rd_data$D_OUT or + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 or MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - fabric_xactors_to_slaves_0_f_rd_data$D_OUT; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - fabric_xactors_to_slaves_1_f_rd_data$D_OUT; WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: fabric_xactors_from_masters_1_f_rd_data$D_IN = - fabric_xactors_to_slaves_2_f_rd_data$D_OUT; + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3: + fabric_xactors_from_masters_1_f_rd_data$D_IN = + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4: + fabric_xactors_from_masters_1_f_rd_data$D_IN = + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1: fabric_xactors_from_masters_1_f_rd_data$D_IN = MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4; @@ -3661,9 +3904,9 @@ module mkFabric_2x3(CLK, endcase end assign fabric_xactors_from_masters_1_f_rd_data$ENQ = + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; assign fabric_xactors_from_masters_1_f_rd_data$DEQ = v_from_masters_1_rready && @@ -3693,17 +3936,14 @@ module mkFabric_2x3(CLK, // submodule fabric_xactors_from_masters_1_f_wr_data assign fabric_xactors_from_masters_1_f_wr_data$D_IN = - { v_from_masters_1_wid, - v_from_masters_1_wdata, + { v_from_masters_1_wdata, v_from_masters_1_wstrb, v_from_masters_1_wlast } ; assign fabric_xactors_from_masters_1_f_wr_data$ENQ = v_from_masters_1_wvalid && fabric_xactors_from_masters_1_f_wr_data$FULL_N ; assign fabric_xactors_from_masters_1_f_wr_data$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 ; assign fabric_xactors_from_masters_1_f_wr_data$CLR = fabric_rg_reset ; // submodule fabric_xactors_from_masters_1_f_wr_resp @@ -3785,12 +4025,14 @@ module mkFabric_2x3(CLK, // submodule fabric_xactors_to_slaves_0_f_wr_data assign fabric_xactors_to_slaves_0_f_wr_data$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ? + MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 ? fabric_xactors_from_masters_0_f_wr_data$D_OUT : fabric_xactors_from_masters_1_f_wr_data$D_OUT ; assign fabric_xactors_to_slaves_0_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 || + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd0 ; assign fabric_xactors_to_slaves_0_f_wr_data$DEQ = fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N && v_to_slaves_0_wready ; @@ -3849,12 +4091,14 @@ module mkFabric_2x3(CLK, // submodule fabric_xactors_to_slaves_1_f_wr_data assign fabric_xactors_to_slaves_1_f_wr_data$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ? + MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 ? fabric_xactors_from_masters_0_f_wr_data$D_OUT : fabric_xactors_from_masters_1_f_wr_data$D_OUT ; assign fabric_xactors_to_slaves_1_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ; + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 || + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd1 ; assign fabric_xactors_to_slaves_1_f_wr_data$DEQ = fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N && v_to_slaves_1_wready ; @@ -3913,12 +4157,14 @@ module mkFabric_2x3(CLK, // submodule fabric_xactors_to_slaves_2_f_wr_data assign fabric_xactors_to_slaves_2_f_wr_data$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ? + MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 ? fabric_xactors_from_masters_0_f_wr_data$D_OUT : fabric_xactors_from_masters_1_f_wr_data$D_OUT ; assign fabric_xactors_to_slaves_2_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 || + WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd2 ; assign fabric_xactors_to_slaves_2_f_wr_data$DEQ = fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N && v_to_slaves_2_wready ; @@ -3941,56 +4187,155 @@ module mkFabric_2x3(CLK, assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; // remaining internal signals - assign NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 = - fabric_cfg_verbosity > 4'd1 ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d150 = + assign IF_fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_ETC___d396 = + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 ? + x1_avValue_rresp__h18070 : + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ; + assign IF_fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_ETC___d435 = + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 ? + x1_avValue_rresp__h18696 : + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ; + assign IF_fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_ETC___d474 = + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 ? + x1_avValue_rresp__h19312 : + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ; + assign _dor1fabric_v_f_rd_mis_0$EN_deq = + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; + assign _dor1fabric_v_f_rd_mis_1$EN_deq = + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; + assign _dor1fabric_v_f_rd_mis_2$EN_deq = + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; + assign fabric_v_f_wd_tasks_0_i_notEmpty__21_AND_fabri_ETC___d130 = + fabric_v_f_wd_tasks_0$EMPTY_N && + CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 ; + assign fabric_v_f_wd_tasks_1_i_notEmpty__49_AND_fabri_ETC___d155 = + fabric_v_f_wd_tasks_1$EMPTY_N && + CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 ; + assign fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 = + fabric_v_rg_r_beat_count_0 == fabric_v_f_rd_mis_0$D_OUT[7:0] ; + assign fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 = + fabric_v_rg_r_beat_count_1 == fabric_v_f_rd_mis_1$D_OUT[7:0] ; + assign fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 = + fabric_v_rg_r_beat_count_2 == fabric_v_f_rd_mis_2$D_OUT[7:0] ; + assign fabric_v_rg_r_err_beat_count_0_18_EQ_fabric_v__ETC___d520 = + fabric_v_rg_r_err_beat_count_0 == + fabric_v_f_rd_err_info_0$D_OUT[11:4] ; + assign fabric_v_rg_r_err_beat_count_1_36_EQ_fabric_v__ETC___d538 = + fabric_v_rg_r_err_beat_count_1 == + fabric_v_f_rd_err_info_1$D_OUT[11:4] ; + assign fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 = + fabric_v_rg_wd_beat_count_0 == fabric_v_f_wd_tasks_0$D_OUT[7:0] ; + assign fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 = + fabric_v_rg_wd_beat_count_1 == fabric_v_f_wd_tasks_1$D_OUT[7:0] ; + assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d275 = fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d155 = + assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d280 = fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < soc_map$m_plic_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d21 = + assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19 = fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28 = + assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d26 = fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < soc_map$m_plic_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d199 = + assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d325 = fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d204 = + assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d330 = fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < soc_map$m_plic_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d100 = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < - soc_map$m_plic_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d95 = + assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83 = fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < soc_map$m_mem0_controller_addr_lim ; - assign soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d148 = - soc_map$m_mem0_controller_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d18 = + assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88 = + fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < + soc_map$m_plic_addr_lim ; + assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 = soc_map$m_mem0_controller_addr_base <= fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d197 = + assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d273 = + soc_map$m_mem0_controller_addr_base <= + fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; + assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d323 = soc_map$m_mem0_controller_addr_base <= fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__5_ULE_fab_ETC___d93 = + assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d81 = soc_map$m_mem0_controller_addr_base <= fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_plic_addr_base__4_ULE_fabric_xactors_ETC___d153 = - soc_map$m_plic_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_plic_addr_base__4_ULE_fabric_xactors_ETC___d202 = - soc_map$m_plic_addr_base <= - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_plic_addr_base__4_ULE_fabric_xactors_ETC___d25 = + assign soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d23 = soc_map$m_plic_addr_base <= fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_plic_addr_base__4_ULE_fabric_xactors_ETC___d98 = + assign soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d278 = + soc_map$m_plic_addr_base <= + fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; + assign soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d328 = + soc_map$m_plic_addr_base <= + fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; + assign soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d86 = soc_map$m_plic_addr_base <= fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; + assign x1_avValue_rresp__h18070 = + (fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) ? + 2'b10 : + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ; + assign x1_avValue_rresp__h18696 = + (fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) ? + 2'b10 : + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ; + assign x1_avValue_rresp__h19312 = + (fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) ? + 2'b10 : + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ; + assign x__h11895 = fabric_v_rg_wd_beat_count_0 + 8'd1 ; + assign x__h12338 = fabric_v_rg_wd_beat_count_1 + 8'd1 ; + assign x__h18092 = fabric_v_rg_r_beat_count_0 + 8'd1 ; + assign x__h18718 = fabric_v_rg_r_beat_count_1 + 8'd1 ; + assign x__h19334 = fabric_v_rg_r_beat_count_2 + 8'd1 ; + assign x__h21638 = fabric_v_rg_r_err_beat_count_0 + 8'd1 ; + assign x__h22039 = fabric_v_rg_r_err_beat_count_1 + 8'd1 ; + always@(fabric_v_f_wd_tasks_0$D_OUT or + fabric_xactors_to_slaves_0_f_wr_data$FULL_N or + fabric_xactors_to_slaves_1_f_wr_data$FULL_N or + fabric_xactors_to_slaves_2_f_wr_data$FULL_N) + begin + case (fabric_v_f_wd_tasks_0$D_OUT[9:8]) + 2'd0: + CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = + fabric_xactors_to_slaves_0_f_wr_data$FULL_N; + 2'd1: + CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = + fabric_xactors_to_slaves_1_f_wr_data$FULL_N; + 2'd2: + CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = + fabric_xactors_to_slaves_2_f_wr_data$FULL_N; + 2'd3: CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = 1'd1; + endcase + end + always@(fabric_v_f_wd_tasks_1$D_OUT or + fabric_xactors_to_slaves_0_f_wr_data$FULL_N or + fabric_xactors_to_slaves_1_f_wr_data$FULL_N or + fabric_xactors_to_slaves_2_f_wr_data$FULL_N) + begin + case (fabric_v_f_wd_tasks_1$D_OUT[9:8]) + 2'd0: + CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = + fabric_xactors_to_slaves_0_f_wr_data$FULL_N; + 2'd1: + CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = + fabric_xactors_to_slaves_1_f_wr_data$FULL_N; + 2'd2: + CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = + fabric_xactors_to_slaves_2_f_wr_data$FULL_N; + 2'd3: CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = 1'd1; + endcase + end // handling of inlined registers @@ -4000,6 +4345,13 @@ module mkFabric_2x3(CLK, begin fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY 1'd1; + fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; + fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; + fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY 8'd0; + fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; + fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; + fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; + fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; end else begin @@ -4008,6 +4360,27 @@ module mkFabric_2x3(CLK, fabric_cfg_verbosity$D_IN; if (fabric_rg_reset$EN) fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY fabric_rg_reset$D_IN; + if (fabric_v_rg_r_beat_count_0$EN) + fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY + fabric_v_rg_r_beat_count_0$D_IN; + if (fabric_v_rg_r_beat_count_1$EN) + fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY + fabric_v_rg_r_beat_count_1$D_IN; + if (fabric_v_rg_r_beat_count_2$EN) + fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY + fabric_v_rg_r_beat_count_2$D_IN; + if (fabric_v_rg_r_err_beat_count_0$EN) + fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY + fabric_v_rg_r_err_beat_count_0$D_IN; + if (fabric_v_rg_r_err_beat_count_1$EN) + fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY + fabric_v_rg_r_err_beat_count_1$D_IN; + if (fabric_v_rg_wd_beat_count_0$EN) + fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY + fabric_v_rg_wd_beat_count_0$D_IN; + if (fabric_v_rg_wd_beat_count_1$EN) + fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY + fabric_v_rg_wd_beat_count_1$D_IN; end end @@ -4018,6 +4391,13 @@ module mkFabric_2x3(CLK, begin fabric_cfg_verbosity = 4'hA; fabric_rg_reset = 1'h0; + fabric_v_rg_r_beat_count_0 = 8'hAA; + fabric_v_rg_r_beat_count_1 = 8'hAA; + fabric_v_rg_r_beat_count_2 = 8'hAA; + fabric_v_rg_r_err_beat_count_0 = 8'hAA; + fabric_v_rg_r_err_beat_count_1 = 8'hAA; + fabric_v_rg_wd_beat_count_0 = 8'hAA; + fabric_v_rg_wd_beat_count_1 = 8'hAA; end `endif // BSV_NO_INITIAL_BLOCKS // synopsys translate_on @@ -4030,2581 +4410,3009 @@ module mkFabric_2x3(CLK, #0; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) begin - v__h8376 = $stime; + v__h8785 = $stime; #0; end - v__h8370 = v__h8376 / 32'd10; + v__h8779 = v__h8785 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: wr master [%0d] -> slave [%0d]", - v__h8370, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", + v__h8779, $signed(32'd0), $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); + fabric_cfg_verbosity != 4'd0) + $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Addr { ", "awid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awaddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && - fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) begin - v__h8854 = $stime; + v__h9160 = $stime; #0; end - v__h8848 = v__h8854 / 32'd10; + v__h9154 = v__h9160 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: wr master [%0d] -> slave [%0d]", - v__h8848, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", + v__h9154, $signed(32'd0), $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); + fabric_cfg_verbosity != 4'd0) + $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Addr { ", "awid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awaddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && - fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) begin - v__h9332 = $stime; + v__h9535 = $stime; #0; end - v__h9326 = v__h9332 / 32'd10; + v__h9529 = v__h9535 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: wr master [%0d] -> slave [%0d]", - v__h9326, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", + v__h9529, $signed(32'd0), $signed(32'd2)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); + fabric_cfg_verbosity != 4'd0) + $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Addr { ", "awid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awaddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "awuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + begin + v__h9980 = $stime; + #0; + end + v__h9974 = v__h9980 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("AXI4_Wr_Data { ", "wid: "); + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", + v__h9974, + $signed(32'd1), + $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[76:73]); + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(" "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "wdata: "); + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Wr_Addr { ", "awid: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awaddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awuser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + begin + v__h10349 = $stime; + #0; + end + v__h10343 = v__h10349 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", + v__h10343, + $signed(32'd1), + $signed(32'd1)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Wr_Addr { ", "awid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awaddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awuser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + begin + v__h10718 = $stime; + #0; + end + v__h10712 = v__h10718 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", + v__h10712, + $signed(32'd1), + $signed(32'd2)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Wr_Addr { ", "awid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awaddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "awuser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && + !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) + begin + v__h11990 = $stime; + #0; + end + v__h11984 = v__h11990 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && + !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) + $display("%0d: %m.rl_wr_xaction_master_to_slave_data: ERROR: m%0d -> s%0d", + v__h11984, + $signed(32'd0), + fabric_v_f_wd_tasks_0$D_OUT[9:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && + !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) + $display(" WLAST not set on final data beat (awlen = %0d)", + fabric_v_f_wd_tasks_0$D_OUT[7:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && + !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && + !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) + $write("AXI4_Wr_Data { ", "wdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && + !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[72:9]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && + !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) $write(", ", "wstrb: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && + !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[8:1]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && + !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) $write(", ", "wlast: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && - fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && + !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) $write(", ", "wuser: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && + !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && + fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && + !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) $write("\n"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 && + !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) begin - v__h9903 = $stime; + v__h12433 = $stime; #0; end - v__h9897 = v__h9903 / 32'd10; + v__h12427 = v__h12433 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: wr master [%0d] -> slave [%0d]", - v__h9897, + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 && + !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) + $display("%0d: %m.rl_wr_xaction_master_to_slave_data: ERROR: m%0d -> s%0d", + v__h12427, $signed(32'd1), - $signed(32'd0)); + fabric_v_f_wd_tasks_1$D_OUT[9:8]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 && + !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) + $display(" WLAST not set on final data beat (awlen = %0d)", + fabric_v_f_wd_tasks_1$D_OUT[7:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("AXI4_Wr_Addr { ", "awid: "); + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 && + !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) + $write(" "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 && + !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) + $write("AXI4_Wr_Data { ", "wdata: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 && + !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[72:9]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 && + !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) $write(", ", "wstrb: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 && + !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[8:1]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 && + !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) $write(", ", "wlast: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && - fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 && !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - begin - v__h10365 = $stime; - #0; - end - v__h10359 = v__h10365 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: wr master [%0d] -> slave [%0d]", - v__h10359, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && - fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 && !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) $write(", ", "wuser: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - begin - v__h10827 = $stime; - #0; - end - v__h10821 = v__h10827 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: wr master [%0d] -> slave [%0d]", - v__h10821, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && - fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 && !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - begin - v__h12052 = $stime; - #0; - end - v__h12046 = v__h12052 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: rd master [%0d] -> slave [%0d]", - v__h12046, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - begin - v__h12404 = $stime; - #0; - end - v__h12398 = v__h12404 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: rd master [%0d] -> slave [%0d]", - v__h12398, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - begin - v__h12756 = $stime; - #0; - end - v__h12750 = v__h12756 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: rd master [%0d] -> slave [%0d]", - v__h12750, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - begin - v__h13171 = $stime; - #0; - end - v__h13165 = v__h13171 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: rd master [%0d] -> slave [%0d]", - v__h13165, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - begin - v__h13499 = $stime; - #0; - end - v__h13493 = v__h13499 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: rd master [%0d] -> slave [%0d]", - v__h13493, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - begin - v__h13827 = $stime; - #0; - end - v__h13821 = v__h13827 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: rd master [%0d] -> slave [%0d]", - v__h13821, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && + fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 && + !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) begin - v__h14823 = $stime; + v__h12808 = $stime; #0; end - v__h14817 = v__h14823 / 32'd10; + v__h12802 = v__h12808 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: wr master [%0d] <- slave [%0d]", - v__h14817, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", + v__h12802, $signed(32'd0), $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) begin - v__h15116 = $stime; + v__h13100 = $stime; #0; end - v__h15110 = v__h15116 / 32'd10; + v__h13094 = v__h13100 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: wr master [%0d] <- slave [%0d]", - v__h15110, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", + v__h13094, $signed(32'd0), $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) begin - v__h15409 = $stime; + v__h13392 = $stime; #0; end - v__h15403 = v__h15409 / 32'd10; + v__h13386 = v__h13392 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: wr master [%0d] <- slave [%0d]", - v__h15403, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", + v__h13386, $signed(32'd0), $signed(32'd2)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) begin - v__h15715 = $stime; + v__h13695 = $stime; #0; end - v__h15709 = v__h15715 / 32'd10; + v__h13689 = v__h13695 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: wr master [%0d] <- slave [%0d]", - v__h15709, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", + v__h13689, $signed(32'd1), $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) begin - v__h15982 = $stime; + v__h13961 = $stime; #0; end - v__h15976 = v__h15982 / 32'd10; + v__h13955 = v__h13961 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: wr master [%0d] <- slave [%0d]", - v__h15976, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", + v__h13955, $signed(32'd1), $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) begin - v__h16249 = $stime; + v__h14227 = $stime; #0; end - v__h16243 = v__h16249 / 32'd10; + v__h14221 = v__h14227 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: wr master [%0d] <- slave [%0d]", - v__h16243, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", + v__h14221, $signed(32'd1), $signed(32'd2)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) begin - v__h16556 = $stime; + v__h14491 = $stime; #0; end - v__h16550 = v__h16556 / 32'd10; + v__h14485 = v__h14491 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: wr master [%0d] <- error", - v__h16550, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_resp_err_to_master: m%0d <- err", + v__h14485, $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_v_f_wr_err_id_0$D_OUT); + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_v_f_wr_err_info_0$D_OUT); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 2'b11); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", 1'h0, " }"); + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) begin - v__h16823 = $stime; + v__h14717 = $stime; #0; end - v__h16817 = v__h16823 / 32'd10; + v__h14711 = v__h14717 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: wr master [%0d] <- error", - v__h16817, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_wr_resp_err_to_master: m%0d <- err", + v__h14711, $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_v_f_wr_err_id_1$D_OUT); + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_v_f_wr_err_info_1$D_OUT); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 2'b11); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", 1'h0, " }"); + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + begin + v__h15146 = $stime; + #0; + end + v__h15140 = v__h15146 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", + v__h15140, + $signed(32'd0), + $signed(32'd0)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Addr { ", "arid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "araddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write(", ", "aruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && + fabric_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + begin + v__h15502 = $stime; + #0; + end + v__h15496 = v__h15502 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", + v__h15496, + $signed(32'd0), + $signed(32'd1)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Addr { ", "arid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "araddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "aruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && + fabric_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + begin + v__h15858 = $stime; + #0; + end + v__h15852 = v__h15858 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", + v__h15852, + $signed(32'd0), + $signed(32'd2)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Addr { ", "arid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "araddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "aruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && + fabric_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + begin + v__h16275 = $stime; + #0; + end + v__h16269 = v__h16275 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", + v__h16269, + $signed(32'd1), + $signed(32'd0)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Addr { ", "arid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "araddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "aruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && + fabric_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + begin + v__h16607 = $stime; + #0; + end + v__h16601 = v__h16607 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", + v__h16601, + $signed(32'd1), + $signed(32'd1)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Addr { ", "arid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "araddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "aruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && + fabric_cfg_verbosity != 4'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + begin + v__h16939 = $stime; + #0; + end + v__h16933 = v__h16939 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", + v__h16933, + $signed(32'd1), + $signed(32'd2)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Addr { ", "arid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "araddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "arregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "aruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) begin - v__h17170 = $stime; + v__h17955 = $stime; #0; end - v__h17164 = v__h17170 / 32'd10; + v__h17949 = v__h17955 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: rd master [%0d] <- slave [%0d]", - v__h17164, + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", + v__h17949, $signed(32'd0), $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $display(" RLAST not set on final data beat (arlen = %0d)", + fabric_v_f_rd_mis_0$D_OUT[7:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1]); + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $write("'h%h", 2'b10); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) + begin + v__h18206 = $stime; + #0; + end + v__h18200 = v__h18206 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", + v__h18200, + $signed(32'd0), + $signed(32'd0)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) + $write(" r: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Data { ", "rid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rresp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", + IF_fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_ETC___d396); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rlast: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) + $write(", ", "ruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) begin - v__h17493 = $stime; + v__h18581 = $stime; #0; end - v__h17487 = v__h17493 / 32'd10; + v__h18575 = v__h18581 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: rd master [%0d] <- slave [%0d]", - v__h17487, + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", + v__h18575, $signed(32'd0), $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $display(" RLAST not set on final data beat (arlen = %0d)", + fabric_v_f_rd_mis_1$D_OUT[7:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1]); + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $write("'h%h", 2'b10); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) + begin + v__h18822 = $stime; + #0; + end + v__h18816 = v__h18822 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", + v__h18816, + $signed(32'd0), + $signed(32'd1)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) + $write(" r: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Data { ", "rid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rresp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", + IF_fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_ETC___d435); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rlast: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "ruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) begin - v__h17816 = $stime; + v__h19197 = $stime; #0; end - v__h17810 = v__h17816 / 32'd10; + v__h19191 = v__h19197 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: rd master [%0d] <- slave [%0d]", - v__h17810, + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", + v__h19191, $signed(32'd0), $signed(32'd2)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $display(" RLAST not set on final data beat (arlen = %0d)", + fabric_v_f_rd_mis_2$D_OUT[7:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1]); + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $write("'h%h", 2'b10); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) + begin + v__h19438 = $stime; + #0; + end + v__h19432 = v__h19438 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", + v__h19432, + $signed(32'd0), + $signed(32'd2)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) + $write(" r: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Data { ", "rid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rresp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", + IF_fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_ETC___d474); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rlast: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "ruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) begin - v__h18143 = $stime; + v__h19800 = $stime; #0; end - v__h18137 = v__h18143 / 32'd10; + v__h19794 = v__h19800 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: rd master [%0d] <- slave [%0d]", - v__h18137, + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", + v__h19794, $signed(32'd1), $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $display(" RLAST not set on final data beat (arlen = %0d)", + fabric_v_f_rd_mis_0$D_OUT[7:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1]); + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $write("'h%h", 2'b10); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) + begin + v__h20051 = $stime; + #0; + end + v__h20045 = v__h20051 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", + v__h20045, + $signed(32'd1), + $signed(32'd0)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) + $write(" r: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Data { ", "rid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rresp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", + IF_fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_ETC___d396); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rlast: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0 && + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0 && + !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "ruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) begin - v__h18429 = $stime; + v__h20381 = $stime; #0; end - v__h18423 = v__h18429 / 32'd10; + v__h20375 = v__h20381 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: rd master [%0d] <- slave [%0d]", - v__h18423, + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", + v__h20375, $signed(32'd1), $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $display(" RLAST not set on final data beat (arlen = %0d)", + fabric_v_f_rd_mis_1$D_OUT[7:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1]); + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $write("'h%h", 2'b10); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) + begin + v__h20622 = $stime; + #0; + end + v__h20616 = v__h20622 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", + v__h20616, + $signed(32'd1), + $signed(32'd1)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) + $write(" r: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Data { ", "rid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rresp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", + IF_fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_ETC___d435); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rlast: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0 && + fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0 && + !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "ruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) begin - v__h18715 = $stime; + v__h20952 = $stime; #0; end - v__h18709 = v__h18715 / 32'd10; + v__h20946 = v__h20952 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: rd master [%0d] <- slave [%0d]", - v__h18709, + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", + v__h20946, $signed(32'd1), $signed(32'd2)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $display(" RLAST not set on final data beat (arlen = %0d)", + fabric_v_f_rd_mis_2$D_OUT[7:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1]); + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $write("'h%h", 2'b10); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36 && + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) + begin + v__h21193 = $stime; + #0; + end + v__h21187 = v__h21193 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", + v__h21187, + $signed(32'd1), + $signed(32'd2)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) + $write(" r: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) + $write("AXI4_Rd_Data { ", "rid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rresp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", + IF_fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_ETC___d474); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "rlast: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0 && + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0 && + !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) + $write(", ", "ruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) begin - v__h19040 = $stime; + v__h21706 = $stime; #0; end - v__h19034 = v__h19040 / 32'd10; + v__h21700 = v__h21706 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: rd master [%0d] <- error", - v__h19034, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_resp_err_to_master: m%0d <- err", + v__h21700, $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); + fabric_cfg_verbosity != 4'd0) + $write(" r: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_v_f_rd_err_id_0$D_OUT); + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_v_f_rd_err_info_0$D_OUT[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 64'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 2'b11); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0 && + fabric_v_rg_r_err_beat_count_0_18_EQ_fabric_v__ETC___d520) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0 && + !fabric_v_rg_r_err_beat_count_0_18_EQ_fabric_v__ETC___d520) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && + fabric_cfg_verbosity != 4'd0) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", 1'h0, " }"); + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) begin - v__h19314 = $stime; + v__h22107 = $stime; #0; end - v__h19308 = v__h19314 / 32'd10; + v__h22101 = v__h22107 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $display("%0d: AXI4_Fabric: rd master [%0d] <- error", - v__h19308, + fabric_cfg_verbosity != 4'd0) + $display("%0d: %m.rl_rd_resp_err_to_master: m%0d <- err", + v__h22101, $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write(" "); + fabric_cfg_verbosity != 4'd0) + $write(" r: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", fabric_v_f_rd_err_id_1$D_OUT); + fabric_cfg_verbosity != 4'd0) + $write("'h%h", fabric_v_f_rd_err_info_1$D_OUT[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 64'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("'h%h", 2'b11); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0 && + fabric_v_rg_r_err_beat_count_1_36_EQ_fabric_v__ETC___d538) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0 && + !fabric_v_rg_r_err_beat_count_1_36_EQ_fabric_v__ETC___d538) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && + fabric_cfg_verbosity != 4'd0) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) - $write("'h%h", 1'h0, " }"); + fabric_cfg_verbosity != 4'd0) + $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__4_ULE_1_5___d36) + fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (fabric_rg_reset) begin - v__h5509 = $stime; + v__h5833 = $stime; #0; end - v__h5503 = v__h5509 / 32'd10; + v__h5827 = v__h5833 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (fabric_rg_reset) $display("%0d: AXI4_Fabric.rl_reset", v__h5503); + if (fabric_rg_reset) $display("%0d: %m.rl_reset", v__h5827); end // synopsys translate_on endmodule // mkFabric_2x3 diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkFetchStage.v b/src_SSITH_P3_sim/Verilog_RTL/mkFetchStage.v index a92a7fb..14d0e8e 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkFetchStage.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkFetchStage.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // @@ -2753,7 +2753,7 @@ module mkFetchStage(CLK, in_ppc__h189440, out___1_tval__h155806, pc_start__h125011, - x__h123136, + x__h123137, x__h188954, x__h199922, x__h199986, @@ -2840,7 +2840,7 @@ module mkFetchStage(CLK, IF_rg_pending_f32d_772_BITS_72_TO_69_580_EQ_0__ETC___d5606, SEL_ARR_f22f3_data_0_738_BITS_3_TO_0_739_f22f3_ETC___d3747, in_main_epoch__h182434, - out_main_epoch__h123143; + out_main_epoch__h123144; reg [2 : 0] CASE_decode_416_BITS_77_TO_75_0_decode_416_BIT_ETC__q5, CASE_decode_998_BITS_77_TO_75_0_decode_998_BIT_ETC__q8, CASE_x8029_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q179, @@ -3205,7 +3205,7 @@ module mkFetchStage(CLK, x1_avValue_fst_tval__h155820, x22084_PLUS_1__q2, x__h122084, - x__h123545, + x__h123541, x__h154964, x__h176295, x__h176310, @@ -5473,7 +5473,7 @@ module mkFetchStage(CLK, assign f22f3_enqReq_lat_0$wget = { 1'd1, SEL_ARR_f12f2_data_0_633_BITS_136_TO_135_634_f_ETC___d3638, - x__h123136, + x__h123137, !CASE_f12f2_deqP_0_NOT_f12f2_data_0_BIT_70_1_NO_ETC__q248, CASE_f12f2_deqP_0_f12f2_data_0_BITS_69_TO_6_1__ETC__q249, iTlb_to_proc_response_get_624_BIT_4_625_OR_NOT_ETC___d3734 } ; @@ -13961,7 +13961,7 @@ module mkFetchStage(CLK, { !iTlb$to_proc_response_get[4] && mmio$getFetchTarget == 2'd1, CASE_f12f2_deqP_0_f12f2_data_0_BIT_5_1_f12f2_d_ETC__q198, CASE_f12f2_deqP_0_f12f2_data_0_BIT_4_1_f12f2_d_ETC__q199, - out_main_epoch__h123143 } ; + out_main_epoch__h123144 } ; assign NOT_instdata_full_dummy2_1_read__945_946_OR_NO_ETC___d3982 = (!instdata_full_dummy2_1$Q_OUT || !instdata_full_dummy2_2$Q_OUT || @@ -14503,7 +14503,7 @@ module mkFetchStage(CLK, 4'd13) ? 4'd13 : 4'd15))))))))))))), - x__h123545, + x__h123541, NOT_iTlb_to_proc_response_get_624_BIT_4_625_62_ETC___d3733 } ; assign imm12__h128729 = { 4'd0, offset__h128572 } ; assign imm12__h129070 = { 5'd0, offset__h129012 } ; @@ -16017,7 +16017,7 @@ module mkFetchStage(CLK, napTrainByExe$whas ? napTrainByExe$wget[63:0] : napTrainByDecQ_data_0[63:0] ; - assign tval__h123547 = { x__h123136[63:2], 2'd0 } ; + assign tval__h123547 = { x__h123137[63:2], 2'd0 } ; assign upd__h175830 = next_deqP__h181686 ; assign upd__h2244 = x__h154964 + 64'd2 ; assign upd__h2271 = @@ -16110,7 +16110,7 @@ module mkFetchStage(CLK, (NOT_IF_pc_reg_dummy2_0_read__235_AND_pc_reg_du_ETC___d3532 ? 2'd2 : IF_NOT_IF_pc_reg_dummy2_0_read__235_AND_pc_reg_ETC___d3591) ; - assign x__h123545 = iTlb$to_proc_response_get[4] ? tval__h123547 : 64'd0 ; + assign x__h123541 = iTlb$to_proc_response_get[4] ? tval__h123547 : 64'd0 ; assign x__h125108 = x__h125124 + y__h125125 ; assign x__h125124 = { 1'd0, b__h125132 } ; assign x__h154964 = @@ -16481,15 +16481,15 @@ module mkFetchStage(CLK, always@(f12f2_deqP or f12f2_data_0 or f12f2_data_1) begin case (f12f2_deqP) - 1'd0: x__h123136 = f12f2_data_0[134:71]; - 1'd1: x__h123136 = f12f2_data_1[134:71]; + 1'd0: x__h123137 = f12f2_data_0[134:71]; + 1'd1: x__h123137 = f12f2_data_1[134:71]; endcase end always@(f12f2_deqP or f12f2_data_0 or f12f2_data_1) begin case (f12f2_deqP) - 1'd0: out_main_epoch__h123143 = f12f2_data_0[3:0]; - 1'd1: out_main_epoch__h123143 = f12f2_data_1[3:0]; + 1'd0: out_main_epoch__h123144 = f12f2_data_0[3:0]; + 1'd1: out_main_epoch__h123144 = f12f2_data_1[3:0]; endcase end always@(f32d_deqP or f32d_data_0 or f32d_data_1) diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkFmaExecQ.v b/src_SSITH_P3_sim/Verilog_RTL/mkFmaExecQ.v index 6aaa7af..19077ae 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkFmaExecQ.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkFmaExecQ.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkFpuMulDivDispToRegFifo.v b/src_SSITH_P3_sim/Verilog_RTL/mkFpuMulDivDispToRegFifo.v index 747f438..6b1a6b1 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkFpuMulDivDispToRegFifo.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkFpuMulDivDispToRegFifo.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkFpuMulDivRegToExeFifo.v b/src_SSITH_P3_sim/Verilog_RTL/mkFpuMulDivRegToExeFifo.v index 1ca18e2..eace33b 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkFpuMulDivRegToExeFifo.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkFpuMulDivRegToExeFifo.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkGSelectGHistReg.v b/src_SSITH_P3_sim/Verilog_RTL/mkGSelectGHistReg.v index bd0ef05..582c46c 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkGSelectGHistReg.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkGSelectGHistReg.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkGSelectPred.v b/src_SSITH_P3_sim/Verilog_RTL/mkGSelectPred.v index 36e3384..a99ba17 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkGSelectPred.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkGSelectPred.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkGShareGHistReg.v b/src_SSITH_P3_sim/Verilog_RTL/mkGShareGHistReg.v index 5237458..8f2496d 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkGShareGHistReg.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkGShareGHistReg.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkGSharePred.v b/src_SSITH_P3_sim/Verilog_RTL/mkGSharePred.v index e5cd5b3..633084f 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkGSharePred.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkGSharePred.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkIBankWrapper.v b/src_SSITH_P3_sim/Verilog_RTL/mkIBankWrapper.v index 3c3850c..5901f61 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkIBankWrapper.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkIBankWrapper.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkICRqMshrWrapper.v b/src_SSITH_P3_sim/Verilog_RTL/mkICRqMshrWrapper.v index 5aaf0d0..6ed7b4a 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkICRqMshrWrapper.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkICRqMshrWrapper.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkICoCache.v b/src_SSITH_P3_sim/Verilog_RTL/mkICoCache.v index 0e9a76c..a18b0ec 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkICoCache.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkICoCache.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkIPRqMshrWrapper.v b/src_SSITH_P3_sim/Verilog_RTL/mkIPRqMshrWrapper.v index d499b8d..5290f98 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkIPRqMshrWrapper.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkIPRqMshrWrapper.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkIPipeline.v b/src_SSITH_P3_sim/Verilog_RTL/mkIPipeline.v index eb4e57b..6e61d33 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkIPipeline.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkIPipeline.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkITlb.v b/src_SSITH_P3_sim/Verilog_RTL/mkITlb.v index 440353a..b2aa8ab 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkITlb.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkITlb.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkJtagTap.v b/src_SSITH_P3_sim/Verilog_RTL/mkJtagTap.v index 7ed7f93..b462cf5 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkJtagTap.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkJtagTap.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkL2Tlb.v b/src_SSITH_P3_sim/Verilog_RTL/mkL2Tlb.v index 77d8041..610e16a 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkL2Tlb.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkL2Tlb.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkLLCache.v b/src_SSITH_P3_sim/Verilog_RTL/mkLLCache.v index f501a66..975be47 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkLLCache.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkLLCache.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkLLPipeline.v b/src_SSITH_P3_sim/Verilog_RTL/mkLLPipeline.v index ae3fee0..fd210a2 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkLLPipeline.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkLLPipeline.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkLSQIssueLdQ.v b/src_SSITH_P3_sim/Verilog_RTL/mkLSQIssueLdQ.v index 0fee9f3..2d74df5 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkLSQIssueLdQ.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkLSQIssueLdQ.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkLastLvCRqMshr.v b/src_SSITH_P3_sim/Verilog_RTL/mkLastLvCRqMshr.v index 1344419..68735ad 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkLastLvCRqMshr.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkLastLvCRqMshr.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkMMIOInst.v b/src_SSITH_P3_sim/Verilog_RTL/mkMMIOInst.v index 93a5651..fbe0527 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkMMIOInst.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkMMIOInst.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkMemDispToRegFifo.v b/src_SSITH_P3_sim/Verilog_RTL/mkMemDispToRegFifo.v index 7aeffc6..2b1d0ad 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkMemDispToRegFifo.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkMemDispToRegFifo.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkMemLoader.v b/src_SSITH_P3_sim/Verilog_RTL/mkMemLoader.v index 1a85428..691d049 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkMemLoader.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkMemLoader.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkMemRegToExeFifo.v b/src_SSITH_P3_sim/Verilog_RTL/mkMemRegToExeFifo.v index 5ae0a73..ea15a1b 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkMemRegToExeFifo.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkMemRegToExeFifo.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkMinimumExecQ.v b/src_SSITH_P3_sim/Verilog_RTL/mkMinimumExecQ.v index bf4cf31..62600d8 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkMinimumExecQ.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkMinimumExecQ.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkMulExecQ.v b/src_SSITH_P3_sim/Verilog_RTL/mkMulExecQ.v index 9d7746d..7ef963e 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkMulExecQ.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkMulExecQ.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkNullTransCache.v b/src_SSITH_P3_sim/Verilog_RTL/mkNullTransCache.v index 394b69f..a186981 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkNullTransCache.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkNullTransCache.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkP3_Core.v b/src_SSITH_P3_sim/Verilog_RTL/mkP3_Core.v index 367c687..343d619 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkP3_Core.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkP3_Core.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // @@ -18,7 +18,6 @@ // master0_awqos O 4 reg // master0_awregion O 4 reg // master0_wvalid O 1 -// master0_wid O 4 reg // master0_wdata O 64 reg // master0_wstrb O 8 reg // master0_wlast O 1 reg @@ -47,7 +46,6 @@ // master1_awqos O 4 reg // master1_awregion O 4 reg // master1_wvalid O 1 reg -// master1_wid O 4 reg // master1_wdata O 64 reg // master1_wstrb O 8 reg // master1_wlast O 1 reg @@ -64,11 +62,6 @@ // master1_arqos O 4 reg // master1_arregion O 4 reg // master1_rready O 1 reg -// tv_verifier_info_tx_tvalid O 1 reg -// tv_verifier_info_tx_tdata O 608 reg -// tv_verifier_info_tx_tstrb O 76 reg -// tv_verifier_info_tx_tkeep O 76 reg -// tv_verifier_info_tx_tlast O 1 reg // jtag_tdo O 1 // CLK_jtag_tclk_out O 1 clock // CLK_GATE_jtag_tclk_out O 1 const @@ -97,8 +90,7 @@ // master1_rresp I 2 reg // master1_rlast I 1 reg // cpu_external_interrupt_req I 16 -// debug_external_interrupt_req_set_not_clear I 1 -// tv_verifier_info_tx_tready I 1 +// debug_external_interrupt_req_set_not_clear I 1 unused // jtag_tdi I 1 // jtag_tms I 1 // jtag_tclk I 1 @@ -150,8 +142,6 @@ module mkP3_Core(CLK, master0_wvalid, - master0_wid, - master0_wdata, master0_wstrb, @@ -224,8 +214,6 @@ module mkP3_Core(CLK, master1_wvalid, - master1_wid, - master1_wdata, master1_wstrb, @@ -276,18 +264,6 @@ module mkP3_Core(CLK, debug_external_interrupt_req_set_not_clear, - tv_verifier_info_tx_tvalid, - - tv_verifier_info_tx_tdata, - - tv_verifier_info_tx_tstrb, - - tv_verifier_info_tx_tkeep, - - tv_verifier_info_tx_tlast, - - tv_verifier_info_tx_tready, - jtag_tdi, jtag_tms, @@ -342,9 +318,6 @@ module mkP3_Core(CLK, // value method master0_m_wvalid output master0_wvalid; - // value method master0_m_wid - output [3 : 0] master0_wid; - // value method master0_m_wdata output [63 : 0] master0_wdata; @@ -456,9 +429,6 @@ module mkP3_Core(CLK, // value method master1_m_wvalid output master1_wvalid; - // value method master1_m_wid - output [3 : 0] master1_wid; - // value method master1_m_wdata output [63 : 0] master1_wdata; @@ -535,30 +505,6 @@ module mkP3_Core(CLK, // action method debug_external_interrupt_req input debug_external_interrupt_req_set_not_clear; - // value method tv_verifier_info_tx_m_tvalid - output tv_verifier_info_tx_tvalid; - - // value method tv_verifier_info_tx_m_tid - - // value method tv_verifier_info_tx_m_tdata - output [607 : 0] tv_verifier_info_tx_tdata; - - // value method tv_verifier_info_tx_m_tstrb - output [75 : 0] tv_verifier_info_tx_tstrb; - - // value method tv_verifier_info_tx_m_tkeep - output [75 : 0] tv_verifier_info_tx_tkeep; - - // value method tv_verifier_info_tx_m_tlast - output tv_verifier_info_tx_tlast; - - // value method tv_verifier_info_tx_m_tdest - - // value method tv_verifier_info_tx_m_tuser - - // action method tv_verifier_info_tx_m_tready - input tv_verifier_info_tx_tready; - // action method jtag_tdi input jtag_tdi; @@ -576,8 +522,6 @@ module mkP3_Core(CLK, output CLK_GATE_jtag_tclk_out; // signals for module outputs - wire [607 : 0] tv_verifier_info_tx_tdata; - wire [75 : 0] tv_verifier_info_tx_tkeep, tv_verifier_info_tx_tstrb; wire [63 : 0] master0_araddr, master0_awaddr, master0_wdata, @@ -598,7 +542,6 @@ module mkP3_Core(CLK, master0_awid, master0_awqos, master0_awregion, - master0_wid, master1_arcache, master1_arid, master1_arqos, @@ -606,8 +549,7 @@ module mkP3_Core(CLK, master1_awcache, master1_awid, master1_awqos, - master1_awregion, - master1_wid; + master1_awregion; wire [2 : 0] master0_arprot, master0_arsize, master0_awprot, @@ -638,9 +580,7 @@ module mkP3_Core(CLK, master1_bready, master1_rready, master1_wlast, - master1_wvalid, - tv_verifier_info_tx_tlast, - tv_verifier_info_tx_tvalid; + master1_wvalid; // inlined wires wire [40 : 0] bus_dmi_req_data_wire$wget; @@ -661,9 +601,14 @@ module mkP3_Core(CLK, reg [33 : 0] bus_dmi_rsp_fifof_q_1$D_IN; wire bus_dmi_rsp_fifof_q_1$EN; - // register rg_once - reg rg_once; - wire rg_once$D_IN, rg_once$EN; + // register rg_corew_start_after_por + reg rg_corew_start_after_por; + wire rg_corew_start_after_por$D_IN, rg_corew_start_after_por$EN; + + // register rg_ndm_reset_delay + reg [7 : 0] rg_ndm_reset_delay; + wire [7 : 0] rg_ndm_reset_delay$D_IN; + wire rg_ndm_reset_delay$EN; // ports of submodule bus_dmi_req_fifof wire [40 : 0] bus_dmi_req_fifof$D_IN, bus_dmi_req_fifof$D_OUT; @@ -674,7 +619,6 @@ module mkP3_Core(CLK, bus_dmi_req_fifof$FULL_N; // ports of submodule corew - wire [607 : 0] corew$tv_verifier_info_get_get; wire [63 : 0] corew$cpu_dmem_master_araddr, corew$cpu_dmem_master_awaddr, corew$cpu_dmem_master_rdata, @@ -683,17 +627,17 @@ module mkP3_Core(CLK, corew$cpu_imem_master_awaddr, corew$cpu_imem_master_rdata, corew$cpu_imem_master_wdata, - corew$set_htif_addrs_fromhost_addr, - corew$set_htif_addrs_tohost_addr, - corew$set_verbosity_logdelay; - wire [31 : 0] corew$dm_dmi_read_data, corew$dm_dmi_write_dm_word; + corew$set_verbosity_logdelay, + corew$start_fromhost_addr, + corew$start_tohost_addr; + wire [31 : 0] corew$dmi_read_data, corew$dmi_write_dm_word; wire [7 : 0] corew$cpu_dmem_master_arlen, corew$cpu_dmem_master_awlen, corew$cpu_dmem_master_wstrb, corew$cpu_imem_master_arlen, corew$cpu_imem_master_awlen, corew$cpu_imem_master_wstrb; - wire [6 : 0] corew$dm_dmi_read_addr_dm_addr, corew$dm_dmi_write_dm_addr; + wire [6 : 0] corew$dmi_read_addr_dm_addr, corew$dmi_write_dm_addr; wire [3 : 0] corew$cpu_dmem_master_arcache, corew$cpu_dmem_master_arid, corew$cpu_dmem_master_arqos, @@ -704,7 +648,6 @@ module mkP3_Core(CLK, corew$cpu_dmem_master_awregion, corew$cpu_dmem_master_bid, corew$cpu_dmem_master_rid, - corew$cpu_dmem_master_wid, corew$cpu_imem_master_arcache, corew$cpu_imem_master_arid, corew$cpu_imem_master_arqos, @@ -715,7 +658,6 @@ module mkP3_Core(CLK, corew$cpu_imem_master_awregion, corew$cpu_imem_master_bid, corew$cpu_imem_master_rid, - corew$cpu_imem_master_wid, corew$set_verbosity_verbosity; wire [2 : 0] corew$cpu_dmem_master_arprot, corew$cpu_dmem_master_arsize, @@ -733,22 +675,19 @@ module mkP3_Core(CLK, corew$cpu_imem_master_awburst, corew$cpu_imem_master_bresp, corew$cpu_imem_master_rresp; - wire corew$EN_cpu_reset_server_request_put, - corew$EN_cpu_reset_server_response_get, - corew$EN_dm_dmi_read_addr, - corew$EN_dm_dmi_read_data, - corew$EN_dm_dmi_write, - corew$EN_dm_ndm_reset_req_get_get, - corew$EN_set_htif_addrs, + wire corew$EN_dmi_read_addr, + corew$EN_dmi_read_data, + corew$EN_dmi_write, + corew$EN_ndm_reset_client_request_get, + corew$EN_ndm_reset_client_response_put, corew$EN_set_verbosity, - corew$EN_tv_verifier_info_get_get, - corew$RDY_cpu_reset_server_request_put, - corew$RDY_cpu_reset_server_response_get, - corew$RDY_dm_dmi_read_addr, - corew$RDY_dm_dmi_read_data, - corew$RDY_dm_dmi_write, - corew$RDY_dm_ndm_reset_req_get_get, - corew$RDY_tv_verifier_info_get_get, + corew$EN_start, + corew$RDY_dmi_read_addr, + corew$RDY_dmi_read_data, + corew$RDY_dmi_write, + corew$RDY_ndm_reset_client_request_get, + corew$RDY_ndm_reset_client_response_put, + corew$RDY_start, corew$core_external_interrupt_sources_0_m_interrupt_req_set_not_clear, corew$core_external_interrupt_sources_10_m_interrupt_req_set_not_clear, corew$core_external_interrupt_sources_11_m_interrupt_req_set_not_clear, @@ -793,7 +732,8 @@ module mkP3_Core(CLK, corew$cpu_imem_master_wlast, corew$cpu_imem_master_wready, corew$cpu_imem_master_wvalid, - corew$debug_external_interrupt_req_set_not_clear; + corew$ndm_reset_client_response_put, + corew$nmi_req_set_not_clear; // ports of submodule jtagtap wire [31 : 0] jtagtap$dmi_req_data, jtagtap$dmi_rsp_data; @@ -809,14 +749,11 @@ module mkP3_Core(CLK, jtagtap$jtag_tdo, jtagtap$jtag_tms; - // ports of submodule tv_xactor - wire [607 : 0] tv_xactor$axi_out_tdata, tv_xactor$tv_in_put; - wire [75 : 0] tv_xactor$axi_out_tkeep, tv_xactor$axi_out_tstrb; - wire tv_xactor$EN_tv_in_put, - tv_xactor$RDY_tv_in_put, - tv_xactor$axi_out_tlast, - tv_xactor$axi_out_tready, - tv_xactor$axi_out_tvalid; + // ports of submodule ndm_reset + wire ndm_reset$RST_OUT; + + // ports of submodule ndm_reset_controller + wire ndm_reset_controller$ASSERT_IN, ndm_reset_controller$OUT_RST; // rule scheduling signals wire CAN_FIRE_RL_bus_dmi_req_do_enq, @@ -824,7 +761,6 @@ module mkP3_Core(CLK, CAN_FIRE_RL_bus_dmi_rsp_fifof_both, CAN_FIRE_RL_bus_dmi_rsp_fifof_decCtr, CAN_FIRE_RL_bus_dmi_rsp_fifof_incCtr, - CAN_FIRE_RL_mkConnectionGetPut, CAN_FIRE_RL_mkConnectionVtoAf, CAN_FIRE_RL_mkConnectionVtoAf_1, CAN_FIRE_RL_mkConnectionVtoAf_2, @@ -834,13 +770,14 @@ module mkP3_Core(CLK, CAN_FIRE_RL_mkConnectionVtoAf_6, CAN_FIRE_RL_mkConnectionVtoAf_7, CAN_FIRE_RL_mkConnectionVtoAf_8, + CAN_FIRE_RL_rl_always, CAN_FIRE_RL_rl_dmi_req, CAN_FIRE_RL_rl_dmi_req_cpu, CAN_FIRE_RL_rl_dmi_rsp, CAN_FIRE_RL_rl_dmi_rsp_cpu, - CAN_FIRE_RL_rl_ndmreset, - CAN_FIRE_RL_rl_once, - CAN_FIRE_RL_rl_reset_response, + CAN_FIRE_RL_rl_ndm_reset, + CAN_FIRE_RL_rl_ndm_reset_wait, + CAN_FIRE_RL_rl_step_0, CAN_FIRE_debug_external_interrupt_req, CAN_FIRE_interrupt_reqs, CAN_FIRE_jtag_tclk, @@ -856,13 +793,11 @@ module mkP3_Core(CLK, CAN_FIRE_master1_m_bvalid, CAN_FIRE_master1_m_rvalid, CAN_FIRE_master1_m_wready, - CAN_FIRE_tv_verifier_info_tx_m_tready, WILL_FIRE_RL_bus_dmi_req_do_enq, WILL_FIRE_RL_bus_dmi_rsp_do_deq, WILL_FIRE_RL_bus_dmi_rsp_fifof_both, WILL_FIRE_RL_bus_dmi_rsp_fifof_decCtr, WILL_FIRE_RL_bus_dmi_rsp_fifof_incCtr, - WILL_FIRE_RL_mkConnectionGetPut, WILL_FIRE_RL_mkConnectionVtoAf, WILL_FIRE_RL_mkConnectionVtoAf_1, WILL_FIRE_RL_mkConnectionVtoAf_2, @@ -872,13 +807,14 @@ module mkP3_Core(CLK, WILL_FIRE_RL_mkConnectionVtoAf_6, WILL_FIRE_RL_mkConnectionVtoAf_7, WILL_FIRE_RL_mkConnectionVtoAf_8, + WILL_FIRE_RL_rl_always, WILL_FIRE_RL_rl_dmi_req, WILL_FIRE_RL_rl_dmi_req_cpu, WILL_FIRE_RL_rl_dmi_rsp, WILL_FIRE_RL_rl_dmi_rsp_cpu, - WILL_FIRE_RL_rl_ndmreset, - WILL_FIRE_RL_rl_once, - WILL_FIRE_RL_rl_reset_response, + WILL_FIRE_RL_rl_ndm_reset, + WILL_FIRE_RL_rl_ndm_reset_wait, + WILL_FIRE_RL_rl_step_0, WILL_FIRE_debug_external_interrupt_req, WILL_FIRE_interrupt_reqs, WILL_FIRE_jtag_tclk, @@ -893,25 +829,34 @@ module mkP3_Core(CLK, WILL_FIRE_master1_m_awready, WILL_FIRE_master1_m_bvalid, WILL_FIRE_master1_m_rvalid, - WILL_FIRE_master1_m_wready, - WILL_FIRE_tv_verifier_info_tx_m_tready; + WILL_FIRE_master1_m_wready; // inputs to muxes for submodule ports wire [33 : 0] MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_1, MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_2, - MUX_bus_dmi_rsp_fifof_q_1$write_1__VAL_2, + MUX_bus_dmi_rsp_fifof_q_1$write_1__VAL_1, MUX_bus_dmi_rsp_fifof_x_wire$wset_1__VAL_1, MUX_bus_dmi_rsp_fifof_x_wire$wset_1__VAL_2; + wire [7 : 0] MUX_rg_ndm_reset_delay$write_1__VAL_1; wire [1 : 0] MUX_bus_dmi_rsp_fifof_cntr_r$write_1__VAL_2; wire MUX_bus_dmi_rsp_fifof_q_0$write_1__SEL_1, MUX_bus_dmi_rsp_fifof_q_0$write_1__SEL_2, MUX_bus_dmi_rsp_fifof_q_1$write_1__SEL_1, MUX_bus_dmi_rsp_fifof_q_1$write_1__SEL_2, - MUX_bus_dmi_rsp_fifof_x_wire$wset_1__SEL_1; + MUX_bus_dmi_rsp_fifof_x_wire$wset_1__SEL_1, + MUX_corew$start_1__SEL_1; + + // declarations used by system tasks + // synopsys translate_off + reg [31 : 0] v__h1270; + reg [31 : 0] v__h1415; + reg [31 : 0] v__h1264; + reg [31 : 0] v__h1409; + // synopsys translate_on // remaining internal signals - wire [1 : 0] bus_dmi_rsp_fifof_cntr_r_0_MINUS_1___d28; - wire IF_bus_dmi_req_fifof_first__7_BITS_1_TO_0_8_EQ_ETC___d78, + wire [1 : 0] bus_dmi_rsp_fifof_cntr_r_4_MINUS_1___d42; + wire IF_bus_dmi_req_fifof_first__1_BITS_1_TO_0_2_EQ_ETC___d92, _dfoo1, _dfoo3; @@ -959,9 +904,6 @@ module mkP3_Core(CLK, // value method master0_m_wvalid assign master0_wvalid = corew$cpu_imem_master_wvalid ; - // value method master0_m_wid - assign master0_wid = corew$cpu_imem_master_wid ; - // value method master0_m_wdata assign master0_wdata = corew$cpu_imem_master_wdata ; @@ -1066,9 +1008,6 @@ module mkP3_Core(CLK, // value method master1_m_wvalid assign master1_wvalid = corew$cpu_dmem_master_wvalid ; - // value method master1_m_wid - assign master1_wid = corew$cpu_dmem_master_wid ; - // value method master1_m_wdata assign master1_wdata = corew$cpu_dmem_master_wdata ; @@ -1141,25 +1080,6 @@ module mkP3_Core(CLK, assign CAN_FIRE_debug_external_interrupt_req = 1'd1 ; assign WILL_FIRE_debug_external_interrupt_req = 1'd1 ; - // value method tv_verifier_info_tx_m_tvalid - assign tv_verifier_info_tx_tvalid = tv_xactor$axi_out_tvalid ; - - // value method tv_verifier_info_tx_m_tdata - assign tv_verifier_info_tx_tdata = tv_xactor$axi_out_tdata ; - - // value method tv_verifier_info_tx_m_tstrb - assign tv_verifier_info_tx_tstrb = tv_xactor$axi_out_tstrb ; - - // value method tv_verifier_info_tx_m_tkeep - assign tv_verifier_info_tx_tkeep = tv_xactor$axi_out_tkeep ; - - // value method tv_verifier_info_tx_m_tlast - assign tv_verifier_info_tx_tlast = tv_xactor$axi_out_tlast ; - - // action method tv_verifier_info_tx_m_tready - assign CAN_FIRE_tv_verifier_info_tx_m_tready = 1'd1 ; - assign WILL_FIRE_tv_verifier_info_tx_m_tready = 1'd1 ; - // action method jtag_tdi assign CAN_FIRE_jtag_tdi = 1'd1 ; assign WILL_FIRE_jtag_tdi = 1'd1 ; @@ -1187,8 +1107,9 @@ module mkP3_Core(CLK, .EMPTY_N(bus_dmi_req_fifof$EMPTY_N)); // submodule corew - mkCoreW corew(.CLK(CLK), - .RST_N(RST_N), + mkCoreW corew(.RST_N_dm_power_on_reset(RST_N), + .CLK(CLK), + .RST_N(ndm_reset$RST_OUT), .core_external_interrupt_sources_0_m_interrupt_req_set_not_clear(corew$core_external_interrupt_sources_0_m_interrupt_req_set_not_clear), .core_external_interrupt_sources_10_m_interrupt_req_set_not_clear(corew$core_external_interrupt_sources_10_m_interrupt_req_set_not_clear), .core_external_interrupt_sources_11_m_interrupt_req_set_not_clear(corew$core_external_interrupt_sources_11_m_interrupt_req_set_not_clear), @@ -1227,27 +1148,24 @@ module mkP3_Core(CLK, .cpu_imem_master_rresp(corew$cpu_imem_master_rresp), .cpu_imem_master_rvalid(corew$cpu_imem_master_rvalid), .cpu_imem_master_wready(corew$cpu_imem_master_wready), - .debug_external_interrupt_req_set_not_clear(corew$debug_external_interrupt_req_set_not_clear), - .dm_dmi_read_addr_dm_addr(corew$dm_dmi_read_addr_dm_addr), - .dm_dmi_write_dm_addr(corew$dm_dmi_write_dm_addr), - .dm_dmi_write_dm_word(corew$dm_dmi_write_dm_word), - .set_htif_addrs_fromhost_addr(corew$set_htif_addrs_fromhost_addr), - .set_htif_addrs_tohost_addr(corew$set_htif_addrs_tohost_addr), + .dmi_read_addr_dm_addr(corew$dmi_read_addr_dm_addr), + .dmi_write_dm_addr(corew$dmi_write_dm_addr), + .dmi_write_dm_word(corew$dmi_write_dm_word), + .ndm_reset_client_response_put(corew$ndm_reset_client_response_put), + .nmi_req_set_not_clear(corew$nmi_req_set_not_clear), .set_verbosity_logdelay(corew$set_verbosity_logdelay), .set_verbosity_verbosity(corew$set_verbosity_verbosity), + .start_fromhost_addr(corew$start_fromhost_addr), + .start_tohost_addr(corew$start_tohost_addr), .EN_set_verbosity(corew$EN_set_verbosity), - .EN_set_htif_addrs(corew$EN_set_htif_addrs), - .EN_cpu_reset_server_request_put(corew$EN_cpu_reset_server_request_put), - .EN_cpu_reset_server_response_get(corew$EN_cpu_reset_server_response_get), - .EN_dm_dmi_read_addr(corew$EN_dm_dmi_read_addr), - .EN_dm_dmi_read_data(corew$EN_dm_dmi_read_data), - .EN_dm_dmi_write(corew$EN_dm_dmi_write), - .EN_dm_ndm_reset_req_get_get(corew$EN_dm_ndm_reset_req_get_get), - .EN_tv_verifier_info_get_get(corew$EN_tv_verifier_info_get_get), + .EN_start(corew$EN_start), + .EN_dmi_read_addr(corew$EN_dmi_read_addr), + .EN_dmi_read_data(corew$EN_dmi_read_data), + .EN_dmi_write(corew$EN_dmi_write), + .EN_ndm_reset_client_request_get(corew$EN_ndm_reset_client_request_get), + .EN_ndm_reset_client_response_put(corew$EN_ndm_reset_client_response_put), .RDY_set_verbosity(), - .RDY_set_htif_addrs(), - .RDY_cpu_reset_server_request_put(corew$RDY_cpu_reset_server_request_put), - .RDY_cpu_reset_server_response_get(corew$RDY_cpu_reset_server_response_get), + .RDY_start(corew$RDY_start), .cpu_imem_master_awvalid(corew$cpu_imem_master_awvalid), .cpu_imem_master_awid(corew$cpu_imem_master_awid), .cpu_imem_master_awaddr(corew$cpu_imem_master_awaddr), @@ -1260,7 +1178,6 @@ module mkP3_Core(CLK, .cpu_imem_master_awqos(corew$cpu_imem_master_awqos), .cpu_imem_master_awregion(corew$cpu_imem_master_awregion), .cpu_imem_master_wvalid(corew$cpu_imem_master_wvalid), - .cpu_imem_master_wid(corew$cpu_imem_master_wid), .cpu_imem_master_wdata(corew$cpu_imem_master_wdata), .cpu_imem_master_wstrb(corew$cpu_imem_master_wstrb), .cpu_imem_master_wlast(corew$cpu_imem_master_wlast), @@ -1289,7 +1206,6 @@ module mkP3_Core(CLK, .cpu_dmem_master_awqos(corew$cpu_dmem_master_awqos), .cpu_dmem_master_awregion(corew$cpu_dmem_master_awregion), .cpu_dmem_master_wvalid(corew$cpu_dmem_master_wvalid), - .cpu_dmem_master_wid(corew$cpu_dmem_master_wid), .cpu_dmem_master_wdata(corew$cpu_dmem_master_wdata), .cpu_dmem_master_wstrb(corew$cpu_dmem_master_wstrb), .cpu_dmem_master_wlast(corew$cpu_dmem_master_wlast), @@ -1306,13 +1222,13 @@ module mkP3_Core(CLK, .cpu_dmem_master_arqos(corew$cpu_dmem_master_arqos), .cpu_dmem_master_arregion(corew$cpu_dmem_master_arregion), .cpu_dmem_master_rready(corew$cpu_dmem_master_rready), - .RDY_dm_dmi_read_addr(corew$RDY_dm_dmi_read_addr), - .dm_dmi_read_data(corew$dm_dmi_read_data), - .RDY_dm_dmi_read_data(corew$RDY_dm_dmi_read_data), - .RDY_dm_dmi_write(corew$RDY_dm_dmi_write), - .RDY_dm_ndm_reset_req_get_get(corew$RDY_dm_ndm_reset_req_get_get), - .tv_verifier_info_get_get(corew$tv_verifier_info_get_get), - .RDY_tv_verifier_info_get_get(corew$RDY_tv_verifier_info_get_get)); + .RDY_dmi_read_addr(corew$RDY_dmi_read_addr), + .dmi_read_data(corew$dmi_read_data), + .RDY_dmi_read_data(corew$RDY_dmi_read_data), + .RDY_dmi_write(corew$RDY_dmi_write), + .ndm_reset_client_request_get(), + .RDY_ndm_reset_client_request_get(corew$RDY_ndm_reset_client_request_get), + .RDY_ndm_reset_client_response_put(corew$RDY_ndm_reset_client_response_put)); // submodule jtagtap mkJtagTap jtagtap(.CLK(CLK), @@ -1333,34 +1249,34 @@ module mkP3_Core(CLK, .CLK_jtag_tclk_out(jtagtap$CLK_jtag_tclk_out), .CLK_GATE_jtag_tclk_out()); - // submodule tv_xactor - mkTV_Xactor tv_xactor(.CLK(CLK), - .RST_N(RST_N), - .axi_out_tready(tv_xactor$axi_out_tready), - .tv_in_put(tv_xactor$tv_in_put), - .EN_tv_in_put(tv_xactor$EN_tv_in_put), - .RDY_tv_in_put(tv_xactor$RDY_tv_in_put), - .axi_out_tvalid(tv_xactor$axi_out_tvalid), - .axi_out_tdata(tv_xactor$axi_out_tdata), - .axi_out_tstrb(tv_xactor$axi_out_tstrb), - .axi_out_tkeep(tv_xactor$axi_out_tkeep), - .axi_out_tlast(tv_xactor$axi_out_tlast)); + // submodule ndm_reset + ResetEither ndm_reset(.A_RST(RST_N), + .B_RST(ndm_reset_controller$OUT_RST), + .RST_OUT(ndm_reset$RST_OUT)); - // rule RL_rl_once - assign CAN_FIRE_RL_rl_once = - corew$RDY_cpu_reset_server_request_put && !rg_once ; - assign WILL_FIRE_RL_rl_once = CAN_FIRE_RL_rl_once ; + // submodule ndm_reset_controller + MakeResetA #(.RSTDELAY(32'd10), .init(1'd1)) ndm_reset_controller(.CLK(CLK), + .RST(RST_N), + .DST_CLK(CLK), + .ASSERT_IN(ndm_reset_controller$ASSERT_IN), + .ASSERT_OUT(), + .OUT_RST(ndm_reset_controller$OUT_RST)); - // rule RL_rl_reset_response - assign CAN_FIRE_RL_rl_reset_response = - corew$RDY_cpu_reset_server_response_get ; - assign WILL_FIRE_RL_rl_reset_response = - corew$RDY_cpu_reset_server_response_get ; + // rule RL_rl_always + assign CAN_FIRE_RL_rl_always = 1'd1 ; + assign WILL_FIRE_RL_rl_always = 1'd1 ; - // rule RL_rl_ndmreset - assign CAN_FIRE_RL_rl_ndmreset = - corew$RDY_dm_ndm_reset_req_get_get && rg_once ; - assign WILL_FIRE_RL_rl_ndmreset = CAN_FIRE_RL_rl_ndmreset ; + // rule RL_rl_ndm_reset + assign CAN_FIRE_RL_rl_ndm_reset = + corew$RDY_ndm_reset_client_request_get && + rg_ndm_reset_delay == 8'd0 ; + assign WILL_FIRE_RL_rl_ndm_reset = CAN_FIRE_RL_rl_ndm_reset ; + + // rule RL_rl_step_0 + assign CAN_FIRE_RL_rl_step_0 = + corew$RDY_start && !rg_corew_start_after_por ; + assign WILL_FIRE_RL_rl_step_0 = + CAN_FIRE_RL_rl_step_0 && !WILL_FIRE_RL_rl_ndm_reset_wait ; // rule RL_mkConnectionVtoAf assign CAN_FIRE_RL_mkConnectionVtoAf = 1'd1 ; @@ -1409,19 +1325,21 @@ module mkP3_Core(CLK, // rule RL_rl_dmi_req_cpu assign CAN_FIRE_RL_rl_dmi_req_cpu = bus_dmi_req_fifof$EMPTY_N && - IF_bus_dmi_req_fifof_first__7_BITS_1_TO_0_8_EQ_ETC___d78 ; + IF_bus_dmi_req_fifof_first__1_BITS_1_TO_0_2_EQ_ETC___d92 ; assign WILL_FIRE_RL_rl_dmi_req_cpu = CAN_FIRE_RL_rl_dmi_req_cpu ; // rule RL_rl_dmi_rsp_cpu assign CAN_FIRE_RL_rl_dmi_rsp_cpu = - bus_dmi_rsp_fifof_cntr_r != 2'd2 && corew$RDY_dm_dmi_read_data ; + bus_dmi_rsp_fifof_cntr_r != 2'd2 && corew$RDY_dmi_read_data ; assign WILL_FIRE_RL_rl_dmi_rsp_cpu = CAN_FIRE_RL_rl_dmi_rsp_cpu && !WILL_FIRE_RL_rl_dmi_req_cpu ; - // rule RL_mkConnectionGetPut - assign CAN_FIRE_RL_mkConnectionGetPut = - corew$RDY_tv_verifier_info_get_get && tv_xactor$RDY_tv_in_put ; - assign WILL_FIRE_RL_mkConnectionGetPut = CAN_FIRE_RL_mkConnectionGetPut ; + // rule RL_rl_ndm_reset_wait + assign CAN_FIRE_RL_rl_ndm_reset_wait = + (rg_ndm_reset_delay != 8'd1 || + corew$RDY_ndm_reset_client_response_put && corew$RDY_start) && + rg_ndm_reset_delay != 8'd0 ; + assign WILL_FIRE_RL_rl_ndm_reset_wait = CAN_FIRE_RL_rl_ndm_reset_wait ; // rule RL_bus_dmi_req_do_enq assign CAN_FIRE_RL_bus_dmi_req_do_enq = @@ -1458,37 +1376,40 @@ module mkP3_Core(CLK, // inputs to muxes for submodule ports assign MUX_bus_dmi_rsp_fifof_q_0$write_1__SEL_1 = + WILL_FIRE_RL_bus_dmi_rsp_fifof_both && _dfoo3 ; + assign MUX_bus_dmi_rsp_fifof_q_0$write_1__SEL_2 = WILL_FIRE_RL_bus_dmi_rsp_fifof_incCtr && bus_dmi_rsp_fifof_cntr_r == 2'd0 ; - assign MUX_bus_dmi_rsp_fifof_q_0$write_1__SEL_2 = - WILL_FIRE_RL_bus_dmi_rsp_fifof_both && _dfoo3 ; assign MUX_bus_dmi_rsp_fifof_q_1$write_1__SEL_1 = + WILL_FIRE_RL_bus_dmi_rsp_fifof_both && _dfoo1 ; + assign MUX_bus_dmi_rsp_fifof_q_1$write_1__SEL_2 = WILL_FIRE_RL_bus_dmi_rsp_fifof_incCtr && bus_dmi_rsp_fifof_cntr_r == 2'd1 ; - assign MUX_bus_dmi_rsp_fifof_q_1$write_1__SEL_2 = - WILL_FIRE_RL_bus_dmi_rsp_fifof_both && _dfoo1 ; assign MUX_bus_dmi_rsp_fifof_x_wire$wset_1__SEL_1 = WILL_FIRE_RL_rl_dmi_req_cpu && bus_dmi_req_fifof$D_OUT[1:0] != 2'd1 ; + assign MUX_corew$start_1__SEL_1 = + WILL_FIRE_RL_rl_ndm_reset_wait && rg_ndm_reset_delay == 8'd1 ; assign MUX_bus_dmi_rsp_fifof_cntr_r$write_1__VAL_2 = bus_dmi_rsp_fifof_cntr_r + 2'd1 ; assign MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_1 = + (bus_dmi_rsp_fifof_cntr_r == 2'd1) ? + MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_2 : + bus_dmi_rsp_fifof_q_1 ; + assign MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_2 = MUX_bus_dmi_rsp_fifof_x_wire$wset_1__SEL_1 ? MUX_bus_dmi_rsp_fifof_x_wire$wset_1__VAL_1 : MUX_bus_dmi_rsp_fifof_x_wire$wset_1__VAL_2 ; - assign MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_2 = - (bus_dmi_rsp_fifof_cntr_r == 2'd1) ? - MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_1 : - bus_dmi_rsp_fifof_q_1 ; - assign MUX_bus_dmi_rsp_fifof_q_1$write_1__VAL_2 = + assign MUX_bus_dmi_rsp_fifof_q_1$write_1__VAL_1 = (bus_dmi_rsp_fifof_cntr_r == 2'd2) ? - MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_1 : + MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_2 : 34'd0 ; assign MUX_bus_dmi_rsp_fifof_x_wire$wset_1__VAL_1 = { 32'hAAAAAAAA, (bus_dmi_req_fifof$D_OUT[1:0] == 2'd2) ? 2'd0 : 2'd2 } ; assign MUX_bus_dmi_rsp_fifof_x_wire$wset_1__VAL_2 = - { corew$dm_dmi_read_data, 2'd0 } ; + { corew$dmi_read_data, 2'd0 } ; + assign MUX_rg_ndm_reset_delay$write_1__VAL_1 = rg_ndm_reset_delay - 8'd1 ; // inlined wires assign bus_dmi_rsp_fifof_enqueueing$whas = @@ -1503,7 +1424,7 @@ module mkP3_Core(CLK, // register bus_dmi_rsp_fifof_cntr_r assign bus_dmi_rsp_fifof_cntr_r$D_IN = WILL_FIRE_RL_bus_dmi_rsp_fifof_decCtr ? - bus_dmi_rsp_fifof_cntr_r_0_MINUS_1___d28 : + bus_dmi_rsp_fifof_cntr_r_4_MINUS_1___d42 : MUX_bus_dmi_rsp_fifof_cntr_r$write_1__VAL_2 ; assign bus_dmi_rsp_fifof_cntr_r$EN = WILL_FIRE_RL_bus_dmi_rsp_fifof_decCtr || @@ -1530,25 +1451,25 @@ module mkP3_Core(CLK, endcase end assign bus_dmi_rsp_fifof_q_0$EN = + WILL_FIRE_RL_bus_dmi_rsp_fifof_both && _dfoo3 || WILL_FIRE_RL_bus_dmi_rsp_fifof_incCtr && bus_dmi_rsp_fifof_cntr_r == 2'd0 || - WILL_FIRE_RL_bus_dmi_rsp_fifof_both && _dfoo3 || WILL_FIRE_RL_bus_dmi_rsp_fifof_decCtr ; // register bus_dmi_rsp_fifof_q_1 always@(MUX_bus_dmi_rsp_fifof_q_1$write_1__SEL_1 or - MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_1 or + MUX_bus_dmi_rsp_fifof_q_1$write_1__VAL_1 or MUX_bus_dmi_rsp_fifof_q_1$write_1__SEL_2 or - MUX_bus_dmi_rsp_fifof_q_1$write_1__VAL_2 or + MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_2 or WILL_FIRE_RL_bus_dmi_rsp_fifof_decCtr) begin case (1'b1) // synopsys parallel_case MUX_bus_dmi_rsp_fifof_q_1$write_1__SEL_1: bus_dmi_rsp_fifof_q_1$D_IN = - MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_1; + MUX_bus_dmi_rsp_fifof_q_1$write_1__VAL_1; MUX_bus_dmi_rsp_fifof_q_1$write_1__SEL_2: bus_dmi_rsp_fifof_q_1$D_IN = - MUX_bus_dmi_rsp_fifof_q_1$write_1__VAL_2; + MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_2; WILL_FIRE_RL_bus_dmi_rsp_fifof_decCtr: bus_dmi_rsp_fifof_q_1$D_IN = 34'd0; default: bus_dmi_rsp_fifof_q_1$D_IN = @@ -1556,14 +1477,22 @@ module mkP3_Core(CLK, endcase end assign bus_dmi_rsp_fifof_q_1$EN = + WILL_FIRE_RL_bus_dmi_rsp_fifof_both && _dfoo1 || WILL_FIRE_RL_bus_dmi_rsp_fifof_incCtr && bus_dmi_rsp_fifof_cntr_r == 2'd1 || - WILL_FIRE_RL_bus_dmi_rsp_fifof_both && _dfoo1 || WILL_FIRE_RL_bus_dmi_rsp_fifof_decCtr ; - // register rg_once - assign rg_once$D_IN = !WILL_FIRE_RL_rl_ndmreset ; - assign rg_once$EN = WILL_FIRE_RL_rl_ndmreset || WILL_FIRE_RL_rl_once ; + // register rg_corew_start_after_por + assign rg_corew_start_after_por$D_IN = 1'd1 ; + assign rg_corew_start_after_por$EN = WILL_FIRE_RL_rl_step_0 ; + + // register rg_ndm_reset_delay + assign rg_ndm_reset_delay$D_IN = + WILL_FIRE_RL_rl_ndm_reset_wait ? + MUX_rg_ndm_reset_delay$write_1__VAL_1 : + 8'd110 ; + assign rg_ndm_reset_delay$EN = + WILL_FIRE_RL_rl_ndm_reset_wait || WILL_FIRE_RL_rl_ndm_reset ; // submodule bus_dmi_req_fifof assign bus_dmi_req_fifof$D_IN = bus_dmi_req_data_wire$wget ; @@ -1626,29 +1555,28 @@ module mkP3_Core(CLK, assign corew$cpu_imem_master_rresp = master0_rresp ; assign corew$cpu_imem_master_rvalid = master0_rvalid ; assign corew$cpu_imem_master_wready = master0_wready ; - assign corew$debug_external_interrupt_req_set_not_clear = - debug_external_interrupt_req_set_not_clear ; - assign corew$dm_dmi_read_addr_dm_addr = bus_dmi_req_fifof$D_OUT[40:34] ; - assign corew$dm_dmi_write_dm_addr = bus_dmi_req_fifof$D_OUT[40:34] ; - assign corew$dm_dmi_write_dm_word = bus_dmi_req_fifof$D_OUT[33:2] ; - assign corew$set_htif_addrs_fromhost_addr = 64'h0 ; - assign corew$set_htif_addrs_tohost_addr = 64'h0 ; + assign corew$dmi_read_addr_dm_addr = bus_dmi_req_fifof$D_OUT[40:34] ; + assign corew$dmi_write_dm_addr = bus_dmi_req_fifof$D_OUT[40:34] ; + assign corew$dmi_write_dm_word = bus_dmi_req_fifof$D_OUT[33:2] ; + assign corew$ndm_reset_client_response_put = 1'd1 ; + assign corew$nmi_req_set_not_clear = 1'd0 ; assign corew$set_verbosity_logdelay = 64'h0 ; assign corew$set_verbosity_verbosity = 4'h0 ; + assign corew$start_fromhost_addr = 64'd0 ; + assign corew$start_tohost_addr = 64'd0 ; assign corew$EN_set_verbosity = 1'b0 ; - assign corew$EN_set_htif_addrs = 1'b0 ; - assign corew$EN_cpu_reset_server_request_put = CAN_FIRE_RL_rl_once ; - assign corew$EN_cpu_reset_server_response_get = - corew$RDY_cpu_reset_server_response_get ; - assign corew$EN_dm_dmi_read_addr = + assign corew$EN_start = + WILL_FIRE_RL_rl_ndm_reset_wait && rg_ndm_reset_delay == 8'd1 || + WILL_FIRE_RL_rl_step_0 ; + assign corew$EN_dmi_read_addr = WILL_FIRE_RL_rl_dmi_req_cpu && bus_dmi_req_fifof$D_OUT[1:0] == 2'd1 ; - assign corew$EN_dm_dmi_read_data = WILL_FIRE_RL_rl_dmi_rsp_cpu ; - assign corew$EN_dm_dmi_write = + assign corew$EN_dmi_read_data = WILL_FIRE_RL_rl_dmi_rsp_cpu ; + assign corew$EN_dmi_write = WILL_FIRE_RL_rl_dmi_req_cpu && bus_dmi_req_fifof$D_OUT[1:0] == 2'd2 ; - assign corew$EN_dm_ndm_reset_req_get_get = CAN_FIRE_RL_rl_ndmreset ; - assign corew$EN_tv_verifier_info_get_get = CAN_FIRE_RL_mkConnectionGetPut ; + assign corew$EN_ndm_reset_client_request_get = CAN_FIRE_RL_rl_ndm_reset ; + assign corew$EN_ndm_reset_client_response_put = MUX_corew$start_1__SEL_1 ; // submodule jtagtap assign jtagtap$dmi_req_ready = bus_dmi_req_fifof$FULL_N ; @@ -1659,26 +1587,24 @@ module mkP3_Core(CLK, assign jtagtap$jtag_tdi = jtag_tdi ; assign jtagtap$jtag_tms = jtag_tms ; - // submodule tv_xactor - assign tv_xactor$axi_out_tready = tv_verifier_info_tx_tready ; - assign tv_xactor$tv_in_put = corew$tv_verifier_info_get_get ; - assign tv_xactor$EN_tv_in_put = CAN_FIRE_RL_mkConnectionGetPut ; + // submodule ndm_reset_controller + assign ndm_reset_controller$ASSERT_IN = CAN_FIRE_RL_rl_ndm_reset ; // remaining internal signals - assign IF_bus_dmi_req_fifof_first__7_BITS_1_TO_0_8_EQ_ETC___d78 = + assign IF_bus_dmi_req_fifof_first__1_BITS_1_TO_0_2_EQ_ETC___d92 = (bus_dmi_req_fifof$D_OUT[1:0] == 2'd1) ? - corew$RDY_dm_dmi_read_addr : + corew$RDY_dmi_read_addr : (bus_dmi_req_fifof$D_OUT[1:0] == 2'd2 || bus_dmi_rsp_fifof_cntr_r != 2'd2) && (bus_dmi_req_fifof$D_OUT[1:0] != 2'd2 || - bus_dmi_rsp_fifof_cntr_r != 2'd2 && corew$RDY_dm_dmi_write) ; + bus_dmi_rsp_fifof_cntr_r != 2'd2 && corew$RDY_dmi_write) ; assign _dfoo1 = bus_dmi_rsp_fifof_cntr_r != 2'd2 || - bus_dmi_rsp_fifof_cntr_r_0_MINUS_1___d28 == 2'd1 ; + bus_dmi_rsp_fifof_cntr_r_4_MINUS_1___d42 == 2'd1 ; assign _dfoo3 = bus_dmi_rsp_fifof_cntr_r != 2'd1 || - bus_dmi_rsp_fifof_cntr_r_0_MINUS_1___d28 == 2'd0 ; - assign bus_dmi_rsp_fifof_cntr_r_0_MINUS_1___d28 = + bus_dmi_rsp_fifof_cntr_r_4_MINUS_1___d42 == 2'd0 ; + assign bus_dmi_rsp_fifof_cntr_r_4_MINUS_1___d42 = bus_dmi_rsp_fifof_cntr_r - 2'd1 ; // handling of inlined registers @@ -1690,7 +1616,8 @@ module mkP3_Core(CLK, bus_dmi_rsp_fifof_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0; bus_dmi_rsp_fifof_q_0 <= `BSV_ASSIGNMENT_DELAY 34'd0; bus_dmi_rsp_fifof_q_1 <= `BSV_ASSIGNMENT_DELAY 34'd0; - rg_once <= `BSV_ASSIGNMENT_DELAY 1'd0; + rg_corew_start_after_por <= `BSV_ASSIGNMENT_DELAY 1'd0; + rg_ndm_reset_delay <= `BSV_ASSIGNMENT_DELAY 8'd0; end else begin @@ -1703,7 +1630,11 @@ module mkP3_Core(CLK, if (bus_dmi_rsp_fifof_q_1$EN) bus_dmi_rsp_fifof_q_1 <= `BSV_ASSIGNMENT_DELAY bus_dmi_rsp_fifof_q_1$D_IN; - if (rg_once$EN) rg_once <= `BSV_ASSIGNMENT_DELAY rg_once$D_IN; + if (rg_corew_start_after_por$EN) + rg_corew_start_after_por <= `BSV_ASSIGNMENT_DELAY + rg_corew_start_after_por$D_IN; + if (rg_ndm_reset_delay$EN) + rg_ndm_reset_delay <= `BSV_ASSIGNMENT_DELAY rg_ndm_reset_delay$D_IN; end end @@ -1715,9 +1646,44 @@ module mkP3_Core(CLK, bus_dmi_rsp_fifof_cntr_r = 2'h2; bus_dmi_rsp_fifof_q_0 = 34'h2AAAAAAAA; bus_dmi_rsp_fifof_q_1 = 34'h2AAAAAAAA; - rg_once = 1'h0; + rg_corew_start_after_por = 1'h0; + rg_ndm_reset_delay = 8'hAA; end `endif // BSV_NO_INITIAL_BLOCKS // synopsys translate_on + + // handling of system tasks + + // synopsys translate_off + always@(negedge CLK) + begin + #0; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_ndm_reset) + begin + v__h1270 = $stime; + #0; + end + v__h1264 = v__h1270 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_ndm_reset) + $display("%0d: %m.rl_ndm_reset: asserting NDM reset (for non-DebugModule) for %0d cycles", + v__h1264, + $signed(32'd10)); + if (RST_N != `BSV_RESET_VALUE) + if (ndm_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_ndm_reset_wait && rg_ndm_reset_delay == 8'd1) + begin + v__h1415 = $stime; + #0; + end + v__h1409 = v__h1415 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (ndm_reset$RST_OUT != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_ndm_reset_wait && rg_ndm_reset_delay == 8'd1) + $display("%0d: %m.rl_ndm_reset_wait: sent NDM reset ack (for non-DebugModule) to Debug Module", + v__h1409); + end + // synopsys translate_on endmodule // mkP3_Core diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkPLIC_16_2_7.v b/src_SSITH_P3_sim/Verilog_RTL/mkPLIC_16_2_7.v index a4e336f..6ec76ff 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkPLIC_16_2_7.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkPLIC_16_2_7.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // @@ -41,7 +41,6 @@ // axi4_slave_awqos I 4 reg // axi4_slave_awregion I 4 reg // axi4_slave_wvalid I 1 -// axi4_slave_wid I 4 reg // axi4_slave_wdata I 64 reg // axi4_slave_wstrb I 8 reg // axi4_slave_wlast I 1 reg @@ -133,7 +132,6 @@ module mkPLIC_16_2_7(CLK, axi4_slave_awready, axi4_slave_wvalid, - axi4_slave_wid, axi4_slave_wdata, axi4_slave_wstrb, axi4_slave_wlast, @@ -253,7 +251,6 @@ module mkPLIC_16_2_7(CLK, // action method axi4_slave_m_wvalid input axi4_slave_wvalid; - input [3 : 0] axi4_slave_wid; input [63 : 0] axi4_slave_wdata; input [7 : 0] axi4_slave_wstrb; input axi4_slave_wlast; @@ -814,7 +811,7 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_f_wr_addr$FULL_N; // ports of submodule m_slave_xactor_f_wr_data - wire [76 : 0] m_slave_xactor_f_wr_data$D_IN, m_slave_xactor_f_wr_data$D_OUT; + wire [72 : 0] m_slave_xactor_f_wr_data$D_IN, m_slave_xactor_f_wr_data$D_OUT; wire m_slave_xactor_f_wr_data$CLR, m_slave_xactor_f_wr_data$DEQ, m_slave_xactor_f_wr_data$EMPTY_N, @@ -1015,22 +1012,22 @@ module mkPLIC_16_2_7(CLK, // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h75671; - reg [31 : 0] v__h75866; - reg [31 : 0] v__h76061; - reg [31 : 0] v__h76256; - reg [31 : 0] v__h76451; - reg [31 : 0] v__h76646; - reg [31 : 0] v__h76841; - reg [31 : 0] v__h77036; - reg [31 : 0] v__h77231; - reg [31 : 0] v__h77426; - reg [31 : 0] v__h77621; - reg [31 : 0] v__h77816; - reg [31 : 0] v__h78011; - reg [31 : 0] v__h78206; - reg [31 : 0] v__h78401; - reg [31 : 0] v__h78596; + reg [31 : 0] v__h75656; + reg [31 : 0] v__h75851; + reg [31 : 0] v__h76046; + reg [31 : 0] v__h76241; + reg [31 : 0] v__h76436; + reg [31 : 0] v__h76631; + reg [31 : 0] v__h76826; + reg [31 : 0] v__h77021; + reg [31 : 0] v__h77216; + reg [31 : 0] v__h77411; + reg [31 : 0] v__h77606; + reg [31 : 0] v__h77801; + reg [31 : 0] v__h77996; + reg [31 : 0] v__h78191; + reg [31 : 0] v__h78386; + reg [31 : 0] v__h78581; reg [31 : 0] v__h6142; reg [31 : 0] v__h13078; reg [31 : 0] v__h13263; @@ -1042,19 +1039,19 @@ module mkPLIC_16_2_7(CLK, reg [31 : 0] v__h24054; reg [31 : 0] v__h26248; reg [31 : 0] v__h26461; - reg [31 : 0] v__h26738; - reg [31 : 0] v__h26966; - reg [31 : 0] v__h27863; - reg [31 : 0] v__h28046; - reg [31 : 0] v__h67028; - reg [31 : 0] v__h67316; - reg [31 : 0] v__h67845; - reg [31 : 0] v__h67931; - reg [31 : 0] v__h68130; - reg [31 : 0] v__h68351; - reg [31 : 0] v__h74688; - reg [31 : 0] v__h74798; - reg [31 : 0] v__h74911; + reg [31 : 0] v__h26735; + reg [31 : 0] v__h26959; + reg [31 : 0] v__h27854; + reg [31 : 0] v__h28037; + reg [31 : 0] v__h67019; + reg [31 : 0] v__h67307; + reg [31 : 0] v__h67836; + reg [31 : 0] v__h67922; + reg [31 : 0] v__h68121; + reg [31 : 0] v__h68340; + reg [31 : 0] v__h74675; + reg [31 : 0] v__h74785; + reg [31 : 0] v__h74898; reg [31 : 0] v__h6136; reg [31 : 0] v__h13072; reg [31 : 0] v__h13257; @@ -1066,42 +1063,42 @@ module mkPLIC_16_2_7(CLK, reg [31 : 0] v__h25967; reg [31 : 0] v__h26242; reg [31 : 0] v__h26455; - reg [31 : 0] v__h26732; - reg [31 : 0] v__h26960; - reg [31 : 0] v__h27857; - reg [31 : 0] v__h28040; - reg [31 : 0] v__h67022; - reg [31 : 0] v__h67310; - reg [31 : 0] v__h67839; - reg [31 : 0] v__h67925; - reg [31 : 0] v__h68124; - reg [31 : 0] v__h68345; - reg [31 : 0] v__h74682; - reg [31 : 0] v__h74792; - reg [31 : 0] v__h74905; - reg [31 : 0] v__h75665; - reg [31 : 0] v__h75860; - reg [31 : 0] v__h76055; - reg [31 : 0] v__h76250; - reg [31 : 0] v__h76445; - reg [31 : 0] v__h76640; - reg [31 : 0] v__h76835; - reg [31 : 0] v__h77030; - reg [31 : 0] v__h77225; - reg [31 : 0] v__h77420; - reg [31 : 0] v__h77615; - reg [31 : 0] v__h77810; - reg [31 : 0] v__h78005; - reg [31 : 0] v__h78200; - reg [31 : 0] v__h78395; - reg [31 : 0] v__h78590; + reg [31 : 0] v__h26729; + reg [31 : 0] v__h26953; + reg [31 : 0] v__h27848; + reg [31 : 0] v__h28031; + reg [31 : 0] v__h67013; + reg [31 : 0] v__h67301; + reg [31 : 0] v__h67830; + reg [31 : 0] v__h67916; + reg [31 : 0] v__h68115; + reg [31 : 0] v__h68334; + reg [31 : 0] v__h74669; + reg [31 : 0] v__h74779; + reg [31 : 0] v__h74892; + reg [31 : 0] v__h75650; + reg [31 : 0] v__h75845; + reg [31 : 0] v__h76040; + reg [31 : 0] v__h76235; + reg [31 : 0] v__h76430; + reg [31 : 0] v__h76625; + reg [31 : 0] v__h76820; + reg [31 : 0] v__h77015; + reg [31 : 0] v__h77210; + reg [31 : 0] v__h77405; + reg [31 : 0] v__h77600; + reg [31 : 0] v__h77795; + reg [31 : 0] v__h77990; + reg [31 : 0] v__h78185; + reg [31 : 0] v__h78380; + reg [31 : 0] v__h78575; // synopsys translate_on // remaining internal signals reg [63 : 0] y_avValue_fst__h26146; - reg [4 : 0] x__h24009, x__h67485; + reg [4 : 0] x__h24009, x__h67476; reg [2 : 0] x__h13491, x__h23830; - reg [1 : 0] v__h67105, y_avValue_snd__h26147; + reg [1 : 0] v__h67096, y_avValue_snd__h26147; reg CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1, CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10, CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11, @@ -1150,7 +1147,7 @@ module mkPLIC_16_2_7(CLK, CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46, CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47, CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48, - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919, + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918, SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102, SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107, SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111, @@ -1248,7 +1245,7 @@ module mkPLIC_16_2_7(CLK, SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515, SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520; wire [63 : 0] addr_offset__h13214, - addr_offset__h26927, + addr_offset__h26920, rdata___1__h26402, rdata__h26200, v__h13420, @@ -1269,9 +1266,9 @@ module mkPLIC_16_2_7(CLK, y_avValue_fst__h26192; wire [31 : 0] v_ie__h18145, v_ip__h13672, - wdata32__h26928, + wdata32__h26921, x__h23671, - x__h67108; + x__h67099; wire [9 : 0] source_id__h15663, source_id__h15770, source_id__h15843, @@ -1334,121 +1331,121 @@ module mkPLIC_16_2_7(CLK, source_id__h23227, source_id__h23335, source_id__h23443, - source_id__h29473, - source_id__h30683, - source_id__h31893, - source_id__h33103, - source_id__h34313, - source_id__h35523, - source_id__h36733, - source_id__h37943, - source_id__h39153, - source_id__h40363, - source_id__h41573, - source_id__h42783, - source_id__h43993, - source_id__h45203, - source_id__h46413, - source_id__h47623, - source_id__h48833, - source_id__h50043, - source_id__h51253, - source_id__h52463, - source_id__h53673, - source_id__h54883, - source_id__h56093, - source_id__h57303, - source_id__h58513, - source_id__h59723, - source_id__h60933, - source_id__h62143, - source_id__h63353, - source_id__h64563, - source_id__h65773, - source_id__h67434, + source_id__h29464, + source_id__h30674, + source_id__h31884, + source_id__h33094, + source_id__h34304, + source_id__h35514, + source_id__h36724, + source_id__h37934, + source_id__h39144, + source_id__h40354, + source_id__h41564, + source_id__h42774, + source_id__h43984, + source_id__h45194, + source_id__h46404, + source_id__h47614, + source_id__h48824, + source_id__h50034, + source_id__h51244, + source_id__h52454, + source_id__h53664, + source_id__h54874, + source_id__h56084, + source_id__h57294, + source_id__h58504, + source_id__h59714, + source_id__h60924, + source_id__h62134, + source_id__h63344, + source_id__h64554, + source_id__h65764, + source_id__h67425, source_id_base__h13628, - source_id_base__h28146; - wire [4 : 0] IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3102, - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3196, + source_id_base__h28137; + wire [4 : 0] IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3101, + IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3195, IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d667, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3104, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3198, + IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3103, + IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3197, IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d669, - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3106, - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3200, + IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3105, + IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3199, IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d671, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3094, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3188, + IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3093, + IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3187, IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d659, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3096, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3190, + IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3095, + IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3189, IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d661, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3098, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3192, + IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3097, + IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3191, IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d663, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3100, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3194, + IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3099, + IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3193, IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d665, - b__h71311, - b__h73316, + b__h71298, + b__h73303, max_id__h23957; - wire [2 : 0] IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3061, - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3155, + wire [2 : 0] IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3060, + IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3154, IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d615, - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3066, - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3160, + IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3065, + IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3159, IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d622, - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3071, - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3165, + IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3070, + IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3164, IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d629, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3076, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3170, + IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3075, + IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3169, IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d636, - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3081, - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3175, + IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3080, + IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3174, IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d643, - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3086, - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3180, - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3016, - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3110, + IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3085, + IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3179, + IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3015, + IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3109, IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d552, - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3021, - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3115, + IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3020, + IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3114, IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d559, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3026, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3120, + IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3025, + IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3119, IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d566, - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3031, - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3125, + IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3030, + IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3124, IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d573, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3036, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3130, + IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3035, + IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3129, IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d580, - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3041, - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3135, + IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3040, + IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3134, IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d587, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3046, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3140, + IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3045, + IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3139, IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d594, - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3051, - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3145, + IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3050, + IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3144, IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d601, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3056, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3150, + IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3055, + IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3149, IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d608, - a__h71310, - a__h73315; + a__h71297, + a__h73302; wire [1 : 0] rresp__h26201, - v__h26932, - v__h27092, - v__h27105, - v__h27940, - v__h27959, - v__h28123, - v__h28142, - v__h67142, - v__h67430, - v__h67474, + v__h26925, + v__h27083, + v__h27096, + v__h27931, + v__h27950, + v__h28114, + v__h28133, + v__h67133, + v__h67421, + v__h67465, y_avValue_snd__h26093, y_avValue_snd__h26114, y_avValue_snd__h26126, @@ -1460,8 +1457,8 @@ module mkPLIC_16_2_7(CLK, y_avValue_snd__h26193; wire IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d769, IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771, - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2989, - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991, + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2988, + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990, NOT_m_cfg_verbosity_read_ULE_1_5___d16, NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d248, NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d538, @@ -1469,62 +1466,62 @@ module mkPLIC_16_2_7(CLK, NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d74, NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d744, NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2870, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2883, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2894, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2966, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2976, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d852, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d906, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d918, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982, - NOT_m_vrg_source_busy_0_901_238_AND_NOT_m_cfg__ETC___d3242, - NOT_m_vrg_source_busy_10_911_316_AND_NOT_m_cfg_ETC___d3320, - NOT_m_vrg_source_busy_11_912_324_AND_NOT_m_cfg_ETC___d3328, - NOT_m_vrg_source_busy_12_913_332_AND_NOT_m_cfg_ETC___d3336, - NOT_m_vrg_source_busy_13_914_340_AND_NOT_m_cfg_ETC___d3344, - NOT_m_vrg_source_busy_14_915_348_AND_NOT_m_cfg_ETC___d3352, - NOT_m_vrg_source_busy_15_916_356_AND_NOT_m_cfg_ETC___d3360, - NOT_m_vrg_source_busy_1_902_245_AND_NOT_m_cfg__ETC___d3249, - NOT_m_vrg_source_busy_2_903_252_AND_NOT_m_cfg__ETC___d3256, - NOT_m_vrg_source_busy_3_904_260_AND_NOT_m_cfg__ETC___d3264, - NOT_m_vrg_source_busy_4_905_268_AND_NOT_m_cfg__ETC___d3272, - NOT_m_vrg_source_busy_5_906_276_AND_NOT_m_cfg__ETC___d3280, - NOT_m_vrg_source_busy_6_907_284_AND_NOT_m_cfg__ETC___d3288, - NOT_m_vrg_source_busy_7_908_292_AND_NOT_m_cfg__ETC___d3296, - NOT_m_vrg_source_busy_8_909_300_AND_NOT_m_cfg__ETC___d3304, - NOT_m_vrg_source_busy_9_910_308_AND_NOT_m_cfg__ETC___d3312, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2869, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2882, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2893, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2965, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2975, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d851, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d905, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d917, + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981, + NOT_m_vrg_source_busy_0_900_236_AND_NOT_m_cfg__ETC___d3240, + NOT_m_vrg_source_busy_10_910_314_AND_NOT_m_cfg_ETC___d3318, + NOT_m_vrg_source_busy_11_911_322_AND_NOT_m_cfg_ETC___d3326, + NOT_m_vrg_source_busy_12_912_330_AND_NOT_m_cfg_ETC___d3334, + NOT_m_vrg_source_busy_13_913_338_AND_NOT_m_cfg_ETC___d3342, + NOT_m_vrg_source_busy_14_914_346_AND_NOT_m_cfg_ETC___d3350, + NOT_m_vrg_source_busy_15_915_354_AND_NOT_m_cfg_ETC___d3358, + NOT_m_vrg_source_busy_1_901_243_AND_NOT_m_cfg__ETC___d3247, + NOT_m_vrg_source_busy_2_902_250_AND_NOT_m_cfg__ETC___d3254, + NOT_m_vrg_source_busy_3_903_258_AND_NOT_m_cfg__ETC___d3262, + NOT_m_vrg_source_busy_4_904_266_AND_NOT_m_cfg__ETC___d3270, + NOT_m_vrg_source_busy_5_905_274_AND_NOT_m_cfg__ETC___d3278, + NOT_m_vrg_source_busy_6_906_282_AND_NOT_m_cfg__ETC___d3286, + NOT_m_vrg_source_busy_7_907_290_AND_NOT_m_cfg__ETC___d3294, + NOT_m_vrg_source_busy_8_908_298_AND_NOT_m_cfg__ETC___d3302, + NOT_m_vrg_source_busy_9_909_306_AND_NOT_m_cfg__ETC___d3310, _dfoo1, _dfoo10, _dfoo100, @@ -3098,83 +3095,83 @@ module mkPLIC_16_2_7(CLK, m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532, m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68, m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2886, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2888, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d863, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d865, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d867, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d869, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d871, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d873, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d875, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d877, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d879, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d881, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d883, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d885, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d887, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d889, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d891, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d893, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d895, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2885, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2887, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d862, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d864, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d866, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d868, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d870, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d872, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d874, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d876, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d878, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d880, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d882, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d884, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d886, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d888, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d890, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d892, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d894, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913, m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957, - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3060, - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3154, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920, + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956, + m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3059, + m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3153, m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614, - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3065, - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3159, + m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3064, + m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3158, m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d621, - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3070, - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3164, + m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3069, + m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3163, m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628, - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3075, - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3169, + m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3074, + m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3168, m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d635, m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d691, - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3080, - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3174, + m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3079, + m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3173, m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642, - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3085, - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3179, + m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3084, + m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3178, m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d649, - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3090, - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3184, + m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3089, + m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3183, m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d656, m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d694, m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551, - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3020, - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3114, + m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3019, + m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3113, m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558, - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3025, - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3119, + m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3024, + m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3118, m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d565, - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3030, - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3124, + m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3029, + m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3123, m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572, - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3035, - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3129, + m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3034, + m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3128, m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d579, - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3040, - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3134, + m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3039, + m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3133, m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586, - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3045, - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3139, + m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3044, + m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3138, m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d593, m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d685, - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3050, - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3144, + m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3049, + m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3143, m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600, - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3055, - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3149, + m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3054, + m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3148, m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607, m_vrg_source_prio_16_3_ULE_IF_m_vrg_source_ip__ETC___d651; @@ -3321,10 +3318,10 @@ module mkPLIC_16_2_7(CLK, assign WILL_FIRE_v_sources_15_m_interrupt_req = 1'd1 ; // value method v_targets_0_m_eip - assign v_targets_0_m_eip = a__h71310 > m_vrg_target_threshold_0 ; + assign v_targets_0_m_eip = a__h71297 > m_vrg_target_threshold_0 ; // value method v_targets_1_m_eip - assign v_targets_1_m_eip = a__h73315 > m_vrg_target_threshold_1 ; + assign v_targets_1_m_eip = a__h73302 > m_vrg_target_threshold_1 ; // submodule m_f_reset_reqs FIFO20 #(.guarded(32'd1)) m_f_reset_reqs(.RST(RST_N), @@ -3381,7 +3378,7 @@ module mkPLIC_16_2_7(CLK, .EMPTY_N(m_slave_xactor_f_wr_addr$EMPTY_N)); // submodule m_slave_xactor_f_wr_data - FIFO2 #(.width(32'd77), + FIFO2 #(.width(32'd73), .guarded(32'd1)) m_slave_xactor_f_wr_data(.RST(RST_N), .CLK(CLK), .D_IN(m_slave_xactor_f_wr_data$D_IN), @@ -3442,181 +3439,181 @@ module mkPLIC_16_2_7(CLK, !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; assign MUX_m_vrg_source_busy_0$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67434 == 10'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; assign MUX_m_vrg_source_busy_1$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd1 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; assign MUX_m_vrg_source_busy_1$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67434 == 10'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; assign MUX_m_vrg_source_busy_10$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd10 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; assign MUX_m_vrg_source_busy_10$write_1__SEL_2 = WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67434 == 10'd10 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; + source_id__h67425 == 10'd10 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; assign MUX_m_vrg_source_busy_11$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd11 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; assign MUX_m_vrg_source_busy_11$write_1__SEL_2 = WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67434 == 10'd11 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; + source_id__h67425 == 10'd11 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; assign MUX_m_vrg_source_busy_12$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd12 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; assign MUX_m_vrg_source_busy_12$write_1__SEL_2 = WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67434 == 10'd12 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; + source_id__h67425 == 10'd12 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; assign MUX_m_vrg_source_busy_13$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd13 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; assign MUX_m_vrg_source_busy_13$write_1__SEL_2 = WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67434 == 10'd13 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; + source_id__h67425 == 10'd13 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; assign MUX_m_vrg_source_busy_14$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd14 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; assign MUX_m_vrg_source_busy_14$write_1__SEL_2 = WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67434 == 10'd14 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; + source_id__h67425 == 10'd14 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; assign MUX_m_vrg_source_busy_15$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd15 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; assign MUX_m_vrg_source_busy_15$write_1__SEL_2 = WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67434 == 10'd15 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; + source_id__h67425 == 10'd15 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; assign MUX_m_vrg_source_busy_16$write_1__SEL_2 = WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67434 == 10'd16 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; + source_id__h67425 == 10'd16 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; assign MUX_m_vrg_source_busy_2$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd2 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; assign MUX_m_vrg_source_busy_2$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67434 == 10'd2 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd2 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; assign MUX_m_vrg_source_busy_3$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd3 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; assign MUX_m_vrg_source_busy_3$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67434 == 10'd3 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd3 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; assign MUX_m_vrg_source_busy_4$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd4 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; assign MUX_m_vrg_source_busy_4$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67434 == 10'd4 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd4 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; assign MUX_m_vrg_source_busy_5$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd5 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; assign MUX_m_vrg_source_busy_5$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67434 == 10'd5 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd5 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; assign MUX_m_vrg_source_busy_6$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd6 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; assign MUX_m_vrg_source_busy_6$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67434 == 10'd6 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd6 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; assign MUX_m_vrg_source_busy_7$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd7 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; assign MUX_m_vrg_source_busy_7$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67434 == 10'd7 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd7 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; assign MUX_m_vrg_source_busy_8$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd8 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; assign MUX_m_vrg_source_busy_8$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67434 == 10'd8 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd8 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; assign MUX_m_vrg_source_busy_9$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd9 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; assign MUX_m_vrg_source_busy_9$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67434 == 10'd9 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd9 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; assign MUX_m_vrg_source_prio_0$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - addr_offset__h26927[11:2] == 10'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d852 ; + addr_offset__h26920[11:2] == 10'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d851 ; assign MUX_m_vrg_source_prio_1$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d863 ; + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d862 ; assign MUX_m_vrg_source_prio_10$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d881 ; + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d880 ; assign MUX_m_vrg_source_prio_11$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d883 ; + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d882 ; assign MUX_m_vrg_source_prio_12$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d885 ; + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d884 ; assign MUX_m_vrg_source_prio_13$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d887 ; + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d886 ; assign MUX_m_vrg_source_prio_14$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d889 ; + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d888 ; assign MUX_m_vrg_source_prio_15$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d891 ; + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d890 ; assign MUX_m_vrg_source_prio_16$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d893 ; + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d892 ; assign MUX_m_vrg_source_prio_2$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d865 ; + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d864 ; assign MUX_m_vrg_source_prio_3$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d867 ; + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d866 ; assign MUX_m_vrg_source_prio_4$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d869 ; + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d868 ; assign MUX_m_vrg_source_prio_5$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d871 ; + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d870 ; assign MUX_m_vrg_source_prio_6$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d873 ; + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d872 ; assign MUX_m_vrg_source_prio_7$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d875 ; + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d874 ; assign MUX_m_vrg_source_prio_8$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d877 ; + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d876 ; assign MUX_m_vrg_source_prio_9$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d879 ; + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d878 ; assign MUX_m_vrg_target_threshold_0$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2886 ; + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2885 ; assign MUX_m_vrg_target_threshold_1$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2888 ; + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2887 ; assign MUX_m_vvrg_ie_0_0$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2107 ; assign MUX_m_vvrg_ie_0_1$write_1__SEL_1 = @@ -3686,174 +3683,174 @@ module mkPLIC_16_2_7(CLK, assign MUX_m_vvrg_ie_1_9$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2055 ; assign MUX_m_vvrg_ie_0_0$write_1__VAL_1 = - (source_id_base__h28146 == 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd0 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? + wdata32__h26921[0] : _dfoo2040 ; assign MUX_m_vvrg_ie_0_1$write_1__VAL_1 = - (source_id_base__h28146 == 10'd1 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd1 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? + wdata32__h26921[0] : _dfoo2038 ; assign MUX_m_vvrg_ie_0_10$write_1__VAL_1 = - (source_id_base__h28146 == 10'd10 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd10 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? + wdata32__h26921[0] : _dfoo2020 ; assign MUX_m_vvrg_ie_0_11$write_1__VAL_1 = - (source_id_base__h28146 == 10'd11 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd11 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? + wdata32__h26921[0] : _dfoo2018 ; assign MUX_m_vvrg_ie_0_12$write_1__VAL_1 = - (source_id_base__h28146 == 10'd12 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd12 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? + wdata32__h26921[0] : _dfoo2016 ; assign MUX_m_vvrg_ie_0_13$write_1__VAL_1 = - (source_id_base__h28146 == 10'd13 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd13 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? + wdata32__h26921[0] : _dfoo2014 ; assign MUX_m_vvrg_ie_0_14$write_1__VAL_1 = - (source_id_base__h28146 == 10'd14 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd14 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? + wdata32__h26921[0] : _dfoo2012 ; assign MUX_m_vvrg_ie_0_15$write_1__VAL_1 = - (source_id_base__h28146 == 10'd15 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd15 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? + wdata32__h26921[0] : _dfoo2010 ; assign MUX_m_vvrg_ie_0_16$write_1__VAL_1 = - (source_id_base__h28146 == 10'd16 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd16 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? + wdata32__h26921[0] : _dfoo2008 ; assign MUX_m_vvrg_ie_0_2$write_1__VAL_1 = - (source_id_base__h28146 == 10'd2 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd2 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? + wdata32__h26921[0] : _dfoo2036 ; assign MUX_m_vvrg_ie_0_3$write_1__VAL_1 = - (source_id_base__h28146 == 10'd3 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd3 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? + wdata32__h26921[0] : _dfoo2034 ; assign MUX_m_vvrg_ie_0_4$write_1__VAL_1 = - (source_id_base__h28146 == 10'd4 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd4 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? + wdata32__h26921[0] : _dfoo2032 ; assign MUX_m_vvrg_ie_0_5$write_1__VAL_1 = - (source_id_base__h28146 == 10'd5 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd5 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? + wdata32__h26921[0] : _dfoo2030 ; assign MUX_m_vvrg_ie_0_6$write_1__VAL_1 = - (source_id_base__h28146 == 10'd6 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd6 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? + wdata32__h26921[0] : _dfoo2028 ; assign MUX_m_vvrg_ie_0_7$write_1__VAL_1 = - (source_id_base__h28146 == 10'd7 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd7 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? + wdata32__h26921[0] : _dfoo2026 ; assign MUX_m_vvrg_ie_0_8$write_1__VAL_1 = - (source_id_base__h28146 == 10'd8 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd8 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? + wdata32__h26921[0] : _dfoo2024 ; assign MUX_m_vvrg_ie_0_9$write_1__VAL_1 = - (source_id_base__h28146 == 10'd9 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd9 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? + wdata32__h26921[0] : _dfoo2022 ; assign MUX_m_vvrg_ie_1_0$write_1__VAL_1 = - (source_id_base__h28146 == 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd0 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? + wdata32__h26921[0] : _dfoo2006 ; assign MUX_m_vvrg_ie_1_1$write_1__VAL_1 = - (source_id_base__h28146 == 10'd1 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd1 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? + wdata32__h26921[0] : _dfoo2004 ; assign MUX_m_vvrg_ie_1_10$write_1__VAL_1 = - (source_id_base__h28146 == 10'd10 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd10 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? + wdata32__h26921[0] : _dfoo1986 ; assign MUX_m_vvrg_ie_1_11$write_1__VAL_1 = - (source_id_base__h28146 == 10'd11 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd11 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? + wdata32__h26921[0] : _dfoo1984 ; assign MUX_m_vvrg_ie_1_12$write_1__VAL_1 = - (source_id_base__h28146 == 10'd12 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd12 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? + wdata32__h26921[0] : _dfoo1982 ; assign MUX_m_vvrg_ie_1_13$write_1__VAL_1 = - (source_id_base__h28146 == 10'd13 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd13 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? + wdata32__h26921[0] : _dfoo1980 ; assign MUX_m_vvrg_ie_1_14$write_1__VAL_1 = - (source_id_base__h28146 == 10'd14 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd14 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? + wdata32__h26921[0] : _dfoo1978 ; assign MUX_m_vvrg_ie_1_15$write_1__VAL_1 = - (source_id_base__h28146 == 10'd15 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd15 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? + wdata32__h26921[0] : _dfoo1976 ; assign MUX_m_vvrg_ie_1_16$write_1__VAL_1 = - (source_id_base__h28146 == 10'd16 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd16 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? + wdata32__h26921[0] : _dfoo1974 ; assign MUX_m_vvrg_ie_1_2$write_1__VAL_1 = - (source_id_base__h28146 == 10'd2 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd2 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? + wdata32__h26921[0] : _dfoo2002 ; assign MUX_m_vvrg_ie_1_3$write_1__VAL_1 = - (source_id_base__h28146 == 10'd3 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd3 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? + wdata32__h26921[0] : _dfoo2000 ; assign MUX_m_vvrg_ie_1_4$write_1__VAL_1 = - (source_id_base__h28146 == 10'd4 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd4 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? + wdata32__h26921[0] : _dfoo1998 ; assign MUX_m_vvrg_ie_1_5$write_1__VAL_1 = - (source_id_base__h28146 == 10'd5 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd5 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? + wdata32__h26921[0] : _dfoo1996 ; assign MUX_m_vvrg_ie_1_6$write_1__VAL_1 = - (source_id_base__h28146 == 10'd6 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd6 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? + wdata32__h26921[0] : _dfoo1994 ; assign MUX_m_vvrg_ie_1_7$write_1__VAL_1 = - (source_id_base__h28146 == 10'd7 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd7 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? + wdata32__h26921[0] : _dfoo1992 ; assign MUX_m_vvrg_ie_1_8$write_1__VAL_1 = - (source_id_base__h28146 == 10'd8 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd8 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? + wdata32__h26921[0] : _dfoo1990 ; assign MUX_m_vvrg_ie_1_9$write_1__VAL_1 = - (source_id_base__h28146 == 10'd9 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26928[0] : + (source_id_base__h28137 == 10'd9 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? + wdata32__h26921[0] : _dfoo1988 ; // register m_cfg_verbosity @@ -3879,8 +3876,8 @@ module mkPLIC_16_2_7(CLK, !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || WILL_FIRE_RL_m_rl_process_wr_req && - addr_offset__h26927[16:12] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + addr_offset__h26920[16:12] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_servicing_source_1 @@ -3894,8 +3891,8 @@ module mkPLIC_16_2_7(CLK, !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || WILL_FIRE_RL_m_rl_process_wr_req && - addr_offset__h26927[16:12] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + addr_offset__h26920[16:12] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_0 @@ -3906,8 +3903,8 @@ module mkPLIC_16_2_7(CLK, WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd0 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67434 == 10'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_1 @@ -3918,8 +3915,8 @@ module mkPLIC_16_2_7(CLK, WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd1 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67434 == 10'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_10 @@ -3931,8 +3928,8 @@ module mkPLIC_16_2_7(CLK, !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67434 == 10'd10 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + source_id__h67425 == 10'd10 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_11 @@ -3944,8 +3941,8 @@ module mkPLIC_16_2_7(CLK, !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67434 == 10'd11 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + source_id__h67425 == 10'd11 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_12 @@ -3957,8 +3954,8 @@ module mkPLIC_16_2_7(CLK, !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67434 == 10'd12 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + source_id__h67425 == 10'd12 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_13 @@ -3970,8 +3967,8 @@ module mkPLIC_16_2_7(CLK, !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67434 == 10'd13 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + source_id__h67425 == 10'd13 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_14 @@ -3983,8 +3980,8 @@ module mkPLIC_16_2_7(CLK, !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67434 == 10'd14 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + source_id__h67425 == 10'd14 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_15 @@ -3996,8 +3993,8 @@ module mkPLIC_16_2_7(CLK, !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67434 == 10'd15 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + source_id__h67425 == 10'd15 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_16 @@ -4009,8 +4006,8 @@ module mkPLIC_16_2_7(CLK, !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67434 == 10'd16 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + source_id__h67425 == 10'd16 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_2 @@ -4021,8 +4018,8 @@ module mkPLIC_16_2_7(CLK, WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd2 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67434 == 10'd2 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd2 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_3 @@ -4033,8 +4030,8 @@ module mkPLIC_16_2_7(CLK, WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd3 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67434 == 10'd3 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd3 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_4 @@ -4045,8 +4042,8 @@ module mkPLIC_16_2_7(CLK, WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd4 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67434 == 10'd4 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd4 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_5 @@ -4057,8 +4054,8 @@ module mkPLIC_16_2_7(CLK, WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd5 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67434 == 10'd5 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd5 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_6 @@ -4069,8 +4066,8 @@ module mkPLIC_16_2_7(CLK, WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd6 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67434 == 10'd6 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd6 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_7 @@ -4081,8 +4078,8 @@ module mkPLIC_16_2_7(CLK, WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd7 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67434 == 10'd7 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd7 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_8 @@ -4093,8 +4090,8 @@ module mkPLIC_16_2_7(CLK, WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd8 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67434 == 10'd8 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd8 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_9 @@ -4105,8 +4102,8 @@ module mkPLIC_16_2_7(CLK, WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd9 && !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67434 == 10'd9 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd9 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_ip_0 @@ -4312,192 +4309,192 @@ module mkPLIC_16_2_7(CLK, // register m_vrg_source_prio_0 assign m_vrg_source_prio_0$D_IN = MUX_m_vrg_source_prio_0$write_1__SEL_1 ? - wdata32__h26928[2:0] : + wdata32__h26921[2:0] : 3'd0 ; assign m_vrg_source_prio_0$EN = WILL_FIRE_RL_m_rl_process_wr_req && - addr_offset__h26927[11:2] == 10'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d852 || + addr_offset__h26920[11:2] == 10'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d851 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_1 assign m_vrg_source_prio_1$D_IN = MUX_m_vrg_source_prio_1$write_1__SEL_1 ? - wdata32__h26928[2:0] : + wdata32__h26921[2:0] : 3'd0 ; assign m_vrg_source_prio_1$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d863 || + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d862 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_10 assign m_vrg_source_prio_10$D_IN = MUX_m_vrg_source_prio_10$write_1__SEL_1 ? - wdata32__h26928[2:0] : + wdata32__h26921[2:0] : 3'd0 ; assign m_vrg_source_prio_10$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d881 || + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d880 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_11 assign m_vrg_source_prio_11$D_IN = MUX_m_vrg_source_prio_11$write_1__SEL_1 ? - wdata32__h26928[2:0] : + wdata32__h26921[2:0] : 3'd0 ; assign m_vrg_source_prio_11$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d883 || + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d882 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_12 assign m_vrg_source_prio_12$D_IN = MUX_m_vrg_source_prio_12$write_1__SEL_1 ? - wdata32__h26928[2:0] : + wdata32__h26921[2:0] : 3'd0 ; assign m_vrg_source_prio_12$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d885 || + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d884 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_13 assign m_vrg_source_prio_13$D_IN = MUX_m_vrg_source_prio_13$write_1__SEL_1 ? - wdata32__h26928[2:0] : + wdata32__h26921[2:0] : 3'd0 ; assign m_vrg_source_prio_13$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d887 || + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d886 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_14 assign m_vrg_source_prio_14$D_IN = MUX_m_vrg_source_prio_14$write_1__SEL_1 ? - wdata32__h26928[2:0] : + wdata32__h26921[2:0] : 3'd0 ; assign m_vrg_source_prio_14$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d889 || + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d888 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_15 assign m_vrg_source_prio_15$D_IN = MUX_m_vrg_source_prio_15$write_1__SEL_1 ? - wdata32__h26928[2:0] : + wdata32__h26921[2:0] : 3'd0 ; assign m_vrg_source_prio_15$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d891 || + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d890 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_16 assign m_vrg_source_prio_16$D_IN = MUX_m_vrg_source_prio_16$write_1__SEL_1 ? - wdata32__h26928[2:0] : + wdata32__h26921[2:0] : 3'd0 ; assign m_vrg_source_prio_16$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d893 || + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d892 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_2 assign m_vrg_source_prio_2$D_IN = MUX_m_vrg_source_prio_2$write_1__SEL_1 ? - wdata32__h26928[2:0] : + wdata32__h26921[2:0] : 3'd0 ; assign m_vrg_source_prio_2$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d865 || + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d864 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_3 assign m_vrg_source_prio_3$D_IN = MUX_m_vrg_source_prio_3$write_1__SEL_1 ? - wdata32__h26928[2:0] : + wdata32__h26921[2:0] : 3'd0 ; assign m_vrg_source_prio_3$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d867 || + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d866 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_4 assign m_vrg_source_prio_4$D_IN = MUX_m_vrg_source_prio_4$write_1__SEL_1 ? - wdata32__h26928[2:0] : + wdata32__h26921[2:0] : 3'd0 ; assign m_vrg_source_prio_4$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d869 || + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d868 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_5 assign m_vrg_source_prio_5$D_IN = MUX_m_vrg_source_prio_5$write_1__SEL_1 ? - wdata32__h26928[2:0] : + wdata32__h26921[2:0] : 3'd0 ; assign m_vrg_source_prio_5$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d871 || + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d870 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_6 assign m_vrg_source_prio_6$D_IN = MUX_m_vrg_source_prio_6$write_1__SEL_1 ? - wdata32__h26928[2:0] : + wdata32__h26921[2:0] : 3'd0 ; assign m_vrg_source_prio_6$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d873 || + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d872 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_7 assign m_vrg_source_prio_7$D_IN = MUX_m_vrg_source_prio_7$write_1__SEL_1 ? - wdata32__h26928[2:0] : + wdata32__h26921[2:0] : 3'd0 ; assign m_vrg_source_prio_7$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d875 || + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d874 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_8 assign m_vrg_source_prio_8$D_IN = MUX_m_vrg_source_prio_8$write_1__SEL_1 ? - wdata32__h26928[2:0] : + wdata32__h26921[2:0] : 3'd0 ; assign m_vrg_source_prio_8$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d877 || + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d876 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_9 assign m_vrg_source_prio_9$D_IN = MUX_m_vrg_source_prio_9$write_1__SEL_1 ? - wdata32__h26928[2:0] : + wdata32__h26921[2:0] : 3'd0 ; assign m_vrg_source_prio_9$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d879 || + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d878 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_target_threshold_0 assign m_vrg_target_threshold_0$D_IN = MUX_m_vrg_target_threshold_0$write_1__SEL_1 ? - wdata32__h26928[2:0] : + wdata32__h26921[2:0] : 3'd7 ; assign m_vrg_target_threshold_0$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2886 || + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2885 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_target_threshold_1 assign m_vrg_target_threshold_1$D_IN = MUX_m_vrg_target_threshold_1$write_1__SEL_1 ? - wdata32__h26928[2:0] : + wdata32__h26921[2:0] : 3'd7 ; assign m_vrg_target_threshold_1$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2888 || + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2887 || WILL_FIRE_RL_m_rl_reset ; // register m_vvrg_ie_0_0 @@ -4829,10 +4826,7 @@ module mkPLIC_16_2_7(CLK, // submodule m_slave_xactor_f_wr_data assign m_slave_xactor_f_wr_data$D_IN = - { axi4_slave_wid, - axi4_slave_wdata, - axi4_slave_wstrb, - axi4_slave_wlast } ; + { axi4_slave_wdata, axi4_slave_wstrb, axi4_slave_wlast } ; assign m_slave_xactor_f_wr_data$ENQ = axi4_slave_wvalid && m_slave_xactor_f_wr_data$FULL_N ; assign m_slave_xactor_f_wr_data$DEQ = WILL_FIRE_RL_m_rl_process_wr_req ; @@ -4840,7 +4834,7 @@ module mkPLIC_16_2_7(CLK, // submodule m_slave_xactor_f_wr_resp assign m_slave_xactor_f_wr_resp$D_IN = - { m_slave_xactor_f_wr_addr$D_OUT[96:93], v__h26932 } ; + { m_slave_xactor_f_wr_addr$D_OUT[96:93], v__h26925 } ; assign m_slave_xactor_f_wr_resp$ENQ = WILL_FIRE_RL_m_rl_process_wr_req ; assign m_slave_xactor_f_wr_resp$DEQ = axi4_slave_bready && m_slave_xactor_f_wr_resp$EMPTY_N ; @@ -4863,54 +4857,54 @@ module mkPLIC_16_2_7(CLK, (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 ? !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 : IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d769) ; - assign IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2989 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 ? - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 || - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 : - ((x__h67108 == 32'h00200000) ? - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 : - x__h67108 != 32'h00200004 || - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 || - !SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919) ; - assign IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 ? - addr_offset__h26927[11:2] == 10'd0 || - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 : - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 ? - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 : - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2989) ; - assign IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3061 = - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3060 ? + assign IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2988 = + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 ? + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 || + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 : + ((x__h67099 == 32'h00200000) ? + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879 : + x__h67099 != 32'h00200004 || + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879 || + !SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918) ; + assign IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990 = + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 ? + addr_offset__h26920[11:2] == 10'd0 || + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 : + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 ? + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 : + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2988) ; + assign IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3060 = + m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3059 ? m_vrg_source_prio_10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3056 ; - assign IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3155 = - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3154 ? + IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3055 ; + assign IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3154 = + m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3153 ? m_vrg_source_prio_10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3150 ; + IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3149 ; assign IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d615 = m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614 ? m_vrg_source_prio_10 : IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d608 ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3066 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3065 ? + assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3065 = + m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3064 ? m_vrg_source_prio_11 : - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3061 ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3102 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3065 ? + IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3060 ; + assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3101 = + m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3064 ? 5'd11 : - (m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3060 ? + (m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3059 ? 5'd10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3100) ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3160 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3159 ? + IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3099) ; + assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3159 = + m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3158 ? m_vrg_source_prio_11 : - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3155 ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3196 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3159 ? + IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3154 ; + assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3195 = + m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3158 ? 5'd11 : - (m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3154 ? + (m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3153 ? 5'd10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3194) ; + IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3193) ; assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d622 = m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d621 ? m_vrg_source_prio_11 : @@ -4921,38 +4915,38 @@ module mkPLIC_16_2_7(CLK, (m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614 ? 5'd10 : IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d665) ; - assign IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3071 = - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3070 ? + assign IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3070 = + m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3069 ? m_vrg_source_prio_12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3066 ; - assign IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3165 = - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3164 ? + IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3065 ; + assign IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3164 = + m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3163 ? m_vrg_source_prio_12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3160 ; + IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3159 ; assign IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d629 = m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628 ? m_vrg_source_prio_12 : IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d622 ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3076 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3075 ? + assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3075 = + m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3074 ? m_vrg_source_prio_13 : - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3071 ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3104 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3075 ? + IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3070 ; + assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3103 = + m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3074 ? 5'd13 : - (m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3070 ? + (m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3069 ? 5'd12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3102) ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3170 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3169 ? + IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3101) ; + assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3169 = + m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3168 ? m_vrg_source_prio_13 : - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3165 ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3198 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3169 ? + IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3164 ; + assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3197 = + m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3168 ? 5'd13 : - (m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3164 ? + (m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3163 ? 5'd12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3196) ; + IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3195) ; assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d636 = m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d635 ? m_vrg_source_prio_13 : @@ -4963,50 +4957,50 @@ module mkPLIC_16_2_7(CLK, (m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628 ? 5'd12 : IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d667) ; - assign IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3081 = - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3080 ? + assign IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3080 = + m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3079 ? m_vrg_source_prio_14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3076 ; - assign IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3175 = - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3174 ? + IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3075 ; + assign IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3174 = + m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3173 ? m_vrg_source_prio_14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3170 ; + IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3169 ; assign IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d643 = m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642 ? m_vrg_source_prio_14 : IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d636 ; - assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3086 = - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3085 ? + assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3085 = + m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3084 ? m_vrg_source_prio_15 : - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3081 ; - assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3106 = - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3085 ? + IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3080 ; + assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3105 = + m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3084 ? 5'd15 : - (m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3080 ? + (m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3079 ? 5'd14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3104) ; - assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3180 = - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3179 ? + IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3103) ; + assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3179 = + m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3178 ? m_vrg_source_prio_15 : - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3175 ; - assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3200 = - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3179 ? + IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3174 ; + assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3199 = + m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3178 ? 5'd15 : - (m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3174 ? + (m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3173 ? 5'd14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3198) ; + IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3197) ; assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d671 = m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d649 ? 5'd15 : (m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642 ? 5'd14 : IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d669) ; - assign IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3016 = + assign IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3015 = (m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && m_vvrg_ie_0_1) ? m_vrg_source_prio_1 : 3'd0 ; - assign IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3110 = + assign IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3109 = (m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && m_vvrg_ie_1_1) ? m_vrg_source_prio_1 : @@ -5015,39 +5009,39 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551 ? m_vrg_source_prio_1 : 3'd0 ; - assign IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3021 = - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3020 ? + assign IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3020 = + m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3019 ? m_vrg_source_prio_2 : - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3016 ; - assign IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3115 = - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3114 ? + IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3015 ; + assign IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3114 = + m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3113 ? m_vrg_source_prio_2 : - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3110 ; + IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3109 ; assign IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d559 = m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558 ? m_vrg_source_prio_2 : IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d552 ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3026 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3025 ? + assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3025 = + m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3024 ? m_vrg_source_prio_3 : - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3021 ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3094 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3025 ? + IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3020 ; + assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3093 = + m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3024 ? 5'd3 : - (m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3020 ? + (m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3019 ? 5'd2 : ((m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && m_vvrg_ie_0_1) ? 5'd1 : 5'd0)) ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3120 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3119 ? + assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3119 = + m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3118 ? m_vrg_source_prio_3 : - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3115 ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3188 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3119 ? + IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3114 ; + assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3187 = + m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3118 ? 5'd3 : - (m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3114 ? + (m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3113 ? 5'd2 : ((m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && m_vvrg_ie_1_1) ? @@ -5065,38 +5059,38 @@ module mkPLIC_16_2_7(CLK, (m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551 ? 5'd1 : 5'd0)) ; - assign IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3031 = - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3030 ? + assign IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3030 = + m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3029 ? m_vrg_source_prio_4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3026 ; - assign IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3125 = - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3124 ? + IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3025 ; + assign IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3124 = + m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3123 ? m_vrg_source_prio_4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3120 ; + IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3119 ; assign IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d573 = m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572 ? m_vrg_source_prio_4 : IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d566 ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3036 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3035 ? + assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3035 = + m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3034 ? m_vrg_source_prio_5 : - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3031 ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3096 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3035 ? + IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3030 ; + assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3095 = + m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3034 ? 5'd5 : - (m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3030 ? + (m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3029 ? 5'd4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3094) ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3130 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3129 ? + IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3093) ; + assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3129 = + m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3128 ? m_vrg_source_prio_5 : - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3125 ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3190 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3129 ? + IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3124 ; + assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3189 = + m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3128 ? 5'd5 : - (m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3124 ? + (m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3123 ? 5'd4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3188) ; + IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3187) ; assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d580 = m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d579 ? m_vrg_source_prio_5 : @@ -5107,38 +5101,38 @@ module mkPLIC_16_2_7(CLK, (m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572 ? 5'd4 : IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d659) ; - assign IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3041 = - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3040 ? + assign IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3040 = + m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3039 ? m_vrg_source_prio_6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3036 ; - assign IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3135 = - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3134 ? + IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3035 ; + assign IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3134 = + m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3133 ? m_vrg_source_prio_6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3130 ; + IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3129 ; assign IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d587 = m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586 ? m_vrg_source_prio_6 : IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d580 ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3046 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3045 ? + assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3045 = + m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3044 ? m_vrg_source_prio_7 : - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3041 ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3098 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3045 ? + IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3040 ; + assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3097 = + m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3044 ? 5'd7 : - (m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3040 ? + (m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3039 ? 5'd6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3096) ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3140 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3139 ? + IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3095) ; + assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3139 = + m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3138 ? m_vrg_source_prio_7 : - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3135 ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3192 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3139 ? + IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3134 ; + assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3191 = + m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3138 ? 5'd7 : - (m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3134 ? + (m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3133 ? 5'd6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3190) ; + IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3189) ; assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d594 = m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d593 ? m_vrg_source_prio_7 : @@ -5149,38 +5143,38 @@ module mkPLIC_16_2_7(CLK, (m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586 ? 5'd6 : IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d661) ; - assign IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3051 = - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3050 ? + assign IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3050 = + m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3049 ? m_vrg_source_prio_8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3046 ; - assign IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3145 = - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3144 ? + IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3045 ; + assign IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3144 = + m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3143 ? m_vrg_source_prio_8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3140 ; + IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3139 ; assign IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d601 = m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600 ? m_vrg_source_prio_8 : IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d594 ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3056 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3055 ? + assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3055 = + m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3054 ? m_vrg_source_prio_9 : - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3051 ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3100 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3055 ? + IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3050 ; + assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3099 = + m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3054 ? 5'd9 : - (m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3050 ? + (m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3049 ? 5'd8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3098) ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3150 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3149 ? + IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3097) ; + assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3149 = + m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3148 ? m_vrg_source_prio_9 : - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3145 ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3194 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3149 ? + IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3144 ; + assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3193 = + m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3148 ? 5'd9 : - (m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3144 ? + (m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3143 ? 5'd8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3192) ; + IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3191) ; assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d608 = m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607 ? m_vrg_source_prio_9 : @@ -5237,10792 +5231,10792 @@ module mkPLIC_16_2_7(CLK, x__h23671 == 32'h00200004 && m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 && x__h24009 != 5'd0 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h30683 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h30674 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h31893 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h31884 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h33103 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h33094 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h34313 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h34304 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h35523 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h35514 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h36733 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h36724 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h37943 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h37934 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h39153 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h39144 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h40363 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h40354 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h41573 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h41564 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h42783 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h42774 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h43993 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h43984 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h45203 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h45194 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h46413 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h46404 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h47623 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h47614 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h48833 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h48824 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h50043 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h50034 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h51253 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h51244 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h52463 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h52454 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h53673 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h53664 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h54883 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h54874 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h56093 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h56084 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h57303 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h57294 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h58513 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h58504 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h59723 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h59714 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h60933 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h60924 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h62143 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h62134 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h63353 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h63344 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h64563 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h64554 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h65773 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2870 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + source_id__h65764 <= 10'd16 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2869 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2883 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - x__h67108 == 32'h00200000 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2894 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - x__h67108 == 32'h00200000 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 && + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2882 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + x__h67099 == 32'h00200000 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2893 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + x__h67099 == 32'h00200000 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879 && m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - x__h67108 == 32'h00200004 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 && - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2966 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - x__h67108 == 32'h00200004 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 && - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 && + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + x__h67099 == 32'h00200004 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879 && + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2965 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + x__h67099 == 32'h00200004 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879 && + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 && m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2976 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - x__h67108 == 32'h00200004 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 && - !SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d852 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - addr_offset__h26927[11:2] != 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d906 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2975 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + x__h67099 == 32'h00200004 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879 && + !SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d851 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + addr_offset__h26920[11:2] != 10'd0 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d905 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d918 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d917 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 ; + assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 = + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h29473 <= 10'd16 ; - assign NOT_m_vrg_source_busy_0_901_238_AND_NOT_m_cfg__ETC___d3242 = + source_id__h29464 <= 10'd16 ; + assign NOT_m_vrg_source_busy_0_900_236_AND_NOT_m_cfg__ETC___d3240 = !m_vrg_source_busy_0 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_0 != v_sources_0_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_10_911_316_AND_NOT_m_cfg_ETC___d3320 = + assign NOT_m_vrg_source_busy_10_910_314_AND_NOT_m_cfg_ETC___d3318 = !m_vrg_source_busy_10 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_10 != v_sources_10_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_11_912_324_AND_NOT_m_cfg_ETC___d3328 = + assign NOT_m_vrg_source_busy_11_911_322_AND_NOT_m_cfg_ETC___d3326 = !m_vrg_source_busy_11 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_11 != v_sources_11_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_12_913_332_AND_NOT_m_cfg_ETC___d3336 = + assign NOT_m_vrg_source_busy_12_912_330_AND_NOT_m_cfg_ETC___d3334 = !m_vrg_source_busy_12 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_12 != v_sources_12_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_13_914_340_AND_NOT_m_cfg_ETC___d3344 = + assign NOT_m_vrg_source_busy_13_913_338_AND_NOT_m_cfg_ETC___d3342 = !m_vrg_source_busy_13 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_13 != v_sources_13_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_14_915_348_AND_NOT_m_cfg_ETC___d3352 = + assign NOT_m_vrg_source_busy_14_914_346_AND_NOT_m_cfg_ETC___d3350 = !m_vrg_source_busy_14 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_14 != v_sources_14_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_15_916_356_AND_NOT_m_cfg_ETC___d3360 = + assign NOT_m_vrg_source_busy_15_915_354_AND_NOT_m_cfg_ETC___d3358 = !m_vrg_source_busy_15 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_15 != v_sources_15_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_1_902_245_AND_NOT_m_cfg__ETC___d3249 = + assign NOT_m_vrg_source_busy_1_901_243_AND_NOT_m_cfg__ETC___d3247 = !m_vrg_source_busy_1 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_1 != v_sources_1_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_2_903_252_AND_NOT_m_cfg__ETC___d3256 = + assign NOT_m_vrg_source_busy_2_902_250_AND_NOT_m_cfg__ETC___d3254 = !m_vrg_source_busy_2 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_2 != v_sources_2_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_3_904_260_AND_NOT_m_cfg__ETC___d3264 = + assign NOT_m_vrg_source_busy_3_903_258_AND_NOT_m_cfg__ETC___d3262 = !m_vrg_source_busy_3 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_3 != v_sources_3_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_4_905_268_AND_NOT_m_cfg__ETC___d3272 = + assign NOT_m_vrg_source_busy_4_904_266_AND_NOT_m_cfg__ETC___d3270 = !m_vrg_source_busy_4 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_4 != v_sources_4_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_5_906_276_AND_NOT_m_cfg__ETC___d3280 = + assign NOT_m_vrg_source_busy_5_905_274_AND_NOT_m_cfg__ETC___d3278 = !m_vrg_source_busy_5 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_5 != v_sources_5_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_6_907_284_AND_NOT_m_cfg__ETC___d3288 = + assign NOT_m_vrg_source_busy_6_906_282_AND_NOT_m_cfg__ETC___d3286 = !m_vrg_source_busy_6 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_6 != v_sources_6_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_7_908_292_AND_NOT_m_cfg__ETC___d3296 = + assign NOT_m_vrg_source_busy_7_907_290_AND_NOT_m_cfg__ETC___d3294 = !m_vrg_source_busy_7 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_7 != v_sources_7_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_8_909_300_AND_NOT_m_cfg__ETC___d3304 = + assign NOT_m_vrg_source_busy_8_908_298_AND_NOT_m_cfg__ETC___d3302 = !m_vrg_source_busy_8 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_8 != v_sources_8_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_9_910_308_AND_NOT_m_cfg__ETC___d3312 = + assign NOT_m_vrg_source_busy_9_909_306_AND_NOT_m_cfg__ETC___d3310 = !m_vrg_source_busy_9 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_9 != v_sources_9_m_interrupt_req_set_not_clear ; assign _dfoo1 = - source_id__h64563 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo10 = - (source_id__h64563 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo100 = - (source_id__h63353 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo32 ; assign _dfoo1000 = - (source_id__h47623 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo932 ; assign _dfoo1001 = - source_id__h47623 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo865 ; assign _dfoo1002 = - (source_id__h47623 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo934 ; assign _dfoo1003 = - source_id__h47623 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo867 ; assign _dfoo1004 = - (source_id__h47623 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo936 ; assign _dfoo1005 = - source_id__h47623 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo869 ; assign _dfoo1006 = - (source_id__h47623 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo938 ; assign _dfoo1007 = - source_id__h47623 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo871 ; assign _dfoo1008 = - (source_id__h47623 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo940 ; assign _dfoo1009 = - source_id__h47623 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo873 ; assign _dfoo1010 = - (source_id__h47623 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo942 ; assign _dfoo1011 = - source_id__h47623 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo875 ; assign _dfoo1012 = - (source_id__h47623 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo944 ; assign _dfoo1013 = - source_id__h47623 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo877 ; assign _dfoo1014 = - (source_id__h47623 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo946 ; assign _dfoo1015 = - source_id__h47623 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo879 ; assign _dfoo1016 = - (source_id__h47623 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo948 ; assign _dfoo1017 = - source_id__h47623 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo881 ; assign _dfoo1018 = - (source_id__h47623 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo950 ; assign _dfoo1019 = - source_id__h47623 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo883 ; assign _dfoo102 = - (source_id__h63353 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo34 ; assign _dfoo1020 = - (source_id__h47623 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo952 ; assign _dfoo1022 = - (source_id__h46413 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo954 ; assign _dfoo1024 = - (source_id__h46413 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo956 ; assign _dfoo1026 = - (source_id__h46413 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo958 ; assign _dfoo1028 = - (source_id__h46413 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo960 ; assign _dfoo1030 = - (source_id__h46413 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo962 ; assign _dfoo1032 = - (source_id__h46413 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo964 ; assign _dfoo1034 = - (source_id__h46413 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo966 ; assign _dfoo1036 = - (source_id__h46413 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo968 ; assign _dfoo1038 = - (source_id__h46413 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo970 ; assign _dfoo104 = - (source_id__h63353 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo36 ; assign _dfoo1040 = - (source_id__h46413 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo972 ; assign _dfoo1042 = - (source_id__h46413 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo974 ; assign _dfoo1044 = - (source_id__h46413 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo976 ; assign _dfoo1046 = - (source_id__h46413 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo978 ; assign _dfoo1048 = - (source_id__h46413 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo980 ; assign _dfoo1050 = - (source_id__h46413 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo982 ; assign _dfoo1052 = - (source_id__h46413 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo984 ; assign _dfoo1054 = - (source_id__h46413 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo986 ; assign _dfoo1056 = - (source_id__h46413 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo988 ; assign _dfoo1058 = - (source_id__h46413 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo990 ; assign _dfoo106 = - (source_id__h63353 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo38 ; assign _dfoo1060 = - (source_id__h46413 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo992 ; assign _dfoo1062 = - (source_id__h46413 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo994 ; assign _dfoo1064 = - (source_id__h46413 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo996 ; assign _dfoo1066 = - (source_id__h46413 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo998 ; assign _dfoo1068 = - (source_id__h46413 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo1000 ; assign _dfoo1070 = - (source_id__h46413 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo1002 ; assign _dfoo1072 = - (source_id__h46413 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo1004 ; assign _dfoo1074 = - (source_id__h46413 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo1006 ; assign _dfoo1076 = - (source_id__h46413 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo1008 ; assign _dfoo1078 = - (source_id__h46413 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo1010 ; assign _dfoo108 = - (source_id__h63353 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo40 ; assign _dfoo1080 = - (source_id__h46413 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo1012 ; assign _dfoo1082 = - (source_id__h46413 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo1014 ; assign _dfoo1084 = - (source_id__h46413 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo1016 ; assign _dfoo1086 = - (source_id__h46413 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo1018 ; assign _dfoo1088 = - (source_id__h46413 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26928[15] : + (source_id__h46404 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? + wdata32__h26921[15] : _dfoo1020 ; assign _dfoo1089 = - source_id__h45203 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo953 ; assign _dfoo1090 = - (source_id__h45203 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1022 ; assign _dfoo1091 = - source_id__h45203 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo955 ; assign _dfoo1092 = - (source_id__h45203 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1024 ; assign _dfoo1093 = - source_id__h45203 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo957 ; assign _dfoo1094 = - (source_id__h45203 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1026 ; assign _dfoo1095 = - source_id__h45203 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo959 ; assign _dfoo1096 = - (source_id__h45203 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1028 ; assign _dfoo1097 = - source_id__h45203 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo961 ; assign _dfoo1098 = - (source_id__h45203 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1030 ; assign _dfoo1099 = - source_id__h45203 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo963 ; assign _dfoo11 = - source_id__h64563 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo110 = - (source_id__h63353 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo42 ; assign _dfoo1100 = - (source_id__h45203 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1032 ; assign _dfoo1101 = - source_id__h45203 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo965 ; assign _dfoo1102 = - (source_id__h45203 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1034 ; assign _dfoo1103 = - source_id__h45203 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo967 ; assign _dfoo1104 = - (source_id__h45203 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1036 ; assign _dfoo1105 = - source_id__h45203 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo969 ; assign _dfoo1106 = - (source_id__h45203 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1038 ; assign _dfoo1107 = - source_id__h45203 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo971 ; assign _dfoo1108 = - (source_id__h45203 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1040 ; assign _dfoo1109 = - source_id__h45203 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo973 ; assign _dfoo1110 = - (source_id__h45203 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1042 ; assign _dfoo1111 = - source_id__h45203 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo975 ; assign _dfoo1112 = - (source_id__h45203 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1044 ; assign _dfoo1113 = - source_id__h45203 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo977 ; assign _dfoo1114 = - (source_id__h45203 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1046 ; assign _dfoo1115 = - source_id__h45203 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo979 ; assign _dfoo1116 = - (source_id__h45203 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1048 ; assign _dfoo1117 = - source_id__h45203 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo981 ; assign _dfoo1118 = - (source_id__h45203 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1050 ; assign _dfoo1119 = - source_id__h45203 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo983 ; assign _dfoo112 = - (source_id__h63353 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo44 ; assign _dfoo1120 = - (source_id__h45203 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1052 ; assign _dfoo1121 = - source_id__h45203 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo985 ; assign _dfoo1122 = - (source_id__h45203 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1054 ; assign _dfoo1123 = - source_id__h45203 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo987 ; assign _dfoo1124 = - (source_id__h45203 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1056 ; assign _dfoo1125 = - source_id__h45203 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo989 ; assign _dfoo1126 = - (source_id__h45203 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1058 ; assign _dfoo1127 = - source_id__h45203 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo991 ; assign _dfoo1128 = - (source_id__h45203 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1060 ; assign _dfoo1129 = - source_id__h45203 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo993 ; assign _dfoo1130 = - (source_id__h45203 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1062 ; assign _dfoo1131 = - source_id__h45203 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo995 ; assign _dfoo1132 = - (source_id__h45203 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1064 ; assign _dfoo1133 = - source_id__h45203 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo997 ; assign _dfoo1134 = - (source_id__h45203 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1066 ; assign _dfoo1135 = - source_id__h45203 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo999 ; assign _dfoo1136 = - (source_id__h45203 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1068 ; assign _dfoo1137 = - source_id__h45203 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo1001 ; assign _dfoo1138 = - (source_id__h45203 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1070 ; assign _dfoo1139 = - source_id__h45203 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo1003 ; assign _dfoo114 = - (source_id__h63353 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo46 ; assign _dfoo1140 = - (source_id__h45203 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1072 ; assign _dfoo1141 = - source_id__h45203 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo1005 ; assign _dfoo1142 = - (source_id__h45203 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1074 ; assign _dfoo1143 = - source_id__h45203 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo1007 ; assign _dfoo1144 = - (source_id__h45203 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1076 ; assign _dfoo1145 = - source_id__h45203 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo1009 ; assign _dfoo1146 = - (source_id__h45203 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1078 ; assign _dfoo1147 = - source_id__h45203 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo1011 ; assign _dfoo1148 = - (source_id__h45203 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1080 ; assign _dfoo1149 = - source_id__h45203 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo1013 ; assign _dfoo1150 = - (source_id__h45203 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1082 ; assign _dfoo1151 = - source_id__h45203 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo1015 ; assign _dfoo1152 = - (source_id__h45203 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1084 ; assign _dfoo1153 = - source_id__h45203 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo1017 ; assign _dfoo1154 = - (source_id__h45203 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1086 ; assign _dfoo1155 = - source_id__h45203 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46413 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || + source_id__h45194 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || + source_id__h46404 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || _dfoo1019 ; assign _dfoo1156 = - (source_id__h45203 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26928[14] : + (source_id__h45194 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? + wdata32__h26921[14] : _dfoo1088 ; assign _dfoo1158 = - (source_id__h43993 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1090 ; assign _dfoo116 = - (source_id__h63353 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo48 ; assign _dfoo1160 = - (source_id__h43993 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1092 ; assign _dfoo1162 = - (source_id__h43993 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1094 ; assign _dfoo1164 = - (source_id__h43993 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1096 ; assign _dfoo1166 = - (source_id__h43993 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1098 ; assign _dfoo1168 = - (source_id__h43993 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1100 ; assign _dfoo1170 = - (source_id__h43993 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1102 ; assign _dfoo1172 = - (source_id__h43993 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1104 ; assign _dfoo1174 = - (source_id__h43993 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1106 ; assign _dfoo1176 = - (source_id__h43993 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1108 ; assign _dfoo1178 = - (source_id__h43993 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1110 ; assign _dfoo118 = - (source_id__h63353 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo50 ; assign _dfoo1180 = - (source_id__h43993 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1112 ; assign _dfoo1182 = - (source_id__h43993 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1114 ; assign _dfoo1184 = - (source_id__h43993 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1116 ; assign _dfoo1186 = - (source_id__h43993 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1118 ; assign _dfoo1188 = - (source_id__h43993 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1120 ; assign _dfoo1190 = - (source_id__h43993 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1122 ; assign _dfoo1192 = - (source_id__h43993 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1124 ; assign _dfoo1194 = - (source_id__h43993 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1126 ; assign _dfoo1196 = - (source_id__h43993 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1128 ; assign _dfoo1198 = - (source_id__h43993 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1130 ; assign _dfoo12 = - (source_id__h64563 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo120 = - (source_id__h63353 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo52 ; assign _dfoo1200 = - (source_id__h43993 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1132 ; assign _dfoo1202 = - (source_id__h43993 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1134 ; assign _dfoo1204 = - (source_id__h43993 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1136 ; assign _dfoo1206 = - (source_id__h43993 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1138 ; assign _dfoo1208 = - (source_id__h43993 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1140 ; assign _dfoo1210 = - (source_id__h43993 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1142 ; assign _dfoo1212 = - (source_id__h43993 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1144 ; assign _dfoo1214 = - (source_id__h43993 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1146 ; assign _dfoo1216 = - (source_id__h43993 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1148 ; assign _dfoo1218 = - (source_id__h43993 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1150 ; assign _dfoo122 = - (source_id__h63353 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo54 ; assign _dfoo1220 = - (source_id__h43993 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1152 ; assign _dfoo1222 = - (source_id__h43993 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1154 ; assign _dfoo1224 = - (source_id__h43993 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26928[13] : + (source_id__h43984 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? + wdata32__h26921[13] : _dfoo1156 ; assign _dfoo1225 = - source_id__h42783 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1089 ; assign _dfoo1226 = - (source_id__h42783 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1158 ; assign _dfoo1227 = - source_id__h42783 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1091 ; assign _dfoo1228 = - (source_id__h42783 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1160 ; assign _dfoo1229 = - source_id__h42783 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1093 ; assign _dfoo1230 = - (source_id__h42783 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1162 ; assign _dfoo1231 = - source_id__h42783 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1095 ; assign _dfoo1232 = - (source_id__h42783 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1164 ; assign _dfoo1233 = - source_id__h42783 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1097 ; assign _dfoo1234 = - (source_id__h42783 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1166 ; assign _dfoo1235 = - source_id__h42783 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1099 ; assign _dfoo1236 = - (source_id__h42783 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1168 ; assign _dfoo1237 = - source_id__h42783 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1101 ; assign _dfoo1238 = - (source_id__h42783 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1170 ; assign _dfoo1239 = - source_id__h42783 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1103 ; assign _dfoo124 = - (source_id__h63353 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo56 ; assign _dfoo1240 = - (source_id__h42783 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1172 ; assign _dfoo1241 = - source_id__h42783 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1105 ; assign _dfoo1242 = - (source_id__h42783 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1174 ; assign _dfoo1243 = - source_id__h42783 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1107 ; assign _dfoo1244 = - (source_id__h42783 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1176 ; assign _dfoo1245 = - source_id__h42783 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1109 ; assign _dfoo1246 = - (source_id__h42783 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1178 ; assign _dfoo1247 = - source_id__h42783 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1111 ; assign _dfoo1248 = - (source_id__h42783 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1180 ; assign _dfoo1249 = - source_id__h42783 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1113 ; assign _dfoo1250 = - (source_id__h42783 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1182 ; assign _dfoo1251 = - source_id__h42783 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1115 ; assign _dfoo1252 = - (source_id__h42783 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1184 ; assign _dfoo1253 = - source_id__h42783 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1117 ; assign _dfoo1254 = - (source_id__h42783 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1186 ; assign _dfoo1255 = - source_id__h42783 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1119 ; assign _dfoo1256 = - (source_id__h42783 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1188 ; assign _dfoo1257 = - source_id__h42783 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1121 ; assign _dfoo1258 = - (source_id__h42783 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1190 ; assign _dfoo1259 = - source_id__h42783 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1123 ; assign _dfoo126 = - (source_id__h63353 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo58 ; assign _dfoo1260 = - (source_id__h42783 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1192 ; assign _dfoo1261 = - source_id__h42783 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1125 ; assign _dfoo1262 = - (source_id__h42783 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1194 ; assign _dfoo1263 = - source_id__h42783 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1127 ; assign _dfoo1264 = - (source_id__h42783 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1196 ; assign _dfoo1265 = - source_id__h42783 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1129 ; assign _dfoo1266 = - (source_id__h42783 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1198 ; assign _dfoo1267 = - source_id__h42783 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1131 ; assign _dfoo1268 = - (source_id__h42783 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1200 ; assign _dfoo1269 = - source_id__h42783 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1133 ; assign _dfoo1270 = - (source_id__h42783 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1202 ; assign _dfoo1271 = - source_id__h42783 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1135 ; assign _dfoo1272 = - (source_id__h42783 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1204 ; assign _dfoo1273 = - source_id__h42783 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1137 ; assign _dfoo1274 = - (source_id__h42783 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1206 ; assign _dfoo1275 = - source_id__h42783 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1139 ; assign _dfoo1276 = - (source_id__h42783 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1208 ; assign _dfoo1277 = - source_id__h42783 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1141 ; assign _dfoo1278 = - (source_id__h42783 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1210 ; assign _dfoo1279 = - source_id__h42783 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1143 ; assign _dfoo128 = - (source_id__h63353 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo60 ; assign _dfoo1280 = - (source_id__h42783 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1212 ; assign _dfoo1281 = - source_id__h42783 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1145 ; assign _dfoo1282 = - (source_id__h42783 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1214 ; assign _dfoo1283 = - source_id__h42783 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1147 ; assign _dfoo1284 = - (source_id__h42783 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1216 ; assign _dfoo1285 = - source_id__h42783 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1149 ; assign _dfoo1286 = - (source_id__h42783 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1218 ; assign _dfoo1287 = - source_id__h42783 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1151 ; assign _dfoo1288 = - (source_id__h42783 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1220 ; assign _dfoo1289 = - source_id__h42783 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1153 ; assign _dfoo1290 = - (source_id__h42783 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1222 ; assign _dfoo1291 = - source_id__h42783 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43993 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || + source_id__h42774 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || + source_id__h43984 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || _dfoo1155 ; assign _dfoo1292 = - (source_id__h42783 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26928[12] : + (source_id__h42774 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? + wdata32__h26921[12] : _dfoo1224 ; assign _dfoo1294 = - (source_id__h41573 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1226 ; assign _dfoo1296 = - (source_id__h41573 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1228 ; assign _dfoo1298 = - (source_id__h41573 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1230 ; assign _dfoo13 = - source_id__h64563 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo130 = - (source_id__h63353 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo62 ; assign _dfoo1300 = - (source_id__h41573 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1232 ; assign _dfoo1302 = - (source_id__h41573 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1234 ; assign _dfoo1304 = - (source_id__h41573 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1236 ; assign _dfoo1306 = - (source_id__h41573 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1238 ; assign _dfoo1308 = - (source_id__h41573 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1240 ; assign _dfoo1310 = - (source_id__h41573 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1242 ; assign _dfoo1312 = - (source_id__h41573 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1244 ; assign _dfoo1314 = - (source_id__h41573 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1246 ; assign _dfoo1316 = - (source_id__h41573 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1248 ; assign _dfoo1318 = - (source_id__h41573 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1250 ; assign _dfoo132 = - (source_id__h63353 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo64 ; assign _dfoo1320 = - (source_id__h41573 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1252 ; assign _dfoo1322 = - (source_id__h41573 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1254 ; assign _dfoo1324 = - (source_id__h41573 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1256 ; assign _dfoo1326 = - (source_id__h41573 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1258 ; assign _dfoo1328 = - (source_id__h41573 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1260 ; assign _dfoo1330 = - (source_id__h41573 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1262 ; assign _dfoo1332 = - (source_id__h41573 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1264 ; assign _dfoo1334 = - (source_id__h41573 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1266 ; assign _dfoo1336 = - (source_id__h41573 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1268 ; assign _dfoo1338 = - (source_id__h41573 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1270 ; assign _dfoo134 = - (source_id__h63353 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo66 ; assign _dfoo1340 = - (source_id__h41573 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1272 ; assign _dfoo1342 = - (source_id__h41573 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1274 ; assign _dfoo1344 = - (source_id__h41573 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1276 ; assign _dfoo1346 = - (source_id__h41573 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1278 ; assign _dfoo1348 = - (source_id__h41573 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1280 ; assign _dfoo1350 = - (source_id__h41573 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1282 ; assign _dfoo1352 = - (source_id__h41573 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1284 ; assign _dfoo1354 = - (source_id__h41573 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1286 ; assign _dfoo1356 = - (source_id__h41573 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1288 ; assign _dfoo1358 = - (source_id__h41573 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1290 ; assign _dfoo136 = - (source_id__h63353 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo68 ; assign _dfoo1360 = - (source_id__h41573 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26928[11] : + (source_id__h41564 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? + wdata32__h26921[11] : _dfoo1292 ; assign _dfoo1361 = - source_id__h40363 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1225 ; assign _dfoo1362 = - (source_id__h40363 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1294 ; assign _dfoo1363 = - source_id__h40363 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1227 ; assign _dfoo1364 = - (source_id__h40363 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1296 ; assign _dfoo1365 = - source_id__h40363 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1229 ; assign _dfoo1366 = - (source_id__h40363 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1298 ; assign _dfoo1367 = - source_id__h40363 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1231 ; assign _dfoo1368 = - (source_id__h40363 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1300 ; assign _dfoo1369 = - source_id__h40363 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1233 ; assign _dfoo137 = - source_id__h62143 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo1 ; assign _dfoo1370 = - (source_id__h40363 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1302 ; assign _dfoo1371 = - source_id__h40363 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1235 ; assign _dfoo1372 = - (source_id__h40363 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1304 ; assign _dfoo1373 = - source_id__h40363 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1237 ; assign _dfoo1374 = - (source_id__h40363 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1306 ; assign _dfoo1375 = - source_id__h40363 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1239 ; assign _dfoo1376 = - (source_id__h40363 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1308 ; assign _dfoo1377 = - source_id__h40363 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1241 ; assign _dfoo1378 = - (source_id__h40363 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1310 ; assign _dfoo1379 = - source_id__h40363 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1243 ; assign _dfoo138 = - (source_id__h62143 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo70 ; assign _dfoo1380 = - (source_id__h40363 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1312 ; assign _dfoo1381 = - source_id__h40363 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1245 ; assign _dfoo1382 = - (source_id__h40363 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1314 ; assign _dfoo1383 = - source_id__h40363 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1247 ; assign _dfoo1384 = - (source_id__h40363 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1316 ; assign _dfoo1385 = - source_id__h40363 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1249 ; assign _dfoo1386 = - (source_id__h40363 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1318 ; assign _dfoo1387 = - source_id__h40363 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1251 ; assign _dfoo1388 = - (source_id__h40363 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1320 ; assign _dfoo1389 = - source_id__h40363 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1253 ; assign _dfoo139 = - source_id__h62143 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo3 ; assign _dfoo1390 = - (source_id__h40363 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1322 ; assign _dfoo1391 = - source_id__h40363 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1255 ; assign _dfoo1392 = - (source_id__h40363 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1324 ; assign _dfoo1393 = - source_id__h40363 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1257 ; assign _dfoo1394 = - (source_id__h40363 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1326 ; assign _dfoo1395 = - source_id__h40363 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1259 ; assign _dfoo1396 = - (source_id__h40363 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1328 ; assign _dfoo1397 = - source_id__h40363 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1261 ; assign _dfoo1398 = - (source_id__h40363 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1330 ; assign _dfoo1399 = - source_id__h40363 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1263 ; assign _dfoo14 = - (source_id__h64563 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo140 = - (source_id__h62143 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo72 ; assign _dfoo1400 = - (source_id__h40363 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1332 ; assign _dfoo1401 = - source_id__h40363 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1265 ; assign _dfoo1402 = - (source_id__h40363 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1334 ; assign _dfoo1403 = - source_id__h40363 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1267 ; assign _dfoo1404 = - (source_id__h40363 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1336 ; assign _dfoo1405 = - source_id__h40363 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1269 ; assign _dfoo1406 = - (source_id__h40363 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1338 ; assign _dfoo1407 = - source_id__h40363 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1271 ; assign _dfoo1408 = - (source_id__h40363 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1340 ; assign _dfoo1409 = - source_id__h40363 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1273 ; assign _dfoo141 = - source_id__h62143 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo5 ; assign _dfoo1410 = - (source_id__h40363 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1342 ; assign _dfoo1411 = - source_id__h40363 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1275 ; assign _dfoo1412 = - (source_id__h40363 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1344 ; assign _dfoo1413 = - source_id__h40363 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1277 ; assign _dfoo1414 = - (source_id__h40363 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1346 ; assign _dfoo1415 = - source_id__h40363 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1279 ; assign _dfoo1416 = - (source_id__h40363 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1348 ; assign _dfoo1417 = - source_id__h40363 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1281 ; assign _dfoo1418 = - (source_id__h40363 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1350 ; assign _dfoo1419 = - source_id__h40363 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1283 ; assign _dfoo142 = - (source_id__h62143 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo74 ; assign _dfoo1420 = - (source_id__h40363 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1352 ; assign _dfoo1421 = - source_id__h40363 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1285 ; assign _dfoo1422 = - (source_id__h40363 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1354 ; assign _dfoo1423 = - source_id__h40363 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1287 ; assign _dfoo1424 = - (source_id__h40363 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1356 ; assign _dfoo1425 = - source_id__h40363 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1289 ; assign _dfoo1426 = - (source_id__h40363 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1358 ; assign _dfoo1427 = - source_id__h40363 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41573 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || + source_id__h40354 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || + source_id__h41564 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || _dfoo1291 ; assign _dfoo1428 = - (source_id__h40363 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26928[10] : + (source_id__h40354 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? + wdata32__h26921[10] : _dfoo1360 ; assign _dfoo143 = - source_id__h62143 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo7 ; assign _dfoo1430 = - (source_id__h39153 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1362 ; assign _dfoo1432 = - (source_id__h39153 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1364 ; assign _dfoo1434 = - (source_id__h39153 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1366 ; assign _dfoo1436 = - (source_id__h39153 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1368 ; assign _dfoo1438 = - (source_id__h39153 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1370 ; assign _dfoo144 = - (source_id__h62143 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo76 ; assign _dfoo1440 = - (source_id__h39153 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1372 ; assign _dfoo1442 = - (source_id__h39153 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1374 ; assign _dfoo1444 = - (source_id__h39153 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1376 ; assign _dfoo1446 = - (source_id__h39153 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1378 ; assign _dfoo1448 = - (source_id__h39153 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1380 ; assign _dfoo145 = - source_id__h62143 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo9 ; assign _dfoo1450 = - (source_id__h39153 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1382 ; assign _dfoo1452 = - (source_id__h39153 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1384 ; assign _dfoo1454 = - (source_id__h39153 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1386 ; assign _dfoo1456 = - (source_id__h39153 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1388 ; assign _dfoo1458 = - (source_id__h39153 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1390 ; assign _dfoo146 = - (source_id__h62143 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo78 ; assign _dfoo1460 = - (source_id__h39153 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1392 ; assign _dfoo1462 = - (source_id__h39153 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1394 ; assign _dfoo1464 = - (source_id__h39153 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1396 ; assign _dfoo1466 = - (source_id__h39153 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1398 ; assign _dfoo1468 = - (source_id__h39153 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1400 ; assign _dfoo147 = - source_id__h62143 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo11 ; assign _dfoo1470 = - (source_id__h39153 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1402 ; assign _dfoo1472 = - (source_id__h39153 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1404 ; assign _dfoo1474 = - (source_id__h39153 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1406 ; assign _dfoo1476 = - (source_id__h39153 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1408 ; assign _dfoo1478 = - (source_id__h39153 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1410 ; assign _dfoo148 = - (source_id__h62143 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo80 ; assign _dfoo1480 = - (source_id__h39153 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1412 ; assign _dfoo1482 = - (source_id__h39153 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1414 ; assign _dfoo1484 = - (source_id__h39153 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1416 ; assign _dfoo1486 = - (source_id__h39153 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1418 ; assign _dfoo1488 = - (source_id__h39153 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1420 ; assign _dfoo149 = - source_id__h62143 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo13 ; assign _dfoo1490 = - (source_id__h39153 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1422 ; assign _dfoo1492 = - (source_id__h39153 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1424 ; assign _dfoo1494 = - (source_id__h39153 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1426 ; assign _dfoo1496 = - (source_id__h39153 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26928[9] : + (source_id__h39144 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? + wdata32__h26921[9] : _dfoo1428 ; assign _dfoo1497 = - source_id__h37943 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1361 ; assign _dfoo1498 = - (source_id__h37943 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1430 ; assign _dfoo1499 = - source_id__h37943 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1363 ; assign _dfoo15 = - source_id__h64563 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo150 = - (source_id__h62143 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo82 ; assign _dfoo1500 = - (source_id__h37943 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1432 ; assign _dfoo1501 = - source_id__h37943 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1365 ; assign _dfoo1502 = - (source_id__h37943 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1434 ; assign _dfoo1503 = - source_id__h37943 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1367 ; assign _dfoo1504 = - (source_id__h37943 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1436 ; assign _dfoo1505 = - source_id__h37943 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1369 ; assign _dfoo1506 = - (source_id__h37943 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1438 ; assign _dfoo1507 = - source_id__h37943 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1371 ; assign _dfoo1508 = - (source_id__h37943 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1440 ; assign _dfoo1509 = - source_id__h37943 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1373 ; assign _dfoo151 = - source_id__h62143 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo15 ; assign _dfoo1510 = - (source_id__h37943 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1442 ; assign _dfoo1511 = - source_id__h37943 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1375 ; assign _dfoo1512 = - (source_id__h37943 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1444 ; assign _dfoo1513 = - source_id__h37943 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1377 ; assign _dfoo1514 = - (source_id__h37943 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1446 ; assign _dfoo1515 = - source_id__h37943 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1379 ; assign _dfoo1516 = - (source_id__h37943 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1448 ; assign _dfoo1517 = - source_id__h37943 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1381 ; assign _dfoo1518 = - (source_id__h37943 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1450 ; assign _dfoo1519 = - source_id__h37943 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1383 ; assign _dfoo152 = - (source_id__h62143 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo84 ; assign _dfoo1520 = - (source_id__h37943 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1452 ; assign _dfoo1521 = - source_id__h37943 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1385 ; assign _dfoo1522 = - (source_id__h37943 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1454 ; assign _dfoo1523 = - source_id__h37943 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1387 ; assign _dfoo1524 = - (source_id__h37943 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1456 ; assign _dfoo1525 = - source_id__h37943 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1389 ; assign _dfoo1526 = - (source_id__h37943 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1458 ; assign _dfoo1527 = - source_id__h37943 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1391 ; assign _dfoo1528 = - (source_id__h37943 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1460 ; assign _dfoo1529 = - source_id__h37943 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1393 ; assign _dfoo153 = - source_id__h62143 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo17 ; assign _dfoo1530 = - (source_id__h37943 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1462 ; assign _dfoo1531 = - source_id__h37943 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1395 ; assign _dfoo1532 = - (source_id__h37943 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1464 ; assign _dfoo1533 = - source_id__h37943 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1397 ; assign _dfoo1534 = - (source_id__h37943 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1466 ; assign _dfoo1535 = - source_id__h37943 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1399 ; assign _dfoo1536 = - (source_id__h37943 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1468 ; assign _dfoo1537 = - source_id__h37943 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1401 ; assign _dfoo1538 = - (source_id__h37943 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1470 ; assign _dfoo1539 = - source_id__h37943 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1403 ; assign _dfoo154 = - (source_id__h62143 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo86 ; assign _dfoo1540 = - (source_id__h37943 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1472 ; assign _dfoo1541 = - source_id__h37943 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1405 ; assign _dfoo1542 = - (source_id__h37943 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1474 ; assign _dfoo1543 = - source_id__h37943 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1407 ; assign _dfoo1544 = - (source_id__h37943 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1476 ; assign _dfoo1545 = - source_id__h37943 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1409 ; assign _dfoo1546 = - (source_id__h37943 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1478 ; assign _dfoo1547 = - source_id__h37943 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1411 ; assign _dfoo1548 = - (source_id__h37943 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1480 ; assign _dfoo1549 = - source_id__h37943 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1413 ; assign _dfoo155 = - source_id__h62143 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo19 ; assign _dfoo1550 = - (source_id__h37943 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1482 ; assign _dfoo1551 = - source_id__h37943 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1415 ; assign _dfoo1552 = - (source_id__h37943 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1484 ; assign _dfoo1553 = - source_id__h37943 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1417 ; assign _dfoo1554 = - (source_id__h37943 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1486 ; assign _dfoo1555 = - source_id__h37943 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1419 ; assign _dfoo1556 = - (source_id__h37943 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1488 ; assign _dfoo1557 = - source_id__h37943 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1421 ; assign _dfoo1558 = - (source_id__h37943 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1490 ; assign _dfoo1559 = - source_id__h37943 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1423 ; assign _dfoo156 = - (source_id__h62143 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo88 ; assign _dfoo1560 = - (source_id__h37943 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1492 ; assign _dfoo1561 = - source_id__h37943 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1425 ; assign _dfoo1562 = - (source_id__h37943 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1494 ; assign _dfoo1563 = - source_id__h37943 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39153 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || + source_id__h37934 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || + source_id__h39144 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || _dfoo1427 ; assign _dfoo1564 = - (source_id__h37943 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26928[8] : + (source_id__h37934 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? + wdata32__h26921[8] : _dfoo1496 ; assign _dfoo1566 = - (source_id__h36733 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1498 ; assign _dfoo1568 = - (source_id__h36733 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1500 ; assign _dfoo157 = - source_id__h62143 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo21 ; assign _dfoo1570 = - (source_id__h36733 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1502 ; assign _dfoo1572 = - (source_id__h36733 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1504 ; assign _dfoo1574 = - (source_id__h36733 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1506 ; assign _dfoo1576 = - (source_id__h36733 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1508 ; assign _dfoo1578 = - (source_id__h36733 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1510 ; assign _dfoo158 = - (source_id__h62143 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo90 ; assign _dfoo1580 = - (source_id__h36733 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1512 ; assign _dfoo1582 = - (source_id__h36733 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1514 ; assign _dfoo1584 = - (source_id__h36733 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1516 ; assign _dfoo1586 = - (source_id__h36733 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1518 ; assign _dfoo1588 = - (source_id__h36733 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1520 ; assign _dfoo159 = - source_id__h62143 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo23 ; assign _dfoo1590 = - (source_id__h36733 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1522 ; assign _dfoo1592 = - (source_id__h36733 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1524 ; assign _dfoo1594 = - (source_id__h36733 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1526 ; assign _dfoo1596 = - (source_id__h36733 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1528 ; assign _dfoo1598 = - (source_id__h36733 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1530 ; assign _dfoo16 = - (source_id__h64563 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo160 = - (source_id__h62143 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo92 ; assign _dfoo1600 = - (source_id__h36733 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1532 ; assign _dfoo1602 = - (source_id__h36733 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1534 ; assign _dfoo1604 = - (source_id__h36733 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1536 ; assign _dfoo1606 = - (source_id__h36733 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1538 ; assign _dfoo1608 = - (source_id__h36733 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1540 ; assign _dfoo161 = - source_id__h62143 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo25 ; assign _dfoo1610 = - (source_id__h36733 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1542 ; assign _dfoo1612 = - (source_id__h36733 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1544 ; assign _dfoo1614 = - (source_id__h36733 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1546 ; assign _dfoo1616 = - (source_id__h36733 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1548 ; assign _dfoo1618 = - (source_id__h36733 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1550 ; assign _dfoo162 = - (source_id__h62143 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo94 ; assign _dfoo1620 = - (source_id__h36733 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1552 ; assign _dfoo1622 = - (source_id__h36733 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1554 ; assign _dfoo1624 = - (source_id__h36733 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1556 ; assign _dfoo1626 = - (source_id__h36733 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1558 ; assign _dfoo1628 = - (source_id__h36733 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1560 ; assign _dfoo163 = - source_id__h62143 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo27 ; assign _dfoo1630 = - (source_id__h36733 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1562 ; assign _dfoo1632 = - (source_id__h36733 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26928[7] : + (source_id__h36724 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? + wdata32__h26921[7] : _dfoo1564 ; assign _dfoo1633 = - source_id__h35523 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1497 ; assign _dfoo1634 = - (source_id__h35523 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1566 ; assign _dfoo1635 = - source_id__h35523 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1499 ; assign _dfoo1636 = - (source_id__h35523 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1568 ; assign _dfoo1637 = - source_id__h35523 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1501 ; assign _dfoo1638 = - (source_id__h35523 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1570 ; assign _dfoo1639 = - source_id__h35523 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1503 ; assign _dfoo164 = - (source_id__h62143 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo96 ; assign _dfoo1640 = - (source_id__h35523 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1572 ; assign _dfoo1641 = - source_id__h35523 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1505 ; assign _dfoo1642 = - (source_id__h35523 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1574 ; assign _dfoo1643 = - source_id__h35523 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1507 ; assign _dfoo1644 = - (source_id__h35523 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1576 ; assign _dfoo1645 = - source_id__h35523 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1509 ; assign _dfoo1646 = - (source_id__h35523 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1578 ; assign _dfoo1647 = - source_id__h35523 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1511 ; assign _dfoo1648 = - (source_id__h35523 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1580 ; assign _dfoo1649 = - source_id__h35523 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1513 ; assign _dfoo165 = - source_id__h62143 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo29 ; assign _dfoo1650 = - (source_id__h35523 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1582 ; assign _dfoo1651 = - source_id__h35523 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1515 ; assign _dfoo1652 = - (source_id__h35523 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1584 ; assign _dfoo1653 = - source_id__h35523 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1517 ; assign _dfoo1654 = - (source_id__h35523 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1586 ; assign _dfoo1655 = - source_id__h35523 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1519 ; assign _dfoo1656 = - (source_id__h35523 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1588 ; assign _dfoo1657 = - source_id__h35523 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1521 ; assign _dfoo1658 = - (source_id__h35523 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1590 ; assign _dfoo1659 = - source_id__h35523 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1523 ; assign _dfoo166 = - (source_id__h62143 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo98 ; assign _dfoo1660 = - (source_id__h35523 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1592 ; assign _dfoo1661 = - source_id__h35523 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1525 ; assign _dfoo1662 = - (source_id__h35523 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1594 ; assign _dfoo1663 = - source_id__h35523 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1527 ; assign _dfoo1664 = - (source_id__h35523 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1596 ; assign _dfoo1665 = - source_id__h35523 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1529 ; assign _dfoo1666 = - (source_id__h35523 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1598 ; assign _dfoo1667 = - source_id__h35523 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1531 ; assign _dfoo1668 = - (source_id__h35523 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1600 ; assign _dfoo1669 = - source_id__h35523 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1533 ; assign _dfoo167 = - source_id__h62143 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo31 ; assign _dfoo1670 = - (source_id__h35523 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1602 ; assign _dfoo1671 = - source_id__h35523 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1535 ; assign _dfoo1672 = - (source_id__h35523 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1604 ; assign _dfoo1673 = - source_id__h35523 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1537 ; assign _dfoo1674 = - (source_id__h35523 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1606 ; assign _dfoo1675 = - source_id__h35523 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1539 ; assign _dfoo1676 = - (source_id__h35523 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1608 ; assign _dfoo1677 = - source_id__h35523 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1541 ; assign _dfoo1678 = - (source_id__h35523 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1610 ; assign _dfoo1679 = - source_id__h35523 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1543 ; assign _dfoo168 = - (source_id__h62143 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo100 ; assign _dfoo1680 = - (source_id__h35523 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1612 ; assign _dfoo1681 = - source_id__h35523 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1545 ; assign _dfoo1682 = - (source_id__h35523 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1614 ; assign _dfoo1683 = - source_id__h35523 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1547 ; assign _dfoo1684 = - (source_id__h35523 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1616 ; assign _dfoo1685 = - source_id__h35523 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1549 ; assign _dfoo1686 = - (source_id__h35523 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1618 ; assign _dfoo1687 = - source_id__h35523 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1551 ; assign _dfoo1688 = - (source_id__h35523 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1620 ; assign _dfoo1689 = - source_id__h35523 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1553 ; assign _dfoo169 = - source_id__h62143 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo33 ; assign _dfoo1690 = - (source_id__h35523 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1622 ; assign _dfoo1691 = - source_id__h35523 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1555 ; assign _dfoo1692 = - (source_id__h35523 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1624 ; assign _dfoo1693 = - source_id__h35523 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1557 ; assign _dfoo1694 = - (source_id__h35523 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1626 ; assign _dfoo1695 = - source_id__h35523 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1559 ; assign _dfoo1696 = - (source_id__h35523 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1628 ; assign _dfoo1697 = - source_id__h35523 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1561 ; assign _dfoo1698 = - (source_id__h35523 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1630 ; assign _dfoo1699 = - source_id__h35523 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36733 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || + source_id__h35514 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || + source_id__h36724 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || _dfoo1563 ; assign _dfoo17 = - source_id__h64563 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo170 = - (source_id__h62143 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo102 ; assign _dfoo1700 = - (source_id__h35523 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26928[6] : + (source_id__h35514 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? + wdata32__h26921[6] : _dfoo1632 ; assign _dfoo1702 = - (source_id__h34313 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1634 ; assign _dfoo1704 = - (source_id__h34313 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1636 ; assign _dfoo1706 = - (source_id__h34313 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1638 ; assign _dfoo1708 = - (source_id__h34313 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1640 ; assign _dfoo171 = - source_id__h62143 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo35 ; assign _dfoo1710 = - (source_id__h34313 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1642 ; assign _dfoo1712 = - (source_id__h34313 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1644 ; assign _dfoo1714 = - (source_id__h34313 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1646 ; assign _dfoo1716 = - (source_id__h34313 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1648 ; assign _dfoo1718 = - (source_id__h34313 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1650 ; assign _dfoo172 = - (source_id__h62143 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo104 ; assign _dfoo1720 = - (source_id__h34313 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1652 ; assign _dfoo1722 = - (source_id__h34313 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1654 ; assign _dfoo1724 = - (source_id__h34313 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1656 ; assign _dfoo1726 = - (source_id__h34313 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1658 ; assign _dfoo1728 = - (source_id__h34313 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1660 ; assign _dfoo173 = - source_id__h62143 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo37 ; assign _dfoo1730 = - (source_id__h34313 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1662 ; assign _dfoo1732 = - (source_id__h34313 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1664 ; assign _dfoo1734 = - (source_id__h34313 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1666 ; assign _dfoo1736 = - (source_id__h34313 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1668 ; assign _dfoo1738 = - (source_id__h34313 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1670 ; assign _dfoo174 = - (source_id__h62143 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo106 ; assign _dfoo1740 = - (source_id__h34313 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1672 ; assign _dfoo1742 = - (source_id__h34313 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1674 ; assign _dfoo1744 = - (source_id__h34313 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1676 ; assign _dfoo1746 = - (source_id__h34313 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1678 ; assign _dfoo1748 = - (source_id__h34313 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1680 ; assign _dfoo175 = - source_id__h62143 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo39 ; assign _dfoo1750 = - (source_id__h34313 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1682 ; assign _dfoo1752 = - (source_id__h34313 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1684 ; assign _dfoo1754 = - (source_id__h34313 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1686 ; assign _dfoo1756 = - (source_id__h34313 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1688 ; assign _dfoo1758 = - (source_id__h34313 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1690 ; assign _dfoo176 = - (source_id__h62143 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo108 ; assign _dfoo1760 = - (source_id__h34313 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1692 ; assign _dfoo1762 = - (source_id__h34313 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1694 ; assign _dfoo1764 = - (source_id__h34313 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1696 ; assign _dfoo1766 = - (source_id__h34313 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1698 ; assign _dfoo1768 = - (source_id__h34313 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26928[5] : + (source_id__h34304 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? + wdata32__h26921[5] : _dfoo1700 ; assign _dfoo1769 = - source_id__h33103 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1633 ; assign _dfoo177 = - source_id__h62143 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo41 ; assign _dfoo1770 = - (source_id__h33103 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1702 ; assign _dfoo1771 = - source_id__h33103 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1635 ; assign _dfoo1772 = - (source_id__h33103 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1704 ; assign _dfoo1773 = - source_id__h33103 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1637 ; assign _dfoo1774 = - (source_id__h33103 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1706 ; assign _dfoo1775 = - source_id__h33103 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1639 ; assign _dfoo1776 = - (source_id__h33103 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1708 ; assign _dfoo1777 = - source_id__h33103 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1641 ; assign _dfoo1778 = - (source_id__h33103 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1710 ; assign _dfoo1779 = - source_id__h33103 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1643 ; assign _dfoo178 = - (source_id__h62143 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo110 ; assign _dfoo1780 = - (source_id__h33103 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1712 ; assign _dfoo1781 = - source_id__h33103 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1645 ; assign _dfoo1782 = - (source_id__h33103 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1714 ; assign _dfoo1783 = - source_id__h33103 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1647 ; assign _dfoo1784 = - (source_id__h33103 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1716 ; assign _dfoo1785 = - source_id__h33103 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1649 ; assign _dfoo1786 = - (source_id__h33103 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1718 ; assign _dfoo1787 = - source_id__h33103 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1651 ; assign _dfoo1788 = - (source_id__h33103 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1720 ; assign _dfoo1789 = - source_id__h33103 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1653 ; assign _dfoo179 = - source_id__h62143 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo43 ; assign _dfoo1790 = - (source_id__h33103 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1722 ; assign _dfoo1791 = - source_id__h33103 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1655 ; assign _dfoo1792 = - (source_id__h33103 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1724 ; assign _dfoo1793 = - source_id__h33103 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1657 ; assign _dfoo1794 = - (source_id__h33103 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1726 ; assign _dfoo1795 = - source_id__h33103 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1659 ; assign _dfoo1796 = - (source_id__h33103 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1728 ; assign _dfoo1797 = - source_id__h33103 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1661 ; assign _dfoo1798 = - (source_id__h33103 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1730 ; assign _dfoo1799 = - source_id__h33103 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1663 ; assign _dfoo18 = - (source_id__h64563 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo180 = - (source_id__h62143 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo112 ; assign _dfoo1800 = - (source_id__h33103 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1732 ; assign _dfoo1801 = - source_id__h33103 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1665 ; assign _dfoo1802 = - (source_id__h33103 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1734 ; assign _dfoo1803 = - source_id__h33103 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1667 ; assign _dfoo1804 = - (source_id__h33103 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1736 ; assign _dfoo1805 = - source_id__h33103 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1669 ; assign _dfoo1806 = - (source_id__h33103 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1738 ; assign _dfoo1807 = - source_id__h33103 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1671 ; assign _dfoo1808 = - (source_id__h33103 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1740 ; assign _dfoo1809 = - source_id__h33103 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1673 ; assign _dfoo181 = - source_id__h62143 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo45 ; assign _dfoo1810 = - (source_id__h33103 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1742 ; assign _dfoo1811 = - source_id__h33103 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1675 ; assign _dfoo1812 = - (source_id__h33103 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1744 ; assign _dfoo1813 = - source_id__h33103 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1677 ; assign _dfoo1814 = - (source_id__h33103 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1746 ; assign _dfoo1815 = - source_id__h33103 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1679 ; assign _dfoo1816 = - (source_id__h33103 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1748 ; assign _dfoo1817 = - source_id__h33103 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1681 ; assign _dfoo1818 = - (source_id__h33103 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1750 ; assign _dfoo1819 = - source_id__h33103 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1683 ; assign _dfoo182 = - (source_id__h62143 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo114 ; assign _dfoo1820 = - (source_id__h33103 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1752 ; assign _dfoo1821 = - source_id__h33103 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1685 ; assign _dfoo1822 = - (source_id__h33103 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1754 ; assign _dfoo1823 = - source_id__h33103 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1687 ; assign _dfoo1824 = - (source_id__h33103 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1756 ; assign _dfoo1825 = - source_id__h33103 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1689 ; assign _dfoo1826 = - (source_id__h33103 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1758 ; assign _dfoo1827 = - source_id__h33103 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1691 ; assign _dfoo1828 = - (source_id__h33103 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1760 ; assign _dfoo1829 = - source_id__h33103 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1693 ; assign _dfoo183 = - source_id__h62143 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo47 ; assign _dfoo1830 = - (source_id__h33103 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1762 ; assign _dfoo1831 = - source_id__h33103 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1695 ; assign _dfoo1832 = - (source_id__h33103 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1764 ; assign _dfoo1833 = - source_id__h33103 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1697 ; assign _dfoo1834 = - (source_id__h33103 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1766 ; assign _dfoo1835 = - source_id__h33103 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34313 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || + source_id__h33094 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || + source_id__h34304 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || _dfoo1699 ; assign _dfoo1836 = - (source_id__h33103 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26928[4] : + (source_id__h33094 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? + wdata32__h26921[4] : _dfoo1768 ; assign _dfoo1838 = - (source_id__h31893 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1770 ; assign _dfoo184 = - (source_id__h62143 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo116 ; assign _dfoo1840 = - (source_id__h31893 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1772 ; assign _dfoo1842 = - (source_id__h31893 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1774 ; assign _dfoo1844 = - (source_id__h31893 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1776 ; assign _dfoo1846 = - (source_id__h31893 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1778 ; assign _dfoo1848 = - (source_id__h31893 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1780 ; assign _dfoo185 = - source_id__h62143 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo49 ; assign _dfoo1850 = - (source_id__h31893 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1782 ; assign _dfoo1852 = - (source_id__h31893 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1784 ; assign _dfoo1854 = - (source_id__h31893 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1786 ; assign _dfoo1856 = - (source_id__h31893 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1788 ; assign _dfoo1858 = - (source_id__h31893 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1790 ; assign _dfoo186 = - (source_id__h62143 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo118 ; assign _dfoo1860 = - (source_id__h31893 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1792 ; assign _dfoo1862 = - (source_id__h31893 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1794 ; assign _dfoo1864 = - (source_id__h31893 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1796 ; assign _dfoo1866 = - (source_id__h31893 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1798 ; assign _dfoo1868 = - (source_id__h31893 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1800 ; assign _dfoo187 = - source_id__h62143 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo51 ; assign _dfoo1870 = - (source_id__h31893 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1802 ; assign _dfoo1872 = - (source_id__h31893 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1804 ; assign _dfoo1874 = - (source_id__h31893 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1806 ; assign _dfoo1876 = - (source_id__h31893 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1808 ; assign _dfoo1878 = - (source_id__h31893 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1810 ; assign _dfoo188 = - (source_id__h62143 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo120 ; assign _dfoo1880 = - (source_id__h31893 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1812 ; assign _dfoo1882 = - (source_id__h31893 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1814 ; assign _dfoo1884 = - (source_id__h31893 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1816 ; assign _dfoo1886 = - (source_id__h31893 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1818 ; assign _dfoo1888 = - (source_id__h31893 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1820 ; assign _dfoo189 = - source_id__h62143 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo53 ; assign _dfoo1890 = - (source_id__h31893 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1822 ; assign _dfoo1892 = - (source_id__h31893 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1824 ; assign _dfoo1894 = - (source_id__h31893 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1826 ; assign _dfoo1896 = - (source_id__h31893 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1828 ; assign _dfoo1898 = - (source_id__h31893 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1830 ; assign _dfoo19 = - source_id__h64563 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo190 = - (source_id__h62143 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo122 ; assign _dfoo1900 = - (source_id__h31893 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1832 ; assign _dfoo1902 = - (source_id__h31893 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1834 ; assign _dfoo1904 = - (source_id__h31893 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26928[3] : + (source_id__h31884 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? + wdata32__h26921[3] : _dfoo1836 ; assign _dfoo1905 = - source_id__h30683 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1769 ; assign _dfoo1906 = - (source_id__h30683 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1838 ; assign _dfoo1907 = - source_id__h30683 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1771 ; assign _dfoo1908 = - (source_id__h30683 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1840 ; assign _dfoo1909 = - source_id__h30683 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1773 ; assign _dfoo191 = - source_id__h62143 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo55 ; assign _dfoo1910 = - (source_id__h30683 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1842 ; assign _dfoo1911 = - source_id__h30683 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1775 ; assign _dfoo1912 = - (source_id__h30683 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1844 ; assign _dfoo1913 = - source_id__h30683 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1777 ; assign _dfoo1914 = - (source_id__h30683 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1846 ; assign _dfoo1915 = - source_id__h30683 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1779 ; assign _dfoo1916 = - (source_id__h30683 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1848 ; assign _dfoo1917 = - source_id__h30683 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1781 ; assign _dfoo1918 = - (source_id__h30683 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1850 ; assign _dfoo1919 = - source_id__h30683 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1783 ; assign _dfoo192 = - (source_id__h62143 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo124 ; assign _dfoo1920 = - (source_id__h30683 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1852 ; assign _dfoo1921 = - source_id__h30683 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1785 ; assign _dfoo1922 = - (source_id__h30683 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1854 ; assign _dfoo1923 = - source_id__h30683 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1787 ; assign _dfoo1924 = - (source_id__h30683 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1856 ; assign _dfoo1925 = - source_id__h30683 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1789 ; assign _dfoo1926 = - (source_id__h30683 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1858 ; assign _dfoo1927 = - source_id__h30683 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1791 ; assign _dfoo1928 = - (source_id__h30683 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1860 ; assign _dfoo1929 = - source_id__h30683 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1793 ; assign _dfoo193 = - source_id__h62143 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo57 ; assign _dfoo1930 = - (source_id__h30683 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1862 ; assign _dfoo1931 = - source_id__h30683 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1795 ; assign _dfoo1932 = - (source_id__h30683 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1864 ; assign _dfoo1933 = - source_id__h30683 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1797 ; assign _dfoo1934 = - (source_id__h30683 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1866 ; assign _dfoo1935 = - source_id__h30683 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1799 ; assign _dfoo1936 = - (source_id__h30683 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1868 ; assign _dfoo1937 = - source_id__h30683 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1801 ; assign _dfoo1938 = - (source_id__h30683 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1870 ; assign _dfoo1939 = - source_id__h30683 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1803 ; assign _dfoo194 = - (source_id__h62143 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo126 ; assign _dfoo1940 = - (source_id__h30683 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1872 ; assign _dfoo1941 = - source_id__h30683 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1805 ; assign _dfoo1942 = - (source_id__h30683 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1874 ; assign _dfoo1943 = - source_id__h30683 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1807 ; assign _dfoo1944 = - (source_id__h30683 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1876 ; assign _dfoo1945 = - source_id__h30683 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1809 ; assign _dfoo1946 = - (source_id__h30683 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1878 ; assign _dfoo1947 = - source_id__h30683 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1811 ; assign _dfoo1948 = - (source_id__h30683 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1880 ; assign _dfoo1949 = - source_id__h30683 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1813 ; assign _dfoo195 = - source_id__h62143 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo59 ; assign _dfoo1950 = - (source_id__h30683 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1882 ; assign _dfoo1951 = - source_id__h30683 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1815 ; assign _dfoo1952 = - (source_id__h30683 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1884 ; assign _dfoo1953 = - source_id__h30683 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1817 ; assign _dfoo1954 = - (source_id__h30683 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1886 ; assign _dfoo1955 = - source_id__h30683 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1819 ; assign _dfoo1956 = - (source_id__h30683 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1888 ; assign _dfoo1957 = - source_id__h30683 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1821 ; assign _dfoo1958 = - (source_id__h30683 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1890 ; assign _dfoo1959 = - source_id__h30683 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1823 ; assign _dfoo196 = - (source_id__h62143 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo128 ; assign _dfoo1960 = - (source_id__h30683 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1892 ; assign _dfoo1961 = - source_id__h30683 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1825 ; assign _dfoo1962 = - (source_id__h30683 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1894 ; assign _dfoo1963 = - source_id__h30683 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1827 ; assign _dfoo1964 = - (source_id__h30683 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1896 ; assign _dfoo1965 = - source_id__h30683 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1829 ; assign _dfoo1966 = - (source_id__h30683 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1898 ; assign _dfoo1967 = - source_id__h30683 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1831 ; assign _dfoo1968 = - (source_id__h30683 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1900 ; assign _dfoo1969 = - source_id__h30683 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1833 ; assign _dfoo197 = - source_id__h62143 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo61 ; assign _dfoo1970 = - (source_id__h30683 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1902 ; assign _dfoo1971 = - source_id__h30683 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31893 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || + source_id__h30674 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || + source_id__h31884 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || _dfoo1835 ; assign _dfoo1972 = - (source_id__h30683 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26928[2] : + (source_id__h30674 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? + wdata32__h26921[2] : _dfoo1904 ; assign _dfoo1974 = - (source_id__h29473 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1906 ; assign _dfoo1976 = - (source_id__h29473 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1908 ; assign _dfoo1978 = - (source_id__h29473 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1910 ; assign _dfoo198 = - (source_id__h62143 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo130 ; assign _dfoo1980 = - (source_id__h29473 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1912 ; assign _dfoo1982 = - (source_id__h29473 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1914 ; assign _dfoo1984 = - (source_id__h29473 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1916 ; assign _dfoo1986 = - (source_id__h29473 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1918 ; assign _dfoo1988 = - (source_id__h29473 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1920 ; assign _dfoo199 = - source_id__h62143 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo63 ; assign _dfoo1990 = - (source_id__h29473 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1922 ; assign _dfoo1992 = - (source_id__h29473 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1924 ; assign _dfoo1994 = - (source_id__h29473 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1926 ; assign _dfoo1996 = - (source_id__h29473 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1928 ; assign _dfoo1998 = - (source_id__h29473 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1930 ; assign _dfoo2 = - (source_id__h64563 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo20 = - (source_id__h64563 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo200 = - (source_id__h62143 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo132 ; assign _dfoo2000 = - (source_id__h29473 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1932 ; assign _dfoo2002 = - (source_id__h29473 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1934 ; assign _dfoo2004 = - (source_id__h29473 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1936 ; assign _dfoo2006 = - (source_id__h29473 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1938 ; assign _dfoo2008 = - (source_id__h29473 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1940 ; assign _dfoo201 = - source_id__h62143 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo65 ; assign _dfoo2010 = - (source_id__h29473 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1942 ; assign _dfoo2012 = - (source_id__h29473 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1944 ; assign _dfoo2014 = - (source_id__h29473 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1946 ; assign _dfoo2016 = - (source_id__h29473 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1948 ; assign _dfoo2018 = - (source_id__h29473 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1950 ; assign _dfoo202 = - (source_id__h62143 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo134 ; assign _dfoo2020 = - (source_id__h29473 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1952 ; assign _dfoo2022 = - (source_id__h29473 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1954 ; assign _dfoo2024 = - (source_id__h29473 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1956 ; assign _dfoo2026 = - (source_id__h29473 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1958 ; assign _dfoo2028 = - (source_id__h29473 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1960 ; assign _dfoo203 = - source_id__h62143 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63353 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || + source_id__h62134 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || + source_id__h63344 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || _dfoo67 ; assign _dfoo2030 = - (source_id__h29473 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1962 ; assign _dfoo2032 = - (source_id__h29473 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1964 ; assign _dfoo2034 = - (source_id__h29473 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1966 ; assign _dfoo2036 = - (source_id__h29473 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1968 ; assign _dfoo2038 = - (source_id__h29473 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1970 ; assign _dfoo204 = - (source_id__h62143 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26928[28] : + (source_id__h62134 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? + wdata32__h26921[28] : _dfoo136 ; assign _dfoo2040 = - (source_id__h29473 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26928[1] : + (source_id__h29464 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? + wdata32__h26921[1] : _dfoo1972 ; assign _dfoo2041 = - source_id_base__h28146 == 10'd16 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29473 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd16 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || + source_id__h29464 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1905 ; assign _dfoo2043 = - source_id_base__h28146 == 10'd15 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29473 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd15 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || + source_id__h29464 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1907 ; assign _dfoo2045 = - source_id_base__h28146 == 10'd14 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29473 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd14 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || + source_id__h29464 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1909 ; assign _dfoo2047 = - source_id_base__h28146 == 10'd13 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29473 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd13 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || + source_id__h29464 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1911 ; assign _dfoo2049 = - source_id_base__h28146 == 10'd12 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29473 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd12 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || + source_id__h29464 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1913 ; assign _dfoo2051 = - source_id_base__h28146 == 10'd11 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29473 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd11 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || + source_id__h29464 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1915 ; assign _dfoo2053 = - source_id_base__h28146 == 10'd10 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29473 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd10 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || + source_id__h29464 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1917 ; assign _dfoo2055 = - source_id_base__h28146 == 10'd9 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29473 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd9 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || + source_id__h29464 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1919 ; assign _dfoo2057 = - source_id_base__h28146 == 10'd8 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29473 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd8 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || + source_id__h29464 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1921 ; assign _dfoo2059 = - source_id_base__h28146 == 10'd7 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29473 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd7 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || + source_id__h29464 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1923 ; assign _dfoo206 = - (source_id__h60933 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo138 ; assign _dfoo2061 = - source_id_base__h28146 == 10'd6 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29473 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd6 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || + source_id__h29464 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1925 ; assign _dfoo2063 = - source_id_base__h28146 == 10'd5 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29473 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd5 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || + source_id__h29464 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1927 ; assign _dfoo2065 = - source_id_base__h28146 == 10'd4 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29473 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd4 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || + source_id__h29464 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1929 ; assign _dfoo2067 = - source_id_base__h28146 == 10'd3 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29473 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd3 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || + source_id__h29464 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1931 ; assign _dfoo2069 = - source_id_base__h28146 == 10'd2 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29473 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd2 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || + source_id__h29464 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1933 ; assign _dfoo2071 = - source_id_base__h28146 == 10'd1 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29473 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd1 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || + source_id__h29464 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1935 ; assign _dfoo2073 = - source_id_base__h28146 == 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29473 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd0 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || + source_id__h29464 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1937 ; assign _dfoo2075 = - source_id_base__h28146 == 10'd16 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29473 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd16 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || + source_id__h29464 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1939 ; assign _dfoo2077 = - source_id_base__h28146 == 10'd15 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29473 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd15 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || + source_id__h29464 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1941 ; assign _dfoo2079 = - source_id_base__h28146 == 10'd14 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29473 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd14 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || + source_id__h29464 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1943 ; assign _dfoo208 = - (source_id__h60933 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo140 ; assign _dfoo2081 = - source_id_base__h28146 == 10'd13 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29473 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd13 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || + source_id__h29464 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1945 ; assign _dfoo2083 = - source_id_base__h28146 == 10'd12 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29473 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd12 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || + source_id__h29464 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1947 ; assign _dfoo2085 = - source_id_base__h28146 == 10'd11 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29473 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd11 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || + source_id__h29464 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1949 ; assign _dfoo2087 = - source_id_base__h28146 == 10'd10 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29473 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd10 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || + source_id__h29464 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1951 ; assign _dfoo2089 = - source_id_base__h28146 == 10'd9 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29473 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd9 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || + source_id__h29464 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1953 ; assign _dfoo2091 = - source_id_base__h28146 == 10'd8 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29473 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd8 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || + source_id__h29464 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1955 ; assign _dfoo2093 = - source_id_base__h28146 == 10'd7 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29473 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd7 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || + source_id__h29464 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1957 ; assign _dfoo2095 = - source_id_base__h28146 == 10'd6 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29473 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd6 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || + source_id__h29464 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1959 ; assign _dfoo2097 = - source_id_base__h28146 == 10'd5 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29473 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd5 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || + source_id__h29464 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1961 ; assign _dfoo2099 = - source_id_base__h28146 == 10'd4 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29473 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd4 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || + source_id__h29464 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1963 ; assign _dfoo21 = - source_id__h64563 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo210 = - (source_id__h60933 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo142 ; assign _dfoo2101 = - source_id_base__h28146 == 10'd3 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29473 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd3 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || + source_id__h29464 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1965 ; assign _dfoo2103 = - source_id_base__h28146 == 10'd2 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29473 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd2 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || + source_id__h29464 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1967 ; assign _dfoo2105 = - source_id_base__h28146 == 10'd1 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29473 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd1 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || + source_id__h29464 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1969 ; assign _dfoo2107 = - source_id_base__h28146 == 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29473 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || + source_id_base__h28137 == 10'd0 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || + source_id__h29464 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || _dfoo1971 ; assign _dfoo212 = - (source_id__h60933 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo144 ; assign _dfoo214 = - (source_id__h60933 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo146 ; assign _dfoo216 = - (source_id__h60933 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo148 ; assign _dfoo218 = - (source_id__h60933 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo150 ; assign _dfoo22 = - (source_id__h64563 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo220 = - (source_id__h60933 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo152 ; assign _dfoo222 = - (source_id__h60933 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo154 ; assign _dfoo224 = - (source_id__h60933 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo156 ; assign _dfoo226 = - (source_id__h60933 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo158 ; assign _dfoo228 = - (source_id__h60933 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo160 ; assign _dfoo23 = - source_id__h64563 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo230 = - (source_id__h60933 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo162 ; assign _dfoo232 = - (source_id__h60933 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo164 ; assign _dfoo234 = - (source_id__h60933 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo166 ; assign _dfoo236 = - (source_id__h60933 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo168 ; assign _dfoo238 = - (source_id__h60933 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo170 ; assign _dfoo24 = - (source_id__h64563 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo240 = - (source_id__h60933 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo172 ; assign _dfoo242 = - (source_id__h60933 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo174 ; assign _dfoo244 = - (source_id__h60933 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo176 ; assign _dfoo246 = - (source_id__h60933 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo178 ; assign _dfoo248 = - (source_id__h60933 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo180 ; assign _dfoo25 = - source_id__h64563 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo250 = - (source_id__h60933 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo182 ; assign _dfoo252 = - (source_id__h60933 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo184 ; assign _dfoo254 = - (source_id__h60933 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo186 ; assign _dfoo256 = - (source_id__h60933 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo188 ; assign _dfoo258 = - (source_id__h60933 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo190 ; assign _dfoo26 = - (source_id__h64563 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo260 = - (source_id__h60933 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo192 ; assign _dfoo262 = - (source_id__h60933 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo194 ; assign _dfoo264 = - (source_id__h60933 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo196 ; assign _dfoo266 = - (source_id__h60933 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo198 ; assign _dfoo268 = - (source_id__h60933 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo200 ; assign _dfoo27 = - source_id__h64563 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo270 = - (source_id__h60933 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo202 ; assign _dfoo272 = - (source_id__h60933 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26928[27] : + (source_id__h60924 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? + wdata32__h26921[27] : _dfoo204 ; assign _dfoo273 = - source_id__h59723 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo137 ; assign _dfoo274 = - (source_id__h59723 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo206 ; assign _dfoo275 = - source_id__h59723 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo139 ; assign _dfoo276 = - (source_id__h59723 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo208 ; assign _dfoo277 = - source_id__h59723 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo141 ; assign _dfoo278 = - (source_id__h59723 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo210 ; assign _dfoo279 = - source_id__h59723 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo143 ; assign _dfoo28 = - (source_id__h64563 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo280 = - (source_id__h59723 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo212 ; assign _dfoo281 = - source_id__h59723 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo145 ; assign _dfoo282 = - (source_id__h59723 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo214 ; assign _dfoo283 = - source_id__h59723 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo147 ; assign _dfoo284 = - (source_id__h59723 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo216 ; assign _dfoo285 = - source_id__h59723 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo149 ; assign _dfoo286 = - (source_id__h59723 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo218 ; assign _dfoo287 = - source_id__h59723 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo151 ; assign _dfoo288 = - (source_id__h59723 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo220 ; assign _dfoo289 = - source_id__h59723 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo153 ; assign _dfoo29 = - source_id__h64563 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo290 = - (source_id__h59723 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo222 ; assign _dfoo291 = - source_id__h59723 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo155 ; assign _dfoo292 = - (source_id__h59723 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo224 ; assign _dfoo293 = - source_id__h59723 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo157 ; assign _dfoo294 = - (source_id__h59723 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo226 ; assign _dfoo295 = - source_id__h59723 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo159 ; assign _dfoo296 = - (source_id__h59723 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo228 ; assign _dfoo297 = - source_id__h59723 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo161 ; assign _dfoo298 = - (source_id__h59723 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo230 ; assign _dfoo299 = - source_id__h59723 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo163 ; assign _dfoo3 = - source_id__h64563 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo30 = - (source_id__h64563 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo300 = - (source_id__h59723 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo232 ; assign _dfoo301 = - source_id__h59723 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo165 ; assign _dfoo302 = - (source_id__h59723 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo234 ; assign _dfoo303 = - source_id__h59723 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo167 ; assign _dfoo304 = - (source_id__h59723 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo236 ; assign _dfoo305 = - source_id__h59723 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo169 ; assign _dfoo306 = - (source_id__h59723 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo238 ; assign _dfoo307 = - source_id__h59723 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo171 ; assign _dfoo308 = - (source_id__h59723 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo240 ; assign _dfoo309 = - source_id__h59723 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo173 ; assign _dfoo31 = - source_id__h64563 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo310 = - (source_id__h59723 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo242 ; assign _dfoo311 = - source_id__h59723 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo175 ; assign _dfoo312 = - (source_id__h59723 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo244 ; assign _dfoo313 = - source_id__h59723 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo177 ; assign _dfoo314 = - (source_id__h59723 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo246 ; assign _dfoo315 = - source_id__h59723 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo179 ; assign _dfoo316 = - (source_id__h59723 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo248 ; assign _dfoo317 = - source_id__h59723 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo181 ; assign _dfoo318 = - (source_id__h59723 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo250 ; assign _dfoo319 = - source_id__h59723 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo183 ; assign _dfoo32 = - (source_id__h64563 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo320 = - (source_id__h59723 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo252 ; assign _dfoo321 = - source_id__h59723 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo185 ; assign _dfoo322 = - (source_id__h59723 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo254 ; assign _dfoo323 = - source_id__h59723 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo187 ; assign _dfoo324 = - (source_id__h59723 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo256 ; assign _dfoo325 = - source_id__h59723 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo189 ; assign _dfoo326 = - (source_id__h59723 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo258 ; assign _dfoo327 = - source_id__h59723 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo191 ; assign _dfoo328 = - (source_id__h59723 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo260 ; assign _dfoo329 = - source_id__h59723 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo193 ; assign _dfoo33 = - source_id__h64563 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo330 = - (source_id__h59723 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo262 ; assign _dfoo331 = - source_id__h59723 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo195 ; assign _dfoo332 = - (source_id__h59723 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo264 ; assign _dfoo333 = - source_id__h59723 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo197 ; assign _dfoo334 = - (source_id__h59723 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo266 ; assign _dfoo335 = - source_id__h59723 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo199 ; assign _dfoo336 = - (source_id__h59723 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo268 ; assign _dfoo337 = - source_id__h59723 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo201 ; assign _dfoo338 = - (source_id__h59723 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo270 ; assign _dfoo339 = - source_id__h59723 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60933 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || + source_id__h59714 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || + source_id__h60924 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || _dfoo203 ; assign _dfoo34 = - (source_id__h64563 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo340 = - (source_id__h59723 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26928[26] : + (source_id__h59714 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? + wdata32__h26921[26] : _dfoo272 ; assign _dfoo342 = - (source_id__h58513 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo274 ; assign _dfoo344 = - (source_id__h58513 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo276 ; assign _dfoo346 = - (source_id__h58513 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo278 ; assign _dfoo348 = - (source_id__h58513 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo280 ; assign _dfoo35 = - source_id__h64563 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo350 = - (source_id__h58513 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo282 ; assign _dfoo352 = - (source_id__h58513 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo284 ; assign _dfoo354 = - (source_id__h58513 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo286 ; assign _dfoo356 = - (source_id__h58513 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo288 ; assign _dfoo358 = - (source_id__h58513 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo290 ; assign _dfoo36 = - (source_id__h64563 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo360 = - (source_id__h58513 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo292 ; assign _dfoo362 = - (source_id__h58513 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo294 ; assign _dfoo364 = - (source_id__h58513 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo296 ; assign _dfoo366 = - (source_id__h58513 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo298 ; assign _dfoo368 = - (source_id__h58513 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo300 ; assign _dfoo37 = - source_id__h64563 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo370 = - (source_id__h58513 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo302 ; assign _dfoo372 = - (source_id__h58513 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo304 ; assign _dfoo374 = - (source_id__h58513 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo306 ; assign _dfoo376 = - (source_id__h58513 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo308 ; assign _dfoo378 = - (source_id__h58513 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo310 ; assign _dfoo38 = - (source_id__h64563 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo380 = - (source_id__h58513 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo312 ; assign _dfoo382 = - (source_id__h58513 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo314 ; assign _dfoo384 = - (source_id__h58513 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo316 ; assign _dfoo386 = - (source_id__h58513 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo318 ; assign _dfoo388 = - (source_id__h58513 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo320 ; assign _dfoo39 = - source_id__h64563 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo390 = - (source_id__h58513 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo322 ; assign _dfoo392 = - (source_id__h58513 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo324 ; assign _dfoo394 = - (source_id__h58513 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo326 ; assign _dfoo396 = - (source_id__h58513 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo328 ; assign _dfoo398 = - (source_id__h58513 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo330 ; assign _dfoo4 = - (source_id__h64563 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo40 = - (source_id__h64563 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo400 = - (source_id__h58513 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo332 ; assign _dfoo402 = - (source_id__h58513 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo334 ; assign _dfoo404 = - (source_id__h58513 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo336 ; assign _dfoo406 = - (source_id__h58513 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo338 ; assign _dfoo408 = - (source_id__h58513 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26928[25] : + (source_id__h58504 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? + wdata32__h26921[25] : _dfoo340 ; assign _dfoo409 = - source_id__h57303 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo273 ; assign _dfoo41 = - source_id__h64563 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo410 = - (source_id__h57303 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo342 ; assign _dfoo411 = - source_id__h57303 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo275 ; assign _dfoo412 = - (source_id__h57303 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo344 ; assign _dfoo413 = - source_id__h57303 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo277 ; assign _dfoo414 = - (source_id__h57303 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo346 ; assign _dfoo415 = - source_id__h57303 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo279 ; assign _dfoo416 = - (source_id__h57303 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo348 ; assign _dfoo417 = - source_id__h57303 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo281 ; assign _dfoo418 = - (source_id__h57303 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo350 ; assign _dfoo419 = - source_id__h57303 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo283 ; assign _dfoo42 = - (source_id__h64563 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo420 = - (source_id__h57303 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo352 ; assign _dfoo421 = - source_id__h57303 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo285 ; assign _dfoo422 = - (source_id__h57303 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo354 ; assign _dfoo423 = - source_id__h57303 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo287 ; assign _dfoo424 = - (source_id__h57303 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo356 ; assign _dfoo425 = - source_id__h57303 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo289 ; assign _dfoo426 = - (source_id__h57303 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo358 ; assign _dfoo427 = - source_id__h57303 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo291 ; assign _dfoo428 = - (source_id__h57303 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo360 ; assign _dfoo429 = - source_id__h57303 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo293 ; assign _dfoo43 = - source_id__h64563 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo430 = - (source_id__h57303 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo362 ; assign _dfoo431 = - source_id__h57303 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo295 ; assign _dfoo432 = - (source_id__h57303 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo364 ; assign _dfoo433 = - source_id__h57303 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo297 ; assign _dfoo434 = - (source_id__h57303 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo366 ; assign _dfoo435 = - source_id__h57303 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo299 ; assign _dfoo436 = - (source_id__h57303 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo368 ; assign _dfoo437 = - source_id__h57303 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo301 ; assign _dfoo438 = - (source_id__h57303 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo370 ; assign _dfoo439 = - source_id__h57303 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo303 ; assign _dfoo44 = - (source_id__h64563 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo440 = - (source_id__h57303 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo372 ; assign _dfoo441 = - source_id__h57303 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo305 ; assign _dfoo442 = - (source_id__h57303 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo374 ; assign _dfoo443 = - source_id__h57303 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo307 ; assign _dfoo444 = - (source_id__h57303 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo376 ; assign _dfoo445 = - source_id__h57303 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo309 ; assign _dfoo446 = - (source_id__h57303 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo378 ; assign _dfoo447 = - source_id__h57303 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo311 ; assign _dfoo448 = - (source_id__h57303 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo380 ; assign _dfoo449 = - source_id__h57303 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo313 ; assign _dfoo45 = - source_id__h64563 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo450 = - (source_id__h57303 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo382 ; assign _dfoo451 = - source_id__h57303 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo315 ; assign _dfoo452 = - (source_id__h57303 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo384 ; assign _dfoo453 = - source_id__h57303 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo317 ; assign _dfoo454 = - (source_id__h57303 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo386 ; assign _dfoo455 = - source_id__h57303 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo319 ; assign _dfoo456 = - (source_id__h57303 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo388 ; assign _dfoo457 = - source_id__h57303 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo321 ; assign _dfoo458 = - (source_id__h57303 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo390 ; assign _dfoo459 = - source_id__h57303 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo323 ; assign _dfoo46 = - (source_id__h64563 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo460 = - (source_id__h57303 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo392 ; assign _dfoo461 = - source_id__h57303 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo325 ; assign _dfoo462 = - (source_id__h57303 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo394 ; assign _dfoo463 = - source_id__h57303 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo327 ; assign _dfoo464 = - (source_id__h57303 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo396 ; assign _dfoo465 = - source_id__h57303 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo329 ; assign _dfoo466 = - (source_id__h57303 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo398 ; assign _dfoo467 = - source_id__h57303 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo331 ; assign _dfoo468 = - (source_id__h57303 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo400 ; assign _dfoo469 = - source_id__h57303 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo333 ; assign _dfoo47 = - source_id__h64563 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo470 = - (source_id__h57303 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo402 ; assign _dfoo471 = - source_id__h57303 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo335 ; assign _dfoo472 = - (source_id__h57303 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo404 ; assign _dfoo473 = - source_id__h57303 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo337 ; assign _dfoo474 = - (source_id__h57303 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo406 ; assign _dfoo475 = - source_id__h57303 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58513 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || + source_id__h57294 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || + source_id__h58504 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || _dfoo339 ; assign _dfoo476 = - (source_id__h57303 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26928[24] : + (source_id__h57294 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? + wdata32__h26921[24] : _dfoo408 ; assign _dfoo478 = - (source_id__h56093 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo410 ; assign _dfoo48 = - (source_id__h64563 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo480 = - (source_id__h56093 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo412 ; assign _dfoo482 = - (source_id__h56093 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo414 ; assign _dfoo484 = - (source_id__h56093 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo416 ; assign _dfoo486 = - (source_id__h56093 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo418 ; assign _dfoo488 = - (source_id__h56093 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo420 ; assign _dfoo49 = - source_id__h64563 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo490 = - (source_id__h56093 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo422 ; assign _dfoo492 = - (source_id__h56093 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo424 ; assign _dfoo494 = - (source_id__h56093 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo426 ; assign _dfoo496 = - (source_id__h56093 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo428 ; assign _dfoo498 = - (source_id__h56093 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo430 ; assign _dfoo5 = - source_id__h64563 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo50 = - (source_id__h64563 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo500 = - (source_id__h56093 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo432 ; assign _dfoo502 = - (source_id__h56093 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo434 ; assign _dfoo504 = - (source_id__h56093 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo436 ; assign _dfoo506 = - (source_id__h56093 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo438 ; assign _dfoo508 = - (source_id__h56093 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo440 ; assign _dfoo51 = - source_id__h64563 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo510 = - (source_id__h56093 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo442 ; assign _dfoo512 = - (source_id__h56093 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo444 ; assign _dfoo514 = - (source_id__h56093 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo446 ; assign _dfoo516 = - (source_id__h56093 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo448 ; assign _dfoo518 = - (source_id__h56093 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo450 ; assign _dfoo52 = - (source_id__h64563 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo520 = - (source_id__h56093 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo452 ; assign _dfoo522 = - (source_id__h56093 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo454 ; assign _dfoo524 = - (source_id__h56093 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo456 ; assign _dfoo526 = - (source_id__h56093 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo458 ; assign _dfoo528 = - (source_id__h56093 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo460 ; assign _dfoo53 = - source_id__h64563 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo530 = - (source_id__h56093 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo462 ; assign _dfoo532 = - (source_id__h56093 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo464 ; assign _dfoo534 = - (source_id__h56093 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo466 ; assign _dfoo536 = - (source_id__h56093 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo468 ; assign _dfoo538 = - (source_id__h56093 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo470 ; assign _dfoo54 = - (source_id__h64563 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo540 = - (source_id__h56093 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo472 ; assign _dfoo542 = - (source_id__h56093 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo474 ; assign _dfoo544 = - (source_id__h56093 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26928[23] : + (source_id__h56084 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? + wdata32__h26921[23] : _dfoo476 ; assign _dfoo545 = - source_id__h54883 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo409 ; assign _dfoo546 = - (source_id__h54883 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo478 ; assign _dfoo547 = - source_id__h54883 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo411 ; assign _dfoo548 = - (source_id__h54883 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo480 ; assign _dfoo549 = - source_id__h54883 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo413 ; assign _dfoo55 = - source_id__h64563 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo550 = - (source_id__h54883 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo482 ; assign _dfoo551 = - source_id__h54883 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo415 ; assign _dfoo552 = - (source_id__h54883 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo484 ; assign _dfoo553 = - source_id__h54883 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo417 ; assign _dfoo554 = - (source_id__h54883 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo486 ; assign _dfoo555 = - source_id__h54883 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo419 ; assign _dfoo556 = - (source_id__h54883 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo488 ; assign _dfoo557 = - source_id__h54883 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo421 ; assign _dfoo558 = - (source_id__h54883 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo490 ; assign _dfoo559 = - source_id__h54883 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo423 ; assign _dfoo56 = - (source_id__h64563 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo560 = - (source_id__h54883 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo492 ; assign _dfoo561 = - source_id__h54883 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo425 ; assign _dfoo562 = - (source_id__h54883 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo494 ; assign _dfoo563 = - source_id__h54883 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo427 ; assign _dfoo564 = - (source_id__h54883 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo496 ; assign _dfoo565 = - source_id__h54883 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo429 ; assign _dfoo566 = - (source_id__h54883 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo498 ; assign _dfoo567 = - source_id__h54883 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo431 ; assign _dfoo568 = - (source_id__h54883 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo500 ; assign _dfoo569 = - source_id__h54883 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo433 ; assign _dfoo57 = - source_id__h64563 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo570 = - (source_id__h54883 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo502 ; assign _dfoo571 = - source_id__h54883 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo435 ; assign _dfoo572 = - (source_id__h54883 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo504 ; assign _dfoo573 = - source_id__h54883 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo437 ; assign _dfoo574 = - (source_id__h54883 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo506 ; assign _dfoo575 = - source_id__h54883 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo439 ; assign _dfoo576 = - (source_id__h54883 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo508 ; assign _dfoo577 = - source_id__h54883 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo441 ; assign _dfoo578 = - (source_id__h54883 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo510 ; assign _dfoo579 = - source_id__h54883 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo443 ; assign _dfoo58 = - (source_id__h64563 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo580 = - (source_id__h54883 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo512 ; assign _dfoo581 = - source_id__h54883 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo445 ; assign _dfoo582 = - (source_id__h54883 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo514 ; assign _dfoo583 = - source_id__h54883 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo447 ; assign _dfoo584 = - (source_id__h54883 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo516 ; assign _dfoo585 = - source_id__h54883 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo449 ; assign _dfoo586 = - (source_id__h54883 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo518 ; assign _dfoo587 = - source_id__h54883 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo451 ; assign _dfoo588 = - (source_id__h54883 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo520 ; assign _dfoo589 = - source_id__h54883 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo453 ; assign _dfoo59 = - source_id__h64563 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo590 = - (source_id__h54883 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo522 ; assign _dfoo591 = - source_id__h54883 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo455 ; assign _dfoo592 = - (source_id__h54883 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo524 ; assign _dfoo593 = - source_id__h54883 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo457 ; assign _dfoo594 = - (source_id__h54883 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo526 ; assign _dfoo595 = - source_id__h54883 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo459 ; assign _dfoo596 = - (source_id__h54883 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo528 ; assign _dfoo597 = - source_id__h54883 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo461 ; assign _dfoo598 = - (source_id__h54883 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo530 ; assign _dfoo599 = - source_id__h54883 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo463 ; assign _dfoo6 = - (source_id__h64563 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo60 = - (source_id__h64563 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo600 = - (source_id__h54883 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo532 ; assign _dfoo601 = - source_id__h54883 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo465 ; assign _dfoo602 = - (source_id__h54883 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo534 ; assign _dfoo603 = - source_id__h54883 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo467 ; assign _dfoo604 = - (source_id__h54883 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo536 ; assign _dfoo605 = - source_id__h54883 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo469 ; assign _dfoo606 = - (source_id__h54883 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo538 ; assign _dfoo607 = - source_id__h54883 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo471 ; assign _dfoo608 = - (source_id__h54883 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo540 ; assign _dfoo609 = - source_id__h54883 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo473 ; assign _dfoo61 = - source_id__h64563 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo610 = - (source_id__h54883 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo542 ; assign _dfoo611 = - source_id__h54883 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56093 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || + source_id__h54874 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || + source_id__h56084 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || _dfoo475 ; assign _dfoo612 = - (source_id__h54883 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26928[22] : + (source_id__h54874 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? + wdata32__h26921[22] : _dfoo544 ; assign _dfoo614 = - (source_id__h53673 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo546 ; assign _dfoo616 = - (source_id__h53673 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo548 ; assign _dfoo618 = - (source_id__h53673 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo550 ; assign _dfoo62 = - (source_id__h64563 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo620 = - (source_id__h53673 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo552 ; assign _dfoo622 = - (source_id__h53673 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo554 ; assign _dfoo624 = - (source_id__h53673 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo556 ; assign _dfoo626 = - (source_id__h53673 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo558 ; assign _dfoo628 = - (source_id__h53673 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo560 ; assign _dfoo63 = - source_id__h64563 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo630 = - (source_id__h53673 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo562 ; assign _dfoo632 = - (source_id__h53673 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo564 ; assign _dfoo634 = - (source_id__h53673 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo566 ; assign _dfoo636 = - (source_id__h53673 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo568 ; assign _dfoo638 = - (source_id__h53673 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo570 ; assign _dfoo64 = - (source_id__h64563 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo640 = - (source_id__h53673 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo572 ; assign _dfoo642 = - (source_id__h53673 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo574 ; assign _dfoo644 = - (source_id__h53673 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo576 ; assign _dfoo646 = - (source_id__h53673 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo578 ; assign _dfoo648 = - (source_id__h53673 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo580 ; assign _dfoo65 = - source_id__h64563 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo650 = - (source_id__h53673 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo582 ; assign _dfoo652 = - (source_id__h53673 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo584 ; assign _dfoo654 = - (source_id__h53673 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo586 ; assign _dfoo656 = - (source_id__h53673 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo588 ; assign _dfoo658 = - (source_id__h53673 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo590 ; assign _dfoo66 = - (source_id__h64563 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo660 = - (source_id__h53673 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo592 ; assign _dfoo662 = - (source_id__h53673 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo594 ; assign _dfoo664 = - (source_id__h53673 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo596 ; assign _dfoo666 = - (source_id__h53673 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo598 ; assign _dfoo668 = - (source_id__h53673 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo600 ; assign _dfoo67 = - source_id__h64563 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo670 = - (source_id__h53673 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo602 ; assign _dfoo672 = - (source_id__h53673 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo604 ; assign _dfoo674 = - (source_id__h53673 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo606 ; assign _dfoo676 = - (source_id__h53673 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo608 ; assign _dfoo678 = - (source_id__h53673 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo610 ; assign _dfoo68 = - (source_id__h64563 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo680 = - (source_id__h53673 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26928[21] : + (source_id__h53664 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? + wdata32__h26921[21] : _dfoo612 ; assign _dfoo681 = - source_id__h52463 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo545 ; assign _dfoo682 = - (source_id__h52463 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo614 ; assign _dfoo683 = - source_id__h52463 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo547 ; assign _dfoo684 = - (source_id__h52463 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo616 ; assign _dfoo685 = - source_id__h52463 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo549 ; assign _dfoo686 = - (source_id__h52463 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo618 ; assign _dfoo687 = - source_id__h52463 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo551 ; assign _dfoo688 = - (source_id__h52463 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo620 ; assign _dfoo689 = - source_id__h52463 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo553 ; assign _dfoo690 = - (source_id__h52463 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo622 ; assign _dfoo691 = - source_id__h52463 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo555 ; assign _dfoo692 = - (source_id__h52463 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo624 ; assign _dfoo693 = - source_id__h52463 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo557 ; assign _dfoo694 = - (source_id__h52463 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo626 ; assign _dfoo695 = - source_id__h52463 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo559 ; assign _dfoo696 = - (source_id__h52463 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo628 ; assign _dfoo697 = - source_id__h52463 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo561 ; assign _dfoo698 = - (source_id__h52463 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo630 ; assign _dfoo699 = - source_id__h52463 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo563 ; assign _dfoo7 = - source_id__h64563 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo70 = - (source_id__h63353 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo2 ; assign _dfoo700 = - (source_id__h52463 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo632 ; assign _dfoo701 = - source_id__h52463 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo565 ; assign _dfoo702 = - (source_id__h52463 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo634 ; assign _dfoo703 = - source_id__h52463 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo567 ; assign _dfoo704 = - (source_id__h52463 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo636 ; assign _dfoo705 = - source_id__h52463 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo569 ; assign _dfoo706 = - (source_id__h52463 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo638 ; assign _dfoo707 = - source_id__h52463 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo571 ; assign _dfoo708 = - (source_id__h52463 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo640 ; assign _dfoo709 = - source_id__h52463 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo573 ; assign _dfoo710 = - (source_id__h52463 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo642 ; assign _dfoo711 = - source_id__h52463 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo575 ; assign _dfoo712 = - (source_id__h52463 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo644 ; assign _dfoo713 = - source_id__h52463 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo577 ; assign _dfoo714 = - (source_id__h52463 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo646 ; assign _dfoo715 = - source_id__h52463 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo579 ; assign _dfoo716 = - (source_id__h52463 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo648 ; assign _dfoo717 = - source_id__h52463 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo581 ; assign _dfoo718 = - (source_id__h52463 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo650 ; assign _dfoo719 = - source_id__h52463 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo583 ; assign _dfoo72 = - (source_id__h63353 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo4 ; assign _dfoo720 = - (source_id__h52463 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo652 ; assign _dfoo721 = - source_id__h52463 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo585 ; assign _dfoo722 = - (source_id__h52463 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo654 ; assign _dfoo723 = - source_id__h52463 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo587 ; assign _dfoo724 = - (source_id__h52463 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo656 ; assign _dfoo725 = - source_id__h52463 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo589 ; assign _dfoo726 = - (source_id__h52463 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo658 ; assign _dfoo727 = - source_id__h52463 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo591 ; assign _dfoo728 = - (source_id__h52463 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo660 ; assign _dfoo729 = - source_id__h52463 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo593 ; assign _dfoo730 = - (source_id__h52463 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo662 ; assign _dfoo731 = - source_id__h52463 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo595 ; assign _dfoo732 = - (source_id__h52463 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo664 ; assign _dfoo733 = - source_id__h52463 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo597 ; assign _dfoo734 = - (source_id__h52463 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo666 ; assign _dfoo735 = - source_id__h52463 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo599 ; assign _dfoo736 = - (source_id__h52463 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo668 ; assign _dfoo737 = - source_id__h52463 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo601 ; assign _dfoo738 = - (source_id__h52463 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo670 ; assign _dfoo739 = - source_id__h52463 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo603 ; assign _dfoo74 = - (source_id__h63353 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo6 ; assign _dfoo740 = - (source_id__h52463 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo672 ; assign _dfoo741 = - source_id__h52463 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo605 ; assign _dfoo742 = - (source_id__h52463 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo674 ; assign _dfoo743 = - source_id__h52463 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo607 ; assign _dfoo744 = - (source_id__h52463 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo676 ; assign _dfoo745 = - source_id__h52463 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo609 ; assign _dfoo746 = - (source_id__h52463 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo678 ; assign _dfoo747 = - source_id__h52463 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53673 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || + source_id__h52454 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || + source_id__h53664 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || _dfoo611 ; assign _dfoo748 = - (source_id__h52463 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26928[20] : + (source_id__h52454 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? + wdata32__h26921[20] : _dfoo680 ; assign _dfoo750 = - (source_id__h51253 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo682 ; assign _dfoo752 = - (source_id__h51253 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo684 ; assign _dfoo754 = - (source_id__h51253 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo686 ; assign _dfoo756 = - (source_id__h51253 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo688 ; assign _dfoo758 = - (source_id__h51253 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo690 ; assign _dfoo76 = - (source_id__h63353 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo8 ; assign _dfoo760 = - (source_id__h51253 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo692 ; assign _dfoo762 = - (source_id__h51253 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo694 ; assign _dfoo764 = - (source_id__h51253 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo696 ; assign _dfoo766 = - (source_id__h51253 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo698 ; assign _dfoo768 = - (source_id__h51253 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo700 ; assign _dfoo770 = - (source_id__h51253 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo702 ; assign _dfoo772 = - (source_id__h51253 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo704 ; assign _dfoo774 = - (source_id__h51253 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo706 ; assign _dfoo776 = - (source_id__h51253 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo708 ; assign _dfoo778 = - (source_id__h51253 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo710 ; assign _dfoo78 = - (source_id__h63353 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo10 ; assign _dfoo780 = - (source_id__h51253 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo712 ; assign _dfoo782 = - (source_id__h51253 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo714 ; assign _dfoo784 = - (source_id__h51253 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo716 ; assign _dfoo786 = - (source_id__h51253 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo718 ; assign _dfoo788 = - (source_id__h51253 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo720 ; assign _dfoo790 = - (source_id__h51253 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo722 ; assign _dfoo792 = - (source_id__h51253 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo724 ; assign _dfoo794 = - (source_id__h51253 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo726 ; assign _dfoo796 = - (source_id__h51253 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo728 ; assign _dfoo798 = - (source_id__h51253 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo730 ; assign _dfoo8 = - (source_id__h64563 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26928[30] : - wdata32__h26928[31] ; + (source_id__h64554 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? + wdata32__h26921[30] : + wdata32__h26921[31] ; assign _dfoo80 = - (source_id__h63353 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo12 ; assign _dfoo800 = - (source_id__h51253 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo732 ; assign _dfoo802 = - (source_id__h51253 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo734 ; assign _dfoo804 = - (source_id__h51253 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo736 ; assign _dfoo806 = - (source_id__h51253 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo738 ; assign _dfoo808 = - (source_id__h51253 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo740 ; assign _dfoo810 = - (source_id__h51253 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo742 ; assign _dfoo812 = - (source_id__h51253 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo744 ; assign _dfoo814 = - (source_id__h51253 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo746 ; assign _dfoo816 = - (source_id__h51253 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26928[19] : + (source_id__h51244 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? + wdata32__h26921[19] : _dfoo748 ; assign _dfoo817 = - source_id__h50043 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo681 ; assign _dfoo818 = - (source_id__h50043 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo750 ; assign _dfoo819 = - source_id__h50043 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo683 ; assign _dfoo82 = - (source_id__h63353 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo14 ; assign _dfoo820 = - (source_id__h50043 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo752 ; assign _dfoo821 = - source_id__h50043 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo685 ; assign _dfoo822 = - (source_id__h50043 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo754 ; assign _dfoo823 = - source_id__h50043 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo687 ; assign _dfoo824 = - (source_id__h50043 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo756 ; assign _dfoo825 = - source_id__h50043 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo689 ; assign _dfoo826 = - (source_id__h50043 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo758 ; assign _dfoo827 = - source_id__h50043 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo691 ; assign _dfoo828 = - (source_id__h50043 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo760 ; assign _dfoo829 = - source_id__h50043 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo693 ; assign _dfoo830 = - (source_id__h50043 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo762 ; assign _dfoo831 = - source_id__h50043 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo695 ; assign _dfoo832 = - (source_id__h50043 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo764 ; assign _dfoo833 = - source_id__h50043 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo697 ; assign _dfoo834 = - (source_id__h50043 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo766 ; assign _dfoo835 = - source_id__h50043 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo699 ; assign _dfoo836 = - (source_id__h50043 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo768 ; assign _dfoo837 = - source_id__h50043 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo701 ; assign _dfoo838 = - (source_id__h50043 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo770 ; assign _dfoo839 = - source_id__h50043 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo703 ; assign _dfoo84 = - (source_id__h63353 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo16 ; assign _dfoo840 = - (source_id__h50043 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo772 ; assign _dfoo841 = - source_id__h50043 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo705 ; assign _dfoo842 = - (source_id__h50043 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo774 ; assign _dfoo843 = - source_id__h50043 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo707 ; assign _dfoo844 = - (source_id__h50043 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo776 ; assign _dfoo845 = - source_id__h50043 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo709 ; assign _dfoo846 = - (source_id__h50043 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo778 ; assign _dfoo847 = - source_id__h50043 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo711 ; assign _dfoo848 = - (source_id__h50043 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo780 ; assign _dfoo849 = - source_id__h50043 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo713 ; assign _dfoo850 = - (source_id__h50043 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo782 ; assign _dfoo851 = - source_id__h50043 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo715 ; assign _dfoo852 = - (source_id__h50043 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo784 ; assign _dfoo853 = - source_id__h50043 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo717 ; assign _dfoo854 = - (source_id__h50043 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo786 ; assign _dfoo855 = - source_id__h50043 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo719 ; assign _dfoo856 = - (source_id__h50043 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo788 ; assign _dfoo857 = - source_id__h50043 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo721 ; assign _dfoo858 = - (source_id__h50043 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo790 ; assign _dfoo859 = - source_id__h50043 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo723 ; assign _dfoo86 = - (source_id__h63353 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo18 ; assign _dfoo860 = - (source_id__h50043 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo792 ; assign _dfoo861 = - source_id__h50043 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo725 ; assign _dfoo862 = - (source_id__h50043 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo794 ; assign _dfoo863 = - source_id__h50043 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo727 ; assign _dfoo864 = - (source_id__h50043 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo796 ; assign _dfoo865 = - source_id__h50043 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo729 ; assign _dfoo866 = - (source_id__h50043 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo798 ; assign _dfoo867 = - source_id__h50043 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo731 ; assign _dfoo868 = - (source_id__h50043 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo800 ; assign _dfoo869 = - source_id__h50043 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo733 ; assign _dfoo870 = - (source_id__h50043 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo802 ; assign _dfoo871 = - source_id__h50043 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo735 ; assign _dfoo872 = - (source_id__h50043 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo804 ; assign _dfoo873 = - source_id__h50043 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo737 ; assign _dfoo874 = - (source_id__h50043 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo806 ; assign _dfoo875 = - source_id__h50043 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo739 ; assign _dfoo876 = - (source_id__h50043 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo808 ; assign _dfoo877 = - source_id__h50043 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo741 ; assign _dfoo878 = - (source_id__h50043 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo810 ; assign _dfoo879 = - source_id__h50043 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo743 ; assign _dfoo88 = - (source_id__h63353 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo20 ; assign _dfoo880 = - (source_id__h50043 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo812 ; assign _dfoo881 = - source_id__h50043 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo745 ; assign _dfoo882 = - (source_id__h50043 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo814 ; assign _dfoo883 = - source_id__h50043 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51253 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || + source_id__h50034 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || + source_id__h51244 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || _dfoo747 ; assign _dfoo884 = - (source_id__h50043 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26928[18] : + (source_id__h50034 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? + wdata32__h26921[18] : _dfoo816 ; assign _dfoo886 = - (source_id__h48833 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo818 ; assign _dfoo888 = - (source_id__h48833 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo820 ; assign _dfoo890 = - (source_id__h48833 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo822 ; assign _dfoo892 = - (source_id__h48833 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo824 ; assign _dfoo894 = - (source_id__h48833 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo826 ; assign _dfoo896 = - (source_id__h48833 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo828 ; assign _dfoo898 = - (source_id__h48833 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo830 ; assign _dfoo9 = - source_id__h64563 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65773 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; + source_id__h64554 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || + source_id__h65764 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; assign _dfoo90 = - (source_id__h63353 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo22 ; assign _dfoo900 = - (source_id__h48833 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo832 ; assign _dfoo902 = - (source_id__h48833 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo834 ; assign _dfoo904 = - (source_id__h48833 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo836 ; assign _dfoo906 = - (source_id__h48833 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo838 ; assign _dfoo908 = - (source_id__h48833 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo840 ; assign _dfoo910 = - (source_id__h48833 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo842 ; assign _dfoo912 = - (source_id__h48833 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo844 ; assign _dfoo914 = - (source_id__h48833 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo846 ; assign _dfoo916 = - (source_id__h48833 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo848 ; assign _dfoo918 = - (source_id__h48833 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo850 ; assign _dfoo92 = - (source_id__h63353 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo24 ; assign _dfoo920 = - (source_id__h48833 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo852 ; assign _dfoo922 = - (source_id__h48833 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo854 ; assign _dfoo924 = - (source_id__h48833 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo856 ; assign _dfoo926 = - (source_id__h48833 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo858 ; assign _dfoo928 = - (source_id__h48833 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo860 ; assign _dfoo930 = - (source_id__h48833 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo862 ; assign _dfoo932 = - (source_id__h48833 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo864 ; assign _dfoo934 = - (source_id__h48833 == 10'd9 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd9 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo866 ; assign _dfoo936 = - (source_id__h48833 == 10'd8 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd8 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo868 ; assign _dfoo938 = - (source_id__h48833 == 10'd7 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd7 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo870 ; assign _dfoo94 = - (source_id__h63353 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo26 ; assign _dfoo940 = - (source_id__h48833 == 10'd6 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd6 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo872 ; assign _dfoo942 = - (source_id__h48833 == 10'd5 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd5 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo874 ; assign _dfoo944 = - (source_id__h48833 == 10'd4 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd4 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo876 ; assign _dfoo946 = - (source_id__h48833 == 10'd3 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd3 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo878 ; assign _dfoo948 = - (source_id__h48833 == 10'd2 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd2 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo880 ; assign _dfoo950 = - (source_id__h48833 == 10'd1 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd1 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo882 ; assign _dfoo952 = - (source_id__h48833 == 10'd0 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26928[17] : + (source_id__h48824 == 10'd0 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? + wdata32__h26921[17] : _dfoo884 ; assign _dfoo953 = - source_id__h47623 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo817 ; assign _dfoo954 = - (source_id__h47623 == 10'd16 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd16 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo886 ; assign _dfoo955 = - source_id__h47623 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo819 ; assign _dfoo956 = - (source_id__h47623 == 10'd15 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd15 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo888 ; assign _dfoo957 = - source_id__h47623 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo821 ; assign _dfoo958 = - (source_id__h47623 == 10'd14 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd14 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo890 ; assign _dfoo959 = - source_id__h47623 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo823 ; assign _dfoo96 = - (source_id__h63353 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo28 ; assign _dfoo960 = - (source_id__h47623 == 10'd13 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd13 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo892 ; assign _dfoo961 = - source_id__h47623 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo825 ; assign _dfoo962 = - (source_id__h47623 == 10'd12 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd12 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo894 ; assign _dfoo963 = - source_id__h47623 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo827 ; assign _dfoo964 = - (source_id__h47623 == 10'd11 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd11 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo896 ; assign _dfoo965 = - source_id__h47623 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo829 ; assign _dfoo966 = - (source_id__h47623 == 10'd10 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd10 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo898 ; assign _dfoo967 = - source_id__h47623 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo831 ; assign _dfoo968 = - (source_id__h47623 == 10'd9 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd9 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo900 ; assign _dfoo969 = - source_id__h47623 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo833 ; assign _dfoo970 = - (source_id__h47623 == 10'd8 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd8 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo902 ; assign _dfoo971 = - source_id__h47623 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo835 ; assign _dfoo972 = - (source_id__h47623 == 10'd7 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd7 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo904 ; assign _dfoo973 = - source_id__h47623 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo837 ; assign _dfoo974 = - (source_id__h47623 == 10'd6 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd6 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo906 ; assign _dfoo975 = - source_id__h47623 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo839 ; assign _dfoo976 = - (source_id__h47623 == 10'd5 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd5 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo908 ; assign _dfoo977 = - source_id__h47623 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo841 ; assign _dfoo978 = - (source_id__h47623 == 10'd4 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd4 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo910 ; assign _dfoo979 = - source_id__h47623 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo843 ; assign _dfoo98 = - (source_id__h63353 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26928[29] : + (source_id__h63344 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? + wdata32__h26921[29] : _dfoo30 ; assign _dfoo980 = - (source_id__h47623 == 10'd3 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd3 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo912 ; assign _dfoo981 = - source_id__h47623 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo845 ; assign _dfoo982 = - (source_id__h47623 == 10'd2 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd2 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo914 ; assign _dfoo983 = - source_id__h47623 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo847 ; assign _dfoo984 = - (source_id__h47623 == 10'd1 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd1 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo916 ; assign _dfoo985 = - source_id__h47623 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo849 ; assign _dfoo986 = - (source_id__h47623 == 10'd0 && - addr_offset__h26927[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd0 && + addr_offset__h26920[11:7] == 5'd1 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo918 ; assign _dfoo987 = - source_id__h47623 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo851 ; assign _dfoo988 = - (source_id__h47623 == 10'd16 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd16 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo920 ; assign _dfoo989 = - source_id__h47623 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo853 ; assign _dfoo990 = - (source_id__h47623 == 10'd15 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd15 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo922 ; assign _dfoo991 = - source_id__h47623 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo855 ; assign _dfoo992 = - (source_id__h47623 == 10'd14 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd14 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo924 ; assign _dfoo993 = - source_id__h47623 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo857 ; assign _dfoo994 = - (source_id__h47623 == 10'd13 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd13 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo926 ; assign _dfoo995 = - source_id__h47623 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo859 ; assign _dfoo996 = - (source_id__h47623 == 10'd12 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd12 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo928 ; assign _dfoo997 = - source_id__h47623 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo861 ; assign _dfoo998 = - (source_id__h47623 == 10'd11 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26928[16] : + (source_id__h47614 == 10'd11 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? + wdata32__h26921[16] : _dfoo930 ; assign _dfoo999 = - source_id__h47623 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48833 == 10'd10 && - addr_offset__h26927[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || + source_id__h47614 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || + source_id__h48824 == 10'd10 && + addr_offset__h26920[11:7] == 5'd0 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || _dfoo863 ; - assign a__h71310 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3090 ? + assign a__h71297 = + m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3089 ? m_vrg_source_prio_16 : - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3086 ; - assign a__h73315 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3184 ? + IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3085 ; + assign a__h73302 = + m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3183 ? m_vrg_source_prio_16 : - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3180 ; + IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3179 ; assign addr_offset__h13214 = m_slave_xactor_f_rd_addr$D_OUT[92:29] - m_rg_addr_base ; - assign addr_offset__h26927 = + assign addr_offset__h26920 = m_slave_xactor_f_wr_addr$D_OUT[92:29] - m_rg_addr_base ; - assign b__h71311 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3090 ? + assign b__h71298 = + m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3089 ? 5'd16 : - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3106 ; - assign b__h73316 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3184 ? + IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3105 ; + assign b__h73303 = + m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3183 ? 5'd16 : - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3200 ; + IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3199 ; assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 = addr_offset__h13214 < 64'h0000000000003000 ; assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d242 = @@ -16044,181 +16038,181 @@ module mkPLIC_16_2_7(CLK, addr_offset__h13214 < 64'h0000000000002000 ; assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 = source_id_base__h13628 <= 10'd16 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 = - addr_offset__h26927[16:12] <= 5'd1 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2886 = - addr_offset__h26927[16:12] == 5'd0 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2883 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2888 = - addr_offset__h26927[16:12] == 5'd1 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2883 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 = + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879 = + addr_offset__h26920[16:12] <= 5'd1 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2885 = + addr_offset__h26920[16:12] == 5'd0 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2882 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2887 = + addr_offset__h26920[16:12] == 5'd1 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2882 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 = m_slave_xactor_f_wr_addr$D_OUT[92:29] < m_rg_addr_base ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 = - addr_offset__h26927 < 64'h0000000000001000 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 = - addr_offset__h26927[11:2] <= 10'd16 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d863 = - addr_offset__h26927[11:2] == 10'd1 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d865 = - addr_offset__h26927[11:2] == 10'd2 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d867 = - addr_offset__h26927[11:2] == 10'd3 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d869 = - addr_offset__h26927[11:2] == 10'd4 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d871 = - addr_offset__h26927[11:2] == 10'd5 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d873 = - addr_offset__h26927[11:2] == 10'd6 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d875 = - addr_offset__h26927[11:2] == 10'd7 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d877 = - addr_offset__h26927[11:2] == 10'd8 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d879 = - addr_offset__h26927[11:2] == 10'd9 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d881 = - addr_offset__h26927[11:2] == 10'd10 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d883 = - addr_offset__h26927[11:2] == 10'd11 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d885 = - addr_offset__h26927[11:2] == 10'd12 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d887 = - addr_offset__h26927[11:2] == 10'd13 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d889 = - addr_offset__h26927[11:2] == 10'd14 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d891 = - addr_offset__h26927[11:2] == 10'd15 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d893 = - addr_offset__h26927[11:2] == 10'd16 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d895 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - addr_offset__h26927[11:2] != 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 && + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 = + addr_offset__h26920 < 64'h0000000000001000 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 = + addr_offset__h26920[11:2] <= 10'd16 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d862 = + addr_offset__h26920[11:2] == 10'd1 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d864 = + addr_offset__h26920[11:2] == 10'd2 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d866 = + addr_offset__h26920[11:2] == 10'd3 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d868 = + addr_offset__h26920[11:2] == 10'd4 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d870 = + addr_offset__h26920[11:2] == 10'd5 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d872 = + addr_offset__h26920[11:2] == 10'd6 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d874 = + addr_offset__h26920[11:2] == 10'd7 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d876 = + addr_offset__h26920[11:2] == 10'd8 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d878 = + addr_offset__h26920[11:2] == 10'd9 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d880 = + addr_offset__h26920[11:2] == 10'd10 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d882 = + addr_offset__h26920[11:2] == 10'd11 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d884 = + addr_offset__h26920[11:2] == 10'd12 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d886 = + addr_offset__h26920[11:2] == 10'd13 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d888 = + addr_offset__h26920[11:2] == 10'd14 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d890 = + addr_offset__h26920[11:2] == 10'd15 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d892 = + addr_offset__h26920[11:2] == 10'd16 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d894 = + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + addr_offset__h26920[11:2] != 10'd0 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 && m_cfg_verbosity != 4'd0 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 = - addr_offset__h26927 < 64'h0000000000002000 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 = - source_id_base__h28146 <= 10'd16 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 = + addr_offset__h26920 < 64'h0000000000002000 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 = + source_id_base__h28137 <= 10'd16 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 = + addr_offset__h26920 < 64'h0000000000003000 ; assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 = - addr_offset__h26927 < 64'h0000000000003000 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 = - addr_offset__h26927[11:7] <= 5'd1 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 = - addr_offset__h26927[11:7] == 5'd0 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d918 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 = - addr_offset__h26927[11:7] == 5'd1 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d918 ; - assign m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3060 = + addr_offset__h26920[11:7] <= 5'd1 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 = + addr_offset__h26920[11:7] == 5'd0 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d917 ; + assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 = + addr_offset__h26920[11:7] == 5'd1 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d917 ; + assign m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3059 = m_vrg_source_ip_10 && m_vrg_source_prio_10 > - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3056 && + IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3055 && m_vvrg_ie_0_10 ; - assign m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3154 = + assign m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3153 = m_vrg_source_ip_10 && m_vrg_source_prio_10 > - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3150 && + IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3149 && m_vvrg_ie_1_10 ; assign m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614 = m_vrg_source_ip_10 && m_vrg_source_prio_10 > IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d608 && CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 ; - assign m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3065 = + assign m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3064 = m_vrg_source_ip_11 && m_vrg_source_prio_11 > - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3061 && + IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3060 && m_vvrg_ie_0_11 ; - assign m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3159 = + assign m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3158 = m_vrg_source_ip_11 && m_vrg_source_prio_11 > - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3155 && + IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3154 && m_vvrg_ie_1_11 ; assign m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d621 = m_vrg_source_ip_11 && m_vrg_source_prio_11 > IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d615 && CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 ; - assign m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3070 = + assign m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3069 = m_vrg_source_ip_12 && m_vrg_source_prio_12 > - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3066 && + IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3065 && m_vvrg_ie_0_12 ; - assign m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3164 = + assign m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3163 = m_vrg_source_ip_12 && m_vrg_source_prio_12 > - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3160 && + IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3159 && m_vvrg_ie_1_12 ; assign m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628 = m_vrg_source_ip_12 && m_vrg_source_prio_12 > IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d622 && CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 ; - assign m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3075 = + assign m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3074 = m_vrg_source_ip_13 && m_vrg_source_prio_13 > - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3071 && + IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3070 && m_vvrg_ie_0_13 ; - assign m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3169 = + assign m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3168 = m_vrg_source_ip_13 && m_vrg_source_prio_13 > - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3165 && + IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3164 && m_vvrg_ie_1_13 ; assign m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d635 = m_vrg_source_ip_13 && @@ -16233,45 +16227,45 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607 || m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600 || m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d685 ; - assign m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3080 = + assign m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3079 = m_vrg_source_ip_14 && m_vrg_source_prio_14 > - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3076 && + IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3075 && m_vvrg_ie_0_14 ; - assign m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3174 = + assign m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3173 = m_vrg_source_ip_14 && m_vrg_source_prio_14 > - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3170 && + IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3169 && m_vvrg_ie_1_14 ; assign m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642 = m_vrg_source_ip_14 && m_vrg_source_prio_14 > IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d636 && CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 ; - assign m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3085 = + assign m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3084 = m_vrg_source_ip_15 && m_vrg_source_prio_15 > - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3081 && + IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3080 && m_vvrg_ie_0_15 ; - assign m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3179 = + assign m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3178 = m_vrg_source_ip_15 && m_vrg_source_prio_15 > - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3175 && + IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3174 && m_vvrg_ie_1_15 ; assign m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d649 = m_vrg_source_ip_15 && m_vrg_source_prio_15 > IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d643 && CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 ; - assign m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3090 = + assign m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3089 = m_vrg_source_ip_16 && m_vrg_source_prio_16 > - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3086 && + IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3085 && m_vvrg_ie_0_16 ; - assign m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3184 = + assign m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3183 = m_vrg_source_ip_16 && m_vrg_source_prio_16 > - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3180 && + IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3179 && m_vvrg_ie_1_16 ; assign m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d656 = m_vrg_source_ip_16 && @@ -16285,90 +16279,90 @@ module mkPLIC_16_2_7(CLK, assign m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551 = m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 ; - assign m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3020 = + assign m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3019 = m_vrg_source_ip_2 && m_vrg_source_prio_2 > - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3016 && + IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3015 && m_vvrg_ie_0_2 ; - assign m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3114 = + assign m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3113 = m_vrg_source_ip_2 && m_vrg_source_prio_2 > - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3110 && + IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3109 && m_vvrg_ie_1_2 ; assign m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558 = m_vrg_source_ip_2 && m_vrg_source_prio_2 > IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d552 && CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 ; - assign m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3025 = + assign m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3024 = m_vrg_source_ip_3 && m_vrg_source_prio_3 > - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3021 && + IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3020 && m_vvrg_ie_0_3 ; - assign m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3119 = + assign m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3118 = m_vrg_source_ip_3 && m_vrg_source_prio_3 > - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3115 && + IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3114 && m_vvrg_ie_1_3 ; assign m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d565 = m_vrg_source_ip_3 && m_vrg_source_prio_3 > IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d559 && CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 ; - assign m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3030 = + assign m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3029 = m_vrg_source_ip_4 && m_vrg_source_prio_4 > - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3026 && + IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3025 && m_vvrg_ie_0_4 ; - assign m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3124 = + assign m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3123 = m_vrg_source_ip_4 && m_vrg_source_prio_4 > - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3120 && + IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3119 && m_vvrg_ie_1_4 ; assign m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572 = m_vrg_source_ip_4 && m_vrg_source_prio_4 > IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d566 && CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 ; - assign m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3035 = + assign m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3034 = m_vrg_source_ip_5 && m_vrg_source_prio_5 > - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3031 && + IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3030 && m_vvrg_ie_0_5 ; - assign m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3129 = + assign m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3128 = m_vrg_source_ip_5 && m_vrg_source_prio_5 > - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3125 && + IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3124 && m_vvrg_ie_1_5 ; assign m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d579 = m_vrg_source_ip_5 && m_vrg_source_prio_5 > IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d573 && CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 ; - assign m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3040 = + assign m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3039 = m_vrg_source_ip_6 && m_vrg_source_prio_6 > - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3036 && + IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3035 && m_vvrg_ie_0_6 ; - assign m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3134 = + assign m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3133 = m_vrg_source_ip_6 && m_vrg_source_prio_6 > - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3130 && + IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3129 && m_vvrg_ie_1_6 ; assign m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586 = m_vrg_source_ip_6 && m_vrg_source_prio_6 > IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d580 && CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 ; - assign m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3045 = + assign m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3044 = m_vrg_source_ip_7 && m_vrg_source_prio_7 > - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3041 && + IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3040 && m_vvrg_ie_0_7 ; - assign m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3139 = + assign m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3138 = m_vrg_source_ip_7 && m_vrg_source_prio_7 > - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3135 && + IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3134 && m_vvrg_ie_1_7 ; assign m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d593 = m_vrg_source_ip_7 && @@ -16383,30 +16377,30 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d565 || m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558 || m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551 ; - assign m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3050 = + assign m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3049 = m_vrg_source_ip_8 && m_vrg_source_prio_8 > - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3046 && + IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3045 && m_vvrg_ie_0_8 ; - assign m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3144 = + assign m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3143 = m_vrg_source_ip_8 && m_vrg_source_prio_8 > - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3140 && + IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3139 && m_vvrg_ie_1_8 ; assign m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600 = m_vrg_source_ip_8 && m_vrg_source_prio_8 > IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d594 && CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 ; - assign m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3055 = + assign m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3054 = m_vrg_source_ip_9 && m_vrg_source_prio_9 > - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3051 && + IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3050 && m_vvrg_ie_0_9 ; - assign m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3149 = + assign m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3148 = m_vrg_source_ip_9 && m_vrg_source_prio_9 > - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3145 && + IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3144 && m_vvrg_ie_1_9 ; assign m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607 = m_vrg_source_ip_9 && @@ -16493,40 +16487,40 @@ module mkPLIC_16_2_7(CLK, assign source_id__h23227 = 10'd3 + source_id_base__h13628 ; assign source_id__h23335 = 10'd2 + source_id_base__h13628 ; assign source_id__h23443 = 10'd1 + source_id_base__h13628 ; - assign source_id__h29473 = { addr_offset__h26927[4:0], 5'd1 } ; - assign source_id__h30683 = { addr_offset__h26927[4:0], 5'd2 } ; - assign source_id__h31893 = { addr_offset__h26927[4:0], 5'd3 } ; - assign source_id__h33103 = { addr_offset__h26927[4:0], 5'd4 } ; - assign source_id__h34313 = { addr_offset__h26927[4:0], 5'd5 } ; - assign source_id__h35523 = { addr_offset__h26927[4:0], 5'd6 } ; - assign source_id__h36733 = { addr_offset__h26927[4:0], 5'd7 } ; - assign source_id__h37943 = { addr_offset__h26927[4:0], 5'd8 } ; - assign source_id__h39153 = { addr_offset__h26927[4:0], 5'd9 } ; - assign source_id__h40363 = { addr_offset__h26927[4:0], 5'd10 } ; - assign source_id__h41573 = { addr_offset__h26927[4:0], 5'd11 } ; - assign source_id__h42783 = { addr_offset__h26927[4:0], 5'd12 } ; - assign source_id__h43993 = { addr_offset__h26927[4:0], 5'd13 } ; - assign source_id__h45203 = { addr_offset__h26927[4:0], 5'd14 } ; - assign source_id__h46413 = { addr_offset__h26927[4:0], 5'd15 } ; - assign source_id__h47623 = { addr_offset__h26927[4:0], 5'd16 } ; - assign source_id__h48833 = { addr_offset__h26927[4:0], 5'd17 } ; - assign source_id__h50043 = { addr_offset__h26927[4:0], 5'd18 } ; - assign source_id__h51253 = { addr_offset__h26927[4:0], 5'd19 } ; - assign source_id__h52463 = { addr_offset__h26927[4:0], 5'd20 } ; - assign source_id__h53673 = { addr_offset__h26927[4:0], 5'd21 } ; - assign source_id__h54883 = { addr_offset__h26927[4:0], 5'd22 } ; - assign source_id__h56093 = { addr_offset__h26927[4:0], 5'd23 } ; - assign source_id__h57303 = { addr_offset__h26927[4:0], 5'd24 } ; - assign source_id__h58513 = { addr_offset__h26927[4:0], 5'd25 } ; - assign source_id__h59723 = { addr_offset__h26927[4:0], 5'd26 } ; - assign source_id__h60933 = { addr_offset__h26927[4:0], 5'd27 } ; - assign source_id__h62143 = { addr_offset__h26927[4:0], 5'd28 } ; - assign source_id__h63353 = { addr_offset__h26927[4:0], 5'd29 } ; - assign source_id__h64563 = { addr_offset__h26927[4:0], 5'd30 } ; - assign source_id__h65773 = { addr_offset__h26927[4:0], 5'd31 } ; - assign source_id__h67434 = { 5'd0, x__h67485 } ; + assign source_id__h29464 = { addr_offset__h26920[4:0], 5'd1 } ; + assign source_id__h30674 = { addr_offset__h26920[4:0], 5'd2 } ; + assign source_id__h31884 = { addr_offset__h26920[4:0], 5'd3 } ; + assign source_id__h33094 = { addr_offset__h26920[4:0], 5'd4 } ; + assign source_id__h34304 = { addr_offset__h26920[4:0], 5'd5 } ; + assign source_id__h35514 = { addr_offset__h26920[4:0], 5'd6 } ; + assign source_id__h36724 = { addr_offset__h26920[4:0], 5'd7 } ; + assign source_id__h37934 = { addr_offset__h26920[4:0], 5'd8 } ; + assign source_id__h39144 = { addr_offset__h26920[4:0], 5'd9 } ; + assign source_id__h40354 = { addr_offset__h26920[4:0], 5'd10 } ; + assign source_id__h41564 = { addr_offset__h26920[4:0], 5'd11 } ; + assign source_id__h42774 = { addr_offset__h26920[4:0], 5'd12 } ; + assign source_id__h43984 = { addr_offset__h26920[4:0], 5'd13 } ; + assign source_id__h45194 = { addr_offset__h26920[4:0], 5'd14 } ; + assign source_id__h46404 = { addr_offset__h26920[4:0], 5'd15 } ; + assign source_id__h47614 = { addr_offset__h26920[4:0], 5'd16 } ; + assign source_id__h48824 = { addr_offset__h26920[4:0], 5'd17 } ; + assign source_id__h50034 = { addr_offset__h26920[4:0], 5'd18 } ; + assign source_id__h51244 = { addr_offset__h26920[4:0], 5'd19 } ; + assign source_id__h52454 = { addr_offset__h26920[4:0], 5'd20 } ; + assign source_id__h53664 = { addr_offset__h26920[4:0], 5'd21 } ; + assign source_id__h54874 = { addr_offset__h26920[4:0], 5'd22 } ; + assign source_id__h56084 = { addr_offset__h26920[4:0], 5'd23 } ; + assign source_id__h57294 = { addr_offset__h26920[4:0], 5'd24 } ; + assign source_id__h58504 = { addr_offset__h26920[4:0], 5'd25 } ; + assign source_id__h59714 = { addr_offset__h26920[4:0], 5'd26 } ; + assign source_id__h60924 = { addr_offset__h26920[4:0], 5'd27 } ; + assign source_id__h62134 = { addr_offset__h26920[4:0], 5'd28 } ; + assign source_id__h63344 = { addr_offset__h26920[4:0], 5'd29 } ; + assign source_id__h64554 = { addr_offset__h26920[4:0], 5'd30 } ; + assign source_id__h65764 = { addr_offset__h26920[4:0], 5'd31 } ; + assign source_id__h67425 = { 5'd0, x__h67476 } ; assign source_id_base__h13628 = { addr_offset__h13214[4:0], 5'h0 } ; - assign source_id_base__h28146 = { addr_offset__h26927[4:0], 5'h0 } ; + assign source_id_base__h28137 = { addr_offset__h26920[4:0], 5'h0 } ; assign v__h13420 = { 61'd0, x__h13491 } ; assign v__h13669 = { 32'd0, v_ip__h13672 } ; assign v__h18142 = { 32'd0, v_ie__h18145 } ; @@ -16536,48 +16530,48 @@ module mkPLIC_16_2_7(CLK, v__h25472 : 64'd0 ; assign v__h25472 = { 59'd0, max_id__h23957 } ; - assign v__h26932 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 ? + assign v__h26925 = + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 ? 2'b11 : - v__h27092 ; - assign v__h27092 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 ? - v__h27105 : - v__h27940 ; - assign v__h27105 = - (addr_offset__h26927[11:2] != 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849) ? + v__h27083 ; + assign v__h27083 = + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 ? + v__h27096 : + v__h27931 ; + assign v__h27096 = + (addr_offset__h26920[11:2] != 10'd0 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848) ? 2'b0 : 2'b10 ; - assign v__h27940 = - (!m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900) ? - v__h27959 : - v__h28123 ; - assign v__h27959 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 ? + assign v__h27931 = + (!m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899) ? + v__h27950 : + v__h28114 ; + assign v__h27950 = + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 ? 2'b0 : 2'b10 ; - assign v__h28123 = - (!m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && + assign v__h28114 = + (!m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913) ? + v__h28133 : + v__h67096 ; + assign v__h28133 = + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914) ? - v__h28142 : - v__h67105 ; - assign v__h28142 = - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915) ? 2'b0 : 2'b10 ; - assign v__h67142 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 ? + assign v__h67133 = + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879 ? 2'b0 : 2'b10 ; - assign v__h67430 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 ? - v__h67474 : + assign v__h67421 = + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879 ? + v__h67465 : 2'b10 ; - assign v__h67474 = - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 ? + assign v__h67465 = + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 ? 2'b0 : 2'b10 ; assign v_ie__h18145 = @@ -16710,8 +16704,8 @@ module mkPLIC_16_2_7(CLK, SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233, m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 && SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 } ; - assign wdata32__h26928 = - (addr_offset__h26927[2:0] == 3'd4) ? + assign wdata32__h26921 = + (addr_offset__h26920[2:0] == 3'd4) ? m_slave_xactor_f_wr_data$D_OUT[72:41] : m_slave_xactor_f_wr_data$D_OUT[40:9] ; assign x__h23671 = @@ -16720,8 +16714,8 @@ module mkPLIC_16_2_7(CLK, (addr_offset__h13214[2:0] == 3'd4) ? rdata___1__h26402 : rdata__h26200 ; - assign x__h67108 = - { addr_offset__h26927[31:16], 4'd0, addr_offset__h26927[11:0] } ; + assign x__h67099 = + { addr_offset__h26920[31:16], 4'd0, addr_offset__h26920[11:0] } ; assign y_avValue_fst__h26092 = (x__h24009 == 5'd0) ? v__h25453 : 64'd0 ; assign y_avValue_fst__h26113 = m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 ? @@ -16853,13 +16847,13 @@ module mkPLIC_16_2_7(CLK, default: x__h24009 = 5'b01010 /* unspecified value */ ; endcase end - always@(addr_offset__h26927 or + always@(addr_offset__h26920 or m_vrg_servicing_source_0 or m_vrg_servicing_source_1) begin - case (addr_offset__h26927[16:12]) - 5'd0: x__h67485 = m_vrg_servicing_source_0; - 5'd1: x__h67485 = m_vrg_servicing_source_1; - default: x__h67485 = 5'b01010 /* unspecified value */ ; + case (addr_offset__h26920[16:12]) + 5'd0: x__h67476 = m_vrg_servicing_source_0; + 5'd1: x__h67476 = m_vrg_servicing_source_1; + default: x__h67476 = 5'b01010 /* unspecified value */ ; endcase end always@(source_id__h16208 or @@ -24574,7 +24568,7 @@ module mkPLIC_16_2_7(CLK, default: y_avValue_fst__h26146 = 64'd0; endcase end - always@(source_id__h67434 or + always@(source_id__h67425 or m_vrg_source_busy_0 or m_vrg_source_busy_1 or m_vrg_source_busy_2 or @@ -24592,68 +24586,68 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_busy_14 or m_vrg_source_busy_15 or m_vrg_source_busy_16) begin - case (source_id__h67434) + case (source_id__h67425) 10'd0: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = m_vrg_source_busy_0; 10'd1: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = m_vrg_source_busy_1; 10'd2: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = m_vrg_source_busy_2; 10'd3: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = m_vrg_source_busy_3; 10'd4: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = m_vrg_source_busy_4; 10'd5: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = m_vrg_source_busy_5; 10'd6: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = m_vrg_source_busy_6; 10'd7: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = m_vrg_source_busy_7; 10'd8: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = m_vrg_source_busy_8; 10'd9: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = m_vrg_source_busy_9; 10'd10: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = m_vrg_source_busy_10; 10'd11: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = m_vrg_source_busy_11; 10'd12: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = m_vrg_source_busy_12; 10'd13: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = m_vrg_source_busy_13; 10'd14: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = m_vrg_source_busy_14; 10'd15: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = m_vrg_source_busy_15; 10'd16: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = + SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = m_vrg_source_busy_16; - default: SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = + default: SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = 1'b0 /* unspecified value */ ; endcase end - always@(x__h67108 or v__h67142 or v__h67430) + always@(x__h67099 or v__h67133 or v__h67421) begin - case (x__h67108) - 32'h00200000: v__h67105 = v__h67142; - 32'h00200004: v__h67105 = v__h67430; - default: v__h67105 = 2'b10; + case (x__h67099) + 32'h00200000: v__h67096 = v__h67133; + 32'h00200004: v__h67096 = v__h67421; + default: v__h67096 = 2'b10; endcase end @@ -25240,9 +25234,9 @@ module mkPLIC_16_2_7(CLK, if (RST_N != `BSV_RESET_VALUE) if (EN_show_PLIC_state) $display(" MaxPri %0d, Thresh %0d, MaxId %0d, Svcing %0d", - a__h71310, + a__h71297, m_vrg_target_threshold_0, - b__h71311, + b__h71298, m_vrg_servicing_source_0); if (RST_N != `BSV_RESET_VALUE) if (EN_show_PLIC_state) $write("T %0d IEs :", $signed(32'd1)); @@ -25283,216 +25277,216 @@ module mkPLIC_16_2_7(CLK, if (RST_N != `BSV_RESET_VALUE) if (EN_show_PLIC_state) $display(" MaxPri %0d, Thresh %0d, MaxId %0d, Svcing %0d", - a__h73315, + a__h73302, m_vrg_target_threshold_1, - b__h73316, + b__h73303, m_vrg_servicing_source_1); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_0_901_238_AND_NOT_m_cfg__ETC___d3242) + if (NOT_m_vrg_source_busy_0_900_236_AND_NOT_m_cfg__ETC___d3240) begin - v__h75671 = $stime; + v__h75656 = $stime; #0; end - v__h75665 = v__h75671 / 32'd10; + v__h75650 = v__h75656 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_0_901_238_AND_NOT_m_cfg__ETC___d3242) + if (NOT_m_vrg_source_busy_0_900_236_AND_NOT_m_cfg__ETC___d3240) $display("%0d: Changing vrg_source_ip [%0d] to %0d", - v__h75665, + v__h75650, $signed(32'd0), v_sources_0_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_1_902_245_AND_NOT_m_cfg__ETC___d3249) + if (NOT_m_vrg_source_busy_1_901_243_AND_NOT_m_cfg__ETC___d3247) begin - v__h75866 = $stime; + v__h75851 = $stime; #0; end - v__h75860 = v__h75866 / 32'd10; + v__h75845 = v__h75851 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_1_902_245_AND_NOT_m_cfg__ETC___d3249) + if (NOT_m_vrg_source_busy_1_901_243_AND_NOT_m_cfg__ETC___d3247) $display("%0d: Changing vrg_source_ip [%0d] to %0d", - v__h75860, + v__h75845, $signed(32'd1), v_sources_1_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_2_903_252_AND_NOT_m_cfg__ETC___d3256) + if (NOT_m_vrg_source_busy_2_902_250_AND_NOT_m_cfg__ETC___d3254) begin - v__h76061 = $stime; + v__h76046 = $stime; #0; end - v__h76055 = v__h76061 / 32'd10; + v__h76040 = v__h76046 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_2_903_252_AND_NOT_m_cfg__ETC___d3256) + if (NOT_m_vrg_source_busy_2_902_250_AND_NOT_m_cfg__ETC___d3254) $display("%0d: Changing vrg_source_ip [%0d] to %0d", - v__h76055, + v__h76040, $signed(32'd2), v_sources_2_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_3_904_260_AND_NOT_m_cfg__ETC___d3264) + if (NOT_m_vrg_source_busy_3_903_258_AND_NOT_m_cfg__ETC___d3262) begin - v__h76256 = $stime; + v__h76241 = $stime; #0; end - v__h76250 = v__h76256 / 32'd10; + v__h76235 = v__h76241 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_3_904_260_AND_NOT_m_cfg__ETC___d3264) + if (NOT_m_vrg_source_busy_3_903_258_AND_NOT_m_cfg__ETC___d3262) $display("%0d: Changing vrg_source_ip [%0d] to %0d", - v__h76250, + v__h76235, $signed(32'd3), v_sources_3_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_4_905_268_AND_NOT_m_cfg__ETC___d3272) + if (NOT_m_vrg_source_busy_4_904_266_AND_NOT_m_cfg__ETC___d3270) begin - v__h76451 = $stime; + v__h76436 = $stime; #0; end - v__h76445 = v__h76451 / 32'd10; + v__h76430 = v__h76436 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_4_905_268_AND_NOT_m_cfg__ETC___d3272) + if (NOT_m_vrg_source_busy_4_904_266_AND_NOT_m_cfg__ETC___d3270) $display("%0d: Changing vrg_source_ip [%0d] to %0d", - v__h76445, + v__h76430, $signed(32'd4), v_sources_4_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_5_906_276_AND_NOT_m_cfg__ETC___d3280) + if (NOT_m_vrg_source_busy_5_905_274_AND_NOT_m_cfg__ETC___d3278) begin - v__h76646 = $stime; + v__h76631 = $stime; #0; end - v__h76640 = v__h76646 / 32'd10; + v__h76625 = v__h76631 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_5_906_276_AND_NOT_m_cfg__ETC___d3280) + if (NOT_m_vrg_source_busy_5_905_274_AND_NOT_m_cfg__ETC___d3278) $display("%0d: Changing vrg_source_ip [%0d] to %0d", - v__h76640, + v__h76625, $signed(32'd5), v_sources_5_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_6_907_284_AND_NOT_m_cfg__ETC___d3288) + if (NOT_m_vrg_source_busy_6_906_282_AND_NOT_m_cfg__ETC___d3286) begin - v__h76841 = $stime; + v__h76826 = $stime; #0; end - v__h76835 = v__h76841 / 32'd10; + v__h76820 = v__h76826 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_6_907_284_AND_NOT_m_cfg__ETC___d3288) + if (NOT_m_vrg_source_busy_6_906_282_AND_NOT_m_cfg__ETC___d3286) $display("%0d: Changing vrg_source_ip [%0d] to %0d", - v__h76835, + v__h76820, $signed(32'd6), v_sources_6_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_7_908_292_AND_NOT_m_cfg__ETC___d3296) + if (NOT_m_vrg_source_busy_7_907_290_AND_NOT_m_cfg__ETC___d3294) begin - v__h77036 = $stime; + v__h77021 = $stime; #0; end - v__h77030 = v__h77036 / 32'd10; + v__h77015 = v__h77021 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_7_908_292_AND_NOT_m_cfg__ETC___d3296) + if (NOT_m_vrg_source_busy_7_907_290_AND_NOT_m_cfg__ETC___d3294) $display("%0d: Changing vrg_source_ip [%0d] to %0d", - v__h77030, + v__h77015, $signed(32'd7), v_sources_7_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_8_909_300_AND_NOT_m_cfg__ETC___d3304) + if (NOT_m_vrg_source_busy_8_908_298_AND_NOT_m_cfg__ETC___d3302) begin - v__h77231 = $stime; + v__h77216 = $stime; #0; end - v__h77225 = v__h77231 / 32'd10; + v__h77210 = v__h77216 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_8_909_300_AND_NOT_m_cfg__ETC___d3304) + if (NOT_m_vrg_source_busy_8_908_298_AND_NOT_m_cfg__ETC___d3302) $display("%0d: Changing vrg_source_ip [%0d] to %0d", - v__h77225, + v__h77210, $signed(32'd8), v_sources_8_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_9_910_308_AND_NOT_m_cfg__ETC___d3312) + if (NOT_m_vrg_source_busy_9_909_306_AND_NOT_m_cfg__ETC___d3310) begin - v__h77426 = $stime; + v__h77411 = $stime; #0; end - v__h77420 = v__h77426 / 32'd10; + v__h77405 = v__h77411 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_9_910_308_AND_NOT_m_cfg__ETC___d3312) + if (NOT_m_vrg_source_busy_9_909_306_AND_NOT_m_cfg__ETC___d3310) $display("%0d: Changing vrg_source_ip [%0d] to %0d", - v__h77420, + v__h77405, $signed(32'd9), v_sources_9_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_10_911_316_AND_NOT_m_cfg_ETC___d3320) + if (NOT_m_vrg_source_busy_10_910_314_AND_NOT_m_cfg_ETC___d3318) begin - v__h77621 = $stime; + v__h77606 = $stime; #0; end - v__h77615 = v__h77621 / 32'd10; + v__h77600 = v__h77606 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_10_911_316_AND_NOT_m_cfg_ETC___d3320) + if (NOT_m_vrg_source_busy_10_910_314_AND_NOT_m_cfg_ETC___d3318) $display("%0d: Changing vrg_source_ip [%0d] to %0d", - v__h77615, + v__h77600, $signed(32'd10), v_sources_10_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_11_912_324_AND_NOT_m_cfg_ETC___d3328) + if (NOT_m_vrg_source_busy_11_911_322_AND_NOT_m_cfg_ETC___d3326) begin - v__h77816 = $stime; + v__h77801 = $stime; #0; end - v__h77810 = v__h77816 / 32'd10; + v__h77795 = v__h77801 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_11_912_324_AND_NOT_m_cfg_ETC___d3328) + if (NOT_m_vrg_source_busy_11_911_322_AND_NOT_m_cfg_ETC___d3326) $display("%0d: Changing vrg_source_ip [%0d] to %0d", - v__h77810, + v__h77795, $signed(32'd11), v_sources_11_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_12_913_332_AND_NOT_m_cfg_ETC___d3336) + if (NOT_m_vrg_source_busy_12_912_330_AND_NOT_m_cfg_ETC___d3334) begin - v__h78011 = $stime; + v__h77996 = $stime; #0; end - v__h78005 = v__h78011 / 32'd10; + v__h77990 = v__h77996 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_12_913_332_AND_NOT_m_cfg_ETC___d3336) + if (NOT_m_vrg_source_busy_12_912_330_AND_NOT_m_cfg_ETC___d3334) $display("%0d: Changing vrg_source_ip [%0d] to %0d", - v__h78005, + v__h77990, $signed(32'd12), v_sources_12_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_13_914_340_AND_NOT_m_cfg_ETC___d3344) + if (NOT_m_vrg_source_busy_13_913_338_AND_NOT_m_cfg_ETC___d3342) begin - v__h78206 = $stime; + v__h78191 = $stime; #0; end - v__h78200 = v__h78206 / 32'd10; + v__h78185 = v__h78191 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_13_914_340_AND_NOT_m_cfg_ETC___d3344) + if (NOT_m_vrg_source_busy_13_913_338_AND_NOT_m_cfg_ETC___d3342) $display("%0d: Changing vrg_source_ip [%0d] to %0d", - v__h78200, + v__h78185, $signed(32'd13), v_sources_13_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_14_915_348_AND_NOT_m_cfg_ETC___d3352) + if (NOT_m_vrg_source_busy_14_914_346_AND_NOT_m_cfg_ETC___d3350) begin - v__h78401 = $stime; + v__h78386 = $stime; #0; end - v__h78395 = v__h78401 / 32'd10; + v__h78380 = v__h78386 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_14_915_348_AND_NOT_m_cfg_ETC___d3352) + if (NOT_m_vrg_source_busy_14_914_346_AND_NOT_m_cfg_ETC___d3350) $display("%0d: Changing vrg_source_ip [%0d] to %0d", - v__h78395, + v__h78380, $signed(32'd14), v_sources_14_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_15_916_356_AND_NOT_m_cfg_ETC___d3360) + if (NOT_m_vrg_source_busy_15_915_354_AND_NOT_m_cfg_ETC___d3358) begin - v__h78596 = $stime; + v__h78581 = $stime; #0; end - v__h78590 = v__h78596 / 32'd10; + v__h78575 = v__h78581 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_15_916_356_AND_NOT_m_cfg_ETC___d3360) + if (NOT_m_vrg_source_busy_15_915_354_AND_NOT_m_cfg_ETC___d3358) $display("%0d: Changing vrg_source_ip [%0d] to %0d", - v__h78590, + v__h78575, $signed(32'd15), v_sources_15_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) @@ -26127,14 +26121,14 @@ module mkPLIC_16_2_7(CLK, if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_cfg_verbosity_read_ULE_1_5___d16) begin - v__h26738 = $stime; + v__h26735 = $stime; #0; end - v__h26732 = v__h26738 / 32'd10; + v__h26729 = v__h26735 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $display("%0d: PLIC.rl_process_wr_req", v__h26732); + $display("%0d: PLIC.rl_process_wr_req", v__h26729); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_cfg_verbosity_read_ULE_1_5___d16) @@ -26238,15 +26232,7 @@ module mkPLIC_16_2_7(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "wdata: "); + $write("AXI4_Wr_Data { ", "wdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_cfg_verbosity_read_ULE_1_5___d16) @@ -26287,485 +26273,467 @@ module mkPLIC_16_2_7(CLK, $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) begin - v__h26966 = $stime; + v__h26959 = $stime; #0; end - v__h26960 = v__h26966 / 32'd10; + v__h26953 = v__h26959 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $display("%0d: ERROR: PLIC.rl_process_wr_req: unrecognized addr", - v__h26960); + v__h26953); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write("AXI4_Wr_Addr { ", "awid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[96:93]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write(", ", "awaddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[92:29]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write(", ", "awlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[28:21]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write(", ", "awsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[20:18]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write(", ", "awburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[17:16]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write(", ", "awlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[15]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write(", ", "awcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[14:11]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write(", ", "awprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[10:8]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write(", ", "awqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[7:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write(", ", "awregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write(", ", "awuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("AXI4_Wr_Data { ", "wid: "); + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) + $write("AXI4_Wr_Data { ", "wdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[72:9]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write(", ", "wstrb: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[8:1]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write(", ", "wlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && m_slave_xactor_f_wr_data$D_OUT[0]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && !m_slave_xactor_f_wr_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write(", ", "wuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d895) + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d894) begin - v__h27863 = $stime; + v__h27854 = $stime; #0; end - v__h27857 = v__h27863 / 32'd10; + v__h27848 = v__h27854 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d895) + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d894) $display("%0d: PLIC.rl_process_wr_req: writing Source Priority: source %0d = 0x%0h", - v__h27857, - addr_offset__h26927[11:2], - wdata32__h26928); + v__h27848, + addr_offset__h26920[11:2], + wdata32__h26921); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d906) + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d905) begin - v__h28046 = $stime; + v__h28037 = $stime; #0; end - v__h28040 = v__h28046 / 32'd10; + v__h28031 = v__h28037 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d906) + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d905) $display("%0d: PLIC.rl_process_wr_req: Ignoring write to Read-only Intr Pending 32 bits from source %0d", - v__h28040, - source_id_base__h28146); + v__h28031, + source_id_base__h28137); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2870) + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2869) begin - v__h67028 = $stime; + v__h67019 = $stime; #0; end - v__h67022 = v__h67028 / 32'd10; + v__h67013 = v__h67019 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2870) + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2869) $display("%0d: PLIC.rl_process_wr_req: writing Intr Enable 32 bits for target %0d from source %0d = 0x%0h", - v__h67022, - addr_offset__h26927[11:7], - source_id_base__h28146, - wdata32__h26928); + v__h67013, + addr_offset__h26920[11:7], + source_id_base__h28137, + wdata32__h26921); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2894) + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2893) begin - v__h67316 = $stime; + v__h67307 = $stime; #0; end - v__h67310 = v__h67316 / 32'd10; + v__h67301 = v__h67307 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2894) + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2893) $display("%0d: PLIC.rl_process_wr_req: writing threshold for target %0d = 0x%0h", - v__h67310, - addr_offset__h26927[16:12], - wdata32__h26928); + v__h67301, + addr_offset__h26920[16:12], + wdata32__h26921); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2966) + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2965) begin - v__h67845 = $stime; + v__h67836 = $stime; #0; end - v__h67839 = v__h67845 / 32'd10; + v__h67830 = v__h67836 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2966) + !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2965) $display("%0d: PLIC.rl_process_wr_req: writing completion for target %0d for source 0x%0h", - v__h67839, - addr_offset__h26927[16:12], - source_id__h67434); + v__h67830, + addr_offset__h26920[16:12], + source_id__h67425); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2976) + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2975) begin - v__h67931 = $stime; + v__h67922 = $stime; #0; end - v__h67925 = v__h67931 / 32'd10; + v__h67916 = v__h67922 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2976) + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2975) $display("%0d: ERROR: PLIC: interrupt completion to source that is not being serviced", - v__h67925); + v__h67916); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2976) + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2975) $display(" Completion message from target %0d to source %0d", - addr_offset__h26927[16:12], - source_id__h67434); + addr_offset__h26920[16:12], + source_id__h67425); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2976) + NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2975) $display(" Ignoring"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) begin - v__h68130 = $stime; + v__h68121 = $stime; #0; end - v__h68124 = v__h68130 / 32'd10; + v__h68115 = v__h68121 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $display("%0d: ERROR: PLIC.rl_process_wr_req: unrecognized addr", - v__h68124); + v__h68115); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write("AXI4_Wr_Addr { ", "awid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[96:93]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write(", ", "awaddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[92:29]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write(", ", "awlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[28:21]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write(", ", "awsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[20:18]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write(", ", "awburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[17:16]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write(", ", "awlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[15]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write(", ", "awcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[14:11]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write(", ", "awprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[10:8]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write(", ", "awqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[7:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write(", ", "awregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write(", ", "awuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("AXI4_Wr_Data { ", "wid: "); + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) + $write("AXI4_Wr_Data { ", "wdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[72:9]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write(", ", "wstrb: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[8:1]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write(", ", "wlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991) && + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990) && m_slave_xactor_f_wr_data$D_OUT[0]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991) && + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990) && !m_slave_xactor_f_wr_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write(", ", "wuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) + (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || + IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_cfg_verbosity_read_ULE_1_5___d16) begin - v__h68351 = $stime; + v__h68340 = $stime; #0; end - v__h68345 = v__h68351 / 32'd10; + v__h68334 = v__h68340 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $display("%0d: PLIC.AXI4.rl_process_wr_req", v__h68345); + $display("%0d: PLIC.AXI4.rl_process_wr_req", v__h68334); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_cfg_verbosity_read_ULE_1_5___d16) @@ -26869,15 +26837,7 @@ module mkPLIC_16_2_7(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "wdata: "); + $write("AXI4_Wr_Data { ", "wdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_cfg_verbosity_read_ULE_1_5___d16) @@ -26935,7 +26895,7 @@ module mkPLIC_16_2_7(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", v__h26932); + $write("'h%h", v__h26925); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && NOT_m_cfg_verbosity_read_ULE_1_5___d16) @@ -26951,38 +26911,38 @@ module mkPLIC_16_2_7(CLK, if (RST_N != `BSV_RESET_VALUE) if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0) begin - v__h74688 = $stime; + v__h74675 = $stime; #0; end - v__h74682 = v__h74688 / 32'd10; + v__h74669 = v__h74675 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0) $display("%0d: WARNING: PLIC.set_addr_map: addr_base 0x%0h is not 4-Byte-aligned", - v__h74682, + v__h74669, set_addr_map_addr_base); if (RST_N != `BSV_RESET_VALUE) if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0) begin - v__h74798 = $stime; + v__h74785 = $stime; #0; end - v__h74792 = v__h74798 / 32'd10; + v__h74779 = v__h74785 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0) $display("%0d: WARNING: PLIC.set_addr_map: addr_lim 0x%0h is not 4-Byte-aligned", - v__h74792, + v__h74779, set_addr_map_addr_lim); if (RST_N != `BSV_RESET_VALUE) if (EN_set_addr_map && m_cfg_verbosity != 4'd0) begin - v__h74911 = $stime; + v__h74898 = $stime; #0; end - v__h74905 = v__h74911 / 32'd10; + v__h74892 = v__h74898 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_set_addr_map && m_cfg_verbosity != 4'd0) $display("%0d: PLIC.set_addr_map: base 0x%0h limit 0x%0h", - v__h74905, + v__h74892, set_addr_map_addr_base, set_addr_map_addr_lim); end diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkProc.v b/src_SSITH_P3_sim/Verilog_RTL/mkProc.v index 7ad341c..b07f90a 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkProc.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkProc.v @@ -1,13 +1,11 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // // // Ports: // Name I/O size props -// RDY_hart0_server_reset_request_put O 1 reg -// RDY_hart0_server_reset_response_get O 1 reg // RDY_start O 1 // master0_awvalid O 1 // master0_awid O 4 reg @@ -21,7 +19,6 @@ // master0_awqos O 4 reg // master0_awregion O 4 reg // master0_wvalid O 1 -// master0_wid O 4 reg // master0_wdata O 64 reg // master0_wstrb O 8 reg // master0_wlast O 1 reg @@ -50,7 +47,6 @@ // master1_awqos O 4 reg // master1_awregion O 4 reg // master1_wvalid O 1 -// master1_wid O 4 reg // master1_wdata O 64 reg // master1_wstrb O 8 reg // master1_wlast O 1 reg @@ -92,10 +88,6 @@ // hart0_csr_mem_server_response_get O 65 reg // RDY_hart0_csr_mem_server_response_get O 1 reg // RDY_hart0_put_other_req_put O 1 const -// v_to_TV_0_get O 320 -// RDY_v_to_TV_0_get O 1 reg -// v_to_TV_1_get O 320 -// RDY_v_to_TV_1_get O 1 reg // CLK I 1 clock // RST_N I 1 reset // start_startpc I 64 @@ -125,7 +117,6 @@ // master1_rlast I 1 reg // m_external_interrupt_req_set_not_clear I 1 // s_external_interrupt_req_set_not_clear I 1 -// debug_external_interrupt_req_set_not_clear I 1 // non_maskable_interrupt_req_set_not_clear I 1 unused // set_verbosity_verbosity I 4 // debug_module_mem_server_awvalid I 1 @@ -140,7 +131,6 @@ // debug_module_mem_server_awqos I 4 reg // debug_module_mem_server_awregion I 4 reg // debug_module_mem_server_wvalid I 1 -// debug_module_mem_server_wid I 4 reg // debug_module_mem_server_wdata I 64 reg // debug_module_mem_server_wstrb I 8 reg // debug_module_mem_server_wlast I 1 reg @@ -162,8 +152,6 @@ // hart0_fpr_mem_server_request_put I 70 reg // hart0_csr_mem_server_request_put I 77 reg // hart0_put_other_req_put I 4 -// EN_hart0_server_reset_request_put I 1 -// EN_hart0_server_reset_response_get I 1 // EN_start I 1 // EN_set_verbosity I 1 // EN_hart0_run_halt_server_request_put I 1 @@ -175,8 +163,6 @@ // EN_hart0_gpr_mem_server_response_get I 1 // EN_hart0_fpr_mem_server_response_get I 1 // EN_hart0_csr_mem_server_response_get I 1 -// EN_v_to_TV_0_get I 1 -// EN_v_to_TV_1_get I 1 // // Combinational paths from inputs to outputs: // (master0_awready, master0_wready) -> master0_bready @@ -200,12 +186,6 @@ module mkProc(CLK, RST_N, - EN_hart0_server_reset_request_put, - RDY_hart0_server_reset_request_put, - - EN_hart0_server_reset_response_get, - RDY_hart0_server_reset_response_get, - start_startpc, start_tohostAddr, start_fromhostAddr, @@ -238,8 +218,6 @@ module mkProc(CLK, master0_wvalid, - master0_wid, - master0_wdata, master0_wstrb, @@ -312,8 +290,6 @@ module mkProc(CLK, master1_wvalid, - master1_wid, - master1_wdata, master1_wstrb, @@ -364,8 +340,6 @@ module mkProc(CLK, s_external_interrupt_req_set_not_clear, - debug_external_interrupt_req_set_not_clear, - non_maskable_interrupt_req_set_not_clear, set_verbosity_verbosity, @@ -387,7 +361,6 @@ module mkProc(CLK, debug_module_mem_server_awready, debug_module_mem_server_wvalid, - debug_module_mem_server_wid, debug_module_mem_server_wdata, debug_module_mem_server_wstrb, debug_module_mem_server_wlast, @@ -462,26 +435,10 @@ module mkProc(CLK, hart0_put_other_req_put, EN_hart0_put_other_req_put, - RDY_hart0_put_other_req_put, - - EN_v_to_TV_0_get, - v_to_TV_0_get, - RDY_v_to_TV_0_get, - - EN_v_to_TV_1_get, - v_to_TV_1_get, - RDY_v_to_TV_1_get); + RDY_hart0_put_other_req_put); input CLK; input RST_N; - // action method hart0_server_reset_request_put - input EN_hart0_server_reset_request_put; - output RDY_hart0_server_reset_request_put; - - // action method hart0_server_reset_response_get - input EN_hart0_server_reset_response_get; - output RDY_hart0_server_reset_response_get; - // action method start input [63 : 0] start_startpc; input [63 : 0] start_tohostAddr; @@ -530,9 +487,6 @@ module mkProc(CLK, // value method master0_m_wvalid output master0_wvalid; - // value method master0_m_wid - output [3 : 0] master0_wid; - // value method master0_m_wdata output [63 : 0] master0_wdata; @@ -644,9 +598,6 @@ module mkProc(CLK, // value method master1_m_wvalid output master1_wvalid; - // value method master1_m_wid - output [3 : 0] master1_wid; - // value method master1_m_wdata output [63 : 0] master1_wdata; @@ -723,9 +674,6 @@ module mkProc(CLK, // action method s_external_interrupt_req input s_external_interrupt_req_set_not_clear; - // action method debug_external_interrupt_req - input debug_external_interrupt_req_set_not_clear; - // action method non_maskable_interrupt_req input non_maskable_interrupt_req_set_not_clear; @@ -752,7 +700,6 @@ module mkProc(CLK, // action method debug_module_mem_server_m_wvalid input debug_module_mem_server_wvalid; - input [3 : 0] debug_module_mem_server_wid; input [63 : 0] debug_module_mem_server_wdata; input [7 : 0] debug_module_mem_server_wstrb; input debug_module_mem_server_wlast; @@ -855,18 +802,7 @@ module mkProc(CLK, input EN_hart0_put_other_req_put; output RDY_hart0_put_other_req_put; - // actionvalue method v_to_TV_0_get - input EN_v_to_TV_0_get; - output [319 : 0] v_to_TV_0_get; - output RDY_v_to_TV_0_get; - - // actionvalue method v_to_TV_1_get - input EN_v_to_TV_1_get; - output [319 : 0] v_to_TV_1_get; - output RDY_v_to_TV_1_get; - // signals for module outputs - wire [319 : 0] v_to_TV_0_get, v_to_TV_1_get; wire [64 : 0] hart0_csr_mem_server_response_get, hart0_fpr_mem_server_response_get, hart0_gpr_mem_server_response_get; @@ -893,7 +829,6 @@ module mkProc(CLK, master0_awid, master0_awqos, master0_awregion, - master0_wid, master1_arcache, master1_arid, master1_arqos, @@ -901,8 +836,7 @@ module mkProc(CLK, master1_awcache, master1_awid, master1_awqos, - master1_awregion, - master1_wid; + master1_awregion; wire [2 : 0] master0_arprot, master0_arsize, master0_awprot, @@ -926,12 +860,8 @@ module mkProc(CLK, RDY_hart0_put_other_req_put, RDY_hart0_run_halt_server_request_put, RDY_hart0_run_halt_server_response_get, - RDY_hart0_server_reset_request_put, - RDY_hart0_server_reset_response_get, RDY_set_verbosity, RDY_start, - RDY_v_to_TV_0_get, - RDY_v_to_TV_1_get, debug_module_mem_server_arready, debug_module_mem_server_awready, debug_module_mem_server_bvalid, @@ -966,11 +896,9 @@ module mkProc(CLK, wire [3 : 0] llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1, llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1, llc_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read, - llc_axi4_adapter_ctr_wr_rsps_pending_crg$port3__read, mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1, mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1, - mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read, - mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port3__read; + mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read; wire llc_axi4_adapter_master_xactor_crg_rd_addr_full$EN_port1__write, llc_axi4_adapter_master_xactor_crg_rd_addr_full$port2__read, llc_axi4_adapter_master_xactor_crg_rd_addr_full$port3__read, @@ -1074,8 +1002,8 @@ module mkProc(CLK, wire llc_axi4_adapter_master_xactor_rg_wr_addr$EN; // register llc_axi4_adapter_master_xactor_rg_wr_data - reg [76 : 0] llc_axi4_adapter_master_xactor_rg_wr_data; - wire [76 : 0] llc_axi4_adapter_master_xactor_rg_wr_data$D_IN; + reg [72 : 0] llc_axi4_adapter_master_xactor_rg_wr_data; + wire [72 : 0] llc_axi4_adapter_master_xactor_rg_wr_data$D_IN; wire llc_axi4_adapter_master_xactor_rg_wr_data$EN; // register llc_axi4_adapter_master_xactor_rg_wr_resp @@ -1122,6 +1050,26 @@ module mkProc(CLK, reg llc_mem_server_propDstIdx_0_rl; wire llc_mem_server_propDstIdx_0_rl$D_IN, llc_mem_server_propDstIdx_0_rl$EN; + // register llc_mem_server_rg_cacheline_cache_addr + reg [63 : 0] llc_mem_server_rg_cacheline_cache_addr; + wire [63 : 0] llc_mem_server_rg_cacheline_cache_addr$D_IN; + wire llc_mem_server_rg_cacheline_cache_addr$EN; + + // register llc_mem_server_rg_cacheline_cache_data + reg [511 : 0] llc_mem_server_rg_cacheline_cache_data; + wire [511 : 0] llc_mem_server_rg_cacheline_cache_data$D_IN; + wire llc_mem_server_rg_cacheline_cache_data$EN; + + // register llc_mem_server_rg_cacheline_cache_dirty_delay + reg [9 : 0] llc_mem_server_rg_cacheline_cache_dirty_delay; + wire [9 : 0] llc_mem_server_rg_cacheline_cache_dirty_delay$D_IN; + wire llc_mem_server_rg_cacheline_cache_dirty_delay$EN; + + // register llc_mem_server_rg_cacheline_cache_state + reg [2 : 0] llc_mem_server_rg_cacheline_cache_state; + reg [2 : 0] llc_mem_server_rg_cacheline_cache_state$D_IN; + wire llc_mem_server_rg_cacheline_cache_state$EN; + // register mmioPlatform_amoResp reg [63 : 0] mmioPlatform_amoResp; wire [63 : 0] mmioPlatform_amoResp$D_IN; @@ -1322,8 +1270,8 @@ module mkProc(CLK, wire mmio_axi4_adapter_master_xactor_rg_wr_addr$EN; // register mmio_axi4_adapter_master_xactor_rg_wr_data - reg [76 : 0] mmio_axi4_adapter_master_xactor_rg_wr_data; - wire [76 : 0] mmio_axi4_adapter_master_xactor_rg_wr_data$D_IN; + reg [72 : 0] mmio_axi4_adapter_master_xactor_rg_wr_data; + wire [72 : 0] mmio_axi4_adapter_master_xactor_rg_wr_data$D_IN; wire mmio_axi4_adapter_master_xactor_rg_wr_data$EN; // register mmio_axi4_adapter_master_xactor_rg_wr_resp @@ -1382,7 +1330,6 @@ module mkProc(CLK, core_0$iCacheToParent_fromP_enq_x; wire [578 : 0] core_0$dCacheToParent_rsToP_first, core_0$iCacheToParent_rsToP_first; - wire [319 : 0] core_0$v_to_TV_0_get, core_0$v_to_TV_1_get; wire [141 : 0] core_0$mmioToPlatform_cRq_first; wire [76 : 0] core_0$hart0_csr_mem_server_request_put; wire [71 : 0] core_0$dCacheToParent_rqToP_first, @@ -1435,13 +1382,10 @@ module mkProc(CLK, core_0$EN_recvDoStats, core_0$EN_renameDebug_renameErr_get, core_0$EN_sendDoStats, - core_0$EN_setDEIP, core_0$EN_setMEIP, core_0$EN_setSEIP, core_0$EN_tlbToMem_memReq_deq, core_0$EN_tlbToMem_respLd_enq, - core_0$EN_v_to_TV_0_get, - core_0$EN_v_to_TV_1_get, core_0$RDY_coreIndInv_terminate, core_0$RDY_dCacheToParent_fromP_enq, core_0$RDY_dCacheToParent_rqToP_deq, @@ -1481,15 +1425,12 @@ module mkProc(CLK, core_0$RDY_tlbToMem_memReq_deq, core_0$RDY_tlbToMem_memReq_first, core_0$RDY_tlbToMem_respLd_enq, - core_0$RDY_v_to_TV_0_get, - core_0$RDY_v_to_TV_1_get, core_0$hart0_run_halt_server_request_put, core_0$hart0_run_halt_server_response_get, core_0$mmioToPlatform_cRq_notEmpty, core_0$mmioToPlatform_cRs_first, core_0$recvDoStats_x, core_0$sendDoStats, - core_0$setDEIP_v, core_0$setMEIP_v, core_0$setSEIP_v; @@ -1509,20 +1450,6 @@ module mkProc(CLK, enqDst_1_0_dummy2_1$EN, enqDst_1_0_dummy2_1$Q_OUT; - // ports of submodule f_reset_reqs - wire f_reset_reqs$CLR, - f_reset_reqs$DEQ, - f_reset_reqs$EMPTY_N, - f_reset_reqs$ENQ, - f_reset_reqs$FULL_N; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - // ports of submodule llc reg [644 : 0] llc$dma_memReq_enq_x; wire [640 : 0] llc$to_mem_toM_first; @@ -1603,7 +1530,7 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_f_wr_addr$FULL_N; // ports of submodule llc_mem_server_axi4_slave_xactor_f_wr_data - wire [76 : 0] llc_mem_server_axi4_slave_xactor_f_wr_data$D_IN, + wire [72 : 0] llc_mem_server_axi4_slave_xactor_f_wr_data$D_IN, llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT; wire llc_mem_server_axi4_slave_xactor_f_wr_data$CLR, llc_mem_server_axi4_slave_xactor_f_wr_data$DEQ, @@ -1631,13 +1558,10 @@ module mkProc(CLK, llc_mem_server_enqDst_0_dummy2_1$Q_OUT; // ports of submodule llc_mem_server_f_dword_in_line - wire [2 : 0] llc_mem_server_f_dword_in_line$D_IN, - llc_mem_server_f_dword_in_line$D_OUT; + wire [2 : 0] llc_mem_server_f_dword_in_line$D_IN; wire llc_mem_server_f_dword_in_line$CLR, llc_mem_server_f_dword_in_line$DEQ, - llc_mem_server_f_dword_in_line$EMPTY_N, - llc_mem_server_f_dword_in_line$ENQ, - llc_mem_server_f_dword_in_line$FULL_N; + llc_mem_server_f_dword_in_line$ENQ; // ports of submodule llc_mem_server_propDstData_0_dummy2_0 wire llc_mem_server_propDstData_0_dummy2_0$D_IN, @@ -1843,11 +1767,17 @@ module mkProc(CLK, CAN_FIRE_RL_llc_mem_server_enqDst_0_canon, CAN_FIRE_RL_llc_mem_server_propDstData_0_canon, CAN_FIRE_RL_llc_mem_server_propDstIdx_0_canon, - CAN_FIRE_RL_llc_mem_server_sendLdRespToMemLoader, + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish, + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld, + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st, + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged, + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_delay, + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish, + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss, + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss, + CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req, + CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req, CAN_FIRE_RL_llc_mem_server_sendLdRespToTlb, - CAN_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd, - CAN_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr, - CAN_FIRE_RL_llc_mem_server_sendStRespToMemLoader, CAN_FIRE_RL_llc_mem_server_sendStRespToTlb, CAN_FIRE_RL_llc_mem_server_sendTlbReqToLLC, CAN_FIRE_RL_llc_mem_server_srcPropose, @@ -1901,7 +1831,6 @@ module mkProc(CLK, CAN_FIRE_RL_rl_dummy7, CAN_FIRE_RL_rl_dummy8, CAN_FIRE_RL_rl_dummy9, - CAN_FIRE_RL_rl_reset, CAN_FIRE_RL_rl_terminate, CAN_FIRE_RL_rl_tohost, CAN_FIRE_RL_sendPRq, @@ -1912,7 +1841,6 @@ module mkProc(CLK, CAN_FIRE_RL_srcPropose_1, CAN_FIRE_RL_srcPropose_2, CAN_FIRE_RL_srcPropose_3, - CAN_FIRE_debug_external_interrupt_req, CAN_FIRE_debug_module_mem_server_m_arvalid, CAN_FIRE_debug_module_mem_server_m_awvalid, CAN_FIRE_debug_module_mem_server_m_bready, @@ -1927,8 +1855,6 @@ module mkProc(CLK, CAN_FIRE_hart0_put_other_req_put, CAN_FIRE_hart0_run_halt_server_request_put, CAN_FIRE_hart0_run_halt_server_response_get, - CAN_FIRE_hart0_server_reset_request_put, - CAN_FIRE_hart0_server_reset_response_get, CAN_FIRE_m_external_interrupt_req, CAN_FIRE_master0_m_arready, CAN_FIRE_master0_m_awready, @@ -1944,8 +1870,6 @@ module mkProc(CLK, CAN_FIRE_s_external_interrupt_req, CAN_FIRE_set_verbosity, CAN_FIRE_start, - CAN_FIRE_v_to_TV_0_get, - CAN_FIRE_v_to_TV_1_get, WILL_FIRE_RL_broadcastStats, WILL_FIRE_RL_doEnq, WILL_FIRE_RL_doEnq_1, @@ -1962,11 +1886,17 @@ module mkProc(CLK, WILL_FIRE_RL_llc_mem_server_enqDst_0_canon, WILL_FIRE_RL_llc_mem_server_propDstData_0_canon, WILL_FIRE_RL_llc_mem_server_propDstIdx_0_canon, - WILL_FIRE_RL_llc_mem_server_sendLdRespToMemLoader, + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish, + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld, + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st, + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged, + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_delay, + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish, + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss, + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss, + WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req, + WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req, WILL_FIRE_RL_llc_mem_server_sendLdRespToTlb, - WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd, - WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr, - WILL_FIRE_RL_llc_mem_server_sendStRespToMemLoader, WILL_FIRE_RL_llc_mem_server_sendStRespToTlb, WILL_FIRE_RL_llc_mem_server_sendTlbReqToLLC, WILL_FIRE_RL_llc_mem_server_srcPropose, @@ -2020,7 +1950,6 @@ module mkProc(CLK, WILL_FIRE_RL_rl_dummy7, WILL_FIRE_RL_rl_dummy8, WILL_FIRE_RL_rl_dummy9, - WILL_FIRE_RL_rl_reset, WILL_FIRE_RL_rl_terminate, WILL_FIRE_RL_rl_tohost, WILL_FIRE_RL_sendPRq, @@ -2031,7 +1960,6 @@ module mkProc(CLK, WILL_FIRE_RL_srcPropose_1, WILL_FIRE_RL_srcPropose_2, WILL_FIRE_RL_srcPropose_3, - WILL_FIRE_debug_external_interrupt_req, WILL_FIRE_debug_module_mem_server_m_arvalid, WILL_FIRE_debug_module_mem_server_m_awvalid, WILL_FIRE_debug_module_mem_server_m_bready, @@ -2046,8 +1974,6 @@ module mkProc(CLK, WILL_FIRE_hart0_put_other_req_put, WILL_FIRE_hart0_run_halt_server_request_put, WILL_FIRE_hart0_run_halt_server_response_get, - WILL_FIRE_hart0_server_reset_request_put, - WILL_FIRE_hart0_server_reset_response_get, WILL_FIRE_m_external_interrupt_req, WILL_FIRE_master0_m_arready, WILL_FIRE_master0_m_awready, @@ -2062,18 +1988,18 @@ module mkProc(CLK, WILL_FIRE_non_maskable_interrupt_req, WILL_FIRE_s_external_interrupt_req, WILL_FIRE_set_verbosity, - WILL_FIRE_start, - WILL_FIRE_v_to_TV_0_get, - WILL_FIRE_v_to_TV_1_get; + WILL_FIRE_start; // inputs to muxes for submodule ports reg [1 : 0] MUX_mmioPlatform_state$write_1__VAL_3, MUX_mmioPlatform_state$write_1__VAL_4; wire [644 : 0] MUX_llc$dma_memReq_enq_1__VAL_1, MUX_llc$dma_memReq_enq_1__VAL_2, - MUX_llc$dma_memReq_enq_1__VAL_3; + MUX_llc$dma_memReq_enq_1__VAL_3, + MUX_llc$dma_memReq_enq_1__VAL_4; wire [582 : 0] MUX_core_0$dCacheToParent_fromP_enq_1__VAL_1, MUX_core_0$dCacheToParent_fromP_enq_1__VAL_2; + wire [511 : 0] MUX_llc_mem_server_rg_cacheline_cache_data$write_1__VAL_1; wire [141 : 0] MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_1, MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_2, MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_3, @@ -2097,6 +2023,7 @@ module mkProc(CLK, wire [38 : 0] MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_2, MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_3, MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_4; + wire [9 : 0] MUX_llc_mem_server_rg_cacheline_cache_dirty_delay$write_1__VAL_2; wire [6 : 0] MUX_mmioPlatform_cycle$write_1__VAL_1; wire [1 : 0] MUX_mmioPlatform_state$write_1__VAL_1, MUX_mmioPlatform_state$write_1__VAL_2, @@ -2111,7 +2038,8 @@ module mkProc(CLK, MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_4, MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_5, MUX_llc$dma_memReq_enq_1__SEL_1, - MUX_llc$dma_memReq_enq_1__SEL_2, + MUX_llc_mem_server_rg_cacheline_cache_state$write_1__SEL_2, + MUX_llc_mem_server_rg_cacheline_cache_state$write_1__SEL_3, MUX_mmioPlatform_amoResp$write_1__SEL_1, MUX_mmioPlatform_amoResp$write_1__SEL_2, MUX_mmioPlatform_curReq$write_1__SEL_1, @@ -2127,315 +2055,295 @@ module mkProc(CLK, // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h152458; - reg [31 : 0] v__h4189; - reg [31 : 0] v__h4362; - reg [31 : 0] v__h4626; - reg [31 : 0] v__h6665; - reg [31 : 0] v__h2465; - reg [31 : 0] v__h6966; - reg [31 : 0] v__h7459; - reg [31 : 0] v__h7622; - reg [31 : 0] v__h94627; - reg [31 : 0] v__h94672; - reg [31 : 0] v__h94582; - reg [31 : 0] v__h105664; - reg [31 : 0] v__h105619; - reg [31 : 0] v__h124262; - reg [31 : 0] v__h124429; - reg [31 : 0] v__h126532; - reg [31 : 0] v__h143878; - reg [31 : 0] v__h123643; - reg [31 : 0] v__h150573; - reg [31 : 0] v__h151081; - reg [31 : 0] v__h2459; - reg [31 : 0] v__h4183; - reg [31 : 0] v__h4356; - reg [31 : 0] v__h4620; - reg [31 : 0] v__h6659; - reg [31 : 0] v__h6960; - reg [31 : 0] v__h7453; - reg [31 : 0] v__h7616; - reg [31 : 0] v__h94576; - reg [31 : 0] v__h94621; - reg [31 : 0] v__h94666; - reg [31 : 0] v__h105613; - reg [31 : 0] v__h105658; - reg [31 : 0] v__h123637; - reg [31 : 0] v__h124256; - reg [31 : 0] v__h124423; - reg [31 : 0] v__h126526; - reg [31 : 0] v__h143872; - reg [31 : 0] v__h150567; - reg [31 : 0] v__h151075; - reg [31 : 0] v__h152452; + reg [31 : 0] v__h160855; + reg [31 : 0] v__h160396; + reg [31 : 0] v__h3984; + reg [31 : 0] v__h4157; + reg [31 : 0] v__h4421; + reg [31 : 0] v__h6458; + reg [31 : 0] v__h2260; + reg [31 : 0] v__h6758; + reg [31 : 0] v__h7251; + reg [31 : 0] v__h7414; + reg [31 : 0] v__h132353; + reg [31 : 0] v__h132520; + reg [31 : 0] v__h134623; + reg [31 : 0] v__h151967; + reg [31 : 0] v__h131734; + reg [31 : 0] v__h158661; + reg [31 : 0] v__h159169; + reg [31 : 0] v__h2254; + reg [31 : 0] v__h3978; + reg [31 : 0] v__h4151; + reg [31 : 0] v__h4415; + reg [31 : 0] v__h6452; + reg [31 : 0] v__h6752; + reg [31 : 0] v__h7245; + reg [31 : 0] v__h7408; + reg [31 : 0] v__h131728; + reg [31 : 0] v__h132347; + reg [31 : 0] v__h132514; + reg [31 : 0] v__h134617; + reg [31 : 0] v__h151961; + reg [31 : 0] v__h158655; + reg [31 : 0] v__h159163; + reg [31 : 0] v__h160390; + reg [31 : 0] v__h160849; // synopsys translate_on // remaining internal signals - reg [63 : 0] CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13, - CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14, - CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17, - CASE_x7786_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24, - CASE_x7786_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25, - CASE_x7786_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26, - CASE_x7786_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27, - CASE_x7786_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28, - CASE_x7786_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29, - CASE_x7786_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30, - CASE_x7786_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31, - CASE_x7786_0_n__read_addr7964_1_n__read_addr80_ETC__q34, - CASE_x8979_0_n__read_addr9161_1_n__read_addr92_ETC__q23, - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d774, - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d787, - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d826, - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d838, - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d908, - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d917, - IF_mmioPlatform_reqAmofunc_49_EQ_0_50_THEN_IF__ETC___d884, - IF_mmioPlatform_reqSz_44_EQ_0b10_51_THEN_SEXT__ETC___d852, - IF_mmioPlatform_reqSz_44_EQ_0b10_51_THEN_SEXT__ETC___d854, - data64__h137702, - ld_data__h121714, - rd_data_rdata__h120163, - w1__h45579, - w1__h45584, - w2__h45580, - w2__h45586, - x__h45575; - reg [31 : 0] SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d952; - reg [11 : 0] CASE_core_0v_to_TV_0_get_BITS_153_TO_142_1_co_ETC__q5, - CASE_core_0v_to_TV_1_get_BITS_153_TO_142_1_co_ETC__q1; - reg [7 : 0] strb8__h137703; - reg [5 : 0] IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_ETC___d442; - reg [3 : 0] CASE_core_0v_to_TV_0_get_BITS_139_TO_136_0_co_ETC__q6, - CASE_core_0v_to_TV_0_get_BITS_139_TO_136_0_co_ETC__q7, - CASE_core_0v_to_TV_1_get_BITS_139_TO_136_0_co_ETC__q2, - CASE_core_0v_to_TV_1_get_BITS_139_TO_136_0_co_ETC__q3; - reg [2 : 0] x__h59293; - reg [1 : 0] CASE_core_0v_to_TV_0_get_BITS_71_TO_70_0_core_ETC__q8, - CASE_core_0v_to_TV_1_get_BITS_71_TO_70_0_core_ETC__q4, - CASE_x7786_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32, - CASE_x8979_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21, - CASE_x8979_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22; - reg CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q18, - CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q19, - CASE_x7786_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33, - CASE_x8979_0_propDstData_0_dummy2_1_read__065__ETC__q20, - SEL_ARR_propDstIdx_0_dummy2_1_read__027_AND_IF_ETC___d1058, - SEL_ARR_propDstIdx_1_0_dummy2_1_read__291_AND__ETC___d1332, - x__h59300, - x__h80202; - wire [579 : 0] IF_enqDst_1_0_lat_1_whas__236_THEN_enqDst_1_0__ETC___d1283; - wire [515 : 0] SEL_ARR_IF_propDstData_1_0_dummy2_1_read__339__ETC___d1431; - wire [513 : 0] IF_enqDst_1_0_lat_1_whas__236_THEN_enqDst_1_0__ETC___d1282; - wire [511 : 0] IF_enqDst_1_0_lat_0_whas__239_THEN_enqDst_1_0__ETC___d1274, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__163_THE_ETC___d1424, - new_cline__h124565; - wire [383 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__163_THE_ETC___d1407; - wire [255 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__163_THE_ETC___d1390; - wire [127 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__163_THE_ETC___d1373; - wire [66 : 0] IF_core_0_mmioToPlatform_cRq_first__43_BITS_14_ETC___d366; - wire [65 : 0] DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_01_BIT_ETC___d645; - wire [64 : 0] IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_2_ETC___d687; - wire [63 : 0] IF_enqDst_1_0_lat_0_whas__239_THEN_enqDst_1_0__ETC___d1254, - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d794, - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d845, - IF_mmioPlatform_reqBE_04_BIT_4_05_THEN_SEXT_mm_ETC___d538, - IF_mmioPlatform_reqBE_04_BIT_4_05_THEN_SEXT_mm_ETC___d602, - IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d513, - IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d575, - IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d679, - IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_1_ETC___d539, - IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_1_ETC___d603, - IF_propDstData_1_0_lat_0_whas__163_THEN_propDs_ETC___d1168, - IF_propDstData_1_1_lat_0_whas__201_THEN_propDs_ETC___d1206, - data__h29436, - failed_testnum__h152501, - line_addr__h105593, - mem_req_rd_addr_araddr__h123863, - mem_req_wr_addr_awaddr__h137787, - mmioPlatform_fromHostQ_data_0__h40231, - mmioPlatform_mtime__h34750, - mmioPlatform_reqData__h46171, - n__read_addr__h59161, - n__read_addr__h59246, - n__read_addr__h77964, - n__read_addr__h78043, - n__read_snd_addr__h92909, - newData__h29517, - newData__h32447, - op_result__h46187, - op_result__h46717, - op_result__h46722, - op_result__h46727, - op_result__h46732, - op_result__h46738, - op_result__h46745, - op_result__h46751, - req_addr__h94733, + reg [63 : 0] CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5, + CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6, + CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9, + CASE_x7578_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16, + CASE_x7578_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17, + CASE_x7578_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18, + CASE_x7578_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19, + CASE_x7578_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20, + CASE_x7578_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21, + CASE_x7578_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22, + CASE_x7578_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23, + CASE_x7578_0_n__read_addr7756_1_n__read_addr78_ETC__q26, + CASE_x8771_0_n__read_addr8953_1_n__read_addr90_ETC__q15, + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d773, + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d786, + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d825, + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d837, + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d907, + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d916, + IF_mmioPlatform_reqAmofunc_48_EQ_0_49_THEN_IF__ETC___d883, + IF_mmioPlatform_reqSz_43_EQ_0b10_50_THEN_SEXT__ETC___d851, + IF_mmioPlatform_reqSz_43_EQ_0b10_50_THEN_SEXT__ETC___d853, + data64__h145793, + dword__h91660, + ld_data__h129909, + old_dword__h87350, + w1__h45371, + w1__h45376, + w2__h45372, + w2__h45378, + x__h45367; + reg [31 : 0] SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d951; + reg [7 : 0] strb8__h145794; + reg [5 : 0] IF_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_ETC___d441; + reg [2 : 0] x__h59085; + reg [1 : 0] CASE_x7578_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24, + CASE_x8771_0_IF_propDstData_0_dummy2_1_read__0_ETC__q13, + CASE_x8771_0_IF_propDstData_0_dummy2_1_read__0_ETC__q14; + reg CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q10, + CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q11, + CASE_x7578_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25, + CASE_x8771_0_propDstData_0_dummy2_1_read__064__ETC__q12, + SEL_ARR_propDstIdx_0_dummy2_1_read__026_AND_IF_ETC___d1057, + SEL_ARR_propDstIdx_1_0_dummy2_1_read__290_AND__ETC___d1331, + x__h59092, + x__h79994; + wire [579 : 0] IF_enqDst_1_0_lat_1_whas__235_THEN_enqDst_1_0__ETC___d1282; + wire [515 : 0] SEL_ARR_IF_propDstData_1_0_dummy2_1_read__338__ETC___d1430; + wire [513 : 0] IF_enqDst_1_0_lat_1_whas__235_THEN_enqDst_1_0__ETC___d1281; + wire [511 : 0] IF_enqDst_1_0_lat_0_whas__238_THEN_enqDst_1_0__ETC___d1273, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__162_THE_ETC___d1423, + new_cline__h132656; + wire [383 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1561, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__162_THE_ETC___d1406; + wire [255 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1556, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__162_THE_ETC___d1389; + wire [127 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__162_THE_ETC___d1372; + wire [66 : 0] IF_core_0_mmioToPlatform_cRq_first__42_BITS_14_ETC___d365; + wire [65 : 0] DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_00_BIT_ETC___d644; + wire [64 : 0] IF_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_2_ETC___d686; + wire [63 : 0] IF_enqDst_1_0_lat_0_whas__238_THEN_enqDst_1_0__ETC___d1253, + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d793, + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d844, + IF_mmioPlatform_reqBE_03_BIT_4_04_THEN_SEXT_mm_ETC___d537, + IF_mmioPlatform_reqBE_03_BIT_4_04_THEN_SEXT_mm_ETC___d601, + IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d512, + IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d574, + IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d678, + IF_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_1_ETC___d538, + IF_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_1_ETC___d602, + IF_propDstData_1_0_lat_0_whas__162_THEN_propDs_ETC___d1167, + IF_propDstData_1_1_lat_0_whas__200_THEN_propDs_ETC___d1205, + data__h29228, + failed_testnum__h160439, + line_addr__h99724, + line_addr__h99810, + mask__h87347, + mem_req_rd_addr_araddr__h131954, + mem_req_wr_addr_awaddr__h145878, + mmioPlatform_fromHostQ_data_0__h40023, + mmioPlatform_mtime__h34542, + mmioPlatform_reqData__h45963, + n__read_addr__h58953, + n__read_addr__h59038, + n__read_addr__h77756, + n__read_addr__h77835, + n__read_snd_addr__h121251, + newData__h29309, + newData__h32239, + new_dword__h87351, + op_result__h45979, + op_result__h46509, + op_result__h46514, + op_result__h46519, + op_result__h46524, + op_result__h46530, + op_result__h46537, + op_result__h46543, + result__h45422, + result__h45546, + result__h45574, + result__h45602, result__h45630, - result__h45754, - result__h45782, - result__h45810, - result__h45838, - result__h45866, - result__h45894, - result__h45922, - result__h45950, - result__h45995, - result__h46023, - result__h46051, - result__h46079, + result__h45658, + result__h45686, + result__h45714, + result__h45742, + result__h45787, + result__h45815, + result__h45843, + result__h45871, + result__h45912, + result__h45940, + result__h46066, + result__h46093, result__h46120, - result__h46148, - result__h46274, - result__h46301, - result__h46328, - result__h46355, - result__h46382, - result__h46409, - result__h46436, - result__h46463, - result__h46507, - result__h46534, - result__h46561, - result__h46588, - result__h46628, - result__h46655, - result__h46772, - result__h46838, - result__h46904, - result__h46970, - result__h47036, - result__h47102, - result__h47168, - result__h47230, - result__h47275, - result__h47341, - result__h47407, - result__h47465, - result__h47510, - w1___1__h45689, - w2___1__h45690, - x1_avValue_data__h37903, - x1_avValue_data__h42508, - x__h29628, - x__h32538, - x__h34898, - x__h38421, - x__h38432, - x__h40487, - x__h40498, - x__h47687; - wire [47 : 0] IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d505, - IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d570, - IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d674; - wire [31 : 0] IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d496, - IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d565, - IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d669, - IF_mmio_axi4_adapter_f_rsps_to_core_first__25__ETC___d960, - mmioPlatform_mtime_BITS_31_TO_0__q12, - mmioPlatform_mtime_BITS_63_TO_32__q11, - mmioPlatform_mtimecmp_0_BITS_31_TO_0__q10, - mmioPlatform_mtimecmp_0_BITS_63_TO_32__q9, - v__h29229, - v__h29266, - w15579_BITS_31_TO_0__q15, - w25580_BITS_31_TO_0__q16, - x_data__h28019; - wire [8 : 0] SEL_ARR_IF_propDstData_0_dummy2_1_read__065_TH_ETC___d1129; - wire [5 : 0] x__h123898, x__h137812; - wire [4 : 0] SEL_ARR_propDstData_0_dummy2_1_read__065_AND_I_ETC___d1128; - wire [3 : 0] b__h123570, b__h2359; - wire [2 : 0] n__read_id__h59165, n__read_id__h59250; - wire [1 : 0] IF_enqDst_1_0_lat_0_whas__239_THEN_enqDst_1_0__ETC___d1259, - IF_propDstData_0_dummy2_1_read__065_THEN_IF_pr_ETC___d1081, - IF_propDstData_0_dummy2_1_read__065_THEN_IF_pr_ETC___d1091, - IF_propDstData_1_0_lat_0_whas__163_THEN_propDs_ETC___d1173, - IF_propDstData_1_1_lat_0_whas__201_THEN_propDs_ETC___d1211, - IF_propDstData_1_dummy2_1_read__070_THEN_IF_pr_ETC___d1085, - IF_propDstData_1_dummy2_1_read__070_THEN_IF_pr_ETC___d1095; - wire IF_IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4__ETC___d520, - IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d417, - IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515, - IF_NOT_propDstIdx_0_dummy2_1_read__027_028_OR__ETC___d1062, - IF_NOT_propDstIdx_1_0_dummy2_1_read__291_292_O_ETC___d1336, - IF_SEL_ARR_propDstIdx_0_dummy2_1_read__027_AND_ETC___d1134, - IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__291_A_ETC___d1436, - IF_enqDst_0_lat_0_whas__003_THEN_enqDst_0_lat__ETC___d1008, - IF_enqDst_1_0_lat_0_whas__239_THEN_enqDst_1_0__ETC___d1244, - IF_enqDst_1_0_lat_0_whas__239_THEN_enqDst_1_0__ETC___d1264, - IF_enqDst_1_0_lat_0_whas__239_THEN_enqDst_1_0__ETC___d1280, - IF_llc_mem_server_enqDst_0_lat_0_whas__500_THE_ETC___d1505, - IF_llc_mem_server_propDstIdx_0_lat_0_whas__485_ETC___d1488, - IF_mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioP_ETC___d586, - IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_ETC___d418, - IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__56__ETC___d165, - IF_mmioPlatform_waitLowerMSIPCRs_53_THEN_core__ETC___d461, - IF_mmio_axi4_adapter_f_rsps_to_core_first__25__ETC___d939, - IF_propDstData_1_0_lat_0_whas__163_THEN_propDs_ETC___d1194, - IF_propDstData_1_1_lat_0_whas__201_THEN_propDs_ETC___d1232, - IF_propDstIdx_0_lat_0_whas__74_THEN_propDstIdx_ETC___d977, - IF_propDstIdx_1_0_lat_0_whas__148_THEN_propDst_ETC___d1151, - IF_propDstIdx_1_1_lat_0_whas__155_THEN_propDst_ETC___d1158, - IF_propDstIdx_1_lat_0_whas__81_THEN_propDstIdx_ETC___d984, - NOT_enqDst_0_dummy2_0_read__048_049_OR_NOT_enq_ETC___d1064, - NOT_enqDst_1_0_dummy2_0_read__322_323_OR_NOT_e_ETC___d1338, - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785, - NOT_llc_mem_server_enqDst_0_dummy2_0_read__531_ETC___d1538, - NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d715, - NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d723, - NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d728, - NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d738, - NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d929, - NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d942, - NOT_mmioPlatform_fromHostQ_clearReq_dummy2_1_r_ETC___d283, - NOT_mmioPlatform_fromHostQ_enqReq_dummy2_2_rea_ETC___d304, - NOT_mmioPlatform_mtip_0_20_27_AND_mmioPlatform_ETC___d335, - NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ__ETC___d451, - NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ__ETC___d546, - NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ__ETC___d609, - NOT_mmioPlatform_toHostQ_clearReq_dummy2_1_rea_ETC___d205, - NOT_mmioPlatform_toHostQ_enqReq_dummy2_2_read__ETC___d226, - NOT_propDstData_1_0_dummy2_1_read__339_350_OR__ETC___d1351, - NOT_propDstData_1_1_dummy2_1_read__341_352_OR__ETC___d1353, - NOT_propDstIdx_0_dummy2_1_read__027_028_OR_IF__ETC___d1061, - NOT_propDstIdx_1_0_dummy2_1_read__291_292_OR_I_ETC___d1335, - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1605, - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1644, - mmioPlatform_cycle_12_ULT_99___d313, - mmioPlatform_fetchingWay_34_ULT_mmioPlatform_r_ETC___d944, - mmioPlatform_fromHostQ_enqReq_dummy2_2_read__8_ETC___d296, - mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577, - mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322, - mmioPlatform_reqBE_BIT_0___h27644, - mmioPlatform_reqBE_BIT_4___h27604, - mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_03_ETC___d428, - mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_03_ETC___d532, - mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_03_ETC___d597, - mmioPlatform_toHostQ_enqReq_dummy2_2_read__06__ETC___d218, - n__read_child__h59166, - n__read_child__h59251, - n__read_child__h77967, - n__read_child__h78046, - n__read_snd_id__h92910, - propDstData_0_dummy2_1_read__065_AND_IF_propDs_ETC___d1101, - propDstData_1_dummy2_1_read__070_AND_IF_propDs_ETC___d1105, - x__h58979, - x__h72715, - x__h77786; - - // action method hart0_server_reset_request_put - assign RDY_hart0_server_reset_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_hart0_server_reset_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_hart0_server_reset_request_put = - EN_hart0_server_reset_request_put ; - - // action method hart0_server_reset_response_get - assign RDY_hart0_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_hart0_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_hart0_server_reset_response_get = - EN_hart0_server_reset_response_get ; + result__h46147, + result__h46174, + result__h46201, + result__h46228, + result__h46255, + result__h46299, + result__h46326, + result__h46353, + result__h46380, + result__h46420, + result__h46447, + result__h46564, + result__h46630, + result__h46696, + result__h46762, + result__h46828, + result__h46894, + result__h46960, + result__h47022, + result__h47067, + result__h47133, + result__h47199, + result__h47257, + result__h47302, + w1___1__h45481, + w2___1__h45482, + x1_avValue_data__h37695, + x1_avValue_data__h42300, + x__h29420, + x__h32330, + x__h34690, + x__h38213, + x__h38224, + x__h40279, + x__h40290, + x__h47479, + x__h88513, + y__h88514, + y__h88515; + wire [47 : 0] IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d504, + IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d569, + IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d673; + wire [31 : 0] IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d495, + IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d564, + IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d668, + IF_mmio_axi4_adapter_f_rsps_to_core_first__24__ETC___d959, + mmioPlatform_mtime_BITS_31_TO_0__q4, + mmioPlatform_mtime_BITS_63_TO_32__q3, + mmioPlatform_mtimecmp_0_BITS_31_TO_0__q2, + mmioPlatform_mtimecmp_0_BITS_63_TO_32__q1, + v__h29021, + v__h29058, + w15371_BITS_31_TO_0__q7, + w25372_BITS_31_TO_0__q8, + x_data__h27811; + wire [8 : 0] SEL_ARR_IF_propDstData_0_dummy2_1_read__064_TH_ETC___d1128; + wire [5 : 0] x__h131989, x__h145903; + wire [4 : 0] SEL_ARR_propDstData_0_dummy2_1_read__064_AND_I_ETC___d1127; + wire [3 : 0] b__h131661, b__h2154; + wire [2 : 0] n__read_id__h58957, n__read_id__h59042; + wire [1 : 0] IF_enqDst_1_0_lat_0_whas__238_THEN_enqDst_1_0__ETC___d1258, + IF_propDstData_0_dummy2_1_read__064_THEN_IF_pr_ETC___d1080, + IF_propDstData_0_dummy2_1_read__064_THEN_IF_pr_ETC___d1090, + IF_propDstData_1_0_lat_0_whas__162_THEN_propDs_ETC___d1172, + IF_propDstData_1_1_lat_0_whas__200_THEN_propDs_ETC___d1210, + IF_propDstData_1_dummy2_1_read__069_THEN_IF_pr_ETC___d1084, + IF_propDstData_1_dummy2_1_read__069_THEN_IF_pr_ETC___d1094; + wire IF_IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4__ETC___d519, + IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01__ETC___d416, + IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01__ETC___d514, + IF_NOT_propDstIdx_0_dummy2_1_read__026_027_OR__ETC___d1061, + IF_NOT_propDstIdx_1_0_dummy2_1_read__290_291_O_ETC___d1335, + IF_SEL_ARR_propDstIdx_0_dummy2_1_read__026_AND_ETC___d1133, + IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__290_A_ETC___d1435, + IF_enqDst_0_lat_0_whas__002_THEN_enqDst_0_lat__ETC___d1007, + IF_enqDst_1_0_lat_0_whas__238_THEN_enqDst_1_0__ETC___d1243, + IF_enqDst_1_0_lat_0_whas__238_THEN_enqDst_1_0__ETC___d1263, + IF_enqDst_1_0_lat_0_whas__238_THEN_enqDst_1_0__ETC___d1279, + IF_llc_mem_server_enqDst_0_lat_0_whas__641_THE_ETC___d1646, + IF_llc_mem_server_propDstIdx_0_lat_0_whas__626_ETC___d1629, + IF_mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioP_ETC___d585, + IF_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_ETC___d417, + IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__55__ETC___d164, + IF_mmioPlatform_waitLowerMSIPCRs_52_THEN_core__ETC___d460, + IF_mmio_axi4_adapter_f_rsps_to_core_first__24__ETC___d938, + IF_propDstData_1_0_lat_0_whas__162_THEN_propDs_ETC___d1193, + IF_propDstData_1_1_lat_0_whas__200_THEN_propDs_ETC___d1231, + IF_propDstIdx_0_lat_0_whas__73_THEN_propDstIdx_ETC___d976, + IF_propDstIdx_1_0_lat_0_whas__147_THEN_propDst_ETC___d1150, + IF_propDstIdx_1_1_lat_0_whas__154_THEN_propDst_ETC___d1157, + IF_propDstIdx_1_lat_0_whas__80_THEN_propDstIdx_ETC___d983, + NOT_enqDst_0_dummy2_0_read__047_048_OR_NOT_enq_ETC___d1063, + NOT_enqDst_1_0_dummy2_0_read__321_322_OR_NOT_e_ETC___d1337, + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763, + NOT_llc_mem_server_enqDst_0_dummy2_0_read__672_ETC___d1679, + NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d714, + NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d722, + NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d727, + NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d737, + NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d928, + NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d941, + NOT_mmioPlatform_fromHostQ_clearReq_dummy2_1_r_ETC___d282, + NOT_mmioPlatform_fromHostQ_enqReq_dummy2_2_rea_ETC___d303, + NOT_mmioPlatform_mtip_0_19_26_AND_mmioPlatform_ETC___d334, + NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ__ETC___d450, + NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ__ETC___d545, + NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ__ETC___d608, + NOT_mmioPlatform_toHostQ_clearReq_dummy2_1_rea_ETC___d204, + NOT_mmioPlatform_toHostQ_enqReq_dummy2_2_read__ETC___d225, + NOT_propDstData_1_0_dummy2_1_read__338_349_OR__ETC___d1350, + NOT_propDstData_1_1_dummy2_1_read__340_351_OR__ETC___d1352, + NOT_propDstIdx_0_dummy2_1_read__026_027_OR_IF__ETC___d1060, + NOT_propDstIdx_1_0_dummy2_1_read__290_291_OR_I_ETC___d1334, + llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1573, + llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1495, + mmioPlatform_cycle_11_ULT_99___d312, + mmioPlatform_fetchingWay_33_ULT_mmioPlatform_r_ETC___d943, + mmioPlatform_fromHostQ_enqReq_dummy2_2_read__8_ETC___d295, + mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioPlat_ETC___d576, + mmioPlatform_mtimecmp_0_20_ULE_mmioPlatform_mt_ETC___d321, + mmioPlatform_reqBE_BIT_0___h27436, + mmioPlatform_reqBE_BIT_4___h27396, + mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_02_ETC___d427, + mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_02_ETC___d531, + mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_02_ETC___d596, + mmioPlatform_toHostQ_enqReq_dummy2_2_read__05__ETC___d217, + n__read_child__h58958, + n__read_child__h59043, + n__read_child__h77759, + n__read_child__h77838, + n__read_snd_id__h121252, + propDstData_0_dummy2_1_read__064_AND_IF_propDs_ETC___d1100, + propDstData_1_dummy2_1_read__069_AND_IF_propDs_ETC___d1104, + x__h58771, + x__h72507, + x__h77578; // action method start assign RDY_start = mmioPlatform_state == 2'd0 ; @@ -2482,9 +2390,6 @@ module mkProc(CLK, // value method master0_m_wvalid assign master0_wvalid = llc_axi4_adapter_master_xactor_crg_wr_data_full ; - // value method master0_m_wid - assign master0_wid = llc_axi4_adapter_master_xactor_rg_wr_data[76:73] ; - // value method master0_m_wdata assign master0_wdata = llc_axi4_adapter_master_xactor_rg_wr_data[72:9] ; @@ -2591,9 +2496,6 @@ module mkProc(CLK, // value method master1_m_wvalid assign master1_wvalid = mmio_axi4_adapter_master_xactor_crg_wr_data_full ; - // value method master1_m_wid - assign master1_wid = mmio_axi4_adapter_master_xactor_rg_wr_data[76:73] ; - // value method master1_m_wdata assign master1_wdata = mmio_axi4_adapter_master_xactor_rg_wr_data[72:9] ; @@ -2668,10 +2570,6 @@ module mkProc(CLK, assign CAN_FIRE_s_external_interrupt_req = 1'd1 ; assign WILL_FIRE_s_external_interrupt_req = 1'd1 ; - // action method debug_external_interrupt_req - assign CAN_FIRE_debug_external_interrupt_req = 1'd1 ; - assign WILL_FIRE_debug_external_interrupt_req = 1'd1 ; - // action method non_maskable_interrupt_req assign CAN_FIRE_non_maskable_interrupt_req = 1'd1 ; assign WILL_FIRE_non_maskable_interrupt_req = 1'd1 ; @@ -2822,46 +2720,6 @@ module mkProc(CLK, assign CAN_FIRE_hart0_put_other_req_put = 1'd1 ; assign WILL_FIRE_hart0_put_other_req_put = EN_hart0_put_other_req_put ; - // actionvalue method v_to_TV_0_get - assign v_to_TV_0_get = - { core_0$v_to_TV_0_get[319:154], - core_0$v_to_TV_0_get[154] ? - CASE_core_0v_to_TV_0_get_BITS_153_TO_142_1_co_ETC__q5 : - 12'hAAA, - core_0$v_to_TV_0_get[141], - core_0$v_to_TV_0_get[141] ? - { core_0$v_to_TV_0_get[140], - core_0$v_to_TV_0_get[140] ? - CASE_core_0v_to_TV_0_get_BITS_139_TO_136_0_co_ETC__q6 : - CASE_core_0v_to_TV_0_get_BITS_139_TO_136_0_co_ETC__q7 } : - 5'h0A, - core_0$v_to_TV_0_get[135:72], - CASE_core_0v_to_TV_0_get_BITS_71_TO_70_0_core_ETC__q8, - core_0$v_to_TV_0_get[69:0] } ; - assign RDY_v_to_TV_0_get = core_0$RDY_v_to_TV_0_get ; - assign CAN_FIRE_v_to_TV_0_get = core_0$RDY_v_to_TV_0_get ; - assign WILL_FIRE_v_to_TV_0_get = EN_v_to_TV_0_get ; - - // actionvalue method v_to_TV_1_get - assign v_to_TV_1_get = - { core_0$v_to_TV_1_get[319:154], - core_0$v_to_TV_1_get[154] ? - CASE_core_0v_to_TV_1_get_BITS_153_TO_142_1_co_ETC__q1 : - 12'hAAA, - core_0$v_to_TV_1_get[141], - core_0$v_to_TV_1_get[141] ? - { core_0$v_to_TV_1_get[140], - core_0$v_to_TV_1_get[140] ? - CASE_core_0v_to_TV_1_get_BITS_139_TO_136_0_co_ETC__q2 : - CASE_core_0v_to_TV_1_get_BITS_139_TO_136_0_co_ETC__q3 } : - 5'h0A, - core_0$v_to_TV_1_get[135:72], - CASE_core_0v_to_TV_1_get_BITS_71_TO_70_0_core_ETC__q4, - core_0$v_to_TV_1_get[69:0] } ; - assign RDY_v_to_TV_1_get = core_0$RDY_v_to_TV_1_get ; - assign CAN_FIRE_v_to_TV_1_get = core_0$RDY_v_to_TV_1_get ; - assign WILL_FIRE_v_to_TV_1_get = EN_v_to_TV_1_get ; - // submodule core_0 mkCore core_0(.CLK(CLK), .RST_N(RST_N), @@ -2880,7 +2738,6 @@ module mkProc(CLK, .mmioToPlatform_pRs_enq_x(core_0$mmioToPlatform_pRs_enq_x), .mmioToPlatform_setTime_t(core_0$mmioToPlatform_setTime_t), .recvDoStats_x(core_0$recvDoStats_x), - .setDEIP_v(core_0$setDEIP_v), .setMEIP_v(core_0$setMEIP_v), .setSEIP_v(core_0$setSEIP_v), .tlbToMem_respLd_enq_x(core_0$tlbToMem_respLd_enq_x), @@ -2915,7 +2772,6 @@ module mkProc(CLK, .EN_renameDebug_renameErr_get(core_0$EN_renameDebug_renameErr_get), .EN_setMEIP(core_0$EN_setMEIP), .EN_setSEIP(core_0$EN_setSEIP), - .EN_setDEIP(core_0$EN_setDEIP), .EN_hart0_run_halt_server_request_put(core_0$EN_hart0_run_halt_server_request_put), .EN_hart0_run_halt_server_response_get(core_0$EN_hart0_run_halt_server_response_get), .EN_hart0_gpr_mem_server_request_put(core_0$EN_hart0_gpr_mem_server_request_put), @@ -2924,8 +2780,6 @@ module mkProc(CLK, .EN_hart0_fpr_mem_server_response_get(core_0$EN_hart0_fpr_mem_server_response_get), .EN_hart0_csr_mem_server_request_put(core_0$EN_hart0_csr_mem_server_request_put), .EN_hart0_csr_mem_server_response_get(core_0$EN_hart0_csr_mem_server_response_get), - .EN_v_to_TV_0_get(core_0$EN_v_to_TV_0_get), - .EN_v_to_TV_1_get(core_0$EN_v_to_TV_1_get), .RDY_coreReq_start(), .RDY_coreReq_perfReq(), .coreIndInv_perfResp(), @@ -3006,7 +2860,6 @@ module mkProc(CLK, .RDY_renameDebug_renameErr_get(core_0$RDY_renameDebug_renameErr_get), .RDY_setMEIP(), .RDY_setSEIP(), - .RDY_setDEIP(), .RDY_hart0_run_halt_server_request_put(core_0$RDY_hart0_run_halt_server_request_put), .hart0_run_halt_server_response_get(core_0$hart0_run_halt_server_response_get), .RDY_hart0_run_halt_server_response_get(core_0$RDY_hart0_run_halt_server_response_get), @@ -3018,11 +2871,7 @@ module mkProc(CLK, .RDY_hart0_fpr_mem_server_response_get(core_0$RDY_hart0_fpr_mem_server_response_get), .RDY_hart0_csr_mem_server_request_put(core_0$RDY_hart0_csr_mem_server_request_put), .hart0_csr_mem_server_response_get(core_0$hart0_csr_mem_server_response_get), - .RDY_hart0_csr_mem_server_response_get(core_0$RDY_hart0_csr_mem_server_response_get), - .v_to_TV_0_get(core_0$v_to_TV_0_get), - .RDY_v_to_TV_0_get(core_0$RDY_v_to_TV_0_get), - .v_to_TV_1_get(core_0$v_to_TV_1_get), - .RDY_v_to_TV_1_get(core_0$RDY_v_to_TV_1_get)); + .RDY_hart0_csr_mem_server_response_get(core_0$RDY_hart0_csr_mem_server_response_get)); // submodule enqDst_0_dummy2_0 RevertReg #(.width(32'd1), .init(1'd1)) enqDst_0_dummy2_0(.CLK(CLK), @@ -3048,24 +2897,6 @@ module mkProc(CLK, .EN(enqDst_1_0_dummy2_1$EN), .Q_OUT(enqDst_1_0_dummy2_1$Q_OUT)); - // submodule f_reset_reqs - FIFO20 #(.guarded(32'd1)) f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_reqs$ENQ), - .DEQ(f_reset_reqs$DEQ), - .CLR(f_reset_reqs$CLR), - .FULL_N(f_reset_reqs$FULL_N), - .EMPTY_N(f_reset_reqs$EMPTY_N)); - - // submodule f_reset_rsps - FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - // submodule llc mkLLCache llc(.CLK(CLK), .RST_N(RST_N), @@ -3189,7 +3020,7 @@ module mkProc(CLK, .EMPTY_N(llc_mem_server_axi4_slave_xactor_f_wr_addr$EMPTY_N)); // submodule llc_mem_server_axi4_slave_xactor_f_wr_data - FIFO2 #(.width(32'd77), + FIFO2 #(.width(32'd73), .guarded(32'd1)) llc_mem_server_axi4_slave_xactor_f_wr_data(.RST(RST_N), .CLK(CLK), .D_IN(llc_mem_server_axi4_slave_xactor_f_wr_data$D_IN), @@ -3234,9 +3065,9 @@ module mkProc(CLK, .ENQ(llc_mem_server_f_dword_in_line$ENQ), .DEQ(llc_mem_server_f_dword_in_line$DEQ), .CLR(llc_mem_server_f_dword_in_line$CLR), - .D_OUT(llc_mem_server_f_dword_in_line$D_OUT), - .FULL_N(llc_mem_server_f_dword_in_line$FULL_N), - .EMPTY_N(llc_mem_server_f_dword_in_line$EMPTY_N)); + .D_OUT(), + .FULL_N(), + .EMPTY_N()); // submodule llc_mem_server_propDstData_0_dummy2_0 RevertReg #(.width(32'd1), @@ -3532,7 +3363,7 @@ module mkProc(CLK, // rule RL_doEnq assign CAN_FIRE_RL_doEnq = llc$RDY_to_child_rqFromC_enq && enqDst_0_dummy2_1$Q_OUT && - IF_enqDst_0_lat_0_whas__003_THEN_enqDst_0_lat__ETC___d1008 ; + IF_enqDst_0_lat_0_whas__002_THEN_enqDst_0_lat__ETC___d1007 ; assign WILL_FIRE_RL_doEnq = CAN_FIRE_RL_doEnq ; // rule RL_srcPropose_2 @@ -3560,7 +3391,7 @@ module mkProc(CLK, // rule RL_doEnq_1 assign CAN_FIRE_RL_doEnq_1 = llc$RDY_to_child_rsFromC_enq && enqDst_1_0_dummy2_1$Q_OUT && - IF_enqDst_1_0_lat_0_whas__239_THEN_enqDst_1_0__ETC___d1244 ; + IF_enqDst_1_0_lat_0_whas__238_THEN_enqDst_1_0__ETC___d1243 ; assign WILL_FIRE_RL_doEnq_1 = CAN_FIRE_RL_doEnq_1 ; // rule RL_sendPRq @@ -3671,13 +3502,13 @@ module mkProc(CLK, !mmio_axi4_adapter_master_xactor_crg_rd_addr_full$port2__read && mmio_axi4_adapter_f_reqs_from_core$EMPTY_N && mmio_axi4_adapter_f_reqs_from_core$D_OUT[77:76] == 2'd1 && - b__h2359 == 4'd0 ; + b__h2154 == 4'd0 ; assign WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req = CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req ; // rule RL_mmio_axi4_adapter_rl_discard_write_rsp assign CAN_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp = - b__h2359 != 4'd0 && + b__h2154 != 4'd0 && mmio_axi4_adapter_master_xactor_crg_wr_resp_full && (mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0 || mmio_axi4_adapter_f_rsps_to_core$FULL_N) ; @@ -3701,23 +3532,23 @@ module mkProc(CLK, // rule RL_mmioPlatform_incCycle assign CAN_FIRE_RL_mmioPlatform_incCycle = mmioPlatform_state != 2'd0 && - mmioPlatform_cycle_12_ULT_99___d313 ; + mmioPlatform_cycle_11_ULT_99___d312 ; assign WILL_FIRE_RL_mmioPlatform_incCycle = CAN_FIRE_RL_mmioPlatform_incCycle ; // rule RL_mmioPlatform_incTime assign CAN_FIRE_RL_mmioPlatform_incTime = mmioPlatform_state == 2'd1 && - !mmioPlatform_cycle_12_ULT_99___d313 ; + !mmioPlatform_cycle_11_ULT_99___d312 ; assign WILL_FIRE_RL_mmioPlatform_incTime = CAN_FIRE_RL_mmioPlatform_incTime ; // rule RL_mmioPlatform_selectReq assign CAN_FIRE_RL_mmioPlatform_selectReq = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322 || + !mmioPlatform_mtimecmp_0_20_ULE_mmioPlatform_mt_ETC___d321 || core_0$RDY_mmioToPlatform_pRq_enq) && - NOT_mmioPlatform_mtip_0_20_27_AND_mmioPlatform_ETC___d335 && + NOT_mmioPlatform_mtip_0_19_26_AND_mmioPlatform_ETC___d334 && mmioPlatform_state == 2'd1 ; assign WILL_FIRE_RL_mmioPlatform_selectReq = CAN_FIRE_RL_mmioPlatform_selectReq && @@ -3734,7 +3565,7 @@ module mkProc(CLK, // rule RL_mmioPlatform_processMSIP assign CAN_FIRE_RL_mmioPlatform_processMSIP = - IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_ETC___d418 && + IF_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_ETC___d417 && mmioPlatform_curReq[66:64] == 3'd2 && mmioPlatform_state == 2'd2 ; assign WILL_FIRE_RL_mmioPlatform_processMSIP = @@ -3743,7 +3574,7 @@ module mkProc(CLK, // rule RL_mmioPlatform_waitMSIPDone assign CAN_FIRE_RL_mmioPlatform_waitMSIPDone = core_0$RDY_mmioToPlatform_pRs_enq && - IF_mmioPlatform_waitLowerMSIPCRs_53_THEN_core__ETC___d461 && + IF_mmioPlatform_waitLowerMSIPCRs_52_THEN_core__ETC___d460 && mmioPlatform_curReq[66:64] == 3'd2 && mmioPlatform_state == 2'd3 ; assign WILL_FIRE_RL_mmioPlatform_waitMSIPDone = @@ -3751,7 +3582,7 @@ module mkProc(CLK, // rule RL_mmioPlatform_processMTimeCmp assign CAN_FIRE_RL_mmioPlatform_processMTimeCmp = - CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q18 && + CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q10 && mmioPlatform_curReq[66:64] == 3'd3 && mmioPlatform_state == 2'd2 ; assign WILL_FIRE_RL_mmioPlatform_processMTimeCmp = @@ -3768,7 +3599,7 @@ module mkProc(CLK, // rule RL_mmioPlatform_processMTime assign CAN_FIRE_RL_mmioPlatform_processMTime = - CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q19 && + CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q11 && mmioPlatform_state == 2'd2 && mmioPlatform_curReq[66:64] == 3'd4 ; assign WILL_FIRE_RL_mmioPlatform_processMTime = @@ -3789,7 +3620,7 @@ module mkProc(CLK, core_0$RDY_mmioToPlatform_pRs_enq && (mmioPlatform_reqFunc[5:4] != 2'd2 || !mmioPlatform_toHostQ_empty || - x__h40487 == 64'd0 || + x__h40279 == 64'd0 || !mmioPlatform_toHostQ_full) && mmioPlatform_state == 2'd2 && mmioPlatform_curReq[66:64] == 3'd5 ; @@ -3807,7 +3638,7 @@ module mkProc(CLK, // rule RL_mmioPlatform_rl_mmio_to_fabric_req assign CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req = mmio_axi4_adapter_f_reqs_from_core$FULL_N && - NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d715 ; + NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d714 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req = CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req ; @@ -3815,14 +3646,14 @@ module mkProc(CLK, assign CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp = core_0$RDY_mmioToPlatform_pRs_enq && mmio_axi4_adapter_f_rsps_to_core$EMPTY_N && - NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d723 ; + NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d722 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp = CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp ; // rule RL_mmioPlatform_rl_mmio_to_fabric_amo_req assign CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req = mmio_axi4_adapter_f_reqs_from_core$FULL_N && - NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d728 ; + NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d727 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req = CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req ; @@ -3832,22 +3663,22 @@ module mkProc(CLK, mmio_axi4_adapter_f_rsps_to_core$EMPTY_N && (!mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] || mmio_axi4_adapter_f_reqs_from_core$FULL_N) && - NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d738 ; + NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d737 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp = CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp ; // rule RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req assign CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req = mmio_axi4_adapter_f_reqs_from_core$FULL_N && - NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d929 ; + NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d928 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req = CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req ; // rule RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp assign CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp = mmio_axi4_adapter_f_rsps_to_core$EMPTY_N && - IF_mmio_axi4_adapter_f_rsps_to_core_first__25__ETC___d939 && - NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d942 ; + IF_mmio_axi4_adapter_f_rsps_to_core_first__24__ETC___d938 && + NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d941 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp = CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp ; @@ -3923,6 +3754,101 @@ module mkProc(CLK, assign CAN_FIRE_RL_enqDst_1_0_canon = 1'd1 ; assign WILL_FIRE_RL_enqDst_1_0_canon = 1'd1 ; + // rule RL_llc_mem_server_rl_handle_MemLoader_ld_req + assign CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req = + llc_mem_server_axi4_slave_xactor_f_rd_addr$EMPTY_N && + llc_mem_server_axi4_slave_xactor_f_rd_data$FULL_N && + (llc_mem_server_rg_cacheline_cache_state == 3'd3 || + llc_mem_server_rg_cacheline_cache_state == 3'd4) && + llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1573 ; + assign WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req = + CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req ; + + // rule RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_delay + assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_delay = + llc_mem_server_rg_cacheline_cache_state == 3'd4 && + llc_mem_server_rg_cacheline_cache_dirty_delay != 10'd0 ; + assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_delay = + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_delay ; + + // rule RL_llc_mem_server_rl_handle_MemLoader_st_req + assign CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req = + llc_mem_server_axi4_slave_xactor_f_wr_addr$EMPTY_N && + llc_mem_server_axi4_slave_xactor_f_wr_data$EMPTY_N && + llc_mem_server_axi4_slave_xactor_f_wr_resp$FULL_N && + (llc_mem_server_rg_cacheline_cache_state == 3'd3 || + llc_mem_server_rg_cacheline_cache_state == 3'd4) && + llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1495 ; + assign WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req = + CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ; + + // rule RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged + assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged = + llc$RDY_dma_memReq_enq && + llc_mem_server_rg_cacheline_cache_state == 3'd4 && + llc_mem_server_rg_cacheline_cache_dirty_delay == 10'd0 ; + assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged = + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged && + !WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ; + + // rule RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss + assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss = + llc$RDY_dma_memReq_enq && + llc_mem_server_axi4_slave_xactor_f_wr_addr$EMPTY_N && + llc_mem_server_rg_cacheline_cache_state == 3'd4 && + !llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1495 ; + assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss = + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss && + !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged ; + + // rule RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss + assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss = + llc$RDY_dma_memReq_enq && + llc_mem_server_axi4_slave_xactor_f_rd_addr$EMPTY_N && + llc_mem_server_rg_cacheline_cache_state == 3'd4 && + !llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1573 ; + assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss = + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss && + !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss && + !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged && + !WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ; + + // rule RL_llc_mem_server_rl_cacheline_cache_writeback_finish + assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish = + llc$RDY_dma_respSt_first && llc$RDY_dma_respSt_deq && + !llc$dma_respSt_first[4] && + llc_mem_server_rg_cacheline_cache_state == 3'd1 ; + assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish = + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish ; + + // rule RL_llc_mem_server_rl_cacheline_cache_reload_req_st + assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st = + llc$RDY_dma_memReq_enq && + llc_mem_server_axi4_slave_xactor_f_wr_addr$EMPTY_N && + llc_mem_server_rg_cacheline_cache_state == 3'd3 && + !llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1495 ; + assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st = + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ; + + // rule RL_llc_mem_server_rl_cacheline_cache_reload_req_ld + assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld = + llc$RDY_dma_memReq_enq && + llc_mem_server_axi4_slave_xactor_f_rd_addr$EMPTY_N && + llc_mem_server_rg_cacheline_cache_state == 3'd3 && + !llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1573 ; + assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld = + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld && + !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st && + !WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ; + + // rule RL_llc_mem_server_rl_cacheline_cache_reload_finish + assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish = + llc$RDY_dma_respLd_first && llc$RDY_dma_respLd_deq && + !llc$dma_respLd_first[4] && + llc_mem_server_rg_cacheline_cache_state == 3'd2 ; + assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish = + CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish ; + // rule RL_llc_mem_server_srcPropose assign CAN_FIRE_RL_llc_mem_server_srcPropose = core_0$RDY_tlbToMem_memReq_first && @@ -3941,64 +3867,20 @@ module mkProc(CLK, assign CAN_FIRE_RL_llc_mem_server_doEnq = llc_mem_server_tlbQ$FULL_N && llc_mem_server_enqDst_0_dummy2_1$Q_OUT && - IF_llc_mem_server_enqDst_0_lat_0_whas__500_THE_ETC___d1505 ; + IF_llc_mem_server_enqDst_0_lat_0_whas__641_THE_ETC___d1646 ; assign WILL_FIRE_RL_llc_mem_server_doEnq = CAN_FIRE_RL_llc_mem_server_doEnq ; - // rule RL_llc_mem_server_sendMemLoaderReqToLLC_wr - assign CAN_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr = - llc_mem_server_axi4_slave_xactor_f_wr_addr$EMPTY_N && - llc_mem_server_axi4_slave_xactor_f_wr_data$EMPTY_N && - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != - 8'd0 || - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != - 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != - 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != - 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != - 3'b011 || - !llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[0] || - llc$RDY_dma_memReq_enq) ; - assign WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr = - CAN_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr ; - - // rule RL_llc_mem_server_sendMemLoaderReqToLLC_rd - assign CAN_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd = - llc_mem_server_axi4_slave_xactor_f_rd_addr$EMPTY_N && - (llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != - 8'd0 || - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != - 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != - 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != - 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != - 3'b011 || - llc$RDY_dma_memReq_enq && - llc_mem_server_f_dword_in_line$FULL_N) ; - assign WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd = - CAN_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - !WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr ; - // rule RL_llc_mem_server_sendTlbReqToLLC assign CAN_FIRE_RL_llc_mem_server_sendTlbReqToLLC = llc$RDY_dma_memReq_enq && llc_mem_server_tlbQ$EMPTY_N ; assign WILL_FIRE_RL_llc_mem_server_sendTlbReqToLLC = CAN_FIRE_RL_llc_mem_server_sendTlbReqToLLC && - !WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - !WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr ; - - // rule RL_llc_mem_server_sendLdRespToMemLoader - assign CAN_FIRE_RL_llc_mem_server_sendLdRespToMemLoader = - llc$RDY_dma_respLd_first && llc$RDY_dma_respLd_deq && - llc_mem_server_f_dword_in_line$EMPTY_N && - llc_mem_server_axi4_slave_xactor_f_rd_data$FULL_N && - !llc$dma_respLd_first[4] ; - assign WILL_FIRE_RL_llc_mem_server_sendLdRespToMemLoader = - CAN_FIRE_RL_llc_mem_server_sendLdRespToMemLoader ; + !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld && + !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st && + !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss && + !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss && + !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged ; // rule RL_llc_mem_server_sendLdRespToTlb assign CAN_FIRE_RL_llc_mem_server_sendLdRespToTlb = @@ -4008,14 +3890,6 @@ module mkProc(CLK, assign WILL_FIRE_RL_llc_mem_server_sendLdRespToTlb = CAN_FIRE_RL_llc_mem_server_sendLdRespToTlb ; - // rule RL_llc_mem_server_sendStRespToMemLoader - assign CAN_FIRE_RL_llc_mem_server_sendStRespToMemLoader = - llc$RDY_dma_respSt_first && llc$RDY_dma_respSt_deq && - llc_mem_server_axi4_slave_xactor_f_wr_resp$FULL_N && - !llc$dma_respSt_first[4] ; - assign WILL_FIRE_RL_llc_mem_server_sendStRespToMemLoader = - CAN_FIRE_RL_llc_mem_server_sendStRespToMemLoader ; - // rule RL_llc_mem_server_sendStRespToTlb assign CAN_FIRE_RL_llc_mem_server_sendStRespToTlb = llc$RDY_dma_respSt_first && llc$RDY_dma_respSt_deq && @@ -4066,27 +3940,23 @@ module mkProc(CLK, (llc_axi4_adapter_rg_rd_req_beat != 3'd7 || llc$RDY_to_mem_toM_deq) && !llc$to_mem_toM_first[640] && - b__h123570 == 4'd0 ; + b__h131661 == 4'd0 ; assign WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ; // rule RL_llc_axi4_adapter_rl_discard_write_rsp assign CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp = - b__h123570 != 4'd0 && + b__h131661 != 4'd0 && llc_axi4_adapter_master_xactor_crg_wr_resp_full && (llc_axi4_adapter_rg_wr_rsp_beat != 3'd7 || llc_axi4_adapter_f_pending_writes$EMPTY_N) ; assign WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp = CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp ; - // rule RL_rl_reset - assign CAN_FIRE_RL_rl_reset = f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - assign WILL_FIRE_RL_rl_reset = CAN_FIRE_RL_rl_reset ; - // inputs to muxes for submodule ports assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322 ; + mmioPlatform_mtimecmp_0_20_ULE_mmioPlatform_mt_ETC___d321 ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_2 = WILL_FIRE_RL_mmioPlatform_processMSIP && mmioPlatform_reqFunc[5:4] != 2'd0 && @@ -4094,41 +3964,36 @@ module mkProc(CLK, mmioPlatform_reqBE[0] ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_3 = WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ__ETC___d546 ; + NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ__ETC___d545 ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_4 = WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ__ETC___d609 ; + NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ__ETC___d608 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_processMSIP && - mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_03_ETC___d428 ; + mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_02_ETC___d427 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_2 = WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_03_ETC___d532 ; + mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_02_ETC___d531 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_3 = WILL_FIRE_RL_mmioPlatform_processMTime && - mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_03_ETC___d597 ; + mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_02_ETC___d596 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_4 = WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && - (!mmioPlatform_fetchingWay_34_ULT_mmioPlatform_r_ETC___d944 || + (!mmioPlatform_fetchingWay_33_ULT_mmioPlatform_r_ETC___d943 || !mmio_axi4_adapter_f_rsps_to_core$D_OUT[64]) ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_5 = WILL_FIRE_RL_mmioPlatform_waitMTimeDone || WILL_FIRE_RL_mmioPlatform_waitMTimeCmpDone ; assign MUX_llc$dma_memReq_enq_1__SEL_1 = - WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1605 ; - assign MUX_llc$dma_memReq_enq_1__SEL_2 = - WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == - 8'd0 && - (llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] == - 3'b0 || - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] == - 3'b001 || - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] == - 3'b010 || - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] == - 3'b011) ; + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged ; + assign MUX_llc_mem_server_rg_cacheline_cache_state$write_1__SEL_2 = + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ; + assign MUX_llc_mem_server_rg_cacheline_cache_state$write_1__SEL_3 = + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish ; assign MUX_mmioPlatform_amoResp$write_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_processMTimeCmp && mmioPlatform_reqFunc[5:4] != 2'd0 && @@ -4140,12 +4005,12 @@ module mkProc(CLK, assign MUX_mmioPlatform_curReq$write_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_selectReq && (!mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322 || + mmioPlatform_mtimecmp_0_20_ULE_mmioPlatform_mt_ETC___d321 || core_0$mmioToPlatform_cRq_notEmpty) ; assign MUX_mmioPlatform_fetchingWay$write_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322) && + !mmioPlatform_mtimecmp_0_20_ULE_mmioPlatform_mt_ETC___d321) && core_0$mmioToPlatform_cRq_notEmpty ; assign MUX_mmioPlatform_state$write_1__SEL_6 = WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp || @@ -4175,20 +4040,20 @@ module mkProc(CLK, { 1'd0, llc$to_child_toC_first[582:1] } ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_2 = { 1'd0, - IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_ETC___d442, + IF_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_ETC___d441, (mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? mmioPlatform_reqData[31:0] : - x_data__h28019 } ; + x_data__h27811 } ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_3 = { 7'd106, - (IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515 && + (IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01__ETC___d514 && !mmioPlatform_mtip_0) ? 32'd1 : 32'd0 } ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_4 = { 7'd106, - (mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 && + (mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioPlat_ETC___d576 && !mmioPlatform_mtip_0) ? 32'd1 : 32'd0 } ; @@ -4202,35 +4067,35 @@ module mkProc(CLK, (mmioPlatform_reqFunc[5:4] == 2'd0) ? 66'h155555554AAAAAAAA : { 2'h1, - IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_1_ETC___d539 } } ; + IF_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_1_ETC___d538 } } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_3 = { mmioPlatform_reqFunc[5:4] != 2'd0, (mmioPlatform_reqFunc[5:4] == 2'd0) ? 66'h155555554AAAAAAAA : { 2'h1, - IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_1_ETC___d603 } } ; + IF_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_1_ETC___d602 } } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_4 = { 1'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] && mmioPlatform_fetchingWay, - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d952, + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d951, mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] || mmioPlatform_fetchingWay, - IF_mmio_axi4_adapter_f_rsps_to_core_first__25__ETC___d960 } ; + IF_mmio_axi4_adapter_f_rsps_to_core_first__24__ETC___d959 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_5 = { 3'd5, mmioPlatform_amoResp } ; - assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6 = { 3'd5, data__h29436 } ; + assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6 = { 3'd5, data__h29228 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_7 = { mmioPlatform_reqFunc[5:4] != 2'd0, (mmioPlatform_reqFunc[5:4] == 2'd0) ? 66'h155555554AAAAAAAA : - DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_01_BIT_ETC___d645 } ; + DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_00_BIT_ETC___d644 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_8 = { mmioPlatform_reqFunc[5:4] != 2'd0, (mmioPlatform_reqFunc[5:4] == 2'd0) ? 66'h155555554AAAAAAAA : { 1'h0, - IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_2_ETC___d687 } } ; + IF_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_2_ETC___d686 } } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_9 = { 2'd2, mmio_axi4_adapter_f_rsps_to_core$D_OUT } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_10 = @@ -4239,91 +4104,44 @@ module mkProc(CLK, { 1'd1, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:0] } : mmio_axi4_adapter_f_rsps_to_core$D_OUT } ; assign MUX_llc$dma_memReq_enq_1__VAL_1 = - { req_addr__h94733, - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == - 3'd7) ? - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8:1] : - 8'd0, - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == - 3'd6) ? - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8:1] : - 8'd0, - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == - 3'd5) ? - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8:1] : - 8'd0, - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == - 3'd4) ? - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8:1] : - 8'd0, - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == - 3'd3) ? - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8:1] : - 8'd0, - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == - 3'd2) ? - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8:1] : - 8'd0, - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == - 3'd1) ? - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8:1] : - 8'd0, - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == - 3'd0) ? - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8:1] : - 8'd0, - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == - 3'd7) ? - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[72:9] : - 64'd0, - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == - 3'd6) ? - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[72:9] : - 64'd0, - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == - 3'd5) ? - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[72:9] : - 64'd0, - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == - 3'd4) ? - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[72:9] : - 64'd0, - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == - 3'd3) ? - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[72:9] : - 64'd0, - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == - 3'd2) ? - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[72:9] : - 64'd0, - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == - 3'd1) ? - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[72:9] : - 64'd0, - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == - 3'd0) ? - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[72:9] : - 64'd0, + { llc_mem_server_rg_cacheline_cache_addr, + 64'hFFFFFFFFFFFFFFFF, + llc_mem_server_rg_cacheline_cache_data, 5'd10 } ; assign MUX_llc$dma_memReq_enq_1__VAL_2 = - { line_addr__h105593, + { line_addr__h99724, 581'h0000000000000000155555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555554A } ; assign MUX_llc$dma_memReq_enq_1__VAL_3 = + { line_addr__h99810, + 581'h0000000000000000155555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555554A } ; + assign MUX_llc$dma_memReq_enq_1__VAL_4 = { llc_mem_server_tlbQ$D_OUT[64:1], 577'h0000000000000000155555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555, llc_mem_server_tlbQ$D_OUT[0], llc_mem_server_tlbQ$D_OUT[6:4] } ; + assign MUX_llc_mem_server_rg_cacheline_cache_data$write_1__VAL_1 = + { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1561, + (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == + 3'd1) ? + new_dword__h87351 : + llc_mem_server_rg_cacheline_cache_data[127:64], + (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == + 3'd0) ? + new_dword__h87351 : + llc_mem_server_rg_cacheline_cache_data[63:0] } ; + assign MUX_llc_mem_server_rg_cacheline_cache_dirty_delay$write_1__VAL_2 = + llc_mem_server_rg_cacheline_cache_dirty_delay - 10'd1 ; assign MUX_mmioPlatform_amoResp$write_1__VAL_1 = (mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtimecmp_0 : - IF_mmioPlatform_reqBE_04_BIT_4_05_THEN_SEXT_mm_ETC___d538 ; + IF_mmioPlatform_reqBE_03_BIT_4_04_THEN_SEXT_mm_ETC___d537 ; assign MUX_mmioPlatform_amoResp$write_1__VAL_2 = (mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtime : - IF_mmioPlatform_reqBE_04_BIT_4_05_THEN_SEXT_mm_ETC___d602 ; + IF_mmioPlatform_reqBE_03_BIT_4_04_THEN_SEXT_mm_ETC___d601 ; assign MUX_mmioPlatform_curReq$write_1__VAL_1 = (!mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322) ? + mmioPlatform_mtimecmp_0_20_ULE_mmioPlatform_mt_ETC___d321) ? 67'h1AAAAAAAAAAAAAAAA : ((core_0$mmioToPlatform_cRq_first[141:81] >= 61'd33554432 && core_0$mmioToPlatform_cRq_first[141:81] < 61'd33554433) ? @@ -4334,7 +4152,7 @@ module mkProc(CLK, ((core_0$mmioToPlatform_cRq_first[141:81] == 61'd33560575) ? 67'h4AAAAAAAAAAAAAAAA : - IF_core_0_mmioToPlatform_cRq_first__43_BITS_14_ETC___d366))) ; + IF_core_0_mmioToPlatform_cRq_first__42_BITS_14_ETC___d365))) ; assign MUX_mmioPlatform_curReq$write_1__VAL_2 = { 3'd7, mmioPlatform_instSel ? @@ -4347,11 +4165,11 @@ module mkProc(CLK, mmioPlatform_instSel + 1'd1 ; assign MUX_mmioPlatform_mtime$write_1__VAL_2 = mmioPlatform_mtime + 64'd1 ; assign MUX_mmioPlatform_mtip_0$write_1__VAL_2 = - IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515 && + IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01__ETC___d514 && !mmioPlatform_mtip_0 ; assign MUX_mmioPlatform_state$write_1__VAL_1 = (!mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322) ? + mmioPlatform_mtimecmp_0_20_ULE_mmioPlatform_mt_ETC___d321) ? 2'd3 : 2'd2 ; assign MUX_mmioPlatform_state$write_1__VAL_2 = @@ -4362,32 +4180,32 @@ module mkProc(CLK, (mmioPlatform_reqBE[0] ? 2'd3 : 2'd1) : 2'd3) ; always@(mmioPlatform_reqFunc or - IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515 or + IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01__ETC___d514 or mmioPlatform_mtip_0) begin case (mmioPlatform_reqFunc[5:4]) 2'd0: MUX_mmioPlatform_state$write_1__VAL_3 = 2'd1; 2'd1: MUX_mmioPlatform_state$write_1__VAL_3 = mmioPlatform_reqFunc[5:4]; default: MUX_mmioPlatform_state$write_1__VAL_3 = - (IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515 && + (IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01__ETC___d514 && !mmioPlatform_mtip_0 || - !IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515 && + !IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01__ETC___d514 && mmioPlatform_mtip_0) ? 2'd3 : 2'd1; endcase end always@(mmioPlatform_reqFunc or - mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 or + mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioPlat_ETC___d576 or mmioPlatform_mtip_0) begin case (mmioPlatform_reqFunc[5:4]) 2'd0: MUX_mmioPlatform_state$write_1__VAL_4 = 2'd1; 2'd1: MUX_mmioPlatform_state$write_1__VAL_4 = mmioPlatform_reqFunc[5:4]; default: MUX_mmioPlatform_state$write_1__VAL_4 = - (mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 && + (mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioPlat_ETC___d576 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 && + !mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioPlat_ETC___d576 && mmioPlatform_mtip_0) ? 2'd3 : 2'd1; @@ -4395,75 +4213,75 @@ module mkProc(CLK, end assign MUX_mmioPlatform_state$write_1__VAL_5 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] ? - (mmioPlatform_fetchingWay_34_ULT_mmioPlatform_r_ETC___d944 ? + (mmioPlatform_fetchingWay_33_ULT_mmioPlatform_r_ETC___d943 ? 2'd2 : 2'd1) : 2'd1 ; assign MUX_mmioPlatform_waitMTIPCRs$write_1__VAL_2 = - mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 && + mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioPlat_ETC___d576 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 && + !mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioPlat_ETC___d576 && mmioPlatform_mtip_0 ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_1 = { mmioPlatform_curReq[63:0], 6'd42, mmioPlatform_reqBE, - x__h45575 } ; + x__h45367 } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_2 = { mmioPlatform_curReq[63:0], - IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_ETC___d442, + IF_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_ETC___d441, mmioPlatform_reqBE, mmioPlatform_reqData } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_3 = { mmioPlatform_curReq[63:0], 78'h1AAAAAAAAAAAAAAAAAAA } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_4 = - { x__h47687, 78'h1AAAAAAAAAAAAAAAAAAA } ; + { x__h47479, 78'h1AAAAAAAAAAAAAAAAAAA } ; assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_2 = { mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] == 2'b0, mmio_axi4_adapter_master_xactor_rg_rd_data[66:3] } ; // inlined wires - assign mmioPlatform_toHostQ_enqReq_lat_0$wget = { 1'd1, x__h40487 } ; + assign mmioPlatform_toHostQ_enqReq_lat_0$wget = { 1'd1, x__h40279 } ; assign mmioPlatform_toHostQ_enqReq_lat_0$whas = WILL_FIRE_RL_mmioPlatform_processToHost && mmioPlatform_reqFunc[5:4] == 2'd2 && mmioPlatform_toHostQ_empty && - x__h40487 != 64'd0 ; + x__h40279 != 64'd0 ; assign mmioPlatform_fromHostQ_deqReq_lat_0$whas = WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && !mmioPlatform_fromHostQ_empty && - x__h38421 == 64'd0 ; + x__h38213 == 64'd0 ; assign propDstIdx_0_lat_1$whas = - NOT_enqDst_0_dummy2_0_read__048_049_OR_NOT_enq_ETC___d1064 && - IF_SEL_ARR_propDstIdx_0_dummy2_1_read__027_AND_ETC___d1134 ; + NOT_enqDst_0_dummy2_0_read__047_048_OR_NOT_enq_ETC___d1063 && + IF_SEL_ARR_propDstIdx_0_dummy2_1_read__026_AND_ETC___d1133 ; assign propDstIdx_1_lat_1$whas = - NOT_enqDst_0_dummy2_0_read__048_049_OR_NOT_enq_ETC___d1064 && - x__h58979 ; + NOT_enqDst_0_dummy2_0_read__047_048_OR_NOT_enq_ETC___d1063 && + x__h58771 ; assign propDstData_0_lat_0$wget = { core_0$dCacheToParent_rqToP_first, 1'd0 } ; assign propDstData_1_lat_0$wget = { core_0$iCacheToParent_rqToP_first, 1'd1 } ; assign enqDst_0_lat_0$wget = { 1'd1, - CASE_x8979_0_n__read_addr9161_1_n__read_addr92_ETC__q23, - SEL_ARR_IF_propDstData_0_dummy2_1_read__065_TH_ETC___d1129 } ; + CASE_x8771_0_n__read_addr8953_1_n__read_addr90_ETC__q15, + SEL_ARR_IF_propDstData_0_dummy2_1_read__064_TH_ETC___d1128 } ; assign propDstIdx_1_0_lat_1$whas = - NOT_enqDst_1_0_dummy2_0_read__322_323_OR_NOT_e_ETC___d1338 && - IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__291_A_ETC___d1436 ; + NOT_enqDst_1_0_dummy2_0_read__321_322_OR_NOT_e_ETC___d1337 && + IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__290_A_ETC___d1435 ; assign propDstIdx_1_1_lat_1$whas = - NOT_enqDst_1_0_dummy2_0_read__322_323_OR_NOT_e_ETC___d1338 && - x__h77786 ; + NOT_enqDst_1_0_dummy2_0_read__321_322_OR_NOT_e_ETC___d1337 && + x__h77578 ; assign propDstData_1_0_lat_0$wget = { core_0$dCacheToParent_rsToP_first, 1'd0 } ; assign propDstData_1_1_lat_0$wget = { core_0$iCacheToParent_rsToP_first, 1'd1 } ; assign enqDst_1_0_lat_0$wget = { 1'd1, - CASE_x7786_0_n__read_addr7964_1_n__read_addr80_ETC__q34, - SEL_ARR_IF_propDstData_1_0_dummy2_1_read__339__ETC___d1431 } ; + CASE_x7578_0_n__read_addr7756_1_n__read_addr78_ETC__q26, + SEL_ARR_IF_propDstData_1_0_dummy2_1_read__338__ETC___d1430 } ; assign llc_mem_server_enqDst_0_lat_0$wget = - { 1'd1, n__read_snd_addr__h92909, n__read_snd_id__h92910 } ; + { 1'd1, n__read_snd_addr__h121251, n__read_snd_id__h121252 } ; assign mmio_axi4_adapter_master_xactor_crg_wr_addr_full$EN_port1__write = mmio_axi4_adapter_master_xactor_crg_wr_addr_full && master1_awready ; @@ -4512,15 +4330,11 @@ module mkProc(CLK, assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 = mmio_axi4_adapter_ctr_wr_rsps_pending_crg + 4'd1 ; assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 = - b__h2359 - 4'd1 ; + b__h2154 - 4'd1 ; assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read = WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp ? mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 : - b__h2359 ; - assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port3__read = - CAN_FIRE_RL_rl_reset ? - 4'd0 : - mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read ; + b__h2154 ; assign llc_axi4_adapter_master_xactor_crg_wr_addr_full$EN_port1__write = llc_axi4_adapter_master_xactor_crg_wr_addr_full && master0_awready ; @@ -4569,15 +4383,11 @@ module mkProc(CLK, assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 = llc_axi4_adapter_ctr_wr_rsps_pending_crg + 4'd1 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 = - b__h123570 - 4'd1 ; + b__h131661 - 4'd1 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read = CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp ? llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 : - b__h123570 ; - assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port3__read = - CAN_FIRE_RL_rl_reset ? - 4'd0 : - llc_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read ; + b__h131661 ; // register cfg_verbosity assign cfg_verbosity$D_IN = @@ -4589,10 +4399,10 @@ module mkProc(CLK, // register enqDst_0_rl assign enqDst_0_rl$D_IN = { !CAN_FIRE_RL_doEnq && - IF_enqDst_0_lat_0_whas__003_THEN_enqDst_0_lat__ETC___d1008, + IF_enqDst_0_lat_0_whas__002_THEN_enqDst_0_lat__ETC___d1007, CAN_FIRE_RL_doEnq ? 73'h0AAAAAAAAAAAAAAAAAA : - (NOT_enqDst_0_dummy2_0_read__048_049_OR_NOT_enq_ETC___d1064 ? + (NOT_enqDst_0_dummy2_0_read__047_048_OR_NOT_enq_ETC___d1063 ? enqDst_0_lat_0$wget[72:0] : enqDst_0_rl[72:0]) } ; assign enqDst_0_rl$EN = 1'd1 ; @@ -4600,8 +4410,8 @@ module mkProc(CLK, // register enqDst_1_0_rl assign enqDst_1_0_rl$D_IN = { !CAN_FIRE_RL_doEnq_1 && - IF_enqDst_1_0_lat_0_whas__239_THEN_enqDst_1_0__ETC___d1244, - IF_enqDst_1_0_lat_1_whas__236_THEN_enqDst_1_0__ETC___d1283 } ; + IF_enqDst_1_0_lat_0_whas__238_THEN_enqDst_1_0__ETC___d1243, + IF_enqDst_1_0_lat_1_whas__235_THEN_enqDst_1_0__ETC___d1282 } ; assign enqDst_1_0_rl$EN = 1'd1 ; // register llc_axi4_adapter_cfg_verbosity @@ -4610,7 +4420,7 @@ module mkProc(CLK, // register llc_axi4_adapter_ctr_wr_rsps_pending_crg assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$D_IN = - llc_axi4_adapter_ctr_wr_rsps_pending_crg$port3__read ; + llc_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$EN = 1'b1 ; // register llc_axi4_adapter_master_xactor_crg_rd_addr_full @@ -4640,7 +4450,7 @@ module mkProc(CLK, // register llc_axi4_adapter_master_xactor_rg_rd_addr assign llc_axi4_adapter_master_xactor_rg_rd_addr$D_IN = - { 4'd0, mem_req_rd_addr_araddr__h123863, 29'd851968 } ; + { 4'd0, mem_req_rd_addr_araddr__h131954, 29'd851968 } ; assign llc_axi4_adapter_master_xactor_rg_rd_addr$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ; @@ -4651,13 +4461,13 @@ module mkProc(CLK, // register llc_axi4_adapter_master_xactor_rg_wr_addr assign llc_axi4_adapter_master_xactor_rg_wr_addr$D_IN = - { 4'd0, mem_req_wr_addr_awaddr__h137787, 29'd851968 } ; + { 4'd0, mem_req_wr_addr_awaddr__h145878, 29'd851968 } ; assign llc_axi4_adapter_master_xactor_rg_wr_addr$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ; // register llc_axi4_adapter_master_xactor_rg_wr_data assign llc_axi4_adapter_master_xactor_rg_wr_data$D_IN = - { 4'd0, data64__h137702, strb8__h137703, 1'd1 } ; + { data64__h145793, strb8__h145794, 1'd1 } ; assign llc_axi4_adapter_master_xactor_rg_wr_data$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ; @@ -4669,7 +4479,7 @@ module mkProc(CLK, !llc_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read ; // register llc_axi4_adapter_rg_cline - assign llc_axi4_adapter_rg_cline$D_IN = new_cline__h124565 ; + assign llc_axi4_adapter_rg_cline$D_IN = new_cline__h132656 ; assign llc_axi4_adapter_rg_cline$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps ; @@ -4700,10 +4510,10 @@ module mkProc(CLK, // register llc_mem_server_enqDst_0_rl assign llc_mem_server_enqDst_0_rl$D_IN = { !CAN_FIRE_RL_llc_mem_server_doEnq && - IF_llc_mem_server_enqDst_0_lat_0_whas__500_THE_ETC___d1505, + IF_llc_mem_server_enqDst_0_lat_0_whas__641_THE_ETC___d1646, CAN_FIRE_RL_llc_mem_server_doEnq ? 65'h0AAAAAAAAAAAAAAAA : - (NOT_llc_mem_server_enqDst_0_dummy2_0_read__531_ETC___d1538 ? + (NOT_llc_mem_server_enqDst_0_dummy2_0_read__672_ETC___d1679 ? llc_mem_server_enqDst_0_lat_0$wget[64:0] : llc_mem_server_enqDst_0_rl[64:0]) } ; assign llc_mem_server_enqDst_0_rl$EN = 1'd1 ; @@ -4717,10 +4527,66 @@ module mkProc(CLK, // register llc_mem_server_propDstIdx_0_rl assign llc_mem_server_propDstIdx_0_rl$D_IN = - !NOT_llc_mem_server_enqDst_0_dummy2_0_read__531_ETC___d1538 && - IF_llc_mem_server_propDstIdx_0_lat_0_whas__485_ETC___d1488 ; + !NOT_llc_mem_server_enqDst_0_dummy2_0_read__672_ETC___d1679 && + IF_llc_mem_server_propDstIdx_0_lat_0_whas__626_ETC___d1629 ; assign llc_mem_server_propDstIdx_0_rl$EN = 1'd1 ; + // register llc_mem_server_rg_cacheline_cache_addr + assign llc_mem_server_rg_cacheline_cache_addr$D_IN = + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ? + line_addr__h99724 : + line_addr__h99810 ; + assign llc_mem_server_rg_cacheline_cache_addr$EN = + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld ; + + // register llc_mem_server_rg_cacheline_cache_data + assign llc_mem_server_rg_cacheline_cache_data$D_IN = + WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ? + MUX_llc_mem_server_rg_cacheline_cache_data$write_1__VAL_1 : + llc$dma_respLd_first[516:5] ; + assign llc_mem_server_rg_cacheline_cache_data$EN = + WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish ; + + // register llc_mem_server_rg_cacheline_cache_dirty_delay + assign llc_mem_server_rg_cacheline_cache_dirty_delay$D_IN = + WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ? + 10'd1023 : + MUX_llc_mem_server_rg_cacheline_cache_dirty_delay$write_1__VAL_2 ; + assign llc_mem_server_rg_cacheline_cache_dirty_delay$EN = + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_delay || + WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ; + + // register llc_mem_server_rg_cacheline_cache_state + always@(MUX_llc$dma_memReq_enq_1__SEL_1 or + MUX_llc_mem_server_rg_cacheline_cache_state$write_1__SEL_2 or + MUX_llc_mem_server_rg_cacheline_cache_state$write_1__SEL_3 or + WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req) + begin + case (1'b1) // synopsys parallel_case + MUX_llc$dma_memReq_enq_1__SEL_1: + llc_mem_server_rg_cacheline_cache_state$D_IN = 3'd1; + MUX_llc_mem_server_rg_cacheline_cache_state$write_1__SEL_2: + llc_mem_server_rg_cacheline_cache_state$D_IN = 3'd2; + MUX_llc_mem_server_rg_cacheline_cache_state$write_1__SEL_3: + llc_mem_server_rg_cacheline_cache_state$D_IN = 3'd3; + WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req: + llc_mem_server_rg_cacheline_cache_state$D_IN = 3'd4; + default: llc_mem_server_rg_cacheline_cache_state$D_IN = + 3'b010 /* unspecified value */ ; + endcase + end + assign llc_mem_server_rg_cacheline_cache_state$EN = + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish || + WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ; + // register mmioPlatform_amoResp assign mmioPlatform_amoResp$D_IN = MUX_mmioPlatform_amoResp$write_1__SEL_1 ? @@ -4743,7 +4609,7 @@ module mkProc(CLK, MUX_mmioPlatform_curReq$write_1__SEL_1 || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] && - mmioPlatform_fetchingWay_34_ULT_mmioPlatform_r_ETC___d944 ; + mmioPlatform_fetchingWay_33_ULT_mmioPlatform_r_ETC___d943 ; // register mmioPlatform_cycle assign mmioPlatform_cycle$D_IN = @@ -4756,11 +4622,11 @@ module mkProc(CLK, // register mmioPlatform_fetchedInsts_0 assign mmioPlatform_fetchedInsts_0$D_IN = - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d952 ; + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d951 ; assign mmioPlatform_fetchedInsts_0$EN = WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] && - mmioPlatform_fetchingWay_34_ULT_mmioPlatform_r_ETC___d944 && + mmioPlatform_fetchingWay_33_ULT_mmioPlatform_r_ETC___d943 && !mmioPlatform_fetchingWay ; // register mmioPlatform_fetchingWay @@ -4770,11 +4636,11 @@ module mkProc(CLK, assign mmioPlatform_fetchingWay$EN = WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322) && + !mmioPlatform_mtimecmp_0_20_ULE_mmioPlatform_mt_ETC___d321) && core_0$mmioToPlatform_cRq_notEmpty || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] && - mmioPlatform_fetchingWay_34_ULT_mmioPlatform_r_ETC___d944 ; + mmioPlatform_fetchingWay_33_ULT_mmioPlatform_r_ETC___d943 ; // register mmioPlatform_fromHostAddr assign mmioPlatform_fromHostAddr$D_IN = start_fromhostAddr[63:3] ; @@ -4788,7 +4654,7 @@ module mkProc(CLK, assign mmioPlatform_fromHostQ_data_0$D_IN = mmioPlatform_fromHostQ_enqReq_rl[63:0] ; assign mmioPlatform_fromHostQ_data_0$EN = - NOT_mmioPlatform_fromHostQ_clearReq_dummy2_1_r_ETC___d283 && + NOT_mmioPlatform_fromHostQ_clearReq_dummy2_1_r_ETC___d282 && mmioPlatform_fromHostQ_enqReq_dummy2_2$Q_OUT && mmioPlatform_fromHostQ_enqReq_rl[64] ; @@ -4800,7 +4666,7 @@ module mkProc(CLK, assign mmioPlatform_fromHostQ_empty$D_IN = mmioPlatform_fromHostQ_clearReq_dummy2_1$Q_OUT && mmioPlatform_fromHostQ_clearReq_rl || - NOT_mmioPlatform_fromHostQ_enqReq_dummy2_2_rea_ETC___d304 ; + NOT_mmioPlatform_fromHostQ_enqReq_dummy2_2_rea_ETC___d303 ; assign mmioPlatform_fromHostQ_empty$EN = 1'd1 ; // register mmioPlatform_fromHostQ_enqReq_rl @@ -4809,8 +4675,8 @@ module mkProc(CLK, // register mmioPlatform_fromHostQ_full assign mmioPlatform_fromHostQ_full$D_IN = - NOT_mmioPlatform_fromHostQ_clearReq_dummy2_1_r_ETC___d283 && - mmioPlatform_fromHostQ_enqReq_dummy2_2_read__8_ETC___d296 ; + NOT_mmioPlatform_fromHostQ_clearReq_dummy2_1_r_ETC___d282 && + mmioPlatform_fromHostQ_enqReq_dummy2_2_read__8_ETC___d295 ; assign mmioPlatform_fromHostQ_full$EN = 1'd1 ; // register mmioPlatform_instSel @@ -4821,16 +4687,16 @@ module mkProc(CLK, assign mmioPlatform_instSel$EN = WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322) && + !mmioPlatform_mtimecmp_0_20_ULE_mmioPlatform_mt_ETC___d321) && core_0$mmioToPlatform_cRq_notEmpty || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] && - mmioPlatform_fetchingWay_34_ULT_mmioPlatform_r_ETC___d944 ; + mmioPlatform_fetchingWay_33_ULT_mmioPlatform_r_ETC___d943 ; // register mmioPlatform_mtime assign mmioPlatform_mtime$D_IN = MUX_mmioPlatform_amoResp$write_1__SEL_2 ? - newData__h32447 : + newData__h32239 : MUX_mmioPlatform_mtime$write_1__VAL_2 ; assign mmioPlatform_mtime$EN = WILL_FIRE_RL_mmioPlatform_processMTime && @@ -4839,7 +4705,7 @@ module mkProc(CLK, WILL_FIRE_RL_mmioPlatform_incTime ; // register mmioPlatform_mtimecmp_0 - assign mmioPlatform_mtimecmp_0$D_IN = newData__h29517 ; + assign mmioPlatform_mtimecmp_0$D_IN = newData__h29309 ; assign mmioPlatform_mtimecmp_0$EN = MUX_mmioPlatform_amoResp$write_1__SEL_1 ; @@ -4849,9 +4715,9 @@ module mkProc(CLK, MUX_mmioPlatform_mtip_0$write_1__VAL_2 ; assign mmioPlatform_mtip_0$EN = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322 || + mmioPlatform_mtimecmp_0_20_ULE_mmioPlatform_mt_ETC___d321 || WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ__ETC___d546 ; + NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ__ETC___d545 ; // register mmioPlatform_reqAmofunc assign mmioPlatform_reqAmofunc$D_IN = @@ -4953,9 +4819,9 @@ module mkProc(CLK, mmioPlatform_toHostQ_enqReq_lat_0$wget[63:0] : mmioPlatform_toHostQ_enqReq_rl[63:0] ; assign mmioPlatform_toHostQ_data_0$EN = - NOT_mmioPlatform_toHostQ_clearReq_dummy2_1_rea_ETC___d205 && + NOT_mmioPlatform_toHostQ_clearReq_dummy2_1_rea_ETC___d204 && mmioPlatform_toHostQ_enqReq_dummy2_2$Q_OUT && - IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__56__ETC___d165 ; + IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__55__ETC___d164 ; // register mmioPlatform_toHostQ_deqReq_rl assign mmioPlatform_toHostQ_deqReq_rl$D_IN = 1'd0 ; @@ -4965,7 +4831,7 @@ module mkProc(CLK, assign mmioPlatform_toHostQ_empty$D_IN = mmioPlatform_toHostQ_clearReq_dummy2_1$Q_OUT && mmioPlatform_toHostQ_clearReq_rl || - NOT_mmioPlatform_toHostQ_enqReq_dummy2_2_read__ETC___d226 ; + NOT_mmioPlatform_toHostQ_enqReq_dummy2_2_read__ETC___d225 ; assign mmioPlatform_toHostQ_empty$EN = 1'd1 ; // register mmioPlatform_toHostQ_enqReq_rl @@ -4974,8 +4840,8 @@ module mkProc(CLK, // register mmioPlatform_toHostQ_full assign mmioPlatform_toHostQ_full$D_IN = - NOT_mmioPlatform_toHostQ_clearReq_dummy2_1_rea_ETC___d205 && - mmioPlatform_toHostQ_enqReq_dummy2_2_read__06__ETC___d218 ; + NOT_mmioPlatform_toHostQ_clearReq_dummy2_1_rea_ETC___d204 && + mmioPlatform_toHostQ_enqReq_dummy2_2_read__05__ETC___d217 ; assign mmioPlatform_toHostQ_full$EN = 1'd1 ; // register mmioPlatform_waitLowerMSIPCRs @@ -4985,7 +4851,7 @@ module mkProc(CLK, mmioPlatform_reqBE[0] ; assign mmioPlatform_waitLowerMSIPCRs$EN = WILL_FIRE_RL_mmioPlatform_processMSIP && - NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ__ETC___d451 ; + NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ__ETC___d450 ; // register mmioPlatform_waitMTIPCRs assign mmioPlatform_waitMTIPCRs$D_IN = @@ -4993,15 +4859,15 @@ module mkProc(CLK, MUX_mmioPlatform_waitMTIPCRs$write_1__VAL_2 ; assign mmioPlatform_waitMTIPCRs$EN = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322 || + mmioPlatform_mtimecmp_0_20_ULE_mmioPlatform_mt_ETC___d321 || WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ__ETC___d609 ; + NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ__ETC___d608 ; // register mmioPlatform_waitUpperMSIPCRs assign mmioPlatform_waitUpperMSIPCRs$D_IN = 1'd0 ; assign mmioPlatform_waitUpperMSIPCRs$EN = WILL_FIRE_RL_mmioPlatform_processMSIP && - NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ__ETC___d451 ; + NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ__ETC___d450 ; // register mmio_axi4_adapter_cfg_verbosity assign mmio_axi4_adapter_cfg_verbosity$D_IN = 4'h0 ; @@ -5009,7 +4875,7 @@ module mkProc(CLK, // register mmio_axi4_adapter_ctr_wr_rsps_pending_crg assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$D_IN = - mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port3__read ; + mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read ; assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$EN = 1'b1 ; // register mmio_axi4_adapter_master_xactor_crg_rd_addr_full @@ -5060,8 +4926,7 @@ module mkProc(CLK, // register mmio_axi4_adapter_master_xactor_rg_wr_data assign mmio_axi4_adapter_master_xactor_rg_wr_data$D_IN = - { 4'd0, - mmio_axi4_adapter_f_reqs_from_core$D_OUT[63:0], + { mmio_axi4_adapter_f_reqs_from_core$D_OUT[63:0], mmio_axi4_adapter_f_reqs_from_core$D_OUT[71:64], 1'd1 } ; assign mmio_axi4_adapter_master_xactor_rg_wr_data$EN = @@ -5083,28 +4948,28 @@ module mkProc(CLK, // register propDstData_1_0_rl assign propDstData_1_0_rl$D_IN = - { IF_propDstData_1_0_lat_0_whas__163_THEN_propDs_ETC___d1168, - IF_propDstData_1_0_lat_0_whas__163_THEN_propDs_ETC___d1173, + { IF_propDstData_1_0_lat_0_whas__162_THEN_propDs_ETC___d1167, + IF_propDstData_1_0_lat_0_whas__162_THEN_propDs_ETC___d1172, CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[513] : propDstData_1_0_rl[513], CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[512:1] : propDstData_1_0_rl[512:1], - IF_propDstData_1_0_lat_0_whas__163_THEN_propDs_ETC___d1194 } ; + IF_propDstData_1_0_lat_0_whas__162_THEN_propDs_ETC___d1193 } ; assign propDstData_1_0_rl$EN = 1'd1 ; // register propDstData_1_1_rl assign propDstData_1_1_rl$D_IN = - { IF_propDstData_1_1_lat_0_whas__201_THEN_propDs_ETC___d1206, - IF_propDstData_1_1_lat_0_whas__201_THEN_propDs_ETC___d1211, + { IF_propDstData_1_1_lat_0_whas__200_THEN_propDs_ETC___d1205, + IF_propDstData_1_1_lat_0_whas__200_THEN_propDs_ETC___d1210, CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[513] : propDstData_1_1_rl[513], CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[512:1] : propDstData_1_1_rl[512:1], - IF_propDstData_1_1_lat_0_whas__201_THEN_propDs_ETC___d1232 } ; + IF_propDstData_1_1_lat_0_whas__200_THEN_propDs_ETC___d1231 } ; assign propDstData_1_1_rl$EN = 1'd1 ; // register propDstData_1_rl @@ -5117,36 +4982,36 @@ module mkProc(CLK, // register propDstIdx_0_rl assign propDstIdx_0_rl$D_IN = !propDstIdx_0_lat_1$whas && - IF_propDstIdx_0_lat_0_whas__74_THEN_propDstIdx_ETC___d977 ; + IF_propDstIdx_0_lat_0_whas__73_THEN_propDstIdx_ETC___d976 ; assign propDstIdx_0_rl$EN = 1'd1 ; // register propDstIdx_1_0_rl assign propDstIdx_1_0_rl$D_IN = !propDstIdx_1_0_lat_1$whas && - IF_propDstIdx_1_0_lat_0_whas__148_THEN_propDst_ETC___d1151 ; + IF_propDstIdx_1_0_lat_0_whas__147_THEN_propDst_ETC___d1150 ; assign propDstIdx_1_0_rl$EN = 1'd1 ; // register propDstIdx_1_1_rl assign propDstIdx_1_1_rl$D_IN = !propDstIdx_1_1_lat_1$whas && - IF_propDstIdx_1_1_lat_0_whas__155_THEN_propDst_ETC___d1158 ; + IF_propDstIdx_1_1_lat_0_whas__154_THEN_propDst_ETC___d1157 ; assign propDstIdx_1_1_rl$EN = 1'd1 ; // register propDstIdx_1_rl assign propDstIdx_1_rl$D_IN = !propDstIdx_1_lat_1$whas && - IF_propDstIdx_1_lat_0_whas__81_THEN_propDstIdx_ETC___d984 ; + IF_propDstIdx_1_lat_0_whas__80_THEN_propDstIdx_ETC___d983 ; assign propDstIdx_1_rl$EN = 1'd1 ; // register srcRR_0 assign srcRR_0$D_IN = srcRR_0 + 1'd1 ; assign srcRR_0$EN = - NOT_enqDst_0_dummy2_0_read__048_049_OR_NOT_enq_ETC___d1064 ; + NOT_enqDst_0_dummy2_0_read__047_048_OR_NOT_enq_ETC___d1063 ; // register srcRR_1_0 assign srcRR_1_0$D_IN = srcRR_1_0 + 1'd1 ; assign srcRR_1_0$EN = - NOT_enqDst_1_0_dummy2_0_read__322_323_OR_NOT_e_ETC___d1338 ; + NOT_enqDst_1_0_dummy2_0_read__321_322_OR_NOT_e_ETC___d1337 ; // submodule core_0 assign core_0$coreReq_perfReq_loc = 4'h0 ; @@ -5252,11 +5117,10 @@ module mkProc(CLK, end assign core_0$mmioToPlatform_setTime_t = mmioPlatform_mtime ; assign core_0$recvDoStats_x = core_0$sendDoStats ; - assign core_0$setDEIP_v = debug_external_interrupt_req_set_not_clear ; assign core_0$setMEIP_v = m_external_interrupt_req_set_not_clear ; assign core_0$setSEIP_v = s_external_interrupt_req_set_not_clear ; assign core_0$tlbToMem_respLd_enq_x = - { ld_data__h121714, llc$dma_respLd_first[3] } ; + { ld_data__h129909, llc$dma_respLd_first[3] } ; assign core_0$EN_coreReq_start = EN_start ; assign core_0$EN_coreReq_perfReq = 1'b0 ; assign core_0$EN_coreIndInv_perfResp = 1'b0 ; @@ -5277,13 +5141,13 @@ module mkProc(CLK, MUX_mmioPlatform_fetchingWay$write_1__SEL_1 ; assign core_0$EN_mmioToPlatform_pRs_enq = WILL_FIRE_RL_mmioPlatform_processMSIP && - mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_03_ETC___d428 || + mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_02_ETC___d427 || WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_03_ETC___d532 || + mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_02_ETC___d531 || WILL_FIRE_RL_mmioPlatform_processMTime && - mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_03_ETC___d597 || + mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_02_ETC___d596 || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && - (!mmioPlatform_fetchingWay_34_ULT_mmioPlatform_r_ETC___d944 || + (!mmioPlatform_fetchingWay_33_ULT_mmioPlatform_r_ETC___d943 || !mmio_axi4_adapter_f_rsps_to_core$D_OUT[64]) || WILL_FIRE_RL_mmioPlatform_waitMTimeDone || WILL_FIRE_RL_mmioPlatform_waitMTimeCmpDone || @@ -5294,15 +5158,15 @@ module mkProc(CLK, WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp ; assign core_0$EN_mmioToPlatform_pRq_enq = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322 || + mmioPlatform_mtimecmp_0_20_ULE_mmioPlatform_mt_ETC___d321 || WILL_FIRE_RL_mmioPlatform_processMSIP && mmioPlatform_reqFunc[5:4] != 2'd0 && !mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0] || WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ__ETC___d546 || + NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ__ETC___d545 || WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ__ETC___d609 ; + NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ__ETC___d608 ; assign core_0$EN_mmioToPlatform_cRs_deq = (WILL_FIRE_RL_mmioPlatform_waitMTimeDone || WILL_FIRE_RL_mmioPlatform_waitTimerInterruptDone) && @@ -5337,7 +5201,6 @@ module mkProc(CLK, core_0$RDY_renameDebug_renameErr_get ; assign core_0$EN_setMEIP = 1'd1 ; assign core_0$EN_setSEIP = 1'd1 ; - assign core_0$EN_setDEIP = 1'd1 ; assign core_0$EN_hart0_run_halt_server_request_put = EN_hart0_run_halt_server_request_put ; assign core_0$EN_hart0_run_halt_server_response_get = @@ -5354,13 +5217,11 @@ module mkProc(CLK, EN_hart0_csr_mem_server_request_put ; assign core_0$EN_hart0_csr_mem_server_response_get = EN_hart0_csr_mem_server_response_get ; - assign core_0$EN_v_to_TV_0_get = EN_v_to_TV_0_get ; - assign core_0$EN_v_to_TV_1_get = EN_v_to_TV_1_get ; // submodule enqDst_0_dummy2_0 assign enqDst_0_dummy2_0$D_IN = 1'd1 ; assign enqDst_0_dummy2_0$EN = - NOT_enqDst_0_dummy2_0_read__048_049_OR_NOT_enq_ETC___d1064 ; + NOT_enqDst_0_dummy2_0_read__047_048_OR_NOT_enq_ETC___d1063 ; // submodule enqDst_0_dummy2_1 assign enqDst_0_dummy2_1$D_IN = 1'd1 ; @@ -5369,37 +5230,31 @@ module mkProc(CLK, // submodule enqDst_1_0_dummy2_0 assign enqDst_1_0_dummy2_0$D_IN = 1'd1 ; assign enqDst_1_0_dummy2_0$EN = - NOT_enqDst_1_0_dummy2_0_read__322_323_OR_NOT_e_ETC___d1338 ; + NOT_enqDst_1_0_dummy2_0_read__321_322_OR_NOT_e_ETC___d1337 ; // submodule enqDst_1_0_dummy2_1 assign enqDst_1_0_dummy2_1$D_IN = 1'd1 ; assign enqDst_1_0_dummy2_1$EN = CAN_FIRE_RL_doEnq_1 ; - // submodule f_reset_reqs - assign f_reset_reqs$ENQ = EN_hart0_server_reset_request_put ; - assign f_reset_reqs$DEQ = CAN_FIRE_RL_rl_reset ; - assign f_reset_reqs$CLR = 1'b0 ; - - // submodule f_reset_rsps - assign f_reset_rsps$ENQ = CAN_FIRE_RL_rl_reset ; - assign f_reset_rsps$DEQ = EN_hart0_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - // submodule llc always@(MUX_llc$dma_memReq_enq_1__SEL_1 or MUX_llc$dma_memReq_enq_1__VAL_1 or - MUX_llc$dma_memReq_enq_1__SEL_2 or + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st or MUX_llc$dma_memReq_enq_1__VAL_2 or + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld or + MUX_llc$dma_memReq_enq_1__VAL_3 or WILL_FIRE_RL_llc_mem_server_sendTlbReqToLLC or - MUX_llc$dma_memReq_enq_1__VAL_3) + MUX_llc$dma_memReq_enq_1__VAL_4) begin case (1'b1) // synopsys parallel_case MUX_llc$dma_memReq_enq_1__SEL_1: llc$dma_memReq_enq_x = MUX_llc$dma_memReq_enq_1__VAL_1; - MUX_llc$dma_memReq_enq_1__SEL_2: + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st: llc$dma_memReq_enq_x = MUX_llc$dma_memReq_enq_1__VAL_2; - WILL_FIRE_RL_llc_mem_server_sendTlbReqToLLC: + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld: llc$dma_memReq_enq_x = MUX_llc$dma_memReq_enq_1__VAL_3; + WILL_FIRE_RL_llc_mem_server_sendTlbReqToLLC: + llc$dma_memReq_enq_x = MUX_llc$dma_memReq_enq_1__VAL_4; default: llc$dma_memReq_enq_x = 645'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase @@ -5407,17 +5262,17 @@ module mkProc(CLK, assign llc$perf_req_r = 4'h0 ; assign llc$perf_setStatus_doStats = core_0$sendDoStats ; assign llc$to_child_rqFromC_enq_x = - NOT_enqDst_0_dummy2_0_read__048_049_OR_NOT_enq_ETC___d1064 ? + NOT_enqDst_0_dummy2_0_read__047_048_OR_NOT_enq_ETC___d1063 ? enqDst_0_lat_0$wget[72:0] : enqDst_0_rl[72:0] ; assign llc$to_child_rsFromC_enq_x = - { IF_enqDst_1_0_lat_0_whas__239_THEN_enqDst_1_0__ETC___d1254, - IF_enqDst_1_0_lat_0_whas__239_THEN_enqDst_1_0__ETC___d1259, - IF_enqDst_1_0_lat_0_whas__239_THEN_enqDst_1_0__ETC___d1264, - IF_enqDst_1_0_lat_0_whas__239_THEN_enqDst_1_0__ETC___d1274, - IF_enqDst_1_0_lat_0_whas__239_THEN_enqDst_1_0__ETC___d1280 } ; + { IF_enqDst_1_0_lat_0_whas__238_THEN_enqDst_1_0__ETC___d1253, + IF_enqDst_1_0_lat_0_whas__238_THEN_enqDst_1_0__ETC___d1258, + IF_enqDst_1_0_lat_0_whas__238_THEN_enqDst_1_0__ETC___d1263, + IF_enqDst_1_0_lat_0_whas__238_THEN_enqDst_1_0__ETC___d1273, + IF_enqDst_1_0_lat_0_whas__238_THEN_enqDst_1_0__ETC___d1279 } ; assign llc$to_mem_rsFromM_enq_x = - { new_cline__h124565, + { new_cline__h132656, llc_axi4_adapter_f_pending_reads$D_OUT[4:0] } ; assign llc$EN_to_child_rsFromC_enq = CAN_FIRE_RL_doEnq_1 ; assign llc$EN_to_child_rqFromC_enq = CAN_FIRE_RL_doEnq ; @@ -5426,26 +5281,18 @@ module mkProc(CLK, WILL_FIRE_RL_sendPRs || WILL_FIRE_RL_sendPRq ; assign llc$EN_dma_memReq_enq = - WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1605 || - WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == - 8'd0 && - (llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] == - 3'b0 || - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] == - 3'b001 || - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] == - 3'b010 || - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] == - 3'b011) || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st || + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld || WILL_FIRE_RL_llc_mem_server_sendTlbReqToLLC ; assign llc$EN_dma_respLd_deq = WILL_FIRE_RL_llc_mem_server_sendLdRespToTlb || - WILL_FIRE_RL_llc_mem_server_sendLdRespToMemLoader ; + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish ; assign llc$EN_dma_respSt_deq = WILL_FIRE_RL_llc_mem_server_sendStRespToTlb || - WILL_FIRE_RL_llc_mem_server_sendStRespToMemLoader ; + WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish ; assign llc$EN_to_mem_toM_deq = WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && llc_axi4_adapter_rg_rd_req_beat == 3'd7 || @@ -5496,14 +5343,14 @@ module mkProc(CLK, debug_module_mem_server_arvalid && llc_mem_server_axi4_slave_xactor_f_rd_addr$FULL_N ; assign llc_mem_server_axi4_slave_xactor_f_rd_addr$DEQ = - WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd ; + CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req ; assign llc_mem_server_axi4_slave_xactor_f_rd_addr$CLR = 1'b0 ; // submodule llc_mem_server_axi4_slave_xactor_f_rd_data assign llc_mem_server_axi4_slave_xactor_f_rd_data$D_IN = - { 4'd0, rd_data_rdata__h120163, 3'd1 } ; + { 4'd0, dword__h91660, 3'd1 } ; assign llc_mem_server_axi4_slave_xactor_f_rd_data$ENQ = - CAN_FIRE_RL_llc_mem_server_sendLdRespToMemLoader ; + CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req ; assign llc_mem_server_axi4_slave_xactor_f_rd_data$DEQ = debug_module_mem_server_rready && llc_mem_server_axi4_slave_xactor_f_rd_data$EMPTY_N ; @@ -5525,26 +5372,25 @@ module mkProc(CLK, debug_module_mem_server_awvalid && llc_mem_server_axi4_slave_xactor_f_wr_addr$FULL_N ; assign llc_mem_server_axi4_slave_xactor_f_wr_addr$DEQ = - CAN_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr ; + CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ; assign llc_mem_server_axi4_slave_xactor_f_wr_addr$CLR = 1'b0 ; // submodule llc_mem_server_axi4_slave_xactor_f_wr_data assign llc_mem_server_axi4_slave_xactor_f_wr_data$D_IN = - { debug_module_mem_server_wid, - debug_module_mem_server_wdata, + { debug_module_mem_server_wdata, debug_module_mem_server_wstrb, debug_module_mem_server_wlast } ; assign llc_mem_server_axi4_slave_xactor_f_wr_data$ENQ = debug_module_mem_server_wvalid && llc_mem_server_axi4_slave_xactor_f_wr_data$FULL_N ; assign llc_mem_server_axi4_slave_xactor_f_wr_data$DEQ = - CAN_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr ; + CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ; assign llc_mem_server_axi4_slave_xactor_f_wr_data$CLR = 1'b0 ; // submodule llc_mem_server_axi4_slave_xactor_f_wr_resp assign llc_mem_server_axi4_slave_xactor_f_wr_resp$D_IN = 6'd0 ; assign llc_mem_server_axi4_slave_xactor_f_wr_resp$ENQ = - CAN_FIRE_RL_llc_mem_server_sendStRespToMemLoader ; + CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ; assign llc_mem_server_axi4_slave_xactor_f_wr_resp$DEQ = debug_module_mem_server_bready && llc_mem_server_axi4_slave_xactor_f_wr_resp$EMPTY_N ; @@ -5553,7 +5399,7 @@ module mkProc(CLK, // submodule llc_mem_server_enqDst_0_dummy2_0 assign llc_mem_server_enqDst_0_dummy2_0$D_IN = 1'd1 ; assign llc_mem_server_enqDst_0_dummy2_0$EN = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__531_ETC___d1538 ; + NOT_llc_mem_server_enqDst_0_dummy2_0_read__672_ETC___d1679 ; // submodule llc_mem_server_enqDst_0_dummy2_1 assign llc_mem_server_enqDst_0_dummy2_1$D_IN = 1'd1 ; @@ -5561,12 +5407,9 @@ module mkProc(CLK, CAN_FIRE_RL_llc_mem_server_doEnq ; // submodule llc_mem_server_f_dword_in_line - assign llc_mem_server_f_dword_in_line$D_IN = - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[34:32] ; - assign llc_mem_server_f_dword_in_line$ENQ = - MUX_llc$dma_memReq_enq_1__SEL_2 ; - assign llc_mem_server_f_dword_in_line$DEQ = - CAN_FIRE_RL_llc_mem_server_sendLdRespToMemLoader ; + assign llc_mem_server_f_dword_in_line$D_IN = 3'h0 ; + assign llc_mem_server_f_dword_in_line$ENQ = 1'b0 ; + assign llc_mem_server_f_dword_in_line$DEQ = 1'b0 ; assign llc_mem_server_f_dword_in_line$CLR = 1'b0 ; // submodule llc_mem_server_propDstData_0_dummy2_0 @@ -5586,11 +5429,11 @@ module mkProc(CLK, // submodule llc_mem_server_propDstIdx_0_dummy2_1 assign llc_mem_server_propDstIdx_0_dummy2_1$D_IN = 1'd1 ; assign llc_mem_server_propDstIdx_0_dummy2_1$EN = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__531_ETC___d1538 ; + NOT_llc_mem_server_enqDst_0_dummy2_0_read__672_ETC___d1679 ; // submodule llc_mem_server_tlbQ assign llc_mem_server_tlbQ$D_IN = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__531_ETC___d1538 ? + NOT_llc_mem_server_enqDst_0_dummy2_0_read__672_ETC___d1679 ? llc_mem_server_enqDst_0_lat_0$wget[64:0] : llc_mem_server_enqDst_0_rl[64:0] ; assign llc_mem_server_tlbQ$ENQ = CAN_FIRE_RL_llc_mem_server_doEnq ; @@ -5783,87 +5626,87 @@ module mkProc(CLK, assign propDstIdx_1_dummy2_1$EN = propDstIdx_1_lat_1$whas ; // remaining internal signals - module_amoExec instance_amoExec_2(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h27604 && - mmioPlatform_reqBE_BIT_0___h27644, - 2'd0 }), - .amoExec_current_data(mmioPlatform_fromHostQ_data_0__h40231), - .amoExec_in_data(mmioPlatform_reqData__h46171), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h27604 && - !mmioPlatform_reqBE_BIT_0___h27644), - .amoExec(x__h38432)); module_amoExec instance_amoExec_0(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h27604 && - mmioPlatform_reqBE_BIT_0___h27644, + mmioPlatform_reqBE_BIT_4___h27396 && + mmioPlatform_reqBE_BIT_0___h27436, 2'd0 }), - .amoExec_current_data(x__h34898), - .amoExec_in_data(mmioPlatform_reqData__h46171), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h27604 && - !mmioPlatform_reqBE_BIT_0___h27644), - .amoExec(x__h29628)); + .amoExec_current_data(x__h34690), + .amoExec_in_data(mmioPlatform_reqData__h45963), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h27396 && + !mmioPlatform_reqBE_BIT_0___h27436), + .amoExec(x__h29420)); + module_amoExec instance_amoExec_1(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], + mmioPlatform_reqBE_BIT_4___h27396 && + mmioPlatform_reqBE_BIT_0___h27436, + 2'd0 }), + .amoExec_current_data(mmioPlatform_mtime__h34542), + .amoExec_in_data(mmioPlatform_reqData__h45963), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h27396 && + !mmioPlatform_reqBE_BIT_0___h27436), + .amoExec(x__h32330)); + module_amoExec instance_amoExec_2(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], + mmioPlatform_reqBE_BIT_4___h27396 && + mmioPlatform_reqBE_BIT_0___h27436, + 2'd0 }), + .amoExec_current_data(mmioPlatform_fromHostQ_data_0__h40023), + .amoExec_in_data(mmioPlatform_reqData__h45963), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h27396 && + !mmioPlatform_reqBE_BIT_0___h27436), + .amoExec(x__h38224)); module_amoExec instance_amoExec_3(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h27604 && - mmioPlatform_reqBE_BIT_0___h27644, + mmioPlatform_reqBE_BIT_4___h27396 && + mmioPlatform_reqBE_BIT_0___h27436, 2'd0 }), .amoExec_current_data(64'd0), - .amoExec_in_data(mmioPlatform_reqData__h46171), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h27604 && - !mmioPlatform_reqBE_BIT_0___h27644), - .amoExec(x__h40498)); - module_amoExec instance_amoExec_1(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h27604 && - mmioPlatform_reqBE_BIT_0___h27644, - 2'd0 }), - .amoExec_current_data(mmioPlatform_mtime__h34750), - .amoExec_in_data(mmioPlatform_reqData__h46171), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h27604 && - !mmioPlatform_reqBE_BIT_0___h27644), - .amoExec(x__h32538)); - assign DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_01_BIT_ETC___d645 = + .amoExec_in_data(mmioPlatform_reqData__h45963), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h27396 && + !mmioPlatform_reqBE_BIT_0___h27436), + .amoExec(x__h40290)); + assign DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_00_BIT_ETC___d644 = { 1'h0, (mmioPlatform_reqFunc[5:4] == 2'd2) ? { mmioPlatform_toHostQ_empty, 64'hAAAAAAAAAAAAAAAA } : { mmioPlatform_reqFunc[5:4] == 2'd1, - x1_avValue_data__h37903 } } ; - assign IF_IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4__ETC___d520 = - (IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515 && + x1_avValue_data__h37695 } } ; + assign IF_IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4__ETC___d519 = + (IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01__ETC___d514 && !mmioPlatform_mtip_0 || - !IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515 && + !IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01__ETC___d514 && mmioPlatform_mtip_0) ? core_0$RDY_mmioToPlatform_pRq_enq : core_0$RDY_mmioToPlatform_pRs_enq ; - assign IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d417 = + assign IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01__ETC___d416 = (mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? (mmioPlatform_reqBE[0] ? core_0$RDY_mmioToPlatform_pRq_enq : core_0$RDY_mmioToPlatform_pRs_enq) : !mmioPlatform_reqBE[0] || core_0$RDY_mmioToPlatform_pRq_enq ; - assign IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515 = - newData__h29517 <= mmioPlatform_mtime ; - assign IF_NOT_propDstIdx_0_dummy2_1_read__027_028_OR__ETC___d1062 = - NOT_propDstIdx_0_dummy2_1_read__027_028_OR_IF__ETC___d1061 ? + assign IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01__ETC___d514 = + newData__h29309 <= mmioPlatform_mtime ; + assign IF_NOT_propDstIdx_0_dummy2_1_read__026_027_OR__ETC___d1061 = + NOT_propDstIdx_0_dummy2_1_read__026_027_OR_IF__ETC___d1060 ? propDstIdx_1_dummy2_1$Q_OUT && - IF_propDstIdx_1_lat_0_whas__81_THEN_propDstIdx_ETC___d984 : + IF_propDstIdx_1_lat_0_whas__80_THEN_propDstIdx_ETC___d983 : propDstIdx_0_dummy2_1$Q_OUT && - IF_propDstIdx_0_lat_0_whas__74_THEN_propDstIdx_ETC___d977 ; - assign IF_NOT_propDstIdx_1_0_dummy2_1_read__291_292_O_ETC___d1336 = - NOT_propDstIdx_1_0_dummy2_1_read__291_292_OR_I_ETC___d1335 ? + IF_propDstIdx_0_lat_0_whas__73_THEN_propDstIdx_ETC___d976 ; + assign IF_NOT_propDstIdx_1_0_dummy2_1_read__290_291_O_ETC___d1335 = + NOT_propDstIdx_1_0_dummy2_1_read__290_291_OR_I_ETC___d1334 ? propDstIdx_1_1_dummy2_1$Q_OUT && - IF_propDstIdx_1_1_lat_0_whas__155_THEN_propDst_ETC___d1158 : + IF_propDstIdx_1_1_lat_0_whas__154_THEN_propDst_ETC___d1157 : propDstIdx_1_0_dummy2_1$Q_OUT && - IF_propDstIdx_1_0_lat_0_whas__148_THEN_propDst_ETC___d1151 ; - assign IF_SEL_ARR_propDstIdx_0_dummy2_1_read__027_AND_ETC___d1134 = - SEL_ARR_propDstIdx_0_dummy2_1_read__027_AND_IF_ETC___d1058 ? + IF_propDstIdx_1_0_lat_0_whas__147_THEN_propDst_ETC___d1150 ; + assign IF_SEL_ARR_propDstIdx_0_dummy2_1_read__026_AND_ETC___d1133 = + SEL_ARR_propDstIdx_0_dummy2_1_read__026_AND_IF_ETC___d1057 ? !srcRR_0 : propDstIdx_0_dummy2_1$Q_OUT && - IF_propDstIdx_0_lat_0_whas__74_THEN_propDstIdx_ETC___d977 ; - assign IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__291_A_ETC___d1436 = - SEL_ARR_propDstIdx_1_0_dummy2_1_read__291_AND__ETC___d1332 ? + IF_propDstIdx_0_lat_0_whas__73_THEN_propDstIdx_ETC___d976 ; + assign IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__290_A_ETC___d1435 = + SEL_ARR_propDstIdx_1_0_dummy2_1_read__290_AND__ETC___d1331 ? !srcRR_1_0 : propDstIdx_1_0_dummy2_1$Q_OUT && - IF_propDstIdx_1_0_lat_0_whas__148_THEN_propDst_ETC___d1151 ; - assign IF_core_0_mmioToPlatform_cRq_first__43_BITS_14_ETC___d366 = + IF_propDstIdx_1_0_lat_0_whas__147_THEN_propDst_ETC___d1150 ; + assign IF_core_0_mmioToPlatform_cRq_first__42_BITS_14_ETC___d365 = (core_0$mmioToPlatform_cRq_first[141:81] == mmioPlatform_toHostAddr) ? 67'h5AAAAAAAAAAAAAAAA : @@ -5871,89 +5714,116 @@ module mkProc(CLK, mmioPlatform_fromHostAddr) ? 67'h6AAAAAAAAAAAAAAAA : { 3'd7, core_0$mmioToPlatform_cRq_first[141:78] }) ; - assign IF_enqDst_0_lat_0_whas__003_THEN_enqDst_0_lat__ETC___d1008 = - NOT_enqDst_0_dummy2_0_read__048_049_OR_NOT_enq_ETC___d1064 ? + assign IF_enqDst_0_lat_0_whas__002_THEN_enqDst_0_lat__ETC___d1007 = + NOT_enqDst_0_dummy2_0_read__047_048_OR_NOT_enq_ETC___d1063 ? enqDst_0_lat_0$wget[73] : enqDst_0_rl[73] ; - assign IF_enqDst_1_0_lat_0_whas__239_THEN_enqDst_1_0__ETC___d1244 = - NOT_enqDst_1_0_dummy2_0_read__322_323_OR_NOT_e_ETC___d1338 ? + assign IF_enqDst_1_0_lat_0_whas__238_THEN_enqDst_1_0__ETC___d1243 = + NOT_enqDst_1_0_dummy2_0_read__321_322_OR_NOT_e_ETC___d1337 ? enqDst_1_0_lat_0$wget[580] : enqDst_1_0_rl[580] ; - assign IF_enqDst_1_0_lat_0_whas__239_THEN_enqDst_1_0__ETC___d1254 = - NOT_enqDst_1_0_dummy2_0_read__322_323_OR_NOT_e_ETC___d1338 ? + assign IF_enqDst_1_0_lat_0_whas__238_THEN_enqDst_1_0__ETC___d1253 = + NOT_enqDst_1_0_dummy2_0_read__321_322_OR_NOT_e_ETC___d1337 ? enqDst_1_0_lat_0$wget[579:516] : enqDst_1_0_rl[579:516] ; - assign IF_enqDst_1_0_lat_0_whas__239_THEN_enqDst_1_0__ETC___d1259 = - NOT_enqDst_1_0_dummy2_0_read__322_323_OR_NOT_e_ETC___d1338 ? + assign IF_enqDst_1_0_lat_0_whas__238_THEN_enqDst_1_0__ETC___d1258 = + NOT_enqDst_1_0_dummy2_0_read__321_322_OR_NOT_e_ETC___d1337 ? enqDst_1_0_lat_0$wget[515:514] : enqDst_1_0_rl[515:514] ; - assign IF_enqDst_1_0_lat_0_whas__239_THEN_enqDst_1_0__ETC___d1264 = - NOT_enqDst_1_0_dummy2_0_read__322_323_OR_NOT_e_ETC___d1338 ? + assign IF_enqDst_1_0_lat_0_whas__238_THEN_enqDst_1_0__ETC___d1263 = + NOT_enqDst_1_0_dummy2_0_read__321_322_OR_NOT_e_ETC___d1337 ? enqDst_1_0_lat_0$wget[513] : enqDst_1_0_rl[513] ; - assign IF_enqDst_1_0_lat_0_whas__239_THEN_enqDst_1_0__ETC___d1274 = - NOT_enqDst_1_0_dummy2_0_read__322_323_OR_NOT_e_ETC___d1338 ? + assign IF_enqDst_1_0_lat_0_whas__238_THEN_enqDst_1_0__ETC___d1273 = + NOT_enqDst_1_0_dummy2_0_read__321_322_OR_NOT_e_ETC___d1337 ? enqDst_1_0_lat_0$wget[512:1] : enqDst_1_0_rl[512:1] ; - assign IF_enqDst_1_0_lat_0_whas__239_THEN_enqDst_1_0__ETC___d1280 = - NOT_enqDst_1_0_dummy2_0_read__322_323_OR_NOT_e_ETC___d1338 ? + assign IF_enqDst_1_0_lat_0_whas__238_THEN_enqDst_1_0__ETC___d1279 = + NOT_enqDst_1_0_dummy2_0_read__321_322_OR_NOT_e_ETC___d1337 ? enqDst_1_0_lat_0$wget[0] : enqDst_1_0_rl[0] ; - assign IF_enqDst_1_0_lat_1_whas__236_THEN_enqDst_1_0__ETC___d1282 = + assign IF_enqDst_1_0_lat_1_whas__235_THEN_enqDst_1_0__ETC___d1281 = { CAN_FIRE_RL_doEnq_1 || - IF_enqDst_1_0_lat_0_whas__239_THEN_enqDst_1_0__ETC___d1264, + IF_enqDst_1_0_lat_0_whas__238_THEN_enqDst_1_0__ETC___d1263, CAN_FIRE_RL_doEnq_1 ? 512'h55555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555 : - IF_enqDst_1_0_lat_0_whas__239_THEN_enqDst_1_0__ETC___d1274, - x__h72715 } ; - assign IF_enqDst_1_0_lat_1_whas__236_THEN_enqDst_1_0__ETC___d1283 = + IF_enqDst_1_0_lat_0_whas__238_THEN_enqDst_1_0__ETC___d1273, + x__h72507 } ; + assign IF_enqDst_1_0_lat_1_whas__235_THEN_enqDst_1_0__ETC___d1282 = { CAN_FIRE_RL_doEnq_1 ? 64'hAAAAAAAAAAAAAAAA : - IF_enqDst_1_0_lat_0_whas__239_THEN_enqDst_1_0__ETC___d1254, + IF_enqDst_1_0_lat_0_whas__238_THEN_enqDst_1_0__ETC___d1253, CAN_FIRE_RL_doEnq_1 ? 2'b10 : - IF_enqDst_1_0_lat_0_whas__239_THEN_enqDst_1_0__ETC___d1259, - IF_enqDst_1_0_lat_1_whas__236_THEN_enqDst_1_0__ETC___d1282 } ; - assign IF_llc_mem_server_enqDst_0_lat_0_whas__500_THE_ETC___d1505 = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__531_ETC___d1538 ? + IF_enqDst_1_0_lat_0_whas__238_THEN_enqDst_1_0__ETC___d1258, + IF_enqDst_1_0_lat_1_whas__235_THEN_enqDst_1_0__ETC___d1281 } ; + assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1556 = + { (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == + 3'd7) ? + new_dword__h87351 : + llc_mem_server_rg_cacheline_cache_data[511:448], + (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == + 3'd6) ? + new_dword__h87351 : + llc_mem_server_rg_cacheline_cache_data[447:384], + (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == + 3'd5) ? + new_dword__h87351 : + llc_mem_server_rg_cacheline_cache_data[383:320], + (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == + 3'd4) ? + new_dword__h87351 : + llc_mem_server_rg_cacheline_cache_data[319:256] } ; + assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1561 = + { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1556, + (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == + 3'd3) ? + new_dword__h87351 : + llc_mem_server_rg_cacheline_cache_data[255:192], + (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == + 3'd2) ? + new_dword__h87351 : + llc_mem_server_rg_cacheline_cache_data[191:128] } ; + assign IF_llc_mem_server_enqDst_0_lat_0_whas__641_THE_ETC___d1646 = + NOT_llc_mem_server_enqDst_0_dummy2_0_read__672_ETC___d1679 ? llc_mem_server_enqDst_0_lat_0$wget[65] : llc_mem_server_enqDst_0_rl[65] ; - assign IF_llc_mem_server_propDstIdx_0_lat_0_whas__485_ETC___d1488 = + assign IF_llc_mem_server_propDstIdx_0_lat_0_whas__626_ETC___d1629 = CAN_FIRE_RL_llc_mem_server_srcPropose || llc_mem_server_propDstIdx_0_rl ; - assign IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d794 = + assign IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d793 = (mmioPlatform_curReq[2:0] == 3'h0) ? mmioPlatform_reqData : 64'd0 ; - assign IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d845 = + assign IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d844 = (mmioPlatform_curReq[2:0] == 3'h0) ? mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:0] : 64'd0 ; - assign IF_mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioP_ETC___d586 = - ((mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 && + assign IF_mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioP_ETC___d585 = + ((mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioPlat_ETC___d576 && !mmioPlatform_mtip_0) ? core_0$RDY_mmioToPlatform_pRq_enq : - mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 || + mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioPlat_ETC___d576 || !mmioPlatform_mtip_0 || core_0$RDY_mmioToPlatform_pRq_enq) && - (mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 && + (mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioPlat_ETC___d576 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 && + !mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioPlat_ETC___d576 && mmioPlatform_mtip_0 || core_0$RDY_mmioToPlatform_pRs_enq) ; - assign IF_mmioPlatform_reqBE_04_BIT_4_05_THEN_SEXT_mm_ETC___d538 = + assign IF_mmioPlatform_reqBE_03_BIT_4_04_THEN_SEXT_mm_ETC___d537 = mmioPlatform_reqBE[4] ? - { {32{mmioPlatform_mtimecmp_0_BITS_63_TO_32__q9[31]}}, - mmioPlatform_mtimecmp_0_BITS_63_TO_32__q9 } : - { {32{mmioPlatform_mtimecmp_0_BITS_31_TO_0__q10[31]}}, - mmioPlatform_mtimecmp_0_BITS_31_TO_0__q10 } ; - assign IF_mmioPlatform_reqBE_04_BIT_4_05_THEN_SEXT_mm_ETC___d602 = + { {32{mmioPlatform_mtimecmp_0_BITS_63_TO_32__q1[31]}}, + mmioPlatform_mtimecmp_0_BITS_63_TO_32__q1 } : + { {32{mmioPlatform_mtimecmp_0_BITS_31_TO_0__q2[31]}}, + mmioPlatform_mtimecmp_0_BITS_31_TO_0__q2 } ; + assign IF_mmioPlatform_reqBE_03_BIT_4_04_THEN_SEXT_mm_ETC___d601 = mmioPlatform_reqBE[4] ? - { {32{mmioPlatform_mtime_BITS_63_TO_32__q11[31]}}, - mmioPlatform_mtime_BITS_63_TO_32__q11 } : - { {32{mmioPlatform_mtime_BITS_31_TO_0__q12[31]}}, - mmioPlatform_mtime_BITS_31_TO_0__q12 } ; - assign IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d496 = + { {32{mmioPlatform_mtime_BITS_63_TO_32__q3[31]}}, + mmioPlatform_mtime_BITS_63_TO_32__q3 } : + { {32{mmioPlatform_mtime_BITS_31_TO_0__q4[31]}}, + mmioPlatform_mtime_BITS_31_TO_0__q4 } ; + assign IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d495 = { mmioPlatform_reqBE[7] ? mmioPlatform_reqData[63:56] : mmioPlatform_mtimecmp_0[63:56], @@ -5966,23 +5836,23 @@ module mkProc(CLK, mmioPlatform_reqBE[4] ? mmioPlatform_reqData[39:32] : mmioPlatform_mtimecmp_0[39:32] } ; - assign IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d505 = - { IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d496, + assign IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d504 = + { IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d495, mmioPlatform_reqBE[3] ? mmioPlatform_reqData[31:24] : mmioPlatform_mtimecmp_0[31:24], mmioPlatform_reqBE[2] ? mmioPlatform_reqData[23:16] : mmioPlatform_mtimecmp_0[23:16] } ; - assign IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d513 = - { IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d505, + assign IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d512 = + { IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d504, mmioPlatform_reqBE[1] ? mmioPlatform_reqData[15:8] : mmioPlatform_mtimecmp_0[15:8], mmioPlatform_reqBE[0] ? mmioPlatform_reqData[7:0] : mmioPlatform_mtimecmp_0[7:0] } ; - assign IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d565 = + assign IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d564 = { mmioPlatform_reqBE[7] ? mmioPlatform_reqData[63:56] : mmioPlatform_mtime[63:56], @@ -5995,23 +5865,23 @@ module mkProc(CLK, mmioPlatform_reqBE[4] ? mmioPlatform_reqData[39:32] : mmioPlatform_mtime[39:32] } ; - assign IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d570 = - { IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d565, + assign IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d569 = + { IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d564, mmioPlatform_reqBE[3] ? mmioPlatform_reqData[31:24] : mmioPlatform_mtime[31:24], mmioPlatform_reqBE[2] ? mmioPlatform_reqData[23:16] : mmioPlatform_mtime[23:16] } ; - assign IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d575 = - { IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d570, + assign IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d574 = + { IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d569, mmioPlatform_reqBE[1] ? mmioPlatform_reqData[15:8] : mmioPlatform_mtime[15:8], mmioPlatform_reqBE[0] ? mmioPlatform_reqData[7:0] : mmioPlatform_mtime[7:0] } ; - assign IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d669 = + assign IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d668 = { mmioPlatform_reqBE[7] ? mmioPlatform_reqData[63:56] : mmioPlatform_fromHostQ_data_0[63:56], @@ -6024,49 +5894,49 @@ module mkProc(CLK, mmioPlatform_reqBE[4] ? mmioPlatform_reqData[39:32] : mmioPlatform_fromHostQ_data_0[39:32] } ; - assign IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d674 = - { IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d669, + assign IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d673 = + { IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d668, mmioPlatform_reqBE[3] ? mmioPlatform_reqData[31:24] : mmioPlatform_fromHostQ_data_0[31:24], mmioPlatform_reqBE[2] ? mmioPlatform_reqData[23:16] : mmioPlatform_fromHostQ_data_0[23:16] } ; - assign IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d679 = - { IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d674, + assign IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d678 = + { IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d673, mmioPlatform_reqBE[1] ? mmioPlatform_reqData[15:8] : mmioPlatform_fromHostQ_data_0[15:8], mmioPlatform_reqBE[0] ? mmioPlatform_reqData[7:0] : mmioPlatform_fromHostQ_data_0[7:0] } ; - assign IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_ETC___d418 = + assign IF_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_ETC___d417 = (mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqBE[4]) ? core_0$RDY_mmioToPlatform_pRs_enq : - IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d417 ; - assign IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_1_ETC___d539 = + IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01__ETC___d416 ; + assign IF_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_1_ETC___d538 = (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtimecmp_0 : - IF_mmioPlatform_reqBE_04_BIT_4_05_THEN_SEXT_mm_ETC___d538 ; - assign IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_1_ETC___d603 = + IF_mmioPlatform_reqBE_03_BIT_4_04_THEN_SEXT_mm_ETC___d537 ; + assign IF_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_1_ETC___d602 = (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtime : - IF_mmioPlatform_reqBE_04_BIT_4_05_THEN_SEXT_mm_ETC___d602 ; - assign IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_2_ETC___d687 = + IF_mmioPlatform_reqBE_03_BIT_4_04_THEN_SEXT_mm_ETC___d601 ; + assign IF_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_2_ETC___d686 = (mmioPlatform_reqFunc[5:4] == 2'd2) ? { mmioPlatform_fromHostQ_empty ? - x__h40487 == 64'd0 : - x__h38421 == 64'd0, + x__h40279 == 64'd0 : + x__h38213 == 64'd0, 64'hAAAAAAAAAAAAAAAA } : { mmioPlatform_reqFunc[5:4] == 2'd1, - x1_avValue_data__h42508 } ; - assign IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__56__ETC___d165 = + x1_avValue_data__h42300 } ; + assign IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__55__ETC___d164 = mmioPlatform_toHostQ_enqReq_lat_0$whas ? mmioPlatform_toHostQ_enqReq_lat_0$wget[64] : mmioPlatform_toHostQ_enqReq_rl[64] ; - assign IF_mmioPlatform_waitLowerMSIPCRs_53_THEN_core__ETC___d461 = + assign IF_mmioPlatform_waitLowerMSIPCRs_52_THEN_core__ETC___d460 = mmioPlatform_waitLowerMSIPCRs ? core_0$RDY_mmioToPlatform_cRs_first && core_0$RDY_mmioToPlatform_cRs_deq : @@ -6074,94 +5944,94 @@ module mkProc(CLK, core_0$RDY_mmioToPlatform_cRs_first) && (!mmioPlatform_waitUpperMSIPCRs || core_0$RDY_mmioToPlatform_cRs_deq) ; - assign IF_mmio_axi4_adapter_f_rsps_to_core_first__25__ETC___d939 = + assign IF_mmio_axi4_adapter_f_rsps_to_core_first__24__ETC___d938 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] ? mmioPlatform_fetchingWay < (mmioPlatform_reqFunc[5:4] == 2'd0 && mmioPlatform_reqFunc[0]) || core_0$RDY_mmioToPlatform_pRs_enq : core_0$RDY_mmioToPlatform_pRs_enq ; - assign IF_mmio_axi4_adapter_f_rsps_to_core_first__25__ETC___d960 = + assign IF_mmio_axi4_adapter_f_rsps_to_core_first__24__ETC___d959 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] ? (mmioPlatform_fetchingWay ? mmioPlatform_fetchedInsts_0 : - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d952) : + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d951) : mmioPlatform_fetchedInsts_0 ; - assign IF_propDstData_0_dummy2_1_read__065_THEN_IF_pr_ETC___d1081 = + assign IF_propDstData_0_dummy2_1_read__064_THEN_IF_pr_ETC___d1080 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[8:7] : propDstData_0_rl[8:7]) : 2'd0 ; - assign IF_propDstData_0_dummy2_1_read__065_THEN_IF_pr_ETC___d1091 = + assign IF_propDstData_0_dummy2_1_read__064_THEN_IF_pr_ETC___d1090 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[6:5] : propDstData_0_rl[6:5]) : 2'd0 ; - assign IF_propDstData_1_0_lat_0_whas__163_THEN_propDs_ETC___d1168 = + assign IF_propDstData_1_0_lat_0_whas__162_THEN_propDs_ETC___d1167 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[579:516] : propDstData_1_0_rl[579:516] ; - assign IF_propDstData_1_0_lat_0_whas__163_THEN_propDs_ETC___d1173 = + assign IF_propDstData_1_0_lat_0_whas__162_THEN_propDs_ETC___d1172 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[515:514] : propDstData_1_0_rl[515:514] ; - assign IF_propDstData_1_0_lat_0_whas__163_THEN_propDs_ETC___d1194 = + assign IF_propDstData_1_0_lat_0_whas__162_THEN_propDs_ETC___d1193 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[0] : propDstData_1_0_rl[0] ; - assign IF_propDstData_1_1_lat_0_whas__201_THEN_propDs_ETC___d1206 = + assign IF_propDstData_1_1_lat_0_whas__200_THEN_propDs_ETC___d1205 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[579:516] : propDstData_1_1_rl[579:516] ; - assign IF_propDstData_1_1_lat_0_whas__201_THEN_propDs_ETC___d1211 = + assign IF_propDstData_1_1_lat_0_whas__200_THEN_propDs_ETC___d1210 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[515:514] : propDstData_1_1_rl[515:514] ; - assign IF_propDstData_1_1_lat_0_whas__201_THEN_propDs_ETC___d1232 = + assign IF_propDstData_1_1_lat_0_whas__200_THEN_propDs_ETC___d1231 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[0] : propDstData_1_1_rl[0] ; - assign IF_propDstData_1_dummy2_1_read__070_THEN_IF_pr_ETC___d1085 = + assign IF_propDstData_1_dummy2_1_read__069_THEN_IF_pr_ETC___d1084 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[8:7] : propDstData_1_rl[8:7]) : 2'd0 ; - assign IF_propDstData_1_dummy2_1_read__070_THEN_IF_pr_ETC___d1095 = + assign IF_propDstData_1_dummy2_1_read__069_THEN_IF_pr_ETC___d1094 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[6:5] : propDstData_1_rl[6:5]) : 2'd0 ; - assign IF_propDstIdx_0_lat_0_whas__74_THEN_propDstIdx_ETC___d977 = + assign IF_propDstIdx_0_lat_0_whas__73_THEN_propDstIdx_ETC___d976 = CAN_FIRE_RL_srcPropose || propDstIdx_0_rl ; - assign IF_propDstIdx_1_0_lat_0_whas__148_THEN_propDst_ETC___d1151 = + assign IF_propDstIdx_1_0_lat_0_whas__147_THEN_propDst_ETC___d1150 = CAN_FIRE_RL_srcPropose_2 || propDstIdx_1_0_rl ; - assign IF_propDstIdx_1_1_lat_0_whas__155_THEN_propDst_ETC___d1158 = + assign IF_propDstIdx_1_1_lat_0_whas__154_THEN_propDst_ETC___d1157 = CAN_FIRE_RL_srcPropose_3 || propDstIdx_1_1_rl ; - assign IF_propDstIdx_1_lat_0_whas__81_THEN_propDstIdx_ETC___d984 = + assign IF_propDstIdx_1_lat_0_whas__80_THEN_propDstIdx_ETC___d983 = CAN_FIRE_RL_srcPropose_1 || propDstIdx_1_rl ; - assign NOT_enqDst_0_dummy2_0_read__048_049_OR_NOT_enq_ETC___d1064 = + assign NOT_enqDst_0_dummy2_0_read__047_048_OR_NOT_enq_ETC___d1063 = (!enqDst_0_dummy2_0$Q_OUT || !enqDst_0_dummy2_1$Q_OUT || !enqDst_0_rl[73]) && - (SEL_ARR_propDstIdx_0_dummy2_1_read__027_AND_IF_ETC___d1058 || - IF_NOT_propDstIdx_0_dummy2_1_read__027_028_OR__ETC___d1062) ; - assign NOT_enqDst_1_0_dummy2_0_read__322_323_OR_NOT_e_ETC___d1338 = + (SEL_ARR_propDstIdx_0_dummy2_1_read__026_AND_IF_ETC___d1057 || + IF_NOT_propDstIdx_0_dummy2_1_read__026_027_OR__ETC___d1061) ; + assign NOT_enqDst_1_0_dummy2_0_read__321_322_OR_NOT_e_ETC___d1337 = (!enqDst_1_0_dummy2_0$Q_OUT || !enqDst_1_0_dummy2_1$Q_OUT || !enqDst_1_0_rl[580]) && - (SEL_ARR_propDstIdx_1_0_dummy2_1_read__291_AND__ETC___d1332 || - IF_NOT_propDstIdx_1_0_dummy2_1_read__291_292_O_ETC___d1336) ; - assign NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785 = + (SEL_ARR_propDstIdx_1_0_dummy2_1_read__290_AND__ETC___d1331 || + IF_NOT_propDstIdx_1_0_dummy2_1_read__290_291_O_ETC___d1335) ; + assign NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763 = llc_axi4_adapter_cfg_verbosity > 4'd1 ; - assign NOT_llc_mem_server_enqDst_0_dummy2_0_read__531_ETC___d1538 = + assign NOT_llc_mem_server_enqDst_0_dummy2_0_read__672_ETC___d1679 = (!llc_mem_server_enqDst_0_dummy2_0$Q_OUT || !llc_mem_server_enqDst_0_dummy2_1$Q_OUT || !llc_mem_server_enqDst_0_rl[65]) && llc_mem_server_propDstIdx_0_dummy2_1$Q_OUT && - IF_llc_mem_server_propDstIdx_0_lat_0_whas__485_ETC___d1488 ; - assign NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d715 = + IF_llc_mem_server_propDstIdx_0_lat_0_whas__626_ETC___d1629 ; + assign NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d714 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -6172,7 +6042,7 @@ module mkProc(CLK, mmioPlatform_state == 2'd2 && (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqFunc[5:4] == 2'd2) ; - assign NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d723 = + assign NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d722 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -6183,7 +6053,7 @@ module mkProc(CLK, mmioPlatform_state == 2'd3 && (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqFunc[5:4] == 2'd2) ; - assign NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d728 = + assign NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d727 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -6195,7 +6065,7 @@ module mkProc(CLK, mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2 ; - assign NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d738 = + assign NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d737 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -6207,7 +6077,7 @@ module mkProc(CLK, mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2 ; - assign NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d929 = + assign NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d928 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -6217,7 +6087,7 @@ module mkProc(CLK, mmioPlatform_curReq[66:64] != 3'd6 && mmioPlatform_state == 2'd2 && mmioPlatform_reqFunc[5:4] == 2'd0 ; - assign NOT_mmioPlatform_curReq_96_BITS_66_TO_64_97_EQ_ETC___d942 = + assign NOT_mmioPlatform_curReq_95_BITS_66_TO_64_96_EQ_ETC___d941 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -6227,44 +6097,44 @@ module mkProc(CLK, mmioPlatform_curReq[66:64] != 3'd6 && mmioPlatform_state == 2'd3 && mmioPlatform_reqFunc[5:4] == 2'd0 ; - assign NOT_mmioPlatform_fromHostQ_clearReq_dummy2_1_r_ETC___d283 = + assign NOT_mmioPlatform_fromHostQ_clearReq_dummy2_1_r_ETC___d282 = !mmioPlatform_fromHostQ_clearReq_dummy2_1$Q_OUT || !mmioPlatform_fromHostQ_clearReq_rl ; - assign NOT_mmioPlatform_fromHostQ_enqReq_dummy2_2_rea_ETC___d304 = + assign NOT_mmioPlatform_fromHostQ_enqReq_dummy2_2_rea_ETC___d303 = (!mmioPlatform_fromHostQ_enqReq_dummy2_2$Q_OUT || !mmioPlatform_fromHostQ_enqReq_rl[64]) && (mmioPlatform_fromHostQ_deqReq_dummy2_2$Q_OUT && (mmioPlatform_fromHostQ_deqReq_lat_0$whas || mmioPlatform_fromHostQ_deqReq_rl) || mmioPlatform_fromHostQ_empty) ; - assign NOT_mmioPlatform_mtip_0_20_27_AND_mmioPlatform_ETC___d335 = + assign NOT_mmioPlatform_mtip_0_19_26_AND_mmioPlatform_ETC___d334 = !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322 || + mmioPlatform_mtimecmp_0_20_ULE_mmioPlatform_mt_ETC___d321 || !core_0$mmioToPlatform_cRq_notEmpty || core_0$RDY_mmioToPlatform_cRq_first && core_0$RDY_mmioToPlatform_cRq_deq ; - assign NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ__ETC___d451 = + assign NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ__ETC___d450 = mmioPlatform_reqFunc[5:4] != 2'd0 && !mmioPlatform_reqBE[4] && (mmioPlatform_reqBE[0] || mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqFunc[5:4] == 2'd2) ; - assign NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ__ETC___d546 = + assign NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ__ETC___d545 = mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && - (IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515 && + (IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01__ETC___d514 && !mmioPlatform_mtip_0 || - !IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515 && + !IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01__ETC___d514 && mmioPlatform_mtip_0) ; - assign NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ__ETC___d609 = + assign NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ__ETC___d608 = mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && - (mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 && + (mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioPlat_ETC___d576 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 && + !mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioPlat_ETC___d576 && mmioPlatform_mtip_0) ; - assign NOT_mmioPlatform_toHostQ_clearReq_dummy2_1_rea_ETC___d205 = + assign NOT_mmioPlatform_toHostQ_clearReq_dummy2_1_rea_ETC___d204 = !mmioPlatform_toHostQ_clearReq_dummy2_1$Q_OUT || !mmioPlatform_toHostQ_clearReq_rl ; - assign NOT_mmioPlatform_toHostQ_enqReq_dummy2_2_read__ETC___d226 = + assign NOT_mmioPlatform_toHostQ_enqReq_dummy2_2_read__ETC___d225 = (!mmioPlatform_toHostQ_enqReq_dummy2_2$Q_OUT || (mmioPlatform_toHostQ_enqReq_lat_0$whas ? !mmioPlatform_toHostQ_enqReq_lat_0$wget[64] : @@ -6273,378 +6143,384 @@ module mkProc(CLK, (!mmioPlatform_toHostQ_empty || mmioPlatform_toHostQ_deqReq_rl) || mmioPlatform_toHostQ_empty) ; - assign NOT_propDstData_1_0_dummy2_1_read__339_350_OR__ETC___d1351 = + assign NOT_propDstData_1_0_dummy2_1_read__338_349_OR__ETC___d1350 = !propDstData_1_0_dummy2_1$Q_OUT || (CAN_FIRE_RL_srcPropose_2 ? !propDstData_1_0_lat_0$wget[513] : !propDstData_1_0_rl[513]) ; - assign NOT_propDstData_1_1_dummy2_1_read__341_352_OR__ETC___d1353 = + assign NOT_propDstData_1_1_dummy2_1_read__340_351_OR__ETC___d1352 = !propDstData_1_1_dummy2_1$Q_OUT || (CAN_FIRE_RL_srcPropose_3 ? !propDstData_1_1_lat_0$wget[513] : !propDstData_1_1_rl[513]) ; - assign NOT_propDstIdx_0_dummy2_1_read__027_028_OR_IF__ETC___d1061 = + assign NOT_propDstIdx_0_dummy2_1_read__026_027_OR_IF__ETC___d1060 = !propDstIdx_0_dummy2_1$Q_OUT || !CAN_FIRE_RL_srcPropose && !propDstIdx_0_rl ; - assign NOT_propDstIdx_1_0_dummy2_1_read__291_292_OR_I_ETC___d1335 = + assign NOT_propDstIdx_1_0_dummy2_1_read__290_291_OR_I_ETC___d1334 = !propDstIdx_1_0_dummy2_1$Q_OUT || !CAN_FIRE_RL_srcPropose_2 && !propDstIdx_1_0_rl ; - assign SEL_ARR_IF_propDstData_0_dummy2_1_read__065_TH_ETC___d1129 = - { CASE_x8979_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21, - CASE_x8979_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22, - SEL_ARR_propDstData_0_dummy2_1_read__065_AND_I_ETC___d1128 } ; - assign SEL_ARR_IF_propDstData_1_0_dummy2_1_read__339__ETC___d1431 = - { CASE_x7786_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32, - !CASE_x7786_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__163_THE_ETC___d1424, - x__h80202 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__163_THE_ETC___d1373 = - { CASE_x7786_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24, - CASE_x7786_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__163_THE_ETC___d1390 = - { SEL_ARR_IF_propDstData_1_0_lat_0_whas__163_THE_ETC___d1373, - CASE_x7786_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26, - CASE_x7786_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__163_THE_ETC___d1407 = - { SEL_ARR_IF_propDstData_1_0_lat_0_whas__163_THE_ETC___d1390, - CASE_x7786_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28, - CASE_x7786_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__163_THE_ETC___d1424 = - { SEL_ARR_IF_propDstData_1_0_lat_0_whas__163_THE_ETC___d1407, - CASE_x7786_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30, - CASE_x7786_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 } ; - assign SEL_ARR_propDstData_0_dummy2_1_read__065_AND_I_ETC___d1128 = - { CASE_x8979_0_propDstData_0_dummy2_1_read__065__ETC__q20, - x__h59293, - x__h59300 } ; - assign b__h123570 = + assign SEL_ARR_IF_propDstData_0_dummy2_1_read__064_TH_ETC___d1128 = + { CASE_x8771_0_IF_propDstData_0_dummy2_1_read__0_ETC__q13, + CASE_x8771_0_IF_propDstData_0_dummy2_1_read__0_ETC__q14, + SEL_ARR_propDstData_0_dummy2_1_read__064_AND_I_ETC___d1127 } ; + assign SEL_ARR_IF_propDstData_1_0_dummy2_1_read__338__ETC___d1430 = + { CASE_x7578_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24, + !CASE_x7578_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__162_THE_ETC___d1423, + x__h79994 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__162_THE_ETC___d1372 = + { CASE_x7578_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16, + CASE_x7578_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__162_THE_ETC___d1389 = + { SEL_ARR_IF_propDstData_1_0_lat_0_whas__162_THE_ETC___d1372, + CASE_x7578_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18, + CASE_x7578_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__162_THE_ETC___d1406 = + { SEL_ARR_IF_propDstData_1_0_lat_0_whas__162_THE_ETC___d1389, + CASE_x7578_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20, + CASE_x7578_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__162_THE_ETC___d1423 = + { SEL_ARR_IF_propDstData_1_0_lat_0_whas__162_THE_ETC___d1406, + CASE_x7578_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22, + CASE_x7578_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 } ; + assign SEL_ARR_propDstData_0_dummy2_1_read__064_AND_I_ETC___d1127 = + { CASE_x8771_0_propDstData_0_dummy2_1_read__064__ETC__q12, + x__h59085, + x__h59092 } ; + assign b__h131661 = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ? llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 : llc_axi4_adapter_ctr_wr_rsps_pending_crg ; - assign b__h2359 = + assign b__h2154 = CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req ? mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 : mmio_axi4_adapter_ctr_wr_rsps_pending_crg ; - assign data__h29436 = + assign data__h29228 = mmioPlatform_waitLowerMSIPCRs ? { 63'd0, core_0$mmioToPlatform_cRs_first } : - { v__h29229, 32'd0 } ; - assign failed_testnum__h152501 = + { v__h29021, 32'd0 } ; + assign failed_testnum__h160439 = { 1'd0, mmioPlatform_toHostQ_data_0[63:1] } ; - assign line_addr__h105593 = + assign line_addr__h99724 = + { llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[92:35], + 6'b0 } ; + assign line_addr__h99810 = { llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[92:35], 6'b0 } ; - assign llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1605 = - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == - 8'd0 && - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] == - 3'b0 || - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] == - 3'b001 || - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] == - 3'b010 || - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] == - 3'b011) && - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[0] ; - assign llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1644 = - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == - 8'd0 && - (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] == - 3'b0 || - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] == - 3'b001 || - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] == - 3'b010 || - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] == - 3'b011) && - !llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[0] ; - assign mem_req_rd_addr_araddr__h123863 = - { llc$to_mem_toM_first[68:11], x__h123898 } ; - assign mem_req_wr_addr_awaddr__h137787 = - { llc$to_mem_toM_first[639:582], x__h137812 } ; - assign mmioPlatform_cycle_12_ULT_99___d313 = mmioPlatform_cycle < 7'd99 ; - assign mmioPlatform_fetchingWay_34_ULT_mmioPlatform_r_ETC___d944 = + assign llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1573 = + line_addr__h99810 == llc_mem_server_rg_cacheline_cache_addr ; + assign llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1495 = + line_addr__h99724 == llc_mem_server_rg_cacheline_cache_addr ; + assign mask__h87347 = + { llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8] ? + 8'hFF : + 8'h0, + llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[7] ? + 8'hFF : + 8'h0, + llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[6] ? + 8'hFF : + 8'h0, + llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[5] ? + 8'hFF : + 8'h0, + llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[4] ? + 8'hFF : + 8'h0, + llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[3] ? + 8'hFF : + 8'h0, + llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[2] ? + 8'hFF : + 8'h0, + llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[1] ? + 8'hFF : + 8'h0 } ; + assign mem_req_rd_addr_araddr__h131954 = + { llc$to_mem_toM_first[68:11], x__h131989 } ; + assign mem_req_wr_addr_awaddr__h145878 = + { llc$to_mem_toM_first[639:582], x__h145903 } ; + assign mmioPlatform_cycle_11_ULT_99___d312 = mmioPlatform_cycle < 7'd99 ; + assign mmioPlatform_fetchingWay_33_ULT_mmioPlatform_r_ETC___d943 = mmioPlatform_fetchingWay < mmioPlatform_reqFunc[0] ; - assign mmioPlatform_fromHostQ_data_0__h40231 = + assign mmioPlatform_fromHostQ_data_0__h40023 = mmioPlatform_fromHostQ_data_0 ; - assign mmioPlatform_fromHostQ_enqReq_dummy2_2_read__8_ETC___d296 = + assign mmioPlatform_fromHostQ_enqReq_dummy2_2_read__8_ETC___d295 = mmioPlatform_fromHostQ_enqReq_dummy2_2$Q_OUT && mmioPlatform_fromHostQ_enqReq_rl[64] || (!mmioPlatform_fromHostQ_deqReq_dummy2_2$Q_OUT || !mmioPlatform_fromHostQ_deqReq_lat_0$whas && !mmioPlatform_fromHostQ_deqReq_rl) && mmioPlatform_fromHostQ_full ; - assign mmioPlatform_mtime_BITS_31_TO_0__q12 = mmioPlatform_mtime[31:0] ; - assign mmioPlatform_mtime_BITS_63_TO_32__q11 = mmioPlatform_mtime[63:32] ; - assign mmioPlatform_mtime__h34750 = mmioPlatform_mtime ; - assign mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 = - mmioPlatform_mtimecmp_0 <= newData__h32447 ; - assign mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322 = + assign mmioPlatform_mtime_BITS_31_TO_0__q4 = mmioPlatform_mtime[31:0] ; + assign mmioPlatform_mtime_BITS_63_TO_32__q3 = mmioPlatform_mtime[63:32] ; + assign mmioPlatform_mtime__h34542 = mmioPlatform_mtime ; + assign mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioPlat_ETC___d576 = + mmioPlatform_mtimecmp_0 <= newData__h32239 ; + assign mmioPlatform_mtimecmp_0_20_ULE_mmioPlatform_mt_ETC___d321 = mmioPlatform_mtimecmp_0 <= mmioPlatform_mtime ; - assign mmioPlatform_mtimecmp_0_BITS_31_TO_0__q10 = + assign mmioPlatform_mtimecmp_0_BITS_31_TO_0__q2 = mmioPlatform_mtimecmp_0[31:0] ; - assign mmioPlatform_mtimecmp_0_BITS_63_TO_32__q9 = + assign mmioPlatform_mtimecmp_0_BITS_63_TO_32__q1 = mmioPlatform_mtimecmp_0[63:32] ; - assign mmioPlatform_reqBE_BIT_0___h27644 = mmioPlatform_reqBE[0] ; - assign mmioPlatform_reqBE_BIT_4___h27604 = mmioPlatform_reqBE[4] ; - assign mmioPlatform_reqData__h46171 = mmioPlatform_reqData ; - assign mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_03_ETC___d428 = + assign mmioPlatform_reqBE_BIT_0___h27436 = mmioPlatform_reqBE[0] ; + assign mmioPlatform_reqBE_BIT_4___h27396 = mmioPlatform_reqBE[4] ; + assign mmioPlatform_reqData__h45963 = mmioPlatform_reqData ; + assign mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_02_ETC___d427 = mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqBE[4] || mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2 && !mmioPlatform_reqBE[0] ; - assign mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_03_ETC___d532 = + assign mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_02_ETC___d531 = mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqFunc[5:4] == 2'd1 || - (!IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515 || + (!IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01__ETC___d514 || mmioPlatform_mtip_0) && - (IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515 || + (IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4_01__ETC___d514 || !mmioPlatform_mtip_0) ; - assign mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_03_ETC___d597 = + assign mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_02_ETC___d596 = mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqFunc[5:4] == 2'd1 || - (!mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 || + (!mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioPlat_ETC___d576 || mmioPlatform_mtip_0) && - (mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 || + (mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioPlat_ETC___d576 || !mmioPlatform_mtip_0) ; - assign mmioPlatform_toHostQ_enqReq_dummy2_2_read__06__ETC___d218 = + assign mmioPlatform_toHostQ_enqReq_dummy2_2_read__05__ETC___d217 = mmioPlatform_toHostQ_enqReq_dummy2_2$Q_OUT && - IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__56__ETC___d165 || + IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__55__ETC___d164 || (!mmioPlatform_toHostQ_deqReq_dummy2_2$Q_OUT || !(!mmioPlatform_toHostQ_empty) && !mmioPlatform_toHostQ_deqReq_rl) && mmioPlatform_toHostQ_full ; - assign n__read_addr__h59161 = + assign n__read_addr__h58953 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[72:9] : propDstData_0_rl[72:9]) : 64'd0 ; - assign n__read_addr__h59246 = + assign n__read_addr__h59038 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[72:9] : propDstData_1_rl[72:9]) : 64'd0 ; - assign n__read_addr__h77964 = + assign n__read_addr__h77756 = propDstData_1_0_dummy2_1$Q_OUT ? - IF_propDstData_1_0_lat_0_whas__163_THEN_propDs_ETC___d1168 : + IF_propDstData_1_0_lat_0_whas__162_THEN_propDs_ETC___d1167 : 64'd0 ; - assign n__read_addr__h78043 = + assign n__read_addr__h77835 = propDstData_1_1_dummy2_1$Q_OUT ? - IF_propDstData_1_1_lat_0_whas__201_THEN_propDs_ETC___d1206 : + IF_propDstData_1_1_lat_0_whas__200_THEN_propDs_ETC___d1205 : 64'd0 ; - assign n__read_child__h59166 = + assign n__read_child__h58958 = propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[0] : propDstData_0_rl[0]) ; - assign n__read_child__h59251 = + assign n__read_child__h59043 = propDstData_1_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[0] : propDstData_1_rl[0]) ; - assign n__read_child__h77967 = + assign n__read_child__h77759 = propDstData_1_0_dummy2_1$Q_OUT && - IF_propDstData_1_0_lat_0_whas__163_THEN_propDs_ETC___d1194 ; - assign n__read_child__h78046 = + IF_propDstData_1_0_lat_0_whas__162_THEN_propDs_ETC___d1193 ; + assign n__read_child__h77838 = propDstData_1_1_dummy2_1$Q_OUT && - IF_propDstData_1_1_lat_0_whas__201_THEN_propDs_ETC___d1232 ; - assign n__read_id__h59165 = + IF_propDstData_1_1_lat_0_whas__200_THEN_propDs_ETC___d1231 ; + assign n__read_id__h58957 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[3:1] : propDstData_0_rl[3:1]) : 3'd0 ; - assign n__read_id__h59250 = + assign n__read_id__h59042 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[3:1] : propDstData_1_rl[3:1]) : 3'd0 ; - assign n__read_snd_addr__h92909 = + assign n__read_snd_addr__h121251 = llc_mem_server_propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_llc_mem_server_srcPropose ? core_0$tlbToMem_memReq_first[64:1] : llc_mem_server_propDstData_0_rl[64:1]) : 64'd0 ; - assign n__read_snd_id__h92910 = + assign n__read_snd_id__h121252 = llc_mem_server_propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_llc_mem_server_srcPropose ? core_0$tlbToMem_memReq_first[0] : llc_mem_server_propDstData_0_rl[0]) ; - assign newData__h29517 = + assign newData__h29309 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h29628 : - IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d513 ; - assign newData__h32447 = + x__h29420 : + IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d512 ; + assign newData__h32239 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h32538 : - IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d575 ; - assign new_cline__h124565 = + x__h32330 : + IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d574 ; + assign new_cline__h132656 = { llc_axi4_adapter_master_xactor_rg_rd_data[66:3], llc_axi4_adapter_rg_cline[511:64] } ; - assign op_result__h46187 = - IF_mmioPlatform_reqSz_44_EQ_0b10_51_THEN_SEXT__ETC___d852 + - IF_mmioPlatform_reqSz_44_EQ_0b10_51_THEN_SEXT__ETC___d854 ; - assign op_result__h46717 = w1__h45584 ^ w2__h45586 ; - assign op_result__h46722 = w1__h45584 & w2__h45586 ; - assign op_result__h46727 = w1__h45584 | w2__h45586 ; - assign op_result__h46732 = - (w1__h45584 < w2__h45586) ? w1__h45584 : w2__h45586 ; - assign op_result__h46738 = - (w1__h45584 <= w2__h45586) ? w2__h45586 : w1__h45584 ; - assign op_result__h46745 = - ((IF_mmioPlatform_reqSz_44_EQ_0b10_51_THEN_SEXT__ETC___d852 ^ + assign new_dword__h87351 = x__h88513 | y__h88514 ; + assign op_result__h45979 = + IF_mmioPlatform_reqSz_43_EQ_0b10_50_THEN_SEXT__ETC___d851 + + IF_mmioPlatform_reqSz_43_EQ_0b10_50_THEN_SEXT__ETC___d853 ; + assign op_result__h46509 = w1__h45376 ^ w2__h45378 ; + assign op_result__h46514 = w1__h45376 & w2__h45378 ; + assign op_result__h46519 = w1__h45376 | w2__h45378 ; + assign op_result__h46524 = + (w1__h45376 < w2__h45378) ? w1__h45376 : w2__h45378 ; + assign op_result__h46530 = + (w1__h45376 <= w2__h45378) ? w2__h45378 : w1__h45376 ; + assign op_result__h46537 = + ((IF_mmioPlatform_reqSz_43_EQ_0b10_50_THEN_SEXT__ETC___d851 ^ 64'h8000000000000000) < - (IF_mmioPlatform_reqSz_44_EQ_0b10_51_THEN_SEXT__ETC___d854 ^ + (IF_mmioPlatform_reqSz_43_EQ_0b10_50_THEN_SEXT__ETC___d853 ^ 64'h8000000000000000)) ? - w1__h45584 : - w2__h45586 ; - assign op_result__h46751 = - ((IF_mmioPlatform_reqSz_44_EQ_0b10_51_THEN_SEXT__ETC___d852 ^ + w1__h45376 : + w2__h45378 ; + assign op_result__h46543 = + ((IF_mmioPlatform_reqSz_43_EQ_0b10_50_THEN_SEXT__ETC___d851 ^ 64'h8000000000000000) <= - (IF_mmioPlatform_reqSz_44_EQ_0b10_51_THEN_SEXT__ETC___d854 ^ + (IF_mmioPlatform_reqSz_43_EQ_0b10_50_THEN_SEXT__ETC___d853 ^ 64'h8000000000000000)) ? - w2__h45586 : - w1__h45584 ; - assign propDstData_0_dummy2_1_read__065_AND_IF_propDs_ETC___d1101 = + w2__h45378 : + w1__h45376 ; + assign propDstData_0_dummy2_1_read__064_AND_IF_propDs_ETC___d1100 = propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[4] : propDstData_0_rl[4]) ; - assign propDstData_1_dummy2_1_read__070_AND_IF_propDs_ETC___d1105 = + assign propDstData_1_dummy2_1_read__069_AND_IF_propDs_ETC___d1104 = propDstData_1_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[4] : propDstData_1_rl[4]) ; - assign req_addr__h94733 = - { llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[92:35], - 6'b0 } ; - assign result__h45630 = + assign result__h45422 = { mmioPlatform_reqData[63:8], - IF_mmioPlatform_reqAmofunc_49_EQ_0_50_THEN_IF__ETC___d884[7:0] } ; - assign result__h45754 = { 56'd0, mmioPlatform_reqData[7:0] } ; - assign result__h45782 = { 56'd0, mmioPlatform_reqData[15:8] } ; - assign result__h45810 = { 56'd0, mmioPlatform_reqData[23:16] } ; - assign result__h45838 = { 56'd0, mmioPlatform_reqData[31:24] } ; - assign result__h45866 = { 56'd0, mmioPlatform_reqData[39:32] } ; - assign result__h45894 = { 56'd0, mmioPlatform_reqData[47:40] } ; - assign result__h45922 = { 56'd0, mmioPlatform_reqData[55:48] } ; - assign result__h45950 = { 56'd0, mmioPlatform_reqData[63:56] } ; - assign result__h45995 = { 48'd0, mmioPlatform_reqData[15:0] } ; - assign result__h46023 = { 48'd0, mmioPlatform_reqData[31:16] } ; - assign result__h46051 = { 48'd0, mmioPlatform_reqData[47:32] } ; - assign result__h46079 = { 48'd0, mmioPlatform_reqData[63:48] } ; - assign result__h46120 = { 32'd0, mmioPlatform_reqData[31:0] } ; - assign result__h46148 = { 32'd0, mmioPlatform_reqData[63:32] } ; - assign result__h46274 = + IF_mmioPlatform_reqAmofunc_48_EQ_0_49_THEN_IF__ETC___d883[7:0] } ; + assign result__h45546 = { 56'd0, mmioPlatform_reqData[7:0] } ; + assign result__h45574 = { 56'd0, mmioPlatform_reqData[15:8] } ; + assign result__h45602 = { 56'd0, mmioPlatform_reqData[23:16] } ; + assign result__h45630 = { 56'd0, mmioPlatform_reqData[31:24] } ; + assign result__h45658 = { 56'd0, mmioPlatform_reqData[39:32] } ; + assign result__h45686 = { 56'd0, mmioPlatform_reqData[47:40] } ; + assign result__h45714 = { 56'd0, mmioPlatform_reqData[55:48] } ; + assign result__h45742 = { 56'd0, mmioPlatform_reqData[63:56] } ; + assign result__h45787 = { 48'd0, mmioPlatform_reqData[15:0] } ; + assign result__h45815 = { 48'd0, mmioPlatform_reqData[31:16] } ; + assign result__h45843 = { 48'd0, mmioPlatform_reqData[47:32] } ; + assign result__h45871 = { 48'd0, mmioPlatform_reqData[63:48] } ; + assign result__h45912 = { 32'd0, mmioPlatform_reqData[31:0] } ; + assign result__h45940 = { 32'd0, mmioPlatform_reqData[63:32] } ; + assign result__h46066 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[7:0] } ; - assign result__h46301 = + assign result__h46093 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[15:8] } ; - assign result__h46328 = + assign result__h46120 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[23:16] } ; - assign result__h46355 = + assign result__h46147 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:24] } ; - assign result__h46382 = + assign result__h46174 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[39:32] } ; - assign result__h46409 = + assign result__h46201 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[47:40] } ; - assign result__h46436 = + assign result__h46228 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[55:48] } ; - assign result__h46463 = + assign result__h46255 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:56] } ; - assign result__h46507 = + assign result__h46299 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[15:0] } ; - assign result__h46534 = + assign result__h46326 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:16] } ; - assign result__h46561 = + assign result__h46353 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[47:32] } ; - assign result__h46588 = + assign result__h46380 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:48] } ; - assign result__h46628 = + assign result__h46420 = { 32'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:0] } ; - assign result__h46655 = + assign result__h46447 = { 32'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:32] } ; - assign result__h46772 = + assign result__h46564 = { mmioPlatform_reqData[63:16], - IF_mmioPlatform_reqAmofunc_49_EQ_0_50_THEN_IF__ETC___d884[7:0], + IF_mmioPlatform_reqAmofunc_48_EQ_0_49_THEN_IF__ETC___d883[7:0], mmioPlatform_reqData[7:0] } ; - assign result__h46838 = + assign result__h46630 = { mmioPlatform_reqData[63:24], - IF_mmioPlatform_reqAmofunc_49_EQ_0_50_THEN_IF__ETC___d884[7:0], + IF_mmioPlatform_reqAmofunc_48_EQ_0_49_THEN_IF__ETC___d883[7:0], mmioPlatform_reqData[15:0] } ; - assign result__h46904 = + assign result__h46696 = { mmioPlatform_reqData[63:32], - IF_mmioPlatform_reqAmofunc_49_EQ_0_50_THEN_IF__ETC___d884[7:0], + IF_mmioPlatform_reqAmofunc_48_EQ_0_49_THEN_IF__ETC___d883[7:0], mmioPlatform_reqData[23:0] } ; - assign result__h46970 = + assign result__h46762 = { mmioPlatform_reqData[63:40], - IF_mmioPlatform_reqAmofunc_49_EQ_0_50_THEN_IF__ETC___d884[7:0], + IF_mmioPlatform_reqAmofunc_48_EQ_0_49_THEN_IF__ETC___d883[7:0], mmioPlatform_reqData[31:0] } ; - assign result__h47036 = + assign result__h46828 = { mmioPlatform_reqData[63:48], - IF_mmioPlatform_reqAmofunc_49_EQ_0_50_THEN_IF__ETC___d884[7:0], + IF_mmioPlatform_reqAmofunc_48_EQ_0_49_THEN_IF__ETC___d883[7:0], mmioPlatform_reqData[39:0] } ; - assign result__h47102 = + assign result__h46894 = { mmioPlatform_reqData[63:56], - IF_mmioPlatform_reqAmofunc_49_EQ_0_50_THEN_IF__ETC___d884[7:0], + IF_mmioPlatform_reqAmofunc_48_EQ_0_49_THEN_IF__ETC___d883[7:0], mmioPlatform_reqData[47:0] } ; - assign result__h47168 = - { IF_mmioPlatform_reqAmofunc_49_EQ_0_50_THEN_IF__ETC___d884[7:0], + assign result__h46960 = + { IF_mmioPlatform_reqAmofunc_48_EQ_0_49_THEN_IF__ETC___d883[7:0], mmioPlatform_reqData[55:0] } ; - assign result__h47230 = + assign result__h47022 = { mmioPlatform_reqData[63:16], - IF_mmioPlatform_reqAmofunc_49_EQ_0_50_THEN_IF__ETC___d884[15:0] } ; - assign result__h47275 = + IF_mmioPlatform_reqAmofunc_48_EQ_0_49_THEN_IF__ETC___d883[15:0] } ; + assign result__h47067 = { mmioPlatform_reqData[63:32], - IF_mmioPlatform_reqAmofunc_49_EQ_0_50_THEN_IF__ETC___d884[15:0], + IF_mmioPlatform_reqAmofunc_48_EQ_0_49_THEN_IF__ETC___d883[15:0], mmioPlatform_reqData[15:0] } ; - assign result__h47341 = + assign result__h47133 = { mmioPlatform_reqData[63:48], - IF_mmioPlatform_reqAmofunc_49_EQ_0_50_THEN_IF__ETC___d884[15:0], + IF_mmioPlatform_reqAmofunc_48_EQ_0_49_THEN_IF__ETC___d883[15:0], mmioPlatform_reqData[31:0] } ; - assign result__h47407 = - { IF_mmioPlatform_reqAmofunc_49_EQ_0_50_THEN_IF__ETC___d884[15:0], + assign result__h47199 = + { IF_mmioPlatform_reqAmofunc_48_EQ_0_49_THEN_IF__ETC___d883[15:0], mmioPlatform_reqData[47:0] } ; - assign result__h47465 = + assign result__h47257 = { mmioPlatform_reqData[63:32], - IF_mmioPlatform_reqAmofunc_49_EQ_0_50_THEN_IF__ETC___d884[31:0] } ; - assign result__h47510 = - { IF_mmioPlatform_reqAmofunc_49_EQ_0_50_THEN_IF__ETC___d884[31:0], + IF_mmioPlatform_reqAmofunc_48_EQ_0_49_THEN_IF__ETC___d883[31:0] } ; + assign result__h47302 = + { IF_mmioPlatform_reqAmofunc_48_EQ_0_49_THEN_IF__ETC___d883[31:0], mmioPlatform_reqData[31:0] } ; - assign v__h29229 = mmioPlatform_waitUpperMSIPCRs ? v__h29266 : 32'd0 ; - assign v__h29266 = { 31'd0, core_0$mmioToPlatform_cRs_first } ; - assign w15579_BITS_31_TO_0__q15 = w1__h45579[31:0] ; - assign w1___1__h45689 = { 32'd0, w1__h45579[31:0] } ; - assign w25580_BITS_31_TO_0__q16 = w2__h45580[31:0] ; - assign w2___1__h45690 = { 32'd0, w2__h45580[31:0] } ; - assign x1_avValue_data__h37903 = + assign v__h29021 = mmioPlatform_waitUpperMSIPCRs ? v__h29058 : 32'd0 ; + assign v__h29058 = { 31'd0, core_0$mmioToPlatform_cRs_first } ; + assign w15371_BITS_31_TO_0__q7 = w1__h45371[31:0] ; + assign w1___1__h45481 = { 32'd0, w1__h45371[31:0] } ; + assign w25372_BITS_31_TO_0__q8 = w2__h45372[31:0] ; + assign w2___1__h45482 = { 32'd0, w2__h45372[31:0] } ; + assign x1_avValue_data__h37695 = mmioPlatform_toHostQ_empty ? 64'd0 : mmioPlatform_toHostQ_data_0 ; - assign x1_avValue_data__h42508 = + assign x1_avValue_data__h42300 = mmioPlatform_fromHostQ_empty ? 64'd0 : mmioPlatform_fromHostQ_data_0 ; - assign x__h123898 = { llc_axi4_adapter_rg_rd_req_beat, 3'b0 } ; - assign x__h137812 = { llc_axi4_adapter_rg_wr_req_beat, 3'b0 } ; - assign x__h34898 = mmioPlatform_mtimecmp_0 ; - assign x__h38421 = + assign x__h131989 = { llc_axi4_adapter_rg_rd_req_beat, 3'b0 } ; + assign x__h145903 = { llc_axi4_adapter_rg_wr_req_beat, 3'b0 } ; + assign x__h34690 = mmioPlatform_mtimecmp_0 ; + assign x__h38213 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h38432 : - IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d679 ; - assign x__h40487 = + x__h38224 : + IF_mmioPlatform_reqBE_03_BIT_7_79_THEN_mmioPla_ETC___d678 ; + assign x__h40279 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h40498 : + x__h40290 : { mmioPlatform_reqBE[7] ? mmioPlatform_reqData[63:56] : 8'd0, mmioPlatform_reqBE[6] ? mmioPlatform_reqData[55:48] : 8'd0, mmioPlatform_reqBE[5] ? mmioPlatform_reqData[47:40] : 8'd0, @@ -6653,644 +6529,512 @@ module mkProc(CLK, mmioPlatform_reqBE[2] ? mmioPlatform_reqData[23:16] : 8'd0, mmioPlatform_reqBE[1] ? mmioPlatform_reqData[15:8] : 8'd0, mmioPlatform_reqBE[0] ? mmioPlatform_reqData[7:0] : 8'd0 } ; - assign x__h47687 = { mmioPlatform_curReq[63:3], 3'b0 } ; - assign x__h58979 = - SEL_ARR_propDstIdx_0_dummy2_1_read__027_AND_IF_ETC___d1058 ? + assign x__h47479 = { mmioPlatform_curReq[63:3], 3'b0 } ; + assign x__h58771 = + SEL_ARR_propDstIdx_0_dummy2_1_read__026_AND_IF_ETC___d1057 ? srcRR_0 : - NOT_propDstIdx_0_dummy2_1_read__027_028_OR_IF__ETC___d1061 ; - assign x__h72715 = + NOT_propDstIdx_0_dummy2_1_read__026_027_OR_IF__ETC___d1060 ; + assign x__h72507 = !CAN_FIRE_RL_doEnq_1 && - IF_enqDst_1_0_lat_0_whas__239_THEN_enqDst_1_0__ETC___d1280 ; - assign x__h77786 = - SEL_ARR_propDstIdx_1_0_dummy2_1_read__291_AND__ETC___d1332 ? + IF_enqDst_1_0_lat_0_whas__238_THEN_enqDst_1_0__ETC___d1279 ; + assign x__h77578 = + SEL_ARR_propDstIdx_1_0_dummy2_1_read__290_AND__ETC___d1331 ? srcRR_1_0 : - NOT_propDstIdx_1_0_dummy2_1_read__291_292_OR_I_ETC___d1335 ; - assign x_data__h28019 = { 31'd0, mmioPlatform_reqData[0] } ; - always@(core_0$v_to_TV_1_get) + NOT_propDstIdx_1_0_dummy2_1_read__290_291_OR_I_ETC___d1334 ; + assign x__h88513 = old_dword__h87350 & y__h88515 ; + assign x_data__h27811 = { 31'd0, mmioPlatform_reqData[0] } ; + assign y__h88514 = + llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[72:9] & + mask__h87347 ; + assign y__h88515 = + { llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8] ? + 8'd0 : + 8'd255, + llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[7] ? + 8'd0 : + 8'd255, + llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[6] ? + 8'd0 : + 8'd255, + llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[5] ? + 8'd0 : + 8'd255, + llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[4] ? + 8'd0 : + 8'd255, + llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[3] ? + 8'd0 : + 8'd255, + llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[2] ? + 8'd0 : + 8'd255, + llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[1] ? + 8'd0 : + 8'd255 } ; + always@(llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT or + llc_mem_server_rg_cacheline_cache_data) begin - case (core_0$v_to_TV_1_get[153:142]) - 12'd1, - 12'd2, - 12'd3, - 12'd256, - 12'd260, - 12'd261, - 12'd262, - 12'd320, - 12'd321, - 12'd322, - 12'd323, - 12'd324, - 12'd384, - 12'd768, - 12'd769, - 12'd770, - 12'd771, - 12'd772, - 12'd773, - 12'd774, - 12'd832, - 12'd833, - 12'd834, - 12'd835, - 12'd836, - 12'd1968, - 12'd1969, - 12'd1970, - 12'd1971, - 12'd2048, - 12'd2049, - 12'd2816, - 12'd2818, - 12'd3072, - 12'd3073, - 12'd3074, - 12'd3857, - 12'd3858, - 12'd3859, - 12'd3860: - CASE_core_0v_to_TV_1_get_BITS_153_TO_142_1_co_ETC__q1 = - core_0$v_to_TV_1_get[153:142]; - default: CASE_core_0v_to_TV_1_get_BITS_153_TO_142_1_co_ETC__q1 = - 12'd2303; - endcase - end - always@(core_0$v_to_TV_1_get) - begin - case (core_0$v_to_TV_1_get[139:136]) - 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: - CASE_core_0v_to_TV_1_get_BITS_139_TO_136_0_co_ETC__q2 = - core_0$v_to_TV_1_get[139:136]; - default: CASE_core_0v_to_TV_1_get_BITS_139_TO_136_0_co_ETC__q2 = 4'd15; - endcase - end - always@(core_0$v_to_TV_1_get) - begin - case (core_0$v_to_TV_1_get[139:136]) - 4'd0, - 4'd1, - 4'd2, - 4'd3, - 4'd4, - 4'd5, - 4'd6, - 4'd7, - 4'd8, - 4'd9, - 4'd11, - 4'd12, - 4'd13: - CASE_core_0v_to_TV_1_get_BITS_139_TO_136_0_co_ETC__q3 = - core_0$v_to_TV_1_get[139:136]; - default: CASE_core_0v_to_TV_1_get_BITS_139_TO_136_0_co_ETC__q3 = 4'd15; - endcase - end - always@(core_0$v_to_TV_1_get) - begin - case (core_0$v_to_TV_1_get[71:70]) - 2'd0, 2'd1: - CASE_core_0v_to_TV_1_get_BITS_71_TO_70_0_core_ETC__q4 = - core_0$v_to_TV_1_get[71:70]; - default: CASE_core_0v_to_TV_1_get_BITS_71_TO_70_0_core_ETC__q4 = 2'd2; - endcase - end - always@(core_0$v_to_TV_0_get) - begin - case (core_0$v_to_TV_0_get[153:142]) - 12'd1, - 12'd2, - 12'd3, - 12'd256, - 12'd260, - 12'd261, - 12'd262, - 12'd320, - 12'd321, - 12'd322, - 12'd323, - 12'd324, - 12'd384, - 12'd768, - 12'd769, - 12'd770, - 12'd771, - 12'd772, - 12'd773, - 12'd774, - 12'd832, - 12'd833, - 12'd834, - 12'd835, - 12'd836, - 12'd1968, - 12'd1969, - 12'd1970, - 12'd1971, - 12'd2048, - 12'd2049, - 12'd2816, - 12'd2818, - 12'd3072, - 12'd3073, - 12'd3074, - 12'd3857, - 12'd3858, - 12'd3859, - 12'd3860: - CASE_core_0v_to_TV_0_get_BITS_153_TO_142_1_co_ETC__q5 = - core_0$v_to_TV_0_get[153:142]; - default: CASE_core_0v_to_TV_0_get_BITS_153_TO_142_1_co_ETC__q5 = - 12'd2303; - endcase - end - always@(core_0$v_to_TV_0_get) - begin - case (core_0$v_to_TV_0_get[139:136]) - 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: - CASE_core_0v_to_TV_0_get_BITS_139_TO_136_0_co_ETC__q6 = - core_0$v_to_TV_0_get[139:136]; - default: CASE_core_0v_to_TV_0_get_BITS_139_TO_136_0_co_ETC__q6 = 4'd15; - endcase - end - always@(core_0$v_to_TV_0_get) - begin - case (core_0$v_to_TV_0_get[139:136]) - 4'd0, - 4'd1, - 4'd2, - 4'd3, - 4'd4, - 4'd5, - 4'd6, - 4'd7, - 4'd8, - 4'd9, - 4'd11, - 4'd12, - 4'd13: - CASE_core_0v_to_TV_0_get_BITS_139_TO_136_0_co_ETC__q7 = - core_0$v_to_TV_0_get[139:136]; - default: CASE_core_0v_to_TV_0_get_BITS_139_TO_136_0_co_ETC__q7 = 4'd15; - endcase - end - always@(core_0$v_to_TV_0_get) - begin - case (core_0$v_to_TV_0_get[71:70]) - 2'd0, 2'd1: - CASE_core_0v_to_TV_0_get_BITS_71_TO_70_0_core_ETC__q8 = - core_0$v_to_TV_0_get[71:70]; - default: CASE_core_0v_to_TV_0_get_BITS_71_TO_70_0_core_ETC__q8 = 2'd2; - endcase - end - always@(llc_mem_server_f_dword_in_line$D_OUT or llc$dma_respLd_first) - begin - case (llc_mem_server_f_dword_in_line$D_OUT) - 3'd0: rd_data_rdata__h120163 = llc$dma_respLd_first[68:5]; - 3'd1: rd_data_rdata__h120163 = llc$dma_respLd_first[132:69]; - 3'd2: rd_data_rdata__h120163 = llc$dma_respLd_first[196:133]; - 3'd3: rd_data_rdata__h120163 = llc$dma_respLd_first[260:197]; - 3'd4: rd_data_rdata__h120163 = llc$dma_respLd_first[324:261]; - 3'd5: rd_data_rdata__h120163 = llc$dma_respLd_first[388:325]; - 3'd6: rd_data_rdata__h120163 = llc$dma_respLd_first[452:389]; - 3'd7: rd_data_rdata__h120163 = llc$dma_respLd_first[516:453]; + case (llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[34:32]) + 3'd0: dword__h91660 = llc_mem_server_rg_cacheline_cache_data[63:0]; + 3'd1: dword__h91660 = llc_mem_server_rg_cacheline_cache_data[127:64]; + 3'd2: dword__h91660 = llc_mem_server_rg_cacheline_cache_data[191:128]; + 3'd3: dword__h91660 = llc_mem_server_rg_cacheline_cache_data[255:192]; + 3'd4: dword__h91660 = llc_mem_server_rg_cacheline_cache_data[319:256]; + 3'd5: dword__h91660 = llc_mem_server_rg_cacheline_cache_data[383:320]; + 3'd6: dword__h91660 = llc_mem_server_rg_cacheline_cache_data[447:384]; + 3'd7: dword__h91660 = llc_mem_server_rg_cacheline_cache_data[511:448]; endcase end always@(llc$dma_respLd_first) begin case (llc$dma_respLd_first[2:0]) - 3'd0: ld_data__h121714 = llc$dma_respLd_first[68:5]; - 3'd1: ld_data__h121714 = llc$dma_respLd_first[132:69]; - 3'd2: ld_data__h121714 = llc$dma_respLd_first[196:133]; - 3'd3: ld_data__h121714 = llc$dma_respLd_first[260:197]; - 3'd4: ld_data__h121714 = llc$dma_respLd_first[324:261]; - 3'd5: ld_data__h121714 = llc$dma_respLd_first[388:325]; - 3'd6: ld_data__h121714 = llc$dma_respLd_first[452:389]; - 3'd7: ld_data__h121714 = llc$dma_respLd_first[516:453]; + 3'd0: ld_data__h129909 = llc$dma_respLd_first[68:5]; + 3'd1: ld_data__h129909 = llc$dma_respLd_first[132:69]; + 3'd2: ld_data__h129909 = llc$dma_respLd_first[196:133]; + 3'd3: ld_data__h129909 = llc$dma_respLd_first[260:197]; + 3'd4: ld_data__h129909 = llc$dma_respLd_first[324:261]; + 3'd5: ld_data__h129909 = llc$dma_respLd_first[388:325]; + 3'd6: ld_data__h129909 = llc$dma_respLd_first[452:389]; + 3'd7: ld_data__h129909 = llc$dma_respLd_first[516:453]; endcase end always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) begin case (llc_axi4_adapter_rg_wr_req_beat) - 3'd0: data64__h137702 = llc$to_mem_toM_first[63:0]; - 3'd1: data64__h137702 = llc$to_mem_toM_first[127:64]; - 3'd2: data64__h137702 = llc$to_mem_toM_first[191:128]; - 3'd3: data64__h137702 = llc$to_mem_toM_first[255:192]; - 3'd4: data64__h137702 = llc$to_mem_toM_first[319:256]; - 3'd5: data64__h137702 = llc$to_mem_toM_first[383:320]; - 3'd6: data64__h137702 = llc$to_mem_toM_first[447:384]; - 3'd7: data64__h137702 = llc$to_mem_toM_first[511:448]; + 3'd0: data64__h145793 = llc$to_mem_toM_first[63:0]; + 3'd1: data64__h145793 = llc$to_mem_toM_first[127:64]; + 3'd2: data64__h145793 = llc$to_mem_toM_first[191:128]; + 3'd3: data64__h145793 = llc$to_mem_toM_first[255:192]; + 3'd4: data64__h145793 = llc$to_mem_toM_first[319:256]; + 3'd5: data64__h145793 = llc$to_mem_toM_first[383:320]; + 3'd6: data64__h145793 = llc$to_mem_toM_first[447:384]; + 3'd7: data64__h145793 = llc$to_mem_toM_first[511:448]; endcase end always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) begin case (llc_axi4_adapter_rg_wr_req_beat) - 3'd0: strb8__h137703 = llc$to_mem_toM_first[519:512]; - 3'd1: strb8__h137703 = llc$to_mem_toM_first[527:520]; - 3'd2: strb8__h137703 = llc$to_mem_toM_first[535:528]; - 3'd3: strb8__h137703 = llc$to_mem_toM_first[543:536]; - 3'd4: strb8__h137703 = llc$to_mem_toM_first[551:544]; - 3'd5: strb8__h137703 = llc$to_mem_toM_first[559:552]; - 3'd6: strb8__h137703 = llc$to_mem_toM_first[567:560]; - 3'd7: strb8__h137703 = llc$to_mem_toM_first[575:568]; + 3'd0: strb8__h145794 = llc$to_mem_toM_first[519:512]; + 3'd1: strb8__h145794 = llc$to_mem_toM_first[527:520]; + 3'd2: strb8__h145794 = llc$to_mem_toM_first[535:528]; + 3'd3: strb8__h145794 = llc$to_mem_toM_first[543:536]; + 3'd4: strb8__h145794 = llc$to_mem_toM_first[551:544]; + 3'd5: strb8__h145794 = llc$to_mem_toM_first[559:552]; + 3'd6: strb8__h145794 = llc$to_mem_toM_first[567:560]; + 3'd7: strb8__h145794 = llc$to_mem_toM_first[575:568]; + endcase + end + always@(llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT or + llc_mem_server_rg_cacheline_cache_data) + begin + case (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32]) + 3'd0: old_dword__h87350 = llc_mem_server_rg_cacheline_cache_data[63:0]; + 3'd1: + old_dword__h87350 = llc_mem_server_rg_cacheline_cache_data[127:64]; + 3'd2: + old_dword__h87350 = llc_mem_server_rg_cacheline_cache_data[191:128]; + 3'd3: + old_dword__h87350 = llc_mem_server_rg_cacheline_cache_data[255:192]; + 3'd4: + old_dword__h87350 = llc_mem_server_rg_cacheline_cache_data[319:256]; + 3'd5: + old_dword__h87350 = llc_mem_server_rg_cacheline_cache_data[383:320]; + 3'd6: + old_dword__h87350 = llc_mem_server_rg_cacheline_cache_data[447:384]; + 3'd7: + old_dword__h87350 = llc_mem_server_rg_cacheline_cache_data[511:448]; endcase end always@(mmioPlatform_curReq or - result__h45995 or - result__h46023 or result__h46051 or result__h46079) + result__h45546 or + result__h45574 or + result__h45602 or + result__h45630 or + result__h45658 or + result__h45686 or result__h45714 or result__h45742) begin case (mmioPlatform_curReq[2:0]) 3'h0: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d787 = - result__h45995; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d773 = + result__h45546; + 3'h1: + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d773 = + result__h45574; 3'h2: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d787 = - result__h46023; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d773 = + result__h45602; + 3'h3: + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d773 = + result__h45630; 3'h4: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d787 = - result__h46051; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d773 = + result__h45658; + 3'h5: + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d773 = + result__h45686; 3'h6: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d787 = - result__h46079; - default: IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d787 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d773 = + result__h45714; + 3'h7: + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d773 = + result__h45742; + endcase + end + always@(mmioPlatform_curReq or + result__h45787 or + result__h45815 or result__h45843 or result__h45871) + begin + case (mmioPlatform_curReq[2:0]) + 3'h0: + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d786 = + result__h45787; + 3'h2: + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d786 = + result__h45815; + 3'h4: + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d786 = + result__h45843; + 3'h6: + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d786 = + result__h45871; + default: IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d786 = 64'd0; endcase end - always@(mmioPlatform_curReq or - result__h45754 or - result__h45782 or - result__h45810 or - result__h45838 or - result__h45866 or - result__h45894 or result__h45922 or result__h45950) + always@(mmioPlatform_curReq or result__h45912 or result__h45940) begin case (mmioPlatform_curReq[2:0]) 3'h0: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d774 = - result__h45754; - 3'h1: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d774 = - result__h45782; - 3'h2: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d774 = - result__h45810; - 3'h3: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d774 = - result__h45838; + CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5 = + result__h45912; 3'h4: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d774 = - result__h45866; - 3'h5: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d774 = - result__h45894; - 3'h6: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d774 = - result__h45922; - 3'h7: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d774 = - result__h45950; + CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5 = + result__h45940; + default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5 = 64'd0; endcase end - always@(mmioPlatform_curReq or result__h46120 or result__h46148) + always@(mmioPlatform_reqSz or + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d773 or + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d786 or + CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5 or + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d793) + begin + case (mmioPlatform_reqSz) + 2'b0: + w2__h45372 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d773; + 2'b01: + w2__h45372 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d786; + 2'b10: + w2__h45372 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5; + 2'b11: + w2__h45372 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d793; + endcase + end + always@(mmioPlatform_reqSz or + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d773 or + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d786 or + w2___1__h45482 or + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d793) + begin + case (mmioPlatform_reqSz) + 2'b0: + w2__h45378 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d773; + 2'b01: + w2__h45378 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d786; + 2'b10: w2__h45378 = w2___1__h45482; + 2'b11: + w2__h45378 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d793; + endcase + end + always@(mmioPlatform_curReq or + result__h46066 or + result__h46093 or + result__h46120 or + result__h46147 or + result__h46174 or + result__h46201 or result__h46228 or result__h46255) begin case (mmioPlatform_curReq[2:0]) 3'h0: - CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d825 = + result__h46066; + 3'h1: + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d825 = + result__h46093; + 3'h2: + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d825 = result__h46120; - 3'h4: - CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13 = - result__h46148; - default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13 = - 64'd0; - endcase - end - always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d774 or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d787 or - CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13 or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d794) - begin - case (mmioPlatform_reqSz) - 2'b0: - w2__h45580 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d774; - 2'b01: - w2__h45580 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d787; - 2'b10: - w2__h45580 = - CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13; - 2'b11: - w2__h45580 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d794; - endcase - end - always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d774 or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d787 or - w2___1__h45690 or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d794) - begin - case (mmioPlatform_reqSz) - 2'b0: - w2__h45586 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d774; - 2'b01: - w2__h45586 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d787; - 2'b10: w2__h45586 = w2___1__h45690; - 2'b11: - w2__h45586 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d794; - endcase - end - always@(mmioPlatform_curReq or - result__h46507 or - result__h46534 or result__h46561 or result__h46588) - begin - case (mmioPlatform_curReq[2:0]) - 3'h0: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d838 = - result__h46507; - 3'h2: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d838 = - result__h46534; - 3'h4: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d838 = - result__h46561; - 3'h6: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d838 = - result__h46588; - default: IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d838 = - 64'd0; - endcase - end - always@(mmioPlatform_curReq or - result__h46274 or - result__h46301 or - result__h46328 or - result__h46355 or - result__h46382 or - result__h46409 or result__h46436 or result__h46463) - begin - case (mmioPlatform_curReq[2:0]) - 3'h0: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d826 = - result__h46274; - 3'h1: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d826 = - result__h46301; - 3'h2: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d826 = - result__h46328; 3'h3: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d826 = - result__h46355; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d825 = + result__h46147; 3'h4: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d826 = - result__h46382; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d825 = + result__h46174; 3'h5: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d826 = - result__h46409; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d825 = + result__h46201; 3'h6: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d826 = - result__h46436; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d825 = + result__h46228; 3'h7: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d826 = - result__h46463; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d825 = + result__h46255; endcase end - always@(mmioPlatform_curReq or result__h46628 or result__h46655) + always@(mmioPlatform_curReq or + result__h46299 or + result__h46326 or result__h46353 or result__h46380) begin case (mmioPlatform_curReq[2:0]) 3'h0: - CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14 = - result__h46628; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d837 = + result__h46299; + 3'h2: + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d837 = + result__h46326; 3'h4: - CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14 = - result__h46655; - default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d837 = + result__h46353; + 3'h6: + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d837 = + result__h46380; + default: IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d837 = 64'd0; endcase end - always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d826 or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d838 or - CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14 or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d845) + always@(mmioPlatform_curReq or result__h46420 or result__h46447) begin - case (mmioPlatform_reqSz) - 2'b0: - w1__h45579 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d826; - 2'b01: - w1__h45579 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d838; - 2'b10: - w1__h45579 = - CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14; - 2'b11: - w1__h45579 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d845; + case (mmioPlatform_curReq[2:0]) + 3'h0: + CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6 = + result__h46420; + 3'h4: + CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6 = + result__h46447; + default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6 = 64'd0; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d826 or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d838 or - w1___1__h45689 or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d845) + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d825 or + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d837 or + CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6 or + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d844) begin case (mmioPlatform_reqSz) 2'b0: - w1__h45584 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d826; + w1__h45371 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d825; 2'b01: - w1__h45584 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d838; - 2'b10: w1__h45584 = w1___1__h45689; + w1__h45371 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d837; + 2'b10: + w1__h45371 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6; 2'b11: - w1__h45584 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d845; + w1__h45371 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d844; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d826 or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d838 or - w15579_BITS_31_TO_0__q15 or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d845) + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d825 or + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d837 or + w1___1__h45481 or + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d844) begin case (mmioPlatform_reqSz) 2'b0: - IF_mmioPlatform_reqSz_44_EQ_0b10_51_THEN_SEXT__ETC___d852 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d826; + w1__h45376 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d825; 2'b01: - IF_mmioPlatform_reqSz_44_EQ_0b10_51_THEN_SEXT__ETC___d852 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d838; - 2'b10: - IF_mmioPlatform_reqSz_44_EQ_0b10_51_THEN_SEXT__ETC___d852 = - { {32{w15579_BITS_31_TO_0__q15[31]}}, - w15579_BITS_31_TO_0__q15 }; + w1__h45376 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d837; + 2'b10: w1__h45376 = w1___1__h45481; 2'b11: - IF_mmioPlatform_reqSz_44_EQ_0b10_51_THEN_SEXT__ETC___d852 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d845; + w1__h45376 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d844; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d774 or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d787 or - w25580_BITS_31_TO_0__q16 or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d794) + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d825 or + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d837 or + w15371_BITS_31_TO_0__q7 or + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d844) begin case (mmioPlatform_reqSz) 2'b0: - IF_mmioPlatform_reqSz_44_EQ_0b10_51_THEN_SEXT__ETC___d854 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d774; + IF_mmioPlatform_reqSz_43_EQ_0b10_50_THEN_SEXT__ETC___d851 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d825; 2'b01: - IF_mmioPlatform_reqSz_44_EQ_0b10_51_THEN_SEXT__ETC___d854 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d787; + IF_mmioPlatform_reqSz_43_EQ_0b10_50_THEN_SEXT__ETC___d851 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d837; 2'b10: - IF_mmioPlatform_reqSz_44_EQ_0b10_51_THEN_SEXT__ETC___d854 = - { {32{w25580_BITS_31_TO_0__q16[31]}}, - w25580_BITS_31_TO_0__q16 }; + IF_mmioPlatform_reqSz_43_EQ_0b10_50_THEN_SEXT__ETC___d851 = + { {32{w15371_BITS_31_TO_0__q7[31]}}, w15371_BITS_31_TO_0__q7 }; 2'b11: - IF_mmioPlatform_reqSz_44_EQ_0b10_51_THEN_SEXT__ETC___d854 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d794; + IF_mmioPlatform_reqSz_43_EQ_0b10_50_THEN_SEXT__ETC___d851 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d844; + endcase + end + always@(mmioPlatform_reqSz or + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d773 or + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d786 or + w25372_BITS_31_TO_0__q8 or + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d793) + begin + case (mmioPlatform_reqSz) + 2'b0: + IF_mmioPlatform_reqSz_43_EQ_0b10_50_THEN_SEXT__ETC___d853 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d773; + 2'b01: + IF_mmioPlatform_reqSz_43_EQ_0b10_50_THEN_SEXT__ETC___d853 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d786; + 2'b10: + IF_mmioPlatform_reqSz_43_EQ_0b10_50_THEN_SEXT__ETC___d853 = + { {32{w25372_BITS_31_TO_0__q8[31]}}, w25372_BITS_31_TO_0__q8 }; + 2'b11: + IF_mmioPlatform_reqSz_43_EQ_0b10_50_THEN_SEXT__ETC___d853 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d793; endcase end always@(mmioPlatform_reqAmofunc or - op_result__h46751 or - w2__h45586 or - op_result__h46187 or - op_result__h46717 or - op_result__h46722 or - op_result__h46727 or - op_result__h46745 or op_result__h46732 or op_result__h46738) + op_result__h46543 or + w2__h45378 or + op_result__h45979 or + op_result__h46509 or + op_result__h46514 or + op_result__h46519 or + op_result__h46537 or op_result__h46524 or op_result__h46530) begin case (mmioPlatform_reqAmofunc) 4'd0: - IF_mmioPlatform_reqAmofunc_49_EQ_0_50_THEN_IF__ETC___d884 = - w2__h45586; + IF_mmioPlatform_reqAmofunc_48_EQ_0_49_THEN_IF__ETC___d883 = + w2__h45378; 4'd1: - IF_mmioPlatform_reqAmofunc_49_EQ_0_50_THEN_IF__ETC___d884 = - op_result__h46187; + IF_mmioPlatform_reqAmofunc_48_EQ_0_49_THEN_IF__ETC___d883 = + op_result__h45979; 4'd2: - IF_mmioPlatform_reqAmofunc_49_EQ_0_50_THEN_IF__ETC___d884 = - op_result__h46717; + IF_mmioPlatform_reqAmofunc_48_EQ_0_49_THEN_IF__ETC___d883 = + op_result__h46509; 4'd3: - IF_mmioPlatform_reqAmofunc_49_EQ_0_50_THEN_IF__ETC___d884 = - op_result__h46722; + IF_mmioPlatform_reqAmofunc_48_EQ_0_49_THEN_IF__ETC___d883 = + op_result__h46514; 4'd4: - IF_mmioPlatform_reqAmofunc_49_EQ_0_50_THEN_IF__ETC___d884 = - op_result__h46727; + IF_mmioPlatform_reqAmofunc_48_EQ_0_49_THEN_IF__ETC___d883 = + op_result__h46519; 4'd5: - IF_mmioPlatform_reqAmofunc_49_EQ_0_50_THEN_IF__ETC___d884 = - op_result__h46745; + IF_mmioPlatform_reqAmofunc_48_EQ_0_49_THEN_IF__ETC___d883 = + op_result__h46537; 4'd7: - IF_mmioPlatform_reqAmofunc_49_EQ_0_50_THEN_IF__ETC___d884 = - op_result__h46732; + IF_mmioPlatform_reqAmofunc_48_EQ_0_49_THEN_IF__ETC___d883 = + op_result__h46524; 4'd8: - IF_mmioPlatform_reqAmofunc_49_EQ_0_50_THEN_IF__ETC___d884 = - op_result__h46738; - default: IF_mmioPlatform_reqAmofunc_49_EQ_0_50_THEN_IF__ETC___d884 = - op_result__h46751; + IF_mmioPlatform_reqAmofunc_48_EQ_0_49_THEN_IF__ETC___d883 = + op_result__h46530; + default: IF_mmioPlatform_reqAmofunc_48_EQ_0_49_THEN_IF__ETC___d883 = + op_result__h46543; endcase end always@(mmioPlatform_curReq or - result__h47230 or - result__h47275 or result__h47341 or result__h47407) + result__h47022 or + result__h47067 or result__h47133 or result__h47199) begin case (mmioPlatform_curReq[2:0]) 3'h0: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d917 = - result__h47230; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d916 = + result__h47022; 3'h2: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d917 = - result__h47275; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d916 = + result__h47067; 3'h4: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d917 = - result__h47341; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d916 = + result__h47133; 3'h6: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d917 = - result__h47407; - default: IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d917 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d916 = + result__h47199; + default: IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d916 = 64'd0; endcase end always@(mmioPlatform_curReq or - result__h45630 or - result__h46772 or - result__h46838 or - result__h46904 or - result__h46970 or - result__h47036 or result__h47102 or result__h47168) + result__h45422 or + result__h46564 or + result__h46630 or + result__h46696 or + result__h46762 or + result__h46828 or result__h46894 or result__h46960) begin case (mmioPlatform_curReq[2:0]) 3'h0: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d908 = - result__h45630; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d907 = + result__h45422; 3'h1: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d908 = - result__h46772; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d907 = + result__h46564; 3'h2: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d908 = - result__h46838; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d907 = + result__h46630; 3'h3: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d908 = - result__h46904; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d907 = + result__h46696; 3'h4: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d908 = - result__h46970; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d907 = + result__h46762; 3'h5: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d908 = - result__h47036; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d907 = + result__h46828; 3'h6: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d908 = - result__h47102; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d907 = + result__h46894; 3'h7: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d908 = - result__h47168; + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d907 = + result__h46960; endcase end - always@(mmioPlatform_curReq or result__h47465 or result__h47510) + always@(mmioPlatform_curReq or result__h47257 or result__h47302) begin case (mmioPlatform_curReq[2:0]) 3'h0: - CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17 = - result__h47465; + CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9 = + result__h47257; 3'h4: - CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17 = - result__h47510; - default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17 = - 64'd0; + CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9 = + result__h47302; + default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9 = 64'd0; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d908 or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d917 or - CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17 or - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d794) + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d907 or + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d916 or + CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9 or + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d793) begin case (mmioPlatform_reqSz) 2'b0: - x__h45575 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d908; + x__h45367 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d907; 2'b01: - x__h45575 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d917; + x__h45367 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d916; 2'b10: - x__h45575 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17; + x__h45367 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9; 2'b11: - x__h45575 = - IF_mmioPlatform_curReq_96_BITS_2_TO_0_46_EQ_0x_ETC___d794; + x__h45367 = + IF_mmioPlatform_curReq_95_BITS_2_TO_0_45_EQ_0x_ETC___d793; endcase end always@(mmioPlatform_reqFunc) begin case (mmioPlatform_reqFunc[5:4]) 2'd0, 2'd1, 2'd2: - IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_ETC___d442 = + IF_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_ETC___d441 = mmioPlatform_reqFunc; 2'd3: - IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_ETC___d442 = + IF_mmioPlatform_reqFunc_00_BITS_5_TO_4_01_EQ_0_ETC___d441 = { 2'd3, mmioPlatform_reqFunc[3:0] }; endcase end @@ -7298,343 +7042,343 @@ module mkProc(CLK, begin case (mmioPlatform_instSel) 1'd0: - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d952 = + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d951 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:0]; 1'd1: - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d952 = + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d951 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:32]; endcase end always@(mmioPlatform_reqFunc or - IF_IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4__ETC___d520 or + IF_IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4__ETC___d519 or core_0$RDY_mmioToPlatform_pRs_enq) begin case (mmioPlatform_reqFunc[5:4]) 2'd0, 2'd1: - CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q18 = + CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q10 = core_0$RDY_mmioToPlatform_pRs_enq; - default: CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q18 = - IF_IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4__ETC___d520; + default: CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q10 = + IF_IF_NOT_mmioPlatform_reqFunc_00_BITS_5_TO_4__ETC___d519; endcase end always@(mmioPlatform_reqFunc or - IF_mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioP_ETC___d586 or + IF_mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioP_ETC___d585 or core_0$RDY_mmioToPlatform_pRs_enq) begin case (mmioPlatform_reqFunc[5:4]) 2'd0, 2'd1: - CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q19 = + CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q11 = core_0$RDY_mmioToPlatform_pRs_enq; - default: CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q19 = - IF_mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioP_ETC___d586; + default: CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q11 = + IF_mmioPlatform_mtimecmp_0_20_ULE_IF_NOT_mmioP_ETC___d585; endcase end always@(srcRR_0 or propDstIdx_0_dummy2_1$Q_OUT or - IF_propDstIdx_0_lat_0_whas__74_THEN_propDstIdx_ETC___d977 or + IF_propDstIdx_0_lat_0_whas__73_THEN_propDstIdx_ETC___d976 or propDstIdx_1_dummy2_1$Q_OUT or - IF_propDstIdx_1_lat_0_whas__81_THEN_propDstIdx_ETC___d984) + IF_propDstIdx_1_lat_0_whas__80_THEN_propDstIdx_ETC___d983) begin case (srcRR_0) 1'd0: - SEL_ARR_propDstIdx_0_dummy2_1_read__027_AND_IF_ETC___d1058 = + SEL_ARR_propDstIdx_0_dummy2_1_read__026_AND_IF_ETC___d1057 = propDstIdx_0_dummy2_1$Q_OUT && - IF_propDstIdx_0_lat_0_whas__74_THEN_propDstIdx_ETC___d977; + IF_propDstIdx_0_lat_0_whas__73_THEN_propDstIdx_ETC___d976; 1'd1: - SEL_ARR_propDstIdx_0_dummy2_1_read__027_AND_IF_ETC___d1058 = + SEL_ARR_propDstIdx_0_dummy2_1_read__026_AND_IF_ETC___d1057 = propDstIdx_1_dummy2_1$Q_OUT && - IF_propDstIdx_1_lat_0_whas__81_THEN_propDstIdx_ETC___d984; + IF_propDstIdx_1_lat_0_whas__80_THEN_propDstIdx_ETC___d983; endcase end always@(srcRR_1_0 or propDstIdx_1_0_dummy2_1$Q_OUT or - IF_propDstIdx_1_0_lat_0_whas__148_THEN_propDst_ETC___d1151 or + IF_propDstIdx_1_0_lat_0_whas__147_THEN_propDst_ETC___d1150 or propDstIdx_1_1_dummy2_1$Q_OUT or - IF_propDstIdx_1_1_lat_0_whas__155_THEN_propDst_ETC___d1158) + IF_propDstIdx_1_1_lat_0_whas__154_THEN_propDst_ETC___d1157) begin case (srcRR_1_0) 1'd0: - SEL_ARR_propDstIdx_1_0_dummy2_1_read__291_AND__ETC___d1332 = + SEL_ARR_propDstIdx_1_0_dummy2_1_read__290_AND__ETC___d1331 = propDstIdx_1_0_dummy2_1$Q_OUT && - IF_propDstIdx_1_0_lat_0_whas__148_THEN_propDst_ETC___d1151; + IF_propDstIdx_1_0_lat_0_whas__147_THEN_propDst_ETC___d1150; 1'd1: - SEL_ARR_propDstIdx_1_0_dummy2_1_read__291_AND__ETC___d1332 = + SEL_ARR_propDstIdx_1_0_dummy2_1_read__290_AND__ETC___d1331 = propDstIdx_1_1_dummy2_1$Q_OUT && - IF_propDstIdx_1_1_lat_0_whas__155_THEN_propDst_ETC___d1158; + IF_propDstIdx_1_1_lat_0_whas__154_THEN_propDst_ETC___d1157; endcase end - always@(x__h58979 or n__read_id__h59165 or n__read_id__h59250) + always@(x__h58771 or n__read_id__h58957 or n__read_id__h59042) begin - case (x__h58979) - 1'd0: x__h59293 = n__read_id__h59165; - 1'd1: x__h59293 = n__read_id__h59250; + case (x__h58771) + 1'd0: x__h59085 = n__read_id__h58957; + 1'd1: x__h59085 = n__read_id__h59042; endcase end - always@(x__h58979 or n__read_child__h59166 or n__read_child__h59251) + always@(x__h58771 or n__read_child__h58958 or n__read_child__h59043) begin - case (x__h58979) - 1'd0: x__h59300 = n__read_child__h59166; - 1'd1: x__h59300 = n__read_child__h59251; + case (x__h58771) + 1'd0: x__h59092 = n__read_child__h58958; + 1'd1: x__h59092 = n__read_child__h59043; endcase end - always@(x__h58979 or - propDstData_0_dummy2_1_read__065_AND_IF_propDs_ETC___d1101 or - propDstData_1_dummy2_1_read__070_AND_IF_propDs_ETC___d1105) + always@(x__h58771 or + propDstData_0_dummy2_1_read__064_AND_IF_propDs_ETC___d1100 or + propDstData_1_dummy2_1_read__069_AND_IF_propDs_ETC___d1104) begin - case (x__h58979) + case (x__h58771) 1'd0: - CASE_x8979_0_propDstData_0_dummy2_1_read__065__ETC__q20 = - propDstData_0_dummy2_1_read__065_AND_IF_propDs_ETC___d1101; + CASE_x8771_0_propDstData_0_dummy2_1_read__064__ETC__q12 = + propDstData_0_dummy2_1_read__064_AND_IF_propDs_ETC___d1100; 1'd1: - CASE_x8979_0_propDstData_0_dummy2_1_read__065__ETC__q20 = - propDstData_1_dummy2_1_read__070_AND_IF_propDs_ETC___d1105; + CASE_x8771_0_propDstData_0_dummy2_1_read__064__ETC__q12 = + propDstData_1_dummy2_1_read__069_AND_IF_propDs_ETC___d1104; endcase end - always@(x__h58979 or - IF_propDstData_0_dummy2_1_read__065_THEN_IF_pr_ETC___d1081 or - IF_propDstData_1_dummy2_1_read__070_THEN_IF_pr_ETC___d1085) + always@(x__h58771 or + IF_propDstData_0_dummy2_1_read__064_THEN_IF_pr_ETC___d1080 or + IF_propDstData_1_dummy2_1_read__069_THEN_IF_pr_ETC___d1084) begin - case (x__h58979) + case (x__h58771) 1'd0: - CASE_x8979_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21 = - IF_propDstData_0_dummy2_1_read__065_THEN_IF_pr_ETC___d1081; + CASE_x8771_0_IF_propDstData_0_dummy2_1_read__0_ETC__q13 = + IF_propDstData_0_dummy2_1_read__064_THEN_IF_pr_ETC___d1080; 1'd1: - CASE_x8979_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21 = - IF_propDstData_1_dummy2_1_read__070_THEN_IF_pr_ETC___d1085; + CASE_x8771_0_IF_propDstData_0_dummy2_1_read__0_ETC__q13 = + IF_propDstData_1_dummy2_1_read__069_THEN_IF_pr_ETC___d1084; endcase end - always@(x__h58979 or - IF_propDstData_0_dummy2_1_read__065_THEN_IF_pr_ETC___d1091 or - IF_propDstData_1_dummy2_1_read__070_THEN_IF_pr_ETC___d1095) + always@(x__h58771 or + IF_propDstData_0_dummy2_1_read__064_THEN_IF_pr_ETC___d1090 or + IF_propDstData_1_dummy2_1_read__069_THEN_IF_pr_ETC___d1094) begin - case (x__h58979) + case (x__h58771) 1'd0: - CASE_x8979_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22 = - IF_propDstData_0_dummy2_1_read__065_THEN_IF_pr_ETC___d1091; + CASE_x8771_0_IF_propDstData_0_dummy2_1_read__0_ETC__q14 = + IF_propDstData_0_dummy2_1_read__064_THEN_IF_pr_ETC___d1090; 1'd1: - CASE_x8979_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22 = - IF_propDstData_1_dummy2_1_read__070_THEN_IF_pr_ETC___d1095; + CASE_x8771_0_IF_propDstData_0_dummy2_1_read__0_ETC__q14 = + IF_propDstData_1_dummy2_1_read__069_THEN_IF_pr_ETC___d1094; endcase end - always@(x__h58979 or n__read_addr__h59161 or n__read_addr__h59246) + always@(x__h58771 or n__read_addr__h58953 or n__read_addr__h59038) begin - case (x__h58979) + case (x__h58771) 1'd0: - CASE_x8979_0_n__read_addr9161_1_n__read_addr92_ETC__q23 = - n__read_addr__h59161; + CASE_x8771_0_n__read_addr8953_1_n__read_addr90_ETC__q15 = + n__read_addr__h58953; 1'd1: - CASE_x8979_0_n__read_addr9161_1_n__read_addr92_ETC__q23 = - n__read_addr__h59246; + CASE_x8771_0_n__read_addr8953_1_n__read_addr90_ETC__q15 = + n__read_addr__h59038; endcase end - always@(x__h77786 or n__read_child__h77967 or n__read_child__h78046) + always@(x__h77578 or n__read_child__h77759 or n__read_child__h77838) begin - case (x__h77786) - 1'd0: x__h80202 = n__read_child__h77967; - 1'd1: x__h80202 = n__read_child__h78046; + case (x__h77578) + 1'd0: x__h79994 = n__read_child__h77759; + 1'd1: x__h79994 = n__read_child__h77838; endcase end - always@(x__h77786 or + always@(x__h77578 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h77786) + case (x__h77578) 1'd0: - CASE_x7786_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24 = + CASE_x7578_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[512:449] : propDstData_1_0_rl[512:449]; 1'd1: - CASE_x7786_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24 = + CASE_x7578_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[512:449] : propDstData_1_1_rl[512:449]; endcase end - always@(x__h77786 or + always@(x__h77578 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h77786) + case (x__h77578) 1'd0: - CASE_x7786_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 = + CASE_x7578_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[448:385] : propDstData_1_0_rl[448:385]; 1'd1: - CASE_x7786_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 = + CASE_x7578_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[448:385] : propDstData_1_1_rl[448:385]; endcase end - always@(x__h77786 or + always@(x__h77578 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h77786) + case (x__h77578) 1'd0: - CASE_x7786_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26 = + CASE_x7578_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[384:321] : propDstData_1_0_rl[384:321]; 1'd1: - CASE_x7786_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26 = + CASE_x7578_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[384:321] : propDstData_1_1_rl[384:321]; endcase end - always@(x__h77786 or + always@(x__h77578 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h77786) + case (x__h77578) 1'd0: - CASE_x7786_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 = + CASE_x7578_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[320:257] : propDstData_1_0_rl[320:257]; 1'd1: - CASE_x7786_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 = + CASE_x7578_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[320:257] : propDstData_1_1_rl[320:257]; endcase end - always@(x__h77786 or + always@(x__h77578 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h77786) + case (x__h77578) 1'd0: - CASE_x7786_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28 = + CASE_x7578_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[256:193] : propDstData_1_0_rl[256:193]; 1'd1: - CASE_x7786_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28 = + CASE_x7578_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[256:193] : propDstData_1_1_rl[256:193]; endcase end - always@(x__h77786 or + always@(x__h77578 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h77786) + case (x__h77578) 1'd0: - CASE_x7786_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 = + CASE_x7578_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[192:129] : propDstData_1_0_rl[192:129]; 1'd1: - CASE_x7786_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 = + CASE_x7578_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[192:129] : propDstData_1_1_rl[192:129]; endcase end - always@(x__h77786 or + always@(x__h77578 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h77786) + case (x__h77578) 1'd0: - CASE_x7786_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30 = + CASE_x7578_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[128:65] : propDstData_1_0_rl[128:65]; 1'd1: - CASE_x7786_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30 = + CASE_x7578_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[128:65] : propDstData_1_1_rl[128:65]; endcase end - always@(x__h77786 or + always@(x__h77578 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h77786) + case (x__h77578) 1'd0: - CASE_x7786_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 = + CASE_x7578_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[64:1] : propDstData_1_0_rl[64:1]; 1'd1: - CASE_x7786_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 = + CASE_x7578_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[64:1] : propDstData_1_1_rl[64:1]; endcase end - always@(x__h77786 or + always@(x__h77578 or propDstData_1_0_dummy2_1$Q_OUT or - IF_propDstData_1_0_lat_0_whas__163_THEN_propDs_ETC___d1173 or + IF_propDstData_1_0_lat_0_whas__162_THEN_propDs_ETC___d1172 or propDstData_1_1_dummy2_1$Q_OUT or - IF_propDstData_1_1_lat_0_whas__201_THEN_propDs_ETC___d1211) + IF_propDstData_1_1_lat_0_whas__200_THEN_propDs_ETC___d1210) begin - case (x__h77786) + case (x__h77578) 1'd0: - CASE_x7786_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32 = + CASE_x7578_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24 = propDstData_1_0_dummy2_1$Q_OUT ? - IF_propDstData_1_0_lat_0_whas__163_THEN_propDs_ETC___d1173 : + IF_propDstData_1_0_lat_0_whas__162_THEN_propDs_ETC___d1172 : 2'd0; 1'd1: - CASE_x7786_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32 = + CASE_x7578_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24 = propDstData_1_1_dummy2_1$Q_OUT ? - IF_propDstData_1_1_lat_0_whas__201_THEN_propDs_ETC___d1211 : + IF_propDstData_1_1_lat_0_whas__200_THEN_propDs_ETC___d1210 : 2'd0; endcase end - always@(x__h77786 or - NOT_propDstData_1_0_dummy2_1_read__339_350_OR__ETC___d1351 or - NOT_propDstData_1_1_dummy2_1_read__341_352_OR__ETC___d1353) + always@(x__h77578 or + NOT_propDstData_1_0_dummy2_1_read__338_349_OR__ETC___d1350 or + NOT_propDstData_1_1_dummy2_1_read__340_351_OR__ETC___d1352) begin - case (x__h77786) + case (x__h77578) 1'd0: - CASE_x7786_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33 = - NOT_propDstData_1_0_dummy2_1_read__339_350_OR__ETC___d1351; + CASE_x7578_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25 = + NOT_propDstData_1_0_dummy2_1_read__338_349_OR__ETC___d1350; 1'd1: - CASE_x7786_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33 = - NOT_propDstData_1_1_dummy2_1_read__341_352_OR__ETC___d1353; + CASE_x7578_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25 = + NOT_propDstData_1_1_dummy2_1_read__340_351_OR__ETC___d1352; endcase end - always@(x__h77786 or n__read_addr__h77964 or n__read_addr__h78043) + always@(x__h77578 or n__read_addr__h77756 or n__read_addr__h77835) begin - case (x__h77786) + case (x__h77578) 1'd0: - CASE_x7786_0_n__read_addr7964_1_n__read_addr80_ETC__q34 = - n__read_addr__h77964; + CASE_x7578_0_n__read_addr7756_1_n__read_addr78_ETC__q26 = + n__read_addr__h77756; 1'd1: - CASE_x7786_0_n__read_addr7964_1_n__read_addr80_ETC__q34 = - n__read_addr__h78043; + CASE_x7578_0_n__read_addr7756_1_n__read_addr78_ETC__q26 = + n__read_addr__h77835; endcase end @@ -7670,6 +7414,10 @@ module mkProc(CLK, llc_mem_server_propDstData_0_rl <= `BSV_ASSIGNMENT_DELAY 65'h0AAAAAAAAAAAAAAAA; llc_mem_server_propDstIdx_0_rl <= `BSV_ASSIGNMENT_DELAY 1'd0; + llc_mem_server_rg_cacheline_cache_addr <= `BSV_ASSIGNMENT_DELAY 64'd1; + llc_mem_server_rg_cacheline_cache_dirty_delay <= `BSV_ASSIGNMENT_DELAY + 10'd0; + llc_mem_server_rg_cacheline_cache_state <= `BSV_ASSIGNMENT_DELAY 3'd3; mmioPlatform_cycle <= `BSV_ASSIGNMENT_DELAY 7'd0; mmioPlatform_fromHostAddr <= `BSV_ASSIGNMENT_DELAY 61'd0; mmioPlatform_fromHostQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0; @@ -7767,6 +7515,15 @@ module mkProc(CLK, if (llc_mem_server_propDstIdx_0_rl$EN) llc_mem_server_propDstIdx_0_rl <= `BSV_ASSIGNMENT_DELAY llc_mem_server_propDstIdx_0_rl$D_IN; + if (llc_mem_server_rg_cacheline_cache_addr$EN) + llc_mem_server_rg_cacheline_cache_addr <= `BSV_ASSIGNMENT_DELAY + llc_mem_server_rg_cacheline_cache_addr$D_IN; + if (llc_mem_server_rg_cacheline_cache_dirty_delay$EN) + llc_mem_server_rg_cacheline_cache_dirty_delay <= `BSV_ASSIGNMENT_DELAY + llc_mem_server_rg_cacheline_cache_dirty_delay$D_IN; + if (llc_mem_server_rg_cacheline_cache_state$EN) + llc_mem_server_rg_cacheline_cache_state <= `BSV_ASSIGNMENT_DELAY + llc_mem_server_rg_cacheline_cache_state$D_IN; if (mmioPlatform_cycle$EN) mmioPlatform_cycle <= `BSV_ASSIGNMENT_DELAY mmioPlatform_cycle$D_IN; if (mmioPlatform_fromHostAddr$EN) @@ -7879,6 +7636,9 @@ module mkProc(CLK, if (llc_axi4_adapter_rg_cline$EN) llc_axi4_adapter_rg_cline <= `BSV_ASSIGNMENT_DELAY llc_axi4_adapter_rg_cline$D_IN; + if (llc_mem_server_rg_cacheline_cache_data$EN) + llc_mem_server_rg_cacheline_cache_data <= `BSV_ASSIGNMENT_DELAY + llc_mem_server_rg_cacheline_cache_data$D_IN; if (mmioPlatform_amoResp$EN) mmioPlatform_amoResp <= `BSV_ASSIGNMENT_DELAY mmioPlatform_amoResp$D_IN; if (mmioPlatform_curReq$EN) @@ -7947,7 +7707,7 @@ module mkProc(CLK, llc_axi4_adapter_master_xactor_rg_rd_addr = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; llc_axi4_adapter_master_xactor_rg_rd_data = 71'h2AAAAAAAAAAAAAAAAA; llc_axi4_adapter_master_xactor_rg_wr_addr = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; - llc_axi4_adapter_master_xactor_rg_wr_data = 77'h0AAAAAAAAAAAAAAAAAAA; + llc_axi4_adapter_master_xactor_rg_wr_data = 73'h0AAAAAAAAAAAAAAAAAA; llc_axi4_adapter_master_xactor_rg_wr_resp = 6'h2A; llc_axi4_adapter_rg_cline = 512'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; @@ -7958,6 +7718,11 @@ module mkProc(CLK, llc_mem_server_enqDst_0_rl = 66'h2AAAAAAAAAAAAAAAA; llc_mem_server_propDstData_0_rl = 65'h0AAAAAAAAAAAAAAAA; llc_mem_server_propDstIdx_0_rl = 1'h0; + llc_mem_server_rg_cacheline_cache_addr = 64'hAAAAAAAAAAAAAAAA; + llc_mem_server_rg_cacheline_cache_data = + 512'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + llc_mem_server_rg_cacheline_cache_dirty_delay = 10'h2AA; + llc_mem_server_rg_cacheline_cache_state = 3'h2; mmioPlatform_amoResp = 64'hAAAAAAAAAAAAAAAA; mmioPlatform_curReq = 67'h2AAAAAAAAAAAAAAAA; mmioPlatform_cycle = 7'h2A; @@ -8002,7 +7767,7 @@ module mkProc(CLK, mmio_axi4_adapter_master_xactor_rg_rd_data = 71'h2AAAAAAAAAAAAAAAAA; mmio_axi4_adapter_master_xactor_rg_wr_addr = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; - mmio_axi4_adapter_master_xactor_rg_wr_data = 77'h0AAAAAAAAAAAAAAAAAAA; + mmio_axi4_adapter_master_xactor_rg_wr_data = 73'h0AAAAAAAAAAAAAAAAAA; mmio_axi4_adapter_master_xactor_rg_wr_resp = 6'h2A; propDstData_0_rl = 73'h0AAAAAAAAAAAAAAAAAA; propDstData_1_0_rl = @@ -8028,29 +7793,37 @@ module mkProc(CLK, #0; if (RST_N != `BSV_RESET_VALUE) if (EN_start) - $display("Proc.start: startpc = 0x%0h, tohostAddr = 0x%0h, fromhostAddr = %0h", + begin + v__h160855 = $stime; + #0; + end + v__h160849 = v__h160855 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (EN_start) + $display("%0d: %m.method start: startpc %0h, tohostAddr %0h, fromhostAddr %0h", + v__h160849, start_startpc, start_tohostAddr, start_fromhostAddr); if (RST_N != `BSV_RESET_VALUE) - if (NOT_enqDst_0_dummy2_0_read__048_049_OR_NOT_enq_ETC___d1064 && - IF_SEL_ARR_propDstIdx_0_dummy2_1_read__027_AND_ETC___d1134 && - NOT_propDstIdx_0_dummy2_1_read__027_028_OR_IF__ETC___d1061) + if (NOT_enqDst_0_dummy2_0_read__047_048_OR_NOT_enq_ETC___d1063 && + IF_SEL_ARR_propDstIdx_0_dummy2_1_read__026_AND_ETC___d1133 && + NOT_propDstIdx_0_dummy2_1_read__026_027_OR_IF__ETC___d1060) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) - if (NOT_enqDst_0_dummy2_0_read__048_049_OR_NOT_enq_ETC___d1064 && - x__h58979 && + if (NOT_enqDst_0_dummy2_0_read__047_048_OR_NOT_enq_ETC___d1063 && + x__h58771 && (!propDstIdx_1_dummy2_1$Q_OUT || !CAN_FIRE_RL_srcPropose_1 && !propDstIdx_1_rl)) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) - if (NOT_enqDst_1_0_dummy2_0_read__322_323_OR_NOT_e_ETC___d1338 && - IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__291_A_ETC___d1436 && - NOT_propDstIdx_1_0_dummy2_1_read__291_292_OR_I_ETC___d1335) + if (NOT_enqDst_1_0_dummy2_0_read__321_322_OR_NOT_e_ETC___d1337 && + IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__290_A_ETC___d1435 && + NOT_propDstIdx_1_0_dummy2_1_read__290_291_OR_I_ETC___d1334) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) - if (NOT_enqDst_1_0_dummy2_0_read__322_323_OR_NOT_e_ETC___d1338 && - x__h77786 && + if (NOT_enqDst_1_0_dummy2_0_read__321_322_OR_NOT_e_ETC___d1337 && + x__h77578 && (!propDstIdx_1_1_dummy2_1$Q_OUT || !CAN_FIRE_RL_srcPropose_3 && !propDstIdx_1_1_rl)) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); @@ -8060,14 +7833,14 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost) begin - v__h152458 = $stime; + v__h160396 = $stime; #0; end - v__h152452 = v__h152458 / 32'd10; + v__h160390 = v__h160396 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost) $display("%0d: mmioPlatform.rl_tohost: 0x%0x (= %0d)", - v__h152452, + v__h160390, mmioPlatform_toHostQ_data_0, mmioPlatform_toHostQ_data_0); if (RST_N != `BSV_RESET_VALUE) @@ -8077,7 +7850,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0 && mmioPlatform_toHostQ_data_0[63:1] != 63'd0) - $display("FAIL %0d", failed_testnum__h152501); + $display("FAIL %0d", failed_testnum__h160439); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0) $finish(32'd0); @@ -8085,14 +7858,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h4189 = $stime; + v__h3984 = $stime; #0; end - v__h4183 = v__h4189 / 32'd10; + v__h3978 = v__h3984 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%0d: MMIO_AXI4_Adapter.rl_handle_read_rsps ", v__h4183); + $display("%0d: MMIO_AXI4_Adapter.rl_handle_read_rsps ", v__h3978); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -8152,16 +7925,16 @@ module mkProc(CLK, mmio_axi4_adapter_cfg_verbosity != 4'd0 && mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) begin - v__h4362 = $stime; + v__h4157 = $stime; #0; end - v__h4356 = v__h4362 / 32'd10; + v__h4151 = v__h4157 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0 && mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) $display("%0d: MMIO_AXI4_Adapter.rl_handle_read_rsp: fabric response error", - v__h4356); + v__h4151); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0 && @@ -8265,15 +8038,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h4626 = $stime; + v__h4421 = $stime; #0; end - v__h4620 = v__h4626 / 32'd10; + v__h4415 = v__h4421 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) $display("%d: MMIO_AXI4_Adapter.rl_handle_write_req: St request:", - v__h4620); + v__h4415); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -8442,14 +8215,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) begin - v__h6665 = $stime; + v__h6458 = $stime; #0; end - v__h6659 = v__h6665 / 32'd10; + v__h6452 = v__h6458 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h6659); + $display("%0d: ERROR: CreditCounter: overflow", v__h6452); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) @@ -8557,15 +8330,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && - mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write(", ", "wdata: "); + $write("AXI4_Wr_Data { ", "wdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -8602,15 +8367,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h2465 = $stime; + v__h2260 = $stime; #0; end - v__h2459 = v__h2465 / 32'd10; + v__h2254 = v__h2260 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) $display("%0d: MMIO_AXI4_Adapter.rl_handle_read_req: Ld request", - v__h2459); + v__h2254); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -8875,14 +8640,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h6966 = $stime; + v__h6758 = $stime; #0; end - v__h6960 = v__h6966 / 32'd10; + v__h6752 = v__h6758 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%0d: MMIO_AXI4_Adapter.rl_discard_write_rsp", v__h6960); + $display("%0d: MMIO_AXI4_Adapter.rl_discard_write_rsp", v__h6752); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -8919,15 +8684,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) begin - v__h7459 = $stime; + v__h7251 = $stime; #0; end - v__h7453 = v__h7459 / 32'd10; + v__h7245 = v__h7251 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) $display("%0d: MMIO_AXI4_Adapter.rl_discard_write_rsp: fabric response error: exit", - v__h7453); + v__h7245); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) @@ -8967,14 +8732,14 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) begin - v__h7622 = $stime; + v__h7414 = $stime; #0; end - v__h7616 = v__h7622 / 32'd10; + v__h7408 = v__h7414 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $display("%0d: ERROR: MMIO_AXI4_Adapter.rl_handle_non_Ld_St", - v__h7616); + v__h7408); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write(" "); if (RST_N != `BSV_RESET_VALUE) @@ -9172,13 +8937,13 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && mmioPlatform_fromHostQ_empty && - x__h40487 != 64'd0) + x__h40279 != 64'd0) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && !mmioPlatform_fromHostQ_empty && - x__h38421 != 64'd0) + x__h38213 != 64'd0) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && @@ -9187,1096 +8952,94 @@ module mkProc(CLK, mmioPlatform_reqFunc[5:4] != 2'd1) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) - if (NOT_llc_mem_server_enqDst_0_dummy2_0_read__531_ETC___d1538 && + if (NOT_llc_mem_server_enqDst_0_dummy2_0_read__672_ETC___d1679 && !CAN_FIRE_RL_llc_mem_server_srcPropose && !llc_mem_server_propDstIdx_0_rl) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - begin - v__h94627 = $stime; - #0; - end - v__h94621 = v__h94627 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $display("%0d: %m.sendMemLoaderReqToLLC_wr: ERROR: awsize is not code for 1,2,4,8", - v__h94621); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011 && - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011 && - !llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1644) - begin - v__h94672 = $stime; - #0; - end - v__h94666 = v__h94672 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1644) - $display("%0d: %m.sendMemLoaderReqToLLC_wr: ERROR: wlast is 1", - v__h94666); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1644) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1644) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1644) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1644) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1644) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1644) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1644) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1644) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1644) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1644) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1644) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1644) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1644) - $write("'h%h", llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1644) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1644) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1644) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1644) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1644) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1644) - $write("'h%h", llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1644) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1644) - $write("'h%h", llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1644) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1644) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1644) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1644) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1644) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1644) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1644) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1644) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1644) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1644) - $write("'h%h", llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1644) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1644) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1644) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1644) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1644) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - begin - v__h94582 = $stime; - #0; - end - v__h94576 = v__h94582 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $display("%0d: %m.sendMemLoaderReqToLLC_wr: ERROR: awlen is not 0 (burst length is not 1)", - v__h94576); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0 && - llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0 && - !llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_wr && - llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[28:21] != 8'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - begin - v__h105664 = $stime; - #0; - end - v__h105658 = v__h105664 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $display("%0d: %m.sendMemLoaderReqToLLC_rd: ERROR: arsize is not code for 1,2,4,8", - v__h105658); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] == 8'd0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b001 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b010 && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - begin - v__h105619 = $stime; - #0; - end - v__h105613 = v__h105619 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $display("%0d: %m.sendMemLoaderReqToLLC_rd: ERROR: arlen is not 0 (burst length is not 1)", - v__h105613); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_mem_server_sendMemLoaderReqToLLC_rd && - llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[28:21] != 8'd0) - $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_mem_server_sendStRespToTlb) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) begin - v__h124262 = $stime; + v__h132353 = $stime; #0; end - v__h124256 = v__h124262 / 32'd10; + v__h132347 = v__h132353 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsps: beat %0d ", - v__h124256, + v__h132347, llc_axi4_adapter_rg_rd_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[2:1]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785 && + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763 && llc_axi4_adapter_master_xactor_rg_rd_data[0]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785 && + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763 && !llc_axi4_adapter_master_xactor_rg_rd_data[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) begin - v__h124429 = $stime; + v__h132520 = $stime; #0; end - v__h124423 = v__h124429 / 32'd10; + v__h132514 = v__h132520 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsp: fabric response error; exit", - v__h124423); + v__h132514); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) @@ -10338,135 +9101,135 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write(" Response to LLC: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write("MemRsMsg { ", "data: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write(", ", "child: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write(", ", "id: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write("LdMemRqId { ", "refill: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785 && + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763 && llc_axi4_adapter_f_pending_reads$D_OUT[4]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785 && + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763 && !llc_axi4_adapter_f_pending_reads$D_OUT[4]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write(", ", "mshrIdx: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write("'h%h", llc_axi4_adapter_f_pending_reads$D_OUT[3:0], " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write(" }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_wr_req_beat == 3'd0) begin - v__h126532 = $stime; + v__h134623 = $stime; #0; end - v__h126526 = v__h126532 / 32'd10; + v__h134617 = v__h134623 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_wr_req_beat == 3'd0) $display("%d: LLC_AXI4_Adapter.rl_handle_write_req: Wb request from LLC to memory:", - v__h126526); + v__h134617); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && @@ -11664,177 +10427,169 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) begin - v__h143878 = $stime; + v__h151967 = $stime; #0; end - v__h143872 = v__h143878 / 32'd10; + v__h151961 = v__h151967 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h143872); + $display("%0d: ERROR: CreditCounter: overflow", v__h151961); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) $finish(32'd1); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write(" To fabric: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write("AXI4_Wr_Addr { ", "awid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write(", ", "awaddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) - $write("'h%h", mem_req_wr_addr_awaddr__h137787); + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) + $write("'h%h", mem_req_wr_addr_awaddr__h145878); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write(", ", "awlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write("'h%h", 8'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write(", ", "awsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write("'h%h", 3'b011); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write(", ", "awburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write("'h%h", 2'b01); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write(", ", "awlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write("'h%h", 1'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write(", ", "awcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write("'h%h", 4'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write(", ", "awprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write("'h%h", 3'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write(", ", "awqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write(", ", "awregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write(", ", "awuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write("'h%h", 1'h0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) - $write("AXI4_Wr_Data { ", "wid: "); + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) + $write("AXI4_Wr_Data { ", "wdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) - $write("'h%h", 4'd0); + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) + $write("'h%h", data64__h145793); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) - $write("'h%h", data64__h137702); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write(", ", "wstrb: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) - $write("'h%h", strb8__h137703); + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) + $write("'h%h", strb8__h145794); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write(", ", "wlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write(", ", "wuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write("'h%h", 1'h0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_rd_req_beat == 3'd0) begin - v__h123643 = $stime; + v__h131734 = $stime; #0; end - v__h123637 = v__h123643 / 32'd10; + v__h131728 = v__h131734 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_rd_req_beat == 3'd0) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_req: Ld request from LLC to memory: beat %0d", - v__h123637, + v__h131728, llc_axi4_adapter_rg_rd_req_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && @@ -11905,159 +10660,159 @@ module mkProc(CLK, $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write("AXI4_Rd_Addr { ", "arid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write(", ", "araddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) - $write("'h%h", mem_req_rd_addr_araddr__h123863); + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) + $write("'h%h", mem_req_rd_addr_araddr__h131954); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write(", ", "arlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write("'h%h", 8'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write(", ", "arsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write("'h%h", 3'b011); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write(", ", "arburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write("'h%h", 2'b01); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write(", ", "arlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write("'h%h", 1'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write(", ", "arcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write("'h%h", 4'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write(", ", "arprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write("'h%h", 3'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write(", ", "arqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write(", ", "arregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write(", ", "aruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write("'h%h", 1'h0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) begin - v__h150573 = $stime; + v__h158661 = $stime; #0; end - v__h150567 = v__h150573 / 32'd10; + v__h158655 = v__h158661 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $display("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: beat %0d ", - v__h150567, + v__h158655, llc_axi4_adapter_rg_wr_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write("'h%h", llc_axi4_adapter_master_xactor_rg_wr_resp[5:2]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write("'h%h", llc_axi4_adapter_master_xactor_rg_wr_resp[1:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__768_U_ETC___d1785) + NOT_llc_axi4_adapter_cfg_verbosity_read__746_U_ETC___d1763) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) begin - v__h151081 = $stime; + v__h159169 = $stime; #0; end - v__h151075 = v__h151081 / 32'd10; + v__h159163 = v__h159169 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) $display("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: fabric response error: exit", - v__h151075); + v__h159163); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkRFileSynth.v b/src_SSITH_P3_sim/Verilog_RTL/mkRFileSynth.v index 35cd8cb..05c143e 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkRFileSynth.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkRFileSynth.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkRas.v b/src_SSITH_P3_sim/Verilog_RTL/mkRas.v index 969976c..9192168 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkRas.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkRas.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkRegRenamingTable.v b/src_SSITH_P3_sim/Verilog_RTL/mkRegRenamingTable.v index 2180978..e87942d 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkRegRenamingTable.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkRegRenamingTable.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkReorderBufferSynth.v b/src_SSITH_P3_sim/Verilog_RTL/mkReorderBufferSynth.v index a6f105b..e10567f 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkReorderBufferSynth.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkReorderBufferSynth.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkReservationStationAlu.v b/src_SSITH_P3_sim/Verilog_RTL/mkReservationStationAlu.v index 8332a8e..7f24bd5 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkReservationStationAlu.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkReservationStationAlu.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkReservationStationFpuMulDiv.v b/src_SSITH_P3_sim/Verilog_RTL/mkReservationStationFpuMulDiv.v index 3c450e9..91cde75 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkReservationStationFpuMulDiv.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkReservationStationFpuMulDiv.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // @@ -12792,71 +12792,6 @@ module mkReservationStationFpuMulDiv(CLK, m_tag_15[11]; endcase end - always@(idx__h159797 or - m_data_0 or - m_data_1 or - m_data_2 or - m_data_3 or - m_data_4 or - m_data_5 or - m_data_6 or - m_data_7 or - m_data_8 or - m_data_9 or - m_data_10 or - m_data_11 or m_data_12 or m_data_13 or m_data_14 or m_data_15) - begin - case (idx__h159797) - 4'd0: - SEL_ARR_m_data_0_093_BIT_2_637_m_data_1_096_BI_ETC___d1654 = - m_data_0[2]; - 4'd1: - SEL_ARR_m_data_0_093_BIT_2_637_m_data_1_096_BI_ETC___d1654 = - m_data_1[2]; - 4'd2: - SEL_ARR_m_data_0_093_BIT_2_637_m_data_1_096_BI_ETC___d1654 = - m_data_2[2]; - 4'd3: - SEL_ARR_m_data_0_093_BIT_2_637_m_data_1_096_BI_ETC___d1654 = - m_data_3[2]; - 4'd4: - SEL_ARR_m_data_0_093_BIT_2_637_m_data_1_096_BI_ETC___d1654 = - m_data_4[2]; - 4'd5: - SEL_ARR_m_data_0_093_BIT_2_637_m_data_1_096_BI_ETC___d1654 = - m_data_5[2]; - 4'd6: - SEL_ARR_m_data_0_093_BIT_2_637_m_data_1_096_BI_ETC___d1654 = - m_data_6[2]; - 4'd7: - SEL_ARR_m_data_0_093_BIT_2_637_m_data_1_096_BI_ETC___d1654 = - m_data_7[2]; - 4'd8: - SEL_ARR_m_data_0_093_BIT_2_637_m_data_1_096_BI_ETC___d1654 = - m_data_8[2]; - 4'd9: - SEL_ARR_m_data_0_093_BIT_2_637_m_data_1_096_BI_ETC___d1654 = - m_data_9[2]; - 4'd10: - SEL_ARR_m_data_0_093_BIT_2_637_m_data_1_096_BI_ETC___d1654 = - m_data_10[2]; - 4'd11: - SEL_ARR_m_data_0_093_BIT_2_637_m_data_1_096_BI_ETC___d1654 = - m_data_11[2]; - 4'd12: - SEL_ARR_m_data_0_093_BIT_2_637_m_data_1_096_BI_ETC___d1654 = - m_data_12[2]; - 4'd13: - SEL_ARR_m_data_0_093_BIT_2_637_m_data_1_096_BI_ETC___d1654 = - m_data_13[2]; - 4'd14: - SEL_ARR_m_data_0_093_BIT_2_637_m_data_1_096_BI_ETC___d1654 = - m_data_14[2]; - 4'd15: - SEL_ARR_m_data_0_093_BIT_2_637_m_data_1_096_BI_ETC___d1654 = - m_data_15[2]; - endcase - end always@(idx__h159797 or m_data_0 or m_data_1 or @@ -12922,6 +12857,71 @@ module mkReservationStationFpuMulDiv(CLK, m_data_15[0]; endcase end + always@(idx__h159797 or + m_data_0 or + m_data_1 or + m_data_2 or + m_data_3 or + m_data_4 or + m_data_5 or + m_data_6 or + m_data_7 or + m_data_8 or + m_data_9 or + m_data_10 or + m_data_11 or m_data_12 or m_data_13 or m_data_14 or m_data_15) + begin + case (idx__h159797) + 4'd0: + SEL_ARR_m_data_0_093_BIT_2_637_m_data_1_096_BI_ETC___d1654 = + m_data_0[2]; + 4'd1: + SEL_ARR_m_data_0_093_BIT_2_637_m_data_1_096_BI_ETC___d1654 = + m_data_1[2]; + 4'd2: + SEL_ARR_m_data_0_093_BIT_2_637_m_data_1_096_BI_ETC___d1654 = + m_data_2[2]; + 4'd3: + SEL_ARR_m_data_0_093_BIT_2_637_m_data_1_096_BI_ETC___d1654 = + m_data_3[2]; + 4'd4: + SEL_ARR_m_data_0_093_BIT_2_637_m_data_1_096_BI_ETC___d1654 = + m_data_4[2]; + 4'd5: + SEL_ARR_m_data_0_093_BIT_2_637_m_data_1_096_BI_ETC___d1654 = + m_data_5[2]; + 4'd6: + SEL_ARR_m_data_0_093_BIT_2_637_m_data_1_096_BI_ETC___d1654 = + m_data_6[2]; + 4'd7: + SEL_ARR_m_data_0_093_BIT_2_637_m_data_1_096_BI_ETC___d1654 = + m_data_7[2]; + 4'd8: + SEL_ARR_m_data_0_093_BIT_2_637_m_data_1_096_BI_ETC___d1654 = + m_data_8[2]; + 4'd9: + SEL_ARR_m_data_0_093_BIT_2_637_m_data_1_096_BI_ETC___d1654 = + m_data_9[2]; + 4'd10: + SEL_ARR_m_data_0_093_BIT_2_637_m_data_1_096_BI_ETC___d1654 = + m_data_10[2]; + 4'd11: + SEL_ARR_m_data_0_093_BIT_2_637_m_data_1_096_BI_ETC___d1654 = + m_data_11[2]; + 4'd12: + SEL_ARR_m_data_0_093_BIT_2_637_m_data_1_096_BI_ETC___d1654 = + m_data_12[2]; + 4'd13: + SEL_ARR_m_data_0_093_BIT_2_637_m_data_1_096_BI_ETC___d1654 = + m_data_13[2]; + 4'd14: + SEL_ARR_m_data_0_093_BIT_2_637_m_data_1_096_BI_ETC___d1654 = + m_data_14[2]; + 4'd15: + SEL_ARR_m_data_0_093_BIT_2_637_m_data_1_096_BI_ETC___d1654 = + m_data_15[2]; + endcase + end always@(idx__h159797 or m_data_0 or m_data_1 or diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkReservationStationMem.v b/src_SSITH_P3_sim/Verilog_RTL/mkReservationStationMem.v index e62ab6f..62c6ac0 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkReservationStationMem.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkReservationStationMem.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkRobRowSynth.v b/src_SSITH_P3_sim/Verilog_RTL/mkRobRowSynth.v index 4928ccd..069e4b5 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkRobRowSynth.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkRobRowSynth.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkScoreboardAggr.v b/src_SSITH_P3_sim/Verilog_RTL/mkScoreboardAggr.v index 272eb5f..b3cad00 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkScoreboardAggr.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkScoreboardAggr.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkScoreboardCons.v b/src_SSITH_P3_sim/Verilog_RTL/mkScoreboardCons.v index f4454ce..91b5454 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkScoreboardCons.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkScoreboardCons.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkSimpleRespQ.v b/src_SSITH_P3_sim/Verilog_RTL/mkSimpleRespQ.v index 55f1f95..8874275 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkSimpleRespQ.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkSimpleRespQ.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkSoC_Map.v b/src_SSITH_P3_sim/Verilog_RTL/mkSoC_Map.v index cab40b7..4529f80 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkSoC_Map.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkSoC_Map.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkSpecTagManager.v b/src_SSITH_P3_sim/Verilog_RTL/mkSpecTagManager.v index de644d8..689b342 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkSpecTagManager.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkSpecTagManager.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkSplitLSQ.v b/src_SSITH_P3_sim/Verilog_RTL/mkSplitLSQ.v index f4abb20..8482b6b 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkSplitLSQ.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkSplitLSQ.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkSplitTransCache.v b/src_SSITH_P3_sim/Verilog_RTL/mkSplitTransCache.v index 12bf092..7756330 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkSplitTransCache.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkSplitTransCache.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkStoreBufferEhr.v b/src_SSITH_P3_sim/Verilog_RTL/mkStoreBufferEhr.v index 5a3955d..0e56392 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkStoreBufferEhr.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkStoreBufferEhr.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkSyncBramFifo_w36_d512.v b/src_SSITH_P3_sim/Verilog_RTL/mkSyncBramFifo_w36_d512.v index a35dc56..66d3468 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkSyncBramFifo_w36_d512.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkSyncBramFifo_w36_d512.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkSyncFifo_w32_d16.v b/src_SSITH_P3_sim/Verilog_RTL/mkSyncFifo_w32_d16.v index 912e41c..7b7bf09 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkSyncFifo_w32_d16.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkSyncFifo_w32_d16.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkTourGHistReg.v b/src_SSITH_P3_sim/Verilog_RTL/mkTourGHistReg.v index 332464f..a049da6 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkTourGHistReg.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkTourGHistReg.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkTourPred.v b/src_SSITH_P3_sim/Verilog_RTL/mkTourPred.v index 467a6f5..6cef5a7 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkTourPred.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkTourPred.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkTourPredSecure.v b/src_SSITH_P3_sim/Verilog_RTL/mkTourPredSecure.v index ec4684f..7ab9bb7 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkTourPredSecure.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkTourPredSecure.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkXilinxFpDiv.v b/src_SSITH_P3_sim/Verilog_RTL/mkXilinxFpDiv.v index 5542e05..88e0704 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkXilinxFpDiv.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkXilinxFpDiv.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkXilinxFpDivIP.v b/src_SSITH_P3_sim/Verilog_RTL/mkXilinxFpDivIP.v index e02e15f..6eed40b 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkXilinxFpDivIP.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkXilinxFpDivIP.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkXilinxFpDivSim.v b/src_SSITH_P3_sim/Verilog_RTL/mkXilinxFpDivSim.v index 8aa7c23..e610c1f 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkXilinxFpDivSim.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkXilinxFpDivSim.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkXilinxFpFma.v b/src_SSITH_P3_sim/Verilog_RTL/mkXilinxFpFma.v index 4456a2c..b0b9d18 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkXilinxFpFma.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkXilinxFpFma.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkXilinxFpFmaIP.v b/src_SSITH_P3_sim/Verilog_RTL/mkXilinxFpFmaIP.v index 48aa46a..de3ff14 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkXilinxFpFmaIP.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkXilinxFpFmaIP.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkXilinxFpFmaSim.v b/src_SSITH_P3_sim/Verilog_RTL/mkXilinxFpFmaSim.v index 5e48e45..544866c 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkXilinxFpFmaSim.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkXilinxFpFmaSim.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkXilinxFpSqrt.v b/src_SSITH_P3_sim/Verilog_RTL/mkXilinxFpSqrt.v index 914ee43..69d500c 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkXilinxFpSqrt.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkXilinxFpSqrt.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkXilinxFpSqrtIP.v b/src_SSITH_P3_sim/Verilog_RTL/mkXilinxFpSqrtIP.v index 8e7349c..413315e 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkXilinxFpSqrtIP.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkXilinxFpSqrtIP.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/mkXilinxFpSqrtSim.v b/src_SSITH_P3_sim/Verilog_RTL/mkXilinxFpSqrtSim.v index 0ccba7e..85ac1bf 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/mkXilinxFpSqrtSim.v +++ b/src_SSITH_P3_sim/Verilog_RTL/mkXilinxFpSqrtSim.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/module_alu.v b/src_SSITH_P3_sim/Verilog_RTL/module_alu.v index c1b7f05..3ca27d9 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/module_alu.v +++ b/src_SSITH_P3_sim/Verilog_RTL/module_alu.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/module_aluBr.v b/src_SSITH_P3_sim/Verilog_RTL/module_aluBr.v index 91bc37f..9ec85ca 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/module_aluBr.v +++ b/src_SSITH_P3_sim/Verilog_RTL/module_aluBr.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/module_amoExec.v b/src_SSITH_P3_sim/Verilog_RTL/module_amoExec.v index cf33b5c..fe0dcca 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/module_amoExec.v +++ b/src_SSITH_P3_sim/Verilog_RTL/module_amoExec.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/module_basicExec.v b/src_SSITH_P3_sim/Verilog_RTL/module_basicExec.v index d66bd33..c47f51b 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/module_basicExec.v +++ b/src_SSITH_P3_sim/Verilog_RTL/module_basicExec.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/module_brAddrCalc.v b/src_SSITH_P3_sim/Verilog_RTL/module_brAddrCalc.v index 8fe2740..2ffba0b 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/module_brAddrCalc.v +++ b/src_SSITH_P3_sim/Verilog_RTL/module_brAddrCalc.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/module_checkForException.v b/src_SSITH_P3_sim/Verilog_RTL/module_checkForException.v index 7229e22..2502050 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/module_checkForException.v +++ b/src_SSITH_P3_sim/Verilog_RTL/module_checkForException.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/module_decode.v b/src_SSITH_P3_sim/Verilog_RTL/module_decode.v index 224570a..e10e514 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/module_decode.v +++ b/src_SSITH_P3_sim/Verilog_RTL/module_decode.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/module_decodeBrPred.v b/src_SSITH_P3_sim/Verilog_RTL/module_decodeBrPred.v index 5655d00..76da3ab 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/module_decodeBrPred.v +++ b/src_SSITH_P3_sim/Verilog_RTL/module_decodeBrPred.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/module_execFpuSimple.v b/src_SSITH_P3_sim/Verilog_RTL/module_execFpuSimple.v index 829903f..95a0b64 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/module_execFpuSimple.v +++ b/src_SSITH_P3_sim/Verilog_RTL/module_execFpuSimple.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // // diff --git a/src_SSITH_P3_sim/Verilog_RTL/module_getControlFlow.v b/src_SSITH_P3_sim/Verilog_RTL/module_getControlFlow.v index f1f3ac2..9e73d6c 100644 --- a/src_SSITH_P3_sim/Verilog_RTL/module_getControlFlow.v +++ b/src_SSITH_P3_sim/Verilog_RTL/module_getControlFlow.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // // //