From da1fd3781a69215ed781fd41a682ee07785f6ac1 Mon Sep 17 00:00:00 2001
From: Marno van der Maas <34654485+marnovandermaas@users.noreply.github.com>
Date: Tue, 9 Mar 2021 10:58:56 +0000
Subject: [PATCH] Correction in testbench section

---
 README.md | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/README.md b/README.md
index 63c95e6..72e657c 100644
--- a/README.md
+++ b/README.md
@@ -58,10 +58,10 @@ timer and a UART for console I/O.
 still working out robust mechanisms to import C code, which is used in
 parts of the testbench.]
 
-This repository contains two sample build directories, to build
+This repository contains four sample build directories, to build
 an RV64ACDFIMSUxCHERI simulator, using Bluesim and Verilog simulation.
-The generated Verilog is synthesizable.
 There are also RVFI-DII variants of these to be used with [TestRIG](https://github.com/CTSRD-CHERI/TestRIG).
+The generated Verilog is synthesizable.
 
 #### Simulation