From db57e909fcb31d779e91d27d8cd6b8f8b6189128 Mon Sep 17 00:00:00 2001 From: Marno Date: Wed, 17 Mar 2021 15:56:03 +0000 Subject: [PATCH] Added calling tagsparams.py in Include_Common.mk --- builds/Resources/Include_Common.mk | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/builds/Resources/Include_Common.mk b/builds/Resources/Include_Common.mk index 769b293..89b0927 100644 --- a/builds/Resources/Include_Common.mk +++ b/builds/Resources/Include_Common.mk @@ -17,6 +17,7 @@ help: @echo ' For Bluesim: generates Bluesim intermediate files' @echo ' For Verilog simulation: generates RTL' @echo ' make simulator Compiles and links intermediate files/RTL to create simulation executable' + @echo ' make tagsparams Generates the CHERI tag controller parameters source file' @echo ' (Bluesim, verilator or iverilog)' @echo ' make all = make compile simulator' @echo '' @@ -92,6 +93,18 @@ isa_tests: $(REPO)/Tests/Run_regression.py ./exe_HW_sim $(REPO) ./Logs $(ARCH) @echo "Finished running regressions; saved logs in Logs/" +# ================================================================ +# Generate Bluespec CHERI tag controller source file +CAPSIZE = 128 +TAGS_STRUCT = 0 64 +TAGS_ALIGN = 32 +.PHONY: tagsparams +tagsparams: $(REPO)/libs/TagController/tagsparams.py + @echo "INFO: Re-generating CHERI tag controller parameters" + $^ -v -c $(CAPSIZE) -s $(TAGS_STRUCT:"%"=%) -a $(TAGS_ALIGN) --covered-start-addr 0x80000000 --covered-mem-size 0x3fffc000 --top-addr 0xbffff000 -b TagTableStructure.bsv + @echo "INFO: Re-generated CHERI tag controller parameters" +compile: tagsparams + # ================================================================ .PHONY: clean