diff --git a/libs/RISCV_HPM_Events b/libs/RISCV_HPM_Events
index bf5107c..9e345b2 160000
--- a/libs/RISCV_HPM_Events
+++ b/libs/RISCV_HPM_Events
@@ -1 +1 @@
-Subproject commit bf5107c39ce7e59c21d4372a2c349a25b0145cc4
+Subproject commit 9e345b27e848adbc979abd08f2b8ccdc24845a0e
diff --git a/libs/TagController b/libs/TagController
index 7c9ac94..99c43e8 160000
--- a/libs/TagController
+++ b/libs/TagController
@@ -1 +1 @@
-Subproject commit 7c9ac94d1d93ea4086ac9320c560cb262432dfc5
+Subproject commit 99c43e81384741ae11e098a63514a78bd43637e2
diff --git a/src_Core/CPU/Core.bsv b/src_Core/CPU/Core.bsv
index d40ef31..ad6562a 100644
--- a/src_Core/CPU/Core.bsv
+++ b/src_Core/CPU/Core.bsv
@@ -212,7 +212,7 @@ interface Core;
 
 `ifdef PERFORMANCE_MONITORING
     method Action events_llc(EventsLL events);
-    method Action events_tgc(EventsCacheCore events);
+    method Action events_tgc(EventsTGC events);
 `endif
 endinterface
 
@@ -1150,7 +1150,7 @@ module mkCore#(CoreId coreId)(Core);
      // different fields than the TLB, which makes it safe to combine them
 
      Reg#(EventsLL) events_llc_reg <- mkRegU;
-     Reg#(EventsCacheCore) events_tgc_reg <- mkRegU;
+     Reg#(EventsTGC) events_tgc_reg <- mkRegU;
      rule report_events;
          EventsCore events = unpack(pack(commitStage.events));
          events.evt_REDIRECT = zeroExtend(pack(fetchStage.redirect_evt));
@@ -1160,7 +1160,7 @@ module mkCore#(CoreId coreId)(Core);
      EventsCore core_evts = unpack(pack(coreFix.memExeIfc.events) | pack(hpm_core_events[0]));
      EventsL1I imem_evts = unpack(pack(iMem.events) | pack(iTlb.events));
      EventsL1D dmem_evts = unpack(pack(dMem.events) | pack(dTlb.events));
-     EventsCacheCore tgc_evts = events_tgc_reg;
+     EventsTGC tgc_evts = events_tgc_reg;
      EventsLL llmem_evts = unpack(pack(events_llc_reg) | pack(l2Tlb.events));
      Maybe#(EventsTransExe) mab_trans_exe = tagged Invalid;
 
@@ -1182,7 +1182,7 @@ module mkCore#(CoreId coreId)(Core);
 
      let ev_struct = HPMEvents{mab_EventsCore: tagged Valid core_evts, mab_EventsL1I: tagged Valid imem_evts,
                                mab_EventsL1D: tagged Valid dmem_evts, mab_EventsLL: tagged Valid llmem_evts,
-                               mab_EventsCacheCore: tagged Valid tgc_evts, mab_EventsTransExe: mab_trans_exe,
+                               mab_EventsTGC: tagged Valid tgc_evts, mab_EventsTransExe: mab_trans_exe,
                                mab_AXI4_Slave_Events: tagged Invalid, mab_AXI4_Master_Events: tagged Invalid};
 
      let events = generateHPMVector(ev_struct);
diff --git a/src_Core/CPU/Proc.bsv b/src_Core/CPU/Proc.bsv
index 8355804..243896f 100644
--- a/src_Core/CPU/Proc.bsv
+++ b/src_Core/CPU/Proc.bsv
@@ -179,7 +179,7 @@ module mkProc (Proc_IFC);
    endrule
 
 `ifdef PERFORMANCE_MONITORING
-   Reg#(EventsCacheCore) events_tgc_reg <- mkRegU;
+   Reg#(EventsTGC) events_tgc_reg <- mkRegU;
    rule broadcastPerfEvents;
        for(Integer j = 0; j < valueof(CoreNum); j = j+1) begin
            core[j].events_llc(llc.events);
diff --git a/src_Core/CPU/Proc_IFC.bsv b/src_Core/CPU/Proc_IFC.bsv
index db83ac1..0cc77ee 100644
--- a/src_Core/CPU/Proc_IFC.bsv
+++ b/src_Core/CPU/Proc_IFC.bsv
@@ -130,7 +130,7 @@ interface Proc_IFC;
 `endif
 
 `ifdef PERFORMANCE_MONITORING
-    method Action events_tgc(EventsCacheCore events);
+    method Action events_tgc(EventsTGC events);
 `endif
 
 endinterface
diff --git a/src_Core/Core/CoreW.bsv b/src_Core/Core/CoreW.bsv
index b3bfd94..a77b60b 100644
--- a/src_Core/Core/CoreW.bsv
+++ b/src_Core/Core/CoreW.bsv
@@ -60,6 +60,7 @@ import GetPut_Aux :: *;
 import Routable   :: *;
 import AXI4       :: *;
 import TagControllerAXI :: *;
+import CacheCore  :: *;
 
 // ================================================================
 // Project imports
@@ -178,7 +179,17 @@ module mkCoreW #(Reset dm_power_on_reset)
    mkConnection(proc.master0, tagController.slave, reset_by all_harts_reset);
 `ifdef PERFORMANCE_MONITORING
    rule report_tagController_events;
-      EventsCacheCore evts = tagController.events;
+      EventsCacheCore cache_core_evts = tagController.events;
+      EventsTGC evts = unpack(0);
+      evts.evt_WRITE = zeroExtend(pack(cache_core_evts.evt_WRITE));
+      evts.evt_WRITE_MISS = zeroExtend(pack(cache_core_evts.evt_WRITE_MISS));
+      evts.evt_READ = zeroExtend(pack(cache_core_evts.evt_READ));
+      evts.evt_READ_MISS = zeroExtend(pack(cache_core_evts.evt_READ_MISS));
+      evts.evt_EVICT = zeroExtend(pack(cache_core_evts.evt_EVICT));
+`ifdef USECAP
+      evts.evt_SET_TAG_WRITE = zeroExtend(pack(cache_core_evts.evt_SET_TAG_WRITE));
+      evts.evt_SET_TAG_READ = zeroExtend(pack(cache_core_evts.evt_SET_TAG_READ));
+`endif
       proc.events_tgc(evts);
    endrule
 `endif