diff --git a/src_Core/RISCY_OOO/coherence/src/SelfInvIBank.bsv b/src_Core/RISCY_OOO/coherence/src/SelfInvIBank.bsv
index 785cdca..5986c80 100644
--- a/src_Core/RISCY_OOO/coherence/src/SelfInvIBank.bsv
+++ b/src_Core/RISCY_OOO/coherence/src/SelfInvIBank.bsv
@@ -33,7 +33,7 @@
 // ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 // CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 // SOFTWARE.
-
+`ifdef SELF_INF_CACHE
 `include "ProcConfig.bsv"
 
 import Types::*;
@@ -660,3 +660,4 @@ endmodule
 // unsafe version: all reads read the original reg value, except sendRsToC, which should bypass from pipelineResp
 // all writes are cononicalized. NOTE: writes of sendRsToC should be after pipelineResp
 // we maintain the logical ordering in safe version
+`endif // SELF_INF_CACHE
diff --git a/src_Core/RISCY_OOO/coherence/src/SelfInvIPipe.bsv b/src_Core/RISCY_OOO/coherence/src/SelfInvIPipe.bsv
index 4fffd6d..a767949 100644
--- a/src_Core/RISCY_OOO/coherence/src/SelfInvIPipe.bsv
+++ b/src_Core/RISCY_OOO/coherence/src/SelfInvIPipe.bsv
@@ -34,6 +34,8 @@
 // CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 // SOFTWARE.
 
+`ifdef SELF_INV_CACHE
+
 import Assert::*;
 import ConfigReg::*;
 import Vector::*;
@@ -481,3 +483,4 @@ module mkSelfInvIPipe(
         return !needReconcile;
     endmethod
 endmodule
+`endif // SELF_INV_CACHE
diff --git a/src_Core/RISCY_OOO/coherence/src/SelfInvL1Bank.bsv b/src_Core/RISCY_OOO/coherence/src/SelfInvL1Bank.bsv
index 88060e6..8fc2a8b 100644
--- a/src_Core/RISCY_OOO/coherence/src/SelfInvL1Bank.bsv
+++ b/src_Core/RISCY_OOO/coherence/src/SelfInvL1Bank.bsv
@@ -33,6 +33,7 @@
 // ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 // CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 // SOFTWARE.
+`ifdef SELF_INV_CACHE
 
 `include "ProcConfig.bsv"
 
@@ -1292,3 +1293,4 @@ module mkSelfInvL1Cache#(
         return fold(\+ , d);
     endmethod
 endmodule
+`endif  // SELF_INV_CACHE
diff --git a/src_Core/RISCY_OOO/coherence/src/SelfInvL1Pipe.bsv b/src_Core/RISCY_OOO/coherence/src/SelfInvL1Pipe.bsv
index 45b4b9a..48792ef 100644
--- a/src_Core/RISCY_OOO/coherence/src/SelfInvL1Pipe.bsv
+++ b/src_Core/RISCY_OOO/coherence/src/SelfInvL1Pipe.bsv
@@ -33,6 +33,7 @@
 // ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 // CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 // SOFTWARE.
+`ifdef SELF_INV_CACHE
 
 import Assert::*;
 import ConfigReg::*;
@@ -508,3 +509,4 @@ module mkSelfInvL1Pipe(
         return !needReconcile;
     endmethod
 endmodule
+`endif //  SELF_INV_CACHE
diff --git a/src_Core/RISCY_OOO/coherence/src/SelfInvLLBank.bsv b/src_Core/RISCY_OOO/coherence/src/SelfInvLLBank.bsv
index c2c19df..6c66bda 100644
--- a/src_Core/RISCY_OOO/coherence/src/SelfInvLLBank.bsv
+++ b/src_Core/RISCY_OOO/coherence/src/SelfInvLLBank.bsv
@@ -33,6 +33,7 @@
 // ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 // CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 // SOFTWARE.
+`ifdef SELF_INV_CACHE
 
 import Vector::*;
 import FIFO::*;
@@ -1505,3 +1506,4 @@ endmodule
 //    -- this cRq is different from that in sendRsToC/sendRsToDma
 //    -- XXX this cRq may be the same as that in sendRqToC!!!
 
+`endif // SELF_INV_CACHE
diff --git a/src_Core/RISCY_OOO/coherence/src/SelfInvLLPipe.bsv b/src_Core/RISCY_OOO/coherence/src/SelfInvLLPipe.bsv
index 72f6314..a577aee 100644
--- a/src_Core/RISCY_OOO/coherence/src/SelfInvLLPipe.bsv
+++ b/src_Core/RISCY_OOO/coherence/src/SelfInvLLPipe.bsv
@@ -33,6 +33,7 @@
 // ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 // CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 // SOFTWARE.
+`ifdef SELF_INV_CACHE
 
 import Vector::*;
 import FShow::*;
@@ -381,3 +382,4 @@ module mkSelfInvLLPipe(
         pipe.deqWrite(newCmd, wrRam, updateRep);
     endmethod
 endmodule
+`endif // SELF_INV_CACHE