From dce934500d70bb2ae26064580e81da758166d4ca Mon Sep 17 00:00:00 2001
From: Franz Fuchs <franz.fuchs@cl.cam.ac.uk>
Date: Fri, 11 Jun 2021 10:47:15 +0100
Subject: [PATCH] Added counter mechanism for wild jumps

---
 src_Core/CPU/Core.bsv                         | 12 ++++++++++-
 .../procs/RV64G_OOO/AluExePipeline.bsv        | 20 +++++++++++++++++++
 src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv    |  1 +
 3 files changed, 32 insertions(+), 1 deletion(-)

diff --git a/src_Core/CPU/Core.bsv b/src_Core/CPU/Core.bsv
index e90fd54..9410b8f 100644
--- a/src_Core/CPU/Core.bsv
+++ b/src_Core/CPU/Core.bsv
@@ -1141,7 +1141,17 @@ module mkCore#(CoreId coreId)(Core);
      Vector #(32, Bit #(Report_Width)) tgc_evts_vec = to_large_vector (events_tgc_reg);
      EventsCache llMem = unpack(pack(events_llc_reg) | pack(l2Tlb.events));
      Vector #(16, Bit #(Report_Width)) llc_evts_vec = to_large_vector (llMem);
-     Vector #(16, Bit #(Report_Width)) trans_exe_evts_vec = to_large_vector (renameStage.events);
+     //Vector #(16, Bit #(Report_Width)) trans_exe_evts_vec = to_large_vector (renameStage.events);
+
+     EventsTransExe transExe = renameStage.events;
+     Bit#(Report_Width) wildJumps = 0;
+     for(Integer i = 0; i < valueof(AluExeNum); i = i+1) begin
+          let alu_events = coreFix.aluExeIfc[i].events;
+          wildJumps = wildJumps + alu_events.evt_WILD_JUMP;
+     end
+
+     transExe.evt_EXECUTED_INSTS = executedInsts;
+     Vector #(16, Bit #(Report_Width)) trans_exe_evts_vec = to_large_vector (transExe);
 
      let events = append (null_evt, core_evts_vec);
      events = append (events, imem_evts_vec);
diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv
index b2ebb32..3c1d49a 100755
--- a/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv
+++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv
@@ -205,6 +205,10 @@ interface AluExePipeline;
     interface ReservationStationAlu rsAluIfc;
     interface SpeculationUpdate specUpdate;
     method Data getPerf(ExeStagePerfType t);
+
+`ifdef PERFORMANCE_MONITORING
+    method EventsTransExe events;
+`endif
 endinterface
 
 module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline);
@@ -223,6 +227,10 @@ module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline);
     Integer exeSendBypassPort = 0;
     Integer finishSendBypassPort = 1;
 
+`ifdef PERFORMANCE_MONITORING
+    Reg#(EventsTransExe) events_reg <- mkDReg(unpack(0));
+`endif
+
 `ifdef PERF_COUNT
     // performance counters
     Count#(Data) exeRedirectBrCnt <- mkCount(0);
@@ -285,7 +293,19 @@ module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline);
         let ppc = inIfc.rob_getPredPC(x.tag);
         let orig_inst = inIfc.rob_getOrig_Inst (x.tag);
 
+`ifdef PERFORMANCE_MONITORING
         let res = inIfc.checkTarget(ppc);
+        if(!res) begin
+            let ppc_addr = getAddr(ppc);
+            let pc_addr = getAddr(pc);
+            if((ppc != pc + 2) || (ppc != pc + 4)) begin
+                $display("Not a previous target: pc = ", fshow(pc), ", ppc = ", fshow(ppc));
+                EventsTransExe events = unpack(0);
+                events.evt_WILD_JUMP = 1;
+                events_reg <= events;
+            end
+        end
+`endif
 
         // go to next stage
         regToExeQ.enq(ToSpecFifo {
diff --git a/src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv b/src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv
index 5b8564c..0162789 100755
--- a/src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv
+++ b/src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv
@@ -1123,6 +1123,7 @@ typedef TDiv#(SizeOf#(EventsCoreMem),Report_Width) EventsCoreMemElements;
 
 typedef struct {
    SupCnt evt_RENAMED_INST;
+   SupCnt evt_WILD_JUMP;
 } EventsTransExe deriving (Bits, FShow);
 typedef TDiv#(SizeOf#(EventsTransExe),SizeOf#(SupCnt)) EventsTransExeElements;
 `endif