diff --git a/builds/RV64ACDFIMSU_Toooba_RVFIDII_verilator/Makefile b/builds/RV64ACDFIMSU_Toooba_RVFIDII_verilator/Makefile
index bcc0c54..7b3808c 100644
--- a/builds/RV64ACDFIMSU_Toooba_RVFIDII_verilator/Makefile
+++ b/builds/RV64ACDFIMSU_Toooba_RVFIDII_verilator/Makefile
@@ -33,6 +33,9 @@ MORE_DEFINES = RV64 \
                MULT_SYNTH \
                Near_Mem_Caches \
                FABRIC64 \
+               CheriBusBytes=8 \
+               CheriMasterIDWidth=1 \
+               CheriTransactionIDWidth=5 \
                CAP128 \
                MEM64 \
                RVFI_DII \
diff --git a/builds/RV64ACDFIMSU_Toooba_bluesim/Makefile b/builds/RV64ACDFIMSU_Toooba_bluesim/Makefile
index 714341d..19dadaa 100644
--- a/builds/RV64ACDFIMSU_Toooba_bluesim/Makefile
+++ b/builds/RV64ACDFIMSU_Toooba_bluesim/Makefile
@@ -26,6 +26,9 @@ BSC_COMPILATION_FLAGS += \
 	-D ISA_PRIV_M  -D ISA_PRIV_U  -D ISA_PRIV_S  \
 	-D SV39  \
 	-D ISA_I  -D ISA_M  -D ISA_A  -D ISA_F  -D ISA_D  -D ISA_FD_DIV  -D ISA_C  \
+	-D CheriBusBytes=8 \
+	-D CheriMasterIDWidth=1 \
+	-D CheriTransactionIDWidth=5 \
 	-D SHIFT_BARREL    \
 	-D MULT_SYNTH    \
 	-D Near_Mem_Caches    \
diff --git a/builds/RV64ACDFIMSU_Toooba_verilator/Makefile b/builds/RV64ACDFIMSU_Toooba_verilator/Makefile
index 28013af..ab2c0d7 100644
--- a/builds/RV64ACDFIMSU_Toooba_verilator/Makefile
+++ b/builds/RV64ACDFIMSU_Toooba_verilator/Makefile
@@ -31,6 +31,9 @@ MORE_DEFINES = RV64 \
                MULT_SYNTH \
                Near_Mem_Caches \
                FABRIC64 \
+               CheriBusBytes=8 \
+               CheriMasterIDWidth=1 \
+               CheriTransactionIDWidth=5 \
                CAP128 BLUESIM\
                MEM64 \
                RISCV
diff --git a/src_Core/Core/CoreW.bsv b/src_Core/Core/CoreW.bsv
index 7806f18..cd2a3ba 100644
--- a/src_Core/Core/CoreW.bsv
+++ b/src_Core/Core/CoreW.bsv
@@ -157,8 +157,9 @@ module mkCoreW #(Reset dm_power_on_reset)
 
    // handle cached interface
    // AXI4 tagController
-   let tagController <- mkTagControllerAXI(reset_by hart0_reset); // TODO double check if reseting like this is good enough
-   AXI4_Master#(5, 64, 64, 0, 1, 0, 0, 1) tmp2 <- fromAXI4_Master_Synth(proc.master0, reset_by hart0_reset);
+   TagControllerAXI#(Wd_MId, Wd_Addr, Wd_Data) tagController <- mkTagControllerAXI(reset_by hart0_reset); // TODO double check if reseting like this is good enough
+   AXI4_Master#(Wd_MId, Wd_Addr, Wd_Data, Wd_AW_User, Wd_W_User, Wd_B_User, Wd_AR_User, Wd_R_User)
+                tmp2 <- fromAXI4_Master_Synth(proc.master0, reset_by hart0_reset);
    mkConnection(tmp2, tagController.slave, reset_by hart0_reset);
 
    // PLIC (Platform-Level Interrupt Controller)