From ded8dc72e76c914f6152533b2d14517c71b99b45 Mon Sep 17 00:00:00 2001
From: Jonathan Woodruff <jonwoodruff@gmail.com>
Date: Fri, 27 Mar 2020 15:55:02 +0000
Subject: [PATCH] Do the MTCC->PCC->MEPCC shuffle on trap.

---
 src_Core/CHERI/ScrFile.bsv                       | 16 +++++++++-------
 .../RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv    |  3 ++-
 2 files changed, 11 insertions(+), 8 deletions(-)

diff --git a/src_Core/CHERI/ScrFile.bsv b/src_Core/CHERI/ScrFile.bsv
index d4f1fa9..54e3580 100644
--- a/src_Core/CHERI/ScrFile.bsv
+++ b/src_Core/CHERI/ScrFile.bsv
@@ -56,7 +56,7 @@ import SoC_Map::*;
 // Information returned on traps and mret/sret/uret
 
 typedef struct {
-    Addr      new_pc;
+    Bit#(0) nothing_now;
   } Scr_Trap_Updates
 deriving (Bits, FShow);
 
@@ -90,7 +90,7 @@ interface ScrFile;
     method CapReg warl_xform (SCR csr, CapReg x);
 
     // Methods for handling traps
-    method ActionValue#(Scr_Trap_Updates) trap(Trap t, Addr pc, Addr faultAddr, Bit #(32) orig_inst);
+    method ActionValue#(Scr_Trap_Updates) trap(CapPipe pc, Bit#(2) prv);
     method ActionValue#(Scr_RET_Updates) sret;
     method ActionValue#(Scr_RET_Updates) mret;
 
@@ -136,8 +136,8 @@ module mkScrFile (ScrFile);
     let mkCsrEhr = mkConfigEhr;
 
     // User level SCRs
-    Ehr#(SupSize, CapReg) pcc_reg <- mkCsrEhr(defaultValue);
-    Reg#(CapReg) ddc_reg       <- mkCsrReg(defaultValue);
+    Ehr#(SupSize, CapReg) pcc_reg <- mkConfigEhr(defaultValue);
+    Reg#(CapReg) ddc_reg          <- mkCsrReg(defaultValue);
 
     // User level SCRs with accessSysRegs
     Reg#(CapReg) utcc_reg      <- mkCsrReg(defaultValue);
@@ -155,7 +155,7 @@ module mkScrFile (ScrFile);
     Reg#(CapReg) mtcc_reg      <- mkCsrReg(defaultValue);
     Reg#(CapReg) mtdc_reg      <- mkCsrReg(nullCap);
     Reg#(CapReg) mScratchC_reg <- mkCsrReg(nullCap);
-    Reg#(CapReg) mepcc_reg     <- mkCsrReg(defaultValue);
+    Ehr#(2, CapReg) mepcc_reg  <- mkConfigEhr(defaultValue);
 
     // Function for getting a csr given an index
     function Reg#(CapReg) get_scr(SCR scr);
@@ -177,7 +177,7 @@ module mkScrFile (ScrFile);
             SCR_MTCC:      mtcc_reg;
             SCR_MTDC:      mtdc_reg;
             SCR_MScratchC: mScratchC_reg;
-            SCR_MEPCC:     mepcc_reg;
+            SCR_MEPCC:     mepcc_reg[1];
         endcase);
     endfunction
 
@@ -194,7 +194,9 @@ module mkScrFile (ScrFile);
 
     interface pccWr = map(toPut,pcc_reg);
 
-    method ActionValue#(Scr_Trap_Updates) trap(Trap t, Addr pc, Addr addr, Bit #(32) orig_inst);
+    method ActionValue#(Scr_Trap_Updates) trap(CapPipe pc, Bit#(2) prv);
+        mepcc_reg[0] <= cast(pc);
+        pcc_reg[0] <= mtcc_reg;
         return ?;
     endmethod
 
diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv
index 2384f46..c862106 100644
--- a/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv
+++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv
@@ -726,6 +726,7 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
                                        : 1));
              csrf.dcsr_cause_write (dcsr_cause);
              csrf.dpc_write (trap.pc);
+             scaprfIfc.trap(trap.pc,?);
 
              // Tell fetch stage to wait for redirect
              // Note: rule doCommitTrap_flush may have done this already; redundant call is ok.
@@ -743,7 +744,7 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
        if (! debugger_halt) begin
           // trap handling & redirect
           let trap_updates <- csrf.trap(trap.trap, getAddr(trap.pc), trap.addr, trap.orig_inst);
-          let cap_trap_updates <- scaprf.trap(trap.trap, getAddr(trap.pc), trap.addr, trap.orig_inst);
+          let cap_trap_updates <- scaprf.trap(trap.pc, ?);
           inIfc.redirectPc(trap_updates.new_pc
 `ifdef RVFI_DII
                            , trap.x.diid + 1