Merge branch 'LoadTagsImprove' into CHERI

2022-11-14 13:28:44 +00:00
parent 6335668b81 8ba929438d
commit e120b3427d
9 changed files with 46 additions and 38 deletions
--- a/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv
+++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv
@@ -1518,7 +1518,7 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
        dMem.procReq.req(ProcRq {
            id: zeroExtend(lsqTag),
            addr: addr,
-            toState: multicore ? S : E, // in case of single core, just fetch to E
+            toState: loadTags ? T : (multicore ? S : E), // in case of single core, just fetch to E
            op: Ld,
            byteEn: ?,
            data: ?,