diff --git a/builds/Resources/Include_bluesim.mk b/builds/Resources/Include_bluesim.mk
index fa47617..75f09b5 100644
--- a/builds/Resources/Include_bluesim.mk
+++ b/builds/Resources/Include_bluesim.mk
@@ -15,7 +15,7 @@ build_dir:
 ifeq (,$(filter clean full_clean,$(MAKECMDGOALS)))
 include .depends.mk
 
-.depends.mk: TagTableStructure.bsv StatCounters.bsv | build_dir
+.depends.mk: TagTableStructure.bsv StatCounters.bsv GenerateHPMVector.bsv | build_dir
 	if ! bluetcl -exec makedepend -elab -sim  $(TMP_DIRS)  $(RTL_GEN_DIRS)  $(BSC_COMPILATION_FLAGS)  -p $(BSC_PATH) -o $@ $(TOPFILE); then rm -f $@ && false; fi
 endif
 
diff --git a/src_Core/CPU/Core.bsv b/src_Core/CPU/Core.bsv
index 324a10c..b2ae722 100644
--- a/src_Core/CPU/Core.bsv
+++ b/src_Core/CPU/Core.bsv
@@ -105,6 +105,7 @@ import CHERICC_Fat::*;
 import Bag::*;
 import VnD::*;
 import StatCounters::*;
+import GenerateHPMVector::*;
 
 `ifdef RVFI_DII
 import Toooba_RVFI_DII_Bridge::*;
@@ -1178,12 +1179,17 @@ module mkCore#(CoreId coreId)(Core);
      //Vector #(31, Bit #(Report_Width)) mem_core_evts_vec =  to_large_vector (coreFix.memExeIfc.events);
      //Vector #(31, Bit #(Report_Width)) other_core_evts_vec = to_large_vector (hpm_core_events[0]);
      //Vector #(31, Bit #(Report_Width)) core_evts_vec = unpack(pack(mem_core_evts_vec) | pack(other_core_evts_vec));
+     EventsCore core_evts = unpack(pack(coreFix.memExeIfc.events) | pack(hpm_core_events[0]));
      //EventsCache instMem = unpack(pack(iMem.events) | pack(iTlb.events));
+     EventsL1I imem_evts = unpack(pack(iMem.events) | pack(iTlb.events));
      //Vector #(16, Bit #(Report_Width)) imem_evts_vec = to_large_vector (instMem);
      //EventsCache dataMem = unpack(pack(dMem.events) | pack(dTlb.events));
+     EventsL1D dmem_evts = unpack(pack(dMem.events) | pack(dTlb.events));
      //Vector #(16, Bit #(Report_Width)) dmem_evts_vec = to_large_vector (dataMem);
+     EventsCacheCore tgc_evts = events_tgc_reg;
      //Vector #(32, Bit #(Report_Width)) tgc_evts_vec = to_large_vector (events_tgc_reg);
      //EventsCache llMem = unpack(pack(events_llc_reg) | pack(l2Tlb.events));
+     EventsLL llmem_evts = unpack(pack(events_llc_reg) | pack(l2Tlb.events));
      //Vector #(16, Bit #(Report_Width)) llc_evts_vec = to_large_vector (llMem);
 
 `ifdef CONTRACTS_VERIFY
@@ -1206,7 +1212,11 @@ module mkCore#(CoreId coreId)(Core);
      //events = append (events, dmem_evts_vec);
      //events = append (events, tgc_evts_vec);
      //events = append (events, llc_evts_vec);
-     Vector#(112, Bit#(Report_Width)) events = replicate(0);
+     //Vector#(109, Bit#(Report_Width)) events = replicate(0);
+     let ev_struct = HPMEvents{mab_EventsCore: tagged Valid core_evts, mab_EventsL1I: tagged Valid imem_evts,
+                               mab_EventsL1D: tagged Valid dmem_evts, mab_EventsLL: tagged Valid llmem_evts,
+                               mab_EventsCacheCore: tagged Valid tgc_evts};
+     let events = generateHPMVector(ev_struct);
 `ifdef CONTRACTS_VERIFY
      events = append (events, trans_exe_evts_vec);
 `endif
diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv
index c176f37..efc5bb7 100644
--- a/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv
+++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv
@@ -1311,19 +1311,19 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
 `endif
 `ifdef PERFORMANCE_MONITORING
         EventsCore events = unpack(0);
-        events.evt_BRANCH = brCnt;
-        events.evt_JAL = jmpCnt;
-        events.evt_JALR = jrCnt;
-        events.evt_AUIPC = auipcCnt; // XXX
-        events.evt_LOAD = ldCnt;
-        events.evt_STORE = stCnt;
-        events.evt_LR = lrCnt;
-        events.evt_SC = scCnt;
-        events.evt_AMO = amoCnt;
-        events.evt_SERIAL_SHIFT = shiftCnt;
-        events.evt_INT_MUL_DIV_REM = muldivCnt;
-        events.evt_FP = fpuCnt;
-        events.evt_FENCE = fenceCnt;
+        events.evt_BRANCH = zeroExtend(brCnt);
+        events.evt_JAL = zeroExtend(jmpCnt);
+        events.evt_JALR = zeroExtend(jrCnt);
+        events.evt_AUIPC = zeroExtend(auipcCnt); // XXX
+        events.evt_LOAD = zeroExtend(ldCnt);
+        events.evt_STORE = zeroExtend(stCnt);
+        events.evt_LR = zeroExtend(lrCnt);
+        events.evt_SC = zeroExtend(scCnt);
+        events.evt_AMO = zeroExtend(amoCnt);
+        events.evt_SERIAL_SHIFT = zeroExtend(shiftCnt);
+        events.evt_INT_MUL_DIV_REM = zeroExtend(muldivCnt);
+        events.evt_FP = zeroExtend(fpuCnt);
+        events.evt_FENCE = zeroExtend(fenceCnt);
         events_reg <= events;
 `ifdef CONTRACTS_VERIFY
         inIfc.updateTargets(targets);