diff --git a/libs/BlueStuff b/libs/BlueStuff index 8a36aa9..7e3686c 160000 --- a/libs/BlueStuff +++ b/libs/BlueStuff @@ -1 +1 @@ -Subproject commit 8a36aa9af4d35851053b6f474b959a340e9a72c7 +Subproject commit 7e3686c5dc361a7125e859cf60c609596a1a9b83 diff --git a/libs/TagController b/libs/TagController index 2e2198b..99c43e8 160000 --- a/libs/TagController +++ b/libs/TagController @@ -1 +1 @@ -Subproject commit 2e2198b05f3c7cea61d690e3aa438211d0de9e8d +Subproject commit 99c43e81384741ae11e098a63514a78bd43637e2 diff --git a/libs/WindCoreInterface b/libs/WindCoreInterface index 237f28e..946b4ec 160000 --- a/libs/WindCoreInterface +++ b/libs/WindCoreInterface @@ -1 +1 @@ -Subproject commit 237f28e3e4c3ea51d4b93476246cf8880f660d36 +Subproject commit 946b4ecc178a5a3ccade790765c53dcb18db386e diff --git a/libs/cheri-cap-lib b/libs/cheri-cap-lib index b80c1b3..806b687 160000 --- a/libs/cheri-cap-lib +++ b/libs/cheri-cap-lib @@ -1 +1 @@ -Subproject commit b80c1b3c5977b3aad0cf38125788566458e01493 +Subproject commit 806b687e8a7613f68151032965349b164b34713e diff --git a/src_Core/CPU/MMIO_AXI4_Adapter.bsv b/src_Core/CPU/MMIO_AXI4_Adapter.bsv index 633f61b..694c637 100644 --- a/src_Core/CPU/MMIO_AXI4_Adapter.bsv +++ b/src_Core/CPU/MMIO_AXI4_Adapter.bsv @@ -66,9 +66,9 @@ interface MMIO_AXI4_Adapter_IFC; interface Server #(MMIOCRq, MMIODataPRs) core_side; // Fabric master interface for IO - interface AXI4_Master #(Wd_MId_2x3, Wd_Addr, Wd_Data, - Wd_AW_User, Wd_W_User, Wd_B_User, - Wd_AR_User, Wd_R_User) mmio_master; + interface AXI4_Master #( Wd_CoreW_Bus_MId, Wd_Addr, Wd_Data + , Wd_AW_User, Wd_W_User, Wd_B_User + , Wd_AR_User, Wd_R_User) mmio_master; endinterface // ================================================================ @@ -127,7 +127,7 @@ module mkMMIO_AXI4_Adapter (MMIO_AXI4_Adapter_IFC); // necessary; the AXI4 fabric should return a DECERR for illegal // addrs; but not all AXI4 fabrics do the right thing. if (soc_map.m_is_IO_addr (req.addr, False)) begin - let mem_req_rd_addr = AXI4_ARFlit {arid: fabric_2x3_default_mid, + let mem_req_rd_addr = AXI4_ARFlit {arid: fabric_corew_bus_default_mid, araddr: req.addr, arlen: (burst) ? 1:0, // burst len = arlen+1 arsize: size, @@ -220,8 +220,8 @@ module mkMMIO_AXI4_Adapter (MMIO_AXI4_Adapter_IFC); // on first flit... // ================ if (first) begin - AXI4_AWFlit #(Wd_MId_2x3, Wd_Addr, Wd_AW_User) - mem_req_wr_addr = AXI4_AWFlit {awid: fabric_2x3_default_mid, + AXI4_AWFlit #(Wd_CoreW_Bus_MId, Wd_Addr, Wd_AW_User) + mem_req_wr_addr = AXI4_AWFlit {awid: fabric_corew_bus_default_mid, awaddr: req.addr, awlen: (burst) ? 1:0, // burst len = awlen+1 awsize: size, diff --git a/src_Core/CPU/Proc_IFC.bsv b/src_Core/CPU/Proc_IFC.bsv index 2aaedd0..4b2697f 100644 --- a/src_Core/CPU/Proc_IFC.bsv +++ b/src_Core/CPU/Proc_IFC.bsv @@ -72,9 +72,9 @@ interface Proc_IFC; Wd_AR_User, Wd_R_User) master0; // Fabric master interface for IO (from MMIOPlatform) - interface AXI4_Master #(Wd_MId_2x3, Wd_Addr, Wd_Data, - Wd_AW_User, Wd_W_User, Wd_B_User, - Wd_AR_User, Wd_R_User) master1; + interface AXI4_Master #( Wd_CoreW_Bus_MId, Wd_Addr, Wd_Data + , Wd_AW_User, Wd_W_User, Wd_B_User + , Wd_AR_User, Wd_R_User) master1; // ---------------- // External interrupts @@ -99,9 +99,9 @@ interface Proc_IFC; // ---------------- // Coherent port into LLC (used by Debug Module, DMA engines, ... to read/write memory) - interface AXI4_Slave #(Wd_SId_2x3, Wd_Addr, Wd_Data, - Wd_AW_User, Wd_W_User, Wd_B_User, - Wd_AR_User, Wd_R_User) debug_module_mem_server; + interface AXI4_Slave #( Wd_CoreW_Bus_SId, Wd_Addr, Wd_Data + , Wd_AW_User, Wd_W_User, Wd_B_User + , Wd_AR_User, Wd_R_User) debug_module_mem_server; `ifdef RVFI_DII interface Toooba_RVFI_DII_Server rvfi_dii_server; diff --git a/src_Core/Core/CoreW.bsv b/src_Core/Core/CoreW.bsv index 00627f1..5431624 100644 --- a/src_Core/Core/CoreW.bsv +++ b/src_Core/Core/CoreW.bsv @@ -115,11 +115,11 @@ import DM_CPU_Req_Rsp ::*; typedef WindCoreMid #( // AXI lite subordinate control port parameters 21, 32, 0, 0, 0, 0, 0 // AXI manager 0 port parameters - , TAdd#(Wd_MId,1), Wd_Addr, Wd_Data, 0, 0, 0, 0, 0 + , TAdd #(Wd_MId, 1), Wd_Addr, Wd_Data, 0, 0, 0, 0, 0 // AXI manager 1 port parameters - , TAdd#(Wd_MId,1), Wd_Addr, Wd_Data, 0, 0, 0, 0, 0 + , TAdd #(Wd_MId, 1), Wd_Addr, Wd_Data, 0, 0, 0, 0, 0 // AXI subordinate 0 port parameters - , 0, 0, 0, 0, 0, 0, 0, 0 + , 4, 32, 128, 0, 0, 0, 0, 0 // Number of interrupt lines , t_n_irq) CoreW_IFC #(numeric type t_n_irq); @@ -200,14 +200,16 @@ module mkCoreW_reset #(Reset porReset) Proc_IFC proc <- mkProc (reset_by all_harts_reset); // handle uncached interface - let proc_uncached = prepend_AXI4_Master_id (0, zero_AXI4_Master_user (proc.master1)); + let proc_uncached = + prepend_AXI4_Master_id (0, zero_AXI4_Master_user (proc.master1)); // Bridge for uncached expernal bus transactions. let uncached_mem_shim <- mkAXI4ShimFF(reset_by all_harts_reset); // handle cached interface // AXI4 tagController - TagControllerAXI#(Wd_MId, Wd_Addr, Wd_Data) tagController <- mkTagControllerAXI(reset_by all_harts_reset); // TODO double check if reseting like this is good enough - mkConnection(proc.master0, tagController.slave, reset_by all_harts_reset); + TagControllerAXI #(Wd_MId, Wd_Addr, Wd_Data) + tagController <- mkTagControllerAXI (reset_by all_harts_reset); // TODO double check if reseting like this is good enough + mkConnection (proc.master0, tagController.slave, reset_by all_harts_reset); `ifdef PERFORMANCE_MONITORING rule report_tagController_events; EventsCacheCore cache_core_evts = tagController.events; @@ -412,30 +414,44 @@ module mkCoreW_reset #(Reset porReset) // ================================================================ - // Connect the local 2x3 fabric + // new internal AXI4 manager from interace subordinate port + AXI4_Shim #(4, 32, Wd_Data, 0, 0, 0, 0, 0) + subShim <- mkAXI4Shim; + AXI4_Slave #( 4, 32, 128, 0, 0, 0, 0, 0) + outerSubIfc <- toWider_AXI4_Slave (subShim.slave); + AXI4_Master #( Wd_CoreW_Bus_MId, Wd_Addr, Wd_Data + , Wd_AW_User, Wd_W_User, Wd_B_User + , Wd_AR_User, Wd_R_User) innerSubIfc = + prepend_AXI4_Master_addr (0 , zero_AXI4_Master_user (subShim.master)); - // Masters on the local 2x3 fabric - Vector#(Num_Masters_2x3, AXI4_Master #(Wd_MId_2x3, Wd_Addr, Wd_Data, - Wd_AW_User, Wd_W_User, Wd_B_User, - Wd_AR_User, Wd_R_User)) - master_vector = newVector; + // ================================================================ + // Connect the local bus + + // Masters on the local bus + Vector #( CoreW_Bus_Num_Masters + , AXI4_Master #( Wd_CoreW_Bus_MId, Wd_Addr, Wd_Data + , Wd_AW_User, Wd_W_User, Wd_B_User + , Wd_AR_User, Wd_R_User)) + master_vector = newVector; //let master_vector = newVector; master_vector[cpu_uncached_master_num] = proc_uncached; master_vector[debug_module_sba_master_num] = dm_master_local; + master_vector[sub_ifc_master_num] = innerSubIfc; - // Slaves on the local 2x3 fabric + // Slaves on the local bus // default slave is forwarded out directly to the Core interface - Vector#(Num_Slaves_2x3, AXI4_Slave #(Wd_SId_2x3, Wd_Addr, Wd_Data, - Wd_AW_User, Wd_W_User, Wd_B_User, - Wd_AR_User, Wd_R_User)) - slave_vector = newVector; + Vector #( CoreW_Bus_Num_Slaves + , AXI4_Slave #( Wd_CoreW_Bus_SId, Wd_Addr, Wd_Data + , Wd_AW_User, Wd_W_User, Wd_B_User + , Wd_AR_User, Wd_R_User)) + slave_vector = newVector; //let slave_vector = newVector; slave_vector[default_slave_num] = uncached_mem_shim.slave; slave_vector[llc_slave_num] = proc.debug_module_mem_server; slave_vector[plic_slave_num] = zero_AXI4_Slave_user (plic.axi4_slave); - function Vector#(Num_Slaves_2x3, Bool) route_2x3 (Bit#(Wd_Addr) addr); - Vector#(Num_Slaves_2x3, Bool) res = replicate(False); + function Vector #(CoreW_Bus_Num_Slaves, Bool) route (Bit #(Wd_Addr) addr); + Vector #(CoreW_Bus_Num_Slaves, Bool) res = replicate(False); if (inRange(soc_map.m_mem0_controller_addr_range, addr)) res[llc_slave_num] = True; else if (inRange(soc_map.m_plic_addr_range, addr)) @@ -447,7 +463,7 @@ module mkCoreW_reset #(Reset porReset) return res; endfunction - mkAXI4Bus (route_2x3, master_vector, slave_vector, reset_by all_harts_reset); + mkAXI4Bus (route, master_vector, slave_vector, reset_by all_harts_reset); // ================================================================ // Connect external interrupt lines from PLIC to CPU @@ -568,10 +584,10 @@ module mkCoreW_reset #(Reset porReset) // Cached master to Fabric master interface interface manager_0 = tagController.master; // Uncached master to Fabric master interface - interface manager_1 = - extendIDFields (zeroMasterUserFields (uncached_mem_shim.master), 0); + interface manager_1 = prepend_AXI4_Master_id + (0, zero_AXI4_Master_user (uncached_mem_shim.master)); // TODO: - interface subordinate_0 = culDeSac; + interface subordinate_0 = outerSubIfc; endinterface; /* @@ -596,21 +612,22 @@ module mkCoreW_reset #(Reset porReset) endmodule: mkCoreW_reset // ================================================================ -// 2x3 Fabric for this Core +// internal bus for this Core // Masters: CPU DMem, Debug Module System Bus Access, External access // ---------------- // Fabric port numbers for masters -Master_Num_2x3 cpu_uncached_master_num = 0; -Master_Num_2x3 debug_module_sba_master_num = 1; +CoreW_Bus_Master_Num cpu_uncached_master_num = 0; +CoreW_Bus_Master_Num debug_module_sba_master_num = 1; +CoreW_Bus_Master_Num sub_ifc_master_num = 2; // ---------------- // Fabric port numbers for slaves -Slave_Num_2x3 default_slave_num = 0; // for I/O, uncached memory, etc. -Slave_Num_2x3 plic_slave_num = 1; // PLIC mem-mapped registers -Slave_Num_2x3 llc_slave_num = 2; // Normal cached memory (connects to coherent Last-Level Cache) +CoreW_Bus_Slave_Num default_slave_num = 0; // for I/O, uncached memory, etc. +CoreW_Bus_Slave_Num plic_slave_num = 1; // PLIC mem-mapped registers +CoreW_Bus_Slave_Num llc_slave_num = 2; // Normal cached memory (connects to coherent Last-Level Cache) // ================================================================ diff --git a/src_Core/Core/Fabric_Defs.bsv b/src_Core/Core/Fabric_Defs.bsv index c9cdb1a..9443091 100644 --- a/src_Core/Core/Fabric_Defs.bsv +++ b/src_Core/Core/Fabric_Defs.bsv @@ -35,17 +35,17 @@ import ISA_Decls_CHERI :: *; // ================================================================ // Core local Fabric parameters -typedef 2 Num_Masters_2x3; -typedef 3 Num_Slaves_2x3; +typedef 3 CoreW_Bus_Num_Masters; +typedef 3 CoreW_Bus_Num_Slaves; -typedef Bit#(TLog #(Num_Masters_2x3)) Master_Num_2x3; -typedef Bit#(TLog #(Num_Slaves_2x3)) Slave_Num_2x3; +typedef Bit#(TLog #(CoreW_Bus_Num_Masters)) CoreW_Bus_Master_Num; +typedef Bit#(TLog #(CoreW_Bus_Num_Slaves)) CoreW_Bus_Slave_Num; // ---------------- // Width of fabric 'Id' buses -typedef 4 Wd_MId_2x3; -typedef TAdd#(Wd_MId_2x3, TLog#(Num_Masters_2x3)) Wd_SId_2x3; -typedef Wd_SId_2x3 Wd_MId; +typedef 4 Wd_CoreW_Bus_MId; +typedef TAdd#(Wd_CoreW_Bus_MId, TLog#(CoreW_Bus_Num_Masters)) Wd_CoreW_Bus_SId; +typedef Wd_CoreW_Bus_SId Wd_MId; // ---------------- // Width of fabric 'addr' buses @@ -104,7 +104,7 @@ Integer zlsbs_aligned_fabric_addr = valueOf (ZLSBs_Aligned_Fabric_Addr); // ================================================================ // AXI4 defaults for this project -Bit#(Wd_MId_2x3) fabric_2x3_default_mid = 0; +Bit#(Wd_CoreW_Bus_MId) fabric_corew_bus_default_mid = 0; Bit#(Wd_MId) fabric_default_mid = 0; AXI4_Burst fabric_default_burst = INCR; AXI4_Lock fabric_default_lock = NORMAL; diff --git a/src_Core/Debug_Module/DM_System_Bus.bsv b/src_Core/Debug_Module/DM_System_Bus.bsv index 08417d2..be7a24a 100644 --- a/src_Core/Debug_Module/DM_System_Bus.bsv +++ b/src_Core/Debug_Module/DM_System_Bus.bsv @@ -54,9 +54,9 @@ interface DM_System_Bus_IFC; // ---------------- // Facing System - interface AXI4_Master #(Wd_MId_2x3, Wd_Addr, Wd_Data_Periph, - Wd_AW_User, Wd_W_User, Wd_B_User, - Wd_AR_User, Wd_R_User) master; + interface AXI4_Master #( Wd_CoreW_Bus_MId, Wd_Addr, Wd_Data_Periph + , Wd_AW_User, Wd_W_User, Wd_B_User + , Wd_AR_User, Wd_R_User) master; endinterface // ================================================================ @@ -283,7 +283,7 @@ module mkDM_System_Bus (DM_System_Bus_IFC); function Action fa_fabric_send_read_req (Bit #(64) addr64); action Fabric_Addr fabric_addr = truncate (addr64); - let rda = AXI4_ARFlit {arid: fabric_2x3_default_mid, + let rda = AXI4_ARFlit {arid: fabric_corew_bus_default_mid, araddr: fabric_addr, arlen: 0, // burst len = arlen+1 arsize: fn_DM_sbaccess_to_AXI4_Size (rg_sbcs_sbaccess), @@ -318,13 +318,13 @@ module mkDM_System_Bus (DM_System_Bus_IFC); .fabric_data, .fabric_strb, .fabric_size} = fn_to_fabric_write_fields (rg_sbcs_sbaccess, sbaddress, data64); - + // fabric_addr is always fabric-data-width aligned // fabric_data is properly lane-adjusted // fabric_strb identifies the lanes to be written // awsize is always the fabric width - let wra = AXI4_AWFlit {awid: fabric_2x3_default_mid, + let wra = AXI4_AWFlit {awid: fabric_corew_bus_default_mid, awaddr: fabric_addr, awlen: 0, // burst len = awlen+1 awsize: fabric_size, diff --git a/src_Core/Debug_Module/Debug_Module.bsv b/src_Core/Debug_Module/Debug_Module.bsv index 9c17d71..90f1981 100644 --- a/src_Core/Debug_Module/Debug_Module.bsv +++ b/src_Core/Debug_Module/Debug_Module.bsv @@ -136,9 +136,9 @@ interface Debug_Module_IFC; interface Client #(Bool, Bool) ndm_reset_client; // Read/Write RISC-V memory - interface AXI4_Master #(Wd_MId_2x3, Wd_Addr, Wd_Data_Periph, - Wd_AW_User, Wd_W_User, Wd_B_User, - Wd_AR_User, Wd_R_User) master; + interface AXI4_Master #( Wd_CoreW_Bus_MId, Wd_Addr, Wd_Data_Periph + , Wd_AW_User, Wd_W_User, Wd_B_User + , Wd_AR_User, Wd_R_User) master; endinterface // ================================================================ diff --git a/src_Core/PLIC/PLIC.bsv b/src_Core/PLIC/PLIC.bsv index 6dc3da9..95670d9 100644 --- a/src_Core/PLIC/PLIC.bsv +++ b/src_Core/PLIC/PLIC.bsv @@ -98,8 +98,8 @@ interface PLIC_IFC #(numeric type t_n_external_sources, method Action set_addr_map (Bit #(64) addr_base, Bit #(64) addr_lim); // Memory-mapped access - interface AXI4_Slave #( Wd_SId_2x3, Wd_Addr, Wd_Data, 0, 0, 0, 0, 0) - axi4_slave; + interface AXI4_Slave #( Wd_CoreW_Bus_SId, Wd_Addr, Wd_Data + , 0, 0, 0, 0, 0) axi4_slave; // sources interface Vector #(t_n_external_sources, PLIC_Source_IFC) v_sources; diff --git a/src_Core/RISCY_OOO/procs/lib/LLCDmaConnect.bsv b/src_Core/RISCY_OOO/procs/lib/LLCDmaConnect.bsv index 916c602..0c9d13f 100644 --- a/src_Core/RISCY_OOO/procs/lib/LLCDmaConnect.bsv +++ b/src_Core/RISCY_OOO/procs/lib/LLCDmaConnect.bsv @@ -127,15 +127,14 @@ endfunction // ================================================================ -module mkLLCDmaConnect #( - DmaServer#(LLCDmaReqId) llc, - // MemLoaderMemClient memLoader, // REPLACED BY AXI4_Slave_interface - Vector#(CoreNum, TlbMemClient) tlb -)(AXI4_Slave #(Wd_SId_2x3, Wd_Addr, Wd_Data, - Wd_AW_User, Wd_W_User, Wd_B_User, - Wd_AR_User, Wd_R_User)) provisos ( - Alias#(dmaRqT, DmaRq#(LLCDmaReqId)) -); +module mkLLCDmaConnect #( DmaServer#(LLCDmaReqId) llc + // REPLACED BY AXI4_Slave_interface + //, MemLoaderMemClient memLoader + , Vector#(CoreNum, TlbMemClient) tlb ) + (AXI4_Slave #( Wd_CoreW_Bus_SId, Wd_Addr, Wd_Data + , Wd_AW_User, Wd_W_User, Wd_B_User + , Wd_AR_User, Wd_R_User)) + provisos (Alias #(dmaRqT, DmaRq #(LLCDmaReqId))); Bool verbose = False; Integer verbosity = 0;