From e579f895dcb9f7218e245db1f4b83d975993cc98 Mon Sep 17 00:00:00 2001 From: Jessica Clarke Date: Wed, 3 Jun 2020 18:14:58 +0100 Subject: [PATCH] CPU_Decode_C.bsv: Sync from Flute This incorporates the fix made to Piccolo and Flute to not trap on C.FLWSP/C.FLDSP when rd == 0; unlike the compressed stack pointer relative integer loads/stores, these are legal, since f0 is a real FPR rather than a constant zero. --- src_Core/CPU/CPU_Decode_C.bsv | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/src_Core/CPU/CPU_Decode_C.bsv b/src_Core/CPU/CPU_Decode_C.bsv index 00ddb8e..99168bf 100644 --- a/src_Core/CPU/CPU_Decode_C.bsv +++ b/src_Core/CPU/CPU_Decode_C.bsv @@ -239,10 +239,9 @@ function Tuple2 #(Bool, Instr) fv_decode_C_FLWSP (MISA misa, Bit #(2) xl, Inst Bit #(8) offset = { imm_at_6_2 [1:0], imm_at_12, imm_at_6_2 [4:2], 2'b0 }; Bool is_legal = ((misa.c == 1'b1) - && (op == opcode_C2) - && (rd != 0) - && (funct3 == funct3_C_FLWSP) - && (misa.f == 1'b1)); + && (op == opcode_C2) + && (funct3 == funct3_C_FLWSP) + && (misa.f == 1'b1)); RegName rs1 = reg_sp; let instr = mkInstr_I_type (zeroExtend (offset), rs1, f3_FLW, rd, op_LOAD_FP); @@ -261,12 +260,11 @@ function Tuple2 #(Bool, Instr) fv_decode_C_FLDSP (MISA misa, Bit #(2) xl, Inst Bit #(9) offset = { imm_at_6_2 [2:0], imm_at_12, imm_at_6_2 [4:3], 3'b0 }; Bool is_legal = ((misa.c == 1'b1) - && (op == opcode_C2) - && (rd != 0) - && (funct3 == funct3_C_FLDSP) - && (misa.d == 1'b1) - && ( (xl == misa_mxl_64) - || (xl == misa_mxl_128))); + && (op == opcode_C2) + && (funct3 == funct3_C_FLDSP) + && (misa.d == 1'b1) + && ( (xl == misa_mxl_64) + || (xl == misa_mxl_128))); RegName rs1 = reg_sp; let instr = mkInstr_I_type (zeroExtend (offset), rs1, f3_FLD, rd, op_LOAD_FP);