From e600fd7d38c238a7d0ff468b2df86e790f8ebb29 Mon Sep 17 00:00:00 2001 From: Jonathan Woodruff Date: Sat, 8 Jan 2022 10:15:22 +0000 Subject: [PATCH] Delay BTB update by a cycle for timing. This should not be a primary degredation of performance since the redirection gets on seperately from this update which will only affect future predictions. --- src_Core/RISCY_OOO/procs/lib/Btb.bsv | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src_Core/RISCY_OOO/procs/lib/Btb.bsv b/src_Core/RISCY_OOO/procs/lib/Btb.bsv index 335d1ab..a1d9059 100644 --- a/src_Core/RISCY_OOO/procs/lib/Btb.bsv +++ b/src_Core/RISCY_OOO/procs/lib/Btb.bsv @@ -38,6 +38,7 @@ import Types::*; import ProcTypes::*; import ConfigReg::*; +import DReg::*; import Map::*; import Vector::*; import CHERICC_Fat::*; @@ -100,7 +101,7 @@ module mkBtbCore(NextAddrPred#(hashSz)) fullRecords <- replicateM(mkMapLossyBRAM); Vector#(SupSizeX2, MapSplit#(HashedTag#(hashSz), BtbIndex, VnD#(CompressedTarget), BtbAssociativity)) compressedRecords <- replicateM(mkMapLossyBRAM); - RWire#(BtbUpdate) updateEn <- mkRWire; + Reg#(Maybe#(BtbUpdate)) updateEn <- mkDReg(Invalid); function BtbAddr getBtbAddr(CapMem pc) = unpack(truncateLSB(getAddr(pc))); function BtbBank getBank(CapMem pc) = getBtbAddr(pc).bank; @@ -111,7 +112,7 @@ module mkBtbCore(NextAddrPred#(hashSz)) // no flush, accept update (* fire_when_enabled, no_implicit_conditions *) - rule canonUpdate(updateEn.wget matches tagged Valid .upd); + rule canonUpdate(updateEn matches tagged Valid .upd); let pc = upd.pc; let nextPc = upd.nextPc; let taken = upd.taken; @@ -149,7 +150,7 @@ module mkBtbCore(NextAddrPred#(hashSz)) endmethod method Action update(CapMem pc, CapMem nextPc, Bool taken); - updateEn.wset(BtbUpdate {pc: pc, nextPc: nextPc, taken: taken}); + updateEn <= Valid(BtbUpdate {pc: pc, nextPc: nextPc, taken: taken}); endmethod `ifdef SECURITY