diff --git a/builds/Resources/Include_Common.mk b/builds/Resources/Include_Common.mk
index 1a51f0e..9bc23e0 100644
--- a/builds/Resources/Include_Common.mk
+++ b/builds/Resources/Include_Common.mk
@@ -88,6 +88,7 @@ BSC_COMPILATION_FLAGS += \
 	-D MEM64 \
 	-D RISCV \
 	-D PERFORMANCE_MONITORING \
+	-D RAS_HIT_TRACING \
 	-D TSO_MM \
 	-keep-fires -aggressive-conditions -no-warn-action-shadowing -check-assert \
 	-suppress-warnings G0020 -steps-max-intervals 10000000   \
diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv
index 73b8aa1..0bd1678 100755
--- a/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv
+++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv
@@ -362,6 +362,21 @@ module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline);
         // execution
         ExecResult exec_result = basicExec(x.dInst, x.rVal1, x.rVal2, cast(x.pc), cast(x.ppc), x.orig_inst);
 
+`ifdef RAS_HIT_TRACING
+        function Bool linkedR(Bit#(5) r);
+           Bool res = False;
+           if ((r == 1 || r == 5)) begin
+              res = True;
+           end
+           return res;
+        endfunction
+        if (linkedR(x.orig_inst[19:15]) && (x.orig_inst[19:15] != x.orig_inst[11:7])) begin
+            case (x.dInst.iType)
+                Jr, CJALR: $display("Jr/CJALR ra: PC: %x Mispredict: %x , %x vs %x src1: %d", getAddr(x.pc), exec_result.controlFlow.mispredict, getAddr(exec_result.controlFlow.nextPc), getAddr(x.ppc), x.orig_inst[19:15]);
+            endcase
+        end
+`endif
+
         if (verbosity > 0) begin
            $display ("AluExePipeline.doExeAlu: regToExe    = ", fshow (regToExe));
            $display ("AluExePipeline.doExeAlu: exec_result = ", fshow (exec_result));