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Bugfix in MMIOPlatform.bsv for instruction-fetch from IO addrs

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Detail: an "instruction-fetch" response from mmioplatform to core
should be an "InstFetch". This was true for successful fabric reads,
but on error responses it was wrongly returned as a "DataAccess"
response.  This was causing a deadlock.
This commit is contained in:
rsnikhil
2019-04-17 15:29:10 -04:00
parent e9c04c7050
commit e7fbf32b38
177 changed files with 103548 additions and 94531 deletions
Download Patch File Download Diff File Expand all files Collapse all files

29
src_Core/CPU/MMIOPlatform.bsv
View File

@@ -397,8 +397,8 @@ module mkMMIOPlatform #(Vector#(CoreNum, MMIOCoreToPlatform) cores,
// process valid req
state <= ProcessReq;
if(verbosity > 0) begin
$display("[Platform - SelectReq] new req, core %d, req ",
i, fshow(req), ", type ", fshow(newReq));
$display("[Platform - SelectReq] core %d, req ", i, fshow(req));
$display(" req type ", fshow(newReq));
end
end
end
@@ -983,13 +983,15 @@ module mkMMIOPlatform #(Vector#(CoreNum, MMIOCoreToPlatform) cores,
&&& (state == ProcessReq)
&&& isInstFetch);
// Note: addr may not be FabricData-aligned; result will be Data that contains addr
// TODO: currently assumes superscalarity fits in fabric width
Addr addr1 = { addr [63:3], 3'b_000 };
let req = MMIOCRq {addr:addr1, func: tagged Ld, byteEn: ?, data: ? };
mmio_fabric_adapter_core_side.request.put (req);
state <= WaitResp;
if (verbosity > 0) begin
$display ("MMIOPlatform.rl_mmio_to_fabric_ifetch_req: addr 0x%0h", addr);
$display ("MMIOPlatform.rl_mmio_to_fabric_ifetch_req: addr 0x%0h fetchingWay %0d",
addr, fetchingWay);
$display (" ", fshow (req));
end
endrule
@@ -1000,11 +1002,24 @@ module mkMMIOPlatform #(Vector#(CoreNum, MMIOCoreToPlatform) cores,
MMIODataPRs dprs <- mmio_fabric_adapter_core_side.response.get;
if (! dprs.valid) begin
// Access fault
let prs = tagged DataAccess dprs;
cores[reqCore].pRs.enq (prs);
state <= SelectReq;
Vector #(SupSize, Maybe #(Instruction)) resp = replicate (Invalid);
for(Integer i = 0; i < valueof (SupSize); i = i+1) begin
if (fromInteger (i) < fetchingWay)
resp [i] = Valid (fetchedInsts [i]);
else if (fromInteger (i) == fetchingWay)
resp [i] = tagged Invalid;
end
cores[reqCore].pRs.enq (tagged InstFetch (resp));
state <= SelectReq;
if (verbosity > 0) begin
$display ("MMIOPlatform.rl_mmio_from_fabric_ifetch_rsp: access fault; final resp to core:");
$display (" ", fshow (resp));
end
end
else begin
// No access fault
let data = dprs.data;
SupWaySel maxWay = 0;
@@ -1061,8 +1076,6 @@ module mkMMIOPlatform #(Vector#(CoreNum, MMIOCoreToPlatform) cores,
toHostAddr <= getDataAlignedAddr(toHost);
fromHostAddr <= getDataAlignedAddr(fromHost);
state <= SelectReq;
$display ("MMIOPlatform.start: tohostAddr = 0x%0h, fromhostAddr = %0h",
toHost, fromHost);
endmethod
method ActionValue#(Data) to_host;

4
src_Core/RISCY_OOO/procs/lib/MMIOAddrs.bsv
View File

@@ -47,7 +47,7 @@ DataAlignedAddr bootRomBaseAddr = getDataAlignedAddr(soc_map_struct.boot_rom_a
DataAlignedAddr msipBaseAddr = getDataAlignedAddr(soc_map_struct.near_mem_io_addr_base + 64'h_0000_0000);
DataAlignedAddr mtimecmpBaseAddr = getDataAlignedAddr(soc_map_struct.near_mem_io_addr_base + 64'h_0000_4000);
DataAlignedAddr mtimeBaseAddr = getDataAlignedAddr(soc_map_struct.near_mem_io_addr_base + 64'h_0000_bff8);
DataAlignedAddr mainMemBaseAddr = getDataAlignedAddr(soc_map_struct.mem0_controller_addr_base);
DataAlignedAddr mainMemBaseAddr = getDataAlignedAddr(soc_map_struct.main_mem_addr_base);
// XXX Each msip reg is 32-bit, while mtime and each mtimecmp are 64-bit. We
// assume Data is 64-bit. We hard code this relation in all MMIO logic.
@@ -61,7 +61,7 @@ DataAlignedAddr mainMemBaseAddr = getDataAlignedAddr(soc_map_struct.mem0_contr
DataAlignedAddr bootRomBoundAddr = bootRomBaseAddr +
fromInteger(valueof(TExp#(LgBootRomSzData)));
DataAlignedAddr mainMemBoundAddr = (mainMemBaseAddr +
getDataAlignedAddr(soc_map_struct.mem0_controller_addr_size));
getDataAlignedAddr(soc_map_struct.main_mem_addr_size));
DataAlignedAddr msipBoundAddr = msipBaseAddr +
fromInteger(valueof(TDiv#(CoreNum, 2)));
DataAlignedAddr mtimecmpBoundAddr = mtimecmpBaseAddr +

14
src_Core/RISCY_OOO/procs/lib/MMIOInst.bsv
View File

@@ -77,15 +77,13 @@ module mkMMIOInst(MMIOInst);
method InstFetchTarget getFetchTarget(Addr phyPc);
let addr = getDataAlignedAddr(phyPc);
if (soc_map.m_is_IO_addr (phyPc)) begin
return IODevice;
end
else if(addr >= mainMemBaseAddr && (addr < mainMemBoundAddr) &&
addr != toHostAddr && addr != fromHostAddr) begin
return MainMem;
end
if(addr >= mainMemBaseAddr && (addr < mainMemBoundAddr) &&
addr != toHostAddr && addr != fromHostAddr)
begin
return MainMem;
end
else begin
return Fault;
return IODevice;
end
endmethod