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Bugfix in MMIOPlatform.bsv for instruction-fetch from IO addrs

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Detail: an "instruction-fetch" response from mmioplatform to core
should be an "InstFetch". This was true for successful fabric reads,
but on error responses it was wrongly returned as a "DataAccess"
response.  This was causing a deadlock.
This commit is contained in:
rsnikhil
2019-04-17 15:29:10 -04:00
parent e9c04c7050
commit e7fbf32b38
177 changed files with 103548 additions and 94531 deletions
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74
src_SSITH_P3/Verilog_RTL/mkSplitTransCache.v
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@@ -1,5 +1,5 @@
//
// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21)
// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17)
//
//
//
@@ -945,8 +945,8 @@ module mkSplitTransCache(CLK,
MUX_caches_0_updRepIdx_lat_1$wset_1__VAL_2,
MUX_caches_1_updRepIdx_lat_1$wset_1__VAL_1,
MUX_caches_1_updRepIdx_lat_1$wset_1__VAL_2;
wire MUX_caches_0_updRepIdx_dummy_1_0$wset_1__VAL_2,
MUX_caches_0_updRepIdx_lat_1$wset_1__SEL_1,
wire MUX_caches_0_updRepIdx_dummy2_1$write_1__SEL_1,
MUX_caches_0_updRepIdx_dummy_1_0$wset_1__VAL_1,
MUX_caches_0_validVec_0$write_1__SEL_1,
MUX_caches_0_validVec_1$write_1__SEL_1,
MUX_caches_0_validVec_10$write_1__SEL_1,
@@ -971,8 +971,8 @@ module mkSplitTransCache(CLK,
MUX_caches_0_validVec_7$write_1__SEL_1,
MUX_caches_0_validVec_8$write_1__SEL_1,
MUX_caches_0_validVec_9$write_1__SEL_1,
MUX_caches_1_updRepIdx_dummy_1_0$wset_1__VAL_2,
MUX_caches_1_updRepIdx_lat_1$wset_1__SEL_1,
MUX_caches_1_updRepIdx_dummy2_1$write_1__SEL_1,
MUX_caches_1_updRepIdx_dummy_1_0$wset_1__VAL_1,
MUX_caches_1_validVec_0$write_1__SEL_1,
MUX_caches_1_validVec_1$write_1__SEL_1,
MUX_caches_1_validVec_10$write_1__SEL_1,
@@ -1621,7 +1621,9 @@ module mkSplitTransCache(CLK,
assign WILL_FIRE_RL_respQ_full_canon = 1'd1 ;
// inputs to muxes for submodule ports
assign MUX_caches_0_updRepIdx_lat_1$wset_1__SEL_1 = EN_addEntry && _dfoo7 ;
assign MUX_caches_0_updRepIdx_dummy2_1$write_1__SEL_1 =
EN_req &&
IF_NOT_caches_0_validVec_0_14_15_OR_NOT_req_vp_ETC___d347 ;
assign MUX_caches_0_validVec_0$write_1__SEL_1 =
EN_addEntry && v__h56242 == 5'd0 &&
IF_NOT_caches_0_validVec_0_14_15_OR_NOT_addEnt_ETC___d1148 &&
@@ -1718,7 +1720,9 @@ module mkSplitTransCache(CLK,
EN_addEntry && v__h56242 == 5'd9 &&
IF_NOT_caches_0_validVec_0_14_15_OR_NOT_addEnt_ETC___d1148 &&
x__h45838 == 2'd0 ;
assign MUX_caches_1_updRepIdx_lat_1$wset_1__SEL_1 = EN_addEntry && _dfoo1 ;
assign MUX_caches_1_updRepIdx_dummy2_1$write_1__SEL_1 =
EN_req &&
IF_NOT_caches_1_validVec_0_72_73_OR_NOT_req_vp_ETC___d605 ;
assign MUX_caches_1_validVec_0$write_1__SEL_1 =
EN_addEntry && v__h75347 == 5'd0 &&
IF_NOT_caches_1_validVec_0_72_73_OR_NOT_addEnt_ETC___d1571 &&
@@ -1817,44 +1821,44 @@ module mkSplitTransCache(CLK,
x__h45838 == 2'd1 ;
assign MUX_caches_0_lruBit_lat_0$wset_1__VAL_1 =
(val__h8215 == 24'd16777215) ? x__h8289 : val__h8215 ;
assign MUX_caches_0_updRepIdx_dummy_1_0$wset_1__VAL_2 =
assign MUX_caches_0_updRepIdx_dummy_1_0$wset_1__VAL_1 =
WILL_FIRE_RL_caches_0_doUpdateRep || EN_flush ;
assign MUX_caches_0_updRepIdx_lat_1$wset_1__VAL_1 =
assign MUX_caches_0_updRepIdx_lat_1$wset_1__VAL_1 = { 1'd1, i__h28105 } ;
assign MUX_caches_0_updRepIdx_lat_1$wset_1__VAL_2 =
(IF_NOT_caches_0_validVec_0_14_15_OR_NOT_addEnt_ETC___d912 &&
x__h45838 == 2'd0) ?
{ 1'd1,
IF_NOT_caches_0_validVec_0_14_15_OR_NOT_addEnt_ETC___d938 } :
{ 1'd1, v__h56242 } ;
assign MUX_caches_0_updRepIdx_lat_1$wset_1__VAL_2 = { 1'd1, i__h28105 } ;
assign MUX_caches_1_lruBit_lat_0$wset_1__VAL_1 =
(val__h16746 == 24'd16777215) ? x__h16820 : val__h16746 ;
assign MUX_caches_1_updRepIdx_dummy_1_0$wset_1__VAL_2 =
assign MUX_caches_1_updRepIdx_dummy_1_0$wset_1__VAL_1 =
WILL_FIRE_RL_caches_1_doUpdateRep || EN_flush ;
assign MUX_caches_1_updRepIdx_lat_1$wset_1__VAL_1 =
assign MUX_caches_1_updRepIdx_lat_1$wset_1__VAL_1 = { 1'd1, i__h37522 } ;
assign MUX_caches_1_updRepIdx_lat_1$wset_1__VAL_2 =
(IF_NOT_caches_1_validVec_0_72_73_OR_NOT_addEnt_ETC___d1336 &&
x__h45838 == 2'd1) ?
{ 1'd1,
IF_NOT_caches_1_validVec_0_72_73_OR_NOT_addEnt_ETC___d1361 } :
{ 1'd1, v__h75347 } ;
assign MUX_caches_1_updRepIdx_lat_1$wset_1__VAL_2 = { 1'd1, i__h37522 } ;
// inlined wires
assign caches_0_updRepIdx_lat_1$wget =
MUX_caches_0_updRepIdx_lat_1$wset_1__SEL_1 ?
MUX_caches_0_updRepIdx_dummy2_1$write_1__SEL_1 ?
MUX_caches_0_updRepIdx_lat_1$wset_1__VAL_1 :
MUX_caches_0_updRepIdx_lat_1$wset_1__VAL_2 ;
assign caches_0_updRepIdx_lat_1$whas =
EN_addEntry && _dfoo7 ||
EN_req &&
IF_NOT_caches_0_validVec_0_14_15_OR_NOT_req_vp_ETC___d347 ;
IF_NOT_caches_0_validVec_0_14_15_OR_NOT_req_vp_ETC___d347 ||
EN_addEntry && _dfoo7 ;
assign caches_1_updRepIdx_lat_1$wget =
MUX_caches_1_updRepIdx_lat_1$wset_1__SEL_1 ?
MUX_caches_1_updRepIdx_dummy2_1$write_1__SEL_1 ?
MUX_caches_1_updRepIdx_lat_1$wset_1__VAL_1 :
MUX_caches_1_updRepIdx_lat_1$wset_1__VAL_2 ;
assign caches_1_updRepIdx_lat_1$whas =
EN_addEntry && _dfoo1 ||
EN_req &&
IF_NOT_caches_1_validVec_0_72_73_OR_NOT_req_vp_ETC___d605 ;
IF_NOT_caches_1_validVec_0_72_73_OR_NOT_req_vp_ETC___d605 ||
EN_addEntry && _dfoo1 ;
// register caches_0_lruBit_rl
assign caches_0_lruBit_rl$D_IN =
@@ -2675,7 +2679,7 @@ module mkSplitTransCache(CLK,
// submodule caches_0_lruBit_dummy2_0
assign caches_0_lruBit_dummy2_0$D_IN = 1'd1 ;
assign caches_0_lruBit_dummy2_0$EN =
MUX_caches_0_updRepIdx_dummy_1_0$wset_1__VAL_2 ;
MUX_caches_0_updRepIdx_dummy_1_0$wset_1__VAL_1 ;
// submodule caches_0_lruBit_dummy2_1
assign caches_0_lruBit_dummy2_1$D_IN = 1'b0 ;
@@ -2684,19 +2688,19 @@ module mkSplitTransCache(CLK,
// submodule caches_0_updRepIdx_dummy2_0
assign caches_0_updRepIdx_dummy2_0$D_IN = 1'd1 ;
assign caches_0_updRepIdx_dummy2_0$EN =
MUX_caches_0_updRepIdx_dummy_1_0$wset_1__VAL_2 ;
MUX_caches_0_updRepIdx_dummy_1_0$wset_1__VAL_1 ;
// submodule caches_0_updRepIdx_dummy2_1
assign caches_0_updRepIdx_dummy2_1$D_IN = 1'd1 ;
assign caches_0_updRepIdx_dummy2_1$EN =
EN_addEntry && _dfoo7 ||
EN_req &&
IF_NOT_caches_0_validVec_0_14_15_OR_NOT_req_vp_ETC___d347 ;
IF_NOT_caches_0_validVec_0_14_15_OR_NOT_req_vp_ETC___d347 ||
EN_addEntry && _dfoo7 ;
// submodule caches_1_lruBit_dummy2_0
assign caches_1_lruBit_dummy2_0$D_IN = 1'd1 ;
assign caches_1_lruBit_dummy2_0$EN =
MUX_caches_1_updRepIdx_dummy_1_0$wset_1__VAL_2 ;
MUX_caches_1_updRepIdx_dummy_1_0$wset_1__VAL_1 ;
// submodule caches_1_lruBit_dummy2_1
assign caches_1_lruBit_dummy2_1$D_IN = 1'b0 ;
@@ -2705,14 +2709,14 @@ module mkSplitTransCache(CLK,
// submodule caches_1_updRepIdx_dummy2_0
assign caches_1_updRepIdx_dummy2_0$D_IN = 1'd1 ;
assign caches_1_updRepIdx_dummy2_0$EN =
MUX_caches_1_updRepIdx_dummy_1_0$wset_1__VAL_2 ;
MUX_caches_1_updRepIdx_dummy_1_0$wset_1__VAL_1 ;
// submodule caches_1_updRepIdx_dummy2_1
assign caches_1_updRepIdx_dummy2_1$D_IN = 1'd1 ;
assign caches_1_updRepIdx_dummy2_1$EN =
EN_addEntry && _dfoo1 ||
EN_req &&
IF_NOT_caches_1_validVec_0_72_73_OR_NOT_req_vp_ETC___d605 ;
IF_NOT_caches_1_validVec_0_72_73_OR_NOT_req_vp_ETC___d605 ||
EN_addEntry && _dfoo1 ;
// submodule respQ_deqP_dummy2_0
assign respQ_deqP_dummy2_0$D_IN = 1'd1 ;
@@ -3956,18 +3960,18 @@ module mkSplitTransCache(CLK,
~IF_caches_0_lruBit_lat_0_whas_THEN_caches_0_lr_ETC___d6 :
24'd16777215 ;
assign IF_caches_0_lruBit_lat_0_whas_THEN_caches_0_lr_ETC___d6 =
MUX_caches_0_updRepIdx_dummy_1_0$wset_1__VAL_2 ?
MUX_caches_0_updRepIdx_dummy_1_0$wset_1__VAL_1 ?
upd__h60528 :
caches_0_lruBit_rl ;
assign IF_caches_0_updRepIdx_lat_1_whas_THEN_caches_0_ETC___d17 =
caches_0_updRepIdx_lat_1$whas ?
caches_0_updRepIdx_lat_1$wget[5] :
!MUX_caches_0_updRepIdx_dummy_1_0$wset_1__VAL_2 &&
!MUX_caches_0_updRepIdx_dummy_1_0$wset_1__VAL_1 &&
caches_0_updRepIdx_rl[5] ;
assign IF_caches_0_updRepIdx_lat_1_whas_THEN_caches_0_ETC___d27 =
caches_0_updRepIdx_lat_1$whas ?
caches_0_updRepIdx_lat_1$wget[4:0] :
(MUX_caches_0_updRepIdx_dummy_1_0$wset_1__VAL_2 ?
(MUX_caches_0_updRepIdx_dummy_1_0$wset_1__VAL_1 ?
5'b01010 :
caches_0_updRepIdx_rl[4:0]) ;
assign IF_caches_0_validVec_0_14_AND_caches_0_validVe_ETC___d1001 =
@@ -4017,18 +4021,18 @@ module mkSplitTransCache(CLK,
~IF_caches_1_lruBit_lat_0_whas__0_THEN_caches_1_ETC___d53 :
24'd16777215 ;
assign IF_caches_1_lruBit_lat_0_whas__0_THEN_caches_1_ETC___d53 =
MUX_caches_1_updRepIdx_dummy_1_0$wset_1__VAL_2 ?
MUX_caches_1_updRepIdx_dummy_1_0$wset_1__VAL_1 ?
upd__h79630 :
caches_1_lruBit_rl ;
assign IF_caches_1_updRepIdx_lat_1_whas__5_THEN_cache_ETC___d64 =
caches_1_updRepIdx_lat_1$whas ?
caches_1_updRepIdx_lat_1$wget[5] :
!MUX_caches_1_updRepIdx_dummy_1_0$wset_1__VAL_2 &&
!MUX_caches_1_updRepIdx_dummy_1_0$wset_1__VAL_1 &&
caches_1_updRepIdx_rl[5] ;
assign IF_caches_1_updRepIdx_lat_1_whas__5_THEN_cache_ETC___d74 =
caches_1_updRepIdx_lat_1$whas ?
caches_1_updRepIdx_lat_1$wget[4:0] :
(MUX_caches_1_updRepIdx_dummy_1_0$wset_1__VAL_2 ?
(MUX_caches_1_updRepIdx_dummy_1_0$wset_1__VAL_1 ?
5'b01010 :
caches_1_updRepIdx_rl[4:0]) ;
assign IF_caches_1_validVec_0_72_AND_caches_1_validVe_ETC___d1424 =
@@ -4075,7 +4079,7 @@ module mkSplitTransCache(CLK,
IF_caches_1_validVec_8_36_AND_caches_1_validVe_ETC___d1417 ;
assign NOT_caches_0_updRepIdx_dummy2_1_read__3_48_OR__ETC___d749 =
!caches_0_updRepIdx_dummy2_1$Q_OUT ||
MUX_caches_0_updRepIdx_dummy_1_0$wset_1__VAL_2 ||
MUX_caches_0_updRepIdx_dummy_1_0$wset_1__VAL_1 ||
!caches_0_updRepIdx_rl[5] ;
assign NOT_caches_0_validVec_0_14_15_OR_NOT_addEntry__ETC___d781 =
(!caches_0_validVec_0 ||
@@ -4235,7 +4239,7 @@ module mkSplitTransCache(CLK,
!caches_0_validVec_15 ;
assign NOT_caches_1_updRepIdx_dummy2_1_read__0_51_OR__ETC___d752 =
!caches_1_updRepIdx_dummy2_1$Q_OUT ||
MUX_caches_1_updRepIdx_dummy_1_0$wset_1__VAL_2 ||
MUX_caches_1_updRepIdx_dummy_1_0$wset_1__VAL_1 ||
!caches_1_updRepIdx_rl[5] ;
assign NOT_caches_1_validVec_0_72_73_OR_NOT_addEntry__ETC___d1205 =
(!caches_1_validVec_0 ||