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Regenerate verilog

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This commit is contained in:
Jessica Clarke
2020-07-13 18:54:53 +01:00
parent 26a5376f9c
commit e89f7a8130
294 changed files with 181908 additions and 323568 deletions
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46
src_SSITH_P3/Verilog_RTL_sim/mkIBankWrapper.v
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@@ -1,7 +1,7 @@
//
// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
//
// On Fri Jul 10 20:58:22 BST 2020
// On Mon Jul 13 18:32:19 BST 2020
//
//
// Ports:
@@ -587,7 +587,7 @@ module mkIBankWrapper(CLK,
SEL_ARR_m_fromPQ_data_0_13_BITS_65_TO_2_22_m_f_ETC___d425,
addr__h42425;
reg [31 : 0] CASE_m_cRqMshrpipelineResp_getRq_BITS_5_TO_2__ETC__q37,
CASE_sel1594_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36;
CASE_sel1593_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36;
reg [2 : 0] CASE_m_rqToPQ_deqP_0_m_rqToPQ_data_0_BITS_2_TO_ETC__q31,
x__h45568;
reg [1 : 0] CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_1_TO_ETC__q38,
@@ -620,7 +620,7 @@ module mkIBankWrapper(CLK,
IF_m_pipeline_first__60_BITS_518_TO_516_65_EQ__ETC___d608;
wire [5 : 0] IF_m_pipeline_first__60_BITS_521_TO_520_71_EQ__ETC___d613,
SEL_ARR_m_rqToPQ_data_0_32_BITS_5_TO_4_42_m_rq_ETC___d854;
wire [3 : 0] sel__h51594;
wire [3 : 0] sel__h51593;
wire [2 : 0] IF_m_cRqMshr_pipelineResp_searchEndOfChain_m_c_ETC___d628,
SEL_ARR_m_fromPQ_data_0_13_BIT_518_49_m_fromPQ_ETC___d461,
SEL_ARR_m_rsToPQ_data_0_58_BIT_515_75_m_rsToPQ_ETC___d787,
@@ -1054,7 +1054,7 @@ module mkIBankWrapper(CLK,
WILL_FIRE_RL_m_pipelineResp_pRq && !m_pipeline$first[574] ;
assign MUX_m_cRqMshr$pipelineResp_setResult_2__VAL_1 =
{ 4'd15 - m_cRqMshr$pipelineResp_getRq[5:2] != 4'd0,
CASE_sel1594_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36,
CASE_sel1593_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36,
1'd1,
CASE_m_cRqMshrpipelineResp_getRq_BITS_5_TO_2__ETC__q37 } ;
assign MUX_m_cRqMshr$pipelineResp_setStateSlot_2__VAL_2 =
@@ -1713,7 +1713,7 @@ module mkIBankWrapper(CLK,
assign resp_addr__h45889 =
{ m_cRqMshr$sendRsToP_cRq_getSlot[52:1],
m_cRqMshr$sendRsToP_cRq_getRq[11:0] } ;
assign sel__h51594 = m_cRqMshr$pipelineResp_getRq[5:2] + 4'd1 ;
assign sel__h51593 = m_cRqMshr$pipelineResp_getRq[5:2] + 4'd1 ;
assign v__h10212 =
IF_m_rsToPQ_enqReq_lat_1_whas__1_THEN_m_rsToPQ_ETC___d40 ?
v__h10363 :
@@ -2149,56 +2149,56 @@ module mkIBankWrapper(CLK,
m_fromPQ_data_1[586];
endcase
end
always@(sel__h51594 or m_pipeline$first)
always@(sel__h51593 or m_pipeline$first)
begin
case (sel__h51594)
case (sel__h51593)
4'd0:
CASE_sel1594_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 =
CASE_sel1593_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 =
m_pipeline$first[31:0];
4'd1:
CASE_sel1594_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 =
CASE_sel1593_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 =
m_pipeline$first[63:32];
4'd2:
CASE_sel1594_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 =
CASE_sel1593_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 =
m_pipeline$first[95:64];
4'd3:
CASE_sel1594_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 =
CASE_sel1593_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 =
m_pipeline$first[127:96];
4'd4:
CASE_sel1594_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 =
CASE_sel1593_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 =
m_pipeline$first[159:128];
4'd5:
CASE_sel1594_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 =
CASE_sel1593_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 =
m_pipeline$first[191:160];
4'd6:
CASE_sel1594_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 =
CASE_sel1593_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 =
m_pipeline$first[223:192];
4'd7:
CASE_sel1594_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 =
CASE_sel1593_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 =
m_pipeline$first[255:224];
4'd8:
CASE_sel1594_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 =
CASE_sel1593_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 =
m_pipeline$first[287:256];
4'd9:
CASE_sel1594_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 =
CASE_sel1593_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 =
m_pipeline$first[319:288];
4'd10:
CASE_sel1594_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 =
CASE_sel1593_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 =
m_pipeline$first[351:320];
4'd11:
CASE_sel1594_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 =
CASE_sel1593_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 =
m_pipeline$first[383:352];
4'd12:
CASE_sel1594_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 =
CASE_sel1593_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 =
m_pipeline$first[415:384];
4'd13:
CASE_sel1594_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 =
CASE_sel1593_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 =
m_pipeline$first[447:416];
4'd14:
CASE_sel1594_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 =
CASE_sel1593_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 =
m_pipeline$first[479:448];
4'd15:
CASE_sel1594_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 =
CASE_sel1593_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q36 =
m_pipeline$first[511:480];
endcase
end