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Regenerate verilog

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This commit is contained in:
Jessica Clarke
2020-07-14 19:01:47 +01:00
parent 956c9686a6
commit e8c1de7793
294 changed files with 229618 additions and 214038 deletions
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10
src_SSITH_P3/Verilog_RTL_sim/module_basicExec.v
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@@ -1,7 +1,7 @@
//
// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
//
// On Mon Jul 13 18:24:55 BST 2020
// On Tue Jul 14 18:06:14 BST 2020
//
//
// Ports:
@@ -517,7 +517,7 @@ module module_basicExec(basicExec_dInst,
3'd1) ?
{ 3'd1, basicExec_dInst[100:99] } :
{ CASE_IF_basicExec_dInst_BITS_103_TO_101_50_EQ__ETC__q2,
2'h2 }) ;
2'bxx /* unspecified value */ }) ;
assign IF_basicExec_dInst_BITS_107_TO_104_4_EQ_0_5_OR_ETC___d209 =
(basicExec_dInst[107:104] == 4'd0 ||
basicExec_dInst[107:104] != 4'd1 &&
@@ -563,18 +563,18 @@ module module_basicExec(basicExec_dInst,
basicExec_dInst[107:104] != 4'd6 &&
IF_basicExec_dInst_BITS_107_TO_104_4_EQ_7_8_OR_ETC___d37 ==
4'd4) ?
9'd138 :
{ 4'd4, 5'bxxxxx /* unspecified value */ } :
((basicExec_dInst[107:104] == 4'd5 ||
basicExec_dInst[107:104] != 4'd6 &&
IF_basicExec_dInst_BITS_107_TO_104_4_EQ_7_8_OR_ETC___d37 ==
4'd5) ?
9'd170 :
{ 4'd5, 5'bxxxxx /* unspecified value */ } :
((basicExec_dInst[107:104] == 4'd6 ||
IF_basicExec_dInst_BITS_107_TO_104_4_EQ_7_8_OR_ETC___d37 ==
4'd6) ?
{ 4'd6, basicExec_dInst[103:99] } :
{ CASE_IF_basicExec_dInst_BITS_107_TO_104_4_EQ_7_ETC__q5,
5'h0A })))) ;
5'bxxxxx /* unspecified value */ })))) ;
assign IF_basicExec_dInst_BITS_109_TO_108_0_EQ_0_1_TH_ETC___d599 =
(basicExec_dInst[109:108] == 2'd0) ?
34'h344000000 :