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Regenerate verilog

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This commit is contained in:
Jessica Clarke
2020-07-14 19:01:47 +01:00
parent 956c9686a6
commit e8c1de7793
294 changed files with 229618 additions and 214038 deletions
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6
src_SSITH_P3/Verilog_RTL_sim/module_capModify.v
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@@ -1,7 +1,7 @@
//
// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
//
// On Mon Jul 13 18:24:54 BST 2020
// On Tue Jul 14 18:06:13 BST 2020
//
//
// Ports:
@@ -223,7 +223,7 @@ module module_capModify(capModify_a,
capModify_a_BITS_23_TO_21_06_ULT_capModify_a_B_ETC___d110,
IF_capModify_func_BIT_0_4_THEN_capModify_a_BIT_ETC___d112,
IF_capModify_a_BITS_37_TO_35_08_ULT_capModify__ETC___d122,
1'h0 } :
1'bx /* unspecified value */ } :
IF_capModify_func_BITS_8_TO_5_EQ_1_OR_NOT_capM_ETC___d609 ;
// remaining internal signals
@@ -441,7 +441,7 @@ module module_capModify(capModify_a,
4'd1) ?
setBoundsALU___d134 :
{ IF_capModify_func_BITS_8_TO_5_EQ_2_OR_NOT_capM_ETC___d607,
1'h0 } ;
1'bx /* unspecified value */ } ;
assign IF_capModify_func_BITS_8_TO_5_EQ_2_OR_NOT_capM_ETC___d607 =
(capModify_func[8:5] == 4'd2 ||
capModify_func[8:5] != 4'd3 && capModify_func[8:5] != 4'd4 &&