From e9d212fcbce847d725901382e845c440486b35f1 Mon Sep 17 00:00:00 2001 From: Jessica Clarke Date: Mon, 6 Jul 2020 19:01:56 +0100 Subject: [PATCH] LLC_AXI4_Adapter.bsv: Make more obviously correct Previously we were relying on the beat count registers being exactly the right number of bits such that we'd overflow from 7 back to 0 after the final flit. This change aligns the LLC adapter with the MMIO adapter, which already does things in a safer way. We can also just look at rlast for read respones rather than a full 3-bit comparison (the MMIO adapter also makes this micro-optimisation). --- src_Core/CPU/LLC_AXI4_Adapter.bsv | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/src_Core/CPU/LLC_AXI4_Adapter.bsv b/src_Core/CPU/LLC_AXI4_Adapter.bsv index 0c8afa4..9fa964b 100644 --- a/src_Core/CPU/LLC_AXI4_Adapter.bsv +++ b/src_Core/CPU/LLC_AXI4_Adapter.bsv @@ -154,7 +154,7 @@ module mkLLC_AXi4_Adapter #(MemFifoClient #(idT, childT) llc) let new_cline = CLine { tag: rg_rd_rsp_beat[0] == 0 ? unpack(new_cline_tag) : rg_cline.tag , data: unpack(new_cline_data) }; - if (rg_rd_rsp_beat == 7) begin + if (mem_rsp.rlast) begin let ldreq <- pop (f_pending_reads); MemRsMsg #(idT, childT) resp = MemRsMsg {data: new_cline, child: ldreq.child, @@ -164,10 +164,13 @@ module mkLLC_AXi4_Adapter #(MemFifoClient #(idT, childT) llc) if (cfg_verbosity > 1) $display (" Response to LLC: ", fshow (resp)); - end - rg_cline <= new_cline; - rg_rd_rsp_beat <= rg_rd_rsp_beat + 1; + rg_rd_rsp_beat <= 0; + rg_cline <= unpack(0); + end else begin + rg_rd_rsp_beat <= rg_rd_rsp_beat + 1; + rg_cline <= new_cline; + end endrule // ================================================================ @@ -204,8 +207,11 @@ module mkLLC_AXi4_Adapter #(MemFifoClient #(idT, childT) llc) // on last flit... // =============== - if (rg_wr_req_beat == 7) + if (rg_wr_req_beat == 7) begin llc.toM.deq; + rg_wr_req_beat <= 0; + end else // increment flit counter + rg_wr_req_beat <= rg_wr_req_beat + 1; // on each flit ... // ================ @@ -217,9 +223,6 @@ module mkLLC_AXi4_Adapter #(MemFifoClient #(idT, childT) llc) wstrb: line_strb[rg_wr_req_beat], wlast: rg_wr_req_beat == 7, wuser: pack(line_data[rg_wr_req_beat[2:1]].tag)}); - // increment flit counter - rg_wr_req_beat <= rg_wr_req_beat + 1; - endrule // ----------------