From eb755801eb87645f2fea29ef3fe48d52028048d8 Mon Sep 17 00:00:00 2001 From: Peter Rugg Date: Wed, 1 Mar 2023 14:38:13 +0000 Subject: [PATCH] Revert "Revert "Use wide to narrow AXI4 shim"" This reverts commit 93180fbe252e3436def3c0dfca6d725e5b05d1cc. --- src_SSITH_P3/src_BSV/P3_Core.bsv | 19 +++++++++---------- src_Testbench/SoC/SoC_Top.bsv | 22 ++++++++++------------ 2 files changed, 19 insertions(+), 22 deletions(-) diff --git a/src_SSITH_P3/src_BSV/P3_Core.bsv b/src_SSITH_P3/src_BSV/P3_Core.bsv index 12b2411..a20f371 100644 --- a/src_SSITH_P3/src_BSV/P3_Core.bsv +++ b/src_SSITH_P3/src_BSV/P3_Core.bsv @@ -32,6 +32,7 @@ import Vector :: *; import GetPut_Aux :: *; import Routable :: *; +import BlueBasics :: *; import BlueAXI4 :: *; import SourceSink :: *; import WindCoreInterface :: *; @@ -166,15 +167,13 @@ module mkP3_Core (P3_Core_IFC); <- mkCoreW_reset (dm_power_on_reset, reset_by ndm_reset); match {.otherRst, .corew} = both; // AXI4 Narrower Master in front of cached memory master - AXI4_Shim#(TAdd#(Wd_MId,1), Wd_Addr, Wd_Data_Periph, 0, 0, 0, 0, 0) - manager_0_narrow <- mkAXI4ShimFF; - AXI4_Slave #(TAdd#(Wd_MId,1), Wd_Addr, TDiv#(Wd_Data,4), 0, 0, 0, 0, 0) - manager_0_wide_a <- toWider_AXI4_Slave(manager_0_narrow.slave); - AXI4_Slave #(TAdd#(Wd_MId,1), Wd_Addr, TDiv#(Wd_Data,2), 0, 0, 0, 0, 0) - manager_0_wide_b <- toWider_AXI4_Slave(manager_0_wide_a); - AXI4_Slave #(TAdd#(Wd_MId,1), Wd_Addr, Wd_Data, 0, 0, 0, 0, 0) - manager_0_wide <- toWider_AXI4_Slave(manager_0_wide_b); - mkConnection(corew.manager_0,manager_0_wide); + NumProxy #(4) proxyInDepth = error ("don't look inside a proxy"); + NumProxy #(4) proxyOutDepth = error ("don't look inside a proxy"); + Tuple2 #( AXI4_Slave #(TAdd#(Wd_MId,1), Wd_Addr, Wd_Data, 0, 0, 0, 0, 0) + , AXI4_Master #(TAdd#(Wd_MId,1), Wd_Addr, Wd_Data_Periph, 0, 0, 0, 0, 0) ) + wideS_narrowM <- mkAXI4DataWidthShim_WideToNarrow (proxyInDepth, proxyOutDepth); + match {.wideS, .narrowM} = wideS_narrowM; + mkConnection(corew.manager_0, wideS); `ifdef INCLUDE_GDB_CONTROL @@ -271,7 +270,7 @@ module mkP3_Core (P3_Core_IFC); // ================================================================ // INTERFACE - let master0_sig <- toAXI4_Master_Sig (manager_0_narrow.master); + let master0_sig <- toAXI4_Master_Sig (narrowM); let master1_sig <- toAXI4_Master_Sig (corew.manager_1); // ---------------------------------------------------------------- // Core CPU interfaces diff --git a/src_Testbench/SoC/SoC_Top.bsv b/src_Testbench/SoC/SoC_Top.bsv index 78b843d..af9779c 100644 --- a/src_Testbench/SoC/SoC_Top.bsv +++ b/src_Testbench/SoC/SoC_Top.bsv @@ -46,8 +46,8 @@ import Vector :: *; import Cur_Cycle :: *; import GetPut_Aux :: *; import Routable :: *; -import AXI4 :: *; -import AXI4Lite :: *; +import BlueBasics :: *; +import BlueAXI4 :: *; // ================================================================ // Project imports @@ -163,15 +163,13 @@ module mkSoC_Top #(Reset dm_power_on_reset) mem0_controller_axi4_deburster <- mkBurstToNoBurst; // AXI4 Narrower Master in front of cached memory master - AXI4_Shim#(TAdd#(Wd_MId,1), Wd_Addr, Wd_Data_Periph, 0, 0, 0, 0, 0) - manager_0_narrow <- mkAXI4ShimFF; - AXI4_Slave #(TAdd#(Wd_MId,1), Wd_Addr, TDiv#(Wd_Data,4), 0, 0, 0, 0, 0) - manager_0_wide_a <- toWider_AXI4_Slave(manager_0_narrow.slave); - AXI4_Slave #(TAdd#(Wd_MId,1), Wd_Addr, TDiv#(Wd_Data,2), 0, 0, 0, 0, 0) - manager_0_wide_b <- toWider_AXI4_Slave(manager_0_wide_a); - AXI4_Slave #(TAdd#(Wd_MId,1), Wd_Addr, Wd_Data, 0, 0, 0, 0, 0) - manager_0_wide <- toWider_AXI4_Slave(manager_0_wide_b); - mkConnection(corew.manager_0,manager_0_wide); + NumProxy #(4) proxyInDepth = error ("don't look inside a proxy"); + NumProxy #(4) proxyOutDepth = error ("don't look inside a proxy"); + Tuple2 #( AXI4_Slave #(TAdd#(Wd_MId,1), Wd_Addr, Wd_Data, 0, 0, 0, 0, 0) + , AXI4_Master #(TAdd#(Wd_MId,1), Wd_Addr, Wd_Data_Periph, 0, 0, 0, 0, 0) ) + wideS_narrowM <- mkAXI4DataWidthShim_WideToNarrow (proxyInDepth, proxyOutDepth); + match {.wideS, .narrowM} = wideS_narrowM; + mkConnection(corew.manager_0, wideS); // SoC IPs UART_IFC uart0 <- mkUART; @@ -190,7 +188,7 @@ module mkSoC_Top #(Reset dm_power_on_reset) master_vector = newVector; // CPU IMem master to fabric - master_vector[imem_master_num] = manager_0_narrow.master; + master_vector[imem_master_num] = narrowM; // CPU DMem master to fabric master_vector[dmem_master_num] = corew.manager_1;