From ec9f19dc26c6f933639b150b3b4b53aabb45e44e Mon Sep 17 00:00:00 2001 From: Peter Rugg Date: Mon, 11 May 2020 22:39:12 +0100 Subject: [PATCH] Disable assert since normal instructions can read SCRs --- src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv index c3b2b41..119c5ca 100755 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv @@ -309,9 +309,9 @@ module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline); end // when inst needs to store scrData in ROB, it must have iType = Scr, cannot mispredict if(isValid(x.dInst.scr)) begin - doAssert(x.dInst.iType == Scr, "Only Scr inst needs to update scrData in ROB"); + // doAssert(x.dInst.iType == Scr, "Only Scr inst needs to update scrData in ROB"); // Removed because normal instructions can read SCRs doAssert(!exec_result.controlFlow.mispredict, "Scr inst cannot mispredict"); - doAssert(cast(exec_result.controlFlow.nextPc) == x.ppc && x.ppc == addPc(x.pc, 4), "Csr inst ppc = pc+4"); + doAssert(cast(exec_result.controlFlow.nextPc) == x.ppc && x.ppc == addPc(x.pc, 4), "Scr inst ppc = pc+4"); end // send bypass