From ed9541e8d05156dfc577e85f953a84ad079885f1 Mon Sep 17 00:00:00 2001
From: Marno van der Maas <34654485+marnovandermaas@users.noreply.github.com>
Date: Fri, 2 Oct 2020 13:09:51 +0100
Subject: [PATCH] Put all dirs for source description in code blocks

---
 README.md | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/README.md b/README.md
index 836e269..a14ac44 100644
--- a/README.md
+++ b/README.md
@@ -93,10 +93,10 @@ library RTL can be found in the directory `src_bsc_lib_RTL`.
 
 - `src_Core/`, for the CPU core, with sub-directories:
    - `Core/`: the top-level of the CPU Core (specifically, the files CoreW_IFC.bsv and CoreW.bsv)
-   - 'CPU/': more CPU core sources
-   - 'RISCY_OOO': the bulk of the code, taken from MIT's riscy-ooo design, with local modifications.
+   - `CPU/`: more CPU core sources
+   - `RISCY_OOO`: the bulk of the code, taken from MIT's riscy-ooo design, with local modifications.
    - `ISA/`:  generic types/constants/functions for the RISC-V ISA (not CPU-implementation-specific)
-   - 'PLIC/': Platform-Level Interrupt Controller (standard RISC-V spec)
+   - `PLIC/`: Platform-Level Interrupt Controller (standard RISC-V spec)
    - `BSV_Additional_Libs/`: generic utilities (not CPU-specific)
    - `Debug_Module/`: RISC-V Debug Module to debug the CPU from GDB or other debuggers