Initial load of files
This commit is contained in:
rsnikhil
94
src_Core/Debug_Module/Test/Makefile
Normal file
94
src_Core/Debug_Module/Test/Makefile
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@@ -0,0 +1,94 @@
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default: compile link
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all: compile link simulate
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TOP = Testbench
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TOPFILE = $(TOP).bsv
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TOPMODULE = mk$(TOP)
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# BSCFLAGS = -keep-fires -aggressive-conditions -no-warn-action-shadowing -no-inline-rwire
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# BSCFLAGS = -keep-fires -aggressive-conditions -no-inline-rwire -show-range-conflict -show-schedule
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BSCFLAGS = -D RV32 \
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-keep-fires \
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-aggressive-conditions \
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-suppress-warnings G0020 \
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-show-schedule
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# ----------------------------------------------------------------
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# FOR BLUESIM
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ISA_DECLS_DIR = $(HOME)/Projects/RISCV/Bluespec_RISCV/ISA
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TRX_DIR = $(HOME)/Projects/RISCV/Bluespec_RISCV/Fabrics/TRX
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ADDL_LIBS_DIR = $(HOME)/Projects/RISCV/Bluespec_RISCV/BSV_Additional_Libs/BSV
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BSCDIRS_BSIM = -simdir build_bsim -bdir build -info-dir build
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BSCPATH_BSIM = -p .:..:$(ISA_DECLS_DIR):$(TRX_DIR):$(ADDL_LIBS_DIR):%/Prelude:%/Libraries
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build_bsim:
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mkdir -p $@
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build:
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mkdir -p $@
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.PHONY: compile
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compile: build_bsim build
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@echo Compiling...
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bsc -u -sim $(BSCDIRS_BSIM) $(BSCFLAGS) $(BSCPATH_BSIM) $(TOPFILE)
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@echo Compilation finished
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.PHONY: link
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link:
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@echo Linking...
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bsc -e $(TOPMODULE) $(BSCFLAGS) -parallel-sim-link 8 -sim -o ./$(TOP)_bsim_exe $(BSCDIRS_BSIM) $(BSCPATH_BSIM)
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@echo Linking finished
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.PHONY: simulate
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simulate:
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@echo Simulation...
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logsave bsim.log ./$(TOP)_bsim_exe -V
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@echo Simulation finished
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# ----------------------------------------------------------------
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# FOR VERILOG
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BSCDIRS_V = -vdir verilog -bdir build_v -info-dir build_v
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BSCPATH_V = -p .:./$(SRC_BSV):%/Prelude:%/Libraries:%/Libraries/TLM3
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# Set VSIM to desired Verilog simulator
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# VSIM = modelsim
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VSIM ?= cvc
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# VSIM ?= iverilog
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build_v:
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mkdir -p $@
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verilog:
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mkdir -p $@
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.PHONY: rtl
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rtl: build_v verilog
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@echo Verilog generation ...
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bsc -u -elab -verilog $(BSCDIRS_V) $(BSCFLAGS) $(BSCPATH_V) $(TOPFILE)
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@echo Verilog generation finished
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.PHONY: vlink
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vlink:
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bsc -v -e $(TOPMODULE) -verilog -o ./out_v -vdir verilog -vsim $(VSIM) -keep-fires \
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verilog/$(TOPMODULE).v
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.PHONY: vsim
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vsim:
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@echo Simulation...
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./out_v
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@echo Simulation finished
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# ----------------------------------------------------------------
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.PHONY: clean
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clean:
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rm -f *~ src_*/*~ src_*/*.o build/* build_bsim/* build_v/* *.cxx *.h *.o
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.PHONY: full_clean
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full_clean: clean
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rm -r -f *_bsim_exe *.so out_v verilog build build_bsim dump.vcd bsim.log
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597
src_Core/Debug_Module/Test/Testbench.bsv
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597
src_Core/Debug_Module/Test/Testbench.bsv
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@@ -0,0 +1,597 @@
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package Testbench;
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// ================================================================
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// Testbench for basic sanity-check testing of the Debug Module.
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// ================================================================
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// BSV library imports
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import FIFOF :: *;
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import GetPut :: *;
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import ClientServer :: *;
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import Connectable :: *;
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import StmtFSM :: *;
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// ----------------
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// Other library imports
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import Semi_FIFOF :: *;
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// ================================================================
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import ISA_Decls :: *;
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import TRX :: *;
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import Debug_Module :: *;
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// ================================================================
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Integer csr_addr_dcsr = 'h7b0;
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Integer csr_addr_dpc = 'h7b1;
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Integer csr_addr_dscratch0 = 'h7b2;
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Integer csr_addr_dscratch1 = 'h7b3;
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// ================================================================
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(* synthesize *)
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module mkTestbench (Empty);
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// ================================================================
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// Cycle-counter and cycle-limit termination
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Reg #(Bit #(32)) rg_cycle <- mkReg (0);
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Integer cycle_limit = 100;
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rule rl_count_cycles;
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if (rg_cycle == fromInteger (100)) begin
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$display ("Testench: stopping at cycle %0d", cycle_limit);
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$finish (0);
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end
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rg_cycle <= rg_cycle +1;
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endrule
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// ================================================================
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// The Debug Module
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Debug_Module_IFC dm <- mkDebug_Module;
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// ================================================================
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// Model of a hart, and connections to dm
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Hart_DM_IFC hart0 <- mkHart_Model (0);
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// Reset
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mkConnection (dm.hart0_reset_req, hart0.hart_reset_req);
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// Run-control
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mkConnection (dm.hart0_run_req_rsp, hart0.hart_run_req_rsp);
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// GPR access
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mkConnection (dm.master_for_gprs, hart0.slave_for_gprs);
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// CSR access
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mkConnection (dm.master_for_csrs, hart0.slave_for_csrs);
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// ================================================================
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// Over-simplified model of platform reset (all except DM)
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rule rl_ndm_reset;
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let x <- dm.ndm_reset_req.get;
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$display ("Testbench.rl_ndm_reset: Resetting all platform except Debug Module");
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endrule
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// ================================================================
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// Over-simplified model of system (RISC-V) memory
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// On reads, return addr + 2.
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rule rl_mem_read;
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let rda <- pop_o (dm.master.fo_rda);
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let data = rda.addr + 2; // Bogus data, for now
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let rdr = TRX_RdR {trans_id: rda.trans_id,
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status : TRX_OKAY,
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data : data};
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dm.master.fi_rdr.enq (rdr);
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$display ("Testbench: memory read [0x%08h] => 0x%08h", rda.addr, data);
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endrule
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rule rl_mem_write;
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let wra <- pop_o (dm.master.fo_wra);
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let wrd <- pop_o (dm.master.fo_wrd);
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let wrr = TRX_WrR {trans_id: wra.trans_id,
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status : TRX_OKAY};
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dm.master.fi_wrr.enq (wrr);
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$display ("Testbench: memory write [0x%08h] <= 0x%08h", wra.addr, wrd.data);
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endrule
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// ================================================================
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// Abstract command sequences (read/write GPR/CSR)
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Reg #(Bit #(32)) rg_abstractcs <- mkRegU;
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// Read a register
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function Stmt fn_stmt_read_reg (Bit #(16) regno);
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return
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seq
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$display ("----------------\nRead RISC-V reg");
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// Clear any prior error status
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dm.write (dm_addr_abstractcs, fn_mk_abstractcs (dm_cmderr_w1c));
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// Perform the read
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dm.write (dm_addr_command,
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fn_mk_command_access_reg (DM_COMMAND_ACCESS_REG_SIZE_LOWER32,
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False, // postexec
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True, // transfer
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False, // write
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regno));
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// Read status to check no error
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action
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let x <- dm.av_read (dm_addr_abstractcs);
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rg_abstractcs <= x;
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endaction
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while (fn_abstractcs_busy (rg_abstractcs)) seq
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$display ("Testbench: read reg: busy");
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action
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let x <- dm.av_read (dm_addr_abstractcs);
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rg_abstractcs <= x;
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endaction
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endseq
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if (fn_abstractcs_cmderr (rg_abstractcs) != DM_ABSTRACTCS_CMDERR_NONE)
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$display ("Testbench: read reg => ", fshow (fn_abstractcs_cmderr (rg_abstractcs)));
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else action
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let x <- dm.av_read (dm_addr_data0);
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$display ("Testbench: read reg => 0x%08h", x);
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endaction
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endseq;
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endfunction
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// Write a register
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function Stmt fn_stmt_write_reg (Bit #(16) regno, Bit #(32) data);
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return
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seq
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$display ("----------------\nWrite RISC-V reg");
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// Clear any prior error status
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dm.write (dm_addr_abstractcs, fn_mk_abstractcs (dm_cmderr_w1c));
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// Write data0
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dm.write (dm_addr_data0, data);
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// Perform the write
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dm.write (dm_addr_command,
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fn_mk_command_access_reg (DM_COMMAND_ACCESS_REG_SIZE_LOWER32,
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False, // postexec
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True, // transfer
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True, // write
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regno));
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// Read status to check no error
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action
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let x <- dm.av_read (dm_addr_abstractcs);
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rg_abstractcs <= x;
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endaction
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while (fn_abstractcs_busy (rg_abstractcs)) seq
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$display ("Testbench: write reg: busy");
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action
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let x <- dm.av_read (dm_addr_abstractcs);
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rg_abstractcs <= x;
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endaction
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endseq
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$display ("Testbench: write reg => ", fshow (fn_abstractcs_cmderr (rg_abstractcs)));
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endseq;
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endfunction
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// ================================================================
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// System Bus access sequences (read/write RISC-V memory)
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Reg #(Bool) rg_busy <- mkRegU;
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Reg #(Bit #(32)) rg_j <- mkRegU;
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Reg #(Bit #(32)) rg_addr <- mkRegU;
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Reg #(Bit #(32)) rg_data <- mkRegU;
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Stmt stmt_wait_for_sb_nonbusy = (
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seq
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rg_busy <= True;
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while (rg_busy) seq
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delay (1);
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action
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let x <- dm.av_read (dm_addr_sbcs);
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let sberror = fn_sbcs_sberror (x);
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rg_busy <= (sberror == DM_SBERROR_BUSY_STALE);
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if ( (sberror != DM_SBERROR_NONE)
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&& (sberror != DM_SBERROR_BUSY_STALE))
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begin
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$display ("Testbench: stmt_wait_for_sb_nonbusy: ", fshow (sberror));
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$finish (1);
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end
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endaction
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endseq
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endseq);
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// Do a single-read from memory
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Stmt stmt_mem_read_1 = (
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seq
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dm.write (dm_addr_sbaddress0, 'h1_0000);
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dm.write (dm_addr_sbcs, fn_mk_sbcs (True, // sbsingleread
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DM_SBACCESS_32_BIT,
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False, // sbautoincrement
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False, // sbautoread
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DM_SBERROR_UNDEF7_W1C)); // clear sberror
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stmt_wait_for_sb_nonbusy;
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action
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let x <- dm.av_read (dm_addr_sbdata0);
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$display ("stmt_mem_read_1: read-data = 0x%08h", x);
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endaction
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endseq);
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// Do a multiple-read from memory
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Stmt stmt_mem_read_4 = (
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seq
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dm.write (dm_addr_sbaddress0, 'h1_0000);
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dm.write (dm_addr_sbcs, fn_mk_sbcs (True, // sbsingleread
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DM_SBACCESS_32_BIT,
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True, // sbautoincrement
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True, // sbautoread
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DM_SBERROR_UNDEF7_W1C)); // clear sberror
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for (rg_j <= 0; rg_j < 3; rg_j <= rg_j + 1) seq
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stmt_wait_for_sb_nonbusy;
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action
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let x <- dm.av_read (dm_addr_sbdata0);
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$display ("stmt_mem_read_4: read-data [%0d] = 0x%08h", rg_j, x);
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endaction
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endseq
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dm.write (dm_addr_sbcs, fn_mk_sbcs (False, // sbsingleread
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DM_SBACCESS_32_BIT,
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False, // sbautoincrement
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False, // sbautoread
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DM_SBERROR_UNDEF7_W1C)); // clear sberror
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stmt_wait_for_sb_nonbusy;
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action
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let x <- dm.av_read (dm_addr_sbdata0);
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$display ("stmt_mem_read_4: read-data [%0d] = 0x%08h", rg_j, x);
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endaction
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endseq);
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// Do a single-write to memory
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Stmt stmt_mem_write_1 = (
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seq
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dm.write (dm_addr_sbcs, fn_mk_sbcs (False, // sbsingleread
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DM_SBACCESS_32_BIT,
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False, // sbautoincrement
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False, // sbautoread
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DM_SBERROR_UNDEF7_W1C)); // clear sberror
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stmt_wait_for_sb_nonbusy;
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dm.write (dm_addr_sbaddress0, 'h1_0000);
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dm.write (dm_addr_sbdata0, 'h_BEEF);
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endseq);
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// Do a multiple-write to memory
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Stmt stmt_mem_write_4 = (
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seq
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dm.write (dm_addr_sbcs, fn_mk_sbcs (False, // sbsingleread
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DM_SBACCESS_32_BIT,
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True, // sbautoincrement
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False, // sbautoread
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DM_SBERROR_UNDEF7_W1C)); // clear sberror
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stmt_wait_for_sb_nonbusy;
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action
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rg_addr <= 'h_2000;
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rg_data <= 'h_DAFA_0000;
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endaction
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dm.write (dm_addr_sbaddress0, rg_addr);
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for (rg_j <= 0; rg_j < 4; rg_j <= rg_j + 1) seq
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stmt_wait_for_sb_nonbusy;
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action
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$display ("stmt_mem_write_4: [0x%08h] x = 0x%08h", rg_addr + rg_j, rg_data);
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dm.write (dm_addr_sbdata0, rg_data);
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rg_data <= rg_data + 1;
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endaction
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||||
endseq
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||||
endseq);
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||||
|
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// ================================================================
|
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// Run-control test sequences (reset, run, halt, single-step)
|
||||
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let dmcontrol_dm_reset
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= fn_mk_dmcontrol (False, // haltreq
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||||
False, // resumereq
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||||
False, // hartreset
|
||||
False, // hasel
|
||||
0, // hartsel,
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||||
False, // ndmreset
|
||||
False); // dmactive; assert reset
|
||||
|
||||
let dmcontrol_ndmreset
|
||||
= fn_mk_dmcontrol (False, // haltreq
|
||||
False, // resumereq
|
||||
False, // hartreset
|
||||
False, // hasel,
|
||||
0, // hartsel
|
||||
True, // ndmreset
|
||||
True); // dmactive
|
||||
|
||||
let dmcontrol_err_hasel
|
||||
= fn_mk_dmcontrol (False, // haltreq
|
||||
False, // resumereq
|
||||
False, // hartreset
|
||||
True, // hasel,
|
||||
0, // hartsel
|
||||
False, // ndmreset
|
||||
True); // dmactive
|
||||
|
||||
let dmcontrol_err_hartsel
|
||||
= fn_mk_dmcontrol (False, // haltreq
|
||||
False, // resumereq
|
||||
False, // hartreset
|
||||
False, // hasel,
|
||||
3, // hartsel
|
||||
False, // ndmreset
|
||||
True); // dmactive
|
||||
|
||||
let dmcontrol_hartreset
|
||||
= fn_mk_dmcontrol (False, // haltreq
|
||||
False, // resumereq
|
||||
True, // hartreset
|
||||
False, // hasel,
|
||||
0, // hartsel
|
||||
False, // ndmreset
|
||||
True); // dmactive
|
||||
|
||||
let dmcontrol_err_haltreq_resumereq
|
||||
= fn_mk_dmcontrol (True, // haltreq
|
||||
True, // resumereq
|
||||
False, // hartreset
|
||||
False, // hasel,
|
||||
0, // hartsel
|
||||
False, // ndmreset
|
||||
True); // dmactive
|
||||
|
||||
let dmcontrol_haltreq
|
||||
= fn_mk_dmcontrol (True, // haltreq
|
||||
False, // resumereq
|
||||
False, // hartreset
|
||||
False, // hasel,
|
||||
0, // hartsel
|
||||
False, // ndmreset
|
||||
True); // dmactive
|
||||
|
||||
let dmcontrol_resumereq
|
||||
= fn_mk_dmcontrol (False, // haltreq
|
||||
True, // resumereq
|
||||
False, // hartreset
|
||||
False, // hasel,
|
||||
0, // hartsel
|
||||
False, // ndmreset
|
||||
True); // dmactive
|
||||
|
||||
function Stmt fn_stmt_run_control (DM_Word dm_word);
|
||||
return seq
|
||||
dm.write (dm_addr_dmcontrol, dm_word);
|
||||
delay (5);
|
||||
// Check and show status
|
||||
action
|
||||
let x <- dm.av_read (dm_addr_dmstatus);
|
||||
$display (" ", fshow_dmstatus (x));
|
||||
endaction
|
||||
endseq;
|
||||
endfunction
|
||||
|
||||
// ----------------
|
||||
// For single-step, set 'step' bit in DCSR, then run
|
||||
|
||||
let dcsr_step = {4'h4, // xdebugver
|
||||
12'b0,
|
||||
1'b0, // ebreakm
|
||||
1'b0,
|
||||
1'b0, // ebreaks
|
||||
1'b0, // ebreaku
|
||||
1'b0, // stepie
|
||||
1'b0, // stepcount
|
||||
1'b0, // steptime
|
||||
3'b0, // cause
|
||||
3'b0,
|
||||
1'b1, // step
|
||||
2'h3};
|
||||
|
||||
Stmt stmt_single_step = (
|
||||
seq
|
||||
// set 'step' in dcsr
|
||||
fn_stmt_write_reg (fromInteger (dm_command_access_reg_regno_csr_0 + csr_addr_dcsr),
|
||||
dcsr_step); // priv
|
||||
fn_stmt_run_control (dmcontrol_resumereq);
|
||||
endseq);
|
||||
|
||||
// ================================================================
|
||||
// Top-level test. Comment/Uncomment desired parts.
|
||||
|
||||
Stmt test = seq
|
||||
// Reset DM
|
||||
$display ("----------------\n'Testbench: Reset DM'");
|
||||
fn_stmt_run_control (dmcontrol_dm_reset);
|
||||
|
||||
/*
|
||||
$display ("----------------\n'Testbench: Reset Platform'");
|
||||
fn_stmt_run_control (dmcontrol_ndmreset);
|
||||
|
||||
$display ("----------------\n'Testbench: Err hasel'");
|
||||
fn_stmt_run_control (dmcontrol_err_hasel);
|
||||
|
||||
$display ("----------------\n'Testbench: Err hartsel'");
|
||||
fn_stmt_run_control (dmcontrol_err_hartsel);
|
||||
|
||||
$display ("----------------\n'Testbench: Reset hart'");
|
||||
fn_stmt_run_control (dmcontrol_hartreset);
|
||||
|
||||
$display ("----------------\n'Testbench: Err haltreq and resumereq'");
|
||||
fn_stmt_run_control (dmcontrol_err_haltreq_resumereq);
|
||||
|
||||
$display ("----------------\n'Testbench: Continue'");
|
||||
fn_stmt_run_control (dmcontrol_resumereq);
|
||||
|
||||
$display ("----------------\n'Testbench: Halt'");
|
||||
fn_stmt_run_control (dmcontrol_haltreq);
|
||||
|
||||
$display ("----------------\n'Testbench: Single step'");
|
||||
stmt_single_step;
|
||||
*/
|
||||
|
||||
$display ("----------------\n'Testbench: Read GPR'");
|
||||
fn_stmt_read_reg (fromInteger (dm_command_access_reg_regno_gpr_0 + 5));
|
||||
$display ("----------------\n'Testbench: Read CSR'");
|
||||
fn_stmt_read_reg (fromInteger (dm_command_access_reg_regno_csr_0 + 3));
|
||||
|
||||
$display ("----------------\n'Testbench: Write GPR'");
|
||||
fn_stmt_write_reg (fromInteger (dm_command_access_reg_regno_gpr_0 + 5), 'h_AAAA_0005);
|
||||
$display ("----------------\n'Testbench: Write CSR'");
|
||||
fn_stmt_write_reg (fromInteger (dm_command_access_reg_regno_csr_0 + 3), 'h_CCCC_0003);
|
||||
|
||||
/*
|
||||
$display ("----------------\n'Testbench: Read 1'");
|
||||
stmt_mem_read_1;
|
||||
|
||||
$display ("----------------\n'Testbench: Write 1'");
|
||||
stmt_mem_write_1;
|
||||
|
||||
$display ("----------------\n'Testbench: Read 4'");
|
||||
stmt_mem_read_4;
|
||||
|
||||
$display ("----------------\n'Testbench: Write 4'");
|
||||
stmt_mem_write_4;
|
||||
*/
|
||||
|
||||
await (False);
|
||||
endseq;
|
||||
|
||||
mkAutoFSM (test);
|
||||
|
||||
endmodule
|
||||
|
||||
// ================================================================
|
||||
// Over-simplified model of a hart (reset, run/halt, read/write GPR/CSR)
|
||||
|
||||
interface Hart_DM_IFC;
|
||||
// Reset
|
||||
interface Put #(Token) hart_reset_req;
|
||||
|
||||
// Run-control
|
||||
interface Server #(Bool, Bool) hart_run_req_rsp;
|
||||
|
||||
// GPR access
|
||||
interface TRX_Slave_IFC #(5,32,0) slave_for_gprs;
|
||||
|
||||
// CSR access
|
||||
interface TRX_Slave_IFC #(12,32,0) slave_for_csrs;
|
||||
endinterface
|
||||
|
||||
|
||||
(* synthesize *)
|
||||
module mkHart_Model #(parameter Bit #(10) hart_id) (Hart_DM_IFC);
|
||||
|
||||
Reg #(Bool) rg_hart_running <- mkReg (False);
|
||||
|
||||
FIFOF #(Token) f_hart_reset_reqs <- mkFIFOF;
|
||||
|
||||
FIFOF #(Bool) f_hart_run_reqs <- mkFIFOF;
|
||||
FIFOF #(Bool) f_hart_run_rsps <- mkFIFOF;
|
||||
|
||||
// TRX interface to gprs
|
||||
TRX_Buffer_IFC #(5,32,0) trx_buf_gprs <- mkTRX_Buffer;
|
||||
|
||||
// TRX interface to crs
|
||||
TRX_Buffer_IFC #(12,32,0) trx_buf_csrs <- mkTRX_Buffer;
|
||||
|
||||
// ----------------------------------------------------------------
|
||||
// BEHAVIOR
|
||||
|
||||
// ----------------
|
||||
// Reset
|
||||
|
||||
rule rl_hart_reset;
|
||||
let x = f_hart_reset_reqs.first;
|
||||
f_hart_reset_reqs.deq;
|
||||
|
||||
$display ("Testbench.hart [%0d]: reset", hart_id);
|
||||
endrule
|
||||
|
||||
// ----------------
|
||||
// Run-control
|
||||
|
||||
rule rl_resume_hart (f_hart_run_reqs.first);
|
||||
f_hart_run_reqs.deq;
|
||||
rg_hart_running <= True;
|
||||
|
||||
if (rg_hart_running)
|
||||
$display ("Testbench.hart [%0d].rl_resume_hart: already running", hart_id);
|
||||
else
|
||||
$display ("Testbench.hart [%0d].rl_resume_hart: resuming", hart_id);
|
||||
|
||||
f_hart_run_rsps.enq (True);
|
||||
endrule
|
||||
|
||||
rule rl_halt_hart (! f_hart_run_reqs.first);
|
||||
f_hart_run_reqs.deq;
|
||||
rg_hart_running <= False;
|
||||
|
||||
if (rg_hart_running)
|
||||
$display ("Testbench.hart [%0d].rl_halt_hart: halting", hart_id);
|
||||
else
|
||||
$display ("Testbench.hart [%0d].rl_halt_hart: already halted", hart_id);
|
||||
|
||||
f_hart_run_rsps.enq (False);
|
||||
endrule
|
||||
|
||||
// ----------------
|
||||
// GPR access
|
||||
|
||||
rule rl_read_gpr;
|
||||
let rda <- pop_o (trx_buf_gprs.master.fo_rda);
|
||||
Bit #(32) data = extend (rda.addr) + 'h1000;
|
||||
let rdr = TRX_RdR {trans_id: rda.trans_id,
|
||||
status: TRX_OKAY,
|
||||
data: data};
|
||||
trx_buf_gprs.master.fi_rdr.enq (rdr);
|
||||
$display ("Testbench.hart [%0d]: Read GPR [%0h] => 0x%08h", hart_id, rda.addr, data);
|
||||
endrule
|
||||
|
||||
rule rl_read_csr;
|
||||
let rda <- pop_o (trx_buf_csrs.master.fo_rda);
|
||||
Bit #(32) data = extend (rda.addr) + 'h2000;
|
||||
let rdr = TRX_RdR {trans_id: rda.trans_id,
|
||||
status: TRX_OKAY,
|
||||
data: data};
|
||||
trx_buf_csrs.master.fi_rdr.enq (rdr);
|
||||
$display ("Testbench.hart [%0d]: Read CSR [%0h] => 0x%08h", hart_id, rda.addr, data);
|
||||
endrule
|
||||
|
||||
rule rl_write_gpr;
|
||||
let wra <- pop_o (trx_buf_gprs.master.fo_wra);
|
||||
let wrd <- pop_o (trx_buf_gprs.master.fo_wrd);
|
||||
let wrr = TRX_WrR {trans_id: wra.trans_id, status: TRX_OKAY};
|
||||
trx_buf_gprs.master.fi_wrr.enq (wrr);
|
||||
$display ("Testbench.hart [%0d]: Write GPR [%0h] <= 0x%08h", hart_id, wra.addr, wrd.data);
|
||||
endrule
|
||||
|
||||
rule rl_write_csr;
|
||||
let wra <- pop_o (trx_buf_csrs.master.fo_wra);
|
||||
let wrd <- pop_o (trx_buf_csrs.master.fo_wrd);
|
||||
let wrr = TRX_WrR {trans_id: wra.trans_id, status: TRX_OKAY};
|
||||
trx_buf_csrs.master.fi_wrr.enq (wrr);
|
||||
$display ("Testbench.hart [%0d]: Write CSR [%0h] <= 0x%08h", hart_id, wra.addr, wrd.data);
|
||||
endrule
|
||||
|
||||
// ----------------------------------------------------------------
|
||||
// INTERFACE
|
||||
|
||||
// Reset
|
||||
interface Put hart_reset_req = toPut (f_hart_reset_reqs);
|
||||
|
||||
// Run-control
|
||||
interface Server hart_run_req_rsp = toGPServer (f_hart_run_reqs, f_hart_run_rsps);
|
||||
|
||||
// GPR access
|
||||
interface TRX_Slave_IFC slave_for_gprs = trx_buf_gprs.slave;
|
||||
|
||||
// CSR access
|
||||
interface TRX_Slave_IFC slave_for_csrs = trx_buf_csrs.slave;
|
||||
endmodule
|
||||
|
||||
// ================================================================
|
||||
|
||||
endpackage
|
||||
Reference in New Issue
Block a user