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rsnikhil
281
src_bsc_lib_RTL/SizedFIFO.v
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281
src_bsc_lib_RTL/SizedFIFO.v
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// Copyright (c) 2000-2012 Bluespec, Inc.
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// Permission is hereby granted, free of charge, to any person obtaining a copy
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// of this software and associated documentation files (the "Software"), to deal
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// in the Software without restriction, including without limitation the rights
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// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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// copies of the Software, and to permit persons to whom the Software is
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// furnished to do so, subject to the following conditions:
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// The above copyright notice and this permission notice shall be included in
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// all copies or substantial portions of the Software.
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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// THE SOFTWARE.
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//
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// $Revision$
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// $Date$
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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`ifdef BSV_ASYNC_RESET
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`define BSV_ARESET_EDGE_META or `BSV_RESET_EDGE RST
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`else
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`define BSV_ARESET_EDGE_META
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`endif
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`ifdef BSV_RESET_FIFO_HEAD
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`define BSV_ARESET_EDGE_HEAD `BSV_ARESET_EDGE_META
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`else
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`define BSV_ARESET_EDGE_HEAD
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`endif
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`ifdef BSV_RESET_FIFO_ARRAY
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`define BSV_ARESET_EDGE_ARRAY `BSV_ARESET_EDGE_META
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`else
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`define BSV_ARESET_EDGE_ARRAY
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`endif
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// Sized fifo. Model has output register which improves timing
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module SizedFIFO(CLK, RST, D_IN, ENQ, FULL_N, D_OUT, DEQ, EMPTY_N, CLR);
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parameter p1width = 1; // data width
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parameter p2depth = 3;
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parameter p3cntr_width = 1; // log(p2depth-1)
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// The -1 is allowed since this model has a fast output register
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parameter guarded = 1;
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localparam p2depth2 = (p2depth >= 2) ? (p2depth -2) : 0 ;
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input CLK;
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input RST;
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input CLR;
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input [p1width - 1 : 0] D_IN;
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input ENQ;
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input DEQ;
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output FULL_N;
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output EMPTY_N;
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output [p1width - 1 : 0] D_OUT;
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reg not_ring_full;
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reg ring_empty;
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reg [p3cntr_width-1 : 0] head;
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wire [p3cntr_width-1 : 0] next_head;
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reg [p3cntr_width-1 : 0] tail;
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wire [p3cntr_width-1 : 0] next_tail;
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// if the depth is too small, don't create an ill-sized array;
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// instead, make a 1-sized array and let the initial block report an error
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reg [p1width - 1 : 0] arr[0: p2depth2];
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reg [p1width - 1 : 0] D_OUT;
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reg hasodata;
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wire [p3cntr_width-1:0] depthLess2 = p2depth2[p3cntr_width-1:0] ;
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wire [p3cntr_width-1 : 0] incr_tail;
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wire [p3cntr_width-1 : 0] incr_head;
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assign incr_tail = tail + 1'b1 ;
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assign incr_head = head + 1'b1 ;
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assign next_head = (head == depthLess2 ) ? {p3cntr_width{1'b0}} : incr_head ;
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assign next_tail = (tail == depthLess2 ) ? {p3cntr_width{1'b0}} : incr_tail ;
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assign EMPTY_N = hasodata;
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assign FULL_N = not_ring_full;
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`ifdef BSV_NO_INITIAL_BLOCKS
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`else // not BSV_NO_INITIAL_BLOCKS
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// synopsys translate_off
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initial
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begin : initial_block
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integer i;
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D_OUT = {((p1width + 1)/2){2'b10}} ;
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ring_empty = 1'b1;
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not_ring_full = 1'b1;
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hasodata = 1'b0;
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head = {p3cntr_width {1'b0}} ;
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tail = {p3cntr_width {1'b0}} ;
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for (i = 0; i <= p2depth2; i = i + 1)
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begin
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arr[i] = D_OUT ;
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end
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end
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// synopsys translate_on
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`endif // BSV_NO_INITIAL_BLOCKS
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always @(posedge CLK `BSV_ARESET_EDGE_META)
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begin
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if (RST == `BSV_RESET_VALUE)
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begin
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head <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ;
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tail <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ;
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ring_empty <= `BSV_ASSIGNMENT_DELAY 1'b1;
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not_ring_full <= `BSV_ASSIGNMENT_DELAY 1'b1;
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hasodata <= `BSV_ASSIGNMENT_DELAY 1'b0;
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end // if (RST == `BSV_RESET_VALUE)
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else
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begin
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casez ({CLR, DEQ, ENQ, hasodata, ring_empty})
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// Clear operation
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5'b1????: begin
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head <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ;
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tail <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ;
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ring_empty <= `BSV_ASSIGNMENT_DELAY 1'b1;
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not_ring_full <= `BSV_ASSIGNMENT_DELAY 1'b1;
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hasodata <= `BSV_ASSIGNMENT_DELAY 1'b0;
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end
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// -----------------------
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// DEQ && ENQ case -- change head and tail if added to ring
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5'b011?0: begin
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tail <= `BSV_ASSIGNMENT_DELAY next_tail;
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head <= `BSV_ASSIGNMENT_DELAY next_head;
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end
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// -----------------------
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// DEQ only and NO data is in ring
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5'b010?1: begin
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hasodata <= `BSV_ASSIGNMENT_DELAY 1'b0;
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end
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// DEQ only and data is in ring (move the head pointer)
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5'b010?0: begin
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head <= `BSV_ASSIGNMENT_DELAY next_head;
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not_ring_full <= `BSV_ASSIGNMENT_DELAY 1'b1;
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ring_empty <= `BSV_ASSIGNMENT_DELAY next_head == tail ;
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end
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// -----------------------
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// ENQ only when empty
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5'b0010?: begin
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hasodata <= `BSV_ASSIGNMENT_DELAY 1'b1;
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end
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// ENQ only when not empty
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5'b0011?: begin
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if ( not_ring_full ) // Drop this test to save redundant test
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// but be warnned that with test fifo overflow causes loss of new data
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// while without test fifo drops all but head entry! (pointer overflow)
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begin
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tail <= `BSV_ASSIGNMENT_DELAY next_tail;
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ring_empty <= `BSV_ASSIGNMENT_DELAY 1'b0;
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not_ring_full <= `BSV_ASSIGNMENT_DELAY ! (next_tail == head) ;
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end
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end
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endcase
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end // else: !if(RST == `BSV_RESET_VALUE)
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end // always @ (posedge CLK)
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// Update the fast data out register
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always @(posedge CLK `BSV_ARESET_EDGE_HEAD)
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begin
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`ifdef BSV_RESET_FIFO_HEAD
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if (RST == `BSV_RESET_VALUE)
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begin
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D_OUT <= `BSV_ASSIGNMENT_DELAY {p1width {1'b0}} ;
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end // if (RST == `BSV_RESET_VALUE)
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else
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`endif
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begin
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casez ({CLR, DEQ, ENQ, hasodata, ring_empty})
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// DEQ && ENQ cases
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5'b011?0: begin D_OUT <= `BSV_ASSIGNMENT_DELAY arr[head]; end
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5'b011?1: begin D_OUT <= `BSV_ASSIGNMENT_DELAY D_IN; end
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// DEQ only and data is in ring
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5'b010?0: begin D_OUT <= `BSV_ASSIGNMENT_DELAY arr[head]; end
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// ENQ only when empty
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5'b0010?: begin D_OUT <= `BSV_ASSIGNMENT_DELAY D_IN; end
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endcase
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end // else: !if(RST == `BSV_RESET_VALUE)
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end // always @ (posedge CLK)
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// Update the memory array reset is OFF
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always @(posedge CLK `BSV_ARESET_EDGE_ARRAY)
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begin: array
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`ifdef BSV_RESET_FIFO_ARRAY
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if (RST == `BSV_RESET_VALUE)
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begin: rst_array
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integer i;
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for (i = 0; i <= p2depth2 && p2depth > 2; i = i + 1)
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begin
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arr[i] <= `BSV_ASSIGNMENT_DELAY {p1width {1'b0}} ;
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end
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end // if (RST == `BSV_RESET_VALUE)
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else
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`endif
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begin
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if (!CLR && ENQ && ((DEQ && !ring_empty) || (!DEQ && hasodata && not_ring_full)))
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begin
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arr[tail] <= `BSV_ASSIGNMENT_DELAY D_IN;
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end
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end // else: !if(RST == `BSV_RESET_VALUE)
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end // always @ (posedge CLK)
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// synopsys translate_off
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always@(posedge CLK)
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begin: error_checks
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reg deqerror, enqerror ;
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deqerror = 0;
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enqerror = 0;
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if (RST == ! `BSV_RESET_VALUE)
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begin
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if ( ! EMPTY_N && DEQ )
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begin
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deqerror = 1 ;
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$display( "Warning: SizedFIFO: %m -- Dequeuing from empty fifo" ) ;
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end
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if ( ! FULL_N && ENQ && (!DEQ || guarded) )
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begin
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enqerror = 1 ;
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$display( "Warning: SizedFIFO: %m -- Enqueuing to a full fifo" ) ;
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end
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end
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end // block: error_checks
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// synopsys translate_on
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// synopsys translate_off
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// Some assertions about parameter values
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initial
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begin : parameter_assertions
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integer ok ;
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ok = 1 ;
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if ( p2depth <= 1)
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begin
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ok = 0;
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$display ( "Warning SizedFIFO: %m -- depth parameter increased from %0d to 2", p2depth);
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end
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if ( p3cntr_width <= 0 )
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begin
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ok = 0;
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$display ( "ERROR SizedFIFO: %m -- width parameter must be greater than 0" ) ;
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end
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if ( ok == 0 ) $finish ;
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end // initial begin
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// synopsys translate_on
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endmodule
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