From f02e9af515fef389e8ab813d0eecda6628689b00 Mon Sep 17 00:00:00 2001 From: rsnikhil Date: Wed, 11 Mar 2020 22:42:18 -0400 Subject: [PATCH] Improved avoidance of initial timer interrupt in MMIOPlatform; removed spurios MSTATUS TV report on CSRRS/C with rs1==0 --- .../Verilog_RTL/mkCore.v | 2508 +++++++------- .../Verilog_RTL/mkProc.v | 2646 +++++++------- src_Core/CPU/MMIOPlatform.bsv | 24 +- .../RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv | 5 +- src_SSITH_P3/Verilog_RTL/mkCore.v | 2859 ++++++++-------- src_SSITH_P3/Verilog_RTL/mkCoreW.v | 20 +- src_SSITH_P3/Verilog_RTL/mkP3_Core.v | 2 +- src_SSITH_P3/Verilog_RTL/mkProc.v | 2546 +++++++------- .../Verilog_RTL/mkTrace_Data2_to_Trace_Data.v | 70 +- src_SSITH_P3/Verilog_RTL_sim/mkCore.v | 3040 +++++++++-------- src_SSITH_P3/Verilog_RTL_sim/mkCoreW.v | 20 +- src_SSITH_P3/Verilog_RTL_sim/mkP3_Core.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkProc.v | 2572 +++++++------- .../mkTrace_Data2_to_Trace_Data.v | 70 +- src_SSITH_P3/xilinx_ip/hdl/mkCore.v | 2859 ++++++++-------- src_SSITH_P3/xilinx_ip/hdl/mkCoreW.v | 20 +- src_SSITH_P3/xilinx_ip/hdl/mkP3_Core.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkProc.v | 2546 +++++++------- .../hdl/mkTrace_Data2_to_Trace_Data.v | 70 +- 19 files changed, 10931 insertions(+), 10950 deletions(-) diff --git a/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkCore.v b/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkCore.v index 6be85e7..3a44eb8 100644 --- a/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkCore.v +++ b/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkCore.v @@ -4129,7 +4129,7 @@ module mkCore(CLK, curData__h195305, rVal1__h615934, rVal1__h640779, - trap_val__h709616, + trap_val__h709719, x__h200348; reg [51 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q10, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q12, @@ -4211,7 +4211,7 @@ module mkCore(CLK, CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q284, CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q280, IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13043, - IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13691; + IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13701; reg [15 : 0] SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1367, SEL_ARR_mmio_dataRespQ_data_0_109_BITS_15_TO_0_ETC___d1417; reg [11 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q272, @@ -4220,7 +4220,7 @@ module mkCore(CLK, CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q278, CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q221, CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q275, - CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q229, + CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q228, IF_fetchStage_pipelines_0_first__2928_BITS_172_ETC___d13125; reg [10 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q11, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q7, @@ -4296,9 +4296,9 @@ module mkCore(CLK, reg [5 : 0] CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q266, CASE_mmio_cRqQ_data_0_BITS_77_TO_76_0_mmio_cRq_ETC__q1, CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q263, - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768; - reg [4 : 0] IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14221, - IF_fetchStage_pipelines_1_first__2937_BITS_191_ETC___d14384; + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778; + reg [4 : 0] IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14231, + IF_fetchStage_pipelines_1_first__2937_BITS_191_ETC___d14394; reg [3 : 0] CASE_IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2956__ETC__q227, CASE_checkForException_3160_BITS_3_TO_0_0_chec_ETC__q226, CASE_coreFix_memExe_dTlbprocResp_BITS_105_TO__ETC__q13, @@ -4307,11 +4307,11 @@ module mkCore(CLK, CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q264, CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q260, CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q261, - IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14224, + IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14234, IF_fetchStage_pipelines_0_first__2928_BIT_68_2_ETC___d13266, - IF_fetchStage_pipelines_1_first__2937_BITS_191_ETC___d14385, - i__h708608, - i__h708768; + IF_fetchStage_pipelines_1_first__2937_BITS_191_ETC___d14395, + i__h708711, + i__h708871; reg [2 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q270, CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q222, CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q267, @@ -4323,7 +4323,7 @@ module mkCore(CLK, CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q279, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q255, CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q225, - CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q228, + CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q229, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10828, x__h290394, x__h296164; @@ -4397,7 +4397,7 @@ module mkCore(CLK, CASE_guard96447_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q84, CASE_guard96447_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q83, CASE_guard98956_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137, - CASE_k74927_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232, + CASE_k75030_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6542, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6555, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6559, @@ -4435,31 +4435,31 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d11133, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d8507, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d8520, - IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13570, - IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13626, - IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14215, - IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14218, - IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13574, - IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13598, - IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13631, - IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13940, - IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13961, - IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13978, - IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14031, - IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14033, - IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14047, - IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14054, - IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14123, - IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14134, - IF_fetchStage_pipelines_1_first__2937_BITS_191_ETC___d14382, - IF_fetchStage_pipelines_1_first__2937_BITS_191_ETC___d14383, - IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13989, - IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d14120, - IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d14145, - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__354_ETC___d13591, - SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__292_ETC___d14081, - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3548_co_ETC___d13558, - SEL_ARR_fetchStage_pipelines_0_canDeq__2926_AN_ETC___d13867; + IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13580, + IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13636, + IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14225, + IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14228, + IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13584, + IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13608, + IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13641, + IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13950, + IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13971, + IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13988, + IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14041, + IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14043, + IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14057, + IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14064, + IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14133, + IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14144, + IF_fetchStage_pipelines_1_first__2937_BITS_191_ETC___d14392, + IF_fetchStage_pipelines_1_first__2937_BITS_191_ETC___d14393, + IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13999, + IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d14130, + IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d14155, + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__355_ETC___d13601, + SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__292_ETC___d14091, + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3558_co_ETC___d13568, + SEL_ARR_fetchStage_pipelines_0_canDeq__2926_AN_ETC___d13877; wire [581 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3343; wire [569 : 0] IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2538, IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2549, @@ -4468,20 +4468,21 @@ module mkCore(CLK, wire [517 : 0] SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3038; wire [511 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2236, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3031, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15300; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15310; wire [447 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2033; wire [383 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2231, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3022, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15291; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15301; wire [321 : 0] basicExec___d12101, basicExec___d12775; wire [319 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2028; wire [255 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2226, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3013, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15282, + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15292, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d11187, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d11200, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d11193; wire [191 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2023; + wire [181 : 0] fetchStage_pipelines_0_first__2928_BIT_173_304_ETC___d13522; wire [127 : 0] b__h608523, b__h608599, b__h608700, b__h608712, x__h609552; wire [68 : 0] execFpuSimple___d11167; wire [65 : 0] IF_IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_NOT_ETC___d627; @@ -4516,7 +4517,7 @@ module mkCore(CLK, IF_coreFix_memExe_lsq_firstLd__285_BIT_96_350__ETC___d1386, IF_coreFix_memExe_lsq_firstLd__285_BIT_96_350__ETC___d1435, IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8, - IF_rob_deqPort_0_canDeq__4986_THEN_IF_NOT_rob__ETC___d15095, + IF_rob_deqPort_0_canDeq__4996_THEN_IF_NOT_rob__ETC___d15105, _theResult___fst__h608923, _theResult___snd__h608924, a___1__h608537, @@ -4526,16 +4527,16 @@ module mkCore(CLK, b___1__h608538, b___1__h608989, b__h608376, - base__h711516, - base__h711536, + base__h711619, + base__h711639, coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d11256, coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d11257, data___1__h479776, data___1__h480708, data__h479264, data__h480196, - fallthrough_pc__h671219, - fallthrough_pc__h686965, + fallthrough_pc__h671322, + fallthrough_pc__h687068, fcsr_csr__read__h616236, fflags_csr__read__h616211, frm_csr__read__h616222, @@ -4552,8 +4553,8 @@ module mkCore(CLK, n__read__h618215, n__read__h618406, n__read__h6331, - n__read__h720223, - next_pc__h719433, + n__read__h720326, + next_pc__h719536, q___1__h480783, rVal1__h487145, rVal2__h487146, @@ -4566,7 +4567,7 @@ module mkCore(CLK, res_data__h433924, resp_addr__h296630, rg_tdata1__read__h619066, - rob_deqPort_0_deq_data__4456_BITS_353_TO_290_4_ETC___d14959, + rob_deqPort_0_deq_data__4466_BITS_353_TO_290_4_ETC___d14969, robdeqPort_0_deq_data_BITS_95_TO_32__q262, satp_csr__read__h616939, scause_csr__read__h616736, @@ -4601,14 +4602,14 @@ module mkCore(CLK, x__h623647, x__h646276, x__h646277, - x__h704922, + x__h705025, x_addr__h318727, x_quotient__h479960, x_reg_ifc__read__h616341, x_remainder__h479961, y__h626448, y__h648785, - y__h723317, + y__h723420, y_avValue__h183779, y_avValue__h184498, y_avValue__h484114, @@ -4618,11 +4619,11 @@ module mkCore(CLK, y_avValue__h621656, y_avValue__h640724, y_avValue__h644296, - y_avValue_new_pc__h711297, - y_avValue_new_pc__h711483, - y_avValue_snd_snd_snd_snd_snd__h722711, - y_avValue_snd_snd_snd_snd_snd__h723370, - y_avValue_snd_snd_snd_snd_snd__h723399; + y_avValue_new_pc__h711400, + y_avValue_new_pc__h711586, + y_avValue_snd_snd_snd_snd_snd__h722814, + y_avValue_snd_snd_snd_snd_snd__h723473, + y_avValue_snd_snd_snd_snd_snd__h723502; wire [62 : 0] IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10763, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9993, r1__read__h619391, @@ -4969,8 +4970,8 @@ module mkCore(CLK, wire [42 : 0] r1__read__h620594; wire [41 : 0] r1__read__h620596; wire [40 : 0] r1__read__h620598; - wire [37 : 0] IF_fetchStage_pipelines_0_first__2928_BIT_160__ETC___d14227, - IF_fetchStage_pipelines_1_first__2937_BIT_160__ETC___d14388; + wire [37 : 0] IF_fetchStage_pipelines_0_first__2928_BIT_160__ETC___d14237, + IF_fetchStage_pipelines_1_first__2937_BIT_160__ETC___d14398; wire [31 : 0] coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q4, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q3, coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q5, @@ -4985,11 +4986,11 @@ module mkCore(CLK, x__h433934, x__h75785, x_data__h65634, - x_data_imm__h682272, - x_data_imm__h698176; + x_data_imm__h682375, + x_data_imm__h698279; wire [29 : 0] r1__read__h619419, r1__read__h620602; wire [27 : 0] r1__read__h620604; - wire [24 : 0] NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d14273, + wire [24 : 0] NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d14283, sfd__h358941, sfd__h367523, sfd__h376707, @@ -5090,7 +5091,7 @@ module mkCore(CLK, out_sfd__h468527, out_sfd__h477163; wire [19 : 0] r1__read__h620539; - wire [12 : 0] fetchStage_pipelines_1_first__2937_BIT_173_369_ETC___d13775; + wire [12 : 0] fetchStage_pipelines_1_first__2937_BIT_173_370_ETC___d13785; wire [11 : 0] IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992, IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10542, IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9057, @@ -5125,10 +5126,10 @@ module mkCore(CLK, enabled_ints___1__h658445, enabled_ints__h658491, pend_ints__h658030, - renaming_spec_bits__h690391, + renaming_spec_bits__h690494, result__h653739, result__h653790, - spec_bits__h693518, + spec_bits__h693621, w__h653734, x__h369120, x__h414817, @@ -5140,10 +5141,10 @@ module mkCore(CLK, x__h653789, y__h653768, y__h658457, - y__h693531, - y_avValue_fst__h686815, - y_avValue_snd_fst__h687089, - y_avValue_snd_fst__h687124; + y__h693634, + y_avValue_fst__h686918, + y_avValue_snd_fst__h687192, + y_avValue_snd_fst__h687227; wire [10 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10647, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10649, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9167, @@ -5430,11 +5431,11 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4574, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7358, IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2172, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d15326, + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d15336, x__h184873, - x__h711531; - wire [4 : 0] IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d14441, - IF_rob_deqPort_0_canDeq__4986_THEN_IF_NOT_rob__ETC___d15185, + x__h711634; + wire [4 : 0] IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d14451, + IF_rob_deqPort_0_canDeq__4996_THEN_IF_NOT_rob__ETC___d15195, _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5265, _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6657, _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d8049, @@ -5451,8 +5452,8 @@ module mkCore(CLK, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6669, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d8061, checkForException___d13160, - checkForException___d13797, - fflags__h723294, + checkForException___d13807, + fflags__h723397, r1__read__h620942, res_fflags__h342523, res_fflags__h388225, @@ -5462,9 +5463,9 @@ module mkCore(CLK, x__h158639, x__h161455, x__h291827, - y_avValue_fst__h722271, - y_avValue_fst__h723213, - y_avValue_fst__h723241; + y_avValue_fst__h722374, + y_avValue_fst__h723316, + y_avValue_fst__h723344; wire [3 : 0] IF_IF_coreFix_memExe_dTlb_procResp__740_BIT_11_ETC___d1875, IF_IF_coreFix_memExe_dTlb_procResp__740_BIT_11_ETC___d1877, IF_IF_coreFix_memExe_dTlb_procResp__740_BIT_11_ETC___d1879, @@ -5491,7 +5492,7 @@ module mkCore(CLK, IF_coreFix_memExe_dTlb_procResp__740_BITS_105__ETC___d1820, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1263, IF_fetchStage_pipelines_0_first__2928_BIT_68_2_ETC___d13385, - cause_code__h708593, + cause_code__h708696, vm_mode_reg__read__h620545; wire [2 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2567, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2886, @@ -5504,7 +5505,7 @@ module mkCore(CLK, x_decodeInfo_frm__h661526; wire [1 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2882, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1216, - IF_rob_deqPort_0_canDeq__4986_THEN_IF_NOT_rob__ETC___d15207, + IF_rob_deqPort_0_canDeq__4996_THEN_IF_NOT_rob__ETC___d15217, IF_sfdin04540_BIT_33_THEN_2_ELSE_0__q57, IF_sfdin16488_BIT_4_THEN_2_ELSE_0__q131, IF_sfdin22306_BIT_33_THEN_2_ELSE_0__q67, @@ -5547,18 +5548,18 @@ module mkCore(CLK, guard__h577113, guard__h586425, guard__h595494, - prv__h724809, - prv__h724853, + prv__h724912, + prv__h724956, r1__read_BITS_13_TO_12___h661711, sbIdx__h158518, v__h609622, v__h609632, v__h610690, - x__h719602, - x__h723542, - y_avValue_snd_snd_snd_fst__h722705, - y_avValue_snd_snd_snd_fst__h723364, - y_avValue_snd_snd_snd_fst__h723393; + x__h719705, + x__h723645, + y_avValue_snd_snd_snd_fst__h722808, + y_avValue_snd_snd_snd_fst__h723467, + y_avValue_snd_snd_snd_fst__h723496; wire IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5165, IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5215, IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6557, @@ -5578,8 +5579,8 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9096, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9811, IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d13204, - IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d13852, - IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d13888, + IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d13862, + IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d13898, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10048, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10049, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10585, @@ -5643,11 +5644,11 @@ module mkCore(CLK, IF_NOT_coreFix_memExe_bypassWire_0_whas__584_5_ETC___d1667, IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2114, IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2131, - IF_NOT_fetchStage_pipelines_0_canDeq__2926_292_ETC___d13995, - IF_NOT_fetchStage_pipelines_0_canDeq__2926_292_ETC___d14003, - IF_NOT_fetchStage_pipelines_1_first__2937_BITS_ETC___d13925, - IF_NOT_fetchStage_pipelines_1_first__2937_BITS_ETC___d14002, - IF_NOT_rob_deqPort_1_deq_data__4993_BIT_25_499_ETC___d15198, + IF_NOT_fetchStage_pipelines_0_canDeq__2926_292_ETC___d14005, + IF_NOT_fetchStage_pipelines_0_canDeq__2926_292_ETC___d14013, + IF_NOT_fetchStage_pipelines_1_first__2937_BITS_ETC___d13935, + IF_NOT_fetchStage_pipelines_1_first__2937_BITS_ETC___d14012, + IF_NOT_rob_deqPort_1_deq_data__5003_BIT_25_500_ETC___d15208, IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10047, IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10583, IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10816, @@ -5759,18 +5760,18 @@ module mkCore(CLK, IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d3745, IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3730, IF_coreFix_memExe_respLrScAmoQ_enqReq_lat_1_wh_ETC___d3654, - IF_fetchStage_RDY_pipelines_0_first__2925_AND__ETC___d13545, - IF_fetchStage_RDY_pipelines_1_first__2936_AND__ETC___d13927, - IF_fetchStage_RDY_pipelines_1_first__2936_AND__ETC___d13992, - IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14040, - IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d14161, + IF_fetchStage_RDY_pipelines_0_first__2925_AND__ETC___d13555, + IF_fetchStage_RDY_pipelines_1_first__2936_AND__ETC___d13937, + IF_fetchStage_RDY_pipelines_1_first__2936_AND__ETC___d14002, + IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14050, + IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d14171, IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmio_c_ETC___d339, IF_mmio_cRsQ_enqReq_lat_1_whas__74_THEN_mmio_c_ETC___d783, IF_mmio_dataReqQ_enqReq_lat_1_whas__7_THEN_mmi_ETC___d46, IF_mmio_dataRespQ_enqReq_lat_1_whas__92_THEN_m_ETC___d201, IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmio_p_ETC___d642, IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_mmio_p_ETC___d491, - IF_rob_deqPort_1_canDeq__4990_THEN_IF_NOT_rob__ETC___d15199, + IF_rob_deqPort_1_canDeq__5000_THEN_IF_NOT_rob__ETC___d15209, NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5317, NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5345, NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d6709, @@ -5778,9 +5779,9 @@ module mkCore(CLK, NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d8101, NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d8129, NOT_IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_295_ETC___d13442, - NOT_IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_295_ETC___d13533, - NOT_IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_295_ETC___d13824, - NOT_IF_NOT_rob_deqPort_0_canDeq__4986_4987_OR__ETC___d15204, + NOT_IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_295_ETC___d13543, + NOT_IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_295_ETC___d13834, + NOT_IF_NOT_rob_deqPort_0_canDeq__4996_4997_OR__ETC___d15214, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10167, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10876, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10918, @@ -5794,8 +5795,8 @@ module mkCore(CLK, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11117, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8667, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9397, - NOT_IF_rob_deqPort_0_deq_data__4456_BITS_97_TO_ETC___d14962, - NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13593, + NOT_IF_rob_deqPort_0_deq_data__4466_BITS_97_TO_ETC___d14972, + NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13603, NOT_coreFix_aluExe_0_bypassWire_0_whas__2366_2_ETC___d12393, NOT_coreFix_aluExe_0_bypassWire_0_whas__2366_2_ETC___d12423, NOT_coreFix_aluExe_1_bypassWire_0_whas__1510_1_ETC___d11537, @@ -5807,7 +5808,7 @@ module mkCore(CLK, NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4519, NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7303, NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__48_ETC___d8540, - NOT_coreFix_fpuMulDivExe_0_rsFpuMulDiv_canEnq__ETC___d13936, + NOT_coreFix_fpuMulDivExe_0_rsFpuMulDiv_canEnq__ETC___d13946, NOT_coreFix_memExe_bypassWire_0_whas__584_590__ETC___d1611, NOT_coreFix_memExe_bypassWire_0_whas__584_590__ETC___d1640, NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqMsh_ETC___d2554, @@ -5856,45 +5857,45 @@ module mkCore(CLK, NOT_coreFix_memExe_respLrScAmoQ_clearReq_dummy_ETC___d3643, NOT_coreFix_memExe_respLrScAmoQ_enqReq_dummy2__ETC___d3685, NOT_coreFix_memExe_respLrScAmoQ_full_977_978_A_ETC___d2110, - NOT_coreFix_memExe_rsMem_canEnq__3561_3623_OR__ETC___d13937, + NOT_coreFix_memExe_rsMem_canEnq__3571_3633_OR__ETC___d13947, NOT_csrf_fs_reg_read__1726_EQ_0_3149_3150_OR_N_ETC___d13435, - NOT_csrf_fs_reg_read__1726_EQ_0_3149_3150_OR_N_ETC___d13531, - NOT_csrf_fs_reg_read__1726_EQ_0_3149_3150_OR_N_ETC___d13822, - NOT_csrf_prv_reg_read__2956_ULE_1_4597_4661_OR_ETC___d14665, - NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d13908, - NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d13919, - NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d13958, - NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d13975, - NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14096, - NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14115, - NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14167, - NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14299, - NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14301, - NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14312, - NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14348, - NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14368, - NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14376, - NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14397, - NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14420, + NOT_csrf_fs_reg_read__1726_EQ_0_3149_3150_OR_N_ETC___d13541, + NOT_csrf_fs_reg_read__1726_EQ_0_3149_3150_OR_N_ETC___d13832, + NOT_csrf_prv_reg_read__2956_ULE_1_4607_4671_OR_ETC___d14675, + NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d13918, + NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d13929, + NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d13968, + NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d13985, + NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14106, + NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14125, + NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14177, + NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14309, + NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14311, + NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14322, + NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14358, + NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14378, + NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14386, + NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14407, + NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14430, NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13429, - NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13538, - NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13575, - NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13842, - NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13848, - NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d14000, - NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d14173, - NOT_fetchStage_pipelines_0_first__2928_BITS_32_ETC___d14197, - NOT_fetchStage_pipelines_0_first__2928_BIT_68__ETC___d13586, + NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13548, + NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13585, + NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13852, + NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13858, + NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d14010, + NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d14183, + NOT_fetchStage_pipelines_0_first__2928_BITS_32_ETC___d14207, + NOT_fetchStage_pipelines_0_first__2928_BIT_68__ETC___d13596, NOT_fetchStage_pipelines_1_canDeq__2934_2935_O_ETC___d12943, - NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d13833, - NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d13835, - NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d13946, - NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d13967, - NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d13984, - NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d14309, - NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d14371, - NOT_fetchStage_pipelines_1_first__2937_BITS_32_ETC___d14363, - NOT_fetchStage_pipelines_1_first__2937_BIT_68__ETC___d14306, + NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d13843, + NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d13845, + NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d13956, + NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d13977, + NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d13994, + NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d14319, + NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d14381, + NOT_fetchStage_pipelines_1_first__2937_BITS_32_ETC___d14373, + NOT_fetchStage_pipelines_1_first__2937_BIT_68__ETC___d14316, NOT_mmio_cRqQ_clearReq_dummy2_1_read__26_27_OR_ETC___d431, NOT_mmio_cRqQ_enqReq_dummy2_2_read__32_47_OR_I_ETC___d452, NOT_mmio_cRsQ_clearReq_dummy2_1_read__18_19_OR_ETC___d823, @@ -5910,18 +5911,18 @@ module mkCore(CLK, NOT_mmio_pRqQ_enqReq_dummy2_2_read__35_50_OR_I_ETC___d755, NOT_mmio_pRsQ_clearReq_dummy2_1_read__88_89_OR_ETC___d593, NOT_mmio_pRsQ_enqReq_dummy2_2_read__94_09_OR_I_ETC___d614, - NOT_regRenamingTable_rename_0_canRename__3518__ETC___d13617, - NOT_regRenamingTable_rename_0_canRename__3518__ETC___d13952, - NOT_regRenamingTable_rename_0_canRename__3518__ETC___d14007, - NOT_regRenamingTable_rename_1_canRename__3637__ETC___d14065, - NOT_rob_deqPort_0_canDeq__4986_4987_OR_regRena_ETC___d15025, - NOT_rob_deqPort_0_canDeq__4986_4987_OR_rob_deq_ETC___d15178, - NOT_rob_deqPort_0_deq_data__4456_BITS_257_TO_2_ETC___d14778, - NOT_rob_deqPort_0_deq_data__4456_BITS_257_TO_2_ETC___d14972, - NOT_rob_deqPort_1_deq_data__4993_BIT_25_4994_4_ETC___d15022, - NOT_specTagManager_canClaim__3516_3601_OR_NOT__ETC___d14086, - NOT_specTagManager_canClaim__3516_3601_OR_NOT__ETC___d14151, - SEL_ARR_fetchStage_pipelines_0_canDeq__2926_AN_ETC___d13897, + NOT_regRenamingTable_rename_0_canRename__3528__ETC___d13627, + NOT_regRenamingTable_rename_0_canRename__3528__ETC___d13962, + NOT_regRenamingTable_rename_0_canRename__3528__ETC___d14017, + NOT_regRenamingTable_rename_1_canRename__3647__ETC___d14075, + NOT_rob_deqPort_0_canDeq__4996_4997_OR_regRena_ETC___d15035, + NOT_rob_deqPort_0_canDeq__4996_4997_OR_rob_deq_ETC___d15188, + NOT_rob_deqPort_0_deq_data__4466_BITS_257_TO_2_ETC___d14788, + NOT_rob_deqPort_0_deq_data__4466_BITS_257_TO_2_ETC___d14982, + NOT_rob_deqPort_1_deq_data__5003_BIT_25_5004_5_ETC___d15032, + NOT_specTagManager_canClaim__3526_3611_OR_NOT__ETC___d14096, + NOT_specTagManager_canClaim__3526_3611_OR_NOT__ETC___d14161, + SEL_ARR_fetchStage_pipelines_0_canDeq__2926_AN_ETC___d13907, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10243, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10244, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8758, @@ -5955,11 +5956,11 @@ module mkCore(CLK, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6361, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7360, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7753, - _0_OR_NOT_fetchStage_pipelines_0_first__2928_BI_ETC___d14014, - _0_OR_NOT_fetchStage_pipelines_1_first__2937_BI_ETC___d14099, - _0_OR_fetchStage_RDY_pipelines_0_first__2925_39_ETC___d13922, - _0b0_CONCAT_csrf_medeleg_15_reg_read__1825_1826_ETC___d14634, - _0b0_CONCAT_csrf_mideleg_11_reg_read__1833_1834_ETC___d14615, + _0_OR_NOT_fetchStage_pipelines_0_first__2928_BI_ETC___d14024, + _0_OR_NOT_fetchStage_pipelines_1_first__2937_BI_ETC___d14109, + _0_OR_fetchStage_RDY_pipelines_0_first__2925_39_ETC___d13932, + _0b0_CONCAT_csrf_medeleg_15_reg_read__1825_1826_ETC___d14644, + _0b0_CONCAT_csrf_mideleg_11_reg_read__1833_1834_ETC___d14625, _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4108, _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4109, _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5280, @@ -6026,7 +6027,7 @@ module mkCore(CLK, coreFix_aluExe_0_bypassWire_3_wget__2395_BITS__ETC___d12424, coreFix_aluExe_0_dispToRegQ_RDY_first__2344_AN_ETC___d12435, coreFix_aluExe_0_exeToFinQ_RDY_first__2811_AND_ETC___d12851, - coreFix_aluExe_0_rsAlu_approximateCount__3552__ETC___d13554, + coreFix_aluExe_0_rsAlu_approximateCount__3562__ETC___d13564, coreFix_aluExe_1_bypassWire_0_wget__1511_BITS__ETC___d11513, coreFix_aluExe_1_bypassWire_0_wget__1511_BITS__ETC___d11554, coreFix_aluExe_1_bypassWire_1_wget__1524_BITS__ETC___d11526, @@ -6060,7 +6061,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ_first__482_BI_ETC___d11047, coreFix_fpuMulDivExe_0_regToExeQ_first__482_BI_ETC___d11089, coreFix_fpuMulDivExe_0_regToExeQ_first__482_BI_ETC___d11131, - coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__40_ETC___d14106, + coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__40_ETC___d14116, coreFix_memExe_bypassWire_0_wget__585_BITS_70__ETC___d1587, coreFix_memExe_bypassWire_0_wget__585_BITS_70__ETC___d1627, coreFix_memExe_bypassWire_1_wget__598_BITS_70__ETC___d1600, @@ -6132,48 +6133,48 @@ module mkCore(CLK, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1271, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1275, coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2_re_ETC___d3670, - coreFix_memExe_stb_isEmpty__011_AND_coreFix_me_ETC___d14783, + coreFix_memExe_stb_isEmpty__011_AND_coreFix_me_ETC___d14793, csrf_fs_reg_read__1726_EQ_0_3149_AND_fetchStag_ETC___d13197, - csrf_fs_reg_read__1726_EQ_0_3149_AND_fetchStag_ETC___d13610, - csrf_fs_reg_read__1726_EQ_0_3149_AND_fetchStag_ETC___d13886, - csrf_prv_reg_read__2956_ULE_1_4597_AND_IF_comm_ETC___d14636, - csrf_prv_reg_read__2956_ULE_1___d14597, + csrf_fs_reg_read__1726_EQ_0_3149_AND_fetchStag_ETC___d13620, + csrf_fs_reg_read__1726_EQ_0_3149_AND_fetchStag_ETC___d13896, + csrf_prv_reg_read__2956_ULE_1_4607_AND_IF_comm_ETC___d14646, + csrf_prv_reg_read__2956_ULE_1___d14607, csrf_prv_reg_read__2956_ULT_IF_fetchStage_pipe_ETC___d13192, - fetchStage_RDY_pipelines_0_first__2925_AND_NOT_ETC___d13541, + fetchStage_RDY_pipelines_0_first__2925_AND_NOT_ETC___d13551, fetchStage_RDY_pipelines_0_first__2925_AND_epo_ETC___d13407, - fetchStage_RDY_pipelines_0_first__2925_AND_fet_ETC___d13607, - fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14097, - fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14176, - fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14295, - fetchStage_pipelines_0_canDeq__2926_AND_fetchS_ETC___d14165, - fetchStage_pipelines_0_canDeq__2926_AND_regRen_ETC___d14103, - fetchStage_pipelines_0_canDeq__2926_AND_regRen_ETC___d14110, - fetchStage_pipelines_0_canDeq__2926_AND_regRen_ETC___d14131, - fetchStage_pipelines_0_canDeq__2926_AND_regRen_ETC___d14142, - fetchStage_pipelines_0_canDeq__2926_AND_regRen_ETC___d14431, - fetchStage_pipelines_0_canDeq__2926_AND_specTa_ETC___d14259, + fetchStage_RDY_pipelines_0_first__2925_AND_fet_ETC___d13617, + fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14107, + fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14186, + fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14305, + fetchStage_pipelines_0_canDeq__2926_AND_fetchS_ETC___d14175, + fetchStage_pipelines_0_canDeq__2926_AND_regRen_ETC___d14113, + fetchStage_pipelines_0_canDeq__2926_AND_regRen_ETC___d14120, + fetchStage_pipelines_0_canDeq__2926_AND_regRen_ETC___d14141, + fetchStage_pipelines_0_canDeq__2926_AND_regRen_ETC___d14152, + fetchStage_pipelines_0_canDeq__2926_AND_regRen_ETC___d14441, + fetchStage_pipelines_0_canDeq__2926_AND_specTa_ETC___d14269, fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d13190, - fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d13841, - fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d13862, - fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d13934, - fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d14042, - fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d14048, - fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d14070, - fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d14077, - fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d14290, - fetchStage_pipelines_0_first__2928_BITS_199_TO_ETC___d13855, - fetchStage_pipelines_0_first__2928_BIT_68_2955_ETC___d13615, - fetchStage_pipelines_1_first__2937_BITS_194_TO_ETC___d14059, - fetchStage_pipelines_1_first__2937_BITS_199_TO_ETC___d13894, - fetchStage_pipelines_1_first__2937_BIT_68_3665_ETC___d14063, + fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d13851, + fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d13872, + fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d13944, + fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d14052, + fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d14058, + fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d14080, + fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d14087, + fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d14300, + fetchStage_pipelines_0_first__2928_BITS_199_TO_ETC___d13865, + fetchStage_pipelines_0_first__2928_BIT_68_2955_ETC___d13625, + fetchStage_pipelines_1_first__2937_BITS_194_TO_ETC___d14069, + fetchStage_pipelines_1_first__2937_BITS_199_TO_ETC___d13904, + fetchStage_pipelines_1_first__2937_BIT_68_3675_ETC___d14073, guard__h368985, guard__h414682, guard__h460377, guard__h508866, guard__h547719, guard__h587023, - idx__h690522, - k__h674927, + idx__h690625, + k__h675030, mmio_cRqQ_enqReq_dummy2_2_read__32_AND_IF_mmio_ETC___d444, mmio_cRsQ_enqReq_dummy2_2_read__24_AND_IF_mmio_ETC___d836, mmio_dataPendQ_enqReq_dummy2_2_read__00_AND_IF_ETC___d312, @@ -6181,7 +6182,7 @@ module mkCore(CLK, mmio_dataRespQ_enqReq_dummy2_2_read__42_AND_IF_ETC___d254, mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13208, mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13461, - mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14170, + mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14180, mmio_pRqQ_enqReq_dummy2_2_read__35_AND_IF_mmio_ETC___d747, mmio_pRsQ_enqReq_dummy2_2_read__94_AND_IF_mmio_ETC___d606, msip__h75670, @@ -6192,29 +6193,29 @@ module mkCore(CLK, next_deqP___1__h336866, r1__read_BIT_20___h662375, r__h619423, - regRenamingTable_RDY_rename_0_getRename__3398__ETC___d14027, - regRenamingTable_RDY_rename_1_getRename__4083__ETC___d14101, - regRenamingTable_rename_0_canRename__3518_AND__ETC___d13588, - regRenamingTable_rename_0_canRename__3518_AND__ETC___d13602, - regRenamingTable_rename_0_canRename__3518_AND__ETC___d13917, - regRenamingTable_rename_0_canRename__3518_AND__ETC___d14056, - regRenamingTable_rename_0_canRename__3518_AND__ETC___d14188, - regRenamingTable_rename_0_canRename__3518_AND__ETC___d14201, - regRenamingTable_rename_0_canRename__3518_AND__ETC___d14206, - regRenamingTable_rename_0_canRename__3518_AND__ETC___d14211, - regRenamingTable_rename_0_canRename__3518_AND__ETC___d14231, - regRenamingTable_rename_0_canRename__3518_AND__ETC___d14235, - regRenamingTable_rename_0_canRename__3518_AND__ETC___d14241, - regRenamingTable_rename_0_canRename__3518_AND__ETC___d14245, - regRenamingTable_rename_0_canRename__3518_AND__ETC___d14253, - regRenamingTable_rename_0_canRename__3518_AND__ETC___d14429, - regRenamingTable_rename_1_canRename__3637_AND__ETC___d14308, - regRenamingTable_rename_1_canRename__3637_AND__ETC___d14392, - regRenamingTable_rename_1_canRename__3637_AND__ETC___d14402, - rob_RDY_enqPort_1_enq__4147_AND_NOT_fetchStage_ETC___d14155, - rob_enqPort_1_canEnq__3826_AND_epochManager_ch_ETC___d13831, - rob_enqPort_1_canEnq__3826_AND_epochManager_ch_ETC___d13965, - rob_enqPort_1_canEnq__3826_AND_epochManager_ch_ETC___d13982, + regRenamingTable_RDY_rename_0_getRename__3398__ETC___d14037, + regRenamingTable_RDY_rename_1_getRename__4093__ETC___d14111, + regRenamingTable_rename_0_canRename__3528_AND__ETC___d13598, + regRenamingTable_rename_0_canRename__3528_AND__ETC___d13612, + regRenamingTable_rename_0_canRename__3528_AND__ETC___d13927, + regRenamingTable_rename_0_canRename__3528_AND__ETC___d14066, + regRenamingTable_rename_0_canRename__3528_AND__ETC___d14198, + regRenamingTable_rename_0_canRename__3528_AND__ETC___d14211, + regRenamingTable_rename_0_canRename__3528_AND__ETC___d14216, + regRenamingTable_rename_0_canRename__3528_AND__ETC___d14221, + regRenamingTable_rename_0_canRename__3528_AND__ETC___d14241, + regRenamingTable_rename_0_canRename__3528_AND__ETC___d14245, + regRenamingTable_rename_0_canRename__3528_AND__ETC___d14251, + regRenamingTable_rename_0_canRename__3528_AND__ETC___d14255, + regRenamingTable_rename_0_canRename__3528_AND__ETC___d14263, + regRenamingTable_rename_0_canRename__3528_AND__ETC___d14439, + regRenamingTable_rename_1_canRename__3647_AND__ETC___d14318, + regRenamingTable_rename_1_canRename__3647_AND__ETC___d14402, + regRenamingTable_rename_1_canRename__3647_AND__ETC___d14412, + rob_RDY_enqPort_1_enq__4157_AND_NOT_fetchStage_ETC___d14165, + rob_enqPort_1_canEnq__3836_AND_epochManager_ch_ETC___d13841, + rob_enqPort_1_canEnq__3836_AND_epochManager_ch_ETC___d13975, + rob_enqPort_1_canEnq__3836_AND_epochManager_ch_ETC___d13992, v__h303939, v__h304457, v__h314453, @@ -6266,7 +6267,7 @@ module mkCore(CLK, { CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q247, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q248, !CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q249, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15300 } ; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15310 } ; assign RDY_dCacheToParent_rsToP_first = !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty ; @@ -6286,7 +6287,7 @@ module mkCore(CLK, assign dCacheToParent_rqToP_first = { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q256, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q257, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d15326 } ; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d15336 } ; assign RDY_dCacheToParent_rqToP_first = !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty ; @@ -9679,7 +9680,7 @@ module mkCore(CLK, // rule RL_commitStage_doCommitSystemInst assign CAN_FIRE_RL_commitStage_doCommitSystemInst = - coreFix_memExe_stb_isEmpty__011_AND_coreFix_me_ETC___d14783 && + coreFix_memExe_stb_isEmpty__011_AND_coreFix_me_ETC___d14793 && !commitStage_commitTrap[165] && !rob$deqPort_0_deq_data[167] && !rob$deqPort_0_deq_data[18] && @@ -9724,7 +9725,7 @@ module mkCore(CLK, // rule RL_commitStage_doCommitNormalInst assign CAN_FIRE_RL_commitStage_doCommitNormalInst = rob$RDY_deqPort_0_deq_data && - NOT_rob_deqPort_0_canDeq__4986_4987_OR_regRena_ETC___d15025 && + NOT_rob_deqPort_0_canDeq__4996_4997_OR_regRena_ETC___d15035 && !commitStage_commitTrap[165] && !rob$deqPort_0_deq_data[167] && !rob$deqPort_0_deq_data[18] && @@ -10702,11 +10703,11 @@ module mkCore(CLK, // rule RL_renameStage_doRenaming assign CAN_FIRE_RL_renameStage_doRenaming = (!fetchStage$pipelines_0_canDeq || - IF_fetchStage_RDY_pipelines_0_first__2925_AND__ETC___d13545) && - IF_NOT_fetchStage_pipelines_0_canDeq__2926_292_ETC___d13995 && - IF_NOT_fetchStage_pipelines_0_canDeq__2926_292_ETC___d14003 && - NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14167 && - mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14170 ; + IF_fetchStage_RDY_pipelines_0_first__2925_AND__ETC___d13555) && + IF_NOT_fetchStage_pipelines_0_canDeq__2926_292_ETC___d14005 && + IF_NOT_fetchStage_pipelines_0_canDeq__2926_292_ETC___d14013 && + NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14177 && + mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14180 ; assign WILL_FIRE_RL_renameStage_doRenaming = CAN_FIRE_RL_renameStage_doRenaming && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && @@ -10940,41 +10941,41 @@ module mkCore(CLK, assign MUX_csrf_external_int_pend_vec_1$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[257:253] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + (IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd16 || - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd29) ; assign MUX_csrf_external_int_pend_vec_3$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[257:253] == 5'd13 && - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd29 ; assign MUX_csrf_fflags_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[257:253] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + (IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd0 || - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd2) ; assign MUX_csrf_fs_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[257:253] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + (IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd0 || - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd1 || - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd2 || - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd8 || - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd18) ; assign MUX_csrf_ie_vec_1$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - csrf_prv_reg_read__2956_ULE_1_4597_AND_IF_comm_ETC___d14636 ; + csrf_prv_reg_read__2956_ULE_1_4607_AND_IF_comm_ETC___d14646 ; assign MUX_csrf_ie_vec_3$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_csrf_prv_reg_read__2956_ULE_1_4597_4661_OR_ETC___d14665 ; + NOT_csrf_prv_reg_read__2956_ULE_1_4607_4671_OR_ETC___d14675 ; assign MUX_csrf_prv_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && (rob$deqPort_0_deq_data[257:253] == 5'd19 || @@ -10982,13 +10983,13 @@ module mkCore(CLK, assign MUX_epochManager$updatePrevEpoch_0_update_1__SEL_2 = WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d14173 && - IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13598 ; + NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d14183 && + IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13608 ; assign MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2 = WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14299 && - NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d14309 && - IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13989 ; + NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14309 && + NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d14319 && + IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13999 ; assign MUX_flush_reservation$write_1__SEL_1 = WILL_FIRE_RL_prepareCachesAndTlbs && flush_reservation ; assign MUX_flush_tlbs$write_1__SEL_1 = @@ -11035,7 +11036,7 @@ module mkCore(CLK, assign MUX_commitStage_commitTrap$write_1__VAL_2 = { 1'd1, rob$deqPort_0_deq_data[353:290], - x__h704922, + x__h705025, rob$deqPort_0_deq_data[166], rob$deqPort_0_deq_data[166] ? CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q260 : @@ -11044,7 +11045,7 @@ module mkCore(CLK, assign MUX_commitStage_rg_serial_num$write_1__VAL_1 = commitStage_rg_serial_num + 64'd1 ; assign MUX_commitStage_rg_serial_num$write_1__VAL_2 = - commitStage_rg_serial_num + y__h723317 ; + commitStage_rg_serial_num + y__h723420 ; assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_1 = { fetchStage$pipelines_0_first[199:195], IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13043, @@ -11058,8 +11059,8 @@ module mkCore(CLK, 5'd10, sbAggr$eagerLookup_0_get } ; assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_2 = - (k__h674927 == 1'd0 && - fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14176) ? + (k__h675030 == 1'd0 && + fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14186) ? { fetchStage$pipelines_0_first[199:195], IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13043, fetchStage$pipelines_0_first[173], @@ -11073,13 +11074,13 @@ module mkCore(CLK, specTagManager$nextSpecTag, sbAggr$eagerLookup_0_get } : { fetchStage$pipelines_1_first[199:195], - IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13691, - fetchStage_pipelines_1_first__2937_BIT_173_369_ETC___d13775, + IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13701, + fetchStage_pipelines_1_first__2937_BIT_173_370_ETC___d13785, fetchStage$pipelines_1_first[160:128], fetchStage$pipelines_1_first[255:232], regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h690391, + renaming_spec_bits__h690494, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -11386,11 +11387,11 @@ module mkCore(CLK, MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_1 || MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_2 ; assign MUX_csrf_fflags_reg$write_1__VAL_2 = - csrf_fflags_reg | fflags__h723294 ; - always@(IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 or + csrf_fflags_reg | fflags__h723397 ; + always@(IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 or robdeqPort_0_deq_data_BITS_95_TO_32__q262) begin - case (IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768) + case (IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778) 6'd0, 6'd1, 6'd2: MUX_csrf_fs_reg$write_1__VAL_1 = 2'b11; default: MUX_csrf_fs_reg$write_1__VAL_1 = robdeqPort_0_deq_data_BITS_95_TO_32__q262[14:13]; @@ -11398,50 +11399,50 @@ module mkCore(CLK, end assign MUX_csrf_ie_vec_1$write_1__VAL_2 = (rob$deqPort_0_deq_data[257:253] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + (IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd8 || - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd18)) ? robdeqPort_0_deq_data_BITS_95_TO_32__q262[1] : csrf_prev_ie_vec_1 ; assign MUX_csrf_ie_vec_3$write_1__VAL_2 = (rob$deqPort_0_deq_data[257:253] == 5'd13 && - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd18) ? robdeqPort_0_deq_data_BITS_95_TO_32__q262[3] : csrf_prev_ie_vec_3 ; assign MUX_csrf_mepc_csr$write_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ; assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1 = - n__read__h720223 + 64'd1 ; + n__read__h720326 + 64'd1 ; assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2 = - n__read__h720223 + { 62'd0, x__h723542 } ; + n__read__h720326 + { 62'd0, x__h723645 } ; assign MUX_csrf_mpp_reg$write_1__VAL_2 = (rob$deqPort_0_deq_data[257:253] == 5'd13 && - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd18) ? MUX_csrf_mepc_csr$write_1__VAL_2[12:11] : 2'd0 ; assign MUX_csrf_mtval_csr$write_1__VAL_1 = - commitStage_commitTrap[36] ? 64'd0 : trap_val__h709616 ; + commitStage_commitTrap[36] ? 64'd0 : trap_val__h709719 ; assign MUX_csrf_mtval_csr$write_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ; assign MUX_csrf_prev_ie_vec_1$write_1__VAL_2 = rob$deqPort_0_deq_data[257:253] != 5'd13 || - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 != + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 != 6'd8 && - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 != + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 != 6'd18 || MUX_csrf_mtval_csr$write_1__VAL_2[5] ; assign MUX_csrf_prev_ie_vec_3$write_1__VAL_2 = rob$deqPort_0_deq_data[257:253] != 5'd13 || - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 != + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 != 6'd18 || MUX_csrf_mtval_csr$write_1__VAL_2[7] ; assign MUX_csrf_prv_reg$write_1__VAL_1 = (rob$deqPort_0_deq_data[257:253] == 5'd19) ? - x__h719602 : + x__h719705 : csrf_mpp_reg ; assign MUX_csrf_prv_reg$write_1__VAL_2 = - csrf_prv_reg_read__2956_ULE_1_4597_AND_IF_comm_ETC___d14636 ? + csrf_prv_reg_read__2956_ULE_1_4607_AND_IF_comm_ETC___d14646 ? 2'd1 : 2'd3 ; assign MUX_csrf_sepc_csr$write_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ; @@ -11451,22 +11452,22 @@ module mkCore(CLK, amoExec___d882[0] ; assign MUX_csrf_spp_reg$write_1__VAL_2 = rob$deqPort_0_deq_data[257:253] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + (IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd8 || - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd18) && MUX_csrf_sepc_csr$write_1__VAL_2[8] ; assign MUX_fetchStage$redirect_1__VAL_4 = - csrf_prv_reg_read__2956_ULE_1_4597_AND_IF_comm_ETC___d14636 ? - y_avValue_new_pc__h711297 : - y_avValue_new_pc__h711483 ; + csrf_prv_reg_read__2956_ULE_1_4607_AND_IF_comm_ETC___d14646 ? + y_avValue_new_pc__h711400 : + y_avValue_new_pc__h711586 ; always@(rob$deqPort_0_deq_data or - next_pc__h719433 or csrf_sepc_csr or csrf_mepc_csr) + next_pc__h719536 or csrf_sepc_csr or csrf_mepc_csr) begin case (rob$deqPort_0_deq_data[257:253]) 5'd19: MUX_fetchStage$redirect_1__VAL_5 = csrf_sepc_csr; 5'd20: MUX_fetchStage$redirect_1__VAL_5 = csrf_mepc_csr; - default: MUX_fetchStage$redirect_1__VAL_5 = next_pc__h719433; + default: MUX_fetchStage$redirect_1__VAL_5 = next_pc__h719536; endcase end assign MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_1 = @@ -11545,7 +11546,7 @@ module mkCore(CLK, fetchStage$pipelines_0_first[194:192] != 3'd2 && fetchStage$pipelines_0_first[194:192] != 3'd3 && fetchStage$pipelines_0_first[194:192] != 3'd4, - NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d14273 } ; + NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d14283 } ; assign MUX_rob$enqPort_0_enq_1__VAL_2 = { fetchStage$pipelines_0_first[387:324], fetchStage$pipelines_0_first[127:96], @@ -11580,21 +11581,7 @@ module mkCore(CLK, fetchStage$pipelines_0_first[199:195], fetchStage$pipelines_0_first[75:69], 64'hAAAAAAAAAAAAAAAA, - fetchStage$pipelines_0_first[173], - IF_fetchStage_pipelines_0_first__2928_BITS_172_ETC___d13125, - 73'h1280000000000000000, - fetchStage$pipelines_0_first[323:260], - 5'd0, - fetchStage$pipelines_0_first[173] && - fetchStage$pipelines_0_first[199:195] == 5'd13 && - (fetchStage$pipelines_0_first[172:161] == 12'd1 || - fetchStage$pipelines_0_first[172:161] == 12'd2 || - fetchStage$pipelines_0_first[172:161] == 12'd3) || - fetchStage$pipelines_0_first[75] && - fetchStage$pipelines_0_first[74], - fetchStage$pipelines_0_first[194:192] != 3'd0, - 13'h1521, - specTagManager$currentSpecBits } ; + fetchStage_pipelines_0_first__2928_BIT_173_304_ETC___d13522 } ; assign MUX_rob$setExecuted_deqLSQ_2__VAL_2 = { 1'd1, CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q264 } ; @@ -11618,7 +11605,7 @@ module mkCore(CLK, assign csrf_minstret_ehr_data_lat_0$whas = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[257:253] == 5'd13 && - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd31 ; assign csrf_minstret_ehr_data_lat_1$whas = WILL_FIRE_RL_commitStage_doCommitSystemInst || @@ -11630,7 +11617,7 @@ module mkCore(CLK, assign csrf_mcycle_ehr_data_lat_0$whas = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[257:253] == 5'd13 && - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd30 ; assign csrInstOrInterruptInflight_lat_1$whas = WILL_FIRE_RL_renameStage_doRenaming_SystemInst && @@ -12691,9 +12678,9 @@ module mkCore(CLK, assign csrf_external_int_en_vec_1$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[257:253] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + (IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd9 || - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd22) ; // register csrf_external_int_en_vec_3 @@ -12702,7 +12689,7 @@ module mkCore(CLK, assign csrf_external_int_en_vec_3$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[257:253] == 5'd13 && - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd22 ; // register csrf_external_int_pend_vec_0 @@ -12725,7 +12712,7 @@ module mkCore(CLK, assign csrf_external_int_pend_vec_3$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[257:253] == 5'd13 && - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd29 || EN_setMEIP ; @@ -12737,25 +12724,25 @@ module mkCore(CLK, assign csrf_fflags_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[257:253] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + (IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd0 || - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd2) || WILL_FIRE_RL_commitStage_doCommitNormalInst && - NOT_IF_NOT_rob_deqPort_0_canDeq__4986_4987_OR__ETC___d15204 ; + NOT_IF_NOT_rob_deqPort_0_canDeq__4996_4997_OR__ETC___d15214 ; // register csrf_frm_reg assign csrf_frm_reg$D_IN = - (IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + (IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd1) ? csrf_mcycle_ehr_data_lat_0$wget[2:0] : csrf_mcycle_ehr_data_lat_0$wget[7:5] ; assign csrf_frm_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[257:253] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + (IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd1 || - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd2) ; // register csrf_fs_reg @@ -12766,16 +12753,16 @@ module mkCore(CLK, assign csrf_fs_reg$EN = MUX_csrf_fs_reg$write_1__SEL_1 || WILL_FIRE_RL_commitStage_doCommitNormalInst && - NOT_IF_NOT_rob_deqPort_0_canDeq__4986_4987_OR__ETC___d15204 ; + NOT_IF_NOT_rob_deqPort_0_canDeq__4996_4997_OR__ETC___d15214 ; // register csrf_ie_vec_0 assign csrf_ie_vec_0$D_IN = csrf_mcycle_ehr_data_lat_0$wget[0] ; assign csrf_ie_vec_0$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[257:253] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + (IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd8 || - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd18) ; // register csrf_ie_vec_1 @@ -12784,7 +12771,7 @@ module mkCore(CLK, MUX_csrf_ie_vec_1$write_1__VAL_2 ; assign csrf_ie_vec_1$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - csrf_prv_reg_read__2956_ULE_1_4597_AND_IF_comm_ETC___d14636 || + csrf_prv_reg_read__2956_ULE_1_4607_AND_IF_comm_ETC___d14646 || WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; // register csrf_ie_vec_3 @@ -12793,20 +12780,20 @@ module mkCore(CLK, MUX_csrf_ie_vec_3$write_1__VAL_2 ; assign csrf_ie_vec_3$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_csrf_prv_reg_read__2956_ULE_1_4597_4661_OR_ETC___d14665 || + NOT_csrf_prv_reg_read__2956_ULE_1_4607_4671_OR_ETC___d14675 || WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 ; // register csrf_mcause_code_reg assign csrf_mcause_code_reg$D_IN = MUX_csrf_ie_vec_3$write_1__SEL_1 ? - cause_code__h708593 : + cause_code__h708696 : csrf_mcycle_ehr_data_lat_0$wget[3:0] ; assign csrf_mcause_code_reg$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_csrf_prv_reg_read__2956_ULE_1_4597_4661_OR_ETC___d14665 || + NOT_csrf_prv_reg_read__2956_ULE_1_4607_4671_OR_ETC___d14675 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[257:253] == 5'd13 && - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd27 ; // register csrf_mcause_interrupt_reg @@ -12816,10 +12803,10 @@ module mkCore(CLK, csrf_mcycle_ehr_data_lat_0$wget[63] ; assign csrf_mcause_interrupt_reg$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_csrf_prv_reg_read__2956_ULE_1_4597_4661_OR_ETC___d14665 || + NOT_csrf_prv_reg_read__2956_ULE_1_4607_4671_OR_ETC___d14675 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[257:253] == 5'd13 && - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd27 ; // register csrf_mcounteren_cy_reg @@ -12827,7 +12814,7 @@ module mkCore(CLK, assign csrf_mcounteren_cy_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[257:253] == 5'd13 && - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd24 ; // register csrf_mcounteren_ir_reg @@ -12835,7 +12822,7 @@ module mkCore(CLK, assign csrf_mcounteren_ir_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[257:253] == 5'd13 && - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd24 ; // register csrf_mcounteren_tm_reg @@ -12843,7 +12830,7 @@ module mkCore(CLK, assign csrf_mcounteren_tm_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[257:253] == 5'd13 && - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd24 ; // register csrf_mcycle_ehr_data_rl @@ -12856,7 +12843,7 @@ module mkCore(CLK, assign csrf_medeleg_13_11_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[257:253] == 5'd13 && - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd20 ; // register csrf_medeleg_15_reg @@ -12864,7 +12851,7 @@ module mkCore(CLK, assign csrf_medeleg_15_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[257:253] == 5'd13 && - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd20 ; // register csrf_medeleg_9_0_reg @@ -12872,7 +12859,7 @@ module mkCore(CLK, assign csrf_medeleg_9_0_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[257:253] == 5'd13 && - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd20 ; // register csrf_mepc_csr @@ -12882,10 +12869,10 @@ module mkCore(CLK, rob$deqPort_0_deq_data[95:32] ; assign csrf_mepc_csr$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_csrf_prv_reg_read__2956_ULE_1_4597_4661_OR_ETC___d14665 || + NOT_csrf_prv_reg_read__2956_ULE_1_4607_4671_OR_ETC___d14675 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[257:253] == 5'd13 && - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd26 ; // register csrf_mideleg_11_reg @@ -12893,7 +12880,7 @@ module mkCore(CLK, assign csrf_mideleg_11_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[257:253] == 5'd13 && - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd21 ; // register csrf_mideleg_1_0_reg @@ -12901,7 +12888,7 @@ module mkCore(CLK, assign csrf_mideleg_1_0_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[257:253] == 5'd13 && - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd21 ; // register csrf_mideleg_5_3_reg @@ -12909,7 +12896,7 @@ module mkCore(CLK, assign csrf_mideleg_5_3_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[257:253] == 5'd13 && - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd21 ; // register csrf_mideleg_9_7_reg @@ -12917,7 +12904,7 @@ module mkCore(CLK, assign csrf_mideleg_9_7_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[257:253] == 5'd13 && - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd21 ; // register csrf_minstret_ehr_data_rl @@ -12934,7 +12921,7 @@ module mkCore(CLK, MUX_csrf_mpp_reg$write_1__VAL_2 ; assign csrf_mpp_reg$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_csrf_prv_reg_read__2956_ULE_1_4597_4661_OR_ETC___d14665 || + NOT_csrf_prv_reg_read__2956_ULE_1_4607_4671_OR_ETC___d14675 || WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 ; // register csrf_mprv_reg @@ -12942,7 +12929,7 @@ module mkCore(CLK, assign csrf_mprv_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[257:253] == 5'd13 && - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd18 ; // register csrf_mscratch_csr @@ -12950,7 +12937,7 @@ module mkCore(CLK, assign csrf_mscratch_csr$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[257:253] == 5'd13 && - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd25 ; // register csrf_mtval_csr @@ -12960,10 +12947,10 @@ module mkCore(CLK, rob$deqPort_0_deq_data[95:32] ; assign csrf_mtval_csr$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_csrf_prv_reg_read__2956_ULE_1_4597_4661_OR_ETC___d14665 || + NOT_csrf_prv_reg_read__2956_ULE_1_4607_4671_OR_ETC___d14675 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[257:253] == 5'd13 && - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd28 ; // register csrf_mtvec_base_hi_reg @@ -12971,7 +12958,7 @@ module mkCore(CLK, assign csrf_mtvec_base_hi_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[257:253] == 5'd13 && - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd23 ; // register csrf_mtvec_mode_low_reg @@ -12979,7 +12966,7 @@ module mkCore(CLK, assign csrf_mtvec_mode_low_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[257:253] == 5'd13 && - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd23 ; // register csrf_mxr_reg @@ -12987,9 +12974,9 @@ module mkCore(CLK, assign csrf_mxr_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[257:253] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + (IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd8 || - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd18) ; // register csrf_ppn_reg @@ -12997,7 +12984,7 @@ module mkCore(CLK, assign csrf_ppn_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[257:253] == 5'd13 && - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd17 ; // register csrf_prev_ie_vec_0 @@ -13005,9 +12992,9 @@ module mkCore(CLK, assign csrf_prev_ie_vec_0$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[257:253] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + (IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd8 || - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd18) ; // register csrf_prev_ie_vec_1 @@ -13017,7 +13004,7 @@ module mkCore(CLK, MUX_csrf_prev_ie_vec_1$write_1__VAL_2 ; assign csrf_prev_ie_vec_1$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - csrf_prv_reg_read__2956_ULE_1_4597_AND_IF_comm_ETC___d14636 || + csrf_prv_reg_read__2956_ULE_1_4607_AND_IF_comm_ETC___d14646 || WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; // register csrf_prev_ie_vec_3 @@ -13027,7 +13014,7 @@ module mkCore(CLK, MUX_csrf_prev_ie_vec_3$write_1__VAL_2 ; assign csrf_prev_ie_vec_3$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_csrf_prv_reg_read__2956_ULE_1_4597_4661_OR_ETC___d14665 || + NOT_csrf_prv_reg_read__2956_ULE_1_4607_4671_OR_ETC___d14675 || WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 ; // register csrf_prv_reg @@ -13046,7 +13033,7 @@ module mkCore(CLK, assign csrf_rg_tdata1_data$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[257:253] == 5'd13 && - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd37 ; // register csrf_rg_tdata1_dmode @@ -13054,7 +13041,7 @@ module mkCore(CLK, assign csrf_rg_tdata1_dmode$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[257:253] == 5'd13 && - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd37 ; // register csrf_rg_tdata2 @@ -13062,7 +13049,7 @@ module mkCore(CLK, assign csrf_rg_tdata2$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[257:253] == 5'd13 && - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd38 ; // register csrf_rg_tdata3 @@ -13070,7 +13057,7 @@ module mkCore(CLK, assign csrf_rg_tdata3$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[257:253] == 5'd13 && - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd39 ; // register csrf_rg_tselect @@ -13078,20 +13065,20 @@ module mkCore(CLK, assign csrf_rg_tselect$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[257:253] == 5'd13 && - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd36 ; // register csrf_scause_code_reg assign csrf_scause_code_reg$D_IN = MUX_csrf_ie_vec_1$write_1__SEL_1 ? - cause_code__h708593 : + cause_code__h708696 : csrf_rg_tdata3$D_IN[3:0] ; assign csrf_scause_code_reg$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - csrf_prv_reg_read__2956_ULE_1_4597_AND_IF_comm_ETC___d14636 || + csrf_prv_reg_read__2956_ULE_1_4607_AND_IF_comm_ETC___d14646 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[257:253] == 5'd13 && - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd14 ; // register csrf_scause_interrupt_reg @@ -13101,10 +13088,10 @@ module mkCore(CLK, csrf_rg_tselect$D_IN[63] ; assign csrf_scause_interrupt_reg$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - csrf_prv_reg_read__2956_ULE_1_4597_AND_IF_comm_ETC___d14636 || + csrf_prv_reg_read__2956_ULE_1_4607_AND_IF_comm_ETC___d14646 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[257:253] == 5'd13 && - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd14 ; // register csrf_scounteren_cy_reg @@ -13112,7 +13099,7 @@ module mkCore(CLK, assign csrf_scounteren_cy_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[257:253] == 5'd13 && - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd11 ; // register csrf_scounteren_ir_reg @@ -13120,7 +13107,7 @@ module mkCore(CLK, assign csrf_scounteren_ir_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[257:253] == 5'd13 && - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd11 ; // register csrf_scounteren_tm_reg @@ -13128,7 +13115,7 @@ module mkCore(CLK, assign csrf_scounteren_tm_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[257:253] == 5'd13 && - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd11 ; // register csrf_sepc_csr @@ -13138,10 +13125,10 @@ module mkCore(CLK, rob$deqPort_0_deq_data[95:32] ; assign csrf_sepc_csr$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - csrf_prv_reg_read__2956_ULE_1_4597_AND_IF_comm_ETC___d14636 || + csrf_prv_reg_read__2956_ULE_1_4607_AND_IF_comm_ETC___d14646 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[257:253] == 5'd13 && - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd13 ; // register csrf_software_int_en_vec_0 @@ -13153,9 +13140,9 @@ module mkCore(CLK, assign csrf_software_int_en_vec_1$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[257:253] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + (IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd9 || - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd22) ; // register csrf_software_int_en_vec_3 @@ -13163,7 +13150,7 @@ module mkCore(CLK, assign csrf_software_int_en_vec_3$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[257:253] == 5'd13 && - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd22 ; // register csrf_software_int_pend_vec_0 @@ -13186,7 +13173,7 @@ module mkCore(CLK, mmio_pRqQ_data_0[37:36] != 2'd1 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[257:253] == 5'd13 && - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd29 ; // register csrf_spp_reg @@ -13196,7 +13183,7 @@ module mkCore(CLK, MUX_csrf_spp_reg$write_1__VAL_2 ; assign csrf_spp_reg$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - csrf_prv_reg_read__2956_ULE_1_4597_AND_IF_comm_ETC___d14636 || + csrf_prv_reg_read__2956_ULE_1_4607_AND_IF_comm_ETC___d14646 || WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; // register csrf_sscratch_csr @@ -13204,7 +13191,7 @@ module mkCore(CLK, assign csrf_sscratch_csr$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[257:253] == 5'd13 && - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd12 ; // register csrf_stats_module_doStats @@ -13218,10 +13205,10 @@ module mkCore(CLK, rob$deqPort_0_deq_data[95:32] ; assign csrf_stval_csr$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - csrf_prv_reg_read__2956_ULE_1_4597_AND_IF_comm_ETC___d14636 || + csrf_prv_reg_read__2956_ULE_1_4607_AND_IF_comm_ETC___d14646 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[257:253] == 5'd13 && - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd15 ; // register csrf_stvec_base_hi_reg @@ -13229,7 +13216,7 @@ module mkCore(CLK, assign csrf_stvec_base_hi_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[257:253] == 5'd13 && - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd10 ; // register csrf_stvec_mode_low_reg @@ -13237,7 +13224,7 @@ module mkCore(CLK, assign csrf_stvec_mode_low_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[257:253] == 5'd13 && - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd10 ; // register csrf_sum_reg @@ -13245,9 +13232,9 @@ module mkCore(CLK, assign csrf_sum_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[257:253] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + (IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd8 || - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd18) ; // register csrf_time_reg @@ -13263,9 +13250,9 @@ module mkCore(CLK, assign csrf_timer_int_en_vec_1$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[257:253] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + (IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd9 || - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd22) ; // register csrf_timer_int_en_vec_3 @@ -13273,7 +13260,7 @@ module mkCore(CLK, assign csrf_timer_int_en_vec_3$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[257:253] == 5'd13 && - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd22 ; // register csrf_timer_int_pend_vec_0 @@ -13296,7 +13283,7 @@ module mkCore(CLK, assign csrf_tsr_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[257:253] == 5'd13 && - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd18 ; // register csrf_tvm_reg @@ -13304,7 +13291,7 @@ module mkCore(CLK, assign csrf_tvm_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[257:253] == 5'd13 && - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd18 ; // register csrf_tw_reg @@ -13312,7 +13299,7 @@ module mkCore(CLK, assign csrf_tw_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[257:253] == 5'd13 && - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd18 ; // register csrf_vm_mode_sv39_reg @@ -13320,7 +13307,7 @@ module mkCore(CLK, assign csrf_vm_mode_sv39_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[257:253] == 5'd13 && - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd17 ; // register flush_reservation @@ -13337,7 +13324,7 @@ module mkCore(CLK, WILL_FIRE_RL_commitStage_doCommitSystemInst && (rob$deqPort_0_deq_data[257:253] == 5'd16 || rob$deqPort_0_deq_data[257:253] == 5'd13 && - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd17) ; // register mmio_cRqQ_clearReq_rl @@ -14062,8 +14049,8 @@ module mkCore(CLK, // submodule coreFix_aluExe_1_rsAlu assign coreFix_aluExe_1_rsAlu$enq_x = - (k__h674927 == 1'd1 && - fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14176) ? + (k__h675030 == 1'd1 && + fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14186) ? { fetchStage$pipelines_0_first[199:195], IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13043, fetchStage$pipelines_0_first[173], @@ -14077,13 +14064,13 @@ module mkCore(CLK, specTagManager$nextSpecTag, sbAggr$eagerLookup_0_get } : { fetchStage$pipelines_1_first[199:195], - IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13691, - fetchStage_pipelines_1_first__2937_BIT_173_369_ETC___d13775, + IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13701, + fetchStage_pipelines_1_first__2937_BIT_173_370_ETC___d13785, fetchStage$pipelines_1_first[160:128], fetchStage$pipelines_1_first[255:232], regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h690391, + renaming_spec_bits__h690494, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -14181,11 +14168,11 @@ module mkCore(CLK, end assign coreFix_aluExe_1_rsAlu$EN_enq = WILL_FIRE_RL_renameStage_doRenaming && - (k__h674927 == 1'd1 && - fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14176 || - fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14295 == + (k__h675030 == 1'd1 && + fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14186 || + fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14305 == 1'd1 && - NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14312) ; + NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14322) ; assign coreFix_aluExe_1_rsAlu$EN_setRobEnqTime = 1'd1 ; assign coreFix_aluExe_1_rsAlu$EN_doDispatch = WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu ; @@ -14724,7 +14711,7 @@ module mkCore(CLK, // submodule coreFix_fpuMulDivExe_0_rsFpuMulDiv assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$enq_x = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3518_AND__ETC___d14188) ? + regRenamingTable_rename_0_canRename__3528_AND__ETC___d14198) ? { IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13043, regRenamingTable$rename_0_getRename, rob$enqPort_0_getEnqInstTag, @@ -14732,10 +14719,10 @@ module mkCore(CLK, fetchStage$pipelines_0_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_0_get } : - { IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13691, + { IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13701, regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h690391, + renaming_spec_bits__h690494, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -14834,12 +14821,12 @@ module mkCore(CLK, assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_enq = WILL_FIRE_RL_renameStage_doRenaming && (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3518_AND__ETC___d14188 || - NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14299 && - regRenamingTable_rename_1_canRename__3637_AND__ETC___d14308 && + regRenamingTable_rename_0_canRename__3528_AND__ETC___d14198 || + NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14309 && + regRenamingTable_rename_1_canRename__3647_AND__ETC___d14318 && (fetchStage$pipelines_1_first[194:192] == 3'd3 || fetchStage$pipelines_1_first[194:192] == 3'd4) && - NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14348 && + NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14358 && coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) ; assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRobEnqTime = 1'd1 ; assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_doDispatch = @@ -15584,8 +15571,8 @@ module mkCore(CLK, { l2Tlb$toChildren_rsToC_first[80:0], l2Tlb$toChildren_rsToC_first[82:81] } ; assign coreFix_memExe_dTlb$updateVMInfo_vm = - { prv__h724853, - prv__h724853 != 2'd3 && csrf_vm_mode_sv39_reg, + { prv__h724956, + prv__h724956 != 2'd3 && csrf_vm_mode_sv39_reg, csrf_mxr_reg, csrf_sum_reg, csrf_ppn_reg } ; @@ -15693,44 +15680,44 @@ module mkCore(CLK, // submodule coreFix_memExe_lsq assign coreFix_memExe_lsq$enqLd_dst = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3518_AND__ETC___d14245) ? + regRenamingTable_rename_0_canRename__3528_AND__ETC___d14255) ? regRenamingTable$rename_0_getRename[8:0] : regRenamingTable$rename_1_getRename[8:0] ; assign coreFix_memExe_lsq$enqLd_inst_tag = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3518_AND__ETC___d14245) ? + regRenamingTable_rename_0_canRename__3528_AND__ETC___d14255) ? rob$enqPort_0_getEnqInstTag : rob$enqPort_1_getEnqInstTag ; assign coreFix_memExe_lsq$enqLd_mem_inst = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3518_AND__ETC___d14245) ? + regRenamingTable_rename_0_canRename__3528_AND__ETC___d14255) ? fetchStage$pipelines_0_first[191:174] : fetchStage$pipelines_1_first[191:174] ; assign coreFix_memExe_lsq$enqLd_spec_bits = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3518_AND__ETC___d14245) ? + regRenamingTable_rename_0_canRename__3528_AND__ETC___d14255) ? specTagManager$currentSpecBits : - renaming_spec_bits__h690391 ; + renaming_spec_bits__h690494 ; assign coreFix_memExe_lsq$enqSt_dst = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3518_AND__ETC___d14253) ? + regRenamingTable_rename_0_canRename__3528_AND__ETC___d14263) ? regRenamingTable$rename_0_getRename[8:0] : regRenamingTable$rename_1_getRename[8:0] ; assign coreFix_memExe_lsq$enqSt_inst_tag = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3518_AND__ETC___d14253) ? + regRenamingTable_rename_0_canRename__3528_AND__ETC___d14263) ? rob$enqPort_0_getEnqInstTag : rob$enqPort_1_getEnqInstTag ; assign coreFix_memExe_lsq$enqSt_mem_inst = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3518_AND__ETC___d14253) ? + regRenamingTable_rename_0_canRename__3528_AND__ETC___d14263) ? fetchStage$pipelines_0_first[191:174] : fetchStage$pipelines_1_first[191:174] ; assign coreFix_memExe_lsq$enqSt_spec_bits = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3518_AND__ETC___d14253) ? + regRenamingTable_rename_0_canRename__3528_AND__ETC___d14263) ? specTagManager$currentSpecBits : - renaming_spec_bits__h690391 ; + renaming_spec_bits__h690494 ; assign coreFix_memExe_lsq$getHit_t = MUX_coreFix_memExe_lsq$getHit_1__SEL_1 ? MUX_coreFix_memExe_lsq$getHit_1__VAL_1 : @@ -16162,9 +16149,9 @@ module mkCore(CLK, // submodule coreFix_memExe_rsMem assign coreFix_memExe_rsMem$enq_x = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3518_AND__ETC___d14211) ? + regRenamingTable_rename_0_canRename__3528_AND__ETC___d14221) ? { fetchStage$pipelines_0_first[191:189], - IF_fetchStage_pipelines_0_first__2928_BIT_160__ETC___d14227, + IF_fetchStage_pipelines_0_first__2928_BIT_160__ETC___d14237, regRenamingTable$rename_0_getRename, rob$enqPort_0_getEnqInstTag, specTagManager$currentSpecBits, @@ -16172,10 +16159,10 @@ module mkCore(CLK, specTagManager$nextSpecTag, sbAggr$eagerLookup_0_get } : { fetchStage$pipelines_1_first[191:189], - IF_fetchStage_pipelines_1_first__2937_BIT_160__ETC___d14388, + IF_fetchStage_pipelines_1_first__2937_BIT_160__ETC___d14398, regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h690391, + renaming_spec_bits__h690494, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -16420,7 +16407,7 @@ module mkCore(CLK, assign csrf_stats_module_writeQ$ENQ = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[257:253] == 5'd13 && - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd7 ; assign csrf_stats_module_writeQ$DEQ = EN_sendDoStats ; assign csrf_stats_module_writeQ$CLR = 1'b0 ; @@ -16429,7 +16416,7 @@ module mkCore(CLK, assign csrf_terminate_module_terminateQ$ENQ = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[257:253] == 5'd13 && - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd6 ; assign csrf_terminate_module_terminateQ$DEQ = EN_coreIndInv_terminate ; assign csrf_terminate_module_terminateQ$CLR = 1'b0 ; @@ -16448,8 +16435,8 @@ module mkCore(CLK, fetchStage$pipelines_0_canDeq || WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d14173 && - IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13598 || + NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d14183 && + IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13608 || WILL_FIRE_RL_renameStage_doRenaming_SystemInst || WILL_FIRE_RL_renameStage_doRenaming_Trap ; assign epochManager$EN_updatePrevEpoch_1_update = @@ -16457,9 +16444,9 @@ module mkCore(CLK, fetchStage$pipelines_1_canDeq && !epochManager$checkEpoch_1_check || WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14299 && - NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d14309 && - IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13989 ; + NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14309 && + NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d14319 && + IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13999 ; assign epochManager$EN_incrementEpoch = WILL_FIRE_RL_commitStage_doCommitTrap_flush && !rob$deqPort_0_deq_data[12] || @@ -16552,8 +16539,8 @@ module mkCore(CLK, fetchStage$pipelines_0_canDeq || WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d14173 && - IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13598 || + NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d14183 && + IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13608 || WILL_FIRE_RL_renameStage_doRenaming_SystemInst || WILL_FIRE_RL_renameStage_doRenaming_Trap ; assign fetchStage$EN_pipelines_1_deq = @@ -16561,9 +16548,9 @@ module mkCore(CLK, fetchStage$pipelines_1_canDeq && !epochManager$checkEpoch_1_check || WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14299 && - NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d14309 && - IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13989 ; + NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14309 && + NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d14319 && + IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13999 ; assign fetchStage$EN_iTlbIfc_flush = MUX_flush_tlbs$write_1__SEL_1 ; assign fetchStage$EN_iTlbIfc_updateVMInfo = MUX_update_vm_info$write_1__SEL_1 ; @@ -16888,7 +16875,7 @@ module mkCore(CLK, assign regRenamingTable$rename_1_claimRename_r = fetchStage$pipelines_1_first[95:69] ; assign regRenamingTable$rename_1_claimRename_sb = - renaming_spec_bits__h690391 ; + renaming_spec_bits__h690494 ; assign regRenamingTable$rename_1_getRename_r = fetchStage$pipelines_1_first[95:69] ; assign regRenamingTable$specUpdate_correctSpeculation_mask = @@ -16918,8 +16905,8 @@ module mkCore(CLK, assign regRenamingTable$EN_rename_0_claimRename = WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d14173 && - IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13598 || + NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d14183 && + IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13608 || WILL_FIRE_RL_renameStage_doRenaming_SystemInst ; assign regRenamingTable$EN_rename_1_claimRename = MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2 ; @@ -17139,7 +17126,7 @@ module mkCore(CLK, fetchStage$pipelines_1_first[199:195], fetchStage$pipelines_1_first[75:69], 64'hAAAAAAAAAAAAAAAA, - fetchStage_pipelines_1_first__2937_BIT_173_369_ETC___d13775, + fetchStage_pipelines_1_first__2937_BIT_173_370_ETC___d13785, 73'h1280000000000000000, fetchStage$pipelines_1_first[323:260], 5'd0, @@ -17151,11 +17138,11 @@ module mkCore(CLK, fetchStage$pipelines_1_first[194:192] != 3'd3 && fetchStage$pipelines_1_first[194:192] != 3'd4, fetchStage$pipelines_1_first[194:192] != 3'd2 || - fetchStage_pipelines_0_canDeq__2926_AND_regRen_ETC___d14431 || - IF_fetchStage_pipelines_1_first__2937_BITS_191_ETC___d14382, - IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d14441, + fetchStage_pipelines_0_canDeq__2926_AND_regRen_ETC___d14441 || + IF_fetchStage_pipelines_1_first__2937_BITS_191_ETC___d14392, + IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d14451, 7'd32, - renaming_spec_bits__h690391 } ; + renaming_spec_bits__h690494 } ; assign rob$getOrigPC_0_get_x = coreFix_aluExe_0_dispToRegQ$first[52:41] ; assign rob$getOrigPC_1_get_x = coreFix_aluExe_1_dispToRegQ$first[52:41] ; assign rob$getOrigPC_2_get_x = 12'h0 ; @@ -17388,8 +17375,8 @@ module mkCore(CLK, assign rob$EN_enqPort_0_enq = WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d14173 && - IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13598 || + NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d14183 && + IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13608 || WILL_FIRE_RL_renameStage_doRenaming_Trap || WILL_FIRE_RL_renameStage_doRenaming_SystemInst ; assign rob$EN_enqPort_1_enq = @@ -17514,8 +17501,8 @@ module mkCore(CLK, assign sbAggr$EN_setBusy_0_set = WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d14173 && - IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13598 || + NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d14183 && + IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13608 || WILL_FIRE_RL_renameStage_doRenaming_SystemInst ; assign sbAggr$EN_setBusy_1_set = MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2 ; @@ -17629,8 +17616,8 @@ module mkCore(CLK, assign sbCons$EN_setBusy_0_set = WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d14173 && - IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13598 || + NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d14183 && + IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13608 || WILL_FIRE_RL_renameStage_doRenaming_SystemInst ; assign sbCons$EN_setBusy_1_set = MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2 ; @@ -17692,9 +17679,9 @@ module mkCore(CLK, end assign specTagManager$EN_claimSpecTag = WILL_FIRE_RL_renameStage_doRenaming && - (fetchStage_pipelines_0_canDeq__2926_AND_specTa_ETC___d14259 || - NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14299 && - NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14420) ; + (fetchStage_pipelines_0_canDeq__2926_AND_specTa_ETC___d14269 || + NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14309 && + NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14430) ; assign specTagManager$EN_specUpdate_incorrectSpeculation = WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T || WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T || @@ -17744,7 +17731,7 @@ module mkCore(CLK, { { fetchStage$pipelines_0_first[173], IF_fetchStage_pipelines_0_first__2928_BITS_172_ETC___d13125 }, fetchStage$pipelines_0_first[160], - x_data_imm__h682272 } }), + x_data_imm__h682375 } }), .checkForException_regs({ fetchStage$pipelines_0_first[95], fetchStage$pipelines_0_first[94:89], { fetchStage$pipelines_0_first[88], @@ -17756,7 +17743,7 @@ module mkCore(CLK, .checkForException_csrState({ x_decodeInfo_frm__h661526, r1__read_BITS_13_TO_12___h661711 != 2'd0, - { prv__h724809, + { prv__h724912, csrf_tvm_reg, { r1__read_BIT_20___h662375, csrf_tsr_reg, @@ -17771,10 +17758,10 @@ module mkCore(CLK, csrf_scounteren_tm_reg } } } } } }), .checkForException(checkForException___d13160)); module_checkForException instance_checkForException_1(.checkForException_dInst({ fetchStage$pipelines_1_first[199:195], - IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13691, - { fetchStage_pipelines_1_first__2937_BIT_173_369_ETC___d13775, + IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13701, + { fetchStage_pipelines_1_first__2937_BIT_173_370_ETC___d13785, fetchStage$pipelines_1_first[160], - x_data_imm__h698176 } }), + x_data_imm__h698279 } }), .checkForException_regs({ fetchStage$pipelines_1_first[95], fetchStage$pipelines_1_first[94:89], { fetchStage$pipelines_1_first[88], @@ -17786,7 +17773,7 @@ module mkCore(CLK, .checkForException_csrState({ x_decodeInfo_frm__h661526, r1__read_BITS_13_TO_12___h661711 != 2'd0, - { prv__h724809, + { prv__h724912, csrf_tvm_reg, { r1__read_BIT_20___h662375, csrf_tsr_reg, @@ -17799,7 +17786,7 @@ module mkCore(CLK, { csrf_mcounteren_tm_reg, csrf_mcounteren_tm_reg && csrf_scounteren_tm_reg } } } } } }), - .checkForException(checkForException___d13797)); + .checkForException(checkForException___d13807)); module_execFpuSimple instance_execFpuSimple_4(.execFpuSimple_fpu_inst({ coreFix_fpuMulDivExe_0_regToExeQ$first[233:229], CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q242, coreFix_fpuMulDivExe_0_regToExeQ$first[225] }), @@ -19675,7 +19662,7 @@ module mkCore(CLK, fetchStage$pipelines_0_first[231:200] == 32'h10500073 && csrf_tw_reg && csrf_prv_reg != 2'd3 ; - assign IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d13852 = + assign IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d13862 = IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[0] || IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[1] || IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[2] || @@ -19689,8 +19676,8 @@ module mkCore(CLK, IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[10] || IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[11] || checkForException___d13160[4] || - csrf_fs_reg_read__1726_EQ_0_3149_AND_fetchStag_ETC___d13610 ; - assign IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d13888 = + csrf_fs_reg_read__1726_EQ_0_3149_AND_fetchStag_ETC___d13620 ; + assign IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d13898 = IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[0] || IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[1] || IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[2] || @@ -19703,8 +19690,8 @@ module mkCore(CLK, IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[9] || IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[10] || IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[11] || - checkForException___d13797[4] || - csrf_fs_reg_read__1726_EQ_0_3149_AND_fetchStag_ETC___d13886 ; + checkForException___d13807[4] || + csrf_fs_reg_read__1726_EQ_0_3149_AND_fetchStag_ETC___d13896 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10048 = (f3_exp__h565827 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9351 ? @@ -20702,45 +20689,45 @@ module mkCore(CLK, coreFix_memExe_dTlb$procResp[12]) ? CASE_coreFix_memExe_dTlbprocResp_BITS_105_TO__ETC__q13 : CASE_coreFix_memExe_dTlbprocResp_BITS_109_TO__ETC__q14 ; - assign IF_NOT_fetchStage_pipelines_0_canDeq__2926_292_ETC___d13995 = + assign IF_NOT_fetchStage_pipelines_0_canDeq__2926_292_ETC___d14005 = ((!fetchStage$pipelines_0_canDeq || - NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13575) && + NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13585) && fetchStage$pipelines_1_canDeq) ? fetchStage$RDY_pipelines_1_first && (fetchStage$pipelines_1_first[194:192] != 3'd1 || !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first) && - IF_fetchStage_RDY_pipelines_1_first__2936_AND__ETC___d13992 : + IF_fetchStage_RDY_pipelines_1_first__2936_AND__ETC___d14002 : !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first ; - assign IF_NOT_fetchStage_pipelines_0_canDeq__2926_292_ETC___d14003 = + assign IF_NOT_fetchStage_pipelines_0_canDeq__2926_292_ETC___d14013 = ((!fetchStage$pipelines_0_canDeq || - NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13575) && + NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13585) && fetchStage$pipelines_1_canDeq) ? - IF_NOT_fetchStage_pipelines_1_first__2937_BITS_ETC___d14002 : + IF_NOT_fetchStage_pipelines_1_first__2937_BITS_ETC___d14012 : fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d14000 ; - assign IF_NOT_fetchStage_pipelines_1_first__2937_BITS_ETC___d13925 = + NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d14010 ; + assign IF_NOT_fetchStage_pipelines_1_first__2937_BITS_ETC___d13935 = (fetchStage$pipelines_1_first[194:192] == 3'd3 || fetchStage$pipelines_1_first[194:192] == 3'd4) ? - NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d13908 : + NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d13918 : ((fetchStage$pipelines_1_first[194:192] == 3'd2) ? - NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d13919 : + NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d13929 : (fetchStage$pipelines_1_first[194:192] != 3'd1 || !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first) && - _0_OR_fetchStage_RDY_pipelines_0_first__2925_39_ETC___d13922) ; - assign IF_NOT_fetchStage_pipelines_1_first__2937_BITS_ETC___d14002 = - NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d13835 ? - IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13989 || + _0_OR_fetchStage_RDY_pipelines_0_first__2925_39_ETC___d13932) ; + assign IF_NOT_fetchStage_pipelines_1_first__2937_BITS_ETC___d14012 = + NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d13845 ? + IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13999 || fetchStage$pipelines_0_canDeq && (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3518_AND__ETC___d13588 && - IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13598 : + regRenamingTable_rename_0_canRename__3528_AND__ETC___d13598 && + IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13608 : fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d14000 ; - assign IF_NOT_rob_deqPort_1_deq_data__4993_BIT_25_499_ETC___d15198 = + NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d14010 ; + assign IF_NOT_rob_deqPort_1_deq_data__5003_BIT_25_500_ETC___d15208 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[257:253] == 5'd0 || @@ -22184,48 +22171,48 @@ module mkCore(CLK, csrf_minstret_ehr_data_lat_0$whas ? rob$deqPort_0_deq_data[95:32] : csrf_minstret_ehr_data_rl ; - assign IF_fetchStage_RDY_pipelines_0_first__2925_AND__ETC___d13545 = - fetchStage_RDY_pipelines_0_first__2925_AND_NOT_ETC___d13541 ? + assign IF_fetchStage_RDY_pipelines_0_first__2925_AND__ETC___d13555 = + fetchStage_RDY_pipelines_0_first__2925_AND_NOT_ETC___d13551 ? fetchStage$RDY_pipelines_0_first : !regRenamingTable$rename_0_canRename || fetchStage$RDY_pipelines_0_first ; - assign IF_fetchStage_RDY_pipelines_1_first__2936_AND__ETC___d13927 = + assign IF_fetchStage_RDY_pipelines_1_first__2936_AND__ETC___d13937 = (fetchStage$RDY_pipelines_1_first && (fetchStage$pipelines_1_first[194:192] == 3'd0 || fetchStage$pipelines_1_first[194:192] == 3'd1)) ? (!fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first) && - SEL_ARR_fetchStage_pipelines_0_canDeq__2926_AN_ETC___d13897 : + SEL_ARR_fetchStage_pipelines_0_canDeq__2926_AN_ETC___d13907 : fetchStage$RDY_pipelines_1_first && - IF_NOT_fetchStage_pipelines_1_first__2937_BITS_ETC___d13925 ; - assign IF_fetchStage_RDY_pipelines_1_first__2936_AND__ETC___d13992 = + IF_NOT_fetchStage_pipelines_1_first__2937_BITS_ETC___d13935 ; + assign IF_fetchStage_RDY_pipelines_1_first__2936_AND__ETC___d14002 = (fetchStage$RDY_pipelines_1_first && (fetchStage$pipelines_1_first[194:192] != 3'd1 || !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first) && - fetchStage_RDY_pipelines_0_first__2925_AND_fet_ETC___d13607 && - NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d13835) ? - IF_fetchStage_RDY_pipelines_1_first__2936_AND__ETC___d13927 && - (IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13989 || + fetchStage_RDY_pipelines_0_first__2925_AND_fet_ETC___d13617 && + NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d13845) ? + IF_fetchStage_RDY_pipelines_1_first__2936_AND__ETC___d13937 && + (IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13999 || !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first) : !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first ; - assign IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14040 = - IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14033 || + assign IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14050 = + IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14043 || fetchStage$RDY_pipelines_0_deq && regRenamingTable$RDY_rename_0_getRename && regRenamingTable$RDY_rename_0_claimRename && rob$RDY_enqPort_0_enq && (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$RDY_claimSpecTag) ; - assign IF_fetchStage_pipelines_0_first__2928_BIT_160__ETC___d14227 = + assign IF_fetchStage_pipelines_0_first__2928_BIT_160__ETC___d14237 = { fetchStage$pipelines_0_first[159:128], - IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14215, - IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14218 ? - IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14221 : + IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14225, + IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14228 ? + IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14231 : { 1'h0, - IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14224 } } ; + IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14234 } } ; assign IF_fetchStage_pipelines_0_first__2928_BIT_68_2_ETC___d13385 = (fetchStage$pipelines_0_first[68] || !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[0] && @@ -22242,28 +22229,28 @@ module mkCore(CLK, !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[11]) ? IF_IF_fetchStage_pipelines_0_first__2928_BIT_6_ETC___d13346 : CASE_IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2956__ETC__q227 ; - assign IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d14161 = - IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d14120 && - IF_fetchStage_RDY_pipelines_1_first__2936_AND__ETC___d13927 && - (IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d14145 || + assign IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d14171 = + IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d14130 && + IF_fetchStage_RDY_pipelines_1_first__2936_AND__ETC___d13937 && + (IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d14155 || fetchStage$RDY_pipelines_1_deq && regRenamingTable$RDY_rename_1_getRename && regRenamingTable$RDY_rename_1_claimRename && - rob_RDY_enqPort_1_enq__4147_AND_NOT_fetchStage_ETC___d14155) ; - assign IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d14441 = + rob_RDY_enqPort_1_enq__4157_AND_NOT_fetchStage_ETC___d14165) ; + assign IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d14451 = (fetchStage$pipelines_1_first[194:192] == 3'd2 && - NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14376 && - IF_fetchStage_pipelines_1_first__2937_BITS_191_ETC___d14383) ? - IF_fetchStage_pipelines_1_first__2937_BITS_191_ETC___d14384 : + NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14386 && + IF_fetchStage_pipelines_1_first__2937_BITS_191_ETC___d14393) ? + IF_fetchStage_pipelines_1_first__2937_BITS_191_ETC___d14394 : { 1'h0, - IF_fetchStage_pipelines_1_first__2937_BITS_191_ETC___d14385 } ; - assign IF_fetchStage_pipelines_1_first__2937_BIT_160__ETC___d14388 = + IF_fetchStage_pipelines_1_first__2937_BITS_191_ETC___d14395 } ; + assign IF_fetchStage_pipelines_1_first__2937_BIT_160__ETC___d14398 = { fetchStage$pipelines_1_first[159:128], - IF_fetchStage_pipelines_1_first__2937_BITS_191_ETC___d14382, - IF_fetchStage_pipelines_1_first__2937_BITS_191_ETC___d14383 ? - IF_fetchStage_pipelines_1_first__2937_BITS_191_ETC___d14384 : + IF_fetchStage_pipelines_1_first__2937_BITS_191_ETC___d14392, + IF_fetchStage_pipelines_1_first__2937_BITS_191_ETC___d14393 ? + IF_fetchStage_pipelines_1_first__2937_BITS_191_ETC___d14394 : { 1'h0, - IF_fetchStage_pipelines_1_first__2937_BITS_191_ETC___d14385 } } ; + IF_fetchStage_pipelines_1_first__2937_BITS_191_ETC___d14395 } } ; assign IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmio_c_ETC___d339 = mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[142] : @@ -22288,19 +22275,19 @@ module mkCore(CLK, EN_mmioToPlatform_pRs_enq ? mmio_pRsQ_enqReq_lat_0$wget[67] : mmio_pRsQ_enqReq_rl[67] ; - assign IF_rob_deqPort_0_canDeq__4986_THEN_IF_NOT_rob__ETC___d15095 = + assign IF_rob_deqPort_0_canDeq__4996_THEN_IF_NOT_rob__ETC___d15105 = rob$deqPort_0_canDeq ? - y_avValue_snd_snd_snd_snd_snd__h722711 : + y_avValue_snd_snd_snd_snd_snd__h722814 : 64'd0 ; - assign IF_rob_deqPort_0_canDeq__4986_THEN_IF_NOT_rob__ETC___d15185 = - rob$deqPort_0_canDeq ? y_avValue_fst__h722271 : 5'd0 ; - assign IF_rob_deqPort_0_canDeq__4986_THEN_IF_NOT_rob__ETC___d15207 = + assign IF_rob_deqPort_0_canDeq__4996_THEN_IF_NOT_rob__ETC___d15195 = + rob$deqPort_0_canDeq ? y_avValue_fst__h722374 : 5'd0 ; + assign IF_rob_deqPort_0_canDeq__4996_THEN_IF_NOT_rob__ETC___d15217 = rob$deqPort_0_canDeq ? - y_avValue_snd_snd_snd_fst__h722705 : + y_avValue_snd_snd_snd_fst__h722808 : 2'd0 ; - assign IF_rob_deqPort_1_canDeq__4990_THEN_IF_NOT_rob__ETC___d15199 = + assign IF_rob_deqPort_1_canDeq__5000_THEN_IF_NOT_rob__ETC___d15209 = rob$deqPort_1_canDeq ? - IF_NOT_rob_deqPort_1_deq_data__4993_BIT_25_499_ETC___d15198 : + IF_NOT_rob_deqPort_1_deq_data__5003_BIT_25_500_ETC___d15208 : rob$deqPort_0_canDeq && rob$deqPort_0_deq_data[26] ; assign IF_sfdin04540_BIT_33_THEN_2_ELSE_0__q57 = sfdin__h404540[33] ? 2'd2 : 2'd0 ; @@ -22392,7 +22379,7 @@ module mkCore(CLK, (fetchStage$pipelines_0_first[231:200] != 32'h10500073 || !csrf_tw_reg || csrf_prv_reg == 2'd3) ; - assign NOT_IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_295_ETC___d13533 = + assign NOT_IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_295_ETC___d13543 = !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[0] && !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[1] && !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[2] && @@ -22406,8 +22393,8 @@ module mkCore(CLK, !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[10] && !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[11] && !checkForException___d13160[4] && - NOT_csrf_fs_reg_read__1726_EQ_0_3149_3150_OR_N_ETC___d13531 ; - assign NOT_IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_295_ETC___d13824 = + NOT_csrf_fs_reg_read__1726_EQ_0_3149_3150_OR_N_ETC___d13541 ; + assign NOT_IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_295_ETC___d13834 = !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[0] && !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[1] && !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[2] && @@ -22420,13 +22407,13 @@ module mkCore(CLK, !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[9] && !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[10] && !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[11] && - !checkForException___d13797[4] && - NOT_csrf_fs_reg_read__1726_EQ_0_3149_3150_OR_N_ETC___d13822 ; - assign NOT_IF_NOT_rob_deqPort_0_canDeq__4986_4987_OR__ETC___d15204 = - (fflags__h723294 & csrf_fflags_reg) != fflags__h723294 || + !checkForException___d13807[4] && + NOT_csrf_fs_reg_read__1726_EQ_0_3149_3150_OR_N_ETC___d13832 ; + assign NOT_IF_NOT_rob_deqPort_0_canDeq__4996_4997_OR__ETC___d15214 = + (fflags__h723397 & csrf_fflags_reg) != fflags__h723397 || !r__h619423 && - (IF_rob_deqPort_1_canDeq__4990_THEN_IF_NOT_rob__ETC___d15199 || - fflags__h723294 != 5'd0) ; + (IF_rob_deqPort_1_canDeq__5000_THEN_IF_NOT_rob__ETC___d15209 || + fflags__h723397 != 5'd0) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10167 = !f2_sfd__h526524[21] && !f2_sfd__h526524[20] && !f2_sfd__h526524[19] && @@ -22548,15 +22535,15 @@ module mkCore(CLK, !f3_sfd__h565828[2] && !f3_sfd__h565828[1] && !f3_sfd__h565828[0] ; - assign NOT_IF_rob_deqPort_0_deq_data__4456_BITS_97_TO_ETC___d14962 = - next_pc__h719433 != - rob_deqPort_0_deq_data__4456_BITS_353_TO_290_4_ETC___d14959 ; - assign NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13593 = - !SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__354_ETC___d13591 && + assign NOT_IF_rob_deqPort_0_deq_data__4466_BITS_97_TO_ETC___d14972 = + next_pc__h719536 != + rob_deqPort_0_deq_data__4466_BITS_353_TO_290_4_ETC___d14969 ; + assign NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13603 = + !SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__355_ETC___d13601 && (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && regRenamingTable$rename_0_canRename && - NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13538 ; + NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13548 ; assign NOT_coreFix_aluExe_0_bypassWire_0_whas__2366_2_ETC___d12393 = (!coreFix_aluExe_0_bypassWire_0$whas || !coreFix_aluExe_0_bypassWire_0_wget__2367_BITS__ETC___d12369) && @@ -22768,7 +22755,7 @@ module mkCore(CLK, assign NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__48_ETC___d8540 = coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] != 3'd3 || CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q252 ; - assign NOT_coreFix_fpuMulDivExe_0_rsFpuMulDiv_canEnq__ETC___d13936 = + assign NOT_coreFix_fpuMulDivExe_0_rsFpuMulDiv_canEnq__ETC___d13946 = !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq || fetchStage$pipelines_0_first[68] || IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[0] || @@ -23124,9 +23111,9 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_pipelineResp_releaseEntry && (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc[3] || !coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full) ; - assign NOT_coreFix_memExe_rsMem_canEnq__3561_3623_OR__ETC___d13937 = + assign NOT_coreFix_memExe_rsMem_canEnq__3571_3633_OR__ETC___d13947 = !coreFix_memExe_rsMem$canEnq || - IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13626 || + IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13636 || fetchStage$pipelines_0_first[68] || IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[0] || IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[1] || @@ -23153,7 +23140,7 @@ module mkCore(CLK, NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13429 && !csrf_prv_reg_read__2956_ULT_IF_fetchStage_pipe_ETC___d13192 && csr_addr__h661841 != 12'h8FF) ; - assign NOT_csrf_fs_reg_read__1726_EQ_0_3149_3150_OR_N_ETC___d13531 = + assign NOT_csrf_fs_reg_read__1726_EQ_0_3149_3150_OR_N_ETC___d13541 = (csrf_fs_reg != 2'd0 || (!fetchStage$pipelines_0_first[95] || !fetchStage$pipelines_0_first[94]) && @@ -23165,7 +23152,7 @@ module mkCore(CLK, (fetchStage$pipelines_0_first[231:200] != 32'h10500073 || !csrf_tw_reg || csrf_prv_reg == 2'd3) ; - assign NOT_csrf_fs_reg_read__1726_EQ_0_3149_3150_OR_N_ETC___d13822 = + assign NOT_csrf_fs_reg_read__1726_EQ_0_3149_3150_OR_N_ETC___d13832 = (csrf_fs_reg != 2'd0 || (!fetchStage$pipelines_1_first[95] || !fetchStage$pipelines_1_first[94]) && @@ -23177,107 +23164,107 @@ module mkCore(CLK, (fetchStage$pipelines_1_first[231:200] != 32'h10500073 || !csrf_tw_reg || csrf_prv_reg == 2'd3) ; - assign NOT_csrf_prv_reg_read__2956_ULE_1_4597_4661_OR_ETC___d14665 = - !csrf_prv_reg_read__2956_ULE_1___d14597 || + assign NOT_csrf_prv_reg_read__2956_ULE_1_4607_4671_OR_ETC___d14675 = + !csrf_prv_reg_read__2956_ULE_1___d14607 || (commitStage_commitTrap[36] ? - !_0b0_CONCAT_csrf_mideleg_11_reg_read__1833_1834_ETC___d14615 : - !_0b0_CONCAT_csrf_medeleg_15_reg_read__1825_1826_ETC___d14634) ; - assign NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d13908 = + !_0b0_CONCAT_csrf_mideleg_11_reg_read__1833_1834_ETC___d14625 : + !_0b0_CONCAT_csrf_medeleg_15_reg_read__1825_1826_ETC___d14644) ; + assign NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d13918 = (!fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first) && - (regRenamingTable_rename_0_canRename__3518_AND__ETC___d13588 && + (regRenamingTable_rename_0_canRename__3528_AND__ETC___d13598 && (fetchStage$pipelines_0_first[194:192] == 3'd3 || fetchStage$pipelines_0_first[194:192] == 3'd4) || !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq || !regRenamingTable$rename_1_canRename || - fetchStage_pipelines_1_first__2937_BITS_199_TO_ETC___d13894) ; - assign NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d13919 = + fetchStage_pipelines_1_first__2937_BITS_199_TO_ETC___d13904) ; + assign NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d13929 = (!fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first) && - (regRenamingTable_rename_0_canRename__3518_AND__ETC___d13917 || + (regRenamingTable_rename_0_canRename__3528_AND__ETC___d13927 || !regRenamingTable$rename_1_canRename || - fetchStage_pipelines_1_first__2937_BITS_199_TO_ETC___d13894) ; - assign NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d13958 = + fetchStage_pipelines_1_first__2937_BITS_199_TO_ETC___d13904) ; + assign NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d13968 = !fetchStage$pipelines_0_canDeq || - NOT_regRenamingTable_rename_0_canRename__3518__ETC___d13952 || + NOT_regRenamingTable_rename_0_canRename__3528__ETC___d13962 || fetchStage$pipelines_0_first[194:192] != 3'd3 && fetchStage$pipelines_0_first[194:192] != 3'd4 ; - assign NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d13975 = + assign NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d13985 = (!fetchStage$pipelines_0_canDeq || - NOT_regRenamingTable_rename_0_canRename__3518__ETC___d13617 || + NOT_regRenamingTable_rename_0_canRename__3528__ETC___d13627 || fetchStage$pipelines_0_first[194:192] != 3'd2 || - IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13626) && + IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13636) && coreFix_memExe_rsMem$canEnq && CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q231 ; - assign NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14096 = + assign NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14106 = (!fetchStage$pipelines_0_canDeq || fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || - NOT_regRenamingTable_rename_0_canRename__3518__ETC___d13952 || + NOT_regRenamingTable_rename_0_canRename__3528__ETC___d13962 || fetchStage$pipelines_0_first[194:192] != 3'd0 && fetchStage$pipelines_0_first[194:192] != 3'd1 || - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3548_co_ETC___d13558) && + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3558_co_ETC___d13568) && coreFix_aluExe_1_rsAlu$canEnq && - !coreFix_aluExe_0_rsAlu_approximateCount__3552__ETC___d13554 ; - assign NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14115 = + !coreFix_aluExe_0_rsAlu_approximateCount__3562__ETC___d13564 ; + assign NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14125 = (!fetchStage$pipelines_0_canDeq || - NOT_specTagManager_canClaim__3516_3601_OR_NOT__ETC___d14086) && + NOT_specTagManager_canClaim__3526_3611_OR_NOT__ETC___d14096) && CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q235 && (fetchStage$pipelines_1_first[199:195] == 5'd14 || coreFix_memExe_rsMem$RDY_enq) ; - assign NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14167 = + assign NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14177 = (!fetchStage$pipelines_0_canDeq || - fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d14042 && - IF_fetchStage_RDY_pipelines_0_first__2925_AND__ETC___d13545) && + fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d14052 && + IF_fetchStage_RDY_pipelines_0_first__2925_AND__ETC___d13555) && fetchStage$RDY_pipelines_0_first && - fetchStage_pipelines_0_canDeq__2926_AND_fetchS_ETC___d14165 ; - assign NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14299 = + fetchStage_pipelines_0_canDeq__2926_AND_fetchS_ETC___d14175 ; + assign NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14309 = (!fetchStage$pipelines_0_canDeq || - NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d14173 && - IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13574) && + NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d14183 && + IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13584) && fetchStage$pipelines_1_canDeq ; - assign NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14301 = + assign NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14311 = !fetchStage$pipelines_0_canDeq || - NOT_regRenamingTable_rename_0_canRename__3518__ETC___d14007 || - IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13631 || + NOT_regRenamingTable_rename_0_canRename__3528__ETC___d14017 || + IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13641 || fetchStage$pipelines_0_first[194:192] != 3'd1 ; - assign NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14312 = - NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14299 && - NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d14309 && + assign NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14322 = + NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14309 && + NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d14319 && (fetchStage$pipelines_1_first[194:192] == 3'd0 || fetchStage$pipelines_1_first[194:192] == 3'd1) && - SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__292_ETC___d14081 ; - assign NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14348 = + SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__292_ETC___d14091 ; + assign NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14358 = !fetchStage$pipelines_0_canDeq || - NOT_regRenamingTable_rename_0_canRename__3518__ETC___d14007 || + NOT_regRenamingTable_rename_0_canRename__3528__ETC___d14017 || fetchStage$pipelines_0_first[194:192] != 3'd3 && fetchStage$pipelines_0_first[194:192] != 3'd4 ; - assign NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14368 = - NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14299 && - regRenamingTable_rename_1_canRename__3637_AND__ETC___d14308 && + assign NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14378 = + NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14309 && + regRenamingTable_rename_1_canRename__3647_AND__ETC___d14318 && (fetchStage$pipelines_1_first[194:192] == 3'd3 || fetchStage$pipelines_1_first[194:192] == 3'd4) && - NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14348 && + NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14358 && coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq && - NOT_fetchStage_pipelines_1_first__2937_BITS_32_ETC___d14363 ; - assign NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14376 = + NOT_fetchStage_pipelines_1_first__2937_BITS_32_ETC___d14373 ; + assign NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14386 = (!fetchStage$pipelines_0_canDeq || - NOT_regRenamingTable_rename_0_canRename__3518__ETC___d14007 || + NOT_regRenamingTable_rename_0_canRename__3528__ETC___d14017 || fetchStage$pipelines_0_first[194:192] != 3'd2 || - IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13626) && + IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13636) && coreFix_memExe_rsMem$canEnq && CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q231 ; - assign NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14397 = - NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14299 && - regRenamingTable_rename_1_canRename__3637_AND__ETC___d14308 && + assign NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14407 = + NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14309 && + regRenamingTable_rename_1_canRename__3647_AND__ETC___d14318 && fetchStage$pipelines_1_first[194:192] == 3'd2 && - NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14376 && + NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14386 && fetchStage$pipelines_1_first[173] ; - assign NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14420 = - NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14301 && + assign NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14430 = + NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14311 && specTagManager$canClaim && - regRenamingTable_rename_1_canRename__3637_AND__ETC___d14308 && - IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13989 && + regRenamingTable_rename_1_canRename__3647_AND__ETC___d14318 && + IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13999 && fetchStage$pipelines_1_first[194:192] == 3'd1 ; assign NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13429 = (fetchStage$pipelines_0_first[194:192] != 3'd0 || @@ -23285,7 +23272,7 @@ module mkCore(CLK, rs1__h661842 == 5'd0 && imm__h661843 == 32'd0 || csr_addr__h661841[11:10] != 2'b11 ; - assign NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13538 = + assign NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13548 = fetchStage$pipelines_0_first[199:195] != 5'd0 && fetchStage$pipelines_0_first[199:195] != 5'd21 && fetchStage$pipelines_0_first[199:195] != 5'd17 && @@ -23296,64 +23283,64 @@ module mkCore(CLK, fetchStage$pipelines_0_first[199:195] != 5'd19 && fetchStage$pipelines_0_first[199:195] != 5'd20 && !fetchStage$pipelines_0_first[68] && - NOT_IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_295_ETC___d13533 && + NOT_IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_295_ETC___d13543 && rob$enqPort_0_canEnq && epochManager$checkEpoch_0_check ; - assign NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13575 = + assign NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13585 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && regRenamingTable$rename_0_canRename && - NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13538 && - IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13574 ; - assign NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13842 = + NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13548 && + IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13584 ; + assign NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13852 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && regRenamingTable$rename_0_canRename && - NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13538 && - fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d13841 ; - assign NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13848 = + NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13548 && + fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d13851 ; + assign NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13858 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && regRenamingTable$rename_0_canRename && - NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13538 && + NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13548 && (fetchStage$pipelines_0_first[194:192] == 3'd0 || fetchStage$pipelines_0_first[194:192] == 3'd1) && - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3548_co_ETC___d13558 && + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3558_co_ETC___d13568 && (!coreFix_aluExe_0_rsAlu$canEnq || - !coreFix_aluExe_0_rsAlu_approximateCount__3552__ETC___d13554) ; - assign NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d14000 = + !coreFix_aluExe_0_rsAlu_approximateCount__3562__ETC___d13564) ; + assign NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d14010 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && regRenamingTable$rename_0_canRename && - NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13538 && - IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13598 ; - assign NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d14173 = + NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13548 && + IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13608 ; + assign NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d14183 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && regRenamingTable$rename_0_canRename && !checkForException___d13160[4] && rob$enqPort_0_canEnq ; - assign NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d14273 = + assign NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d14283 = { fetchStage$pipelines_0_first[194:192] != 3'd2 || !coreFix_memExe_rsMem$canEnq || - IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13626 || - IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14215, + IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13636 || + IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14225, (fetchStage$pipelines_0_first[194:192] == 3'd2 && coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13570 && - IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14218) ? - IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14221 : + IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13580 && + IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14228) ? + IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14231 : { 1'h0, - IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14224 }, + IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14234 }, 7'd32, specTagManager$currentSpecBits } ; - assign NOT_fetchStage_pipelines_0_first__2928_BITS_32_ETC___d14197 = + assign NOT_fetchStage_pipelines_0_first__2928_BITS_32_ETC___d14207 = fetchStage$pipelines_0_first[323:260] != - fallthrough_pc__h671219 ; - assign NOT_fetchStage_pipelines_0_first__2928_BIT_68__ETC___d13586 = + fallthrough_pc__h671322 ; + assign NOT_fetchStage_pipelines_0_first__2928_BIT_68__ETC___d13596 = !fetchStage$pipelines_0_first[68] && !checkForException___d13160[4] && - NOT_csrf_fs_reg_read__1726_EQ_0_3149_3150_OR_N_ETC___d13531 && + NOT_csrf_fs_reg_read__1726_EQ_0_3149_3150_OR_N_ETC___d13541 && rob$enqPort_0_canEnq && epochManager$checkEpoch_0_check ; assign NOT_fetchStage_pipelines_1_canDeq__2934_2935_O_ETC___d12943 = @@ -23361,7 +23348,7 @@ module mkCore(CLK, fetchStage$RDY_pipelines_1_first && (epochManager$checkEpoch_1_check || fetchStage$RDY_pipelines_1_deq) ; - assign NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d13833 = + assign NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d13843 = fetchStage$pipelines_1_first[199:195] != 5'd0 && fetchStage$pipelines_1_first[199:195] != 5'd21 && fetchStage$pipelines_1_first[199:195] != 5'd17 && @@ -23372,27 +23359,27 @@ module mkCore(CLK, fetchStage$pipelines_1_first[199:195] != 5'd19 && fetchStage$pipelines_1_first[199:195] != 5'd20 && !fetchStage$pipelines_1_first[68] && - NOT_IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_295_ETC___d13824 && - rob_enqPort_1_canEnq__3826_AND_epochManager_ch_ETC___d13831 ; - assign NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d13835 = + NOT_IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_295_ETC___d13834 && + rob_enqPort_1_canEnq__3836_AND_epochManager_ch_ETC___d13841 ; + assign NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d13845 = (fetchStage$pipelines_1_first[194:192] != 3'd1 || (!fetchStage$pipelines_0_canDeq || - NOT_regRenamingTable_rename_0_canRename__3518__ETC___d13617 || - IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13631 || + NOT_regRenamingTable_rename_0_canRename__3528__ETC___d13627 || + IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13641 || fetchStage$pipelines_0_first[194:192] != 3'd1) && specTagManager$canClaim) && regRenamingTable$rename_1_canRename && - NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d13833 ; - assign NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d13946 = + NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d13843 ; + assign NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d13956 = (fetchStage$pipelines_1_first[194:192] != 3'd1 || (!fetchStage$pipelines_0_canDeq || - NOT_regRenamingTable_rename_0_canRename__3518__ETC___d13617 || - IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13940 || + NOT_regRenamingTable_rename_0_canRename__3528__ETC___d13627 || + IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13950 || fetchStage$pipelines_0_first[194:192] != 3'd1) && specTagManager$canClaim) && regRenamingTable$rename_1_canRename && - NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d13833 ; - assign NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d13967 = + NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d13843 ; + assign NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d13977 = fetchStage$pipelines_1_first[199:195] != 5'd0 && fetchStage$pipelines_1_first[199:195] != 5'd21 && fetchStage$pipelines_1_first[199:195] != 5'd17 && @@ -23403,9 +23390,9 @@ module mkCore(CLK, fetchStage$pipelines_1_first[199:195] != 5'd19 && fetchStage$pipelines_1_first[199:195] != 5'd20 && !fetchStage$pipelines_1_first[68] && - NOT_IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_295_ETC___d13824 && - rob_enqPort_1_canEnq__3826_AND_epochManager_ch_ETC___d13965 ; - assign NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d13984 = + NOT_IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_295_ETC___d13834 && + rob_enqPort_1_canEnq__3836_AND_epochManager_ch_ETC___d13975 ; + assign NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d13994 = fetchStage$pipelines_1_first[199:195] != 5'd0 && fetchStage$pipelines_1_first[199:195] != 5'd21 && fetchStage$pipelines_1_first[199:195] != 5'd17 && @@ -23416,26 +23403,26 @@ module mkCore(CLK, fetchStage$pipelines_1_first[199:195] != 5'd19 && fetchStage$pipelines_1_first[199:195] != 5'd20 && !fetchStage$pipelines_1_first[68] && - NOT_IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_295_ETC___d13824 && - rob_enqPort_1_canEnq__3826_AND_epochManager_ch_ETC___d13982 ; - assign NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d14309 = + NOT_IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_295_ETC___d13834 && + rob_enqPort_1_canEnq__3836_AND_epochManager_ch_ETC___d13992 ; + assign NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d14319 = (fetchStage$pipelines_1_first[194:192] != 3'd1 || - NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14301 && + NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14311 && specTagManager$canClaim) && - regRenamingTable_rename_1_canRename__3637_AND__ETC___d14308 ; - assign NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d14371 = + regRenamingTable_rename_1_canRename__3647_AND__ETC___d14318 ; + assign NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d14381 = (fetchStage$pipelines_1_first[194:192] == 3'd3 || fetchStage$pipelines_1_first[194:192] == 3'd4) && - NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14348 && + NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14358 && coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq && fetchStage$pipelines_1_first[173] ; - assign NOT_fetchStage_pipelines_1_first__2937_BITS_32_ETC___d14363 = + assign NOT_fetchStage_pipelines_1_first__2937_BITS_32_ETC___d14373 = fetchStage$pipelines_1_first[323:260] != - fallthrough_pc__h686965 ; - assign NOT_fetchStage_pipelines_1_first__2937_BIT_68__ETC___d14306 = + fallthrough_pc__h687068 ; + assign NOT_fetchStage_pipelines_1_first__2937_BIT_68__ETC___d14316 = !fetchStage$pipelines_1_first[68] && - !checkForException___d13797[4] && - NOT_csrf_fs_reg_read__1726_EQ_0_3149_3150_OR_N_ETC___d13822 && + !checkForException___d13807[4] && + NOT_csrf_fs_reg_read__1726_EQ_0_3149_3150_OR_N_ETC___d13832 && rob$enqPort_1_canEnq && epochManager$checkEpoch_1_check ; assign NOT_mmio_cRqQ_clearReq_dummy2_1_read__26_27_OR_ETC___d431 = @@ -23517,7 +23504,7 @@ module mkCore(CLK, (mmio_pRsQ_deqReq_dummy2_2$Q_OUT && (mmio_pRsQ_deqReq_lat_0$whas || mmio_pRsQ_deqReq_rl) || mmio_pRsQ_empty) ; - assign NOT_regRenamingTable_rename_0_canRename__3518__ETC___d13617 = + assign NOT_regRenamingTable_rename_0_canRename__3528__ETC___d13627 = !regRenamingTable$rename_0_canRename || fetchStage$pipelines_0_first[199:195] == 5'd0 || fetchStage$pipelines_0_first[199:195] == 5'd21 || @@ -23528,8 +23515,8 @@ module mkCore(CLK, fetchStage$pipelines_0_first[199:195] == 5'd15 || fetchStage$pipelines_0_first[199:195] == 5'd19 || fetchStage$pipelines_0_first[199:195] == 5'd20 || - fetchStage_pipelines_0_first__2928_BIT_68_2955_ETC___d13615 ; - assign NOT_regRenamingTable_rename_0_canRename__3518__ETC___d13952 = + fetchStage_pipelines_0_first__2928_BIT_68_2955_ETC___d13625 ; + assign NOT_regRenamingTable_rename_0_canRename__3528__ETC___d13962 = !regRenamingTable$rename_0_canRename || fetchStage$pipelines_0_first[199:195] == 5'd0 || fetchStage$pipelines_0_first[199:195] == 5'd21 || @@ -23540,13 +23527,13 @@ module mkCore(CLK, fetchStage$pipelines_0_first[199:195] == 5'd15 || fetchStage$pipelines_0_first[199:195] == 5'd19 || fetchStage$pipelines_0_first[199:195] == 5'd20 || - fetchStage_pipelines_0_first__2928_BIT_68_2955_ETC___d13615 ; - assign NOT_regRenamingTable_rename_0_canRename__3518__ETC___d14007 = + fetchStage_pipelines_0_first__2928_BIT_68_2955_ETC___d13625 ; + assign NOT_regRenamingTable_rename_0_canRename__3528__ETC___d14017 = !regRenamingTable$rename_0_canRename || fetchStage$pipelines_0_first[68] || checkForException___d13160[4] || !rob$enqPort_0_canEnq ; - assign NOT_regRenamingTable_rename_1_canRename__3637__ETC___d14065 = + assign NOT_regRenamingTable_rename_1_canRename__3647__ETC___d14075 = !regRenamingTable$rename_1_canRename || fetchStage$pipelines_1_first[199:195] == 5'd0 || fetchStage$pipelines_1_first[199:195] == 5'd21 || @@ -23557,15 +23544,15 @@ module mkCore(CLK, fetchStage$pipelines_1_first[199:195] == 5'd15 || fetchStage$pipelines_1_first[199:195] == 5'd19 || fetchStage$pipelines_1_first[199:195] == 5'd20 || - fetchStage_pipelines_1_first__2937_BIT_68_3665_ETC___d14063 ; - assign NOT_rob_deqPort_0_canDeq__4986_4987_OR_regRena_ETC___d15025 = + fetchStage_pipelines_1_first__2937_BIT_68_3675_ETC___d14073 ; + assign NOT_rob_deqPort_0_canDeq__4996_4997_OR_regRena_ETC___d15035 = (!rob$deqPort_0_canDeq || regRenamingTable$RDY_commit_0_commit && rob$RDY_deqPort_0_deq) && (!rob$deqPort_1_canDeq || rob$RDY_deqPort_1_deq_data && - NOT_rob_deqPort_1_deq_data__4993_BIT_25_4994_4_ETC___d15022) ; - assign NOT_rob_deqPort_0_canDeq__4986_4987_OR_rob_deq_ETC___d15178 = + NOT_rob_deqPort_1_deq_data__5003_BIT_25_5004_5_ETC___d15032) ; + assign NOT_rob_deqPort_0_canDeq__4996_4997_OR_rob_deq_ETC___d15188 = (!rob$deqPort_0_canDeq || rob$deqPort_0_deq_data[25] && !rob$deqPort_0_deq_data[18] && !rob$deqPort_0_deq_data[167] && @@ -23579,18 +23566,18 @@ module mkCore(CLK, rob$deqPort_0_deq_data[257:253] != 5'd19 && rob$deqPort_0_deq_data[257:253] != 5'd20) && rob$deqPort_1_canDeq ; - assign NOT_rob_deqPort_0_deq_data__4456_BITS_257_TO_2_ETC___d14778 = + assign NOT_rob_deqPort_0_deq_data__4466_BITS_257_TO_2_ETC___d14788 = rob$deqPort_0_deq_data[257:253] != 5'd13 || - (IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 != + (IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 != 6'd7 || csrf_stats_module_writeQ$FULL_N) && - (IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 != + (IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 != 6'd6 || csrf_terminate_module_terminateQ$FULL_N) ; - assign NOT_rob_deqPort_0_deq_data__4456_BITS_257_TO_2_ETC___d14972 = + assign NOT_rob_deqPort_0_deq_data__4466_BITS_257_TO_2_ETC___d14982 = (rob$deqPort_0_deq_data[257:253] == 5'd13) != rob$deqPort_0_deq_data[181] ; - assign NOT_rob_deqPort_1_deq_data__4993_BIT_25_4994_4_ETC___d15022 = + assign NOT_rob_deqPort_1_deq_data__5003_BIT_25_5004_5_ETC___d15032 = !rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[257:253] == 5'd0 || @@ -23603,16 +23590,16 @@ module mkCore(CLK, rob$deqPort_1_deq_data[257:253] == 5'd19 || rob$deqPort_1_deq_data[257:253] == 5'd20 || regRenamingTable$RDY_commit_1_commit && rob$RDY_deqPort_1_deq ; - assign NOT_specTagManager_canClaim__3516_3601_OR_NOT__ETC___d14086 = + assign NOT_specTagManager_canClaim__3526_3611_OR_NOT__ETC___d14096 = !specTagManager$canClaim || - NOT_regRenamingTable_rename_0_canRename__3518__ETC___d13952 || - IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14033 || + NOT_regRenamingTable_rename_0_canRename__3528__ETC___d13962 || + IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14043 || fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$RDY_nextSpecTag ; - assign NOT_specTagManager_canClaim__3516_3601_OR_NOT__ETC___d14151 = + assign NOT_specTagManager_canClaim__3526_3611_OR_NOT__ETC___d14161 = !specTagManager$canClaim || - NOT_regRenamingTable_rename_0_canRename__3518__ETC___d14007 || - IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14033 || + NOT_regRenamingTable_rename_0_canRename__3528__ETC___d14017 || + IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14043 || fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$RDY_nextSpecTag ; assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3013 = @@ -23633,29 +23620,29 @@ module mkCore(CLK, !CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q251, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3031, x__h296164 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d15326 = + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d15336 = { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q253, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q254, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q255 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15282 = + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15292 = { CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q236, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q237, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q238, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q239 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15291 = - { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15282, + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15301 = + { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15292, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q240, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q241 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15300 = - { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15291, + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15310 = + { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15301, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q245, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q246 } ; - assign SEL_ARR_fetchStage_pipelines_0_canDeq__2926_AN_ETC___d13897 = - SEL_ARR_fetchStage_pipelines_0_canDeq__2926_AN_ETC___d13867 || + assign SEL_ARR_fetchStage_pipelines_0_canDeq__2926_AN_ETC___d13907 = + SEL_ARR_fetchStage_pipelines_0_canDeq__2926_AN_ETC___d13877 || fetchStage$pipelines_1_first[194:192] == 3'd1 && - regRenamingTable_rename_0_canRename__3518_AND__ETC___d13602 || + regRenamingTable_rename_0_canRename__3528_AND__ETC___d13612 || !regRenamingTable$rename_1_canRename || - fetchStage_pipelines_1_first__2937_BITS_199_TO_ETC___d13894 ; + fetchStage_pipelines_1_first__2937_BITS_199_TO_ETC___d13904 ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10242 = { {4{f2_exp26523_MINUS_127__q168[7]}}, f2_exp26523_MINUS_127__q168 } ; @@ -24040,20 +24027,20 @@ module mkCore(CLK, guard__h450849 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d11193 = b__h608700 * b__h608712 ; - assign _0_OR_NOT_fetchStage_pipelines_0_first__2928_BI_ETC___d14014 = + assign _0_OR_NOT_fetchStage_pipelines_0_first__2928_BI_ETC___d14024 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$RDY_nextSpecTag) && - CASE_k74927_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232 ; - assign _0_OR_NOT_fetchStage_pipelines_1_first__2937_BI_ETC___d14099 = + CASE_k75030_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232 ; + assign _0_OR_NOT_fetchStage_pipelines_1_first__2937_BI_ETC___d14109 = (fetchStage$pipelines_1_first[194:192] != 3'd1 || specTagManager$RDY_nextSpecTag) && CASE_fetchStage_pipelines_0_canDeq__2926_AND_N_ETC__q234 ; - assign _0_OR_fetchStage_RDY_pipelines_0_first__2925_39_ETC___d13922 = + assign _0_OR_fetchStage_RDY_pipelines_0_first__2925_39_ETC___d13932 = fetchStage$RDY_pipelines_0_first && fetchStage$pipelines_1_first[194:192] == 3'd1 && - regRenamingTable_rename_0_canRename__3518_AND__ETC___d13602 || + regRenamingTable_rename_0_canRename__3528_AND__ETC___d13612 || !regRenamingTable$rename_1_canRename || - fetchStage_pipelines_1_first__2937_BITS_199_TO_ETC___d13894 ; + fetchStage_pipelines_1_first__2937_BITS_199_TO_ETC___d13904 ; assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d10249 = sfd__h526885 >> _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d10245 ; @@ -24078,10 +24065,10 @@ module mkCore(CLK, (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7434[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7434) ; - assign _0b0_CONCAT_csrf_medeleg_15_reg_read__1825_1826_ETC___d14634 = - medeleg_csr__read__h617230[i__h708608] ; - assign _0b0_CONCAT_csrf_mideleg_11_reg_read__1833_1834_ETC___d14615 = - mideleg_csr__read__h617325[i__h708768] ; + assign _0b0_CONCAT_csrf_medeleg_15_reg_read__1825_1826_ETC___d14644 = + medeleg_csr__read__h617230[i__h708711] ; + assign _0b0_CONCAT_csrf_mideleg_11_reg_read__1833_1834_ETC___d14625 = + mideleg_csr__read__h617325[i__h708871] ; assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4107 = 12'd3074 - { 6'd0, @@ -24669,46 +24656,46 @@ module mkCore(CLK, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7431 ; assign _dfoo12 = fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3518_AND__ETC___d14211 || - NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14299 && - regRenamingTable_rename_1_canRename__3637_AND__ETC___d14308 && + regRenamingTable_rename_0_canRename__3528_AND__ETC___d14221 || + NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14309 && + regRenamingTable_rename_1_canRename__3647_AND__ETC___d14318 && fetchStage$pipelines_1_first[194:192] == 3'd2 && - NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14376 && + NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14386 && fetchStage$pipelines_1_first[199:195] != 5'd14 ; assign _dfoo18 = - k__h674927 == 1'd0 && - fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14176 || - fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14295 == + k__h675030 == 1'd0 && + fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14186 || + fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14305 == 1'd0 && - NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14312 ; + NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14322 ; assign _dfoo2 = fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3518_AND__ETC___d14253 || - NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14299 && - regRenamingTable_rename_1_canRename__3637_AND__ETC___d14308 && + regRenamingTable_rename_0_canRename__3528_AND__ETC___d14263 || + NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14309 && + regRenamingTable_rename_1_canRename__3647_AND__ETC___d14318 && fetchStage$pipelines_1_first[194:192] == 3'd2 && - NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14376 && + NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14386 && fetchStage$pipelines_1_first[191:189] != 3'd0 && fetchStage$pipelines_1_first[191:189] != 3'd2 ; assign _dfoo20 = rob$deqPort_0_deq_data[257:253] == 5'd13 && - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd18 || rob$deqPort_0_deq_data[257:253] == 5'd20 ; assign _dfoo26 = rob$deqPort_0_deq_data[257:253] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + (IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd8 || - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd18) || rob$deqPort_0_deq_data[257:253] == 5'd19 ; assign _dfoo7 = fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3518_AND__ETC___d14245 || - NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14299 && - regRenamingTable_rename_1_canRename__3637_AND__ETC___d14308 && + regRenamingTable_rename_0_canRename__3528_AND__ETC___d14255 || + NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14309 && + regRenamingTable_rename_1_canRename__3647_AND__ETC___d14318 && fetchStage$pipelines_1_first[194:192] == 3'd2 && - NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14376 && + NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14386 && (fetchStage$pipelines_1_first[191:189] == 3'd0 || fetchStage$pipelines_1_first[191:189] == 3'd2) ; assign _dor1coreFix_aluExe_0_bypassWire_2$EN_wset = @@ -27575,10 +27562,10 @@ module mkCore(CLK, assign b__h608599 = { {64{b__h608376[63]}}, b__h608376 } ; assign b__h608700 = { 64'd0, a__h608375 } ; assign b__h608712 = { 64'd0, b__h608376 } ; - assign base__h711516 = { csrf_stvec_base_hi_reg, 2'b0 } ; - assign base__h711536 = { csrf_mtvec_base_hi_reg, 2'b0 } ; - assign cause_code__h708593 = - commitStage_commitTrap[36] ? i__h708768 : i__h708608 ; + assign base__h711619 = { csrf_stvec_base_hi_reg, 2'b0 } ; + assign base__h711639 = { csrf_mtvec_base_hi_reg, 2'b0 } ; + assign cause_code__h708696 = + commitStage_commitTrap[36] ? i__h708871 : i__h708711 ; assign coreFix_aluExe_0_bypassWire_0_wget__2367_BITS__ETC___d12369 = coreFix_aluExe_0_bypassWire_0$wget[70:64] == coreFix_aluExe_0_dispToRegQ$first[84:78] ; @@ -27620,7 +27607,7 @@ module mkCore(CLK, (coreFix_aluExe_0_exeToFinQ$first[326:322] != 5'd9 && coreFix_aluExe_0_exeToFinQ$first[326:322] != 5'd10 || coreFix_trainBPQ_0$FULL_N) ; - assign coreFix_aluExe_0_rsAlu_approximateCount__3552__ETC___d13554 = + assign coreFix_aluExe_0_rsAlu_approximateCount__3562__ETC___d13564 = coreFix_aluExe_0_rsAlu$approximateCount < coreFix_aluExe_1_rsAlu$approximateCount ; assign coreFix_aluExe_1_bypassWire_0_wget__1511_BITS__ETC___d11513 = @@ -27813,11 +27800,11 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107:76] ; assign coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q3 = coreFix_fpuMulDivExe_0_regToExeQ$first[171:140] ; - assign coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__40_ETC___d14106 = + assign coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__40_ETC___d14116 = coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_enq && regRenamingTable$RDY_rename_1_getRename && (!fetchStage$pipelines_0_canDeq || - NOT_specTagManager_canClaim__3516_3601_OR_NOT__ETC___d14086) ; + NOT_specTagManager_canClaim__3526_3611_OR_NOT__ETC___d14096) ; assign coreFix_memExe_bypassWire_0_wget__585_BITS_70__ETC___d1587 = coreFix_aluExe_0_bypassWire_0$wget[70:64] == coreFix_memExe_dispToRegQ$first[61:55] ; @@ -28204,14 +28191,14 @@ module mkCore(CLK, !coreFix_memExe_respLrScAmoQ_deqReq_lat_0$whas && !coreFix_memExe_respLrScAmoQ_deqReq_rl) && coreFix_memExe_respLrScAmoQ_full ; - assign coreFix_memExe_stb_isEmpty__011_AND_coreFix_me_ETC___d14783 = + assign coreFix_memExe_stb_isEmpty__011_AND_coreFix_me_ETC___d14793 = coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty && regRenamingTable$RDY_commit_0_commit && rob$RDY_deqPort_0_deq && rob$RDY_deqPort_0_deq_data && fetchStage$iTlbIfc_noPendingReq && coreFix_memExe_dTlb$noPendingReq && - NOT_rob_deqPort_0_deq_data__4456_BITS_257_TO_2_ETC___d14778 ; + NOT_rob_deqPort_0_deq_data__4466_BITS_257_TO_2_ETC___d14788 ; assign csr_addr__h661841 = fetchStage$pipelines_0_first[173] ? IF_fetchStage_pipelines_0_first__2928_BITS_172_ETC___d13125 : @@ -28238,7 +28225,7 @@ module mkCore(CLK, (fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d13190 || csrf_prv_reg_read__2956_ULT_IF_fetchStage_pipe_ETC___d13192 || csr_addr__h661841 == 12'h8FF) ; - assign csrf_fs_reg_read__1726_EQ_0_3149_AND_fetchStag_ETC___d13610 = + assign csrf_fs_reg_read__1726_EQ_0_3149_AND_fetchStag_ETC___d13620 = csrf_fs_reg == 2'd0 && (fetchStage$pipelines_0_first[95] && fetchStage$pipelines_0_first[94] || @@ -28250,7 +28237,7 @@ module mkCore(CLK, fetchStage$pipelines_0_first[231:200] == 32'h10500073 && csrf_tw_reg && csrf_prv_reg != 2'd3 ; - assign csrf_fs_reg_read__1726_EQ_0_3149_AND_fetchStag_ETC___d13886 = + assign csrf_fs_reg_read__1726_EQ_0_3149_AND_fetchStag_ETC___d13896 = csrf_fs_reg == 2'd0 && (fetchStage$pipelines_1_first[95] && fetchStage$pipelines_1_first[94] || @@ -28262,12 +28249,12 @@ module mkCore(CLK, fetchStage$pipelines_1_first[231:200] == 32'h10500073 && csrf_tw_reg && csrf_prv_reg != 2'd3 ; - assign csrf_prv_reg_read__2956_ULE_1_4597_AND_IF_comm_ETC___d14636 = - csrf_prv_reg_read__2956_ULE_1___d14597 && + assign csrf_prv_reg_read__2956_ULE_1_4607_AND_IF_comm_ETC___d14646 = + csrf_prv_reg_read__2956_ULE_1___d14607 && (commitStage_commitTrap[36] ? - _0b0_CONCAT_csrf_mideleg_11_reg_read__1833_1834_ETC___d14615 : - _0b0_CONCAT_csrf_medeleg_15_reg_read__1825_1826_ETC___d14634) ; - assign csrf_prv_reg_read__2956_ULE_1___d14597 = csrf_prv_reg <= 2'd1 ; + _0b0_CONCAT_csrf_mideleg_11_reg_read__1833_1834_ETC___d14625 : + _0b0_CONCAT_csrf_medeleg_15_reg_read__1825_1826_ETC___d14644) ; + assign csrf_prv_reg_read__2956_ULE_1___d14607 = csrf_prv_reg <= 2'd1 ; assign csrf_prv_reg_read__2956_ULT_IF_fetchStage_pipe_ETC___d13192 = csrf_prv_reg < csr_addr__h661841[9:8] ; assign data79264_BITS_31_TO_0__q2 = data__h479264[31:0] ; @@ -28344,21 +28331,21 @@ module mkCore(CLK, (coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] : 23'd4194304 ; - assign fallthrough_pc__h671219 = + assign fallthrough_pc__h671322 = (fetchStage$pipelines_0_first[97:96] == 2'b11) ? fetchStage$pipelines_0_first[387:324] + 64'd4 : fetchStage$pipelines_0_first[387:324] + 64'd2 ; - assign fallthrough_pc__h686965 = + assign fallthrough_pc__h687068 = (fetchStage$pipelines_1_first[97:96] == 2'b11) ? fetchStage$pipelines_1_first[387:324] + 64'd4 : fetchStage$pipelines_1_first[387:324] + 64'd2 ; assign fcsr_csr__read__h616236 = { 56'd0, x__h619376 } ; - assign fetchStage_RDY_pipelines_0_first__2925_AND_NOT_ETC___d13541 = + assign fetchStage_RDY_pipelines_0_first__2925_AND_NOT_ETC___d13551 = fetchStage$RDY_pipelines_0_first && (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && regRenamingTable$rename_0_canRename && - NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13538 ; + NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13548 ; assign fetchStage_RDY_pipelines_0_first__2925_AND_epo_ETC___d13407 = fetchStage$RDY_pipelines_0_first && epochManager$RDY_incrementEpoch && @@ -28367,86 +28354,86 @@ module mkCore(CLK, rob$RDY_enqPort_0_enq && (fetchStage$pipelines_0_first[194:192] != 3'd0 || coreFix_aluExe_0_rsAlu$RDY_enq) ; - assign fetchStage_RDY_pipelines_0_first__2925_AND_fet_ETC___d13607 = + assign fetchStage_RDY_pipelines_0_first__2925_AND_fet_ETC___d13617 = fetchStage$RDY_pipelines_0_first && fetchStage$pipelines_1_first[194:192] == 3'd1 && - regRenamingTable_rename_0_canRename__3518_AND__ETC___d13602 || + regRenamingTable_rename_0_canRename__3528_AND__ETC___d13612 || !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first && - IF_fetchStage_RDY_pipelines_0_first__2925_AND__ETC___d13545 ; - assign fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14097 = + IF_fetchStage_RDY_pipelines_0_first__2925_AND__ETC___d13555 ; + assign fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14107 = fetchStage$pipelines_0_canDeq && (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3518_AND__ETC___d13588 && - fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d13841 || + regRenamingTable_rename_0_canRename__3528_AND__ETC___d13598 && + fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d13851 || !coreFix_aluExe_0_rsAlu$canEnq || - NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14096 ; - assign fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14176 = + NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14106 ; + assign fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14186 = fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d14173 && + NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d14183 && (fetchStage$pipelines_0_first[194:192] == 3'd0 || fetchStage$pipelines_0_first[194:192] == 3'd1) && - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3548_co_ETC___d13558 ; - assign fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14295 = + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3558_co_ETC___d13568 ; + assign fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14305 = fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d14173 && - fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d13841 || + NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d14183 && + fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d13851 || !coreFix_aluExe_0_rsAlu$canEnq || (!fetchStage$pipelines_0_canDeq || - fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d14290 || + fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d14300 || fetchStage$pipelines_0_first[194:192] != 3'd0 && fetchStage$pipelines_0_first[194:192] != 3'd1 || - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3548_co_ETC___d13558) && + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3558_co_ETC___d13568) && coreFix_aluExe_1_rsAlu$canEnq && - !coreFix_aluExe_0_rsAlu_approximateCount__3552__ETC___d13554 ; - assign fetchStage_pipelines_0_canDeq__2926_AND_fetchS_ETC___d14165 = + !coreFix_aluExe_0_rsAlu_approximateCount__3562__ETC___d13564 ; + assign fetchStage_pipelines_0_canDeq__2926_AND_fetchS_ETC___d14175 = fetchStage$pipelines_0_canDeq && - fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d14048 || + fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d14058 || !fetchStage$pipelines_1_canDeq || fetchStage$RDY_pipelines_1_first && - (fetchStage_pipelines_1_first__2937_BITS_194_TO_ETC___d14059 || - NOT_regRenamingTable_rename_1_canRename__3637__ETC___d14065 || - IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d14161) && - IF_fetchStage_RDY_pipelines_1_first__2936_AND__ETC___d13992 ; - assign fetchStage_pipelines_0_canDeq__2926_AND_regRen_ETC___d14103 = + (fetchStage_pipelines_1_first__2937_BITS_194_TO_ETC___d14069 || + NOT_regRenamingTable_rename_1_canRename__3647__ETC___d14075 || + IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d14171) && + IF_fetchStage_RDY_pipelines_1_first__2936_AND__ETC___d14002 ; + assign fetchStage_pipelines_0_canDeq__2926_AND_regRen_ETC___d14113 = fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3518_AND__ETC___d13588 && + regRenamingTable_rename_0_canRename__3528_AND__ETC___d13598 && (fetchStage$pipelines_0_first[194:192] == 3'd3 || fetchStage$pipelines_0_first[194:192] == 3'd4) ; - assign fetchStage_pipelines_0_canDeq__2926_AND_regRen_ETC___d14110 = + assign fetchStage_pipelines_0_canDeq__2926_AND_regRen_ETC___d14120 = fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3518_AND__ETC___d13588 && + regRenamingTable_rename_0_canRename__3528_AND__ETC___d13598 && fetchStage$pipelines_0_first[194:192] == 3'd2 && - IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13570 || + IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13580 || !coreFix_memExe_rsMem$canEnq || CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q230 ; - assign fetchStage_pipelines_0_canDeq__2926_AND_regRen_ETC___d14131 = - fetchStage_pipelines_0_canDeq__2926_AND_regRen_ETC___d14103 || + assign fetchStage_pipelines_0_canDeq__2926_AND_regRen_ETC___d14141 = + fetchStage_pipelines_0_canDeq__2926_AND_regRen_ETC___d14113 || !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq || fetchStage$pipelines_0_canDeq && (fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || - NOT_regRenamingTable_rename_0_canRename__3518__ETC___d13617 || - IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14123) ; - assign fetchStage_pipelines_0_canDeq__2926_AND_regRen_ETC___d14142 = - fetchStage_pipelines_0_canDeq__2926_AND_regRen_ETC___d14110 || + NOT_regRenamingTable_rename_0_canRename__3528__ETC___d13627 || + IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14133) ; + assign fetchStage_pipelines_0_canDeq__2926_AND_regRen_ETC___d14152 = + fetchStage_pipelines_0_canDeq__2926_AND_regRen_ETC___d14120 || fetchStage$pipelines_0_canDeq && (fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || - NOT_regRenamingTable_rename_0_canRename__3518__ETC___d13617 || - IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14134) ; - assign fetchStage_pipelines_0_canDeq__2926_AND_regRen_ETC___d14431 = + NOT_regRenamingTable_rename_0_canRename__3528__ETC___d13627 || + IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14144) ; + assign fetchStage_pipelines_0_canDeq__2926_AND_regRen_ETC___d14441 = fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3518_AND__ETC___d14429 || + regRenamingTable_rename_0_canRename__3528_AND__ETC___d14439 || !coreFix_memExe_rsMem$canEnq || CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q230 ; - assign fetchStage_pipelines_0_canDeq__2926_AND_specTa_ETC___d14259 = + assign fetchStage_pipelines_0_canDeq__2926_AND_specTa_ETC___d14269 = fetchStage$pipelines_0_canDeq && specTagManager$canClaim && regRenamingTable$rename_0_canRename && !checkForException___d13160[4] && rob$enqPort_0_canEnq && - IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13598 && + IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13608 && fetchStage$pipelines_0_first[194:192] == 3'd1 ; assign fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d13190 = (fetchStage$pipelines_0_first[194:192] == 3'd0 && @@ -28454,21 +28441,21 @@ module mkCore(CLK, rs1__h661842 != 5'd0 || imm__h661843 != 32'd0) && csr_addr__h661841[11:10] == 2'b11 ; - assign fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d13841 = + assign fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d13851 = (fetchStage$pipelines_0_first[194:192] == 3'd0 || fetchStage$pipelines_0_first[194:192] == 3'd1) && - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3548_co_ETC___d13558 && + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3558_co_ETC___d13568 && (!coreFix_aluExe_1_rsAlu$canEnq || - coreFix_aluExe_0_rsAlu_approximateCount__3552__ETC___d13554) ; - assign fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d13862 = + coreFix_aluExe_0_rsAlu_approximateCount__3562__ETC___d13564) ; + assign fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d13872 = fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || !regRenamingTable$rename_0_canRename || - fetchStage_pipelines_0_first__2928_BITS_199_TO_ETC___d13855 || + fetchStage_pipelines_0_first__2928_BITS_199_TO_ETC___d13865 || fetchStage$pipelines_0_first[194:192] != 3'd0 && fetchStage$pipelines_0_first[194:192] != 3'd1 || - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3548_co_ETC___d13558 ; - assign fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d13934 = + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3558_co_ETC___d13568 ; + assign fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d13944 = fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || fetchStage$pipelines_0_first[68] || @@ -28484,45 +28471,45 @@ module mkCore(CLK, IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[9] || IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[10] || IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[11] ; - assign fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d14042 = + assign fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d14052 = fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || - NOT_regRenamingTable_rename_0_canRename__3518__ETC___d14007 || - IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14031 && - IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14040 ; - assign fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d14048 = + NOT_regRenamingTable_rename_0_canRename__3528__ETC___d14017 || + IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14041 && + IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14050 ; + assign fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d14058 = fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || - NOT_regRenamingTable_rename_0_canRename__3518__ETC___d14007 || - IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14047 ; - assign fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d14070 = + NOT_regRenamingTable_rename_0_canRename__3528__ETC___d14017 || + IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14057 ; + assign fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d14080 = fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || !regRenamingTable$rename_0_canRename || - fetchStage_pipelines_0_first__2928_BITS_199_TO_ETC___d13855 || + fetchStage_pipelines_0_first__2928_BITS_199_TO_ETC___d13865 || fetchStage$pipelines_0_first[194:192] != 3'd0 && fetchStage$pipelines_0_first[194:192] != 3'd1 || - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3548_co_ETC___d13558 || + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3558_co_ETC___d13568 || coreFix_aluExe_1_rsAlu$canEnq && - !coreFix_aluExe_0_rsAlu_approximateCount__3552__ETC___d13554 ; - assign fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d14077 = + !coreFix_aluExe_0_rsAlu_approximateCount__3562__ETC___d13564 ; + assign fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d14087 = fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || !regRenamingTable$rename_0_canRename || - fetchStage_pipelines_0_first__2928_BITS_199_TO_ETC___d13855 || + fetchStage_pipelines_0_first__2928_BITS_199_TO_ETC___d13865 || fetchStage$pipelines_0_first[194:192] != 3'd0 && fetchStage$pipelines_0_first[194:192] != 3'd1 || - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3548_co_ETC___d13558 || + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3558_co_ETC___d13568 || coreFix_aluExe_0_rsAlu$canEnq && - coreFix_aluExe_0_rsAlu_approximateCount__3552__ETC___d13554 ; - assign fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d14290 = + coreFix_aluExe_0_rsAlu_approximateCount__3562__ETC___d13564 ; + assign fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d14300 = fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || !regRenamingTable$rename_0_canRename || fetchStage$pipelines_0_first[68] || checkForException___d13160[4] || !rob$enqPort_0_canEnq ; - assign fetchStage_pipelines_0_first__2928_BITS_199_TO_ETC___d13855 = + assign fetchStage_pipelines_0_first__2928_BITS_199_TO_ETC___d13865 = fetchStage$pipelines_0_first[199:195] == 5'd0 || fetchStage$pipelines_0_first[199:195] == 5'd21 || fetchStage$pipelines_0_first[199:195] == 5'd17 || @@ -28533,21 +28520,44 @@ module mkCore(CLK, fetchStage$pipelines_0_first[199:195] == 5'd19 || fetchStage$pipelines_0_first[199:195] == 5'd20 || fetchStage$pipelines_0_first[68] || - IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d13852 || + IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d13862 || !rob$enqPort_0_canEnq || !epochManager$checkEpoch_0_check ; - assign fetchStage_pipelines_0_first__2928_BIT_68_2955_ETC___d13615 = + assign fetchStage_pipelines_0_first__2928_BIT_173_304_ETC___d13522 = + { fetchStage$pipelines_0_first[173], + IF_fetchStage_pipelines_0_first__2928_BITS_172_ETC___d13125, + 73'h1280000000000000000, + fetchStage$pipelines_0_first[323:260], + 5'd0, + (fetchStage$pipelines_0_first[173] && + fetchStage$pipelines_0_first[199:195] == 5'd13 && + (fetchStage$pipelines_0_first[172:161] == 12'd1 || + fetchStage$pipelines_0_first[172:161] == 12'd2 || + fetchStage$pipelines_0_first[172:161] == 12'd3)) ? + fetchStage$pipelines_0_first[194:192] == 3'd0 && + fetchStage$pipelines_0_first[178:174] == 5'd15 || + (!fetchStage$pipelines_0_first[88] || + fetchStage$pipelines_0_first[87] || + fetchStage$pipelines_0_first[86:82] != 5'd0) && + (!fetchStage$pipelines_0_first[160] || + fetchStage$pipelines_0_first[159:128] != 32'd0) : + fetchStage$pipelines_0_first[75] && + fetchStage$pipelines_0_first[74], + fetchStage$pipelines_0_first[194:192] != 3'd0, + 13'h1521, + specTagManager$currentSpecBits } ; + assign fetchStage_pipelines_0_first__2928_BIT_68_2955_ETC___d13625 = fetchStage$pipelines_0_first[68] || checkForException___d13160[4] || - csrf_fs_reg_read__1726_EQ_0_3149_AND_fetchStag_ETC___d13610 || + csrf_fs_reg_read__1726_EQ_0_3149_AND_fetchStag_ETC___d13620 || !rob$enqPort_0_canEnq || !epochManager$checkEpoch_0_check ; - assign fetchStage_pipelines_1_first__2937_BITS_194_TO_ETC___d14059 = + assign fetchStage_pipelines_1_first__2937_BITS_194_TO_ETC___d14069 = fetchStage$pipelines_1_first[194:192] == 3'd1 && (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3518_AND__ETC___d14056 || + regRenamingTable_rename_0_canRename__3528_AND__ETC___d14066 || !specTagManager$canClaim) ; - assign fetchStage_pipelines_1_first__2937_BITS_199_TO_ETC___d13894 = + assign fetchStage_pipelines_1_first__2937_BITS_199_TO_ETC___d13904 = fetchStage$pipelines_1_first[199:195] == 5'd0 || fetchStage$pipelines_1_first[199:195] == 5'd21 || fetchStage$pipelines_1_first[199:195] == 5'd17 || @@ -28558,27 +28568,27 @@ module mkCore(CLK, fetchStage$pipelines_1_first[199:195] == 5'd19 || fetchStage$pipelines_1_first[199:195] == 5'd20 || fetchStage$pipelines_1_first[68] || - IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d13888 || + IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d13898 || !rob$enqPort_1_canEnq || !epochManager$checkEpoch_1_check || !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first && - IF_fetchStage_RDY_pipelines_0_first__2925_AND__ETC___d13545 ; - assign fetchStage_pipelines_1_first__2937_BIT_173_369_ETC___d13775 = + IF_fetchStage_RDY_pipelines_0_first__2925_AND__ETC___d13555 ; + assign fetchStage_pipelines_1_first__2937_BIT_173_370_ETC___d13785 = { fetchStage$pipelines_1_first[173], - CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q229 } ; - assign fetchStage_pipelines_1_first__2937_BIT_68_3665_ETC___d14063 = + CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q228 } ; + assign fetchStage_pipelines_1_first__2937_BIT_68_3675_ETC___d14073 = fetchStage$pipelines_1_first[68] || - checkForException___d13797[4] || - csrf_fs_reg_read__1726_EQ_0_3149_AND_fetchStag_ETC___d13886 || + checkForException___d13807[4] || + csrf_fs_reg_read__1726_EQ_0_3149_AND_fetchStag_ETC___d13896 || !rob$enqPort_1_canEnq || !epochManager$checkEpoch_1_check || fetchStage$pipelines_0_canDeq && - fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d14048 ; - assign fflags__h723294 = - NOT_rob_deqPort_0_canDeq__4986_4987_OR_rob_deq_ETC___d15178 ? - y_avValue_fst__h723241 : - IF_rob_deqPort_0_canDeq__4986_THEN_IF_NOT_rob__ETC___d15185 ; + fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d14058 ; + assign fflags__h723397 = + NOT_rob_deqPort_0_canDeq__4996_4997_OR_rob_deq_ETC___d15188 ? + y_avValue_fst__h723344 : + IF_rob_deqPort_0_canDeq__4996_THEN_IF_NOT_rob__ETC___d15195 ; assign fflags_csr__read__h616211 = { 59'd0, csrf_fflags_reg } ; assign frm_csr__read__h616222 = { 61'd0, csrf_frm_reg } ; assign guard__h350748 = @@ -28650,22 +28660,22 @@ module mkCore(CLK, assign guard__h595494 = { IF_theResult___snd03430_BIT_4_THEN_2_ELSE_0__q151[1], { _theResult___snd__h603430[3:0], 52'd0 } != 56'd0 } ; - assign idx__h690522 = + assign idx__h690625 = fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13842 || + NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13852 || !coreFix_aluExe_0_rsAlu$canEnq || (!fetchStage$pipelines_0_canDeq || - fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d13862) && + fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d13872) && coreFix_aluExe_1_rsAlu$canEnq && - !coreFix_aluExe_0_rsAlu_approximateCount__3552__ETC___d13554 ; + !coreFix_aluExe_0_rsAlu_approximateCount__3562__ETC___d13564 ; assign imm__h661843 = fetchStage$pipelines_0_first[160] ? fetchStage$pipelines_0_first[159:128] : 32'd0 ; - assign k__h674927 = + assign k__h675030 = !coreFix_aluExe_0_rsAlu$canEnq || coreFix_aluExe_1_rsAlu$canEnq && - !coreFix_aluExe_0_rsAlu_approximateCount__3552__ETC___d13554 ; + !coreFix_aluExe_0_rsAlu_approximateCount__3562__ETC___d13564 ; assign mcause_csr__read__h617878 = { r1__read__h620839, csrf_mcause_code_reg } ; assign mcounteren_csr__read__h617623 = @@ -28726,10 +28736,10 @@ module mkCore(CLK, fetchStage$pipelines_0_first[199:195] == 5'd15 || fetchStage$pipelines_0_first[199:195] == 5'd19 || fetchStage$pipelines_0_first[199:195] == 5'd20) ; - assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14170 = + assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14180 = mmio_pRqQ_empty && epochManager$checkEpoch_0_check && !fetchStage$pipelines_0_first[68] && - NOT_IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_295_ETC___d13533 && + NOT_IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_295_ETC___d13543 && fetchStage$pipelines_0_first[199:195] != 5'd0 && fetchStage$pipelines_0_first[199:195] != 5'd21 && fetchStage$pipelines_0_first[199:195] != 5'd17 && @@ -28796,7 +28806,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[95:32] : csrf_mcycle_ehr_data_rl) : 64'd0 ; - assign n__read__h720223 = + assign n__read__h720326 = csrf_minstret_ehr_data_dummy2_1$Q_OUT ? IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8 : 64'd0 ; @@ -28814,10 +28824,10 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP + 1'd1 ; assign next_deqP___1__h333641 = coreFix_memExe_memRespLdQ_deqP + 1'd1 ; assign next_deqP___1__h336866 = coreFix_memExe_forwardQ_deqP + 1'd1 ; - assign next_pc__h719433 = + assign next_pc__h719536 = (rob$deqPort_0_deq_data[97:96] == 2'd0) ? rob$deqPort_0_deq_data[95:32] : - rob_deqPort_0_deq_data__4456_BITS_353_TO_290_4_ETC___d14959 ; + rob_deqPort_0_deq_data__4466_BITS_353_TO_290_4_ETC___d14969 ; assign out___1_sfd__h487593 = { f1_sfd__h487530, 29'd0 } ; assign out___1_sfd__h526587 = { f2_sfd__h526524, 29'd0 } ; assign out___1_sfd__h565891 = { f3_sfd__h565828, 29'd0 } ; @@ -29031,8 +29041,8 @@ module mkCore(CLK, 1'd0, csrf_software_int_en_vec_1 & csrf_software_int_pend_vec_1, 1'd0 } ; - assign prv__h724809 = csrf_prv_reg ; - assign prv__h724853 = csrf_mprv_reg ? csrf_mpp_reg : csrf_prv_reg ; + assign prv__h724912 = csrf_prv_reg ; + assign prv__h724956 = csrf_mprv_reg ? csrf_mpp_reg : csrf_prv_reg ; assign q___1__h480783 = 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[203:140] ; @@ -29155,17 +29165,17 @@ module mkCore(CLK, 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[139:76] ; assign r__h619423 = csrf_fs_reg == 2'b11 ; - assign regRenamingTable_RDY_rename_0_getRename__3398__ETC___d14027 = + assign regRenamingTable_RDY_rename_0_getRename__3398__ETC___d14037 = regRenamingTable$RDY_rename_0_getRename && CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q233 && (fetchStage$pipelines_0_first[199:195] == 5'd14 || coreFix_memExe_rsMem$RDY_enq) ; - assign regRenamingTable_RDY_rename_1_getRename__4083__ETC___d14101 = + assign regRenamingTable_RDY_rename_1_getRename__4093__ETC___d14111 = regRenamingTable$RDY_rename_1_getRename && (!fetchStage$pipelines_0_canDeq || - NOT_specTagManager_canClaim__3516_3601_OR_NOT__ETC___d14086) && - _0_OR_NOT_fetchStage_pipelines_1_first__2937_BI_ETC___d14099 ; - assign regRenamingTable_rename_0_canRename__3518_AND__ETC___d13588 = + NOT_specTagManager_canClaim__3526_3611_OR_NOT__ETC___d14096) && + _0_OR_NOT_fetchStage_pipelines_1_first__2937_BI_ETC___d14109 ; + assign regRenamingTable_rename_0_canRename__3528_AND__ETC___d13598 = regRenamingTable$rename_0_canRename && fetchStage$pipelines_0_first[199:195] != 5'd0 && fetchStage$pipelines_0_first[199:195] != 5'd21 && @@ -29176,40 +29186,40 @@ module mkCore(CLK, fetchStage$pipelines_0_first[199:195] != 5'd15 && fetchStage$pipelines_0_first[199:195] != 5'd19 && fetchStage$pipelines_0_first[199:195] != 5'd20 && - NOT_fetchStage_pipelines_0_first__2928_BIT_68__ETC___d13586 ; - assign regRenamingTable_rename_0_canRename__3518_AND__ETC___d13602 = - regRenamingTable_rename_0_canRename__3518_AND__ETC___d13588 && - IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13598 && + NOT_fetchStage_pipelines_0_first__2928_BIT_68__ETC___d13596 ; + assign regRenamingTable_rename_0_canRename__3528_AND__ETC___d13612 = + regRenamingTable_rename_0_canRename__3528_AND__ETC___d13598 && + IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13608 && fetchStage$pipelines_0_first[194:192] == 3'd1 || !specTagManager$canClaim ; - assign regRenamingTable_rename_0_canRename__3518_AND__ETC___d13917 = - regRenamingTable_rename_0_canRename__3518_AND__ETC___d13588 && + assign regRenamingTable_rename_0_canRename__3528_AND__ETC___d13927 = + regRenamingTable_rename_0_canRename__3528_AND__ETC___d13598 && fetchStage$pipelines_0_first[194:192] == 3'd2 && - IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13570 || + IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13580 || !coreFix_memExe_rsMem$canEnq || CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q230 ; - assign regRenamingTable_rename_0_canRename__3518_AND__ETC___d14056 = + assign regRenamingTable_rename_0_canRename__3528_AND__ETC___d14066 = regRenamingTable$rename_0_canRename && !checkForException___d13160[4] && rob$enqPort_0_canEnq && - IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14054 && + IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14064 && fetchStage$pipelines_0_first[194:192] == 3'd1 ; - assign regRenamingTable_rename_0_canRename__3518_AND__ETC___d14188 = + assign regRenamingTable_rename_0_canRename__3528_AND__ETC___d14198 = regRenamingTable$rename_0_canRename && !checkForException___d13160[4] && rob$enqPort_0_canEnq && (fetchStage$pipelines_0_first[194:192] == 3'd3 || fetchStage$pipelines_0_first[194:192] == 3'd4) && coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq ; - assign regRenamingTable_rename_0_canRename__3518_AND__ETC___d14201 = + assign regRenamingTable_rename_0_canRename__3528_AND__ETC___d14211 = regRenamingTable$rename_0_canRename && !checkForException___d13160[4] && rob$enqPort_0_canEnq && (fetchStage$pipelines_0_first[194:192] == 3'd3 || fetchStage$pipelines_0_first[194:192] == 3'd4) && coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq && - NOT_fetchStage_pipelines_0_first__2928_BITS_32_ETC___d14197 ; - assign regRenamingTable_rename_0_canRename__3518_AND__ETC___d14206 = + NOT_fetchStage_pipelines_0_first__2928_BITS_32_ETC___d14207 ; + assign regRenamingTable_rename_0_canRename__3528_AND__ETC___d14216 = regRenamingTable$rename_0_canRename && !checkForException___d13160[4] && rob$enqPort_0_canEnq && @@ -29217,64 +29227,64 @@ module mkCore(CLK, fetchStage$pipelines_0_first[194:192] == 3'd4) && coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq && fetchStage$pipelines_0_first[173] ; - assign regRenamingTable_rename_0_canRename__3518_AND__ETC___d14211 = + assign regRenamingTable_rename_0_canRename__3528_AND__ETC___d14221 = regRenamingTable$rename_0_canRename && !checkForException___d13160[4] && rob$enqPort_0_canEnq && fetchStage$pipelines_0_first[194:192] == 3'd2 && coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13570 && + IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13580 && fetchStage$pipelines_0_first[199:195] != 5'd14 ; - assign regRenamingTable_rename_0_canRename__3518_AND__ETC___d14231 = + assign regRenamingTable_rename_0_canRename__3528_AND__ETC___d14241 = regRenamingTable$rename_0_canRename && !checkForException___d13160[4] && rob$enqPort_0_canEnq && fetchStage$pipelines_0_first[194:192] == 3'd2 && coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13570 && - NOT_fetchStage_pipelines_0_first__2928_BITS_32_ETC___d14197 ; - assign regRenamingTable_rename_0_canRename__3518_AND__ETC___d14235 = + IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13580 && + NOT_fetchStage_pipelines_0_first__2928_BITS_32_ETC___d14207 ; + assign regRenamingTable_rename_0_canRename__3528_AND__ETC___d14245 = regRenamingTable$rename_0_canRename && !checkForException___d13160[4] && rob$enqPort_0_canEnq && fetchStage$pipelines_0_first[194:192] == 3'd2 && coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13570 && + IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13580 && fetchStage$pipelines_0_first[173] ; - assign regRenamingTable_rename_0_canRename__3518_AND__ETC___d14241 = + assign regRenamingTable_rename_0_canRename__3528_AND__ETC___d14251 = regRenamingTable$rename_0_canRename && !checkForException___d13160[4] && rob$enqPort_0_canEnq && fetchStage$pipelines_0_first[194:192] == 3'd2 && coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13570 && + IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13580 && (fetchStage$pipelines_0_first[199:195] != 5'd14) != fetchStage$pipelines_0_first[160] ; - assign regRenamingTable_rename_0_canRename__3518_AND__ETC___d14245 = + assign regRenamingTable_rename_0_canRename__3528_AND__ETC___d14255 = regRenamingTable$rename_0_canRename && !checkForException___d13160[4] && rob$enqPort_0_canEnq && fetchStage$pipelines_0_first[194:192] == 3'd2 && coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13570 && + IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13580 && (fetchStage$pipelines_0_first[191:189] == 3'd0 || fetchStage$pipelines_0_first[191:189] == 3'd2) ; - assign regRenamingTable_rename_0_canRename__3518_AND__ETC___d14253 = + assign regRenamingTable_rename_0_canRename__3528_AND__ETC___d14263 = regRenamingTable$rename_0_canRename && !checkForException___d13160[4] && rob$enqPort_0_canEnq && fetchStage$pipelines_0_first[194:192] == 3'd2 && coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13570 && + IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13580 && fetchStage$pipelines_0_first[191:189] != 3'd0 && fetchStage$pipelines_0_first[191:189] != 3'd2 ; - assign regRenamingTable_rename_0_canRename__3518_AND__ETC___d14429 = + assign regRenamingTable_rename_0_canRename__3528_AND__ETC___d14439 = regRenamingTable$rename_0_canRename && !checkForException___d13160[4] && rob$enqPort_0_canEnq && fetchStage$pipelines_0_first[194:192] == 3'd2 && - IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13570 ; - assign regRenamingTable_rename_1_canRename__3637_AND__ETC___d14308 = + IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13580 ; + assign regRenamingTable_rename_1_canRename__3647_AND__ETC___d14318 = regRenamingTable$rename_1_canRename && fetchStage$pipelines_1_first[199:195] != 5'd0 && fetchStage$pipelines_1_first[199:195] != 5'd21 && @@ -29285,21 +29295,21 @@ module mkCore(CLK, fetchStage$pipelines_1_first[199:195] != 5'd15 && fetchStage$pipelines_1_first[199:195] != 5'd19 && fetchStage$pipelines_1_first[199:195] != 5'd20 && - NOT_fetchStage_pipelines_1_first__2937_BIT_68__ETC___d14306 ; - assign regRenamingTable_rename_1_canRename__3637_AND__ETC___d14392 = - regRenamingTable_rename_1_canRename__3637_AND__ETC___d14308 && + NOT_fetchStage_pipelines_1_first__2937_BIT_68__ETC___d14316 ; + assign regRenamingTable_rename_1_canRename__3647_AND__ETC___d14402 = + regRenamingTable_rename_1_canRename__3647_AND__ETC___d14318 && fetchStage$pipelines_1_first[194:192] == 3'd2 && - NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14376 && - NOT_fetchStage_pipelines_1_first__2937_BITS_32_ETC___d14363 ; - assign regRenamingTable_rename_1_canRename__3637_AND__ETC___d14402 = - regRenamingTable_rename_1_canRename__3637_AND__ETC___d14308 && + NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14386 && + NOT_fetchStage_pipelines_1_first__2937_BITS_32_ETC___d14373 ; + assign regRenamingTable_rename_1_canRename__3647_AND__ETC___d14412 = + regRenamingTable_rename_1_canRename__3647_AND__ETC___d14318 && fetchStage$pipelines_1_first[194:192] == 3'd2 && - NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14376 && + NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14386 && (fetchStage$pipelines_1_first[199:195] != 5'd14) != fetchStage$pipelines_1_first[160] ; - assign renaming_spec_bits__h690391 = + assign renaming_spec_bits__h690494 = fetchStage$pipelines_0_canDeq ? - y_avValue_snd_fst__h687089 : + y_avValue_snd_fst__h687192 : specTagManager$currentSpecBits ; assign res_data__h342522 = { 32'hFFFFFFFF, x__h342537 } ; assign res_data__h342527 = @@ -29578,35 +29588,35 @@ module mkCore(CLK, assign result__h653790 = ~x__h653789 ; assign rg_tdata1__read__h619066 = { r1__read__h620942, csrf_rg_tdata1_data } ; - assign rob_RDY_enqPort_1_enq__4147_AND_NOT_fetchStage_ETC___d14155 = + assign rob_RDY_enqPort_1_enq__4157_AND_NOT_fetchStage_ETC___d14165 = rob$RDY_enqPort_1_enq && (!fetchStage$pipelines_0_canDeq || - NOT_specTagManager_canClaim__3516_3601_OR_NOT__ETC___d14151) && + NOT_specTagManager_canClaim__3526_3611_OR_NOT__ETC___d14161) && (fetchStage$pipelines_1_first[194:192] != 3'd1 || specTagManager$RDY_claimSpecTag) ; - assign rob_deqPort_0_deq_data__4456_BITS_353_TO_290_4_ETC___d14959 = + assign rob_deqPort_0_deq_data__4466_BITS_353_TO_290_4_ETC___d14969 = rob$deqPort_0_deq_data[353:290] + 64'd4 ; - assign rob_enqPort_1_canEnq__3826_AND_epochManager_ch_ETC___d13831 = + assign rob_enqPort_1_canEnq__3836_AND_epochManager_ch_ETC___d13841 = rob$enqPort_1_canEnq && epochManager$checkEpoch_1_check && (!fetchStage$pipelines_0_canDeq || (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3518_AND__ETC___d13588 && - IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13574) ; - assign rob_enqPort_1_canEnq__3826_AND_epochManager_ch_ETC___d13965 = + regRenamingTable_rename_0_canRename__3528_AND__ETC___d13598 && + IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13584) ; + assign rob_enqPort_1_canEnq__3836_AND_epochManager_ch_ETC___d13975 = rob$enqPort_1_canEnq && epochManager$checkEpoch_1_check && (!fetchStage$pipelines_0_canDeq || (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3518_AND__ETC___d13588 && - IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13961) ; - assign rob_enqPort_1_canEnq__3826_AND_epochManager_ch_ETC___d13982 = + regRenamingTable_rename_0_canRename__3528_AND__ETC___d13598 && + IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13971) ; + assign rob_enqPort_1_canEnq__3836_AND_epochManager_ch_ETC___d13992 = rob$enqPort_1_canEnq && epochManager$checkEpoch_1_check && (!fetchStage$pipelines_0_canDeq || (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3518_AND__ETC___d13588 && - IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13978) ; + regRenamingTable_rename_0_canRename__3528_AND__ETC___d13598 && + IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13988) ; assign robdeqPort_0_deq_data_BITS_95_TO_32__q262 = rob$deqPort_0_deq_data[95:32] ; assign rs1__h661842 = @@ -29776,7 +29786,7 @@ module mkCore(CLK, coreFix_memExe_regToExeQ$first[75:12] << x__h184873 ; assign sie_csr__read__h616502 = { r1__read__h619795, 1'b0 } ; assign sip_csr__read__h616876 = { r1__read__h620329, 1'b0 } ; - assign spec_bits__h693518 = specTagManager$currentSpecBits | y__h693531 ; + assign spec_bits__h693621 = specTagManager$currentSpecBits | y__h693634 ; assign sstatus_csr__read__h616432 = { r1__read__h619391, csrf_ie_vec_0 } ; assign stvec_csr__read__h616545 = { r1__read__h620305, csrf_stvec_mode_low_reg } ; @@ -30026,18 +30036,18 @@ module mkCore(CLK, sbCons$lazyLookup_0_get[2] ? rf$read_0_rd2 : y_avValue__h644296 ; assign x__h653738 = 12'd1 << coreFix_aluExe_1_exeToFinQ$first[15:12] ; assign x__h653789 = 12'd1 << coreFix_aluExe_0_exeToFinQ$first[15:12] ; - assign x__h704922 = + assign x__h705025 = (!rob$deqPort_0_deq_data[166] && (rob$deqPort_0_deq_data[165:162] == 4'd1 || rob$deqPort_0_deq_data[165:162] == 4'd12)) ? rob$deqPort_0_deq_data[161:98] : rob$deqPort_0_deq_data[95:32] ; - assign x__h711531 = { cause_code__h708593, 2'b0 } ; - assign x__h719602 = { 1'b0, csrf_spp_reg } ; - assign x__h723542 = - NOT_rob_deqPort_0_canDeq__4986_4987_OR_rob_deq_ETC___d15178 ? - y_avValue_snd_snd_snd_fst__h723364 : - IF_rob_deqPort_0_canDeq__4986_THEN_IF_NOT_rob__ETC___d15207 ; + assign x__h711634 = { cause_code__h708696, 2'b0 } ; + assign x__h719705 = { 1'b0, csrf_spp_reg } ; + assign x__h723645 = + NOT_rob_deqPort_0_canDeq__4996_4997_OR_rob_deq_ETC___d15188 ? + y_avValue_snd_snd_snd_fst__h723467 : + IF_rob_deqPort_0_canDeq__4996_THEN_IF_NOT_rob__ETC___d15217 ; assign x__h75785 = mmio_pRqQ_data_0[31:0] ; assign x_addr__h318727 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? @@ -30047,8 +30057,8 @@ module mkCore(CLK, EN_mmioToPlatform_pRq_enq ? mmio_pRqQ_enqReq_lat_0$wget[31:0] : mmio_pRqQ_enqReq_rl[31:0] ; - assign x_data_imm__h682272 = fetchStage$pipelines_0_first[159:128] ; - assign x_data_imm__h698176 = fetchStage$pipelines_1_first[159:128] ; + assign x_data_imm__h682375 = fetchStage$pipelines_0_first[159:128] ; + assign x_data_imm__h698279 = fetchStage$pipelines_1_first[159:128] ; assign x_decodeInfo_frm__h661526 = csrf_frm_reg ; assign x_quotient__h479960 = coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[75] ? @@ -30079,11 +30089,11 @@ module mkCore(CLK, ~csrf_mideleg_5_3_reg, 1'd1, ~csrf_mideleg_1_0_reg } ; - assign y__h693531 = 12'd1 << specTagManager$nextSpecTag ; - assign y__h723317 = - NOT_rob_deqPort_0_canDeq__4986_4987_OR_rob_deq_ETC___d15178 ? - y_avValue_snd_snd_snd_snd_snd__h723370 : - IF_rob_deqPort_0_canDeq__4986_THEN_IF_NOT_rob__ETC___d15095 ; + assign y__h693634 = 12'd1 << specTagManager$nextSpecTag ; + assign y__h723420 = + NOT_rob_deqPort_0_canDeq__4996_4997_OR_rob_deq_ETC___d15188 ? + y_avValue_snd_snd_snd_snd_snd__h723473 : + IF_rob_deqPort_0_canDeq__4996_THEN_IF_NOT_rob__ETC___d15105 ; assign y_avValue__h183779 = NOT_coreFix_memExe_bypassWire_0_whas__584_590__ETC___d1611 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : @@ -30120,11 +30130,11 @@ module mkCore(CLK, NOT_coreFix_aluExe_0_bypassWire_0_whas__2366_2_ETC___d12423 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12626 ; - assign y_avValue_fst__h686815 = + assign y_avValue_fst__h686918 = (fetchStage$pipelines_0_first[194:192] == 3'd1) ? - spec_bits__h693518 : + spec_bits__h693621 : specTagManager$currentSpecBits ; - assign y_avValue_fst__h722271 = + assign y_avValue_fst__h722374 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[167] || rob$deqPort_0_deq_data[257:253] == 5'd0 || @@ -30138,10 +30148,10 @@ module mkCore(CLK, rob$deqPort_0_deq_data[257:253] == 5'd20) ? 5'd0 : rob$deqPort_0_deq_data[31:27] ; - assign y_avValue_fst__h723213 = - IF_rob_deqPort_0_canDeq__4986_THEN_IF_NOT_rob__ETC___d15185 | + assign y_avValue_fst__h723316 = + IF_rob_deqPort_0_canDeq__4996_THEN_IF_NOT_rob__ETC___d15195 | rob$deqPort_1_deq_data[31:27] ; - assign y_avValue_fst__h723241 = + assign y_avValue_fst__h723344 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[257:253] == 5'd0 || @@ -30153,28 +30163,28 @@ module mkCore(CLK, rob$deqPort_1_deq_data[257:253] == 5'd15 || rob$deqPort_1_deq_data[257:253] == 5'd19 || rob$deqPort_1_deq_data[257:253] == 5'd20) ? - IF_rob_deqPort_0_canDeq__4986_THEN_IF_NOT_rob__ETC___d15185 : - y_avValue_fst__h723213 ; - assign y_avValue_new_pc__h711297 = + IF_rob_deqPort_0_canDeq__4996_THEN_IF_NOT_rob__ETC___d15195 : + y_avValue_fst__h723316 ; + assign y_avValue_new_pc__h711400 = (csrf_stvec_mode_low_reg && commitStage_commitTrap[36]) ? - base__h711516 + { 58'd0, x__h711531 } : - base__h711516 ; - assign y_avValue_new_pc__h711483 = + base__h711619 + { 58'd0, x__h711634 } : + base__h711619 ; + assign y_avValue_new_pc__h711586 = (csrf_mtvec_mode_low_reg && commitStage_commitTrap[36]) ? - base__h711536 + { 58'd0, x__h711531 } : - base__h711536 ; - assign y_avValue_snd_fst__h687089 = + base__h711639 + { 58'd0, x__h711634 } : + base__h711639 ; + assign y_avValue_snd_fst__h687192 = ((fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && regRenamingTable$rename_0_canRename && - NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13538) ? - y_avValue_snd_fst__h687124 : + NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13548) ? + y_avValue_snd_fst__h687227 : specTagManager$currentSpecBits ; - assign y_avValue_snd_fst__h687124 = - IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13598 ? - y_avValue_fst__h686815 : + assign y_avValue_snd_fst__h687227 = + IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13608 ? + y_avValue_fst__h686918 : specTagManager$currentSpecBits ; - assign y_avValue_snd_snd_snd_fst__h722705 = + assign y_avValue_snd_snd_snd_fst__h722808 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[167] || rob$deqPort_0_deq_data[257:253] == 5'd0 || @@ -30188,7 +30198,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[257:253] == 5'd20) ? 2'd0 : 2'd1 ; - assign y_avValue_snd_snd_snd_fst__h723364 = + assign y_avValue_snd_snd_snd_fst__h723467 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[257:253] == 5'd0 || @@ -30200,12 +30210,12 @@ module mkCore(CLK, rob$deqPort_1_deq_data[257:253] == 5'd15 || rob$deqPort_1_deq_data[257:253] == 5'd19 || rob$deqPort_1_deq_data[257:253] == 5'd20) ? - IF_rob_deqPort_0_canDeq__4986_THEN_IF_NOT_rob__ETC___d15207 : - y_avValue_snd_snd_snd_fst__h723393 ; - assign y_avValue_snd_snd_snd_fst__h723393 = - IF_rob_deqPort_0_canDeq__4986_THEN_IF_NOT_rob__ETC___d15207 + + IF_rob_deqPort_0_canDeq__4996_THEN_IF_NOT_rob__ETC___d15217 : + y_avValue_snd_snd_snd_fst__h723496 ; + assign y_avValue_snd_snd_snd_fst__h723496 = + IF_rob_deqPort_0_canDeq__4996_THEN_IF_NOT_rob__ETC___d15217 + 2'd1 ; - assign y_avValue_snd_snd_snd_snd_snd__h722711 = + assign y_avValue_snd_snd_snd_snd_snd__h722814 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[167] || rob$deqPort_0_deq_data[257:253] == 5'd0 || @@ -30219,7 +30229,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[257:253] == 5'd20) ? 64'd0 : 64'd1 ; - assign y_avValue_snd_snd_snd_snd_snd__h723370 = + assign y_avValue_snd_snd_snd_snd_snd__h723473 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[257:253] == 5'd0 || @@ -30231,10 +30241,10 @@ module mkCore(CLK, rob$deqPort_1_deq_data[257:253] == 5'd15 || rob$deqPort_1_deq_data[257:253] == 5'd19 || rob$deqPort_1_deq_data[257:253] == 5'd20) ? - IF_rob_deqPort_0_canDeq__4986_THEN_IF_NOT_rob__ETC___d15095 : - y_avValue_snd_snd_snd_snd_snd__h723399 ; - assign y_avValue_snd_snd_snd_snd_snd__h723399 = - IF_rob_deqPort_0_canDeq__4986_THEN_IF_NOT_rob__ETC___d15095 + + IF_rob_deqPort_0_canDeq__4996_THEN_IF_NOT_rob__ETC___d15105 : + y_avValue_snd_snd_snd_snd_snd__h723502 ; + assign y_avValue_snd_snd_snd_snd_snd__h723502 = + IF_rob_deqPort_0_canDeq__4996_THEN_IF_NOT_rob__ETC___d15105 + 64'd1 ; always@(mmio_cRqQ_data_0) begin @@ -30360,9 +30370,9 @@ module mkCore(CLK, always@(commitStage_commitTrap) begin case (commitStage_commitTrap[35:32]) - 4'd0, 4'd3: trap_val__h709616 = commitStage_commitTrap[164:101]; - 4'd2: trap_val__h709616 = { 32'd0, commitStage_commitTrap[31:0] }; - default: trap_val__h709616 = + 4'd0, 4'd3: trap_val__h709719 = commitStage_commitTrap[164:101]; + 4'd2: trap_val__h709719 = { 32'd0, commitStage_commitTrap[31:0] }; + default: trap_val__h709719 = (commitStage_commitTrap[35:32] != 4'd8 && commitStage_commitTrap[35:32] != 4'd9 && commitStage_commitTrap[35:32] != 4'd11) ? @@ -30785,16 +30795,16 @@ module mkCore(CLK, 4'd11, 4'd12, 4'd13: - i__h708608 = commitStage_commitTrap[35:32]; - default: i__h708608 = 4'd15; + i__h708711 = commitStage_commitTrap[35:32]; + default: i__h708711 = 4'd15; endcase end always@(commitStage_commitTrap) begin case (commitStage_commitTrap[35:32]) 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9: - i__h708768 = commitStage_commitTrap[35:32]; - default: i__h708768 = 4'd11; + i__h708871 = commitStage_commitTrap[35:32]; + default: i__h708871 = 4'd11; endcase end always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) @@ -35145,15 +35155,15 @@ module mkCore(CLK, 4'd11; endcase end - always@(k__h674927 or + always@(k__h675030 or coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq) begin - case (k__h674927) + case (k__h675030) 1'd0: - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3548_co_ETC___d13558 = + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3558_co_ETC___d13568 = coreFix_aluExe_0_rsAlu$canEnq; 1'd1: - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3548_co_ETC___d13558 = + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3558_co_ETC___d13568 = coreFix_aluExe_1_rsAlu$canEnq; endcase end @@ -35162,69 +35172,69 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13570 = + IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13580 = coreFix_memExe_lsq$enqLdTag[6]; - default: IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13570 = + default: IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13580 = coreFix_memExe_lsq$enqStTag[6]; endcase end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13570 or - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3548_co_ETC___d13558 or + IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13580 or + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3558_co_ETC___d13568 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13574 = - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3548_co_ETC___d13558; + IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13584 = + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3558_co_ETC___d13568; 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13574 = + IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13584 = coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq; - default: IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13574 = + default: IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13584 = fetchStage$pipelines_0_first[194:192] != 3'd2 || coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13570; + IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13580; endcase end - always@(k__h674927 or + always@(k__h675030 or coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq) begin - case (k__h674927) + case (k__h675030) 1'd0: - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__354_ETC___d13591 = + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__355_ETC___d13601 = !coreFix_aluExe_0_rsAlu$canEnq; 1'd1: - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__354_ETC___d13591 = + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__355_ETC___d13601 = !coreFix_aluExe_1_rsAlu$canEnq; endcase end always@(fetchStage$pipelines_0_first or regRenamingTable$rename_0_canRename or - NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13538 or - NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13593 or + NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13548 or + NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13603 or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13570 or + IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13580 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13598 = - NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13593; + IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13608 = + NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13603; 3'd2: - IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13598 = + IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13608 = coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13570 && + IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13580 && regRenamingTable$rename_0_canRename && - NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13538; + NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13548; 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13598 = + IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13608 = coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq && regRenamingTable$rename_0_canRename && - NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13538; - default: IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13598 = + NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13548; + default: IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13608 = regRenamingTable$rename_0_canRename && - NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13538; + NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13548; endcase end always@(fetchStage$pipelines_0_first or @@ -35232,59 +35242,32 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13626 = + IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13636 = !coreFix_memExe_lsq$enqLdTag[6]; - default: IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13626 = + default: IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13636 = !coreFix_memExe_lsq$enqStTag[6]; endcase end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13626 or - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__354_ETC___d13591 or + IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13636 or + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__355_ETC___d13601 or specTagManager$canClaim or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13631 = - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__354_ETC___d13591 || + IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13641 = + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__355_ETC___d13601 || fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim; 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13631 = + IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13641 = !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq; - default: IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13631 = + default: IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13641 = fetchStage$pipelines_0_first[194:192] == 3'd2 && (!coreFix_memExe_rsMem$canEnq || - IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13626); - endcase - end - always@(fetchStage$pipelines_1_first) - begin - case (fetchStage$pipelines_1_first[177:175]) - 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q228 = - fetchStage$pipelines_1_first[177:175]; - default: CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q228 = 3'd7; - endcase - end - always@(fetchStage$pipelines_1_first or - CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q228) - begin - case (fetchStage$pipelines_1_first[194:192]) - 3'd0, 3'd1, 3'd2, 3'd3: - IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13691 = - fetchStage$pipelines_1_first[194:174]; - 3'd4: - IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13691 = - { fetchStage$pipelines_1_first[194:192], - 9'h0AA, - fetchStage$pipelines_1_first[182:178], - CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q228, - fetchStage$pipelines_1_first[174] }; - default: IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13691 = - 21'd1485482; + IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13636); endcase end always@(fetchStage$pipelines_1_first) @@ -35330,29 +35313,56 @@ module mkCore(CLK, 12'd3858, 12'd3859, 12'd3860: - CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q229 = + CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q228 = fetchStage$pipelines_1_first[172:161]; - default: CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q229 = + default: CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q228 = 12'd2303; endcase end - always@(idx__h690522 or + always@(fetchStage$pipelines_1_first) + begin + case (fetchStage$pipelines_1_first[177:175]) + 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: + CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q229 = + fetchStage$pipelines_1_first[177:175]; + default: CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q229 = 3'd7; + endcase + end + always@(fetchStage$pipelines_1_first or + CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q229) + begin + case (fetchStage$pipelines_1_first[194:192]) + 3'd0, 3'd1, 3'd2, 3'd3: + IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13701 = + fetchStage$pipelines_1_first[194:174]; + 3'd4: + IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13701 = + { fetchStage$pipelines_1_first[194:192], + 9'h0AA, + fetchStage$pipelines_1_first[182:178], + CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q229, + fetchStage$pipelines_1_first[174] }; + default: IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13701 = + 21'd1485482; + endcase + end + always@(idx__h690625 or fetchStage$pipelines_0_canDeq or - NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13842 or + NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13852 or coreFix_aluExe_0_rsAlu$canEnq or - NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13848 or + NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13858 or coreFix_aluExe_1_rsAlu$canEnq) begin - case (idx__h690522) + case (idx__h690625) 1'd0: - SEL_ARR_fetchStage_pipelines_0_canDeq__2926_AN_ETC___d13867 = + SEL_ARR_fetchStage_pipelines_0_canDeq__2926_AN_ETC___d13877 = fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13842 || + NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13852 || !coreFix_aluExe_0_rsAlu$canEnq; 1'd1: - SEL_ARR_fetchStage_pipelines_0_canDeq__2926_AN_ETC___d13867 = + SEL_ARR_fetchStage_pipelines_0_canDeq__2926_AN_ETC___d13877 = fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13848 || + NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13858 || !coreFix_aluExe_1_rsAlu$canEnq; endcase end @@ -35369,23 +35379,23 @@ module mkCore(CLK, end always@(fetchStage$pipelines_0_first or IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992 or - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__354_ETC___d13591 or - fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d13934 or - NOT_coreFix_memExe_rsMem_canEnq__3561_3623_OR__ETC___d13937 or - NOT_coreFix_fpuMulDivExe_0_rsFpuMulDiv_canEnq__ETC___d13936) + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__355_ETC___d13601 or + fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d13944 or + NOT_coreFix_memExe_rsMem_canEnq__3571_3633_OR__ETC___d13947 or + NOT_coreFix_fpuMulDivExe_0_rsFpuMulDiv_canEnq__ETC___d13946) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13940 = - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__354_ETC___d13591 || - fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d13934; + IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13950 = + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__355_ETC___d13601 || + fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d13944; 3'd2: - IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13940 = - NOT_coreFix_memExe_rsMem_canEnq__3561_3623_OR__ETC___d13937; + IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13950 = + NOT_coreFix_memExe_rsMem_canEnq__3571_3633_OR__ETC___d13947; 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13940 = - NOT_coreFix_fpuMulDivExe_0_rsFpuMulDiv_canEnq__ETC___d13936; - default: IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13940 = + IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13950 = + NOT_coreFix_fpuMulDivExe_0_rsFpuMulDiv_canEnq__ETC___d13946; + default: IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13950 = fetchStage$pipelines_0_first[68] || IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[0] || IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[1] || @@ -35403,34 +35413,34 @@ module mkCore(CLK, end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13570 or - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3548_co_ETC___d13558) + IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13580 or + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3558_co_ETC___d13568) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13961 = - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3548_co_ETC___d13558; - default: IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13961 = + IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13971 = + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3558_co_ETC___d13568; + default: IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13971 = fetchStage$pipelines_0_first[194:192] != 3'd2 || coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13570; + IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13580; endcase end always@(fetchStage$pipelines_0_first or - IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13570 or - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3548_co_ETC___d13558 or + IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13580 or + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3558_co_ETC___d13568 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13978 = - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3548_co_ETC___d13558; + IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13988 = + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3558_co_ETC___d13568; 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13978 = + IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13988 = coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq; - default: IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13978 = + default: IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13988 = fetchStage$pipelines_0_first[194:192] != 3'd2 || - IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13570; + IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13580; endcase end always@(fetchStage$pipelines_1_first or @@ -35446,45 +35456,45 @@ module mkCore(CLK, end always@(fetchStage$pipelines_1_first or regRenamingTable$rename_1_canRename or - NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d13833 or - SEL_ARR_fetchStage_pipelines_0_canDeq__2926_AN_ETC___d13867 or - NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d13946 or - NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d13975 or - NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d13984 or - NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d13958 or + NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d13843 or + SEL_ARR_fetchStage_pipelines_0_canDeq__2926_AN_ETC___d13877 or + NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d13956 or + NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d13985 or + NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d13994 or + NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d13968 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq or - NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d13967) + NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d13977) begin case (fetchStage$pipelines_1_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13989 = - !SEL_ARR_fetchStage_pipelines_0_canDeq__2926_AN_ETC___d13867 && - NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d13946; + IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13999 = + !SEL_ARR_fetchStage_pipelines_0_canDeq__2926_AN_ETC___d13877 && + NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d13956; 3'd2: - IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13989 = - NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d13975 && + IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13999 = + NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d13985 && regRenamingTable$rename_1_canRename && - NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d13984; + NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d13994; 3'd3, 3'd4: - IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13989 = - NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d13958 && + IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13999 = + NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d13968 && coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq && regRenamingTable$rename_1_canRename && - NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d13967; - default: IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13989 = + NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d13977; + default: IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13999 = regRenamingTable$rename_1_canRename && - NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d13833; + NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d13843; endcase end - always@(k__h674927 or + always@(k__h675030 or coreFix_aluExe_0_rsAlu$RDY_enq or coreFix_aluExe_1_rsAlu$RDY_enq) begin - case (k__h674927) + case (k__h675030) 1'd0: - CASE_k74927_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232 = + CASE_k75030_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232 = coreFix_aluExe_0_rsAlu$RDY_enq; 1'd1: - CASE_k74927_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232 = + CASE_k75030_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232 = coreFix_aluExe_1_rsAlu$RDY_enq; endcase end @@ -35501,116 +35511,116 @@ module mkCore(CLK, end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13626 or - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__354_ETC___d13591 or + IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13636 or + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__355_ETC___d13601 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14033 = - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__354_ETC___d13591; + IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14043 = + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__355_ETC___d13601; 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14033 = + IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14043 = !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq; - default: IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14033 = + default: IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14043 = fetchStage$pipelines_0_first[194:192] == 3'd2 && (!coreFix_memExe_rsMem$canEnq || - IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13626); + IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13636); endcase end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13626 or - regRenamingTable_RDY_rename_0_getRename__3398__ETC___d14027 or - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3548_co_ETC___d13558 or + IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13636 or + regRenamingTable_RDY_rename_0_getRename__3398__ETC___d14037 or + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3558_co_ETC___d13568 or regRenamingTable$RDY_rename_0_getRename or - _0_OR_NOT_fetchStage_pipelines_0_first__2928_BI_ETC___d14014 or + _0_OR_NOT_fetchStage_pipelines_0_first__2928_BI_ETC___d14024 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq or coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_enq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14031 = - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3548_co_ETC___d13558 || + IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14041 = + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3558_co_ETC___d13568 || regRenamingTable$RDY_rename_0_getRename && - _0_OR_NOT_fetchStage_pipelines_0_first__2928_BI_ETC___d14014; + _0_OR_NOT_fetchStage_pipelines_0_first__2928_BI_ETC___d14024; 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14031 = + IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14041 = !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq || coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_enq && regRenamingTable$RDY_rename_0_getRename; - default: IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14031 = + default: IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14041 = fetchStage$pipelines_0_first[194:192] != 3'd2 || !coreFix_memExe_rsMem$canEnq || - IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13626 || - regRenamingTable_RDY_rename_0_getRename__3398__ETC___d14027; + IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13636 || + regRenamingTable_RDY_rename_0_getRename__3398__ETC___d14037; endcase end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13626 or - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3548_co_ETC___d13558 or + IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13636 or + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3558_co_ETC___d13568 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14047 = - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3548_co_ETC___d13558; + IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14057 = + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3558_co_ETC___d13568; 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14047 = + IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14057 = !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq; - default: IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14047 = + default: IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14057 = fetchStage$pipelines_0_first[194:192] == 3'd2 && (!coreFix_memExe_rsMem$canEnq || - IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13626); + IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13636); endcase end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13570 or - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__354_ETC___d13591 or + IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13580 or + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__355_ETC___d13601 or specTagManager$canClaim or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14054 = - !SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__354_ETC___d13591 && + IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14064 = + !SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__355_ETC___d13601 && (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim); 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14054 = + IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14064 = coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq; - default: IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14054 = + default: IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14064 = fetchStage$pipelines_0_first[194:192] != 3'd2 || coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13570; + IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13580; endcase end - always@(idx__h690522 or + always@(idx__h690625 or fetchStage$pipelines_0_canDeq or - fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d14070 or + fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d14080 or coreFix_aluExe_0_rsAlu$canEnq or - fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d14077 or + fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d14087 or coreFix_aluExe_1_rsAlu$canEnq) begin - case (idx__h690522) + case (idx__h690625) 1'd0: - SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__292_ETC___d14081 = + SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__292_ETC___d14091 = (!fetchStage$pipelines_0_canDeq || - fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d14070) && + fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d14080) && coreFix_aluExe_0_rsAlu$canEnq; 1'd1: - SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__292_ETC___d14081 = + SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__292_ETC___d14091 = (!fetchStage$pipelines_0_canDeq || - fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d14077) && + fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d14087) && coreFix_aluExe_1_rsAlu$canEnq; endcase end - always@(fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14097 or + always@(fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14107 or coreFix_aluExe_0_rsAlu$RDY_enq or coreFix_aluExe_1_rsAlu$RDY_enq) begin - case (fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14097) + case (fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14107) 1'd0: CASE_fetchStage_pipelines_0_canDeq__2926_AND_N_ETC__q234 = coreFix_aluExe_0_rsAlu$RDY_enq; @@ -35631,79 +35641,79 @@ module mkCore(CLK, endcase end always@(fetchStage$pipelines_0_first or - coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13626 or - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3548_co_ETC___d13558) - begin - case (fetchStage$pipelines_0_first[194:192]) - 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14123 = - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3548_co_ETC___d13558; - default: IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14123 = - fetchStage$pipelines_0_first[194:192] == 3'd2 && - (!coreFix_memExe_rsMem$canEnq || - IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13626); - endcase - end - always@(fetchStage$pipelines_0_first or - IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13626 or - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3548_co_ETC___d13558 or + IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13636 or + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3558_co_ETC___d13568 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14134 = - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3548_co_ETC___d13558; + IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14144 = + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3558_co_ETC___d13568; 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14134 = + IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14144 = !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq; - default: IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14134 = + default: IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14144 = fetchStage$pipelines_0_first[194:192] == 3'd2 && - IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13626; + IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13636; + endcase + end + always@(fetchStage$pipelines_0_first or + coreFix_memExe_rsMem$canEnq or + IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13636 or + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3558_co_ETC___d13568) + begin + case (fetchStage$pipelines_0_first[194:192]) + 3'd0, 3'd1: + IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14133 = + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3558_co_ETC___d13568; + default: IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14133 = + fetchStage$pipelines_0_first[194:192] == 3'd2 && + (!coreFix_memExe_rsMem$canEnq || + IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13636); endcase end always@(fetchStage$pipelines_1_first or - fetchStage_pipelines_0_canDeq__2926_AND_regRen_ETC___d14142 or - SEL_ARR_fetchStage_pipelines_0_canDeq__2926_AN_ETC___d13867 or - fetchStage_pipelines_0_canDeq__2926_AND_regRen_ETC___d14131) + fetchStage_pipelines_0_canDeq__2926_AND_regRen_ETC___d14152 or + SEL_ARR_fetchStage_pipelines_0_canDeq__2926_AN_ETC___d13877 or + fetchStage_pipelines_0_canDeq__2926_AND_regRen_ETC___d14141) begin case (fetchStage$pipelines_1_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d14145 = - SEL_ARR_fetchStage_pipelines_0_canDeq__2926_AN_ETC___d13867; + IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d14155 = + SEL_ARR_fetchStage_pipelines_0_canDeq__2926_AN_ETC___d13877; 3'd3, 3'd4: - IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d14145 = - fetchStage_pipelines_0_canDeq__2926_AND_regRen_ETC___d14131; - default: IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d14145 = + IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d14155 = + fetchStage_pipelines_0_canDeq__2926_AND_regRen_ETC___d14141; + default: IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d14155 = fetchStage$pipelines_1_first[194:192] == 3'd2 && - fetchStage_pipelines_0_canDeq__2926_AND_regRen_ETC___d14142; + fetchStage_pipelines_0_canDeq__2926_AND_regRen_ETC___d14152; endcase end always@(fetchStage$pipelines_1_first or - fetchStage_pipelines_0_canDeq__2926_AND_regRen_ETC___d14110 or + fetchStage_pipelines_0_canDeq__2926_AND_regRen_ETC___d14120 or regRenamingTable$RDY_rename_1_getRename or - NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14115 or - SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__292_ETC___d14081 or - regRenamingTable_RDY_rename_1_getRename__4083__ETC___d14101 or - fetchStage_pipelines_0_canDeq__2926_AND_regRen_ETC___d14103 or + NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14125 or + SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__292_ETC___d14091 or + regRenamingTable_RDY_rename_1_getRename__4093__ETC___d14111 or + fetchStage_pipelines_0_canDeq__2926_AND_regRen_ETC___d14113 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq or - coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__40_ETC___d14106) + coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__40_ETC___d14116) begin case (fetchStage$pipelines_1_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d14120 = - !SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__292_ETC___d14081 || - regRenamingTable_RDY_rename_1_getRename__4083__ETC___d14101; + IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d14130 = + !SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__292_ETC___d14091 || + regRenamingTable_RDY_rename_1_getRename__4093__ETC___d14111; 3'd3, 3'd4: - IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d14120 = - fetchStage_pipelines_0_canDeq__2926_AND_regRen_ETC___d14103 || + IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d14130 = + fetchStage_pipelines_0_canDeq__2926_AND_regRen_ETC___d14113 || !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq || - coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__40_ETC___d14106; - default: IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d14120 = + coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__40_ETC___d14116; + default: IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d14130 = fetchStage$pipelines_1_first[194:192] != 3'd2 || - fetchStage_pipelines_0_canDeq__2926_AND_regRen_ETC___d14110 || + fetchStage_pipelines_0_canDeq__2926_AND_regRen_ETC___d14120 || regRenamingTable$RDY_rename_1_getRename && - NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14115; + NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14125; endcase end always@(fetchStage$pipelines_0_first or @@ -35711,9 +35721,9 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14218 = + IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14228 = !coreFix_memExe_lsq$enqLdTag[5]; - default: IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14218 = + default: IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14228 = !coreFix_memExe_lsq$enqStTag[5]; endcase end @@ -35722,9 +35732,20 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14215 = + IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14234 = + coreFix_memExe_lsq$enqLdTag[3:0]; + default: IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14234 = + coreFix_memExe_lsq$enqStTag[3:0]; + endcase + end + always@(fetchStage$pipelines_0_first or + coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag) + begin + case (fetchStage$pipelines_0_first[191:189]) + 3'd0, 3'd2: + IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14225 = coreFix_memExe_lsq$enqLdTag[5]; - default: IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14215 = + default: IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14225 = coreFix_memExe_lsq$enqStTag[5]; endcase end @@ -35733,20 +35754,20 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14221 = + IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14231 = coreFix_memExe_lsq$enqLdTag[4:0]; - default: IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14221 = + default: IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14231 = coreFix_memExe_lsq$enqStTag[4:0]; endcase end - always@(fetchStage$pipelines_0_first or + always@(fetchStage$pipelines_1_first or coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag) begin - case (fetchStage$pipelines_0_first[191:189]) + case (fetchStage$pipelines_1_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14224 = + IF_fetchStage_pipelines_1_first__2937_BITS_191_ETC___d14395 = coreFix_memExe_lsq$enqLdTag[3:0]; - default: IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14224 = + default: IF_fetchStage_pipelines_1_first__2937_BITS_191_ETC___d14395 = coreFix_memExe_lsq$enqStTag[3:0]; endcase end @@ -35755,20 +35776,9 @@ module mkCore(CLK, begin case (fetchStage$pipelines_1_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_1_first__2937_BITS_191_ETC___d14385 = - coreFix_memExe_lsq$enqLdTag[3:0]; - default: IF_fetchStage_pipelines_1_first__2937_BITS_191_ETC___d14385 = - coreFix_memExe_lsq$enqStTag[3:0]; - endcase - end - always@(fetchStage$pipelines_1_first or - coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag) - begin - case (fetchStage$pipelines_1_first[191:189]) - 3'd0, 3'd2: - IF_fetchStage_pipelines_1_first__2937_BITS_191_ETC___d14383 = + IF_fetchStage_pipelines_1_first__2937_BITS_191_ETC___d14393 = !coreFix_memExe_lsq$enqLdTag[5]; - default: IF_fetchStage_pipelines_1_first__2937_BITS_191_ETC___d14383 = + default: IF_fetchStage_pipelines_1_first__2937_BITS_191_ETC___d14393 = !coreFix_memExe_lsq$enqStTag[5]; endcase end @@ -35777,9 +35787,9 @@ module mkCore(CLK, begin case (fetchStage$pipelines_1_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_1_first__2937_BITS_191_ETC___d14382 = + IF_fetchStage_pipelines_1_first__2937_BITS_191_ETC___d14392 = coreFix_memExe_lsq$enqLdTag[5]; - default: IF_fetchStage_pipelines_1_first__2937_BITS_191_ETC___d14382 = + default: IF_fetchStage_pipelines_1_first__2937_BITS_191_ETC___d14392 = coreFix_memExe_lsq$enqStTag[5]; endcase end @@ -35788,9 +35798,9 @@ module mkCore(CLK, begin case (fetchStage$pipelines_1_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_1_first__2937_BITS_191_ETC___d14384 = + IF_fetchStage_pipelines_1_first__2937_BITS_191_ETC___d14394 = coreFix_memExe_lsq$enqLdTag[4:0]; - default: IF_fetchStage_pipelines_1_first__2937_BITS_191_ETC___d14384 = + default: IF_fetchStage_pipelines_1_first__2937_BITS_191_ETC___d14394 = coreFix_memExe_lsq$enqStTag[4:0]; endcase end @@ -35798,86 +35808,86 @@ module mkCore(CLK, begin case (rob$deqPort_0_deq_data[180:169]) 12'd1: - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 = 6'd0; + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd0; 12'd2: - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 = 6'd1; + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd1; 12'd3: - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 = 6'd2; + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd2; 12'd256: - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 = 6'd8; + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd8; 12'd260: - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 = 6'd9; + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd9; 12'd261: - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 = 6'd10; + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd10; 12'd262: - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 = 6'd11; + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd11; 12'd320: - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 = 6'd12; + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd12; 12'd321: - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 = 6'd13; + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd13; 12'd322: - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 = 6'd14; + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd14; 12'd323: - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 = 6'd15; + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd15; 12'd324: - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 = 6'd16; + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd16; 12'd384: - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 = 6'd17; + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd17; 12'd768: - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 = 6'd18; + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd18; 12'd769: - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 = 6'd19; + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd19; 12'd770: - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 = 6'd20; + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd20; 12'd771: - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 = 6'd21; + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd21; 12'd772: - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 = 6'd22; + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd22; 12'd773: - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 = 6'd23; + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd23; 12'd774: - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 = 6'd24; + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd24; 12'd832: - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 = 6'd25; + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd25; 12'd833: - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 = 6'd26; + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd26; 12'd834: - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 = 6'd27; + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd27; 12'd835: - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 = 6'd28; + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd28; 12'd836: - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 = 6'd29; + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd29; 12'd1952: - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 = 6'd36; + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd36; 12'd1953: - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 = 6'd37; + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd37; 12'd1954: - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 = 6'd38; + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd38; 12'd1955: - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 = 6'd39; + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd39; 12'd2048: - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 = 6'd6; + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd6; 12'd2049: - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 = 6'd7; + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd7; 12'd2816: - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 = 6'd30; + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd30; 12'd2818: - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 = 6'd31; + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd31; 12'd3072: - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 = 6'd3; + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd3; 12'd3073: - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 = 6'd4; + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd4; 12'd3074: - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 = 6'd5; + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd5; 12'd3857: - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 = 6'd32; + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd32; 12'd3858: - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 = 6'd33; + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd33; 12'd3859: - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 = 6'd34; + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd34; 12'd3860: - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 = 6'd35; - default: IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 = + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd35; + default: IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd40; endcase end @@ -38570,21 +38580,21 @@ module mkCore(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[257:253] == 5'd13 && - IF_rob_deqPort_0_deq_data__4456_BIT_181_4686_T_ETC___d14768 == 6'd6) + IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd6) $display("[Terminate CSR] being written (val = %x), ", "send terminate signal to host", rob$deqPort_0_deq_data[95:32]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && - NOT_IF_rob_deqPort_0_deq_data__4456_BITS_97_TO_ETC___d14962) + NOT_IF_rob_deqPort_0_deq_data__4466_BITS_97_TO_ETC___d14972) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && - NOT_IF_rob_deqPort_0_deq_data__4456_BITS_97_TO_ETC___d14962) + NOT_IF_rob_deqPort_0_deq_data__4466_BITS_97_TO_ETC___d14972) $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv\", line 763, column 39\nppc must be pc + 4"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && - NOT_IF_rob_deqPort_0_deq_data__4456_BITS_97_TO_ETC___d14962) + NOT_IF_rob_deqPort_0_deq_data__4466_BITS_97_TO_ETC___d14972) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && @@ -38600,15 +38610,15 @@ module mkCore(CLK, $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && - NOT_rob_deqPort_0_deq_data__4456_BITS_257_TO_2_ETC___d14972) + NOT_rob_deqPort_0_deq_data__4466_BITS_257_TO_2_ETC___d14982) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && - NOT_rob_deqPort_0_deq_data__4456_BITS_257_TO_2_ETC___d14972) + NOT_rob_deqPort_0_deq_data__4466_BITS_257_TO_2_ETC___d14982) $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv\", line 825, column 54\nonly CSR has valid csr idx"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && - NOT_rob_deqPort_0_deq_data__4456_BITS_257_TO_2_ETC___d14972) + NOT_rob_deqPort_0_deq_data__4466_BITS_257_TO_2_ETC___d14982) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && @@ -38758,7 +38768,7 @@ module mkCore(CLK, rob$deqPort_1_deq_data[257:253] != 5'd20) $write("instret:%0d PC:0x%0h instr:0x%08h", commitStage_rg_serial_num + - IF_rob_deqPort_0_canDeq__4986_THEN_IF_NOT_rob__ETC___d15095, + IF_rob_deqPort_0_canDeq__4996_THEN_IF_NOT_rob__ETC___d15105, rob$deqPort_1_deq_data[353:290], rob$deqPort_1_deq_data[289:258], " iType:"); @@ -40015,149 +40025,149 @@ module mkCore(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3518_AND__ETC___d14201) + regRenamingTable_rename_0_canRename__3528_AND__ETC___d14211) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3518_AND__ETC___d14201) - $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv\", line 978, column 61\nFpuMulDiv next PC is not PC+4/PC+2"); + regRenamingTable_rename_0_canRename__3528_AND__ETC___d14211) + $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv\", line 981, column 61\nFpuMulDiv next PC is not PC+4/PC+2"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3518_AND__ETC___d14201) + regRenamingTable_rename_0_canRename__3528_AND__ETC___d14211) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3518_AND__ETC___d14206) + regRenamingTable_rename_0_canRename__3528_AND__ETC___d14216) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3518_AND__ETC___d14206) - $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv\", line 979, column 59\nFpuMulDiv never explicitly read/write CSR"); + regRenamingTable_rename_0_canRename__3528_AND__ETC___d14216) + $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv\", line 982, column 59\nFpuMulDiv never explicitly read/write CSR"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3518_AND__ETC___d14206) + regRenamingTable_rename_0_canRename__3528_AND__ETC___d14216) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3518_AND__ETC___d14231) + regRenamingTable_rename_0_canRename__3528_AND__ETC___d14241) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3518_AND__ETC___d14231) - $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv\", line 1010, column 65\nMem next PC is not PC+4/PC+2"); + regRenamingTable_rename_0_canRename__3528_AND__ETC___d14241) + $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv\", line 1013, column 65\nMem next PC is not PC+4/PC+2"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3518_AND__ETC___d14231) + regRenamingTable_rename_0_canRename__3528_AND__ETC___d14241) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3518_AND__ETC___d14235) + regRenamingTable_rename_0_canRename__3528_AND__ETC___d14245) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3518_AND__ETC___d14235) - $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv\", line 1011, column 63\nMem never explicitly read/write CSR"); + regRenamingTable_rename_0_canRename__3528_AND__ETC___d14245) + $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv\", line 1014, column 63\nMem never explicitly read/write CSR"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3518_AND__ETC___d14235) + regRenamingTable_rename_0_canRename__3528_AND__ETC___d14245) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3518_AND__ETC___d14241) + regRenamingTable_rename_0_canRename__3528_AND__ETC___d14251) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3518_AND__ETC___d14241) - $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv\", line 1013, column 42\nMem (non-Fence) needs imm for virtual addr"); + regRenamingTable_rename_0_canRename__3528_AND__ETC___d14251) + $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv\", line 1016, column 42\nMem (non-Fence) needs imm for virtual addr"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3518_AND__ETC___d14241) + regRenamingTable_rename_0_canRename__3528_AND__ETC___d14251) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14368) + NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14378) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14368) - $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv\", line 978, column 61\nFpuMulDiv next PC is not PC+4/PC+2"); + NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14378) + $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv\", line 981, column 61\nFpuMulDiv next PC is not PC+4/PC+2"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14368) + NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14378) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14299 && - regRenamingTable_rename_1_canRename__3637_AND__ETC___d14308 && - NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d14371) + NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14309 && + regRenamingTable_rename_1_canRename__3647_AND__ETC___d14318 && + NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d14381) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14299 && - regRenamingTable_rename_1_canRename__3637_AND__ETC___d14308 && - NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d14371) - $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv\", line 979, column 59\nFpuMulDiv never explicitly read/write CSR"); + NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14309 && + regRenamingTable_rename_1_canRename__3647_AND__ETC___d14318 && + NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d14381) + $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv\", line 982, column 59\nFpuMulDiv never explicitly read/write CSR"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14299 && - regRenamingTable_rename_1_canRename__3637_AND__ETC___d14308 && - NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d14371) + NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14309 && + regRenamingTable_rename_1_canRename__3647_AND__ETC___d14318 && + NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d14381) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14299 && - regRenamingTable_rename_1_canRename__3637_AND__ETC___d14392) + NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14309 && + regRenamingTable_rename_1_canRename__3647_AND__ETC___d14402) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14299 && - regRenamingTable_rename_1_canRename__3637_AND__ETC___d14392) - $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv\", line 1010, column 65\nMem next PC is not PC+4/PC+2"); + NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14309 && + regRenamingTable_rename_1_canRename__3647_AND__ETC___d14402) + $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv\", line 1013, column 65\nMem next PC is not PC+4/PC+2"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14299 && - regRenamingTable_rename_1_canRename__3637_AND__ETC___d14392) + NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14309 && + regRenamingTable_rename_1_canRename__3647_AND__ETC___d14402) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14397) + NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14407) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14397) - $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv\", line 1011, column 63\nMem never explicitly read/write CSR"); + NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14407) + $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv\", line 1014, column 63\nMem never explicitly read/write CSR"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14397) + NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14407) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14299 && - regRenamingTable_rename_1_canRename__3637_AND__ETC___d14402) + NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14309 && + regRenamingTable_rename_1_canRename__3647_AND__ETC___d14412) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14299 && - regRenamingTable_rename_1_canRename__3637_AND__ETC___d14402) - $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv\", line 1013, column 42\nMem (non-Fence) needs imm for virtual addr"); + NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14309 && + regRenamingTable_rename_1_canRename__3647_AND__ETC___d14412) + $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv\", line 1016, column 42\nMem (non-Fence) needs imm for virtual addr"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14299 && - regRenamingTable_rename_1_canRename__3637_AND__ETC___d14402) + NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14309 && + regRenamingTable_rename_1_canRename__3647_AND__ETC___d14412) $finish(32'd0); end // synopsys translate_on diff --git a/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkProc.v b/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkProc.v index de21a79..0159abb 100644 --- a/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkProc.v +++ b/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkProc.v @@ -1904,8 +1904,8 @@ module mkProc(CLK, // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h163702; - reg [31 : 0] v__h163266; + reg [31 : 0] v__h163686; + reg [31 : 0] v__h163250; reg [31 : 0] v__h5300; reg [31 : 0] v__h5473; reg [31 : 0] v__h5733; @@ -1916,13 +1916,13 @@ module mkProc(CLK, reg [31 : 0] v__h9260; reg [31 : 0] v__h9753; reg [31 : 0] v__h9916; - reg [31 : 0] v__h135223; - reg [31 : 0] v__h135390; - reg [31 : 0] v__h137493; - reg [31 : 0] v__h154837; - reg [31 : 0] v__h134604; - reg [31 : 0] v__h161531; - reg [31 : 0] v__h162039; + reg [31 : 0] v__h135207; + reg [31 : 0] v__h135374; + reg [31 : 0] v__h137477; + reg [31 : 0] v__h154821; + reg [31 : 0] v__h134588; + reg [31 : 0] v__h161515; + reg [31 : 0] v__h162023; reg [31 : 0] v__h2444; reg [31 : 0] v__h4117; reg [31 : 0] v__h5294; @@ -1933,276 +1933,274 @@ module mkProc(CLK, reg [31 : 0] v__h9254; reg [31 : 0] v__h9747; reg [31 : 0] v__h9910; - reg [31 : 0] v__h134598; - reg [31 : 0] v__h135217; - reg [31 : 0] v__h135384; - reg [31 : 0] v__h137487; - reg [31 : 0] v__h154831; - reg [31 : 0] v__h161525; - reg [31 : 0] v__h162033; - reg [31 : 0] v__h163260; - reg [31 : 0] v__h163696; + reg [31 : 0] v__h134582; + reg [31 : 0] v__h135201; + reg [31 : 0] v__h135368; + reg [31 : 0] v__h137471; + reg [31 : 0] v__h154815; + reg [31 : 0] v__h161509; + reg [31 : 0] v__h162017; + reg [31 : 0] v__h163244; + reg [31 : 0] v__h163680; // synopsys translate_on // remaining internal signals reg [63 : 0] CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5, CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6, CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9, - CASE_x0307_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16, - CASE_x0307_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17, - CASE_x0307_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18, - CASE_x0307_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19, - CASE_x0307_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20, - CASE_x0307_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21, - CASE_x0307_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22, - CASE_x0307_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23, - CASE_x0307_0_n__read_addr0485_1_n__read_addr05_ETC__q26, - CASE_x1422_0_n__read_addr1604_1_n__read_addr16_ETC__q15, - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d813, - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d826, - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d865, - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d877, - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d947, - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d956, - IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923, - IF_mmioPlatform_reqSz_83_EQ_0b10_90_THEN_SEXT__ETC___d891, - IF_mmioPlatform_reqSz_83_EQ_0b10_90_THEN_SEXT__ETC___d893, - data64__h148663, - dword__h94465, - ld_data__h132752, - old_dword__h90155, - w1__h48022, - w1__h48027, - w2__h48023, - w2__h48029, - x__h48018; - reg [31 : 0] SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d991; - reg [7 : 0] strb8__h148664; - reg [5 : 0] IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_ETC___d481; - reg [2 : 0] x__h61736; - reg [1 : 0] CASE_x0307_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24, - CASE_x1422_0_IF_propDstData_0_dummy2_1_read__1_ETC__q13, - CASE_x1422_0_IF_propDstData_0_dummy2_1_read__1_ETC__q14; + CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16, + CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17, + CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18, + CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19, + CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20, + CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21, + CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22, + CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23, + CASE_x0291_0_n__read_addr0469_1_n__read_addr05_ETC__q26, + CASE_x1406_0_n__read_addr1588_1_n__read_addr16_ETC__q15, + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809, + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822, + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861, + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873, + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943, + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d952, + IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919, + IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d887, + IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d889, + data64__h148647, + dword__h94449, + ld_data__h132736, + old_dword__h90139, + w1__h48006, + w1__h48011, + w2__h48007, + w2__h48013, + x__h48002; + reg [31 : 0] SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d987; + reg [7 : 0] strb8__h148648; + reg [5 : 0] IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d477; + reg [2 : 0] x__h61720; + reg [1 : 0] CASE_x0291_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24, + CASE_x1406_0_IF_propDstData_0_dummy2_1_read__1_ETC__q13, + CASE_x1406_0_IF_propDstData_0_dummy2_1_read__1_ETC__q14; reg CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q10, CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q11, - CASE_x0307_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25, - CASE_x1422_0_propDstData_0_dummy2_1_read__104__ETC__q12, - SEL_ARR_propDstIdx_0_dummy2_1_read__066_AND_IF_ETC___d1097, - SEL_ARR_propDstIdx_1_0_dummy2_1_read__330_AND__ETC___d1371, - x__h61743, - x__h82723; - wire [579 : 0] IF_enqDst_1_0_lat_1_whas__275_THEN_enqDst_1_0__ETC___d1322; - wire [515 : 0] SEL_ARR_IF_propDstData_1_0_dummy2_1_read__378__ETC___d1470; - wire [513 : 0] IF_enqDst_1_0_lat_1_whas__275_THEN_enqDst_1_0__ETC___d1321; - wire [511 : 0] IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1313, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__202_THE_ETC___d1463, - new_cline__h135526; - wire [383 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1600, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__202_THE_ETC___d1446; - wire [255 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1595, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__202_THE_ETC___d1429; - wire [127 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__202_THE_ETC___d1412; - wire [66 : 0] IF_core_0_mmioToPlatform_cRq_first__82_BITS_14_ETC___d405; - wire [65 : 0] DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_40_BIT_ETC___d684; - wire [64 : 0] IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_2_ETC___d726; - wire [63 : 0] IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1293, - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d833, - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d884, - IF_mmioPlatform_reqBE_43_BIT_4_44_THEN_SEXT_mm_ETC___d577, - IF_mmioPlatform_reqBE_43_BIT_4_44_THEN_SEXT_mm_ETC___d641, - IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d552, - IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d614, - IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d718, - IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_1_ETC___d578, - IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_1_ETC___d642, - IF_propDstData_1_0_lat_0_whas__202_THEN_propDs_ETC___d1207, - IF_propDstData_1_1_lat_0_whas__240_THEN_propDs_ETC___d1245, - data__h31746, - failed_testnum__h163309, - line_addr__h102529, - line_addr__h102615, - mask__h90152, - mem_req_rd_addr_araddr__h134824, - mem_req_wr_addr_awaddr__h148748, - mmioPlatform_fromHostQ_data_0__h42593, - mmioPlatform_mtime__h37060, - mmioPlatform_reqData__h48614, - n__read_addr__h61604, - n__read_addr__h61689, - n__read_addr__h80485, - n__read_addr__h80564, - n__read_snd_addr__h124056, - newData__h31827, - newData__h34757, - new_dword__h90156, - op_result__h48630, - op_result__h49160, + CASE_x0291_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25, + CASE_x1406_0_propDstData_0_dummy2_1_read__100__ETC__q12, + SEL_ARR_propDstIdx_0_dummy2_1_read__062_AND_IF_ETC___d1093, + SEL_ARR_propDstIdx_1_0_dummy2_1_read__326_AND__ETC___d1367, + x__h61727, + x__h82707; + wire [579 : 0] IF_enqDst_1_0_lat_1_whas__271_THEN_enqDst_1_0__ETC___d1318; + wire [515 : 0] SEL_ARR_IF_propDstData_1_0_dummy2_1_read__374__ETC___d1466; + wire [513 : 0] IF_enqDst_1_0_lat_1_whas__271_THEN_enqDst_1_0__ETC___d1317; + wire [511 : 0] IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1309, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1459, + new_cline__h135510; + wire [383 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1596, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1442; + wire [255 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1591, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1425; + wire [127 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1408; + wire [66 : 0] IF_core_0_mmioToPlatform_cRq_first__78_BITS_14_ETC___d401; + wire [65 : 0] DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_36_BIT_ETC___d680; + wire [64 : 0] IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_2_ETC___d722; + wire [63 : 0] IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1289, + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829, + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d880, + IF_mmioPlatform_reqBE_39_BIT_4_40_THEN_SEXT_mm_ETC___d573, + IF_mmioPlatform_reqBE_39_BIT_4_40_THEN_SEXT_mm_ETC___d637, + IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d548, + IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d610, + IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d714, + IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_1_ETC___d574, + IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_1_ETC___d638, + IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1203, + IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1241, + data__h31730, + failed_testnum__h163293, + line_addr__h102513, + line_addr__h102599, + mask__h90136, + mem_req_rd_addr_araddr__h134808, + mem_req_wr_addr_awaddr__h148732, + mmioPlatform_fromHostQ_data_0__h42577, + mmioPlatform_mtime__h37044, + mmioPlatform_reqData__h48598, + n__read_addr__h61588, + n__read_addr__h61673, + n__read_addr__h80469, + n__read_addr__h80548, + n__read_snd_addr__h124040, + newData__h31811, + newData__h34741, + new_dword__h90140, + op_result__h48614, + op_result__h49144, + op_result__h49149, + op_result__h49154, + op_result__h49159, op_result__h49165, - op_result__h49170, - op_result__h49175, - op_result__h49181, - op_result__h49188, - op_result__h49194, - result__h48073, - result__h48197, - result__h48225, - result__h48253, - result__h48281, - result__h48309, - result__h48337, - result__h48365, - result__h48393, - result__h48438, - result__h48466, - result__h48494, - result__h48522, - result__h48563, - result__h48591, - result__h48717, - result__h48744, - result__h48771, - result__h48798, - result__h48825, - result__h48852, - result__h48879, - result__h48906, - result__h48950, - result__h48977, - result__h49004, - result__h49031, - result__h49071, - result__h49098, - result__h49215, - result__h49281, - result__h49347, - result__h49413, - result__h49479, - result__h49545, - result__h49611, - result__h49673, - result__h49718, - result__h49784, - result__h49850, - result__h49908, - result__h49953, - w1___1__h48132, - w2___1__h48133, - x1_avValue_data__h40265, - x1_avValue_data__h44951, - x__h31938, - x__h34848, - x__h37208, - x__h40783, - x__h40794, - x__h42876, - x__h42887, - x__h50130, - x__h91318, - y__h91319, - y__h91320; - wire [47 : 0] IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d544, - IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d609, - IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d713; - wire [31 : 0] IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d535, - IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d604, - IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d708, - IF_mmio_axi4_adapter_f_rsps_to_core_first__64__ETC___d999, + op_result__h49172, + op_result__h49178, + result__h48057, + result__h48181, + result__h48209, + result__h48237, + result__h48265, + result__h48293, + result__h48321, + result__h48349, + result__h48377, + result__h48422, + result__h48450, + result__h48478, + result__h48506, + result__h48547, + result__h48575, + result__h48701, + result__h48728, + result__h48755, + result__h48782, + result__h48809, + result__h48836, + result__h48863, + result__h48890, + result__h48934, + result__h48961, + result__h48988, + result__h49015, + result__h49055, + result__h49082, + result__h49199, + result__h49265, + result__h49331, + result__h49397, + result__h49463, + result__h49529, + result__h49595, + result__h49657, + result__h49702, + result__h49768, + result__h49834, + result__h49892, + result__h49937, + w1___1__h48116, + w2___1__h48117, + x1_avValue_data__h40249, + x1_avValue_data__h44935, + x__h31922, + x__h34832, + x__h37192, + x__h40767, + x__h40778, + x__h42860, + x__h42871, + x__h50114, + x__h91302, + y__h91303, + y__h91304; + wire [47 : 0] IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d540, + IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d605, + IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d709; + wire [31 : 0] IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d531, + IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d600, + IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d704, + IF_mmio_axi4_adapter_f_rsps_to_core_first__60__ETC___d995, mmioPlatform_mtime_BITS_31_TO_0__q4, mmioPlatform_mtime_BITS_63_TO_32__q3, mmioPlatform_mtimecmp_0_BITS_31_TO_0__q2, mmioPlatform_mtimecmp_0_BITS_63_TO_32__q1, - v__h31539, - v__h31576, - w18022_BITS_31_TO_0__q7, - w28023_BITS_31_TO_0__q8, - x_data__h30329; - wire [8 : 0] SEL_ARR_IF_propDstData_0_dummy2_1_read__104_TH_ETC___d1168; - wire [5 : 0] x__h134859, x__h148773; - wire [4 : 0] SEL_ARR_propDstData_0_dummy2_1_read__104_AND_I_ETC___d1167; - wire [3 : 0] b__h134531, b__h2344; - wire [2 : 0] n__read_id__h61608, n__read_id__h61693, x__h7705; - wire [1 : 0] IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1298, - IF_propDstData_0_dummy2_1_read__104_THEN_IF_pr_ETC___d1120, - IF_propDstData_0_dummy2_1_read__104_THEN_IF_pr_ETC___d1130, - IF_propDstData_1_0_lat_0_whas__202_THEN_propDs_ETC___d1212, - IF_propDstData_1_1_lat_0_whas__240_THEN_propDs_ETC___d1250, - IF_propDstData_1_dummy2_1_read__109_THEN_IF_pr_ETC___d1124, - IF_propDstData_1_dummy2_1_read__109_THEN_IF_pr_ETC___d1134; - wire IF_IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4__ETC___d559, - IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d456, - IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554, - IF_NOT_propDstIdx_0_dummy2_1_read__066_067_OR__ETC___d1101, - IF_NOT_propDstIdx_1_0_dummy2_1_read__330_331_O_ETC___d1375, - IF_SEL_ARR_propDstIdx_0_dummy2_1_read__066_AND_ETC___d1173, - IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__330_A_ETC___d1475, - IF_enqDst_0_lat_0_whas__042_THEN_enqDst_0_lat__ETC___d1047, - IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1283, - IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1303, - IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1319, - IF_llc_mem_server_enqDst_0_lat_0_whas__680_THE_ETC___d1685, - IF_llc_mem_server_propDstIdx_0_lat_0_whas__665_ETC___d1668, - IF_mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioP_ETC___d625, - IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_ETC___d457, + v__h31523, + v__h31560, + w18006_BITS_31_TO_0__q7, + w28007_BITS_31_TO_0__q8, + x_data__h30313; + wire [8 : 0] SEL_ARR_IF_propDstData_0_dummy2_1_read__100_TH_ETC___d1164; + wire [5 : 0] x__h134843, x__h148757; + wire [4 : 0] SEL_ARR_propDstData_0_dummy2_1_read__100_AND_I_ETC___d1163; + wire [3 : 0] b__h134515, b__h2344; + wire [2 : 0] n__read_id__h61592, n__read_id__h61677, x__h7705; + wire [1 : 0] IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1294, + IF_propDstData_0_dummy2_1_read__100_THEN_IF_pr_ETC___d1116, + IF_propDstData_0_dummy2_1_read__100_THEN_IF_pr_ETC___d1126, + IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1208, + IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1246, + IF_propDstData_1_dummy2_1_read__105_THEN_IF_pr_ETC___d1120, + IF_propDstData_1_dummy2_1_read__105_THEN_IF_pr_ETC___d1130; + wire IF_IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4__ETC___d555, + IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d452, + IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550, + IF_NOT_propDstIdx_0_dummy2_1_read__062_063_OR__ETC___d1097, + IF_NOT_propDstIdx_1_0_dummy2_1_read__326_327_O_ETC___d1371, + IF_SEL_ARR_propDstIdx_0_dummy2_1_read__062_AND_ETC___d1169, + IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__326_A_ETC___d1471, + IF_enqDst_0_lat_0_whas__038_THEN_enqDst_0_lat__ETC___d1043, + IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1279, + IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1299, + IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1315, + IF_llc_mem_server_enqDst_0_lat_0_whas__676_THE_ETC___d1681, + IF_llc_mem_server_propDstIdx_0_lat_0_whas__661_ETC___d1664, + IF_mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioP_ETC___d621, + IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d453, IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__91__ETC___d200, - IF_mmioPlatform_waitLowerMSIPCRs_92_THEN_core__ETC___d500, - IF_mmio_axi4_adapter_f_rsps_to_core_first__64__ETC___d978, + IF_mmioPlatform_waitLowerMSIPCRs_88_THEN_core__ETC___d496, + IF_mmio_axi4_adapter_f_rsps_to_core_first__60__ETC___d974, IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d103, - IF_propDstData_1_0_lat_0_whas__202_THEN_propDs_ETC___d1233, - IF_propDstData_1_1_lat_0_whas__240_THEN_propDs_ETC___d1271, - IF_propDstIdx_0_lat_0_whas__013_THEN_propDstId_ETC___d1016, - IF_propDstIdx_1_0_lat_0_whas__187_THEN_propDst_ETC___d1190, - IF_propDstIdx_1_1_lat_0_whas__194_THEN_propDst_ETC___d1197, - IF_propDstIdx_1_lat_0_whas__020_THEN_propDstId_ETC___d1023, - NOT_enqDst_0_dummy2_0_read__087_088_OR_NOT_enq_ETC___d1103, - NOT_enqDst_1_0_dummy2_0_read__361_362_OR_NOT_e_ETC___d1377, - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801, - NOT_llc_mem_server_enqDst_0_dummy2_0_read__711_ETC___d1718, - NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d754, - NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d762, - NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d767, - NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d777, - NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d968, - NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d981, + IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1229, + IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1267, + IF_propDstIdx_0_lat_0_whas__009_THEN_propDstId_ETC___d1012, + IF_propDstIdx_1_0_lat_0_whas__183_THEN_propDst_ETC___d1186, + IF_propDstIdx_1_1_lat_0_whas__190_THEN_propDst_ETC___d1193, + IF_propDstIdx_1_lat_0_whas__016_THEN_propDstId_ETC___d1019, + NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099, + NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373, + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797, + NOT_llc_mem_server_enqDst_0_dummy2_0_read__707_ETC___d1714, + NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d750, + NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d758, + NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d763, + NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d773, + NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d964, + NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d977, NOT_mmioPlatform_fromHostQ_clearReq_dummy2_1_r_ETC___d318, NOT_mmioPlatform_fromHostQ_enqReq_dummy2_2_rea_ETC___d339, - NOT_mmioPlatform_mtip_0_55_64_AND_mmioPlatform_ETC___d374, - NOT_mmioPlatform_mtip_0_55_64_AND_mmioPlatform_ETC___d379, - NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d490, - NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d585, - NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d648, + NOT_mmioPlatform_mtip_0_55_62_AND_mmioPlatform_ETC___d370, + NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d486, + NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d581, + NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d644, NOT_mmioPlatform_toHostQ_clearReq_dummy2_1_rea_ETC___d240, NOT_mmioPlatform_toHostQ_enqReq_dummy2_2_read__ETC___d261, - NOT_propDstData_1_0_dummy2_1_read__378_389_OR__ETC___d1390, - NOT_propDstData_1_1_dummy2_1_read__380_391_OR__ETC___d1392, - NOT_propDstIdx_0_dummy2_1_read__066_067_OR_IF__ETC___d1100, - NOT_propDstIdx_1_0_dummy2_1_read__330_331_OR_I_ETC___d1374, - NOT_propDstIdx_1_1_dummy2_1_read__348_349_OR_I_ETC___d1481, - NOT_propDstIdx_1_dummy2_1_read__079_080_OR_IF__ETC___d1179, - llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1612, - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1534, + NOT_propDstData_1_0_dummy2_1_read__374_385_OR__ETC___d1386, + NOT_propDstData_1_1_dummy2_1_read__376_387_OR__ETC___d1388, + NOT_propDstIdx_0_dummy2_1_read__062_063_OR_IF__ETC___d1096, + NOT_propDstIdx_1_0_dummy2_1_read__326_327_OR_I_ETC___d1370, + NOT_propDstIdx_1_1_dummy2_1_read__344_345_OR_I_ETC___d1477, + NOT_propDstIdx_1_dummy2_1_read__075_076_OR_IF__ETC___d1175, + llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1608, + llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1530, mmioPlatform_cycle_47_ULT_99___d348, - mmioPlatform_fetchingWay_73_ULT_mmioPlatform_r_ETC___d983, + mmioPlatform_fetchingWay_69_ULT_mmioPlatform_r_ETC___d979, mmioPlatform_fromHostQ_enqReq_dummy2_2_read__1_ETC___d331, - mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616, + mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612, mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357, - mmioPlatform_mtip_0_55_OR_NOT_mmioPlatform_mti_ETC___d410, - mmioPlatform_reqBE_BIT_0___h29954, - mmioPlatform_reqBE_BIT_4___h29914, - mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d467, - mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d571, - mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d636, + mmioPlatform_reqBE_BIT_0___h29938, + mmioPlatform_reqBE_BIT_4___h29898, + mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d463, + mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d567, + mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d632, mmioPlatform_toHostQ_enqReq_dummy2_2_read__41__ETC___d253, mmio_axi4_adapter_f_reqs_from_core_i_notEmpty__ETC___d9, - n__read_child__h61609, - n__read_child__h61694, - n__read_child__h80488, - n__read_child__h80567, - n__read_snd_id__h124057, - propDstData_0_dummy2_1_read__104_AND_IF_propDs_ETC___d1140, - propDstData_1_dummy2_1_read__109_AND_IF_propDs_ETC___d1144, - x__h61422, - x__h75236, - x__h80307; + n__read_child__h61593, + n__read_child__h61678, + n__read_child__h80472, + n__read_child__h80551, + n__read_snd_id__h124041, + propDstData_0_dummy2_1_read__100_AND_IF_propDs_ETC___d1136, + propDstData_1_dummy2_1_read__105_AND_IF_propDs_ETC___d1140, + x__h61406, + x__h75220, + x__h80291; // action method start assign RDY_start = mmioPlatform_state == 2'd0 ; @@ -3152,7 +3150,7 @@ module mkProc(CLK, // rule RL_doEnq assign CAN_FIRE_RL_doEnq = llc$RDY_to_child_rqFromC_enq && enqDst_0_dummy2_1$Q_OUT && - IF_enqDst_0_lat_0_whas__042_THEN_enqDst_0_lat__ETC___d1047 ; + IF_enqDst_0_lat_0_whas__038_THEN_enqDst_0_lat__ETC___d1043 ; assign WILL_FIRE_RL_doEnq = CAN_FIRE_RL_doEnq ; // rule RL_srcPropose_2 @@ -3180,7 +3178,7 @@ module mkProc(CLK, // rule RL_doEnq_1 assign CAN_FIRE_RL_doEnq_1 = llc$RDY_to_child_rsFromC_enq && enqDst_1_0_dummy2_1$Q_OUT && - IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1283 ; + IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1279 ; assign WILL_FIRE_RL_doEnq_1 = CAN_FIRE_RL_doEnq_1 ; // rule RL_sendPRq @@ -3341,9 +3339,8 @@ module mkProc(CLK, assign CAN_FIRE_RL_mmioPlatform_selectReq = (mmioPlatform_mtip_0 || !mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 || - mmioPlatform_mtimecmp_0 == 64'd0 || core_0$RDY_mmioToPlatform_pRq_enq) && - NOT_mmioPlatform_mtip_0_55_64_AND_mmioPlatform_ETC___d374 && + NOT_mmioPlatform_mtip_0_55_62_AND_mmioPlatform_ETC___d370 && mmioPlatform_state == 2'd1 ; assign WILL_FIRE_RL_mmioPlatform_selectReq = CAN_FIRE_RL_mmioPlatform_selectReq && @@ -3360,7 +3357,7 @@ module mkProc(CLK, // rule RL_mmioPlatform_processMSIP assign CAN_FIRE_RL_mmioPlatform_processMSIP = - IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_ETC___d457 && + IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d453 && mmioPlatform_curReq[66:64] == 3'd2 && mmioPlatform_state == 2'd2 ; assign WILL_FIRE_RL_mmioPlatform_processMSIP = @@ -3369,7 +3366,7 @@ module mkProc(CLK, // rule RL_mmioPlatform_waitMSIPDone assign CAN_FIRE_RL_mmioPlatform_waitMSIPDone = core_0$RDY_mmioToPlatform_pRs_enq && - IF_mmioPlatform_waitLowerMSIPCRs_92_THEN_core__ETC___d500 && + IF_mmioPlatform_waitLowerMSIPCRs_88_THEN_core__ETC___d496 && mmioPlatform_curReq[66:64] == 3'd2 && mmioPlatform_state == 2'd3 ; assign WILL_FIRE_RL_mmioPlatform_waitMSIPDone = @@ -3415,7 +3412,7 @@ module mkProc(CLK, core_0$RDY_mmioToPlatform_pRs_enq && (mmioPlatform_reqFunc[5:4] != 2'd2 || !mmioPlatform_toHostQ_empty || - x__h42876 == 64'd0 || + x__h42860 == 64'd0 || !mmioPlatform_toHostQ_full) && mmioPlatform_state == 2'd2 && mmioPlatform_curReq[66:64] == 3'd5 ; @@ -3433,7 +3430,7 @@ module mkProc(CLK, // rule RL_mmioPlatform_rl_mmio_to_fabric_req assign CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req = mmio_axi4_adapter_f_reqs_from_core$FULL_N && - NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d754 ; + NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d750 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req = CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req ; @@ -3441,14 +3438,14 @@ module mkProc(CLK, assign CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp = core_0$RDY_mmioToPlatform_pRs_enq && mmio_axi4_adapter_f_rsps_to_core$EMPTY_N && - NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d762 ; + NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d758 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp = CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp ; // rule RL_mmioPlatform_rl_mmio_to_fabric_amo_req assign CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req = mmio_axi4_adapter_f_reqs_from_core$FULL_N && - NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d767 ; + NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d763 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req = CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req ; @@ -3458,22 +3455,22 @@ module mkProc(CLK, mmio_axi4_adapter_f_rsps_to_core$EMPTY_N && (!mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] || mmio_axi4_adapter_f_reqs_from_core$FULL_N) && - NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d777 ; + NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d773 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp = CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp ; // rule RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req assign CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req = mmio_axi4_adapter_f_reqs_from_core$FULL_N && - NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d968 ; + NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d964 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req = CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req ; // rule RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp assign CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp = mmio_axi4_adapter_f_rsps_to_core$EMPTY_N && - IF_mmio_axi4_adapter_f_rsps_to_core_first__64__ETC___d978 && - NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d981 ; + IF_mmio_axi4_adapter_f_rsps_to_core_first__60__ETC___d974 && + NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d977 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp = CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp ; @@ -3555,7 +3552,7 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_f_rd_data$FULL_N && (llc_mem_server_rg_cacheline_cache_state == 3'd3 || llc_mem_server_rg_cacheline_cache_state == 3'd4) && - llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1612 ; + llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1608 ; assign WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req = CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req ; @@ -3573,7 +3570,7 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_f_wr_resp$FULL_N && (llc_mem_server_rg_cacheline_cache_state == 3'd3 || llc_mem_server_rg_cacheline_cache_state == 3'd4) && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1534 ; + llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1530 ; assign WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req = CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ; @@ -3591,7 +3588,7 @@ module mkProc(CLK, llc$RDY_dma_memReq_enq && llc_mem_server_axi4_slave_xactor_f_wr_addr$EMPTY_N && llc_mem_server_rg_cacheline_cache_state == 3'd4 && - !llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1534 ; + !llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1530 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss && !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged ; @@ -3601,7 +3598,7 @@ module mkProc(CLK, llc$RDY_dma_memReq_enq && llc_mem_server_axi4_slave_xactor_f_rd_addr$EMPTY_N && llc_mem_server_rg_cacheline_cache_state == 3'd4 && - !llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1612 ; + !llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1608 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss && !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss && @@ -3621,7 +3618,7 @@ module mkProc(CLK, llc$RDY_dma_memReq_enq && llc_mem_server_axi4_slave_xactor_f_wr_addr$EMPTY_N && llc_mem_server_rg_cacheline_cache_state == 3'd3 && - !llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1534 ; + !llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1530 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ; @@ -3630,7 +3627,7 @@ module mkProc(CLK, llc$RDY_dma_memReq_enq && llc_mem_server_axi4_slave_xactor_f_rd_addr$EMPTY_N && llc_mem_server_rg_cacheline_cache_state == 3'd3 && - !llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1612 ; + !llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1608 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld && !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st && @@ -3662,7 +3659,7 @@ module mkProc(CLK, assign CAN_FIRE_RL_llc_mem_server_doEnq = llc_mem_server_tlbQ$FULL_N && llc_mem_server_enqDst_0_dummy2_1$Q_OUT && - IF_llc_mem_server_enqDst_0_lat_0_whas__680_THE_ETC___d1685 ; + IF_llc_mem_server_enqDst_0_lat_0_whas__676_THE_ETC___d1681 ; assign WILL_FIRE_RL_llc_mem_server_doEnq = CAN_FIRE_RL_llc_mem_server_doEnq ; @@ -3735,13 +3732,13 @@ module mkProc(CLK, (llc_axi4_adapter_rg_rd_req_beat != 3'd7 || llc$RDY_to_mem_toM_deq) && !llc$to_mem_toM_first[640] && - b__h134531 == 4'd0 ; + b__h134515 == 4'd0 ; assign WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ; // rule RL_llc_axi4_adapter_rl_discard_write_rsp assign CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp = - b__h134531 != 4'd0 && + b__h134515 != 4'd0 && llc_axi4_adapter_master_xactor_crg_wr_resp_full && (llc_axi4_adapter_rg_wr_rsp_beat != 3'd7 || llc_axi4_adapter_f_pending_writes$EMPTY_N) ; @@ -3751,8 +3748,7 @@ module mkProc(CLK, // inputs to muxes for submodule ports assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 && - mmioPlatform_mtimecmp_0 != 64'd0 ; + mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_2 = WILL_FIRE_RL_mmioPlatform_processMSIP && mmioPlatform_reqFunc[5:4] != 2'd0 && @@ -3760,22 +3756,22 @@ module mkProc(CLK, mmioPlatform_reqBE[0] ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_3 = WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d585 ; + NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d581 ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_4 = WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d648 ; + NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d644 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_processMSIP && - mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d467 ; + mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d463 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_2 = WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d571 ; + mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d567 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_3 = WILL_FIRE_RL_mmioPlatform_processMTime && - mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d636 ; + mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d632 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_4 = WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && - (!mmioPlatform_fetchingWay_73_ULT_mmioPlatform_r_ETC___d983 || + (!mmioPlatform_fetchingWay_69_ULT_mmioPlatform_r_ETC___d979 || !mmio_axi4_adapter_f_rsps_to_core$D_OUT[64]) ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_5 = WILL_FIRE_RL_mmioPlatform_waitMTimeDone || @@ -3800,10 +3796,14 @@ module mkProc(CLK, mmioPlatform_reqFunc[5:4] != 2'd1 ; assign MUX_mmioPlatform_curReq$write_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_selectReq && - NOT_mmioPlatform_mtip_0_55_64_AND_mmioPlatform_ETC___d379 ; + (!mmioPlatform_mtip_0 && + mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 || + core_0$mmioToPlatform_cRq_notEmpty) ; assign MUX_mmioPlatform_fetchingWay$write_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_55_OR_NOT_mmioPlatform_mti_ETC___d410 ; + (mmioPlatform_mtip_0 || + !mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357) && + core_0$mmioToPlatform_cRq_notEmpty ; assign MUX_mmioPlatform_state$write_1__SEL_6 = WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp || @@ -3838,20 +3838,20 @@ module mkProc(CLK, llc$to_child_toC_first[515:0] } ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_2 = { 1'd0, - IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_ETC___d481, + IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d477, (mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? mmioPlatform_reqData[31:0] : - x_data__h30329 } ; + x_data__h30313 } ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_3 = { 7'd106, - (IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 && + (IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && !mmioPlatform_mtip_0) ? 32'd1 : 32'd0 } ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_4 = { 7'd106, - (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && + (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && !mmioPlatform_mtip_0) ? 32'd1 : 32'd0 } ; @@ -3865,35 +3865,35 @@ module mkProc(CLK, (mmioPlatform_reqFunc[5:4] == 2'd0) ? 66'h155555554AAAAAAAA : { 2'h1, - IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_1_ETC___d578 } } ; + IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_1_ETC___d574 } } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_3 = { mmioPlatform_reqFunc[5:4] != 2'd0, (mmioPlatform_reqFunc[5:4] == 2'd0) ? 66'h155555554AAAAAAAA : { 2'h1, - IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_1_ETC___d642 } } ; + IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_1_ETC___d638 } } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_4 = { 1'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] && mmioPlatform_fetchingWay, - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d991, + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d987, mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] || mmioPlatform_fetchingWay, - IF_mmio_axi4_adapter_f_rsps_to_core_first__64__ETC___d999 } ; + IF_mmio_axi4_adapter_f_rsps_to_core_first__60__ETC___d995 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_5 = { 3'd5, mmioPlatform_amoResp } ; - assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6 = { 3'd5, data__h31746 } ; + assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6 = { 3'd5, data__h31730 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_7 = { mmioPlatform_reqFunc[5:4] != 2'd0, (mmioPlatform_reqFunc[5:4] == 2'd0) ? 66'h155555554AAAAAAAA : - DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_40_BIT_ETC___d684 } ; + DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_36_BIT_ETC___d680 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_8 = { mmioPlatform_reqFunc[5:4] != 2'd0, (mmioPlatform_reqFunc[5:4] == 2'd0) ? 66'h155555554AAAAAAAA : { 1'h0, - IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_2_ETC___d726 } } ; + IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_2_ETC___d722 } } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_9 = { 2'd2, mmio_axi4_adapter_f_rsps_to_core$D_OUT } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_10 = @@ -3907,10 +3907,10 @@ module mkProc(CLK, llc_mem_server_rg_cacheline_cache_data, 5'd10 } ; assign MUX_llc$dma_memReq_enq_1__VAL_2 = - { line_addr__h102529, + { line_addr__h102513, 581'h0000000000000000155555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555554A } ; assign MUX_llc$dma_memReq_enq_1__VAL_3 = - { line_addr__h102615, + { line_addr__h102599, 581'h0000000000000000155555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555554A } ; assign MUX_llc$dma_memReq_enq_1__VAL_4 = { llc_mem_server_tlbQ$D_OUT[64:1], @@ -3918,29 +3918,28 @@ module mkProc(CLK, llc_mem_server_tlbQ$D_OUT[0], llc_mem_server_tlbQ$D_OUT[6:4] } ; assign MUX_llc_mem_server_rg_cacheline_cache_data$write_1__VAL_1 = - { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1600, + { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1596, (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd1) ? - new_dword__h90156 : + new_dword__h90140 : llc_mem_server_rg_cacheline_cache_data[127:64], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd0) ? - new_dword__h90156 : + new_dword__h90140 : llc_mem_server_rg_cacheline_cache_data[63:0] } ; assign MUX_llc_mem_server_rg_cacheline_cache_dirty_delay$write_1__VAL_2 = llc_mem_server_rg_cacheline_cache_dirty_delay - 10'd1 ; assign MUX_mmioPlatform_amoResp$write_1__VAL_1 = (mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtimecmp_0 : - IF_mmioPlatform_reqBE_43_BIT_4_44_THEN_SEXT_mm_ETC___d577 ; + IF_mmioPlatform_reqBE_39_BIT_4_40_THEN_SEXT_mm_ETC___d573 ; assign MUX_mmioPlatform_amoResp$write_1__VAL_2 = (mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtime : - IF_mmioPlatform_reqBE_43_BIT_4_44_THEN_SEXT_mm_ETC___d641 ; + IF_mmioPlatform_reqBE_39_BIT_4_40_THEN_SEXT_mm_ETC___d637 ; assign MUX_mmioPlatform_curReq$write_1__VAL_1 = (!mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 && - mmioPlatform_mtimecmp_0 != 64'd0) ? + mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357) ? 67'h1AAAAAAAAAAAAAAAA : ((core_0$mmioToPlatform_cRq_first[141:81] >= 61'd4194304 && core_0$mmioToPlatform_cRq_first[141:81] < 61'd4194305) ? @@ -3951,7 +3950,7 @@ module mkProc(CLK, ((core_0$mmioToPlatform_cRq_first[141:81] == 61'd4200447) ? 67'h4AAAAAAAAAAAAAAAA : - IF_core_0_mmioToPlatform_cRq_first__82_BITS_14_ETC___d405))) ; + IF_core_0_mmioToPlatform_cRq_first__78_BITS_14_ETC___d401))) ; assign MUX_mmioPlatform_curReq$write_1__VAL_2 = { 3'd7, mmioPlatform_instSel ? @@ -3964,12 +3963,11 @@ module mkProc(CLK, mmioPlatform_instSel + 1'd1 ; assign MUX_mmioPlatform_mtime$write_1__VAL_2 = mmioPlatform_mtime + 64'd1 ; assign MUX_mmioPlatform_mtip_0$write_1__VAL_2 = - IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 && + IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && !mmioPlatform_mtip_0 ; assign MUX_mmioPlatform_state$write_1__VAL_1 = (!mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 && - mmioPlatform_mtimecmp_0 != 64'd0) ? + mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357) ? 2'd3 : 2'd2 ; assign MUX_mmioPlatform_state$write_1__VAL_2 = @@ -3980,32 +3978,32 @@ module mkProc(CLK, (mmioPlatform_reqBE[0] ? 2'd3 : 2'd1) : 2'd3) ; always@(mmioPlatform_reqFunc or - IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 or + IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 or mmioPlatform_mtip_0) begin case (mmioPlatform_reqFunc[5:4]) 2'd0: MUX_mmioPlatform_state$write_1__VAL_3 = 2'd1; 2'd1: MUX_mmioPlatform_state$write_1__VAL_3 = mmioPlatform_reqFunc[5:4]; default: MUX_mmioPlatform_state$write_1__VAL_3 = - (IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 && + (IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && !mmioPlatform_mtip_0 || - !IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 && + !IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && mmioPlatform_mtip_0) ? 2'd3 : 2'd1; endcase end always@(mmioPlatform_reqFunc or - mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 or + mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 or mmioPlatform_mtip_0) begin case (mmioPlatform_reqFunc[5:4]) 2'd0: MUX_mmioPlatform_state$write_1__VAL_4 = 2'd1; 2'd1: MUX_mmioPlatform_state$write_1__VAL_4 = mmioPlatform_reqFunc[5:4]; default: MUX_mmioPlatform_state$write_1__VAL_4 = - (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && + (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && + !mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && mmioPlatform_mtip_0) ? 2'd3 : 2'd1; @@ -4013,29 +4011,29 @@ module mkProc(CLK, end assign MUX_mmioPlatform_state$write_1__VAL_5 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] ? - (mmioPlatform_fetchingWay_73_ULT_mmioPlatform_r_ETC___d983 ? + (mmioPlatform_fetchingWay_69_ULT_mmioPlatform_r_ETC___d979 ? 2'd2 : 2'd1) : 2'd1 ; assign MUX_mmioPlatform_waitMTIPCRs$write_1__VAL_2 = - mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && + mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && + !mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && mmioPlatform_mtip_0 ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_1 = { mmioPlatform_curReq[63:0], 6'd42, mmioPlatform_reqBE, - x__h48018 } ; + x__h48002 } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_2 = { mmioPlatform_curReq[63:0], - IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_ETC___d481, + IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d477, mmioPlatform_reqBE, mmioPlatform_reqData } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_3 = { mmioPlatform_curReq[63:0], 78'h1AAAAAAAAAAAAAAAAAAA } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_4 = - { x__h50130, 78'h1AAAAAAAAAAAAAAAAAAA } ; + { x__h50114, 78'h1AAAAAAAAAAAAAAAAAAA } ; assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_1 = { 1'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[141:78] } ; assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_3 = @@ -4043,47 +4041,47 @@ module mkProc(CLK, mmio_axi4_adapter_master_xactor_rg_rd_data[66:3] } ; // inlined wires - assign mmioPlatform_toHostQ_enqReq_lat_0$wget = { 1'd1, x__h42876 } ; + assign mmioPlatform_toHostQ_enqReq_lat_0$wget = { 1'd1, x__h42860 } ; assign mmioPlatform_toHostQ_enqReq_lat_0$whas = WILL_FIRE_RL_mmioPlatform_processToHost && mmioPlatform_reqFunc[5:4] == 2'd2 && mmioPlatform_toHostQ_empty && - x__h42876 != 64'd0 ; + x__h42860 != 64'd0 ; assign mmioPlatform_fromHostQ_deqReq_lat_0$whas = WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && !mmioPlatform_fromHostQ_empty && - x__h40783 == 64'd0 ; + x__h40767 == 64'd0 ; assign propDstIdx_0_lat_1$whas = - NOT_enqDst_0_dummy2_0_read__087_088_OR_NOT_enq_ETC___d1103 && - IF_SEL_ARR_propDstIdx_0_dummy2_1_read__066_AND_ETC___d1173 ; + NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 && + IF_SEL_ARR_propDstIdx_0_dummy2_1_read__062_AND_ETC___d1169 ; assign propDstIdx_1_lat_1$whas = - NOT_enqDst_0_dummy2_0_read__087_088_OR_NOT_enq_ETC___d1103 && - x__h61422 ; + NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 && + x__h61406 ; assign propDstData_0_lat_0$wget = { core_0$dCacheToParent_rqToP_first, 1'd0 } ; assign propDstData_1_lat_0$wget = { core_0$iCacheToParent_rqToP_first, 1'd1 } ; assign enqDst_0_lat_0$wget = { 1'd1, - CASE_x1422_0_n__read_addr1604_1_n__read_addr16_ETC__q15, - SEL_ARR_IF_propDstData_0_dummy2_1_read__104_TH_ETC___d1168 } ; + CASE_x1406_0_n__read_addr1588_1_n__read_addr16_ETC__q15, + SEL_ARR_IF_propDstData_0_dummy2_1_read__100_TH_ETC___d1164 } ; assign propDstIdx_1_0_lat_1$whas = - NOT_enqDst_1_0_dummy2_0_read__361_362_OR_NOT_e_ETC___d1377 && - IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__330_A_ETC___d1475 ; + NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 && + IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__326_A_ETC___d1471 ; assign propDstIdx_1_1_lat_1$whas = - NOT_enqDst_1_0_dummy2_0_read__361_362_OR_NOT_e_ETC___d1377 && - x__h80307 ; + NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 && + x__h80291 ; assign propDstData_1_0_lat_0$wget = { core_0$dCacheToParent_rsToP_first, 1'd0 } ; assign propDstData_1_1_lat_0$wget = { core_0$iCacheToParent_rsToP_first, 1'd1 } ; assign enqDst_1_0_lat_0$wget = { 1'd1, - CASE_x0307_0_n__read_addr0485_1_n__read_addr05_ETC__q26, - SEL_ARR_IF_propDstData_1_0_dummy2_1_read__378__ETC___d1470 } ; + CASE_x0291_0_n__read_addr0469_1_n__read_addr05_ETC__q26, + SEL_ARR_IF_propDstData_1_0_dummy2_1_read__374__ETC___d1466 } ; assign llc_mem_server_enqDst_0_lat_0$wget = - { 1'd1, n__read_snd_addr__h124056, n__read_snd_id__h124057 } ; + { 1'd1, n__read_snd_addr__h124040, n__read_snd_id__h124041 } ; assign mmio_axi4_adapter_master_xactor_crg_wr_addr_full$EN_port1__write = mmio_axi4_adapter_master_xactor_crg_wr_addr_full && master1_awready ; @@ -4197,11 +4195,11 @@ module mkProc(CLK, assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 = llc_axi4_adapter_ctr_wr_rsps_pending_crg + 4'd1 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 = - b__h134531 - 4'd1 ; + b__h134515 - 4'd1 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read = CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp ? llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 : - b__h134531 ; + b__h134515 ; // register cfg_verbosity assign cfg_verbosity$D_IN = set_verbosity_verbosity ; @@ -4210,10 +4208,10 @@ module mkProc(CLK, // register enqDst_0_rl assign enqDst_0_rl$D_IN = { !CAN_FIRE_RL_doEnq && - IF_enqDst_0_lat_0_whas__042_THEN_enqDst_0_lat__ETC___d1047, + IF_enqDst_0_lat_0_whas__038_THEN_enqDst_0_lat__ETC___d1043, CAN_FIRE_RL_doEnq ? 73'h0AAAAAAAAAAAAAAAAAA : - (NOT_enqDst_0_dummy2_0_read__087_088_OR_NOT_enq_ETC___d1103 ? + (NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 ? enqDst_0_lat_0$wget[72:0] : enqDst_0_rl[72:0]) } ; assign enqDst_0_rl$EN = 1'd1 ; @@ -4221,8 +4219,8 @@ module mkProc(CLK, // register enqDst_1_0_rl assign enqDst_1_0_rl$D_IN = { !CAN_FIRE_RL_doEnq_1 && - IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1283, - IF_enqDst_1_0_lat_1_whas__275_THEN_enqDst_1_0__ETC___d1322 } ; + IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1279, + IF_enqDst_1_0_lat_1_whas__271_THEN_enqDst_1_0__ETC___d1318 } ; assign enqDst_1_0_rl$EN = 1'd1 ; // register llc_axi4_adapter_cfg_verbosity @@ -4261,7 +4259,7 @@ module mkProc(CLK, // register llc_axi4_adapter_master_xactor_rg_rd_addr assign llc_axi4_adapter_master_xactor_rg_rd_addr$D_IN = - { 4'd0, mem_req_rd_addr_araddr__h134824, 29'd851968 } ; + { 4'd0, mem_req_rd_addr_araddr__h134808, 29'd851968 } ; assign llc_axi4_adapter_master_xactor_rg_rd_addr$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ; @@ -4272,13 +4270,13 @@ module mkProc(CLK, // register llc_axi4_adapter_master_xactor_rg_wr_addr assign llc_axi4_adapter_master_xactor_rg_wr_addr$D_IN = - { 4'd0, mem_req_wr_addr_awaddr__h148748, 29'd851968 } ; + { 4'd0, mem_req_wr_addr_awaddr__h148732, 29'd851968 } ; assign llc_axi4_adapter_master_xactor_rg_wr_addr$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ; // register llc_axi4_adapter_master_xactor_rg_wr_data assign llc_axi4_adapter_master_xactor_rg_wr_data$D_IN = - { data64__h148663, strb8__h148664, 1'd1 } ; + { data64__h148647, strb8__h148648, 1'd1 } ; assign llc_axi4_adapter_master_xactor_rg_wr_data$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ; @@ -4290,7 +4288,7 @@ module mkProc(CLK, !llc_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read ; // register llc_axi4_adapter_rg_cline - assign llc_axi4_adapter_rg_cline$D_IN = new_cline__h135526 ; + assign llc_axi4_adapter_rg_cline$D_IN = new_cline__h135510 ; assign llc_axi4_adapter_rg_cline$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps ; @@ -4321,10 +4319,10 @@ module mkProc(CLK, // register llc_mem_server_enqDst_0_rl assign llc_mem_server_enqDst_0_rl$D_IN = { !CAN_FIRE_RL_llc_mem_server_doEnq && - IF_llc_mem_server_enqDst_0_lat_0_whas__680_THE_ETC___d1685, + IF_llc_mem_server_enqDst_0_lat_0_whas__676_THE_ETC___d1681, CAN_FIRE_RL_llc_mem_server_doEnq ? 65'h0AAAAAAAAAAAAAAAA : - (NOT_llc_mem_server_enqDst_0_dummy2_0_read__711_ETC___d1718 ? + (NOT_llc_mem_server_enqDst_0_dummy2_0_read__707_ETC___d1714 ? llc_mem_server_enqDst_0_lat_0$wget[64:0] : llc_mem_server_enqDst_0_rl[64:0]) } ; assign llc_mem_server_enqDst_0_rl$EN = 1'd1 ; @@ -4338,15 +4336,15 @@ module mkProc(CLK, // register llc_mem_server_propDstIdx_0_rl assign llc_mem_server_propDstIdx_0_rl$D_IN = - !NOT_llc_mem_server_enqDst_0_dummy2_0_read__711_ETC___d1718 && - IF_llc_mem_server_propDstIdx_0_lat_0_whas__665_ETC___d1668 ; + !NOT_llc_mem_server_enqDst_0_dummy2_0_read__707_ETC___d1714 && + IF_llc_mem_server_propDstIdx_0_lat_0_whas__661_ETC___d1664 ; assign llc_mem_server_propDstIdx_0_rl$EN = 1'd1 ; // register llc_mem_server_rg_cacheline_cache_addr assign llc_mem_server_rg_cacheline_cache_addr$D_IN = WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ? - line_addr__h102529 : - line_addr__h102615 ; + line_addr__h102513 : + line_addr__h102599 ; assign llc_mem_server_rg_cacheline_cache_addr$EN = WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st || WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld ; @@ -4417,11 +4415,10 @@ module mkProc(CLK, MUX_mmioPlatform_curReq$write_1__VAL_1 : MUX_mmioPlatform_curReq$write_1__VAL_2 ; assign mmioPlatform_curReq$EN = - WILL_FIRE_RL_mmioPlatform_selectReq && - NOT_mmioPlatform_mtip_0_55_64_AND_mmioPlatform_ETC___d379 || + MUX_mmioPlatform_curReq$write_1__SEL_1 || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] && - mmioPlatform_fetchingWay_73_ULT_mmioPlatform_r_ETC___d983 ; + mmioPlatform_fetchingWay_69_ULT_mmioPlatform_r_ETC___d979 ; // register mmioPlatform_cycle assign mmioPlatform_cycle$D_IN = @@ -4434,11 +4431,11 @@ module mkProc(CLK, // register mmioPlatform_fetchedInsts_0 assign mmioPlatform_fetchedInsts_0$D_IN = - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d991 ; + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d987 ; assign mmioPlatform_fetchedInsts_0$EN = WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] && - mmioPlatform_fetchingWay_73_ULT_mmioPlatform_r_ETC___d983 && + mmioPlatform_fetchingWay_69_ULT_mmioPlatform_r_ETC___d979 && !mmioPlatform_fetchingWay ; // register mmioPlatform_fetchingWay @@ -4447,10 +4444,12 @@ module mkProc(CLK, MUX_mmioPlatform_fetchingWay$write_1__VAL_2 ; assign mmioPlatform_fetchingWay$EN = WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_55_OR_NOT_mmioPlatform_mti_ETC___d410 || + (mmioPlatform_mtip_0 || + !mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357) && + core_0$mmioToPlatform_cRq_notEmpty || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] && - mmioPlatform_fetchingWay_73_ULT_mmioPlatform_r_ETC___d983 ; + mmioPlatform_fetchingWay_69_ULT_mmioPlatform_r_ETC___d979 ; // register mmioPlatform_fromHostAddr assign mmioPlatform_fromHostAddr$D_IN = start_fromhostAddr[63:3] ; @@ -4496,15 +4495,17 @@ module mkProc(CLK, MUX_mmioPlatform_instSel$write_1__VAL_2 ; assign mmioPlatform_instSel$EN = WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_55_OR_NOT_mmioPlatform_mti_ETC___d410 || + (mmioPlatform_mtip_0 || + !mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357) && + core_0$mmioToPlatform_cRq_notEmpty || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] && - mmioPlatform_fetchingWay_73_ULT_mmioPlatform_r_ETC___d983 ; + mmioPlatform_fetchingWay_69_ULT_mmioPlatform_r_ETC___d979 ; // register mmioPlatform_mtime assign mmioPlatform_mtime$D_IN = MUX_mmioPlatform_amoResp$write_1__SEL_2 ? - newData__h34757 : + newData__h34741 : MUX_mmioPlatform_mtime$write_1__VAL_2 ; assign mmioPlatform_mtime$EN = WILL_FIRE_RL_mmioPlatform_processMTime && @@ -4513,7 +4514,7 @@ module mkProc(CLK, WILL_FIRE_RL_mmioPlatform_incTime ; // register mmioPlatform_mtimecmp_0 - assign mmioPlatform_mtimecmp_0$D_IN = newData__h31827 ; + assign mmioPlatform_mtimecmp_0$D_IN = newData__h31811 ; assign mmioPlatform_mtimecmp_0$EN = MUX_mmioPlatform_amoResp$write_1__SEL_1 ; @@ -4523,10 +4524,9 @@ module mkProc(CLK, MUX_mmioPlatform_mtip_0$write_1__VAL_2 ; assign mmioPlatform_mtip_0$EN = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 && - mmioPlatform_mtimecmp_0 != 64'd0 || + mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 || WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d585 ; + NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d581 ; // register mmioPlatform_reqAmofunc assign mmioPlatform_reqAmofunc$D_IN = @@ -4596,8 +4596,7 @@ module mkProc(CLK, endcase end assign mmioPlatform_state$EN = - WILL_FIRE_RL_mmioPlatform_selectReq && - NOT_mmioPlatform_mtip_0_55_64_AND_mmioPlatform_ETC___d379 || + MUX_mmioPlatform_curReq$write_1__SEL_1 || WILL_FIRE_RL_mmioPlatform_processMSIP || WILL_FIRE_RL_mmioPlatform_processMTimeCmp || WILL_FIRE_RL_mmioPlatform_processMTime || @@ -4661,7 +4660,7 @@ module mkProc(CLK, mmioPlatform_reqBE[0] ; assign mmioPlatform_waitLowerMSIPCRs$EN = WILL_FIRE_RL_mmioPlatform_processMSIP && - NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d490 ; + NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d486 ; // register mmioPlatform_waitMTIPCRs assign mmioPlatform_waitMTIPCRs$D_IN = @@ -4669,16 +4668,15 @@ module mkProc(CLK, MUX_mmioPlatform_waitMTIPCRs$write_1__VAL_2 ; assign mmioPlatform_waitMTIPCRs$EN = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 && - mmioPlatform_mtimecmp_0 != 64'd0 || + mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 || WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d648 ; + NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d644 ; // register mmioPlatform_waitUpperMSIPCRs assign mmioPlatform_waitUpperMSIPCRs$D_IN = 1'd0 ; assign mmioPlatform_waitUpperMSIPCRs$EN = WILL_FIRE_RL_mmioPlatform_processMSIP && - NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d490 ; + NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d486 ; // register mmio_axi4_adapter_cfg_verbosity assign mmio_axi4_adapter_cfg_verbosity$D_IN = 4'h0 ; @@ -4764,28 +4762,28 @@ module mkProc(CLK, // register propDstData_1_0_rl assign propDstData_1_0_rl$D_IN = - { IF_propDstData_1_0_lat_0_whas__202_THEN_propDs_ETC___d1207, - IF_propDstData_1_0_lat_0_whas__202_THEN_propDs_ETC___d1212, + { IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1203, + IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1208, CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[513] : propDstData_1_0_rl[513], CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[512:1] : propDstData_1_0_rl[512:1], - IF_propDstData_1_0_lat_0_whas__202_THEN_propDs_ETC___d1233 } ; + IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1229 } ; assign propDstData_1_0_rl$EN = 1'd1 ; // register propDstData_1_1_rl assign propDstData_1_1_rl$D_IN = - { IF_propDstData_1_1_lat_0_whas__240_THEN_propDs_ETC___d1245, - IF_propDstData_1_1_lat_0_whas__240_THEN_propDs_ETC___d1250, + { IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1241, + IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1246, CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[513] : propDstData_1_1_rl[513], CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[512:1] : propDstData_1_1_rl[512:1], - IF_propDstData_1_1_lat_0_whas__240_THEN_propDs_ETC___d1271 } ; + IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1267 } ; assign propDstData_1_1_rl$EN = 1'd1 ; // register propDstData_1_rl @@ -4798,36 +4796,36 @@ module mkProc(CLK, // register propDstIdx_0_rl assign propDstIdx_0_rl$D_IN = !propDstIdx_0_lat_1$whas && - IF_propDstIdx_0_lat_0_whas__013_THEN_propDstId_ETC___d1016 ; + IF_propDstIdx_0_lat_0_whas__009_THEN_propDstId_ETC___d1012 ; assign propDstIdx_0_rl$EN = 1'd1 ; // register propDstIdx_1_0_rl assign propDstIdx_1_0_rl$D_IN = !propDstIdx_1_0_lat_1$whas && - IF_propDstIdx_1_0_lat_0_whas__187_THEN_propDst_ETC___d1190 ; + IF_propDstIdx_1_0_lat_0_whas__183_THEN_propDst_ETC___d1186 ; assign propDstIdx_1_0_rl$EN = 1'd1 ; // register propDstIdx_1_1_rl assign propDstIdx_1_1_rl$D_IN = !propDstIdx_1_1_lat_1$whas && - IF_propDstIdx_1_1_lat_0_whas__194_THEN_propDst_ETC___d1197 ; + IF_propDstIdx_1_1_lat_0_whas__190_THEN_propDst_ETC___d1193 ; assign propDstIdx_1_1_rl$EN = 1'd1 ; // register propDstIdx_1_rl assign propDstIdx_1_rl$D_IN = !propDstIdx_1_lat_1$whas && - IF_propDstIdx_1_lat_0_whas__020_THEN_propDstId_ETC___d1023 ; + IF_propDstIdx_1_lat_0_whas__016_THEN_propDstId_ETC___d1019 ; assign propDstIdx_1_rl$EN = 1'd1 ; // register srcRR_0 assign srcRR_0$D_IN = srcRR_0 + 1'd1 ; assign srcRR_0$EN = - NOT_enqDst_0_dummy2_0_read__087_088_OR_NOT_enq_ETC___d1103 ; + NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 ; // register srcRR_1_0 assign srcRR_1_0$D_IN = srcRR_1_0 + 1'd1 ; assign srcRR_1_0$EN = - NOT_enqDst_1_0_dummy2_0_read__361_362_OR_NOT_e_ETC___d1377 ; + NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 ; // submodule core_0 assign core_0$coreReq_perfReq_loc = 4'h0 ; @@ -4928,7 +4926,7 @@ module mkProc(CLK, assign core_0$setMEIP_v = m_external_interrupt_req_set_not_clear ; assign core_0$setSEIP_v = s_external_interrupt_req_set_not_clear ; assign core_0$tlbToMem_respLd_enq_x = - { ld_data__h132752, llc$dma_respLd_first[3] } ; + { ld_data__h132736, llc$dma_respLd_first[3] } ; assign core_0$EN_coreReq_start = EN_start ; assign core_0$EN_coreReq_perfReq = 1'b0 ; assign core_0$EN_coreIndInv_perfResp = 1'b0 ; @@ -4949,13 +4947,13 @@ module mkProc(CLK, MUX_mmioPlatform_fetchingWay$write_1__SEL_1 ; assign core_0$EN_mmioToPlatform_pRs_enq = WILL_FIRE_RL_mmioPlatform_processMSIP && - mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d467 || + mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d463 || WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d571 || + mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d567 || WILL_FIRE_RL_mmioPlatform_processMTime && - mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d636 || + mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d632 || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && - (!mmioPlatform_fetchingWay_73_ULT_mmioPlatform_r_ETC___d983 || + (!mmioPlatform_fetchingWay_69_ULT_mmioPlatform_r_ETC___d979 || !mmio_axi4_adapter_f_rsps_to_core$D_OUT[64]) || WILL_FIRE_RL_mmioPlatform_waitMTimeDone || WILL_FIRE_RL_mmioPlatform_waitMTimeCmpDone || @@ -4966,16 +4964,15 @@ module mkProc(CLK, WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp ; assign core_0$EN_mmioToPlatform_pRq_enq = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 && - mmioPlatform_mtimecmp_0 != 64'd0 || + mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 || WILL_FIRE_RL_mmioPlatform_processMSIP && mmioPlatform_reqFunc[5:4] != 2'd0 && !mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0] || WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d585 || + NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d581 || WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d648 ; + NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d644 ; assign core_0$EN_mmioToPlatform_cRs_deq = (WILL_FIRE_RL_mmioPlatform_waitMTimeDone || WILL_FIRE_RL_mmioPlatform_waitTimerInterruptDone) && @@ -5014,7 +5011,7 @@ module mkProc(CLK, // submodule enqDst_0_dummy2_0 assign enqDst_0_dummy2_0$D_IN = 1'd1 ; assign enqDst_0_dummy2_0$EN = - NOT_enqDst_0_dummy2_0_read__087_088_OR_NOT_enq_ETC___d1103 ; + NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 ; // submodule enqDst_0_dummy2_1 assign enqDst_0_dummy2_1$D_IN = 1'd1 ; @@ -5023,7 +5020,7 @@ module mkProc(CLK, // submodule enqDst_1_0_dummy2_0 assign enqDst_1_0_dummy2_0$D_IN = 1'd1 ; assign enqDst_1_0_dummy2_0$EN = - NOT_enqDst_1_0_dummy2_0_read__361_362_OR_NOT_e_ETC___d1377 ; + NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 ; // submodule enqDst_1_0_dummy2_1 assign enqDst_1_0_dummy2_1$D_IN = 1'd1 ; @@ -5055,17 +5052,17 @@ module mkProc(CLK, assign llc$perf_req_r = 4'h0 ; assign llc$perf_setStatus_doStats = core_0$sendDoStats ; assign llc$to_child_rqFromC_enq_x = - NOT_enqDst_0_dummy2_0_read__087_088_OR_NOT_enq_ETC___d1103 ? + NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 ? enqDst_0_lat_0$wget[72:0] : enqDst_0_rl[72:0] ; assign llc$to_child_rsFromC_enq_x = - { IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1293, - IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1298, - IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1303, - IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1313, - IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1319 } ; + { IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1289, + IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1294, + IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1299, + IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1309, + IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1315 } ; assign llc$to_mem_rsFromM_enq_x = - { new_cline__h135526, + { new_cline__h135510, llc_axi4_adapter_f_pending_reads$D_OUT[4:0] } ; assign llc$EN_to_child_rsFromC_enq = CAN_FIRE_RL_doEnq_1 ; assign llc$EN_to_child_rqFromC_enq = CAN_FIRE_RL_doEnq ; @@ -5141,7 +5138,7 @@ module mkProc(CLK, // submodule llc_mem_server_axi4_slave_xactor_f_rd_data assign llc_mem_server_axi4_slave_xactor_f_rd_data$D_IN = - { 4'd0, dword__h94465, 3'd1 } ; + { 4'd0, dword__h94449, 3'd1 } ; assign llc_mem_server_axi4_slave_xactor_f_rd_data$ENQ = CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req ; assign llc_mem_server_axi4_slave_xactor_f_rd_data$DEQ = @@ -5192,7 +5189,7 @@ module mkProc(CLK, // submodule llc_mem_server_enqDst_0_dummy2_0 assign llc_mem_server_enqDst_0_dummy2_0$D_IN = 1'd1 ; assign llc_mem_server_enqDst_0_dummy2_0$EN = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__711_ETC___d1718 ; + NOT_llc_mem_server_enqDst_0_dummy2_0_read__707_ETC___d1714 ; // submodule llc_mem_server_enqDst_0_dummy2_1 assign llc_mem_server_enqDst_0_dummy2_1$D_IN = 1'd1 ; @@ -5222,11 +5219,11 @@ module mkProc(CLK, // submodule llc_mem_server_propDstIdx_0_dummy2_1 assign llc_mem_server_propDstIdx_0_dummy2_1$D_IN = 1'd1 ; assign llc_mem_server_propDstIdx_0_dummy2_1$EN = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__711_ETC___d1718 ; + NOT_llc_mem_server_enqDst_0_dummy2_0_read__707_ETC___d1714 ; // submodule llc_mem_server_tlbQ assign llc_mem_server_tlbQ$D_IN = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__711_ETC___d1718 ? + NOT_llc_mem_server_enqDst_0_dummy2_0_read__707_ETC___d1714 ? llc_mem_server_enqDst_0_lat_0$wget[64:0] : llc_mem_server_enqDst_0_rl[64:0] ; assign llc_mem_server_tlbQ$ENQ = CAN_FIRE_RL_llc_mem_server_doEnq ; @@ -5444,86 +5441,86 @@ module mkProc(CLK, // remaining internal signals module_amoExec instance_amoExec_0(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h29914 && - mmioPlatform_reqBE_BIT_0___h29954, + mmioPlatform_reqBE_BIT_4___h29898 && + mmioPlatform_reqBE_BIT_0___h29938, 2'd0 }), - .amoExec_current_data(x__h37208), - .amoExec_in_data(mmioPlatform_reqData__h48614), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h29914 && - !mmioPlatform_reqBE_BIT_0___h29954), - .amoExec(x__h31938)); + .amoExec_current_data(x__h37192), + .amoExec_in_data(mmioPlatform_reqData__h48598), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h29898 && + !mmioPlatform_reqBE_BIT_0___h29938), + .amoExec(x__h31922)); module_amoExec instance_amoExec_1(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h29914 && - mmioPlatform_reqBE_BIT_0___h29954, + mmioPlatform_reqBE_BIT_4___h29898 && + mmioPlatform_reqBE_BIT_0___h29938, 2'd0 }), - .amoExec_current_data(mmioPlatform_mtime__h37060), - .amoExec_in_data(mmioPlatform_reqData__h48614), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h29914 && - !mmioPlatform_reqBE_BIT_0___h29954), - .amoExec(x__h34848)); + .amoExec_current_data(mmioPlatform_mtime__h37044), + .amoExec_in_data(mmioPlatform_reqData__h48598), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h29898 && + !mmioPlatform_reqBE_BIT_0___h29938), + .amoExec(x__h34832)); module_amoExec instance_amoExec_2(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h29914 && - mmioPlatform_reqBE_BIT_0___h29954, + mmioPlatform_reqBE_BIT_4___h29898 && + mmioPlatform_reqBE_BIT_0___h29938, 2'd0 }), - .amoExec_current_data(mmioPlatform_fromHostQ_data_0__h42593), - .amoExec_in_data(mmioPlatform_reqData__h48614), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h29914 && - !mmioPlatform_reqBE_BIT_0___h29954), - .amoExec(x__h40794)); + .amoExec_current_data(mmioPlatform_fromHostQ_data_0__h42577), + .amoExec_in_data(mmioPlatform_reqData__h48598), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h29898 && + !mmioPlatform_reqBE_BIT_0___h29938), + .amoExec(x__h40778)); module_amoExec instance_amoExec_3(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h29914 && - mmioPlatform_reqBE_BIT_0___h29954, + mmioPlatform_reqBE_BIT_4___h29898 && + mmioPlatform_reqBE_BIT_0___h29938, 2'd0 }), .amoExec_current_data(64'd0), - .amoExec_in_data(mmioPlatform_reqData__h48614), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h29914 && - !mmioPlatform_reqBE_BIT_0___h29954), - .amoExec(x__h42887)); - assign DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_40_BIT_ETC___d684 = + .amoExec_in_data(mmioPlatform_reqData__h48598), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h29898 && + !mmioPlatform_reqBE_BIT_0___h29938), + .amoExec(x__h42871)); + assign DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_36_BIT_ETC___d680 = { 1'h0, (mmioPlatform_reqFunc[5:4] == 2'd2) ? { mmioPlatform_toHostQ_empty, 64'hAAAAAAAAAAAAAAAA } : { mmioPlatform_reqFunc[5:4] == 2'd1, - x1_avValue_data__h40265 } } ; - assign IF_IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4__ETC___d559 = - (IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 && + x1_avValue_data__h40249 } } ; + assign IF_IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4__ETC___d555 = + (IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && !mmioPlatform_mtip_0 || - !IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 && + !IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && mmioPlatform_mtip_0) ? core_0$RDY_mmioToPlatform_pRq_enq : core_0$RDY_mmioToPlatform_pRs_enq ; - assign IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d456 = + assign IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d452 = (mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? (mmioPlatform_reqBE[0] ? core_0$RDY_mmioToPlatform_pRq_enq : core_0$RDY_mmioToPlatform_pRs_enq) : !mmioPlatform_reqBE[0] || core_0$RDY_mmioToPlatform_pRq_enq ; - assign IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 = - newData__h31827 <= mmioPlatform_mtime ; - assign IF_NOT_propDstIdx_0_dummy2_1_read__066_067_OR__ETC___d1101 = - NOT_propDstIdx_0_dummy2_1_read__066_067_OR_IF__ETC___d1100 ? + assign IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 = + newData__h31811 <= mmioPlatform_mtime ; + assign IF_NOT_propDstIdx_0_dummy2_1_read__062_063_OR__ETC___d1097 = + NOT_propDstIdx_0_dummy2_1_read__062_063_OR_IF__ETC___d1096 ? propDstIdx_1_dummy2_1$Q_OUT && - IF_propDstIdx_1_lat_0_whas__020_THEN_propDstId_ETC___d1023 : + IF_propDstIdx_1_lat_0_whas__016_THEN_propDstId_ETC___d1019 : propDstIdx_0_dummy2_1$Q_OUT && - IF_propDstIdx_0_lat_0_whas__013_THEN_propDstId_ETC___d1016 ; - assign IF_NOT_propDstIdx_1_0_dummy2_1_read__330_331_O_ETC___d1375 = - NOT_propDstIdx_1_0_dummy2_1_read__330_331_OR_I_ETC___d1374 ? + IF_propDstIdx_0_lat_0_whas__009_THEN_propDstId_ETC___d1012 ; + assign IF_NOT_propDstIdx_1_0_dummy2_1_read__326_327_O_ETC___d1371 = + NOT_propDstIdx_1_0_dummy2_1_read__326_327_OR_I_ETC___d1370 ? propDstIdx_1_1_dummy2_1$Q_OUT && - IF_propDstIdx_1_1_lat_0_whas__194_THEN_propDst_ETC___d1197 : + IF_propDstIdx_1_1_lat_0_whas__190_THEN_propDst_ETC___d1193 : propDstIdx_1_0_dummy2_1$Q_OUT && - IF_propDstIdx_1_0_lat_0_whas__187_THEN_propDst_ETC___d1190 ; - assign IF_SEL_ARR_propDstIdx_0_dummy2_1_read__066_AND_ETC___d1173 = - SEL_ARR_propDstIdx_0_dummy2_1_read__066_AND_IF_ETC___d1097 ? + IF_propDstIdx_1_0_lat_0_whas__183_THEN_propDst_ETC___d1186 ; + assign IF_SEL_ARR_propDstIdx_0_dummy2_1_read__062_AND_ETC___d1169 = + SEL_ARR_propDstIdx_0_dummy2_1_read__062_AND_IF_ETC___d1093 ? !srcRR_0 : propDstIdx_0_dummy2_1$Q_OUT && - IF_propDstIdx_0_lat_0_whas__013_THEN_propDstId_ETC___d1016 ; - assign IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__330_A_ETC___d1475 = - SEL_ARR_propDstIdx_1_0_dummy2_1_read__330_AND__ETC___d1371 ? + IF_propDstIdx_0_lat_0_whas__009_THEN_propDstId_ETC___d1012 ; + assign IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__326_A_ETC___d1471 = + SEL_ARR_propDstIdx_1_0_dummy2_1_read__326_AND__ETC___d1367 ? !srcRR_1_0 : propDstIdx_1_0_dummy2_1$Q_OUT && - IF_propDstIdx_1_0_lat_0_whas__187_THEN_propDst_ETC___d1190 ; - assign IF_core_0_mmioToPlatform_cRq_first__82_BITS_14_ETC___d405 = + IF_propDstIdx_1_0_lat_0_whas__183_THEN_propDst_ETC___d1186 ; + assign IF_core_0_mmioToPlatform_cRq_first__78_BITS_14_ETC___d401 = (core_0$mmioToPlatform_cRq_first[141:81] == mmioPlatform_toHostAddr) ? 67'h5AAAAAAAAAAAAAAAA : @@ -5531,116 +5528,116 @@ module mkProc(CLK, mmioPlatform_fromHostAddr) ? 67'h6AAAAAAAAAAAAAAAA : { 3'd7, core_0$mmioToPlatform_cRq_first[141:78] }) ; - assign IF_enqDst_0_lat_0_whas__042_THEN_enqDst_0_lat__ETC___d1047 = - NOT_enqDst_0_dummy2_0_read__087_088_OR_NOT_enq_ETC___d1103 ? + assign IF_enqDst_0_lat_0_whas__038_THEN_enqDst_0_lat__ETC___d1043 = + NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 ? enqDst_0_lat_0$wget[73] : enqDst_0_rl[73] ; - assign IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1283 = - NOT_enqDst_1_0_dummy2_0_read__361_362_OR_NOT_e_ETC___d1377 ? + assign IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1279 = + NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 ? enqDst_1_0_lat_0$wget[580] : enqDst_1_0_rl[580] ; - assign IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1293 = - NOT_enqDst_1_0_dummy2_0_read__361_362_OR_NOT_e_ETC___d1377 ? + assign IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1289 = + NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 ? enqDst_1_0_lat_0$wget[579:516] : enqDst_1_0_rl[579:516] ; - assign IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1298 = - NOT_enqDst_1_0_dummy2_0_read__361_362_OR_NOT_e_ETC___d1377 ? + assign IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1294 = + NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 ? enqDst_1_0_lat_0$wget[515:514] : enqDst_1_0_rl[515:514] ; - assign IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1303 = - NOT_enqDst_1_0_dummy2_0_read__361_362_OR_NOT_e_ETC___d1377 ? + assign IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1299 = + NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 ? enqDst_1_0_lat_0$wget[513] : enqDst_1_0_rl[513] ; - assign IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1313 = - NOT_enqDst_1_0_dummy2_0_read__361_362_OR_NOT_e_ETC___d1377 ? + assign IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1309 = + NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 ? enqDst_1_0_lat_0$wget[512:1] : enqDst_1_0_rl[512:1] ; - assign IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1319 = - NOT_enqDst_1_0_dummy2_0_read__361_362_OR_NOT_e_ETC___d1377 ? + assign IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1315 = + NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 ? enqDst_1_0_lat_0$wget[0] : enqDst_1_0_rl[0] ; - assign IF_enqDst_1_0_lat_1_whas__275_THEN_enqDst_1_0__ETC___d1321 = + assign IF_enqDst_1_0_lat_1_whas__271_THEN_enqDst_1_0__ETC___d1317 = { CAN_FIRE_RL_doEnq_1 || - IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1303, + IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1299, CAN_FIRE_RL_doEnq_1 ? 512'h55555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555 : - IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1313, - x__h75236 } ; - assign IF_enqDst_1_0_lat_1_whas__275_THEN_enqDst_1_0__ETC___d1322 = + IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1309, + x__h75220 } ; + assign IF_enqDst_1_0_lat_1_whas__271_THEN_enqDst_1_0__ETC___d1318 = { CAN_FIRE_RL_doEnq_1 ? 64'hAAAAAAAAAAAAAAAA : - IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1293, + IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1289, CAN_FIRE_RL_doEnq_1 ? 2'b10 : - IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1298, - IF_enqDst_1_0_lat_1_whas__275_THEN_enqDst_1_0__ETC___d1321 } ; - assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1595 = + IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1294, + IF_enqDst_1_0_lat_1_whas__271_THEN_enqDst_1_0__ETC___d1317 } ; + assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1591 = { (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd7) ? - new_dword__h90156 : + new_dword__h90140 : llc_mem_server_rg_cacheline_cache_data[511:448], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd6) ? - new_dword__h90156 : + new_dword__h90140 : llc_mem_server_rg_cacheline_cache_data[447:384], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd5) ? - new_dword__h90156 : + new_dword__h90140 : llc_mem_server_rg_cacheline_cache_data[383:320], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd4) ? - new_dword__h90156 : + new_dword__h90140 : llc_mem_server_rg_cacheline_cache_data[319:256] } ; - assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1600 = - { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1595, + assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1596 = + { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1591, (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd3) ? - new_dword__h90156 : + new_dword__h90140 : llc_mem_server_rg_cacheline_cache_data[255:192], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd2) ? - new_dword__h90156 : + new_dword__h90140 : llc_mem_server_rg_cacheline_cache_data[191:128] } ; - assign IF_llc_mem_server_enqDst_0_lat_0_whas__680_THE_ETC___d1685 = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__711_ETC___d1718 ? + assign IF_llc_mem_server_enqDst_0_lat_0_whas__676_THE_ETC___d1681 = + NOT_llc_mem_server_enqDst_0_dummy2_0_read__707_ETC___d1714 ? llc_mem_server_enqDst_0_lat_0$wget[65] : llc_mem_server_enqDst_0_rl[65] ; - assign IF_llc_mem_server_propDstIdx_0_lat_0_whas__665_ETC___d1668 = + assign IF_llc_mem_server_propDstIdx_0_lat_0_whas__661_ETC___d1664 = CAN_FIRE_RL_llc_mem_server_srcPropose || llc_mem_server_propDstIdx_0_rl ; - assign IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d833 = + assign IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829 = (mmioPlatform_curReq[2:0] == 3'h0) ? mmioPlatform_reqData : 64'd0 ; - assign IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d884 = + assign IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d880 = (mmioPlatform_curReq[2:0] == 3'h0) ? mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:0] : 64'd0 ; - assign IF_mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioP_ETC___d625 = - ((mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && + assign IF_mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioP_ETC___d621 = + ((mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && !mmioPlatform_mtip_0) ? core_0$RDY_mmioToPlatform_pRq_enq : - mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 || + mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 || !mmioPlatform_mtip_0 || core_0$RDY_mmioToPlatform_pRq_enq) && - (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && + (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && + !mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && mmioPlatform_mtip_0 || core_0$RDY_mmioToPlatform_pRs_enq) ; - assign IF_mmioPlatform_reqBE_43_BIT_4_44_THEN_SEXT_mm_ETC___d577 = + assign IF_mmioPlatform_reqBE_39_BIT_4_40_THEN_SEXT_mm_ETC___d573 = mmioPlatform_reqBE[4] ? { {32{mmioPlatform_mtimecmp_0_BITS_63_TO_32__q1[31]}}, mmioPlatform_mtimecmp_0_BITS_63_TO_32__q1 } : { {32{mmioPlatform_mtimecmp_0_BITS_31_TO_0__q2[31]}}, mmioPlatform_mtimecmp_0_BITS_31_TO_0__q2 } ; - assign IF_mmioPlatform_reqBE_43_BIT_4_44_THEN_SEXT_mm_ETC___d641 = + assign IF_mmioPlatform_reqBE_39_BIT_4_40_THEN_SEXT_mm_ETC___d637 = mmioPlatform_reqBE[4] ? { {32{mmioPlatform_mtime_BITS_63_TO_32__q3[31]}}, mmioPlatform_mtime_BITS_63_TO_32__q3 } : { {32{mmioPlatform_mtime_BITS_31_TO_0__q4[31]}}, mmioPlatform_mtime_BITS_31_TO_0__q4 } ; - assign IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d535 = + assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d531 = { mmioPlatform_reqBE[7] ? mmioPlatform_reqData[63:56] : mmioPlatform_mtimecmp_0[63:56], @@ -5653,23 +5650,23 @@ module mkProc(CLK, mmioPlatform_reqBE[4] ? mmioPlatform_reqData[39:32] : mmioPlatform_mtimecmp_0[39:32] } ; - assign IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d544 = - { IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d535, + assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d540 = + { IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d531, mmioPlatform_reqBE[3] ? mmioPlatform_reqData[31:24] : mmioPlatform_mtimecmp_0[31:24], mmioPlatform_reqBE[2] ? mmioPlatform_reqData[23:16] : mmioPlatform_mtimecmp_0[23:16] } ; - assign IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d552 = - { IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d544, + assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d548 = + { IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d540, mmioPlatform_reqBE[1] ? mmioPlatform_reqData[15:8] : mmioPlatform_mtimecmp_0[15:8], mmioPlatform_reqBE[0] ? mmioPlatform_reqData[7:0] : mmioPlatform_mtimecmp_0[7:0] } ; - assign IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d604 = + assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d600 = { mmioPlatform_reqBE[7] ? mmioPlatform_reqData[63:56] : mmioPlatform_mtime[63:56], @@ -5682,23 +5679,23 @@ module mkProc(CLK, mmioPlatform_reqBE[4] ? mmioPlatform_reqData[39:32] : mmioPlatform_mtime[39:32] } ; - assign IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d609 = - { IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d604, + assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d605 = + { IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d600, mmioPlatform_reqBE[3] ? mmioPlatform_reqData[31:24] : mmioPlatform_mtime[31:24], mmioPlatform_reqBE[2] ? mmioPlatform_reqData[23:16] : mmioPlatform_mtime[23:16] } ; - assign IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d614 = - { IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d609, + assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d610 = + { IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d605, mmioPlatform_reqBE[1] ? mmioPlatform_reqData[15:8] : mmioPlatform_mtime[15:8], mmioPlatform_reqBE[0] ? mmioPlatform_reqData[7:0] : mmioPlatform_mtime[7:0] } ; - assign IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d708 = + assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d704 = { mmioPlatform_reqBE[7] ? mmioPlatform_reqData[63:56] : mmioPlatform_fromHostQ_data_0[63:56], @@ -5711,49 +5708,49 @@ module mkProc(CLK, mmioPlatform_reqBE[4] ? mmioPlatform_reqData[39:32] : mmioPlatform_fromHostQ_data_0[39:32] } ; - assign IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d713 = - { IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d708, + assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d709 = + { IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d704, mmioPlatform_reqBE[3] ? mmioPlatform_reqData[31:24] : mmioPlatform_fromHostQ_data_0[31:24], mmioPlatform_reqBE[2] ? mmioPlatform_reqData[23:16] : mmioPlatform_fromHostQ_data_0[23:16] } ; - assign IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d718 = - { IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d713, + assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d714 = + { IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d709, mmioPlatform_reqBE[1] ? mmioPlatform_reqData[15:8] : mmioPlatform_fromHostQ_data_0[15:8], mmioPlatform_reqBE[0] ? mmioPlatform_reqData[7:0] : mmioPlatform_fromHostQ_data_0[7:0] } ; - assign IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_ETC___d457 = + assign IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d453 = (mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqBE[4]) ? core_0$RDY_mmioToPlatform_pRs_enq : - IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d456 ; - assign IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_1_ETC___d578 = + IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d452 ; + assign IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_1_ETC___d574 = (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtimecmp_0 : - IF_mmioPlatform_reqBE_43_BIT_4_44_THEN_SEXT_mm_ETC___d577 ; - assign IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_1_ETC___d642 = + IF_mmioPlatform_reqBE_39_BIT_4_40_THEN_SEXT_mm_ETC___d573 ; + assign IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_1_ETC___d638 = (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtime : - IF_mmioPlatform_reqBE_43_BIT_4_44_THEN_SEXT_mm_ETC___d641 ; - assign IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_2_ETC___d726 = + IF_mmioPlatform_reqBE_39_BIT_4_40_THEN_SEXT_mm_ETC___d637 ; + assign IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_2_ETC___d722 = (mmioPlatform_reqFunc[5:4] == 2'd2) ? { mmioPlatform_fromHostQ_empty ? - x__h42876 == 64'd0 : - x__h40783 == 64'd0, + x__h42860 == 64'd0 : + x__h40767 == 64'd0, 64'hAAAAAAAAAAAAAAAA } : { mmioPlatform_reqFunc[5:4] == 2'd1, - x1_avValue_data__h44951 } ; + x1_avValue_data__h44935 } ; assign IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__91__ETC___d200 = mmioPlatform_toHostQ_enqReq_lat_0$whas ? mmioPlatform_toHostQ_enqReq_lat_0$wget[64] : mmioPlatform_toHostQ_enqReq_rl[64] ; - assign IF_mmioPlatform_waitLowerMSIPCRs_92_THEN_core__ETC___d500 = + assign IF_mmioPlatform_waitLowerMSIPCRs_88_THEN_core__ETC___d496 = mmioPlatform_waitLowerMSIPCRs ? core_0$RDY_mmioToPlatform_cRs_first && core_0$RDY_mmioToPlatform_cRs_deq : @@ -5761,99 +5758,99 @@ module mkProc(CLK, core_0$RDY_mmioToPlatform_cRs_first) && (!mmioPlatform_waitUpperMSIPCRs || core_0$RDY_mmioToPlatform_cRs_deq) ; - assign IF_mmio_axi4_adapter_f_rsps_to_core_first__64__ETC___d978 = + assign IF_mmio_axi4_adapter_f_rsps_to_core_first__60__ETC___d974 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] ? mmioPlatform_fetchingWay < (mmioPlatform_reqFunc[5:4] == 2'd0 && mmioPlatform_reqFunc[0]) || core_0$RDY_mmioToPlatform_pRs_enq : core_0$RDY_mmioToPlatform_pRs_enq ; - assign IF_mmio_axi4_adapter_f_rsps_to_core_first__64__ETC___d999 = + assign IF_mmio_axi4_adapter_f_rsps_to_core_first__60__ETC___d995 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] ? (mmioPlatform_fetchingWay ? mmioPlatform_fetchedInsts_0 : - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d991) : + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d987) : mmioPlatform_fetchedInsts_0 ; assign IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d103 = mmio_axi4_adapter_soc_map$m_is_IO_addr ? !mmio_axi4_adapter_master_xactor_crg_wr_addr_full$port2__read && !mmio_axi4_adapter_master_xactor_crg_wr_data_full$port2__read : mmio_axi4_adapter_f_rsps_to_core$FULL_N ; - assign IF_propDstData_0_dummy2_1_read__104_THEN_IF_pr_ETC___d1120 = + assign IF_propDstData_0_dummy2_1_read__100_THEN_IF_pr_ETC___d1116 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[8:7] : propDstData_0_rl[8:7]) : 2'd0 ; - assign IF_propDstData_0_dummy2_1_read__104_THEN_IF_pr_ETC___d1130 = + assign IF_propDstData_0_dummy2_1_read__100_THEN_IF_pr_ETC___d1126 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[6:5] : propDstData_0_rl[6:5]) : 2'd0 ; - assign IF_propDstData_1_0_lat_0_whas__202_THEN_propDs_ETC___d1207 = + assign IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1203 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[579:516] : propDstData_1_0_rl[579:516] ; - assign IF_propDstData_1_0_lat_0_whas__202_THEN_propDs_ETC___d1212 = + assign IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1208 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[515:514] : propDstData_1_0_rl[515:514] ; - assign IF_propDstData_1_0_lat_0_whas__202_THEN_propDs_ETC___d1233 = + assign IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1229 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[0] : propDstData_1_0_rl[0] ; - assign IF_propDstData_1_1_lat_0_whas__240_THEN_propDs_ETC___d1245 = + assign IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1241 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[579:516] : propDstData_1_1_rl[579:516] ; - assign IF_propDstData_1_1_lat_0_whas__240_THEN_propDs_ETC___d1250 = + assign IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1246 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[515:514] : propDstData_1_1_rl[515:514] ; - assign IF_propDstData_1_1_lat_0_whas__240_THEN_propDs_ETC___d1271 = + assign IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1267 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[0] : propDstData_1_1_rl[0] ; - assign IF_propDstData_1_dummy2_1_read__109_THEN_IF_pr_ETC___d1124 = + assign IF_propDstData_1_dummy2_1_read__105_THEN_IF_pr_ETC___d1120 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[8:7] : propDstData_1_rl[8:7]) : 2'd0 ; - assign IF_propDstData_1_dummy2_1_read__109_THEN_IF_pr_ETC___d1134 = + assign IF_propDstData_1_dummy2_1_read__105_THEN_IF_pr_ETC___d1130 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[6:5] : propDstData_1_rl[6:5]) : 2'd0 ; - assign IF_propDstIdx_0_lat_0_whas__013_THEN_propDstId_ETC___d1016 = + assign IF_propDstIdx_0_lat_0_whas__009_THEN_propDstId_ETC___d1012 = CAN_FIRE_RL_srcPropose || propDstIdx_0_rl ; - assign IF_propDstIdx_1_0_lat_0_whas__187_THEN_propDst_ETC___d1190 = + assign IF_propDstIdx_1_0_lat_0_whas__183_THEN_propDst_ETC___d1186 = CAN_FIRE_RL_srcPropose_2 || propDstIdx_1_0_rl ; - assign IF_propDstIdx_1_1_lat_0_whas__194_THEN_propDst_ETC___d1197 = + assign IF_propDstIdx_1_1_lat_0_whas__190_THEN_propDst_ETC___d1193 = CAN_FIRE_RL_srcPropose_3 || propDstIdx_1_1_rl ; - assign IF_propDstIdx_1_lat_0_whas__020_THEN_propDstId_ETC___d1023 = + assign IF_propDstIdx_1_lat_0_whas__016_THEN_propDstId_ETC___d1019 = CAN_FIRE_RL_srcPropose_1 || propDstIdx_1_rl ; - assign NOT_enqDst_0_dummy2_0_read__087_088_OR_NOT_enq_ETC___d1103 = + assign NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 = (!enqDst_0_dummy2_0$Q_OUT || !enqDst_0_dummy2_1$Q_OUT || !enqDst_0_rl[73]) && - (SEL_ARR_propDstIdx_0_dummy2_1_read__066_AND_IF_ETC___d1097 || - IF_NOT_propDstIdx_0_dummy2_1_read__066_067_OR__ETC___d1101) ; - assign NOT_enqDst_1_0_dummy2_0_read__361_362_OR_NOT_e_ETC___d1377 = + (SEL_ARR_propDstIdx_0_dummy2_1_read__062_AND_IF_ETC___d1093 || + IF_NOT_propDstIdx_0_dummy2_1_read__062_063_OR__ETC___d1097) ; + assign NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 = (!enqDst_1_0_dummy2_0$Q_OUT || !enqDst_1_0_dummy2_1$Q_OUT || !enqDst_1_0_rl[580]) && - (SEL_ARR_propDstIdx_1_0_dummy2_1_read__330_AND__ETC___d1371 || - IF_NOT_propDstIdx_1_0_dummy2_1_read__330_331_O_ETC___d1375) ; - assign NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801 = + (SEL_ARR_propDstIdx_1_0_dummy2_1_read__326_AND__ETC___d1367 || + IF_NOT_propDstIdx_1_0_dummy2_1_read__326_327_O_ETC___d1371) ; + assign NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797 = llc_axi4_adapter_cfg_verbosity > 4'd1 ; - assign NOT_llc_mem_server_enqDst_0_dummy2_0_read__711_ETC___d1718 = + assign NOT_llc_mem_server_enqDst_0_dummy2_0_read__707_ETC___d1714 = (!llc_mem_server_enqDst_0_dummy2_0$Q_OUT || !llc_mem_server_enqDst_0_dummy2_1$Q_OUT || !llc_mem_server_enqDst_0_rl[65]) && llc_mem_server_propDstIdx_0_dummy2_1$Q_OUT && - IF_llc_mem_server_propDstIdx_0_lat_0_whas__665_ETC___d1668 ; - assign NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d754 = + IF_llc_mem_server_propDstIdx_0_lat_0_whas__661_ETC___d1664 ; + assign NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d750 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -5864,7 +5861,7 @@ module mkProc(CLK, mmioPlatform_state == 2'd2 && (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqFunc[5:4] == 2'd2) ; - assign NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d762 = + assign NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d758 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -5875,7 +5872,7 @@ module mkProc(CLK, mmioPlatform_state == 2'd3 && (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqFunc[5:4] == 2'd2) ; - assign NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d767 = + assign NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d763 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -5887,7 +5884,7 @@ module mkProc(CLK, mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2 ; - assign NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d777 = + assign NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d773 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -5899,7 +5896,7 @@ module mkProc(CLK, mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2 ; - assign NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d968 = + assign NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d964 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -5909,7 +5906,7 @@ module mkProc(CLK, mmioPlatform_curReq[66:64] != 3'd6 && mmioPlatform_state == 2'd2 && mmioPlatform_reqFunc[5:4] == 2'd0 ; - assign NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d981 = + assign NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d977 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -5929,35 +5926,29 @@ module mkProc(CLK, (mmioPlatform_fromHostQ_deqReq_lat_0$whas || mmioPlatform_fromHostQ_deqReq_rl) || mmioPlatform_fromHostQ_empty) ; - assign NOT_mmioPlatform_mtip_0_55_64_AND_mmioPlatform_ETC___d374 = + assign NOT_mmioPlatform_mtip_0_55_62_AND_mmioPlatform_ETC___d370 = !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 && - mmioPlatform_mtimecmp_0 != 64'd0 || + mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 || !core_0$mmioToPlatform_cRq_notEmpty || core_0$RDY_mmioToPlatform_cRq_first && core_0$RDY_mmioToPlatform_cRq_deq ; - assign NOT_mmioPlatform_mtip_0_55_64_AND_mmioPlatform_ETC___d379 = - !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 && - mmioPlatform_mtimecmp_0 != 64'd0 || - core_0$mmioToPlatform_cRq_notEmpty ; - assign NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d490 = + assign NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d486 = mmioPlatform_reqFunc[5:4] != 2'd0 && !mmioPlatform_reqBE[4] && (mmioPlatform_reqBE[0] || mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqFunc[5:4] == 2'd2) ; - assign NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d585 = + assign NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d581 = mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && - (IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 && + (IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && !mmioPlatform_mtip_0 || - !IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 && + !IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && mmioPlatform_mtip_0) ; - assign NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d648 = + assign NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d644 = mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && - (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && + (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && + !mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && mmioPlatform_mtip_0) ; assign NOT_mmioPlatform_toHostQ_clearReq_dummy2_1_rea_ETC___d240 = !mmioPlatform_toHostQ_clearReq_dummy2_1$Q_OUT || @@ -5971,57 +5962,57 @@ module mkProc(CLK, (!mmioPlatform_toHostQ_empty || mmioPlatform_toHostQ_deqReq_rl) || mmioPlatform_toHostQ_empty) ; - assign NOT_propDstData_1_0_dummy2_1_read__378_389_OR__ETC___d1390 = + assign NOT_propDstData_1_0_dummy2_1_read__374_385_OR__ETC___d1386 = !propDstData_1_0_dummy2_1$Q_OUT || (CAN_FIRE_RL_srcPropose_2 ? !propDstData_1_0_lat_0$wget[513] : !propDstData_1_0_rl[513]) ; - assign NOT_propDstData_1_1_dummy2_1_read__380_391_OR__ETC___d1392 = + assign NOT_propDstData_1_1_dummy2_1_read__376_387_OR__ETC___d1388 = !propDstData_1_1_dummy2_1$Q_OUT || (CAN_FIRE_RL_srcPropose_3 ? !propDstData_1_1_lat_0$wget[513] : !propDstData_1_1_rl[513]) ; - assign NOT_propDstIdx_0_dummy2_1_read__066_067_OR_IF__ETC___d1100 = + assign NOT_propDstIdx_0_dummy2_1_read__062_063_OR_IF__ETC___d1096 = !propDstIdx_0_dummy2_1$Q_OUT || !CAN_FIRE_RL_srcPropose && !propDstIdx_0_rl ; - assign NOT_propDstIdx_1_0_dummy2_1_read__330_331_OR_I_ETC___d1374 = + assign NOT_propDstIdx_1_0_dummy2_1_read__326_327_OR_I_ETC___d1370 = !propDstIdx_1_0_dummy2_1$Q_OUT || !CAN_FIRE_RL_srcPropose_2 && !propDstIdx_1_0_rl ; - assign NOT_propDstIdx_1_1_dummy2_1_read__348_349_OR_I_ETC___d1481 = + assign NOT_propDstIdx_1_1_dummy2_1_read__344_345_OR_I_ETC___d1477 = !propDstIdx_1_1_dummy2_1$Q_OUT || !CAN_FIRE_RL_srcPropose_3 && !propDstIdx_1_1_rl ; - assign NOT_propDstIdx_1_dummy2_1_read__079_080_OR_IF__ETC___d1179 = + assign NOT_propDstIdx_1_dummy2_1_read__075_076_OR_IF__ETC___d1175 = !propDstIdx_1_dummy2_1$Q_OUT || !CAN_FIRE_RL_srcPropose_1 && !propDstIdx_1_rl ; - assign SEL_ARR_IF_propDstData_0_dummy2_1_read__104_TH_ETC___d1168 = - { CASE_x1422_0_IF_propDstData_0_dummy2_1_read__1_ETC__q13, - CASE_x1422_0_IF_propDstData_0_dummy2_1_read__1_ETC__q14, - SEL_ARR_propDstData_0_dummy2_1_read__104_AND_I_ETC___d1167 } ; - assign SEL_ARR_IF_propDstData_1_0_dummy2_1_read__378__ETC___d1470 = - { CASE_x0307_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24, - !CASE_x0307_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__202_THE_ETC___d1463, - x__h82723 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__202_THE_ETC___d1412 = - { CASE_x0307_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16, - CASE_x0307_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__202_THE_ETC___d1429 = - { SEL_ARR_IF_propDstData_1_0_lat_0_whas__202_THE_ETC___d1412, - CASE_x0307_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18, - CASE_x0307_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__202_THE_ETC___d1446 = - { SEL_ARR_IF_propDstData_1_0_lat_0_whas__202_THE_ETC___d1429, - CASE_x0307_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20, - CASE_x0307_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__202_THE_ETC___d1463 = - { SEL_ARR_IF_propDstData_1_0_lat_0_whas__202_THE_ETC___d1446, - CASE_x0307_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22, - CASE_x0307_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 } ; - assign SEL_ARR_propDstData_0_dummy2_1_read__104_AND_I_ETC___d1167 = - { CASE_x1422_0_propDstData_0_dummy2_1_read__104__ETC__q12, - x__h61736, - x__h61743 } ; - assign b__h134531 = + assign SEL_ARR_IF_propDstData_0_dummy2_1_read__100_TH_ETC___d1164 = + { CASE_x1406_0_IF_propDstData_0_dummy2_1_read__1_ETC__q13, + CASE_x1406_0_IF_propDstData_0_dummy2_1_read__1_ETC__q14, + SEL_ARR_propDstData_0_dummy2_1_read__100_AND_I_ETC___d1163 } ; + assign SEL_ARR_IF_propDstData_1_0_dummy2_1_read__374__ETC___d1466 = + { CASE_x0291_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24, + !CASE_x0291_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1459, + x__h82707 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1408 = + { CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16, + CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1425 = + { SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1408, + CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18, + CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1442 = + { SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1425, + CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20, + CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1459 = + { SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1442, + CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22, + CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 } ; + assign SEL_ARR_propDstData_0_dummy2_1_read__100_AND_I_ETC___d1163 = + { CASE_x1406_0_propDstData_0_dummy2_1_read__100__ETC__q12, + x__h61720, + x__h61727 } ; + assign b__h134515 = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ? llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 : llc_axi4_adapter_ctr_wr_rsps_pending_crg ; @@ -6029,23 +6020,23 @@ module mkProc(CLK, mmio_axi4_adapter_ctr_wr_rsps_pending_crg$EN_port0__write ? mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 : mmio_axi4_adapter_ctr_wr_rsps_pending_crg ; - assign data__h31746 = + assign data__h31730 = mmioPlatform_waitLowerMSIPCRs ? { 63'd0, core_0$mmioToPlatform_cRs_first } : - { v__h31539, 32'd0 } ; - assign failed_testnum__h163309 = + { v__h31523, 32'd0 } ; + assign failed_testnum__h163293 = { 1'd0, mmioPlatform_toHostQ_data_0[63:1] } ; - assign line_addr__h102529 = + assign line_addr__h102513 = { llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[92:35], 6'b0 } ; - assign line_addr__h102615 = + assign line_addr__h102599 = { llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[92:35], 6'b0 } ; - assign llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1612 = - line_addr__h102615 == llc_mem_server_rg_cacheline_cache_addr ; - assign llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1534 = - line_addr__h102529 == llc_mem_server_rg_cacheline_cache_addr ; - assign mask__h90152 = + assign llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1608 = + line_addr__h102599 == llc_mem_server_rg_cacheline_cache_addr ; + assign llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1530 = + line_addr__h102513 == llc_mem_server_rg_cacheline_cache_addr ; + assign mask__h90136 = { llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8] ? 8'hFF : 8'h0, @@ -6070,14 +6061,14 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[1] ? 8'hFF : 8'h0 } ; - assign mem_req_rd_addr_araddr__h134824 = - { llc$to_mem_toM_first[68:11], x__h134859 } ; - assign mem_req_wr_addr_awaddr__h148748 = - { llc$to_mem_toM_first[639:582], x__h148773 } ; + assign mem_req_rd_addr_araddr__h134808 = + { llc$to_mem_toM_first[68:11], x__h134843 } ; + assign mem_req_wr_addr_awaddr__h148732 = + { llc$to_mem_toM_first[639:582], x__h148757 } ; assign mmioPlatform_cycle_47_ULT_99___d348 = mmioPlatform_cycle < 7'd99 ; - assign mmioPlatform_fetchingWay_73_ULT_mmioPlatform_r_ETC___d983 = + assign mmioPlatform_fetchingWay_69_ULT_mmioPlatform_r_ETC___d979 = mmioPlatform_fetchingWay < mmioPlatform_reqFunc[0] ; - assign mmioPlatform_fromHostQ_data_0__h42593 = + assign mmioPlatform_fromHostQ_data_0__h42577 = mmioPlatform_fromHostQ_data_0 ; assign mmioPlatform_fromHostQ_enqReq_dummy2_2_read__1_ETC___d331 = mmioPlatform_fromHostQ_enqReq_dummy2_2$Q_OUT && @@ -6088,41 +6079,36 @@ module mkProc(CLK, mmioPlatform_fromHostQ_full ; assign mmioPlatform_mtime_BITS_31_TO_0__q4 = mmioPlatform_mtime[31:0] ; assign mmioPlatform_mtime_BITS_63_TO_32__q3 = mmioPlatform_mtime[63:32] ; - assign mmioPlatform_mtime__h37060 = mmioPlatform_mtime ; - assign mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 = - mmioPlatform_mtimecmp_0 <= newData__h34757 ; + assign mmioPlatform_mtime__h37044 = mmioPlatform_mtime ; + assign mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 = + mmioPlatform_mtimecmp_0 <= newData__h34741 ; assign mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 = mmioPlatform_mtimecmp_0 <= mmioPlatform_mtime ; assign mmioPlatform_mtimecmp_0_BITS_31_TO_0__q2 = mmioPlatform_mtimecmp_0[31:0] ; assign mmioPlatform_mtimecmp_0_BITS_63_TO_32__q1 = mmioPlatform_mtimecmp_0[63:32] ; - assign mmioPlatform_mtip_0_55_OR_NOT_mmioPlatform_mti_ETC___d410 = - (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 || - mmioPlatform_mtimecmp_0 == 64'd0) && - core_0$mmioToPlatform_cRq_notEmpty ; - assign mmioPlatform_reqBE_BIT_0___h29954 = mmioPlatform_reqBE[0] ; - assign mmioPlatform_reqBE_BIT_4___h29914 = mmioPlatform_reqBE[4] ; - assign mmioPlatform_reqData__h48614 = mmioPlatform_reqData ; - assign mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d467 = + assign mmioPlatform_reqBE_BIT_0___h29938 = mmioPlatform_reqBE[0] ; + assign mmioPlatform_reqBE_BIT_4___h29898 = mmioPlatform_reqBE[4] ; + assign mmioPlatform_reqData__h48598 = mmioPlatform_reqData ; + assign mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d463 = mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqBE[4] || mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2 && !mmioPlatform_reqBE[0] ; - assign mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d571 = + assign mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d567 = mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqFunc[5:4] == 2'd1 || - (!IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 || + (!IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 || mmioPlatform_mtip_0) && - (IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 || + (IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 || !mmioPlatform_mtip_0) ; - assign mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d636 = + assign mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d632 = mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqFunc[5:4] == 2'd1 || - (!mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 || + (!mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 || mmioPlatform_mtip_0) && - (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 || + (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 || !mmioPlatform_mtip_0) ; assign mmioPlatform_toHostQ_enqReq_dummy2_2_read__41__ETC___d253 = mmioPlatform_toHostQ_enqReq_dummy2_2$Q_OUT && @@ -6136,235 +6122,235 @@ module mkProc(CLK, (mmio_axi4_adapter_soc_map$m_is_IO_addr ? !mmio_axi4_adapter_master_xactor_crg_rd_addr_full$port2__read : mmio_axi4_adapter_f_rsps_to_core$FULL_N) ; - assign n__read_addr__h61604 = + assign n__read_addr__h61588 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[72:9] : propDstData_0_rl[72:9]) : 64'd0 ; - assign n__read_addr__h61689 = + assign n__read_addr__h61673 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[72:9] : propDstData_1_rl[72:9]) : 64'd0 ; - assign n__read_addr__h80485 = + assign n__read_addr__h80469 = propDstData_1_0_dummy2_1$Q_OUT ? - IF_propDstData_1_0_lat_0_whas__202_THEN_propDs_ETC___d1207 : + IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1203 : 64'd0 ; - assign n__read_addr__h80564 = + assign n__read_addr__h80548 = propDstData_1_1_dummy2_1$Q_OUT ? - IF_propDstData_1_1_lat_0_whas__240_THEN_propDs_ETC___d1245 : + IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1241 : 64'd0 ; - assign n__read_child__h61609 = + assign n__read_child__h61593 = propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[0] : propDstData_0_rl[0]) ; - assign n__read_child__h61694 = + assign n__read_child__h61678 = propDstData_1_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[0] : propDstData_1_rl[0]) ; - assign n__read_child__h80488 = + assign n__read_child__h80472 = propDstData_1_0_dummy2_1$Q_OUT && - IF_propDstData_1_0_lat_0_whas__202_THEN_propDs_ETC___d1233 ; - assign n__read_child__h80567 = + IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1229 ; + assign n__read_child__h80551 = propDstData_1_1_dummy2_1$Q_OUT && - IF_propDstData_1_1_lat_0_whas__240_THEN_propDs_ETC___d1271 ; - assign n__read_id__h61608 = + IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1267 ; + assign n__read_id__h61592 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[3:1] : propDstData_0_rl[3:1]) : 3'd0 ; - assign n__read_id__h61693 = + assign n__read_id__h61677 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[3:1] : propDstData_1_rl[3:1]) : 3'd0 ; - assign n__read_snd_addr__h124056 = + assign n__read_snd_addr__h124040 = llc_mem_server_propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_llc_mem_server_srcPropose ? core_0$tlbToMem_memReq_first[64:1] : llc_mem_server_propDstData_0_rl[64:1]) : 64'd0 ; - assign n__read_snd_id__h124057 = + assign n__read_snd_id__h124041 = llc_mem_server_propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_llc_mem_server_srcPropose ? core_0$tlbToMem_memReq_first[0] : llc_mem_server_propDstData_0_rl[0]) ; - assign newData__h31827 = + assign newData__h31811 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h31938 : - IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d552 ; - assign newData__h34757 = + x__h31922 : + IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d548 ; + assign newData__h34741 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h34848 : - IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d614 ; - assign new_cline__h135526 = + x__h34832 : + IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d610 ; + assign new_cline__h135510 = { llc_axi4_adapter_master_xactor_rg_rd_data[66:3], llc_axi4_adapter_rg_cline[511:64] } ; - assign new_dword__h90156 = x__h91318 | y__h91319 ; - assign op_result__h48630 = - IF_mmioPlatform_reqSz_83_EQ_0b10_90_THEN_SEXT__ETC___d891 + - IF_mmioPlatform_reqSz_83_EQ_0b10_90_THEN_SEXT__ETC___d893 ; - assign op_result__h49160 = w1__h48027 ^ w2__h48029 ; - assign op_result__h49165 = w1__h48027 & w2__h48029 ; - assign op_result__h49170 = w1__h48027 | w2__h48029 ; - assign op_result__h49175 = - (w1__h48027 < w2__h48029) ? w1__h48027 : w2__h48029 ; - assign op_result__h49181 = - (w1__h48027 <= w2__h48029) ? w2__h48029 : w1__h48027 ; - assign op_result__h49188 = - ((IF_mmioPlatform_reqSz_83_EQ_0b10_90_THEN_SEXT__ETC___d891 ^ + assign new_dword__h90140 = x__h91302 | y__h91303 ; + assign op_result__h48614 = + IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d887 + + IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d889 ; + assign op_result__h49144 = w1__h48011 ^ w2__h48013 ; + assign op_result__h49149 = w1__h48011 & w2__h48013 ; + assign op_result__h49154 = w1__h48011 | w2__h48013 ; + assign op_result__h49159 = + (w1__h48011 < w2__h48013) ? w1__h48011 : w2__h48013 ; + assign op_result__h49165 = + (w1__h48011 <= w2__h48013) ? w2__h48013 : w1__h48011 ; + assign op_result__h49172 = + ((IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d887 ^ 64'h8000000000000000) < - (IF_mmioPlatform_reqSz_83_EQ_0b10_90_THEN_SEXT__ETC___d893 ^ + (IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d889 ^ 64'h8000000000000000)) ? - w1__h48027 : - w2__h48029 ; - assign op_result__h49194 = - ((IF_mmioPlatform_reqSz_83_EQ_0b10_90_THEN_SEXT__ETC___d891 ^ + w1__h48011 : + w2__h48013 ; + assign op_result__h49178 = + ((IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d887 ^ 64'h8000000000000000) <= - (IF_mmioPlatform_reqSz_83_EQ_0b10_90_THEN_SEXT__ETC___d893 ^ + (IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d889 ^ 64'h8000000000000000)) ? - w2__h48029 : - w1__h48027 ; - assign propDstData_0_dummy2_1_read__104_AND_IF_propDs_ETC___d1140 = + w2__h48013 : + w1__h48011 ; + assign propDstData_0_dummy2_1_read__100_AND_IF_propDs_ETC___d1136 = propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[4] : propDstData_0_rl[4]) ; - assign propDstData_1_dummy2_1_read__109_AND_IF_propDs_ETC___d1144 = + assign propDstData_1_dummy2_1_read__105_AND_IF_propDs_ETC___d1140 = propDstData_1_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[4] : propDstData_1_rl[4]) ; - assign result__h48073 = + assign result__h48057 = { mmioPlatform_reqData[63:8], - IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923[7:0] } ; - assign result__h48197 = { 56'd0, mmioPlatform_reqData[7:0] } ; - assign result__h48225 = { 56'd0, mmioPlatform_reqData[15:8] } ; - assign result__h48253 = { 56'd0, mmioPlatform_reqData[23:16] } ; - assign result__h48281 = { 56'd0, mmioPlatform_reqData[31:24] } ; - assign result__h48309 = { 56'd0, mmioPlatform_reqData[39:32] } ; - assign result__h48337 = { 56'd0, mmioPlatform_reqData[47:40] } ; - assign result__h48365 = { 56'd0, mmioPlatform_reqData[55:48] } ; - assign result__h48393 = { 56'd0, mmioPlatform_reqData[63:56] } ; - assign result__h48438 = { 48'd0, mmioPlatform_reqData[15:0] } ; - assign result__h48466 = { 48'd0, mmioPlatform_reqData[31:16] } ; - assign result__h48494 = { 48'd0, mmioPlatform_reqData[47:32] } ; - assign result__h48522 = { 48'd0, mmioPlatform_reqData[63:48] } ; - assign result__h48563 = { 32'd0, mmioPlatform_reqData[31:0] } ; - assign result__h48591 = { 32'd0, mmioPlatform_reqData[63:32] } ; - assign result__h48717 = + IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[7:0] } ; + assign result__h48181 = { 56'd0, mmioPlatform_reqData[7:0] } ; + assign result__h48209 = { 56'd0, mmioPlatform_reqData[15:8] } ; + assign result__h48237 = { 56'd0, mmioPlatform_reqData[23:16] } ; + assign result__h48265 = { 56'd0, mmioPlatform_reqData[31:24] } ; + assign result__h48293 = { 56'd0, mmioPlatform_reqData[39:32] } ; + assign result__h48321 = { 56'd0, mmioPlatform_reqData[47:40] } ; + assign result__h48349 = { 56'd0, mmioPlatform_reqData[55:48] } ; + assign result__h48377 = { 56'd0, mmioPlatform_reqData[63:56] } ; + assign result__h48422 = { 48'd0, mmioPlatform_reqData[15:0] } ; + assign result__h48450 = { 48'd0, mmioPlatform_reqData[31:16] } ; + assign result__h48478 = { 48'd0, mmioPlatform_reqData[47:32] } ; + assign result__h48506 = { 48'd0, mmioPlatform_reqData[63:48] } ; + assign result__h48547 = { 32'd0, mmioPlatform_reqData[31:0] } ; + assign result__h48575 = { 32'd0, mmioPlatform_reqData[63:32] } ; + assign result__h48701 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[7:0] } ; - assign result__h48744 = + assign result__h48728 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[15:8] } ; - assign result__h48771 = + assign result__h48755 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[23:16] } ; - assign result__h48798 = + assign result__h48782 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:24] } ; - assign result__h48825 = + assign result__h48809 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[39:32] } ; - assign result__h48852 = + assign result__h48836 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[47:40] } ; - assign result__h48879 = + assign result__h48863 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[55:48] } ; - assign result__h48906 = + assign result__h48890 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:56] } ; - assign result__h48950 = + assign result__h48934 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[15:0] } ; - assign result__h48977 = + assign result__h48961 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:16] } ; - assign result__h49004 = + assign result__h48988 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[47:32] } ; - assign result__h49031 = + assign result__h49015 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:48] } ; - assign result__h49071 = + assign result__h49055 = { 32'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:0] } ; - assign result__h49098 = + assign result__h49082 = { 32'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:32] } ; - assign result__h49215 = + assign result__h49199 = { mmioPlatform_reqData[63:16], - IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923[7:0], + IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[7:0], mmioPlatform_reqData[7:0] } ; - assign result__h49281 = + assign result__h49265 = { mmioPlatform_reqData[63:24], - IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923[7:0], + IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[7:0], mmioPlatform_reqData[15:0] } ; - assign result__h49347 = + assign result__h49331 = { mmioPlatform_reqData[63:32], - IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923[7:0], + IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[7:0], mmioPlatform_reqData[23:0] } ; - assign result__h49413 = + assign result__h49397 = { mmioPlatform_reqData[63:40], - IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923[7:0], + IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[7:0], mmioPlatform_reqData[31:0] } ; - assign result__h49479 = + assign result__h49463 = { mmioPlatform_reqData[63:48], - IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923[7:0], + IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[7:0], mmioPlatform_reqData[39:0] } ; - assign result__h49545 = + assign result__h49529 = { mmioPlatform_reqData[63:56], - IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923[7:0], + IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[7:0], mmioPlatform_reqData[47:0] } ; - assign result__h49611 = - { IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923[7:0], + assign result__h49595 = + { IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[7:0], mmioPlatform_reqData[55:0] } ; - assign result__h49673 = + assign result__h49657 = { mmioPlatform_reqData[63:16], - IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923[15:0] } ; - assign result__h49718 = + IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[15:0] } ; + assign result__h49702 = { mmioPlatform_reqData[63:32], - IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923[15:0], + IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[15:0], mmioPlatform_reqData[15:0] } ; - assign result__h49784 = + assign result__h49768 = { mmioPlatform_reqData[63:48], - IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923[15:0], + IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[15:0], mmioPlatform_reqData[31:0] } ; - assign result__h49850 = - { IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923[15:0], + assign result__h49834 = + { IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[15:0], mmioPlatform_reqData[47:0] } ; - assign result__h49908 = + assign result__h49892 = { mmioPlatform_reqData[63:32], - IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923[31:0] } ; - assign result__h49953 = - { IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923[31:0], + IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[31:0] } ; + assign result__h49937 = + { IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[31:0], mmioPlatform_reqData[31:0] } ; - assign v__h31539 = mmioPlatform_waitUpperMSIPCRs ? v__h31576 : 32'd0 ; - assign v__h31576 = { 31'd0, core_0$mmioToPlatform_cRs_first } ; - assign w18022_BITS_31_TO_0__q7 = w1__h48022[31:0] ; - assign w1___1__h48132 = { 32'd0, w1__h48022[31:0] } ; - assign w28023_BITS_31_TO_0__q8 = w2__h48023[31:0] ; - assign w2___1__h48133 = { 32'd0, w2__h48023[31:0] } ; - assign x1_avValue_data__h40265 = + assign v__h31523 = mmioPlatform_waitUpperMSIPCRs ? v__h31560 : 32'd0 ; + assign v__h31560 = { 31'd0, core_0$mmioToPlatform_cRs_first } ; + assign w18006_BITS_31_TO_0__q7 = w1__h48006[31:0] ; + assign w1___1__h48116 = { 32'd0, w1__h48006[31:0] } ; + assign w28007_BITS_31_TO_0__q8 = w2__h48007[31:0] ; + assign w2___1__h48117 = { 32'd0, w2__h48007[31:0] } ; + assign x1_avValue_data__h40249 = mmioPlatform_toHostQ_empty ? 64'd0 : mmioPlatform_toHostQ_data_0 ; - assign x1_avValue_data__h44951 = + assign x1_avValue_data__h44935 = mmioPlatform_fromHostQ_empty ? 64'd0 : mmioPlatform_fromHostQ_data_0 ; - assign x__h134859 = { llc_axi4_adapter_rg_rd_req_beat, 3'b0 } ; - assign x__h148773 = { llc_axi4_adapter_rg_wr_req_beat, 3'b0 } ; - assign x__h37208 = mmioPlatform_mtimecmp_0 ; - assign x__h40783 = + assign x__h134843 = { llc_axi4_adapter_rg_rd_req_beat, 3'b0 } ; + assign x__h148757 = { llc_axi4_adapter_rg_wr_req_beat, 3'b0 } ; + assign x__h37192 = mmioPlatform_mtimecmp_0 ; + assign x__h40767 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h40794 : - IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d718 ; - assign x__h42876 = + x__h40778 : + IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d714 ; + assign x__h42860 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h42887 : + x__h42871 : { mmioPlatform_reqBE[7] ? mmioPlatform_reqData[63:56] : 8'd0, mmioPlatform_reqBE[6] ? mmioPlatform_reqData[55:48] : 8'd0, mmioPlatform_reqBE[5] ? mmioPlatform_reqData[47:40] : 8'd0, @@ -6373,29 +6359,29 @@ module mkProc(CLK, mmioPlatform_reqBE[2] ? mmioPlatform_reqData[23:16] : 8'd0, mmioPlatform_reqBE[1] ? mmioPlatform_reqData[15:8] : 8'd0, mmioPlatform_reqBE[0] ? mmioPlatform_reqData[7:0] : 8'd0 } ; - assign x__h50130 = { mmioPlatform_curReq[63:3], 3'b0 } ; - assign x__h61422 = - SEL_ARR_propDstIdx_0_dummy2_1_read__066_AND_IF_ETC___d1097 ? + assign x__h50114 = { mmioPlatform_curReq[63:3], 3'b0 } ; + assign x__h61406 = + SEL_ARR_propDstIdx_0_dummy2_1_read__062_AND_IF_ETC___d1093 ? srcRR_0 : - NOT_propDstIdx_0_dummy2_1_read__066_067_OR_IF__ETC___d1100 ; - assign x__h75236 = + NOT_propDstIdx_0_dummy2_1_read__062_063_OR_IF__ETC___d1096 ; + assign x__h75220 = !CAN_FIRE_RL_doEnq_1 && - IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1319 ; + IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1315 ; assign x__h7705 = (mmio_axi4_adapter_f_reqs_from_core$D_OUT[71:68] == 4'd0 || mmio_axi4_adapter_f_reqs_from_core$D_OUT[67:64] == 4'd0) ? 3'b010 : 3'b011 ; - assign x__h80307 = - SEL_ARR_propDstIdx_1_0_dummy2_1_read__330_AND__ETC___d1371 ? + assign x__h80291 = + SEL_ARR_propDstIdx_1_0_dummy2_1_read__326_AND__ETC___d1367 ? srcRR_1_0 : - NOT_propDstIdx_1_0_dummy2_1_read__330_331_OR_I_ETC___d1374 ; - assign x__h91318 = old_dword__h90155 & y__h91320 ; - assign x_data__h30329 = { 31'd0, mmioPlatform_reqData[0] } ; - assign y__h91319 = + NOT_propDstIdx_1_0_dummy2_1_read__326_327_OR_I_ETC___d1370 ; + assign x__h91302 = old_dword__h90139 & y__h91304 ; + assign x_data__h30313 = { 31'd0, mmioPlatform_reqData[0] } ; + assign y__h91303 = llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[72:9] & - mask__h90152 ; - assign y__h91320 = + mask__h90136 ; + assign y__h91304 = { llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8] ? 8'd0 : 8'd255, @@ -6424,466 +6410,466 @@ module mkProc(CLK, llc_mem_server_rg_cacheline_cache_data) begin case (llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[34:32]) - 3'd0: dword__h94465 = llc_mem_server_rg_cacheline_cache_data[63:0]; - 3'd1: dword__h94465 = llc_mem_server_rg_cacheline_cache_data[127:64]; - 3'd2: dword__h94465 = llc_mem_server_rg_cacheline_cache_data[191:128]; - 3'd3: dword__h94465 = llc_mem_server_rg_cacheline_cache_data[255:192]; - 3'd4: dword__h94465 = llc_mem_server_rg_cacheline_cache_data[319:256]; - 3'd5: dword__h94465 = llc_mem_server_rg_cacheline_cache_data[383:320]; - 3'd6: dword__h94465 = llc_mem_server_rg_cacheline_cache_data[447:384]; - 3'd7: dword__h94465 = llc_mem_server_rg_cacheline_cache_data[511:448]; + 3'd0: dword__h94449 = llc_mem_server_rg_cacheline_cache_data[63:0]; + 3'd1: dword__h94449 = llc_mem_server_rg_cacheline_cache_data[127:64]; + 3'd2: dword__h94449 = llc_mem_server_rg_cacheline_cache_data[191:128]; + 3'd3: dword__h94449 = llc_mem_server_rg_cacheline_cache_data[255:192]; + 3'd4: dword__h94449 = llc_mem_server_rg_cacheline_cache_data[319:256]; + 3'd5: dword__h94449 = llc_mem_server_rg_cacheline_cache_data[383:320]; + 3'd6: dword__h94449 = llc_mem_server_rg_cacheline_cache_data[447:384]; + 3'd7: dword__h94449 = llc_mem_server_rg_cacheline_cache_data[511:448]; endcase end always@(llc$dma_respLd_first) begin case (llc$dma_respLd_first[2:0]) - 3'd0: ld_data__h132752 = llc$dma_respLd_first[68:5]; - 3'd1: ld_data__h132752 = llc$dma_respLd_first[132:69]; - 3'd2: ld_data__h132752 = llc$dma_respLd_first[196:133]; - 3'd3: ld_data__h132752 = llc$dma_respLd_first[260:197]; - 3'd4: ld_data__h132752 = llc$dma_respLd_first[324:261]; - 3'd5: ld_data__h132752 = llc$dma_respLd_first[388:325]; - 3'd6: ld_data__h132752 = llc$dma_respLd_first[452:389]; - 3'd7: ld_data__h132752 = llc$dma_respLd_first[516:453]; + 3'd0: ld_data__h132736 = llc$dma_respLd_first[68:5]; + 3'd1: ld_data__h132736 = llc$dma_respLd_first[132:69]; + 3'd2: ld_data__h132736 = llc$dma_respLd_first[196:133]; + 3'd3: ld_data__h132736 = llc$dma_respLd_first[260:197]; + 3'd4: ld_data__h132736 = llc$dma_respLd_first[324:261]; + 3'd5: ld_data__h132736 = llc$dma_respLd_first[388:325]; + 3'd6: ld_data__h132736 = llc$dma_respLd_first[452:389]; + 3'd7: ld_data__h132736 = llc$dma_respLd_first[516:453]; endcase end always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) begin case (llc_axi4_adapter_rg_wr_req_beat) - 3'd0: data64__h148663 = llc$to_mem_toM_first[63:0]; - 3'd1: data64__h148663 = llc$to_mem_toM_first[127:64]; - 3'd2: data64__h148663 = llc$to_mem_toM_first[191:128]; - 3'd3: data64__h148663 = llc$to_mem_toM_first[255:192]; - 3'd4: data64__h148663 = llc$to_mem_toM_first[319:256]; - 3'd5: data64__h148663 = llc$to_mem_toM_first[383:320]; - 3'd6: data64__h148663 = llc$to_mem_toM_first[447:384]; - 3'd7: data64__h148663 = llc$to_mem_toM_first[511:448]; + 3'd0: data64__h148647 = llc$to_mem_toM_first[63:0]; + 3'd1: data64__h148647 = llc$to_mem_toM_first[127:64]; + 3'd2: data64__h148647 = llc$to_mem_toM_first[191:128]; + 3'd3: data64__h148647 = llc$to_mem_toM_first[255:192]; + 3'd4: data64__h148647 = llc$to_mem_toM_first[319:256]; + 3'd5: data64__h148647 = llc$to_mem_toM_first[383:320]; + 3'd6: data64__h148647 = llc$to_mem_toM_first[447:384]; + 3'd7: data64__h148647 = llc$to_mem_toM_first[511:448]; endcase end always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) begin case (llc_axi4_adapter_rg_wr_req_beat) - 3'd0: strb8__h148664 = llc$to_mem_toM_first[519:512]; - 3'd1: strb8__h148664 = llc$to_mem_toM_first[527:520]; - 3'd2: strb8__h148664 = llc$to_mem_toM_first[535:528]; - 3'd3: strb8__h148664 = llc$to_mem_toM_first[543:536]; - 3'd4: strb8__h148664 = llc$to_mem_toM_first[551:544]; - 3'd5: strb8__h148664 = llc$to_mem_toM_first[559:552]; - 3'd6: strb8__h148664 = llc$to_mem_toM_first[567:560]; - 3'd7: strb8__h148664 = llc$to_mem_toM_first[575:568]; + 3'd0: strb8__h148648 = llc$to_mem_toM_first[519:512]; + 3'd1: strb8__h148648 = llc$to_mem_toM_first[527:520]; + 3'd2: strb8__h148648 = llc$to_mem_toM_first[535:528]; + 3'd3: strb8__h148648 = llc$to_mem_toM_first[543:536]; + 3'd4: strb8__h148648 = llc$to_mem_toM_first[551:544]; + 3'd5: strb8__h148648 = llc$to_mem_toM_first[559:552]; + 3'd6: strb8__h148648 = llc$to_mem_toM_first[567:560]; + 3'd7: strb8__h148648 = llc$to_mem_toM_first[575:568]; endcase end always@(llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT or llc_mem_server_rg_cacheline_cache_data) begin case (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32]) - 3'd0: old_dword__h90155 = llc_mem_server_rg_cacheline_cache_data[63:0]; + 3'd0: old_dword__h90139 = llc_mem_server_rg_cacheline_cache_data[63:0]; 3'd1: - old_dword__h90155 = llc_mem_server_rg_cacheline_cache_data[127:64]; + old_dword__h90139 = llc_mem_server_rg_cacheline_cache_data[127:64]; 3'd2: - old_dword__h90155 = llc_mem_server_rg_cacheline_cache_data[191:128]; + old_dword__h90139 = llc_mem_server_rg_cacheline_cache_data[191:128]; 3'd3: - old_dword__h90155 = llc_mem_server_rg_cacheline_cache_data[255:192]; + old_dword__h90139 = llc_mem_server_rg_cacheline_cache_data[255:192]; 3'd4: - old_dword__h90155 = llc_mem_server_rg_cacheline_cache_data[319:256]; + old_dword__h90139 = llc_mem_server_rg_cacheline_cache_data[319:256]; 3'd5: - old_dword__h90155 = llc_mem_server_rg_cacheline_cache_data[383:320]; + old_dword__h90139 = llc_mem_server_rg_cacheline_cache_data[383:320]; 3'd6: - old_dword__h90155 = llc_mem_server_rg_cacheline_cache_data[447:384]; + old_dword__h90139 = llc_mem_server_rg_cacheline_cache_data[447:384]; 3'd7: - old_dword__h90155 = llc_mem_server_rg_cacheline_cache_data[511:448]; + old_dword__h90139 = llc_mem_server_rg_cacheline_cache_data[511:448]; endcase end always@(mmioPlatform_curReq or - result__h48197 or - result__h48225 or - result__h48253 or - result__h48281 or - result__h48309 or - result__h48337 or result__h48365 or result__h48393) + result__h48181 or + result__h48209 or + result__h48237 or + result__h48265 or + result__h48293 or + result__h48321 or result__h48349 or result__h48377) begin case (mmioPlatform_curReq[2:0]) 3'h0: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d813 = - result__h48197; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 = + result__h48181; 3'h1: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d813 = - result__h48225; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 = + result__h48209; 3'h2: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d813 = - result__h48253; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 = + result__h48237; 3'h3: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d813 = - result__h48281; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 = + result__h48265; 3'h4: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d813 = - result__h48309; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 = + result__h48293; 3'h5: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d813 = - result__h48337; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 = + result__h48321; 3'h6: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d813 = - result__h48365; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 = + result__h48349; 3'h7: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d813 = - result__h48393; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 = + result__h48377; endcase end always@(mmioPlatform_curReq or - result__h48438 or - result__h48466 or result__h48494 or result__h48522) + result__h48422 or + result__h48450 or result__h48478 or result__h48506) begin case (mmioPlatform_curReq[2:0]) 3'h0: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d826 = - result__h48438; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822 = + result__h48422; 3'h2: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d826 = - result__h48466; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822 = + result__h48450; 3'h4: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d826 = - result__h48494; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822 = + result__h48478; 3'h6: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d826 = - result__h48522; - default: IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d826 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822 = + result__h48506; + default: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822 = 64'd0; endcase end - always@(mmioPlatform_curReq or result__h48563 or result__h48591) + always@(mmioPlatform_curReq or result__h48547 or result__h48575) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5 = - result__h48563; + result__h48547; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5 = - result__h48591; + result__h48575; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5 = 64'd0; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d813 or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d826 or + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 or + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822 or CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5 or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d833) + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829) begin case (mmioPlatform_reqSz) 2'b0: - w2__h48023 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d813; + w2__h48007 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809; 2'b01: - w2__h48023 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d826; + w2__h48007 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822; 2'b10: - w2__h48023 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5; + w2__h48007 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5; 2'b11: - w2__h48023 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d833; + w2__h48007 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d813 or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d826 or - w2___1__h48133 or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d833) + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 or + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822 or + w2___1__h48117 or + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829) begin case (mmioPlatform_reqSz) 2'b0: - w2__h48029 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d813; + w2__h48013 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809; 2'b01: - w2__h48029 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d826; - 2'b10: w2__h48029 = w2___1__h48133; + w2__h48013 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822; + 2'b10: w2__h48013 = w2___1__h48117; 2'b11: - w2__h48029 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d833; + w2__h48013 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829; endcase end always@(mmioPlatform_curReq or - result__h48950 or - result__h48977 or result__h49004 or result__h49031) + result__h48934 or + result__h48961 or result__h48988 or result__h49015) begin case (mmioPlatform_curReq[2:0]) 3'h0: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d877 = - result__h48950; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873 = + result__h48934; 3'h2: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d877 = - result__h48977; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873 = + result__h48961; 3'h4: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d877 = - result__h49004; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873 = + result__h48988; 3'h6: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d877 = - result__h49031; - default: IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d877 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873 = + result__h49015; + default: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873 = 64'd0; endcase end always@(mmioPlatform_curReq or - result__h48717 or - result__h48744 or - result__h48771 or - result__h48798 or - result__h48825 or - result__h48852 or result__h48879 or result__h48906) + result__h48701 or + result__h48728 or + result__h48755 or + result__h48782 or + result__h48809 or + result__h48836 or result__h48863 or result__h48890) begin case (mmioPlatform_curReq[2:0]) 3'h0: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d865 = - result__h48717; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 = + result__h48701; 3'h1: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d865 = - result__h48744; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 = + result__h48728; 3'h2: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d865 = - result__h48771; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 = + result__h48755; 3'h3: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d865 = - result__h48798; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 = + result__h48782; 3'h4: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d865 = - result__h48825; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 = + result__h48809; 3'h5: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d865 = - result__h48852; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 = + result__h48836; 3'h6: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d865 = - result__h48879; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 = + result__h48863; 3'h7: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d865 = - result__h48906; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 = + result__h48890; endcase end - always@(mmioPlatform_curReq or result__h49071 or result__h49098) + always@(mmioPlatform_curReq or result__h49055 or result__h49082) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6 = - result__h49071; + result__h49055; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6 = - result__h49098; + result__h49082; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6 = 64'd0; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d865 or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d877 or + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 or + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873 or CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6 or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d884) + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d880) begin case (mmioPlatform_reqSz) 2'b0: - w1__h48022 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d865; + w1__h48006 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861; 2'b01: - w1__h48022 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d877; + w1__h48006 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873; 2'b10: - w1__h48022 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6; + w1__h48006 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6; 2'b11: - w1__h48022 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d884; + w1__h48006 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d880; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d865 or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d877 or - w1___1__h48132 or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d884) + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 or + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873 or + w1___1__h48116 or + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d880) begin case (mmioPlatform_reqSz) 2'b0: - w1__h48027 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d865; + w1__h48011 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861; 2'b01: - w1__h48027 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d877; - 2'b10: w1__h48027 = w1___1__h48132; + w1__h48011 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873; + 2'b10: w1__h48011 = w1___1__h48116; 2'b11: - w1__h48027 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d884; + w1__h48011 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d880; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d865 or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d877 or - w18022_BITS_31_TO_0__q7 or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d884) + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 or + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873 or + w18006_BITS_31_TO_0__q7 or + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d880) begin case (mmioPlatform_reqSz) 2'b0: - IF_mmioPlatform_reqSz_83_EQ_0b10_90_THEN_SEXT__ETC___d891 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d865; + IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d887 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861; 2'b01: - IF_mmioPlatform_reqSz_83_EQ_0b10_90_THEN_SEXT__ETC___d891 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d877; + IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d887 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873; 2'b10: - IF_mmioPlatform_reqSz_83_EQ_0b10_90_THEN_SEXT__ETC___d891 = - { {32{w18022_BITS_31_TO_0__q7[31]}}, w18022_BITS_31_TO_0__q7 }; + IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d887 = + { {32{w18006_BITS_31_TO_0__q7[31]}}, w18006_BITS_31_TO_0__q7 }; 2'b11: - IF_mmioPlatform_reqSz_83_EQ_0b10_90_THEN_SEXT__ETC___d891 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d884; + IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d887 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d880; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d813 or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d826 or - w28023_BITS_31_TO_0__q8 or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d833) + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 or + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822 or + w28007_BITS_31_TO_0__q8 or + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829) begin case (mmioPlatform_reqSz) 2'b0: - IF_mmioPlatform_reqSz_83_EQ_0b10_90_THEN_SEXT__ETC___d893 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d813; + IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d889 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809; 2'b01: - IF_mmioPlatform_reqSz_83_EQ_0b10_90_THEN_SEXT__ETC___d893 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d826; + IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d889 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822; 2'b10: - IF_mmioPlatform_reqSz_83_EQ_0b10_90_THEN_SEXT__ETC___d893 = - { {32{w28023_BITS_31_TO_0__q8[31]}}, w28023_BITS_31_TO_0__q8 }; + IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d889 = + { {32{w28007_BITS_31_TO_0__q8[31]}}, w28007_BITS_31_TO_0__q8 }; 2'b11: - IF_mmioPlatform_reqSz_83_EQ_0b10_90_THEN_SEXT__ETC___d893 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d833; + IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d889 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829; endcase end always@(mmioPlatform_reqAmofunc or - op_result__h49194 or - w2__h48029 or - op_result__h48630 or - op_result__h49160 or - op_result__h49165 or - op_result__h49170 or - op_result__h49188 or op_result__h49175 or op_result__h49181) + op_result__h49178 or + w2__h48013 or + op_result__h48614 or + op_result__h49144 or + op_result__h49149 or + op_result__h49154 or + op_result__h49172 or op_result__h49159 or op_result__h49165) begin case (mmioPlatform_reqAmofunc) 4'd0: - IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923 = - w2__h48029; + IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 = + w2__h48013; 4'd1: - IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923 = - op_result__h48630; + IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 = + op_result__h48614; 4'd2: - IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923 = - op_result__h49160; + IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 = + op_result__h49144; 4'd3: - IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923 = - op_result__h49165; + IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 = + op_result__h49149; 4'd4: - IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923 = - op_result__h49170; + IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 = + op_result__h49154; 4'd5: - IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923 = - op_result__h49188; + IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 = + op_result__h49172; 4'd7: - IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923 = - op_result__h49175; + IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 = + op_result__h49159; 4'd8: - IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923 = - op_result__h49181; - default: IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923 = - op_result__h49194; + IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 = + op_result__h49165; + default: IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 = + op_result__h49178; endcase end always@(mmioPlatform_curReq or - result__h49673 or - result__h49718 or result__h49784 or result__h49850) + result__h49657 or + result__h49702 or result__h49768 or result__h49834) begin case (mmioPlatform_curReq[2:0]) 3'h0: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d956 = - result__h49673; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d952 = + result__h49657; 3'h2: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d956 = - result__h49718; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d952 = + result__h49702; 3'h4: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d956 = - result__h49784; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d952 = + result__h49768; 3'h6: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d956 = - result__h49850; - default: IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d956 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d952 = + result__h49834; + default: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d952 = 64'd0; endcase end always@(mmioPlatform_curReq or - result__h48073 or - result__h49215 or - result__h49281 or - result__h49347 or - result__h49413 or - result__h49479 or result__h49545 or result__h49611) + result__h48057 or + result__h49199 or + result__h49265 or + result__h49331 or + result__h49397 or + result__h49463 or result__h49529 or result__h49595) begin case (mmioPlatform_curReq[2:0]) 3'h0: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d947 = - result__h48073; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 = + result__h48057; 3'h1: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d947 = - result__h49215; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 = + result__h49199; 3'h2: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d947 = - result__h49281; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 = + result__h49265; 3'h3: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d947 = - result__h49347; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 = + result__h49331; 3'h4: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d947 = - result__h49413; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 = + result__h49397; 3'h5: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d947 = - result__h49479; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 = + result__h49463; 3'h6: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d947 = - result__h49545; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 = + result__h49529; 3'h7: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d947 = - result__h49611; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 = + result__h49595; endcase end - always@(mmioPlatform_curReq or result__h49908 or result__h49953) + always@(mmioPlatform_curReq or result__h49892 or result__h49937) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9 = - result__h49908; + result__h49892; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9 = - result__h49953; + result__h49937; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9 = 64'd0; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d947 or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d956 or + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 or + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d952 or CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9 or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d833) + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829) begin case (mmioPlatform_reqSz) 2'b0: - x__h48018 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d947; + x__h48002 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943; 2'b01: - x__h48018 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d956; + x__h48002 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d952; 2'b10: - x__h48018 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9; + x__h48002 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9; 2'b11: - x__h48018 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d833; + x__h48002 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829; endcase end always@(mmioPlatform_reqFunc) begin case (mmioPlatform_reqFunc[5:4]) 2'd0, 2'd1, 2'd2: - IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_ETC___d481 = + IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d477 = mmioPlatform_reqFunc; 2'd3: - IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_ETC___d481 = + IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d477 = { 2'd3, mmioPlatform_reqFunc[3:0] }; endcase end @@ -6891,15 +6877,15 @@ module mkProc(CLK, begin case (mmioPlatform_instSel) 1'd0: - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d991 = + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d987 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:0]; 1'd1: - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d991 = + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d987 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:32]; endcase end always@(mmioPlatform_reqFunc or - IF_IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4__ETC___d559 or + IF_IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4__ETC___d555 or core_0$RDY_mmioToPlatform_pRs_enq) begin case (mmioPlatform_reqFunc[5:4]) @@ -6907,11 +6893,11 @@ module mkProc(CLK, CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q10 = core_0$RDY_mmioToPlatform_pRs_enq; default: CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q10 = - IF_IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4__ETC___d559; + IF_IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4__ETC___d555; endcase end always@(mmioPlatform_reqFunc or - IF_mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioP_ETC___d625 or + IF_mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioP_ETC___d621 or core_0$RDY_mmioToPlatform_pRs_enq) begin case (mmioPlatform_reqFunc[5:4]) @@ -6919,315 +6905,315 @@ module mkProc(CLK, CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q11 = core_0$RDY_mmioToPlatform_pRs_enq; default: CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q11 = - IF_mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioP_ETC___d625; + IF_mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioP_ETC___d621; endcase end always@(srcRR_0 or propDstIdx_0_dummy2_1$Q_OUT or - IF_propDstIdx_0_lat_0_whas__013_THEN_propDstId_ETC___d1016 or + IF_propDstIdx_0_lat_0_whas__009_THEN_propDstId_ETC___d1012 or propDstIdx_1_dummy2_1$Q_OUT or - IF_propDstIdx_1_lat_0_whas__020_THEN_propDstId_ETC___d1023) + IF_propDstIdx_1_lat_0_whas__016_THEN_propDstId_ETC___d1019) begin case (srcRR_0) 1'd0: - SEL_ARR_propDstIdx_0_dummy2_1_read__066_AND_IF_ETC___d1097 = + SEL_ARR_propDstIdx_0_dummy2_1_read__062_AND_IF_ETC___d1093 = propDstIdx_0_dummy2_1$Q_OUT && - IF_propDstIdx_0_lat_0_whas__013_THEN_propDstId_ETC___d1016; + IF_propDstIdx_0_lat_0_whas__009_THEN_propDstId_ETC___d1012; 1'd1: - SEL_ARR_propDstIdx_0_dummy2_1_read__066_AND_IF_ETC___d1097 = + SEL_ARR_propDstIdx_0_dummy2_1_read__062_AND_IF_ETC___d1093 = propDstIdx_1_dummy2_1$Q_OUT && - IF_propDstIdx_1_lat_0_whas__020_THEN_propDstId_ETC___d1023; + IF_propDstIdx_1_lat_0_whas__016_THEN_propDstId_ETC___d1019; endcase end always@(srcRR_1_0 or propDstIdx_1_0_dummy2_1$Q_OUT or - IF_propDstIdx_1_0_lat_0_whas__187_THEN_propDst_ETC___d1190 or + IF_propDstIdx_1_0_lat_0_whas__183_THEN_propDst_ETC___d1186 or propDstIdx_1_1_dummy2_1$Q_OUT or - IF_propDstIdx_1_1_lat_0_whas__194_THEN_propDst_ETC___d1197) + IF_propDstIdx_1_1_lat_0_whas__190_THEN_propDst_ETC___d1193) begin case (srcRR_1_0) 1'd0: - SEL_ARR_propDstIdx_1_0_dummy2_1_read__330_AND__ETC___d1371 = + SEL_ARR_propDstIdx_1_0_dummy2_1_read__326_AND__ETC___d1367 = propDstIdx_1_0_dummy2_1$Q_OUT && - IF_propDstIdx_1_0_lat_0_whas__187_THEN_propDst_ETC___d1190; + IF_propDstIdx_1_0_lat_0_whas__183_THEN_propDst_ETC___d1186; 1'd1: - SEL_ARR_propDstIdx_1_0_dummy2_1_read__330_AND__ETC___d1371 = + SEL_ARR_propDstIdx_1_0_dummy2_1_read__326_AND__ETC___d1367 = propDstIdx_1_1_dummy2_1$Q_OUT && - IF_propDstIdx_1_1_lat_0_whas__194_THEN_propDst_ETC___d1197; + IF_propDstIdx_1_1_lat_0_whas__190_THEN_propDst_ETC___d1193; endcase end - always@(x__h61422 or n__read_id__h61608 or n__read_id__h61693) + always@(x__h61406 or n__read_id__h61592 or n__read_id__h61677) begin - case (x__h61422) - 1'd0: x__h61736 = n__read_id__h61608; - 1'd1: x__h61736 = n__read_id__h61693; + case (x__h61406) + 1'd0: x__h61720 = n__read_id__h61592; + 1'd1: x__h61720 = n__read_id__h61677; endcase end - always@(x__h61422 or n__read_child__h61609 or n__read_child__h61694) + always@(x__h61406 or n__read_child__h61593 or n__read_child__h61678) begin - case (x__h61422) - 1'd0: x__h61743 = n__read_child__h61609; - 1'd1: x__h61743 = n__read_child__h61694; + case (x__h61406) + 1'd0: x__h61727 = n__read_child__h61593; + 1'd1: x__h61727 = n__read_child__h61678; endcase end - always@(x__h61422 or - propDstData_0_dummy2_1_read__104_AND_IF_propDs_ETC___d1140 or - propDstData_1_dummy2_1_read__109_AND_IF_propDs_ETC___d1144) + always@(x__h61406 or + propDstData_0_dummy2_1_read__100_AND_IF_propDs_ETC___d1136 or + propDstData_1_dummy2_1_read__105_AND_IF_propDs_ETC___d1140) begin - case (x__h61422) + case (x__h61406) 1'd0: - CASE_x1422_0_propDstData_0_dummy2_1_read__104__ETC__q12 = - propDstData_0_dummy2_1_read__104_AND_IF_propDs_ETC___d1140; + CASE_x1406_0_propDstData_0_dummy2_1_read__100__ETC__q12 = + propDstData_0_dummy2_1_read__100_AND_IF_propDs_ETC___d1136; 1'd1: - CASE_x1422_0_propDstData_0_dummy2_1_read__104__ETC__q12 = - propDstData_1_dummy2_1_read__109_AND_IF_propDs_ETC___d1144; + CASE_x1406_0_propDstData_0_dummy2_1_read__100__ETC__q12 = + propDstData_1_dummy2_1_read__105_AND_IF_propDs_ETC___d1140; endcase end - always@(x__h61422 or - IF_propDstData_0_dummy2_1_read__104_THEN_IF_pr_ETC___d1120 or - IF_propDstData_1_dummy2_1_read__109_THEN_IF_pr_ETC___d1124) + always@(x__h61406 or + IF_propDstData_0_dummy2_1_read__100_THEN_IF_pr_ETC___d1116 or + IF_propDstData_1_dummy2_1_read__105_THEN_IF_pr_ETC___d1120) begin - case (x__h61422) + case (x__h61406) 1'd0: - CASE_x1422_0_IF_propDstData_0_dummy2_1_read__1_ETC__q13 = - IF_propDstData_0_dummy2_1_read__104_THEN_IF_pr_ETC___d1120; + CASE_x1406_0_IF_propDstData_0_dummy2_1_read__1_ETC__q13 = + IF_propDstData_0_dummy2_1_read__100_THEN_IF_pr_ETC___d1116; 1'd1: - CASE_x1422_0_IF_propDstData_0_dummy2_1_read__1_ETC__q13 = - IF_propDstData_1_dummy2_1_read__109_THEN_IF_pr_ETC___d1124; + CASE_x1406_0_IF_propDstData_0_dummy2_1_read__1_ETC__q13 = + IF_propDstData_1_dummy2_1_read__105_THEN_IF_pr_ETC___d1120; endcase end - always@(x__h61422 or - IF_propDstData_0_dummy2_1_read__104_THEN_IF_pr_ETC___d1130 or - IF_propDstData_1_dummy2_1_read__109_THEN_IF_pr_ETC___d1134) + always@(x__h61406 or + IF_propDstData_0_dummy2_1_read__100_THEN_IF_pr_ETC___d1126 or + IF_propDstData_1_dummy2_1_read__105_THEN_IF_pr_ETC___d1130) begin - case (x__h61422) + case (x__h61406) 1'd0: - CASE_x1422_0_IF_propDstData_0_dummy2_1_read__1_ETC__q14 = - IF_propDstData_0_dummy2_1_read__104_THEN_IF_pr_ETC___d1130; + CASE_x1406_0_IF_propDstData_0_dummy2_1_read__1_ETC__q14 = + IF_propDstData_0_dummy2_1_read__100_THEN_IF_pr_ETC___d1126; 1'd1: - CASE_x1422_0_IF_propDstData_0_dummy2_1_read__1_ETC__q14 = - IF_propDstData_1_dummy2_1_read__109_THEN_IF_pr_ETC___d1134; + CASE_x1406_0_IF_propDstData_0_dummy2_1_read__1_ETC__q14 = + IF_propDstData_1_dummy2_1_read__105_THEN_IF_pr_ETC___d1130; endcase end - always@(x__h61422 or n__read_addr__h61604 or n__read_addr__h61689) + always@(x__h61406 or n__read_addr__h61588 or n__read_addr__h61673) begin - case (x__h61422) + case (x__h61406) 1'd0: - CASE_x1422_0_n__read_addr1604_1_n__read_addr16_ETC__q15 = - n__read_addr__h61604; + CASE_x1406_0_n__read_addr1588_1_n__read_addr16_ETC__q15 = + n__read_addr__h61588; 1'd1: - CASE_x1422_0_n__read_addr1604_1_n__read_addr16_ETC__q15 = - n__read_addr__h61689; + CASE_x1406_0_n__read_addr1588_1_n__read_addr16_ETC__q15 = + n__read_addr__h61673; endcase end - always@(x__h80307 or n__read_child__h80488 or n__read_child__h80567) + always@(x__h80291 or n__read_child__h80472 or n__read_child__h80551) begin - case (x__h80307) - 1'd0: x__h82723 = n__read_child__h80488; - 1'd1: x__h82723 = n__read_child__h80567; + case (x__h80291) + 1'd0: x__h82707 = n__read_child__h80472; + 1'd1: x__h82707 = n__read_child__h80551; endcase end - always@(x__h80307 or + always@(x__h80291 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h80307) + case (x__h80291) 1'd0: - CASE_x0307_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16 = + CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[512:449] : propDstData_1_0_rl[512:449]; 1'd1: - CASE_x0307_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16 = + CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[512:449] : propDstData_1_1_rl[512:449]; endcase end - always@(x__h80307 or + always@(x__h80291 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h80307) + case (x__h80291) 1'd0: - CASE_x0307_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 = + CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[448:385] : propDstData_1_0_rl[448:385]; 1'd1: - CASE_x0307_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 = + CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[448:385] : propDstData_1_1_rl[448:385]; endcase end - always@(x__h80307 or + always@(x__h80291 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h80307) + case (x__h80291) 1'd0: - CASE_x0307_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18 = + CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[384:321] : propDstData_1_0_rl[384:321]; 1'd1: - CASE_x0307_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18 = + CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[384:321] : propDstData_1_1_rl[384:321]; endcase end - always@(x__h80307 or + always@(x__h80291 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h80307) + case (x__h80291) 1'd0: - CASE_x0307_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 = + CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[320:257] : propDstData_1_0_rl[320:257]; 1'd1: - CASE_x0307_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 = + CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[320:257] : propDstData_1_1_rl[320:257]; endcase end - always@(x__h80307 or + always@(x__h80291 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h80307) + case (x__h80291) 1'd0: - CASE_x0307_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20 = + CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[256:193] : propDstData_1_0_rl[256:193]; 1'd1: - CASE_x0307_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20 = + CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[256:193] : propDstData_1_1_rl[256:193]; endcase end - always@(x__h80307 or + always@(x__h80291 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h80307) + case (x__h80291) 1'd0: - CASE_x0307_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 = + CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[192:129] : propDstData_1_0_rl[192:129]; 1'd1: - CASE_x0307_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 = + CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[192:129] : propDstData_1_1_rl[192:129]; endcase end - always@(x__h80307 or + always@(x__h80291 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h80307) + case (x__h80291) 1'd0: - CASE_x0307_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22 = + CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[128:65] : propDstData_1_0_rl[128:65]; 1'd1: - CASE_x0307_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22 = + CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[128:65] : propDstData_1_1_rl[128:65]; endcase end - always@(x__h80307 or + always@(x__h80291 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h80307) + case (x__h80291) 1'd0: - CASE_x0307_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 = + CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[64:1] : propDstData_1_0_rl[64:1]; 1'd1: - CASE_x0307_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 = + CASE_x0291_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[64:1] : propDstData_1_1_rl[64:1]; endcase end - always@(x__h80307 or + always@(x__h80291 or propDstData_1_0_dummy2_1$Q_OUT or - IF_propDstData_1_0_lat_0_whas__202_THEN_propDs_ETC___d1212 or + IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1208 or propDstData_1_1_dummy2_1$Q_OUT or - IF_propDstData_1_1_lat_0_whas__240_THEN_propDs_ETC___d1250) + IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1246) begin - case (x__h80307) + case (x__h80291) 1'd0: - CASE_x0307_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24 = + CASE_x0291_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24 = propDstData_1_0_dummy2_1$Q_OUT ? - IF_propDstData_1_0_lat_0_whas__202_THEN_propDs_ETC___d1212 : + IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1208 : 2'd0; 1'd1: - CASE_x0307_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24 = + CASE_x0291_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24 = propDstData_1_1_dummy2_1$Q_OUT ? - IF_propDstData_1_1_lat_0_whas__240_THEN_propDs_ETC___d1250 : + IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1246 : 2'd0; endcase end - always@(x__h80307 or - NOT_propDstData_1_0_dummy2_1_read__378_389_OR__ETC___d1390 or - NOT_propDstData_1_1_dummy2_1_read__380_391_OR__ETC___d1392) + always@(x__h80291 or + NOT_propDstData_1_0_dummy2_1_read__374_385_OR__ETC___d1386 or + NOT_propDstData_1_1_dummy2_1_read__376_387_OR__ETC___d1388) begin - case (x__h80307) + case (x__h80291) 1'd0: - CASE_x0307_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25 = - NOT_propDstData_1_0_dummy2_1_read__378_389_OR__ETC___d1390; + CASE_x0291_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25 = + NOT_propDstData_1_0_dummy2_1_read__374_385_OR__ETC___d1386; 1'd1: - CASE_x0307_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25 = - NOT_propDstData_1_1_dummy2_1_read__380_391_OR__ETC___d1392; + CASE_x0291_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25 = + NOT_propDstData_1_1_dummy2_1_read__376_387_OR__ETC___d1388; endcase end - always@(x__h80307 or n__read_addr__h80485 or n__read_addr__h80564) + always@(x__h80291 or n__read_addr__h80469 or n__read_addr__h80548) begin - case (x__h80307) + case (x__h80291) 1'd0: - CASE_x0307_0_n__read_addr0485_1_n__read_addr05_ETC__q26 = - n__read_addr__h80485; + CASE_x0291_0_n__read_addr0469_1_n__read_addr05_ETC__q26 = + n__read_addr__h80469; 1'd1: - CASE_x0307_0_n__read_addr0485_1_n__read_addr05_ETC__q26 = - n__read_addr__h80564; + CASE_x0291_0_n__read_addr0469_1_n__read_addr05_ETC__q26 = + n__read_addr__h80548; endcase end @@ -7278,7 +7264,7 @@ module mkProc(CLK, mmioPlatform_fromHostQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0; mmioPlatform_mtime <= `BSV_ASSIGNMENT_DELAY 64'd0; mmioPlatform_mtimecmp_0 <= `BSV_ASSIGNMENT_DELAY 64'd0; - mmioPlatform_mtip_0 <= `BSV_ASSIGNMENT_DELAY 1'd0; + mmioPlatform_mtip_0 <= `BSV_ASSIGNMENT_DELAY 1'd1; mmioPlatform_state <= `BSV_ASSIGNMENT_DELAY 2'd0; mmioPlatform_toHostAddr <= `BSV_ASSIGNMENT_DELAY 61'd0; mmioPlatform_toHostQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0; @@ -7643,76 +7629,76 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (EN_start) begin - v__h163702 = $stime; + v__h163686 = $stime; #0; end - v__h163696 = v__h163702 / 32'd10; + v__h163680 = v__h163686 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_start) $display("%0d: %m.method start: startpc %0h, tohostAddr %0h, fromhostAddr %0h", - v__h163696, + v__h163680, start_startpc, start_tohostAddr, start_fromhostAddr); if (RST_N != `BSV_RESET_VALUE) - if (NOT_enqDst_0_dummy2_0_read__087_088_OR_NOT_enq_ETC___d1103 && - IF_SEL_ARR_propDstIdx_0_dummy2_1_read__066_AND_ETC___d1173 && - NOT_propDstIdx_0_dummy2_1_read__066_067_OR_IF__ETC___d1100) + if (NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 && + IF_SEL_ARR_propDstIdx_0_dummy2_1_read__062_AND_ETC___d1169 && + NOT_propDstIdx_0_dummy2_1_read__062_063_OR_IF__ETC___d1096) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) - if (NOT_enqDst_0_dummy2_0_read__087_088_OR_NOT_enq_ETC___d1103 && - IF_SEL_ARR_propDstIdx_0_dummy2_1_read__066_AND_ETC___d1173 && - NOT_propDstIdx_0_dummy2_1_read__066_067_OR_IF__ETC___d1100) + if (NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 && + IF_SEL_ARR_propDstIdx_0_dummy2_1_read__062_AND_ETC___d1169 && + NOT_propDstIdx_0_dummy2_1_read__062_063_OR_IF__ETC___d1096) $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/coherence/src/CrossBar.bsv\", line 123, column 53\nsrc must be proposing"); if (RST_N != `BSV_RESET_VALUE) - if (NOT_enqDst_0_dummy2_0_read__087_088_OR_NOT_enq_ETC___d1103 && - IF_SEL_ARR_propDstIdx_0_dummy2_1_read__066_AND_ETC___d1173 && - NOT_propDstIdx_0_dummy2_1_read__066_067_OR_IF__ETC___d1100) + if (NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 && + IF_SEL_ARR_propDstIdx_0_dummy2_1_read__062_AND_ETC___d1169 && + NOT_propDstIdx_0_dummy2_1_read__062_063_OR_IF__ETC___d1096) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) - if (NOT_enqDst_0_dummy2_0_read__087_088_OR_NOT_enq_ETC___d1103 && - x__h61422 && - NOT_propDstIdx_1_dummy2_1_read__079_080_OR_IF__ETC___d1179) + if (NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 && + x__h61406 && + NOT_propDstIdx_1_dummy2_1_read__075_076_OR_IF__ETC___d1175) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) - if (NOT_enqDst_0_dummy2_0_read__087_088_OR_NOT_enq_ETC___d1103 && - x__h61422 && - NOT_propDstIdx_1_dummy2_1_read__079_080_OR_IF__ETC___d1179) + if (NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 && + x__h61406 && + NOT_propDstIdx_1_dummy2_1_read__075_076_OR_IF__ETC___d1175) $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/coherence/src/CrossBar.bsv\", line 123, column 53\nsrc must be proposing"); if (RST_N != `BSV_RESET_VALUE) - if (NOT_enqDst_0_dummy2_0_read__087_088_OR_NOT_enq_ETC___d1103 && - x__h61422 && - NOT_propDstIdx_1_dummy2_1_read__079_080_OR_IF__ETC___d1179) + if (NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 && + x__h61406 && + NOT_propDstIdx_1_dummy2_1_read__075_076_OR_IF__ETC___d1175) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) - if (NOT_enqDst_1_0_dummy2_0_read__361_362_OR_NOT_e_ETC___d1377 && - IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__330_A_ETC___d1475 && - NOT_propDstIdx_1_0_dummy2_1_read__330_331_OR_I_ETC___d1374) + if (NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 && + IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__326_A_ETC___d1471 && + NOT_propDstIdx_1_0_dummy2_1_read__326_327_OR_I_ETC___d1370) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) - if (NOT_enqDst_1_0_dummy2_0_read__361_362_OR_NOT_e_ETC___d1377 && - IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__330_A_ETC___d1475 && - NOT_propDstIdx_1_0_dummy2_1_read__330_331_OR_I_ETC___d1374) + if (NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 && + IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__326_A_ETC___d1471 && + NOT_propDstIdx_1_0_dummy2_1_read__326_327_OR_I_ETC___d1370) $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/coherence/src/CrossBar.bsv\", line 123, column 53\nsrc must be proposing"); if (RST_N != `BSV_RESET_VALUE) - if (NOT_enqDst_1_0_dummy2_0_read__361_362_OR_NOT_e_ETC___d1377 && - IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__330_A_ETC___d1475 && - NOT_propDstIdx_1_0_dummy2_1_read__330_331_OR_I_ETC___d1374) + if (NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 && + IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__326_A_ETC___d1471 && + NOT_propDstIdx_1_0_dummy2_1_read__326_327_OR_I_ETC___d1370) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) - if (NOT_enqDst_1_0_dummy2_0_read__361_362_OR_NOT_e_ETC___d1377 && - x__h80307 && - NOT_propDstIdx_1_1_dummy2_1_read__348_349_OR_I_ETC___d1481) + if (NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 && + x__h80291 && + NOT_propDstIdx_1_1_dummy2_1_read__344_345_OR_I_ETC___d1477) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) - if (NOT_enqDst_1_0_dummy2_0_read__361_362_OR_NOT_e_ETC___d1377 && - x__h80307 && - NOT_propDstIdx_1_1_dummy2_1_read__348_349_OR_I_ETC___d1481) + if (NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 && + x__h80291 && + NOT_propDstIdx_1_1_dummy2_1_read__344_345_OR_I_ETC___d1477) $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/coherence/src/CrossBar.bsv\", line 123, column 53\nsrc must be proposing"); if (RST_N != `BSV_RESET_VALUE) - if (NOT_enqDst_1_0_dummy2_0_read__361_362_OR_NOT_e_ETC___d1377 && - x__h80307 && - NOT_propDstIdx_1_1_dummy2_1_read__348_349_OR_I_ETC___d1481) + if (NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 && + x__h80291 && + NOT_propDstIdx_1_1_dummy2_1_read__344_345_OR_I_ETC___d1477) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (core_0$RDY_coreIndInv_terminate) @@ -7720,14 +7706,14 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost) begin - v__h163266 = $stime; + v__h163250 = $stime; #0; end - v__h163260 = v__h163266 / 32'd10; + v__h163244 = v__h163250 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost) $display("%0d: mmioPlatform.rl_tohost: 0x%0x (= %0d)", - v__h163260, + v__h163244, mmioPlatform_toHostQ_data_0, mmioPlatform_toHostQ_data_0); if (RST_N != `BSV_RESET_VALUE) @@ -7737,7 +7723,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0 && mmioPlatform_toHostQ_data_0[63:1] != 63'd0) - $display("FAIL %0d", failed_testnum__h163309); + $display("FAIL %0d", failed_testnum__h163293); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0) $finish(32'd0); @@ -9309,7 +9295,7 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmioPlatform_processToHost && mmioPlatform_reqFunc[5:4] == 2'd2 && !mmioPlatform_toHostQ_empty) - $display("Dynamic assertion failed: \"../../src_Core/CPU/MMIOPlatform.bsv\", line 800, column 30\nCannot write tohost when toHostQ not empty"); + $display("Dynamic assertion failed: \"../../src_Core/CPU/MMIOPlatform.bsv\", line 798, column 30\nCannot write tohost when toHostQ not empty"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processToHost && mmioPlatform_reqFunc[5:4] == 2'd2 && @@ -9326,7 +9312,7 @@ module mkProc(CLK, mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd2 && mmioPlatform_reqFunc[5:4] != 2'd1) - $display("Dynamic assertion failed: \"../../src_Core/CPU/MMIOPlatform.bsv\", line 822, column 33\nCannot do AMO on toHost"); + $display("Dynamic assertion failed: \"../../src_Core/CPU/MMIOPlatform.bsv\", line 820, column 33\nCannot do AMO on toHost"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processToHost && mmioPlatform_reqFunc[5:4] != 2'd0 && @@ -9337,37 +9323,37 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && mmioPlatform_fromHostQ_empty && - x__h42876 != 64'd0) + x__h42860 != 64'd0) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && mmioPlatform_fromHostQ_empty && - x__h42876 != 64'd0) - $display("Dynamic assertion failed: \"../../src_Core/CPU/MMIOPlatform.bsv\", line 858, column 41\nCan only write 0 to fromhost"); + x__h42860 != 64'd0) + $display("Dynamic assertion failed: \"../../src_Core/CPU/MMIOPlatform.bsv\", line 856, column 41\nCan only write 0 to fromhost"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && mmioPlatform_fromHostQ_empty && - x__h42876 != 64'd0) + x__h42860 != 64'd0) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && !mmioPlatform_fromHostQ_empty && - x__h40783 != 64'd0) + x__h40767 != 64'd0) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && !mmioPlatform_fromHostQ_empty && - x__h40783 != 64'd0) - $display("Dynamic assertion failed: \"../../src_Core/CPU/MMIOPlatform.bsv\", line 850, column 41\nCan only write 0 to fromhost"); + x__h40767 != 64'd0) + $display("Dynamic assertion failed: \"../../src_Core/CPU/MMIOPlatform.bsv\", line 848, column 41\nCan only write 0 to fromhost"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && !mmioPlatform_fromHostQ_empty && - x__h40783 != 64'd0) + x__h40767 != 64'd0) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && @@ -9380,7 +9366,7 @@ module mkProc(CLK, mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd2 && mmioPlatform_reqFunc[5:4] != 2'd1) - $display("Dynamic assertion failed: \"../../src_Core/CPU/MMIOPlatform.bsv\", line 873, column 33\nCannot do AMO on fromHost"); + $display("Dynamic assertion failed: \"../../src_Core/CPU/MMIOPlatform.bsv\", line 871, column 33\nCannot do AMO on fromHost"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] != 2'd0 && @@ -9388,7 +9374,7 @@ module mkProc(CLK, mmioPlatform_reqFunc[5:4] != 2'd1) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) - if (NOT_llc_mem_server_enqDst_0_dummy2_0_read__711_ETC___d1718 && + if (NOT_llc_mem_server_enqDst_0_dummy2_0_read__707_ETC___d1714 && !CAN_FIRE_RL_llc_mem_server_srcPropose && !llc_mem_server_propDstIdx_0_rl) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); @@ -9402,85 +9388,85 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_mem_server_sendStRespToTlb) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) begin - v__h135223 = $stime; + v__h135207 = $stime; #0; end - v__h135217 = v__h135223 / 32'd10; + v__h135201 = v__h135207 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsps: beat %0d ", - v__h135217, + v__h135201, llc_axi4_adapter_rg_rd_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[2:1]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801 && + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797 && llc_axi4_adapter_master_xactor_rg_rd_data[0]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801 && + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797 && !llc_axi4_adapter_master_xactor_rg_rd_data[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) begin - v__h135390 = $stime; + v__h135374 = $stime; #0; end - v__h135384 = v__h135390 / 32'd10; + v__h135368 = v__h135374 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsp: fabric response error; exit", - v__h135384); + v__h135368); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) @@ -9542,135 +9528,135 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(" Response to LLC: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("MemRsMsg { ", "data: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "child: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "id: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("LdMemRqId { ", "refill: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801 && + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797 && llc_axi4_adapter_f_pending_reads$D_OUT[4]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801 && + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797 && !llc_axi4_adapter_f_pending_reads$D_OUT[4]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "mshrIdx: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", llc_axi4_adapter_f_pending_reads$D_OUT[3:0], " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(" }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_wr_req_beat == 3'd0) begin - v__h137493 = $stime; + v__h137477 = $stime; #0; end - v__h137487 = v__h137493 / 32'd10; + v__h137471 = v__h137477 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_wr_req_beat == 3'd0) $display("%d: LLC_AXI4_Adapter.rl_handle_write_req: Wb request from LLC to memory:", - v__h137487); + v__h137471); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && @@ -10868,169 +10854,169 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) begin - v__h154837 = $stime; + v__h154821 = $stime; #0; end - v__h154831 = v__h154837 / 32'd10; + v__h154815 = v__h154821 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h154831); + $display("%0d: ERROR: CreditCounter: overflow", v__h154815); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) $finish(32'd1); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(" To fabric: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("AXI4_Wr_Addr { ", "awid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "awaddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) - $write("'h%h", mem_req_wr_addr_awaddr__h148748); + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + $write("'h%h", mem_req_wr_addr_awaddr__h148732); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "awlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 8'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "awsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 3'b011); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "awburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 2'b01); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "awlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 1'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "awcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 4'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "awprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 3'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "awqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "awregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "awuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 1'h0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("AXI4_Wr_Data { ", "wdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) - $write("'h%h", data64__h148663); + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + $write("'h%h", data64__h148647); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "wstrb: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) - $write("'h%h", strb8__h148664); + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + $write("'h%h", strb8__h148648); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "wlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "wuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 1'h0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_rd_req_beat == 3'd0) begin - v__h134604 = $stime; + v__h134588 = $stime; #0; end - v__h134598 = v__h134604 / 32'd10; + v__h134582 = v__h134588 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_rd_req_beat == 3'd0) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_req: Ld request from LLC to memory: beat %0d", - v__h134598, + v__h134582, llc_axi4_adapter_rg_rd_req_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && @@ -11101,159 +11087,159 @@ module mkProc(CLK, $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("AXI4_Rd_Addr { ", "arid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "araddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) - $write("'h%h", mem_req_rd_addr_araddr__h134824); + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + $write("'h%h", mem_req_rd_addr_araddr__h134808); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "arlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 8'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "arsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 3'b011); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "arburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 2'b01); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "arlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 1'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "arcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 4'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "arprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 3'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "arqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "arregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "aruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 1'h0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) begin - v__h161531 = $stime; + v__h161515 = $stime; #0; end - v__h161525 = v__h161531 / 32'd10; + v__h161509 = v__h161515 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $display("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: beat %0d ", - v__h161525, + v__h161509, llc_axi4_adapter_rg_wr_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", llc_axi4_adapter_master_xactor_rg_wr_resp[5:2]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", llc_axi4_adapter_master_xactor_rg_wr_resp[1:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) begin - v__h162039 = $stime; + v__h162023 = $stime; #0; end - v__h162033 = v__h162039 / 32'd10; + v__h162017 = v__h162023 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) $display("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: fabric response error: exit", - v__h162033); + v__h162017); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) diff --git a/src_Core/CPU/MMIOPlatform.bsv b/src_Core/CPU/MMIOPlatform.bsv index 259825e..83cbe1b 100644 --- a/src_Core/CPU/MMIOPlatform.bsv +++ b/src_Core/CPU/MMIOPlatform.bsv @@ -288,7 +288,8 @@ module mkMMIOPlatform #(Vector#(CoreNum, MMIOCoreToPlatform) cores, // To avoid posting timer interrupt repeatedly, we keep a copy of MTIP // here. Since each core cannot write MTIP by CSRXXX inst, the only way to // change MTIP is through here. - Vector#(CoreNum, Reg#(Bool)) mtip <- replicateM(mkReg(False)); + // We initialize to True to avoid an timer interrupt at start of time. + Vector#(CoreNum, Reg#(Bool)) mtip <- replicateM(mkReg(True)); // pass mtime to each core rule propagateTime(state != Init); @@ -321,18 +322,15 @@ module mkMMIOPlatform #(Vector#(CoreNum, MMIOCoreToPlatform) cores, // check for timer interrupt Vector#(CoreNum, Bool) needTimerInt = replicate(False); for(Integer i = 0; i < valueof(CoreNum); i = i+1) begin - if(!mtip[i] - && (mtimecmp[i] <= mtime) - && (mtimecmp [i] != 0)) // Avoid interrupt until mtimecmp has actually been written - begin - cores[i].pRq.enq(MMIOPRq { - target: MTIP, - func: St, - data: 1 - }); - mtip[i] <= True; - needTimerInt[i] = True; - end + if(!mtip[i] && mtimecmp[i] <= mtime) begin + cores[i].pRq.enq(MMIOPRq { + target: MTIP, + func: St, + data: 1 + }); + mtip[i] <= True; + needTimerInt[i] = True; + end end if(needTimerInt != replicate(False)) begin state <= WaitResp; diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv index 9ad2355..c15b93b 100644 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv @@ -531,7 +531,10 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage); &&& ((dInst.iType == Csr) && ((csr == CSRfflags) || (csr == CSRfrm) || (csr == CSRfcsr)))) begin - will_dirty_fpu_state = True; + Bool is_CSRR_W = (dInst.execFunc == tagged Alu Csrw); + Bool rs1_is_0 = ((arch_regs.src2 == tagged Valid (tagged Gpr 0)) + || (dInst.imm == tagged Valid 0)); + will_dirty_fpu_state = (is_CSRR_W || (! rs1_is_0)); end RobInstState rob_inst_state = to_exec ? NotDone : Executed; diff --git a/src_SSITH_P3/Verilog_RTL/mkCore.v b/src_SSITH_P3/Verilog_RTL/mkCore.v index 7bcc820..5e6fe7f 100644 --- a/src_SSITH_P3/Verilog_RTL/mkCore.v +++ b/src_SSITH_P3/Verilog_RTL/mkCore.v @@ -4517,13 +4517,13 @@ module mkCore(CLK, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2875, addr__h290070, curData__h192919, - data_out__h738236, - data_warl_xformed__h723335, + data_out__h738339, + data_warl_xformed__h723438, rVal1__h609054, rVal1__h633783, - trap_val__h711388, + trap_val__h711491, x__h197129, - x__h723943; + x__h724046; reg [51 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q19, @@ -4604,7 +4604,7 @@ module mkCore(CLK, CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q298, CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q294, IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d12883, - IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13589; + IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13599; reg [15 : 0] SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359, SEL_ARR_mmio_dataRespQ_data_0_101_BITS_15_TO_0_ETC___d1407; reg [11 : 0] CASE_commitStage_f_rob_dataD_OUT_BITS_180_TO__ETC__q279, @@ -4694,9 +4694,9 @@ module mkCore(CLK, reg [5 : 0] CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q280, CASE_mmio_cRqQ_data_0_BITS_77_TO_76_0_mmio_cRq_ETC__q9, CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q276, - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988; - reg [4 : 0] IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14133, - IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14266; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998; + reg [4 : 0] IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14143, + IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14276; reg [3 : 0] CASE_checkForException_3008_BITS_3_TO_0_0_chec_ETC__q234, CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q250, CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q251, @@ -4710,11 +4710,11 @@ module mkCore(CLK, CASE_v_f_to_TV_0D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q7, CASE_v_f_to_TV_1D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q2, CASE_v_f_to_TV_1D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q3, - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14136, + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14146, IF_fetchStage_pipelines_0_first__2757_BIT_68_2_ETC___d13130, - IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14267, - i__h710364, - i__h710524; + IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14277, + i__h710467, + i__h710627; reg [2 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q284, CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q230, CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q281, @@ -4763,7 +4763,7 @@ module mkCore(CLK, CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q243, CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q244, CASE_fetchStage_pipelines_0_canDeq__2755_AND_N_ETC__q241, - CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q240, + CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q239, CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q237, CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q238, CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q242, @@ -4806,7 +4806,7 @@ module mkCore(CLK, CASE_guard91798_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91, CASE_guard91798_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90, CASE_guard93571_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145, - CASE_k70531_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239, + CASE_k70634_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q240, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6446, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6459, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6463, @@ -4845,31 +4845,31 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d8396, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d8409, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d8428, - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13466, - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13524, - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14127, - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14130, - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13470, - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13494, - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13529, - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13855, - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13877, - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13895, - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13950, - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13952, - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13966, - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13973, - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d14049, - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d14061, - IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14264, - IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14265, - IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13907, - IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14046, - IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14073, - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__344_ETC___d13487, - SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__275_ETC___d14007, - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3443_co_ETC___d13453, - SEL_ARR_fetchStage_pipelines_0_canDeq__2755_AN_ETC___d13777; + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13476, + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13534, + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14137, + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14140, + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13480, + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13504, + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13539, + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13865, + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13887, + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13905, + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13960, + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13962, + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13976, + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13983, + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d14059, + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d14071, + IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14274, + IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14275, + IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13917, + IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14056, + IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14083, + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__345_ETC___d13497, + SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__275_ETC___d14017, + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463, + SEL_ARR_fetchStage_pipelines_0_canDeq__2755_AN_ETC___d13787; wire [581 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3247; wire [569 : 0] IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2510, IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2521, @@ -4878,24 +4878,25 @@ module mkCore(CLK, wire [517 : 0] SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2945; wire [511 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2208, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2938, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16071; - wire [463 : 0] commitStage_f_rob_data_first__4760_BIT_167_485_ETC___d14932; - wire [457 : 0] rob_deqPort_0_deq_data__4344_BITS_161_TO_98_43_ETC___d15316; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16081; + wire [463 : 0] commitStage_f_rob_data_first__4770_BIT_167_486_ETC___d14942; + wire [457 : 0] rob_deqPort_0_deq_data__4354_BITS_161_TO_98_43_ETC___d15326; wire [447 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2008; - wire [393 : 0] IF_commitStage_f_rob_data_first__4760_BITS_97__ETC___d14931; + wire [393 : 0] IF_commitStage_f_rob_data_first__4770_BITS_97__ETC___d14941; wire [383 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2203, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2929, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16062; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16072; wire [321 : 0] basicExec___d11943, basicExec___d12617; wire [319 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2003; wire [255 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2198, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2920, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16053; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16063; wire [191 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1998; + wire [181 : 0] fetchStage_pipelines_0_first__2757_BIT_173_288_ETC___d13411; wire [144 : 0] coreFix_memExe_lsq_getOrigBE_coreFix_memExe_re_ETC___d1706; wire [68 : 0] execFpuSimple___d11056; wire [65 : 0] IF_IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_NOT_ETC___d627, - IF_rob_deqPort_0_deq_data__4344_BITS_97_TO_96__ETC___d14517; + IF_rob_deqPort_0_deq_data__4354_BITS_97_TO_96__ETC___d14527; wire [64 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2570; wire [63 : 0] IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9173, IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12448, @@ -4927,7 +4928,7 @@ module mkCore(CLK, IF_coreFix_memExe_lsq_firstLd__277_BIT_96_342__ETC___d1378, IF_coreFix_memExe_lsq_firstLd__277_BIT_96_342__ETC___d1425, IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8, - IF_rob_deqPort_0_deq_data__4344_BITS_329_TO_32_ETC___d15196, + IF_rob_deqPort_0_deq_data__4354_BITS_329_TO_32_ETC___d15206, _theResult___fst__h603374, _theResult___snd__h603375, a___1__h603093, @@ -4937,9 +4938,9 @@ module mkCore(CLK, b___1__h603094, b___1__h603424, b__h602953, - base__h713309, - base__h713329, - commitStage_rg_serial_num_4333_PLUS_IF_rob_deq_ETC___d15459, + base__h713412, + base__h713432, + commitStage_rg_serial_num_4343_PLUS_IF_rob_deq_ETC___d15469, data___1__h475012, data___1__h475820, data__h475286, @@ -4959,10 +4960,10 @@ module mkCore(CLK, n__read__h611359, n__read__h611550, n__read__h6761, - n__read__h727564, - new_mstatus___1__h726926, - next_pc__h723361, - pc__h713293, + n__read__h727667, + new_mstatus___1__h727029, + next_pc__h723464, + pc__h713396, q___1__h475885, rVal1__h481765, rVal2__h481766, @@ -4984,11 +4985,11 @@ module mkCore(CLK, sip_csr__read__h610020, sstatus_csr__read__h609576, stvec_csr__read__h609689, - trap_val__h710350, + trap_val__h710453, upd__h3994, upd__h5311, upd__h6875, - upd__h727675, + upd__h727778, v__h607938, v__h632822, x__h153734, @@ -5011,18 +5012,18 @@ module mkCore(CLK, x__h617236, x__h639745, x__h639746, - x__h703283, - x__h715551, - x__h715743, - x__h726917, - x__h727058, - x__h733638, + x__h703386, + x__h715654, + x__h715846, + x__h727020, + x__h727161, + x__h733741, x_addr__h314077, x_quotient__h475200, x_reg_ifc__read__h609485, x_remainder__h475201, - y__h731332, - y__h734147, + y__h731435, + y__h734250, y_avValue__h180567, y_avValue__h181173, y_avValue__h478810, @@ -5032,15 +5033,15 @@ module mkCore(CLK, y_avValue__h615060, y_avValue__h633575, y_avValue__h637580, - y_avValue_new_pc__h713085, - y_avValue_new_pc__h713271, - y_avValue_snd_snd_snd_snd_snd_fst__h731355, - y_avValue_snd_snd_snd_snd_snd_fst__h734208, - y_avValue_snd_snd_snd_snd_snd_fst__h734244, - y_avValue_snd_snd_snd_snd_snd_snd_snd__h733620; + y_avValue_new_pc__h713188, + y_avValue_new_pc__h713374, + y_avValue_snd_snd_snd_snd_snd_fst__h731458, + y_avValue_snd_snd_snd_snd_snd_fst__h734311, + y_avValue_snd_snd_snd_snd_snd_fst__h734347, + y_avValue_snd_snd_snd_snd_snd_snd_snd__h733723; wire [62 : 0] IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10652, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9882, - IF_csrf_prv_reg_read__2787_ULE_1_4701_AND_IF_c_ETC___d14925, + IF_csrf_prv_reg_read__2787_ULE_1_4711_AND_IF_c_ETC___d14935, r1__read__h613053, r1__read__h613457, r1__read__h613967, @@ -5378,7 +5379,7 @@ module mkCore(CLK, wire [50 : 0] r1__read__h613067, r1__read__h614244; wire [49 : 0] r1__read__h614353; wire [48 : 0] r1__read__h613069, r1__read__h614246, r1__read__h614355; - wire [47 : 0] r1__read_BITS_61_TO_14___h726985; + wire [47 : 0] r1__read_BITS_61_TO_14___h727088; wire [46 : 0] r1__read__h613071, r1__read__h614248; wire [45 : 0] r1__read__h613073, r1__read__h614250; wire [44 : 0] r1__read__h613075, r1__read__h614252; @@ -5386,8 +5387,8 @@ module mkCore(CLK, wire [42 : 0] r1__read__h614256; wire [41 : 0] r1__read__h614258; wire [40 : 0] r1__read__h614260; - wire [37 : 0] IF_fetchStage_pipelines_0_first__2757_BIT_160__ETC___d14139, - IF_fetchStage_pipelines_1_first__2766_BIT_160__ETC___d14270; + wire [37 : 0] IF_fetchStage_pipelines_0_first__2757_BIT_160__ETC___d14149, + IF_fetchStage_pipelines_1_first__2766_BIT_160__ETC___d14280; wire [31 : 0] IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q133, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q12, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q11, @@ -5402,11 +5403,11 @@ module mkCore(CLK, x__h429285, x__h76239, x_data__h66088, - x_data_imm__h677563, - x_data_imm__h693617; + x_data_imm__h677666, + x_data_imm__h693720; wire [29 : 0] r1__read__h613081, r1__read__h614264; wire [27 : 0] r1__read__h614266; - wire [24 : 0] NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14171, + wire [24 : 0] NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14181, sfd__h354292, sfd__h362874, sfd__h372058, @@ -5514,9 +5515,9 @@ module mkCore(CLK, pend_ints__h651121, y__h651660; wire [13 : 0] r1__read_BITS_13_TO_0___h651670; - wire [12 : 0] IF_rob_deqPort_0_deq_data__4344_BITS_329_TO_32_ETC___d15306, - fetchStage_pipelines_1_first__2766_BIT_173_359_ETC___d13681, - rob_deqPort_0_deq_data__4344_BIT_181_4419_CONC_ETC___d14510; + wire [12 : 0] IF_rob_deqPort_0_deq_data__4354_BITS_329_TO_32_ETC___d15316, + fetchStage_pipelines_1_first__2766_BIT_173_360_ETC___d13691, + rob_deqPort_0_deq_data__4354_BIT_181_4429_CONC_ETC___d14520; wire [11 : 0] IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10431, IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d8946, IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9661, @@ -5547,10 +5548,10 @@ module mkCore(CLK, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5946, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7338, csr_addr__h655332, - renaming_spec_bits__h686145, + renaming_spec_bits__h686248, result__h646700, result__h646751, - spec_bits__h689304, + spec_bits__h689407, w__h646695, x__h364471, x__h410168, @@ -5561,10 +5562,10 @@ module mkCore(CLK, x__h646699, x__h646750, y__h646729, - y__h689317, - y_avValue_fst__h682477, - y_avValue_fst__h682506, - y_avValue_fst__h682540; + y__h689420, + y_avValue_fst__h682580, + y_avValue_fst__h682609, + y_avValue_fst__h682643; wire [10 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10536, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10538, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9056, @@ -5849,11 +5850,11 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4478, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7262, IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2144, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16097, + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16107, x__h181702, - x__h713324; - wire [4 : 0] IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14311, - IF_rob_deqPort_0_canDeq__5338_THEN_IF_NOT_rob__ETC___d15665, + x__h713427; + wire [4 : 0] IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14321, + IF_rob_deqPort_0_canDeq__5348_THEN_IF_NOT_rob__ETC___d15675, _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5169, _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6561, _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7953, @@ -5870,24 +5871,24 @@ module mkCore(CLK, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6573, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7965, checkForException___d13008, - checkForException___d13703, - fflags__h734124, - old_fflags1__h733611, - po_fflags__h728848, - po_fflags__h731495, + checkForException___d13713, + fflags__h734227, + old_fflags1__h733714, + po_fflags__h728951, + po_fflags__h731598, r1__read__h614604, res_fflags__h337874, res_fflags__h383576, res_fflags__h429271, - rob_deqPort_0_deq_data__4344_BIT_166_4360_CONC_ETC___d14409, + rob_deqPort_0_deq_data__4354_BIT_166_4370_CONC_ETC___d14419, rs1__h655333, x__h153728, x__h157275, x__h160091, x__h287282, - y_avValue_fst__h730870, - y_avValue_fst__h734029, - y_avValue_fst__h734061; + y_avValue_fst__h730973, + y_avValue_fst__h734132, + y_avValue_fst__h734164; wire [3 : 0] IF_IF_coreFix_memExe_dTlb_procResp__714_BIT_18_ETC___d1851, IF_IF_coreFix_memExe_dTlb_procResp__714_BIT_18_ETC___d1853, IF_IF_coreFix_memExe_dTlb_procResp__714_BIT_18_ETC___d1855, @@ -5914,13 +5915,13 @@ module mkCore(CLK, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2836, IF_coreFix_memExe_dTlb_procResp__714_BITS_177__ETC___d1796, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1255, - cause_code__h710349, + cause_code__h710452, vm_mode_reg__read__h614207; wire [2 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2539, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2793, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1212, _theResult_____2__h296524, - dcsr_cause__h709868, + dcsr_cause__h709971, next_deqP___1__h296803, v__h295944, v__h296175, @@ -5928,7 +5929,7 @@ module mkCore(CLK, x_decodeInfo_frm__h655017; wire [1 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2789, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1208, - IF_rob_deqPort_0_canDeq__5338_THEN_IF_NOT_rob__ETC___d15684, + IF_rob_deqPort_0_canDeq__5348_THEN_IF_NOT_rob__ETC___d15694, IF_sfdin11103_BIT_4_THEN_2_ELSE_0__q139, IF_sfdin17657_BIT_33_THEN_2_ELSE_0__q74, IF_sfdin45586_BIT_33_THEN_2_ELSE_0__q99, @@ -5971,20 +5972,20 @@ module mkCore(CLK, guard__h571728, guard__h581040, guard__h590109, - prv__h735791, - prv__h735835, + prv__h735894, + prv__h735938, r1__read_BITS_13_TO_12___h655202, sbIdx__h157154, v__h603887, v__h603897, v__h604532, - x__h723465, - x__h734388, - x_prv__h713393, - x_prv__h723923, - y_avValue_snd_snd_snd_fst__h731345, - y_avValue_snd_snd_snd_fst__h734198, - y_avValue_snd_snd_snd_fst__h734234; + x__h723568, + x__h734491, + x_prv__h713496, + x_prv__h724026, + y_avValue_snd_snd_snd_fst__h731448, + y_avValue_snd_snd_snd_fst__h734301, + y_avValue_snd_snd_snd_fst__h734337; wire IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5069, IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5119, IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6461, @@ -6004,8 +6005,8 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9907, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9934, IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d13052, - IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d13761, - IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d13798, + IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d13771, + IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d13808, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10474, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10706, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10707, @@ -6060,11 +6061,11 @@ module mkCore(CLK, IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1629, IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2086, IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2103, - IF_NOT_fetchStage_pipelines_0_canDeq__2755_275_ETC___d13913, - IF_NOT_fetchStage_pipelines_0_canDeq__2755_275_ETC___d13921, - IF_NOT_fetchStage_pipelines_1_first__2766_BITS_ETC___d13836, - IF_NOT_fetchStage_pipelines_1_first__2766_BITS_ETC___d13920, - IF_NOT_rob_deqPort_1_deq_data__5346_BIT_25_534_ETC___d15675, + IF_NOT_fetchStage_pipelines_0_canDeq__2755_275_ETC___d13923, + IF_NOT_fetchStage_pipelines_0_canDeq__2755_275_ETC___d13931, + IF_NOT_fetchStage_pipelines_1_first__2766_BITS_ETC___d13846, + IF_NOT_fetchStage_pipelines_1_first__2766_BITS_ETC___d13930, + IF_NOT_rob_deqPort_1_deq_data__5356_BIT_25_535_ETC___d15685, IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10472, IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10705, IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10900, @@ -6176,18 +6177,18 @@ module mkCore(CLK, IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d3649, IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3634, IF_coreFix_memExe_respLrScAmoQ_enqReq_lat_1_wh_ETC___d3558, - IF_fetchStage_RDY_pipelines_0_first__2754_AND__ETC___d13440, - IF_fetchStage_RDY_pipelines_1_first__2765_AND__ETC___d13838, - IF_fetchStage_RDY_pipelines_1_first__2765_AND__ETC___d13910, - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13959, - IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14089, + IF_fetchStage_RDY_pipelines_0_first__2754_AND__ETC___d13450, + IF_fetchStage_RDY_pipelines_1_first__2765_AND__ETC___d13848, + IF_fetchStage_RDY_pipelines_1_first__2765_AND__ETC___d13920, + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13969, + IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14099, IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmio_c_ETC___d339, IF_mmio_cRsQ_enqReq_lat_1_whas__74_THEN_mmio_c_ETC___d783, IF_mmio_dataReqQ_enqReq_lat_1_whas__7_THEN_mmi_ETC___d46, IF_mmio_dataRespQ_enqReq_lat_1_whas__92_THEN_m_ETC___d201, IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmio_p_ETC___d642, IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_mmio_p_ETC___d491, - IF_rob_deqPort_1_canDeq__5343_THEN_IF_NOT_rob__ETC___d15676, + IF_rob_deqPort_1_canDeq__5353_THEN_IF_NOT_rob__ETC___d15686, NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5221, NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5249, NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d6613, @@ -6195,9 +6196,9 @@ module mkCore(CLK, NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d8005, NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d8033, NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13344, - NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13427, - NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13730, - NOT_IF_NOT_rob_deqPort_0_canDeq__5338_5339_OR__ETC___d15681, + NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13437, + NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13740, + NOT_IF_NOT_rob_deqPort_0_canDeq__5348_5349_OR__ETC___d15691, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10056, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10765, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10807, @@ -6211,13 +6212,13 @@ module mkCore(CLK, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11006, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8556, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9286, - NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13489, - NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14629, - NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14636, - NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14700, - NOT_commitStage_rg_run_state_4350_4351_AND_NOT_ETC___d15010, - NOT_commitStage_rg_run_state_4350_4351_AND_NOT_ETC___d15021, - NOT_commitStage_rg_run_state_4350_4351_AND_NOT_ETC___d15392, + NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13499, + NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14639, + NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14646, + NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710, + NOT_commitStage_rg_run_state_4360_4361_AND_NOT_ETC___d15020, + NOT_commitStage_rg_run_state_4360_4361_AND_NOT_ETC___d15031, + NOT_commitStage_rg_run_state_4360_4361_AND_NOT_ETC___d15402, NOT_coreFix_aluExe_0_bypassWire_0_whas__2202_2_ETC___d12229, NOT_coreFix_aluExe_0_bypassWire_0_whas__2202_2_ETC___d12257, NOT_coreFix_aluExe_1_bypassWire_0_whas__1342_1_ETC___d11369, @@ -6271,36 +6272,36 @@ module mkCore(CLK, NOT_coreFix_memExe_respLrScAmoQ_enqReq_dummy2__ETC___d3589, NOT_coreFix_memExe_respLrScAmoQ_full_952_953_A_ETC___d2082, NOT_csrf_fs_reg_read__1546_EQ_0_2997_2998_OR_N_ETC___d13337, - NOT_csrf_fs_reg_read__1546_EQ_0_2997_2998_OR_N_ETC___d13425, - NOT_csrf_fs_reg_read__1546_EQ_0_2997_2998_OR_N_ETC___d13728, - NOT_csrf_prv_reg_read__2787_ULE_1_4701_4743_OR_ETC___d14747, - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13532, - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13775, - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13819, - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13874, - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13892, - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14041, - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14095, - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14194, - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14199, - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14201, - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14213, - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14257, - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14258, - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14288, + NOT_csrf_fs_reg_read__1546_EQ_0_2997_2998_OR_N_ETC___d13435, + NOT_csrf_fs_reg_read__1546_EQ_0_2997_2998_OR_N_ETC___d13738, + NOT_csrf_prv_reg_read__2787_ULE_1_4711_4753_OR_ETC___d14757, + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13542, + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13785, + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13829, + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13884, + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13902, + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14051, + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14105, + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14204, + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14209, + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14211, + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14223, + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14267, + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14268, + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14298, NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13331, - NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13471, - NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13751, - NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13757, - NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13918, - NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14102, - NOT_fetchStage_pipelines_0_first__2757_BIT_68__ETC___d13482, + NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13481, + NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13761, + NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13767, + NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13928, + NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14112, + NOT_fetchStage_pipelines_0_first__2757_BIT_68__ETC___d13492, NOT_fetchStage_pipelines_1_canDeq__2763_2764_O_ETC___d12772, - NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d13505, - NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d13744, - NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d13861, - NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d14210, - NOT_fetchStage_pipelines_1_first__2766_BIT_68__ETC___d14207, + NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d13515, + NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d13754, + NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d13871, + NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d14220, + NOT_fetchStage_pipelines_1_first__2766_BIT_68__ETC___d14217, NOT_mmio_cRqQ_clearReq_dummy2_1_read__26_27_OR_ETC___d431, NOT_mmio_cRqQ_enqReq_dummy2_2_read__32_47_OR_I_ETC___d452, NOT_mmio_cRsQ_clearReq_dummy2_1_read__18_19_OR_ETC___d823, @@ -6316,21 +6317,21 @@ module mkCore(CLK, NOT_mmio_pRqQ_enqReq_dummy2_2_read__35_50_OR_I_ETC___d755, NOT_mmio_pRsQ_clearReq_dummy2_1_read__88_89_OR_ETC___d593, NOT_mmio_pRsQ_enqReq_dummy2_2_read__94_09_OR_I_ETC___d614, - NOT_regRenamingTable_rename_0_canRename__3408__ETC___d13766, - NOT_regRenamingTable_rename_0_canRename__3408__ETC___d13842, - NOT_regRenamingTable_rename_0_canRename__3408__ETC___d14189, - NOT_regRenamingTable_rename_1_canRename__3535__ETC___d13806, + NOT_regRenamingTable_rename_0_canRename__3418__ETC___d13776, + NOT_regRenamingTable_rename_0_canRename__3418__ETC___d13852, + NOT_regRenamingTable_rename_0_canRename__3418__ETC___d14199, + NOT_regRenamingTable_rename_1_canRename__3545__ETC___d13816, NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13102, - NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13432, - NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13741, - NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13883, - NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13901, - NOT_rob_deqPort_0_canDeq__5338_5339_OR_regRena_ETC___d15380, - NOT_rob_deqPort_0_canDeq__5338_5339_OR_rob_deq_ETC___d15659, - NOT_rob_deqPort_0_deq_data__4344_BITS_329_TO_3_ETC___d14998, - NOT_rob_deqPort_1_deq_data__5346_BIT_25_5347_5_ETC___d15377, - NOT_specTagManager_canClaim__3406_3497_OR_NOT__ETC___d14012, - NOT_specTagManager_canClaim__3406_3497_OR_NOT__ETC___d14079, + NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13442, + NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13751, + NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13893, + NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13911, + NOT_rob_deqPort_0_canDeq__5348_5349_OR_rob_RDY_ETC___d15390, + NOT_rob_deqPort_0_canDeq__5348_5349_OR_rob_deq_ETC___d15669, + NOT_rob_deqPort_0_deq_data__4354_BITS_329_TO_3_ETC___d15008, + NOT_rob_deqPort_1_deq_data__5356_BIT_25_5357_5_ETC___d15387, + NOT_specTagManager_canClaim__3416_3507_OR_NOT__ETC___d14022, + NOT_specTagManager_canClaim__3416_3507_OR_NOT__ETC___d14089, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10132, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10133, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8647, @@ -6364,12 +6365,12 @@ module mkCore(CLK, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6265, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7264, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7657, - _0_OR_NOT_fetchStage_pipelines_0_first__2757_BI_ETC___d13933, - _0_OR_NOT_fetchStage_pipelines_1_first__2766_BI_ETC___d13834, - _0_OR_NOT_fetchStage_pipelines_1_first__2766_BI_ETC___d14025, - _0b0_CONCAT_csrf_external_int_pend_vec_3_read___ETC___d14329, - _0b0_CONCAT_csrf_medeleg_15_reg_read__1645_1646_ETC___d14721, - _0b0_CONCAT_csrf_mideleg_11_reg_read__1653_1654_ETC___d14703, + _0_OR_NOT_fetchStage_pipelines_0_first__2757_BI_ETC___d13943, + _0_OR_NOT_fetchStage_pipelines_1_first__2766_BI_ETC___d13844, + _0_OR_NOT_fetchStage_pipelines_1_first__2766_BI_ETC___d14035, + _0b0_CONCAT_csrf_external_int_pend_vec_3_read___ETC___d14339, + _0b0_CONCAT_csrf_medeleg_15_reg_read__1645_1646_ETC___d14731, + _0b0_CONCAT_csrf_mideleg_11_reg_read__1653_1654_ETC___d14713, _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4012, _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4013, _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5184, @@ -6395,7 +6396,7 @@ module mkCore(CLK, _dfoo16, _dfoo18, _dfoo2, - _dfoo22, + _dfoo20, _dfoo24, _dfoo26, _dfoo32, @@ -6429,7 +6430,7 @@ module mkCore(CLK, _theResult_____2__h318368, _theResult_____2__h328712, _theResult_____2__h331937, - commitStage_commitTrap_4352_BIT_36_4594_AND_co_ETC___d14659, + commitStage_commitTrap_4362_BIT_36_4604_AND_co_ETC___d14669, coreFix_aluExe_0_bypassWire_0_wget__2203_BITS__ETC___d12205, coreFix_aluExe_0_bypassWire_0_wget__2203_BITS__ETC___d12244, coreFix_aluExe_0_bypassWire_1_wget__2216_BITS__ETC___d12218, @@ -6438,7 +6439,7 @@ module mkCore(CLK, coreFix_aluExe_0_bypassWire_2_wget__2224_BITS__ETC___d12254, coreFix_aluExe_0_dispToRegQ_first__2182_BIT_13_ETC___d12267, coreFix_aluExe_0_exeToFinQ_RDY_first__2641_AND_ETC___d12680, - coreFix_aluExe_0_rsAlu_approximateCount__3447__ETC___d13449, + coreFix_aluExe_0_rsAlu_approximateCount__3457__ETC___d13459, coreFix_aluExe_1_bypassWire_0_wget__1343_BITS__ETC___d11345, coreFix_aluExe_1_bypassWire_0_wget__1343_BITS__ETC___d11384, coreFix_aluExe_1_bypassWire_1_wget__1356_BITS__ETC___d11358, @@ -6466,7 +6467,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d10936, coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d10978, coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d11020, - coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__39_ETC___d14032, + coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__39_ETC___d14042, coreFix_memExe_bypassWire_0_wget__569_BITS_70__ETC___d1571, coreFix_memExe_bypassWire_0_wget__569_BITS_70__ETC___d1609, coreFix_memExe_bypassWire_1_wget__582_BITS_70__ETC___d1584, @@ -6528,50 +6529,50 @@ module mkCore(CLK, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1263, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1267, coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2_re_ETC___d3574, - coreFix_memExe_stb_isEmpty__009_AND_coreFix_me_ETC___d14661, + coreFix_memExe_stb_isEmpty__009_AND_coreFix_me_ETC___d14671, csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13045, - csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13507, - csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13796, - csrf_prv_reg_read__2787_ULE_1_4701_AND_IF_comm_ETC___d14723, - csrf_prv_reg_read__2787_ULE_1___d14701, + csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13517, + csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13806, + csrf_prv_reg_read__2787_ULE_1_4711_AND_IF_comm_ETC___d14733, + csrf_prv_reg_read__2787_ULE_1___d14711, csrf_prv_reg_read__2787_ULT_IF_fetchStage_pipe_ETC___d13040, - csrf_rg_dcsr_read__1720_BIT_2_3062_OR_NOT_fetc_ETC___d13503, - epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13739, - epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13881, - epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13899, - f_csr_rsps_i_notFull__5791_AND_f_csr_reqs_firs_ETC___d15894, - fetchStage_RDY_pipelines_0_first__2754_AND_epo_ETC___d13309, - fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14023, - fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14105, - fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14181, - fetchStage_pipelines_0_canDeq__2755_AND_fetchS_ETC___d14093, - fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14029, - fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14036, - fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14058, - fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14070, - fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14301, - fetchStage_pipelines_0_canDeq__2755_AND_specTa_ETC___d14157, + csrf_rg_dcsr_read__1720_BIT_2_3062_OR_NOT_fetc_ETC___d13513, + epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13749, + epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13891, + epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13909, + f_csr_rsps_i_notFull__5801_AND_f_csr_reqs_firs_ETC___d15904, + fetchStage_RDY_pipelines_1_deq__2769_AND_NOT_f_ETC___d14093, + fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14033, + fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14115, + fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14191, + fetchStage_pipelines_0_canDeq__2755_AND_fetchS_ETC___d14103, + fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14039, + fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14046, + fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14068, + fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14080, + fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14311, + fetchStage_pipelines_0_canDeq__2755_AND_specTa_ETC___d14167, fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13038, - fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13750, - fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13849, - fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13961, - fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13967, - fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13984, - fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13996, - fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d14003, - fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d14019, - fetchStage_pipelines_0_first__2757_BITS_199_TO_ETC___d13514, - fetchStage_pipelines_0_first__2757_BIT_68_2786_ETC___d13840, - fetchStage_pipelines_1_first__2766_BITS_194_TO_ETC___d13978, - fetchStage_pipelines_1_first__2766_BITS_199_TO_ETC___d13990, + fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13760, + fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13859, + fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13971, + fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13977, + fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13994, + fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d14006, + fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d14013, + fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d14029, + fetchStage_pipelines_0_first__2757_BITS_199_TO_ETC___d13524, + fetchStage_pipelines_0_first__2757_BIT_68_2786_ETC___d13850, + fetchStage_pipelines_1_first__2766_BITS_194_TO_ETC___d13988, + fetchStage_pipelines_1_first__2766_BITS_199_TO_ETC___d14000, guard__h364336, guard__h410033, guard__h455728, guard__h503481, guard__h542334, guard__h581638, - idx__h686276, - k__h670531, + idx__h686379, + k__h670634, mmio_cRqQ_enqReq_dummy2_2_read__32_AND_IF_mmio_ETC___d444, mmio_cRsQ_enqReq_dummy2_2_read__24_AND_IF_mmio_ETC___d836, mmio_dataPendQ_enqReq_dummy2_2_read__00_AND_IF_ETC___d312, @@ -6580,8 +6581,8 @@ module mkCore(CLK, mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13055, mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13347, mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13365, - mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14097, - mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14099, + mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14107, + mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14109, mmio_pRqQ_enqReq_dummy2_2_read__35_AND_IF_mmio_ETC___d747, mmio_pRsQ_enqReq_dummy2_2_read__94_AND_IF_mmio_ETC___d606, msip__h76124, @@ -6591,37 +6592,37 @@ module mkCore(CLK, next_deqP___1__h328991, next_deqP___1__h332216, r1__read_BIT_20___h655898, - regRenamingTable_RDY_commit_0_commit__4943_AND_ETC___d15003, - regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13946, - regRenamingTable_RDY_rename_1_getRename__4009__ETC___d14027, - regRenamingTable_rename_0_canRename__3408_AND__ETC___d13434, - regRenamingTable_rename_0_canRename__3408_AND__ETC___d13484, - regRenamingTable_rename_0_canRename__3408_AND__ETC___d13498, - regRenamingTable_rename_0_canRename__3408_AND__ETC___d13828, - regRenamingTable_rename_0_canRename__3408_AND__ETC___d13975, - regRenamingTable_rename_0_canRename__3408_AND__ETC___d14117, - regRenamingTable_rename_0_canRename__3408_AND__ETC___d14123, - regRenamingTable_rename_0_canRename__3408_AND__ETC___d14143, - regRenamingTable_rename_0_canRename__3408_AND__ETC___d14151, - regRenamingTable_rename_0_canRename__3408_AND__ETC___d14299, - regRenamingTable_rename_1_canRename__3535_AND__ETC___d13743, - regRenamingTable_rename_1_canRename__3535_AND__ETC___d13885, - regRenamingTable_rename_1_canRename__3535_AND__ETC___d13903, - regRenamingTable_rename_1_canRename__3535_AND__ETC___d14209, - regRenamingTable_rename_1_canRename__3535_AND__ETC___d14253, + regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13309, + regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13956, + regRenamingTable_RDY_rename_1_getRename__4019__ETC___d14037, + regRenamingTable_rename_0_canRename__3418_AND__ETC___d13444, + regRenamingTable_rename_0_canRename__3418_AND__ETC___d13494, + regRenamingTable_rename_0_canRename__3418_AND__ETC___d13508, + regRenamingTable_rename_0_canRename__3418_AND__ETC___d13838, + regRenamingTable_rename_0_canRename__3418_AND__ETC___d13985, + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14127, + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14133, + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14153, + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14161, + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14309, + regRenamingTable_rename_1_canRename__3545_AND__ETC___d13753, + regRenamingTable_rename_1_canRename__3545_AND__ETC___d13895, + regRenamingTable_rename_1_canRename__3545_AND__ETC___d13913, + regRenamingTable_rename_1_canRename__3545_AND__ETC___d14219, + regRenamingTable_rename_1_canRename__3545_AND__ETC___d14263, renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_N_ETC___d13068, renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_N_ETC___d13299, - renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13764, - renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13804, - renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13845, - renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13925, - rg_core_run_state_read__3058_EQ_2_3059_AND_NOT_ETC___d15730, - rob_RDY_enqPort_1_enq__4075_AND_NOT_fetchStage_ETC___d14083, + renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13774, + renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13814, + renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13855, + renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13935, + rg_core_run_state_read__3058_EQ_2_3059_AND_NOT_ETC___d15740, + rob_RDY_deqPort_0_deq__4351_AND_rob_RDY_deqPor_ETC___d15013, sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8294, sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8295, sbCons_lazyLookup_3_get_coreFix_memExe_dispToR_ETC___d1632, - tsr_val__h727178, - tvm_val__h727180, + tsr_val__h727281, + tvm_val__h727283, v__h299289, v__h299807, v__h309803, @@ -6673,7 +6674,7 @@ module mkCore(CLK, { CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q264, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q265, !CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q266, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16071 } ; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16081 } ; assign RDY_dCacheToParent_rsToP_first = !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty ; @@ -6693,7 +6694,7 @@ module mkCore(CLK, assign dCacheToParent_rqToP_first = { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q272, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q273, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16097 } ; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16107 } ; assign RDY_dCacheToParent_rqToP_first = !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty ; @@ -9894,7 +9895,7 @@ module mkCore(CLK, // rule RL_readyToFetch assign CAN_FIRE_RL_readyToFetch = fetchStage$RDY_done_flushing && - rg_core_run_state_read__3058_EQ_2_3059_AND_NOT_ETC___d15730 && + rg_core_run_state_read__3058_EQ_2_3059_AND_NOT_ETC___d15740 && !flush_brpred && fetchStage$iMemIfc_flush_done && fetchStage$flush_predictors_done ; @@ -9994,7 +9995,7 @@ module mkCore(CLK, // rule RL_rl_debug_csr_write assign CAN_FIRE_RL_rl_debug_csr_write = f_csr_reqs$EMPTY_N && - f_csr_rsps_i_notFull__5791_AND_f_csr_reqs_firs_ETC___d15894 && + f_csr_rsps_i_notFull__5801_AND_f_csr_reqs_firs_ETC___d15904 && rg_core_run_state == 2'd1 && f_csr_reqs$D_OUT[76] ; assign WILL_FIRE_RL_rl_debug_csr_write = CAN_FIRE_RL_rl_debug_csr_write ; @@ -10352,19 +10353,19 @@ module mkCore(CLK, // rule RL_commitStage_rl_send_mip_csr_change_to_tv assign CAN_FIRE_RL_commitStage_rl_send_mip_csr_change_to_tv = v_f_to_TV_0$FULL_N && !commitStage_rg_just_after_reset && - !_0b0_CONCAT_csrf_external_int_pend_vec_3_read___ETC___d14329 ; + !_0b0_CONCAT_csrf_external_int_pend_vec_3_read___ETC___d14339 ; assign WILL_FIRE_RL_commitStage_rl_send_mip_csr_change_to_tv = CAN_FIRE_RL_commitStage_rl_send_mip_csr_change_to_tv ; // rule RL_commitStage_doCommitTrap_handle assign CAN_FIRE_RL_commitStage_doCommitTrap_handle = commitStage_f_rob_data$EMPTY_N && - NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14636 && - (commitStage_commitTrap_4352_BIT_36_4594_AND_co_ETC___d14659 || - coreFix_memExe_stb_isEmpty__009_AND_coreFix_me_ETC___d14661) && + NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14646 && + (commitStage_commitTrap_4362_BIT_36_4604_AND_co_ETC___d14669 || + coreFix_memExe_stb_isEmpty__009_AND_coreFix_me_ETC___d14671) && commitStage_commitTrap[165] && !commitStage_rg_run_state && - _0b0_CONCAT_csrf_external_int_pend_vec_3_read___ETC___d14329 ; + _0b0_CONCAT_csrf_external_int_pend_vec_3_read___ETC___d14339 ; assign WILL_FIRE_RL_commitStage_doCommitTrap_handle = CAN_FIRE_RL_commitStage_doCommitTrap_handle && !WILL_FIRE_RL_commitStage_rl_send_tv_reset && @@ -10376,8 +10377,8 @@ module mkCore(CLK, // rule RL_commitStage_doCommitKilledLd assign CAN_FIRE_RL_commitStage_doCommitKilledLd = - epochManager$RDY_incrementEpoch && rob$RDY_deqPort_0_deq && - rob$RDY_deqPort_0_deq_data && + rob$RDY_deqPort_0_deq && rob$RDY_deqPort_0_deq_data && + epochManager$RDY_incrementEpoch && !commitStage_rg_run_state && !commitStage_commitTrap[165] && !rob$deqPort_0_deq_data[167] && @@ -10413,8 +10414,8 @@ module mkCore(CLK, // rule RL_commitStage_doCommitSystemInst assign CAN_FIRE_RL_commitStage_doCommitSystemInst = coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty && - regRenamingTable_RDY_commit_0_commit__4943_AND_ETC___d15003 && - NOT_commitStage_rg_run_state_4350_4351_AND_NOT_ETC___d15021 ; + rob_RDY_deqPort_0_deq__4351_AND_rob_RDY_deqPor_ETC___d15013 && + NOT_commitStage_rg_run_state_4360_4361_AND_NOT_ETC___d15031 ; assign WILL_FIRE_RL_commitStage_doCommitSystemInst = CAN_FIRE_RL_commitStage_doCommitSystemInst && !WILL_FIRE_RL_commitStage_rl_send_tv_reset && @@ -10448,8 +10449,8 @@ module mkCore(CLK, // rule RL_commitStage_doCommitNormalInst assign CAN_FIRE_RL_commitStage_doCommitNormalInst = rob$RDY_deqPort_0_deq_data && - NOT_rob_deqPort_0_canDeq__5338_5339_OR_regRena_ETC___d15380 && - NOT_commitStage_rg_run_state_4350_4351_AND_NOT_ETC___d15392 ; + NOT_rob_deqPort_0_canDeq__5348_5349_OR_rob_RDY_ETC___d15390 && + NOT_commitStage_rg_run_state_4360_4361_AND_NOT_ETC___d15402 ; assign WILL_FIRE_RL_commitStage_doCommitNormalInst = CAN_FIRE_RL_commitStage_doCommitNormalInst && !WILL_FIRE_RL_commitStage_rl_send_tv_reset ; @@ -11417,10 +11418,9 @@ module mkCore(CLK, // rule RL_renameStage_doRenaming_Trap assign CAN_FIRE_RL_renameStage_doRenaming_Trap = - fetchStage$RDY_pipelines_0_deq && + rob$RDY_enqPort_0_enq && fetchStage$RDY_pipelines_0_deq && fetchStage$RDY_pipelines_0_first && epochManager$RDY_incrementEpoch && - rob$RDY_enqPort_0_enq && mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13055 && rob$isEmpty && rg_core_run_state == 2'd2 ; @@ -11432,8 +11432,8 @@ module mkCore(CLK, // rule RL_renameStage_doRenaming_SystemInst assign CAN_FIRE_RL_renameStage_doRenaming_SystemInst = - fetchStage$RDY_pipelines_0_deq && - fetchStage_RDY_pipelines_0_first__2754_AND_epo_ETC___d13309 && + rob$RDY_enqPort_0_enq && + regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13309 && mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13365 && rg_core_run_state == 2'd2 ; assign WILL_FIRE_RL_renameStage_doRenaming_SystemInst = @@ -11476,11 +11476,11 @@ module mkCore(CLK, // rule RL_renameStage_doRenaming assign CAN_FIRE_RL_renameStage_doRenaming = (!fetchStage$pipelines_0_canDeq || - IF_fetchStage_RDY_pipelines_0_first__2754_AND__ETC___d13440) && - IF_NOT_fetchStage_pipelines_0_canDeq__2755_275_ETC___d13913 && - IF_NOT_fetchStage_pipelines_0_canDeq__2755_275_ETC___d13921 && - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14095 && - mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14099 ; + IF_fetchStage_RDY_pipelines_0_first__2754_AND__ETC___d13450) && + IF_NOT_fetchStage_pipelines_0_canDeq__2755_275_ETC___d13923 && + IF_NOT_fetchStage_pipelines_0_canDeq__2755_275_ETC___d13931 && + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14105 && + mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14109 ; assign WILL_FIRE_RL_renameStage_doRenaming = CAN_FIRE_RL_renameStage_doRenaming && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && @@ -11519,10 +11519,10 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_fpr_read ; assign MUX_commitStage_rg_run_state$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap_4352_BIT_36_4594_AND_co_ETC___d14659 ; + commitStage_commitTrap_4362_BIT_36_4604_AND_co_ETC___d14669 ; assign MUX_commitStage_rg_serial_num$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14700 ; + NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 ; assign MUX_commitStage_rg_serial_num$write_1__SEL_2 = WILL_FIRE_RL_commitStage_rl_send_mip_csr_change_to_tv || WILL_FIRE_RL_commitStage_doCommitSystemInst ; @@ -11718,9 +11718,9 @@ module mkCore(CLK, assign MUX_csrf_external_int_en_vec_1$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + (IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd9 || - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd22) ; assign MUX_csrf_external_int_en_vec_3$write_1__SEL_1 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11728,9 +11728,9 @@ module mkCore(CLK, assign MUX_csrf_external_int_pend_vec_1$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + (IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd16 || - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd29) ; assign MUX_csrf_external_int_pend_vec_1$write_1__SEL_2 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11739,20 +11739,20 @@ module mkCore(CLK, assign MUX_csrf_external_int_pend_vec_3$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd29 ; assign MUX_csrf_external_int_pend_vec_3$write_1__SEL_2 = WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd836 ; assign MUX_csrf_fflags_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitNormalInst && - NOT_IF_NOT_rob_deqPort_0_canDeq__5338_5339_OR__ETC___d15681 ; + NOT_IF_NOT_rob_deqPort_0_canDeq__5348_5349_OR__ETC___d15691 ; assign MUX_csrf_fflags_reg$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + (IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd0 || - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd2) ; assign MUX_csrf_fflags_reg$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11761,22 +11761,22 @@ module mkCore(CLK, assign MUX_csrf_frm_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + (IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd1 || - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd2) ; assign MUX_csrf_fs_reg$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + (IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd0 || - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd1 || - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd2 || - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd8 || - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd18) ; assign MUX_csrf_fs_reg$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11788,9 +11788,9 @@ module mkCore(CLK, assign MUX_csrf_ie_vec_0$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + (IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd8 || - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd18) ; assign MUX_csrf_ie_vec_0$write_1__SEL_2 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11800,21 +11800,21 @@ module mkCore(CLK, WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 ; assign MUX_csrf_ie_vec_1$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14700 && - csrf_prv_reg_read__2787_ULE_1_4701_AND_IF_comm_ETC___d14723 ; + NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 && + csrf_prv_reg_read__2787_ULE_1_4711_AND_IF_comm_ETC___d14733 ; assign MUX_csrf_ie_vec_3$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; assign MUX_csrf_ie_vec_3$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14700 && - NOT_csrf_prv_reg_read__2787_ULE_1_4701_4743_OR_ETC___d14747 ; + NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 && + NOT_csrf_prv_reg_read__2787_ULE_1_4711_4753_OR_ETC___d14757 ; assign MUX_csrf_ie_vec_3$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd768 ; assign MUX_csrf_mcause_code_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd27 ; assign MUX_csrf_mcause_code_reg$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11828,7 +11828,7 @@ module mkCore(CLK, assign MUX_csrf_mcycle_ehr_data_dummy2_0$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd30 ; assign MUX_csrf_medeleg_13_11_reg$write_1__SEL_1 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11836,7 +11836,7 @@ module mkCore(CLK, assign MUX_csrf_mepc_csr$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd26 ; assign MUX_csrf_mepc_csr$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11850,7 +11850,7 @@ module mkCore(CLK, assign MUX_csrf_minstret_ehr_data_dummy2_0$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd31 ; assign MUX_csrf_mpp_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; @@ -11860,7 +11860,7 @@ module mkCore(CLK, assign MUX_csrf_mtval_csr$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd28 ; assign MUX_csrf_mtval_csr$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11883,12 +11883,12 @@ module mkCore(CLK, assign MUX_csrf_rg_dcsr$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd40 ; assign MUX_csrf_rg_dpc$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd41 ; assign MUX_csrf_rg_dpc$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11914,7 +11914,7 @@ module mkCore(CLK, assign MUX_csrf_scause_code_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd14 ; assign MUX_csrf_scause_code_reg$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11925,7 +11925,7 @@ module mkCore(CLK, assign MUX_csrf_sepc_csr$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd13 ; assign MUX_csrf_sepc_csr$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11945,7 +11945,7 @@ module mkCore(CLK, assign MUX_csrf_stval_csr$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd15 ; assign MUX_csrf_stval_csr$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11956,13 +11956,13 @@ module mkCore(CLK, assign MUX_epochManager$updatePrevEpoch_0_update_1__SEL_2 = WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14102 && - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13494 ; + NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14112 && + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13504 ; assign MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2 = WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14199 && - NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d14210 && - IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13907 ; + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14209 && + NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d14220 && + IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13917 ; assign MUX_f_run_halt_rsps$enq_1__SEL_1 = WILL_FIRE_RL_rl_debug_halted || WILL_FIRE_RL_rl_debug_halt_req_already_halted ; @@ -11978,7 +11978,7 @@ module mkCore(CLK, csrf_rg_dcsr[2] ; assign MUX_renameStage_rg_m_halt_req$write_1__SEL_2 = WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14199 && + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14209 && csrf_rg_dcsr[2] ; assign MUX_rf$write_3_wr_1__SEL_1 = WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && @@ -12033,13 +12033,13 @@ module mkCore(CLK, assign MUX_commitStage_commitTrap$write_1__VAL_2 = { 1'd1, rob$deqPort_0_deq_data[425:362], - x__h703283, - rob_deqPort_0_deq_data__4344_BIT_166_4360_CONC_ETC___d14409, + x__h703386, + rob_deqPort_0_deq_data__4354_BIT_166_4370_CONC_ETC___d14419, rob$deqPort_0_deq_data[361:330] } ; assign MUX_commitStage_rg_serial_num$write_1__VAL_1 = commitStage_rg_serial_num + 64'd1 ; assign MUX_commitStage_rg_serial_num$write_1__VAL_3 = - commitStage_rg_serial_num + y__h734147 ; + commitStage_rg_serial_num + y__h734250 ; assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_1 = { fetchStage$pipelines_0_first[199:195], IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d12883, @@ -12053,8 +12053,8 @@ module mkCore(CLK, 5'd10, sbAggr$eagerLookup_0_get } ; assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_2 = - (k__h670531 == 1'd0 && - fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14105) ? + (k__h670634 == 1'd0 && + fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14115) ? { fetchStage$pipelines_0_first[199:195], IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d12883, fetchStage$pipelines_0_first[173], @@ -12068,13 +12068,13 @@ module mkCore(CLK, specTagManager$nextSpecTag, sbAggr$eagerLookup_0_get } : { fetchStage$pipelines_1_first[199:195], - IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13589, - fetchStage_pipelines_1_first__2766_BIT_173_359_ETC___d13681, + IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13599, + fetchStage_pipelines_1_first__2766_BIT_173_360_ETC___d13691, fetchStage$pipelines_1_first[160:128], fetchStage$pipelines_1_first[255:232], regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h686145, + renaming_spec_bits__h686248, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -12240,8 +12240,8 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getRq, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getData } ; assign MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1 = - { prv__h735835, - prv__h735835 != 2'd3 && csrf_vm_mode_sv39_reg, + { prv__h735938, + prv__h735938 != 2'd3 && csrf_vm_mode_sv39_reg, csrf_mxr_reg, csrf_sum_reg, csrf_ppn_reg } ; @@ -12387,9 +12387,9 @@ module mkCore(CLK, MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_1 || MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_2 ; assign MUX_csrf_fflags_reg$write_1__VAL_1 = - csrf_fflags_reg | fflags__h734124 ; + csrf_fflags_reg | fflags__h734227 ; assign MUX_csrf_frm_reg$write_1__VAL_1 = - (IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + (IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd1) ? robdeqPort_0_deq_data_BITS_95_TO_32__q245[2:0] : robdeqPort_0_deq_data_BITS_95_TO_32__q245[7:5] ; @@ -12397,10 +12397,10 @@ module mkCore(CLK, (f_csr_reqs$D_OUT[75:64] == 12'd2) ? f_csr_reqs$D_OUT[2:0] : f_csr_reqs$D_OUT[7:5] ; - always@(IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 or + always@(IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 or robdeqPort_0_deq_data_BITS_95_TO_32__q245) begin - case (IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988) + case (IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998) 6'd0, 6'd1, 6'd2: MUX_csrf_fs_reg$write_1__VAL_2 = 2'b11; default: MUX_csrf_fs_reg$write_1__VAL_2 = robdeqPort_0_deq_data_BITS_95_TO_32__q245[14:13]; @@ -12415,55 +12415,55 @@ module mkCore(CLK, end assign MUX_csrf_ie_vec_1$write_1__VAL_1 = (rob$deqPort_0_deq_data[329:325] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + (IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd8 || - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd18)) ? robdeqPort_0_deq_data_BITS_95_TO_32__q245[1] : csrf_prev_ie_vec_1 ; assign MUX_csrf_ie_vec_3$write_1__VAL_1 = (rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd18) ? robdeqPort_0_deq_data_BITS_95_TO_32__q245[3] : csrf_prev_ie_vec_3 ; assign MUX_csrf_minstret_ehr_data_lat_0$wset_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ; assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1 = - n__read__h727564 + 64'd1 ; + n__read__h727667 + 64'd1 ; assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2 = - n__read__h727564 + { 62'd0, x__h734388 } ; + n__read__h727667 + { 62'd0, x__h734491 } ; assign MUX_csrf_mpp_reg$write_1__VAL_1 = (rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd18) ? MUX_csrf_minstret_ehr_data_lat_0$wset_1__VAL_2[12:11] : 2'd0 ; assign MUX_csrf_mtval_csr$write_1__VAL_1 = rob$deqPort_0_deq_data[95:32] ; assign MUX_csrf_prev_ie_vec_1$write_1__VAL_1 = rob$deqPort_0_deq_data[329:325] != 5'd13 || - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 != + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 != 6'd8 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 != + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 != 6'd18 || MUX_csrf_mtval_csr$write_1__VAL_1[5] ; assign MUX_csrf_prev_ie_vec_3$write_1__VAL_1 = rob$deqPort_0_deq_data[329:325] != 5'd13 || - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 != + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 != 6'd18 || MUX_csrf_mtval_csr$write_1__VAL_1[7] ; assign MUX_csrf_prv_reg$write_1__VAL_1 = (rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd40) ? MUX_csrf_mtval_csr$write_1__VAL_1[1:0] : ((rob$deqPort_0_deq_data[329:325] == 5'd19) ? - x__h723465 : + x__h723568 : csrf_mpp_reg) ; assign MUX_csrf_rg_dcsr$write_1__VAL_2 = { 32'b0, csrf_rg_dcsr[31:9], - dcsr_cause__h709868, + dcsr_cause__h709971, csrf_rg_dcsr[5:2], csrf_prv_reg } ; assign MUX_csrf_sepc_csr$write_1__VAL_1 = rob$deqPort_0_deq_data[95:32] ; @@ -12473,13 +12473,13 @@ module mkCore(CLK, amoExec___d880[0] ; assign MUX_csrf_spp_reg$write_1__VAL_1 = rob$deqPort_0_deq_data[329:325] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + (IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd8 || - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd18) && MUX_csrf_sepc_csr$write_1__VAL_1[8] ; assign MUX_csrf_stval_csr$write_1__VAL_1 = rob$deqPort_0_deq_data[95:32] ; - assign MUX_f_csr_rsps$enq_1__VAL_3 = { 1'd1, data_out__h738236 } ; + assign MUX_f_csr_rsps$enq_1__VAL_3 = { 1'd1, data_out__h738339 } ; assign MUX_f_fpr_rsps$enq_1__VAL_3 = { 1'd1, rf$read_4_rd1 } ; assign MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 = { csrf_prv_reg, @@ -12488,12 +12488,12 @@ module mkCore(CLK, csrf_sum_reg, csrf_ppn_reg } ; always@(rob$deqPort_0_deq_data or - next_pc__h723361 or csrf_sepc_csr or csrf_mepc_csr) + next_pc__h723464 or csrf_sepc_csr or csrf_mepc_csr) begin case (rob$deqPort_0_deq_data[329:325]) 5'd19: MUX_fetchStage$redirect_1__VAL_6 = csrf_sepc_csr; 5'd20: MUX_fetchStage$redirect_1__VAL_6 = csrf_mepc_csr; - default: MUX_fetchStage$redirect_1__VAL_6 = next_pc__h723361; + default: MUX_fetchStage$redirect_1__VAL_6 = next_pc__h723464; endcase end assign MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_1 = @@ -12572,7 +12572,7 @@ module mkCore(CLK, fetchStage$pipelines_0_first[194:192] != 3'd2 && fetchStage$pipelines_0_first[194:192] != 3'd3 && fetchStage$pipelines_0_first[194:192] != 3'd4, - NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14171 } ; + NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14181 } ; assign MUX_rob$enqPort_0_enq_1__VAL_2 = { fetchStage$pipelines_0_first[387:324], fetchStage$pipelines_0_first[127:96], @@ -12595,21 +12595,7 @@ module mkCore(CLK, fetchStage$pipelines_0_first[199:195], fetchStage$pipelines_0_first[75:69], 136'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, - fetchStage$pipelines_0_first[173], - IF_fetchStage_pipelines_0_first__2757_BITS_172_ETC___d12973, - 73'h1280000000000000000, - fetchStage$pipelines_0_first[323:260], - 5'd0, - fetchStage$pipelines_0_first[173] && - fetchStage$pipelines_0_first[199:195] == 5'd13 && - (fetchStage$pipelines_0_first[172:161] == 12'd1 || - fetchStage$pipelines_0_first[172:161] == 12'd2 || - fetchStage$pipelines_0_first[172:161] == 12'd3) || - fetchStage$pipelines_0_first[75] && - fetchStage$pipelines_0_first[74], - fetchStage$pipelines_0_first[194:192] != 3'd0, - 13'h1521, - specTagManager$currentSpecBits } ; + fetchStage_pipelines_0_first__2757_BIT_173_288_ETC___d13411 } ; assign MUX_rob$setExecuted_deqLSQ_2__VAL_2 = { 1'd1, CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q277 } ; @@ -12633,19 +12619,19 @@ module mkCore(CLK, 77'h0AAAAAAAAAAAAAAAAAAA, commitStage_f_rob_data$D_OUT[425:181], CASE_commitStage_f_rob_dataD_OUT_BITS_180_TO__ETC__q279, - commitStage_f_rob_data_first__4760_BIT_167_485_ETC___d14932 } ; + commitStage_f_rob_data_first__4770_BIT_167_486_ETC___d14942 } ; assign MUX_v_f_to_TV_0$enq_1__VAL_2 = { commitStage_rg_serial_num, 77'h0AAAAAAAAAAAAAAAAAAA, rob$deqPort_0_deq_data[425:182], - rob_deqPort_0_deq_data__4344_BIT_181_4419_CONC_ETC___d14510, + rob_deqPort_0_deq_data__4354_BIT_181_4429_CONC_ETC___d14520, rob$deqPort_0_deq_data[167], - rob_deqPort_0_deq_data__4344_BIT_166_4360_CONC_ETC___d14409, + rob_deqPort_0_deq_data__4354_BIT_166_4370_CONC_ETC___d14419, rob$deqPort_0_deq_data[161:98], - IF_rob_deqPort_0_deq_data__4344_BITS_97_TO_96__ETC___d14517, - po_fflags__h728848, + IF_rob_deqPort_0_deq_data__4354_BITS_97_TO_96__ETC___d14527, + po_fflags__h728951, rob$deqPort_0_deq_data[26], - new_mstatus___1__h726926, + new_mstatus___1__h727029, 258'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; assign MUX_v_f_to_TV_0$enq_1__VAL_4 = { commitStage_rg_serial_num, @@ -12655,12 +12641,12 @@ module mkCore(CLK, assign MUX_v_f_to_TV_0$enq_1__VAL_5 = { commitStage_rg_serial_num, 77'h0AAAAAAAAAAAAAAAAAAA, - x__h723943, + x__h724046, rob$deqPort_0_deq_data[361:182], - rob_deqPort_0_deq_data__4344_BIT_181_4419_CONC_ETC___d14510, + rob_deqPort_0_deq_data__4354_BIT_181_4429_CONC_ETC___d14520, rob$deqPort_0_deq_data[167], - rob_deqPort_0_deq_data__4344_BIT_166_4360_CONC_ETC___d14409, - rob_deqPort_0_deq_data__4344_BITS_161_TO_98_43_ETC___d15316 } ; + rob_deqPort_0_deq_data__4354_BIT_166_4370_CONC_ETC___d14419, + rob_deqPort_0_deq_data__4354_BITS_161_TO_98_43_ETC___d15326 } ; // inlined wires assign csrf_minstret_ehr_data_lat_0$whas = @@ -12960,7 +12946,7 @@ module mkCore(CLK, MUX_commitStage_rg_run_state$write_1__SEL_1 ; assign commitStage_rg_run_state$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap_4352_BIT_36_4594_AND_co_ETC___d14659 || + commitStage_commitTrap_4362_BIT_36_4604_AND_co_ETC___d14669 || WILL_FIRE_RL_rl_debug_resume ; // register commitStage_rg_serial_num @@ -12989,7 +12975,7 @@ module mkCore(CLK, end assign commitStage_rg_serial_num$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14700 || + NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 || WILL_FIRE_RL_commitStage_rl_send_mip_csr_change_to_tv || WILL_FIRE_RL_commitStage_doCommitSystemInst || WILL_FIRE_RL_commitStage_doCommitNormalInst || @@ -13731,7 +13717,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd772 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd22 ; // register csrf_external_int_pend_vec_0 @@ -13780,7 +13766,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd836 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd29 || EN_setMEIP ; @@ -13802,12 +13788,12 @@ module mkCore(CLK, assign csrf_fflags_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + (IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd0 || - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd2) || WILL_FIRE_RL_commitStage_doCommitNormalInst && - NOT_IF_NOT_rob_deqPort_0_canDeq__5338_5339_OR__ETC___d15681 || + NOT_IF_NOT_rob_deqPort_0_canDeq__5348_5349_OR__ETC___d15691 || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd1 || f_csr_reqs$D_OUT[75:64] == 12'd3) ; @@ -13820,9 +13806,9 @@ module mkCore(CLK, assign csrf_frm_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + (IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd1 || - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd2) || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd2 || @@ -13844,7 +13830,7 @@ module mkCore(CLK, assign csrf_fs_reg$EN = MUX_csrf_fs_reg$write_1__SEL_2 || WILL_FIRE_RL_commitStage_doCommitNormalInst && - NOT_IF_NOT_rob_deqPort_0_canDeq__5338_5339_OR__ETC___d15681 || + NOT_IF_NOT_rob_deqPort_0_canDeq__5348_5349_OR__ETC___d15691 || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd1 || f_csr_reqs$D_OUT[75:64] == 12'd2 || @@ -13878,8 +13864,8 @@ module mkCore(CLK, endcase assign csrf_ie_vec_1$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14700 && - csrf_prv_reg_read__2787_ULE_1_4701_AND_IF_comm_ETC___d14723 || + NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 && + csrf_prv_reg_read__2787_ULE_1_4711_AND_IF_comm_ETC___d14733 || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd256 || f_csr_reqs$D_OUT[75:64] == 12'd768) || @@ -13902,21 +13888,21 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14700 && - NOT_csrf_prv_reg_read__2787_ULE_1_4701_4743_OR_ETC___d14747 || + NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 && + NOT_csrf_prv_reg_read__2787_ULE_1_4711_4753_OR_ETC___d14757 || WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; // register csrf_mcause_code_reg always@(MUX_csrf_mcause_code_reg$write_1__SEL_1 or MUX_csrf_stval_csr$write_1__VAL_1 or MUX_csrf_ie_vec_3$write_1__SEL_2 or - cause_code__h710349 or + cause_code__h710452 or MUX_csrf_mcause_code_reg$write_1__SEL_3 or f_csr_reqs$D_OUT) case (1'b1) MUX_csrf_mcause_code_reg$write_1__SEL_1: csrf_mcause_code_reg$D_IN = MUX_csrf_stval_csr$write_1__VAL_1[3:0]; MUX_csrf_ie_vec_3$write_1__SEL_2: - csrf_mcause_code_reg$D_IN = cause_code__h710349; + csrf_mcause_code_reg$D_IN = cause_code__h710452; MUX_csrf_mcause_code_reg$write_1__SEL_3: csrf_mcause_code_reg$D_IN = f_csr_reqs$D_OUT[3:0]; default: csrf_mcause_code_reg$D_IN = 4'b1010 /* unspecified value */ ; @@ -13925,11 +13911,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd834 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14700 && - NOT_csrf_prv_reg_read__2787_ULE_1_4701_4743_OR_ETC___d14747 || + NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 && + NOT_csrf_prv_reg_read__2787_ULE_1_4711_4753_OR_ETC___d14757 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd27 ; // register csrf_mcause_interrupt_reg @@ -13952,11 +13938,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd834 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14700 && - NOT_csrf_prv_reg_read__2787_ULE_1_4701_4743_OR_ETC___d14747 || + NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 && + NOT_csrf_prv_reg_read__2787_ULE_1_4711_4753_OR_ETC___d14757 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd27 ; // register csrf_mcounteren_cy_reg @@ -13969,7 +13955,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd774 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd24 ; // register csrf_mcounteren_ir_reg @@ -13982,7 +13968,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd774 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd24 ; // register csrf_mcounteren_tm_reg @@ -13995,7 +13981,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd774 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd24 ; // register csrf_mcycle_ehr_data_rl @@ -14012,7 +13998,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd770 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd20 ; // register csrf_medeleg_15_reg @@ -14025,7 +14011,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd770 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd20 ; // register csrf_medeleg_9_0_reg @@ -14038,7 +14024,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd770 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd20 ; // register csrf_mepc_csr @@ -14061,11 +14047,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd833 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14700 && - NOT_csrf_prv_reg_read__2787_ULE_1_4701_4743_OR_ETC___d14747 || + NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 && + NOT_csrf_prv_reg_read__2787_ULE_1_4711_4753_OR_ETC___d14757 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd26 ; // register csrf_mideleg_11_reg @@ -14078,7 +14064,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd771 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd21 ; // register csrf_mideleg_1_0_reg @@ -14091,7 +14077,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd771 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd21 ; // register csrf_mideleg_5_3_reg @@ -14104,7 +14090,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd771 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd21 ; // register csrf_mideleg_9_7_reg @@ -14117,7 +14103,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd771 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd21 ; // register csrf_minstret_ehr_data_rl @@ -14145,8 +14131,8 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14700 && - NOT_csrf_prv_reg_read__2787_ULE_1_4701_4743_OR_ETC___d14747 || + NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 && + NOT_csrf_prv_reg_read__2787_ULE_1_4711_4753_OR_ETC___d14757 || WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; // register csrf_mprv_reg @@ -14159,7 +14145,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd18 ; // register csrf_mscratch_csr @@ -14172,19 +14158,19 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd832 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd25 ; // register csrf_mtval_csr always@(MUX_csrf_mtval_csr$write_1__SEL_1 or rob$deqPort_0_deq_data or MUX_csrf_ie_vec_3$write_1__SEL_2 or - trap_val__h710350 or + trap_val__h710453 or MUX_csrf_mtval_csr$write_1__SEL_3 or f_csr_reqs$D_OUT) case (1'b1) MUX_csrf_mtval_csr$write_1__SEL_1: csrf_mtval_csr$D_IN = rob$deqPort_0_deq_data[95:32]; - MUX_csrf_ie_vec_3$write_1__SEL_2: csrf_mtval_csr$D_IN = trap_val__h710350; + MUX_csrf_ie_vec_3$write_1__SEL_2: csrf_mtval_csr$D_IN = trap_val__h710453; MUX_csrf_mtval_csr$write_1__SEL_3: csrf_mtval_csr$D_IN = f_csr_reqs$D_OUT[63:0]; default: csrf_mtval_csr$D_IN = @@ -14194,11 +14180,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd835 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14700 && - NOT_csrf_prv_reg_read__2787_ULE_1_4701_4743_OR_ETC___d14747 || + NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 && + NOT_csrf_prv_reg_read__2787_ULE_1_4711_4753_OR_ETC___d14757 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd28 ; // register csrf_mtvec_base_hi_reg @@ -14211,7 +14197,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd773 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd23 ; // register csrf_mtvec_mode_low_reg @@ -14224,7 +14210,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd773 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd23 ; // register csrf_mxr_reg @@ -14248,7 +14234,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd384 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd17 ; // register csrf_prev_ie_vec_0 @@ -14278,8 +14264,8 @@ module mkCore(CLK, endcase assign csrf_prev_ie_vec_1$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14700 && - csrf_prv_reg_read__2787_ULE_1_4701_AND_IF_comm_ETC___d14723 || + NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 && + csrf_prv_reg_read__2787_ULE_1_4711_AND_IF_comm_ETC___d14733 || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd256 || f_csr_reqs$D_OUT[75:64] == 12'd768) || @@ -14303,28 +14289,28 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14700 && - NOT_csrf_prv_reg_read__2787_ULE_1_4701_4743_OR_ETC___d14747 || + NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 && + NOT_csrf_prv_reg_read__2787_ULE_1_4711_4753_OR_ETC___d14757 || WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; // register csrf_prv_reg always@(MUX_csrf_prv_reg$write_1__SEL_1 or MUX_csrf_prv_reg$write_1__VAL_1 or MUX_commitStage_rg_serial_num$write_1__SEL_1 or - x_prv__h713393 or + x_prv__h713496 or MUX_csrf_prv_reg$write_1__SEL_3 or f_csr_reqs$D_OUT) case (1'b1) MUX_csrf_prv_reg$write_1__SEL_1: csrf_prv_reg$D_IN = MUX_csrf_prv_reg$write_1__VAL_1; MUX_commitStage_rg_serial_num$write_1__SEL_1: - csrf_prv_reg$D_IN = x_prv__h713393; + csrf_prv_reg$D_IN = x_prv__h713496; MUX_csrf_prv_reg$write_1__SEL_3: csrf_prv_reg$D_IN = f_csr_reqs$D_OUT[1:0]; default: csrf_prv_reg$D_IN = 2'b10 /* unspecified value */ ; endcase assign csrf_prv_reg$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14700 || + NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 || WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd1968 || WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo24 ; @@ -14347,12 +14333,12 @@ module mkCore(CLK, endcase assign csrf_rg_dcsr$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap_4352_BIT_36_4594_AND_co_ETC___d14659 || + commitStage_commitTrap_4362_BIT_36_4604_AND_co_ETC___d14669 || WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd1968 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd40 ; // register csrf_rg_dpc @@ -14371,12 +14357,12 @@ module mkCore(CLK, endcase assign csrf_rg_dpc$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap_4352_BIT_36_4594_AND_co_ETC___d14659 || + commitStage_commitTrap_4362_BIT_36_4604_AND_co_ETC___d14669 || WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd1969 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd41 ; // register csrf_rg_dscratch0 @@ -14389,7 +14375,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1970 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd42 ; // register csrf_rg_dscratch1 @@ -14402,7 +14388,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1971 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd43 ; // register csrf_rg_tdata1_data @@ -14415,7 +14401,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1953 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd37 ; // register csrf_rg_tdata1_dmode @@ -14428,7 +14414,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1953 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd37 ; // register csrf_rg_tdata2 @@ -14441,7 +14427,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1954 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd38 ; // register csrf_rg_tdata3 @@ -14454,7 +14440,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1955 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd39 ; // register csrf_rg_tselect @@ -14467,20 +14453,20 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1952 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd36 ; // register csrf_scause_code_reg always@(MUX_csrf_scause_code_reg$write_1__SEL_1 or MUX_csrf_stval_csr$write_1__VAL_1 or MUX_csrf_ie_vec_1$write_1__SEL_2 or - cause_code__h710349 or + cause_code__h710452 or MUX_csrf_scause_code_reg$write_1__SEL_3 or f_csr_reqs$D_OUT) case (1'b1) MUX_csrf_scause_code_reg$write_1__SEL_1: csrf_scause_code_reg$D_IN = MUX_csrf_stval_csr$write_1__VAL_1[3:0]; MUX_csrf_ie_vec_1$write_1__SEL_2: - csrf_scause_code_reg$D_IN = cause_code__h710349; + csrf_scause_code_reg$D_IN = cause_code__h710452; MUX_csrf_scause_code_reg$write_1__SEL_3: csrf_scause_code_reg$D_IN = f_csr_reqs$D_OUT[3:0]; default: csrf_scause_code_reg$D_IN = 4'b1010 /* unspecified value */ ; @@ -14489,11 +14475,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd322 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14700 && - csrf_prv_reg_read__2787_ULE_1_4701_AND_IF_comm_ETC___d14723 || + NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 && + csrf_prv_reg_read__2787_ULE_1_4711_AND_IF_comm_ETC___d14733 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd14 ; // register csrf_scause_interrupt_reg @@ -14516,11 +14502,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd322 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14700 && - csrf_prv_reg_read__2787_ULE_1_4701_AND_IF_comm_ETC___d14723 || + NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 && + csrf_prv_reg_read__2787_ULE_1_4711_AND_IF_comm_ETC___d14733 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd14 ; // register csrf_scounteren_cy_reg @@ -14533,7 +14519,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd262 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd11 ; // register csrf_scounteren_ir_reg @@ -14546,7 +14532,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd262 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd11 ; // register csrf_scounteren_tm_reg @@ -14559,7 +14545,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd262 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd11 ; // register csrf_sepc_csr @@ -14582,11 +14568,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd321 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14700 && - csrf_prv_reg_read__2787_ULE_1_4701_AND_IF_comm_ETC___d14723 || + NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 && + csrf_prv_reg_read__2787_ULE_1_4711_AND_IF_comm_ETC___d14733 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd13 ; // register csrf_software_int_en_vec_0 @@ -14614,7 +14600,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd772 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd22 ; // register csrf_software_int_pend_vec_0 @@ -14658,7 +14644,7 @@ module mkCore(CLK, mmio_pRqQ_data_0[37:36] != 2'd1 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd29 ; // register csrf_spp_reg @@ -14676,8 +14662,8 @@ module mkCore(CLK, endcase assign csrf_spp_reg$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14700 && - csrf_prv_reg_read__2787_ULE_1_4701_AND_IF_comm_ETC___d14723 || + NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 && + csrf_prv_reg_read__2787_ULE_1_4711_AND_IF_comm_ETC___d14733 || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd256 || f_csr_reqs$D_OUT[75:64] == 12'd768) || @@ -14693,7 +14679,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd320 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd12 ; // register csrf_stats_module_doStats @@ -14704,12 +14690,12 @@ module mkCore(CLK, always@(MUX_csrf_stval_csr$write_1__SEL_1 or rob$deqPort_0_deq_data or MUX_csrf_ie_vec_1$write_1__SEL_2 or - trap_val__h710350 or + trap_val__h710453 or MUX_csrf_stval_csr$write_1__SEL_3 or f_csr_reqs$D_OUT) case (1'b1) MUX_csrf_stval_csr$write_1__SEL_1: csrf_stval_csr$D_IN = rob$deqPort_0_deq_data[95:32]; - MUX_csrf_ie_vec_1$write_1__SEL_2: csrf_stval_csr$D_IN = trap_val__h710350; + MUX_csrf_ie_vec_1$write_1__SEL_2: csrf_stval_csr$D_IN = trap_val__h710453; MUX_csrf_stval_csr$write_1__SEL_3: csrf_stval_csr$D_IN = f_csr_reqs$D_OUT[63:0]; default: csrf_stval_csr$D_IN = @@ -14719,11 +14705,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd323 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14700 && - csrf_prv_reg_read__2787_ULE_1_4701_AND_IF_comm_ETC___d14723 || + NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 && + csrf_prv_reg_read__2787_ULE_1_4711_AND_IF_comm_ETC___d14733 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd15 ; // register csrf_stvec_base_hi_reg @@ -14736,7 +14722,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd261 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd10 ; // register csrf_stvec_mode_low_reg @@ -14749,7 +14735,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd261 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd10 ; // register csrf_sum_reg @@ -14792,7 +14778,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd772 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd22 ; // register csrf_timer_int_pend_vec_0 @@ -14826,7 +14812,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd18 ; // register csrf_tvm_reg @@ -14839,7 +14825,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd18 ; // register csrf_tw_reg @@ -14852,7 +14838,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd18 ; // register csrf_vm_mode_sv39_reg @@ -14865,28 +14851,28 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd384 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd17 ; // register flush_brpred assign flush_brpred$D_IN = MUX_commitStage_rg_run_state$write_1__SEL_1 ; assign flush_brpred$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap_4352_BIT_36_4594_AND_co_ETC___d14659 || + commitStage_commitTrap_4362_BIT_36_4604_AND_co_ETC___d14669 || WILL_FIRE_RL_flushBrPred ; // register flush_caches assign flush_caches$D_IN = MUX_commitStage_rg_run_state$write_1__SEL_1 ; assign flush_caches$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap_4352_BIT_36_4594_AND_co_ETC___d14659 || + commitStage_commitTrap_4362_BIT_36_4604_AND_co_ETC___d14669 || WILL_FIRE_RL_flushCaches ; // register flush_reservation assign flush_reservation$D_IN = !MUX_flush_reservation$write_1__SEL_1 ; assign flush_reservation$EN = WILL_FIRE_RL_prepareCachesAndTlbs && flush_reservation || - WILL_FIRE_RL_commitStage_doCommitTrap_handle && _dfoo22 || + WILL_FIRE_RL_commitStage_doCommitTrap_handle && _dfoo20 || WILL_FIRE_RL_commitStage_doCommitSystemInst ; // register flush_tlbs @@ -14894,11 +14880,11 @@ module mkCore(CLK, assign flush_tlbs$EN = WILL_FIRE_RL_prepareCachesAndTlbs && flush_tlbs || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap_4352_BIT_36_4594_AND_co_ETC___d14659 || + commitStage_commitTrap_4362_BIT_36_4604_AND_co_ETC___d14669 || WILL_FIRE_RL_commitStage_doCommitSystemInst && (rob$deqPort_0_deq_data[329:325] == 5'd16 || rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd17) ; // register mmio_cRqQ_clearReq_rl @@ -15198,7 +15184,7 @@ module mkCore(CLK, WILL_FIRE_RL_renameStage_doRenaming_Trap) && csrf_rg_dcsr[2] || WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14199 && + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14209 && csrf_rg_dcsr[2] || WILL_FIRE_RL_rl_debug_resume || WILL_FIRE_RL_rl_debug_halt_req ; @@ -15232,17 +15218,17 @@ module mkCore(CLK, !MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1 ; assign update_vm_info$EN = WILL_FIRE_RL_prepareCachesAndTlbs && update_vm_info || - WILL_FIRE_RL_commitStage_doCommitTrap_handle && _dfoo22 || + WILL_FIRE_RL_commitStage_doCommitTrap_handle && _dfoo20 || WILL_FIRE_RL_commitStage_doCommitSystemInst ; // submodule commitStage_f_rob_data assign commitStage_f_rob_data$D_IN = { rob$deqPort_0_deq_data[425:182], - rob_deqPort_0_deq_data__4344_BIT_181_4419_CONC_ETC___d14510, + rob_deqPort_0_deq_data__4354_BIT_181_4429_CONC_ETC___d14520, rob$deqPort_0_deq_data[168:167], - rob_deqPort_0_deq_data__4344_BIT_166_4360_CONC_ETC___d14409, + rob_deqPort_0_deq_data__4354_BIT_166_4370_CONC_ETC___d14419, rob$deqPort_0_deq_data[161:98], - IF_rob_deqPort_0_deq_data__4344_BITS_97_TO_96__ETC___d14517, + IF_rob_deqPort_0_deq_data__4354_BITS_97_TO_96__ETC___d14527, rob$deqPort_0_deq_data[31:0] } ; assign commitStage_f_rob_data$ENQ = WILL_FIRE_RL_commitStage_doCommitTrap_flush ; @@ -15685,8 +15671,8 @@ module mkCore(CLK, // submodule coreFix_aluExe_1_rsAlu assign coreFix_aluExe_1_rsAlu$enq_x = - (k__h670531 == 1'd1 && - fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14105) ? + (k__h670634 == 1'd1 && + fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14115) ? { fetchStage$pipelines_0_first[199:195], IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d12883, fetchStage$pipelines_0_first[173], @@ -15700,13 +15686,13 @@ module mkCore(CLK, specTagManager$nextSpecTag, sbAggr$eagerLookup_0_get } : { fetchStage$pipelines_1_first[199:195], - IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13589, - fetchStage_pipelines_1_first__2766_BIT_173_359_ETC___d13681, + IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13599, + fetchStage_pipelines_1_first__2766_BIT_173_360_ETC___d13691, fetchStage$pipelines_1_first[160:128], fetchStage$pipelines_1_first[255:232], regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h686145, + renaming_spec_bits__h686248, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -16343,7 +16329,7 @@ module mkCore(CLK, // submodule coreFix_fpuMulDivExe_0_rsFpuMulDiv assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$enq_x = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3408_AND__ETC___d14117) ? + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14127) ? { IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d12883, regRenamingTable$rename_0_getRename, rob$enqPort_0_getEnqInstTag, @@ -16351,10 +16337,10 @@ module mkCore(CLK, fetchStage$pipelines_0_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_0_get } : - { IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13589, + { IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13599, regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h686145, + renaming_spec_bits__h686248, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -16453,9 +16439,9 @@ module mkCore(CLK, assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_enq = WILL_FIRE_RL_renameStage_doRenaming && (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3408_AND__ETC___d14117 || - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14199 && - regRenamingTable_rename_1_canRename__3535_AND__ETC___d14253) ; + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14127 || + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14209 && + regRenamingTable_rename_1_canRename__3545_AND__ETC___d14263) ; assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRobEnqTime = 1'd1 ; assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_doDispatch = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv ; @@ -17303,44 +17289,44 @@ module mkCore(CLK, // submodule coreFix_memExe_lsq assign coreFix_memExe_lsq$enqLd_dst = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3408_AND__ETC___d14143) ? + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14153) ? regRenamingTable$rename_0_getRename[8:0] : regRenamingTable$rename_1_getRename[8:0] ; assign coreFix_memExe_lsq$enqLd_inst_tag = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3408_AND__ETC___d14143) ? + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14153) ? rob$enqPort_0_getEnqInstTag : rob$enqPort_1_getEnqInstTag ; assign coreFix_memExe_lsq$enqLd_mem_inst = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3408_AND__ETC___d14143) ? + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14153) ? fetchStage$pipelines_0_first[191:174] : fetchStage$pipelines_1_first[191:174] ; assign coreFix_memExe_lsq$enqLd_spec_bits = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3408_AND__ETC___d14143) ? + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14153) ? specTagManager$currentSpecBits : - renaming_spec_bits__h686145 ; + renaming_spec_bits__h686248 ; assign coreFix_memExe_lsq$enqSt_dst = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3408_AND__ETC___d14151) ? + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14161) ? regRenamingTable$rename_0_getRename[8:0] : regRenamingTable$rename_1_getRename[8:0] ; assign coreFix_memExe_lsq$enqSt_inst_tag = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3408_AND__ETC___d14151) ? + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14161) ? rob$enqPort_0_getEnqInstTag : rob$enqPort_1_getEnqInstTag ; assign coreFix_memExe_lsq$enqSt_mem_inst = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3408_AND__ETC___d14151) ? + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14161) ? fetchStage$pipelines_0_first[191:174] : fetchStage$pipelines_1_first[191:174] ; assign coreFix_memExe_lsq$enqSt_spec_bits = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3408_AND__ETC___d14151) ? + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14161) ? specTagManager$currentSpecBits : - renaming_spec_bits__h686145 ; + renaming_spec_bits__h686248 ; assign coreFix_memExe_lsq$getHit_t = MUX_coreFix_memExe_lsq$getHit_1__SEL_1 ? MUX_coreFix_memExe_lsq$getHit_1__VAL_1 : @@ -17772,9 +17758,9 @@ module mkCore(CLK, // submodule coreFix_memExe_rsMem assign coreFix_memExe_rsMem$enq_x = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3408_AND__ETC___d14123) ? + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14133) ? { fetchStage$pipelines_0_first[191:189], - IF_fetchStage_pipelines_0_first__2757_BIT_160__ETC___d14139, + IF_fetchStage_pipelines_0_first__2757_BIT_160__ETC___d14149, regRenamingTable$rename_0_getRename, rob$enqPort_0_getEnqInstTag, specTagManager$currentSpecBits, @@ -17782,10 +17768,10 @@ module mkCore(CLK, specTagManager$nextSpecTag, sbAggr$eagerLookup_0_get } : { fetchStage$pipelines_1_first[191:189], - IF_fetchStage_pipelines_1_first__2766_BIT_160__ETC___d14270, + IF_fetchStage_pipelines_1_first__2766_BIT_160__ETC___d14280, regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h686145, + renaming_spec_bits__h686248, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -18013,7 +17999,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd2816 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd30 ; // submodule csrf_mcycle_ehr_data_dummy2_1 @@ -18027,7 +18013,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd2818 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd31 ; // submodule csrf_minstret_ehr_data_dummy2_1 @@ -18045,7 +18031,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd2049 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd7 ; assign csrf_stats_module_writeQ$DEQ = EN_sendDoStats ; assign csrf_stats_module_writeQ$CLR = 1'b0 ; @@ -18056,7 +18042,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd2048 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd6 ; assign csrf_terminate_module_terminateQ$DEQ = EN_coreIndInv_terminate ; assign csrf_terminate_module_terminateQ$CLR = 1'b0 ; @@ -18075,8 +18061,8 @@ module mkCore(CLK, fetchStage$pipelines_0_canDeq || WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14102 && - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13494 || + NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14112 && + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13504 || WILL_FIRE_RL_renameStage_doRenaming_SystemInst || WILL_FIRE_RL_renameStage_doRenaming_Trap ; assign epochManager$EN_updatePrevEpoch_1_update = @@ -18084,9 +18070,9 @@ module mkCore(CLK, fetchStage$pipelines_1_canDeq && !epochManager$checkEpoch_1_check || WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14199 && - NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d14210 && - IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13907 ; + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14209 && + NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d14220 && + IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13917 ; assign epochManager$EN_incrementEpoch = WILL_FIRE_RL_commitStage_doCommitTrap_flush && !rob$deqPort_0_deq_data[12] || @@ -18234,7 +18220,7 @@ module mkCore(CLK, assign fetchStage$perf_req_r = 2'h0 ; assign fetchStage$perf_setStatus_doStats = 1'b0 ; always@(MUX_commitStage_rg_serial_num$write_1__SEL_1 or - pc__h713293 or + pc__h713396 or WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or coreFix_aluExe_1_exeToFinQ$first or WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or @@ -18248,7 +18234,7 @@ module mkCore(CLK, begin case (1'b1) // synopsys parallel_case MUX_commitStage_rg_serial_num$write_1__SEL_1: - fetchStage$redirect_pc = pc__h713293; + fetchStage$redirect_pc = pc__h713396; WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T: fetchStage$redirect_pc = coreFix_aluExe_1_exeToFinQ$first[82:19]; WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T: @@ -18296,8 +18282,8 @@ module mkCore(CLK, fetchStage$pipelines_0_canDeq || WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14102 && - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13494 || + NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14112 && + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13504 || WILL_FIRE_RL_renameStage_doRenaming_SystemInst || WILL_FIRE_RL_renameStage_doRenaming_Trap ; assign fetchStage$EN_pipelines_1_deq = @@ -18305,9 +18291,9 @@ module mkCore(CLK, fetchStage$pipelines_1_canDeq && !epochManager$checkEpoch_1_check || WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14199 && - NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d14210 && - IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13907 ; + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14209 && + NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d14220 && + IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13917 ; assign fetchStage$EN_iTlbIfc_flush = WILL_FIRE_RL_prepareCachesAndTlbs && flush_tlbs || WILL_FIRE_RL_rl_debug_resume ; @@ -18347,14 +18333,14 @@ module mkCore(CLK, assign fetchStage$EN_stop = 1'b0 ; assign fetchStage$EN_setWaitRedirect = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap_4352_BIT_36_4594_AND_co_ETC___d14659 || + commitStage_commitTrap_4362_BIT_36_4604_AND_co_ETC___d14669 || WILL_FIRE_RL_commitStage_doCommitTrap_flush && !rob$deqPort_0_deq_data[12] || WILL_FIRE_RL_renameStage_doRenaming_SystemInst || WILL_FIRE_RL_renameStage_doRenaming_Trap ; assign fetchStage$EN_redirect = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14700 || + NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 || WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T || WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T || WILL_FIRE_RL_commitStage_doCommitKilledLd || @@ -18668,7 +18654,7 @@ module mkCore(CLK, assign regRenamingTable$rename_1_claimRename_r = fetchStage$pipelines_1_first[95:69] ; assign regRenamingTable$rename_1_claimRename_sb = - renaming_spec_bits__h686145 ; + renaming_spec_bits__h686248 ; assign regRenamingTable$rename_1_getRename_r = fetchStage$pipelines_1_first[95:69] ; assign regRenamingTable$specUpdate_correctSpeculation_mask = @@ -18698,8 +18684,8 @@ module mkCore(CLK, assign regRenamingTable$EN_rename_0_claimRename = WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14102 && - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13494 || + NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14112 && + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13504 || WILL_FIRE_RL_renameStage_doRenaming_SystemInst ; assign regRenamingTable$EN_rename_1_claimRename = MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2 ; @@ -18924,7 +18910,7 @@ module mkCore(CLK, fetchStage$pipelines_1_first[199:195], fetchStage$pipelines_1_first[75:69], 136'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, - fetchStage_pipelines_1_first__2766_BIT_173_359_ETC___d13681, + fetchStage_pipelines_1_first__2766_BIT_173_360_ETC___d13691, 73'h1280000000000000000, fetchStage$pipelines_1_first[323:260], 5'd0, @@ -18936,11 +18922,11 @@ module mkCore(CLK, fetchStage$pipelines_1_first[194:192] != 3'd3 && fetchStage$pipelines_1_first[194:192] != 3'd4, fetchStage$pipelines_1_first[194:192] != 3'd2 || - fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14301 || - IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14264, - IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14311, + fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14311 || + IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14274, + IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14321, 7'd32, - renaming_spec_bits__h686145 } ; + renaming_spec_bits__h686248 } ; assign rob$getOrigPC_0_get_x = coreFix_aluExe_0_dispToRegQ$first[52:41] ; assign rob$getOrigPC_1_get_x = coreFix_aluExe_1_dispToRegQ$first[52:41] ; assign rob$getOrigPC_2_get_x = 12'h0 ; @@ -19226,8 +19212,8 @@ module mkCore(CLK, assign rob$EN_enqPort_0_enq = WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14102 && - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13494 || + NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14112 && + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13504 || WILL_FIRE_RL_renameStage_doRenaming_Trap || WILL_FIRE_RL_renameStage_doRenaming_SystemInst ; assign rob$EN_enqPort_1_enq = @@ -19364,8 +19350,8 @@ module mkCore(CLK, assign sbAggr$EN_setBusy_0_set = WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14102 && - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13494 || + NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14112 && + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13504 || WILL_FIRE_RL_renameStage_doRenaming_SystemInst ; assign sbAggr$EN_setBusy_1_set = MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2 ; @@ -19479,8 +19465,8 @@ module mkCore(CLK, assign sbCons$EN_setBusy_0_set = WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14102 && - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13494 || + NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14112 && + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13504 || WILL_FIRE_RL_renameStage_doRenaming_SystemInst ; assign sbCons$EN_setBusy_1_set = MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2 ; @@ -19542,9 +19528,9 @@ module mkCore(CLK, end assign specTagManager$EN_claimSpecTag = WILL_FIRE_RL_renameStage_doRenaming && - (fetchStage_pipelines_0_canDeq__2755_AND_specTa_ETC___d14157 || - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14199 && - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14288) ; + (fetchStage_pipelines_0_canDeq__2755_AND_specTa_ETC___d14167 || + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14209 && + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14298) ; assign specTagManager$EN_specUpdate_incorrectSpeculation = WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T || WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T || @@ -19581,7 +19567,7 @@ module mkCore(CLK, end assign v_f_to_TV_0$ENQ = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14700 || + NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 || WILL_FIRE_RL_commitStage_doCommitNormalInst && rob$deqPort_0_canDeq || WILL_FIRE_RL_commitStage_rl_send_tv_reset || @@ -19592,7 +19578,7 @@ module mkCore(CLK, // submodule v_f_to_TV_1 assign v_f_to_TV_1$D_IN = - { commitStage_rg_serial_num_4333_PLUS_IF_rob_deq_ETC___d15459, + { commitStage_rg_serial_num_4343_PLUS_IF_rob_deq_ETC___d15469, 77'h0AAAAAAAAAAAAAAAAAAA, rob$deqPort_1_deq_data[425:181], CASE_robdeqPort_1_deq_data_BITS_180_TO_169_1__ETC__q300, @@ -19600,9 +19586,9 @@ module mkCore(CLK, rob$deqPort_1_deq_data[161:98], CASE_robdeqPort_1_deq_data_BITS_97_TO_96_0_ro_ETC__q301, rob$deqPort_1_deq_data[95:32], - po_fflags__h731495, + po_fflags__h731598, rob$deqPort_1_deq_data[26], - x__h733638, + x__h733741, 258'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; assign v_f_to_TV_1$ENQ = WILL_FIRE_RL_commitStage_doCommitNormalInst && @@ -19664,7 +19650,7 @@ module mkCore(CLK, { { fetchStage$pipelines_0_first[173], IF_fetchStage_pipelines_0_first__2757_BITS_172_ETC___d12973 }, fetchStage$pipelines_0_first[160], - x_data_imm__h677563 } }), + x_data_imm__h677666 } }), .checkForException_regs({ fetchStage$pipelines_0_first[95], fetchStage$pipelines_0_first[94:89], { fetchStage$pipelines_0_first[88], @@ -19676,10 +19662,10 @@ module mkCore(CLK, .checkForException_csrState({ x_decodeInfo_frm__h655017, r1__read_BITS_13_TO_12___h655202 != 2'd0, - { prv__h735791, - tvm_val__h727180, + { prv__h735894, + tvm_val__h727283, { r1__read_BIT_20___h655898, - tsr_val__h727178, + tsr_val__h727281, { csrf_mcounteren_cy_reg, csrf_mcounteren_cy_reg && csrf_scounteren_cy_reg, @@ -19691,10 +19677,10 @@ module mkCore(CLK, csrf_scounteren_tm_reg } } } } } }), .checkForException(checkForException___d13008)); module_checkForException instance_checkForException_1(.checkForException_dInst({ fetchStage$pipelines_1_first[199:195], - IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13589, - { fetchStage_pipelines_1_first__2766_BIT_173_359_ETC___d13681, + IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13599, + { fetchStage_pipelines_1_first__2766_BIT_173_360_ETC___d13691, fetchStage$pipelines_1_first[160], - x_data_imm__h693617 } }), + x_data_imm__h693720 } }), .checkForException_regs({ fetchStage$pipelines_1_first[95], fetchStage$pipelines_1_first[94:89], { fetchStage$pipelines_1_first[88], @@ -19706,10 +19692,10 @@ module mkCore(CLK, .checkForException_csrState({ x_decodeInfo_frm__h655017, r1__read_BITS_13_TO_12___h655202 != 2'd0, - { prv__h735791, - tvm_val__h727180, + { prv__h735894, + tvm_val__h727283, { r1__read_BIT_20___h655898, - tsr_val__h727178, + tsr_val__h727281, { csrf_mcounteren_cy_reg, csrf_mcounteren_cy_reg && csrf_scounteren_cy_reg, @@ -19719,7 +19705,7 @@ module mkCore(CLK, { csrf_mcounteren_tm_reg, csrf_mcounteren_tm_reg && csrf_scounteren_tm_reg } } } } } }), - .checkForException(checkForException___d13703)); + .checkForException(checkForException___d13713)); module_execFpuSimple instance_execFpuSimple_4(.execFpuSimple_fpu_inst({ coreFix_fpuMulDivExe_0_regToExeQ$first[233:229], CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q259, coreFix_fpuMulDivExe_0_regToExeQ$first[225] }), @@ -21599,7 +21585,7 @@ module mkCore(CLK, fetchStage$pipelines_0_first[231:200] == 32'h10500073 && csrf_tw_reg && csrf_prv_reg != 2'd3 ; - assign IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d13761 = + assign IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d13771 = IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[0] || IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[1] || IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[2] || @@ -21617,8 +21603,8 @@ module mkCore(CLK, IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[14] || IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[15] || checkForException___d13008[4] || - csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13507 ; - assign IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d13798 = + csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13517 ; + assign IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d13808 = IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[0] || IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[1] || IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[2] || @@ -21635,8 +21621,8 @@ module mkCore(CLK, IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[13] || IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[14] || IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[15] || - checkForException___d13703[4] || - csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13796 ; + checkForException___d13713[4] || + csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13806 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10083 = ((f2_exp__h521138 == 8'd0) ? (f2_sfd__h521139[22] ? @@ -22623,44 +22609,44 @@ module mkCore(CLK, coreFix_memExe_dTlb$procResp[12]) ? CASE_coreFix_memExe_dTlbprocResp_BITS_177_TO__ETC__q20 : CASE_coreFix_memExe_dTlbprocResp_BITS_181_TO__ETC__q21 ; - assign IF_NOT_fetchStage_pipelines_0_canDeq__2755_275_ETC___d13913 = + assign IF_NOT_fetchStage_pipelines_0_canDeq__2755_275_ETC___d13923 = ((!fetchStage$pipelines_0_canDeq || - NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13471) && + NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13481) && fetchStage$pipelines_1_canDeq) ? fetchStage$RDY_pipelines_1_first && (fetchStage$pipelines_1_first[194:192] != 3'd1 || !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first) && - IF_fetchStage_RDY_pipelines_1_first__2765_AND__ETC___d13910 : + IF_fetchStage_RDY_pipelines_1_first__2765_AND__ETC___d13920 : !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first ; - assign IF_NOT_fetchStage_pipelines_0_canDeq__2755_275_ETC___d13921 = + assign IF_NOT_fetchStage_pipelines_0_canDeq__2755_275_ETC___d13931 = ((!fetchStage$pipelines_0_canDeq || - NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13471) && + NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13481) && fetchStage$pipelines_1_canDeq) ? - IF_NOT_fetchStage_pipelines_1_first__2766_BITS_ETC___d13920 : + IF_NOT_fetchStage_pipelines_1_first__2766_BITS_ETC___d13930 : fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13918 ; - assign IF_NOT_fetchStage_pipelines_1_first__2766_BITS_ETC___d13836 = + NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13928 ; + assign IF_NOT_fetchStage_pipelines_1_first__2766_BITS_ETC___d13846 = (fetchStage$pipelines_1_first[194:192] == 3'd3 || fetchStage$pipelines_1_first[194:192] == 3'd4) ? - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13819 : + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13829 : ((fetchStage$pipelines_1_first[194:192] == 3'd2) ? (!fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first) && - (regRenamingTable_rename_0_canRename__3408_AND__ETC___d13828 || - NOT_regRenamingTable_rename_1_canRename__3535__ETC___d13806) : - _0_OR_NOT_fetchStage_pipelines_1_first__2766_BI_ETC___d13834) ; - assign IF_NOT_fetchStage_pipelines_1_first__2766_BITS_ETC___d13920 = - NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d13744 ? - IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13907 || + (regRenamingTable_rename_0_canRename__3418_AND__ETC___d13838 || + NOT_regRenamingTable_rename_1_canRename__3545__ETC___d13816) : + _0_OR_NOT_fetchStage_pipelines_1_first__2766_BI_ETC___d13844) ; + assign IF_NOT_fetchStage_pipelines_1_first__2766_BITS_ETC___d13930 = + NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d13754 ? + IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13917 || fetchStage$pipelines_0_canDeq && (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3408_AND__ETC___d13484 && - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13494 : + regRenamingTable_rename_0_canRename__3418_AND__ETC___d13494 && + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13504 : fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13918 ; + NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13928 ; assign IF_NOT_renameStage_rg_m_halt_req_2784_BIT_4_27_ETC___d13283 = NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13102 ? IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13210 : @@ -22718,7 +22704,7 @@ module mkCore(CLK, 4'd9) ? 4'd14 : 4'd15)))))))))) ; - assign IF_NOT_rob_deqPort_1_deq_data__5346_BIT_25_534_ETC___d15675 = + assign IF_NOT_rob_deqPort_1_deq_data__5356_BIT_25_535_ETC___d15685 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[329:325] == 5'd0 || @@ -22953,16 +22939,16 @@ module mkCore(CLK, checkForException___d13008[4] ? CASE_checkForException_3008_BITS_3_TO_0_0_chec_ETC__q234 : 4'd2 ; - assign IF_commitStage_f_rob_data_first__4760_BITS_97__ETC___d14931 = + assign IF_commitStage_f_rob_data_first__4770_BITS_97__ETC___d14941 = { CASE_commitStage_f_rob_dataD_OUT_BITS_97_TO_9_ETC__q249, commitStage_f_rob_data$D_OUT[95:32], 5'h0A, commitStage_f_rob_data$D_OUT[26], 64'hAAAAAAAAAAAAAAAA, - x_prv__h713393, - pc__h713293, - x__h715551, - x__h715743, + x_prv__h713496, + pc__h713396, + x__h715654, + x__h715846, commitStage_commitTrap[164:101] } ; assign IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2181_ETC___d12213 = (coreFix_aluExe_0_dispToRegQ$RDY_first && @@ -24174,10 +24160,10 @@ module mkCore(CLK, coreFix_memExe_respLrScAmoQ_enqReq_rl[64] ; assign IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8 = csrf_minstret_ehr_data_lat_0$whas ? - upd__h727675 : + upd__h727778 : csrf_minstret_ehr_data_rl ; - assign IF_csrf_prv_reg_read__2787_ULE_1_4701_AND_IF_c_ETC___d14925 = - csrf_prv_reg_read__2787_ULE_1_4701_AND_IF_comm_ETC___d14723 ? + assign IF_csrf_prv_reg_read__2787_ULE_1_4711_AND_IF_c_ETC___d14935 = + csrf_prv_reg_read__2787_ULE_1_4711_AND_IF_comm_ETC___d14733 ? { 43'd8192, csrf_mxr_reg, csrf_sum_reg, @@ -24209,73 +24195,73 @@ module mkCore(CLK, 2'd0, csrf_ie_vec_1, csrf_ie_vec_0 } ; - assign IF_fetchStage_RDY_pipelines_0_first__2754_AND__ETC___d13440 = + assign IF_fetchStage_RDY_pipelines_0_first__2754_AND__ETC___d13450 = (fetchStage$RDY_pipelines_0_first && (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3408_AND__ETC___d13434) ? + regRenamingTable_rename_0_canRename__3418_AND__ETC___d13444) ? fetchStage$RDY_pipelines_0_first : !regRenamingTable$rename_0_canRename || fetchStage$RDY_pipelines_0_first ; - assign IF_fetchStage_RDY_pipelines_1_first__2765_AND__ETC___d13838 = + assign IF_fetchStage_RDY_pipelines_1_first__2765_AND__ETC___d13848 = (fetchStage$RDY_pipelines_1_first && (fetchStage$pipelines_1_first[194:192] == 3'd0 || fetchStage$pipelines_1_first[194:192] == 3'd1)) ? (!fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first) && - (SEL_ARR_fetchStage_pipelines_0_canDeq__2755_AN_ETC___d13777 || + (SEL_ARR_fetchStage_pipelines_0_canDeq__2755_AN_ETC___d13787 || fetchStage$pipelines_1_first[194:192] == 3'd1 && - regRenamingTable_rename_0_canRename__3408_AND__ETC___d13498 || - NOT_regRenamingTable_rename_1_canRename__3535__ETC___d13806) : + regRenamingTable_rename_0_canRename__3418_AND__ETC___d13508 || + NOT_regRenamingTable_rename_1_canRename__3545__ETC___d13816) : fetchStage$RDY_pipelines_1_first && - IF_NOT_fetchStage_pipelines_1_first__2766_BITS_ETC___d13836 ; - assign IF_fetchStage_RDY_pipelines_1_first__2765_AND__ETC___d13910 = + IF_NOT_fetchStage_pipelines_1_first__2766_BITS_ETC___d13846 ; + assign IF_fetchStage_RDY_pipelines_1_first__2765_AND__ETC___d13920 = (fetchStage$RDY_pipelines_1_first && - NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d13505 && - NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d13744) ? - IF_fetchStage_RDY_pipelines_1_first__2765_AND__ETC___d13838 && - (IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13907 || + NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d13515 && + NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d13754) ? + IF_fetchStage_RDY_pipelines_1_first__2765_AND__ETC___d13848 && + (IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13917 || !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first) : !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first ; - assign IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13959 = - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13952 || - fetchStage$RDY_pipelines_0_deq && + assign IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13969 = + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13962 || + rob$RDY_enqPort_0_enq && regRenamingTable$RDY_rename_0_getRename && regRenamingTable$RDY_rename_0_claimRename && - rob$RDY_enqPort_0_enq && + fetchStage$RDY_pipelines_0_deq && (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$RDY_claimSpecTag) ; - assign IF_fetchStage_pipelines_0_first__2757_BIT_160__ETC___d14139 = + assign IF_fetchStage_pipelines_0_first__2757_BIT_160__ETC___d14149 = { fetchStage$pipelines_0_first[159:128], - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14127, - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14130 ? - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14133 : + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14137, + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14140 ? + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14143 : { 1'h0, - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14136 } } ; - assign IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14089 = - IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14046 && - IF_fetchStage_RDY_pipelines_1_first__2765_AND__ETC___d13838 && - (IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14073 || - fetchStage$RDY_pipelines_1_deq && + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14146 } } ; + assign IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14099 = + IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14056 && + IF_fetchStage_RDY_pipelines_1_first__2765_AND__ETC___d13848 && + (IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14083 || + rob$RDY_enqPort_1_enq && regRenamingTable$RDY_rename_1_getRename && regRenamingTable$RDY_rename_1_claimRename && - rob_RDY_enqPort_1_enq__4075_AND_NOT_fetchStage_ETC___d14083) ; - assign IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14311 = + fetchStage_RDY_pipelines_1_deq__2769_AND_NOT_f_ETC___d14093) ; + assign IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14321 = (fetchStage$pipelines_1_first[194:192] == 3'd2 && - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14258 && - IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14265) ? - IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14266 : + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14268 && + IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14275) ? + IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14276 : { 1'h0, - IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14267 } ; - assign IF_fetchStage_pipelines_1_first__2766_BIT_160__ETC___d14270 = + IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14277 } ; + assign IF_fetchStage_pipelines_1_first__2766_BIT_160__ETC___d14280 = { fetchStage$pipelines_1_first[159:128], - IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14264, - IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14265 ? - IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14266 : + IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14274, + IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14275 ? + IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14276 : { 1'h0, - IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14267 } } ; + IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14277 } } ; assign IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmio_c_ETC___d339 = mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[142] : @@ -24300,17 +24286,17 @@ module mkCore(CLK, EN_mmioToPlatform_pRs_enq ? mmio_pRsQ_enqReq_lat_0$wget[67] : mmio_pRsQ_enqReq_rl[67] ; - assign IF_rob_deqPort_0_canDeq__5338_THEN_IF_NOT_rob__ETC___d15665 = - rob$deqPort_0_canDeq ? y_avValue_fst__h730870 : 5'd0 ; - assign IF_rob_deqPort_0_canDeq__5338_THEN_IF_NOT_rob__ETC___d15684 = + assign IF_rob_deqPort_0_canDeq__5348_THEN_IF_NOT_rob__ETC___d15675 = + rob$deqPort_0_canDeq ? y_avValue_fst__h730973 : 5'd0 ; + assign IF_rob_deqPort_0_canDeq__5348_THEN_IF_NOT_rob__ETC___d15694 = rob$deqPort_0_canDeq ? - y_avValue_snd_snd_snd_fst__h731345 : + y_avValue_snd_snd_snd_fst__h731448 : 2'd0 ; - assign IF_rob_deqPort_0_deq_data__4344_BITS_329_TO_32_ETC___d15196 = + assign IF_rob_deqPort_0_deq_data__4354_BITS_329_TO_32_ETC___d15206 = (rob$deqPort_0_deq_data[329:325] == 5'd19) ? csrf_sepc_csr : csrf_mepc_csr ; - assign IF_rob_deqPort_0_deq_data__4344_BITS_329_TO_32_ETC___d15306 = + assign IF_rob_deqPort_0_deq_data__4354_BITS_329_TO_32_ETC___d15316 = (rob$deqPort_0_deq_data[329:325] == 5'd19) ? { csrf_mpp_reg, 3'd0, @@ -24330,12 +24316,12 @@ module mkCore(CLK, 1'b0, csrf_ie_vec_1, csrf_ie_vec_0 } ; - assign IF_rob_deqPort_0_deq_data__4344_BITS_97_TO_96__ETC___d14517 = + assign IF_rob_deqPort_0_deq_data__4354_BITS_97_TO_96__ETC___d14527 = { CASE_robdeqPort_0_deq_data_BITS_97_TO_96_0_ro_ETC__q252, rob$deqPort_0_deq_data[95:32] } ; - assign IF_rob_deqPort_1_canDeq__5343_THEN_IF_NOT_rob__ETC___d15676 = + assign IF_rob_deqPort_1_canDeq__5353_THEN_IF_NOT_rob__ETC___d15686 = rob$deqPort_1_canDeq ? - IF_NOT_rob_deqPort_1_deq_data__5346_BIT_25_534_ETC___d15675 : + IF_NOT_rob_deqPort_1_deq_data__5356_BIT_25_535_ETC___d15685 : rob$deqPort_0_canDeq && rob$deqPort_0_deq_data[26] ; assign IF_sfdin11103_BIT_4_THEN_2_ELSE_0__q139 = sfdin__h511103[4] ? 2'd2 : 2'd0 ; @@ -24431,7 +24417,7 @@ module mkCore(CLK, (fetchStage$pipelines_0_first[231:200] != 32'h10500073 || !csrf_tw_reg || csrf_prv_reg == 2'd3) ; - assign NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13427 = + assign NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13437 = !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[0] && !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[1] && !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[2] && @@ -24449,8 +24435,8 @@ module mkCore(CLK, !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[14] && !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[15] && !checkForException___d13008[4] && - NOT_csrf_fs_reg_read__1546_EQ_0_2997_2998_OR_N_ETC___d13425 ; - assign NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13730 = + NOT_csrf_fs_reg_read__1546_EQ_0_2997_2998_OR_N_ETC___d13435 ; + assign NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13740 = !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[0] && !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[1] && !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[2] && @@ -24467,13 +24453,13 @@ module mkCore(CLK, !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[13] && !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[14] && !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[15] && - !checkForException___d13703[4] && - NOT_csrf_fs_reg_read__1546_EQ_0_2997_2998_OR_N_ETC___d13728 ; - assign NOT_IF_NOT_rob_deqPort_0_canDeq__5338_5339_OR__ETC___d15681 = - (fflags__h734124 & csrf_fflags_reg) != fflags__h734124 || + !checkForException___d13713[4] && + NOT_csrf_fs_reg_read__1546_EQ_0_2997_2998_OR_N_ETC___d13738 ; + assign NOT_IF_NOT_rob_deqPort_0_canDeq__5348_5349_OR__ETC___d15691 = + (fflags__h734227 & csrf_fflags_reg) != fflags__h734227 || csrf_fs_reg != 2'b11 && - (IF_rob_deqPort_1_canDeq__5343_THEN_IF_NOT_rob__ETC___d15676 || - fflags__h734124 != 5'd0) ; + (IF_rob_deqPort_1_canDeq__5353_THEN_IF_NOT_rob__ETC___d15686 || + fflags__h734227 != 5'd0) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10056 = !f2_sfd__h521139[21] && !f2_sfd__h521139[20] && !f2_sfd__h521139[19] && @@ -24595,12 +24581,12 @@ module mkCore(CLK, !f3_sfd__h560443[2] && !f3_sfd__h560443[1] && !f3_sfd__h560443[0] ; - assign NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13489 = - !SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__344_ETC___d13487 && + assign NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13499 = + !SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__345_ETC___d13497 && (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3408_AND__ETC___d13434 ; - assign NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14629 = + regRenamingTable_rename_0_canRename__3418_AND__ETC___d13444 ; + assign NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14639 = (!commitStage_commitTrap[36] || commitStage_commitTrap[35:32] == 4'd0 || commitStage_commitTrap[35:32] == 4'd1 || @@ -24614,12 +24600,12 @@ module mkCore(CLK, (commitStage_commitTrap[36] || commitStage_commitTrap[35:32] != 4'd3 || CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q243) ; - assign NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14636 = - NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14629 || + assign NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14646 = + NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14639 || coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty && fetchStage$iTlbIfc_noPendingReq && coreFix_memExe_dTlb$noPendingReq ; - assign NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14700 = + assign NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 = (!commitStage_commitTrap[36] || commitStage_commitTrap[35:32] != 4'd14) && (!commitStage_commitTrap[36] || @@ -24636,13 +24622,13 @@ module mkCore(CLK, (commitStage_commitTrap[36] || commitStage_commitTrap[35:32] != 4'd3 || CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q243) ; - assign NOT_commitStage_rg_run_state_4350_4351_AND_NOT_ETC___d15010 = + assign NOT_commitStage_rg_run_state_4360_4361_AND_NOT_ETC___d15020 = !commitStage_rg_run_state && !commitStage_commitTrap[165] && !rob$deqPort_0_deq_data[167] && !rob$deqPort_0_deq_data[18] && rob$deqPort_0_deq_data[25] ; - assign NOT_commitStage_rg_run_state_4350_4351_AND_NOT_ETC___d15021 = - NOT_commitStage_rg_run_state_4350_4351_AND_NOT_ETC___d15010 && + assign NOT_commitStage_rg_run_state_4360_4361_AND_NOT_ETC___d15031 = + NOT_commitStage_rg_run_state_4360_4361_AND_NOT_ETC___d15020 && (rob$deqPort_0_deq_data[329:325] == 5'd0 || rob$deqPort_0_deq_data[329:325] == 5'd21 || rob$deqPort_0_deq_data[329:325] == 5'd17 || @@ -24652,9 +24638,9 @@ module mkCore(CLK, rob$deqPort_0_deq_data[329:325] == 5'd15 || rob$deqPort_0_deq_data[329:325] == 5'd19 || rob$deqPort_0_deq_data[329:325] == 5'd20) && - _0b0_CONCAT_csrf_external_int_pend_vec_3_read___ETC___d14329 ; - assign NOT_commitStage_rg_run_state_4350_4351_AND_NOT_ETC___d15392 = - NOT_commitStage_rg_run_state_4350_4351_AND_NOT_ETC___d15010 && + _0b0_CONCAT_csrf_external_int_pend_vec_3_read___ETC___d14339 ; + assign NOT_commitStage_rg_run_state_4360_4361_AND_NOT_ETC___d15402 = + NOT_commitStage_rg_run_state_4360_4361_AND_NOT_ETC___d15020 && rob$deqPort_0_deq_data[329:325] != 5'd0 && rob$deqPort_0_deq_data[329:325] != 5'd21 && rob$deqPort_0_deq_data[329:325] != 5'd17 && @@ -24664,7 +24650,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[329:325] != 5'd15 && rob$deqPort_0_deq_data[329:325] != 5'd19 && rob$deqPort_0_deq_data[329:325] != 5'd20 && - _0b0_CONCAT_csrf_external_int_pend_vec_3_read___ETC___d14329 ; + _0b0_CONCAT_csrf_external_int_pend_vec_3_read___ETC___d14339 ; assign NOT_coreFix_aluExe_0_bypassWire_0_whas__2202_2_ETC___d12229 = (!coreFix_aluExe_0_bypassWire_0$whas || !coreFix_aluExe_0_bypassWire_0_wget__2203_BITS__ETC___d12205) && @@ -25170,7 +25156,7 @@ module mkCore(CLK, NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13331 && !csrf_prv_reg_read__2787_ULT_IF_fetchStage_pipe_ETC___d13040 && csr_addr__h655332 != 12'h8FF) ; - assign NOT_csrf_fs_reg_read__1546_EQ_0_2997_2998_OR_N_ETC___d13425 = + assign NOT_csrf_fs_reg_read__1546_EQ_0_2997_2998_OR_N_ETC___d13435 = (csrf_fs_reg != 2'd0 || (!fetchStage$pipelines_0_first[95] || !fetchStage$pipelines_0_first[94]) && @@ -25182,7 +25168,7 @@ module mkCore(CLK, (fetchStage$pipelines_0_first[231:200] != 32'h10500073 || !csrf_tw_reg || csrf_prv_reg == 2'd3) ; - assign NOT_csrf_fs_reg_read__1546_EQ_0_2997_2998_OR_N_ETC___d13728 = + assign NOT_csrf_fs_reg_read__1546_EQ_0_2997_2998_OR_N_ETC___d13738 = (csrf_fs_reg != 2'd0 || (!fetchStage$pipelines_1_first[95] || !fetchStage$pipelines_1_first[94]) && @@ -25194,102 +25180,102 @@ module mkCore(CLK, (fetchStage$pipelines_1_first[231:200] != 32'h10500073 || !csrf_tw_reg || csrf_prv_reg == 2'd3) ; - assign NOT_csrf_prv_reg_read__2787_ULE_1_4701_4743_OR_ETC___d14747 = - !csrf_prv_reg_read__2787_ULE_1___d14701 || + assign NOT_csrf_prv_reg_read__2787_ULE_1_4711_4753_OR_ETC___d14757 = + !csrf_prv_reg_read__2787_ULE_1___d14711 || (commitStage_commitTrap[36] ? - !_0b0_CONCAT_csrf_mideleg_11_reg_read__1653_1654_ETC___d14703 : - !_0b0_CONCAT_csrf_medeleg_15_reg_read__1645_1646_ETC___d14721) ; - assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13532 = + !_0b0_CONCAT_csrf_mideleg_11_reg_read__1653_1654_ETC___d14713 : + !_0b0_CONCAT_csrf_medeleg_15_reg_read__1645_1646_ETC___d14731) ; + assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13542 = !fetchStage$pipelines_0_canDeq || !regRenamingTable$rename_0_canRename || - fetchStage_pipelines_0_first__2757_BITS_199_TO_ETC___d13514 || - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13529 || + fetchStage_pipelines_0_first__2757_BITS_199_TO_ETC___d13524 || + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13539 || fetchStage$pipelines_0_first[194:192] != 3'd1 ; - assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13775 = + assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13785 = (!fetchStage$pipelines_0_canDeq || fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || - NOT_regRenamingTable_rename_0_canRename__3408__ETC___d13766 || + NOT_regRenamingTable_rename_0_canRename__3418__ETC___d13776 || fetchStage$pipelines_0_first[194:192] != 3'd0 && fetchStage$pipelines_0_first[194:192] != 3'd1 || - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3443_co_ETC___d13453) && + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463) && coreFix_aluExe_1_rsAlu$canEnq && - !coreFix_aluExe_0_rsAlu_approximateCount__3447__ETC___d13449 ; - assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13819 = + !coreFix_aluExe_0_rsAlu_approximateCount__3457__ETC___d13459 ; + assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13829 = (!fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first) && - (regRenamingTable_rename_0_canRename__3408_AND__ETC___d13484 && + (regRenamingTable_rename_0_canRename__3418_AND__ETC___d13494 && (fetchStage$pipelines_0_first[194:192] == 3'd3 || fetchStage$pipelines_0_first[194:192] == 3'd4) || !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq || - NOT_regRenamingTable_rename_1_canRename__3535__ETC___d13806) ; - assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13874 = + NOT_regRenamingTable_rename_1_canRename__3545__ETC___d13816) ; + assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13884 = !fetchStage$pipelines_0_canDeq || !regRenamingTable$rename_0_canRename || - fetchStage_pipelines_0_first__2757_BITS_199_TO_ETC___d13514 || + fetchStage_pipelines_0_first__2757_BITS_199_TO_ETC___d13524 || fetchStage$pipelines_0_first[194:192] != 3'd3 && fetchStage$pipelines_0_first[194:192] != 3'd4 ; - assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13892 = + assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13902 = (!fetchStage$pipelines_0_canDeq || - NOT_regRenamingTable_rename_0_canRename__3408__ETC___d13842 || + NOT_regRenamingTable_rename_0_canRename__3418__ETC___d13852 || fetchStage$pipelines_0_first[194:192] != 3'd2 || - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13524) && + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13534) && coreFix_memExe_rsMem$canEnq && CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q238 ; - assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14041 = + assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14051 = (!fetchStage$pipelines_0_canDeq || - NOT_specTagManager_canClaim__3406_3497_OR_NOT__ETC___d14012) && + NOT_specTagManager_canClaim__3416_3507_OR_NOT__ETC___d14022) && CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q242 && (fetchStage$pipelines_1_first[199:195] == 5'd14 || coreFix_memExe_rsMem$RDY_enq) ; - assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14095 = + assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14105 = (!fetchStage$pipelines_0_canDeq || - fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13961 && - IF_fetchStage_RDY_pipelines_0_first__2754_AND__ETC___d13440) && + fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13971 && + IF_fetchStage_RDY_pipelines_0_first__2754_AND__ETC___d13450) && fetchStage$RDY_pipelines_0_first && - fetchStage_pipelines_0_canDeq__2755_AND_fetchS_ETC___d14093 ; - assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14194 = + fetchStage_pipelines_0_canDeq__2755_AND_fetchS_ETC___d14103 ; + assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14204 = (!fetchStage$pipelines_0_canDeq || fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || - NOT_regRenamingTable_rename_0_canRename__3408__ETC___d14189 || + NOT_regRenamingTable_rename_0_canRename__3418__ETC___d14199 || fetchStage$pipelines_0_first[194:192] != 3'd0 && fetchStage$pipelines_0_first[194:192] != 3'd1 || - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3443_co_ETC___d13453) && + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463) && coreFix_aluExe_1_rsAlu$canEnq && - !coreFix_aluExe_0_rsAlu_approximateCount__3447__ETC___d13449 ; - assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14199 = + !coreFix_aluExe_0_rsAlu_approximateCount__3457__ETC___d13459 ; + assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14209 = (!fetchStage$pipelines_0_canDeq || - NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14102 && - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13470) && + NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14112 && + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13480) && fetchStage$pipelines_1_canDeq ; - assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14201 = + assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14211 = !fetchStage$pipelines_0_canDeq || !regRenamingTable$rename_0_canRename || - renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13925 || - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13529 || + renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13935 || + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13539 || fetchStage$pipelines_0_first[194:192] != 3'd1 ; - assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14213 = - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14199 && - NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d14210 && + assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14223 = + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14209 && + NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d14220 && (fetchStage$pipelines_1_first[194:192] == 3'd0 || fetchStage$pipelines_1_first[194:192] == 3'd1) && - SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__275_ETC___d14007 ; - assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14257 = + SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__275_ETC___d14017 ; + assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14267 = !fetchStage$pipelines_0_canDeq || !regRenamingTable$rename_0_canRename || - renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13925 || + renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13935 || fetchStage$pipelines_0_first[194:192] != 3'd2 || - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13524 ; - assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14258 = - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14257 && + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13534 ; + assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14268 = + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14267 && coreFix_memExe_rsMem$canEnq && CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q238 ; - assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14288 = - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14201 && + assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14298 = + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14211 && specTagManager$canClaim && - regRenamingTable_rename_1_canRename__3535_AND__ETC___d14209 && - IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13907 && + regRenamingTable_rename_1_canRename__3545_AND__ETC___d14219 && + IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13917 && fetchStage$pipelines_1_first[194:192] == 3'd1 ; assign NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13331 = (fetchStage$pipelines_0_first[194:192] != 3'd0 || @@ -25297,54 +25283,54 @@ module mkCore(CLK, rs1__h655333 == 5'd0 && imm__h655334 == 32'd0 || csr_addr__h655332[11:10] != 2'b11 ; - assign NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13471 = + assign NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13481 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3408_AND__ETC___d13434 && - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13470 ; - assign NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13751 = + regRenamingTable_rename_0_canRename__3418_AND__ETC___d13444 && + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13480 ; + assign NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13761 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3408_AND__ETC___d13434 && - fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13750 ; - assign NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13757 = + regRenamingTable_rename_0_canRename__3418_AND__ETC___d13444 && + fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13760 ; + assign NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13767 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3408_AND__ETC___d13434 && + regRenamingTable_rename_0_canRename__3418_AND__ETC___d13444 && (fetchStage$pipelines_0_first[194:192] == 3'd0 || fetchStage$pipelines_0_first[194:192] == 3'd1) && - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3443_co_ETC___d13453 && + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463 && (!coreFix_aluExe_0_rsAlu$canEnq || - !coreFix_aluExe_0_rsAlu_approximateCount__3447__ETC___d13449) ; - assign NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13918 = + !coreFix_aluExe_0_rsAlu_approximateCount__3457__ETC___d13459) ; + assign NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13928 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3408_AND__ETC___d13434 && - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13494 ; - assign NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14102 = + regRenamingTable_rename_0_canRename__3418_AND__ETC___d13444 && + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13504 ; + assign NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14112 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && regRenamingTable$rename_0_canRename && !checkForException___d13008[4] && rob$enqPort_0_canEnq ; - assign NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14171 = + assign NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14181 = { fetchStage$pipelines_0_first[194:192] != 3'd2 || !coreFix_memExe_rsMem$canEnq || - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13524 || - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14127, + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13534 || + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14137, (fetchStage$pipelines_0_first[194:192] == 3'd2 && coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13466 && - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14130) ? - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14133 : + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13476 && + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14140) ? + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14143 : { 1'h0, - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14136 }, + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14146 }, 7'd32, specTagManager$currentSpecBits } ; - assign NOT_fetchStage_pipelines_0_first__2757_BIT_68__ETC___d13482 = + assign NOT_fetchStage_pipelines_0_first__2757_BIT_68__ETC___d13492 = !fetchStage$pipelines_0_first[68] && !checkForException___d13008[4] && - NOT_csrf_fs_reg_read__1546_EQ_0_2997_2998_OR_N_ETC___d13425 && + NOT_csrf_fs_reg_read__1546_EQ_0_2997_2998_OR_N_ETC___d13435 && rob$enqPort_0_canEnq && epochManager$checkEpoch_0_check ; assign NOT_fetchStage_pipelines_1_canDeq__2763_2764_O_ETC___d12772 = @@ -25352,36 +25338,36 @@ module mkCore(CLK, fetchStage$RDY_pipelines_1_first && (epochManager$checkEpoch_1_check || fetchStage$RDY_pipelines_1_deq) ; - assign NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d13505 = + assign NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d13515 = (fetchStage$pipelines_1_first[194:192] != 3'd1 || !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first) && (fetchStage$RDY_pipelines_0_first && fetchStage$pipelines_1_first[194:192] == 3'd1 && - regRenamingTable_rename_0_canRename__3408_AND__ETC___d13498 || - csrf_rg_dcsr_read__1720_BIT_2_3062_OR_NOT_fetc_ETC___d13503) ; - assign NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d13744 = + regRenamingTable_rename_0_canRename__3418_AND__ETC___d13508 || + csrf_rg_dcsr_read__1720_BIT_2_3062_OR_NOT_fetc_ETC___d13513) ; + assign NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d13754 = (fetchStage$pipelines_1_first[194:192] != 3'd1 || - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13532 && + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13542 && specTagManager$canClaim) && - regRenamingTable_rename_1_canRename__3535_AND__ETC___d13743 ; - assign NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d13861 = + regRenamingTable_rename_1_canRename__3545_AND__ETC___d13753 ; + assign NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d13871 = (fetchStage$pipelines_1_first[194:192] != 3'd1 || (!fetchStage$pipelines_0_canDeq || - NOT_regRenamingTable_rename_0_canRename__3408__ETC___d13842 || - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13855 || + NOT_regRenamingTable_rename_0_canRename__3418__ETC___d13852 || + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13865 || fetchStage$pipelines_0_first[194:192] != 3'd1) && specTagManager$canClaim) && - regRenamingTable_rename_1_canRename__3535_AND__ETC___d13743 ; - assign NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d14210 = + regRenamingTable_rename_1_canRename__3545_AND__ETC___d13753 ; + assign NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d14220 = (fetchStage$pipelines_1_first[194:192] != 3'd1 || - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14201 && + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14211 && specTagManager$canClaim) && - regRenamingTable_rename_1_canRename__3535_AND__ETC___d14209 ; - assign NOT_fetchStage_pipelines_1_first__2766_BIT_68__ETC___d14207 = + regRenamingTable_rename_1_canRename__3545_AND__ETC___d14219 ; + assign NOT_fetchStage_pipelines_1_first__2766_BIT_68__ETC___d14217 = !fetchStage$pipelines_1_first[68] && - !checkForException___d13703[4] && - NOT_csrf_fs_reg_read__1546_EQ_0_2997_2998_OR_N_ETC___d13728 && + !checkForException___d13713[4] && + NOT_csrf_fs_reg_read__1546_EQ_0_2997_2998_OR_N_ETC___d13738 && rob$enqPort_1_canEnq && epochManager$checkEpoch_1_check && !csrf_rg_dcsr[2] ; @@ -25464,7 +25450,7 @@ module mkCore(CLK, (mmio_pRsQ_deqReq_dummy2_2$Q_OUT && (mmio_pRsQ_deqReq_lat_0$whas || mmio_pRsQ_deqReq_rl) || mmio_pRsQ_empty) ; - assign NOT_regRenamingTable_rename_0_canRename__3408__ETC___d13766 = + assign NOT_regRenamingTable_rename_0_canRename__3418__ETC___d13776 = !regRenamingTable$rename_0_canRename || fetchStage$pipelines_0_first[199:195] == 5'd0 || fetchStage$pipelines_0_first[199:195] == 5'd21 || @@ -25475,8 +25461,8 @@ module mkCore(CLK, fetchStage$pipelines_0_first[199:195] == 5'd15 || fetchStage$pipelines_0_first[199:195] == 5'd19 || fetchStage$pipelines_0_first[199:195] == 5'd20 || - renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13764 ; - assign NOT_regRenamingTable_rename_0_canRename__3408__ETC___d13842 = + renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13774 ; + assign NOT_regRenamingTable_rename_0_canRename__3418__ETC___d13852 = !regRenamingTable$rename_0_canRename || fetchStage$pipelines_0_first[199:195] == 5'd0 || fetchStage$pipelines_0_first[199:195] == 5'd21 || @@ -25487,14 +25473,14 @@ module mkCore(CLK, fetchStage$pipelines_0_first[199:195] == 5'd15 || fetchStage$pipelines_0_first[199:195] == 5'd19 || fetchStage$pipelines_0_first[199:195] == 5'd20 || - fetchStage_pipelines_0_first__2757_BIT_68_2786_ETC___d13840 ; - assign NOT_regRenamingTable_rename_0_canRename__3408__ETC___d14189 = + fetchStage_pipelines_0_first__2757_BIT_68_2786_ETC___d13850 ; + assign NOT_regRenamingTable_rename_0_canRename__3418__ETC___d14199 = !regRenamingTable$rename_0_canRename || renameStage_rg_m_halt_req[4] || fetchStage$pipelines_0_first[68] || checkForException___d13008[4] || !rob$enqPort_0_canEnq ; - assign NOT_regRenamingTable_rename_1_canRename__3535__ETC___d13806 = + assign NOT_regRenamingTable_rename_1_canRename__3545__ETC___d13816 = !regRenamingTable$rename_1_canRename || fetchStage$pipelines_1_first[199:195] == 5'd0 || fetchStage$pipelines_1_first[199:195] == 5'd21 || @@ -25505,7 +25491,7 @@ module mkCore(CLK, fetchStage$pipelines_1_first[199:195] == 5'd15 || fetchStage$pipelines_1_first[199:195] == 5'd19 || fetchStage$pipelines_1_first[199:195] == 5'd20 || - renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13804 ; + renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13814 ; assign NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13102 = !renameStage_rg_m_halt_req[4] && (fetchStage$pipelines_0_first[68] || @@ -25525,38 +25511,38 @@ module mkCore(CLK, !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[13] && !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[14] && !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[15]) ; - assign NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13432 = + assign NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13442 = !renameStage_rg_m_halt_req[4] && !fetchStage$pipelines_0_first[68] && - NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13427 && + NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13437 && rob$enqPort_0_canEnq && epochManager$checkEpoch_0_check ; - assign NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13741 = + assign NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13751 = !renameStage_rg_m_halt_req[4] && !fetchStage$pipelines_1_first[68] && - NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13730 && + NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13740 && rob$enqPort_1_canEnq && - epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13739 ; - assign NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13883 = + epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13749 ; + assign NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13893 = !renameStage_rg_m_halt_req[4] && !fetchStage$pipelines_1_first[68] && - NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13730 && + NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13740 && rob$enqPort_1_canEnq && - epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13881 ; - assign NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13901 = + epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13891 ; + assign NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13911 = !renameStage_rg_m_halt_req[4] && !fetchStage$pipelines_1_first[68] && - NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13730 && + NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13740 && rob$enqPort_1_canEnq && - epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13899 ; - assign NOT_rob_deqPort_0_canDeq__5338_5339_OR_regRena_ETC___d15380 = + epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13909 ; + assign NOT_rob_deqPort_0_canDeq__5348_5349_OR_rob_RDY_ETC___d15390 = (!rob$deqPort_0_canDeq || - regRenamingTable$RDY_commit_0_commit && rob$RDY_deqPort_0_deq && + rob$RDY_deqPort_0_deq && regRenamingTable$RDY_commit_0_commit && v_f_to_TV_0$FULL_N) && (!rob$deqPort_1_canDeq || rob$RDY_deqPort_1_deq_data && - NOT_rob_deqPort_1_deq_data__5346_BIT_25_5347_5_ETC___d15377) ; - assign NOT_rob_deqPort_0_canDeq__5338_5339_OR_rob_deq_ETC___d15659 = + NOT_rob_deqPort_1_deq_data__5356_BIT_25_5357_5_ETC___d15387) ; + assign NOT_rob_deqPort_0_canDeq__5348_5349_OR_rob_deq_ETC___d15669 = (!rob$deqPort_0_canDeq || rob$deqPort_0_deq_data[25] && !rob$deqPort_0_deq_data[18] && !rob$deqPort_0_deq_data[167] && @@ -25570,15 +25556,15 @@ module mkCore(CLK, rob$deqPort_0_deq_data[329:325] != 5'd19 && rob$deqPort_0_deq_data[329:325] != 5'd20) && rob$deqPort_1_canDeq ; - assign NOT_rob_deqPort_0_deq_data__4344_BITS_329_TO_3_ETC___d14998 = + assign NOT_rob_deqPort_0_deq_data__4354_BITS_329_TO_3_ETC___d15008 = rob$deqPort_0_deq_data[329:325] != 5'd13 || - (IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 != + (IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 != 6'd7 || csrf_stats_module_writeQ$FULL_N) && - (IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 != + (IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 != 6'd6 || csrf_terminate_module_terminateQ$FULL_N) ; - assign NOT_rob_deqPort_1_deq_data__5346_BIT_25_5347_5_ETC___d15377 = + assign NOT_rob_deqPort_1_deq_data__5356_BIT_25_5357_5_ETC___d15387 = !rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[329:325] == 5'd0 || @@ -25590,20 +25576,20 @@ module mkCore(CLK, rob$deqPort_1_deq_data[329:325] == 5'd15 || rob$deqPort_1_deq_data[329:325] == 5'd19 || rob$deqPort_1_deq_data[329:325] == 5'd20 || - regRenamingTable$RDY_commit_1_commit && rob$RDY_deqPort_1_deq && + rob$RDY_deqPort_1_deq && regRenamingTable$RDY_commit_1_commit && v_f_to_TV_1$FULL_N ; - assign NOT_specTagManager_canClaim__3406_3497_OR_NOT__ETC___d14012 = + assign NOT_specTagManager_canClaim__3416_3507_OR_NOT__ETC___d14022 = !specTagManager$canClaim || !regRenamingTable$rename_0_canRename || - fetchStage_pipelines_0_first__2757_BITS_199_TO_ETC___d13514 || - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13952 || + fetchStage_pipelines_0_first__2757_BITS_199_TO_ETC___d13524 || + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13962 || fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$RDY_nextSpecTag ; - assign NOT_specTagManager_canClaim__3406_3497_OR_NOT__ETC___d14079 = + assign NOT_specTagManager_canClaim__3416_3507_OR_NOT__ETC___d14089 = !specTagManager$canClaim || !regRenamingTable$rename_0_canRename || - renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13925 || - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13952 || + renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13935 || + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13962 || fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$RDY_nextSpecTag ; assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2920 = @@ -25624,21 +25610,21 @@ module mkCore(CLK, !CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q268, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2938, x__h291619 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16097 = + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16107 = { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q269, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q270, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q271 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16053 = + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16063 = { CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q253, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q254, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q255, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q256 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16062 = - { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16053, + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16072 = + { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16063, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q257, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q258 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16071 = - { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16062, + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16081 = + { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16072, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q262, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q263 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10131 = @@ -26029,19 +26015,19 @@ module mkCore(CLK, 1'd0, csrf_timer_int_en_vec_1 & csrf_timer_int_pend_vec_1, 1'd0 } ; - assign _0_OR_NOT_fetchStage_pipelines_0_first__2757_BI_ETC___d13933 = + assign _0_OR_NOT_fetchStage_pipelines_0_first__2757_BI_ETC___d13943 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$RDY_nextSpecTag) && - CASE_k70531_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239 ; - assign _0_OR_NOT_fetchStage_pipelines_1_first__2766_BI_ETC___d13834 = + CASE_k70634_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q240 ; + assign _0_OR_NOT_fetchStage_pipelines_1_first__2766_BI_ETC___d13844 = (fetchStage$pipelines_1_first[194:192] != 3'd1 || !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first) && (fetchStage$RDY_pipelines_0_first && fetchStage$pipelines_1_first[194:192] == 3'd1 && - regRenamingTable_rename_0_canRename__3408_AND__ETC___d13498 || - NOT_regRenamingTable_rename_1_canRename__3535__ETC___d13806) ; - assign _0_OR_NOT_fetchStage_pipelines_1_first__2766_BI_ETC___d14025 = + regRenamingTable_rename_0_canRename__3418_AND__ETC___d13508 || + NOT_regRenamingTable_rename_1_canRename__3545__ETC___d13816) ; + assign _0_OR_NOT_fetchStage_pipelines_1_first__2766_BI_ETC___d14035 = (fetchStage$pipelines_1_first[194:192] != 3'd1 || specTagManager$RDY_nextSpecTag) && CASE_fetchStage_pipelines_0_canDeq__2755_AND_N_ETC__q241 ; @@ -26069,12 +26055,12 @@ module mkCore(CLK, (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7338[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7338) ; - assign _0b0_CONCAT_csrf_external_int_pend_vec_3_read___ETC___d14329 = + assign _0b0_CONCAT_csrf_external_int_pend_vec_3_read___ETC___d14339 = mip_csr__read__h611255 == commitStage_rg_old_mip_csr_val ; - assign _0b0_CONCAT_csrf_medeleg_15_reg_read__1645_1646_ETC___d14721 = - medeleg_csr__read__h610374[i__h710364] ; - assign _0b0_CONCAT_csrf_mideleg_11_reg_read__1653_1654_ETC___d14703 = - mideleg_csr__read__h610469[i__h710524] ; + assign _0b0_CONCAT_csrf_medeleg_15_reg_read__1645_1646_ETC___d14731 = + medeleg_csr__read__h610374[i__h710467] ; + assign _0b0_CONCAT_csrf_mideleg_11_reg_read__1653_1654_ETC___d14713 = + mideleg_csr__read__h610469[i__h710627] ; assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4011 = 12'd3074 - { 6'd0, @@ -26662,63 +26648,63 @@ module mkCore(CLK, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7335 ; assign _dfoo12 = fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3408_AND__ETC___d14123 || - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14199 && - regRenamingTable_rename_1_canRename__3535_AND__ETC___d14209 && + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14133 || + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14209 && + regRenamingTable_rename_1_canRename__3545_AND__ETC___d14219 && fetchStage$pipelines_1_first[194:192] == 3'd2 && - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14258 && + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14268 && fetchStage$pipelines_1_first[199:195] != 5'd14 ; assign _dfoo16 = - k__h670531 == 1'd1 && - fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14105 || - (fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14181 || - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14194) == + k__h670634 == 1'd1 && + fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14115 || + (fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14191 || + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14204) == 1'd1 && - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14213 ; + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14223 ; assign _dfoo18 = - k__h670531 == 1'd0 && - fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14105 || - (fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14181 || - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14194) == + k__h670634 == 1'd0 && + fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14115 || + (fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14191 || + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14204) == 1'd0 && - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14213 ; + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14223 ; assign _dfoo2 = fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3408_AND__ETC___d14151 || - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14199 && - regRenamingTable_rename_1_canRename__3535_AND__ETC___d14209 && + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14161 || + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14209 && + regRenamingTable_rename_1_canRename__3545_AND__ETC___d14219 && fetchStage$pipelines_1_first[194:192] == 3'd2 && - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14258 && + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14268 && fetchStage$pipelines_1_first[191:189] != 3'd0 && fetchStage$pipelines_1_first[191:189] != 3'd2 ; - assign _dfoo22 = - commitStage_commitTrap_4352_BIT_36_4594_AND_co_ETC___d14659 || - NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14700 ; + assign _dfoo20 = + commitStage_commitTrap_4362_BIT_36_4604_AND_co_ETC___d14669 || + NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 ; assign _dfoo24 = rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd40 || rob$deqPort_0_deq_data[329:325] == 5'd19 || rob$deqPort_0_deq_data[329:325] == 5'd20 ; assign _dfoo26 = rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd18 || rob$deqPort_0_deq_data[329:325] == 5'd20 ; assign _dfoo32 = rob$deqPort_0_deq_data[329:325] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + (IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd8 || - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd18) || rob$deqPort_0_deq_data[329:325] == 5'd19 ; assign _dfoo7 = fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3408_AND__ETC___d14143 || - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14199 && - regRenamingTable_rename_1_canRename__3535_AND__ETC___d14209 && + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14153 || + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14209 && + regRenamingTable_rename_1_canRename__3545_AND__ETC___d14219 && fetchStage$pipelines_1_first[194:192] == 3'd2 && - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14258 && + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14268 && (fetchStage$pipelines_1_first[191:189] == 3'd0 || fetchStage$pipelines_1_first[191:189] == 3'd2) ; assign _dor1coreFix_aluExe_0_bypassWire_2$EN_wset = @@ -29581,11 +29567,11 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[227] ? b___1__h603094 : coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; - assign base__h713309 = { csrf_stvec_base_hi_reg, 2'b0 } ; - assign base__h713329 = { csrf_mtvec_base_hi_reg, 2'b0 } ; - assign cause_code__h710349 = - commitStage_commitTrap[36] ? i__h710524 : i__h710364 ; - assign commitStage_commitTrap_4352_BIT_36_4594_AND_co_ETC___d14659 = + assign base__h713412 = { csrf_stvec_base_hi_reg, 2'b0 } ; + assign base__h713432 = { csrf_mtvec_base_hi_reg, 2'b0 } ; + assign cause_code__h710452 = + commitStage_commitTrap[36] ? i__h710627 : i__h710467 ; + assign commitStage_commitTrap_4362_BIT_36_4604_AND_co_ETC___d14669 = commitStage_commitTrap[36] && commitStage_commitTrap[35:32] != 4'd0 && commitStage_commitTrap[35:32] != 4'd1 && @@ -29599,15 +29585,15 @@ module mkCore(CLK, !commitStage_commitTrap[36] && commitStage_commitTrap[35:32] == 4'd3 && CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q244 ; - assign commitStage_f_rob_data_first__4760_BIT_167_485_ETC___d14932 = + assign commitStage_f_rob_data_first__4770_BIT_167_486_ETC___d14942 = { commitStage_f_rob_data$D_OUT[167:166], commitStage_f_rob_data$D_OUT[166] ? CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q250 : CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q251, - trap_val__h710350, - IF_commitStage_f_rob_data_first__4760_BITS_97__ETC___d14931 } ; - assign commitStage_rg_serial_num_4333_PLUS_IF_rob_deq_ETC___d15459 = - commitStage_rg_serial_num + y__h731332 ; + trap_val__h710453, + IF_commitStage_f_rob_data_first__4770_BITS_97__ETC___d14941 } ; + assign commitStage_rg_serial_num_4343_PLUS_IF_rob_deq_ETC___d15469 = + commitStage_rg_serial_num + y__h731435 ; assign coreFix_aluExe_0_bypassWire_0_wget__2203_BITS__ETC___d12205 = coreFix_aluExe_0_bypassWire_0$wget[70:64] == coreFix_aluExe_0_dispToRegQ$first[84:78] ; @@ -29640,7 +29626,7 @@ module mkCore(CLK, (coreFix_aluExe_0_exeToFinQ$first[326:322] != 5'd9 && coreFix_aluExe_0_exeToFinQ$first[326:322] != 5'd10 || coreFix_trainBPQ_0$FULL_N) ; - assign coreFix_aluExe_0_rsAlu_approximateCount__3447__ETC___d13449 = + assign coreFix_aluExe_0_rsAlu_approximateCount__3457__ETC___d13459 = coreFix_aluExe_0_rsAlu$approximateCount < coreFix_aluExe_1_rsAlu$approximateCount ; assign coreFix_aluExe_1_bypassWire_0_wget__1343_BITS__ETC___d11345 = @@ -29803,11 +29789,11 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107:76] ; assign coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q11 = coreFix_fpuMulDivExe_0_regToExeQ$first[171:140] ; - assign coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__39_ETC___d14032 = + assign coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__39_ETC___d14042 = coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_enq && regRenamingTable$RDY_rename_1_getRename && (!fetchStage$pipelines_0_canDeq || - NOT_specTagManager_canClaim__3406_3497_OR_NOT__ETC___d14012) ; + NOT_specTagManager_canClaim__3416_3507_OR_NOT__ETC___d14022) ; assign coreFix_memExe_bypassWire_0_wget__569_BITS_70__ETC___d1571 = coreFix_aluExe_0_bypassWire_0$wget[70:64] == coreFix_memExe_dispToRegQ$first[61:55] ; @@ -30135,7 +30121,7 @@ module mkCore(CLK, !coreFix_memExe_respLrScAmoQ_deqReq_lat_0$whas && !coreFix_memExe_respLrScAmoQ_deqReq_rl) && coreFix_memExe_respLrScAmoQ_full ; - assign coreFix_memExe_stb_isEmpty__009_AND_coreFix_me_ETC___d14661 = + assign coreFix_memExe_stb_isEmpty__009_AND_coreFix_me_ETC___d14671 = coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty && v_f_to_TV_0$FULL_N && fetchStage$iTlbIfc_noPendingReq && @@ -30157,7 +30143,7 @@ module mkCore(CLK, (fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13038 || csrf_prv_reg_read__2787_ULT_IF_fetchStage_pipe_ETC___d13040 || csr_addr__h655332 == 12'h8FF) ; - assign csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13507 = + assign csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13517 = csrf_fs_reg == 2'd0 && (fetchStage$pipelines_0_first[95] && fetchStage$pipelines_0_first[94] || @@ -30169,7 +30155,7 @@ module mkCore(CLK, fetchStage$pipelines_0_first[231:200] == 32'h10500073 && csrf_tw_reg && csrf_prv_reg != 2'd3 ; - assign csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13796 = + assign csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13806 = csrf_fs_reg == 2'd0 && (fetchStage$pipelines_1_first[95] && fetchStage$pipelines_1_first[94] || @@ -30181,18 +30167,18 @@ module mkCore(CLK, fetchStage$pipelines_1_first[231:200] == 32'h10500073 && csrf_tw_reg && csrf_prv_reg != 2'd3 ; - assign csrf_prv_reg_read__2787_ULE_1_4701_AND_IF_comm_ETC___d14723 = - csrf_prv_reg_read__2787_ULE_1___d14701 && + assign csrf_prv_reg_read__2787_ULE_1_4711_AND_IF_comm_ETC___d14733 = + csrf_prv_reg_read__2787_ULE_1___d14711 && (commitStage_commitTrap[36] ? - _0b0_CONCAT_csrf_mideleg_11_reg_read__1653_1654_ETC___d14703 : - _0b0_CONCAT_csrf_medeleg_15_reg_read__1645_1646_ETC___d14721) ; - assign csrf_prv_reg_read__2787_ULE_1___d14701 = csrf_prv_reg <= 2'd1 ; + _0b0_CONCAT_csrf_mideleg_11_reg_read__1653_1654_ETC___d14713 : + _0b0_CONCAT_csrf_medeleg_15_reg_read__1645_1646_ETC___d14731) ; + assign csrf_prv_reg_read__2787_ULE_1___d14711 = csrf_prv_reg <= 2'd1 ; assign csrf_prv_reg_read__2787_ULT_IF_fetchStage_pipe_ETC___d13040 = csrf_prv_reg < csr_addr__h655332[9:8] ; - assign csrf_rg_dcsr_read__1720_BIT_2_3062_OR_NOT_fetc_ETC___d13503 = + assign csrf_rg_dcsr_read__1720_BIT_2_3062_OR_NOT_fetc_ETC___d13513 = csrf_rg_dcsr[2] || !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first && - IF_fetchStage_RDY_pipelines_0_first__2754_AND__ETC___d13440 ; + IF_fetchStage_RDY_pipelines_0_first__2754_AND__ETC___d13450 ; assign data75286_BITS_31_TO_0__q13 = data__h475286[31:0] ; assign data___1__h475012 = { {32{IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q133[31]}}, @@ -30205,7 +30191,7 @@ module mkCore(CLK, 2'd2) ? x_quotient__h475200 : x_remainder__h475201 ; - assign dcsr_cause__h709868 = + assign dcsr_cause__h709971 = (commitStage_commitTrap[36] && commitStage_commitTrap[35:32] == 4'd14) ? 3'd3 : @@ -30247,27 +30233,27 @@ module mkCore(CLK, assign enabled_ints__h651694 = pend_ints__h651121 & { r1__read_BITS_13_TO_0___h651670, csrf_mideleg_1_0_reg } ; - assign epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13739 = + assign epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13749 = epochManager$checkEpoch_1_check && !csrf_rg_dcsr[2] && (!fetchStage$pipelines_0_canDeq || (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3408_AND__ETC___d13484 && - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13470) ; - assign epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13881 = + regRenamingTable_rename_0_canRename__3418_AND__ETC___d13494 && + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13480) ; + assign epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13891 = epochManager$checkEpoch_1_check && !csrf_rg_dcsr[2] && (!fetchStage$pipelines_0_canDeq || (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3408_AND__ETC___d13484 && - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13877) ; - assign epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13899 = + regRenamingTable_rename_0_canRename__3418_AND__ETC___d13494 && + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13887) ; + assign epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13909 = epochManager$checkEpoch_1_check && !csrf_rg_dcsr[2] && (!fetchStage$pipelines_0_canDeq || (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3408_AND__ETC___d13484 && - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13895) ; + regRenamingTable_rename_0_canRename__3418_AND__ETC___d13494 && + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13905) ; assign f1_exp82144_MINUS_127__q136 = f1_exp__h482144 - 8'd127 ; assign f1_exp__h482144 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == @@ -30299,91 +30285,89 @@ module mkCore(CLK, (coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] : 23'd4194304 ; - assign f_csr_rsps_i_notFull__5791_AND_f_csr_reqs_firs_ETC___d15894 = + assign f_csr_rsps_i_notFull__5801_AND_f_csr_reqs_firs_ETC___d15904 = f_csr_rsps$FULL_N && (f_csr_reqs$D_OUT[75:64] != 12'd2049 || csrf_stats_module_writeQ$FULL_N) && (f_csr_reqs$D_OUT[75:64] != 12'd2048 || csrf_terminate_module_terminateQ$FULL_N) ; assign fcsr_csr__read__h609380 = { 56'd0, x__h613038 } ; - assign fetchStage_RDY_pipelines_0_first__2754_AND_epo_ETC___d13309 = - fetchStage$RDY_pipelines_0_first && - epochManager$RDY_incrementEpoch && - regRenamingTable$RDY_rename_0_getRename && - regRenamingTable$RDY_rename_0_claimRename && - rob$RDY_enqPort_0_enq && - (fetchStage$pipelines_0_first[194:192] != 3'd0 || - coreFix_aluExe_0_rsAlu$RDY_enq) ; - assign fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14023 = + assign fetchStage_RDY_pipelines_1_deq__2769_AND_NOT_f_ETC___d14093 = + fetchStage$RDY_pipelines_1_deq && + (!fetchStage$pipelines_0_canDeq || + NOT_specTagManager_canClaim__3416_3507_OR_NOT__ETC___d14089) && + (fetchStage$pipelines_1_first[194:192] != 3'd1 || + specTagManager$RDY_claimSpecTag) ; + assign fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14033 = fetchStage$pipelines_0_canDeq && (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3408_AND__ETC___d13484 && - fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13750 || + regRenamingTable_rename_0_canRename__3418_AND__ETC___d13494 && + fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13760 || !coreFix_aluExe_0_rsAlu$canEnq || (!fetchStage$pipelines_0_canDeq || - fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d14019) && + fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d14029) && coreFix_aluExe_1_rsAlu$canEnq && - !coreFix_aluExe_0_rsAlu_approximateCount__3447__ETC___d13449 ; - assign fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14105 = + !coreFix_aluExe_0_rsAlu_approximateCount__3457__ETC___d13459 ; + assign fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14115 = fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14102 && + NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14112 && (fetchStage$pipelines_0_first[194:192] == 3'd0 || fetchStage$pipelines_0_first[194:192] == 3'd1) && - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3443_co_ETC___d13453 ; - assign fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14181 = + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463 ; + assign fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14191 = fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14102 && - fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13750 || + NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14112 && + fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13760 || !coreFix_aluExe_0_rsAlu$canEnq ; - assign fetchStage_pipelines_0_canDeq__2755_AND_fetchS_ETC___d14093 = + assign fetchStage_pipelines_0_canDeq__2755_AND_fetchS_ETC___d14103 = fetchStage$pipelines_0_canDeq && - fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13967 || + fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13977 || !fetchStage$pipelines_1_canDeq || fetchStage$RDY_pipelines_1_first && - (fetchStage_pipelines_1_first__2766_BITS_194_TO_ETC___d13978 || + (fetchStage_pipelines_1_first__2766_BITS_194_TO_ETC___d13988 || !regRenamingTable$rename_1_canRename || - fetchStage_pipelines_1_first__2766_BITS_199_TO_ETC___d13990 || - IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14089) && - IF_fetchStage_RDY_pipelines_1_first__2765_AND__ETC___d13910 ; - assign fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14029 = + fetchStage_pipelines_1_first__2766_BITS_199_TO_ETC___d14000 || + IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14099) && + IF_fetchStage_RDY_pipelines_1_first__2765_AND__ETC___d13920 ; + assign fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14039 = fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3408_AND__ETC___d13484 && + regRenamingTable_rename_0_canRename__3418_AND__ETC___d13494 && (fetchStage$pipelines_0_first[194:192] == 3'd3 || fetchStage$pipelines_0_first[194:192] == 3'd4) ; - assign fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14036 = + assign fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14046 = fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3408_AND__ETC___d13484 && + regRenamingTable_rename_0_canRename__3418_AND__ETC___d13494 && fetchStage$pipelines_0_first[194:192] == 3'd2 && - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13466 || + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13476 || !coreFix_memExe_rsMem$canEnq || CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q237 ; - assign fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14058 = - fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14029 || + assign fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14068 = + fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14039 || !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq || fetchStage$pipelines_0_canDeq && (fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || - NOT_regRenamingTable_rename_0_canRename__3408__ETC___d13842 || - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d14049) ; - assign fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14070 = - fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14036 || + NOT_regRenamingTable_rename_0_canRename__3418__ETC___d13852 || + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d14059) ; + assign fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14080 = + fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14046 || fetchStage$pipelines_0_canDeq && (fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || - NOT_regRenamingTable_rename_0_canRename__3408__ETC___d13842 || - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d14061) ; - assign fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14301 = + NOT_regRenamingTable_rename_0_canRename__3418__ETC___d13852 || + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d14071) ; + assign fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14311 = fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3408_AND__ETC___d14299 || + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14309 || !coreFix_memExe_rsMem$canEnq || CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q237 ; - assign fetchStage_pipelines_0_canDeq__2755_AND_specTa_ETC___d14157 = + assign fetchStage_pipelines_0_canDeq__2755_AND_specTa_ETC___d14167 = fetchStage$pipelines_0_canDeq && specTagManager$canClaim && regRenamingTable$rename_0_canRename && !checkForException___d13008[4] && rob$enqPort_0_canEnq && - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13494 && + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13504 && fetchStage$pipelines_0_first[194:192] == 3'd1 ; assign fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13038 = (fetchStage$pipelines_0_first[194:192] == 3'd0 && @@ -30391,64 +30375,64 @@ module mkCore(CLK, rs1__h655333 != 5'd0 || imm__h655334 != 32'd0) && csr_addr__h655332[11:10] == 2'b11 ; - assign fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13750 = + assign fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13760 = (fetchStage$pipelines_0_first[194:192] == 3'd0 || fetchStage$pipelines_0_first[194:192] == 3'd1) && - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3443_co_ETC___d13453 && + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463 && (!coreFix_aluExe_1_rsAlu$canEnq || - coreFix_aluExe_0_rsAlu_approximateCount__3447__ETC___d13449) ; - assign fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13849 = + coreFix_aluExe_0_rsAlu_approximateCount__3457__ETC___d13459) ; + assign fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13859 = fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || - renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13845 ; - assign fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13961 = + renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13855 ; + assign fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13971 = fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || !regRenamingTable$rename_0_canRename || - renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13925 || - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13950 && - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13959 ; - assign fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13967 = + renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13935 || + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13960 && + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13969 ; + assign fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13977 = fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || !regRenamingTable$rename_0_canRename || - renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13925 || - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13966 ; - assign fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13984 = + renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13935 || + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13976 ; + assign fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13994 = fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || !regRenamingTable$rename_0_canRename || fetchStage$pipelines_0_first[68] || checkForException___d13008[4] || !rob$enqPort_0_canEnq || - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13966 ; - assign fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13996 = + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13976 ; + assign fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d14006 = fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || - NOT_regRenamingTable_rename_0_canRename__3408__ETC___d13766 || + NOT_regRenamingTable_rename_0_canRename__3418__ETC___d13776 || fetchStage$pipelines_0_first[194:192] != 3'd0 && fetchStage$pipelines_0_first[194:192] != 3'd1 || - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3443_co_ETC___d13453 || + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463 || coreFix_aluExe_1_rsAlu$canEnq && - !coreFix_aluExe_0_rsAlu_approximateCount__3447__ETC___d13449 ; - assign fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d14003 = + !coreFix_aluExe_0_rsAlu_approximateCount__3457__ETC___d13459 ; + assign fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d14013 = fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || - NOT_regRenamingTable_rename_0_canRename__3408__ETC___d13766 || + NOT_regRenamingTable_rename_0_canRename__3418__ETC___d13776 || fetchStage$pipelines_0_first[194:192] != 3'd0 && fetchStage$pipelines_0_first[194:192] != 3'd1 || - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3443_co_ETC___d13453 || + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463 || coreFix_aluExe_0_rsAlu$canEnq && - coreFix_aluExe_0_rsAlu_approximateCount__3447__ETC___d13449 ; - assign fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d14019 = + coreFix_aluExe_0_rsAlu_approximateCount__3457__ETC___d13459 ; + assign fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d14029 = fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || !regRenamingTable$rename_0_canRename || - fetchStage_pipelines_0_first__2757_BITS_199_TO_ETC___d13514 || + fetchStage_pipelines_0_first__2757_BITS_199_TO_ETC___d13524 || fetchStage$pipelines_0_first[194:192] != 3'd0 && fetchStage$pipelines_0_first[194:192] != 3'd1 || - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3443_co_ETC___d13453 ; - assign fetchStage_pipelines_0_first__2757_BITS_199_TO_ETC___d13514 = + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463 ; + assign fetchStage_pipelines_0_first__2757_BITS_199_TO_ETC___d13524 = fetchStage$pipelines_0_first[199:195] == 5'd0 || fetchStage$pipelines_0_first[199:195] == 5'd21 || fetchStage$pipelines_0_first[199:195] == 5'd17 || @@ -30461,21 +30445,44 @@ module mkCore(CLK, renameStage_rg_m_halt_req[4] || fetchStage$pipelines_0_first[68] || checkForException___d13008[4] || - csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13507 || + csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13517 || !rob$enqPort_0_canEnq || !epochManager$checkEpoch_0_check ; - assign fetchStage_pipelines_0_first__2757_BIT_68_2786_ETC___d13840 = + assign fetchStage_pipelines_0_first__2757_BIT_173_288_ETC___d13411 = + { fetchStage$pipelines_0_first[173], + IF_fetchStage_pipelines_0_first__2757_BITS_172_ETC___d12973, + 73'h1280000000000000000, + fetchStage$pipelines_0_first[323:260], + 5'd0, + (fetchStage$pipelines_0_first[173] && + fetchStage$pipelines_0_first[199:195] == 5'd13 && + (fetchStage$pipelines_0_first[172:161] == 12'd1 || + fetchStage$pipelines_0_first[172:161] == 12'd2 || + fetchStage$pipelines_0_first[172:161] == 12'd3)) ? + fetchStage$pipelines_0_first[194:192] == 3'd0 && + fetchStage$pipelines_0_first[178:174] == 5'd15 || + (!fetchStage$pipelines_0_first[88] || + fetchStage$pipelines_0_first[87] || + fetchStage$pipelines_0_first[86:82] != 5'd0) && + (!fetchStage$pipelines_0_first[160] || + fetchStage$pipelines_0_first[159:128] != 32'd0) : + fetchStage$pipelines_0_first[75] && + fetchStage$pipelines_0_first[74], + fetchStage$pipelines_0_first[194:192] != 3'd0, + 13'h1521, + specTagManager$currentSpecBits } ; + assign fetchStage_pipelines_0_first__2757_BIT_68_2786_ETC___d13850 = fetchStage$pipelines_0_first[68] || checkForException___d13008[4] || - csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13507 || + csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13517 || !rob$enqPort_0_canEnq || !epochManager$checkEpoch_0_check ; - assign fetchStage_pipelines_1_first__2766_BITS_194_TO_ETC___d13978 = + assign fetchStage_pipelines_1_first__2766_BITS_194_TO_ETC___d13988 = fetchStage$pipelines_1_first[194:192] == 3'd1 && (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3408_AND__ETC___d13975 || + regRenamingTable_rename_0_canRename__3418_AND__ETC___d13985 || !specTagManager$canClaim) ; - assign fetchStage_pipelines_1_first__2766_BITS_199_TO_ETC___d13990 = + assign fetchStage_pipelines_1_first__2766_BITS_199_TO_ETC___d14000 = fetchStage$pipelines_1_first[199:195] == 5'd0 || fetchStage$pipelines_1_first[199:195] == 5'd21 || fetchStage$pipelines_1_first[199:195] == 5'd17 || @@ -30487,20 +30494,20 @@ module mkCore(CLK, fetchStage$pipelines_1_first[199:195] == 5'd20 || renameStage_rg_m_halt_req[4] || fetchStage$pipelines_1_first[68] || - checkForException___d13703[4] || - csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13796 || + checkForException___d13713[4] || + csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13806 || !rob$enqPort_1_canEnq || !epochManager$checkEpoch_1_check || csrf_rg_dcsr[2] || fetchStage$pipelines_0_canDeq && - fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13984 ; - assign fetchStage_pipelines_1_first__2766_BIT_173_359_ETC___d13681 = + fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13994 ; + assign fetchStage_pipelines_1_first__2766_BIT_173_360_ETC___d13691 = { fetchStage$pipelines_1_first[173], CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q235 } ; - assign fflags__h734124 = - NOT_rob_deqPort_0_canDeq__5338_5339_OR_rob_deq_ETC___d15659 ? - y_avValue_fst__h734061 : - IF_rob_deqPort_0_canDeq__5338_THEN_IF_NOT_rob__ETC___d15665 ; + assign fflags__h734227 = + NOT_rob_deqPort_0_canDeq__5348_5349_OR_rob_deq_ETC___d15669 ? + y_avValue_fst__h734164 : + IF_rob_deqPort_0_canDeq__5348_THEN_IF_NOT_rob__ETC___d15675 ; assign fflags_csr__read__h609355 = { 59'd0, csrf_fflags_reg } ; assign frm_csr__read__h609366 = { 61'd0, csrf_frm_reg } ; assign guard__h346099 = @@ -30572,19 +30579,19 @@ module mkCore(CLK, assign guard__h590109 = { IF_theResult___snd98045_BIT_4_THEN_2_ELSE_0__q159[1], { _theResult___snd__h598045[3:0], 52'd0 } != 56'd0 } ; - assign idx__h686276 = + assign idx__h686379 = fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13751 || + NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13761 || !coreFix_aluExe_0_rsAlu$canEnq || - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13775 ; + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13785 ; assign imm__h655334 = fetchStage$pipelines_0_first[160] ? fetchStage$pipelines_0_first[159:128] : 32'd0 ; - assign k__h670531 = + assign k__h670634 = !coreFix_aluExe_0_rsAlu$canEnq || coreFix_aluExe_1_rsAlu$canEnq && - !coreFix_aluExe_0_rsAlu_approximateCount__3447__ETC___d13449 ; + !coreFix_aluExe_0_rsAlu_approximateCount__3457__ETC___d13459 ; assign mcause_csr__read__h611022 = { r1__read__h614501, csrf_mcause_code_reg } ; assign mcounteren_csr__read__h610767 = @@ -30649,13 +30656,13 @@ module mkCore(CLK, fetchStage$pipelines_0_first[199:195] == 5'd19 || fetchStage$pipelines_0_first[199:195] == 5'd20) && rob$isEmpty ; - assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14097 = + assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14107 = mmio_pRqQ_empty && epochManager$checkEpoch_0_check && !renameStage_rg_m_halt_req[4] && !fetchStage$pipelines_0_first[68] && - NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13427 ; - assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14099 = - mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14097 && + NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13437 ; + assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14109 = + mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14107 && fetchStage$pipelines_0_first[199:195] != 5'd0 && fetchStage$pipelines_0_first[199:195] != 5'd21 && fetchStage$pipelines_0_first[199:195] != 5'd17 && @@ -30723,11 +30730,11 @@ module mkCore(CLK, upd__h6875 : csrf_mcycle_ehr_data_rl) : 64'd0 ; - assign n__read__h727564 = + assign n__read__h727667 = csrf_minstret_ehr_data_dummy2_1$Q_OUT ? IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8 : 64'd0 ; - assign new_mstatus___1__h726926 = x__h726917 ; + assign new_mstatus___1__h727029 = x__h727020 ; assign next_deqP___1__h296803 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP == 3'd7) ? @@ -30742,12 +30749,12 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP + 1'd1 ; assign next_deqP___1__h328991 = coreFix_memExe_memRespLdQ_deqP + 1'd1 ; assign next_deqP___1__h332216 = coreFix_memExe_forwardQ_deqP + 1'd1 ; - assign next_pc__h723361 = + assign next_pc__h723464 = (rob$deqPort_0_deq_data[329:325] != 5'd13 && rob$deqPort_0_deq_data[97:96] == 2'd0) ? rob$deqPort_0_deq_data[95:32] : rob$deqPort_0_deq_data[425:362] + 64'd4 ; - assign old_fflags1__h733611 = + assign old_fflags1__h733714 = csrf_fflags_reg | rob$deqPort_0_deq_data[31:27] ; assign out___1_sfd__h482208 = { f1_sfd__h482145, 29'd0 } ; assign out___1_sfd__h521202 = { f2_sfd__h521139, 29'd0 } ; @@ -30956,21 +30963,21 @@ module mkCore(CLK, _theResult___snd__h598045[5] ? _theResult___sfd__h598780 : _theResult___snd__h598045[56:5] ; - assign pc__h713293 = - csrf_prv_reg_read__2787_ULE_1_4701_AND_IF_comm_ETC___d14723 ? - y_avValue_new_pc__h713085 : - y_avValue_new_pc__h713271 ; + assign pc__h713396 = + csrf_prv_reg_read__2787_ULE_1_4711_AND_IF_comm_ETC___d14733 ? + y_avValue_new_pc__h713188 : + y_avValue_new_pc__h713374 ; assign pend_ints__h651121 = { _0_CONCAT_csrf_external_int_en_vec_3_read__1664_ETC___d12798, csrf_software_int_en_vec_3 & csrf_software_int_pend_vec_3, 1'd0, csrf_software_int_en_vec_1 & csrf_software_int_pend_vec_1, 1'd0 } ; - assign po_fflags__h728848 = old_fflags1__h733611 ; - assign po_fflags__h731495 = - old_fflags1__h733611 | rob$deqPort_1_deq_data[31:27] ; - assign prv__h735791 = csrf_prv_reg ; - assign prv__h735835 = csrf_mprv_reg ? csrf_mpp_reg : csrf_prv_reg ; + assign po_fflags__h728951 = old_fflags1__h733714 ; + assign po_fflags__h731598 = + old_fflags1__h733714 | rob$deqPort_1_deq_data[31:27] ; + assign prv__h735894 = csrf_prv_reg ; + assign prv__h735938 = csrf_mprv_reg ? csrf_mpp_reg : csrf_prv_reg ; assign q___1__h475885 = 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[127:64] ; @@ -30983,7 +30990,7 @@ module mkCore(CLK, csrf_mideleg_5_3_reg, 1'b0 } ; assign r1__read_BITS_13_TO_12___h655202 = csrf_fs_reg ; - assign r1__read_BITS_61_TO_14___h726985 = + assign r1__read_BITS_61_TO_14___h727088 = { 40'd5120, csrf_tsr_reg, csrf_tw_reg, @@ -31102,24 +31109,25 @@ module mkCore(CLK, assign r___1__h475911 = 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[63:0] ; - assign regRenamingTable_RDY_commit_0_commit__4943_AND_ETC___d15003 = - regRenamingTable$RDY_commit_0_commit && rob$RDY_deqPort_0_deq && - rob$RDY_deqPort_0_deq_data && - v_f_to_TV_0$FULL_N && - fetchStage$iTlbIfc_noPendingReq && - coreFix_memExe_dTlb$noPendingReq && - NOT_rob_deqPort_0_deq_data__4344_BITS_329_TO_3_ETC___d14998 ; - assign regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13946 = + assign regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13309 = regRenamingTable$RDY_rename_0_getRename && - CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q240 && + regRenamingTable$RDY_rename_0_claimRename && + fetchStage$RDY_pipelines_0_deq && + fetchStage$RDY_pipelines_0_first && + epochManager$RDY_incrementEpoch && + (fetchStage$pipelines_0_first[194:192] != 3'd0 || + coreFix_aluExe_0_rsAlu$RDY_enq) ; + assign regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13956 = + regRenamingTable$RDY_rename_0_getRename && + CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q239 && (fetchStage$pipelines_0_first[199:195] == 5'd14 || coreFix_memExe_rsMem$RDY_enq) ; - assign regRenamingTable_RDY_rename_1_getRename__4009__ETC___d14027 = + assign regRenamingTable_RDY_rename_1_getRename__4019__ETC___d14037 = regRenamingTable$RDY_rename_1_getRename && (!fetchStage$pipelines_0_canDeq || - NOT_specTagManager_canClaim__3406_3497_OR_NOT__ETC___d14012) && - _0_OR_NOT_fetchStage_pipelines_1_first__2766_BI_ETC___d14025 ; - assign regRenamingTable_rename_0_canRename__3408_AND__ETC___d13434 = + NOT_specTagManager_canClaim__3416_3507_OR_NOT__ETC___d14022) && + _0_OR_NOT_fetchStage_pipelines_1_first__2766_BI_ETC___d14035 ; + assign regRenamingTable_rename_0_canRename__3418_AND__ETC___d13444 = regRenamingTable$rename_0_canRename && fetchStage$pipelines_0_first[199:195] != 5'd0 && fetchStage$pipelines_0_first[199:195] != 5'd21 && @@ -31130,8 +31138,8 @@ module mkCore(CLK, fetchStage$pipelines_0_first[199:195] != 5'd15 && fetchStage$pipelines_0_first[199:195] != 5'd19 && fetchStage$pipelines_0_first[199:195] != 5'd20 && - NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13432 ; - assign regRenamingTable_rename_0_canRename__3408_AND__ETC___d13484 = + NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13442 ; + assign regRenamingTable_rename_0_canRename__3418_AND__ETC___d13494 = regRenamingTable$rename_0_canRename && fetchStage$pipelines_0_first[199:195] != 5'd0 && fetchStage$pipelines_0_first[199:195] != 5'd21 && @@ -31142,64 +31150,64 @@ module mkCore(CLK, fetchStage$pipelines_0_first[199:195] != 5'd15 && fetchStage$pipelines_0_first[199:195] != 5'd19 && fetchStage$pipelines_0_first[199:195] != 5'd20 && - NOT_fetchStage_pipelines_0_first__2757_BIT_68__ETC___d13482 ; - assign regRenamingTable_rename_0_canRename__3408_AND__ETC___d13498 = - regRenamingTable_rename_0_canRename__3408_AND__ETC___d13484 && - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13494 && + NOT_fetchStage_pipelines_0_first__2757_BIT_68__ETC___d13492 ; + assign regRenamingTable_rename_0_canRename__3418_AND__ETC___d13508 = + regRenamingTable_rename_0_canRename__3418_AND__ETC___d13494 && + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13504 && fetchStage$pipelines_0_first[194:192] == 3'd1 || !specTagManager$canClaim ; - assign regRenamingTable_rename_0_canRename__3408_AND__ETC___d13828 = - regRenamingTable_rename_0_canRename__3408_AND__ETC___d13484 && + assign regRenamingTable_rename_0_canRename__3418_AND__ETC___d13838 = + regRenamingTable_rename_0_canRename__3418_AND__ETC___d13494 && fetchStage$pipelines_0_first[194:192] == 3'd2 && - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13466 || + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13476 || !coreFix_memExe_rsMem$canEnq || CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q237 ; - assign regRenamingTable_rename_0_canRename__3408_AND__ETC___d13975 = + assign regRenamingTable_rename_0_canRename__3418_AND__ETC___d13985 = regRenamingTable$rename_0_canRename && !checkForException___d13008[4] && rob$enqPort_0_canEnq && - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13973 && + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13983 && fetchStage$pipelines_0_first[194:192] == 3'd1 ; - assign regRenamingTable_rename_0_canRename__3408_AND__ETC___d14117 = + assign regRenamingTable_rename_0_canRename__3418_AND__ETC___d14127 = regRenamingTable$rename_0_canRename && !checkForException___d13008[4] && rob$enqPort_0_canEnq && (fetchStage$pipelines_0_first[194:192] == 3'd3 || fetchStage$pipelines_0_first[194:192] == 3'd4) && coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq ; - assign regRenamingTable_rename_0_canRename__3408_AND__ETC___d14123 = + assign regRenamingTable_rename_0_canRename__3418_AND__ETC___d14133 = regRenamingTable$rename_0_canRename && !checkForException___d13008[4] && rob$enqPort_0_canEnq && fetchStage$pipelines_0_first[194:192] == 3'd2 && coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13466 && + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13476 && fetchStage$pipelines_0_first[199:195] != 5'd14 ; - assign regRenamingTable_rename_0_canRename__3408_AND__ETC___d14143 = + assign regRenamingTable_rename_0_canRename__3418_AND__ETC___d14153 = regRenamingTable$rename_0_canRename && !checkForException___d13008[4] && rob$enqPort_0_canEnq && fetchStage$pipelines_0_first[194:192] == 3'd2 && coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13466 && + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13476 && (fetchStage$pipelines_0_first[191:189] == 3'd0 || fetchStage$pipelines_0_first[191:189] == 3'd2) ; - assign regRenamingTable_rename_0_canRename__3408_AND__ETC___d14151 = + assign regRenamingTable_rename_0_canRename__3418_AND__ETC___d14161 = regRenamingTable$rename_0_canRename && !checkForException___d13008[4] && rob$enqPort_0_canEnq && fetchStage$pipelines_0_first[194:192] == 3'd2 && coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13466 && + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13476 && fetchStage$pipelines_0_first[191:189] != 3'd0 && fetchStage$pipelines_0_first[191:189] != 3'd2 ; - assign regRenamingTable_rename_0_canRename__3408_AND__ETC___d14299 = + assign regRenamingTable_rename_0_canRename__3418_AND__ETC___d14309 = regRenamingTable$rename_0_canRename && !checkForException___d13008[4] && rob$enqPort_0_canEnq && fetchStage$pipelines_0_first[194:192] == 3'd2 && - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13466 ; - assign regRenamingTable_rename_1_canRename__3535_AND__ETC___d13743 = + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13476 ; + assign regRenamingTable_rename_1_canRename__3545_AND__ETC___d13753 = regRenamingTable$rename_1_canRename && fetchStage$pipelines_1_first[199:195] != 5'd0 && fetchStage$pipelines_1_first[199:195] != 5'd21 && @@ -31210,8 +31218,8 @@ module mkCore(CLK, fetchStage$pipelines_1_first[199:195] != 5'd15 && fetchStage$pipelines_1_first[199:195] != 5'd19 && fetchStage$pipelines_1_first[199:195] != 5'd20 && - NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13741 ; - assign regRenamingTable_rename_1_canRename__3535_AND__ETC___d13885 = + NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13751 ; + assign regRenamingTable_rename_1_canRename__3545_AND__ETC___d13895 = regRenamingTable$rename_1_canRename && fetchStage$pipelines_1_first[199:195] != 5'd0 && fetchStage$pipelines_1_first[199:195] != 5'd21 && @@ -31222,8 +31230,8 @@ module mkCore(CLK, fetchStage$pipelines_1_first[199:195] != 5'd15 && fetchStage$pipelines_1_first[199:195] != 5'd19 && fetchStage$pipelines_1_first[199:195] != 5'd20 && - NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13883 ; - assign regRenamingTable_rename_1_canRename__3535_AND__ETC___d13903 = + NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13893 ; + assign regRenamingTable_rename_1_canRename__3545_AND__ETC___d13913 = regRenamingTable$rename_1_canRename && fetchStage$pipelines_1_first[199:195] != 5'd0 && fetchStage$pipelines_1_first[199:195] != 5'd21 && @@ -31234,8 +31242,8 @@ module mkCore(CLK, fetchStage$pipelines_1_first[199:195] != 5'd15 && fetchStage$pipelines_1_first[199:195] != 5'd19 && fetchStage$pipelines_1_first[199:195] != 5'd20 && - NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13901 ; - assign regRenamingTable_rename_1_canRename__3535_AND__ETC___d14209 = + NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13911 ; + assign regRenamingTable_rename_1_canRename__3545_AND__ETC___d14219 = regRenamingTable$rename_1_canRename && fetchStage$pipelines_1_first[199:195] != 5'd0 && fetchStage$pipelines_1_first[199:195] != 5'd21 && @@ -31246,14 +31254,14 @@ module mkCore(CLK, fetchStage$pipelines_1_first[199:195] != 5'd15 && fetchStage$pipelines_1_first[199:195] != 5'd19 && fetchStage$pipelines_1_first[199:195] != 5'd20 && - NOT_fetchStage_pipelines_1_first__2766_BIT_68__ETC___d14207 ; - assign regRenamingTable_rename_1_canRename__3535_AND__ETC___d14253 = - regRenamingTable_rename_1_canRename__3535_AND__ETC___d14209 && + NOT_fetchStage_pipelines_1_first__2766_BIT_68__ETC___d14217 ; + assign regRenamingTable_rename_1_canRename__3545_AND__ETC___d14263 = + regRenamingTable_rename_1_canRename__3545_AND__ETC___d14219 && (fetchStage$pipelines_1_first[194:192] == 3'd3 || fetchStage$pipelines_1_first[194:192] == 3'd4) && (!fetchStage$pipelines_0_canDeq || !regRenamingTable$rename_0_canRename || - renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13925 || + renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13935 || fetchStage$pipelines_0_first[194:192] != 3'd3 && fetchStage$pipelines_0_first[194:192] != 3'd4) && coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq ; @@ -31282,20 +31290,20 @@ module mkCore(CLK, IF_fetchStage_pipelines_0_first__2757_BIT_68_2_ETC___d13130 : IF_checkForException_3008_BIT_4_3009_THEN_IF_c_ETC___d13159) == 4'd3 ; - assign renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13764 = + assign renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13774 = renameStage_rg_m_halt_req[4] || fetchStage$pipelines_0_first[68] || - IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d13761 || + IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d13771 || !rob$enqPort_0_canEnq || !epochManager$checkEpoch_0_check ; - assign renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13804 = + assign renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13814 = renameStage_rg_m_halt_req[4] || fetchStage$pipelines_1_first[68] || - IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d13798 || + IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d13808 || !rob$enqPort_1_canEnq || !epochManager$checkEpoch_1_check || - csrf_rg_dcsr_read__1720_BIT_2_3062_OR_NOT_fetc_ETC___d13503 ; - assign renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13845 = + csrf_rg_dcsr_read__1720_BIT_2_3062_OR_NOT_fetc_ETC___d13513 ; + assign renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13855 = renameStage_rg_m_halt_req[4] || fetchStage$pipelines_0_first[68] || IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[0] || @@ -31314,14 +31322,14 @@ module mkCore(CLK, IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[13] || IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[14] || IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[15] ; - assign renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13925 = + assign renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13935 = renameStage_rg_m_halt_req[4] || fetchStage$pipelines_0_first[68] || checkForException___d13008[4] || !rob$enqPort_0_canEnq ; - assign renaming_spec_bits__h686145 = + assign renaming_spec_bits__h686248 = fetchStage$pipelines_0_canDeq ? - y_avValue_fst__h682540 : + y_avValue_fst__h682643 : specTagManager$currentSpecBits ; assign res_data__h337873 = { 32'hFFFFFFFF, x__h337888 } ; assign res_data__h337878 = @@ -31598,7 +31606,7 @@ module mkCore(CLK, guard__h581638 } ; assign result__h646700 = w__h646695 & y__h646729 ; assign result__h646751 = ~x__h646750 ; - assign rg_core_run_state_read__3058_EQ_2_3059_AND_NOT_ETC___d15730 = + assign rg_core_run_state_read__3058_EQ_2_3059_AND_NOT_ETC___d15740 = rg_core_run_state == 2'd2 && !flush_reservation && !flush_tlbs && !update_vm_info && fetchStage$iTlbIfc_flush_done && @@ -31606,13 +31614,14 @@ module mkCore(CLK, !flush_caches ; assign rg_tdata1__read__h612210 = { r1__read__h614604, csrf_rg_tdata1_data } ; - assign rob_RDY_enqPort_1_enq__4075_AND_NOT_fetchStage_ETC___d14083 = - rob$RDY_enqPort_1_enq && - (!fetchStage$pipelines_0_canDeq || - NOT_specTagManager_canClaim__3406_3497_OR_NOT__ETC___d14079) && - (fetchStage$pipelines_1_first[194:192] != 3'd1 || - specTagManager$RDY_claimSpecTag) ; - assign rob_deqPort_0_deq_data__4344_BITS_161_TO_98_43_ETC___d15316 = + assign rob_RDY_deqPort_0_deq__4351_AND_rob_RDY_deqPor_ETC___d15013 = + rob$RDY_deqPort_0_deq && rob$RDY_deqPort_0_deq_data && + regRenamingTable$RDY_commit_0_commit && + v_f_to_TV_0$FULL_N && + fetchStage$iTlbIfc_noPendingReq && + coreFix_memExe_dTlb$noPendingReq && + NOT_rob_deqPort_0_deq_data__4354_BITS_329_TO_3_ETC___d15008 ; + assign rob_deqPort_0_deq_data__4354_BITS_161_TO_98_43_ETC___d15326 = { rob$deqPort_0_deq_data[161:98], (rob$deqPort_0_deq_data[329:325] != 5'd13 && rob$deqPort_0_deq_data[97:96] == 2'd0) ? @@ -31622,21 +31631,21 @@ module mkCore(CLK, { 2'd1, rob$deqPort_0_deq_data[95:32] } : { 2'd2, (rob$deqPort_0_deq_data[329:325] == 5'd13) ? - data_warl_xformed__h723335 : + data_warl_xformed__h723438 : rob$deqPort_0_deq_data[95:32] }), 5'h0A, rob$deqPort_0_deq_data[26], - x__h726917, - x_prv__h723923, + x__h727020, + x_prv__h724026, 64'hAAAAAAAAAAAAAAAA, - x__h727058, + x__h727161, 128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; - assign rob_deqPort_0_deq_data__4344_BIT_166_4360_CONC_ETC___d14409 = + assign rob_deqPort_0_deq_data__4354_BIT_166_4370_CONC_ETC___d14419 = { rob$deqPort_0_deq_data[166], rob$deqPort_0_deq_data[166] ? CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q247 : CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q248 } ; - assign rob_deqPort_0_deq_data__4344_BIT_181_4419_CONC_ETC___d14510 = + assign rob_deqPort_0_deq_data__4354_BIT_181_4429_CONC_ETC___d14520 = { rob$deqPort_0_deq_data[181], CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q246 } ; assign robdeqPort_0_deq_data_BITS_95_TO_32__q245 = @@ -31827,14 +31836,14 @@ module mkCore(CLK, coreFix_memExe_regToExeQ$first[75:12] << x__h181702 ; assign sie_csr__read__h609646 = { r1__read__h613457, 1'b0 } ; assign sip_csr__read__h610020 = { r1__read__h613991, 1'b0 } ; - assign spec_bits__h689304 = specTagManager$currentSpecBits | y__h689317 ; + assign spec_bits__h689407 = specTagManager$currentSpecBits | y__h689420 ; assign sstatus_csr__read__h609576 = { r1__read__h613053, csrf_ie_vec_0 } ; assign stvec_csr__read__h609689 = { r1__read__h613967, csrf_stvec_mode_low_reg } ; - assign trap_val__h710350 = - commitStage_commitTrap[36] ? 64'd0 : trap_val__h711388 ; - assign tsr_val__h727178 = csrf_tsr_reg ; - assign tvm_val__h727180 = csrf_tvm_reg ; + assign trap_val__h710453 = + commitStage_commitTrap[36] ? 64'd0 : trap_val__h711491 ; + assign tsr_val__h727281 = csrf_tsr_reg ; + assign tvm_val__h727283 = csrf_tvm_reg ; assign upd__h3994 = WILL_FIRE_RL_commitStage_doCommitSystemInst ? MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1 : @@ -31844,7 +31853,7 @@ module mkCore(CLK, MUX_csrf_mcycle_ehr_data_dummy2_0$write_1__SEL_1 ? f_csr_reqs$D_OUT[63:0] : rob$deqPort_0_deq_data[95:32] ; - assign upd__h727675 = + assign upd__h727778 = MUX_csrf_minstret_ehr_data_dummy2_0$write_1__SEL_1 ? f_csr_reqs$D_OUT[63:0] : rob$deqPort_0_deq_data[95:32] ; @@ -32078,22 +32087,22 @@ module mkCore(CLK, sbCons$lazyLookup_0_get[2] ? rf$read_0_rd2 : y_avValue__h637580 ; assign x__h646699 = 12'd1 << coreFix_aluExe_1_exeToFinQ$first[15:12] ; assign x__h646750 = 12'd1 << coreFix_aluExe_0_exeToFinQ$first[15:12] ; - assign x__h703283 = + assign x__h703386 = (!rob$deqPort_0_deq_data[166] && (rob$deqPort_0_deq_data[165:162] == 4'd1 || rob$deqPort_0_deq_data[165:162] == 4'd12)) ? rob$deqPort_0_deq_data[161:98] : rob$deqPort_0_deq_data[95:32] ; - assign x__h713324 = { cause_code__h710349, 2'b0 } ; - assign x__h715551 = + assign x__h713427 = { cause_code__h710452, 2'b0 } ; + assign x__h715654 = { csrf_fs_reg == 2'b11, - IF_csrf_prv_reg_read__2787_ULE_1_4701_AND_IF_c_ETC___d14925 } ; - assign x__h715743 = - { commitStage_commitTrap[36], 59'b0, cause_code__h710349 } ; - assign x__h723465 = { 1'b0, csrf_spp_reg } ; - assign x__h726917 = + IF_csrf_prv_reg_read__2787_ULE_1_4711_AND_IF_c_ETC___d14935 } ; + assign x__h715846 = + { commitStage_commitTrap[36], 59'b0, cause_code__h710452 } ; + assign x__h723568 = { 1'b0, csrf_spp_reg } ; + assign x__h727020 = { 1'b1, - r1__read_BITS_61_TO_14___h726985, + r1__read_BITS_61_TO_14___h727088, 2'b11, csrf_mpp_reg, 2'b0, @@ -32106,7 +32115,7 @@ module mkCore(CLK, 1'b0, csrf_ie_vec_1, csrf_ie_vec_0 } ; - assign x__h727058 = + assign x__h727161 = { csrf_fs_reg == 2'b11, 40'd5120, csrf_tsr_reg, @@ -32117,16 +32126,16 @@ module mkCore(CLK, csrf_mprv_reg, 2'd0, csrf_fs_reg, - IF_rob_deqPort_0_deq_data__4344_BITS_329_TO_32_ETC___d15306 } ; - assign x__h733638 = + IF_rob_deqPort_0_deq_data__4354_BITS_329_TO_32_ETC___d15316 } ; + assign x__h733741 = { 1'b1, - y_avValue_snd_snd_snd_snd_snd_snd_snd__h733620[62:15], + y_avValue_snd_snd_snd_snd_snd_snd_snd__h733723[62:15], 2'b11, - y_avValue_snd_snd_snd_snd_snd_snd_snd__h733620[12:0] } ; - assign x__h734388 = - NOT_rob_deqPort_0_canDeq__5338_5339_OR_rob_deq_ETC___d15659 ? - y_avValue_snd_snd_snd_fst__h734198 : - IF_rob_deqPort_0_canDeq__5338_THEN_IF_NOT_rob__ETC___d15684 ; + y_avValue_snd_snd_snd_snd_snd_snd_snd__h733723[12:0] } ; + assign x__h734491 = + NOT_rob_deqPort_0_canDeq__5348_5349_OR_rob_deq_ETC___d15669 ? + y_avValue_snd_snd_snd_fst__h734301 : + IF_rob_deqPort_0_canDeq__5348_THEN_IF_NOT_rob__ETC___d15694 ; assign x__h76239 = mmio_pRqQ_data_0[31:0] ; assign x_addr__h314077 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? @@ -32136,16 +32145,16 @@ module mkCore(CLK, EN_mmioToPlatform_pRq_enq ? mmio_pRqQ_enqReq_lat_0$wget[31:0] : mmio_pRqQ_enqReq_rl[31:0] ; - assign x_data_imm__h677563 = fetchStage$pipelines_0_first[159:128] ; - assign x_data_imm__h693617 = fetchStage$pipelines_1_first[159:128] ; + assign x_data_imm__h677666 = fetchStage$pipelines_0_first[159:128] ; + assign x_data_imm__h693720 = fetchStage$pipelines_1_first[159:128] ; assign x_decodeInfo_frm__h655017 = csrf_frm_reg ; - assign x_prv__h713393 = - csrf_prv_reg_read__2787_ULE_1_4701_AND_IF_comm_ETC___d14723 ? + assign x_prv__h713496 = + csrf_prv_reg_read__2787_ULE_1_4711_AND_IF_comm_ETC___d14733 ? 2'd1 : 2'd3 ; - assign x_prv__h723923 = + assign x_prv__h724026 = (rob$deqPort_0_deq_data[329:325] == 5'd19) ? - x__h723465 : + x__h723568 : csrf_mpp_reg ; assign x_quotient__h475200 = coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[75] ? @@ -32175,15 +32184,15 @@ module mkCore(CLK, ~csrf_mideleg_5_3_reg, 1'd1, ~csrf_mideleg_1_0_reg } ; - assign y__h689317 = 12'd1 << specTagManager$nextSpecTag ; - assign y__h731332 = + assign y__h689420 = 12'd1 << specTagManager$nextSpecTag ; + assign y__h731435 = rob$deqPort_0_canDeq ? - y_avValue_snd_snd_snd_snd_snd_fst__h731355 : + y_avValue_snd_snd_snd_snd_snd_fst__h731458 : 64'd0 ; - assign y__h734147 = - NOT_rob_deqPort_0_canDeq__5338_5339_OR_rob_deq_ETC___d15659 ? - y_avValue_snd_snd_snd_snd_snd_fst__h734208 : - y__h731332 ; + assign y__h734250 = + NOT_rob_deqPort_0_canDeq__5348_5349_OR_rob_deq_ETC___d15669 ? + y_avValue_snd_snd_snd_snd_snd_fst__h734311 : + y__h731435 ; assign y_avValue__h180567 = NOT_coreFix_memExe_bypassWire_0_whas__568_574__ETC___d1595 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : @@ -32220,21 +32229,21 @@ module mkCore(CLK, NOT_coreFix_aluExe_0_bypassWire_0_whas__2202_2_ETC___d12257 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12461 ; - assign y_avValue_fst__h682477 = + assign y_avValue_fst__h682580 = (fetchStage$pipelines_0_first[194:192] == 3'd1) ? - spec_bits__h689304 : + spec_bits__h689407 : specTagManager$currentSpecBits ; - assign y_avValue_fst__h682506 = - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13494 ? - y_avValue_fst__h682477 : + assign y_avValue_fst__h682609 = + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13504 ? + y_avValue_fst__h682580 : specTagManager$currentSpecBits ; - assign y_avValue_fst__h682540 = + assign y_avValue_fst__h682643 = ((fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3408_AND__ETC___d13434) ? - y_avValue_fst__h682506 : + regRenamingTable_rename_0_canRename__3418_AND__ETC___d13444) ? + y_avValue_fst__h682609 : specTagManager$currentSpecBits ; - assign y_avValue_fst__h730870 = + assign y_avValue_fst__h730973 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[167] || rob$deqPort_0_deq_data[329:325] == 5'd0 || @@ -32248,10 +32257,10 @@ module mkCore(CLK, rob$deqPort_0_deq_data[329:325] == 5'd20) ? 5'd0 : rob$deqPort_0_deq_data[31:27] ; - assign y_avValue_fst__h734029 = - IF_rob_deqPort_0_canDeq__5338_THEN_IF_NOT_rob__ETC___d15665 | + assign y_avValue_fst__h734132 = + IF_rob_deqPort_0_canDeq__5348_THEN_IF_NOT_rob__ETC___d15675 | rob$deqPort_1_deq_data[31:27] ; - assign y_avValue_fst__h734061 = + assign y_avValue_fst__h734164 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[329:325] == 5'd0 || @@ -32263,17 +32272,17 @@ module mkCore(CLK, rob$deqPort_1_deq_data[329:325] == 5'd15 || rob$deqPort_1_deq_data[329:325] == 5'd19 || rob$deqPort_1_deq_data[329:325] == 5'd20) ? - IF_rob_deqPort_0_canDeq__5338_THEN_IF_NOT_rob__ETC___d15665 : - y_avValue_fst__h734029 ; - assign y_avValue_new_pc__h713085 = + IF_rob_deqPort_0_canDeq__5348_THEN_IF_NOT_rob__ETC___d15675 : + y_avValue_fst__h734132 ; + assign y_avValue_new_pc__h713188 = (csrf_stvec_mode_low_reg && commitStage_commitTrap[36]) ? - base__h713309 + { 58'd0, x__h713324 } : - base__h713309 ; - assign y_avValue_new_pc__h713271 = + base__h713412 + { 58'd0, x__h713427 } : + base__h713412 ; + assign y_avValue_new_pc__h713374 = (csrf_mtvec_mode_low_reg && commitStage_commitTrap[36]) ? - base__h713329 + { 58'd0, x__h713324 } : - base__h713329 ; - assign y_avValue_snd_snd_snd_fst__h731345 = + base__h713432 + { 58'd0, x__h713427 } : + base__h713432 ; + assign y_avValue_snd_snd_snd_fst__h731448 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[167] || rob$deqPort_0_deq_data[329:325] == 5'd0 || @@ -32287,7 +32296,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[329:325] == 5'd20) ? 2'd0 : 2'd1 ; - assign y_avValue_snd_snd_snd_fst__h734198 = + assign y_avValue_snd_snd_snd_fst__h734301 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[329:325] == 5'd0 || @@ -32299,12 +32308,12 @@ module mkCore(CLK, rob$deqPort_1_deq_data[329:325] == 5'd15 || rob$deqPort_1_deq_data[329:325] == 5'd19 || rob$deqPort_1_deq_data[329:325] == 5'd20) ? - IF_rob_deqPort_0_canDeq__5338_THEN_IF_NOT_rob__ETC___d15684 : - y_avValue_snd_snd_snd_fst__h734234 ; - assign y_avValue_snd_snd_snd_fst__h734234 = - IF_rob_deqPort_0_canDeq__5338_THEN_IF_NOT_rob__ETC___d15684 + + IF_rob_deqPort_0_canDeq__5348_THEN_IF_NOT_rob__ETC___d15694 : + y_avValue_snd_snd_snd_fst__h734337 ; + assign y_avValue_snd_snd_snd_fst__h734337 = + IF_rob_deqPort_0_canDeq__5348_THEN_IF_NOT_rob__ETC___d15694 + 2'd1 ; - assign y_avValue_snd_snd_snd_snd_snd_fst__h731355 = + assign y_avValue_snd_snd_snd_snd_snd_fst__h731458 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[167] || rob$deqPort_0_deq_data[329:325] == 5'd0 || @@ -32318,7 +32327,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[329:325] == 5'd20) ? 64'd0 : 64'd1 ; - assign y_avValue_snd_snd_snd_snd_snd_fst__h734208 = + assign y_avValue_snd_snd_snd_snd_snd_fst__h734311 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[329:325] == 5'd0 || @@ -32330,10 +32339,10 @@ module mkCore(CLK, rob$deqPort_1_deq_data[329:325] == 5'd15 || rob$deqPort_1_deq_data[329:325] == 5'd19 || rob$deqPort_1_deq_data[329:325] == 5'd20) ? - y__h731332 : - y_avValue_snd_snd_snd_snd_snd_fst__h734244 ; - assign y_avValue_snd_snd_snd_snd_snd_fst__h734244 = y__h731332 + 64'd1 ; - assign y_avValue_snd_snd_snd_snd_snd_snd_snd__h733620 = x__h726917 ; + y__h731435 : + y_avValue_snd_snd_snd_snd_snd_fst__h734347 ; + assign y_avValue_snd_snd_snd_snd_snd_fst__h734347 = y__h731435 + 64'd1 ; + assign y_avValue_snd_snd_snd_snd_snd_snd_snd__h733723 = x__h727020 ; always@(v_f_to_TV_1$D_OUT) begin case (v_f_to_TV_1$D_OUT[475:464]) @@ -32642,9 +32651,9 @@ module mkCore(CLK, always@(commitStage_commitTrap) begin case (commitStage_commitTrap[35:32]) - 4'd0, 4'd3: trap_val__h711388 = commitStage_commitTrap[164:101]; - 4'd2: trap_val__h711388 = { 32'd0, commitStage_commitTrap[31:0] }; - default: trap_val__h711388 = + 4'd0, 4'd3: trap_val__h711491 = commitStage_commitTrap[164:101]; + 4'd2: trap_val__h711491 = { 32'd0, commitStage_commitTrap[31:0] }; + default: trap_val__h711491 = (commitStage_commitTrap[35:32] != 4'd8 && commitStage_commitTrap[35:32] != 4'd9 && commitStage_commitTrap[35:32] != 4'd11) ? @@ -32700,46 +32709,46 @@ module mkCore(CLK, n__read__h611359 or n__read__h611550 or csrf_time_reg) begin case (f_csr_reqs$D_OUT[75:64]) - 12'd1: data_out__h738236 = fflags_csr__read__h609355; - 12'd2: data_out__h738236 = frm_csr__read__h609366; - 12'd3: data_out__h738236 = fcsr_csr__read__h609380; - 12'd256: data_out__h738236 = sstatus_csr__read__h609576; - 12'd260: data_out__h738236 = sie_csr__read__h609646; - 12'd261: data_out__h738236 = stvec_csr__read__h609689; - 12'd262: data_out__h738236 = scounteren_csr__read__h609742; - 12'd320: data_out__h738236 = csrf_sscratch_csr; - 12'd321: data_out__h738236 = csrf_sepc_csr; - 12'd322: data_out__h738236 = scause_csr__read__h609880; - 12'd323: data_out__h738236 = csrf_stval_csr; - 12'd324: data_out__h738236 = sip_csr__read__h610020; - 12'd384: data_out__h738236 = satp_csr__read__h610083; - 12'd768: data_out__h738236 = mstatus_csr__read__h610226; - 12'd769: data_out__h738236 = 64'h800000000014112D; - 12'd770: data_out__h738236 = medeleg_csr__read__h610374; - 12'd771: data_out__h738236 = mideleg_csr__read__h610469; - 12'd772: data_out__h738236 = mie_csr__read__h610593; - 12'd773: data_out__h738236 = mtvec_csr__read__h610675; - 12'd774: data_out__h738236 = mcounteren_csr__read__h610767; - 12'd832: data_out__h738236 = csrf_mscratch_csr; - 12'd833: data_out__h738236 = csrf_mepc_csr; - 12'd834: data_out__h738236 = mcause_csr__read__h611022; - 12'd835: data_out__h738236 = csrf_mtval_csr; - 12'd836: data_out__h738236 = mip_csr__read__h611255; - 12'd1952: data_out__h738236 = csrf_rg_tselect; - 12'd1953: data_out__h738236 = rg_tdata1__read__h612210; - 12'd1954: data_out__h738236 = csrf_rg_tdata2; - 12'd1955: data_out__h738236 = csrf_rg_tdata3; - 12'd1968: data_out__h738236 = csrf_rg_dcsr; - 12'd1969: data_out__h738236 = csrf_rg_dpc; - 12'd1970: data_out__h738236 = csrf_rg_dscratch0; - 12'd1971: data_out__h738236 = csrf_rg_dscratch1; + 12'd1: data_out__h738339 = fflags_csr__read__h609355; + 12'd2: data_out__h738339 = frm_csr__read__h609366; + 12'd3: data_out__h738339 = fcsr_csr__read__h609380; + 12'd256: data_out__h738339 = sstatus_csr__read__h609576; + 12'd260: data_out__h738339 = sie_csr__read__h609646; + 12'd261: data_out__h738339 = stvec_csr__read__h609689; + 12'd262: data_out__h738339 = scounteren_csr__read__h609742; + 12'd320: data_out__h738339 = csrf_sscratch_csr; + 12'd321: data_out__h738339 = csrf_sepc_csr; + 12'd322: data_out__h738339 = scause_csr__read__h609880; + 12'd323: data_out__h738339 = csrf_stval_csr; + 12'd324: data_out__h738339 = sip_csr__read__h610020; + 12'd384: data_out__h738339 = satp_csr__read__h610083; + 12'd768: data_out__h738339 = mstatus_csr__read__h610226; + 12'd769: data_out__h738339 = 64'h800000000014112D; + 12'd770: data_out__h738339 = medeleg_csr__read__h610374; + 12'd771: data_out__h738339 = mideleg_csr__read__h610469; + 12'd772: data_out__h738339 = mie_csr__read__h610593; + 12'd773: data_out__h738339 = mtvec_csr__read__h610675; + 12'd774: data_out__h738339 = mcounteren_csr__read__h610767; + 12'd832: data_out__h738339 = csrf_mscratch_csr; + 12'd833: data_out__h738339 = csrf_mepc_csr; + 12'd834: data_out__h738339 = mcause_csr__read__h611022; + 12'd835: data_out__h738339 = csrf_mtval_csr; + 12'd836: data_out__h738339 = mip_csr__read__h611255; + 12'd1952: data_out__h738339 = csrf_rg_tselect; + 12'd1953: data_out__h738339 = rg_tdata1__read__h612210; + 12'd1954: data_out__h738339 = csrf_rg_tdata2; + 12'd1955: data_out__h738339 = csrf_rg_tdata3; + 12'd1968: data_out__h738339 = csrf_rg_dcsr; + 12'd1969: data_out__h738339 = csrf_rg_dpc; + 12'd1970: data_out__h738339 = csrf_rg_dscratch0; + 12'd1971: data_out__h738339 = csrf_rg_dscratch1; 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: - data_out__h738236 = 64'd0; - 12'd2049: data_out__h738236 = x_reg_ifc__read__h609485; - 12'd2816, 12'd3072: data_out__h738236 = n__read__h611359; - 12'd2818, 12'd3074: data_out__h738236 = n__read__h611550; - 12'd3073: data_out__h738236 = csrf_time_reg; - default: data_out__h738236 = 64'b0; + data_out__h738339 = 64'd0; + 12'd2049: data_out__h738339 = x_reg_ifc__read__h609485; + 12'd2816, 12'd3072: data_out__h738339 = n__read__h611359; + 12'd2818, 12'd3074: data_out__h738339 = n__read__h611550; + 12'd3073: data_out__h738339 = csrf_time_reg; + default: data_out__h738339 = 64'b0; endcase end always@(coreFix_aluExe_1_dispToRegQ$first or @@ -33162,16 +33171,16 @@ module mkCore(CLK, 4'd11, 4'd12, 4'd13: - i__h710364 = commitStage_commitTrap[35:32]; - default: i__h710364 = 4'd15; + i__h710467 = commitStage_commitTrap[35:32]; + default: i__h710467 = 4'd15; endcase end always@(commitStage_commitTrap) begin case (commitStage_commitTrap[35:32]) 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: - i__h710524 = commitStage_commitTrap[35:32]; - default: i__h710524 = 4'd15; + i__h710627 = commitStage_commitTrap[35:32]; + default: i__h710627 = 4'd15; endcase end always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) @@ -37518,15 +37527,15 @@ module mkCore(CLK, 4'd13; endcase end - always@(k__h670531 or + always@(k__h670634 or coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq) begin - case (k__h670531) + case (k__h670634) 1'd0: - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3443_co_ETC___d13453 = + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463 = coreFix_aluExe_0_rsAlu$canEnq; 1'd1: - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3443_co_ETC___d13453 = + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463 = coreFix_aluExe_1_rsAlu$canEnq; endcase end @@ -37535,65 +37544,65 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13466 = + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13476 = coreFix_memExe_lsq$enqLdTag[6]; - default: IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13466 = + default: IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13476 = coreFix_memExe_lsq$enqStTag[6]; endcase end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13466 or - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3443_co_ETC___d13453 or + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13476 or + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13470 = - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3443_co_ETC___d13453; + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13480 = + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463; 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13470 = + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13480 = coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq; - default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13470 = + default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13480 = fetchStage$pipelines_0_first[194:192] != 3'd2 || coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13466; + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13476; endcase end - always@(k__h670531 or + always@(k__h670634 or coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq) begin - case (k__h670531) + case (k__h670634) 1'd0: - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__344_ETC___d13487 = + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__345_ETC___d13497 = !coreFix_aluExe_0_rsAlu$canEnq; 1'd1: - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__344_ETC___d13487 = + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__345_ETC___d13497 = !coreFix_aluExe_1_rsAlu$canEnq; endcase end always@(fetchStage$pipelines_0_first or - regRenamingTable_rename_0_canRename__3408_AND__ETC___d13434 or - NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13489 or + regRenamingTable_rename_0_canRename__3418_AND__ETC___d13444 or + NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13499 or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13466 or + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13476 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13494 = - NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13489; + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13504 = + NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13499; 3'd2: - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13494 = + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13504 = coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13466 && - regRenamingTable_rename_0_canRename__3408_AND__ETC___d13434; + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13476 && + regRenamingTable_rename_0_canRename__3418_AND__ETC___d13444; 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13494 = + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13504 = coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq && - regRenamingTable_rename_0_canRename__3408_AND__ETC___d13434; - default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13494 = - regRenamingTable_rename_0_canRename__3408_AND__ETC___d13434; + regRenamingTable_rename_0_canRename__3418_AND__ETC___d13444; + default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13504 = + regRenamingTable_rename_0_canRename__3418_AND__ETC___d13444; endcase end always@(fetchStage$pipelines_0_first or @@ -37601,32 +37610,32 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13524 = + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13534 = !coreFix_memExe_lsq$enqLdTag[6]; - default: IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13524 = + default: IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13534 = !coreFix_memExe_lsq$enqStTag[6]; endcase end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13524 or - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__344_ETC___d13487 or + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13534 or + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__345_ETC___d13497 or specTagManager$canClaim or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13529 = - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__344_ETC___d13487 || + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13539 = + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__345_ETC___d13497 || fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim; 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13529 = + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13539 = !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq; - default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13529 = + default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13539 = fetchStage$pipelines_0_first[194:192] == 3'd2 && (!coreFix_memExe_rsMem$canEnq || - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13524); + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13534); endcase end always@(fetchStage$pipelines_1_first) @@ -37696,36 +37705,36 @@ module mkCore(CLK, begin case (fetchStage$pipelines_1_first[194:192]) 3'd0, 3'd1, 3'd2, 3'd3: - IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13589 = + IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13599 = fetchStage$pipelines_1_first[194:174]; 3'd4: - IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13589 = + IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13599 = { fetchStage$pipelines_1_first[194:192], 9'h0AA, fetchStage$pipelines_1_first[182:178], CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q236, fetchStage$pipelines_1_first[174] }; - default: IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13589 = + default: IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13599 = 21'd1485482; endcase end - always@(idx__h686276 or + always@(idx__h686379 or fetchStage$pipelines_0_canDeq or - NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13751 or + NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13761 or coreFix_aluExe_0_rsAlu$canEnq or - NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13757 or + NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13767 or coreFix_aluExe_1_rsAlu$canEnq) begin - case (idx__h686276) + case (idx__h686379) 1'd0: - SEL_ARR_fetchStage_pipelines_0_canDeq__2755_AN_ETC___d13777 = + SEL_ARR_fetchStage_pipelines_0_canDeq__2755_AN_ETC___d13787 = fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13751 || + NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13761 || !coreFix_aluExe_0_rsAlu$canEnq; 1'd1: - SEL_ARR_fetchStage_pipelines_0_canDeq__2755_AN_ETC___d13777 = + SEL_ARR_fetchStage_pipelines_0_canDeq__2755_AN_ETC___d13787 = fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13757 || + NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13767 || !coreFix_aluExe_1_rsAlu$canEnq; endcase end @@ -37741,61 +37750,61 @@ module mkCore(CLK, endcase end always@(fetchStage$pipelines_0_first or - renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13845 or - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__344_ETC___d13487 or - fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13849 or + renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13855 or + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__345_ETC___d13497 or + fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13859 or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13524 or + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13534 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13855 = - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__344_ETC___d13487 || - fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13849; + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13865 = + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__345_ETC___d13497 || + fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13859; 3'd2: - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13855 = + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13865 = !coreFix_memExe_rsMem$canEnq || - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13524 || - renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13845; + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13534 || + renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13855; 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13855 = + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13865 = !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq || - renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13845; - default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13855 = - renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13845; + renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13855; + default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13865 = + renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13855; endcase end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13466 or - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3443_co_ETC___d13453) + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13476 or + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13877 = - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3443_co_ETC___d13453; - default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13877 = + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13887 = + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463; + default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13887 = fetchStage$pipelines_0_first[194:192] != 3'd2 || coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13466; + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13476; endcase end always@(fetchStage$pipelines_0_first or - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13466 or - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3443_co_ETC___d13453 or + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13476 or + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13895 = - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3443_co_ETC___d13453; + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13905 = + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463; 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13895 = + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13905 = coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq; - default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13895 = + default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13905 = fetchStage$pipelines_0_first[194:192] != 3'd2 || - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13466; + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13476; endcase end always@(fetchStage$pipelines_1_first or @@ -37810,62 +37819,31 @@ module mkCore(CLK, endcase end always@(fetchStage$pipelines_1_first or - regRenamingTable_rename_1_canRename__3535_AND__ETC___d13743 or - SEL_ARR_fetchStage_pipelines_0_canDeq__2755_AN_ETC___d13777 or - NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d13861 or - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13892 or - regRenamingTable_rename_1_canRename__3535_AND__ETC___d13903 or - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13874 or + regRenamingTable_rename_1_canRename__3545_AND__ETC___d13753 or + SEL_ARR_fetchStage_pipelines_0_canDeq__2755_AN_ETC___d13787 or + NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d13871 or + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13902 or + regRenamingTable_rename_1_canRename__3545_AND__ETC___d13913 or + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13884 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq or - regRenamingTable_rename_1_canRename__3535_AND__ETC___d13885) + regRenamingTable_rename_1_canRename__3545_AND__ETC___d13895) begin case (fetchStage$pipelines_1_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13907 = - !SEL_ARR_fetchStage_pipelines_0_canDeq__2755_AN_ETC___d13777 && - NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d13861; + IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13917 = + !SEL_ARR_fetchStage_pipelines_0_canDeq__2755_AN_ETC___d13787 && + NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d13871; 3'd2: - IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13907 = - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13892 && - regRenamingTable_rename_1_canRename__3535_AND__ETC___d13903; + IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13917 = + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13902 && + regRenamingTable_rename_1_canRename__3545_AND__ETC___d13913; 3'd3, 3'd4: - IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13907 = - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13874 && + IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13917 = + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13884 && coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq && - regRenamingTable_rename_1_canRename__3535_AND__ETC___d13885; - default: IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13907 = - regRenamingTable_rename_1_canRename__3535_AND__ETC___d13743; - endcase - end - always@(k__h670531 or - coreFix_aluExe_0_rsAlu$RDY_enq or coreFix_aluExe_1_rsAlu$RDY_enq) - begin - case (k__h670531) - 1'd0: - CASE_k70531_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239 = - coreFix_aluExe_0_rsAlu$RDY_enq; - 1'd1: - CASE_k70531_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239 = - coreFix_aluExe_1_rsAlu$RDY_enq; - endcase - end - always@(fetchStage$pipelines_0_first or - coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13524 or - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__344_ETC___d13487 or - coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) - begin - case (fetchStage$pipelines_0_first[194:192]) - 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13952 = - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__344_ETC___d13487; - 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13952 = - !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq; - default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13952 = - fetchStage$pipelines_0_first[194:192] == 3'd2 && - (!coreFix_memExe_rsMem$canEnq || - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13524); + regRenamingTable_rename_1_canRename__3545_AND__ETC___d13895; + default: IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13917 = + regRenamingTable_rename_1_canRename__3545_AND__ETC___d13753; endcase end always@(fetchStage$pipelines_0_first or @@ -37873,105 +37851,136 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q240 = + CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q239 = coreFix_memExe_lsq$RDY_enqLd; - default: CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q240 = + default: CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q239 = coreFix_memExe_lsq$RDY_enqSt; endcase end + always@(k__h670634 or + coreFix_aluExe_0_rsAlu$RDY_enq or coreFix_aluExe_1_rsAlu$RDY_enq) + begin + case (k__h670634) + 1'd0: + CASE_k70634_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q240 = + coreFix_aluExe_0_rsAlu$RDY_enq; + 1'd1: + CASE_k70634_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q240 = + coreFix_aluExe_1_rsAlu$RDY_enq; + endcase + end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13524 or - regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13946 or - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3443_co_ETC___d13453 or + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13534 or + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__345_ETC___d13497 or + coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) + begin + case (fetchStage$pipelines_0_first[194:192]) + 3'd0, 3'd1: + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13962 = + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__345_ETC___d13497; + 3'd3, 3'd4: + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13962 = + !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq; + default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13962 = + fetchStage$pipelines_0_first[194:192] == 3'd2 && + (!coreFix_memExe_rsMem$canEnq || + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13534); + endcase + end + always@(fetchStage$pipelines_0_first or + coreFix_memExe_rsMem$canEnq or + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13534 or + regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13956 or + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463 or regRenamingTable$RDY_rename_0_getRename or - _0_OR_NOT_fetchStage_pipelines_0_first__2757_BI_ETC___d13933 or + _0_OR_NOT_fetchStage_pipelines_0_first__2757_BI_ETC___d13943 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq or coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_enq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13950 = - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3443_co_ETC___d13453 || + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13960 = + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463 || regRenamingTable$RDY_rename_0_getRename && - _0_OR_NOT_fetchStage_pipelines_0_first__2757_BI_ETC___d13933; + _0_OR_NOT_fetchStage_pipelines_0_first__2757_BI_ETC___d13943; 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13950 = + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13960 = !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq || coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_enq && regRenamingTable$RDY_rename_0_getRename; - default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13950 = + default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13960 = fetchStage$pipelines_0_first[194:192] != 3'd2 || !coreFix_memExe_rsMem$canEnq || - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13524 || - regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13946; + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13534 || + regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13956; endcase end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13524 or - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3443_co_ETC___d13453 or + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13534 or + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13966 = - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3443_co_ETC___d13453; + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13976 = + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463; 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13966 = + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13976 = !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq; - default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13966 = + default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13976 = fetchStage$pipelines_0_first[194:192] == 3'd2 && (!coreFix_memExe_rsMem$canEnq || - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13524); + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13534); endcase end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13466 or - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__344_ETC___d13487 or + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13476 or + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__345_ETC___d13497 or specTagManager$canClaim or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13973 = - !SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__344_ETC___d13487 && + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13983 = + !SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__345_ETC___d13497 && (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim); 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13973 = + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13983 = coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq; - default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13973 = + default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13983 = fetchStage$pipelines_0_first[194:192] != 3'd2 || coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13466; + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13476; endcase end - always@(idx__h686276 or + always@(idx__h686379 or fetchStage$pipelines_0_canDeq or - fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13996 or + fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d14006 or coreFix_aluExe_0_rsAlu$canEnq or - fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d14003 or + fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d14013 or coreFix_aluExe_1_rsAlu$canEnq) begin - case (idx__h686276) + case (idx__h686379) 1'd0: - SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__275_ETC___d14007 = + SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__275_ETC___d14017 = (!fetchStage$pipelines_0_canDeq || - fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13996) && + fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d14006) && coreFix_aluExe_0_rsAlu$canEnq; 1'd1: - SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__275_ETC___d14007 = + SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__275_ETC___d14017 = (!fetchStage$pipelines_0_canDeq || - fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d14003) && + fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d14013) && coreFix_aluExe_1_rsAlu$canEnq; endcase end - always@(fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14023 or + always@(fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14033 or coreFix_aluExe_0_rsAlu$RDY_enq or coreFix_aluExe_1_rsAlu$RDY_enq) begin - case (fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14023) + case (fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14033) 1'd0: CASE_fetchStage_pipelines_0_canDeq__2755_AND_N_ETC__q241 = coreFix_aluExe_0_rsAlu$RDY_enq; @@ -37993,78 +38002,78 @@ module mkCore(CLK, end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13524 or - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3443_co_ETC___d13453) + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13534 or + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d14049 = - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3443_co_ETC___d13453; - default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d14049 = + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d14059 = + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463; + default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d14059 = fetchStage$pipelines_0_first[194:192] == 3'd2 && (!coreFix_memExe_rsMem$canEnq || - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13524); + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13534); endcase end always@(fetchStage$pipelines_0_first or - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13524 or - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3443_co_ETC___d13453 or + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13534 or + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d14061 = - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3443_co_ETC___d13453; + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d14071 = + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463; 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d14061 = + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d14071 = !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq; - default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d14061 = + default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d14071 = fetchStage$pipelines_0_first[194:192] == 3'd2 && - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13524; + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13534; endcase end always@(fetchStage$pipelines_1_first or - fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14070 or - SEL_ARR_fetchStage_pipelines_0_canDeq__2755_AN_ETC___d13777 or - fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14058) + fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14080 or + SEL_ARR_fetchStage_pipelines_0_canDeq__2755_AN_ETC___d13787 or + fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14068) begin case (fetchStage$pipelines_1_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14073 = - SEL_ARR_fetchStage_pipelines_0_canDeq__2755_AN_ETC___d13777; + IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14083 = + SEL_ARR_fetchStage_pipelines_0_canDeq__2755_AN_ETC___d13787; 3'd3, 3'd4: - IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14073 = - fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14058; - default: IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14073 = + IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14083 = + fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14068; + default: IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14083 = fetchStage$pipelines_1_first[194:192] == 3'd2 && - fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14070; + fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14080; endcase end always@(fetchStage$pipelines_1_first or - fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14036 or + fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14046 or regRenamingTable$RDY_rename_1_getRename or - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14041 or - SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__275_ETC___d14007 or - regRenamingTable_RDY_rename_1_getRename__4009__ETC___d14027 or - fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14029 or + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14051 or + SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__275_ETC___d14017 or + regRenamingTable_RDY_rename_1_getRename__4019__ETC___d14037 or + fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14039 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq or - coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__39_ETC___d14032) + coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__39_ETC___d14042) begin case (fetchStage$pipelines_1_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14046 = - !SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__275_ETC___d14007 || - regRenamingTable_RDY_rename_1_getRename__4009__ETC___d14027; + IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14056 = + !SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__275_ETC___d14017 || + regRenamingTable_RDY_rename_1_getRename__4019__ETC___d14037; 3'd3, 3'd4: - IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14046 = - fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14029 || + IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14056 = + fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14039 || !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq || - coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__39_ETC___d14032; - default: IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14046 = + coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__39_ETC___d14042; + default: IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14056 = fetchStage$pipelines_1_first[194:192] != 3'd2 || - fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14036 || + fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14046 || regRenamingTable$RDY_rename_1_getRename && - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14041; + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14051; endcase end always@(fetchStage$pipelines_0_first or @@ -38072,9 +38081,9 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14130 = + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14140 = !coreFix_memExe_lsq$enqLdTag[5]; - default: IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14130 = + default: IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14140 = !coreFix_memExe_lsq$enqStTag[5]; endcase end @@ -38083,9 +38092,9 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14127 = + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14137 = coreFix_memExe_lsq$enqLdTag[5]; - default: IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14127 = + default: IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14137 = coreFix_memExe_lsq$enqStTag[5]; endcase end @@ -38094,9 +38103,9 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14136 = + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14146 = coreFix_memExe_lsq$enqLdTag[3:0]; - default: IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14136 = + default: IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14146 = coreFix_memExe_lsq$enqStTag[3:0]; endcase end @@ -38105,9 +38114,9 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14133 = + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14143 = coreFix_memExe_lsq$enqLdTag[4:0]; - default: IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14133 = + default: IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14143 = coreFix_memExe_lsq$enqStTag[4:0]; endcase end @@ -38116,9 +38125,9 @@ module mkCore(CLK, begin case (fetchStage$pipelines_1_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14267 = + IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14277 = coreFix_memExe_lsq$enqLdTag[3:0]; - default: IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14267 = + default: IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14277 = coreFix_memExe_lsq$enqStTag[3:0]; endcase end @@ -38127,9 +38136,9 @@ module mkCore(CLK, begin case (fetchStage$pipelines_1_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14265 = + IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14275 = !coreFix_memExe_lsq$enqLdTag[5]; - default: IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14265 = + default: IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14275 = !coreFix_memExe_lsq$enqStTag[5]; endcase end @@ -38138,9 +38147,9 @@ module mkCore(CLK, begin case (fetchStage$pipelines_1_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14264 = + IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14274 = coreFix_memExe_lsq$enqLdTag[5]; - default: IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14264 = + default: IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14274 = coreFix_memExe_lsq$enqStTag[5]; endcase end @@ -38149,9 +38158,9 @@ module mkCore(CLK, begin case (fetchStage$pipelines_1_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14266 = + IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14276 = coreFix_memExe_lsq$enqLdTag[4:0]; - default: IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14266 = + default: IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14276 = coreFix_memExe_lsq$enqStTag[4:0]; endcase end @@ -38185,112 +38194,112 @@ module mkCore(CLK, begin case (rob$deqPort_0_deq_data[180:169]) 12'd1: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd0; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd0; 12'd2: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd1; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd1; 12'd3: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd2; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd2; 12'd256: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd8; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd8; 12'd260: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd9; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd9; 12'd261: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd10; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd10; 12'd262: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd11; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd11; 12'd320: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd12; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd12; 12'd321: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd13; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd13; 12'd322: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd14; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd14; 12'd323: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd15; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd15; 12'd324: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd16; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd16; 12'd384: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd17; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd17; 12'd768: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd18; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd18; 12'd769: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd19; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd19; 12'd770: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd20; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd20; 12'd771: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd21; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd21; 12'd772: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd22; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd22; 12'd773: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd23; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd23; 12'd774: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd24; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd24; 12'd832: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd25; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd25; 12'd833: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd26; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd26; 12'd834: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd27; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd27; 12'd835: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd28; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd28; 12'd836: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd29; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd29; 12'd1952: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd36; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd36; 12'd1953: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd37; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd37; 12'd1954: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd38; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd38; 12'd1955: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd39; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd39; 12'd1968: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd40; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd40; 12'd1969: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd41; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd41; 12'd1970: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd42; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd42; 12'd1971: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd43; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd43; 12'd2048: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd6; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd6; 12'd2049: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd7; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd7; 12'd2816: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd30; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd30; 12'd2818: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd31; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd31; 12'd3072: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd3; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd3; 12'd3073: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd4; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd4; 12'd3074: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd5; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd5; 12'd3857: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd32; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd32; 12'd3858: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd33; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd33; 12'd3859: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd34; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd34; 12'd3860: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd35; - default: IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd35; + default: IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd44; endcase end - always@(IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 or + always@(IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 or rob$deqPort_0_deq_data or robdeqPort_0_deq_data_BITS_95_TO_32__q245) begin - case (IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988) + case (IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998) 6'd0: - data_warl_xformed__h723335 = + data_warl_xformed__h723438 = { 59'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[4:0] }; 6'd1, 6'd11, 6'd24: - data_warl_xformed__h723335 = + data_warl_xformed__h723438 = { 61'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[2:0] }; 6'd2: - data_warl_xformed__h723335 = + data_warl_xformed__h723438 = { 56'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[7:0] }; 6'd8: - data_warl_xformed__h723335 = + data_warl_xformed__h723438 = { robdeqPort_0_deq_data_BITS_95_TO_32__q245[14:13] == 2'b11, 43'd8192, robdeqPort_0_deq_data_BITS_95_TO_32__q245[19:18], @@ -38303,7 +38312,7 @@ module mkCore(CLK, 2'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[1:0] }; 6'd9, 6'd16: - data_warl_xformed__h723335 = + data_warl_xformed__h723438 = { 54'd0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[9], 3'd0, @@ -38312,22 +38321,22 @@ module mkCore(CLK, robdeqPort_0_deq_data_BITS_95_TO_32__q245[1], 1'd0 }; 6'd10, 6'd23: - data_warl_xformed__h723335 = + data_warl_xformed__h723438 = { robdeqPort_0_deq_data_BITS_95_TO_32__q245[63:2], 1'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[0] }; 6'd14, 6'd27: - data_warl_xformed__h723335 = + data_warl_xformed__h723438 = { robdeqPort_0_deq_data_BITS_95_TO_32__q245[63], 59'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[3:0] }; 6'd17: - data_warl_xformed__h723335 = + data_warl_xformed__h723438 = { robdeqPort_0_deq_data_BITS_95_TO_32__q245[63], 19'd0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[43:0] }; 6'd18: - data_warl_xformed__h723335 = + data_warl_xformed__h723438 = { robdeqPort_0_deq_data_BITS_95_TO_32__q245[14:13] == 2'b11, 40'd5120, robdeqPort_0_deq_data_BITS_95_TO_32__q245[22:17], @@ -38339,9 +38348,9 @@ module mkCore(CLK, robdeqPort_0_deq_data_BITS_95_TO_32__q245[5:3], 1'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[1:0] }; - 6'd19: data_warl_xformed__h723335 = 64'h800000000014112D; + 6'd19: data_warl_xformed__h723438 = 64'h800000000014112D; 6'd20: - data_warl_xformed__h723335 = + data_warl_xformed__h723438 = { 48'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[15], 1'b0, @@ -38349,7 +38358,7 @@ module mkCore(CLK, 1'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[9:0] }; 6'd21: - data_warl_xformed__h723335 = + data_warl_xformed__h723438 = { 52'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[11], 1'b0, @@ -38359,7 +38368,7 @@ module mkCore(CLK, 1'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[1:0] }; 6'd22, 6'd29: - data_warl_xformed__h723335 = + data_warl_xformed__h723438 = { 52'd0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[11], 1'd0, @@ -38373,12 +38382,12 @@ module mkCore(CLK, 1'd0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[1], 1'd0 }; - 6'd32, 6'd33, 6'd34, 6'd35: data_warl_xformed__h723335 = 64'd0; + 6'd32, 6'd33, 6'd34, 6'd35: data_warl_xformed__h723438 = 64'd0; 6'd37: - data_warl_xformed__h723335 = + data_warl_xformed__h723438 = { 4'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[59:0] }; 6'd40: - data_warl_xformed__h723335 = + data_warl_xformed__h723438 = { 32'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[31:28], 12'b0, @@ -38387,7 +38396,7 @@ module mkCore(CLK, robdeqPort_0_deq_data_BITS_95_TO_32__q245[13:6], 1'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[4:0] }; - default: data_warl_xformed__h723335 = rob$deqPort_0_deq_data[95:32]; + default: data_warl_xformed__h723438 = rob$deqPort_0_deq_data[95:32]; endcase end always@(rob$deqPort_0_deq_data) @@ -38444,13 +38453,13 @@ module mkCore(CLK, endcase end always@(rob$deqPort_0_deq_data or - IF_rob_deqPort_0_deq_data__4344_BITS_329_TO_32_ETC___d15196) + IF_rob_deqPort_0_deq_data__4354_BITS_329_TO_32_ETC___d15206) begin case (rob$deqPort_0_deq_data[329:325]) 5'd19, 5'd20: - x__h723943 = - IF_rob_deqPort_0_deq_data__4344_BITS_329_TO_32_ETC___d15196; - default: x__h723943 = rob$deqPort_0_deq_data[425:362]; + x__h724046 = + IF_rob_deqPort_0_deq_data__4354_BITS_329_TO_32_ETC___d15206; + default: x__h724046 = rob$deqPort_0_deq_data[425:362]; endcase end always@(rob$deqPort_0_deq_data) @@ -41158,7 +41167,7 @@ module mkCore(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == 6'd6) + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd6) $display("[Terminate CSR] being written (val = %x), ", "send terminate signal to host", rob$deqPort_0_deq_data[95:32]); @@ -41270,7 +41279,7 @@ module mkCore(CLK, rob$deqPort_1_deq_data[329:325] != 5'd19 && rob$deqPort_1_deq_data[329:325] != 5'd20) $write("instret:%0d PC:0x%0h instr:0x%08h", - commitStage_rg_serial_num_4333_PLUS_IF_rob_deq_ETC___d15459, + commitStage_rg_serial_num_4343_PLUS_IF_rob_deq_ETC___d15469, rob$deqPort_1_deq_data[425:362], rob$deqPort_1_deq_data[361:330], " iType:"); diff --git a/src_SSITH_P3/Verilog_RTL/mkCoreW.v b/src_SSITH_P3/Verilog_RTL/mkCoreW.v index bb0d3be..ea0a6ee 100644 --- a/src_SSITH_P3/Verilog_RTL/mkCoreW.v +++ b/src_SSITH_P3/Verilog_RTL/mkCoreW.v @@ -2716,22 +2716,22 @@ module mkCoreW(RST_N_dm_power_on_reset, // rule RL_rl_dm_hart0_reset_wait assign CAN_FIRE_RL_rl_dm_hart0_reset_wait = (rg_hart0_reset_delay != 8'd1 || - proc$RDY_start && - debug_module$RDY_hart0_reset_client_response_put) && + debug_module$RDY_hart0_reset_client_response_put && + proc$RDY_start) && rg_hart0_reset_delay != 8'd0 ; assign WILL_FIRE_RL_rl_dm_hart0_reset_wait = CAN_FIRE_RL_rl_dm_hart0_reset_wait && !EN_start ; // rule RL_ClientServerRequest assign CAN_FIRE_RL_ClientServerRequest = - proc$RDY_hart0_run_halt_server_request_put && - debug_module$RDY_hart0_client_run_halt_request_get ; + debug_module$RDY_hart0_client_run_halt_request_get && + proc$RDY_hart0_run_halt_server_request_put ; assign WILL_FIRE_RL_ClientServerRequest = CAN_FIRE_RL_ClientServerRequest ; // rule RL_ClientServerResponse assign CAN_FIRE_RL_ClientServerResponse = - proc$RDY_hart0_run_halt_server_response_get && - debug_module$RDY_hart0_client_run_halt_response_put ; + debug_module$RDY_hart0_client_run_halt_response_put && + proc$RDY_hart0_run_halt_server_response_get ; assign WILL_FIRE_RL_ClientServerResponse = CAN_FIRE_RL_ClientServerResponse ; @@ -2743,25 +2743,25 @@ module mkCoreW(RST_N_dm_power_on_reset, // rule RL_mkConnectionGetPut_1 assign CAN_FIRE_RL_mkConnectionGetPut_1 = - proc$RDY_v_to_TV_0_get && v_td2_to_td_0$RDY_in_put ; + v_td2_to_td_0$RDY_in_put && proc$RDY_v_to_TV_0_get ; assign WILL_FIRE_RL_mkConnectionGetPut_1 = CAN_FIRE_RL_mkConnectionGetPut_1 ; // rule RL_mkConnectionGetPut_2 assign CAN_FIRE_RL_mkConnectionGetPut_2 = - tv_encode$RDY_v_cpu_in_0_put && v_td2_to_td_0$RDY_out_get ; + v_td2_to_td_0$RDY_out_get && tv_encode$RDY_v_cpu_in_0_put ; assign WILL_FIRE_RL_mkConnectionGetPut_2 = CAN_FIRE_RL_mkConnectionGetPut_2 ; // rule RL_mkConnectionGetPut_3 assign CAN_FIRE_RL_mkConnectionGetPut_3 = - proc$RDY_v_to_TV_1_get && v_td2_to_td_1$RDY_in_put ; + v_td2_to_td_1$RDY_in_put && proc$RDY_v_to_TV_1_get ; assign WILL_FIRE_RL_mkConnectionGetPut_3 = CAN_FIRE_RL_mkConnectionGetPut_3 ; // rule RL_mkConnectionGetPut_4 assign CAN_FIRE_RL_mkConnectionGetPut_4 = - tv_encode$RDY_v_cpu_in_1_put && v_td2_to_td_1$RDY_out_get ; + v_td2_to_td_1$RDY_out_get && tv_encode$RDY_v_cpu_in_1_put ; assign WILL_FIRE_RL_mkConnectionGetPut_4 = CAN_FIRE_RL_mkConnectionGetPut_4 ; diff --git a/src_SSITH_P3/Verilog_RTL/mkP3_Core.v b/src_SSITH_P3/Verilog_RTL/mkP3_Core.v index b1f7022..1b6b7c2 100644 --- a/src_SSITH_P3/Verilog_RTL/mkP3_Core.v +++ b/src_SSITH_P3/Verilog_RTL/mkP3_Core.v @@ -1434,7 +1434,7 @@ module mkP3_Core(CLK, // rule RL_rl_ndm_reset_wait assign CAN_FIRE_RL_rl_ndm_reset_wait = (rg_ndm_reset_delay != 8'd1 || - corew$RDY_start && corew$RDY_ndm_reset_client_response_put) && + corew$RDY_ndm_reset_client_response_put && corew$RDY_start) && rg_ndm_reset_delay != 8'd0 ; assign WILL_FIRE_RL_rl_ndm_reset_wait = CAN_FIRE_RL_rl_ndm_reset_wait ; diff --git a/src_SSITH_P3/Verilog_RTL/mkProc.v b/src_SSITH_P3/Verilog_RTL/mkProc.v index 8e3867b..5a65043 100644 --- a/src_SSITH_P3/Verilog_RTL/mkProc.v +++ b/src_SSITH_P3/Verilog_RTL/mkProc.v @@ -2104,8 +2104,8 @@ module mkProc(CLK, // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h162860; - reg [31 : 0] v__h162396; + reg [31 : 0] v__h162844; + reg [31 : 0] v__h162380; reg [31 : 0] v__h5520; reg [31 : 0] v__h5693; reg [31 : 0] v__h5953; @@ -2116,13 +2116,13 @@ module mkProc(CLK, reg [31 : 0] v__h9480; reg [31 : 0] v__h9973; reg [31 : 0] v__h10136; - reg [31 : 0] v__h134353; - reg [31 : 0] v__h134520; - reg [31 : 0] v__h136623; - reg [31 : 0] v__h153967; - reg [31 : 0] v__h133734; - reg [31 : 0] v__h160661; - reg [31 : 0] v__h161169; + reg [31 : 0] v__h134337; + reg [31 : 0] v__h134504; + reg [31 : 0] v__h136607; + reg [31 : 0] v__h153951; + reg [31 : 0] v__h133718; + reg [31 : 0] v__h160645; + reg [31 : 0] v__h161153; reg [31 : 0] v__h2664; reg [31 : 0] v__h4337; reg [31 : 0] v__h5514; @@ -2133,282 +2133,280 @@ module mkProc(CLK, reg [31 : 0] v__h9474; reg [31 : 0] v__h9967; reg [31 : 0] v__h10130; - reg [31 : 0] v__h133728; - reg [31 : 0] v__h134347; - reg [31 : 0] v__h134514; - reg [31 : 0] v__h136617; - reg [31 : 0] v__h153961; - reg [31 : 0] v__h160655; - reg [31 : 0] v__h161163; - reg [31 : 0] v__h162390; - reg [31 : 0] v__h162854; + reg [31 : 0] v__h133712; + reg [31 : 0] v__h134331; + reg [31 : 0] v__h134498; + reg [31 : 0] v__h136601; + reg [31 : 0] v__h153945; + reg [31 : 0] v__h160639; + reg [31 : 0] v__h161147; + reg [31 : 0] v__h162374; + reg [31 : 0] v__h162838; // synopsys translate_on // remaining internal signals reg [63 : 0] CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13, CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14, CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17, - CASE_x1277_0_n__read_addr1459_1_n__read_addr15_ETC__q23, - CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24, - CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25, - CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26, - CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27, - CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28, - CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29, - CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30, - CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31, - CASE_x9900_0_n__read_addr0078_1_n__read_addr01_ETC__q34, - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d805, - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d818, - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d857, - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d869, - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d939, - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d948, - IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915, - IF_mmioPlatform_reqSz_75_EQ_0b10_82_THEN_SEXT__ETC___d883, - IF_mmioPlatform_reqSz_75_EQ_0b10_82_THEN_SEXT__ETC___d885, - data64__h147793, - dword__h93798, - ld_data__h131955, - old_dword__h89488, - w1__h47877, - w1__h47882, - w2__h47878, - w2__h47884, - x__h47873; - reg [31 : 0] SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d983; + CASE_x1261_0_n__read_addr1443_1_n__read_addr15_ETC__q23, + CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24, + CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25, + CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26, + CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27, + CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28, + CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29, + CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30, + CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31, + CASE_x9884_0_n__read_addr0062_1_n__read_addr01_ETC__q34, + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801, + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814, + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853, + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865, + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935, + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d944, + IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911, + IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d879, + IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d881, + data64__h147777, + dword__h93782, + ld_data__h131939, + old_dword__h89472, + w1__h47861, + w1__h47866, + w2__h47862, + w2__h47868, + x__h47857; + reg [31 : 0] SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d979; reg [11 : 0] CASE_core_0v_to_TV_0_get_BITS_475_TO_464_1_co_ETC__q5, CASE_core_0v_to_TV_1_get_BITS_475_TO_464_1_co_ETC__q1; - reg [7 : 0] strb8__h147794; - reg [5 : 0] IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_ETC___d481; + reg [7 : 0] strb8__h147778; + reg [5 : 0] IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d477; reg [3 : 0] CASE_core_0v_to_TV_0_get_BITS_461_TO_458_0_co_ETC__q6, CASE_core_0v_to_TV_0_get_BITS_461_TO_458_0_co_ETC__q7, CASE_core_0v_to_TV_1_get_BITS_461_TO_458_0_co_ETC__q2, CASE_core_0v_to_TV_1_get_BITS_461_TO_458_0_co_ETC__q3; - reg [2 : 0] x__h61591; + reg [2 : 0] x__h61575; reg [1 : 0] CASE_core_0v_to_TV_0_get_BITS_393_TO_392_0_co_ETC__q8, CASE_core_0v_to_TV_1_get_BITS_393_TO_392_0_co_ETC__q4, - CASE_x1277_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21, - CASE_x1277_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22, - CASE_x9900_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32; + CASE_x1261_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21, + CASE_x1261_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22, + CASE_x9884_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32; reg CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q18, CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q19, - CASE_x1277_0_propDstData_0_dummy2_1_read__096__ETC__q20, - CASE_x9900_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33, - SEL_ARR_propDstIdx_0_dummy2_1_read__058_AND_IF_ETC___d1089, - SEL_ARR_propDstIdx_1_0_dummy2_1_read__317_AND__ETC___d1358, - x__h61598, - x__h82316; - wire [579 : 0] IF_enqDst_1_0_lat_1_whas__262_THEN_enqDst_1_0__ETC___d1309; - wire [515 : 0] SEL_ARR_IF_propDstData_1_0_dummy2_1_read__365__ETC___d1457; - wire [513 : 0] IF_enqDst_1_0_lat_1_whas__262_THEN_enqDst_1_0__ETC___d1308; - wire [511 : 0] IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1300, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__189_THE_ETC___d1450, - new_cline__h134656; - wire [383 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1582, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__189_THE_ETC___d1433; - wire [255 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1577, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__189_THE_ETC___d1416; - wire [127 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__189_THE_ETC___d1399; - wire [66 : 0] IF_core_0_mmioToPlatform_cRq_first__82_BITS_14_ETC___d405; - wire [65 : 0] DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_40_BIT_ETC___d684; - wire [64 : 0] IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_2_ETC___d723; - wire [63 : 0] IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1280, - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d825, - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d876, - IF_mmioPlatform_reqBE_43_BIT_4_44_THEN_SEXT_mm_ETC___d577, - IF_mmioPlatform_reqBE_43_BIT_4_44_THEN_SEXT_mm_ETC___d641, - IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d552, - IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d614, - IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d715, - IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_1_ETC___d578, - IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_1_ETC___d642, - IF_propDstData_1_0_lat_0_whas__189_THEN_propDs_ETC___d1194, - IF_propDstData_1_1_lat_0_whas__227_THEN_propDs_ETC___d1232, - data__h31966, - failed_testnum__h162439, - line_addr__h101862, - line_addr__h101948, - mask__h89485, - mem_req_rd_addr_araddr__h133954, - mem_req_wr_addr_awaddr__h147878, - mmioPlatform_fromHostQ_data_0__h42667, - mmioPlatform_mtime__h37280, - mmioPlatform_reqData__h48469, - n__read_addr__h61459, - n__read_addr__h61544, - n__read_addr__h80078, - n__read_addr__h80157, - n__read_snd_addr__h123389, - newData__h32047, - newData__h34977, - new_dword__h89489, - op_result__h48485, - op_result__h49015, + CASE_x1261_0_propDstData_0_dummy2_1_read__092__ETC__q20, + CASE_x9884_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33, + SEL_ARR_propDstIdx_0_dummy2_1_read__054_AND_IF_ETC___d1085, + SEL_ARR_propDstIdx_1_0_dummy2_1_read__313_AND__ETC___d1354, + x__h61582, + x__h82300; + wire [579 : 0] IF_enqDst_1_0_lat_1_whas__258_THEN_enqDst_1_0__ETC___d1305; + wire [515 : 0] SEL_ARR_IF_propDstData_1_0_dummy2_1_read__361__ETC___d1453; + wire [513 : 0] IF_enqDst_1_0_lat_1_whas__258_THEN_enqDst_1_0__ETC___d1304; + wire [511 : 0] IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1296, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1446, + new_cline__h134640; + wire [383 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1578, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1429; + wire [255 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1573, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1412; + wire [127 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1395; + wire [66 : 0] IF_core_0_mmioToPlatform_cRq_first__78_BITS_14_ETC___d401; + wire [65 : 0] DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_36_BIT_ETC___d680; + wire [64 : 0] IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_2_ETC___d719; + wire [63 : 0] IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1276, + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d821, + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d872, + IF_mmioPlatform_reqBE_39_BIT_4_40_THEN_SEXT_mm_ETC___d573, + IF_mmioPlatform_reqBE_39_BIT_4_40_THEN_SEXT_mm_ETC___d637, + IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d548, + IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d610, + IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d711, + IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_1_ETC___d574, + IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_1_ETC___d638, + IF_propDstData_1_0_lat_0_whas__185_THEN_propDs_ETC___d1190, + IF_propDstData_1_1_lat_0_whas__223_THEN_propDs_ETC___d1228, + data__h31950, + failed_testnum__h162423, + line_addr__h101846, + line_addr__h101932, + mask__h89469, + mem_req_rd_addr_araddr__h133938, + mem_req_wr_addr_awaddr__h147862, + mmioPlatform_fromHostQ_data_0__h42651, + mmioPlatform_mtime__h37264, + mmioPlatform_reqData__h48453, + n__read_addr__h61443, + n__read_addr__h61528, + n__read_addr__h80062, + n__read_addr__h80141, + n__read_snd_addr__h123373, + newData__h32031, + newData__h34961, + new_dword__h89473, + op_result__h48469, + op_result__h48999, + op_result__h49004, + op_result__h49009, + op_result__h49014, op_result__h49020, - op_result__h49025, - op_result__h49030, - op_result__h49036, - op_result__h49043, - op_result__h49049, - result__h47928, - result__h48052, - result__h48080, - result__h48108, - result__h48136, - result__h48164, - result__h48192, - result__h48220, - result__h48248, - result__h48293, - result__h48321, - result__h48349, - result__h48377, - result__h48418, - result__h48446, - result__h48572, - result__h48599, - result__h48626, - result__h48653, - result__h48680, - result__h48707, - result__h48734, - result__h48761, - result__h48805, - result__h48832, - result__h48859, - result__h48886, - result__h48926, - result__h48953, - result__h49070, - result__h49136, - result__h49202, - result__h49268, - result__h49334, - result__h49400, - result__h49466, - result__h49528, - result__h49573, - result__h49639, - result__h49705, - result__h49763, - result__h49808, - w1___1__h47987, - w2___1__h47988, - x1_avValue_data__h40339, - x1_avValue_data__h44806, - x__h32158, - x__h35068, - x__h37428, - x__h40857, - x__h40868, - x__h42877, - x__h42888, - x__h49985, - x__h90651, - y__h90652, - y__h90653; - wire [47 : 0] IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d544, - IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d609, - IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d710; - wire [31 : 0] IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d535, - IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d604, - IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d705, - IF_mmio_axi4_adapter_f_rsps_to_core_first__56__ETC___d991, + op_result__h49027, + op_result__h49033, + result__h47912, + result__h48036, + result__h48064, + result__h48092, + result__h48120, + result__h48148, + result__h48176, + result__h48204, + result__h48232, + result__h48277, + result__h48305, + result__h48333, + result__h48361, + result__h48402, + result__h48430, + result__h48556, + result__h48583, + result__h48610, + result__h48637, + result__h48664, + result__h48691, + result__h48718, + result__h48745, + result__h48789, + result__h48816, + result__h48843, + result__h48870, + result__h48910, + result__h48937, + result__h49054, + result__h49120, + result__h49186, + result__h49252, + result__h49318, + result__h49384, + result__h49450, + result__h49512, + result__h49557, + result__h49623, + result__h49689, + result__h49747, + result__h49792, + w1___1__h47971, + w2___1__h47972, + x1_avValue_data__h40323, + x1_avValue_data__h44790, + x__h32142, + x__h35052, + x__h37412, + x__h40841, + x__h40852, + x__h42861, + x__h42872, + x__h49969, + x__h90635, + y__h90636, + y__h90637; + wire [47 : 0] IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d540, + IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d605, + IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d706; + wire [31 : 0] IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d531, + IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d600, + IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d701, + IF_mmio_axi4_adapter_f_rsps_to_core_first__52__ETC___d987, mmioPlatform_mtime_BITS_31_TO_0__q12, mmioPlatform_mtime_BITS_63_TO_32__q11, mmioPlatform_mtimecmp_0_BITS_31_TO_0__q10, mmioPlatform_mtimecmp_0_BITS_63_TO_32__q9, - v__h31759, - v__h31796, - w17877_BITS_31_TO_0__q15, - w27878_BITS_31_TO_0__q16, - x_data__h30549; - wire [8 : 0] SEL_ARR_IF_propDstData_0_dummy2_1_read__096_TH_ETC___d1160; - wire [5 : 0] x__h133989, x__h147903; - wire [4 : 0] SEL_ARR_propDstData_0_dummy2_1_read__096_AND_I_ETC___d1159; - wire [3 : 0] b__h133661, b__h2564; - wire [2 : 0] n__read_id__h61463, n__read_id__h61548, x__h7925; - wire [1 : 0] IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1285, - IF_propDstData_0_dummy2_1_read__096_THEN_IF_pr_ETC___d1112, - IF_propDstData_0_dummy2_1_read__096_THEN_IF_pr_ETC___d1122, - IF_propDstData_1_0_lat_0_whas__189_THEN_propDs_ETC___d1199, - IF_propDstData_1_1_lat_0_whas__227_THEN_propDs_ETC___d1237, - IF_propDstData_1_dummy2_1_read__101_THEN_IF_pr_ETC___d1116, - IF_propDstData_1_dummy2_1_read__101_THEN_IF_pr_ETC___d1126; - wire IF_IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4__ETC___d559, - IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d456, - IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554, - IF_NOT_propDstIdx_0_dummy2_1_read__058_059_OR__ETC___d1093, - IF_NOT_propDstIdx_1_0_dummy2_1_read__317_318_O_ETC___d1362, - IF_SEL_ARR_propDstIdx_0_dummy2_1_read__058_AND_ETC___d1165, - IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__317_A_ETC___d1462, - IF_enqDst_0_lat_0_whas__034_THEN_enqDst_0_lat__ETC___d1039, - IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1270, - IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1290, - IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1306, - IF_llc_mem_server_enqDst_0_lat_0_whas__662_THE_ETC___d1667, - IF_llc_mem_server_propDstIdx_0_lat_0_whas__647_ETC___d1650, - IF_mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioP_ETC___d625, - IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_ETC___d457, + v__h31743, + v__h31780, + w17861_BITS_31_TO_0__q15, + w27862_BITS_31_TO_0__q16, + x_data__h30533; + wire [8 : 0] SEL_ARR_IF_propDstData_0_dummy2_1_read__092_TH_ETC___d1156; + wire [5 : 0] x__h133973, x__h147887; + wire [4 : 0] SEL_ARR_propDstData_0_dummy2_1_read__092_AND_I_ETC___d1155; + wire [3 : 0] b__h133645, b__h2564; + wire [2 : 0] n__read_id__h61447, n__read_id__h61532, x__h7925; + wire [1 : 0] IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1281, + IF_propDstData_0_dummy2_1_read__092_THEN_IF_pr_ETC___d1108, + IF_propDstData_0_dummy2_1_read__092_THEN_IF_pr_ETC___d1118, + IF_propDstData_1_0_lat_0_whas__185_THEN_propDs_ETC___d1195, + IF_propDstData_1_1_lat_0_whas__223_THEN_propDs_ETC___d1233, + IF_propDstData_1_dummy2_1_read__097_THEN_IF_pr_ETC___d1112, + IF_propDstData_1_dummy2_1_read__097_THEN_IF_pr_ETC___d1122; + wire IF_IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4__ETC___d555, + IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d452, + IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550, + IF_NOT_propDstIdx_0_dummy2_1_read__054_055_OR__ETC___d1089, + IF_NOT_propDstIdx_1_0_dummy2_1_read__313_314_O_ETC___d1358, + IF_SEL_ARR_propDstIdx_0_dummy2_1_read__054_AND_ETC___d1161, + IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__313_A_ETC___d1458, + IF_enqDst_0_lat_0_whas__030_THEN_enqDst_0_lat__ETC___d1035, + IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1266, + IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1286, + IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1302, + IF_llc_mem_server_enqDst_0_lat_0_whas__658_THE_ETC___d1663, + IF_llc_mem_server_propDstIdx_0_lat_0_whas__643_ETC___d1646, + IF_mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioP_ETC___d621, + IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d453, IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__91__ETC___d200, - IF_mmioPlatform_waitLowerMSIPCRs_92_THEN_core__ETC___d500, - IF_mmio_axi4_adapter_f_rsps_to_core_first__56__ETC___d970, + IF_mmioPlatform_waitLowerMSIPCRs_88_THEN_core__ETC___d496, + IF_mmio_axi4_adapter_f_rsps_to_core_first__52__ETC___d966, IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d103, - IF_propDstData_1_0_lat_0_whas__189_THEN_propDs_ETC___d1220, - IF_propDstData_1_1_lat_0_whas__227_THEN_propDs_ETC___d1258, - IF_propDstIdx_0_lat_0_whas__005_THEN_propDstId_ETC___d1008, - IF_propDstIdx_1_0_lat_0_whas__174_THEN_propDst_ETC___d1177, - IF_propDstIdx_1_1_lat_0_whas__181_THEN_propDst_ETC___d1184, - IF_propDstIdx_1_lat_0_whas__012_THEN_propDstId_ETC___d1015, - NOT_enqDst_0_dummy2_0_read__079_080_OR_NOT_enq_ETC___d1095, - NOT_enqDst_1_0_dummy2_0_read__348_349_OR_NOT_e_ETC___d1364, - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780, - NOT_llc_mem_server_enqDst_0_dummy2_0_read__693_ETC___d1700, - NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d746, - NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d754, - NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d759, - NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d769, - NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d960, - NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d973, + IF_propDstData_1_0_lat_0_whas__185_THEN_propDs_ETC___d1216, + IF_propDstData_1_1_lat_0_whas__223_THEN_propDs_ETC___d1254, + IF_propDstIdx_0_lat_0_whas__001_THEN_propDstId_ETC___d1004, + IF_propDstIdx_1_0_lat_0_whas__170_THEN_propDst_ETC___d1173, + IF_propDstIdx_1_1_lat_0_whas__177_THEN_propDst_ETC___d1180, + IF_propDstIdx_1_lat_0_whas__008_THEN_propDstId_ETC___d1011, + NOT_enqDst_0_dummy2_0_read__075_076_OR_NOT_enq_ETC___d1091, + NOT_enqDst_1_0_dummy2_0_read__344_345_OR_NOT_e_ETC___d1360, + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776, + NOT_llc_mem_server_enqDst_0_dummy2_0_read__689_ETC___d1696, + NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d742, + NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d750, + NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d755, + NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d765, + NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d956, + NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d969, NOT_mmioPlatform_fromHostQ_clearReq_dummy2_1_r_ETC___d318, NOT_mmioPlatform_fromHostQ_enqReq_dummy2_2_rea_ETC___d339, - NOT_mmioPlatform_mtip_0_55_64_AND_mmioPlatform_ETC___d374, - NOT_mmioPlatform_mtip_0_55_64_AND_mmioPlatform_ETC___d379, - NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d490, - NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d585, - NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d648, + NOT_mmioPlatform_mtip_0_55_62_AND_mmioPlatform_ETC___d370, + NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d486, + NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d581, + NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d644, NOT_mmioPlatform_toHostQ_clearReq_dummy2_1_rea_ETC___d240, NOT_mmioPlatform_toHostQ_enqReq_dummy2_2_read__ETC___d261, - NOT_propDstData_1_0_dummy2_1_read__365_376_OR__ETC___d1377, - NOT_propDstData_1_1_dummy2_1_read__367_378_OR__ETC___d1379, - NOT_propDstIdx_0_dummy2_1_read__058_059_OR_IF__ETC___d1092, - NOT_propDstIdx_1_0_dummy2_1_read__317_318_OR_I_ETC___d1361, - llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1594, - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1516, + NOT_propDstData_1_0_dummy2_1_read__361_372_OR__ETC___d1373, + NOT_propDstData_1_1_dummy2_1_read__363_374_OR__ETC___d1375, + NOT_propDstIdx_0_dummy2_1_read__054_055_OR_IF__ETC___d1088, + NOT_propDstIdx_1_0_dummy2_1_read__313_314_OR_I_ETC___d1357, + llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1590, + llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1512, mmioPlatform_cycle_47_ULT_99___d348, - mmioPlatform_fetchingWay_65_ULT_mmioPlatform_r_ETC___d975, + mmioPlatform_fetchingWay_61_ULT_mmioPlatform_r_ETC___d971, mmioPlatform_fromHostQ_enqReq_dummy2_2_read__1_ETC___d331, - mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616, + mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612, mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357, - mmioPlatform_mtip_0_55_OR_NOT_mmioPlatform_mti_ETC___d410, - mmioPlatform_reqBE_BIT_0___h30174, - mmioPlatform_reqBE_BIT_4___h30134, - mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d467, - mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d571, - mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d636, + mmioPlatform_reqBE_BIT_0___h30158, + mmioPlatform_reqBE_BIT_4___h30118, + mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d463, + mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d567, + mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d632, mmioPlatform_toHostQ_enqReq_dummy2_2_read__41__ETC___d253, mmio_axi4_adapter_f_reqs_from_core_i_notEmpty__ETC___d9, - n__read_child__h61464, - n__read_child__h61549, - n__read_child__h80081, - n__read_child__h80160, - n__read_snd_id__h123390, - propDstData_0_dummy2_1_read__096_AND_IF_propDs_ETC___d1132, - propDstData_1_dummy2_1_read__101_AND_IF_propDs_ETC___d1136, - x__h61277, - x__h74829, - x__h79900; + n__read_child__h61448, + n__read_child__h61533, + n__read_child__h80065, + n__read_child__h80144, + n__read_snd_id__h123374, + propDstData_0_dummy2_1_read__092_AND_IF_propDs_ETC___d1128, + propDstData_1_dummy2_1_read__097_AND_IF_propDs_ETC___d1132, + x__h61261, + x__h74813, + x__h79884; // action method start assign RDY_start = mmioPlatform_state == 2'd0 ; @@ -3536,7 +3534,7 @@ module mkProc(CLK, // rule RL_doEnq assign CAN_FIRE_RL_doEnq = llc$RDY_to_child_rqFromC_enq && enqDst_0_dummy2_1$Q_OUT && - IF_enqDst_0_lat_0_whas__034_THEN_enqDst_0_lat__ETC___d1039 ; + IF_enqDst_0_lat_0_whas__030_THEN_enqDst_0_lat__ETC___d1035 ; assign WILL_FIRE_RL_doEnq = CAN_FIRE_RL_doEnq ; // rule RL_srcPropose_2 @@ -3564,7 +3562,7 @@ module mkProc(CLK, // rule RL_doEnq_1 assign CAN_FIRE_RL_doEnq_1 = llc$RDY_to_child_rsFromC_enq && enqDst_1_0_dummy2_1$Q_OUT && - IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1270 ; + IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1266 ; assign WILL_FIRE_RL_doEnq_1 = CAN_FIRE_RL_doEnq_1 ; // rule RL_sendPRq @@ -3725,9 +3723,8 @@ module mkProc(CLK, assign CAN_FIRE_RL_mmioPlatform_selectReq = (mmioPlatform_mtip_0 || !mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 || - mmioPlatform_mtimecmp_0 == 64'd0 || core_0$RDY_mmioToPlatform_pRq_enq) && - NOT_mmioPlatform_mtip_0_55_64_AND_mmioPlatform_ETC___d374 && + NOT_mmioPlatform_mtip_0_55_62_AND_mmioPlatform_ETC___d370 && mmioPlatform_state == 2'd1 ; assign WILL_FIRE_RL_mmioPlatform_selectReq = CAN_FIRE_RL_mmioPlatform_selectReq && @@ -3744,7 +3741,7 @@ module mkProc(CLK, // rule RL_mmioPlatform_processMSIP assign CAN_FIRE_RL_mmioPlatform_processMSIP = - IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_ETC___d457 && + IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d453 && mmioPlatform_curReq[66:64] == 3'd2 && mmioPlatform_state == 2'd2 ; assign WILL_FIRE_RL_mmioPlatform_processMSIP = @@ -3753,7 +3750,7 @@ module mkProc(CLK, // rule RL_mmioPlatform_waitMSIPDone assign CAN_FIRE_RL_mmioPlatform_waitMSIPDone = core_0$RDY_mmioToPlatform_pRs_enq && - IF_mmioPlatform_waitLowerMSIPCRs_92_THEN_core__ETC___d500 && + IF_mmioPlatform_waitLowerMSIPCRs_88_THEN_core__ETC___d496 && mmioPlatform_curReq[66:64] == 3'd2 && mmioPlatform_state == 2'd3 ; assign WILL_FIRE_RL_mmioPlatform_waitMSIPDone = @@ -3799,7 +3796,7 @@ module mkProc(CLK, core_0$RDY_mmioToPlatform_pRs_enq && (mmioPlatform_reqFunc[5:4] != 2'd2 || !mmioPlatform_toHostQ_empty || - x__h42877 == 64'd0 || + x__h42861 == 64'd0 || !mmioPlatform_toHostQ_full) && mmioPlatform_state == 2'd2 && mmioPlatform_curReq[66:64] == 3'd5 ; @@ -3817,7 +3814,7 @@ module mkProc(CLK, // rule RL_mmioPlatform_rl_mmio_to_fabric_req assign CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req = mmio_axi4_adapter_f_reqs_from_core$FULL_N && - NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d746 ; + NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d742 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req = CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req ; @@ -3825,14 +3822,14 @@ module mkProc(CLK, assign CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp = core_0$RDY_mmioToPlatform_pRs_enq && mmio_axi4_adapter_f_rsps_to_core$EMPTY_N && - NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d754 ; + NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d750 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp = CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp ; // rule RL_mmioPlatform_rl_mmio_to_fabric_amo_req assign CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req = mmio_axi4_adapter_f_reqs_from_core$FULL_N && - NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d759 ; + NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d755 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req = CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req ; @@ -3842,22 +3839,22 @@ module mkProc(CLK, mmio_axi4_adapter_f_rsps_to_core$EMPTY_N && (!mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] || mmio_axi4_adapter_f_reqs_from_core$FULL_N) && - NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d769 ; + NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d765 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp = CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp ; // rule RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req assign CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req = mmio_axi4_adapter_f_reqs_from_core$FULL_N && - NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d960 ; + NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d956 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req = CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req ; // rule RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp assign CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp = mmio_axi4_adapter_f_rsps_to_core$EMPTY_N && - IF_mmio_axi4_adapter_f_rsps_to_core_first__56__ETC___d970 && - NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d973 ; + IF_mmio_axi4_adapter_f_rsps_to_core_first__52__ETC___d966 && + NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d969 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp = CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp ; @@ -3939,7 +3936,7 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_f_rd_data$FULL_N && (llc_mem_server_rg_cacheline_cache_state == 3'd3 || llc_mem_server_rg_cacheline_cache_state == 3'd4) && - llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1594 ; + llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1590 ; assign WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req = CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req ; @@ -3957,7 +3954,7 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_f_wr_resp$FULL_N && (llc_mem_server_rg_cacheline_cache_state == 3'd3 || llc_mem_server_rg_cacheline_cache_state == 3'd4) && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1516 ; + llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1512 ; assign WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req = CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ; @@ -3975,7 +3972,7 @@ module mkProc(CLK, llc$RDY_dma_memReq_enq && llc_mem_server_axi4_slave_xactor_f_wr_addr$EMPTY_N && llc_mem_server_rg_cacheline_cache_state == 3'd4 && - !llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1516 ; + !llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1512 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss && !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged ; @@ -3985,7 +3982,7 @@ module mkProc(CLK, llc$RDY_dma_memReq_enq && llc_mem_server_axi4_slave_xactor_f_rd_addr$EMPTY_N && llc_mem_server_rg_cacheline_cache_state == 3'd4 && - !llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1594 ; + !llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1590 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss && !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss && @@ -4005,7 +4002,7 @@ module mkProc(CLK, llc$RDY_dma_memReq_enq && llc_mem_server_axi4_slave_xactor_f_wr_addr$EMPTY_N && llc_mem_server_rg_cacheline_cache_state == 3'd3 && - !llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1516 ; + !llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1512 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ; @@ -4014,7 +4011,7 @@ module mkProc(CLK, llc$RDY_dma_memReq_enq && llc_mem_server_axi4_slave_xactor_f_rd_addr$EMPTY_N && llc_mem_server_rg_cacheline_cache_state == 3'd3 && - !llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1594 ; + !llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1590 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld && !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st && @@ -4046,7 +4043,7 @@ module mkProc(CLK, assign CAN_FIRE_RL_llc_mem_server_doEnq = llc_mem_server_tlbQ$FULL_N && llc_mem_server_enqDst_0_dummy2_1$Q_OUT && - IF_llc_mem_server_enqDst_0_lat_0_whas__662_THE_ETC___d1667 ; + IF_llc_mem_server_enqDst_0_lat_0_whas__658_THE_ETC___d1663 ; assign WILL_FIRE_RL_llc_mem_server_doEnq = CAN_FIRE_RL_llc_mem_server_doEnq ; @@ -4119,13 +4116,13 @@ module mkProc(CLK, (llc_axi4_adapter_rg_rd_req_beat != 3'd7 || llc$RDY_to_mem_toM_deq) && !llc$to_mem_toM_first[640] && - b__h133661 == 4'd0 ; + b__h133645 == 4'd0 ; assign WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ; // rule RL_llc_axi4_adapter_rl_discard_write_rsp assign CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp = - b__h133661 != 4'd0 && + b__h133645 != 4'd0 && llc_axi4_adapter_master_xactor_crg_wr_resp_full && (llc_axi4_adapter_rg_wr_rsp_beat != 3'd7 || llc_axi4_adapter_f_pending_writes$EMPTY_N) ; @@ -4135,8 +4132,7 @@ module mkProc(CLK, // inputs to muxes for submodule ports assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 && - mmioPlatform_mtimecmp_0 != 64'd0 ; + mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_2 = WILL_FIRE_RL_mmioPlatform_processMSIP && mmioPlatform_reqFunc[5:4] != 2'd0 && @@ -4144,22 +4140,22 @@ module mkProc(CLK, mmioPlatform_reqBE[0] ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_3 = WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d585 ; + NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d581 ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_4 = WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d648 ; + NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d644 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_processMSIP && - mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d467 ; + mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d463 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_2 = WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d571 ; + mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d567 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_3 = WILL_FIRE_RL_mmioPlatform_processMTime && - mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d636 ; + mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d632 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_4 = WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && - (!mmioPlatform_fetchingWay_65_ULT_mmioPlatform_r_ETC___d975 || + (!mmioPlatform_fetchingWay_61_ULT_mmioPlatform_r_ETC___d971 || !mmio_axi4_adapter_f_rsps_to_core$D_OUT[64]) ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_5 = WILL_FIRE_RL_mmioPlatform_waitMTimeDone || @@ -4184,10 +4180,14 @@ module mkProc(CLK, mmioPlatform_reqFunc[5:4] != 2'd1 ; assign MUX_mmioPlatform_curReq$write_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_selectReq && - NOT_mmioPlatform_mtip_0_55_64_AND_mmioPlatform_ETC___d379 ; + (!mmioPlatform_mtip_0 && + mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 || + core_0$mmioToPlatform_cRq_notEmpty) ; assign MUX_mmioPlatform_fetchingWay$write_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_55_OR_NOT_mmioPlatform_mti_ETC___d410 ; + (mmioPlatform_mtip_0 || + !mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357) && + core_0$mmioToPlatform_cRq_notEmpty ; assign MUX_mmioPlatform_state$write_1__SEL_6 = WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp || @@ -4222,20 +4222,20 @@ module mkProc(CLK, llc$to_child_toC_first[515:0] } ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_2 = { 1'd0, - IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_ETC___d481, + IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d477, (mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? mmioPlatform_reqData[31:0] : - x_data__h30549 } ; + x_data__h30533 } ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_3 = { 7'd106, - (IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 && + (IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && !mmioPlatform_mtip_0) ? 32'd1 : 32'd0 } ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_4 = { 7'd106, - (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && + (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && !mmioPlatform_mtip_0) ? 32'd1 : 32'd0 } ; @@ -4249,35 +4249,35 @@ module mkProc(CLK, (mmioPlatform_reqFunc[5:4] == 2'd0) ? 66'h155555554AAAAAAAA : { 2'h1, - IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_1_ETC___d578 } } ; + IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_1_ETC___d574 } } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_3 = { mmioPlatform_reqFunc[5:4] != 2'd0, (mmioPlatform_reqFunc[5:4] == 2'd0) ? 66'h155555554AAAAAAAA : { 2'h1, - IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_1_ETC___d642 } } ; + IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_1_ETC___d638 } } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_4 = { 1'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] && mmioPlatform_fetchingWay, - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d983, + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d979, mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] || mmioPlatform_fetchingWay, - IF_mmio_axi4_adapter_f_rsps_to_core_first__56__ETC___d991 } ; + IF_mmio_axi4_adapter_f_rsps_to_core_first__52__ETC___d987 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_5 = { 3'd5, mmioPlatform_amoResp } ; - assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6 = { 3'd5, data__h31966 } ; + assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6 = { 3'd5, data__h31950 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_7 = { mmioPlatform_reqFunc[5:4] != 2'd0, (mmioPlatform_reqFunc[5:4] == 2'd0) ? 66'h155555554AAAAAAAA : - DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_40_BIT_ETC___d684 } ; + DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_36_BIT_ETC___d680 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_8 = { mmioPlatform_reqFunc[5:4] != 2'd0, (mmioPlatform_reqFunc[5:4] == 2'd0) ? 66'h155555554AAAAAAAA : { 1'h0, - IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_2_ETC___d723 } } ; + IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_2_ETC___d719 } } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_9 = { 2'd2, mmio_axi4_adapter_f_rsps_to_core$D_OUT } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_10 = @@ -4291,10 +4291,10 @@ module mkProc(CLK, llc_mem_server_rg_cacheline_cache_data, 5'd10 } ; assign MUX_llc$dma_memReq_enq_1__VAL_2 = - { line_addr__h101862, + { line_addr__h101846, 581'h0000000000000000155555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555554A } ; assign MUX_llc$dma_memReq_enq_1__VAL_3 = - { line_addr__h101948, + { line_addr__h101932, 581'h0000000000000000155555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555554A } ; assign MUX_llc$dma_memReq_enq_1__VAL_4 = { llc_mem_server_tlbQ$D_OUT[64:1], @@ -4302,29 +4302,28 @@ module mkProc(CLK, llc_mem_server_tlbQ$D_OUT[0], llc_mem_server_tlbQ$D_OUT[6:4] } ; assign MUX_llc_mem_server_rg_cacheline_cache_data$write_1__VAL_1 = - { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1582, + { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1578, (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd1) ? - new_dword__h89489 : + new_dword__h89473 : llc_mem_server_rg_cacheline_cache_data[127:64], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd0) ? - new_dword__h89489 : + new_dword__h89473 : llc_mem_server_rg_cacheline_cache_data[63:0] } ; assign MUX_llc_mem_server_rg_cacheline_cache_dirty_delay$write_1__VAL_2 = llc_mem_server_rg_cacheline_cache_dirty_delay - 10'd1 ; assign MUX_mmioPlatform_amoResp$write_1__VAL_1 = (mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtimecmp_0 : - IF_mmioPlatform_reqBE_43_BIT_4_44_THEN_SEXT_mm_ETC___d577 ; + IF_mmioPlatform_reqBE_39_BIT_4_40_THEN_SEXT_mm_ETC___d573 ; assign MUX_mmioPlatform_amoResp$write_1__VAL_2 = (mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtime : - IF_mmioPlatform_reqBE_43_BIT_4_44_THEN_SEXT_mm_ETC___d641 ; + IF_mmioPlatform_reqBE_39_BIT_4_40_THEN_SEXT_mm_ETC___d637 ; assign MUX_mmioPlatform_curReq$write_1__VAL_1 = (!mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 && - mmioPlatform_mtimecmp_0 != 64'd0) ? + mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357) ? 67'h1AAAAAAAAAAAAAAAA : ((core_0$mmioToPlatform_cRq_first[141:81] >= 61'd33554432 && core_0$mmioToPlatform_cRq_first[141:81] < 61'd33554433) ? @@ -4335,7 +4334,7 @@ module mkProc(CLK, ((core_0$mmioToPlatform_cRq_first[141:81] == 61'd33560575) ? 67'h4AAAAAAAAAAAAAAAA : - IF_core_0_mmioToPlatform_cRq_first__82_BITS_14_ETC___d405))) ; + IF_core_0_mmioToPlatform_cRq_first__78_BITS_14_ETC___d401))) ; assign MUX_mmioPlatform_curReq$write_1__VAL_2 = { 3'd7, mmioPlatform_instSel ? @@ -4348,12 +4347,11 @@ module mkProc(CLK, mmioPlatform_instSel + 1'd1 ; assign MUX_mmioPlatform_mtime$write_1__VAL_2 = mmioPlatform_mtime + 64'd1 ; assign MUX_mmioPlatform_mtip_0$write_1__VAL_2 = - IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 && + IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && !mmioPlatform_mtip_0 ; assign MUX_mmioPlatform_state$write_1__VAL_1 = (!mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 && - mmioPlatform_mtimecmp_0 != 64'd0) ? + mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357) ? 2'd3 : 2'd2 ; assign MUX_mmioPlatform_state$write_1__VAL_2 = @@ -4364,32 +4362,32 @@ module mkProc(CLK, (mmioPlatform_reqBE[0] ? 2'd3 : 2'd1) : 2'd3) ; always@(mmioPlatform_reqFunc or - IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 or + IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 or mmioPlatform_mtip_0) begin case (mmioPlatform_reqFunc[5:4]) 2'd0: MUX_mmioPlatform_state$write_1__VAL_3 = 2'd1; 2'd1: MUX_mmioPlatform_state$write_1__VAL_3 = mmioPlatform_reqFunc[5:4]; default: MUX_mmioPlatform_state$write_1__VAL_3 = - (IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 && + (IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && !mmioPlatform_mtip_0 || - !IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 && + !IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && mmioPlatform_mtip_0) ? 2'd3 : 2'd1; endcase end always@(mmioPlatform_reqFunc or - mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 or + mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 or mmioPlatform_mtip_0) begin case (mmioPlatform_reqFunc[5:4]) 2'd0: MUX_mmioPlatform_state$write_1__VAL_4 = 2'd1; 2'd1: MUX_mmioPlatform_state$write_1__VAL_4 = mmioPlatform_reqFunc[5:4]; default: MUX_mmioPlatform_state$write_1__VAL_4 = - (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && + (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && + !mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && mmioPlatform_mtip_0) ? 2'd3 : 2'd1; @@ -4397,29 +4395,29 @@ module mkProc(CLK, end assign MUX_mmioPlatform_state$write_1__VAL_5 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] ? - (mmioPlatform_fetchingWay_65_ULT_mmioPlatform_r_ETC___d975 ? + (mmioPlatform_fetchingWay_61_ULT_mmioPlatform_r_ETC___d971 ? 2'd2 : 2'd1) : 2'd1 ; assign MUX_mmioPlatform_waitMTIPCRs$write_1__VAL_2 = - mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && + mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && + !mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && mmioPlatform_mtip_0 ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_1 = { mmioPlatform_curReq[63:0], 6'd42, mmioPlatform_reqBE, - x__h47873 } ; + x__h47857 } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_2 = { mmioPlatform_curReq[63:0], - IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_ETC___d481, + IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d477, mmioPlatform_reqBE, mmioPlatform_reqData } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_3 = { mmioPlatform_curReq[63:0], 78'h1AAAAAAAAAAAAAAAAAAA } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_4 = - { x__h49985, 78'h1AAAAAAAAAAAAAAAAAAA } ; + { x__h49969, 78'h1AAAAAAAAAAAAAAAAAAA } ; assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_1 = { 1'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[141:78] } ; assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_3 = @@ -4427,47 +4425,47 @@ module mkProc(CLK, mmio_axi4_adapter_master_xactor_rg_rd_data[66:3] } ; // inlined wires - assign mmioPlatform_toHostQ_enqReq_lat_0$wget = { 1'd1, x__h42877 } ; + assign mmioPlatform_toHostQ_enqReq_lat_0$wget = { 1'd1, x__h42861 } ; assign mmioPlatform_toHostQ_enqReq_lat_0$whas = WILL_FIRE_RL_mmioPlatform_processToHost && mmioPlatform_reqFunc[5:4] == 2'd2 && mmioPlatform_toHostQ_empty && - x__h42877 != 64'd0 ; + x__h42861 != 64'd0 ; assign mmioPlatform_fromHostQ_deqReq_lat_0$whas = WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && !mmioPlatform_fromHostQ_empty && - x__h40857 == 64'd0 ; + x__h40841 == 64'd0 ; assign propDstIdx_0_lat_1$whas = - NOT_enqDst_0_dummy2_0_read__079_080_OR_NOT_enq_ETC___d1095 && - IF_SEL_ARR_propDstIdx_0_dummy2_1_read__058_AND_ETC___d1165 ; + NOT_enqDst_0_dummy2_0_read__075_076_OR_NOT_enq_ETC___d1091 && + IF_SEL_ARR_propDstIdx_0_dummy2_1_read__054_AND_ETC___d1161 ; assign propDstIdx_1_lat_1$whas = - NOT_enqDst_0_dummy2_0_read__079_080_OR_NOT_enq_ETC___d1095 && - x__h61277 ; + NOT_enqDst_0_dummy2_0_read__075_076_OR_NOT_enq_ETC___d1091 && + x__h61261 ; assign propDstData_0_lat_0$wget = { core_0$dCacheToParent_rqToP_first, 1'd0 } ; assign propDstData_1_lat_0$wget = { core_0$iCacheToParent_rqToP_first, 1'd1 } ; assign enqDst_0_lat_0$wget = { 1'd1, - CASE_x1277_0_n__read_addr1459_1_n__read_addr15_ETC__q23, - SEL_ARR_IF_propDstData_0_dummy2_1_read__096_TH_ETC___d1160 } ; + CASE_x1261_0_n__read_addr1443_1_n__read_addr15_ETC__q23, + SEL_ARR_IF_propDstData_0_dummy2_1_read__092_TH_ETC___d1156 } ; assign propDstIdx_1_0_lat_1$whas = - NOT_enqDst_1_0_dummy2_0_read__348_349_OR_NOT_e_ETC___d1364 && - IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__317_A_ETC___d1462 ; + NOT_enqDst_1_0_dummy2_0_read__344_345_OR_NOT_e_ETC___d1360 && + IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__313_A_ETC___d1458 ; assign propDstIdx_1_1_lat_1$whas = - NOT_enqDst_1_0_dummy2_0_read__348_349_OR_NOT_e_ETC___d1364 && - x__h79900 ; + NOT_enqDst_1_0_dummy2_0_read__344_345_OR_NOT_e_ETC___d1360 && + x__h79884 ; assign propDstData_1_0_lat_0$wget = { core_0$dCacheToParent_rsToP_first, 1'd0 } ; assign propDstData_1_1_lat_0$wget = { core_0$iCacheToParent_rsToP_first, 1'd1 } ; assign enqDst_1_0_lat_0$wget = { 1'd1, - CASE_x9900_0_n__read_addr0078_1_n__read_addr01_ETC__q34, - SEL_ARR_IF_propDstData_1_0_dummy2_1_read__365__ETC___d1457 } ; + CASE_x9884_0_n__read_addr0062_1_n__read_addr01_ETC__q34, + SEL_ARR_IF_propDstData_1_0_dummy2_1_read__361__ETC___d1453 } ; assign llc_mem_server_enqDst_0_lat_0$wget = - { 1'd1, n__read_snd_addr__h123389, n__read_snd_id__h123390 } ; + { 1'd1, n__read_snd_addr__h123373, n__read_snd_id__h123374 } ; assign mmio_axi4_adapter_master_xactor_crg_wr_addr_full$EN_port1__write = mmio_axi4_adapter_master_xactor_crg_wr_addr_full && master1_awready ; @@ -4581,11 +4579,11 @@ module mkProc(CLK, assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 = llc_axi4_adapter_ctr_wr_rsps_pending_crg + 4'd1 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 = - b__h133661 - 4'd1 ; + b__h133645 - 4'd1 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read = CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp ? llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 : - b__h133661 ; + b__h133645 ; // register cfg_verbosity assign cfg_verbosity$D_IN = @@ -4597,10 +4595,10 @@ module mkProc(CLK, // register enqDst_0_rl assign enqDst_0_rl$D_IN = { !CAN_FIRE_RL_doEnq && - IF_enqDst_0_lat_0_whas__034_THEN_enqDst_0_lat__ETC___d1039, + IF_enqDst_0_lat_0_whas__030_THEN_enqDst_0_lat__ETC___d1035, CAN_FIRE_RL_doEnq ? 73'h0AAAAAAAAAAAAAAAAAA : - (NOT_enqDst_0_dummy2_0_read__079_080_OR_NOT_enq_ETC___d1095 ? + (NOT_enqDst_0_dummy2_0_read__075_076_OR_NOT_enq_ETC___d1091 ? enqDst_0_lat_0$wget[72:0] : enqDst_0_rl[72:0]) } ; assign enqDst_0_rl$EN = 1'd1 ; @@ -4608,8 +4606,8 @@ module mkProc(CLK, // register enqDst_1_0_rl assign enqDst_1_0_rl$D_IN = { !CAN_FIRE_RL_doEnq_1 && - IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1270, - IF_enqDst_1_0_lat_1_whas__262_THEN_enqDst_1_0__ETC___d1309 } ; + IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1266, + IF_enqDst_1_0_lat_1_whas__258_THEN_enqDst_1_0__ETC___d1305 } ; assign enqDst_1_0_rl$EN = 1'd1 ; // register llc_axi4_adapter_cfg_verbosity @@ -4648,7 +4646,7 @@ module mkProc(CLK, // register llc_axi4_adapter_master_xactor_rg_rd_addr assign llc_axi4_adapter_master_xactor_rg_rd_addr$D_IN = - { 4'd0, mem_req_rd_addr_araddr__h133954, 29'd851968 } ; + { 4'd0, mem_req_rd_addr_araddr__h133938, 29'd851968 } ; assign llc_axi4_adapter_master_xactor_rg_rd_addr$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ; @@ -4659,13 +4657,13 @@ module mkProc(CLK, // register llc_axi4_adapter_master_xactor_rg_wr_addr assign llc_axi4_adapter_master_xactor_rg_wr_addr$D_IN = - { 4'd0, mem_req_wr_addr_awaddr__h147878, 29'd851968 } ; + { 4'd0, mem_req_wr_addr_awaddr__h147862, 29'd851968 } ; assign llc_axi4_adapter_master_xactor_rg_wr_addr$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ; // register llc_axi4_adapter_master_xactor_rg_wr_data assign llc_axi4_adapter_master_xactor_rg_wr_data$D_IN = - { data64__h147793, strb8__h147794, 1'd1 } ; + { data64__h147777, strb8__h147778, 1'd1 } ; assign llc_axi4_adapter_master_xactor_rg_wr_data$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ; @@ -4677,7 +4675,7 @@ module mkProc(CLK, !llc_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read ; // register llc_axi4_adapter_rg_cline - assign llc_axi4_adapter_rg_cline$D_IN = new_cline__h134656 ; + assign llc_axi4_adapter_rg_cline$D_IN = new_cline__h134640 ; assign llc_axi4_adapter_rg_cline$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps ; @@ -4708,10 +4706,10 @@ module mkProc(CLK, // register llc_mem_server_enqDst_0_rl assign llc_mem_server_enqDst_0_rl$D_IN = { !CAN_FIRE_RL_llc_mem_server_doEnq && - IF_llc_mem_server_enqDst_0_lat_0_whas__662_THE_ETC___d1667, + IF_llc_mem_server_enqDst_0_lat_0_whas__658_THE_ETC___d1663, CAN_FIRE_RL_llc_mem_server_doEnq ? 65'h0AAAAAAAAAAAAAAAA : - (NOT_llc_mem_server_enqDst_0_dummy2_0_read__693_ETC___d1700 ? + (NOT_llc_mem_server_enqDst_0_dummy2_0_read__689_ETC___d1696 ? llc_mem_server_enqDst_0_lat_0$wget[64:0] : llc_mem_server_enqDst_0_rl[64:0]) } ; assign llc_mem_server_enqDst_0_rl$EN = 1'd1 ; @@ -4725,15 +4723,15 @@ module mkProc(CLK, // register llc_mem_server_propDstIdx_0_rl assign llc_mem_server_propDstIdx_0_rl$D_IN = - !NOT_llc_mem_server_enqDst_0_dummy2_0_read__693_ETC___d1700 && - IF_llc_mem_server_propDstIdx_0_lat_0_whas__647_ETC___d1650 ; + !NOT_llc_mem_server_enqDst_0_dummy2_0_read__689_ETC___d1696 && + IF_llc_mem_server_propDstIdx_0_lat_0_whas__643_ETC___d1646 ; assign llc_mem_server_propDstIdx_0_rl$EN = 1'd1 ; // register llc_mem_server_rg_cacheline_cache_addr assign llc_mem_server_rg_cacheline_cache_addr$D_IN = WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ? - line_addr__h101862 : - line_addr__h101948 ; + line_addr__h101846 : + line_addr__h101932 ; assign llc_mem_server_rg_cacheline_cache_addr$EN = WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st || WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld ; @@ -4804,11 +4802,10 @@ module mkProc(CLK, MUX_mmioPlatform_curReq$write_1__VAL_1 : MUX_mmioPlatform_curReq$write_1__VAL_2 ; assign mmioPlatform_curReq$EN = - WILL_FIRE_RL_mmioPlatform_selectReq && - NOT_mmioPlatform_mtip_0_55_64_AND_mmioPlatform_ETC___d379 || + MUX_mmioPlatform_curReq$write_1__SEL_1 || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] && - mmioPlatform_fetchingWay_65_ULT_mmioPlatform_r_ETC___d975 ; + mmioPlatform_fetchingWay_61_ULT_mmioPlatform_r_ETC___d971 ; // register mmioPlatform_cycle assign mmioPlatform_cycle$D_IN = @@ -4821,11 +4818,11 @@ module mkProc(CLK, // register mmioPlatform_fetchedInsts_0 assign mmioPlatform_fetchedInsts_0$D_IN = - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d983 ; + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d979 ; assign mmioPlatform_fetchedInsts_0$EN = WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] && - mmioPlatform_fetchingWay_65_ULT_mmioPlatform_r_ETC___d975 && + mmioPlatform_fetchingWay_61_ULT_mmioPlatform_r_ETC___d971 && !mmioPlatform_fetchingWay ; // register mmioPlatform_fetchingWay @@ -4834,10 +4831,12 @@ module mkProc(CLK, MUX_mmioPlatform_fetchingWay$write_1__VAL_2 ; assign mmioPlatform_fetchingWay$EN = WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_55_OR_NOT_mmioPlatform_mti_ETC___d410 || + (mmioPlatform_mtip_0 || + !mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357) && + core_0$mmioToPlatform_cRq_notEmpty || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] && - mmioPlatform_fetchingWay_65_ULT_mmioPlatform_r_ETC___d975 ; + mmioPlatform_fetchingWay_61_ULT_mmioPlatform_r_ETC___d971 ; // register mmioPlatform_fromHostAddr assign mmioPlatform_fromHostAddr$D_IN = start_fromhostAddr[63:3] ; @@ -4883,15 +4882,17 @@ module mkProc(CLK, MUX_mmioPlatform_instSel$write_1__VAL_2 ; assign mmioPlatform_instSel$EN = WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_55_OR_NOT_mmioPlatform_mti_ETC___d410 || + (mmioPlatform_mtip_0 || + !mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357) && + core_0$mmioToPlatform_cRq_notEmpty || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] && - mmioPlatform_fetchingWay_65_ULT_mmioPlatform_r_ETC___d975 ; + mmioPlatform_fetchingWay_61_ULT_mmioPlatform_r_ETC___d971 ; // register mmioPlatform_mtime assign mmioPlatform_mtime$D_IN = MUX_mmioPlatform_amoResp$write_1__SEL_2 ? - newData__h34977 : + newData__h34961 : MUX_mmioPlatform_mtime$write_1__VAL_2 ; assign mmioPlatform_mtime$EN = WILL_FIRE_RL_mmioPlatform_processMTime && @@ -4900,7 +4901,7 @@ module mkProc(CLK, WILL_FIRE_RL_mmioPlatform_incTime ; // register mmioPlatform_mtimecmp_0 - assign mmioPlatform_mtimecmp_0$D_IN = newData__h32047 ; + assign mmioPlatform_mtimecmp_0$D_IN = newData__h32031 ; assign mmioPlatform_mtimecmp_0$EN = MUX_mmioPlatform_amoResp$write_1__SEL_1 ; @@ -4910,10 +4911,9 @@ module mkProc(CLK, MUX_mmioPlatform_mtip_0$write_1__VAL_2 ; assign mmioPlatform_mtip_0$EN = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 && - mmioPlatform_mtimecmp_0 != 64'd0 || + mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 || WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d585 ; + NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d581 ; // register mmioPlatform_reqAmofunc assign mmioPlatform_reqAmofunc$D_IN = @@ -4983,8 +4983,7 @@ module mkProc(CLK, endcase end assign mmioPlatform_state$EN = - WILL_FIRE_RL_mmioPlatform_selectReq && - NOT_mmioPlatform_mtip_0_55_64_AND_mmioPlatform_ETC___d379 || + MUX_mmioPlatform_curReq$write_1__SEL_1 || WILL_FIRE_RL_mmioPlatform_processMSIP || WILL_FIRE_RL_mmioPlatform_processMTimeCmp || WILL_FIRE_RL_mmioPlatform_processMTime || @@ -5048,7 +5047,7 @@ module mkProc(CLK, mmioPlatform_reqBE[0] ; assign mmioPlatform_waitLowerMSIPCRs$EN = WILL_FIRE_RL_mmioPlatform_processMSIP && - NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d490 ; + NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d486 ; // register mmioPlatform_waitMTIPCRs assign mmioPlatform_waitMTIPCRs$D_IN = @@ -5056,16 +5055,15 @@ module mkProc(CLK, MUX_mmioPlatform_waitMTIPCRs$write_1__VAL_2 ; assign mmioPlatform_waitMTIPCRs$EN = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 && - mmioPlatform_mtimecmp_0 != 64'd0 || + mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 || WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d648 ; + NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d644 ; // register mmioPlatform_waitUpperMSIPCRs assign mmioPlatform_waitUpperMSIPCRs$D_IN = 1'd0 ; assign mmioPlatform_waitUpperMSIPCRs$EN = WILL_FIRE_RL_mmioPlatform_processMSIP && - NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d490 ; + NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d486 ; // register mmio_axi4_adapter_cfg_verbosity assign mmio_axi4_adapter_cfg_verbosity$D_IN = 4'h0 ; @@ -5151,28 +5149,28 @@ module mkProc(CLK, // register propDstData_1_0_rl assign propDstData_1_0_rl$D_IN = - { IF_propDstData_1_0_lat_0_whas__189_THEN_propDs_ETC___d1194, - IF_propDstData_1_0_lat_0_whas__189_THEN_propDs_ETC___d1199, + { IF_propDstData_1_0_lat_0_whas__185_THEN_propDs_ETC___d1190, + IF_propDstData_1_0_lat_0_whas__185_THEN_propDs_ETC___d1195, CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[513] : propDstData_1_0_rl[513], CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[512:1] : propDstData_1_0_rl[512:1], - IF_propDstData_1_0_lat_0_whas__189_THEN_propDs_ETC___d1220 } ; + IF_propDstData_1_0_lat_0_whas__185_THEN_propDs_ETC___d1216 } ; assign propDstData_1_0_rl$EN = 1'd1 ; // register propDstData_1_1_rl assign propDstData_1_1_rl$D_IN = - { IF_propDstData_1_1_lat_0_whas__227_THEN_propDs_ETC___d1232, - IF_propDstData_1_1_lat_0_whas__227_THEN_propDs_ETC___d1237, + { IF_propDstData_1_1_lat_0_whas__223_THEN_propDs_ETC___d1228, + IF_propDstData_1_1_lat_0_whas__223_THEN_propDs_ETC___d1233, CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[513] : propDstData_1_1_rl[513], CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[512:1] : propDstData_1_1_rl[512:1], - IF_propDstData_1_1_lat_0_whas__227_THEN_propDs_ETC___d1258 } ; + IF_propDstData_1_1_lat_0_whas__223_THEN_propDs_ETC___d1254 } ; assign propDstData_1_1_rl$EN = 1'd1 ; // register propDstData_1_rl @@ -5185,36 +5183,36 @@ module mkProc(CLK, // register propDstIdx_0_rl assign propDstIdx_0_rl$D_IN = !propDstIdx_0_lat_1$whas && - IF_propDstIdx_0_lat_0_whas__005_THEN_propDstId_ETC___d1008 ; + IF_propDstIdx_0_lat_0_whas__001_THEN_propDstId_ETC___d1004 ; assign propDstIdx_0_rl$EN = 1'd1 ; // register propDstIdx_1_0_rl assign propDstIdx_1_0_rl$D_IN = !propDstIdx_1_0_lat_1$whas && - IF_propDstIdx_1_0_lat_0_whas__174_THEN_propDst_ETC___d1177 ; + IF_propDstIdx_1_0_lat_0_whas__170_THEN_propDst_ETC___d1173 ; assign propDstIdx_1_0_rl$EN = 1'd1 ; // register propDstIdx_1_1_rl assign propDstIdx_1_1_rl$D_IN = !propDstIdx_1_1_lat_1$whas && - IF_propDstIdx_1_1_lat_0_whas__181_THEN_propDst_ETC___d1184 ; + IF_propDstIdx_1_1_lat_0_whas__177_THEN_propDst_ETC___d1180 ; assign propDstIdx_1_1_rl$EN = 1'd1 ; // register propDstIdx_1_rl assign propDstIdx_1_rl$D_IN = !propDstIdx_1_lat_1$whas && - IF_propDstIdx_1_lat_0_whas__012_THEN_propDstId_ETC___d1015 ; + IF_propDstIdx_1_lat_0_whas__008_THEN_propDstId_ETC___d1011 ; assign propDstIdx_1_rl$EN = 1'd1 ; // register srcRR_0 assign srcRR_0$D_IN = srcRR_0 + 1'd1 ; assign srcRR_0$EN = - NOT_enqDst_0_dummy2_0_read__079_080_OR_NOT_enq_ETC___d1095 ; + NOT_enqDst_0_dummy2_0_read__075_076_OR_NOT_enq_ETC___d1091 ; // register srcRR_1_0 assign srcRR_1_0$D_IN = srcRR_1_0 + 1'd1 ; assign srcRR_1_0$EN = - NOT_enqDst_1_0_dummy2_0_read__348_349_OR_NOT_e_ETC___d1364 ; + NOT_enqDst_1_0_dummy2_0_read__344_345_OR_NOT_e_ETC___d1360 ; // submodule core_0 assign core_0$coreReq_perfReq_loc = 4'h0 ; @@ -5323,7 +5321,7 @@ module mkProc(CLK, assign core_0$setMEIP_v = m_external_interrupt_req_set_not_clear ; assign core_0$setSEIP_v = s_external_interrupt_req_set_not_clear ; assign core_0$tlbToMem_respLd_enq_x = - { ld_data__h131955, llc$dma_respLd_first[3] } ; + { ld_data__h131939, llc$dma_respLd_first[3] } ; assign core_0$EN_coreReq_start = EN_start ; assign core_0$EN_coreReq_perfReq = 1'b0 ; assign core_0$EN_coreIndInv_perfResp = 1'b0 ; @@ -5344,13 +5342,13 @@ module mkProc(CLK, MUX_mmioPlatform_fetchingWay$write_1__SEL_1 ; assign core_0$EN_mmioToPlatform_pRs_enq = WILL_FIRE_RL_mmioPlatform_processMSIP && - mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d467 || + mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d463 || WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d571 || + mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d567 || WILL_FIRE_RL_mmioPlatform_processMTime && - mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d636 || + mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d632 || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && - (!mmioPlatform_fetchingWay_65_ULT_mmioPlatform_r_ETC___d975 || + (!mmioPlatform_fetchingWay_61_ULT_mmioPlatform_r_ETC___d971 || !mmio_axi4_adapter_f_rsps_to_core$D_OUT[64]) || WILL_FIRE_RL_mmioPlatform_waitMTimeDone || WILL_FIRE_RL_mmioPlatform_waitMTimeCmpDone || @@ -5361,16 +5359,15 @@ module mkProc(CLK, WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp ; assign core_0$EN_mmioToPlatform_pRq_enq = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 && - mmioPlatform_mtimecmp_0 != 64'd0 || + mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 || WILL_FIRE_RL_mmioPlatform_processMSIP && mmioPlatform_reqFunc[5:4] != 2'd0 && !mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0] || WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d585 || + NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d581 || WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d648 ; + NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d644 ; assign core_0$EN_mmioToPlatform_cRs_deq = (WILL_FIRE_RL_mmioPlatform_waitMTimeDone || WILL_FIRE_RL_mmioPlatform_waitTimerInterruptDone) && @@ -5427,7 +5424,7 @@ module mkProc(CLK, // submodule enqDst_0_dummy2_0 assign enqDst_0_dummy2_0$D_IN = 1'd1 ; assign enqDst_0_dummy2_0$EN = - NOT_enqDst_0_dummy2_0_read__079_080_OR_NOT_enq_ETC___d1095 ; + NOT_enqDst_0_dummy2_0_read__075_076_OR_NOT_enq_ETC___d1091 ; // submodule enqDst_0_dummy2_1 assign enqDst_0_dummy2_1$D_IN = 1'd1 ; @@ -5436,7 +5433,7 @@ module mkProc(CLK, // submodule enqDst_1_0_dummy2_0 assign enqDst_1_0_dummy2_0$D_IN = 1'd1 ; assign enqDst_1_0_dummy2_0$EN = - NOT_enqDst_1_0_dummy2_0_read__348_349_OR_NOT_e_ETC___d1364 ; + NOT_enqDst_1_0_dummy2_0_read__344_345_OR_NOT_e_ETC___d1360 ; // submodule enqDst_1_0_dummy2_1 assign enqDst_1_0_dummy2_1$D_IN = 1'd1 ; @@ -5468,17 +5465,17 @@ module mkProc(CLK, assign llc$perf_req_r = 4'h0 ; assign llc$perf_setStatus_doStats = core_0$sendDoStats ; assign llc$to_child_rqFromC_enq_x = - NOT_enqDst_0_dummy2_0_read__079_080_OR_NOT_enq_ETC___d1095 ? + NOT_enqDst_0_dummy2_0_read__075_076_OR_NOT_enq_ETC___d1091 ? enqDst_0_lat_0$wget[72:0] : enqDst_0_rl[72:0] ; assign llc$to_child_rsFromC_enq_x = - { IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1280, - IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1285, - IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1290, - IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1300, - IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1306 } ; + { IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1276, + IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1281, + IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1286, + IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1296, + IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1302 } ; assign llc$to_mem_rsFromM_enq_x = - { new_cline__h134656, + { new_cline__h134640, llc_axi4_adapter_f_pending_reads$D_OUT[4:0] } ; assign llc$EN_to_child_rsFromC_enq = CAN_FIRE_RL_doEnq_1 ; assign llc$EN_to_child_rqFromC_enq = CAN_FIRE_RL_doEnq ; @@ -5554,7 +5551,7 @@ module mkProc(CLK, // submodule llc_mem_server_axi4_slave_xactor_f_rd_data assign llc_mem_server_axi4_slave_xactor_f_rd_data$D_IN = - { 4'd0, dword__h93798, 3'd1 } ; + { 4'd0, dword__h93782, 3'd1 } ; assign llc_mem_server_axi4_slave_xactor_f_rd_data$ENQ = CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req ; assign llc_mem_server_axi4_slave_xactor_f_rd_data$DEQ = @@ -5605,7 +5602,7 @@ module mkProc(CLK, // submodule llc_mem_server_enqDst_0_dummy2_0 assign llc_mem_server_enqDst_0_dummy2_0$D_IN = 1'd1 ; assign llc_mem_server_enqDst_0_dummy2_0$EN = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__693_ETC___d1700 ; + NOT_llc_mem_server_enqDst_0_dummy2_0_read__689_ETC___d1696 ; // submodule llc_mem_server_enqDst_0_dummy2_1 assign llc_mem_server_enqDst_0_dummy2_1$D_IN = 1'd1 ; @@ -5635,11 +5632,11 @@ module mkProc(CLK, // submodule llc_mem_server_propDstIdx_0_dummy2_1 assign llc_mem_server_propDstIdx_0_dummy2_1$D_IN = 1'd1 ; assign llc_mem_server_propDstIdx_0_dummy2_1$EN = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__693_ETC___d1700 ; + NOT_llc_mem_server_enqDst_0_dummy2_0_read__689_ETC___d1696 ; // submodule llc_mem_server_tlbQ assign llc_mem_server_tlbQ$D_IN = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__693_ETC___d1700 ? + NOT_llc_mem_server_enqDst_0_dummy2_0_read__689_ETC___d1696 ? llc_mem_server_enqDst_0_lat_0$wget[64:0] : llc_mem_server_enqDst_0_rl[64:0] ; assign llc_mem_server_tlbQ$ENQ = CAN_FIRE_RL_llc_mem_server_doEnq ; @@ -5857,86 +5854,86 @@ module mkProc(CLK, // remaining internal signals module_amoExec instance_amoExec_0(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h30134 && - mmioPlatform_reqBE_BIT_0___h30174, + mmioPlatform_reqBE_BIT_4___h30118 && + mmioPlatform_reqBE_BIT_0___h30158, 2'd0 }), - .amoExec_current_data(x__h37428), - .amoExec_in_data(mmioPlatform_reqData__h48469), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30134 && - !mmioPlatform_reqBE_BIT_0___h30174), - .amoExec(x__h32158)); + .amoExec_current_data(x__h37412), + .amoExec_in_data(mmioPlatform_reqData__h48453), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30118 && + !mmioPlatform_reqBE_BIT_0___h30158), + .amoExec(x__h32142)); module_amoExec instance_amoExec_1(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h30134 && - mmioPlatform_reqBE_BIT_0___h30174, + mmioPlatform_reqBE_BIT_4___h30118 && + mmioPlatform_reqBE_BIT_0___h30158, 2'd0 }), - .amoExec_current_data(mmioPlatform_mtime__h37280), - .amoExec_in_data(mmioPlatform_reqData__h48469), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30134 && - !mmioPlatform_reqBE_BIT_0___h30174), - .amoExec(x__h35068)); + .amoExec_current_data(mmioPlatform_mtime__h37264), + .amoExec_in_data(mmioPlatform_reqData__h48453), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30118 && + !mmioPlatform_reqBE_BIT_0___h30158), + .amoExec(x__h35052)); module_amoExec instance_amoExec_2(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h30134 && - mmioPlatform_reqBE_BIT_0___h30174, + mmioPlatform_reqBE_BIT_4___h30118 && + mmioPlatform_reqBE_BIT_0___h30158, 2'd0 }), - .amoExec_current_data(mmioPlatform_fromHostQ_data_0__h42667), - .amoExec_in_data(mmioPlatform_reqData__h48469), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30134 && - !mmioPlatform_reqBE_BIT_0___h30174), - .amoExec(x__h40868)); + .amoExec_current_data(mmioPlatform_fromHostQ_data_0__h42651), + .amoExec_in_data(mmioPlatform_reqData__h48453), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30118 && + !mmioPlatform_reqBE_BIT_0___h30158), + .amoExec(x__h40852)); module_amoExec instance_amoExec_3(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h30134 && - mmioPlatform_reqBE_BIT_0___h30174, + mmioPlatform_reqBE_BIT_4___h30118 && + mmioPlatform_reqBE_BIT_0___h30158, 2'd0 }), .amoExec_current_data(64'd0), - .amoExec_in_data(mmioPlatform_reqData__h48469), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30134 && - !mmioPlatform_reqBE_BIT_0___h30174), - .amoExec(x__h42888)); - assign DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_40_BIT_ETC___d684 = + .amoExec_in_data(mmioPlatform_reqData__h48453), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30118 && + !mmioPlatform_reqBE_BIT_0___h30158), + .amoExec(x__h42872)); + assign DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_36_BIT_ETC___d680 = { 1'h0, (mmioPlatform_reqFunc[5:4] == 2'd2) ? { mmioPlatform_toHostQ_empty, 64'hAAAAAAAAAAAAAAAA } : { mmioPlatform_reqFunc[5:4] == 2'd1, - x1_avValue_data__h40339 } } ; - assign IF_IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4__ETC___d559 = - (IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 && + x1_avValue_data__h40323 } } ; + assign IF_IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4__ETC___d555 = + (IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && !mmioPlatform_mtip_0 || - !IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 && + !IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && mmioPlatform_mtip_0) ? core_0$RDY_mmioToPlatform_pRq_enq : core_0$RDY_mmioToPlatform_pRs_enq ; - assign IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d456 = + assign IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d452 = (mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? (mmioPlatform_reqBE[0] ? core_0$RDY_mmioToPlatform_pRq_enq : core_0$RDY_mmioToPlatform_pRs_enq) : !mmioPlatform_reqBE[0] || core_0$RDY_mmioToPlatform_pRq_enq ; - assign IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 = - newData__h32047 <= mmioPlatform_mtime ; - assign IF_NOT_propDstIdx_0_dummy2_1_read__058_059_OR__ETC___d1093 = - NOT_propDstIdx_0_dummy2_1_read__058_059_OR_IF__ETC___d1092 ? + assign IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 = + newData__h32031 <= mmioPlatform_mtime ; + assign IF_NOT_propDstIdx_0_dummy2_1_read__054_055_OR__ETC___d1089 = + NOT_propDstIdx_0_dummy2_1_read__054_055_OR_IF__ETC___d1088 ? propDstIdx_1_dummy2_1$Q_OUT && - IF_propDstIdx_1_lat_0_whas__012_THEN_propDstId_ETC___d1015 : + IF_propDstIdx_1_lat_0_whas__008_THEN_propDstId_ETC___d1011 : propDstIdx_0_dummy2_1$Q_OUT && - IF_propDstIdx_0_lat_0_whas__005_THEN_propDstId_ETC___d1008 ; - assign IF_NOT_propDstIdx_1_0_dummy2_1_read__317_318_O_ETC___d1362 = - NOT_propDstIdx_1_0_dummy2_1_read__317_318_OR_I_ETC___d1361 ? + IF_propDstIdx_0_lat_0_whas__001_THEN_propDstId_ETC___d1004 ; + assign IF_NOT_propDstIdx_1_0_dummy2_1_read__313_314_O_ETC___d1358 = + NOT_propDstIdx_1_0_dummy2_1_read__313_314_OR_I_ETC___d1357 ? propDstIdx_1_1_dummy2_1$Q_OUT && - IF_propDstIdx_1_1_lat_0_whas__181_THEN_propDst_ETC___d1184 : + IF_propDstIdx_1_1_lat_0_whas__177_THEN_propDst_ETC___d1180 : propDstIdx_1_0_dummy2_1$Q_OUT && - IF_propDstIdx_1_0_lat_0_whas__174_THEN_propDst_ETC___d1177 ; - assign IF_SEL_ARR_propDstIdx_0_dummy2_1_read__058_AND_ETC___d1165 = - SEL_ARR_propDstIdx_0_dummy2_1_read__058_AND_IF_ETC___d1089 ? + IF_propDstIdx_1_0_lat_0_whas__170_THEN_propDst_ETC___d1173 ; + assign IF_SEL_ARR_propDstIdx_0_dummy2_1_read__054_AND_ETC___d1161 = + SEL_ARR_propDstIdx_0_dummy2_1_read__054_AND_IF_ETC___d1085 ? !srcRR_0 : propDstIdx_0_dummy2_1$Q_OUT && - IF_propDstIdx_0_lat_0_whas__005_THEN_propDstId_ETC___d1008 ; - assign IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__317_A_ETC___d1462 = - SEL_ARR_propDstIdx_1_0_dummy2_1_read__317_AND__ETC___d1358 ? + IF_propDstIdx_0_lat_0_whas__001_THEN_propDstId_ETC___d1004 ; + assign IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__313_A_ETC___d1458 = + SEL_ARR_propDstIdx_1_0_dummy2_1_read__313_AND__ETC___d1354 ? !srcRR_1_0 : propDstIdx_1_0_dummy2_1$Q_OUT && - IF_propDstIdx_1_0_lat_0_whas__174_THEN_propDst_ETC___d1177 ; - assign IF_core_0_mmioToPlatform_cRq_first__82_BITS_14_ETC___d405 = + IF_propDstIdx_1_0_lat_0_whas__170_THEN_propDst_ETC___d1173 ; + assign IF_core_0_mmioToPlatform_cRq_first__78_BITS_14_ETC___d401 = (core_0$mmioToPlatform_cRq_first[141:81] == mmioPlatform_toHostAddr) ? 67'h5AAAAAAAAAAAAAAAA : @@ -5944,116 +5941,116 @@ module mkProc(CLK, mmioPlatform_fromHostAddr) ? 67'h6AAAAAAAAAAAAAAAA : { 3'd7, core_0$mmioToPlatform_cRq_first[141:78] }) ; - assign IF_enqDst_0_lat_0_whas__034_THEN_enqDst_0_lat__ETC___d1039 = - NOT_enqDst_0_dummy2_0_read__079_080_OR_NOT_enq_ETC___d1095 ? + assign IF_enqDst_0_lat_0_whas__030_THEN_enqDst_0_lat__ETC___d1035 = + NOT_enqDst_0_dummy2_0_read__075_076_OR_NOT_enq_ETC___d1091 ? enqDst_0_lat_0$wget[73] : enqDst_0_rl[73] ; - assign IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1270 = - NOT_enqDst_1_0_dummy2_0_read__348_349_OR_NOT_e_ETC___d1364 ? + assign IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1266 = + NOT_enqDst_1_0_dummy2_0_read__344_345_OR_NOT_e_ETC___d1360 ? enqDst_1_0_lat_0$wget[580] : enqDst_1_0_rl[580] ; - assign IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1280 = - NOT_enqDst_1_0_dummy2_0_read__348_349_OR_NOT_e_ETC___d1364 ? + assign IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1276 = + NOT_enqDst_1_0_dummy2_0_read__344_345_OR_NOT_e_ETC___d1360 ? enqDst_1_0_lat_0$wget[579:516] : enqDst_1_0_rl[579:516] ; - assign IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1285 = - NOT_enqDst_1_0_dummy2_0_read__348_349_OR_NOT_e_ETC___d1364 ? + assign IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1281 = + NOT_enqDst_1_0_dummy2_0_read__344_345_OR_NOT_e_ETC___d1360 ? enqDst_1_0_lat_0$wget[515:514] : enqDst_1_0_rl[515:514] ; - assign IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1290 = - NOT_enqDst_1_0_dummy2_0_read__348_349_OR_NOT_e_ETC___d1364 ? + assign IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1286 = + NOT_enqDst_1_0_dummy2_0_read__344_345_OR_NOT_e_ETC___d1360 ? enqDst_1_0_lat_0$wget[513] : enqDst_1_0_rl[513] ; - assign IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1300 = - NOT_enqDst_1_0_dummy2_0_read__348_349_OR_NOT_e_ETC___d1364 ? + assign IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1296 = + NOT_enqDst_1_0_dummy2_0_read__344_345_OR_NOT_e_ETC___d1360 ? enqDst_1_0_lat_0$wget[512:1] : enqDst_1_0_rl[512:1] ; - assign IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1306 = - NOT_enqDst_1_0_dummy2_0_read__348_349_OR_NOT_e_ETC___d1364 ? + assign IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1302 = + NOT_enqDst_1_0_dummy2_0_read__344_345_OR_NOT_e_ETC___d1360 ? enqDst_1_0_lat_0$wget[0] : enqDst_1_0_rl[0] ; - assign IF_enqDst_1_0_lat_1_whas__262_THEN_enqDst_1_0__ETC___d1308 = + assign IF_enqDst_1_0_lat_1_whas__258_THEN_enqDst_1_0__ETC___d1304 = { CAN_FIRE_RL_doEnq_1 || - IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1290, + IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1286, CAN_FIRE_RL_doEnq_1 ? 512'h55555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555 : - IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1300, - x__h74829 } ; - assign IF_enqDst_1_0_lat_1_whas__262_THEN_enqDst_1_0__ETC___d1309 = + IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1296, + x__h74813 } ; + assign IF_enqDst_1_0_lat_1_whas__258_THEN_enqDst_1_0__ETC___d1305 = { CAN_FIRE_RL_doEnq_1 ? 64'hAAAAAAAAAAAAAAAA : - IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1280, + IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1276, CAN_FIRE_RL_doEnq_1 ? 2'b10 : - IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1285, - IF_enqDst_1_0_lat_1_whas__262_THEN_enqDst_1_0__ETC___d1308 } ; - assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1577 = + IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1281, + IF_enqDst_1_0_lat_1_whas__258_THEN_enqDst_1_0__ETC___d1304 } ; + assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1573 = { (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd7) ? - new_dword__h89489 : + new_dword__h89473 : llc_mem_server_rg_cacheline_cache_data[511:448], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd6) ? - new_dword__h89489 : + new_dword__h89473 : llc_mem_server_rg_cacheline_cache_data[447:384], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd5) ? - new_dword__h89489 : + new_dword__h89473 : llc_mem_server_rg_cacheline_cache_data[383:320], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd4) ? - new_dword__h89489 : + new_dword__h89473 : llc_mem_server_rg_cacheline_cache_data[319:256] } ; - assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1582 = - { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1577, + assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1578 = + { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1573, (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd3) ? - new_dword__h89489 : + new_dword__h89473 : llc_mem_server_rg_cacheline_cache_data[255:192], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd2) ? - new_dword__h89489 : + new_dword__h89473 : llc_mem_server_rg_cacheline_cache_data[191:128] } ; - assign IF_llc_mem_server_enqDst_0_lat_0_whas__662_THE_ETC___d1667 = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__693_ETC___d1700 ? + assign IF_llc_mem_server_enqDst_0_lat_0_whas__658_THE_ETC___d1663 = + NOT_llc_mem_server_enqDst_0_dummy2_0_read__689_ETC___d1696 ? llc_mem_server_enqDst_0_lat_0$wget[65] : llc_mem_server_enqDst_0_rl[65] ; - assign IF_llc_mem_server_propDstIdx_0_lat_0_whas__647_ETC___d1650 = + assign IF_llc_mem_server_propDstIdx_0_lat_0_whas__643_ETC___d1646 = CAN_FIRE_RL_llc_mem_server_srcPropose || llc_mem_server_propDstIdx_0_rl ; - assign IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d825 = + assign IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d821 = (mmioPlatform_curReq[2:0] == 3'h0) ? mmioPlatform_reqData : 64'd0 ; - assign IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d876 = + assign IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d872 = (mmioPlatform_curReq[2:0] == 3'h0) ? mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:0] : 64'd0 ; - assign IF_mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioP_ETC___d625 = - ((mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && + assign IF_mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioP_ETC___d621 = + ((mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && !mmioPlatform_mtip_0) ? core_0$RDY_mmioToPlatform_pRq_enq : - mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 || + mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 || !mmioPlatform_mtip_0 || core_0$RDY_mmioToPlatform_pRq_enq) && - (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && + (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && + !mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && mmioPlatform_mtip_0 || core_0$RDY_mmioToPlatform_pRs_enq) ; - assign IF_mmioPlatform_reqBE_43_BIT_4_44_THEN_SEXT_mm_ETC___d577 = + assign IF_mmioPlatform_reqBE_39_BIT_4_40_THEN_SEXT_mm_ETC___d573 = mmioPlatform_reqBE[4] ? { {32{mmioPlatform_mtimecmp_0_BITS_63_TO_32__q9[31]}}, mmioPlatform_mtimecmp_0_BITS_63_TO_32__q9 } : { {32{mmioPlatform_mtimecmp_0_BITS_31_TO_0__q10[31]}}, mmioPlatform_mtimecmp_0_BITS_31_TO_0__q10 } ; - assign IF_mmioPlatform_reqBE_43_BIT_4_44_THEN_SEXT_mm_ETC___d641 = + assign IF_mmioPlatform_reqBE_39_BIT_4_40_THEN_SEXT_mm_ETC___d637 = mmioPlatform_reqBE[4] ? { {32{mmioPlatform_mtime_BITS_63_TO_32__q11[31]}}, mmioPlatform_mtime_BITS_63_TO_32__q11 } : { {32{mmioPlatform_mtime_BITS_31_TO_0__q12[31]}}, mmioPlatform_mtime_BITS_31_TO_0__q12 } ; - assign IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d535 = + assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d531 = { mmioPlatform_reqBE[7] ? mmioPlatform_reqData[63:56] : mmioPlatform_mtimecmp_0[63:56], @@ -6066,23 +6063,23 @@ module mkProc(CLK, mmioPlatform_reqBE[4] ? mmioPlatform_reqData[39:32] : mmioPlatform_mtimecmp_0[39:32] } ; - assign IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d544 = - { IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d535, + assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d540 = + { IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d531, mmioPlatform_reqBE[3] ? mmioPlatform_reqData[31:24] : mmioPlatform_mtimecmp_0[31:24], mmioPlatform_reqBE[2] ? mmioPlatform_reqData[23:16] : mmioPlatform_mtimecmp_0[23:16] } ; - assign IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d552 = - { IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d544, + assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d548 = + { IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d540, mmioPlatform_reqBE[1] ? mmioPlatform_reqData[15:8] : mmioPlatform_mtimecmp_0[15:8], mmioPlatform_reqBE[0] ? mmioPlatform_reqData[7:0] : mmioPlatform_mtimecmp_0[7:0] } ; - assign IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d604 = + assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d600 = { mmioPlatform_reqBE[7] ? mmioPlatform_reqData[63:56] : mmioPlatform_mtime[63:56], @@ -6095,23 +6092,23 @@ module mkProc(CLK, mmioPlatform_reqBE[4] ? mmioPlatform_reqData[39:32] : mmioPlatform_mtime[39:32] } ; - assign IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d609 = - { IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d604, + assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d605 = + { IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d600, mmioPlatform_reqBE[3] ? mmioPlatform_reqData[31:24] : mmioPlatform_mtime[31:24], mmioPlatform_reqBE[2] ? mmioPlatform_reqData[23:16] : mmioPlatform_mtime[23:16] } ; - assign IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d614 = - { IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d609, + assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d610 = + { IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d605, mmioPlatform_reqBE[1] ? mmioPlatform_reqData[15:8] : mmioPlatform_mtime[15:8], mmioPlatform_reqBE[0] ? mmioPlatform_reqData[7:0] : mmioPlatform_mtime[7:0] } ; - assign IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d705 = + assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d701 = { mmioPlatform_reqBE[7] ? mmioPlatform_reqData[63:56] : mmioPlatform_fromHostQ_data_0[63:56], @@ -6124,49 +6121,49 @@ module mkProc(CLK, mmioPlatform_reqBE[4] ? mmioPlatform_reqData[39:32] : mmioPlatform_fromHostQ_data_0[39:32] } ; - assign IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d710 = - { IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d705, + assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d706 = + { IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d701, mmioPlatform_reqBE[3] ? mmioPlatform_reqData[31:24] : mmioPlatform_fromHostQ_data_0[31:24], mmioPlatform_reqBE[2] ? mmioPlatform_reqData[23:16] : mmioPlatform_fromHostQ_data_0[23:16] } ; - assign IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d715 = - { IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d710, + assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d711 = + { IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d706, mmioPlatform_reqBE[1] ? mmioPlatform_reqData[15:8] : mmioPlatform_fromHostQ_data_0[15:8], mmioPlatform_reqBE[0] ? mmioPlatform_reqData[7:0] : mmioPlatform_fromHostQ_data_0[7:0] } ; - assign IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_ETC___d457 = + assign IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d453 = (mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqBE[4]) ? core_0$RDY_mmioToPlatform_pRs_enq : - IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d456 ; - assign IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_1_ETC___d578 = + IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d452 ; + assign IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_1_ETC___d574 = (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtimecmp_0 : - IF_mmioPlatform_reqBE_43_BIT_4_44_THEN_SEXT_mm_ETC___d577 ; - assign IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_1_ETC___d642 = + IF_mmioPlatform_reqBE_39_BIT_4_40_THEN_SEXT_mm_ETC___d573 ; + assign IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_1_ETC___d638 = (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtime : - IF_mmioPlatform_reqBE_43_BIT_4_44_THEN_SEXT_mm_ETC___d641 ; - assign IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_2_ETC___d723 = + IF_mmioPlatform_reqBE_39_BIT_4_40_THEN_SEXT_mm_ETC___d637 ; + assign IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_2_ETC___d719 = (mmioPlatform_reqFunc[5:4] == 2'd2) ? { mmioPlatform_fromHostQ_empty ? - x__h42877 == 64'd0 : - x__h40857 == 64'd0, + x__h42861 == 64'd0 : + x__h40841 == 64'd0, 64'hAAAAAAAAAAAAAAAA } : { mmioPlatform_reqFunc[5:4] == 2'd1, - x1_avValue_data__h44806 } ; + x1_avValue_data__h44790 } ; assign IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__91__ETC___d200 = mmioPlatform_toHostQ_enqReq_lat_0$whas ? mmioPlatform_toHostQ_enqReq_lat_0$wget[64] : mmioPlatform_toHostQ_enqReq_rl[64] ; - assign IF_mmioPlatform_waitLowerMSIPCRs_92_THEN_core__ETC___d500 = + assign IF_mmioPlatform_waitLowerMSIPCRs_88_THEN_core__ETC___d496 = mmioPlatform_waitLowerMSIPCRs ? core_0$RDY_mmioToPlatform_cRs_first && core_0$RDY_mmioToPlatform_cRs_deq : @@ -6174,99 +6171,99 @@ module mkProc(CLK, core_0$RDY_mmioToPlatform_cRs_first) && (!mmioPlatform_waitUpperMSIPCRs || core_0$RDY_mmioToPlatform_cRs_deq) ; - assign IF_mmio_axi4_adapter_f_rsps_to_core_first__56__ETC___d970 = + assign IF_mmio_axi4_adapter_f_rsps_to_core_first__52__ETC___d966 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] ? mmioPlatform_fetchingWay < (mmioPlatform_reqFunc[5:4] == 2'd0 && mmioPlatform_reqFunc[0]) || core_0$RDY_mmioToPlatform_pRs_enq : core_0$RDY_mmioToPlatform_pRs_enq ; - assign IF_mmio_axi4_adapter_f_rsps_to_core_first__56__ETC___d991 = + assign IF_mmio_axi4_adapter_f_rsps_to_core_first__52__ETC___d987 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] ? (mmioPlatform_fetchingWay ? mmioPlatform_fetchedInsts_0 : - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d983) : + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d979) : mmioPlatform_fetchedInsts_0 ; assign IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d103 = mmio_axi4_adapter_soc_map$m_is_IO_addr ? !mmio_axi4_adapter_master_xactor_crg_wr_addr_full$port2__read && !mmio_axi4_adapter_master_xactor_crg_wr_data_full$port2__read : mmio_axi4_adapter_f_rsps_to_core$FULL_N ; - assign IF_propDstData_0_dummy2_1_read__096_THEN_IF_pr_ETC___d1112 = + assign IF_propDstData_0_dummy2_1_read__092_THEN_IF_pr_ETC___d1108 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[8:7] : propDstData_0_rl[8:7]) : 2'd0 ; - assign IF_propDstData_0_dummy2_1_read__096_THEN_IF_pr_ETC___d1122 = + assign IF_propDstData_0_dummy2_1_read__092_THEN_IF_pr_ETC___d1118 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[6:5] : propDstData_0_rl[6:5]) : 2'd0 ; - assign IF_propDstData_1_0_lat_0_whas__189_THEN_propDs_ETC___d1194 = + assign IF_propDstData_1_0_lat_0_whas__185_THEN_propDs_ETC___d1190 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[579:516] : propDstData_1_0_rl[579:516] ; - assign IF_propDstData_1_0_lat_0_whas__189_THEN_propDs_ETC___d1199 = + assign IF_propDstData_1_0_lat_0_whas__185_THEN_propDs_ETC___d1195 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[515:514] : propDstData_1_0_rl[515:514] ; - assign IF_propDstData_1_0_lat_0_whas__189_THEN_propDs_ETC___d1220 = + assign IF_propDstData_1_0_lat_0_whas__185_THEN_propDs_ETC___d1216 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[0] : propDstData_1_0_rl[0] ; - assign IF_propDstData_1_1_lat_0_whas__227_THEN_propDs_ETC___d1232 = + assign IF_propDstData_1_1_lat_0_whas__223_THEN_propDs_ETC___d1228 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[579:516] : propDstData_1_1_rl[579:516] ; - assign IF_propDstData_1_1_lat_0_whas__227_THEN_propDs_ETC___d1237 = + assign IF_propDstData_1_1_lat_0_whas__223_THEN_propDs_ETC___d1233 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[515:514] : propDstData_1_1_rl[515:514] ; - assign IF_propDstData_1_1_lat_0_whas__227_THEN_propDs_ETC___d1258 = + assign IF_propDstData_1_1_lat_0_whas__223_THEN_propDs_ETC___d1254 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[0] : propDstData_1_1_rl[0] ; - assign IF_propDstData_1_dummy2_1_read__101_THEN_IF_pr_ETC___d1116 = + assign IF_propDstData_1_dummy2_1_read__097_THEN_IF_pr_ETC___d1112 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[8:7] : propDstData_1_rl[8:7]) : 2'd0 ; - assign IF_propDstData_1_dummy2_1_read__101_THEN_IF_pr_ETC___d1126 = + assign IF_propDstData_1_dummy2_1_read__097_THEN_IF_pr_ETC___d1122 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[6:5] : propDstData_1_rl[6:5]) : 2'd0 ; - assign IF_propDstIdx_0_lat_0_whas__005_THEN_propDstId_ETC___d1008 = + assign IF_propDstIdx_0_lat_0_whas__001_THEN_propDstId_ETC___d1004 = CAN_FIRE_RL_srcPropose || propDstIdx_0_rl ; - assign IF_propDstIdx_1_0_lat_0_whas__174_THEN_propDst_ETC___d1177 = + assign IF_propDstIdx_1_0_lat_0_whas__170_THEN_propDst_ETC___d1173 = CAN_FIRE_RL_srcPropose_2 || propDstIdx_1_0_rl ; - assign IF_propDstIdx_1_1_lat_0_whas__181_THEN_propDst_ETC___d1184 = + assign IF_propDstIdx_1_1_lat_0_whas__177_THEN_propDst_ETC___d1180 = CAN_FIRE_RL_srcPropose_3 || propDstIdx_1_1_rl ; - assign IF_propDstIdx_1_lat_0_whas__012_THEN_propDstId_ETC___d1015 = + assign IF_propDstIdx_1_lat_0_whas__008_THEN_propDstId_ETC___d1011 = CAN_FIRE_RL_srcPropose_1 || propDstIdx_1_rl ; - assign NOT_enqDst_0_dummy2_0_read__079_080_OR_NOT_enq_ETC___d1095 = + assign NOT_enqDst_0_dummy2_0_read__075_076_OR_NOT_enq_ETC___d1091 = (!enqDst_0_dummy2_0$Q_OUT || !enqDst_0_dummy2_1$Q_OUT || !enqDst_0_rl[73]) && - (SEL_ARR_propDstIdx_0_dummy2_1_read__058_AND_IF_ETC___d1089 || - IF_NOT_propDstIdx_0_dummy2_1_read__058_059_OR__ETC___d1093) ; - assign NOT_enqDst_1_0_dummy2_0_read__348_349_OR_NOT_e_ETC___d1364 = + (SEL_ARR_propDstIdx_0_dummy2_1_read__054_AND_IF_ETC___d1085 || + IF_NOT_propDstIdx_0_dummy2_1_read__054_055_OR__ETC___d1089) ; + assign NOT_enqDst_1_0_dummy2_0_read__344_345_OR_NOT_e_ETC___d1360 = (!enqDst_1_0_dummy2_0$Q_OUT || !enqDst_1_0_dummy2_1$Q_OUT || !enqDst_1_0_rl[580]) && - (SEL_ARR_propDstIdx_1_0_dummy2_1_read__317_AND__ETC___d1358 || - IF_NOT_propDstIdx_1_0_dummy2_1_read__317_318_O_ETC___d1362) ; - assign NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780 = + (SEL_ARR_propDstIdx_1_0_dummy2_1_read__313_AND__ETC___d1354 || + IF_NOT_propDstIdx_1_0_dummy2_1_read__313_314_O_ETC___d1358) ; + assign NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776 = llc_axi4_adapter_cfg_verbosity > 4'd1 ; - assign NOT_llc_mem_server_enqDst_0_dummy2_0_read__693_ETC___d1700 = + assign NOT_llc_mem_server_enqDst_0_dummy2_0_read__689_ETC___d1696 = (!llc_mem_server_enqDst_0_dummy2_0$Q_OUT || !llc_mem_server_enqDst_0_dummy2_1$Q_OUT || !llc_mem_server_enqDst_0_rl[65]) && llc_mem_server_propDstIdx_0_dummy2_1$Q_OUT && - IF_llc_mem_server_propDstIdx_0_lat_0_whas__647_ETC___d1650 ; - assign NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d746 = + IF_llc_mem_server_propDstIdx_0_lat_0_whas__643_ETC___d1646 ; + assign NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d742 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -6277,7 +6274,7 @@ module mkProc(CLK, mmioPlatform_state == 2'd2 && (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqFunc[5:4] == 2'd2) ; - assign NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d754 = + assign NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d750 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -6288,7 +6285,7 @@ module mkProc(CLK, mmioPlatform_state == 2'd3 && (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqFunc[5:4] == 2'd2) ; - assign NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d759 = + assign NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d755 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -6300,7 +6297,7 @@ module mkProc(CLK, mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2 ; - assign NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d769 = + assign NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d765 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -6312,7 +6309,7 @@ module mkProc(CLK, mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2 ; - assign NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d960 = + assign NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d956 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -6322,7 +6319,7 @@ module mkProc(CLK, mmioPlatform_curReq[66:64] != 3'd6 && mmioPlatform_state == 2'd2 && mmioPlatform_reqFunc[5:4] == 2'd0 ; - assign NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d973 = + assign NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d969 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -6342,35 +6339,29 @@ module mkProc(CLK, (mmioPlatform_fromHostQ_deqReq_lat_0$whas || mmioPlatform_fromHostQ_deqReq_rl) || mmioPlatform_fromHostQ_empty) ; - assign NOT_mmioPlatform_mtip_0_55_64_AND_mmioPlatform_ETC___d374 = + assign NOT_mmioPlatform_mtip_0_55_62_AND_mmioPlatform_ETC___d370 = !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 && - mmioPlatform_mtimecmp_0 != 64'd0 || + mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 || !core_0$mmioToPlatform_cRq_notEmpty || core_0$RDY_mmioToPlatform_cRq_first && core_0$RDY_mmioToPlatform_cRq_deq ; - assign NOT_mmioPlatform_mtip_0_55_64_AND_mmioPlatform_ETC___d379 = - !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 && - mmioPlatform_mtimecmp_0 != 64'd0 || - core_0$mmioToPlatform_cRq_notEmpty ; - assign NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d490 = + assign NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d486 = mmioPlatform_reqFunc[5:4] != 2'd0 && !mmioPlatform_reqBE[4] && (mmioPlatform_reqBE[0] || mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqFunc[5:4] == 2'd2) ; - assign NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d585 = + assign NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d581 = mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && - (IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 && + (IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && !mmioPlatform_mtip_0 || - !IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 && + !IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && mmioPlatform_mtip_0) ; - assign NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d648 = + assign NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d644 = mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && - (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && + (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && + !mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && mmioPlatform_mtip_0) ; assign NOT_mmioPlatform_toHostQ_clearReq_dummy2_1_rea_ETC___d240 = !mmioPlatform_toHostQ_clearReq_dummy2_1$Q_OUT || @@ -6384,51 +6375,51 @@ module mkProc(CLK, (!mmioPlatform_toHostQ_empty || mmioPlatform_toHostQ_deqReq_rl) || mmioPlatform_toHostQ_empty) ; - assign NOT_propDstData_1_0_dummy2_1_read__365_376_OR__ETC___d1377 = + assign NOT_propDstData_1_0_dummy2_1_read__361_372_OR__ETC___d1373 = !propDstData_1_0_dummy2_1$Q_OUT || (CAN_FIRE_RL_srcPropose_2 ? !propDstData_1_0_lat_0$wget[513] : !propDstData_1_0_rl[513]) ; - assign NOT_propDstData_1_1_dummy2_1_read__367_378_OR__ETC___d1379 = + assign NOT_propDstData_1_1_dummy2_1_read__363_374_OR__ETC___d1375 = !propDstData_1_1_dummy2_1$Q_OUT || (CAN_FIRE_RL_srcPropose_3 ? !propDstData_1_1_lat_0$wget[513] : !propDstData_1_1_rl[513]) ; - assign NOT_propDstIdx_0_dummy2_1_read__058_059_OR_IF__ETC___d1092 = + assign NOT_propDstIdx_0_dummy2_1_read__054_055_OR_IF__ETC___d1088 = !propDstIdx_0_dummy2_1$Q_OUT || !CAN_FIRE_RL_srcPropose && !propDstIdx_0_rl ; - assign NOT_propDstIdx_1_0_dummy2_1_read__317_318_OR_I_ETC___d1361 = + assign NOT_propDstIdx_1_0_dummy2_1_read__313_314_OR_I_ETC___d1357 = !propDstIdx_1_0_dummy2_1$Q_OUT || !CAN_FIRE_RL_srcPropose_2 && !propDstIdx_1_0_rl ; - assign SEL_ARR_IF_propDstData_0_dummy2_1_read__096_TH_ETC___d1160 = - { CASE_x1277_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21, - CASE_x1277_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22, - SEL_ARR_propDstData_0_dummy2_1_read__096_AND_I_ETC___d1159 } ; - assign SEL_ARR_IF_propDstData_1_0_dummy2_1_read__365__ETC___d1457 = - { CASE_x9900_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32, - !CASE_x9900_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__189_THE_ETC___d1450, - x__h82316 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__189_THE_ETC___d1399 = - { CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24, - CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__189_THE_ETC___d1416 = - { SEL_ARR_IF_propDstData_1_0_lat_0_whas__189_THE_ETC___d1399, - CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26, - CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__189_THE_ETC___d1433 = - { SEL_ARR_IF_propDstData_1_0_lat_0_whas__189_THE_ETC___d1416, - CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28, - CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__189_THE_ETC___d1450 = - { SEL_ARR_IF_propDstData_1_0_lat_0_whas__189_THE_ETC___d1433, - CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30, - CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 } ; - assign SEL_ARR_propDstData_0_dummy2_1_read__096_AND_I_ETC___d1159 = - { CASE_x1277_0_propDstData_0_dummy2_1_read__096__ETC__q20, - x__h61591, - x__h61598 } ; - assign b__h133661 = + assign SEL_ARR_IF_propDstData_0_dummy2_1_read__092_TH_ETC___d1156 = + { CASE_x1261_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21, + CASE_x1261_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22, + SEL_ARR_propDstData_0_dummy2_1_read__092_AND_I_ETC___d1155 } ; + assign SEL_ARR_IF_propDstData_1_0_dummy2_1_read__361__ETC___d1453 = + { CASE_x9884_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32, + !CASE_x9884_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1446, + x__h82300 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1395 = + { CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24, + CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1412 = + { SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1395, + CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26, + CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1429 = + { SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1412, + CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28, + CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1446 = + { SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1429, + CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30, + CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 } ; + assign SEL_ARR_propDstData_0_dummy2_1_read__092_AND_I_ETC___d1155 = + { CASE_x1261_0_propDstData_0_dummy2_1_read__092__ETC__q20, + x__h61575, + x__h61582 } ; + assign b__h133645 = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ? llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 : llc_axi4_adapter_ctr_wr_rsps_pending_crg ; @@ -6436,23 +6427,23 @@ module mkProc(CLK, mmio_axi4_adapter_ctr_wr_rsps_pending_crg$EN_port0__write ? mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 : mmio_axi4_adapter_ctr_wr_rsps_pending_crg ; - assign data__h31966 = + assign data__h31950 = mmioPlatform_waitLowerMSIPCRs ? { 63'd0, core_0$mmioToPlatform_cRs_first } : - { v__h31759, 32'd0 } ; - assign failed_testnum__h162439 = + { v__h31743, 32'd0 } ; + assign failed_testnum__h162423 = { 1'd0, mmioPlatform_toHostQ_data_0[63:1] } ; - assign line_addr__h101862 = + assign line_addr__h101846 = { llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[92:35], 6'b0 } ; - assign line_addr__h101948 = + assign line_addr__h101932 = { llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[92:35], 6'b0 } ; - assign llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1594 = - line_addr__h101948 == llc_mem_server_rg_cacheline_cache_addr ; - assign llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1516 = - line_addr__h101862 == llc_mem_server_rg_cacheline_cache_addr ; - assign mask__h89485 = + assign llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1590 = + line_addr__h101932 == llc_mem_server_rg_cacheline_cache_addr ; + assign llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1512 = + line_addr__h101846 == llc_mem_server_rg_cacheline_cache_addr ; + assign mask__h89469 = { llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8] ? 8'hFF : 8'h0, @@ -6477,14 +6468,14 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[1] ? 8'hFF : 8'h0 } ; - assign mem_req_rd_addr_araddr__h133954 = - { llc$to_mem_toM_first[68:11], x__h133989 } ; - assign mem_req_wr_addr_awaddr__h147878 = - { llc$to_mem_toM_first[639:582], x__h147903 } ; + assign mem_req_rd_addr_araddr__h133938 = + { llc$to_mem_toM_first[68:11], x__h133973 } ; + assign mem_req_wr_addr_awaddr__h147862 = + { llc$to_mem_toM_first[639:582], x__h147887 } ; assign mmioPlatform_cycle_47_ULT_99___d348 = mmioPlatform_cycle < 7'd99 ; - assign mmioPlatform_fetchingWay_65_ULT_mmioPlatform_r_ETC___d975 = + assign mmioPlatform_fetchingWay_61_ULT_mmioPlatform_r_ETC___d971 = mmioPlatform_fetchingWay < mmioPlatform_reqFunc[0] ; - assign mmioPlatform_fromHostQ_data_0__h42667 = + assign mmioPlatform_fromHostQ_data_0__h42651 = mmioPlatform_fromHostQ_data_0 ; assign mmioPlatform_fromHostQ_enqReq_dummy2_2_read__1_ETC___d331 = mmioPlatform_fromHostQ_enqReq_dummy2_2$Q_OUT && @@ -6495,41 +6486,36 @@ module mkProc(CLK, mmioPlatform_fromHostQ_full ; assign mmioPlatform_mtime_BITS_31_TO_0__q12 = mmioPlatform_mtime[31:0] ; assign mmioPlatform_mtime_BITS_63_TO_32__q11 = mmioPlatform_mtime[63:32] ; - assign mmioPlatform_mtime__h37280 = mmioPlatform_mtime ; - assign mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 = - mmioPlatform_mtimecmp_0 <= newData__h34977 ; + assign mmioPlatform_mtime__h37264 = mmioPlatform_mtime ; + assign mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 = + mmioPlatform_mtimecmp_0 <= newData__h34961 ; assign mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 = mmioPlatform_mtimecmp_0 <= mmioPlatform_mtime ; assign mmioPlatform_mtimecmp_0_BITS_31_TO_0__q10 = mmioPlatform_mtimecmp_0[31:0] ; assign mmioPlatform_mtimecmp_0_BITS_63_TO_32__q9 = mmioPlatform_mtimecmp_0[63:32] ; - assign mmioPlatform_mtip_0_55_OR_NOT_mmioPlatform_mti_ETC___d410 = - (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 || - mmioPlatform_mtimecmp_0 == 64'd0) && - core_0$mmioToPlatform_cRq_notEmpty ; - assign mmioPlatform_reqBE_BIT_0___h30174 = mmioPlatform_reqBE[0] ; - assign mmioPlatform_reqBE_BIT_4___h30134 = mmioPlatform_reqBE[4] ; - assign mmioPlatform_reqData__h48469 = mmioPlatform_reqData ; - assign mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d467 = + assign mmioPlatform_reqBE_BIT_0___h30158 = mmioPlatform_reqBE[0] ; + assign mmioPlatform_reqBE_BIT_4___h30118 = mmioPlatform_reqBE[4] ; + assign mmioPlatform_reqData__h48453 = mmioPlatform_reqData ; + assign mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d463 = mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqBE[4] || mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2 && !mmioPlatform_reqBE[0] ; - assign mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d571 = + assign mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d567 = mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqFunc[5:4] == 2'd1 || - (!IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 || + (!IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 || mmioPlatform_mtip_0) && - (IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 || + (IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 || !mmioPlatform_mtip_0) ; - assign mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d636 = + assign mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d632 = mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqFunc[5:4] == 2'd1 || - (!mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 || + (!mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 || mmioPlatform_mtip_0) && - (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 || + (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 || !mmioPlatform_mtip_0) ; assign mmioPlatform_toHostQ_enqReq_dummy2_2_read__41__ETC___d253 = mmioPlatform_toHostQ_enqReq_dummy2_2$Q_OUT && @@ -6543,235 +6529,235 @@ module mkProc(CLK, (mmio_axi4_adapter_soc_map$m_is_IO_addr ? !mmio_axi4_adapter_master_xactor_crg_rd_addr_full$port2__read : mmio_axi4_adapter_f_rsps_to_core$FULL_N) ; - assign n__read_addr__h61459 = + assign n__read_addr__h61443 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[72:9] : propDstData_0_rl[72:9]) : 64'd0 ; - assign n__read_addr__h61544 = + assign n__read_addr__h61528 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[72:9] : propDstData_1_rl[72:9]) : 64'd0 ; - assign n__read_addr__h80078 = + assign n__read_addr__h80062 = propDstData_1_0_dummy2_1$Q_OUT ? - IF_propDstData_1_0_lat_0_whas__189_THEN_propDs_ETC___d1194 : + IF_propDstData_1_0_lat_0_whas__185_THEN_propDs_ETC___d1190 : 64'd0 ; - assign n__read_addr__h80157 = + assign n__read_addr__h80141 = propDstData_1_1_dummy2_1$Q_OUT ? - IF_propDstData_1_1_lat_0_whas__227_THEN_propDs_ETC___d1232 : + IF_propDstData_1_1_lat_0_whas__223_THEN_propDs_ETC___d1228 : 64'd0 ; - assign n__read_child__h61464 = + assign n__read_child__h61448 = propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[0] : propDstData_0_rl[0]) ; - assign n__read_child__h61549 = + assign n__read_child__h61533 = propDstData_1_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[0] : propDstData_1_rl[0]) ; - assign n__read_child__h80081 = + assign n__read_child__h80065 = propDstData_1_0_dummy2_1$Q_OUT && - IF_propDstData_1_0_lat_0_whas__189_THEN_propDs_ETC___d1220 ; - assign n__read_child__h80160 = + IF_propDstData_1_0_lat_0_whas__185_THEN_propDs_ETC___d1216 ; + assign n__read_child__h80144 = propDstData_1_1_dummy2_1$Q_OUT && - IF_propDstData_1_1_lat_0_whas__227_THEN_propDs_ETC___d1258 ; - assign n__read_id__h61463 = + IF_propDstData_1_1_lat_0_whas__223_THEN_propDs_ETC___d1254 ; + assign n__read_id__h61447 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[3:1] : propDstData_0_rl[3:1]) : 3'd0 ; - assign n__read_id__h61548 = + assign n__read_id__h61532 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[3:1] : propDstData_1_rl[3:1]) : 3'd0 ; - assign n__read_snd_addr__h123389 = + assign n__read_snd_addr__h123373 = llc_mem_server_propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_llc_mem_server_srcPropose ? core_0$tlbToMem_memReq_first[64:1] : llc_mem_server_propDstData_0_rl[64:1]) : 64'd0 ; - assign n__read_snd_id__h123390 = + assign n__read_snd_id__h123374 = llc_mem_server_propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_llc_mem_server_srcPropose ? core_0$tlbToMem_memReq_first[0] : llc_mem_server_propDstData_0_rl[0]) ; - assign newData__h32047 = + assign newData__h32031 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h32158 : - IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d552 ; - assign newData__h34977 = + x__h32142 : + IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d548 ; + assign newData__h34961 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h35068 : - IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d614 ; - assign new_cline__h134656 = + x__h35052 : + IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d610 ; + assign new_cline__h134640 = { llc_axi4_adapter_master_xactor_rg_rd_data[66:3], llc_axi4_adapter_rg_cline[511:64] } ; - assign new_dword__h89489 = x__h90651 | y__h90652 ; - assign op_result__h48485 = - IF_mmioPlatform_reqSz_75_EQ_0b10_82_THEN_SEXT__ETC___d883 + - IF_mmioPlatform_reqSz_75_EQ_0b10_82_THEN_SEXT__ETC___d885 ; - assign op_result__h49015 = w1__h47882 ^ w2__h47884 ; - assign op_result__h49020 = w1__h47882 & w2__h47884 ; - assign op_result__h49025 = w1__h47882 | w2__h47884 ; - assign op_result__h49030 = - (w1__h47882 < w2__h47884) ? w1__h47882 : w2__h47884 ; - assign op_result__h49036 = - (w1__h47882 <= w2__h47884) ? w2__h47884 : w1__h47882 ; - assign op_result__h49043 = - ((IF_mmioPlatform_reqSz_75_EQ_0b10_82_THEN_SEXT__ETC___d883 ^ + assign new_dword__h89473 = x__h90635 | y__h90636 ; + assign op_result__h48469 = + IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d879 + + IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d881 ; + assign op_result__h48999 = w1__h47866 ^ w2__h47868 ; + assign op_result__h49004 = w1__h47866 & w2__h47868 ; + assign op_result__h49009 = w1__h47866 | w2__h47868 ; + assign op_result__h49014 = + (w1__h47866 < w2__h47868) ? w1__h47866 : w2__h47868 ; + assign op_result__h49020 = + (w1__h47866 <= w2__h47868) ? w2__h47868 : w1__h47866 ; + assign op_result__h49027 = + ((IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d879 ^ 64'h8000000000000000) < - (IF_mmioPlatform_reqSz_75_EQ_0b10_82_THEN_SEXT__ETC___d885 ^ + (IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d881 ^ 64'h8000000000000000)) ? - w1__h47882 : - w2__h47884 ; - assign op_result__h49049 = - ((IF_mmioPlatform_reqSz_75_EQ_0b10_82_THEN_SEXT__ETC___d883 ^ + w1__h47866 : + w2__h47868 ; + assign op_result__h49033 = + ((IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d879 ^ 64'h8000000000000000) <= - (IF_mmioPlatform_reqSz_75_EQ_0b10_82_THEN_SEXT__ETC___d885 ^ + (IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d881 ^ 64'h8000000000000000)) ? - w2__h47884 : - w1__h47882 ; - assign propDstData_0_dummy2_1_read__096_AND_IF_propDs_ETC___d1132 = + w2__h47868 : + w1__h47866 ; + assign propDstData_0_dummy2_1_read__092_AND_IF_propDs_ETC___d1128 = propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[4] : propDstData_0_rl[4]) ; - assign propDstData_1_dummy2_1_read__101_AND_IF_propDs_ETC___d1136 = + assign propDstData_1_dummy2_1_read__097_AND_IF_propDs_ETC___d1132 = propDstData_1_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[4] : propDstData_1_rl[4]) ; - assign result__h47928 = + assign result__h47912 = { mmioPlatform_reqData[63:8], - IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915[7:0] } ; - assign result__h48052 = { 56'd0, mmioPlatform_reqData[7:0] } ; - assign result__h48080 = { 56'd0, mmioPlatform_reqData[15:8] } ; - assign result__h48108 = { 56'd0, mmioPlatform_reqData[23:16] } ; - assign result__h48136 = { 56'd0, mmioPlatform_reqData[31:24] } ; - assign result__h48164 = { 56'd0, mmioPlatform_reqData[39:32] } ; - assign result__h48192 = { 56'd0, mmioPlatform_reqData[47:40] } ; - assign result__h48220 = { 56'd0, mmioPlatform_reqData[55:48] } ; - assign result__h48248 = { 56'd0, mmioPlatform_reqData[63:56] } ; - assign result__h48293 = { 48'd0, mmioPlatform_reqData[15:0] } ; - assign result__h48321 = { 48'd0, mmioPlatform_reqData[31:16] } ; - assign result__h48349 = { 48'd0, mmioPlatform_reqData[47:32] } ; - assign result__h48377 = { 48'd0, mmioPlatform_reqData[63:48] } ; - assign result__h48418 = { 32'd0, mmioPlatform_reqData[31:0] } ; - assign result__h48446 = { 32'd0, mmioPlatform_reqData[63:32] } ; - assign result__h48572 = + IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[7:0] } ; + assign result__h48036 = { 56'd0, mmioPlatform_reqData[7:0] } ; + assign result__h48064 = { 56'd0, mmioPlatform_reqData[15:8] } ; + assign result__h48092 = { 56'd0, mmioPlatform_reqData[23:16] } ; + assign result__h48120 = { 56'd0, mmioPlatform_reqData[31:24] } ; + assign result__h48148 = { 56'd0, mmioPlatform_reqData[39:32] } ; + assign result__h48176 = { 56'd0, mmioPlatform_reqData[47:40] } ; + assign result__h48204 = { 56'd0, mmioPlatform_reqData[55:48] } ; + assign result__h48232 = { 56'd0, mmioPlatform_reqData[63:56] } ; + assign result__h48277 = { 48'd0, mmioPlatform_reqData[15:0] } ; + assign result__h48305 = { 48'd0, mmioPlatform_reqData[31:16] } ; + assign result__h48333 = { 48'd0, mmioPlatform_reqData[47:32] } ; + assign result__h48361 = { 48'd0, mmioPlatform_reqData[63:48] } ; + assign result__h48402 = { 32'd0, mmioPlatform_reqData[31:0] } ; + assign result__h48430 = { 32'd0, mmioPlatform_reqData[63:32] } ; + assign result__h48556 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[7:0] } ; - assign result__h48599 = + assign result__h48583 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[15:8] } ; - assign result__h48626 = + assign result__h48610 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[23:16] } ; - assign result__h48653 = + assign result__h48637 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:24] } ; - assign result__h48680 = + assign result__h48664 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[39:32] } ; - assign result__h48707 = + assign result__h48691 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[47:40] } ; - assign result__h48734 = + assign result__h48718 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[55:48] } ; - assign result__h48761 = + assign result__h48745 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:56] } ; - assign result__h48805 = + assign result__h48789 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[15:0] } ; - assign result__h48832 = + assign result__h48816 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:16] } ; - assign result__h48859 = + assign result__h48843 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[47:32] } ; - assign result__h48886 = + assign result__h48870 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:48] } ; - assign result__h48926 = + assign result__h48910 = { 32'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:0] } ; - assign result__h48953 = + assign result__h48937 = { 32'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:32] } ; - assign result__h49070 = + assign result__h49054 = { mmioPlatform_reqData[63:16], - IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915[7:0], + IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[7:0], mmioPlatform_reqData[7:0] } ; - assign result__h49136 = + assign result__h49120 = { mmioPlatform_reqData[63:24], - IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915[7:0], + IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[7:0], mmioPlatform_reqData[15:0] } ; - assign result__h49202 = + assign result__h49186 = { mmioPlatform_reqData[63:32], - IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915[7:0], + IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[7:0], mmioPlatform_reqData[23:0] } ; - assign result__h49268 = + assign result__h49252 = { mmioPlatform_reqData[63:40], - IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915[7:0], + IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[7:0], mmioPlatform_reqData[31:0] } ; - assign result__h49334 = + assign result__h49318 = { mmioPlatform_reqData[63:48], - IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915[7:0], + IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[7:0], mmioPlatform_reqData[39:0] } ; - assign result__h49400 = + assign result__h49384 = { mmioPlatform_reqData[63:56], - IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915[7:0], + IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[7:0], mmioPlatform_reqData[47:0] } ; - assign result__h49466 = - { IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915[7:0], + assign result__h49450 = + { IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[7:0], mmioPlatform_reqData[55:0] } ; - assign result__h49528 = + assign result__h49512 = { mmioPlatform_reqData[63:16], - IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915[15:0] } ; - assign result__h49573 = + IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[15:0] } ; + assign result__h49557 = { mmioPlatform_reqData[63:32], - IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915[15:0], + IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[15:0], mmioPlatform_reqData[15:0] } ; - assign result__h49639 = + assign result__h49623 = { mmioPlatform_reqData[63:48], - IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915[15:0], + IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[15:0], mmioPlatform_reqData[31:0] } ; - assign result__h49705 = - { IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915[15:0], + assign result__h49689 = + { IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[15:0], mmioPlatform_reqData[47:0] } ; - assign result__h49763 = + assign result__h49747 = { mmioPlatform_reqData[63:32], - IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915[31:0] } ; - assign result__h49808 = - { IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915[31:0], + IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[31:0] } ; + assign result__h49792 = + { IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[31:0], mmioPlatform_reqData[31:0] } ; - assign v__h31759 = mmioPlatform_waitUpperMSIPCRs ? v__h31796 : 32'd0 ; - assign v__h31796 = { 31'd0, core_0$mmioToPlatform_cRs_first } ; - assign w17877_BITS_31_TO_0__q15 = w1__h47877[31:0] ; - assign w1___1__h47987 = { 32'd0, w1__h47877[31:0] } ; - assign w27878_BITS_31_TO_0__q16 = w2__h47878[31:0] ; - assign w2___1__h47988 = { 32'd0, w2__h47878[31:0] } ; - assign x1_avValue_data__h40339 = + assign v__h31743 = mmioPlatform_waitUpperMSIPCRs ? v__h31780 : 32'd0 ; + assign v__h31780 = { 31'd0, core_0$mmioToPlatform_cRs_first } ; + assign w17861_BITS_31_TO_0__q15 = w1__h47861[31:0] ; + assign w1___1__h47971 = { 32'd0, w1__h47861[31:0] } ; + assign w27862_BITS_31_TO_0__q16 = w2__h47862[31:0] ; + assign w2___1__h47972 = { 32'd0, w2__h47862[31:0] } ; + assign x1_avValue_data__h40323 = mmioPlatform_toHostQ_empty ? 64'd0 : mmioPlatform_toHostQ_data_0 ; - assign x1_avValue_data__h44806 = + assign x1_avValue_data__h44790 = mmioPlatform_fromHostQ_empty ? 64'd0 : mmioPlatform_fromHostQ_data_0 ; - assign x__h133989 = { llc_axi4_adapter_rg_rd_req_beat, 3'b0 } ; - assign x__h147903 = { llc_axi4_adapter_rg_wr_req_beat, 3'b0 } ; - assign x__h37428 = mmioPlatform_mtimecmp_0 ; - assign x__h40857 = + assign x__h133973 = { llc_axi4_adapter_rg_rd_req_beat, 3'b0 } ; + assign x__h147887 = { llc_axi4_adapter_rg_wr_req_beat, 3'b0 } ; + assign x__h37412 = mmioPlatform_mtimecmp_0 ; + assign x__h40841 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h40868 : - IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d715 ; - assign x__h42877 = + x__h40852 : + IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d711 ; + assign x__h42861 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h42888 : + x__h42872 : { mmioPlatform_reqBE[7] ? mmioPlatform_reqData[63:56] : 8'd0, mmioPlatform_reqBE[6] ? mmioPlatform_reqData[55:48] : 8'd0, mmioPlatform_reqBE[5] ? mmioPlatform_reqData[47:40] : 8'd0, @@ -6780,29 +6766,29 @@ module mkProc(CLK, mmioPlatform_reqBE[2] ? mmioPlatform_reqData[23:16] : 8'd0, mmioPlatform_reqBE[1] ? mmioPlatform_reqData[15:8] : 8'd0, mmioPlatform_reqBE[0] ? mmioPlatform_reqData[7:0] : 8'd0 } ; - assign x__h49985 = { mmioPlatform_curReq[63:3], 3'b0 } ; - assign x__h61277 = - SEL_ARR_propDstIdx_0_dummy2_1_read__058_AND_IF_ETC___d1089 ? + assign x__h49969 = { mmioPlatform_curReq[63:3], 3'b0 } ; + assign x__h61261 = + SEL_ARR_propDstIdx_0_dummy2_1_read__054_AND_IF_ETC___d1085 ? srcRR_0 : - NOT_propDstIdx_0_dummy2_1_read__058_059_OR_IF__ETC___d1092 ; - assign x__h74829 = + NOT_propDstIdx_0_dummy2_1_read__054_055_OR_IF__ETC___d1088 ; + assign x__h74813 = !CAN_FIRE_RL_doEnq_1 && - IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1306 ; + IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1302 ; assign x__h7925 = (mmio_axi4_adapter_f_reqs_from_core$D_OUT[71:68] == 4'd0 || mmio_axi4_adapter_f_reqs_from_core$D_OUT[67:64] == 4'd0) ? 3'b010 : 3'b011 ; - assign x__h79900 = - SEL_ARR_propDstIdx_1_0_dummy2_1_read__317_AND__ETC___d1358 ? + assign x__h79884 = + SEL_ARR_propDstIdx_1_0_dummy2_1_read__313_AND__ETC___d1354 ? srcRR_1_0 : - NOT_propDstIdx_1_0_dummy2_1_read__317_318_OR_I_ETC___d1361 ; - assign x__h90651 = old_dword__h89488 & y__h90653 ; - assign x_data__h30549 = { 31'd0, mmioPlatform_reqData[0] } ; - assign y__h90652 = + NOT_propDstIdx_1_0_dummy2_1_read__313_314_OR_I_ETC___d1357 ; + assign x__h90635 = old_dword__h89472 & y__h90637 ; + assign x_data__h30533 = { 31'd0, mmioPlatform_reqData[0] } ; + assign y__h90636 = llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[72:9] & - mask__h89485 ; - assign y__h90653 = + mask__h89469 ; + assign y__h90637 = { llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8] ? 8'd0 : 8'd255, @@ -7015,473 +7001,473 @@ module mkProc(CLK, llc_mem_server_rg_cacheline_cache_data) begin case (llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[34:32]) - 3'd0: dword__h93798 = llc_mem_server_rg_cacheline_cache_data[63:0]; - 3'd1: dword__h93798 = llc_mem_server_rg_cacheline_cache_data[127:64]; - 3'd2: dword__h93798 = llc_mem_server_rg_cacheline_cache_data[191:128]; - 3'd3: dword__h93798 = llc_mem_server_rg_cacheline_cache_data[255:192]; - 3'd4: dword__h93798 = llc_mem_server_rg_cacheline_cache_data[319:256]; - 3'd5: dword__h93798 = llc_mem_server_rg_cacheline_cache_data[383:320]; - 3'd6: dword__h93798 = llc_mem_server_rg_cacheline_cache_data[447:384]; - 3'd7: dword__h93798 = llc_mem_server_rg_cacheline_cache_data[511:448]; + 3'd0: dword__h93782 = llc_mem_server_rg_cacheline_cache_data[63:0]; + 3'd1: dword__h93782 = llc_mem_server_rg_cacheline_cache_data[127:64]; + 3'd2: dword__h93782 = llc_mem_server_rg_cacheline_cache_data[191:128]; + 3'd3: dword__h93782 = llc_mem_server_rg_cacheline_cache_data[255:192]; + 3'd4: dword__h93782 = llc_mem_server_rg_cacheline_cache_data[319:256]; + 3'd5: dword__h93782 = llc_mem_server_rg_cacheline_cache_data[383:320]; + 3'd6: dword__h93782 = llc_mem_server_rg_cacheline_cache_data[447:384]; + 3'd7: dword__h93782 = llc_mem_server_rg_cacheline_cache_data[511:448]; endcase end always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) begin case (llc_axi4_adapter_rg_wr_req_beat) - 3'd0: data64__h147793 = llc$to_mem_toM_first[63:0]; - 3'd1: data64__h147793 = llc$to_mem_toM_first[127:64]; - 3'd2: data64__h147793 = llc$to_mem_toM_first[191:128]; - 3'd3: data64__h147793 = llc$to_mem_toM_first[255:192]; - 3'd4: data64__h147793 = llc$to_mem_toM_first[319:256]; - 3'd5: data64__h147793 = llc$to_mem_toM_first[383:320]; - 3'd6: data64__h147793 = llc$to_mem_toM_first[447:384]; - 3'd7: data64__h147793 = llc$to_mem_toM_first[511:448]; + 3'd0: data64__h147777 = llc$to_mem_toM_first[63:0]; + 3'd1: data64__h147777 = llc$to_mem_toM_first[127:64]; + 3'd2: data64__h147777 = llc$to_mem_toM_first[191:128]; + 3'd3: data64__h147777 = llc$to_mem_toM_first[255:192]; + 3'd4: data64__h147777 = llc$to_mem_toM_first[319:256]; + 3'd5: data64__h147777 = llc$to_mem_toM_first[383:320]; + 3'd6: data64__h147777 = llc$to_mem_toM_first[447:384]; + 3'd7: data64__h147777 = llc$to_mem_toM_first[511:448]; endcase end always@(llc$dma_respLd_first) begin case (llc$dma_respLd_first[2:0]) - 3'd0: ld_data__h131955 = llc$dma_respLd_first[68:5]; - 3'd1: ld_data__h131955 = llc$dma_respLd_first[132:69]; - 3'd2: ld_data__h131955 = llc$dma_respLd_first[196:133]; - 3'd3: ld_data__h131955 = llc$dma_respLd_first[260:197]; - 3'd4: ld_data__h131955 = llc$dma_respLd_first[324:261]; - 3'd5: ld_data__h131955 = llc$dma_respLd_first[388:325]; - 3'd6: ld_data__h131955 = llc$dma_respLd_first[452:389]; - 3'd7: ld_data__h131955 = llc$dma_respLd_first[516:453]; + 3'd0: ld_data__h131939 = llc$dma_respLd_first[68:5]; + 3'd1: ld_data__h131939 = llc$dma_respLd_first[132:69]; + 3'd2: ld_data__h131939 = llc$dma_respLd_first[196:133]; + 3'd3: ld_data__h131939 = llc$dma_respLd_first[260:197]; + 3'd4: ld_data__h131939 = llc$dma_respLd_first[324:261]; + 3'd5: ld_data__h131939 = llc$dma_respLd_first[388:325]; + 3'd6: ld_data__h131939 = llc$dma_respLd_first[452:389]; + 3'd7: ld_data__h131939 = llc$dma_respLd_first[516:453]; endcase end always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) begin case (llc_axi4_adapter_rg_wr_req_beat) - 3'd0: strb8__h147794 = llc$to_mem_toM_first[519:512]; - 3'd1: strb8__h147794 = llc$to_mem_toM_first[527:520]; - 3'd2: strb8__h147794 = llc$to_mem_toM_first[535:528]; - 3'd3: strb8__h147794 = llc$to_mem_toM_first[543:536]; - 3'd4: strb8__h147794 = llc$to_mem_toM_first[551:544]; - 3'd5: strb8__h147794 = llc$to_mem_toM_first[559:552]; - 3'd6: strb8__h147794 = llc$to_mem_toM_first[567:560]; - 3'd7: strb8__h147794 = llc$to_mem_toM_first[575:568]; + 3'd0: strb8__h147778 = llc$to_mem_toM_first[519:512]; + 3'd1: strb8__h147778 = llc$to_mem_toM_first[527:520]; + 3'd2: strb8__h147778 = llc$to_mem_toM_first[535:528]; + 3'd3: strb8__h147778 = llc$to_mem_toM_first[543:536]; + 3'd4: strb8__h147778 = llc$to_mem_toM_first[551:544]; + 3'd5: strb8__h147778 = llc$to_mem_toM_first[559:552]; + 3'd6: strb8__h147778 = llc$to_mem_toM_first[567:560]; + 3'd7: strb8__h147778 = llc$to_mem_toM_first[575:568]; endcase end always@(llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT or llc_mem_server_rg_cacheline_cache_data) begin case (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32]) - 3'd0: old_dword__h89488 = llc_mem_server_rg_cacheline_cache_data[63:0]; + 3'd0: old_dword__h89472 = llc_mem_server_rg_cacheline_cache_data[63:0]; 3'd1: - old_dword__h89488 = llc_mem_server_rg_cacheline_cache_data[127:64]; + old_dword__h89472 = llc_mem_server_rg_cacheline_cache_data[127:64]; 3'd2: - old_dword__h89488 = llc_mem_server_rg_cacheline_cache_data[191:128]; + old_dword__h89472 = llc_mem_server_rg_cacheline_cache_data[191:128]; 3'd3: - old_dword__h89488 = llc_mem_server_rg_cacheline_cache_data[255:192]; + old_dword__h89472 = llc_mem_server_rg_cacheline_cache_data[255:192]; 3'd4: - old_dword__h89488 = llc_mem_server_rg_cacheline_cache_data[319:256]; + old_dword__h89472 = llc_mem_server_rg_cacheline_cache_data[319:256]; 3'd5: - old_dword__h89488 = llc_mem_server_rg_cacheline_cache_data[383:320]; + old_dword__h89472 = llc_mem_server_rg_cacheline_cache_data[383:320]; 3'd6: - old_dword__h89488 = llc_mem_server_rg_cacheline_cache_data[447:384]; + old_dword__h89472 = llc_mem_server_rg_cacheline_cache_data[447:384]; 3'd7: - old_dword__h89488 = llc_mem_server_rg_cacheline_cache_data[511:448]; + old_dword__h89472 = llc_mem_server_rg_cacheline_cache_data[511:448]; endcase end always@(mmioPlatform_curReq or - result__h48052 or - result__h48080 or - result__h48108 or - result__h48136 or - result__h48164 or - result__h48192 or result__h48220 or result__h48248) + result__h48036 or + result__h48064 or + result__h48092 or + result__h48120 or + result__h48148 or + result__h48176 or result__h48204 or result__h48232) begin case (mmioPlatform_curReq[2:0]) 3'h0: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d805 = - result__h48052; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 = + result__h48036; 3'h1: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d805 = - result__h48080; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 = + result__h48064; 3'h2: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d805 = - result__h48108; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 = + result__h48092; 3'h3: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d805 = - result__h48136; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 = + result__h48120; 3'h4: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d805 = - result__h48164; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 = + result__h48148; 3'h5: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d805 = - result__h48192; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 = + result__h48176; 3'h6: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d805 = - result__h48220; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 = + result__h48204; 3'h7: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d805 = - result__h48248; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 = + result__h48232; endcase end always@(mmioPlatform_curReq or - result__h48293 or - result__h48321 or result__h48349 or result__h48377) + result__h48277 or + result__h48305 or result__h48333 or result__h48361) begin case (mmioPlatform_curReq[2:0]) 3'h0: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d818 = - result__h48293; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814 = + result__h48277; 3'h2: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d818 = - result__h48321; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814 = + result__h48305; 3'h4: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d818 = - result__h48349; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814 = + result__h48333; 3'h6: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d818 = - result__h48377; - default: IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d818 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814 = + result__h48361; + default: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814 = 64'd0; endcase end - always@(mmioPlatform_curReq or result__h48418 or result__h48446) + always@(mmioPlatform_curReq or result__h48402 or result__h48430) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13 = - result__h48418; + result__h48402; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13 = - result__h48446; + result__h48430; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13 = 64'd0; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d805 or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d818 or + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 or + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814 or CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13 or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d825) + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d821) begin case (mmioPlatform_reqSz) 2'b0: - w2__h47878 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d805; + w2__h47862 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801; 2'b01: - w2__h47878 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d818; + w2__h47862 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814; 2'b10: - w2__h47878 = + w2__h47862 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13; 2'b11: - w2__h47878 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d825; + w2__h47862 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d821; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d805 or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d818 or - w2___1__h47988 or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d825) + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 or + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814 or + w2___1__h47972 or + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d821) begin case (mmioPlatform_reqSz) 2'b0: - w2__h47884 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d805; + w2__h47868 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801; 2'b01: - w2__h47884 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d818; - 2'b10: w2__h47884 = w2___1__h47988; + w2__h47868 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814; + 2'b10: w2__h47868 = w2___1__h47972; 2'b11: - w2__h47884 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d825; + w2__h47868 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d821; endcase end always@(mmioPlatform_curReq or - result__h48572 or - result__h48599 or - result__h48626 or - result__h48653 or - result__h48680 or - result__h48707 or result__h48734 or result__h48761) + result__h48556 or + result__h48583 or + result__h48610 or + result__h48637 or + result__h48664 or + result__h48691 or result__h48718 or result__h48745) begin case (mmioPlatform_curReq[2:0]) 3'h0: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d857 = - result__h48572; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 = + result__h48556; 3'h1: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d857 = - result__h48599; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 = + result__h48583; 3'h2: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d857 = - result__h48626; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 = + result__h48610; 3'h3: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d857 = - result__h48653; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 = + result__h48637; 3'h4: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d857 = - result__h48680; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 = + result__h48664; 3'h5: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d857 = - result__h48707; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 = + result__h48691; 3'h6: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d857 = - result__h48734; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 = + result__h48718; 3'h7: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d857 = - result__h48761; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 = + result__h48745; endcase end always@(mmioPlatform_curReq or - result__h48805 or - result__h48832 or result__h48859 or result__h48886) + result__h48789 or + result__h48816 or result__h48843 or result__h48870) begin case (mmioPlatform_curReq[2:0]) 3'h0: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d869 = - result__h48805; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865 = + result__h48789; 3'h2: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d869 = - result__h48832; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865 = + result__h48816; 3'h4: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d869 = - result__h48859; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865 = + result__h48843; 3'h6: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d869 = - result__h48886; - default: IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d869 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865 = + result__h48870; + default: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865 = 64'd0; endcase end - always@(mmioPlatform_curReq or result__h48926 or result__h48953) + always@(mmioPlatform_curReq or result__h48910 or result__h48937) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14 = - result__h48926; + result__h48910; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14 = - result__h48953; + result__h48937; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14 = 64'd0; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d857 or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d869 or + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 or + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865 or CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14 or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d876) + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d872) begin case (mmioPlatform_reqSz) 2'b0: - w1__h47877 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d857; + w1__h47861 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853; 2'b01: - w1__h47877 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d869; + w1__h47861 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865; 2'b10: - w1__h47877 = + w1__h47861 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14; 2'b11: - w1__h47877 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d876; + w1__h47861 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d872; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d857 or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d869 or - w1___1__h47987 or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d876) + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 or + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865 or + w1___1__h47971 or + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d872) begin case (mmioPlatform_reqSz) 2'b0: - w1__h47882 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d857; + w1__h47866 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853; 2'b01: - w1__h47882 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d869; - 2'b10: w1__h47882 = w1___1__h47987; + w1__h47866 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865; + 2'b10: w1__h47866 = w1___1__h47971; 2'b11: - w1__h47882 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d876; + w1__h47866 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d872; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d857 or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d869 or - w17877_BITS_31_TO_0__q15 or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d876) + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 or + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865 or + w17861_BITS_31_TO_0__q15 or + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d872) begin case (mmioPlatform_reqSz) 2'b0: - IF_mmioPlatform_reqSz_75_EQ_0b10_82_THEN_SEXT__ETC___d883 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d857; + IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d879 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853; 2'b01: - IF_mmioPlatform_reqSz_75_EQ_0b10_82_THEN_SEXT__ETC___d883 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d869; + IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d879 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865; 2'b10: - IF_mmioPlatform_reqSz_75_EQ_0b10_82_THEN_SEXT__ETC___d883 = - { {32{w17877_BITS_31_TO_0__q15[31]}}, - w17877_BITS_31_TO_0__q15 }; + IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d879 = + { {32{w17861_BITS_31_TO_0__q15[31]}}, + w17861_BITS_31_TO_0__q15 }; 2'b11: - IF_mmioPlatform_reqSz_75_EQ_0b10_82_THEN_SEXT__ETC___d883 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d876; + IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d879 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d872; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d805 or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d818 or - w27878_BITS_31_TO_0__q16 or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d825) + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 or + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814 or + w27862_BITS_31_TO_0__q16 or + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d821) begin case (mmioPlatform_reqSz) 2'b0: - IF_mmioPlatform_reqSz_75_EQ_0b10_82_THEN_SEXT__ETC___d885 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d805; + IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d881 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801; 2'b01: - IF_mmioPlatform_reqSz_75_EQ_0b10_82_THEN_SEXT__ETC___d885 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d818; + IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d881 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814; 2'b10: - IF_mmioPlatform_reqSz_75_EQ_0b10_82_THEN_SEXT__ETC___d885 = - { {32{w27878_BITS_31_TO_0__q16[31]}}, - w27878_BITS_31_TO_0__q16 }; + IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d881 = + { {32{w27862_BITS_31_TO_0__q16[31]}}, + w27862_BITS_31_TO_0__q16 }; 2'b11: - IF_mmioPlatform_reqSz_75_EQ_0b10_82_THEN_SEXT__ETC___d885 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d825; + IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d881 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d821; endcase end always@(mmioPlatform_reqAmofunc or - op_result__h49049 or - w2__h47884 or - op_result__h48485 or - op_result__h49015 or - op_result__h49020 or - op_result__h49025 or - op_result__h49043 or op_result__h49030 or op_result__h49036) + op_result__h49033 or + w2__h47868 or + op_result__h48469 or + op_result__h48999 or + op_result__h49004 or + op_result__h49009 or + op_result__h49027 or op_result__h49014 or op_result__h49020) begin case (mmioPlatform_reqAmofunc) 4'd0: - IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915 = - w2__h47884; + IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911 = + w2__h47868; 4'd1: - IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915 = - op_result__h48485; + IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911 = + op_result__h48469; 4'd2: - IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915 = - op_result__h49015; + IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911 = + op_result__h48999; 4'd3: - IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915 = - op_result__h49020; + IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911 = + op_result__h49004; 4'd4: - IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915 = - op_result__h49025; + IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911 = + op_result__h49009; 4'd5: - IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915 = - op_result__h49043; + IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911 = + op_result__h49027; 4'd7: - IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915 = - op_result__h49030; + IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911 = + op_result__h49014; 4'd8: - IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915 = - op_result__h49036; - default: IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915 = - op_result__h49049; + IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911 = + op_result__h49020; + default: IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911 = + op_result__h49033; endcase end always@(mmioPlatform_curReq or - result__h49528 or - result__h49573 or result__h49639 or result__h49705) + result__h49512 or + result__h49557 or result__h49623 or result__h49689) begin case (mmioPlatform_curReq[2:0]) 3'h0: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d948 = - result__h49528; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d944 = + result__h49512; 3'h2: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d948 = - result__h49573; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d944 = + result__h49557; 3'h4: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d948 = - result__h49639; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d944 = + result__h49623; 3'h6: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d948 = - result__h49705; - default: IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d948 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d944 = + result__h49689; + default: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d944 = 64'd0; endcase end always@(mmioPlatform_curReq or - result__h47928 or - result__h49070 or - result__h49136 or - result__h49202 or - result__h49268 or - result__h49334 or result__h49400 or result__h49466) + result__h47912 or + result__h49054 or + result__h49120 or + result__h49186 or + result__h49252 or + result__h49318 or result__h49384 or result__h49450) begin case (mmioPlatform_curReq[2:0]) 3'h0: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d939 = - result__h47928; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935 = + result__h47912; 3'h1: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d939 = - result__h49070; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935 = + result__h49054; 3'h2: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d939 = - result__h49136; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935 = + result__h49120; 3'h3: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d939 = - result__h49202; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935 = + result__h49186; 3'h4: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d939 = - result__h49268; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935 = + result__h49252; 3'h5: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d939 = - result__h49334; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935 = + result__h49318; 3'h6: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d939 = - result__h49400; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935 = + result__h49384; 3'h7: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d939 = - result__h49466; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935 = + result__h49450; endcase end - always@(mmioPlatform_curReq or result__h49763 or result__h49808) + always@(mmioPlatform_curReq or result__h49747 or result__h49792) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17 = - result__h49763; + result__h49747; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17 = - result__h49808; + result__h49792; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17 = 64'd0; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d939 or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d948 or + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935 or + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d944 or CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17 or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d825) + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d821) begin case (mmioPlatform_reqSz) 2'b0: - x__h47873 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d939; + x__h47857 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935; 2'b01: - x__h47873 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d948; + x__h47857 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d944; 2'b10: - x__h47873 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17; + x__h47857 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17; 2'b11: - x__h47873 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d825; + x__h47857 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d821; endcase end always@(mmioPlatform_reqFunc) begin case (mmioPlatform_reqFunc[5:4]) 2'd0, 2'd1, 2'd2: - IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_ETC___d481 = + IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d477 = mmioPlatform_reqFunc; 2'd3: - IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_ETC___d481 = + IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d477 = { 2'd3, mmioPlatform_reqFunc[3:0] }; endcase end @@ -7489,15 +7475,15 @@ module mkProc(CLK, begin case (mmioPlatform_instSel) 1'd0: - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d983 = + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d979 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:0]; 1'd1: - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d983 = + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d979 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:32]; endcase end always@(mmioPlatform_reqFunc or - IF_IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4__ETC___d559 or + IF_IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4__ETC___d555 or core_0$RDY_mmioToPlatform_pRs_enq) begin case (mmioPlatform_reqFunc[5:4]) @@ -7505,11 +7491,11 @@ module mkProc(CLK, CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q18 = core_0$RDY_mmioToPlatform_pRs_enq; default: CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q18 = - IF_IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4__ETC___d559; + IF_IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4__ETC___d555; endcase end always@(mmioPlatform_reqFunc or - IF_mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioP_ETC___d625 or + IF_mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioP_ETC___d621 or core_0$RDY_mmioToPlatform_pRs_enq) begin case (mmioPlatform_reqFunc[5:4]) @@ -7517,315 +7503,315 @@ module mkProc(CLK, CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q19 = core_0$RDY_mmioToPlatform_pRs_enq; default: CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q19 = - IF_mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioP_ETC___d625; + IF_mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioP_ETC___d621; endcase end always@(srcRR_0 or propDstIdx_0_dummy2_1$Q_OUT or - IF_propDstIdx_0_lat_0_whas__005_THEN_propDstId_ETC___d1008 or + IF_propDstIdx_0_lat_0_whas__001_THEN_propDstId_ETC___d1004 or propDstIdx_1_dummy2_1$Q_OUT or - IF_propDstIdx_1_lat_0_whas__012_THEN_propDstId_ETC___d1015) + IF_propDstIdx_1_lat_0_whas__008_THEN_propDstId_ETC___d1011) begin case (srcRR_0) 1'd0: - SEL_ARR_propDstIdx_0_dummy2_1_read__058_AND_IF_ETC___d1089 = + SEL_ARR_propDstIdx_0_dummy2_1_read__054_AND_IF_ETC___d1085 = propDstIdx_0_dummy2_1$Q_OUT && - IF_propDstIdx_0_lat_0_whas__005_THEN_propDstId_ETC___d1008; + IF_propDstIdx_0_lat_0_whas__001_THEN_propDstId_ETC___d1004; 1'd1: - SEL_ARR_propDstIdx_0_dummy2_1_read__058_AND_IF_ETC___d1089 = + SEL_ARR_propDstIdx_0_dummy2_1_read__054_AND_IF_ETC___d1085 = propDstIdx_1_dummy2_1$Q_OUT && - IF_propDstIdx_1_lat_0_whas__012_THEN_propDstId_ETC___d1015; + IF_propDstIdx_1_lat_0_whas__008_THEN_propDstId_ETC___d1011; endcase end always@(srcRR_1_0 or propDstIdx_1_0_dummy2_1$Q_OUT or - IF_propDstIdx_1_0_lat_0_whas__174_THEN_propDst_ETC___d1177 or + IF_propDstIdx_1_0_lat_0_whas__170_THEN_propDst_ETC___d1173 or propDstIdx_1_1_dummy2_1$Q_OUT or - IF_propDstIdx_1_1_lat_0_whas__181_THEN_propDst_ETC___d1184) + IF_propDstIdx_1_1_lat_0_whas__177_THEN_propDst_ETC___d1180) begin case (srcRR_1_0) 1'd0: - SEL_ARR_propDstIdx_1_0_dummy2_1_read__317_AND__ETC___d1358 = + SEL_ARR_propDstIdx_1_0_dummy2_1_read__313_AND__ETC___d1354 = propDstIdx_1_0_dummy2_1$Q_OUT && - IF_propDstIdx_1_0_lat_0_whas__174_THEN_propDst_ETC___d1177; + IF_propDstIdx_1_0_lat_0_whas__170_THEN_propDst_ETC___d1173; 1'd1: - SEL_ARR_propDstIdx_1_0_dummy2_1_read__317_AND__ETC___d1358 = + SEL_ARR_propDstIdx_1_0_dummy2_1_read__313_AND__ETC___d1354 = propDstIdx_1_1_dummy2_1$Q_OUT && - IF_propDstIdx_1_1_lat_0_whas__181_THEN_propDst_ETC___d1184; + IF_propDstIdx_1_1_lat_0_whas__177_THEN_propDst_ETC___d1180; endcase end - always@(x__h61277 or n__read_id__h61463 or n__read_id__h61548) + always@(x__h61261 or n__read_id__h61447 or n__read_id__h61532) begin - case (x__h61277) - 1'd0: x__h61591 = n__read_id__h61463; - 1'd1: x__h61591 = n__read_id__h61548; + case (x__h61261) + 1'd0: x__h61575 = n__read_id__h61447; + 1'd1: x__h61575 = n__read_id__h61532; endcase end - always@(x__h61277 or n__read_child__h61464 or n__read_child__h61549) + always@(x__h61261 or n__read_child__h61448 or n__read_child__h61533) begin - case (x__h61277) - 1'd0: x__h61598 = n__read_child__h61464; - 1'd1: x__h61598 = n__read_child__h61549; + case (x__h61261) + 1'd0: x__h61582 = n__read_child__h61448; + 1'd1: x__h61582 = n__read_child__h61533; endcase end - always@(x__h61277 or - propDstData_0_dummy2_1_read__096_AND_IF_propDs_ETC___d1132 or - propDstData_1_dummy2_1_read__101_AND_IF_propDs_ETC___d1136) + always@(x__h61261 or + propDstData_0_dummy2_1_read__092_AND_IF_propDs_ETC___d1128 or + propDstData_1_dummy2_1_read__097_AND_IF_propDs_ETC___d1132) begin - case (x__h61277) + case (x__h61261) 1'd0: - CASE_x1277_0_propDstData_0_dummy2_1_read__096__ETC__q20 = - propDstData_0_dummy2_1_read__096_AND_IF_propDs_ETC___d1132; + CASE_x1261_0_propDstData_0_dummy2_1_read__092__ETC__q20 = + propDstData_0_dummy2_1_read__092_AND_IF_propDs_ETC___d1128; 1'd1: - CASE_x1277_0_propDstData_0_dummy2_1_read__096__ETC__q20 = - propDstData_1_dummy2_1_read__101_AND_IF_propDs_ETC___d1136; + CASE_x1261_0_propDstData_0_dummy2_1_read__092__ETC__q20 = + propDstData_1_dummy2_1_read__097_AND_IF_propDs_ETC___d1132; endcase end - always@(x__h61277 or - IF_propDstData_0_dummy2_1_read__096_THEN_IF_pr_ETC___d1112 or - IF_propDstData_1_dummy2_1_read__101_THEN_IF_pr_ETC___d1116) + always@(x__h61261 or + IF_propDstData_0_dummy2_1_read__092_THEN_IF_pr_ETC___d1108 or + IF_propDstData_1_dummy2_1_read__097_THEN_IF_pr_ETC___d1112) begin - case (x__h61277) + case (x__h61261) 1'd0: - CASE_x1277_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21 = - IF_propDstData_0_dummy2_1_read__096_THEN_IF_pr_ETC___d1112; + CASE_x1261_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21 = + IF_propDstData_0_dummy2_1_read__092_THEN_IF_pr_ETC___d1108; 1'd1: - CASE_x1277_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21 = - IF_propDstData_1_dummy2_1_read__101_THEN_IF_pr_ETC___d1116; + CASE_x1261_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21 = + IF_propDstData_1_dummy2_1_read__097_THEN_IF_pr_ETC___d1112; endcase end - always@(x__h61277 or - IF_propDstData_0_dummy2_1_read__096_THEN_IF_pr_ETC___d1122 or - IF_propDstData_1_dummy2_1_read__101_THEN_IF_pr_ETC___d1126) + always@(x__h61261 or + IF_propDstData_0_dummy2_1_read__092_THEN_IF_pr_ETC___d1118 or + IF_propDstData_1_dummy2_1_read__097_THEN_IF_pr_ETC___d1122) begin - case (x__h61277) + case (x__h61261) 1'd0: - CASE_x1277_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22 = - IF_propDstData_0_dummy2_1_read__096_THEN_IF_pr_ETC___d1122; + CASE_x1261_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22 = + IF_propDstData_0_dummy2_1_read__092_THEN_IF_pr_ETC___d1118; 1'd1: - CASE_x1277_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22 = - IF_propDstData_1_dummy2_1_read__101_THEN_IF_pr_ETC___d1126; + CASE_x1261_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22 = + IF_propDstData_1_dummy2_1_read__097_THEN_IF_pr_ETC___d1122; endcase end - always@(x__h61277 or n__read_addr__h61459 or n__read_addr__h61544) + always@(x__h61261 or n__read_addr__h61443 or n__read_addr__h61528) begin - case (x__h61277) + case (x__h61261) 1'd0: - CASE_x1277_0_n__read_addr1459_1_n__read_addr15_ETC__q23 = - n__read_addr__h61459; + CASE_x1261_0_n__read_addr1443_1_n__read_addr15_ETC__q23 = + n__read_addr__h61443; 1'd1: - CASE_x1277_0_n__read_addr1459_1_n__read_addr15_ETC__q23 = - n__read_addr__h61544; + CASE_x1261_0_n__read_addr1443_1_n__read_addr15_ETC__q23 = + n__read_addr__h61528; endcase end - always@(x__h79900 or + always@(x__h79884 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h79900) + case (x__h79884) 1'd0: - CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24 = + CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[512:449] : propDstData_1_0_rl[512:449]; 1'd1: - CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24 = + CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[512:449] : propDstData_1_1_rl[512:449]; endcase end - always@(x__h79900 or + always@(x__h79884 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h79900) + case (x__h79884) 1'd0: - CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 = + CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[448:385] : propDstData_1_0_rl[448:385]; 1'd1: - CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 = + CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[448:385] : propDstData_1_1_rl[448:385]; endcase end - always@(x__h79900 or n__read_child__h80081 or n__read_child__h80160) + always@(x__h79884 or n__read_child__h80065 or n__read_child__h80144) begin - case (x__h79900) - 1'd0: x__h82316 = n__read_child__h80081; - 1'd1: x__h82316 = n__read_child__h80160; + case (x__h79884) + 1'd0: x__h82300 = n__read_child__h80065; + 1'd1: x__h82300 = n__read_child__h80144; endcase end - always@(x__h79900 or + always@(x__h79884 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h79900) + case (x__h79884) 1'd0: - CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26 = + CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[384:321] : propDstData_1_0_rl[384:321]; 1'd1: - CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26 = + CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[384:321] : propDstData_1_1_rl[384:321]; endcase end - always@(x__h79900 or + always@(x__h79884 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h79900) + case (x__h79884) 1'd0: - CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 = + CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[320:257] : propDstData_1_0_rl[320:257]; 1'd1: - CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 = + CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[320:257] : propDstData_1_1_rl[320:257]; endcase end - always@(x__h79900 or + always@(x__h79884 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h79900) + case (x__h79884) 1'd0: - CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28 = + CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[256:193] : propDstData_1_0_rl[256:193]; 1'd1: - CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28 = + CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[256:193] : propDstData_1_1_rl[256:193]; endcase end - always@(x__h79900 or + always@(x__h79884 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h79900) + case (x__h79884) 1'd0: - CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 = + CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[192:129] : propDstData_1_0_rl[192:129]; 1'd1: - CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 = + CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[192:129] : propDstData_1_1_rl[192:129]; endcase end - always@(x__h79900 or + always@(x__h79884 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h79900) + case (x__h79884) 1'd0: - CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30 = + CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[128:65] : propDstData_1_0_rl[128:65]; 1'd1: - CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30 = + CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[128:65] : propDstData_1_1_rl[128:65]; endcase end - always@(x__h79900 or + always@(x__h79884 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h79900) + case (x__h79884) 1'd0: - CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 = + CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[64:1] : propDstData_1_0_rl[64:1]; 1'd1: - CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 = + CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[64:1] : propDstData_1_1_rl[64:1]; endcase end - always@(x__h79900 or + always@(x__h79884 or propDstData_1_0_dummy2_1$Q_OUT or - IF_propDstData_1_0_lat_0_whas__189_THEN_propDs_ETC___d1199 or + IF_propDstData_1_0_lat_0_whas__185_THEN_propDs_ETC___d1195 or propDstData_1_1_dummy2_1$Q_OUT or - IF_propDstData_1_1_lat_0_whas__227_THEN_propDs_ETC___d1237) + IF_propDstData_1_1_lat_0_whas__223_THEN_propDs_ETC___d1233) begin - case (x__h79900) + case (x__h79884) 1'd0: - CASE_x9900_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32 = + CASE_x9884_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32 = propDstData_1_0_dummy2_1$Q_OUT ? - IF_propDstData_1_0_lat_0_whas__189_THEN_propDs_ETC___d1199 : + IF_propDstData_1_0_lat_0_whas__185_THEN_propDs_ETC___d1195 : 2'd0; 1'd1: - CASE_x9900_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32 = + CASE_x9884_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32 = propDstData_1_1_dummy2_1$Q_OUT ? - IF_propDstData_1_1_lat_0_whas__227_THEN_propDs_ETC___d1237 : + IF_propDstData_1_1_lat_0_whas__223_THEN_propDs_ETC___d1233 : 2'd0; endcase end - always@(x__h79900 or - NOT_propDstData_1_0_dummy2_1_read__365_376_OR__ETC___d1377 or - NOT_propDstData_1_1_dummy2_1_read__367_378_OR__ETC___d1379) + always@(x__h79884 or + NOT_propDstData_1_0_dummy2_1_read__361_372_OR__ETC___d1373 or + NOT_propDstData_1_1_dummy2_1_read__363_374_OR__ETC___d1375) begin - case (x__h79900) + case (x__h79884) 1'd0: - CASE_x9900_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33 = - NOT_propDstData_1_0_dummy2_1_read__365_376_OR__ETC___d1377; + CASE_x9884_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33 = + NOT_propDstData_1_0_dummy2_1_read__361_372_OR__ETC___d1373; 1'd1: - CASE_x9900_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33 = - NOT_propDstData_1_1_dummy2_1_read__367_378_OR__ETC___d1379; + CASE_x9884_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33 = + NOT_propDstData_1_1_dummy2_1_read__363_374_OR__ETC___d1375; endcase end - always@(x__h79900 or n__read_addr__h80078 or n__read_addr__h80157) + always@(x__h79884 or n__read_addr__h80062 or n__read_addr__h80141) begin - case (x__h79900) + case (x__h79884) 1'd0: - CASE_x9900_0_n__read_addr0078_1_n__read_addr01_ETC__q34 = - n__read_addr__h80078; + CASE_x9884_0_n__read_addr0062_1_n__read_addr01_ETC__q34 = + n__read_addr__h80062; 1'd1: - CASE_x9900_0_n__read_addr0078_1_n__read_addr01_ETC__q34 = - n__read_addr__h80157; + CASE_x9884_0_n__read_addr0062_1_n__read_addr01_ETC__q34 = + n__read_addr__h80141; endcase end @@ -7876,7 +7862,7 @@ module mkProc(CLK, mmioPlatform_fromHostQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0; mmioPlatform_mtime <= `BSV_ASSIGNMENT_DELAY 64'd0; mmioPlatform_mtimecmp_0 <= `BSV_ASSIGNMENT_DELAY 64'd0; - mmioPlatform_mtip_0 <= `BSV_ASSIGNMENT_DELAY 1'd0; + mmioPlatform_mtip_0 <= `BSV_ASSIGNMENT_DELAY 1'd1; mmioPlatform_state <= `BSV_ASSIGNMENT_DELAY 2'd0; mmioPlatform_toHostAddr <= `BSV_ASSIGNMENT_DELAY 61'd0; mmioPlatform_toHostQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0; @@ -8241,14 +8227,14 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (EN_start) begin - v__h162860 = $stime; + v__h162844 = $stime; #0; end - v__h162854 = v__h162860 / 32'd10; + v__h162838 = v__h162844 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_start) $display("%0d: %m.method start: startpc %0h, tohostAddr %0h, fromhostAddr %0h", - v__h162854, + v__h162838, start_startpc, start_tohostAddr, start_fromhostAddr); @@ -8258,14 +8244,14 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost) begin - v__h162396 = $stime; + v__h162380 = $stime; #0; end - v__h162390 = v__h162396 / 32'd10; + v__h162374 = v__h162380 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost) $display("%0d: mmioPlatform.rl_tohost: 0x%0x (= %0d)", - v__h162390, + v__h162374, mmioPlatform_toHostQ_data_0, mmioPlatform_toHostQ_data_0); if (RST_N != `BSV_RESET_VALUE) @@ -8275,7 +8261,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0 && mmioPlatform_toHostQ_data_0[63:1] != 63'd0) - $display("FAIL %0d", failed_testnum__h162439); + $display("FAIL %0d", failed_testnum__h162423); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0) $finish(32'd0); @@ -9840,85 +9826,85 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $finish(32'd1); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) begin - v__h134353 = $stime; + v__h134337 = $stime; #0; end - v__h134347 = v__h134353 / 32'd10; + v__h134331 = v__h134337 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsps: beat %0d ", - v__h134347, + v__h134331, llc_axi4_adapter_rg_rd_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[2:1]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780 && + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776 && llc_axi4_adapter_master_xactor_rg_rd_data[0]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780 && + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776 && !llc_axi4_adapter_master_xactor_rg_rd_data[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) begin - v__h134520 = $stime; + v__h134504 = $stime; #0; end - v__h134514 = v__h134520 / 32'd10; + v__h134498 = v__h134504 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsp: fabric response error; exit", - v__h134514); + v__h134498); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) @@ -9980,135 +9966,135 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(" Response to LLC: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("MemRsMsg { ", "data: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(", ", "child: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(", ", "id: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("LdMemRqId { ", "refill: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780 && + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776 && llc_axi4_adapter_f_pending_reads$D_OUT[4]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780 && + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776 && !llc_axi4_adapter_f_pending_reads$D_OUT[4]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(", ", "mshrIdx: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("'h%h", llc_axi4_adapter_f_pending_reads$D_OUT[3:0], " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(" }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_wr_req_beat == 3'd0) begin - v__h136623 = $stime; + v__h136607 = $stime; #0; end - v__h136617 = v__h136623 / 32'd10; + v__h136601 = v__h136607 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_wr_req_beat == 3'd0) $display("%d: LLC_AXI4_Adapter.rl_handle_write_req: Wb request from LLC to memory:", - v__h136617); + v__h136601); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && @@ -11306,169 +11292,169 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) begin - v__h153967 = $stime; + v__h153951 = $stime; #0; end - v__h153961 = v__h153967 / 32'd10; + v__h153945 = v__h153951 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h153961); + $display("%0d: ERROR: CreditCounter: overflow", v__h153945); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) $finish(32'd1); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(" To fabric: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("AXI4_Wr_Addr { ", "awid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(", ", "awaddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) - $write("'h%h", mem_req_wr_addr_awaddr__h147878); + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + $write("'h%h", mem_req_wr_addr_awaddr__h147862); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(", ", "awlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("'h%h", 8'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(", ", "awsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("'h%h", 3'b011); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(", ", "awburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("'h%h", 2'b01); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(", ", "awlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("'h%h", 1'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(", ", "awcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("'h%h", 4'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(", ", "awprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("'h%h", 3'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(", ", "awqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(", ", "awregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(", ", "awuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("'h%h", 1'h0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("AXI4_Wr_Data { ", "wdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) - $write("'h%h", data64__h147793); + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + $write("'h%h", data64__h147777); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(", ", "wstrb: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) - $write("'h%h", strb8__h147794); + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + $write("'h%h", strb8__h147778); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(", ", "wlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(", ", "wuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("'h%h", 1'h0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_rd_req_beat == 3'd0) begin - v__h133734 = $stime; + v__h133718 = $stime; #0; end - v__h133728 = v__h133734 / 32'd10; + v__h133712 = v__h133718 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_rd_req_beat == 3'd0) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_req: Ld request from LLC to memory: beat %0d", - v__h133728, + v__h133712, llc_axi4_adapter_rg_rd_req_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && @@ -11539,159 +11525,159 @@ module mkProc(CLK, $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("AXI4_Rd_Addr { ", "arid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(", ", "araddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) - $write("'h%h", mem_req_rd_addr_araddr__h133954); + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + $write("'h%h", mem_req_rd_addr_araddr__h133938); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(", ", "arlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("'h%h", 8'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(", ", "arsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("'h%h", 3'b011); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(", ", "arburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("'h%h", 2'b01); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(", ", "arlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("'h%h", 1'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(", ", "arcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("'h%h", 4'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(", ", "arprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("'h%h", 3'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(", ", "arqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(", ", "arregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(", ", "aruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("'h%h", 1'h0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) begin - v__h160661 = $stime; + v__h160645 = $stime; #0; end - v__h160655 = v__h160661 / 32'd10; + v__h160639 = v__h160645 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $display("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: beat %0d ", - v__h160655, + v__h160639, llc_axi4_adapter_rg_wr_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("'h%h", llc_axi4_adapter_master_xactor_rg_wr_resp[5:2]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("'h%h", llc_axi4_adapter_master_xactor_rg_wr_resp[1:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) begin - v__h161169 = $stime; + v__h161153 = $stime; #0; end - v__h161163 = v__h161169 / 32'd10; + v__h161147 = v__h161153 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) $display("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: fabric response error: exit", - v__h161163); + v__h161147); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) diff --git a/src_SSITH_P3/Verilog_RTL/mkTrace_Data2_to_Trace_Data.v b/src_SSITH_P3/Verilog_RTL/mkTrace_Data2_to_Trace_Data.v index 52516d4..e61f0a2 100644 --- a/src_SSITH_P3/Verilog_RTL/mkTrace_Data2_to_Trace_Data.v +++ b/src_SSITH_P3/Verilog_RTL/mkTrace_Data2_to_Trace_Data.v @@ -77,13 +77,13 @@ module mkTrace_Data2_to_Trace_Data(CLK, // remaining internal signals reg [63 : 0] x1_avValue_pc__h3546, x1_avValue_word1__h3550; - reg [11 : 0] CASE_in_put_BITS_475_TO_464_1_in_put_BITS_475__ETC__q2, + reg [11 : 0] CASE_in_put_BITS_475_TO_464_1_in_put_BITS_475__ETC__q1, csr_addr__h5310; - reg [4 : 0] CASE_f_inD_OUT_BITS_624_TO_620_14_5_15_5_16_5_ETC__q1, + reg [4 : 0] CASE_f_inD_OUT_BITS_624_TO_620_14_5_15_5_16_5_ETC__q5, x1_avValue_rd__h3549; - reg [3 : 0] CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q3, - CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q4; - reg [1 : 0] CASE_in_put_BITS_393_TO_392_0_in_put_BITS_393__ETC__q5; + reg [3 : 0] CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q2, + CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q3; + reg [1 : 0] CASE_in_put_BITS_393_TO_392_0_in_put_BITS_393__ETC__q4; wire [63 : 0] td_word2__h3589, td_word2__h3740, td_word3__h3590, @@ -167,13 +167,13 @@ module mkTrace_Data2_to_Trace_Data(CLK, // submodule f_in assign f_in$D_IN = { in_put[861:476], - CASE_in_put_BITS_475_TO_464_1_in_put_BITS_475__ETC__q2, + CASE_in_put_BITS_475_TO_464_1_in_put_BITS_475__ETC__q1, in_put[463:462], in_put[462] ? - CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q3 : - CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q4, + CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q2 : + CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q3, in_put[457:394], - CASE_in_put_BITS_393_TO_392_0_in_put_BITS_393__ETC__q5, + CASE_in_put_BITS_393_TO_392_0_in_put_BITS_393__ETC__q4, in_put[391:0] } ; assign f_in$ENQ = EN_in_put ; assign f_in$DEQ = CAN_FIRE_RL_rl_td2_to_td ; @@ -217,7 +217,7 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[393:392] != 2'd1 && f_in$D_OUT[624:620] == 5'd13) ? 5'd16 : - CASE_f_inD_OUT_BITS_624_TO_620_14_5_15_5_16_5_ETC__q1)))))))))), + CASE_f_inD_OUT_BITS_624_TO_620_14_5_15_5_16_5_ETC__q5)))))))))), x__h4855, f_in$D_OUT[626:625] == 2'b11, f_in$D_OUT[656:625], @@ -227,7 +227,7 @@ module mkTrace_Data2_to_Trace_Data(CLK, x__h5458, x__h5890, x__h5906 } ; - assign f_out$ENQ = f_in$EMPTY_N && f_out$FULL_N ; + assign f_out$ENQ = CAN_FIRE_RL_rl_td2_to_td ; assign f_out$DEQ = EN_out_get ; assign f_out$CLR = 1'b0 ; @@ -466,22 +466,6 @@ module mkTrace_Data2_to_Trace_Data(CLK, default: csr_addr__h5310 = 12'd2303; endcase end - always@(f_in$D_OUT) - begin - case (f_in$D_OUT[624:620]) - 5'd14, 5'd15, 5'd16, 5'd17, 5'd18: - CASE_f_inD_OUT_BITS_624_TO_620_14_5_15_5_16_5_ETC__q1 = 5'd5; - 5'd19, 5'd20: - CASE_f_inD_OUT_BITS_624_TO_620_14_5_15_5_16_5_ETC__q1 = 5'd15; - default: CASE_f_inD_OUT_BITS_624_TO_620_14_5_15_5_16_5_ETC__q1 = - (f_in$D_OUT[393:392] == 2'd1 && - (f_in$D_OUT[624:620] == 5'd2 || - f_in$D_OUT[624:620] == 5'd6 || - f_in$D_OUT[624:620] == 5'd7)) ? - 5'd13 : - 5'd5; - endcase - end always@(in_put) begin case (in_put[475:464]) @@ -529,9 +513,9 @@ module mkTrace_Data2_to_Trace_Data(CLK, 12'd3858, 12'd3859, 12'd3860: - CASE_in_put_BITS_475_TO_464_1_in_put_BITS_475__ETC__q2 = + CASE_in_put_BITS_475_TO_464_1_in_put_BITS_475__ETC__q1 = in_put[475:464]; - default: CASE_in_put_BITS_475_TO_464_1_in_put_BITS_475__ETC__q2 = + default: CASE_in_put_BITS_475_TO_464_1_in_put_BITS_475__ETC__q1 = 12'd2303; endcase end @@ -539,9 +523,9 @@ module mkTrace_Data2_to_Trace_Data(CLK, begin case (in_put[461:458]) 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: - CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q3 = + CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q2 = in_put[461:458]; - default: CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q3 = 4'd15; + default: CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q2 = 4'd15; endcase end always@(in_put) @@ -560,18 +544,34 @@ module mkTrace_Data2_to_Trace_Data(CLK, 4'd11, 4'd12, 4'd13: - CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q4 = + CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q3 = in_put[461:458]; - default: CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q4 = 4'd15; + default: CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q3 = 4'd15; endcase end always@(in_put) begin case (in_put[393:392]) 2'd0, 2'd1: - CASE_in_put_BITS_393_TO_392_0_in_put_BITS_393__ETC__q5 = + CASE_in_put_BITS_393_TO_392_0_in_put_BITS_393__ETC__q4 = in_put[393:392]; - default: CASE_in_put_BITS_393_TO_392_0_in_put_BITS_393__ETC__q5 = 2'd2; + default: CASE_in_put_BITS_393_TO_392_0_in_put_BITS_393__ETC__q4 = 2'd2; + endcase + end + always@(f_in$D_OUT) + begin + case (f_in$D_OUT[624:620]) + 5'd14, 5'd15, 5'd16, 5'd17, 5'd18: + CASE_f_inD_OUT_BITS_624_TO_620_14_5_15_5_16_5_ETC__q5 = 5'd5; + 5'd19, 5'd20: + CASE_f_inD_OUT_BITS_624_TO_620_14_5_15_5_16_5_ETC__q5 = 5'd15; + default: CASE_f_inD_OUT_BITS_624_TO_620_14_5_15_5_16_5_ETC__q5 = + (f_in$D_OUT[393:392] == 2'd1 && + (f_in$D_OUT[624:620] == 5'd2 || + f_in$D_OUT[624:620] == 5'd6 || + f_in$D_OUT[624:620] == 5'd7)) ? + 5'd13 : + 5'd5; endcase end diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkCore.v b/src_SSITH_P3/Verilog_RTL_sim/mkCore.v index f251e7c..efdc7c0 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkCore.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkCore.v @@ -4375,7 +4375,7 @@ module mkCore(CLK, MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6, MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1, MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2, - MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_4; + MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3; wire [5 : 0] MUX_coreFix_memExe_lsq$getHit_1__VAL_1; wire [4 : 0] MUX_csrf_fflags_reg$write_1__VAL_1, MUX_rob$setExecuted_deqLSQ_2__VAL_2, @@ -4563,13 +4563,13 @@ module mkCore(CLK, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2972, addr__h294424, curData__h195856, - data_out__h747867, - data_warl_xformed__h732513, + data_out__h747970, + data_warl_xformed__h732616, rVal1__h615391, rVal1__h640618, - trap_val__h720333, + trap_val__h720436, x__h200595, - x__h733185; + x__h733288; reg [51 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q18, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q20, @@ -4650,7 +4650,7 @@ module mkCore(CLK, CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q299, CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q295, IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13118, - IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d13834; + IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d13844; reg [15 : 0] SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1367, SEL_ARR_mmio_dataRespQ_data_0_109_BITS_15_TO_0_ETC___d1417; reg [11 : 0] CASE_commitStage_f_rob_dataD_OUT_BITS_180_TO__ETC__q280, @@ -4740,9 +4740,9 @@ module mkCore(CLK, reg [5 : 0] CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q281, CASE_mmio_cRqQ_data_0_BITS_77_TO_76_0_mmio_cRq_ETC__q9, CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q277, - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300; - reg [4 : 0] IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d14395, - IF_fetchStage_pipelines_1_first__3001_BITS_191_ETC___d14561; + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310; + reg [4 : 0] IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d14405, + IF_fetchStage_pipelines_1_first__3001_BITS_191_ETC___d14571; reg [3 : 0] CASE_checkForException_3243_BITS_3_TO_0_0_chec_ETC__q234, CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q250, CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q251, @@ -4756,11 +4756,11 @@ module mkCore(CLK, CASE_v_f_to_TV_0D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q7, CASE_v_f_to_TV_1D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q2, CASE_v_f_to_TV_1D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q3, - IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d14398, + IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d14408, IF_fetchStage_pipelines_0_first__2992_BIT_68_3_ETC___d13365, - IF_fetchStage_pipelines_1_first__3001_BITS_191_ETC___d14562, - i__h719309, - i__h719469; + IF_fetchStage_pipelines_1_first__3001_BITS_191_ETC___d14572, + i__h719412, + i__h719572; reg [2 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q285, CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q230, CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q282, @@ -4810,7 +4810,7 @@ module mkCore(CLK, CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q243, CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q244, CASE_fetchStage_pipelines_0_canDeq__2990_AND_N_ETC__q241, - CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q240, + CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q239, CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q237, CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q238, CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q242, @@ -4853,7 +4853,7 @@ module mkCore(CLK, CASE_guard96219_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q92, CASE_guard96219_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q91, CASE_guard98500_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145, - CASE_k78117_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239, + CASE_k78220_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q240, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6546, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6559, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6563, @@ -4891,31 +4891,31 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d11137, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d8511, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d8524, - IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13711, - IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13769, - IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d14389, - IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d14392, - IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13715, - IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13739, - IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13774, - IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14100, - IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14122, - IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14140, - IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14195, - IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14197, - IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14211, - IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14218, - IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14294, - IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14306, - IF_fetchStage_pipelines_1_first__3001_BITS_191_ETC___d14559, - IF_fetchStage_pipelines_1_first__3001_BITS_191_ETC___d14560, - IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d14152, - IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d14291, - IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d14318, - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__368_ETC___d13732, - SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__299_ETC___d14252, - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3689_co_ETC___d13699, - SEL_ARR_fetchStage_pipelines_0_canDeq__2990_AN_ETC___d14022; + IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13721, + IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13779, + IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d14399, + IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d14402, + IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13725, + IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13749, + IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13784, + IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14110, + IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14132, + IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14150, + IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14205, + IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14207, + IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14221, + IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14228, + IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14304, + IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14316, + IF_fetchStage_pipelines_1_first__3001_BITS_191_ETC___d14569, + IF_fetchStage_pipelines_1_first__3001_BITS_191_ETC___d14570, + IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d14162, + IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d14301, + IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d14328, + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__369_ETC___d13742, + SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__299_ETC___d14262, + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3699_co_ETC___d13709, + SEL_ARR_fetchStage_pipelines_0_canDeq__2990_AN_ETC___d14032; wire [581 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3347; wire [569 : 0] IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2542, IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2553, @@ -4924,28 +4924,29 @@ module mkCore(CLK, wire [517 : 0] SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3042; wire [511 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2240, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3035, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16392; - wire [463 : 0] commitStage_f_rob_data_first__5072_BIT_167_517_ETC___d15244; - wire [457 : 0] rob_deqPort_0_deq_data__4651_BITS_161_TO_98_46_ETC___d15630; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16402; + wire [463 : 0] commitStage_f_rob_data_first__5082_BIT_167_518_ETC___d15254; + wire [457 : 0] rob_deqPort_0_deq_data__4661_BITS_161_TO_98_46_ETC___d15640; wire [447 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2037; - wire [393 : 0] IF_commitStage_f_rob_data_first__5072_BITS_97__ETC___d15243; + wire [393 : 0] IF_commitStage_f_rob_data_first__5082_BITS_97__ETC___d15253; wire [383 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2235, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3026, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16383; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16393; wire [321 : 0] basicExec___d12137, basicExec___d12839; wire [319 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2032; wire [255 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2230, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3017, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16374, + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16384, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d11191, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d11204, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d11197; wire [191 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2027; + wire [181 : 0] fetchStage_pipelines_0_first__2992_BIT_173_311_ETC___d13661; wire [144 : 0] coreFix_memExe_lsq_getOrigBE_coreFix_memExe_re_ETC___d1734; wire [127 : 0] b__h608067, b__h608143, b__h608244, b__h608256, x__h609068; wire [68 : 0] execFpuSimple___d11171; wire [65 : 0] IF_IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_NOT_ETC___d627, - IF_rob_deqPort_0_deq_data__4651_BITS_97_TO_96__ETC___d14824; + IF_rob_deqPort_0_deq_data__4661_BITS_97_TO_96__ETC___d14834; wire [64 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2602; wire [63 : 0] IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9288, IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__241_ETC___d12672, @@ -4977,7 +4978,7 @@ module mkCore(CLK, IF_coreFix_memExe_lsq_firstLd__285_BIT_96_350__ETC___d1386, IF_coreFix_memExe_lsq_firstLd__285_BIT_96_350__ETC___d1435, IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8, - IF_rob_deqPort_0_deq_data__4651_BITS_329_TO_32_ETC___d15510, + IF_rob_deqPort_0_deq_data__4661_BITS_329_TO_32_ETC___d15520, _theResult___fst__h608467, _theResult___snd__h608468, a___1__h608081, @@ -4987,17 +4988,17 @@ module mkCore(CLK, b___1__h608082, b___1__h608533, b__h607920, - base__h722254, - base__h722274, - commitStage_rg_serial_num_4640_PLUS_IF_rob_deq_ETC___d15776, + base__h722357, + base__h722377, + commitStage_rg_serial_num_4650_PLUS_IF_rob_deq_ETC___d15786, coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d11260, coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d11261, data___1__h479510, data___1__h480404, data__h478998, data__h479892, - fallthrough_pc__h674338, - fallthrough_pc__h690846, + fallthrough_pc__h674441, + fallthrough_pc__h690949, fcsr_csr__read__h615717, fflags_csr__read__h615692, frm_csr__read__h615703, @@ -5014,10 +5015,10 @@ module mkCore(CLK, n__read__h617696, n__read__h617887, n__read__h6761, - n__read__h736806, - new_mstatus___1__h736168, - next_pc__h732539, - pc__h722238, + n__read__h736909, + new_mstatus___1__h736271, + next_pc__h732642, + pc__h722341, q___1__h480479, rVal1__h486689, rVal2__h486690, @@ -5030,7 +5031,7 @@ module mkCore(CLK, res_data__h433696, resp_addr__h296401, rg_tdata1__read__h618547, - rob_deqPort_0_deq_data__4651_BITS_425_TO_362_4_ETC___d15501, + rob_deqPort_0_deq_data__4661_BITS_425_TO_362_4_ETC___d15511, robdeqPort_0_deq_data_BITS_95_TO_32__q245, satp_csr__read__h616420, scause_csr__read__h616217, @@ -5040,11 +5041,11 @@ module mkCore(CLK, sip_csr__read__h616357, sstatus_csr__read__h615913, stvec_csr__read__h616026, - trap_val__h719295, + trap_val__h719398, upd__h3994, upd__h5311, upd__h6875, - upd__h736917, + upd__h737020, v__h614200, v__h639582, x__h155291, @@ -5068,20 +5069,20 @@ module mkCore(CLK, x__h623647, x__h646654, x__h646655, - x__h712093, - x__h724496, - x__h724688, - x__h736159, - x__h736300, - x__h743208, + x__h712196, + x__h724599, + x__h724791, + x__h736262, + x__h736403, + x__h743311, x_addr__h318498, x_quotient__h479694, x_reg_ifc__read__h615822, x_remainder__h479695, y__h626404, y__h649119, - y__h740902, - y__h743778, + y__h741005, + y__h743881, y_avValue__h183536, y_avValue__h184217, y_avValue__h483734, @@ -5091,15 +5092,15 @@ module mkCore(CLK, y_avValue__h621624, y_avValue__h640563, y_avValue__h644642, - y_avValue_new_pc__h722030, - y_avValue_new_pc__h722216, - y_avValue_snd_snd_snd_snd_snd_fst__h740925, - y_avValue_snd_snd_snd_snd_snd_fst__h743839, - y_avValue_snd_snd_snd_snd_snd_fst__h743875, - y_avValue_snd_snd_snd_snd_snd_snd_snd__h743190; + y_avValue_new_pc__h722133, + y_avValue_new_pc__h722319, + y_avValue_snd_snd_snd_snd_snd_fst__h741028, + y_avValue_snd_snd_snd_snd_snd_fst__h743942, + y_avValue_snd_snd_snd_snd_snd_fst__h743978, + y_avValue_snd_snd_snd_snd_snd_snd_snd__h743293; wire [62 : 0] IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10767, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9997, - IF_csrf_prv_reg_read__3022_ULE_1_5013_AND_IF_c_ETC___d15237, + IF_csrf_prv_reg_read__3022_ULE_1_5023_AND_IF_c_ETC___d15247, r1__read__h619390, r1__read__h619794, r1__read__h620304, @@ -5437,7 +5438,7 @@ module mkCore(CLK, wire [50 : 0] r1__read__h619404, r1__read__h620581; wire [49 : 0] r1__read__h620690; wire [48 : 0] r1__read__h619406, r1__read__h620583, r1__read__h620692; - wire [47 : 0] r1__read_BITS_61_TO_14___h736227; + wire [47 : 0] r1__read_BITS_61_TO_14___h736330; wire [46 : 0] r1__read__h619408, r1__read__h620585; wire [45 : 0] r1__read__h619410, r1__read__h620587; wire [44 : 0] r1__read__h619412, r1__read__h620589; @@ -5445,8 +5446,8 @@ module mkCore(CLK, wire [42 : 0] r1__read__h620593; wire [41 : 0] r1__read__h620595; wire [40 : 0] r1__read__h620597; - wire [37 : 0] IF_fetchStage_pipelines_0_first__2992_BIT_160__ETC___d14401, - IF_fetchStage_pipelines_1_first__3001_BIT_160__ETC___d14565; + wire [37 : 0] IF_fetchStage_pipelines_0_first__2992_BIT_160__ETC___d14411, + IF_fetchStage_pipelines_1_first__3001_BIT_160__ETC___d14575; wire [31 : 0] coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q13, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q12, coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q10, @@ -5461,11 +5462,11 @@ module mkCore(CLK, x__h433706, x__h76239, x_data__h66088, - x_data_imm__h685411, - x_data_imm__h702077; + x_data_imm__h685514, + x_data_imm__h702180; wire [29 : 0] r1__read__h619418, r1__read__h620601; wire [27 : 0] r1__read__h620603; - wire [24 : 0] NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d14447, + wire [24 : 0] NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d14457, sfd__h358713, sfd__h367295, sfd__h376479, @@ -5573,9 +5574,9 @@ module mkCore(CLK, pend_ints__h658379, y__h658918; wire [13 : 0] r1__read_BITS_13_TO_0___h658928; - wire [12 : 0] IF_rob_deqPort_0_deq_data__4651_BITS_329_TO_32_ETC___d15620, - fetchStage_pipelines_1_first__3001_BIT_173_383_ETC___d13926, - rob_deqPort_0_deq_data__4651_BIT_181_4726_CONC_ETC___d14817; + wire [12 : 0] IF_rob_deqPort_0_deq_data__4661_BITS_329_TO_32_ETC___d15630, + fetchStage_pipelines_1_first__3001_BIT_173_384_ETC___d13936, + rob_deqPort_0_deq_data__4661_BIT_181_4736_CONC_ETC___d14827; wire [11 : 0] IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10546, IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9061, IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9776, @@ -5606,10 +5607,10 @@ module mkCore(CLK, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d6046, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7438, csr_addr__h662590, - renaming_spec_bits__h694343, + renaming_spec_bits__h694446, result__h653958, result__h654009, - spec_bits__h697502, + spec_bits__h697605, w__h653953, x__h368892, x__h414589, @@ -5620,10 +5621,10 @@ module mkCore(CLK, x__h653957, x__h654008, y__h653987, - y__h697515, - y_avValue_fst__h690675, - y_avValue_fst__h690704, - y_avValue_fst__h690738; + y__h697618, + y_avValue_fst__h690778, + y_avValue_fst__h690807, + y_avValue_fst__h690841; wire [10 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10651, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10653, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9171, @@ -5908,11 +5909,11 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4578, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7362, IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2176, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16418, + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16428, x__h184592, - x__h722269; - wire [4 : 0] IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d14618, - IF_rob_deqPort_0_canDeq__5654_THEN_IF_NOT_rob__ETC___d15986, + x__h722372; + wire [4 : 0] IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d14628, + IF_rob_deqPort_0_canDeq__5664_THEN_IF_NOT_rob__ETC___d15996, _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5269, _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6661, _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d8053, @@ -5929,24 +5930,24 @@ module mkCore(CLK, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6673, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d8065, checkForException___d13243, - checkForException___d13948, - fflags__h743755, - old_fflags1__h743181, - po_fflags__h738358, - po_fflags__h741065, + checkForException___d13958, + fflags__h743858, + old_fflags1__h743284, + po_fflags__h738461, + po_fflags__h741168, r1__read__h620941, res_fflags__h342295, res_fflags__h387997, res_fflags__h433692, - rob_deqPort_0_deq_data__4651_BIT_166_4667_CONC_ETC___d14716, + rob_deqPort_0_deq_data__4661_BIT_166_4677_CONC_ETC___d14726, rs1__h662591, x__h155285, x__h158832, x__h161648, x__h291636, - y_avValue_fst__h740440, - y_avValue_fst__h743660, - y_avValue_fst__h743692; + y_avValue_fst__h740543, + y_avValue_fst__h743763, + y_avValue_fst__h743795; wire [3 : 0] IF_IF_coreFix_memExe_dTlb_procResp__742_BIT_18_ETC___d1879, IF_IF_coreFix_memExe_dTlb_procResp__742_BIT_18_ETC___d1881, IF_IF_coreFix_memExe_dTlb_procResp__742_BIT_18_ETC___d1883, @@ -5973,13 +5974,13 @@ module mkCore(CLK, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2933, IF_coreFix_memExe_dTlb_procResp__742_BITS_177__ETC___d1824, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1263, - cause_code__h719294, + cause_code__h719397, vm_mode_reg__read__h620544; wire [2 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2571, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2890, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1220, _theResult_____2__h300945, - dcsr_cause__h718813, + dcsr_cause__h718916, next_deqP___1__h301224, v__h300365, v__h300596, @@ -5987,7 +5988,7 @@ module mkCore(CLK, x_decodeInfo_frm__h662275; wire [1 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2886, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1216, - IF_rob_deqPort_0_canDeq__5654_THEN_IF_NOT_rob__ETC___d16005, + IF_rob_deqPort_0_canDeq__5664_THEN_IF_NOT_rob__ETC___d16015, IF_sfdin04312_BIT_33_THEN_2_ELSE_0__q65, IF_sfdin16032_BIT_4_THEN_2_ELSE_0__q139, IF_sfdin22078_BIT_33_THEN_2_ELSE_0__q75, @@ -6030,20 +6031,20 @@ module mkCore(CLK, guard__h576657, guard__h585969, guard__h595038, - prv__h745422, - prv__h745466, + prv__h745525, + prv__h745569, r1__read_BITS_13_TO_12___h662460, sbIdx__h158711, v__h609138, v__h609148, v__h610179, - x__h732714, - x__h744019, - x_prv__h722338, - x_prv__h733165, - y_avValue_snd_snd_snd_fst__h740915, - y_avValue_snd_snd_snd_fst__h743829, - y_avValue_snd_snd_snd_fst__h743865; + x__h732817, + x__h744122, + x_prv__h722441, + x_prv__h733268, + y_avValue_snd_snd_snd_fst__h741018, + y_avValue_snd_snd_snd_fst__h743932, + y_avValue_snd_snd_snd_fst__h743968; wire IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5169, IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5219, IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6561, @@ -6063,8 +6064,8 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9100, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9815, IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_3023_30_ETC___d13287, - IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_3023_30_ETC___d14006, - IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_3023_30_ETC___d14043, + IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_3023_30_ETC___d14016, + IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_3023_30_ETC___d14053, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10052, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10053, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10589, @@ -6119,11 +6120,11 @@ module mkCore(CLK, IF_NOT_coreFix_memExe_bypassWire_0_whas__585_5_ETC___d1648, IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2118, IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2135, - IF_NOT_fetchStage_pipelines_0_canDeq__2990_299_ETC___d14158, - IF_NOT_fetchStage_pipelines_0_canDeq__2990_299_ETC___d14166, - IF_NOT_fetchStage_pipelines_1_first__3001_BITS_ETC___d14081, - IF_NOT_fetchStage_pipelines_1_first__3001_BITS_ETC___d14165, - IF_NOT_rob_deqPort_1_deq_data__5662_BIT_25_566_ETC___d15996, + IF_NOT_fetchStage_pipelines_0_canDeq__2990_299_ETC___d14168, + IF_NOT_fetchStage_pipelines_0_canDeq__2990_299_ETC___d14176, + IF_NOT_fetchStage_pipelines_1_first__3001_BITS_ETC___d14091, + IF_NOT_fetchStage_pipelines_1_first__3001_BITS_ETC___d14175, + IF_NOT_rob_deqPort_1_deq_data__5672_BIT_25_567_ETC___d16006, IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10051, IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10587, IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10820, @@ -6235,18 +6236,18 @@ module mkCore(CLK, IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d3749, IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3734, IF_coreFix_memExe_respLrScAmoQ_enqReq_lat_1_wh_ETC___d3658, - IF_fetchStage_RDY_pipelines_0_first__2989_AND__ETC___d13686, - IF_fetchStage_RDY_pipelines_1_first__3000_AND__ETC___d14083, - IF_fetchStage_RDY_pipelines_1_first__3000_AND__ETC___d14155, - IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14204, - IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d14334, + IF_fetchStage_RDY_pipelines_0_first__2989_AND__ETC___d13696, + IF_fetchStage_RDY_pipelines_1_first__3000_AND__ETC___d14093, + IF_fetchStage_RDY_pipelines_1_first__3000_AND__ETC___d14165, + IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14214, + IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d14344, IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmio_c_ETC___d339, IF_mmio_cRsQ_enqReq_lat_1_whas__74_THEN_mmio_c_ETC___d783, IF_mmio_dataReqQ_enqReq_lat_1_whas__7_THEN_mmi_ETC___d46, IF_mmio_dataRespQ_enqReq_lat_1_whas__92_THEN_m_ETC___d201, IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmio_p_ETC___d642, IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_mmio_p_ETC___d491, - IF_rob_deqPort_1_canDeq__5659_THEN_IF_NOT_rob__ETC___d15997, + IF_rob_deqPort_1_canDeq__5669_THEN_IF_NOT_rob__ETC___d16007, NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5321, NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5349, NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d6713, @@ -6254,9 +6255,9 @@ module mkCore(CLK, NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d8105, NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d8133, NOT_IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_302_ETC___d13579, - NOT_IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_302_ETC___d13673, - NOT_IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_302_ETC___d13975, - NOT_IF_NOT_rob_deqPort_0_canDeq__5654_5655_OR__ETC___d16002, + NOT_IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_302_ETC___d13683, + NOT_IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_302_ETC___d13985, + NOT_IF_NOT_rob_deqPort_0_canDeq__5664_5665_OR__ETC___d16012, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10171, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10880, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10922, @@ -6270,13 +6271,13 @@ module mkCore(CLK, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11121, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8671, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9401, - NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13734, - NOT_commitStage_commitTrap_4659_BIT_36_4906_49_ETC___d14941, - NOT_commitStage_commitTrap_4659_BIT_36_4906_49_ETC___d14948, - NOT_commitStage_commitTrap_4659_BIT_36_4906_49_ETC___d15012, - NOT_commitStage_rg_run_state_4657_4658_AND_NOT_ETC___d15321, - NOT_commitStage_rg_run_state_4657_4658_AND_NOT_ETC___d15332, - NOT_commitStage_rg_run_state_4657_4658_AND_NOT_ETC___d15708, + NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13744, + NOT_commitStage_commitTrap_4669_BIT_36_4916_49_ETC___d14951, + NOT_commitStage_commitTrap_4669_BIT_36_4916_49_ETC___d14958, + NOT_commitStage_commitTrap_4669_BIT_36_4916_49_ETC___d15022, + NOT_commitStage_rg_run_state_4667_4668_AND_NOT_ETC___d15331, + NOT_commitStage_rg_run_state_4667_4668_AND_NOT_ETC___d15342, + NOT_commitStage_rg_run_state_4667_4668_AND_NOT_ETC___d15718, NOT_coreFix_aluExe_0_bypassWire_0_whas__2410_2_ETC___d12437, NOT_coreFix_aluExe_0_bypassWire_0_whas__2410_2_ETC___d12467, NOT_coreFix_aluExe_1_bypassWire_0_whas__1522_1_ETC___d11549, @@ -6334,40 +6335,40 @@ module mkCore(CLK, NOT_coreFix_memExe_respLrScAmoQ_enqReq_dummy2__ETC___d3689, NOT_coreFix_memExe_respLrScAmoQ_full_981_982_A_ETC___d2114, NOT_csrf_fs_reg_read__1746_EQ_0_3232_3233_OR_N_ETC___d13572, - NOT_csrf_fs_reg_read__1746_EQ_0_3232_3233_OR_N_ETC___d13671, - NOT_csrf_fs_reg_read__1746_EQ_0_3232_3233_OR_N_ETC___d13973, - NOT_csrf_prv_reg_read__3022_ULE_1_5013_5055_OR_ETC___d15059, - NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d13777, - NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14020, - NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14064, - NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14119, - NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14137, - NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14286, - NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14340, - NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14470, - NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14475, - NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14477, - NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14489, - NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14525, - NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14545, - NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14552, - NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14553, - NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14597, + NOT_csrf_fs_reg_read__1746_EQ_0_3232_3233_OR_N_ETC___d13681, + NOT_csrf_fs_reg_read__1746_EQ_0_3232_3233_OR_N_ETC___d13983, + NOT_csrf_prv_reg_read__3022_ULE_1_5023_5065_OR_ETC___d15069, + NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d13787, + NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14030, + NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14074, + NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14129, + NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14147, + NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14296, + NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14350, + NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14480, + NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14485, + NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14487, + NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14499, + NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14535, + NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14555, + NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14562, + NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14563, + NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14607, NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d13566, - NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d13716, - NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d13996, - NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d14002, - NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d14163, - NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d14347, - NOT_fetchStage_pipelines_0_first__2992_BITS_32_ETC___d14371, - NOT_fetchStage_pipelines_0_first__2992_BIT_68__ETC___d13727, + NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d13726, + NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d14006, + NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d14012, + NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d14173, + NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d14357, + NOT_fetchStage_pipelines_0_first__2992_BITS_32_ETC___d14381, + NOT_fetchStage_pipelines_0_first__2992_BIT_68__ETC___d13737, NOT_fetchStage_pipelines_1_canDeq__2998_2999_O_ETC___d13007, - NOT_fetchStage_pipelines_1_first__3001_BITS_19_ETC___d13750, - NOT_fetchStage_pipelines_1_first__3001_BITS_19_ETC___d13989, - NOT_fetchStage_pipelines_1_first__3001_BITS_19_ETC___d14106, - NOT_fetchStage_pipelines_1_first__3001_BITS_19_ETC___d14486, - NOT_fetchStage_pipelines_1_first__3001_BITS_32_ETC___d14540, - NOT_fetchStage_pipelines_1_first__3001_BIT_68__ETC___d14483, + NOT_fetchStage_pipelines_1_first__3001_BITS_19_ETC___d13760, + NOT_fetchStage_pipelines_1_first__3001_BITS_19_ETC___d13999, + NOT_fetchStage_pipelines_1_first__3001_BITS_19_ETC___d14116, + NOT_fetchStage_pipelines_1_first__3001_BITS_19_ETC___d14496, + NOT_fetchStage_pipelines_1_first__3001_BITS_32_ETC___d14550, + NOT_fetchStage_pipelines_1_first__3001_BIT_68__ETC___d14493, NOT_mmio_cRqQ_clearReq_dummy2_1_read__26_27_OR_ETC___d431, NOT_mmio_cRqQ_enqReq_dummy2_2_read__32_47_OR_I_ETC___d452, NOT_mmio_cRsQ_clearReq_dummy2_1_read__18_19_OR_ETC___d823, @@ -6383,21 +6384,21 @@ module mkCore(CLK, NOT_mmio_pRqQ_enqReq_dummy2_2_read__35_50_OR_I_ETC___d755, NOT_mmio_pRsQ_clearReq_dummy2_1_read__88_89_OR_ETC___d593, NOT_mmio_pRsQ_enqReq_dummy2_2_read__94_09_OR_I_ETC___d614, - NOT_regRenamingTable_rename_0_canRename__3658__ETC___d14011, - NOT_regRenamingTable_rename_0_canRename__3658__ETC___d14087, - NOT_regRenamingTable_rename_0_canRename__3658__ETC___d14465, - NOT_regRenamingTable_rename_1_canRename__3780__ETC___d14051, + NOT_regRenamingTable_rename_0_canRename__3668__ETC___d14021, + NOT_regRenamingTable_rename_0_canRename__3668__ETC___d14097, + NOT_regRenamingTable_rename_0_canRename__3668__ETC___d14475, + NOT_regRenamingTable_rename_1_canRename__3790__ETC___d14061, NOT_renameStage_rg_m_halt_req_3019_BIT_4_3020__ETC___d13337, - NOT_renameStage_rg_m_halt_req_3019_BIT_4_3020__ETC___d13678, - NOT_renameStage_rg_m_halt_req_3019_BIT_4_3020__ETC___d13986, - NOT_renameStage_rg_m_halt_req_3019_BIT_4_3020__ETC___d14128, - NOT_renameStage_rg_m_halt_req_3019_BIT_4_3020__ETC___d14146, - NOT_rob_deqPort_0_canDeq__5654_5655_OR_regRena_ETC___d15696, - NOT_rob_deqPort_0_canDeq__5654_5655_OR_rob_deq_ETC___d15980, - NOT_rob_deqPort_0_deq_data__4651_BITS_329_TO_3_ETC___d15310, - NOT_rob_deqPort_1_deq_data__5662_BIT_25_5663_5_ETC___d15693, - NOT_specTagManager_canClaim__3656_3742_OR_NOT__ETC___d14257, - NOT_specTagManager_canClaim__3656_3742_OR_NOT__ETC___d14324, + NOT_renameStage_rg_m_halt_req_3019_BIT_4_3020__ETC___d13688, + NOT_renameStage_rg_m_halt_req_3019_BIT_4_3020__ETC___d13996, + NOT_renameStage_rg_m_halt_req_3019_BIT_4_3020__ETC___d14138, + NOT_renameStage_rg_m_halt_req_3019_BIT_4_3020__ETC___d14156, + NOT_rob_deqPort_0_canDeq__5664_5665_OR_rob_RDY_ETC___d15706, + NOT_rob_deqPort_0_canDeq__5664_5665_OR_rob_deq_ETC___d15990, + NOT_rob_deqPort_0_deq_data__4661_BITS_329_TO_3_ETC___d15320, + NOT_rob_deqPort_1_deq_data__5672_BIT_25_5673_5_ETC___d15703, + NOT_specTagManager_canClaim__3666_3752_OR_NOT__ETC___d14267, + NOT_specTagManager_canClaim__3666_3752_OR_NOT__ETC___d14334, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10247, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10248, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8762, @@ -6431,12 +6432,12 @@ module mkCore(CLK, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6365, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7364, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7757, - _0_OR_NOT_fetchStage_pipelines_0_first__2992_BI_ETC___d14178, - _0_OR_NOT_fetchStage_pipelines_1_first__3001_BI_ETC___d14079, - _0_OR_NOT_fetchStage_pipelines_1_first__3001_BI_ETC___d14270, - _0b0_CONCAT_csrf_external_int_pend_vec_3_read___ETC___d14636, - _0b0_CONCAT_csrf_medeleg_15_reg_read__1845_1846_ETC___d15033, - _0b0_CONCAT_csrf_mideleg_11_reg_read__1853_1854_ETC___d15015, + _0_OR_NOT_fetchStage_pipelines_0_first__2992_BI_ETC___d14188, + _0_OR_NOT_fetchStage_pipelines_1_first__3001_BI_ETC___d14089, + _0_OR_NOT_fetchStage_pipelines_1_first__3001_BI_ETC___d14280, + _0b0_CONCAT_csrf_external_int_pend_vec_3_read___ETC___d14646, + _0b0_CONCAT_csrf_medeleg_15_reg_read__1845_1846_ETC___d15043, + _0b0_CONCAT_csrf_mideleg_11_reg_read__1853_1854_ETC___d15025, _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4112, _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4113, _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5284, @@ -6496,7 +6497,7 @@ module mkCore(CLK, _theResult_____2__h322789, _theResult_____2__h333133, _theResult_____2__h336358, - commitStage_commitTrap_4659_BIT_36_4906_AND_co_ETC___d14971, + commitStage_commitTrap_4669_BIT_36_4916_AND_co_ETC___d14981, coreFix_aluExe_0_bypassWire_0_wget__2411_BITS__ETC___d12413, coreFix_aluExe_0_bypassWire_0_wget__2411_BITS__ETC___d12454, coreFix_aluExe_0_bypassWire_1_wget__2424_BITS__ETC___d12426, @@ -6507,7 +6508,7 @@ module mkCore(CLK, coreFix_aluExe_0_bypassWire_3_wget__2439_BITS__ETC___d12468, coreFix_aluExe_0_dispToRegQ_RDY_first__2388_AN_ETC___d12479, coreFix_aluExe_0_exeToFinQ_RDY_first__2875_AND_ETC___d12915, - coreFix_aluExe_0_rsAlu_approximateCount__3693__ETC___d13695, + coreFix_aluExe_0_rsAlu_approximateCount__3703__ETC___d13705, coreFix_aluExe_1_bypassWire_0_wget__1523_BITS__ETC___d11525, coreFix_aluExe_1_bypassWire_0_wget__1523_BITS__ETC___d11566, coreFix_aluExe_1_bypassWire_1_wget__1536_BITS__ETC___d11538, @@ -6541,7 +6542,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ_first__486_BI_ETC___d11051, coreFix_fpuMulDivExe_0_regToExeQ_first__486_BI_ETC___d11093, coreFix_fpuMulDivExe_0_regToExeQ_first__486_BI_ETC___d11135, - coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__41_ETC___d14277, + coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__41_ETC___d14287, coreFix_memExe_bypassWire_0_wget__586_BITS_70__ETC___d1588, coreFix_memExe_bypassWire_0_wget__586_BITS_70__ETC___d1628, coreFix_memExe_bypassWire_1_wget__599_BITS_70__ETC___d1601, @@ -6611,50 +6612,50 @@ module mkCore(CLK, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1271, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1275, coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2_re_ETC___d3674, - coreFix_memExe_stb_isEmpty__011_AND_coreFix_me_ETC___d14973, + coreFix_memExe_stb_isEmpty__011_AND_coreFix_me_ETC___d14983, csrf_fs_reg_read__1746_EQ_0_3232_AND_fetchStag_ETC___d13280, - csrf_fs_reg_read__1746_EQ_0_3232_AND_fetchStag_ETC___d13752, - csrf_fs_reg_read__1746_EQ_0_3232_AND_fetchStag_ETC___d14041, - csrf_prv_reg_read__3022_ULE_1_5013_AND_IF_comm_ETC___d15035, - csrf_prv_reg_read__3022_ULE_1___d15013, + csrf_fs_reg_read__1746_EQ_0_3232_AND_fetchStag_ETC___d13762, + csrf_fs_reg_read__1746_EQ_0_3232_AND_fetchStag_ETC___d14051, + csrf_prv_reg_read__3022_ULE_1_5023_AND_IF_comm_ETC___d15045, + csrf_prv_reg_read__3022_ULE_1___d15023, csrf_prv_reg_read__3022_ULT_IF_fetchStage_pipe_ETC___d13275, - csrf_rg_dcsr_read__1920_BIT_2_3297_OR_NOT_fetc_ETC___d13748, - epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13984, - epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d14126, - epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d14144, - f_csr_rsps_i_notFull__6112_AND_f_csr_reqs_firs_ETC___d16215, - fetchStage_RDY_pipelines_0_first__2989_AND_epo_ETC___d13544, - fetchStage_pipelines_0_canDeq__2990_AND_NOT_fe_ETC___d14268, - fetchStage_pipelines_0_canDeq__2990_AND_NOT_fe_ETC___d14350, - fetchStage_pipelines_0_canDeq__2990_AND_NOT_fe_ETC___d14457, - fetchStage_pipelines_0_canDeq__2990_AND_fetchS_ETC___d14338, - fetchStage_pipelines_0_canDeq__2990_AND_regRen_ETC___d14274, - fetchStage_pipelines_0_canDeq__2990_AND_regRen_ETC___d14281, - fetchStage_pipelines_0_canDeq__2990_AND_regRen_ETC___d14303, - fetchStage_pipelines_0_canDeq__2990_AND_regRen_ETC___d14315, - fetchStage_pipelines_0_canDeq__2990_AND_regRen_ETC___d14608, - fetchStage_pipelines_0_canDeq__2990_AND_specTa_ETC___d14433, + csrf_rg_dcsr_read__1920_BIT_2_3297_OR_NOT_fetc_ETC___d13758, + epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13994, + epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d14136, + epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d14154, + f_csr_rsps_i_notFull__6122_AND_f_csr_reqs_firs_ETC___d16225, + fetchStage_RDY_pipelines_1_deq__3004_AND_NOT_f_ETC___d14338, + fetchStage_pipelines_0_canDeq__2990_AND_NOT_fe_ETC___d14278, + fetchStage_pipelines_0_canDeq__2990_AND_NOT_fe_ETC___d14360, + fetchStage_pipelines_0_canDeq__2990_AND_NOT_fe_ETC___d14467, + fetchStage_pipelines_0_canDeq__2990_AND_fetchS_ETC___d14348, + fetchStage_pipelines_0_canDeq__2990_AND_regRen_ETC___d14284, + fetchStage_pipelines_0_canDeq__2990_AND_regRen_ETC___d14291, + fetchStage_pipelines_0_canDeq__2990_AND_regRen_ETC___d14313, + fetchStage_pipelines_0_canDeq__2990_AND_regRen_ETC___d14325, + fetchStage_pipelines_0_canDeq__2990_AND_regRen_ETC___d14618, + fetchStage_pipelines_0_canDeq__2990_AND_specTa_ETC___d14443, fetchStage_pipelines_0_first__2992_BITS_194_TO_ETC___d13273, - fetchStage_pipelines_0_first__2992_BITS_194_TO_ETC___d13995, - fetchStage_pipelines_0_first__2992_BITS_194_TO_ETC___d14094, - fetchStage_pipelines_0_first__2992_BITS_194_TO_ETC___d14206, - fetchStage_pipelines_0_first__2992_BITS_194_TO_ETC___d14212, - fetchStage_pipelines_0_first__2992_BITS_194_TO_ETC___d14229, - fetchStage_pipelines_0_first__2992_BITS_194_TO_ETC___d14241, - fetchStage_pipelines_0_first__2992_BITS_194_TO_ETC___d14248, - fetchStage_pipelines_0_first__2992_BITS_194_TO_ETC___d14264, - fetchStage_pipelines_0_first__2992_BITS_199_TO_ETC___d13759, - fetchStage_pipelines_0_first__2992_BIT_68_3021_ETC___d14085, - fetchStage_pipelines_1_first__3001_BITS_194_TO_ETC___d14223, - fetchStage_pipelines_1_first__3001_BITS_199_TO_ETC___d14235, + fetchStage_pipelines_0_first__2992_BITS_194_TO_ETC___d14005, + fetchStage_pipelines_0_first__2992_BITS_194_TO_ETC___d14104, + fetchStage_pipelines_0_first__2992_BITS_194_TO_ETC___d14216, + fetchStage_pipelines_0_first__2992_BITS_194_TO_ETC___d14222, + fetchStage_pipelines_0_first__2992_BITS_194_TO_ETC___d14239, + fetchStage_pipelines_0_first__2992_BITS_194_TO_ETC___d14251, + fetchStage_pipelines_0_first__2992_BITS_194_TO_ETC___d14258, + fetchStage_pipelines_0_first__2992_BITS_194_TO_ETC___d14274, + fetchStage_pipelines_0_first__2992_BITS_199_TO_ETC___d13769, + fetchStage_pipelines_0_first__2992_BIT_68_3021_ETC___d14095, + fetchStage_pipelines_1_first__3001_BITS_194_TO_ETC___d14233, + fetchStage_pipelines_1_first__3001_BITS_199_TO_ETC___d14245, guard__h368757, guard__h414454, guard__h460149, guard__h508410, guard__h547263, guard__h586567, - idx__h694474, - k__h678117, + idx__h694577, + k__h678220, mmio_cRqQ_enqReq_dummy2_2_read__32_AND_IF_mmio_ETC___d444, mmio_cRsQ_enqReq_dummy2_2_read__24_AND_IF_mmio_ETC___d836, mmio_dataPendQ_enqReq_dummy2_2_read__00_AND_IF_ETC___d312, @@ -6663,8 +6664,8 @@ module mkCore(CLK, mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13290, mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13582, mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13600, - mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14342, - mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14344, + mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14352, + mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14354, mmio_pRqQ_enqReq_dummy2_2_read__35_AND_IF_mmio_ETC___d747, mmio_pRsQ_enqReq_dummy2_2_read__94_AND_IF_mmio_ETC___d606, msip__h76124, @@ -6674,38 +6675,38 @@ module mkCore(CLK, next_deqP___1__h333412, next_deqP___1__h336637, r1__read_BIT_20___h663156, - regRenamingTable_RDY_commit_0_commit__5255_AND_ETC___d15315, - regRenamingTable_RDY_rename_0_getRename__3535__ETC___d14191, - regRenamingTable_RDY_rename_1_getRename__4254__ETC___d14272, - regRenamingTable_rename_0_canRename__3658_AND__ETC___d13680, - regRenamingTable_rename_0_canRename__3658_AND__ETC___d13729, - regRenamingTable_rename_0_canRename__3658_AND__ETC___d13743, - regRenamingTable_rename_0_canRename__3658_AND__ETC___d14073, - regRenamingTable_rename_0_canRename__3658_AND__ETC___d14220, - regRenamingTable_rename_0_canRename__3658_AND__ETC___d14362, - regRenamingTable_rename_0_canRename__3658_AND__ETC___d14375, - regRenamingTable_rename_0_canRename__3658_AND__ETC___d14380, - regRenamingTable_rename_0_canRename__3658_AND__ETC___d14385, - regRenamingTable_rename_0_canRename__3658_AND__ETC___d14405, - regRenamingTable_rename_0_canRename__3658_AND__ETC___d14409, - regRenamingTable_rename_0_canRename__3658_AND__ETC___d14415, - regRenamingTable_rename_0_canRename__3658_AND__ETC___d14419, - regRenamingTable_rename_0_canRename__3658_AND__ETC___d14427, - regRenamingTable_rename_0_canRename__3658_AND__ETC___d14606, - regRenamingTable_rename_1_canRename__3780_AND__ETC___d13988, - regRenamingTable_rename_1_canRename__3780_AND__ETC___d14130, - regRenamingTable_rename_1_canRename__3780_AND__ETC___d14148, - regRenamingTable_rename_1_canRename__3780_AND__ETC___d14485, + regRenamingTable_RDY_rename_0_getRename__3535__ETC___d13544, + regRenamingTable_RDY_rename_0_getRename__3535__ETC___d14201, + regRenamingTable_RDY_rename_1_getRename__4264__ETC___d14282, + regRenamingTable_rename_0_canRename__3668_AND__ETC___d13690, + regRenamingTable_rename_0_canRename__3668_AND__ETC___d13739, + regRenamingTable_rename_0_canRename__3668_AND__ETC___d13753, + regRenamingTable_rename_0_canRename__3668_AND__ETC___d14083, + regRenamingTable_rename_0_canRename__3668_AND__ETC___d14230, + regRenamingTable_rename_0_canRename__3668_AND__ETC___d14372, + regRenamingTable_rename_0_canRename__3668_AND__ETC___d14385, + regRenamingTable_rename_0_canRename__3668_AND__ETC___d14390, + regRenamingTable_rename_0_canRename__3668_AND__ETC___d14395, + regRenamingTable_rename_0_canRename__3668_AND__ETC___d14415, + regRenamingTable_rename_0_canRename__3668_AND__ETC___d14419, + regRenamingTable_rename_0_canRename__3668_AND__ETC___d14425, + regRenamingTable_rename_0_canRename__3668_AND__ETC___d14429, + regRenamingTable_rename_0_canRename__3668_AND__ETC___d14437, + regRenamingTable_rename_0_canRename__3668_AND__ETC___d14616, + regRenamingTable_rename_1_canRename__3790_AND__ETC___d13998, + regRenamingTable_rename_1_canRename__3790_AND__ETC___d14140, + regRenamingTable_rename_1_canRename__3790_AND__ETC___d14158, + regRenamingTable_rename_1_canRename__3790_AND__ETC___d14495, renameStage_rg_m_halt_req_3019_BIT_4_3020_OR_N_ETC___d13303, renameStage_rg_m_halt_req_3019_BIT_4_3020_OR_N_ETC___d13534, - renameStage_rg_m_halt_req_3019_BIT_4_3020_OR_f_ETC___d14009, - renameStage_rg_m_halt_req_3019_BIT_4_3020_OR_f_ETC___d14049, - renameStage_rg_m_halt_req_3019_BIT_4_3020_OR_f_ETC___d14090, - renameStage_rg_m_halt_req_3019_BIT_4_3020_OR_f_ETC___d14170, - rg_core_run_state_read__3293_EQ_2_3294_AND_NOT_ETC___d16051, - rob_RDY_enqPort_1_enq__4320_AND_NOT_fetchStage_ETC___d14328, - tsr_val__h736420, - tvm_val__h736422, + renameStage_rg_m_halt_req_3019_BIT_4_3020_OR_f_ETC___d14019, + renameStage_rg_m_halt_req_3019_BIT_4_3020_OR_f_ETC___d14059, + renameStage_rg_m_halt_req_3019_BIT_4_3020_OR_f_ETC___d14100, + renameStage_rg_m_halt_req_3019_BIT_4_3020_OR_f_ETC___d14180, + rg_core_run_state_read__3293_EQ_2_3294_AND_NOT_ETC___d16061, + rob_RDY_deqPort_0_deq__4658_AND_rob_RDY_deqPor_ETC___d15325, + tsr_val__h736523, + tvm_val__h736525, v__h303710, v__h304228, v__h314224, @@ -6757,7 +6758,7 @@ module mkCore(CLK, { CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q264, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q265, !CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q266, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16392 } ; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16402 } ; assign RDY_dCacheToParent_rsToP_first = !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty ; @@ -6777,7 +6778,7 @@ module mkCore(CLK, assign dCacheToParent_rqToP_first = { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q273, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q274, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16418 } ; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16428 } ; assign RDY_dCacheToParent_rqToP_first = !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty ; @@ -9970,14 +9971,13 @@ module mkCore(CLK, assign WILL_FIRE_RL_setDoFlushCaches = CAN_FIRE_RL_setDoFlushCaches ; // rule RL_setDoFlushBrPred - assign CAN_FIRE_RL_setDoFlushBrPred = - flush_brpred && fetchStage$emptyForFlush ; - assign WILL_FIRE_RL_setDoFlushBrPred = CAN_FIRE_RL_setDoFlushBrPred ; + assign CAN_FIRE_RL_setDoFlushBrPred = CAN_FIRE_RL_flushBrPred ; + assign WILL_FIRE_RL_setDoFlushBrPred = CAN_FIRE_RL_flushBrPred ; // rule RL_readyToFetch assign CAN_FIRE_RL_readyToFetch = fetchStage$RDY_done_flushing && - rg_core_run_state_read__3293_EQ_2_3294_AND_NOT_ETC___d16051 && + rg_core_run_state_read__3293_EQ_2_3294_AND_NOT_ETC___d16061 && !flush_brpred && fetchStage$iMemIfc_flush_done && fetchStage$flush_predictors_done ; @@ -9988,8 +9988,8 @@ module mkCore(CLK, assign WILL_FIRE_RL_flushCaches = CAN_FIRE_RL_setDoFlushCaches ; // rule RL_flushBrPred - assign CAN_FIRE_RL_flushBrPred = CAN_FIRE_RL_setDoFlushBrPred ; - assign WILL_FIRE_RL_flushBrPred = CAN_FIRE_RL_setDoFlushBrPred ; + assign CAN_FIRE_RL_flushBrPred = flush_brpred && fetchStage$emptyForFlush ; + assign WILL_FIRE_RL_flushBrPred = CAN_FIRE_RL_flushBrPred ; // rule RL_rl_debug_gpr_read assign CAN_FIRE_RL_rl_debug_gpr_read = @@ -10077,7 +10077,7 @@ module mkCore(CLK, // rule RL_rl_debug_csr_write assign CAN_FIRE_RL_rl_debug_csr_write = f_csr_reqs$EMPTY_N && - f_csr_rsps_i_notFull__6112_AND_f_csr_reqs_firs_ETC___d16215 && + f_csr_rsps_i_notFull__6122_AND_f_csr_reqs_firs_ETC___d16225 && rg_core_run_state == 2'd1 && f_csr_reqs$D_OUT[76] ; assign WILL_FIRE_RL_rl_debug_csr_write = CAN_FIRE_RL_rl_debug_csr_write ; @@ -10443,14 +10443,14 @@ module mkCore(CLK, // rule RL_commitStage_rl_send_mip_csr_change_to_tv assign CAN_FIRE_RL_commitStage_rl_send_mip_csr_change_to_tv = v_f_to_TV_0$FULL_N && !commitStage_rg_just_after_reset && - !_0b0_CONCAT_csrf_external_int_pend_vec_3_read___ETC___d14636 ; + !_0b0_CONCAT_csrf_external_int_pend_vec_3_read___ETC___d14646 ; assign WILL_FIRE_RL_commitStage_rl_send_mip_csr_change_to_tv = CAN_FIRE_RL_commitStage_rl_send_mip_csr_change_to_tv ; // rule RL_commitStage_doCommitKilledLd assign CAN_FIRE_RL_commitStage_doCommitKilledLd = - epochManager$RDY_incrementEpoch && rob$RDY_deqPort_0_deq && - rob$RDY_deqPort_0_deq_data && + rob$RDY_deqPort_0_deq && rob$RDY_deqPort_0_deq_data && + epochManager$RDY_incrementEpoch && !commitStage_rg_run_state && !commitStage_commitTrap[165] && !rob$deqPort_0_deq_data[167] && @@ -10486,12 +10486,12 @@ module mkCore(CLK, // rule RL_commitStage_doCommitTrap_handle assign CAN_FIRE_RL_commitStage_doCommitTrap_handle = commitStage_f_rob_data$EMPTY_N && - NOT_commitStage_commitTrap_4659_BIT_36_4906_49_ETC___d14948 && - (commitStage_commitTrap_4659_BIT_36_4906_AND_co_ETC___d14971 || - coreFix_memExe_stb_isEmpty__011_AND_coreFix_me_ETC___d14973) && + NOT_commitStage_commitTrap_4669_BIT_36_4916_49_ETC___d14958 && + (commitStage_commitTrap_4669_BIT_36_4916_AND_co_ETC___d14981 || + coreFix_memExe_stb_isEmpty__011_AND_coreFix_me_ETC___d14983) && commitStage_commitTrap[165] && !commitStage_rg_run_state && - _0b0_CONCAT_csrf_external_int_pend_vec_3_read___ETC___d14636 ; + _0b0_CONCAT_csrf_external_int_pend_vec_3_read___ETC___d14646 ; assign WILL_FIRE_RL_commitStage_doCommitTrap_handle = CAN_FIRE_RL_commitStage_doCommitTrap_handle && !WILL_FIRE_RL_commitStage_rl_send_tv_reset && @@ -10504,8 +10504,8 @@ module mkCore(CLK, // rule RL_commitStage_doCommitSystemInst assign CAN_FIRE_RL_commitStage_doCommitSystemInst = coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty && - regRenamingTable_RDY_commit_0_commit__5255_AND_ETC___d15315 && - NOT_commitStage_rg_run_state_4657_4658_AND_NOT_ETC___d15332 ; + rob_RDY_deqPort_0_deq__4658_AND_rob_RDY_deqPor_ETC___d15325 && + NOT_commitStage_rg_run_state_4667_4668_AND_NOT_ETC___d15342 ; assign WILL_FIRE_RL_commitStage_doCommitSystemInst = CAN_FIRE_RL_commitStage_doCommitSystemInst && !WILL_FIRE_RL_commitStage_rl_send_tv_reset && @@ -10539,8 +10539,8 @@ module mkCore(CLK, // rule RL_commitStage_doCommitNormalInst assign CAN_FIRE_RL_commitStage_doCommitNormalInst = rob$RDY_deqPort_0_deq_data && - NOT_rob_deqPort_0_canDeq__5654_5655_OR_regRena_ETC___d15696 && - NOT_commitStage_rg_run_state_4657_4658_AND_NOT_ETC___d15708 ; + NOT_rob_deqPort_0_canDeq__5664_5665_OR_rob_RDY_ETC___d15706 && + NOT_commitStage_rg_run_state_4667_4668_AND_NOT_ETC___d15718 ; assign WILL_FIRE_RL_commitStage_doCommitNormalInst = CAN_FIRE_RL_commitStage_doCommitNormalInst && !WILL_FIRE_RL_commitStage_rl_send_tv_reset ; @@ -11533,10 +11533,9 @@ module mkCore(CLK, // rule RL_renameStage_doRenaming_Trap assign CAN_FIRE_RL_renameStage_doRenaming_Trap = - fetchStage$RDY_pipelines_0_deq && + rob$RDY_enqPort_0_enq && fetchStage$RDY_pipelines_0_deq && fetchStage$RDY_pipelines_0_first && epochManager$RDY_incrementEpoch && - rob$RDY_enqPort_0_enq && mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13290 && rob$isEmpty && rg_core_run_state == 2'd2 ; @@ -11548,8 +11547,8 @@ module mkCore(CLK, // rule RL_renameStage_doRenaming_SystemInst assign CAN_FIRE_RL_renameStage_doRenaming_SystemInst = - fetchStage$RDY_pipelines_0_deq && - fetchStage_RDY_pipelines_0_first__2989_AND_epo_ETC___d13544 && + rob$RDY_enqPort_0_enq && + regRenamingTable_RDY_rename_0_getRename__3535__ETC___d13544 && mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13600 && rg_core_run_state == 2'd2 ; assign WILL_FIRE_RL_renameStage_doRenaming_SystemInst = @@ -11592,11 +11591,11 @@ module mkCore(CLK, // rule RL_renameStage_doRenaming assign CAN_FIRE_RL_renameStage_doRenaming = (!fetchStage$pipelines_0_canDeq || - IF_fetchStage_RDY_pipelines_0_first__2989_AND__ETC___d13686) && - IF_NOT_fetchStage_pipelines_0_canDeq__2990_299_ETC___d14158 && - IF_NOT_fetchStage_pipelines_0_canDeq__2990_299_ETC___d14166 && - NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14340 && - mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14344 ; + IF_fetchStage_RDY_pipelines_0_first__2989_AND__ETC___d13696) && + IF_NOT_fetchStage_pipelines_0_canDeq__2990_299_ETC___d14168 && + IF_NOT_fetchStage_pipelines_0_canDeq__2990_299_ETC___d14176 && + NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14350 && + mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14354 ; assign WILL_FIRE_RL_renameStage_doRenaming = CAN_FIRE_RL_renameStage_doRenaming && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && @@ -11635,10 +11634,10 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_fpr_read ; assign MUX_commitStage_rg_run_state$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap_4659_BIT_36_4906_AND_co_ETC___d14971 ; + commitStage_commitTrap_4669_BIT_36_4916_AND_co_ETC___d14981 ; assign MUX_commitStage_rg_serial_num$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4659_BIT_36_4906_49_ETC___d15012 ; + NOT_commitStage_commitTrap_4669_BIT_36_4916_49_ETC___d15022 ; assign MUX_commitStage_rg_serial_num$write_1__SEL_2 = WILL_FIRE_RL_commitStage_rl_send_mip_csr_change_to_tv || WILL_FIRE_RL_commitStage_doCommitSystemInst ; @@ -11834,9 +11833,9 @@ module mkCore(CLK, assign MUX_csrf_external_int_en_vec_1$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + (IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd9 || - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd22) ; assign MUX_csrf_external_int_en_vec_3$write_1__SEL_1 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11844,9 +11843,9 @@ module mkCore(CLK, assign MUX_csrf_external_int_pend_vec_1$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + (IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd16 || - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd29) ; assign MUX_csrf_external_int_pend_vec_1$write_1__SEL_2 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11855,20 +11854,20 @@ module mkCore(CLK, assign MUX_csrf_external_int_pend_vec_3$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd29 ; assign MUX_csrf_external_int_pend_vec_3$write_1__SEL_2 = WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd836 ; assign MUX_csrf_fflags_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitNormalInst && - NOT_IF_NOT_rob_deqPort_0_canDeq__5654_5655_OR__ETC___d16002 ; + NOT_IF_NOT_rob_deqPort_0_canDeq__5664_5665_OR__ETC___d16012 ; assign MUX_csrf_fflags_reg$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + (IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd0 || - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd2) ; assign MUX_csrf_fflags_reg$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11877,22 +11876,22 @@ module mkCore(CLK, assign MUX_csrf_frm_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + (IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd1 || - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd2) ; assign MUX_csrf_fs_reg$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + (IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd0 || - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd1 || - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd2 || - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd8 || - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd18) ; assign MUX_csrf_fs_reg$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11904,9 +11903,9 @@ module mkCore(CLK, assign MUX_csrf_ie_vec_0$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + (IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd8 || - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd18) ; assign MUX_csrf_ie_vec_0$write_1__SEL_2 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11916,21 +11915,21 @@ module mkCore(CLK, WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 ; assign MUX_csrf_ie_vec_1$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4659_BIT_36_4906_49_ETC___d15012 && - csrf_prv_reg_read__3022_ULE_1_5013_AND_IF_comm_ETC___d15035 ; + NOT_commitStage_commitTrap_4669_BIT_36_4916_49_ETC___d15022 && + csrf_prv_reg_read__3022_ULE_1_5023_AND_IF_comm_ETC___d15045 ; assign MUX_csrf_ie_vec_3$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; assign MUX_csrf_ie_vec_3$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4659_BIT_36_4906_49_ETC___d15012 && - NOT_csrf_prv_reg_read__3022_ULE_1_5013_5055_OR_ETC___d15059 ; + NOT_commitStage_commitTrap_4669_BIT_36_4916_49_ETC___d15022 && + NOT_csrf_prv_reg_read__3022_ULE_1_5023_5065_OR_ETC___d15069 ; assign MUX_csrf_ie_vec_3$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd768 ; assign MUX_csrf_mcause_code_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd27 ; assign MUX_csrf_mcause_code_reg$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11944,7 +11943,7 @@ module mkCore(CLK, assign MUX_csrf_mcycle_ehr_data_dummy2_0$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd30 ; assign MUX_csrf_medeleg_13_11_reg$write_1__SEL_1 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11952,7 +11951,7 @@ module mkCore(CLK, assign MUX_csrf_mepc_csr$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd26 ; assign MUX_csrf_mepc_csr$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11966,7 +11965,7 @@ module mkCore(CLK, assign MUX_csrf_minstret_ehr_data_dummy2_0$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd31 ; assign MUX_csrf_mpp_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; @@ -11976,7 +11975,7 @@ module mkCore(CLK, assign MUX_csrf_mtval_csr$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd28 ; assign MUX_csrf_mtval_csr$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11999,12 +11998,12 @@ module mkCore(CLK, assign MUX_csrf_rg_dcsr$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd40 ; assign MUX_csrf_rg_dpc$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd41 ; assign MUX_csrf_rg_dpc$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -12030,7 +12029,7 @@ module mkCore(CLK, assign MUX_csrf_scause_code_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd14 ; assign MUX_csrf_scause_code_reg$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -12041,7 +12040,7 @@ module mkCore(CLK, assign MUX_csrf_sepc_csr$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd13 ; assign MUX_csrf_sepc_csr$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -12061,7 +12060,7 @@ module mkCore(CLK, assign MUX_csrf_stval_csr$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd15 ; assign MUX_csrf_stval_csr$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -12072,13 +12071,13 @@ module mkCore(CLK, assign MUX_epochManager$updatePrevEpoch_0_update_1__SEL_2 = WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d14347 && - IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13739 ; + NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d14357 && + IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13749 ; assign MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2 = WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14475 && - NOT_fetchStage_pipelines_1_first__3001_BITS_19_ETC___d14486 && - IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d14152 ; + NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14485 && + NOT_fetchStage_pipelines_1_first__3001_BITS_19_ETC___d14496 && + IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d14162 ; assign MUX_f_run_halt_rsps$enq_1__SEL_1 = WILL_FIRE_RL_rl_debug_halted || WILL_FIRE_RL_rl_debug_halt_req_already_halted ; @@ -12094,7 +12093,7 @@ module mkCore(CLK, csrf_rg_dcsr[2] ; assign MUX_renameStage_rg_m_halt_req$write_1__SEL_2 = WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14475 && + NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14485 && csrf_rg_dcsr[2] ; assign MUX_rf$write_3_wr_1__PSEL_1 = WILL_FIRE_RL_coreFix_memExe_doRespLdForward || @@ -12149,13 +12148,13 @@ module mkCore(CLK, assign MUX_commitStage_commitTrap$write_1__VAL_2 = { 1'd1, rob$deqPort_0_deq_data[425:362], - x__h712093, - rob_deqPort_0_deq_data__4651_BIT_166_4667_CONC_ETC___d14716, + x__h712196, + rob_deqPort_0_deq_data__4661_BIT_166_4677_CONC_ETC___d14726, rob$deqPort_0_deq_data[361:330] } ; assign MUX_commitStage_rg_serial_num$write_1__VAL_1 = commitStage_rg_serial_num + 64'd1 ; assign MUX_commitStage_rg_serial_num$write_1__VAL_3 = - commitStage_rg_serial_num + y__h743778 ; + commitStage_rg_serial_num + y__h743881 ; assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_1 = { fetchStage$pipelines_0_first[199:195], IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13118, @@ -12169,8 +12168,8 @@ module mkCore(CLK, 5'd10, sbAggr$eagerLookup_0_get } ; assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_2 = - (k__h678117 == 1'd0 && - fetchStage_pipelines_0_canDeq__2990_AND_NOT_fe_ETC___d14350) ? + (k__h678220 == 1'd0 && + fetchStage_pipelines_0_canDeq__2990_AND_NOT_fe_ETC___d14360) ? { fetchStage$pipelines_0_first[199:195], IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13118, fetchStage$pipelines_0_first[173], @@ -12184,13 +12183,13 @@ module mkCore(CLK, specTagManager$nextSpecTag, sbAggr$eagerLookup_0_get } : { fetchStage$pipelines_1_first[199:195], - IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d13834, - fetchStage_pipelines_1_first__3001_BIT_173_383_ETC___d13926, + IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d13844, + fetchStage_pipelines_1_first__3001_BIT_173_384_ETC___d13936, fetchStage$pipelines_1_first[160:128], fetchStage$pipelines_1_first[255:232], regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h694343, + renaming_spec_bits__h694446, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -12213,7 +12212,7 @@ module mkCore(CLK, { 1'd1, coreFix_memExe_lsq$firstSt[149:143] } ; assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2 = { 1'd1, coreFix_memExe_lsq$firstLd[88:82] } ; - assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_4 = + assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3 = { 1'd1, coreFix_memExe_lsq$getHit[7:1] } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_2__VAL_1 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ? @@ -12356,8 +12355,8 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getRq, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getData } ; assign MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1 = - { prv__h745466, - prv__h745466 != 2'd3 && csrf_vm_mode_sv39_reg, + { prv__h745569, + prv__h745569 != 2'd3 && csrf_vm_mode_sv39_reg, csrf_mxr_reg, csrf_sum_reg, csrf_ppn_reg } ; @@ -12503,9 +12502,9 @@ module mkCore(CLK, MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_1 || MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_2 ; assign MUX_csrf_fflags_reg$write_1__VAL_1 = - csrf_fflags_reg | fflags__h743755 ; + csrf_fflags_reg | fflags__h743858 ; assign MUX_csrf_frm_reg$write_1__VAL_1 = - (IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + (IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd1) ? robdeqPort_0_deq_data_BITS_95_TO_32__q245[2:0] : robdeqPort_0_deq_data_BITS_95_TO_32__q245[7:5] ; @@ -12513,10 +12512,10 @@ module mkCore(CLK, (f_csr_reqs$D_OUT[75:64] == 12'd2) ? f_csr_reqs$D_OUT[2:0] : f_csr_reqs$D_OUT[7:5] ; - always@(IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 or + always@(IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 or robdeqPort_0_deq_data_BITS_95_TO_32__q245) begin - case (IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300) + case (IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310) 6'd0, 6'd1, 6'd2: MUX_csrf_fs_reg$write_1__VAL_2 = 2'b11; default: MUX_csrf_fs_reg$write_1__VAL_2 = robdeqPort_0_deq_data_BITS_95_TO_32__q245[14:13]; @@ -12531,55 +12530,55 @@ module mkCore(CLK, end assign MUX_csrf_ie_vec_1$write_1__VAL_1 = (rob$deqPort_0_deq_data[329:325] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + (IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd8 || - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd18)) ? robdeqPort_0_deq_data_BITS_95_TO_32__q245[1] : csrf_prev_ie_vec_1 ; assign MUX_csrf_ie_vec_3$write_1__VAL_1 = (rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd18) ? robdeqPort_0_deq_data_BITS_95_TO_32__q245[3] : csrf_prev_ie_vec_3 ; assign MUX_csrf_minstret_ehr_data_lat_0$wset_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ; assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1 = - n__read__h736806 + 64'd1 ; + n__read__h736909 + 64'd1 ; assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2 = - n__read__h736806 + { 62'd0, x__h744019 } ; + n__read__h736909 + { 62'd0, x__h744122 } ; assign MUX_csrf_mpp_reg$write_1__VAL_1 = (rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd18) ? MUX_csrf_minstret_ehr_data_lat_0$wset_1__VAL_2[12:11] : 2'd0 ; assign MUX_csrf_mtval_csr$write_1__VAL_1 = rob$deqPort_0_deq_data[95:32] ; assign MUX_csrf_prev_ie_vec_1$write_1__VAL_1 = rob$deqPort_0_deq_data[329:325] != 5'd13 || - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 != + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 != 6'd8 && - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 != + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 != 6'd18 || MUX_csrf_mtval_csr$write_1__VAL_1[5] ; assign MUX_csrf_prev_ie_vec_3$write_1__VAL_1 = rob$deqPort_0_deq_data[329:325] != 5'd13 || - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 != + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 != 6'd18 || MUX_csrf_mtval_csr$write_1__VAL_1[7] ; assign MUX_csrf_prv_reg$write_1__VAL_1 = (rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd40) ? MUX_csrf_mtval_csr$write_1__VAL_1[1:0] : ((rob$deqPort_0_deq_data[329:325] == 5'd19) ? - x__h732714 : + x__h732817 : csrf_mpp_reg) ; assign MUX_csrf_rg_dcsr$write_1__VAL_2 = { 32'b0, csrf_rg_dcsr[31:9], - dcsr_cause__h718813, + dcsr_cause__h718916, csrf_rg_dcsr[5:2], csrf_prv_reg } ; assign MUX_csrf_sepc_csr$write_1__VAL_1 = rob$deqPort_0_deq_data[95:32] ; @@ -12589,13 +12588,13 @@ module mkCore(CLK, amoExec___d882[0] ; assign MUX_csrf_spp_reg$write_1__VAL_1 = rob$deqPort_0_deq_data[329:325] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + (IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd8 || - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd18) && MUX_csrf_sepc_csr$write_1__VAL_1[8] ; assign MUX_csrf_stval_csr$write_1__VAL_1 = rob$deqPort_0_deq_data[95:32] ; - assign MUX_f_csr_rsps$enq_1__VAL_3 = { 1'd1, data_out__h747867 } ; + assign MUX_f_csr_rsps$enq_1__VAL_3 = { 1'd1, data_out__h747970 } ; assign MUX_f_fpr_rsps$enq_1__VAL_3 = { 1'd1, rf$read_4_rd1 } ; assign MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 = { csrf_prv_reg, @@ -12604,12 +12603,12 @@ module mkCore(CLK, csrf_sum_reg, csrf_ppn_reg } ; always@(rob$deqPort_0_deq_data or - next_pc__h732539 or csrf_sepc_csr or csrf_mepc_csr) + next_pc__h732642 or csrf_sepc_csr or csrf_mepc_csr) begin case (rob$deqPort_0_deq_data[329:325]) 5'd19: MUX_fetchStage$redirect_1__VAL_6 = csrf_sepc_csr; 5'd20: MUX_fetchStage$redirect_1__VAL_6 = csrf_mepc_csr; - default: MUX_fetchStage$redirect_1__VAL_6 = next_pc__h732539; + default: MUX_fetchStage$redirect_1__VAL_6 = next_pc__h732642; endcase end assign MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_1 = @@ -12688,7 +12687,7 @@ module mkCore(CLK, fetchStage$pipelines_0_first[194:192] != 3'd2 && fetchStage$pipelines_0_first[194:192] != 3'd3 && fetchStage$pipelines_0_first[194:192] != 3'd4, - NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d14447 } ; + NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d14457 } ; assign MUX_rob$enqPort_0_enq_1__VAL_2 = { fetchStage$pipelines_0_first[387:324], fetchStage$pipelines_0_first[127:96], @@ -12711,21 +12710,7 @@ module mkCore(CLK, fetchStage$pipelines_0_first[199:195], fetchStage$pipelines_0_first[75:69], 136'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, - fetchStage$pipelines_0_first[173], - IF_fetchStage_pipelines_0_first__2992_BITS_172_ETC___d13208, - 73'h1280000000000000000, - fetchStage$pipelines_0_first[323:260], - 5'd0, - fetchStage$pipelines_0_first[173] && - fetchStage$pipelines_0_first[199:195] == 5'd13 && - (fetchStage$pipelines_0_first[172:161] == 12'd1 || - fetchStage$pipelines_0_first[172:161] == 12'd2 || - fetchStage$pipelines_0_first[172:161] == 12'd3) || - fetchStage$pipelines_0_first[75] && - fetchStage$pipelines_0_first[74], - fetchStage$pipelines_0_first[194:192] != 3'd0, - 13'h1521, - specTagManager$currentSpecBits } ; + fetchStage_pipelines_0_first__2992_BIT_173_311_ETC___d13661 } ; assign MUX_rob$setExecuted_deqLSQ_2__VAL_2 = { 1'd1, CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q278 } ; @@ -12749,19 +12734,19 @@ module mkCore(CLK, 77'h0AAAAAAAAAAAAAAAAAAA, commitStage_f_rob_data$D_OUT[425:181], CASE_commitStage_f_rob_dataD_OUT_BITS_180_TO__ETC__q280, - commitStage_f_rob_data_first__5072_BIT_167_517_ETC___d15244 } ; + commitStage_f_rob_data_first__5082_BIT_167_518_ETC___d15254 } ; assign MUX_v_f_to_TV_0$enq_1__VAL_2 = { commitStage_rg_serial_num, 77'h0AAAAAAAAAAAAAAAAAAA, rob$deqPort_0_deq_data[425:182], - rob_deqPort_0_deq_data__4651_BIT_181_4726_CONC_ETC___d14817, + rob_deqPort_0_deq_data__4661_BIT_181_4736_CONC_ETC___d14827, rob$deqPort_0_deq_data[167], - rob_deqPort_0_deq_data__4651_BIT_166_4667_CONC_ETC___d14716, + rob_deqPort_0_deq_data__4661_BIT_166_4677_CONC_ETC___d14726, rob$deqPort_0_deq_data[161:98], - IF_rob_deqPort_0_deq_data__4651_BITS_97_TO_96__ETC___d14824, - po_fflags__h738358, + IF_rob_deqPort_0_deq_data__4661_BITS_97_TO_96__ETC___d14834, + po_fflags__h738461, rob$deqPort_0_deq_data[26], - new_mstatus___1__h736168, + new_mstatus___1__h736271, 258'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; assign MUX_v_f_to_TV_0$enq_1__VAL_4 = { commitStage_rg_serial_num, @@ -12771,12 +12756,12 @@ module mkCore(CLK, assign MUX_v_f_to_TV_0$enq_1__VAL_5 = { commitStage_rg_serial_num, 77'h0AAAAAAAAAAAAAAAAAAA, - x__h733185, + x__h733288, rob$deqPort_0_deq_data[361:182], - rob_deqPort_0_deq_data__4651_BIT_181_4726_CONC_ETC___d14817, + rob_deqPort_0_deq_data__4661_BIT_181_4736_CONC_ETC___d14827, rob$deqPort_0_deq_data[167], - rob_deqPort_0_deq_data__4651_BIT_166_4667_CONC_ETC___d14716, - rob_deqPort_0_deq_data__4651_BITS_161_TO_98_46_ETC___d15630 } ; + rob_deqPort_0_deq_data__4661_BIT_166_4677_CONC_ETC___d14726, + rob_deqPort_0_deq_data__4661_BITS_161_TO_98_46_ETC___d15640 } ; // inlined wires assign csrf_minstret_ehr_data_lat_0$whas = @@ -13092,7 +13077,7 @@ module mkCore(CLK, MUX_commitStage_rg_run_state$write_1__SEL_1 ; assign commitStage_rg_run_state$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap_4659_BIT_36_4906_AND_co_ETC___d14971 || + commitStage_commitTrap_4669_BIT_36_4916_AND_co_ETC___d14981 || WILL_FIRE_RL_rl_debug_resume ; // register commitStage_rg_serial_num @@ -13121,7 +13106,7 @@ module mkCore(CLK, end assign commitStage_rg_serial_num$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4659_BIT_36_4906_49_ETC___d15012 || + NOT_commitStage_commitTrap_4669_BIT_36_4916_49_ETC___d15022 || WILL_FIRE_RL_commitStage_rl_send_mip_csr_change_to_tv || WILL_FIRE_RL_commitStage_doCommitSystemInst || WILL_FIRE_RL_commitStage_doCommitNormalInst || @@ -13906,7 +13891,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd772 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd22 ; // register csrf_external_int_pend_vec_0 @@ -13955,7 +13940,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd836 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd29 || EN_setMEIP ; @@ -13977,12 +13962,12 @@ module mkCore(CLK, assign csrf_fflags_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + (IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd0 || - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd2) || WILL_FIRE_RL_commitStage_doCommitNormalInst && - NOT_IF_NOT_rob_deqPort_0_canDeq__5654_5655_OR__ETC___d16002 || + NOT_IF_NOT_rob_deqPort_0_canDeq__5664_5665_OR__ETC___d16012 || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd1 || f_csr_reqs$D_OUT[75:64] == 12'd3) ; @@ -13995,9 +13980,9 @@ module mkCore(CLK, assign csrf_frm_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + (IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd1 || - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd2) || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd2 || @@ -14019,7 +14004,7 @@ module mkCore(CLK, assign csrf_fs_reg$EN = MUX_csrf_fs_reg$write_1__SEL_2 || WILL_FIRE_RL_commitStage_doCommitNormalInst && - NOT_IF_NOT_rob_deqPort_0_canDeq__5654_5655_OR__ETC___d16002 || + NOT_IF_NOT_rob_deqPort_0_canDeq__5664_5665_OR__ETC___d16012 || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd1 || f_csr_reqs$D_OUT[75:64] == 12'd2 || @@ -14053,8 +14038,8 @@ module mkCore(CLK, endcase assign csrf_ie_vec_1$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4659_BIT_36_4906_49_ETC___d15012 && - csrf_prv_reg_read__3022_ULE_1_5013_AND_IF_comm_ETC___d15035 || + NOT_commitStage_commitTrap_4669_BIT_36_4916_49_ETC___d15022 && + csrf_prv_reg_read__3022_ULE_1_5023_AND_IF_comm_ETC___d15045 || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd256 || f_csr_reqs$D_OUT[75:64] == 12'd768) || @@ -14077,21 +14062,21 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4659_BIT_36_4906_49_ETC___d15012 && - NOT_csrf_prv_reg_read__3022_ULE_1_5013_5055_OR_ETC___d15059 || + NOT_commitStage_commitTrap_4669_BIT_36_4916_49_ETC___d15022 && + NOT_csrf_prv_reg_read__3022_ULE_1_5023_5065_OR_ETC___d15069 || WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; // register csrf_mcause_code_reg always@(MUX_csrf_mcause_code_reg$write_1__SEL_1 or MUX_csrf_stval_csr$write_1__VAL_1 or MUX_csrf_ie_vec_3$write_1__SEL_2 or - cause_code__h719294 or + cause_code__h719397 or MUX_csrf_mcause_code_reg$write_1__SEL_3 or f_csr_reqs$D_OUT) case (1'b1) MUX_csrf_mcause_code_reg$write_1__SEL_1: csrf_mcause_code_reg$D_IN = MUX_csrf_stval_csr$write_1__VAL_1[3:0]; MUX_csrf_ie_vec_3$write_1__SEL_2: - csrf_mcause_code_reg$D_IN = cause_code__h719294; + csrf_mcause_code_reg$D_IN = cause_code__h719397; MUX_csrf_mcause_code_reg$write_1__SEL_3: csrf_mcause_code_reg$D_IN = f_csr_reqs$D_OUT[3:0]; default: csrf_mcause_code_reg$D_IN = 4'b1010 /* unspecified value */ ; @@ -14100,11 +14085,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd834 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4659_BIT_36_4906_49_ETC___d15012 && - NOT_csrf_prv_reg_read__3022_ULE_1_5013_5055_OR_ETC___d15059 || + NOT_commitStage_commitTrap_4669_BIT_36_4916_49_ETC___d15022 && + NOT_csrf_prv_reg_read__3022_ULE_1_5023_5065_OR_ETC___d15069 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd27 ; // register csrf_mcause_interrupt_reg @@ -14127,11 +14112,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd834 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4659_BIT_36_4906_49_ETC___d15012 && - NOT_csrf_prv_reg_read__3022_ULE_1_5013_5055_OR_ETC___d15059 || + NOT_commitStage_commitTrap_4669_BIT_36_4916_49_ETC___d15022 && + NOT_csrf_prv_reg_read__3022_ULE_1_5023_5065_OR_ETC___d15069 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd27 ; // register csrf_mcounteren_cy_reg @@ -14144,7 +14129,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd774 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd24 ; // register csrf_mcounteren_ir_reg @@ -14157,7 +14142,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd774 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd24 ; // register csrf_mcounteren_tm_reg @@ -14170,7 +14155,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd774 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd24 ; // register csrf_mcycle_ehr_data_rl @@ -14187,7 +14172,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd770 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd20 ; // register csrf_medeleg_15_reg @@ -14200,7 +14185,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd770 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd20 ; // register csrf_medeleg_9_0_reg @@ -14213,7 +14198,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd770 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd20 ; // register csrf_mepc_csr @@ -14236,11 +14221,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd833 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4659_BIT_36_4906_49_ETC___d15012 && - NOT_csrf_prv_reg_read__3022_ULE_1_5013_5055_OR_ETC___d15059 || + NOT_commitStage_commitTrap_4669_BIT_36_4916_49_ETC___d15022 && + NOT_csrf_prv_reg_read__3022_ULE_1_5023_5065_OR_ETC___d15069 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd26 ; // register csrf_mideleg_11_reg @@ -14253,7 +14238,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd771 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd21 ; // register csrf_mideleg_1_0_reg @@ -14266,7 +14251,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd771 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd21 ; // register csrf_mideleg_5_3_reg @@ -14279,7 +14264,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd771 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd21 ; // register csrf_mideleg_9_7_reg @@ -14292,7 +14277,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd771 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd21 ; // register csrf_minstret_ehr_data_rl @@ -14320,8 +14305,8 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4659_BIT_36_4906_49_ETC___d15012 && - NOT_csrf_prv_reg_read__3022_ULE_1_5013_5055_OR_ETC___d15059 || + NOT_commitStage_commitTrap_4669_BIT_36_4916_49_ETC___d15022 && + NOT_csrf_prv_reg_read__3022_ULE_1_5023_5065_OR_ETC___d15069 || WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; // register csrf_mprv_reg @@ -14334,7 +14319,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd18 ; // register csrf_mscratch_csr @@ -14347,19 +14332,19 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd832 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd25 ; // register csrf_mtval_csr always@(MUX_csrf_mtval_csr$write_1__SEL_1 or rob$deqPort_0_deq_data or MUX_csrf_ie_vec_3$write_1__SEL_2 or - trap_val__h719295 or + trap_val__h719398 or MUX_csrf_mtval_csr$write_1__SEL_3 or f_csr_reqs$D_OUT) case (1'b1) MUX_csrf_mtval_csr$write_1__SEL_1: csrf_mtval_csr$D_IN = rob$deqPort_0_deq_data[95:32]; - MUX_csrf_ie_vec_3$write_1__SEL_2: csrf_mtval_csr$D_IN = trap_val__h719295; + MUX_csrf_ie_vec_3$write_1__SEL_2: csrf_mtval_csr$D_IN = trap_val__h719398; MUX_csrf_mtval_csr$write_1__SEL_3: csrf_mtval_csr$D_IN = f_csr_reqs$D_OUT[63:0]; default: csrf_mtval_csr$D_IN = @@ -14369,11 +14354,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd835 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4659_BIT_36_4906_49_ETC___d15012 && - NOT_csrf_prv_reg_read__3022_ULE_1_5013_5055_OR_ETC___d15059 || + NOT_commitStage_commitTrap_4669_BIT_36_4916_49_ETC___d15022 && + NOT_csrf_prv_reg_read__3022_ULE_1_5023_5065_OR_ETC___d15069 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd28 ; // register csrf_mtvec_base_hi_reg @@ -14386,7 +14371,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd773 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd23 ; // register csrf_mtvec_mode_low_reg @@ -14399,7 +14384,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd773 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd23 ; // register csrf_mxr_reg @@ -14423,7 +14408,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd384 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd17 ; // register csrf_prev_ie_vec_0 @@ -14453,8 +14438,8 @@ module mkCore(CLK, endcase assign csrf_prev_ie_vec_1$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4659_BIT_36_4906_49_ETC___d15012 && - csrf_prv_reg_read__3022_ULE_1_5013_AND_IF_comm_ETC___d15035 || + NOT_commitStage_commitTrap_4669_BIT_36_4916_49_ETC___d15022 && + csrf_prv_reg_read__3022_ULE_1_5023_AND_IF_comm_ETC___d15045 || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd256 || f_csr_reqs$D_OUT[75:64] == 12'd768) || @@ -14478,28 +14463,28 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4659_BIT_36_4906_49_ETC___d15012 && - NOT_csrf_prv_reg_read__3022_ULE_1_5013_5055_OR_ETC___d15059 || + NOT_commitStage_commitTrap_4669_BIT_36_4916_49_ETC___d15022 && + NOT_csrf_prv_reg_read__3022_ULE_1_5023_5065_OR_ETC___d15069 || WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; // register csrf_prv_reg always@(MUX_csrf_prv_reg$write_1__SEL_1 or MUX_csrf_prv_reg$write_1__VAL_1 or MUX_commitStage_rg_serial_num$write_1__SEL_1 or - x_prv__h722338 or + x_prv__h722441 or MUX_csrf_prv_reg$write_1__SEL_3 or f_csr_reqs$D_OUT) case (1'b1) MUX_csrf_prv_reg$write_1__SEL_1: csrf_prv_reg$D_IN = MUX_csrf_prv_reg$write_1__VAL_1; MUX_commitStage_rg_serial_num$write_1__SEL_1: - csrf_prv_reg$D_IN = x_prv__h722338; + csrf_prv_reg$D_IN = x_prv__h722441; MUX_csrf_prv_reg$write_1__SEL_3: csrf_prv_reg$D_IN = f_csr_reqs$D_OUT[1:0]; default: csrf_prv_reg$D_IN = 2'b10 /* unspecified value */ ; endcase assign csrf_prv_reg$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4659_BIT_36_4906_49_ETC___d15012 || + NOT_commitStage_commitTrap_4669_BIT_36_4916_49_ETC___d15022 || WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd1968 || WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo24 ; @@ -14522,12 +14507,12 @@ module mkCore(CLK, endcase assign csrf_rg_dcsr$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap_4659_BIT_36_4906_AND_co_ETC___d14971 || + commitStage_commitTrap_4669_BIT_36_4916_AND_co_ETC___d14981 || WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd1968 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd40 ; // register csrf_rg_dpc @@ -14546,12 +14531,12 @@ module mkCore(CLK, endcase assign csrf_rg_dpc$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap_4659_BIT_36_4906_AND_co_ETC___d14971 || + commitStage_commitTrap_4669_BIT_36_4916_AND_co_ETC___d14981 || WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd1969 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd41 ; // register csrf_rg_dscratch0 @@ -14564,7 +14549,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1970 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd42 ; // register csrf_rg_dscratch1 @@ -14577,7 +14562,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1971 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd43 ; // register csrf_rg_tdata1_data @@ -14590,7 +14575,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1953 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd37 ; // register csrf_rg_tdata1_dmode @@ -14603,7 +14588,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1953 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd37 ; // register csrf_rg_tdata2 @@ -14616,7 +14601,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1954 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd38 ; // register csrf_rg_tdata3 @@ -14629,7 +14614,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1955 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd39 ; // register csrf_rg_tselect @@ -14642,20 +14627,20 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1952 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd36 ; // register csrf_scause_code_reg always@(MUX_csrf_scause_code_reg$write_1__SEL_1 or MUX_csrf_stval_csr$write_1__VAL_1 or MUX_csrf_ie_vec_1$write_1__SEL_2 or - cause_code__h719294 or + cause_code__h719397 or MUX_csrf_scause_code_reg$write_1__SEL_3 or f_csr_reqs$D_OUT) case (1'b1) MUX_csrf_scause_code_reg$write_1__SEL_1: csrf_scause_code_reg$D_IN = MUX_csrf_stval_csr$write_1__VAL_1[3:0]; MUX_csrf_ie_vec_1$write_1__SEL_2: - csrf_scause_code_reg$D_IN = cause_code__h719294; + csrf_scause_code_reg$D_IN = cause_code__h719397; MUX_csrf_scause_code_reg$write_1__SEL_3: csrf_scause_code_reg$D_IN = f_csr_reqs$D_OUT[3:0]; default: csrf_scause_code_reg$D_IN = 4'b1010 /* unspecified value */ ; @@ -14664,11 +14649,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd322 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4659_BIT_36_4906_49_ETC___d15012 && - csrf_prv_reg_read__3022_ULE_1_5013_AND_IF_comm_ETC___d15035 || + NOT_commitStage_commitTrap_4669_BIT_36_4916_49_ETC___d15022 && + csrf_prv_reg_read__3022_ULE_1_5023_AND_IF_comm_ETC___d15045 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd14 ; // register csrf_scause_interrupt_reg @@ -14691,11 +14676,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd322 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4659_BIT_36_4906_49_ETC___d15012 && - csrf_prv_reg_read__3022_ULE_1_5013_AND_IF_comm_ETC___d15035 || + NOT_commitStage_commitTrap_4669_BIT_36_4916_49_ETC___d15022 && + csrf_prv_reg_read__3022_ULE_1_5023_AND_IF_comm_ETC___d15045 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd14 ; // register csrf_scounteren_cy_reg @@ -14708,7 +14693,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd262 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd11 ; // register csrf_scounteren_ir_reg @@ -14721,7 +14706,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd262 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd11 ; // register csrf_scounteren_tm_reg @@ -14734,7 +14719,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd262 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd11 ; // register csrf_sepc_csr @@ -14757,11 +14742,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd321 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4659_BIT_36_4906_49_ETC___d15012 && - csrf_prv_reg_read__3022_ULE_1_5013_AND_IF_comm_ETC___d15035 || + NOT_commitStage_commitTrap_4669_BIT_36_4916_49_ETC___d15022 && + csrf_prv_reg_read__3022_ULE_1_5023_AND_IF_comm_ETC___d15045 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd13 ; // register csrf_software_int_en_vec_0 @@ -14789,7 +14774,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd772 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd22 ; // register csrf_software_int_pend_vec_0 @@ -14833,7 +14818,7 @@ module mkCore(CLK, mmio_pRqQ_data_0[37:36] != 2'd1 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd29 ; // register csrf_spp_reg @@ -14851,8 +14836,8 @@ module mkCore(CLK, endcase assign csrf_spp_reg$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4659_BIT_36_4906_49_ETC___d15012 && - csrf_prv_reg_read__3022_ULE_1_5013_AND_IF_comm_ETC___d15035 || + NOT_commitStage_commitTrap_4669_BIT_36_4916_49_ETC___d15022 && + csrf_prv_reg_read__3022_ULE_1_5023_AND_IF_comm_ETC___d15045 || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd256 || f_csr_reqs$D_OUT[75:64] == 12'd768) || @@ -14868,7 +14853,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd320 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd12 ; // register csrf_stats_module_doStats @@ -14879,12 +14864,12 @@ module mkCore(CLK, always@(MUX_csrf_stval_csr$write_1__SEL_1 or rob$deqPort_0_deq_data or MUX_csrf_ie_vec_1$write_1__SEL_2 or - trap_val__h719295 or + trap_val__h719398 or MUX_csrf_stval_csr$write_1__SEL_3 or f_csr_reqs$D_OUT) case (1'b1) MUX_csrf_stval_csr$write_1__SEL_1: csrf_stval_csr$D_IN = rob$deqPort_0_deq_data[95:32]; - MUX_csrf_ie_vec_1$write_1__SEL_2: csrf_stval_csr$D_IN = trap_val__h719295; + MUX_csrf_ie_vec_1$write_1__SEL_2: csrf_stval_csr$D_IN = trap_val__h719398; MUX_csrf_stval_csr$write_1__SEL_3: csrf_stval_csr$D_IN = f_csr_reqs$D_OUT[63:0]; default: csrf_stval_csr$D_IN = @@ -14894,11 +14879,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd323 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4659_BIT_36_4906_49_ETC___d15012 && - csrf_prv_reg_read__3022_ULE_1_5013_AND_IF_comm_ETC___d15035 || + NOT_commitStage_commitTrap_4669_BIT_36_4916_49_ETC___d15022 && + csrf_prv_reg_read__3022_ULE_1_5023_AND_IF_comm_ETC___d15045 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd15 ; // register csrf_stvec_base_hi_reg @@ -14911,7 +14896,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd261 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd10 ; // register csrf_stvec_mode_low_reg @@ -14924,7 +14909,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd261 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd10 ; // register csrf_sum_reg @@ -14967,7 +14952,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd772 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd22 ; // register csrf_timer_int_pend_vec_0 @@ -15001,7 +14986,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd18 ; // register csrf_tvm_reg @@ -15014,7 +14999,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd18 ; // register csrf_tw_reg @@ -15027,7 +15012,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd18 ; // register csrf_vm_mode_sv39_reg @@ -15040,21 +15025,21 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd384 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd17 ; // register flush_brpred assign flush_brpred$D_IN = MUX_commitStage_rg_run_state$write_1__SEL_1 ; assign flush_brpred$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap_4659_BIT_36_4906_AND_co_ETC___d14971 || + commitStage_commitTrap_4669_BIT_36_4916_AND_co_ETC___d14981 || WILL_FIRE_RL_flushBrPred ; // register flush_caches assign flush_caches$D_IN = MUX_commitStage_rg_run_state$write_1__SEL_1 ; assign flush_caches$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap_4659_BIT_36_4906_AND_co_ETC___d14971 || + commitStage_commitTrap_4669_BIT_36_4916_AND_co_ETC___d14981 || WILL_FIRE_RL_flushCaches ; // register flush_reservation @@ -15069,11 +15054,11 @@ module mkCore(CLK, assign flush_tlbs$EN = WILL_FIRE_RL_prepareCachesAndTlbs && flush_tlbs || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap_4659_BIT_36_4906_AND_co_ETC___d14971 || + commitStage_commitTrap_4669_BIT_36_4916_AND_co_ETC___d14981 || WILL_FIRE_RL_commitStage_doCommitSystemInst && (rob$deqPort_0_deq_data[329:325] == 5'd16 || rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd17) ; // register mmio_cRqQ_clearReq_rl @@ -15373,7 +15358,7 @@ module mkCore(CLK, WILL_FIRE_RL_renameStage_doRenaming_Trap) && csrf_rg_dcsr[2] || WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14475 && + NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14485 && csrf_rg_dcsr[2] || WILL_FIRE_RL_rl_debug_resume || WILL_FIRE_RL_rl_debug_halt_req ; @@ -15413,11 +15398,11 @@ module mkCore(CLK, // submodule commitStage_f_rob_data assign commitStage_f_rob_data$D_IN = { rob$deqPort_0_deq_data[425:182], - rob_deqPort_0_deq_data__4651_BIT_181_4726_CONC_ETC___d14817, + rob_deqPort_0_deq_data__4661_BIT_181_4736_CONC_ETC___d14827, rob$deqPort_0_deq_data[168:167], - rob_deqPort_0_deq_data__4651_BIT_166_4667_CONC_ETC___d14716, + rob_deqPort_0_deq_data__4661_BIT_166_4677_CONC_ETC___d14726, rob$deqPort_0_deq_data[161:98], - IF_rob_deqPort_0_deq_data__4651_BITS_97_TO_96__ETC___d14824, + IF_rob_deqPort_0_deq_data__4661_BITS_97_TO_96__ETC___d14834, rob$deqPort_0_deq_data[31:0] } ; assign commitStage_f_rob_data$ENQ = WILL_FIRE_RL_commitStage_doCommitTrap_flush ; @@ -15619,7 +15604,7 @@ module mkCore(CLK, MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_2 or MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2 or MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3 or - MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_4 or + MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3 or MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4) begin case (1'b1) // synopsys parallel_case @@ -15631,10 +15616,10 @@ module mkCore(CLK, MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2; MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3: coreFix_aluExe_0_rsAlu$setRegReady_4_put = - MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_4; + MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3; MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4: coreFix_aluExe_0_rsAlu$setRegReady_4_put = - MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_4; + MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3; default: coreFix_aluExe_0_rsAlu$setRegReady_4_put = 8'b10101010 /* unspecified value */ ; endcase @@ -15860,8 +15845,8 @@ module mkCore(CLK, // submodule coreFix_aluExe_1_rsAlu assign coreFix_aluExe_1_rsAlu$enq_x = - (k__h678117 == 1'd1 && - fetchStage_pipelines_0_canDeq__2990_AND_NOT_fe_ETC___d14350) ? + (k__h678220 == 1'd1 && + fetchStage_pipelines_0_canDeq__2990_AND_NOT_fe_ETC___d14360) ? { fetchStage$pipelines_0_first[199:195], IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13118, fetchStage$pipelines_0_first[173], @@ -15875,13 +15860,13 @@ module mkCore(CLK, specTagManager$nextSpecTag, sbAggr$eagerLookup_0_get } : { fetchStage$pipelines_1_first[199:195], - IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d13834, - fetchStage_pipelines_1_first__3001_BIT_173_383_ETC___d13926, + IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d13844, + fetchStage_pipelines_1_first__3001_BIT_173_384_ETC___d13936, fetchStage$pipelines_1_first[160:128], fetchStage$pipelines_1_first[255:232], regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h694343, + renaming_spec_bits__h694446, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -15932,7 +15917,7 @@ module mkCore(CLK, MUX_coreFix_aluExe_1_rsAlu$setRegReady_4_put_1__SEL_2 or MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2 or MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3 or - MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_4 or + MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3 or MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4) begin case (1'b1) // synopsys parallel_case @@ -15944,10 +15929,10 @@ module mkCore(CLK, MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2; MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3: coreFix_aluExe_1_rsAlu$setRegReady_4_put = - MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_4; + MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3; MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4: coreFix_aluExe_1_rsAlu$setRegReady_4_put = - MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_4; + MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3; default: coreFix_aluExe_1_rsAlu$setRegReady_4_put = 8'b10101010 /* unspecified value */ ; endcase @@ -16517,7 +16502,7 @@ module mkCore(CLK, // submodule coreFix_fpuMulDivExe_0_rsFpuMulDiv assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$enq_x = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3658_AND__ETC___d14362) ? + regRenamingTable_rename_0_canRename__3668_AND__ETC___d14372) ? { IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13118, regRenamingTable$rename_0_getRename, rob$enqPort_0_getEnqInstTag, @@ -16525,10 +16510,10 @@ module mkCore(CLK, fetchStage$pipelines_0_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_0_get } : - { IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d13834, + { IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d13844, regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h694343, + renaming_spec_bits__h694446, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -16579,7 +16564,7 @@ module mkCore(CLK, MUX_coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put_1__SEL_2 or MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2 or MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3 or - MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_4 or + MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3 or MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4) begin case (1'b1) // synopsys parallel_case @@ -16591,10 +16576,10 @@ module mkCore(CLK, MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2; MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3: coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put = - MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_4; + MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3; MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4: coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put = - MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_4; + MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3; default: coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put = 8'b10101010 /* unspecified value */ ; endcase @@ -16627,12 +16612,12 @@ module mkCore(CLK, assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_enq = WILL_FIRE_RL_renameStage_doRenaming && (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3658_AND__ETC___d14362 || - NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14475 && - regRenamingTable_rename_1_canRename__3780_AND__ETC___d14485 && + regRenamingTable_rename_0_canRename__3668_AND__ETC___d14372 || + NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14485 && + regRenamingTable_rename_1_canRename__3790_AND__ETC___d14495 && (fetchStage$pipelines_1_first[194:192] == 3'd3 || fetchStage$pipelines_1_first[194:192] == 3'd4) && - NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14525 && + NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14535 && coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) ; assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRobEnqTime = 1'd1 ; assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_doDispatch = @@ -17481,44 +17466,44 @@ module mkCore(CLK, // submodule coreFix_memExe_lsq assign coreFix_memExe_lsq$enqLd_dst = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3658_AND__ETC___d14419) ? + regRenamingTable_rename_0_canRename__3668_AND__ETC___d14429) ? regRenamingTable$rename_0_getRename[8:0] : regRenamingTable$rename_1_getRename[8:0] ; assign coreFix_memExe_lsq$enqLd_inst_tag = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3658_AND__ETC___d14419) ? + regRenamingTable_rename_0_canRename__3668_AND__ETC___d14429) ? rob$enqPort_0_getEnqInstTag : rob$enqPort_1_getEnqInstTag ; assign coreFix_memExe_lsq$enqLd_mem_inst = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3658_AND__ETC___d14419) ? + regRenamingTable_rename_0_canRename__3668_AND__ETC___d14429) ? fetchStage$pipelines_0_first[191:174] : fetchStage$pipelines_1_first[191:174] ; assign coreFix_memExe_lsq$enqLd_spec_bits = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3658_AND__ETC___d14419) ? + regRenamingTable_rename_0_canRename__3668_AND__ETC___d14429) ? specTagManager$currentSpecBits : - renaming_spec_bits__h694343 ; + renaming_spec_bits__h694446 ; assign coreFix_memExe_lsq$enqSt_dst = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3658_AND__ETC___d14427) ? + regRenamingTable_rename_0_canRename__3668_AND__ETC___d14437) ? regRenamingTable$rename_0_getRename[8:0] : regRenamingTable$rename_1_getRename[8:0] ; assign coreFix_memExe_lsq$enqSt_inst_tag = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3658_AND__ETC___d14427) ? + regRenamingTable_rename_0_canRename__3668_AND__ETC___d14437) ? rob$enqPort_0_getEnqInstTag : rob$enqPort_1_getEnqInstTag ; assign coreFix_memExe_lsq$enqSt_mem_inst = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3658_AND__ETC___d14427) ? + regRenamingTable_rename_0_canRename__3668_AND__ETC___d14437) ? fetchStage$pipelines_0_first[191:174] : fetchStage$pipelines_1_first[191:174] ; assign coreFix_memExe_lsq$enqSt_spec_bits = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3658_AND__ETC___d14427) ? + regRenamingTable_rename_0_canRename__3668_AND__ETC___d14437) ? specTagManager$currentSpecBits : - renaming_spec_bits__h694343 ; + renaming_spec_bits__h694446 ; assign coreFix_memExe_lsq$getHit_t = MUX_coreFix_memExe_lsq$getHit_1__SEL_1 ? MUX_coreFix_memExe_lsq$getHit_1__VAL_1 : @@ -17950,9 +17935,9 @@ module mkCore(CLK, // submodule coreFix_memExe_rsMem assign coreFix_memExe_rsMem$enq_x = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3658_AND__ETC___d14385) ? + regRenamingTable_rename_0_canRename__3668_AND__ETC___d14395) ? { fetchStage$pipelines_0_first[191:189], - IF_fetchStage_pipelines_0_first__2992_BIT_160__ETC___d14401, + IF_fetchStage_pipelines_0_first__2992_BIT_160__ETC___d14411, regRenamingTable$rename_0_getRename, rob$enqPort_0_getEnqInstTag, specTagManager$currentSpecBits, @@ -17960,10 +17945,10 @@ module mkCore(CLK, specTagManager$nextSpecTag, sbAggr$eagerLookup_0_get } : { fetchStage$pipelines_1_first[191:189], - IF_fetchStage_pipelines_1_first__3001_BIT_160__ETC___d14565, + IF_fetchStage_pipelines_1_first__3001_BIT_160__ETC___d14575, regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h694343, + renaming_spec_bits__h694446, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -18014,7 +17999,7 @@ module mkCore(CLK, MUX_coreFix_memExe_rsMem$setRegReady_4_put_1__SEL_2 or MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2 or MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3 or - MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_4 or + MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3 or MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4) begin case (1'b1) // synopsys parallel_case @@ -18026,10 +18011,10 @@ module mkCore(CLK, MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2; MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3: coreFix_memExe_rsMem$setRegReady_4_put = - MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_4; + MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3; MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4: coreFix_memExe_rsMem$setRegReady_4_put = - MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_4; + MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3; default: coreFix_memExe_rsMem$setRegReady_4_put = 8'b10101010 /* unspecified value */ ; endcase @@ -18191,7 +18176,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd2816 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd30 ; // submodule csrf_mcycle_ehr_data_dummy2_1 @@ -18205,7 +18190,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd2818 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd31 ; // submodule csrf_minstret_ehr_data_dummy2_1 @@ -18223,7 +18208,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd2049 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd7 ; assign csrf_stats_module_writeQ$DEQ = EN_sendDoStats ; assign csrf_stats_module_writeQ$CLR = 1'b0 ; @@ -18234,7 +18219,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd2048 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd6 ; assign csrf_terminate_module_terminateQ$DEQ = EN_coreIndInv_terminate ; assign csrf_terminate_module_terminateQ$CLR = 1'b0 ; @@ -18253,8 +18238,8 @@ module mkCore(CLK, fetchStage$pipelines_0_canDeq || WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d14347 && - IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13739 || + NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d14357 && + IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13749 || WILL_FIRE_RL_renameStage_doRenaming_SystemInst || WILL_FIRE_RL_renameStage_doRenaming_Trap ; assign epochManager$EN_updatePrevEpoch_1_update = @@ -18262,9 +18247,9 @@ module mkCore(CLK, fetchStage$pipelines_1_canDeq && !epochManager$checkEpoch_1_check || WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14475 && - NOT_fetchStage_pipelines_1_first__3001_BITS_19_ETC___d14486 && - IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d14152 ; + NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14485 && + NOT_fetchStage_pipelines_1_first__3001_BITS_19_ETC___d14496 && + IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d14162 ; assign epochManager$EN_incrementEpoch = WILL_FIRE_RL_commitStage_doCommitTrap_flush && !rob$deqPort_0_deq_data[12] || @@ -18412,7 +18397,7 @@ module mkCore(CLK, assign fetchStage$perf_req_r = 2'h0 ; assign fetchStage$perf_setStatus_doStats = 1'b0 ; always@(MUX_commitStage_rg_serial_num$write_1__SEL_1 or - pc__h722238 or + pc__h722341 or WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or coreFix_aluExe_1_exeToFinQ$first or WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or @@ -18426,7 +18411,7 @@ module mkCore(CLK, begin case (1'b1) // synopsys parallel_case MUX_commitStage_rg_serial_num$write_1__SEL_1: - fetchStage$redirect_pc = pc__h722238; + fetchStage$redirect_pc = pc__h722341; WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T: fetchStage$redirect_pc = coreFix_aluExe_1_exeToFinQ$first[82:19]; WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T: @@ -18474,8 +18459,8 @@ module mkCore(CLK, fetchStage$pipelines_0_canDeq || WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d14347 && - IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13739 || + NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d14357 && + IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13749 || WILL_FIRE_RL_renameStage_doRenaming_SystemInst || WILL_FIRE_RL_renameStage_doRenaming_Trap ; assign fetchStage$EN_pipelines_1_deq = @@ -18483,9 +18468,9 @@ module mkCore(CLK, fetchStage$pipelines_1_canDeq && !epochManager$checkEpoch_1_check || WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14475 && - NOT_fetchStage_pipelines_1_first__3001_BITS_19_ETC___d14486 && - IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d14152 ; + NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14485 && + NOT_fetchStage_pipelines_1_first__3001_BITS_19_ETC___d14496 && + IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d14162 ; assign fetchStage$EN_iTlbIfc_flush = WILL_FIRE_RL_prepareCachesAndTlbs && flush_tlbs || WILL_FIRE_RL_rl_debug_resume ; @@ -18525,14 +18510,14 @@ module mkCore(CLK, assign fetchStage$EN_stop = 1'b0 ; assign fetchStage$EN_setWaitRedirect = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap_4659_BIT_36_4906_AND_co_ETC___d14971 || + commitStage_commitTrap_4669_BIT_36_4916_AND_co_ETC___d14981 || WILL_FIRE_RL_commitStage_doCommitTrap_flush && !rob$deqPort_0_deq_data[12] || WILL_FIRE_RL_renameStage_doRenaming_SystemInst || WILL_FIRE_RL_renameStage_doRenaming_Trap ; assign fetchStage$EN_redirect = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4659_BIT_36_4906_49_ETC___d15012 || + NOT_commitStage_commitTrap_4669_BIT_36_4916_49_ETC___d15022 || WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T || WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T || WILL_FIRE_RL_commitStage_doCommitKilledLd || @@ -18544,7 +18529,7 @@ module mkCore(CLK, assign fetchStage$EN_train_predictors = coreFix_trainBPQ_1$EMPTY_N || WILL_FIRE_RL_coreFix_doFetchTrainBP_1 ; - assign fetchStage$EN_flush_predictors = CAN_FIRE_RL_setDoFlushBrPred ; + assign fetchStage$EN_flush_predictors = CAN_FIRE_RL_flushBrPred ; assign fetchStage$EN_perf_setStatus = 1'b0 ; assign fetchStage$EN_perf_req = 1'b0 ; assign fetchStage$EN_perf_resp = 1'b0 ; @@ -18846,7 +18831,7 @@ module mkCore(CLK, assign regRenamingTable$rename_1_claimRename_r = fetchStage$pipelines_1_first[95:69] ; assign regRenamingTable$rename_1_claimRename_sb = - renaming_spec_bits__h694343 ; + renaming_spec_bits__h694446 ; assign regRenamingTable$rename_1_getRename_r = fetchStage$pipelines_1_first[95:69] ; assign regRenamingTable$specUpdate_correctSpeculation_mask = @@ -18876,8 +18861,8 @@ module mkCore(CLK, assign regRenamingTable$EN_rename_0_claimRename = WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d14347 && - IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13739 || + NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d14357 && + IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13749 || WILL_FIRE_RL_renameStage_doRenaming_SystemInst ; assign regRenamingTable$EN_rename_1_claimRename = MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2 ; @@ -19102,7 +19087,7 @@ module mkCore(CLK, fetchStage$pipelines_1_first[199:195], fetchStage$pipelines_1_first[75:69], 136'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, - fetchStage_pipelines_1_first__3001_BIT_173_383_ETC___d13926, + fetchStage_pipelines_1_first__3001_BIT_173_384_ETC___d13936, 73'h1280000000000000000, fetchStage$pipelines_1_first[323:260], 5'd0, @@ -19114,11 +19099,11 @@ module mkCore(CLK, fetchStage$pipelines_1_first[194:192] != 3'd3 && fetchStage$pipelines_1_first[194:192] != 3'd4, fetchStage$pipelines_1_first[194:192] != 3'd2 || - fetchStage_pipelines_0_canDeq__2990_AND_regRen_ETC___d14608 || - IF_fetchStage_pipelines_1_first__3001_BITS_191_ETC___d14559, - IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d14618, + fetchStage_pipelines_0_canDeq__2990_AND_regRen_ETC___d14618 || + IF_fetchStage_pipelines_1_first__3001_BITS_191_ETC___d14569, + IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d14628, 7'd32, - renaming_spec_bits__h694343 } ; + renaming_spec_bits__h694446 } ; assign rob$getOrigPC_0_get_x = coreFix_aluExe_0_dispToRegQ$first[52:41] ; assign rob$getOrigPC_1_get_x = coreFix_aluExe_1_dispToRegQ$first[52:41] ; assign rob$getOrigPC_2_get_x = 12'h0 ; @@ -19403,8 +19388,8 @@ module mkCore(CLK, assign rob$EN_enqPort_0_enq = WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d14347 && - IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13739 || + NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d14357 && + IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13749 || WILL_FIRE_RL_renameStage_doRenaming_Trap || WILL_FIRE_RL_renameStage_doRenaming_SystemInst ; assign rob$EN_enqPort_1_enq = @@ -19541,8 +19526,8 @@ module mkCore(CLK, assign sbAggr$EN_setBusy_0_set = WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d14347 && - IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13739 || + NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d14357 && + IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13749 || WILL_FIRE_RL_renameStage_doRenaming_SystemInst ; assign sbAggr$EN_setBusy_1_set = MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2 ; @@ -19656,8 +19641,8 @@ module mkCore(CLK, assign sbCons$EN_setBusy_0_set = WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d14347 && - IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13739 || + NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d14357 && + IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13749 || WILL_FIRE_RL_renameStage_doRenaming_SystemInst ; assign sbCons$EN_setBusy_1_set = MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2 ; @@ -19719,9 +19704,9 @@ module mkCore(CLK, end assign specTagManager$EN_claimSpecTag = WILL_FIRE_RL_renameStage_doRenaming && - (fetchStage_pipelines_0_canDeq__2990_AND_specTa_ETC___d14433 || - NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14475 && - NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14597) ; + (fetchStage_pipelines_0_canDeq__2990_AND_specTa_ETC___d14443 || + NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14485 && + NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14607) ; assign specTagManager$EN_specUpdate_incorrectSpeculation = WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T || WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T || @@ -19758,7 +19743,7 @@ module mkCore(CLK, end assign v_f_to_TV_0$ENQ = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4659_BIT_36_4906_49_ETC___d15012 || + NOT_commitStage_commitTrap_4669_BIT_36_4916_49_ETC___d15022 || WILL_FIRE_RL_commitStage_doCommitNormalInst && rob$deqPort_0_canDeq || WILL_FIRE_RL_commitStage_rl_send_tv_reset || @@ -19769,7 +19754,7 @@ module mkCore(CLK, // submodule v_f_to_TV_1 assign v_f_to_TV_1$D_IN = - { commitStage_rg_serial_num_4640_PLUS_IF_rob_deq_ETC___d15776, + { commitStage_rg_serial_num_4650_PLUS_IF_rob_deq_ETC___d15786, 77'h0AAAAAAAAAAAAAAAAAAA, rob$deqPort_1_deq_data[425:181], CASE_robdeqPort_1_deq_data_BITS_180_TO_169_1__ETC__q301, @@ -19777,9 +19762,9 @@ module mkCore(CLK, rob$deqPort_1_deq_data[161:98], CASE_robdeqPort_1_deq_data_BITS_97_TO_96_0_ro_ETC__q302, rob$deqPort_1_deq_data[95:32], - po_fflags__h741065, + po_fflags__h741168, rob$deqPort_1_deq_data[26], - x__h743208, + x__h743311, 258'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; assign v_f_to_TV_1$ENQ = WILL_FIRE_RL_commitStage_doCommitNormalInst && @@ -19841,7 +19826,7 @@ module mkCore(CLK, { { fetchStage$pipelines_0_first[173], IF_fetchStage_pipelines_0_first__2992_BITS_172_ETC___d13208 }, fetchStage$pipelines_0_first[160], - x_data_imm__h685411 } }), + x_data_imm__h685514 } }), .checkForException_regs({ fetchStage$pipelines_0_first[95], fetchStage$pipelines_0_first[94:89], { fetchStage$pipelines_0_first[88], @@ -19853,10 +19838,10 @@ module mkCore(CLK, .checkForException_csrState({ x_decodeInfo_frm__h662275, r1__read_BITS_13_TO_12___h662460 != 2'd0, - { prv__h745422, - tvm_val__h736422, + { prv__h745525, + tvm_val__h736525, { r1__read_BIT_20___h663156, - tsr_val__h736420, + tsr_val__h736523, { csrf_mcounteren_cy_reg, csrf_mcounteren_cy_reg && csrf_scounteren_cy_reg, @@ -19868,10 +19853,10 @@ module mkCore(CLK, csrf_scounteren_tm_reg } } } } } }), .checkForException(checkForException___d13243)); module_checkForException instance_checkForException_1(.checkForException_dInst({ fetchStage$pipelines_1_first[199:195], - IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d13834, - { fetchStage_pipelines_1_first__3001_BIT_173_383_ETC___d13926, + IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d13844, + { fetchStage_pipelines_1_first__3001_BIT_173_384_ETC___d13936, fetchStage$pipelines_1_first[160], - x_data_imm__h702077 } }), + x_data_imm__h702180 } }), .checkForException_regs({ fetchStage$pipelines_1_first[95], fetchStage$pipelines_1_first[94:89], { fetchStage$pipelines_1_first[88], @@ -19883,10 +19868,10 @@ module mkCore(CLK, .checkForException_csrState({ x_decodeInfo_frm__h662275, r1__read_BITS_13_TO_12___h662460 != 2'd0, - { prv__h745422, - tvm_val__h736422, + { prv__h745525, + tvm_val__h736525, { r1__read_BIT_20___h663156, - tsr_val__h736420, + tsr_val__h736523, { csrf_mcounteren_cy_reg, csrf_mcounteren_cy_reg && csrf_scounteren_cy_reg, @@ -19896,7 +19881,7 @@ module mkCore(CLK, { csrf_mcounteren_tm_reg, csrf_mcounteren_tm_reg && csrf_scounteren_tm_reg } } } } } }), - .checkForException(checkForException___d13948)); + .checkForException(checkForException___d13958)); module_execFpuSimple instance_execFpuSimple_4(.execFpuSimple_fpu_inst({ coreFix_fpuMulDivExe_0_regToExeQ$first[233:229], CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q259, coreFix_fpuMulDivExe_0_regToExeQ$first[225] }), @@ -21776,7 +21761,7 @@ module mkCore(CLK, fetchStage$pipelines_0_first[231:200] == 32'h10500073 && csrf_tw_reg && csrf_prv_reg != 2'd3 ; - assign IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_3023_30_ETC___d14006 = + assign IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_3023_30_ETC___d14016 = IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_3023_30_ETC___d13059[0] || IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_3023_30_ETC___d13059[1] || IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_3023_30_ETC___d13059[2] || @@ -21794,8 +21779,8 @@ module mkCore(CLK, IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_3023_30_ETC___d13059[14] || IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_3023_30_ETC___d13059[15] || checkForException___d13243[4] || - csrf_fs_reg_read__1746_EQ_0_3232_AND_fetchStag_ETC___d13752 ; - assign IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_3023_30_ETC___d14043 = + csrf_fs_reg_read__1746_EQ_0_3232_AND_fetchStag_ETC___d13762 ; + assign IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_3023_30_ETC___d14053 = IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_3023_30_ETC___d13059[0] || IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_3023_30_ETC___d13059[1] || IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_3023_30_ETC___d13059[2] || @@ -21812,8 +21797,8 @@ module mkCore(CLK, IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_3023_30_ETC___d13059[13] || IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_3023_30_ETC___d13059[14] || IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_3023_30_ETC___d13059[15] || - checkForException___d13948[4] || - csrf_fs_reg_read__1746_EQ_0_3232_AND_fetchStag_ETC___d14041 ; + checkForException___d13958[4] || + csrf_fs_reg_read__1746_EQ_0_3232_AND_fetchStag_ETC___d14051 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10052 = (f3_exp__h565371 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9355 ? @@ -22791,44 +22776,44 @@ module mkCore(CLK, coreFix_memExe_dTlb$procResp[12]) ? CASE_coreFix_memExe_dTlbprocResp_BITS_177_TO__ETC__q21 : CASE_coreFix_memExe_dTlbprocResp_BITS_181_TO__ETC__q22 ; - assign IF_NOT_fetchStage_pipelines_0_canDeq__2990_299_ETC___d14158 = + assign IF_NOT_fetchStage_pipelines_0_canDeq__2990_299_ETC___d14168 = ((!fetchStage$pipelines_0_canDeq || - NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d13716) && + NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d13726) && fetchStage$pipelines_1_canDeq) ? fetchStage$RDY_pipelines_1_first && (fetchStage$pipelines_1_first[194:192] != 3'd1 || !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first) && - IF_fetchStage_RDY_pipelines_1_first__3000_AND__ETC___d14155 : + IF_fetchStage_RDY_pipelines_1_first__3000_AND__ETC___d14165 : !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first ; - assign IF_NOT_fetchStage_pipelines_0_canDeq__2990_299_ETC___d14166 = + assign IF_NOT_fetchStage_pipelines_0_canDeq__2990_299_ETC___d14176 = ((!fetchStage$pipelines_0_canDeq || - NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d13716) && + NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d13726) && fetchStage$pipelines_1_canDeq) ? - IF_NOT_fetchStage_pipelines_1_first__3001_BITS_ETC___d14165 : + IF_NOT_fetchStage_pipelines_1_first__3001_BITS_ETC___d14175 : fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d14163 ; - assign IF_NOT_fetchStage_pipelines_1_first__3001_BITS_ETC___d14081 = + NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d14173 ; + assign IF_NOT_fetchStage_pipelines_1_first__3001_BITS_ETC___d14091 = (fetchStage$pipelines_1_first[194:192] == 3'd3 || fetchStage$pipelines_1_first[194:192] == 3'd4) ? - NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14064 : + NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14074 : ((fetchStage$pipelines_1_first[194:192] == 3'd2) ? (!fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first) && - (regRenamingTable_rename_0_canRename__3658_AND__ETC___d14073 || - NOT_regRenamingTable_rename_1_canRename__3780__ETC___d14051) : - _0_OR_NOT_fetchStage_pipelines_1_first__3001_BI_ETC___d14079) ; - assign IF_NOT_fetchStage_pipelines_1_first__3001_BITS_ETC___d14165 = - NOT_fetchStage_pipelines_1_first__3001_BITS_19_ETC___d13989 ? - IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d14152 || + (regRenamingTable_rename_0_canRename__3668_AND__ETC___d14083 || + NOT_regRenamingTable_rename_1_canRename__3790__ETC___d14061) : + _0_OR_NOT_fetchStage_pipelines_1_first__3001_BI_ETC___d14089) ; + assign IF_NOT_fetchStage_pipelines_1_first__3001_BITS_ETC___d14175 = + NOT_fetchStage_pipelines_1_first__3001_BITS_19_ETC___d13999 ? + IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d14162 || fetchStage$pipelines_0_canDeq && (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3658_AND__ETC___d13729 && - IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13739 : + regRenamingTable_rename_0_canRename__3668_AND__ETC___d13739 && + IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13749 : fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d14163 ; + NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d14173 ; assign IF_NOT_renameStage_rg_m_halt_req_3019_BIT_4_30_ETC___d13518 = NOT_renameStage_rg_m_halt_req_3019_BIT_4_3020__ETC___d13337 ? IF_IF_fetchStage_pipelines_0_first__2992_BIT_6_ETC___d13445 : @@ -22886,7 +22871,7 @@ module mkCore(CLK, 4'd9) ? 4'd14 : 4'd15)))))))))) ; - assign IF_NOT_rob_deqPort_1_deq_data__5662_BIT_25_566_ETC___d15996 = + assign IF_NOT_rob_deqPort_1_deq_data__5672_BIT_25_567_ETC___d16006 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[329:325] == 5'd0 || @@ -23121,16 +23106,16 @@ module mkCore(CLK, checkForException___d13243[4] ? CASE_checkForException_3243_BITS_3_TO_0_0_chec_ETC__q234 : 4'd2 ; - assign IF_commitStage_f_rob_data_first__5072_BITS_97__ETC___d15243 = + assign IF_commitStage_f_rob_data_first__5082_BITS_97__ETC___d15253 = { CASE_commitStage_f_rob_dataD_OUT_BITS_97_TO_9_ETC__q249, commitStage_f_rob_data$D_OUT[95:32], 5'h0A, commitStage_f_rob_data$D_OUT[26], 64'hAAAAAAAAAAAAAAAA, - x_prv__h722338, - pc__h722238, - x__h724496, - x__h724688, + x_prv__h722441, + pc__h722341, + x__h724599, + x__h724791, commitStage_commitTrap[164:101] } ; assign IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2388_ETC___d12421 = (coreFix_aluExe_0_dispToRegQ$RDY_first && @@ -24339,10 +24324,10 @@ module mkCore(CLK, coreFix_memExe_respLrScAmoQ_enqReq_rl[64] ; assign IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8 = csrf_minstret_ehr_data_lat_0$whas ? - upd__h736917 : + upd__h737020 : csrf_minstret_ehr_data_rl ; - assign IF_csrf_prv_reg_read__3022_ULE_1_5013_AND_IF_c_ETC___d15237 = - csrf_prv_reg_read__3022_ULE_1_5013_AND_IF_comm_ETC___d15035 ? + assign IF_csrf_prv_reg_read__3022_ULE_1_5023_AND_IF_c_ETC___d15247 = + csrf_prv_reg_read__3022_ULE_1_5023_AND_IF_comm_ETC___d15045 ? { 43'd8192, csrf_mxr_reg, csrf_sum_reg, @@ -24374,73 +24359,73 @@ module mkCore(CLK, 2'd0, csrf_ie_vec_1, csrf_ie_vec_0 } ; - assign IF_fetchStage_RDY_pipelines_0_first__2989_AND__ETC___d13686 = + assign IF_fetchStage_RDY_pipelines_0_first__2989_AND__ETC___d13696 = (fetchStage$RDY_pipelines_0_first && (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3658_AND__ETC___d13680) ? + regRenamingTable_rename_0_canRename__3668_AND__ETC___d13690) ? fetchStage$RDY_pipelines_0_first : !regRenamingTable$rename_0_canRename || fetchStage$RDY_pipelines_0_first ; - assign IF_fetchStage_RDY_pipelines_1_first__3000_AND__ETC___d14083 = + assign IF_fetchStage_RDY_pipelines_1_first__3000_AND__ETC___d14093 = (fetchStage$RDY_pipelines_1_first && (fetchStage$pipelines_1_first[194:192] == 3'd0 || fetchStage$pipelines_1_first[194:192] == 3'd1)) ? (!fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first) && - (SEL_ARR_fetchStage_pipelines_0_canDeq__2990_AN_ETC___d14022 || + (SEL_ARR_fetchStage_pipelines_0_canDeq__2990_AN_ETC___d14032 || fetchStage$pipelines_1_first[194:192] == 3'd1 && - regRenamingTable_rename_0_canRename__3658_AND__ETC___d13743 || - NOT_regRenamingTable_rename_1_canRename__3780__ETC___d14051) : + regRenamingTable_rename_0_canRename__3668_AND__ETC___d13753 || + NOT_regRenamingTable_rename_1_canRename__3790__ETC___d14061) : fetchStage$RDY_pipelines_1_first && - IF_NOT_fetchStage_pipelines_1_first__3001_BITS_ETC___d14081 ; - assign IF_fetchStage_RDY_pipelines_1_first__3000_AND__ETC___d14155 = + IF_NOT_fetchStage_pipelines_1_first__3001_BITS_ETC___d14091 ; + assign IF_fetchStage_RDY_pipelines_1_first__3000_AND__ETC___d14165 = (fetchStage$RDY_pipelines_1_first && - NOT_fetchStage_pipelines_1_first__3001_BITS_19_ETC___d13750 && - NOT_fetchStage_pipelines_1_first__3001_BITS_19_ETC___d13989) ? - IF_fetchStage_RDY_pipelines_1_first__3000_AND__ETC___d14083 && - (IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d14152 || + NOT_fetchStage_pipelines_1_first__3001_BITS_19_ETC___d13760 && + NOT_fetchStage_pipelines_1_first__3001_BITS_19_ETC___d13999) ? + IF_fetchStage_RDY_pipelines_1_first__3000_AND__ETC___d14093 && + (IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d14162 || !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first) : !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first ; - assign IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14204 = - IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14197 || - fetchStage$RDY_pipelines_0_deq && + assign IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14214 = + IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14207 || + rob$RDY_enqPort_0_enq && regRenamingTable$RDY_rename_0_getRename && regRenamingTable$RDY_rename_0_claimRename && - rob$RDY_enqPort_0_enq && + fetchStage$RDY_pipelines_0_deq && (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$RDY_claimSpecTag) ; - assign IF_fetchStage_pipelines_0_first__2992_BIT_160__ETC___d14401 = + assign IF_fetchStage_pipelines_0_first__2992_BIT_160__ETC___d14411 = { fetchStage$pipelines_0_first[159:128], - IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d14389, - IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d14392 ? - IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d14395 : + IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d14399, + IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d14402 ? + IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d14405 : { 1'h0, - IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d14398 } } ; - assign IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d14334 = - IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d14291 && - IF_fetchStage_RDY_pipelines_1_first__3000_AND__ETC___d14083 && - (IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d14318 || - fetchStage$RDY_pipelines_1_deq && + IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d14408 } } ; + assign IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d14344 = + IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d14301 && + IF_fetchStage_RDY_pipelines_1_first__3000_AND__ETC___d14093 && + (IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d14328 || + rob$RDY_enqPort_1_enq && regRenamingTable$RDY_rename_1_getRename && regRenamingTable$RDY_rename_1_claimRename && - rob_RDY_enqPort_1_enq__4320_AND_NOT_fetchStage_ETC___d14328) ; - assign IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d14618 = + fetchStage_RDY_pipelines_1_deq__3004_AND_NOT_f_ETC___d14338) ; + assign IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d14628 = (fetchStage$pipelines_1_first[194:192] == 3'd2 && - NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14553 && - IF_fetchStage_pipelines_1_first__3001_BITS_191_ETC___d14560) ? - IF_fetchStage_pipelines_1_first__3001_BITS_191_ETC___d14561 : + NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14563 && + IF_fetchStage_pipelines_1_first__3001_BITS_191_ETC___d14570) ? + IF_fetchStage_pipelines_1_first__3001_BITS_191_ETC___d14571 : { 1'h0, - IF_fetchStage_pipelines_1_first__3001_BITS_191_ETC___d14562 } ; - assign IF_fetchStage_pipelines_1_first__3001_BIT_160__ETC___d14565 = + IF_fetchStage_pipelines_1_first__3001_BITS_191_ETC___d14572 } ; + assign IF_fetchStage_pipelines_1_first__3001_BIT_160__ETC___d14575 = { fetchStage$pipelines_1_first[159:128], - IF_fetchStage_pipelines_1_first__3001_BITS_191_ETC___d14559, - IF_fetchStage_pipelines_1_first__3001_BITS_191_ETC___d14560 ? - IF_fetchStage_pipelines_1_first__3001_BITS_191_ETC___d14561 : + IF_fetchStage_pipelines_1_first__3001_BITS_191_ETC___d14569, + IF_fetchStage_pipelines_1_first__3001_BITS_191_ETC___d14570 ? + IF_fetchStage_pipelines_1_first__3001_BITS_191_ETC___d14571 : { 1'h0, - IF_fetchStage_pipelines_1_first__3001_BITS_191_ETC___d14562 } } ; + IF_fetchStage_pipelines_1_first__3001_BITS_191_ETC___d14572 } } ; assign IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmio_c_ETC___d339 = mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[142] : @@ -24465,17 +24450,17 @@ module mkCore(CLK, EN_mmioToPlatform_pRs_enq ? mmio_pRsQ_enqReq_lat_0$wget[67] : mmio_pRsQ_enqReq_rl[67] ; - assign IF_rob_deqPort_0_canDeq__5654_THEN_IF_NOT_rob__ETC___d15986 = - rob$deqPort_0_canDeq ? y_avValue_fst__h740440 : 5'd0 ; - assign IF_rob_deqPort_0_canDeq__5654_THEN_IF_NOT_rob__ETC___d16005 = + assign IF_rob_deqPort_0_canDeq__5664_THEN_IF_NOT_rob__ETC___d15996 = + rob$deqPort_0_canDeq ? y_avValue_fst__h740543 : 5'd0 ; + assign IF_rob_deqPort_0_canDeq__5664_THEN_IF_NOT_rob__ETC___d16015 = rob$deqPort_0_canDeq ? - y_avValue_snd_snd_snd_fst__h740915 : + y_avValue_snd_snd_snd_fst__h741018 : 2'd0 ; - assign IF_rob_deqPort_0_deq_data__4651_BITS_329_TO_32_ETC___d15510 = + assign IF_rob_deqPort_0_deq_data__4661_BITS_329_TO_32_ETC___d15520 = (rob$deqPort_0_deq_data[329:325] == 5'd19) ? csrf_sepc_csr : csrf_mepc_csr ; - assign IF_rob_deqPort_0_deq_data__4651_BITS_329_TO_32_ETC___d15620 = + assign IF_rob_deqPort_0_deq_data__4661_BITS_329_TO_32_ETC___d15630 = (rob$deqPort_0_deq_data[329:325] == 5'd19) ? { csrf_mpp_reg, 3'd0, @@ -24495,12 +24480,12 @@ module mkCore(CLK, 1'b0, csrf_ie_vec_1, csrf_ie_vec_0 } ; - assign IF_rob_deqPort_0_deq_data__4651_BITS_97_TO_96__ETC___d14824 = + assign IF_rob_deqPort_0_deq_data__4661_BITS_97_TO_96__ETC___d14834 = { CASE_robdeqPort_0_deq_data_BITS_97_TO_96_0_ro_ETC__q252, rob$deqPort_0_deq_data[95:32] } ; - assign IF_rob_deqPort_1_canDeq__5659_THEN_IF_NOT_rob__ETC___d15997 = + assign IF_rob_deqPort_1_canDeq__5669_THEN_IF_NOT_rob__ETC___d16007 = rob$deqPort_1_canDeq ? - IF_NOT_rob_deqPort_1_deq_data__5662_BIT_25_566_ETC___d15996 : + IF_NOT_rob_deqPort_1_deq_data__5672_BIT_25_567_ETC___d16006 : rob$deqPort_0_canDeq && rob$deqPort_0_deq_data[26] ; assign IF_sfdin04312_BIT_33_THEN_2_ELSE_0__q65 = sfdin__h404312[33] ? 2'd2 : 2'd0 ; @@ -24596,7 +24581,7 @@ module mkCore(CLK, (fetchStage$pipelines_0_first[231:200] != 32'h10500073 || !csrf_tw_reg || csrf_prv_reg == 2'd3) ; - assign NOT_IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_302_ETC___d13673 = + assign NOT_IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_302_ETC___d13683 = !IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_3023_30_ETC___d13059[0] && !IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_3023_30_ETC___d13059[1] && !IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_3023_30_ETC___d13059[2] && @@ -24614,8 +24599,8 @@ module mkCore(CLK, !IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_3023_30_ETC___d13059[14] && !IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_3023_30_ETC___d13059[15] && !checkForException___d13243[4] && - NOT_csrf_fs_reg_read__1746_EQ_0_3232_3233_OR_N_ETC___d13671 ; - assign NOT_IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_302_ETC___d13975 = + NOT_csrf_fs_reg_read__1746_EQ_0_3232_3233_OR_N_ETC___d13681 ; + assign NOT_IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_302_ETC___d13985 = !IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_3023_30_ETC___d13059[0] && !IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_3023_30_ETC___d13059[1] && !IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_3023_30_ETC___d13059[2] && @@ -24632,13 +24617,13 @@ module mkCore(CLK, !IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_3023_30_ETC___d13059[13] && !IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_3023_30_ETC___d13059[14] && !IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_3023_30_ETC___d13059[15] && - !checkForException___d13948[4] && - NOT_csrf_fs_reg_read__1746_EQ_0_3232_3233_OR_N_ETC___d13973 ; - assign NOT_IF_NOT_rob_deqPort_0_canDeq__5654_5655_OR__ETC___d16002 = - (fflags__h743755 & csrf_fflags_reg) != fflags__h743755 || + !checkForException___d13958[4] && + NOT_csrf_fs_reg_read__1746_EQ_0_3232_3233_OR_N_ETC___d13983 ; + assign NOT_IF_NOT_rob_deqPort_0_canDeq__5664_5665_OR__ETC___d16012 = + (fflags__h743858 & csrf_fflags_reg) != fflags__h743858 || csrf_fs_reg != 2'b11 && - (IF_rob_deqPort_1_canDeq__5659_THEN_IF_NOT_rob__ETC___d15997 || - fflags__h743755 != 5'd0) ; + (IF_rob_deqPort_1_canDeq__5669_THEN_IF_NOT_rob__ETC___d16007 || + fflags__h743858 != 5'd0) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10171 = !f2_sfd__h526068[21] && !f2_sfd__h526068[20] && !f2_sfd__h526068[19] && @@ -24760,12 +24745,12 @@ module mkCore(CLK, !f3_sfd__h565372[2] && !f3_sfd__h565372[1] && !f3_sfd__h565372[0] ; - assign NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13734 = - !SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__368_ETC___d13732 && + assign NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13744 = + !SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__369_ETC___d13742 && (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3658_AND__ETC___d13680 ; - assign NOT_commitStage_commitTrap_4659_BIT_36_4906_49_ETC___d14941 = + regRenamingTable_rename_0_canRename__3668_AND__ETC___d13690 ; + assign NOT_commitStage_commitTrap_4669_BIT_36_4916_49_ETC___d14951 = (!commitStage_commitTrap[36] || commitStage_commitTrap[35:32] == 4'd0 || commitStage_commitTrap[35:32] == 4'd1 || @@ -24779,12 +24764,12 @@ module mkCore(CLK, (commitStage_commitTrap[36] || commitStage_commitTrap[35:32] != 4'd3 || CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q243) ; - assign NOT_commitStage_commitTrap_4659_BIT_36_4906_49_ETC___d14948 = - NOT_commitStage_commitTrap_4659_BIT_36_4906_49_ETC___d14941 || + assign NOT_commitStage_commitTrap_4669_BIT_36_4916_49_ETC___d14958 = + NOT_commitStage_commitTrap_4669_BIT_36_4916_49_ETC___d14951 || coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty && fetchStage$iTlbIfc_noPendingReq && coreFix_memExe_dTlb$noPendingReq ; - assign NOT_commitStage_commitTrap_4659_BIT_36_4906_49_ETC___d15012 = + assign NOT_commitStage_commitTrap_4669_BIT_36_4916_49_ETC___d15022 = (!commitStage_commitTrap[36] || commitStage_commitTrap[35:32] != 4'd14) && (!commitStage_commitTrap[36] || @@ -24801,13 +24786,13 @@ module mkCore(CLK, (commitStage_commitTrap[36] || commitStage_commitTrap[35:32] != 4'd3 || CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q243) ; - assign NOT_commitStage_rg_run_state_4657_4658_AND_NOT_ETC___d15321 = + assign NOT_commitStage_rg_run_state_4667_4668_AND_NOT_ETC___d15331 = !commitStage_rg_run_state && !commitStage_commitTrap[165] && !rob$deqPort_0_deq_data[167] && !rob$deqPort_0_deq_data[18] && rob$deqPort_0_deq_data[25] ; - assign NOT_commitStage_rg_run_state_4657_4658_AND_NOT_ETC___d15332 = - NOT_commitStage_rg_run_state_4657_4658_AND_NOT_ETC___d15321 && + assign NOT_commitStage_rg_run_state_4667_4668_AND_NOT_ETC___d15342 = + NOT_commitStage_rg_run_state_4667_4668_AND_NOT_ETC___d15331 && (rob$deqPort_0_deq_data[329:325] == 5'd0 || rob$deqPort_0_deq_data[329:325] == 5'd21 || rob$deqPort_0_deq_data[329:325] == 5'd17 || @@ -24817,9 +24802,9 @@ module mkCore(CLK, rob$deqPort_0_deq_data[329:325] == 5'd15 || rob$deqPort_0_deq_data[329:325] == 5'd19 || rob$deqPort_0_deq_data[329:325] == 5'd20) && - _0b0_CONCAT_csrf_external_int_pend_vec_3_read___ETC___d14636 ; - assign NOT_commitStage_rg_run_state_4657_4658_AND_NOT_ETC___d15708 = - NOT_commitStage_rg_run_state_4657_4658_AND_NOT_ETC___d15321 && + _0b0_CONCAT_csrf_external_int_pend_vec_3_read___ETC___d14646 ; + assign NOT_commitStage_rg_run_state_4667_4668_AND_NOT_ETC___d15718 = + NOT_commitStage_rg_run_state_4667_4668_AND_NOT_ETC___d15331 && rob$deqPort_0_deq_data[329:325] != 5'd0 && rob$deqPort_0_deq_data[329:325] != 5'd21 && rob$deqPort_0_deq_data[329:325] != 5'd17 && @@ -24829,7 +24814,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[329:325] != 5'd15 && rob$deqPort_0_deq_data[329:325] != 5'd19 && rob$deqPort_0_deq_data[329:325] != 5'd20 && - _0b0_CONCAT_csrf_external_int_pend_vec_3_read___ETC___d14636 ; + _0b0_CONCAT_csrf_external_int_pend_vec_3_read___ETC___d14646 ; assign NOT_coreFix_aluExe_0_bypassWire_0_whas__2410_2_ETC___d12437 = (!coreFix_aluExe_0_bypassWire_0$whas || !coreFix_aluExe_0_bypassWire_0_wget__2411_BITS__ETC___d12413) && @@ -25370,7 +25355,7 @@ module mkCore(CLK, NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d13566 && !csrf_prv_reg_read__3022_ULT_IF_fetchStage_pipe_ETC___d13275 && csr_addr__h662590 != 12'h8FF) ; - assign NOT_csrf_fs_reg_read__1746_EQ_0_3232_3233_OR_N_ETC___d13671 = + assign NOT_csrf_fs_reg_read__1746_EQ_0_3232_3233_OR_N_ETC___d13681 = (csrf_fs_reg != 2'd0 || (!fetchStage$pipelines_0_first[95] || !fetchStage$pipelines_0_first[94]) && @@ -25382,7 +25367,7 @@ module mkCore(CLK, (fetchStage$pipelines_0_first[231:200] != 32'h10500073 || !csrf_tw_reg || csrf_prv_reg == 2'd3) ; - assign NOT_csrf_fs_reg_read__1746_EQ_0_3232_3233_OR_N_ETC___d13973 = + assign NOT_csrf_fs_reg_read__1746_EQ_0_3232_3233_OR_N_ETC___d13983 = (csrf_fs_reg != 2'd0 || (!fetchStage$pipelines_1_first[95] || !fetchStage$pipelines_1_first[94]) && @@ -25394,116 +25379,116 @@ module mkCore(CLK, (fetchStage$pipelines_1_first[231:200] != 32'h10500073 || !csrf_tw_reg || csrf_prv_reg == 2'd3) ; - assign NOT_csrf_prv_reg_read__3022_ULE_1_5013_5055_OR_ETC___d15059 = - !csrf_prv_reg_read__3022_ULE_1___d15013 || + assign NOT_csrf_prv_reg_read__3022_ULE_1_5023_5065_OR_ETC___d15069 = + !csrf_prv_reg_read__3022_ULE_1___d15023 || (commitStage_commitTrap[36] ? - !_0b0_CONCAT_csrf_mideleg_11_reg_read__1853_1854_ETC___d15015 : - !_0b0_CONCAT_csrf_medeleg_15_reg_read__1845_1846_ETC___d15033) ; - assign NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d13777 = + !_0b0_CONCAT_csrf_mideleg_11_reg_read__1853_1854_ETC___d15025 : + !_0b0_CONCAT_csrf_medeleg_15_reg_read__1845_1846_ETC___d15043) ; + assign NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d13787 = !fetchStage$pipelines_0_canDeq || !regRenamingTable$rename_0_canRename || - fetchStage_pipelines_0_first__2992_BITS_199_TO_ETC___d13759 || - IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13774 || + fetchStage_pipelines_0_first__2992_BITS_199_TO_ETC___d13769 || + IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13784 || fetchStage$pipelines_0_first[194:192] != 3'd1 ; - assign NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14020 = + assign NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14030 = (!fetchStage$pipelines_0_canDeq || fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || - NOT_regRenamingTable_rename_0_canRename__3658__ETC___d14011 || + NOT_regRenamingTable_rename_0_canRename__3668__ETC___d14021 || fetchStage$pipelines_0_first[194:192] != 3'd0 && fetchStage$pipelines_0_first[194:192] != 3'd1 || - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3689_co_ETC___d13699) && + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3699_co_ETC___d13709) && coreFix_aluExe_1_rsAlu$canEnq && - !coreFix_aluExe_0_rsAlu_approximateCount__3693__ETC___d13695 ; - assign NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14064 = + !coreFix_aluExe_0_rsAlu_approximateCount__3703__ETC___d13705 ; + assign NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14074 = (!fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first) && - (regRenamingTable_rename_0_canRename__3658_AND__ETC___d13729 && + (regRenamingTable_rename_0_canRename__3668_AND__ETC___d13739 && (fetchStage$pipelines_0_first[194:192] == 3'd3 || fetchStage$pipelines_0_first[194:192] == 3'd4) || !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq || - NOT_regRenamingTable_rename_1_canRename__3780__ETC___d14051) ; - assign NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14119 = + NOT_regRenamingTable_rename_1_canRename__3790__ETC___d14061) ; + assign NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14129 = !fetchStage$pipelines_0_canDeq || !regRenamingTable$rename_0_canRename || - fetchStage_pipelines_0_first__2992_BITS_199_TO_ETC___d13759 || + fetchStage_pipelines_0_first__2992_BITS_199_TO_ETC___d13769 || fetchStage$pipelines_0_first[194:192] != 3'd3 && fetchStage$pipelines_0_first[194:192] != 3'd4 ; - assign NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14137 = + assign NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14147 = (!fetchStage$pipelines_0_canDeq || - NOT_regRenamingTable_rename_0_canRename__3658__ETC___d14087 || + NOT_regRenamingTable_rename_0_canRename__3668__ETC___d14097 || fetchStage$pipelines_0_first[194:192] != 3'd2 || - IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13769) && + IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13779) && coreFix_memExe_rsMem$canEnq && CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q238 ; - assign NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14286 = + assign NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14296 = (!fetchStage$pipelines_0_canDeq || - NOT_specTagManager_canClaim__3656_3742_OR_NOT__ETC___d14257) && + NOT_specTagManager_canClaim__3666_3752_OR_NOT__ETC___d14267) && CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q242 && (fetchStage$pipelines_1_first[199:195] == 5'd14 || coreFix_memExe_rsMem$RDY_enq) ; - assign NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14340 = + assign NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14350 = (!fetchStage$pipelines_0_canDeq || - fetchStage_pipelines_0_first__2992_BITS_194_TO_ETC___d14206 && - IF_fetchStage_RDY_pipelines_0_first__2989_AND__ETC___d13686) && + fetchStage_pipelines_0_first__2992_BITS_194_TO_ETC___d14216 && + IF_fetchStage_RDY_pipelines_0_first__2989_AND__ETC___d13696) && fetchStage$RDY_pipelines_0_first && - fetchStage_pipelines_0_canDeq__2990_AND_fetchS_ETC___d14338 ; - assign NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14470 = + fetchStage_pipelines_0_canDeq__2990_AND_fetchS_ETC___d14348 ; + assign NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14480 = (!fetchStage$pipelines_0_canDeq || fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || - NOT_regRenamingTable_rename_0_canRename__3658__ETC___d14465 || + NOT_regRenamingTable_rename_0_canRename__3668__ETC___d14475 || fetchStage$pipelines_0_first[194:192] != 3'd0 && fetchStage$pipelines_0_first[194:192] != 3'd1 || - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3689_co_ETC___d13699) && + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3699_co_ETC___d13709) && coreFix_aluExe_1_rsAlu$canEnq && - !coreFix_aluExe_0_rsAlu_approximateCount__3693__ETC___d13695 ; - assign NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14475 = + !coreFix_aluExe_0_rsAlu_approximateCount__3703__ETC___d13705 ; + assign NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14485 = (!fetchStage$pipelines_0_canDeq || - NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d14347 && - IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13715) && + NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d14357 && + IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13725) && fetchStage$pipelines_1_canDeq ; - assign NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14477 = + assign NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14487 = !fetchStage$pipelines_0_canDeq || !regRenamingTable$rename_0_canRename || - renameStage_rg_m_halt_req_3019_BIT_4_3020_OR_f_ETC___d14170 || - IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13774 || + renameStage_rg_m_halt_req_3019_BIT_4_3020_OR_f_ETC___d14180 || + IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13784 || fetchStage$pipelines_0_first[194:192] != 3'd1 ; - assign NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14489 = - NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14475 && - NOT_fetchStage_pipelines_1_first__3001_BITS_19_ETC___d14486 && + assign NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14499 = + NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14485 && + NOT_fetchStage_pipelines_1_first__3001_BITS_19_ETC___d14496 && (fetchStage$pipelines_1_first[194:192] == 3'd0 || fetchStage$pipelines_1_first[194:192] == 3'd1) && - SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__299_ETC___d14252 ; - assign NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14525 = + SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__299_ETC___d14262 ; + assign NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14535 = !fetchStage$pipelines_0_canDeq || !regRenamingTable$rename_0_canRename || - renameStage_rg_m_halt_req_3019_BIT_4_3020_OR_f_ETC___d14170 || + renameStage_rg_m_halt_req_3019_BIT_4_3020_OR_f_ETC___d14180 || fetchStage$pipelines_0_first[194:192] != 3'd3 && fetchStage$pipelines_0_first[194:192] != 3'd4 ; - assign NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14545 = - NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14475 && - regRenamingTable_rename_1_canRename__3780_AND__ETC___d14485 && + assign NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14555 = + NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14485 && + regRenamingTable_rename_1_canRename__3790_AND__ETC___d14495 && (fetchStage$pipelines_1_first[194:192] == 3'd3 || fetchStage$pipelines_1_first[194:192] == 3'd4) && - NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14525 && + NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14535 && coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq && - NOT_fetchStage_pipelines_1_first__3001_BITS_32_ETC___d14540 ; - assign NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14552 = + NOT_fetchStage_pipelines_1_first__3001_BITS_32_ETC___d14550 ; + assign NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14562 = !fetchStage$pipelines_0_canDeq || !regRenamingTable$rename_0_canRename || - renameStage_rg_m_halt_req_3019_BIT_4_3020_OR_f_ETC___d14170 || + renameStage_rg_m_halt_req_3019_BIT_4_3020_OR_f_ETC___d14180 || fetchStage$pipelines_0_first[194:192] != 3'd2 || - IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13769 ; - assign NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14553 = - NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14552 && + IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13779 ; + assign NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14563 = + NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14562 && coreFix_memExe_rsMem$canEnq && CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q238 ; - assign NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14597 = - NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14477 && + assign NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14607 = + NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14487 && specTagManager$canClaim && - regRenamingTable_rename_1_canRename__3780_AND__ETC___d14485 && - IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d14152 && + regRenamingTable_rename_1_canRename__3790_AND__ETC___d14495 && + IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d14162 && fetchStage$pipelines_1_first[194:192] == 3'd1 ; assign NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d13566 = (fetchStage$pipelines_0_first[194:192] != 3'd0 || @@ -25511,57 +25496,57 @@ module mkCore(CLK, rs1__h662591 == 5'd0 && imm__h662592 == 32'd0 || csr_addr__h662590[11:10] != 2'b11 ; - assign NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d13716 = + assign NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d13726 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3658_AND__ETC___d13680 && - IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13715 ; - assign NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d13996 = + regRenamingTable_rename_0_canRename__3668_AND__ETC___d13690 && + IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13725 ; + assign NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d14006 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3658_AND__ETC___d13680 && - fetchStage_pipelines_0_first__2992_BITS_194_TO_ETC___d13995 ; - assign NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d14002 = + regRenamingTable_rename_0_canRename__3668_AND__ETC___d13690 && + fetchStage_pipelines_0_first__2992_BITS_194_TO_ETC___d14005 ; + assign NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d14012 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3658_AND__ETC___d13680 && + regRenamingTable_rename_0_canRename__3668_AND__ETC___d13690 && (fetchStage$pipelines_0_first[194:192] == 3'd0 || fetchStage$pipelines_0_first[194:192] == 3'd1) && - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3689_co_ETC___d13699 && + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3699_co_ETC___d13709 && (!coreFix_aluExe_0_rsAlu$canEnq || - !coreFix_aluExe_0_rsAlu_approximateCount__3693__ETC___d13695) ; - assign NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d14163 = + !coreFix_aluExe_0_rsAlu_approximateCount__3703__ETC___d13705) ; + assign NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d14173 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3658_AND__ETC___d13680 && - IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13739 ; - assign NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d14347 = + regRenamingTable_rename_0_canRename__3668_AND__ETC___d13690 && + IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13749 ; + assign NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d14357 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && regRenamingTable$rename_0_canRename && !checkForException___d13243[4] && rob$enqPort_0_canEnq ; - assign NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d14447 = + assign NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d14457 = { fetchStage$pipelines_0_first[194:192] != 3'd2 || !coreFix_memExe_rsMem$canEnq || - IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13769 || - IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d14389, + IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13779 || + IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d14399, (fetchStage$pipelines_0_first[194:192] == 3'd2 && coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13711 && - IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d14392) ? - IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d14395 : + IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13721 && + IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d14402) ? + IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d14405 : { 1'h0, - IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d14398 }, + IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d14408 }, 7'd32, specTagManager$currentSpecBits } ; - assign NOT_fetchStage_pipelines_0_first__2992_BITS_32_ETC___d14371 = + assign NOT_fetchStage_pipelines_0_first__2992_BITS_32_ETC___d14381 = fetchStage$pipelines_0_first[323:260] != - fallthrough_pc__h674338 ; - assign NOT_fetchStage_pipelines_0_first__2992_BIT_68__ETC___d13727 = + fallthrough_pc__h674441 ; + assign NOT_fetchStage_pipelines_0_first__2992_BIT_68__ETC___d13737 = !fetchStage$pipelines_0_first[68] && !checkForException___d13243[4] && - NOT_csrf_fs_reg_read__1746_EQ_0_3232_3233_OR_N_ETC___d13671 && + NOT_csrf_fs_reg_read__1746_EQ_0_3232_3233_OR_N_ETC___d13681 && rob$enqPort_0_canEnq && epochManager$checkEpoch_0_check ; assign NOT_fetchStage_pipelines_1_canDeq__2998_2999_O_ETC___d13007 = @@ -25569,39 +25554,39 @@ module mkCore(CLK, fetchStage$RDY_pipelines_1_first && (epochManager$checkEpoch_1_check || fetchStage$RDY_pipelines_1_deq) ; - assign NOT_fetchStage_pipelines_1_first__3001_BITS_19_ETC___d13750 = + assign NOT_fetchStage_pipelines_1_first__3001_BITS_19_ETC___d13760 = (fetchStage$pipelines_1_first[194:192] != 3'd1 || !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first) && (fetchStage$RDY_pipelines_0_first && fetchStage$pipelines_1_first[194:192] == 3'd1 && - regRenamingTable_rename_0_canRename__3658_AND__ETC___d13743 || - csrf_rg_dcsr_read__1920_BIT_2_3297_OR_NOT_fetc_ETC___d13748) ; - assign NOT_fetchStage_pipelines_1_first__3001_BITS_19_ETC___d13989 = + regRenamingTable_rename_0_canRename__3668_AND__ETC___d13753 || + csrf_rg_dcsr_read__1920_BIT_2_3297_OR_NOT_fetc_ETC___d13758) ; + assign NOT_fetchStage_pipelines_1_first__3001_BITS_19_ETC___d13999 = (fetchStage$pipelines_1_first[194:192] != 3'd1 || - NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d13777 && + NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d13787 && specTagManager$canClaim) && - regRenamingTable_rename_1_canRename__3780_AND__ETC___d13988 ; - assign NOT_fetchStage_pipelines_1_first__3001_BITS_19_ETC___d14106 = + regRenamingTable_rename_1_canRename__3790_AND__ETC___d13998 ; + assign NOT_fetchStage_pipelines_1_first__3001_BITS_19_ETC___d14116 = (fetchStage$pipelines_1_first[194:192] != 3'd1 || (!fetchStage$pipelines_0_canDeq || - NOT_regRenamingTable_rename_0_canRename__3658__ETC___d14087 || - IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14100 || + NOT_regRenamingTable_rename_0_canRename__3668__ETC___d14097 || + IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14110 || fetchStage$pipelines_0_first[194:192] != 3'd1) && specTagManager$canClaim) && - regRenamingTable_rename_1_canRename__3780_AND__ETC___d13988 ; - assign NOT_fetchStage_pipelines_1_first__3001_BITS_19_ETC___d14486 = + regRenamingTable_rename_1_canRename__3790_AND__ETC___d13998 ; + assign NOT_fetchStage_pipelines_1_first__3001_BITS_19_ETC___d14496 = (fetchStage$pipelines_1_first[194:192] != 3'd1 || - NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14477 && + NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14487 && specTagManager$canClaim) && - regRenamingTable_rename_1_canRename__3780_AND__ETC___d14485 ; - assign NOT_fetchStage_pipelines_1_first__3001_BITS_32_ETC___d14540 = + regRenamingTable_rename_1_canRename__3790_AND__ETC___d14495 ; + assign NOT_fetchStage_pipelines_1_first__3001_BITS_32_ETC___d14550 = fetchStage$pipelines_1_first[323:260] != - fallthrough_pc__h690846 ; - assign NOT_fetchStage_pipelines_1_first__3001_BIT_68__ETC___d14483 = + fallthrough_pc__h690949 ; + assign NOT_fetchStage_pipelines_1_first__3001_BIT_68__ETC___d14493 = !fetchStage$pipelines_1_first[68] && - !checkForException___d13948[4] && - NOT_csrf_fs_reg_read__1746_EQ_0_3232_3233_OR_N_ETC___d13973 && + !checkForException___d13958[4] && + NOT_csrf_fs_reg_read__1746_EQ_0_3232_3233_OR_N_ETC___d13983 && rob$enqPort_1_canEnq && epochManager$checkEpoch_1_check && !csrf_rg_dcsr[2] ; @@ -25684,7 +25669,7 @@ module mkCore(CLK, (mmio_pRsQ_deqReq_dummy2_2$Q_OUT && (mmio_pRsQ_deqReq_lat_0$whas || mmio_pRsQ_deqReq_rl) || mmio_pRsQ_empty) ; - assign NOT_regRenamingTable_rename_0_canRename__3658__ETC___d14011 = + assign NOT_regRenamingTable_rename_0_canRename__3668__ETC___d14021 = !regRenamingTable$rename_0_canRename || fetchStage$pipelines_0_first[199:195] == 5'd0 || fetchStage$pipelines_0_first[199:195] == 5'd21 || @@ -25695,8 +25680,8 @@ module mkCore(CLK, fetchStage$pipelines_0_first[199:195] == 5'd15 || fetchStage$pipelines_0_first[199:195] == 5'd19 || fetchStage$pipelines_0_first[199:195] == 5'd20 || - renameStage_rg_m_halt_req_3019_BIT_4_3020_OR_f_ETC___d14009 ; - assign NOT_regRenamingTable_rename_0_canRename__3658__ETC___d14087 = + renameStage_rg_m_halt_req_3019_BIT_4_3020_OR_f_ETC___d14019 ; + assign NOT_regRenamingTable_rename_0_canRename__3668__ETC___d14097 = !regRenamingTable$rename_0_canRename || fetchStage$pipelines_0_first[199:195] == 5'd0 || fetchStage$pipelines_0_first[199:195] == 5'd21 || @@ -25707,14 +25692,14 @@ module mkCore(CLK, fetchStage$pipelines_0_first[199:195] == 5'd15 || fetchStage$pipelines_0_first[199:195] == 5'd19 || fetchStage$pipelines_0_first[199:195] == 5'd20 || - fetchStage_pipelines_0_first__2992_BIT_68_3021_ETC___d14085 ; - assign NOT_regRenamingTable_rename_0_canRename__3658__ETC___d14465 = + fetchStage_pipelines_0_first__2992_BIT_68_3021_ETC___d14095 ; + assign NOT_regRenamingTable_rename_0_canRename__3668__ETC___d14475 = !regRenamingTable$rename_0_canRename || renameStage_rg_m_halt_req[4] || fetchStage$pipelines_0_first[68] || checkForException___d13243[4] || !rob$enqPort_0_canEnq ; - assign NOT_regRenamingTable_rename_1_canRename__3780__ETC___d14051 = + assign NOT_regRenamingTable_rename_1_canRename__3790__ETC___d14061 = !regRenamingTable$rename_1_canRename || fetchStage$pipelines_1_first[199:195] == 5'd0 || fetchStage$pipelines_1_first[199:195] == 5'd21 || @@ -25725,7 +25710,7 @@ module mkCore(CLK, fetchStage$pipelines_1_first[199:195] == 5'd15 || fetchStage$pipelines_1_first[199:195] == 5'd19 || fetchStage$pipelines_1_first[199:195] == 5'd20 || - renameStage_rg_m_halt_req_3019_BIT_4_3020_OR_f_ETC___d14049 ; + renameStage_rg_m_halt_req_3019_BIT_4_3020_OR_f_ETC___d14059 ; assign NOT_renameStage_rg_m_halt_req_3019_BIT_4_3020__ETC___d13337 = !renameStage_rg_m_halt_req[4] && (fetchStage$pipelines_0_first[68] || @@ -25745,38 +25730,38 @@ module mkCore(CLK, !IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_3023_30_ETC___d13059[13] && !IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_3023_30_ETC___d13059[14] && !IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_3023_30_ETC___d13059[15]) ; - assign NOT_renameStage_rg_m_halt_req_3019_BIT_4_3020__ETC___d13678 = + assign NOT_renameStage_rg_m_halt_req_3019_BIT_4_3020__ETC___d13688 = !renameStage_rg_m_halt_req[4] && !fetchStage$pipelines_0_first[68] && - NOT_IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_302_ETC___d13673 && + NOT_IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_302_ETC___d13683 && rob$enqPort_0_canEnq && epochManager$checkEpoch_0_check ; - assign NOT_renameStage_rg_m_halt_req_3019_BIT_4_3020__ETC___d13986 = + assign NOT_renameStage_rg_m_halt_req_3019_BIT_4_3020__ETC___d13996 = !renameStage_rg_m_halt_req[4] && !fetchStage$pipelines_1_first[68] && - NOT_IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_302_ETC___d13975 && + NOT_IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_302_ETC___d13985 && rob$enqPort_1_canEnq && - epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13984 ; - assign NOT_renameStage_rg_m_halt_req_3019_BIT_4_3020__ETC___d14128 = + epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13994 ; + assign NOT_renameStage_rg_m_halt_req_3019_BIT_4_3020__ETC___d14138 = !renameStage_rg_m_halt_req[4] && !fetchStage$pipelines_1_first[68] && - NOT_IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_302_ETC___d13975 && + NOT_IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_302_ETC___d13985 && rob$enqPort_1_canEnq && - epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d14126 ; - assign NOT_renameStage_rg_m_halt_req_3019_BIT_4_3020__ETC___d14146 = + epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d14136 ; + assign NOT_renameStage_rg_m_halt_req_3019_BIT_4_3020__ETC___d14156 = !renameStage_rg_m_halt_req[4] && !fetchStage$pipelines_1_first[68] && - NOT_IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_302_ETC___d13975 && + NOT_IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_302_ETC___d13985 && rob$enqPort_1_canEnq && - epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d14144 ; - assign NOT_rob_deqPort_0_canDeq__5654_5655_OR_regRena_ETC___d15696 = + epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d14154 ; + assign NOT_rob_deqPort_0_canDeq__5664_5665_OR_rob_RDY_ETC___d15706 = (!rob$deqPort_0_canDeq || - regRenamingTable$RDY_commit_0_commit && rob$RDY_deqPort_0_deq && + rob$RDY_deqPort_0_deq && regRenamingTable$RDY_commit_0_commit && v_f_to_TV_0$FULL_N) && (!rob$deqPort_1_canDeq || rob$RDY_deqPort_1_deq_data && - NOT_rob_deqPort_1_deq_data__5662_BIT_25_5663_5_ETC___d15693) ; - assign NOT_rob_deqPort_0_canDeq__5654_5655_OR_rob_deq_ETC___d15980 = + NOT_rob_deqPort_1_deq_data__5672_BIT_25_5673_5_ETC___d15703) ; + assign NOT_rob_deqPort_0_canDeq__5664_5665_OR_rob_deq_ETC___d15990 = (!rob$deqPort_0_canDeq || rob$deqPort_0_deq_data[25] && !rob$deqPort_0_deq_data[18] && !rob$deqPort_0_deq_data[167] && @@ -25790,15 +25775,15 @@ module mkCore(CLK, rob$deqPort_0_deq_data[329:325] != 5'd19 && rob$deqPort_0_deq_data[329:325] != 5'd20) && rob$deqPort_1_canDeq ; - assign NOT_rob_deqPort_0_deq_data__4651_BITS_329_TO_3_ETC___d15310 = + assign NOT_rob_deqPort_0_deq_data__4661_BITS_329_TO_3_ETC___d15320 = rob$deqPort_0_deq_data[329:325] != 5'd13 || - (IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 != + (IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 != 6'd7 || csrf_stats_module_writeQ$FULL_N) && - (IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 != + (IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 != 6'd6 || csrf_terminate_module_terminateQ$FULL_N) ; - assign NOT_rob_deqPort_1_deq_data__5662_BIT_25_5663_5_ETC___d15693 = + assign NOT_rob_deqPort_1_deq_data__5672_BIT_25_5673_5_ETC___d15703 = !rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[329:325] == 5'd0 || @@ -25810,20 +25795,20 @@ module mkCore(CLK, rob$deqPort_1_deq_data[329:325] == 5'd15 || rob$deqPort_1_deq_data[329:325] == 5'd19 || rob$deqPort_1_deq_data[329:325] == 5'd20 || - regRenamingTable$RDY_commit_1_commit && rob$RDY_deqPort_1_deq && + rob$RDY_deqPort_1_deq && regRenamingTable$RDY_commit_1_commit && v_f_to_TV_1$FULL_N ; - assign NOT_specTagManager_canClaim__3656_3742_OR_NOT__ETC___d14257 = + assign NOT_specTagManager_canClaim__3666_3752_OR_NOT__ETC___d14267 = !specTagManager$canClaim || !regRenamingTable$rename_0_canRename || - fetchStage_pipelines_0_first__2992_BITS_199_TO_ETC___d13759 || - IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14197 || + fetchStage_pipelines_0_first__2992_BITS_199_TO_ETC___d13769 || + IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14207 || fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$RDY_nextSpecTag ; - assign NOT_specTagManager_canClaim__3656_3742_OR_NOT__ETC___d14324 = + assign NOT_specTagManager_canClaim__3666_3752_OR_NOT__ETC___d14334 = !specTagManager$canClaim || !regRenamingTable$rename_0_canRename || - renameStage_rg_m_halt_req_3019_BIT_4_3020_OR_f_ETC___d14170 || - IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14197 || + renameStage_rg_m_halt_req_3019_BIT_4_3020_OR_f_ETC___d14180 || + IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14207 || fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$RDY_nextSpecTag ; assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3017 = @@ -25844,21 +25829,21 @@ module mkCore(CLK, !CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q268, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3035, x__h295973 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16418 = + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16428 = { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q270, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q271, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q272 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16374 = + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16384 = { CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q253, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q254, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q255, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q256 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16383 = - { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16374, + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16393 = + { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16384, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q257, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q258 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16392 = - { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16383, + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16402 = + { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16393, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q262, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q263 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10246 = @@ -26255,19 +26240,19 @@ module mkCore(CLK, 1'd0, csrf_timer_int_en_vec_1 & csrf_timer_int_pend_vec_1, 1'd0 } ; - assign _0_OR_NOT_fetchStage_pipelines_0_first__2992_BI_ETC___d14178 = + assign _0_OR_NOT_fetchStage_pipelines_0_first__2992_BI_ETC___d14188 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$RDY_nextSpecTag) && - CASE_k78117_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239 ; - assign _0_OR_NOT_fetchStage_pipelines_1_first__3001_BI_ETC___d14079 = + CASE_k78220_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q240 ; + assign _0_OR_NOT_fetchStage_pipelines_1_first__3001_BI_ETC___d14089 = (fetchStage$pipelines_1_first[194:192] != 3'd1 || !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first) && (fetchStage$RDY_pipelines_0_first && fetchStage$pipelines_1_first[194:192] == 3'd1 && - regRenamingTable_rename_0_canRename__3658_AND__ETC___d13743 || - NOT_regRenamingTable_rename_1_canRename__3780__ETC___d14051) ; - assign _0_OR_NOT_fetchStage_pipelines_1_first__3001_BI_ETC___d14270 = + regRenamingTable_rename_0_canRename__3668_AND__ETC___d13753 || + NOT_regRenamingTable_rename_1_canRename__3790__ETC___d14061) ; + assign _0_OR_NOT_fetchStage_pipelines_1_first__3001_BI_ETC___d14280 = (fetchStage$pipelines_1_first[194:192] != 3'd1 || specTagManager$RDY_nextSpecTag) && CASE_fetchStage_pipelines_0_canDeq__2990_AND_N_ETC__q241 ; @@ -26295,12 +26280,12 @@ module mkCore(CLK, (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7438[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7438) ; - assign _0b0_CONCAT_csrf_external_int_pend_vec_3_read___ETC___d14636 = + assign _0b0_CONCAT_csrf_external_int_pend_vec_3_read___ETC___d14646 = mip_csr__read__h617592 == commitStage_rg_old_mip_csr_val ; - assign _0b0_CONCAT_csrf_medeleg_15_reg_read__1845_1846_ETC___d15033 = - medeleg_csr__read__h616711[i__h719309] ; - assign _0b0_CONCAT_csrf_mideleg_11_reg_read__1853_1854_ETC___d15015 = - mideleg_csr__read__h616806[i__h719469] ; + assign _0b0_CONCAT_csrf_medeleg_15_reg_read__1845_1846_ETC___d15043 = + medeleg_csr__read__h616711[i__h719412] ; + assign _0b0_CONCAT_csrf_mideleg_11_reg_read__1853_1854_ETC___d15025 = + mideleg_csr__read__h616806[i__h719572] ; assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4111 = 12'd3074 - { 6'd0, @@ -26888,63 +26873,63 @@ module mkCore(CLK, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7435 ; assign _dfoo12 = fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3658_AND__ETC___d14385 || - NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14475 && - regRenamingTable_rename_1_canRename__3780_AND__ETC___d14485 && + regRenamingTable_rename_0_canRename__3668_AND__ETC___d14395 || + NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14485 && + regRenamingTable_rename_1_canRename__3790_AND__ETC___d14495 && fetchStage$pipelines_1_first[194:192] == 3'd2 && - NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14553 && + NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14563 && fetchStage$pipelines_1_first[199:195] != 5'd14 ; assign _dfoo16 = - k__h678117 == 1'd1 && - fetchStage_pipelines_0_canDeq__2990_AND_NOT_fe_ETC___d14350 || - (fetchStage_pipelines_0_canDeq__2990_AND_NOT_fe_ETC___d14457 || - NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14470) == + k__h678220 == 1'd1 && + fetchStage_pipelines_0_canDeq__2990_AND_NOT_fe_ETC___d14360 || + (fetchStage_pipelines_0_canDeq__2990_AND_NOT_fe_ETC___d14467 || + NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14480) == 1'd1 && - NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14489 ; + NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14499 ; assign _dfoo18 = - k__h678117 == 1'd0 && - fetchStage_pipelines_0_canDeq__2990_AND_NOT_fe_ETC___d14350 || - (fetchStage_pipelines_0_canDeq__2990_AND_NOT_fe_ETC___d14457 || - NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14470) == + k__h678220 == 1'd0 && + fetchStage_pipelines_0_canDeq__2990_AND_NOT_fe_ETC___d14360 || + (fetchStage_pipelines_0_canDeq__2990_AND_NOT_fe_ETC___d14467 || + NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14480) == 1'd0 && - NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14489 ; + NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14499 ; assign _dfoo2 = fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3658_AND__ETC___d14427 || - NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14475 && - regRenamingTable_rename_1_canRename__3780_AND__ETC___d14485 && + regRenamingTable_rename_0_canRename__3668_AND__ETC___d14437 || + NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14485 && + regRenamingTable_rename_1_canRename__3790_AND__ETC___d14495 && fetchStage$pipelines_1_first[194:192] == 3'd2 && - NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14553 && + NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14563 && fetchStage$pipelines_1_first[191:189] != 3'd0 && fetchStage$pipelines_1_first[191:189] != 3'd2 ; assign _dfoo20 = - commitStage_commitTrap_4659_BIT_36_4906_AND_co_ETC___d14971 || - NOT_commitStage_commitTrap_4659_BIT_36_4906_49_ETC___d15012 ; + commitStage_commitTrap_4669_BIT_36_4916_AND_co_ETC___d14981 || + NOT_commitStage_commitTrap_4669_BIT_36_4916_49_ETC___d15022 ; assign _dfoo24 = rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd40 || rob$deqPort_0_deq_data[329:325] == 5'd19 || rob$deqPort_0_deq_data[329:325] == 5'd20 ; assign _dfoo26 = rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd18 || rob$deqPort_0_deq_data[329:325] == 5'd20 ; assign _dfoo32 = rob$deqPort_0_deq_data[329:325] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + (IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd8 || - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd18) || rob$deqPort_0_deq_data[329:325] == 5'd19 ; assign _dfoo7 = fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3658_AND__ETC___d14419 || - NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14475 && - regRenamingTable_rename_1_canRename__3780_AND__ETC___d14485 && + regRenamingTable_rename_0_canRename__3668_AND__ETC___d14429 || + NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14485 && + regRenamingTable_rename_1_canRename__3790_AND__ETC___d14495 && fetchStage$pipelines_1_first[194:192] == 3'd2 && - NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14553 && + NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14563 && (fetchStage$pipelines_1_first[191:189] == 3'd0 || fetchStage$pipelines_1_first[191:189] == 3'd2) ; assign _dor1coreFix_aluExe_0_bypassWire_2$EN_wset = @@ -29811,11 +29796,11 @@ module mkCore(CLK, assign b__h608143 = { {64{b__h607920[63]}}, b__h607920 } ; assign b__h608244 = { 64'd0, a__h607919 } ; assign b__h608256 = { 64'd0, b__h607920 } ; - assign base__h722254 = { csrf_stvec_base_hi_reg, 2'b0 } ; - assign base__h722274 = { csrf_mtvec_base_hi_reg, 2'b0 } ; - assign cause_code__h719294 = - commitStage_commitTrap[36] ? i__h719469 : i__h719309 ; - assign commitStage_commitTrap_4659_BIT_36_4906_AND_co_ETC___d14971 = + assign base__h722357 = { csrf_stvec_base_hi_reg, 2'b0 } ; + assign base__h722377 = { csrf_mtvec_base_hi_reg, 2'b0 } ; + assign cause_code__h719397 = + commitStage_commitTrap[36] ? i__h719572 : i__h719412 ; + assign commitStage_commitTrap_4669_BIT_36_4916_AND_co_ETC___d14981 = commitStage_commitTrap[36] && commitStage_commitTrap[35:32] != 4'd0 && commitStage_commitTrap[35:32] != 4'd1 && @@ -29829,15 +29814,15 @@ module mkCore(CLK, !commitStage_commitTrap[36] && commitStage_commitTrap[35:32] == 4'd3 && CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q244 ; - assign commitStage_f_rob_data_first__5072_BIT_167_517_ETC___d15244 = + assign commitStage_f_rob_data_first__5082_BIT_167_518_ETC___d15254 = { commitStage_f_rob_data$D_OUT[167:166], commitStage_f_rob_data$D_OUT[166] ? CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q250 : CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q251, - trap_val__h719295, - IF_commitStage_f_rob_data_first__5072_BITS_97__ETC___d15243 } ; - assign commitStage_rg_serial_num_4640_PLUS_IF_rob_deq_ETC___d15776 = - commitStage_rg_serial_num + y__h740902 ; + trap_val__h719398, + IF_commitStage_f_rob_data_first__5082_BITS_97__ETC___d15253 } ; + assign commitStage_rg_serial_num_4650_PLUS_IF_rob_deq_ETC___d15786 = + commitStage_rg_serial_num + y__h741005 ; assign coreFix_aluExe_0_bypassWire_0_wget__2411_BITS__ETC___d12413 = coreFix_aluExe_0_bypassWire_0$wget[70:64] == coreFix_aluExe_0_dispToRegQ$first[84:78] ; @@ -29879,7 +29864,7 @@ module mkCore(CLK, (coreFix_aluExe_0_exeToFinQ$first[326:322] != 5'd9 && coreFix_aluExe_0_exeToFinQ$first[326:322] != 5'd10 || coreFix_trainBPQ_0$FULL_N) ; - assign coreFix_aluExe_0_rsAlu_approximateCount__3693__ETC___d13695 = + assign coreFix_aluExe_0_rsAlu_approximateCount__3703__ETC___d13705 = coreFix_aluExe_0_rsAlu$approximateCount < coreFix_aluExe_1_rsAlu$approximateCount ; assign coreFix_aluExe_1_bypassWire_0_wget__1523_BITS__ETC___d11525 = @@ -30072,11 +30057,11 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107:76] ; assign coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q12 = coreFix_fpuMulDivExe_0_regToExeQ$first[171:140] ; - assign coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__41_ETC___d14277 = + assign coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__41_ETC___d14287 = coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_enq && regRenamingTable$RDY_rename_1_getRename && (!fetchStage$pipelines_0_canDeq || - NOT_specTagManager_canClaim__3656_3742_OR_NOT__ETC___d14257) ; + NOT_specTagManager_canClaim__3666_3752_OR_NOT__ETC___d14267) ; assign coreFix_memExe_bypassWire_0_wget__586_BITS_70__ETC___d1588 = coreFix_aluExe_0_bypassWire_0$wget[70:64] == coreFix_memExe_dispToRegQ$first[61:55] ; @@ -30459,7 +30444,7 @@ module mkCore(CLK, !coreFix_memExe_respLrScAmoQ_deqReq_lat_0$whas && !coreFix_memExe_respLrScAmoQ_deqReq_rl) && coreFix_memExe_respLrScAmoQ_full ; - assign coreFix_memExe_stb_isEmpty__011_AND_coreFix_me_ETC___d14973 = + assign coreFix_memExe_stb_isEmpty__011_AND_coreFix_me_ETC___d14983 = coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty && v_f_to_TV_0$FULL_N && fetchStage$iTlbIfc_noPendingReq && @@ -30481,7 +30466,7 @@ module mkCore(CLK, (fetchStage_pipelines_0_first__2992_BITS_194_TO_ETC___d13273 || csrf_prv_reg_read__3022_ULT_IF_fetchStage_pipe_ETC___d13275 || csr_addr__h662590 == 12'h8FF) ; - assign csrf_fs_reg_read__1746_EQ_0_3232_AND_fetchStag_ETC___d13752 = + assign csrf_fs_reg_read__1746_EQ_0_3232_AND_fetchStag_ETC___d13762 = csrf_fs_reg == 2'd0 && (fetchStage$pipelines_0_first[95] && fetchStage$pipelines_0_first[94] || @@ -30493,7 +30478,7 @@ module mkCore(CLK, fetchStage$pipelines_0_first[231:200] == 32'h10500073 && csrf_tw_reg && csrf_prv_reg != 2'd3 ; - assign csrf_fs_reg_read__1746_EQ_0_3232_AND_fetchStag_ETC___d14041 = + assign csrf_fs_reg_read__1746_EQ_0_3232_AND_fetchStag_ETC___d14051 = csrf_fs_reg == 2'd0 && (fetchStage$pipelines_1_first[95] && fetchStage$pipelines_1_first[94] || @@ -30505,18 +30490,18 @@ module mkCore(CLK, fetchStage$pipelines_1_first[231:200] == 32'h10500073 && csrf_tw_reg && csrf_prv_reg != 2'd3 ; - assign csrf_prv_reg_read__3022_ULE_1_5013_AND_IF_comm_ETC___d15035 = - csrf_prv_reg_read__3022_ULE_1___d15013 && + assign csrf_prv_reg_read__3022_ULE_1_5023_AND_IF_comm_ETC___d15045 = + csrf_prv_reg_read__3022_ULE_1___d15023 && (commitStage_commitTrap[36] ? - _0b0_CONCAT_csrf_mideleg_11_reg_read__1853_1854_ETC___d15015 : - _0b0_CONCAT_csrf_medeleg_15_reg_read__1845_1846_ETC___d15033) ; - assign csrf_prv_reg_read__3022_ULE_1___d15013 = csrf_prv_reg <= 2'd1 ; + _0b0_CONCAT_csrf_mideleg_11_reg_read__1853_1854_ETC___d15025 : + _0b0_CONCAT_csrf_medeleg_15_reg_read__1845_1846_ETC___d15043) ; + assign csrf_prv_reg_read__3022_ULE_1___d15023 = csrf_prv_reg <= 2'd1 ; assign csrf_prv_reg_read__3022_ULT_IF_fetchStage_pipe_ETC___d13275 = csrf_prv_reg < csr_addr__h662590[9:8] ; - assign csrf_rg_dcsr_read__1920_BIT_2_3297_OR_NOT_fetc_ETC___d13748 = + assign csrf_rg_dcsr_read__1920_BIT_2_3297_OR_NOT_fetc_ETC___d13758 = csrf_rg_dcsr[2] || !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first && - IF_fetchStage_RDY_pipelines_0_first__2989_AND__ETC___d13686 ; + IF_fetchStage_RDY_pipelines_0_first__2989_AND__ETC___d13696 ; assign data78998_BITS_31_TO_0__q11 = data__h478998[31:0] ; assign data79892_BITS_31_TO_0__q14 = data__h479892[31:0] ; assign data___1__h479510 = @@ -30535,7 +30520,7 @@ module mkCore(CLK, 2'd2) ? x_quotient__h479694 : x_remainder__h479695 ; - assign dcsr_cause__h718813 = + assign dcsr_cause__h718916 = (commitStage_commitTrap[36] && commitStage_commitTrap[35:32] == 4'd14) ? 3'd3 : @@ -30577,27 +30562,27 @@ module mkCore(CLK, assign enabled_ints__h658952 = pend_ints__h658379 & { r1__read_BITS_13_TO_0___h658928, csrf_mideleg_1_0_reg } ; - assign epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13984 = + assign epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13994 = epochManager$checkEpoch_1_check && !csrf_rg_dcsr[2] && (!fetchStage$pipelines_0_canDeq || (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3658_AND__ETC___d13729 && - IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13715) ; - assign epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d14126 = + regRenamingTable_rename_0_canRename__3668_AND__ETC___d13739 && + IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13725) ; + assign epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d14136 = epochManager$checkEpoch_1_check && !csrf_rg_dcsr[2] && (!fetchStage$pipelines_0_canDeq || (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3658_AND__ETC___d13729 && - IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14122) ; - assign epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d14144 = + regRenamingTable_rename_0_canRename__3668_AND__ETC___d13739 && + IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14132) ; + assign epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d14154 = epochManager$checkEpoch_1_check && !csrf_rg_dcsr[2] && (!fetchStage$pipelines_0_canDeq || (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3658_AND__ETC___d13729 && - IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14140) ; + regRenamingTable_rename_0_canRename__3668_AND__ETC___d13739 && + IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14150) ; assign f1_exp87073_MINUS_127__q136 = f1_exp__h487073 - 8'd127 ; assign f1_exp__h487073 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == @@ -30629,99 +30614,97 @@ module mkCore(CLK, (coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] : 23'd4194304 ; - assign f_csr_rsps_i_notFull__6112_AND_f_csr_reqs_firs_ETC___d16215 = + assign f_csr_rsps_i_notFull__6122_AND_f_csr_reqs_firs_ETC___d16225 = f_csr_rsps$FULL_N && (f_csr_reqs$D_OUT[75:64] != 12'd2049 || csrf_stats_module_writeQ$FULL_N) && (f_csr_reqs$D_OUT[75:64] != 12'd2048 || csrf_terminate_module_terminateQ$FULL_N) ; - assign fallthrough_pc__h674338 = + assign fallthrough_pc__h674441 = (fetchStage$pipelines_0_first[97:96] == 2'b11) ? fetchStage$pipelines_0_first[387:324] + 64'd4 : fetchStage$pipelines_0_first[387:324] + 64'd2 ; - assign fallthrough_pc__h690846 = + assign fallthrough_pc__h690949 = (fetchStage$pipelines_1_first[97:96] == 2'b11) ? fetchStage$pipelines_1_first[387:324] + 64'd4 : fetchStage$pipelines_1_first[387:324] + 64'd2 ; assign fcsr_csr__read__h615717 = { 56'd0, x__h619375 } ; - assign fetchStage_RDY_pipelines_0_first__2989_AND_epo_ETC___d13544 = - fetchStage$RDY_pipelines_0_first && - epochManager$RDY_incrementEpoch && - regRenamingTable$RDY_rename_0_getRename && - regRenamingTable$RDY_rename_0_claimRename && - rob$RDY_enqPort_0_enq && - (fetchStage$pipelines_0_first[194:192] != 3'd0 || - coreFix_aluExe_0_rsAlu$RDY_enq) ; - assign fetchStage_pipelines_0_canDeq__2990_AND_NOT_fe_ETC___d14268 = + assign fetchStage_RDY_pipelines_1_deq__3004_AND_NOT_f_ETC___d14338 = + fetchStage$RDY_pipelines_1_deq && + (!fetchStage$pipelines_0_canDeq || + NOT_specTagManager_canClaim__3666_3752_OR_NOT__ETC___d14334) && + (fetchStage$pipelines_1_first[194:192] != 3'd1 || + specTagManager$RDY_claimSpecTag) ; + assign fetchStage_pipelines_0_canDeq__2990_AND_NOT_fe_ETC___d14278 = fetchStage$pipelines_0_canDeq && (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3658_AND__ETC___d13729 && - fetchStage_pipelines_0_first__2992_BITS_194_TO_ETC___d13995 || + regRenamingTable_rename_0_canRename__3668_AND__ETC___d13739 && + fetchStage_pipelines_0_first__2992_BITS_194_TO_ETC___d14005 || !coreFix_aluExe_0_rsAlu$canEnq || (!fetchStage$pipelines_0_canDeq || - fetchStage_pipelines_0_first__2992_BITS_194_TO_ETC___d14264) && + fetchStage_pipelines_0_first__2992_BITS_194_TO_ETC___d14274) && coreFix_aluExe_1_rsAlu$canEnq && - !coreFix_aluExe_0_rsAlu_approximateCount__3693__ETC___d13695 ; - assign fetchStage_pipelines_0_canDeq__2990_AND_NOT_fe_ETC___d14350 = + !coreFix_aluExe_0_rsAlu_approximateCount__3703__ETC___d13705 ; + assign fetchStage_pipelines_0_canDeq__2990_AND_NOT_fe_ETC___d14360 = fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d14347 && + NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d14357 && (fetchStage$pipelines_0_first[194:192] == 3'd0 || fetchStage$pipelines_0_first[194:192] == 3'd1) && - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3689_co_ETC___d13699 ; - assign fetchStage_pipelines_0_canDeq__2990_AND_NOT_fe_ETC___d14457 = + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3699_co_ETC___d13709 ; + assign fetchStage_pipelines_0_canDeq__2990_AND_NOT_fe_ETC___d14467 = fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d14347 && - fetchStage_pipelines_0_first__2992_BITS_194_TO_ETC___d13995 || + NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d14357 && + fetchStage_pipelines_0_first__2992_BITS_194_TO_ETC___d14005 || !coreFix_aluExe_0_rsAlu$canEnq ; - assign fetchStage_pipelines_0_canDeq__2990_AND_fetchS_ETC___d14338 = + assign fetchStage_pipelines_0_canDeq__2990_AND_fetchS_ETC___d14348 = fetchStage$pipelines_0_canDeq && - fetchStage_pipelines_0_first__2992_BITS_194_TO_ETC___d14212 || + fetchStage_pipelines_0_first__2992_BITS_194_TO_ETC___d14222 || !fetchStage$pipelines_1_canDeq || fetchStage$RDY_pipelines_1_first && - (fetchStage_pipelines_1_first__3001_BITS_194_TO_ETC___d14223 || + (fetchStage_pipelines_1_first__3001_BITS_194_TO_ETC___d14233 || !regRenamingTable$rename_1_canRename || - fetchStage_pipelines_1_first__3001_BITS_199_TO_ETC___d14235 || - IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d14334) && - IF_fetchStage_RDY_pipelines_1_first__3000_AND__ETC___d14155 ; - assign fetchStage_pipelines_0_canDeq__2990_AND_regRen_ETC___d14274 = + fetchStage_pipelines_1_first__3001_BITS_199_TO_ETC___d14245 || + IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d14344) && + IF_fetchStage_RDY_pipelines_1_first__3000_AND__ETC___d14165 ; + assign fetchStage_pipelines_0_canDeq__2990_AND_regRen_ETC___d14284 = fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3658_AND__ETC___d13729 && + regRenamingTable_rename_0_canRename__3668_AND__ETC___d13739 && (fetchStage$pipelines_0_first[194:192] == 3'd3 || fetchStage$pipelines_0_first[194:192] == 3'd4) ; - assign fetchStage_pipelines_0_canDeq__2990_AND_regRen_ETC___d14281 = + assign fetchStage_pipelines_0_canDeq__2990_AND_regRen_ETC___d14291 = fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3658_AND__ETC___d13729 && + regRenamingTable_rename_0_canRename__3668_AND__ETC___d13739 && fetchStage$pipelines_0_first[194:192] == 3'd2 && - IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13711 || + IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13721 || !coreFix_memExe_rsMem$canEnq || CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q237 ; - assign fetchStage_pipelines_0_canDeq__2990_AND_regRen_ETC___d14303 = - fetchStage_pipelines_0_canDeq__2990_AND_regRen_ETC___d14274 || + assign fetchStage_pipelines_0_canDeq__2990_AND_regRen_ETC___d14313 = + fetchStage_pipelines_0_canDeq__2990_AND_regRen_ETC___d14284 || !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq || fetchStage$pipelines_0_canDeq && (fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || - NOT_regRenamingTable_rename_0_canRename__3658__ETC___d14087 || - IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14294) ; - assign fetchStage_pipelines_0_canDeq__2990_AND_regRen_ETC___d14315 = - fetchStage_pipelines_0_canDeq__2990_AND_regRen_ETC___d14281 || + NOT_regRenamingTable_rename_0_canRename__3668__ETC___d14097 || + IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14304) ; + assign fetchStage_pipelines_0_canDeq__2990_AND_regRen_ETC___d14325 = + fetchStage_pipelines_0_canDeq__2990_AND_regRen_ETC___d14291 || fetchStage$pipelines_0_canDeq && (fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || - NOT_regRenamingTable_rename_0_canRename__3658__ETC___d14087 || - IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14306) ; - assign fetchStage_pipelines_0_canDeq__2990_AND_regRen_ETC___d14608 = + NOT_regRenamingTable_rename_0_canRename__3668__ETC___d14097 || + IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14316) ; + assign fetchStage_pipelines_0_canDeq__2990_AND_regRen_ETC___d14618 = fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3658_AND__ETC___d14606 || + regRenamingTable_rename_0_canRename__3668_AND__ETC___d14616 || !coreFix_memExe_rsMem$canEnq || CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q237 ; - assign fetchStage_pipelines_0_canDeq__2990_AND_specTa_ETC___d14433 = + assign fetchStage_pipelines_0_canDeq__2990_AND_specTa_ETC___d14443 = fetchStage$pipelines_0_canDeq && specTagManager$canClaim && regRenamingTable$rename_0_canRename && !checkForException___d13243[4] && rob$enqPort_0_canEnq && - IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13739 && + IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13749 && fetchStage$pipelines_0_first[194:192] == 3'd1 ; assign fetchStage_pipelines_0_first__2992_BITS_194_TO_ETC___d13273 = (fetchStage$pipelines_0_first[194:192] == 3'd0 && @@ -30729,64 +30712,64 @@ module mkCore(CLK, rs1__h662591 != 5'd0 || imm__h662592 != 32'd0) && csr_addr__h662590[11:10] == 2'b11 ; - assign fetchStage_pipelines_0_first__2992_BITS_194_TO_ETC___d13995 = + assign fetchStage_pipelines_0_first__2992_BITS_194_TO_ETC___d14005 = (fetchStage$pipelines_0_first[194:192] == 3'd0 || fetchStage$pipelines_0_first[194:192] == 3'd1) && - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3689_co_ETC___d13699 && + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3699_co_ETC___d13709 && (!coreFix_aluExe_1_rsAlu$canEnq || - coreFix_aluExe_0_rsAlu_approximateCount__3693__ETC___d13695) ; - assign fetchStage_pipelines_0_first__2992_BITS_194_TO_ETC___d14094 = + coreFix_aluExe_0_rsAlu_approximateCount__3703__ETC___d13705) ; + assign fetchStage_pipelines_0_first__2992_BITS_194_TO_ETC___d14104 = fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || - renameStage_rg_m_halt_req_3019_BIT_4_3020_OR_f_ETC___d14090 ; - assign fetchStage_pipelines_0_first__2992_BITS_194_TO_ETC___d14206 = + renameStage_rg_m_halt_req_3019_BIT_4_3020_OR_f_ETC___d14100 ; + assign fetchStage_pipelines_0_first__2992_BITS_194_TO_ETC___d14216 = fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || !regRenamingTable$rename_0_canRename || - renameStage_rg_m_halt_req_3019_BIT_4_3020_OR_f_ETC___d14170 || - IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14195 && - IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14204 ; - assign fetchStage_pipelines_0_first__2992_BITS_194_TO_ETC___d14212 = + renameStage_rg_m_halt_req_3019_BIT_4_3020_OR_f_ETC___d14180 || + IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14205 && + IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14214 ; + assign fetchStage_pipelines_0_first__2992_BITS_194_TO_ETC___d14222 = fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || !regRenamingTable$rename_0_canRename || - renameStage_rg_m_halt_req_3019_BIT_4_3020_OR_f_ETC___d14170 || - IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14211 ; - assign fetchStage_pipelines_0_first__2992_BITS_194_TO_ETC___d14229 = + renameStage_rg_m_halt_req_3019_BIT_4_3020_OR_f_ETC___d14180 || + IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14221 ; + assign fetchStage_pipelines_0_first__2992_BITS_194_TO_ETC___d14239 = fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || !regRenamingTable$rename_0_canRename || fetchStage$pipelines_0_first[68] || checkForException___d13243[4] || !rob$enqPort_0_canEnq || - IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14211 ; - assign fetchStage_pipelines_0_first__2992_BITS_194_TO_ETC___d14241 = + IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14221 ; + assign fetchStage_pipelines_0_first__2992_BITS_194_TO_ETC___d14251 = fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || - NOT_regRenamingTable_rename_0_canRename__3658__ETC___d14011 || + NOT_regRenamingTable_rename_0_canRename__3668__ETC___d14021 || fetchStage$pipelines_0_first[194:192] != 3'd0 && fetchStage$pipelines_0_first[194:192] != 3'd1 || - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3689_co_ETC___d13699 || + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3699_co_ETC___d13709 || coreFix_aluExe_1_rsAlu$canEnq && - !coreFix_aluExe_0_rsAlu_approximateCount__3693__ETC___d13695 ; - assign fetchStage_pipelines_0_first__2992_BITS_194_TO_ETC___d14248 = + !coreFix_aluExe_0_rsAlu_approximateCount__3703__ETC___d13705 ; + assign fetchStage_pipelines_0_first__2992_BITS_194_TO_ETC___d14258 = fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || - NOT_regRenamingTable_rename_0_canRename__3658__ETC___d14011 || + NOT_regRenamingTable_rename_0_canRename__3668__ETC___d14021 || fetchStage$pipelines_0_first[194:192] != 3'd0 && fetchStage$pipelines_0_first[194:192] != 3'd1 || - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3689_co_ETC___d13699 || + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3699_co_ETC___d13709 || coreFix_aluExe_0_rsAlu$canEnq && - coreFix_aluExe_0_rsAlu_approximateCount__3693__ETC___d13695 ; - assign fetchStage_pipelines_0_first__2992_BITS_194_TO_ETC___d14264 = + coreFix_aluExe_0_rsAlu_approximateCount__3703__ETC___d13705 ; + assign fetchStage_pipelines_0_first__2992_BITS_194_TO_ETC___d14274 = fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || !regRenamingTable$rename_0_canRename || - fetchStage_pipelines_0_first__2992_BITS_199_TO_ETC___d13759 || + fetchStage_pipelines_0_first__2992_BITS_199_TO_ETC___d13769 || fetchStage$pipelines_0_first[194:192] != 3'd0 && fetchStage$pipelines_0_first[194:192] != 3'd1 || - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3689_co_ETC___d13699 ; - assign fetchStage_pipelines_0_first__2992_BITS_199_TO_ETC___d13759 = + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3699_co_ETC___d13709 ; + assign fetchStage_pipelines_0_first__2992_BITS_199_TO_ETC___d13769 = fetchStage$pipelines_0_first[199:195] == 5'd0 || fetchStage$pipelines_0_first[199:195] == 5'd21 || fetchStage$pipelines_0_first[199:195] == 5'd17 || @@ -30799,21 +30782,44 @@ module mkCore(CLK, renameStage_rg_m_halt_req[4] || fetchStage$pipelines_0_first[68] || checkForException___d13243[4] || - csrf_fs_reg_read__1746_EQ_0_3232_AND_fetchStag_ETC___d13752 || + csrf_fs_reg_read__1746_EQ_0_3232_AND_fetchStag_ETC___d13762 || !rob$enqPort_0_canEnq || !epochManager$checkEpoch_0_check ; - assign fetchStage_pipelines_0_first__2992_BIT_68_3021_ETC___d14085 = + assign fetchStage_pipelines_0_first__2992_BIT_173_311_ETC___d13661 = + { fetchStage$pipelines_0_first[173], + IF_fetchStage_pipelines_0_first__2992_BITS_172_ETC___d13208, + 73'h1280000000000000000, + fetchStage$pipelines_0_first[323:260], + 5'd0, + (fetchStage$pipelines_0_first[173] && + fetchStage$pipelines_0_first[199:195] == 5'd13 && + (fetchStage$pipelines_0_first[172:161] == 12'd1 || + fetchStage$pipelines_0_first[172:161] == 12'd2 || + fetchStage$pipelines_0_first[172:161] == 12'd3)) ? + fetchStage$pipelines_0_first[194:192] == 3'd0 && + fetchStage$pipelines_0_first[178:174] == 5'd15 || + (!fetchStage$pipelines_0_first[88] || + fetchStage$pipelines_0_first[87] || + fetchStage$pipelines_0_first[86:82] != 5'd0) && + (!fetchStage$pipelines_0_first[160] || + fetchStage$pipelines_0_first[159:128] != 32'd0) : + fetchStage$pipelines_0_first[75] && + fetchStage$pipelines_0_first[74], + fetchStage$pipelines_0_first[194:192] != 3'd0, + 13'h1521, + specTagManager$currentSpecBits } ; + assign fetchStage_pipelines_0_first__2992_BIT_68_3021_ETC___d14095 = fetchStage$pipelines_0_first[68] || checkForException___d13243[4] || - csrf_fs_reg_read__1746_EQ_0_3232_AND_fetchStag_ETC___d13752 || + csrf_fs_reg_read__1746_EQ_0_3232_AND_fetchStag_ETC___d13762 || !rob$enqPort_0_canEnq || !epochManager$checkEpoch_0_check ; - assign fetchStage_pipelines_1_first__3001_BITS_194_TO_ETC___d14223 = + assign fetchStage_pipelines_1_first__3001_BITS_194_TO_ETC___d14233 = fetchStage$pipelines_1_first[194:192] == 3'd1 && (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3658_AND__ETC___d14220 || + regRenamingTable_rename_0_canRename__3668_AND__ETC___d14230 || !specTagManager$canClaim) ; - assign fetchStage_pipelines_1_first__3001_BITS_199_TO_ETC___d14235 = + assign fetchStage_pipelines_1_first__3001_BITS_199_TO_ETC___d14245 = fetchStage$pipelines_1_first[199:195] == 5'd0 || fetchStage$pipelines_1_first[199:195] == 5'd21 || fetchStage$pipelines_1_first[199:195] == 5'd17 || @@ -30825,20 +30831,20 @@ module mkCore(CLK, fetchStage$pipelines_1_first[199:195] == 5'd20 || renameStage_rg_m_halt_req[4] || fetchStage$pipelines_1_first[68] || - checkForException___d13948[4] || - csrf_fs_reg_read__1746_EQ_0_3232_AND_fetchStag_ETC___d14041 || + checkForException___d13958[4] || + csrf_fs_reg_read__1746_EQ_0_3232_AND_fetchStag_ETC___d14051 || !rob$enqPort_1_canEnq || !epochManager$checkEpoch_1_check || csrf_rg_dcsr[2] || fetchStage$pipelines_0_canDeq && - fetchStage_pipelines_0_first__2992_BITS_194_TO_ETC___d14229 ; - assign fetchStage_pipelines_1_first__3001_BIT_173_383_ETC___d13926 = + fetchStage_pipelines_0_first__2992_BITS_194_TO_ETC___d14239 ; + assign fetchStage_pipelines_1_first__3001_BIT_173_384_ETC___d13936 = { fetchStage$pipelines_1_first[173], CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q235 } ; - assign fflags__h743755 = - NOT_rob_deqPort_0_canDeq__5654_5655_OR_rob_deq_ETC___d15980 ? - y_avValue_fst__h743692 : - IF_rob_deqPort_0_canDeq__5654_THEN_IF_NOT_rob__ETC___d15986 ; + assign fflags__h743858 = + NOT_rob_deqPort_0_canDeq__5664_5665_OR_rob_deq_ETC___d15990 ? + y_avValue_fst__h743795 : + IF_rob_deqPort_0_canDeq__5664_THEN_IF_NOT_rob__ETC___d15996 ; assign fflags_csr__read__h615692 = { 59'd0, csrf_fflags_reg } ; assign frm_csr__read__h615703 = { 61'd0, csrf_frm_reg } ; assign guard__h350520 = @@ -30910,19 +30916,19 @@ module mkCore(CLK, assign guard__h595038 = { IF_theResult___snd02974_BIT_4_THEN_2_ELSE_0__q159[1], { _theResult___snd__h602974[3:0], 52'd0 } != 56'd0 } ; - assign idx__h694474 = + assign idx__h694577 = fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d13996 || + NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d14006 || !coreFix_aluExe_0_rsAlu$canEnq || - NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14020 ; + NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14030 ; assign imm__h662592 = fetchStage$pipelines_0_first[160] ? fetchStage$pipelines_0_first[159:128] : 32'd0 ; - assign k__h678117 = + assign k__h678220 = !coreFix_aluExe_0_rsAlu$canEnq || coreFix_aluExe_1_rsAlu$canEnq && - !coreFix_aluExe_0_rsAlu_approximateCount__3693__ETC___d13695 ; + !coreFix_aluExe_0_rsAlu_approximateCount__3703__ETC___d13705 ; assign mcause_csr__read__h617359 = { r1__read__h620838, csrf_mcause_code_reg } ; assign mcounteren_csr__read__h617104 = @@ -30987,13 +30993,13 @@ module mkCore(CLK, fetchStage$pipelines_0_first[199:195] == 5'd19 || fetchStage$pipelines_0_first[199:195] == 5'd20) && rob$isEmpty ; - assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14342 = + assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14352 = mmio_pRqQ_empty && epochManager$checkEpoch_0_check && !renameStage_rg_m_halt_req[4] && !fetchStage$pipelines_0_first[68] && - NOT_IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_302_ETC___d13673 ; - assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14344 = - mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14342 && + NOT_IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_302_ETC___d13683 ; + assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14354 = + mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14352 && fetchStage$pipelines_0_first[199:195] != 5'd0 && fetchStage$pipelines_0_first[199:195] != 5'd21 && fetchStage$pipelines_0_first[199:195] != 5'd17 && @@ -31061,11 +31067,11 @@ module mkCore(CLK, upd__h6875 : csrf_mcycle_ehr_data_rl) : 64'd0 ; - assign n__read__h736806 = + assign n__read__h736909 = csrf_minstret_ehr_data_dummy2_1$Q_OUT ? IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8 : 64'd0 ; - assign new_mstatus___1__h736168 = x__h736159 ; + assign new_mstatus___1__h736271 = x__h736262 ; assign next_deqP___1__h301224 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP == 3'd7) ? @@ -31080,12 +31086,12 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP + 1'd1 ; assign next_deqP___1__h333412 = coreFix_memExe_memRespLdQ_deqP + 1'd1 ; assign next_deqP___1__h336637 = coreFix_memExe_forwardQ_deqP + 1'd1 ; - assign next_pc__h732539 = + assign next_pc__h732642 = (rob$deqPort_0_deq_data[329:325] != 5'd13 && rob$deqPort_0_deq_data[97:96] == 2'd0) ? rob$deqPort_0_deq_data[95:32] : - rob_deqPort_0_deq_data__4651_BITS_425_TO_362_4_ETC___d15501 ; - assign old_fflags1__h743181 = + rob_deqPort_0_deq_data__4661_BITS_425_TO_362_4_ETC___d15511 ; + assign old_fflags1__h743284 = csrf_fflags_reg | rob$deqPort_0_deq_data[31:27] ; assign out___1_sfd__h487137 = { f1_sfd__h487074, 29'd0 } ; assign out___1_sfd__h526131 = { f2_sfd__h526068, 29'd0 } ; @@ -31294,21 +31300,21 @@ module mkCore(CLK, _theResult___snd__h602974[5] ? _theResult___sfd__h603709 : _theResult___snd__h602974[56:5] ; - assign pc__h722238 = - csrf_prv_reg_read__3022_ULE_1_5013_AND_IF_comm_ETC___d15035 ? - y_avValue_new_pc__h722030 : - y_avValue_new_pc__h722216 ; + assign pc__h722341 = + csrf_prv_reg_read__3022_ULE_1_5023_AND_IF_comm_ETC___d15045 ? + y_avValue_new_pc__h722133 : + y_avValue_new_pc__h722319 ; assign pend_ints__h658379 = { _0_CONCAT_csrf_external_int_en_vec_3_read__1864_ETC___d13033, csrf_software_int_en_vec_3 & csrf_software_int_pend_vec_3, 1'd0, csrf_software_int_en_vec_1 & csrf_software_int_pend_vec_1, 1'd0 } ; - assign po_fflags__h738358 = old_fflags1__h743181 ; - assign po_fflags__h741065 = - old_fflags1__h743181 | rob$deqPort_1_deq_data[31:27] ; - assign prv__h745422 = csrf_prv_reg ; - assign prv__h745466 = csrf_mprv_reg ? csrf_mpp_reg : csrf_prv_reg ; + assign po_fflags__h738461 = old_fflags1__h743284 ; + assign po_fflags__h741168 = + old_fflags1__h743284 | rob$deqPort_1_deq_data[31:27] ; + assign prv__h745525 = csrf_prv_reg ; + assign prv__h745569 = csrf_mprv_reg ? csrf_mpp_reg : csrf_prv_reg ; assign q___1__h480479 = 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[203:140] ; @@ -31321,7 +31327,7 @@ module mkCore(CLK, csrf_mideleg_5_3_reg, 1'b0 } ; assign r1__read_BITS_13_TO_12___h662460 = csrf_fs_reg ; - assign r1__read_BITS_61_TO_14___h736227 = + assign r1__read_BITS_61_TO_14___h736330 = { 40'd5120, csrf_tsr_reg, csrf_tw_reg, @@ -31440,24 +31446,25 @@ module mkCore(CLK, assign r___1__h480506 = 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[139:76] ; - assign regRenamingTable_RDY_commit_0_commit__5255_AND_ETC___d15315 = - regRenamingTable$RDY_commit_0_commit && rob$RDY_deqPort_0_deq && - rob$RDY_deqPort_0_deq_data && - v_f_to_TV_0$FULL_N && - fetchStage$iTlbIfc_noPendingReq && - coreFix_memExe_dTlb$noPendingReq && - NOT_rob_deqPort_0_deq_data__4651_BITS_329_TO_3_ETC___d15310 ; - assign regRenamingTable_RDY_rename_0_getRename__3535__ETC___d14191 = + assign regRenamingTable_RDY_rename_0_getRename__3535__ETC___d13544 = regRenamingTable$RDY_rename_0_getRename && - CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q240 && + regRenamingTable$RDY_rename_0_claimRename && + fetchStage$RDY_pipelines_0_deq && + fetchStage$RDY_pipelines_0_first && + epochManager$RDY_incrementEpoch && + (fetchStage$pipelines_0_first[194:192] != 3'd0 || + coreFix_aluExe_0_rsAlu$RDY_enq) ; + assign regRenamingTable_RDY_rename_0_getRename__3535__ETC___d14201 = + regRenamingTable$RDY_rename_0_getRename && + CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q239 && (fetchStage$pipelines_0_first[199:195] == 5'd14 || coreFix_memExe_rsMem$RDY_enq) ; - assign regRenamingTable_RDY_rename_1_getRename__4254__ETC___d14272 = + assign regRenamingTable_RDY_rename_1_getRename__4264__ETC___d14282 = regRenamingTable$RDY_rename_1_getRename && (!fetchStage$pipelines_0_canDeq || - NOT_specTagManager_canClaim__3656_3742_OR_NOT__ETC___d14257) && - _0_OR_NOT_fetchStage_pipelines_1_first__3001_BI_ETC___d14270 ; - assign regRenamingTable_rename_0_canRename__3658_AND__ETC___d13680 = + NOT_specTagManager_canClaim__3666_3752_OR_NOT__ETC___d14267) && + _0_OR_NOT_fetchStage_pipelines_1_first__3001_BI_ETC___d14280 ; + assign regRenamingTable_rename_0_canRename__3668_AND__ETC___d13690 = regRenamingTable$rename_0_canRename && fetchStage$pipelines_0_first[199:195] != 5'd0 && fetchStage$pipelines_0_first[199:195] != 5'd21 && @@ -31468,8 +31475,8 @@ module mkCore(CLK, fetchStage$pipelines_0_first[199:195] != 5'd15 && fetchStage$pipelines_0_first[199:195] != 5'd19 && fetchStage$pipelines_0_first[199:195] != 5'd20 && - NOT_renameStage_rg_m_halt_req_3019_BIT_4_3020__ETC___d13678 ; - assign regRenamingTable_rename_0_canRename__3658_AND__ETC___d13729 = + NOT_renameStage_rg_m_halt_req_3019_BIT_4_3020__ETC___d13688 ; + assign regRenamingTable_rename_0_canRename__3668_AND__ETC___d13739 = regRenamingTable$rename_0_canRename && fetchStage$pipelines_0_first[199:195] != 5'd0 && fetchStage$pipelines_0_first[199:195] != 5'd21 && @@ -31480,40 +31487,40 @@ module mkCore(CLK, fetchStage$pipelines_0_first[199:195] != 5'd15 && fetchStage$pipelines_0_first[199:195] != 5'd19 && fetchStage$pipelines_0_first[199:195] != 5'd20 && - NOT_fetchStage_pipelines_0_first__2992_BIT_68__ETC___d13727 ; - assign regRenamingTable_rename_0_canRename__3658_AND__ETC___d13743 = - regRenamingTable_rename_0_canRename__3658_AND__ETC___d13729 && - IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13739 && + NOT_fetchStage_pipelines_0_first__2992_BIT_68__ETC___d13737 ; + assign regRenamingTable_rename_0_canRename__3668_AND__ETC___d13753 = + regRenamingTable_rename_0_canRename__3668_AND__ETC___d13739 && + IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13749 && fetchStage$pipelines_0_first[194:192] == 3'd1 || !specTagManager$canClaim ; - assign regRenamingTable_rename_0_canRename__3658_AND__ETC___d14073 = - regRenamingTable_rename_0_canRename__3658_AND__ETC___d13729 && + assign regRenamingTable_rename_0_canRename__3668_AND__ETC___d14083 = + regRenamingTable_rename_0_canRename__3668_AND__ETC___d13739 && fetchStage$pipelines_0_first[194:192] == 3'd2 && - IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13711 || + IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13721 || !coreFix_memExe_rsMem$canEnq || CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q237 ; - assign regRenamingTable_rename_0_canRename__3658_AND__ETC___d14220 = + assign regRenamingTable_rename_0_canRename__3668_AND__ETC___d14230 = regRenamingTable$rename_0_canRename && !checkForException___d13243[4] && rob$enqPort_0_canEnq && - IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14218 && + IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14228 && fetchStage$pipelines_0_first[194:192] == 3'd1 ; - assign regRenamingTable_rename_0_canRename__3658_AND__ETC___d14362 = + assign regRenamingTable_rename_0_canRename__3668_AND__ETC___d14372 = regRenamingTable$rename_0_canRename && !checkForException___d13243[4] && rob$enqPort_0_canEnq && (fetchStage$pipelines_0_first[194:192] == 3'd3 || fetchStage$pipelines_0_first[194:192] == 3'd4) && coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq ; - assign regRenamingTable_rename_0_canRename__3658_AND__ETC___d14375 = + assign regRenamingTable_rename_0_canRename__3668_AND__ETC___d14385 = regRenamingTable$rename_0_canRename && !checkForException___d13243[4] && rob$enqPort_0_canEnq && (fetchStage$pipelines_0_first[194:192] == 3'd3 || fetchStage$pipelines_0_first[194:192] == 3'd4) && coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq && - NOT_fetchStage_pipelines_0_first__2992_BITS_32_ETC___d14371 ; - assign regRenamingTable_rename_0_canRename__3658_AND__ETC___d14380 = + NOT_fetchStage_pipelines_0_first__2992_BITS_32_ETC___d14381 ; + assign regRenamingTable_rename_0_canRename__3668_AND__ETC___d14390 = regRenamingTable$rename_0_canRename && !checkForException___d13243[4] && rob$enqPort_0_canEnq && @@ -31521,64 +31528,64 @@ module mkCore(CLK, fetchStage$pipelines_0_first[194:192] == 3'd4) && coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq && fetchStage$pipelines_0_first[173] ; - assign regRenamingTable_rename_0_canRename__3658_AND__ETC___d14385 = + assign regRenamingTable_rename_0_canRename__3668_AND__ETC___d14395 = regRenamingTable$rename_0_canRename && !checkForException___d13243[4] && rob$enqPort_0_canEnq && fetchStage$pipelines_0_first[194:192] == 3'd2 && coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13711 && + IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13721 && fetchStage$pipelines_0_first[199:195] != 5'd14 ; - assign regRenamingTable_rename_0_canRename__3658_AND__ETC___d14405 = + assign regRenamingTable_rename_0_canRename__3668_AND__ETC___d14415 = regRenamingTable$rename_0_canRename && !checkForException___d13243[4] && rob$enqPort_0_canEnq && fetchStage$pipelines_0_first[194:192] == 3'd2 && coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13711 && - NOT_fetchStage_pipelines_0_first__2992_BITS_32_ETC___d14371 ; - assign regRenamingTable_rename_0_canRename__3658_AND__ETC___d14409 = + IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13721 && + NOT_fetchStage_pipelines_0_first__2992_BITS_32_ETC___d14381 ; + assign regRenamingTable_rename_0_canRename__3668_AND__ETC___d14419 = regRenamingTable$rename_0_canRename && !checkForException___d13243[4] && rob$enqPort_0_canEnq && fetchStage$pipelines_0_first[194:192] == 3'd2 && coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13711 && + IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13721 && fetchStage$pipelines_0_first[173] ; - assign regRenamingTable_rename_0_canRename__3658_AND__ETC___d14415 = + assign regRenamingTable_rename_0_canRename__3668_AND__ETC___d14425 = regRenamingTable$rename_0_canRename && !checkForException___d13243[4] && rob$enqPort_0_canEnq && fetchStage$pipelines_0_first[194:192] == 3'd2 && coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13711 && + IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13721 && (fetchStage$pipelines_0_first[199:195] != 5'd14) != fetchStage$pipelines_0_first[160] ; - assign regRenamingTable_rename_0_canRename__3658_AND__ETC___d14419 = + assign regRenamingTable_rename_0_canRename__3668_AND__ETC___d14429 = regRenamingTable$rename_0_canRename && !checkForException___d13243[4] && rob$enqPort_0_canEnq && fetchStage$pipelines_0_first[194:192] == 3'd2 && coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13711 && + IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13721 && (fetchStage$pipelines_0_first[191:189] == 3'd0 || fetchStage$pipelines_0_first[191:189] == 3'd2) ; - assign regRenamingTable_rename_0_canRename__3658_AND__ETC___d14427 = + assign regRenamingTable_rename_0_canRename__3668_AND__ETC___d14437 = regRenamingTable$rename_0_canRename && !checkForException___d13243[4] && rob$enqPort_0_canEnq && fetchStage$pipelines_0_first[194:192] == 3'd2 && coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13711 && + IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13721 && fetchStage$pipelines_0_first[191:189] != 3'd0 && fetchStage$pipelines_0_first[191:189] != 3'd2 ; - assign regRenamingTable_rename_0_canRename__3658_AND__ETC___d14606 = + assign regRenamingTable_rename_0_canRename__3668_AND__ETC___d14616 = regRenamingTable$rename_0_canRename && !checkForException___d13243[4] && rob$enqPort_0_canEnq && fetchStage$pipelines_0_first[194:192] == 3'd2 && - IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13711 ; - assign regRenamingTable_rename_1_canRename__3780_AND__ETC___d13988 = + IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13721 ; + assign regRenamingTable_rename_1_canRename__3790_AND__ETC___d13998 = regRenamingTable$rename_1_canRename && fetchStage$pipelines_1_first[199:195] != 5'd0 && fetchStage$pipelines_1_first[199:195] != 5'd21 && @@ -31589,8 +31596,8 @@ module mkCore(CLK, fetchStage$pipelines_1_first[199:195] != 5'd15 && fetchStage$pipelines_1_first[199:195] != 5'd19 && fetchStage$pipelines_1_first[199:195] != 5'd20 && - NOT_renameStage_rg_m_halt_req_3019_BIT_4_3020__ETC___d13986 ; - assign regRenamingTable_rename_1_canRename__3780_AND__ETC___d14130 = + NOT_renameStage_rg_m_halt_req_3019_BIT_4_3020__ETC___d13996 ; + assign regRenamingTable_rename_1_canRename__3790_AND__ETC___d14140 = regRenamingTable$rename_1_canRename && fetchStage$pipelines_1_first[199:195] != 5'd0 && fetchStage$pipelines_1_first[199:195] != 5'd21 && @@ -31601,8 +31608,8 @@ module mkCore(CLK, fetchStage$pipelines_1_first[199:195] != 5'd15 && fetchStage$pipelines_1_first[199:195] != 5'd19 && fetchStage$pipelines_1_first[199:195] != 5'd20 && - NOT_renameStage_rg_m_halt_req_3019_BIT_4_3020__ETC___d14128 ; - assign regRenamingTable_rename_1_canRename__3780_AND__ETC___d14148 = + NOT_renameStage_rg_m_halt_req_3019_BIT_4_3020__ETC___d14138 ; + assign regRenamingTable_rename_1_canRename__3790_AND__ETC___d14158 = regRenamingTable$rename_1_canRename && fetchStage$pipelines_1_first[199:195] != 5'd0 && fetchStage$pipelines_1_first[199:195] != 5'd21 && @@ -31613,8 +31620,8 @@ module mkCore(CLK, fetchStage$pipelines_1_first[199:195] != 5'd15 && fetchStage$pipelines_1_first[199:195] != 5'd19 && fetchStage$pipelines_1_first[199:195] != 5'd20 && - NOT_renameStage_rg_m_halt_req_3019_BIT_4_3020__ETC___d14146 ; - assign regRenamingTable_rename_1_canRename__3780_AND__ETC___d14485 = + NOT_renameStage_rg_m_halt_req_3019_BIT_4_3020__ETC___d14156 ; + assign regRenamingTable_rename_1_canRename__3790_AND__ETC___d14495 = regRenamingTable$rename_1_canRename && fetchStage$pipelines_1_first[199:195] != 5'd0 && fetchStage$pipelines_1_first[199:195] != 5'd21 && @@ -31625,7 +31632,7 @@ module mkCore(CLK, fetchStage$pipelines_1_first[199:195] != 5'd15 && fetchStage$pipelines_1_first[199:195] != 5'd19 && fetchStage$pipelines_1_first[199:195] != 5'd20 && - NOT_fetchStage_pipelines_1_first__3001_BIT_68__ETC___d14483 ; + NOT_fetchStage_pipelines_1_first__3001_BIT_68__ETC___d14493 ; assign renameStage_rg_m_halt_req_3019_BIT_4_3020_OR_N_ETC___d13303 = renameStage_rg_m_halt_req[4] || !fetchStage$pipelines_0_first[68] && @@ -31651,20 +31658,20 @@ module mkCore(CLK, IF_fetchStage_pipelines_0_first__2992_BIT_68_3_ETC___d13365 : IF_checkForException_3243_BIT_4_3244_THEN_IF_c_ETC___d13394) == 4'd3 ; - assign renameStage_rg_m_halt_req_3019_BIT_4_3020_OR_f_ETC___d14009 = + assign renameStage_rg_m_halt_req_3019_BIT_4_3020_OR_f_ETC___d14019 = renameStage_rg_m_halt_req[4] || fetchStage$pipelines_0_first[68] || - IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_3023_30_ETC___d14006 || + IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_3023_30_ETC___d14016 || !rob$enqPort_0_canEnq || !epochManager$checkEpoch_0_check ; - assign renameStage_rg_m_halt_req_3019_BIT_4_3020_OR_f_ETC___d14049 = + assign renameStage_rg_m_halt_req_3019_BIT_4_3020_OR_f_ETC___d14059 = renameStage_rg_m_halt_req[4] || fetchStage$pipelines_1_first[68] || - IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_3023_30_ETC___d14043 || + IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_3023_30_ETC___d14053 || !rob$enqPort_1_canEnq || !epochManager$checkEpoch_1_check || - csrf_rg_dcsr_read__1920_BIT_2_3297_OR_NOT_fetc_ETC___d13748 ; - assign renameStage_rg_m_halt_req_3019_BIT_4_3020_OR_f_ETC___d14090 = + csrf_rg_dcsr_read__1920_BIT_2_3297_OR_NOT_fetc_ETC___d13758 ; + assign renameStage_rg_m_halt_req_3019_BIT_4_3020_OR_f_ETC___d14100 = renameStage_rg_m_halt_req[4] || fetchStage$pipelines_0_first[68] || IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_3023_30_ETC___d13059[0] || @@ -31683,14 +31690,14 @@ module mkCore(CLK, IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_3023_30_ETC___d13059[13] || IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_3023_30_ETC___d13059[14] || IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_3023_30_ETC___d13059[15] ; - assign renameStage_rg_m_halt_req_3019_BIT_4_3020_OR_f_ETC___d14170 = + assign renameStage_rg_m_halt_req_3019_BIT_4_3020_OR_f_ETC___d14180 = renameStage_rg_m_halt_req[4] || fetchStage$pipelines_0_first[68] || checkForException___d13243[4] || !rob$enqPort_0_canEnq ; - assign renaming_spec_bits__h694343 = + assign renaming_spec_bits__h694446 = fetchStage$pipelines_0_canDeq ? - y_avValue_fst__h690738 : + y_avValue_fst__h690841 : specTagManager$currentSpecBits ; assign res_data__h342294 = { 32'hFFFFFFFF, x__h342309 } ; assign res_data__h342299 = @@ -31967,7 +31974,7 @@ module mkCore(CLK, guard__h586567 } ; assign result__h653958 = w__h653953 & y__h653987 ; assign result__h654009 = ~x__h654008 ; - assign rg_core_run_state_read__3293_EQ_2_3294_AND_NOT_ETC___d16051 = + assign rg_core_run_state_read__3293_EQ_2_3294_AND_NOT_ETC___d16061 = rg_core_run_state == 2'd2 && !flush_reservation && !flush_tlbs && !update_vm_info && fetchStage$iTlbIfc_flush_done && @@ -31975,13 +31982,14 @@ module mkCore(CLK, !flush_caches ; assign rg_tdata1__read__h618547 = { r1__read__h620941, csrf_rg_tdata1_data } ; - assign rob_RDY_enqPort_1_enq__4320_AND_NOT_fetchStage_ETC___d14328 = - rob$RDY_enqPort_1_enq && - (!fetchStage$pipelines_0_canDeq || - NOT_specTagManager_canClaim__3656_3742_OR_NOT__ETC___d14324) && - (fetchStage$pipelines_1_first[194:192] != 3'd1 || - specTagManager$RDY_claimSpecTag) ; - assign rob_deqPort_0_deq_data__4651_BITS_161_TO_98_46_ETC___d15630 = + assign rob_RDY_deqPort_0_deq__4658_AND_rob_RDY_deqPor_ETC___d15325 = + rob$RDY_deqPort_0_deq && rob$RDY_deqPort_0_deq_data && + regRenamingTable$RDY_commit_0_commit && + v_f_to_TV_0$FULL_N && + fetchStage$iTlbIfc_noPendingReq && + coreFix_memExe_dTlb$noPendingReq && + NOT_rob_deqPort_0_deq_data__4661_BITS_329_TO_3_ETC___d15320 ; + assign rob_deqPort_0_deq_data__4661_BITS_161_TO_98_46_ETC___d15640 = { rob$deqPort_0_deq_data[161:98], (rob$deqPort_0_deq_data[329:325] != 5'd13 && rob$deqPort_0_deq_data[97:96] == 2'd0) ? @@ -31991,23 +31999,23 @@ module mkCore(CLK, { 2'd1, rob$deqPort_0_deq_data[95:32] } : { 2'd2, (rob$deqPort_0_deq_data[329:325] == 5'd13) ? - data_warl_xformed__h732513 : + data_warl_xformed__h732616 : rob$deqPort_0_deq_data[95:32] }), 5'h0A, rob$deqPort_0_deq_data[26], - x__h736159, - x_prv__h733165, + x__h736262, + x_prv__h733268, 64'hAAAAAAAAAAAAAAAA, - x__h736300, + x__h736403, 128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; - assign rob_deqPort_0_deq_data__4651_BITS_425_TO_362_4_ETC___d15501 = + assign rob_deqPort_0_deq_data__4661_BITS_425_TO_362_4_ETC___d15511 = rob$deqPort_0_deq_data[425:362] + 64'd4 ; - assign rob_deqPort_0_deq_data__4651_BIT_166_4667_CONC_ETC___d14716 = + assign rob_deqPort_0_deq_data__4661_BIT_166_4677_CONC_ETC___d14726 = { rob$deqPort_0_deq_data[166], rob$deqPort_0_deq_data[166] ? CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q247 : CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q248 } ; - assign rob_deqPort_0_deq_data__4651_BIT_181_4726_CONC_ETC___d14817 = + assign rob_deqPort_0_deq_data__4661_BIT_181_4736_CONC_ETC___d14827 = { rob$deqPort_0_deq_data[181], CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q246 } ; assign robdeqPort_0_deq_data_BITS_95_TO_32__q245 = @@ -32179,14 +32187,14 @@ module mkCore(CLK, coreFix_memExe_regToExeQ$first[75:12] << x__h184592 ; assign sie_csr__read__h615983 = { r1__read__h619794, 1'b0 } ; assign sip_csr__read__h616357 = { r1__read__h620328, 1'b0 } ; - assign spec_bits__h697502 = specTagManager$currentSpecBits | y__h697515 ; + assign spec_bits__h697605 = specTagManager$currentSpecBits | y__h697618 ; assign sstatus_csr__read__h615913 = { r1__read__h619390, csrf_ie_vec_0 } ; assign stvec_csr__read__h616026 = { r1__read__h620304, csrf_stvec_mode_low_reg } ; - assign trap_val__h719295 = - commitStage_commitTrap[36] ? 64'd0 : trap_val__h720333 ; - assign tsr_val__h736420 = csrf_tsr_reg ; - assign tvm_val__h736422 = csrf_tvm_reg ; + assign trap_val__h719398 = + commitStage_commitTrap[36] ? 64'd0 : trap_val__h720436 ; + assign tsr_val__h736523 = csrf_tsr_reg ; + assign tvm_val__h736525 = csrf_tvm_reg ; assign upd__h3994 = WILL_FIRE_RL_commitStage_doCommitSystemInst ? MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1 : @@ -32196,7 +32204,7 @@ module mkCore(CLK, MUX_csrf_mcycle_ehr_data_dummy2_0$write_1__SEL_1 ? f_csr_reqs$D_OUT[63:0] : rob$deqPort_0_deq_data[95:32] ; - assign upd__h736917 = + assign upd__h737020 = MUX_csrf_minstret_ehr_data_dummy2_0$write_1__SEL_1 ? f_csr_reqs$D_OUT[63:0] : rob$deqPort_0_deq_data[95:32] ; @@ -32441,22 +32449,22 @@ module mkCore(CLK, sbCons$lazyLookup_0_get[2] ? rf$read_0_rd2 : y_avValue__h644642 ; assign x__h653957 = 12'd1 << coreFix_aluExe_1_exeToFinQ$first[15:12] ; assign x__h654008 = 12'd1 << coreFix_aluExe_0_exeToFinQ$first[15:12] ; - assign x__h712093 = + assign x__h712196 = (!rob$deqPort_0_deq_data[166] && (rob$deqPort_0_deq_data[165:162] == 4'd1 || rob$deqPort_0_deq_data[165:162] == 4'd12)) ? rob$deqPort_0_deq_data[161:98] : rob$deqPort_0_deq_data[95:32] ; - assign x__h722269 = { cause_code__h719294, 2'b0 } ; - assign x__h724496 = + assign x__h722372 = { cause_code__h719397, 2'b0 } ; + assign x__h724599 = { csrf_fs_reg == 2'b11, - IF_csrf_prv_reg_read__3022_ULE_1_5013_AND_IF_c_ETC___d15237 } ; - assign x__h724688 = - { commitStage_commitTrap[36], 59'b0, cause_code__h719294 } ; - assign x__h732714 = { 1'b0, csrf_spp_reg } ; - assign x__h736159 = + IF_csrf_prv_reg_read__3022_ULE_1_5023_AND_IF_c_ETC___d15247 } ; + assign x__h724791 = + { commitStage_commitTrap[36], 59'b0, cause_code__h719397 } ; + assign x__h732817 = { 1'b0, csrf_spp_reg } ; + assign x__h736262 = { 1'b1, - r1__read_BITS_61_TO_14___h736227, + r1__read_BITS_61_TO_14___h736330, 2'b11, csrf_mpp_reg, 2'b0, @@ -32469,7 +32477,7 @@ module mkCore(CLK, 1'b0, csrf_ie_vec_1, csrf_ie_vec_0 } ; - assign x__h736300 = + assign x__h736403 = { csrf_fs_reg == 2'b11, 40'd5120, csrf_tsr_reg, @@ -32480,16 +32488,16 @@ module mkCore(CLK, csrf_mprv_reg, 2'd0, csrf_fs_reg, - IF_rob_deqPort_0_deq_data__4651_BITS_329_TO_32_ETC___d15620 } ; - assign x__h743208 = + IF_rob_deqPort_0_deq_data__4661_BITS_329_TO_32_ETC___d15630 } ; + assign x__h743311 = { 1'b1, - y_avValue_snd_snd_snd_snd_snd_snd_snd__h743190[62:15], + y_avValue_snd_snd_snd_snd_snd_snd_snd__h743293[62:15], 2'b11, - y_avValue_snd_snd_snd_snd_snd_snd_snd__h743190[12:0] } ; - assign x__h744019 = - NOT_rob_deqPort_0_canDeq__5654_5655_OR_rob_deq_ETC___d15980 ? - y_avValue_snd_snd_snd_fst__h743829 : - IF_rob_deqPort_0_canDeq__5654_THEN_IF_NOT_rob__ETC___d16005 ; + y_avValue_snd_snd_snd_snd_snd_snd_snd__h743293[12:0] } ; + assign x__h744122 = + NOT_rob_deqPort_0_canDeq__5664_5665_OR_rob_deq_ETC___d15990 ? + y_avValue_snd_snd_snd_fst__h743932 : + IF_rob_deqPort_0_canDeq__5664_THEN_IF_NOT_rob__ETC___d16015 ; assign x__h76239 = mmio_pRqQ_data_0[31:0] ; assign x_addr__h318498 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? @@ -32499,16 +32507,16 @@ module mkCore(CLK, EN_mmioToPlatform_pRq_enq ? mmio_pRqQ_enqReq_lat_0$wget[31:0] : mmio_pRqQ_enqReq_rl[31:0] ; - assign x_data_imm__h685411 = fetchStage$pipelines_0_first[159:128] ; - assign x_data_imm__h702077 = fetchStage$pipelines_1_first[159:128] ; + assign x_data_imm__h685514 = fetchStage$pipelines_0_first[159:128] ; + assign x_data_imm__h702180 = fetchStage$pipelines_1_first[159:128] ; assign x_decodeInfo_frm__h662275 = csrf_frm_reg ; - assign x_prv__h722338 = - csrf_prv_reg_read__3022_ULE_1_5013_AND_IF_comm_ETC___d15035 ? + assign x_prv__h722441 = + csrf_prv_reg_read__3022_ULE_1_5023_AND_IF_comm_ETC___d15045 ? 2'd1 : 2'd3 ; - assign x_prv__h733165 = + assign x_prv__h733268 = (rob$deqPort_0_deq_data[329:325] == 5'd19) ? - x__h732714 : + x__h732817 : csrf_mpp_reg ; assign x_quotient__h479694 = coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[75] ? @@ -32540,15 +32548,15 @@ module mkCore(CLK, ~csrf_mideleg_5_3_reg, 1'd1, ~csrf_mideleg_1_0_reg } ; - assign y__h697515 = 12'd1 << specTagManager$nextSpecTag ; - assign y__h740902 = + assign y__h697618 = 12'd1 << specTagManager$nextSpecTag ; + assign y__h741005 = rob$deqPort_0_canDeq ? - y_avValue_snd_snd_snd_snd_snd_fst__h740925 : + y_avValue_snd_snd_snd_snd_snd_fst__h741028 : 64'd0 ; - assign y__h743778 = - NOT_rob_deqPort_0_canDeq__5654_5655_OR_rob_deq_ETC___d15980 ? - y_avValue_snd_snd_snd_snd_snd_fst__h743839 : - y__h740902 ; + assign y__h743881 = + NOT_rob_deqPort_0_canDeq__5664_5665_OR_rob_deq_ETC___d15990 ? + y_avValue_snd_snd_snd_snd_snd_fst__h743942 : + y__h741005 ; assign y_avValue__h183536 = NOT_coreFix_memExe_bypassWire_0_whas__585_591__ETC___d1612 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : @@ -32585,21 +32593,21 @@ module mkCore(CLK, NOT_coreFix_aluExe_0_bypassWire_0_whas__2410_2_ETC___d12467 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__241_ETC___d12682 ; - assign y_avValue_fst__h690675 = + assign y_avValue_fst__h690778 = (fetchStage$pipelines_0_first[194:192] == 3'd1) ? - spec_bits__h697502 : + spec_bits__h697605 : specTagManager$currentSpecBits ; - assign y_avValue_fst__h690704 = - IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13739 ? - y_avValue_fst__h690675 : + assign y_avValue_fst__h690807 = + IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13749 ? + y_avValue_fst__h690778 : specTagManager$currentSpecBits ; - assign y_avValue_fst__h690738 = + assign y_avValue_fst__h690841 = ((fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3658_AND__ETC___d13680) ? - y_avValue_fst__h690704 : + regRenamingTable_rename_0_canRename__3668_AND__ETC___d13690) ? + y_avValue_fst__h690807 : specTagManager$currentSpecBits ; - assign y_avValue_fst__h740440 = + assign y_avValue_fst__h740543 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[167] || rob$deqPort_0_deq_data[329:325] == 5'd0 || @@ -32613,10 +32621,10 @@ module mkCore(CLK, rob$deqPort_0_deq_data[329:325] == 5'd20) ? 5'd0 : rob$deqPort_0_deq_data[31:27] ; - assign y_avValue_fst__h743660 = - IF_rob_deqPort_0_canDeq__5654_THEN_IF_NOT_rob__ETC___d15986 | + assign y_avValue_fst__h743763 = + IF_rob_deqPort_0_canDeq__5664_THEN_IF_NOT_rob__ETC___d15996 | rob$deqPort_1_deq_data[31:27] ; - assign y_avValue_fst__h743692 = + assign y_avValue_fst__h743795 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[329:325] == 5'd0 || @@ -32628,17 +32636,17 @@ module mkCore(CLK, rob$deqPort_1_deq_data[329:325] == 5'd15 || rob$deqPort_1_deq_data[329:325] == 5'd19 || rob$deqPort_1_deq_data[329:325] == 5'd20) ? - IF_rob_deqPort_0_canDeq__5654_THEN_IF_NOT_rob__ETC___d15986 : - y_avValue_fst__h743660 ; - assign y_avValue_new_pc__h722030 = + IF_rob_deqPort_0_canDeq__5664_THEN_IF_NOT_rob__ETC___d15996 : + y_avValue_fst__h743763 ; + assign y_avValue_new_pc__h722133 = (csrf_stvec_mode_low_reg && commitStage_commitTrap[36]) ? - base__h722254 + { 58'd0, x__h722269 } : - base__h722254 ; - assign y_avValue_new_pc__h722216 = + base__h722357 + { 58'd0, x__h722372 } : + base__h722357 ; + assign y_avValue_new_pc__h722319 = (csrf_mtvec_mode_low_reg && commitStage_commitTrap[36]) ? - base__h722274 + { 58'd0, x__h722269 } : - base__h722274 ; - assign y_avValue_snd_snd_snd_fst__h740915 = + base__h722377 + { 58'd0, x__h722372 } : + base__h722377 ; + assign y_avValue_snd_snd_snd_fst__h741018 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[167] || rob$deqPort_0_deq_data[329:325] == 5'd0 || @@ -32652,7 +32660,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[329:325] == 5'd20) ? 2'd0 : 2'd1 ; - assign y_avValue_snd_snd_snd_fst__h743829 = + assign y_avValue_snd_snd_snd_fst__h743932 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[329:325] == 5'd0 || @@ -32664,12 +32672,12 @@ module mkCore(CLK, rob$deqPort_1_deq_data[329:325] == 5'd15 || rob$deqPort_1_deq_data[329:325] == 5'd19 || rob$deqPort_1_deq_data[329:325] == 5'd20) ? - IF_rob_deqPort_0_canDeq__5654_THEN_IF_NOT_rob__ETC___d16005 : - y_avValue_snd_snd_snd_fst__h743865 ; - assign y_avValue_snd_snd_snd_fst__h743865 = - IF_rob_deqPort_0_canDeq__5654_THEN_IF_NOT_rob__ETC___d16005 + + IF_rob_deqPort_0_canDeq__5664_THEN_IF_NOT_rob__ETC___d16015 : + y_avValue_snd_snd_snd_fst__h743968 ; + assign y_avValue_snd_snd_snd_fst__h743968 = + IF_rob_deqPort_0_canDeq__5664_THEN_IF_NOT_rob__ETC___d16015 + 2'd1 ; - assign y_avValue_snd_snd_snd_snd_snd_fst__h740925 = + assign y_avValue_snd_snd_snd_snd_snd_fst__h741028 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[167] || rob$deqPort_0_deq_data[329:325] == 5'd0 || @@ -32683,7 +32691,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[329:325] == 5'd20) ? 64'd0 : 64'd1 ; - assign y_avValue_snd_snd_snd_snd_snd_fst__h743839 = + assign y_avValue_snd_snd_snd_snd_snd_fst__h743942 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[329:325] == 5'd0 || @@ -32695,10 +32703,10 @@ module mkCore(CLK, rob$deqPort_1_deq_data[329:325] == 5'd15 || rob$deqPort_1_deq_data[329:325] == 5'd19 || rob$deqPort_1_deq_data[329:325] == 5'd20) ? - y__h740902 : - y_avValue_snd_snd_snd_snd_snd_fst__h743875 ; - assign y_avValue_snd_snd_snd_snd_snd_fst__h743875 = y__h740902 + 64'd1 ; - assign y_avValue_snd_snd_snd_snd_snd_snd_snd__h743190 = x__h736159 ; + y__h741005 : + y_avValue_snd_snd_snd_snd_snd_fst__h743978 ; + assign y_avValue_snd_snd_snd_snd_snd_fst__h743978 = y__h741005 + 64'd1 ; + assign y_avValue_snd_snd_snd_snd_snd_snd_snd__h743293 = x__h736262 ; always@(v_f_to_TV_1$D_OUT) begin case (v_f_to_TV_1$D_OUT[475:464]) @@ -33007,9 +33015,9 @@ module mkCore(CLK, always@(commitStage_commitTrap) begin case (commitStage_commitTrap[35:32]) - 4'd0, 4'd3: trap_val__h720333 = commitStage_commitTrap[164:101]; - 4'd2: trap_val__h720333 = { 32'd0, commitStage_commitTrap[31:0] }; - default: trap_val__h720333 = + 4'd0, 4'd3: trap_val__h720436 = commitStage_commitTrap[164:101]; + 4'd2: trap_val__h720436 = { 32'd0, commitStage_commitTrap[31:0] }; + default: trap_val__h720436 = (commitStage_commitTrap[35:32] != 4'd8 && commitStage_commitTrap[35:32] != 4'd9 && commitStage_commitTrap[35:32] != 4'd11) ? @@ -33065,46 +33073,46 @@ module mkCore(CLK, n__read__h617696 or n__read__h617887 or csrf_time_reg) begin case (f_csr_reqs$D_OUT[75:64]) - 12'd1: data_out__h747867 = fflags_csr__read__h615692; - 12'd2: data_out__h747867 = frm_csr__read__h615703; - 12'd3: data_out__h747867 = fcsr_csr__read__h615717; - 12'd256: data_out__h747867 = sstatus_csr__read__h615913; - 12'd260: data_out__h747867 = sie_csr__read__h615983; - 12'd261: data_out__h747867 = stvec_csr__read__h616026; - 12'd262: data_out__h747867 = scounteren_csr__read__h616079; - 12'd320: data_out__h747867 = csrf_sscratch_csr; - 12'd321: data_out__h747867 = csrf_sepc_csr; - 12'd322: data_out__h747867 = scause_csr__read__h616217; - 12'd323: data_out__h747867 = csrf_stval_csr; - 12'd324: data_out__h747867 = sip_csr__read__h616357; - 12'd384: data_out__h747867 = satp_csr__read__h616420; - 12'd768: data_out__h747867 = mstatus_csr__read__h616563; - 12'd769: data_out__h747867 = 64'h800000000014112D; - 12'd770: data_out__h747867 = medeleg_csr__read__h616711; - 12'd771: data_out__h747867 = mideleg_csr__read__h616806; - 12'd772: data_out__h747867 = mie_csr__read__h616930; - 12'd773: data_out__h747867 = mtvec_csr__read__h617012; - 12'd774: data_out__h747867 = mcounteren_csr__read__h617104; - 12'd832: data_out__h747867 = csrf_mscratch_csr; - 12'd833: data_out__h747867 = csrf_mepc_csr; - 12'd834: data_out__h747867 = mcause_csr__read__h617359; - 12'd835: data_out__h747867 = csrf_mtval_csr; - 12'd836: data_out__h747867 = mip_csr__read__h617592; - 12'd1952: data_out__h747867 = csrf_rg_tselect; - 12'd1953: data_out__h747867 = rg_tdata1__read__h618547; - 12'd1954: data_out__h747867 = csrf_rg_tdata2; - 12'd1955: data_out__h747867 = csrf_rg_tdata3; - 12'd1968: data_out__h747867 = csrf_rg_dcsr; - 12'd1969: data_out__h747867 = csrf_rg_dpc; - 12'd1970: data_out__h747867 = csrf_rg_dscratch0; - 12'd1971: data_out__h747867 = csrf_rg_dscratch1; + 12'd1: data_out__h747970 = fflags_csr__read__h615692; + 12'd2: data_out__h747970 = frm_csr__read__h615703; + 12'd3: data_out__h747970 = fcsr_csr__read__h615717; + 12'd256: data_out__h747970 = sstatus_csr__read__h615913; + 12'd260: data_out__h747970 = sie_csr__read__h615983; + 12'd261: data_out__h747970 = stvec_csr__read__h616026; + 12'd262: data_out__h747970 = scounteren_csr__read__h616079; + 12'd320: data_out__h747970 = csrf_sscratch_csr; + 12'd321: data_out__h747970 = csrf_sepc_csr; + 12'd322: data_out__h747970 = scause_csr__read__h616217; + 12'd323: data_out__h747970 = csrf_stval_csr; + 12'd324: data_out__h747970 = sip_csr__read__h616357; + 12'd384: data_out__h747970 = satp_csr__read__h616420; + 12'd768: data_out__h747970 = mstatus_csr__read__h616563; + 12'd769: data_out__h747970 = 64'h800000000014112D; + 12'd770: data_out__h747970 = medeleg_csr__read__h616711; + 12'd771: data_out__h747970 = mideleg_csr__read__h616806; + 12'd772: data_out__h747970 = mie_csr__read__h616930; + 12'd773: data_out__h747970 = mtvec_csr__read__h617012; + 12'd774: data_out__h747970 = mcounteren_csr__read__h617104; + 12'd832: data_out__h747970 = csrf_mscratch_csr; + 12'd833: data_out__h747970 = csrf_mepc_csr; + 12'd834: data_out__h747970 = mcause_csr__read__h617359; + 12'd835: data_out__h747970 = csrf_mtval_csr; + 12'd836: data_out__h747970 = mip_csr__read__h617592; + 12'd1952: data_out__h747970 = csrf_rg_tselect; + 12'd1953: data_out__h747970 = rg_tdata1__read__h618547; + 12'd1954: data_out__h747970 = csrf_rg_tdata2; + 12'd1955: data_out__h747970 = csrf_rg_tdata3; + 12'd1968: data_out__h747970 = csrf_rg_dcsr; + 12'd1969: data_out__h747970 = csrf_rg_dpc; + 12'd1970: data_out__h747970 = csrf_rg_dscratch0; + 12'd1971: data_out__h747970 = csrf_rg_dscratch1; 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: - data_out__h747867 = 64'd0; - 12'd2049: data_out__h747867 = x_reg_ifc__read__h615822; - 12'd2816, 12'd3072: data_out__h747867 = n__read__h617696; - 12'd2818, 12'd3074: data_out__h747867 = n__read__h617887; - 12'd3073: data_out__h747867 = csrf_time_reg; - default: data_out__h747867 = 64'b0; + data_out__h747970 = 64'd0; + 12'd2049: data_out__h747970 = x_reg_ifc__read__h615822; + 12'd2816, 12'd3072: data_out__h747970 = n__read__h617696; + 12'd2818, 12'd3074: data_out__h747970 = n__read__h617887; + 12'd3073: data_out__h747970 = csrf_time_reg; + default: data_out__h747970 = 64'b0; endcase end always@(coreFix_aluExe_1_dispToRegQ$first or @@ -33527,16 +33535,16 @@ module mkCore(CLK, 4'd11, 4'd12, 4'd13: - i__h719309 = commitStage_commitTrap[35:32]; - default: i__h719309 = 4'd15; + i__h719412 = commitStage_commitTrap[35:32]; + default: i__h719412 = 4'd15; endcase end always@(commitStage_commitTrap) begin case (commitStage_commitTrap[35:32]) 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: - i__h719469 = commitStage_commitTrap[35:32]; - default: i__h719469 = 4'd15; + i__h719572 = commitStage_commitTrap[35:32]; + default: i__h719572 = 4'd15; endcase end always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) @@ -37883,15 +37891,15 @@ module mkCore(CLK, 4'd13; endcase end - always@(k__h678117 or + always@(k__h678220 or coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq) begin - case (k__h678117) + case (k__h678220) 1'd0: - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3689_co_ETC___d13699 = + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3699_co_ETC___d13709 = coreFix_aluExe_0_rsAlu$canEnq; 1'd1: - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3689_co_ETC___d13699 = + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3699_co_ETC___d13709 = coreFix_aluExe_1_rsAlu$canEnq; endcase end @@ -37900,65 +37908,65 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13711 = + IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13721 = coreFix_memExe_lsq$enqLdTag[6]; - default: IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13711 = + default: IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13721 = coreFix_memExe_lsq$enqStTag[6]; endcase end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13711 or - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3689_co_ETC___d13699 or + IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13721 or + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3699_co_ETC___d13709 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13715 = - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3689_co_ETC___d13699; + IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13725 = + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3699_co_ETC___d13709; 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13715 = + IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13725 = coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq; - default: IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13715 = + default: IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13725 = fetchStage$pipelines_0_first[194:192] != 3'd2 || coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13711; + IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13721; endcase end - always@(k__h678117 or + always@(k__h678220 or coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq) begin - case (k__h678117) + case (k__h678220) 1'd0: - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__368_ETC___d13732 = + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__369_ETC___d13742 = !coreFix_aluExe_0_rsAlu$canEnq; 1'd1: - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__368_ETC___d13732 = + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__369_ETC___d13742 = !coreFix_aluExe_1_rsAlu$canEnq; endcase end always@(fetchStage$pipelines_0_first or - regRenamingTable_rename_0_canRename__3658_AND__ETC___d13680 or - NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13734 or + regRenamingTable_rename_0_canRename__3668_AND__ETC___d13690 or + NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13744 or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13711 or + IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13721 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13739 = - NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13734; + IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13749 = + NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13744; 3'd2: - IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13739 = + IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13749 = coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13711 && - regRenamingTable_rename_0_canRename__3658_AND__ETC___d13680; + IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13721 && + regRenamingTable_rename_0_canRename__3668_AND__ETC___d13690; 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13739 = + IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13749 = coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq && - regRenamingTable_rename_0_canRename__3658_AND__ETC___d13680; - default: IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13739 = - regRenamingTable_rename_0_canRename__3658_AND__ETC___d13680; + regRenamingTable_rename_0_canRename__3668_AND__ETC___d13690; + default: IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13749 = + regRenamingTable_rename_0_canRename__3668_AND__ETC___d13690; endcase end always@(fetchStage$pipelines_0_first or @@ -37966,32 +37974,32 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13769 = + IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13779 = !coreFix_memExe_lsq$enqLdTag[6]; - default: IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13769 = + default: IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13779 = !coreFix_memExe_lsq$enqStTag[6]; endcase end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13769 or - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__368_ETC___d13732 or + IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13779 or + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__369_ETC___d13742 or specTagManager$canClaim or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13774 = - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__368_ETC___d13732 || + IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13784 = + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__369_ETC___d13742 || fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim; 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13774 = + IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13784 = !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq; - default: IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13774 = + default: IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13784 = fetchStage$pipelines_0_first[194:192] == 3'd2 && (!coreFix_memExe_rsMem$canEnq || - IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13769); + IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13779); endcase end always@(fetchStage$pipelines_1_first) @@ -38061,36 +38069,36 @@ module mkCore(CLK, begin case (fetchStage$pipelines_1_first[194:192]) 3'd0, 3'd1, 3'd2, 3'd3: - IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d13834 = + IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d13844 = fetchStage$pipelines_1_first[194:174]; 3'd4: - IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d13834 = + IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d13844 = { fetchStage$pipelines_1_first[194:192], 9'h0AA, fetchStage$pipelines_1_first[182:178], CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q236, fetchStage$pipelines_1_first[174] }; - default: IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d13834 = + default: IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d13844 = 21'd1485482; endcase end - always@(idx__h694474 or + always@(idx__h694577 or fetchStage$pipelines_0_canDeq or - NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d13996 or + NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d14006 or coreFix_aluExe_0_rsAlu$canEnq or - NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d14002 or + NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d14012 or coreFix_aluExe_1_rsAlu$canEnq) begin - case (idx__h694474) + case (idx__h694577) 1'd0: - SEL_ARR_fetchStage_pipelines_0_canDeq__2990_AN_ETC___d14022 = + SEL_ARR_fetchStage_pipelines_0_canDeq__2990_AN_ETC___d14032 = fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d13996 || + NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d14006 || !coreFix_aluExe_0_rsAlu$canEnq; 1'd1: - SEL_ARR_fetchStage_pipelines_0_canDeq__2990_AN_ETC___d14022 = + SEL_ARR_fetchStage_pipelines_0_canDeq__2990_AN_ETC___d14032 = fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d14002 || + NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d14012 || !coreFix_aluExe_1_rsAlu$canEnq; endcase end @@ -38106,61 +38114,61 @@ module mkCore(CLK, endcase end always@(fetchStage$pipelines_0_first or - renameStage_rg_m_halt_req_3019_BIT_4_3020_OR_f_ETC___d14090 or - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__368_ETC___d13732 or - fetchStage_pipelines_0_first__2992_BITS_194_TO_ETC___d14094 or + renameStage_rg_m_halt_req_3019_BIT_4_3020_OR_f_ETC___d14100 or + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__369_ETC___d13742 or + fetchStage_pipelines_0_first__2992_BITS_194_TO_ETC___d14104 or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13769 or + IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13779 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14100 = - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__368_ETC___d13732 || - fetchStage_pipelines_0_first__2992_BITS_194_TO_ETC___d14094; + IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14110 = + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__369_ETC___d13742 || + fetchStage_pipelines_0_first__2992_BITS_194_TO_ETC___d14104; 3'd2: - IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14100 = + IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14110 = !coreFix_memExe_rsMem$canEnq || - IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13769 || - renameStage_rg_m_halt_req_3019_BIT_4_3020_OR_f_ETC___d14090; + IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13779 || + renameStage_rg_m_halt_req_3019_BIT_4_3020_OR_f_ETC___d14100; 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14100 = + IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14110 = !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq || - renameStage_rg_m_halt_req_3019_BIT_4_3020_OR_f_ETC___d14090; - default: IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14100 = - renameStage_rg_m_halt_req_3019_BIT_4_3020_OR_f_ETC___d14090; + renameStage_rg_m_halt_req_3019_BIT_4_3020_OR_f_ETC___d14100; + default: IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14110 = + renameStage_rg_m_halt_req_3019_BIT_4_3020_OR_f_ETC___d14100; endcase end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13711 or - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3689_co_ETC___d13699) + IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13721 or + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3699_co_ETC___d13709) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14122 = - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3689_co_ETC___d13699; - default: IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14122 = + IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14132 = + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3699_co_ETC___d13709; + default: IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14132 = fetchStage$pipelines_0_first[194:192] != 3'd2 || coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13711; + IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13721; endcase end always@(fetchStage$pipelines_0_first or - IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13711 or - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3689_co_ETC___d13699 or + IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13721 or + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3699_co_ETC___d13709 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14140 = - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3689_co_ETC___d13699; + IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14150 = + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3699_co_ETC___d13709; 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14140 = + IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14150 = coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq; - default: IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14140 = + default: IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14150 = fetchStage$pipelines_0_first[194:192] != 3'd2 || - IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13711; + IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13721; endcase end always@(fetchStage$pipelines_1_first or @@ -38175,62 +38183,31 @@ module mkCore(CLK, endcase end always@(fetchStage$pipelines_1_first or - regRenamingTable_rename_1_canRename__3780_AND__ETC___d13988 or - SEL_ARR_fetchStage_pipelines_0_canDeq__2990_AN_ETC___d14022 or - NOT_fetchStage_pipelines_1_first__3001_BITS_19_ETC___d14106 or - NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14137 or - regRenamingTable_rename_1_canRename__3780_AND__ETC___d14148 or - NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14119 or + regRenamingTable_rename_1_canRename__3790_AND__ETC___d13998 or + SEL_ARR_fetchStage_pipelines_0_canDeq__2990_AN_ETC___d14032 or + NOT_fetchStage_pipelines_1_first__3001_BITS_19_ETC___d14116 or + NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14147 or + regRenamingTable_rename_1_canRename__3790_AND__ETC___d14158 or + NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14129 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq or - regRenamingTable_rename_1_canRename__3780_AND__ETC___d14130) + regRenamingTable_rename_1_canRename__3790_AND__ETC___d14140) begin case (fetchStage$pipelines_1_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d14152 = - !SEL_ARR_fetchStage_pipelines_0_canDeq__2990_AN_ETC___d14022 && - NOT_fetchStage_pipelines_1_first__3001_BITS_19_ETC___d14106; + IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d14162 = + !SEL_ARR_fetchStage_pipelines_0_canDeq__2990_AN_ETC___d14032 && + NOT_fetchStage_pipelines_1_first__3001_BITS_19_ETC___d14116; 3'd2: - IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d14152 = - NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14137 && - regRenamingTable_rename_1_canRename__3780_AND__ETC___d14148; + IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d14162 = + NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14147 && + regRenamingTable_rename_1_canRename__3790_AND__ETC___d14158; 3'd3, 3'd4: - IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d14152 = - NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14119 && + IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d14162 = + NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14129 && coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq && - regRenamingTable_rename_1_canRename__3780_AND__ETC___d14130; - default: IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d14152 = - regRenamingTable_rename_1_canRename__3780_AND__ETC___d13988; - endcase - end - always@(k__h678117 or - coreFix_aluExe_0_rsAlu$RDY_enq or coreFix_aluExe_1_rsAlu$RDY_enq) - begin - case (k__h678117) - 1'd0: - CASE_k78117_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239 = - coreFix_aluExe_0_rsAlu$RDY_enq; - 1'd1: - CASE_k78117_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239 = - coreFix_aluExe_1_rsAlu$RDY_enq; - endcase - end - always@(fetchStage$pipelines_0_first or - coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13769 or - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__368_ETC___d13732 or - coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) - begin - case (fetchStage$pipelines_0_first[194:192]) - 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14197 = - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__368_ETC___d13732; - 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14197 = - !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq; - default: IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14197 = - fetchStage$pipelines_0_first[194:192] == 3'd2 && - (!coreFix_memExe_rsMem$canEnq || - IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13769); + regRenamingTable_rename_1_canRename__3790_AND__ETC___d14140; + default: IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d14162 = + regRenamingTable_rename_1_canRename__3790_AND__ETC___d13998; endcase end always@(fetchStage$pipelines_0_first or @@ -38238,105 +38215,136 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q240 = + CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q239 = coreFix_memExe_lsq$RDY_enqLd; - default: CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q240 = + default: CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q239 = coreFix_memExe_lsq$RDY_enqSt; endcase end + always@(k__h678220 or + coreFix_aluExe_0_rsAlu$RDY_enq or coreFix_aluExe_1_rsAlu$RDY_enq) + begin + case (k__h678220) + 1'd0: + CASE_k78220_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q240 = + coreFix_aluExe_0_rsAlu$RDY_enq; + 1'd1: + CASE_k78220_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q240 = + coreFix_aluExe_1_rsAlu$RDY_enq; + endcase + end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13769 or - regRenamingTable_RDY_rename_0_getRename__3535__ETC___d14191 or - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3689_co_ETC___d13699 or + IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13779 or + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__369_ETC___d13742 or + coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) + begin + case (fetchStage$pipelines_0_first[194:192]) + 3'd0, 3'd1: + IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14207 = + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__369_ETC___d13742; + 3'd3, 3'd4: + IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14207 = + !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq; + default: IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14207 = + fetchStage$pipelines_0_first[194:192] == 3'd2 && + (!coreFix_memExe_rsMem$canEnq || + IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13779); + endcase + end + always@(fetchStage$pipelines_0_first or + coreFix_memExe_rsMem$canEnq or + IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13779 or + regRenamingTable_RDY_rename_0_getRename__3535__ETC___d14201 or + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3699_co_ETC___d13709 or regRenamingTable$RDY_rename_0_getRename or - _0_OR_NOT_fetchStage_pipelines_0_first__2992_BI_ETC___d14178 or + _0_OR_NOT_fetchStage_pipelines_0_first__2992_BI_ETC___d14188 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq or coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_enq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14195 = - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3689_co_ETC___d13699 || + IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14205 = + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3699_co_ETC___d13709 || regRenamingTable$RDY_rename_0_getRename && - _0_OR_NOT_fetchStage_pipelines_0_first__2992_BI_ETC___d14178; + _0_OR_NOT_fetchStage_pipelines_0_first__2992_BI_ETC___d14188; 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14195 = + IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14205 = !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq || coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_enq && regRenamingTable$RDY_rename_0_getRename; - default: IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14195 = + default: IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14205 = fetchStage$pipelines_0_first[194:192] != 3'd2 || !coreFix_memExe_rsMem$canEnq || - IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13769 || - regRenamingTable_RDY_rename_0_getRename__3535__ETC___d14191; + IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13779 || + regRenamingTable_RDY_rename_0_getRename__3535__ETC___d14201; endcase end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13769 or - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3689_co_ETC___d13699 or + IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13779 or + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3699_co_ETC___d13709 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14211 = - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3689_co_ETC___d13699; + IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14221 = + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3699_co_ETC___d13709; 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14211 = + IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14221 = !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq; - default: IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14211 = + default: IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14221 = fetchStage$pipelines_0_first[194:192] == 3'd2 && (!coreFix_memExe_rsMem$canEnq || - IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13769); + IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13779); endcase end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13711 or - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__368_ETC___d13732 or + IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13721 or + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__369_ETC___d13742 or specTagManager$canClaim or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14218 = - !SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__368_ETC___d13732 && + IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14228 = + !SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__369_ETC___d13742 && (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim); 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14218 = + IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14228 = coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq; - default: IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14218 = + default: IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14228 = fetchStage$pipelines_0_first[194:192] != 3'd2 || coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13711; + IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13721; endcase end - always@(idx__h694474 or + always@(idx__h694577 or fetchStage$pipelines_0_canDeq or - fetchStage_pipelines_0_first__2992_BITS_194_TO_ETC___d14241 or + fetchStage_pipelines_0_first__2992_BITS_194_TO_ETC___d14251 or coreFix_aluExe_0_rsAlu$canEnq or - fetchStage_pipelines_0_first__2992_BITS_194_TO_ETC___d14248 or + fetchStage_pipelines_0_first__2992_BITS_194_TO_ETC___d14258 or coreFix_aluExe_1_rsAlu$canEnq) begin - case (idx__h694474) + case (idx__h694577) 1'd0: - SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__299_ETC___d14252 = + SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__299_ETC___d14262 = (!fetchStage$pipelines_0_canDeq || - fetchStage_pipelines_0_first__2992_BITS_194_TO_ETC___d14241) && + fetchStage_pipelines_0_first__2992_BITS_194_TO_ETC___d14251) && coreFix_aluExe_0_rsAlu$canEnq; 1'd1: - SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__299_ETC___d14252 = + SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__299_ETC___d14262 = (!fetchStage$pipelines_0_canDeq || - fetchStage_pipelines_0_first__2992_BITS_194_TO_ETC___d14248) && + fetchStage_pipelines_0_first__2992_BITS_194_TO_ETC___d14258) && coreFix_aluExe_1_rsAlu$canEnq; endcase end - always@(fetchStage_pipelines_0_canDeq__2990_AND_NOT_fe_ETC___d14268 or + always@(fetchStage_pipelines_0_canDeq__2990_AND_NOT_fe_ETC___d14278 or coreFix_aluExe_0_rsAlu$RDY_enq or coreFix_aluExe_1_rsAlu$RDY_enq) begin - case (fetchStage_pipelines_0_canDeq__2990_AND_NOT_fe_ETC___d14268) + case (fetchStage_pipelines_0_canDeq__2990_AND_NOT_fe_ETC___d14278) 1'd0: CASE_fetchStage_pipelines_0_canDeq__2990_AND_N_ETC__q241 = coreFix_aluExe_0_rsAlu$RDY_enq; @@ -38358,78 +38366,78 @@ module mkCore(CLK, end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13769 or - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3689_co_ETC___d13699) + IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13779 or + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3699_co_ETC___d13709) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14294 = - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3689_co_ETC___d13699; - default: IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14294 = + IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14304 = + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3699_co_ETC___d13709; + default: IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14304 = fetchStage$pipelines_0_first[194:192] == 3'd2 && (!coreFix_memExe_rsMem$canEnq || - IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13769); + IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13779); endcase end always@(fetchStage$pipelines_0_first or - IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13769 or - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3689_co_ETC___d13699 or + IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13779 or + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3699_co_ETC___d13709 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14306 = - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3689_co_ETC___d13699; + IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14316 = + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3699_co_ETC___d13709; 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14306 = + IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14316 = !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq; - default: IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14306 = + default: IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14316 = fetchStage$pipelines_0_first[194:192] == 3'd2 && - IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13769; + IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13779; endcase end always@(fetchStage$pipelines_1_first or - fetchStage_pipelines_0_canDeq__2990_AND_regRen_ETC___d14315 or - SEL_ARR_fetchStage_pipelines_0_canDeq__2990_AN_ETC___d14022 or - fetchStage_pipelines_0_canDeq__2990_AND_regRen_ETC___d14303) + fetchStage_pipelines_0_canDeq__2990_AND_regRen_ETC___d14325 or + SEL_ARR_fetchStage_pipelines_0_canDeq__2990_AN_ETC___d14032 or + fetchStage_pipelines_0_canDeq__2990_AND_regRen_ETC___d14313) begin case (fetchStage$pipelines_1_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d14318 = - SEL_ARR_fetchStage_pipelines_0_canDeq__2990_AN_ETC___d14022; + IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d14328 = + SEL_ARR_fetchStage_pipelines_0_canDeq__2990_AN_ETC___d14032; 3'd3, 3'd4: - IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d14318 = - fetchStage_pipelines_0_canDeq__2990_AND_regRen_ETC___d14303; - default: IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d14318 = + IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d14328 = + fetchStage_pipelines_0_canDeq__2990_AND_regRen_ETC___d14313; + default: IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d14328 = fetchStage$pipelines_1_first[194:192] == 3'd2 && - fetchStage_pipelines_0_canDeq__2990_AND_regRen_ETC___d14315; + fetchStage_pipelines_0_canDeq__2990_AND_regRen_ETC___d14325; endcase end always@(fetchStage$pipelines_1_first or - fetchStage_pipelines_0_canDeq__2990_AND_regRen_ETC___d14281 or + fetchStage_pipelines_0_canDeq__2990_AND_regRen_ETC___d14291 or regRenamingTable$RDY_rename_1_getRename or - NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14286 or - SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__299_ETC___d14252 or - regRenamingTable_RDY_rename_1_getRename__4254__ETC___d14272 or - fetchStage_pipelines_0_canDeq__2990_AND_regRen_ETC___d14274 or + NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14296 or + SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__299_ETC___d14262 or + regRenamingTable_RDY_rename_1_getRename__4264__ETC___d14282 or + fetchStage_pipelines_0_canDeq__2990_AND_regRen_ETC___d14284 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq or - coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__41_ETC___d14277) + coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__41_ETC___d14287) begin case (fetchStage$pipelines_1_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d14291 = - !SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__299_ETC___d14252 || - regRenamingTable_RDY_rename_1_getRename__4254__ETC___d14272; + IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d14301 = + !SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__299_ETC___d14262 || + regRenamingTable_RDY_rename_1_getRename__4264__ETC___d14282; 3'd3, 3'd4: - IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d14291 = - fetchStage_pipelines_0_canDeq__2990_AND_regRen_ETC___d14274 || + IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d14301 = + fetchStage_pipelines_0_canDeq__2990_AND_regRen_ETC___d14284 || !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq || - coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__41_ETC___d14277; - default: IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d14291 = + coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__41_ETC___d14287; + default: IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d14301 = fetchStage$pipelines_1_first[194:192] != 3'd2 || - fetchStage_pipelines_0_canDeq__2990_AND_regRen_ETC___d14281 || + fetchStage_pipelines_0_canDeq__2990_AND_regRen_ETC___d14291 || regRenamingTable$RDY_rename_1_getRename && - NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14286; + NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14296; endcase end always@(fetchStage$pipelines_0_first or @@ -38437,9 +38445,9 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d14392 = + IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d14402 = !coreFix_memExe_lsq$enqLdTag[5]; - default: IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d14392 = + default: IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d14402 = !coreFix_memExe_lsq$enqStTag[5]; endcase end @@ -38448,9 +38456,9 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d14389 = + IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d14399 = coreFix_memExe_lsq$enqLdTag[5]; - default: IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d14389 = + default: IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d14399 = coreFix_memExe_lsq$enqStTag[5]; endcase end @@ -38459,31 +38467,20 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d14398 = - coreFix_memExe_lsq$enqLdTag[3:0]; - default: IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d14398 = - coreFix_memExe_lsq$enqStTag[3:0]; - endcase - end - always@(fetchStage$pipelines_0_first or - coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag) - begin - case (fetchStage$pipelines_0_first[191:189]) - 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d14395 = + IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d14405 = coreFix_memExe_lsq$enqLdTag[4:0]; - default: IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d14395 = + default: IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d14405 = coreFix_memExe_lsq$enqStTag[4:0]; endcase end - always@(fetchStage$pipelines_1_first or + always@(fetchStage$pipelines_0_first or coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag) begin - case (fetchStage$pipelines_1_first[191:189]) + case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_1_first__3001_BITS_191_ETC___d14562 = + IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d14408 = coreFix_memExe_lsq$enqLdTag[3:0]; - default: IF_fetchStage_pipelines_1_first__3001_BITS_191_ETC___d14562 = + default: IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d14408 = coreFix_memExe_lsq$enqStTag[3:0]; endcase end @@ -38492,9 +38489,20 @@ module mkCore(CLK, begin case (fetchStage$pipelines_1_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_1_first__3001_BITS_191_ETC___d14560 = + IF_fetchStage_pipelines_1_first__3001_BITS_191_ETC___d14572 = + coreFix_memExe_lsq$enqLdTag[3:0]; + default: IF_fetchStage_pipelines_1_first__3001_BITS_191_ETC___d14572 = + coreFix_memExe_lsq$enqStTag[3:0]; + endcase + end + always@(fetchStage$pipelines_1_first or + coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag) + begin + case (fetchStage$pipelines_1_first[191:189]) + 3'd0, 3'd2: + IF_fetchStage_pipelines_1_first__3001_BITS_191_ETC___d14570 = !coreFix_memExe_lsq$enqLdTag[5]; - default: IF_fetchStage_pipelines_1_first__3001_BITS_191_ETC___d14560 = + default: IF_fetchStage_pipelines_1_first__3001_BITS_191_ETC___d14570 = !coreFix_memExe_lsq$enqStTag[5]; endcase end @@ -38503,9 +38511,9 @@ module mkCore(CLK, begin case (fetchStage$pipelines_1_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_1_first__3001_BITS_191_ETC___d14559 = + IF_fetchStage_pipelines_1_first__3001_BITS_191_ETC___d14569 = coreFix_memExe_lsq$enqLdTag[5]; - default: IF_fetchStage_pipelines_1_first__3001_BITS_191_ETC___d14559 = + default: IF_fetchStage_pipelines_1_first__3001_BITS_191_ETC___d14569 = coreFix_memExe_lsq$enqStTag[5]; endcase end @@ -38514,9 +38522,9 @@ module mkCore(CLK, begin case (fetchStage$pipelines_1_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_1_first__3001_BITS_191_ETC___d14561 = + IF_fetchStage_pipelines_1_first__3001_BITS_191_ETC___d14571 = coreFix_memExe_lsq$enqLdTag[4:0]; - default: IF_fetchStage_pipelines_1_first__3001_BITS_191_ETC___d14561 = + default: IF_fetchStage_pipelines_1_first__3001_BITS_191_ETC___d14571 = coreFix_memExe_lsq$enqStTag[4:0]; endcase end @@ -38550,112 +38558,112 @@ module mkCore(CLK, begin case (rob$deqPort_0_deq_data[180:169]) 12'd1: - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 = 6'd0; + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 = 6'd0; 12'd2: - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 = 6'd1; + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 = 6'd1; 12'd3: - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 = 6'd2; + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 = 6'd2; 12'd256: - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 = 6'd8; + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 = 6'd8; 12'd260: - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 = 6'd9; + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 = 6'd9; 12'd261: - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 = 6'd10; + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 = 6'd10; 12'd262: - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 = 6'd11; + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 = 6'd11; 12'd320: - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 = 6'd12; + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 = 6'd12; 12'd321: - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 = 6'd13; + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 = 6'd13; 12'd322: - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 = 6'd14; + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 = 6'd14; 12'd323: - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 = 6'd15; + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 = 6'd15; 12'd324: - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 = 6'd16; + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 = 6'd16; 12'd384: - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 = 6'd17; + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 = 6'd17; 12'd768: - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 = 6'd18; + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 = 6'd18; 12'd769: - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 = 6'd19; + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 = 6'd19; 12'd770: - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 = 6'd20; + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 = 6'd20; 12'd771: - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 = 6'd21; + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 = 6'd21; 12'd772: - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 = 6'd22; + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 = 6'd22; 12'd773: - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 = 6'd23; + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 = 6'd23; 12'd774: - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 = 6'd24; + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 = 6'd24; 12'd832: - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 = 6'd25; + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 = 6'd25; 12'd833: - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 = 6'd26; + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 = 6'd26; 12'd834: - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 = 6'd27; + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 = 6'd27; 12'd835: - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 = 6'd28; + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 = 6'd28; 12'd836: - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 = 6'd29; + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 = 6'd29; 12'd1952: - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 = 6'd36; + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 = 6'd36; 12'd1953: - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 = 6'd37; + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 = 6'd37; 12'd1954: - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 = 6'd38; + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 = 6'd38; 12'd1955: - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 = 6'd39; + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 = 6'd39; 12'd1968: - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 = 6'd40; + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 = 6'd40; 12'd1969: - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 = 6'd41; + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 = 6'd41; 12'd1970: - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 = 6'd42; + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 = 6'd42; 12'd1971: - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 = 6'd43; + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 = 6'd43; 12'd2048: - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 = 6'd6; + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 = 6'd6; 12'd2049: - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 = 6'd7; + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 = 6'd7; 12'd2816: - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 = 6'd30; + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 = 6'd30; 12'd2818: - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 = 6'd31; + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 = 6'd31; 12'd3072: - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 = 6'd3; + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 = 6'd3; 12'd3073: - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 = 6'd4; + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 = 6'd4; 12'd3074: - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 = 6'd5; + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 = 6'd5; 12'd3857: - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 = 6'd32; + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 = 6'd32; 12'd3858: - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 = 6'd33; + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 = 6'd33; 12'd3859: - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 = 6'd34; + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 = 6'd34; 12'd3860: - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 = 6'd35; - default: IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 = + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 = 6'd35; + default: IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 = 6'd44; endcase end - always@(IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 or + always@(IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 or rob$deqPort_0_deq_data or robdeqPort_0_deq_data_BITS_95_TO_32__q245) begin - case (IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300) + case (IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310) 6'd0: - data_warl_xformed__h732513 = + data_warl_xformed__h732616 = { 59'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[4:0] }; 6'd1, 6'd11, 6'd24: - data_warl_xformed__h732513 = + data_warl_xformed__h732616 = { 61'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[2:0] }; 6'd2: - data_warl_xformed__h732513 = + data_warl_xformed__h732616 = { 56'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[7:0] }; 6'd8: - data_warl_xformed__h732513 = + data_warl_xformed__h732616 = { robdeqPort_0_deq_data_BITS_95_TO_32__q245[14:13] == 2'b11, 43'd8192, robdeqPort_0_deq_data_BITS_95_TO_32__q245[19:18], @@ -38668,7 +38676,7 @@ module mkCore(CLK, 2'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[1:0] }; 6'd9, 6'd16: - data_warl_xformed__h732513 = + data_warl_xformed__h732616 = { 54'd0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[9], 3'd0, @@ -38677,22 +38685,22 @@ module mkCore(CLK, robdeqPort_0_deq_data_BITS_95_TO_32__q245[1], 1'd0 }; 6'd10, 6'd23: - data_warl_xformed__h732513 = + data_warl_xformed__h732616 = { robdeqPort_0_deq_data_BITS_95_TO_32__q245[63:2], 1'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[0] }; 6'd14, 6'd27: - data_warl_xformed__h732513 = + data_warl_xformed__h732616 = { robdeqPort_0_deq_data_BITS_95_TO_32__q245[63], 59'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[3:0] }; 6'd17: - data_warl_xformed__h732513 = + data_warl_xformed__h732616 = { robdeqPort_0_deq_data_BITS_95_TO_32__q245[63], 19'd0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[43:0] }; 6'd18: - data_warl_xformed__h732513 = + data_warl_xformed__h732616 = { robdeqPort_0_deq_data_BITS_95_TO_32__q245[14:13] == 2'b11, 40'd5120, robdeqPort_0_deq_data_BITS_95_TO_32__q245[22:17], @@ -38704,9 +38712,9 @@ module mkCore(CLK, robdeqPort_0_deq_data_BITS_95_TO_32__q245[5:3], 1'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[1:0] }; - 6'd19: data_warl_xformed__h732513 = 64'h800000000014112D; + 6'd19: data_warl_xformed__h732616 = 64'h800000000014112D; 6'd20: - data_warl_xformed__h732513 = + data_warl_xformed__h732616 = { 48'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[15], 1'b0, @@ -38714,7 +38722,7 @@ module mkCore(CLK, 1'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[9:0] }; 6'd21: - data_warl_xformed__h732513 = + data_warl_xformed__h732616 = { 52'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[11], 1'b0, @@ -38724,7 +38732,7 @@ module mkCore(CLK, 1'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[1:0] }; 6'd22, 6'd29: - data_warl_xformed__h732513 = + data_warl_xformed__h732616 = { 52'd0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[11], 1'd0, @@ -38738,12 +38746,12 @@ module mkCore(CLK, 1'd0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[1], 1'd0 }; - 6'd32, 6'd33, 6'd34, 6'd35: data_warl_xformed__h732513 = 64'd0; + 6'd32, 6'd33, 6'd34, 6'd35: data_warl_xformed__h732616 = 64'd0; 6'd37: - data_warl_xformed__h732513 = + data_warl_xformed__h732616 = { 4'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[59:0] }; 6'd40: - data_warl_xformed__h732513 = + data_warl_xformed__h732616 = { 32'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[31:28], 12'b0, @@ -38752,17 +38760,17 @@ module mkCore(CLK, robdeqPort_0_deq_data_BITS_95_TO_32__q245[13:6], 1'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[4:0] }; - default: data_warl_xformed__h732513 = rob$deqPort_0_deq_data[95:32]; + default: data_warl_xformed__h732616 = rob$deqPort_0_deq_data[95:32]; endcase end always@(rob$deqPort_0_deq_data or - IF_rob_deqPort_0_deq_data__4651_BITS_329_TO_32_ETC___d15510) + IF_rob_deqPort_0_deq_data__4661_BITS_329_TO_32_ETC___d15520) begin case (rob$deqPort_0_deq_data[329:325]) 5'd19, 5'd20: - x__h733185 = - IF_rob_deqPort_0_deq_data__4651_BITS_329_TO_32_ETC___d15510; - default: x__h733185 = rob$deqPort_0_deq_data[425:362]; + x__h733288 = + IF_rob_deqPort_0_deq_data__4661_BITS_329_TO_32_ETC___d15520; + default: x__h733288 = rob$deqPort_0_deq_data[425:362]; endcase end always@(rob$deqPort_0_deq_data) @@ -38979,15 +38987,6 @@ module mkCore(CLK, endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd4, 3'd3, 3'd2, 3'd1, 3'd0: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q259 = - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q259 = 3'd7; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd0: @@ -39218,6 +39217,15 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0]; endcase end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd4, 3'd3, 3'd2, 3'd1, 3'd0: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q259 = + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q259 = 3'd7; + endcase + end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9999 or IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9289 or @@ -41629,14 +41637,14 @@ module mkCore(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4651_BIT_181_4726_T_ETC___d15300 == 6'd6) + IF_rob_deqPort_0_deq_data__4661_BIT_181_4736_T_ETC___d15310 == 6'd6) $display("[Terminate CSR] being written (val = %x), ", "send terminate signal to host", rob$deqPort_0_deq_data[95:32]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && - next_pc__h732539 != - rob_deqPort_0_deq_data__4651_BITS_425_TO_362_4_ETC___d15501) + next_pc__h732642 != + rob_deqPort_0_deq_data__4661_BITS_425_TO_362_4_ETC___d15511) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && @@ -41768,7 +41776,7 @@ module mkCore(CLK, rob$deqPort_1_deq_data[329:325] != 5'd19 && rob$deqPort_1_deq_data[329:325] != 5'd20) $write("instret:%0d PC:0x%0h instr:0x%08h", - commitStage_rg_serial_num_4640_PLUS_IF_rob_deq_ETC___d15776, + commitStage_rg_serial_num_4650_PLUS_IF_rob_deq_ETC___d15786, rob$deqPort_1_deq_data[425:362], rob$deqPort_1_deq_data[361:330], " iType:"); @@ -42340,66 +42348,66 @@ module mkCore(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3658_AND__ETC___d14375) + regRenamingTable_rename_0_canRename__3668_AND__ETC___d14385) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3658_AND__ETC___d14380) + regRenamingTable_rename_0_canRename__3668_AND__ETC___d14390) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3658_AND__ETC___d14405) + regRenamingTable_rename_0_canRename__3668_AND__ETC___d14415) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3658_AND__ETC___d14409) + regRenamingTable_rename_0_canRename__3668_AND__ETC___d14419) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3658_AND__ETC___d14415) + regRenamingTable_rename_0_canRename__3668_AND__ETC___d14425) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14545) + NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14555) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14475 && - regRenamingTable_rename_1_canRename__3780_AND__ETC___d14485 && + NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14485 && + regRenamingTable_rename_1_canRename__3790_AND__ETC___d14495 && fetchStage$pipelines_1_first[194:192] != 3'd0 && fetchStage$pipelines_1_first[194:192] != 3'd1 && (fetchStage$pipelines_1_first[194:192] == 3'd3 || fetchStage$pipelines_1_first[194:192] == 3'd4) && - NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14525 && + NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14535 && coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq && fetchStage$pipelines_1_first[173]) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14475 && - regRenamingTable_rename_1_canRename__3780_AND__ETC___d14485 && + NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14485 && + regRenamingTable_rename_1_canRename__3790_AND__ETC___d14495 && fetchStage$pipelines_1_first[194:192] == 3'd2 && - NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14553 && - NOT_fetchStage_pipelines_1_first__3001_BITS_32_ETC___d14540) + NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14563 && + NOT_fetchStage_pipelines_1_first__3001_BITS_32_ETC___d14550) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14475 && - regRenamingTable_rename_1_canRename__3780_AND__ETC___d14485 && + NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14485 && + regRenamingTable_rename_1_canRename__3790_AND__ETC___d14495 && fetchStage$pipelines_1_first[194:192] == 3'd2 && - NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14553 && + NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14563 && fetchStage$pipelines_1_first[173]) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14475 && - regRenamingTable_rename_1_canRename__3780_AND__ETC___d14485 && + NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14485 && + regRenamingTable_rename_1_canRename__3790_AND__ETC___d14495 && fetchStage$pipelines_1_first[194:192] == 3'd2 && - NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14553 && + NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14563 && (fetchStage$pipelines_1_first[199:195] != 5'd14) != fetchStage$pipelines_1_first[160]) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkCoreW.v b/src_SSITH_P3/Verilog_RTL_sim/mkCoreW.v index bb0d3be..ea0a6ee 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkCoreW.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkCoreW.v @@ -2716,22 +2716,22 @@ module mkCoreW(RST_N_dm_power_on_reset, // rule RL_rl_dm_hart0_reset_wait assign CAN_FIRE_RL_rl_dm_hart0_reset_wait = (rg_hart0_reset_delay != 8'd1 || - proc$RDY_start && - debug_module$RDY_hart0_reset_client_response_put) && + debug_module$RDY_hart0_reset_client_response_put && + proc$RDY_start) && rg_hart0_reset_delay != 8'd0 ; assign WILL_FIRE_RL_rl_dm_hart0_reset_wait = CAN_FIRE_RL_rl_dm_hart0_reset_wait && !EN_start ; // rule RL_ClientServerRequest assign CAN_FIRE_RL_ClientServerRequest = - proc$RDY_hart0_run_halt_server_request_put && - debug_module$RDY_hart0_client_run_halt_request_get ; + debug_module$RDY_hart0_client_run_halt_request_get && + proc$RDY_hart0_run_halt_server_request_put ; assign WILL_FIRE_RL_ClientServerRequest = CAN_FIRE_RL_ClientServerRequest ; // rule RL_ClientServerResponse assign CAN_FIRE_RL_ClientServerResponse = - proc$RDY_hart0_run_halt_server_response_get && - debug_module$RDY_hart0_client_run_halt_response_put ; + debug_module$RDY_hart0_client_run_halt_response_put && + proc$RDY_hart0_run_halt_server_response_get ; assign WILL_FIRE_RL_ClientServerResponse = CAN_FIRE_RL_ClientServerResponse ; @@ -2743,25 +2743,25 @@ module mkCoreW(RST_N_dm_power_on_reset, // rule RL_mkConnectionGetPut_1 assign CAN_FIRE_RL_mkConnectionGetPut_1 = - proc$RDY_v_to_TV_0_get && v_td2_to_td_0$RDY_in_put ; + v_td2_to_td_0$RDY_in_put && proc$RDY_v_to_TV_0_get ; assign WILL_FIRE_RL_mkConnectionGetPut_1 = CAN_FIRE_RL_mkConnectionGetPut_1 ; // rule RL_mkConnectionGetPut_2 assign CAN_FIRE_RL_mkConnectionGetPut_2 = - tv_encode$RDY_v_cpu_in_0_put && v_td2_to_td_0$RDY_out_get ; + v_td2_to_td_0$RDY_out_get && tv_encode$RDY_v_cpu_in_0_put ; assign WILL_FIRE_RL_mkConnectionGetPut_2 = CAN_FIRE_RL_mkConnectionGetPut_2 ; // rule RL_mkConnectionGetPut_3 assign CAN_FIRE_RL_mkConnectionGetPut_3 = - proc$RDY_v_to_TV_1_get && v_td2_to_td_1$RDY_in_put ; + v_td2_to_td_1$RDY_in_put && proc$RDY_v_to_TV_1_get ; assign WILL_FIRE_RL_mkConnectionGetPut_3 = CAN_FIRE_RL_mkConnectionGetPut_3 ; // rule RL_mkConnectionGetPut_4 assign CAN_FIRE_RL_mkConnectionGetPut_4 = - tv_encode$RDY_v_cpu_in_1_put && v_td2_to_td_1$RDY_out_get ; + v_td2_to_td_1$RDY_out_get && tv_encode$RDY_v_cpu_in_1_put ; assign WILL_FIRE_RL_mkConnectionGetPut_4 = CAN_FIRE_RL_mkConnectionGetPut_4 ; diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkP3_Core.v b/src_SSITH_P3/Verilog_RTL_sim/mkP3_Core.v index b1f7022..1b6b7c2 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkP3_Core.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkP3_Core.v @@ -1434,7 +1434,7 @@ module mkP3_Core(CLK, // rule RL_rl_ndm_reset_wait assign CAN_FIRE_RL_rl_ndm_reset_wait = (rg_ndm_reset_delay != 8'd1 || - corew$RDY_start && corew$RDY_ndm_reset_client_response_put) && + corew$RDY_ndm_reset_client_response_put && corew$RDY_start) && rg_ndm_reset_delay != 8'd0 ; assign WILL_FIRE_RL_rl_ndm_reset_wait = CAN_FIRE_RL_rl_ndm_reset_wait ; diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkProc.v b/src_SSITH_P3/Verilog_RTL_sim/mkProc.v index 73ce8a6..702ed9a 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkProc.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkProc.v @@ -2104,8 +2104,8 @@ module mkProc(CLK, // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h163598; - reg [31 : 0] v__h163134; + reg [31 : 0] v__h163582; + reg [31 : 0] v__h163118; reg [31 : 0] v__h5520; reg [31 : 0] v__h5693; reg [31 : 0] v__h5953; @@ -2116,13 +2116,13 @@ module mkProc(CLK, reg [31 : 0] v__h9480; reg [31 : 0] v__h9973; reg [31 : 0] v__h10136; - reg [31 : 0] v__h135091; - reg [31 : 0] v__h135258; - reg [31 : 0] v__h137361; - reg [31 : 0] v__h154705; - reg [31 : 0] v__h134472; - reg [31 : 0] v__h161399; - reg [31 : 0] v__h161907; + reg [31 : 0] v__h135075; + reg [31 : 0] v__h135242; + reg [31 : 0] v__h137345; + reg [31 : 0] v__h154689; + reg [31 : 0] v__h134456; + reg [31 : 0] v__h161383; + reg [31 : 0] v__h161891; reg [31 : 0] v__h2664; reg [31 : 0] v__h4337; reg [31 : 0] v__h5514; @@ -2133,282 +2133,280 @@ module mkProc(CLK, reg [31 : 0] v__h9474; reg [31 : 0] v__h9967; reg [31 : 0] v__h10130; - reg [31 : 0] v__h134466; - reg [31 : 0] v__h135085; - reg [31 : 0] v__h135252; - reg [31 : 0] v__h137355; - reg [31 : 0] v__h154699; - reg [31 : 0] v__h161393; - reg [31 : 0] v__h161901; - reg [31 : 0] v__h163128; - reg [31 : 0] v__h163592; + reg [31 : 0] v__h134450; + reg [31 : 0] v__h135069; + reg [31 : 0] v__h135236; + reg [31 : 0] v__h137339; + reg [31 : 0] v__h154683; + reg [31 : 0] v__h161377; + reg [31 : 0] v__h161885; + reg [31 : 0] v__h163112; + reg [31 : 0] v__h163576; // synopsys translate_on // remaining internal signals reg [63 : 0] CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13, CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14, CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17, - CASE_x0316_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24, - CASE_x0316_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25, - CASE_x0316_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26, - CASE_x0316_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27, - CASE_x0316_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28, - CASE_x0316_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29, - CASE_x0316_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30, - CASE_x0316_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31, - CASE_x0316_0_n__read_addr0494_1_n__read_addr05_ETC__q34, - CASE_x1509_0_n__read_addr1691_1_n__read_addr17_ETC__q23, - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d813, - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d826, - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d865, - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d877, - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d947, - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d956, - IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923, - IF_mmioPlatform_reqSz_83_EQ_0b10_90_THEN_SEXT__ETC___d891, - IF_mmioPlatform_reqSz_83_EQ_0b10_90_THEN_SEXT__ETC___d893, - data64__h148531, - dword__h94398, - ld_data__h132647, - old_dword__h90088, - w1__h48109, - w1__h48114, - w2__h48110, - w2__h48116, - x__h48105; - reg [31 : 0] SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d991; + CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24, + CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25, + CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26, + CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27, + CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28, + CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29, + CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30, + CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31, + CASE_x0300_0_n__read_addr0478_1_n__read_addr05_ETC__q34, + CASE_x1493_0_n__read_addr1675_1_n__read_addr17_ETC__q23, + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809, + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822, + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861, + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873, + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943, + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d952, + IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919, + IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d887, + IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d889, + data64__h148515, + dword__h94382, + ld_data__h132631, + old_dword__h90072, + w1__h48093, + w1__h48098, + w2__h48094, + w2__h48100, + x__h48089; + reg [31 : 0] SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d987; reg [11 : 0] CASE_core_0v_to_TV_0_get_BITS_475_TO_464_1_co_ETC__q5, CASE_core_0v_to_TV_1_get_BITS_475_TO_464_1_co_ETC__q1; - reg [7 : 0] strb8__h148532; - reg [5 : 0] IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_ETC___d481; + reg [7 : 0] strb8__h148516; + reg [5 : 0] IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d477; reg [3 : 0] CASE_core_0v_to_TV_0_get_BITS_461_TO_458_0_co_ETC__q6, CASE_core_0v_to_TV_0_get_BITS_461_TO_458_0_co_ETC__q7, CASE_core_0v_to_TV_1_get_BITS_461_TO_458_0_co_ETC__q2, CASE_core_0v_to_TV_1_get_BITS_461_TO_458_0_co_ETC__q3; - reg [2 : 0] x__h61823; + reg [2 : 0] x__h61807; reg [1 : 0] CASE_core_0v_to_TV_0_get_BITS_393_TO_392_0_co_ETC__q8, CASE_core_0v_to_TV_1_get_BITS_393_TO_392_0_co_ETC__q4, - CASE_x0316_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32, - CASE_x1509_0_IF_propDstData_0_dummy2_1_read__1_ETC__q21, - CASE_x1509_0_IF_propDstData_0_dummy2_1_read__1_ETC__q22; + CASE_x0300_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32, + CASE_x1493_0_IF_propDstData_0_dummy2_1_read__1_ETC__q21, + CASE_x1493_0_IF_propDstData_0_dummy2_1_read__1_ETC__q22; reg CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q18, CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q19, - CASE_x0316_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33, - CASE_x1509_0_propDstData_0_dummy2_1_read__104__ETC__q20, - SEL_ARR_propDstIdx_0_dummy2_1_read__066_AND_IF_ETC___d1097, - SEL_ARR_propDstIdx_1_0_dummy2_1_read__330_AND__ETC___d1371, - x__h61830, - x__h82732; - wire [579 : 0] IF_enqDst_1_0_lat_1_whas__275_THEN_enqDst_1_0__ETC___d1322; - wire [515 : 0] SEL_ARR_IF_propDstData_1_0_dummy2_1_read__378__ETC___d1470; - wire [513 : 0] IF_enqDst_1_0_lat_1_whas__275_THEN_enqDst_1_0__ETC___d1321; - wire [511 : 0] IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1313, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__202_THE_ETC___d1463, - new_cline__h135394; - wire [383 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1600, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__202_THE_ETC___d1446; - wire [255 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1595, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__202_THE_ETC___d1429; - wire [127 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__202_THE_ETC___d1412; - wire [66 : 0] IF_core_0_mmioToPlatform_cRq_first__82_BITS_14_ETC___d405; - wire [65 : 0] DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_40_BIT_ETC___d684; - wire [64 : 0] IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_2_ETC___d726; - wire [63 : 0] IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1293, - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d833, - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d884, - IF_mmioPlatform_reqBE_43_BIT_4_44_THEN_SEXT_mm_ETC___d577, - IF_mmioPlatform_reqBE_43_BIT_4_44_THEN_SEXT_mm_ETC___d641, - IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d552, - IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d614, - IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d718, - IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_1_ETC___d578, - IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_1_ETC___d642, - IF_propDstData_1_0_lat_0_whas__202_THEN_propDs_ETC___d1207, - IF_propDstData_1_1_lat_0_whas__240_THEN_propDs_ETC___d1245, - data__h31966, - failed_testnum__h163177, - line_addr__h102462, - line_addr__h102548, - mask__h90085, - mem_req_rd_addr_araddr__h134692, - mem_req_wr_addr_awaddr__h148616, - mmioPlatform_fromHostQ_data_0__h42761, - mmioPlatform_mtime__h37280, - mmioPlatform_reqData__h48701, - n__read_addr__h61691, - n__read_addr__h61776, - n__read_addr__h80494, - n__read_addr__h80573, - n__read_snd_addr__h123989, - newData__h32047, - newData__h34977, - new_dword__h90089, - op_result__h48717, - op_result__h49247, + CASE_x0300_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33, + CASE_x1493_0_propDstData_0_dummy2_1_read__100__ETC__q20, + SEL_ARR_propDstIdx_0_dummy2_1_read__062_AND_IF_ETC___d1093, + SEL_ARR_propDstIdx_1_0_dummy2_1_read__326_AND__ETC___d1367, + x__h61814, + x__h82716; + wire [579 : 0] IF_enqDst_1_0_lat_1_whas__271_THEN_enqDst_1_0__ETC___d1318; + wire [515 : 0] SEL_ARR_IF_propDstData_1_0_dummy2_1_read__374__ETC___d1466; + wire [513 : 0] IF_enqDst_1_0_lat_1_whas__271_THEN_enqDst_1_0__ETC___d1317; + wire [511 : 0] IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1309, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1459, + new_cline__h135378; + wire [383 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1596, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1442; + wire [255 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1591, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1425; + wire [127 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1408; + wire [66 : 0] IF_core_0_mmioToPlatform_cRq_first__78_BITS_14_ETC___d401; + wire [65 : 0] DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_36_BIT_ETC___d680; + wire [64 : 0] IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_2_ETC___d722; + wire [63 : 0] IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1289, + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829, + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d880, + IF_mmioPlatform_reqBE_39_BIT_4_40_THEN_SEXT_mm_ETC___d573, + IF_mmioPlatform_reqBE_39_BIT_4_40_THEN_SEXT_mm_ETC___d637, + IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d548, + IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d610, + IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d714, + IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_1_ETC___d574, + IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_1_ETC___d638, + IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1203, + IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1241, + data__h31950, + failed_testnum__h163161, + line_addr__h102446, + line_addr__h102532, + mask__h90069, + mem_req_rd_addr_araddr__h134676, + mem_req_wr_addr_awaddr__h148600, + mmioPlatform_fromHostQ_data_0__h42745, + mmioPlatform_mtime__h37264, + mmioPlatform_reqData__h48685, + n__read_addr__h61675, + n__read_addr__h61760, + n__read_addr__h80478, + n__read_addr__h80557, + n__read_snd_addr__h123973, + newData__h32031, + newData__h34961, + new_dword__h90073, + op_result__h48701, + op_result__h49231, + op_result__h49236, + op_result__h49241, + op_result__h49246, op_result__h49252, - op_result__h49257, - op_result__h49262, - op_result__h49268, - op_result__h49275, - op_result__h49281, - result__h48160, - result__h48284, - result__h48312, - result__h48340, - result__h48368, - result__h48396, - result__h48424, - result__h48452, - result__h48480, - result__h48525, - result__h48553, - result__h48581, - result__h48609, - result__h48650, - result__h48678, - result__h48804, - result__h48831, - result__h48858, - result__h48885, - result__h48912, - result__h48939, - result__h48966, - result__h48993, - result__h49037, - result__h49064, - result__h49091, - result__h49118, - result__h49158, - result__h49185, - result__h49302, - result__h49368, - result__h49434, - result__h49500, - result__h49566, - result__h49632, - result__h49698, - result__h49760, - result__h49805, - result__h49871, - result__h49937, - result__h49995, - result__h50040, - w1___1__h48219, - w2___1__h48220, - x1_avValue_data__h40433, - x1_avValue_data__h45038, - x__h32158, - x__h35068, - x__h37428, - x__h40951, - x__h40962, - x__h43017, - x__h43028, - x__h50217, - x__h91251, - y__h91252, - y__h91253; - wire [47 : 0] IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d544, - IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d609, - IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d713; - wire [31 : 0] IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d535, - IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d604, - IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d708, - IF_mmio_axi4_adapter_f_rsps_to_core_first__64__ETC___d999, + op_result__h49259, + op_result__h49265, + result__h48144, + result__h48268, + result__h48296, + result__h48324, + result__h48352, + result__h48380, + result__h48408, + result__h48436, + result__h48464, + result__h48509, + result__h48537, + result__h48565, + result__h48593, + result__h48634, + result__h48662, + result__h48788, + result__h48815, + result__h48842, + result__h48869, + result__h48896, + result__h48923, + result__h48950, + result__h48977, + result__h49021, + result__h49048, + result__h49075, + result__h49102, + result__h49142, + result__h49169, + result__h49286, + result__h49352, + result__h49418, + result__h49484, + result__h49550, + result__h49616, + result__h49682, + result__h49744, + result__h49789, + result__h49855, + result__h49921, + result__h49979, + result__h50024, + w1___1__h48203, + w2___1__h48204, + x1_avValue_data__h40417, + x1_avValue_data__h45022, + x__h32142, + x__h35052, + x__h37412, + x__h40935, + x__h40946, + x__h43001, + x__h43012, + x__h50201, + x__h91235, + y__h91236, + y__h91237; + wire [47 : 0] IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d540, + IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d605, + IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d709; + wire [31 : 0] IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d531, + IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d600, + IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d704, + IF_mmio_axi4_adapter_f_rsps_to_core_first__60__ETC___d995, mmioPlatform_mtime_BITS_31_TO_0__q12, mmioPlatform_mtime_BITS_63_TO_32__q11, mmioPlatform_mtimecmp_0_BITS_31_TO_0__q10, mmioPlatform_mtimecmp_0_BITS_63_TO_32__q9, - v__h31759, - v__h31796, - w18109_BITS_31_TO_0__q15, - w28110_BITS_31_TO_0__q16, - x_data__h30549; - wire [8 : 0] SEL_ARR_IF_propDstData_0_dummy2_1_read__104_TH_ETC___d1168; - wire [5 : 0] x__h134727, x__h148641; - wire [4 : 0] SEL_ARR_propDstData_0_dummy2_1_read__104_AND_I_ETC___d1167; - wire [3 : 0] b__h134399, b__h2564; - wire [2 : 0] n__read_id__h61695, n__read_id__h61780, x__h7925; - wire [1 : 0] IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1298, - IF_propDstData_0_dummy2_1_read__104_THEN_IF_pr_ETC___d1120, - IF_propDstData_0_dummy2_1_read__104_THEN_IF_pr_ETC___d1130, - IF_propDstData_1_0_lat_0_whas__202_THEN_propDs_ETC___d1212, - IF_propDstData_1_1_lat_0_whas__240_THEN_propDs_ETC___d1250, - IF_propDstData_1_dummy2_1_read__109_THEN_IF_pr_ETC___d1124, - IF_propDstData_1_dummy2_1_read__109_THEN_IF_pr_ETC___d1134; - wire IF_IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4__ETC___d559, - IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d456, - IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554, - IF_NOT_propDstIdx_0_dummy2_1_read__066_067_OR__ETC___d1101, - IF_NOT_propDstIdx_1_0_dummy2_1_read__330_331_O_ETC___d1375, - IF_SEL_ARR_propDstIdx_0_dummy2_1_read__066_AND_ETC___d1173, - IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__330_A_ETC___d1475, - IF_enqDst_0_lat_0_whas__042_THEN_enqDst_0_lat__ETC___d1047, - IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1283, - IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1303, - IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1319, - IF_llc_mem_server_enqDst_0_lat_0_whas__680_THE_ETC___d1685, - IF_llc_mem_server_propDstIdx_0_lat_0_whas__665_ETC___d1668, - IF_mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioP_ETC___d625, - IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_ETC___d457, + v__h31743, + v__h31780, + w18093_BITS_31_TO_0__q15, + w28094_BITS_31_TO_0__q16, + x_data__h30533; + wire [8 : 0] SEL_ARR_IF_propDstData_0_dummy2_1_read__100_TH_ETC___d1164; + wire [5 : 0] x__h134711, x__h148625; + wire [4 : 0] SEL_ARR_propDstData_0_dummy2_1_read__100_AND_I_ETC___d1163; + wire [3 : 0] b__h134383, b__h2564; + wire [2 : 0] n__read_id__h61679, n__read_id__h61764, x__h7925; + wire [1 : 0] IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1294, + IF_propDstData_0_dummy2_1_read__100_THEN_IF_pr_ETC___d1116, + IF_propDstData_0_dummy2_1_read__100_THEN_IF_pr_ETC___d1126, + IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1208, + IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1246, + IF_propDstData_1_dummy2_1_read__105_THEN_IF_pr_ETC___d1120, + IF_propDstData_1_dummy2_1_read__105_THEN_IF_pr_ETC___d1130; + wire IF_IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4__ETC___d555, + IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d452, + IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550, + IF_NOT_propDstIdx_0_dummy2_1_read__062_063_OR__ETC___d1097, + IF_NOT_propDstIdx_1_0_dummy2_1_read__326_327_O_ETC___d1371, + IF_SEL_ARR_propDstIdx_0_dummy2_1_read__062_AND_ETC___d1169, + IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__326_A_ETC___d1471, + IF_enqDst_0_lat_0_whas__038_THEN_enqDst_0_lat__ETC___d1043, + IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1279, + IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1299, + IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1315, + IF_llc_mem_server_enqDst_0_lat_0_whas__676_THE_ETC___d1681, + IF_llc_mem_server_propDstIdx_0_lat_0_whas__661_ETC___d1664, + IF_mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioP_ETC___d621, + IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d453, IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__91__ETC___d200, - IF_mmioPlatform_waitLowerMSIPCRs_92_THEN_core__ETC___d500, - IF_mmio_axi4_adapter_f_rsps_to_core_first__64__ETC___d978, + IF_mmioPlatform_waitLowerMSIPCRs_88_THEN_core__ETC___d496, + IF_mmio_axi4_adapter_f_rsps_to_core_first__60__ETC___d974, IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d103, - IF_propDstData_1_0_lat_0_whas__202_THEN_propDs_ETC___d1233, - IF_propDstData_1_1_lat_0_whas__240_THEN_propDs_ETC___d1271, - IF_propDstIdx_0_lat_0_whas__013_THEN_propDstId_ETC___d1016, - IF_propDstIdx_1_0_lat_0_whas__187_THEN_propDst_ETC___d1190, - IF_propDstIdx_1_1_lat_0_whas__194_THEN_propDst_ETC___d1197, - IF_propDstIdx_1_lat_0_whas__020_THEN_propDstId_ETC___d1023, - NOT_enqDst_0_dummy2_0_read__087_088_OR_NOT_enq_ETC___d1103, - NOT_enqDst_1_0_dummy2_0_read__361_362_OR_NOT_e_ETC___d1377, - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801, - NOT_llc_mem_server_enqDst_0_dummy2_0_read__711_ETC___d1718, - NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d754, - NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d762, - NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d767, - NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d777, - NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d968, - NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d981, + IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1229, + IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1267, + IF_propDstIdx_0_lat_0_whas__009_THEN_propDstId_ETC___d1012, + IF_propDstIdx_1_0_lat_0_whas__183_THEN_propDst_ETC___d1186, + IF_propDstIdx_1_1_lat_0_whas__190_THEN_propDst_ETC___d1193, + IF_propDstIdx_1_lat_0_whas__016_THEN_propDstId_ETC___d1019, + NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099, + NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373, + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797, + NOT_llc_mem_server_enqDst_0_dummy2_0_read__707_ETC___d1714, + NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d750, + NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d758, + NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d763, + NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d773, + NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d964, + NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d977, NOT_mmioPlatform_fromHostQ_clearReq_dummy2_1_r_ETC___d318, NOT_mmioPlatform_fromHostQ_enqReq_dummy2_2_rea_ETC___d339, - NOT_mmioPlatform_mtip_0_55_64_AND_mmioPlatform_ETC___d374, - NOT_mmioPlatform_mtip_0_55_64_AND_mmioPlatform_ETC___d379, - NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d490, - NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d585, - NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d648, + NOT_mmioPlatform_mtip_0_55_62_AND_mmioPlatform_ETC___d370, + NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d486, + NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d581, + NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d644, NOT_mmioPlatform_toHostQ_clearReq_dummy2_1_rea_ETC___d240, NOT_mmioPlatform_toHostQ_enqReq_dummy2_2_read__ETC___d261, - NOT_propDstData_1_0_dummy2_1_read__378_389_OR__ETC___d1390, - NOT_propDstData_1_1_dummy2_1_read__380_391_OR__ETC___d1392, - NOT_propDstIdx_0_dummy2_1_read__066_067_OR_IF__ETC___d1100, - NOT_propDstIdx_1_0_dummy2_1_read__330_331_OR_I_ETC___d1374, - llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1612, - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1534, + NOT_propDstData_1_0_dummy2_1_read__374_385_OR__ETC___d1386, + NOT_propDstData_1_1_dummy2_1_read__376_387_OR__ETC___d1388, + NOT_propDstIdx_0_dummy2_1_read__062_063_OR_IF__ETC___d1096, + NOT_propDstIdx_1_0_dummy2_1_read__326_327_OR_I_ETC___d1370, + llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1608, + llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1530, mmioPlatform_cycle_47_ULT_99___d348, - mmioPlatform_fetchingWay_73_ULT_mmioPlatform_r_ETC___d983, + mmioPlatform_fetchingWay_69_ULT_mmioPlatform_r_ETC___d979, mmioPlatform_fromHostQ_enqReq_dummy2_2_read__1_ETC___d331, - mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616, + mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612, mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357, - mmioPlatform_mtip_0_55_OR_NOT_mmioPlatform_mti_ETC___d410, - mmioPlatform_reqBE_BIT_0___h30174, - mmioPlatform_reqBE_BIT_4___h30134, - mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d467, - mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d571, - mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d636, + mmioPlatform_reqBE_BIT_0___h30158, + mmioPlatform_reqBE_BIT_4___h30118, + mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d463, + mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d567, + mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d632, mmioPlatform_toHostQ_enqReq_dummy2_2_read__41__ETC___d253, mmio_axi4_adapter_f_reqs_from_core_i_notEmpty__ETC___d9, - n__read_child__h61696, - n__read_child__h61781, - n__read_child__h80497, - n__read_child__h80576, - n__read_snd_id__h123990, - propDstData_0_dummy2_1_read__104_AND_IF_propDs_ETC___d1140, - propDstData_1_dummy2_1_read__109_AND_IF_propDs_ETC___d1144, - x__h61509, - x__h75245, - x__h80316; + n__read_child__h61680, + n__read_child__h61765, + n__read_child__h80481, + n__read_child__h80560, + n__read_snd_id__h123974, + propDstData_0_dummy2_1_read__100_AND_IF_propDs_ETC___d1136, + propDstData_1_dummy2_1_read__105_AND_IF_propDs_ETC___d1140, + x__h61493, + x__h75229, + x__h80300; // action method start assign RDY_start = mmioPlatform_state == 2'd0 ; @@ -3536,7 +3534,7 @@ module mkProc(CLK, // rule RL_doEnq assign CAN_FIRE_RL_doEnq = llc$RDY_to_child_rqFromC_enq && enqDst_0_dummy2_1$Q_OUT && - IF_enqDst_0_lat_0_whas__042_THEN_enqDst_0_lat__ETC___d1047 ; + IF_enqDst_0_lat_0_whas__038_THEN_enqDst_0_lat__ETC___d1043 ; assign WILL_FIRE_RL_doEnq = CAN_FIRE_RL_doEnq ; // rule RL_srcPropose_2 @@ -3564,7 +3562,7 @@ module mkProc(CLK, // rule RL_doEnq_1 assign CAN_FIRE_RL_doEnq_1 = llc$RDY_to_child_rsFromC_enq && enqDst_1_0_dummy2_1$Q_OUT && - IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1283 ; + IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1279 ; assign WILL_FIRE_RL_doEnq_1 = CAN_FIRE_RL_doEnq_1 ; // rule RL_sendPRq @@ -3725,9 +3723,8 @@ module mkProc(CLK, assign CAN_FIRE_RL_mmioPlatform_selectReq = (mmioPlatform_mtip_0 || !mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 || - mmioPlatform_mtimecmp_0 == 64'd0 || core_0$RDY_mmioToPlatform_pRq_enq) && - NOT_mmioPlatform_mtip_0_55_64_AND_mmioPlatform_ETC___d374 && + NOT_mmioPlatform_mtip_0_55_62_AND_mmioPlatform_ETC___d370 && mmioPlatform_state == 2'd1 ; assign WILL_FIRE_RL_mmioPlatform_selectReq = CAN_FIRE_RL_mmioPlatform_selectReq && @@ -3744,7 +3741,7 @@ module mkProc(CLK, // rule RL_mmioPlatform_processMSIP assign CAN_FIRE_RL_mmioPlatform_processMSIP = - IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_ETC___d457 && + IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d453 && mmioPlatform_curReq[66:64] == 3'd2 && mmioPlatform_state == 2'd2 ; assign WILL_FIRE_RL_mmioPlatform_processMSIP = @@ -3753,7 +3750,7 @@ module mkProc(CLK, // rule RL_mmioPlatform_waitMSIPDone assign CAN_FIRE_RL_mmioPlatform_waitMSIPDone = core_0$RDY_mmioToPlatform_pRs_enq && - IF_mmioPlatform_waitLowerMSIPCRs_92_THEN_core__ETC___d500 && + IF_mmioPlatform_waitLowerMSIPCRs_88_THEN_core__ETC___d496 && mmioPlatform_curReq[66:64] == 3'd2 && mmioPlatform_state == 2'd3 ; assign WILL_FIRE_RL_mmioPlatform_waitMSIPDone = @@ -3799,7 +3796,7 @@ module mkProc(CLK, core_0$RDY_mmioToPlatform_pRs_enq && (mmioPlatform_reqFunc[5:4] != 2'd2 || !mmioPlatform_toHostQ_empty || - x__h43017 == 64'd0 || + x__h43001 == 64'd0 || !mmioPlatform_toHostQ_full) && mmioPlatform_state == 2'd2 && mmioPlatform_curReq[66:64] == 3'd5 ; @@ -3817,7 +3814,7 @@ module mkProc(CLK, // rule RL_mmioPlatform_rl_mmio_to_fabric_req assign CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req = mmio_axi4_adapter_f_reqs_from_core$FULL_N && - NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d754 ; + NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d750 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req = CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req ; @@ -3825,14 +3822,14 @@ module mkProc(CLK, assign CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp = core_0$RDY_mmioToPlatform_pRs_enq && mmio_axi4_adapter_f_rsps_to_core$EMPTY_N && - NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d762 ; + NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d758 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp = CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp ; // rule RL_mmioPlatform_rl_mmio_to_fabric_amo_req assign CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req = mmio_axi4_adapter_f_reqs_from_core$FULL_N && - NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d767 ; + NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d763 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req = CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req ; @@ -3842,22 +3839,22 @@ module mkProc(CLK, mmio_axi4_adapter_f_rsps_to_core$EMPTY_N && (!mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] || mmio_axi4_adapter_f_reqs_from_core$FULL_N) && - NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d777 ; + NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d773 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp = CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp ; // rule RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req assign CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req = mmio_axi4_adapter_f_reqs_from_core$FULL_N && - NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d968 ; + NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d964 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req = CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req ; // rule RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp assign CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp = mmio_axi4_adapter_f_rsps_to_core$EMPTY_N && - IF_mmio_axi4_adapter_f_rsps_to_core_first__64__ETC___d978 && - NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d981 ; + IF_mmio_axi4_adapter_f_rsps_to_core_first__60__ETC___d974 && + NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d977 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp = CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp ; @@ -3939,7 +3936,7 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_f_rd_data$FULL_N && (llc_mem_server_rg_cacheline_cache_state == 3'd3 || llc_mem_server_rg_cacheline_cache_state == 3'd4) && - llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1612 ; + llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1608 ; assign WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req = CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req ; @@ -3957,7 +3954,7 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_f_wr_resp$FULL_N && (llc_mem_server_rg_cacheline_cache_state == 3'd3 || llc_mem_server_rg_cacheline_cache_state == 3'd4) && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1534 ; + llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1530 ; assign WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req = CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ; @@ -3975,7 +3972,7 @@ module mkProc(CLK, llc$RDY_dma_memReq_enq && llc_mem_server_axi4_slave_xactor_f_wr_addr$EMPTY_N && llc_mem_server_rg_cacheline_cache_state == 3'd4 && - !llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1534 ; + !llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1530 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss && !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged ; @@ -3985,7 +3982,7 @@ module mkProc(CLK, llc$RDY_dma_memReq_enq && llc_mem_server_axi4_slave_xactor_f_rd_addr$EMPTY_N && llc_mem_server_rg_cacheline_cache_state == 3'd4 && - !llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1612 ; + !llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1608 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss && !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss && @@ -4005,7 +4002,7 @@ module mkProc(CLK, llc$RDY_dma_memReq_enq && llc_mem_server_axi4_slave_xactor_f_wr_addr$EMPTY_N && llc_mem_server_rg_cacheline_cache_state == 3'd3 && - !llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1534 ; + !llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1530 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ; @@ -4014,7 +4011,7 @@ module mkProc(CLK, llc$RDY_dma_memReq_enq && llc_mem_server_axi4_slave_xactor_f_rd_addr$EMPTY_N && llc_mem_server_rg_cacheline_cache_state == 3'd3 && - !llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1612 ; + !llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1608 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld && !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st && @@ -4046,7 +4043,7 @@ module mkProc(CLK, assign CAN_FIRE_RL_llc_mem_server_doEnq = llc_mem_server_tlbQ$FULL_N && llc_mem_server_enqDst_0_dummy2_1$Q_OUT && - IF_llc_mem_server_enqDst_0_lat_0_whas__680_THE_ETC___d1685 ; + IF_llc_mem_server_enqDst_0_lat_0_whas__676_THE_ETC___d1681 ; assign WILL_FIRE_RL_llc_mem_server_doEnq = CAN_FIRE_RL_llc_mem_server_doEnq ; @@ -4119,13 +4116,13 @@ module mkProc(CLK, (llc_axi4_adapter_rg_rd_req_beat != 3'd7 || llc$RDY_to_mem_toM_deq) && !llc$to_mem_toM_first[640] && - b__h134399 == 4'd0 ; + b__h134383 == 4'd0 ; assign WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ; // rule RL_llc_axi4_adapter_rl_discard_write_rsp assign CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp = - b__h134399 != 4'd0 && + b__h134383 != 4'd0 && llc_axi4_adapter_master_xactor_crg_wr_resp_full && (llc_axi4_adapter_rg_wr_rsp_beat != 3'd7 || llc_axi4_adapter_f_pending_writes$EMPTY_N) ; @@ -4135,8 +4132,7 @@ module mkProc(CLK, // inputs to muxes for submodule ports assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 && - mmioPlatform_mtimecmp_0 != 64'd0 ; + mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_2 = WILL_FIRE_RL_mmioPlatform_processMSIP && mmioPlatform_reqFunc[5:4] != 2'd0 && @@ -4144,22 +4140,22 @@ module mkProc(CLK, mmioPlatform_reqBE[0] ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_3 = WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d585 ; + NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d581 ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_4 = WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d648 ; + NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d644 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_processMSIP && - mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d467 ; + mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d463 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_2 = WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d571 ; + mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d567 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_3 = WILL_FIRE_RL_mmioPlatform_processMTime && - mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d636 ; + mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d632 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_4 = WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && - (!mmioPlatform_fetchingWay_73_ULT_mmioPlatform_r_ETC___d983 || + (!mmioPlatform_fetchingWay_69_ULT_mmioPlatform_r_ETC___d979 || !mmio_axi4_adapter_f_rsps_to_core$D_OUT[64]) ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_5 = WILL_FIRE_RL_mmioPlatform_waitMTimeDone || @@ -4184,10 +4180,14 @@ module mkProc(CLK, mmioPlatform_reqFunc[5:4] != 2'd1 ; assign MUX_mmioPlatform_curReq$write_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_selectReq && - NOT_mmioPlatform_mtip_0_55_64_AND_mmioPlatform_ETC___d379 ; + (!mmioPlatform_mtip_0 && + mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 || + core_0$mmioToPlatform_cRq_notEmpty) ; assign MUX_mmioPlatform_fetchingWay$write_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_55_OR_NOT_mmioPlatform_mti_ETC___d410 ; + (mmioPlatform_mtip_0 || + !mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357) && + core_0$mmioToPlatform_cRq_notEmpty ; assign MUX_mmioPlatform_state$write_1__SEL_6 = WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp || @@ -4222,20 +4222,20 @@ module mkProc(CLK, llc$to_child_toC_first[515:0] } ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_2 = { 1'd0, - IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_ETC___d481, + IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d477, (mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? mmioPlatform_reqData[31:0] : - x_data__h30549 } ; + x_data__h30533 } ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_3 = { 7'd106, - (IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 && + (IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && !mmioPlatform_mtip_0) ? 32'd1 : 32'd0 } ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_4 = { 7'd106, - (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && + (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && !mmioPlatform_mtip_0) ? 32'd1 : 32'd0 } ; @@ -4249,35 +4249,35 @@ module mkProc(CLK, (mmioPlatform_reqFunc[5:4] == 2'd0) ? 66'h155555554AAAAAAAA : { 2'h1, - IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_1_ETC___d578 } } ; + IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_1_ETC___d574 } } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_3 = { mmioPlatform_reqFunc[5:4] != 2'd0, (mmioPlatform_reqFunc[5:4] == 2'd0) ? 66'h155555554AAAAAAAA : { 2'h1, - IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_1_ETC___d642 } } ; + IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_1_ETC___d638 } } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_4 = { 1'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] && mmioPlatform_fetchingWay, - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d991, + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d987, mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] || mmioPlatform_fetchingWay, - IF_mmio_axi4_adapter_f_rsps_to_core_first__64__ETC___d999 } ; + IF_mmio_axi4_adapter_f_rsps_to_core_first__60__ETC___d995 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_5 = { 3'd5, mmioPlatform_amoResp } ; - assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6 = { 3'd5, data__h31966 } ; + assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6 = { 3'd5, data__h31950 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_7 = { mmioPlatform_reqFunc[5:4] != 2'd0, (mmioPlatform_reqFunc[5:4] == 2'd0) ? 66'h155555554AAAAAAAA : - DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_40_BIT_ETC___d684 } ; + DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_36_BIT_ETC___d680 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_8 = { mmioPlatform_reqFunc[5:4] != 2'd0, (mmioPlatform_reqFunc[5:4] == 2'd0) ? 66'h155555554AAAAAAAA : { 1'h0, - IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_2_ETC___d726 } } ; + IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_2_ETC___d722 } } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_9 = { 2'd2, mmio_axi4_adapter_f_rsps_to_core$D_OUT } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_10 = @@ -4291,10 +4291,10 @@ module mkProc(CLK, llc_mem_server_rg_cacheline_cache_data, 5'd10 } ; assign MUX_llc$dma_memReq_enq_1__VAL_2 = - { line_addr__h102462, + { line_addr__h102446, 581'h0000000000000000155555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555554A } ; assign MUX_llc$dma_memReq_enq_1__VAL_3 = - { line_addr__h102548, + { line_addr__h102532, 581'h0000000000000000155555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555554A } ; assign MUX_llc$dma_memReq_enq_1__VAL_4 = { llc_mem_server_tlbQ$D_OUT[64:1], @@ -4302,29 +4302,28 @@ module mkProc(CLK, llc_mem_server_tlbQ$D_OUT[0], llc_mem_server_tlbQ$D_OUT[6:4] } ; assign MUX_llc_mem_server_rg_cacheline_cache_data$write_1__VAL_1 = - { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1600, + { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1596, (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd1) ? - new_dword__h90089 : + new_dword__h90073 : llc_mem_server_rg_cacheline_cache_data[127:64], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd0) ? - new_dword__h90089 : + new_dword__h90073 : llc_mem_server_rg_cacheline_cache_data[63:0] } ; assign MUX_llc_mem_server_rg_cacheline_cache_dirty_delay$write_1__VAL_2 = llc_mem_server_rg_cacheline_cache_dirty_delay - 10'd1 ; assign MUX_mmioPlatform_amoResp$write_1__VAL_1 = (mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtimecmp_0 : - IF_mmioPlatform_reqBE_43_BIT_4_44_THEN_SEXT_mm_ETC___d577 ; + IF_mmioPlatform_reqBE_39_BIT_4_40_THEN_SEXT_mm_ETC___d573 ; assign MUX_mmioPlatform_amoResp$write_1__VAL_2 = (mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtime : - IF_mmioPlatform_reqBE_43_BIT_4_44_THEN_SEXT_mm_ETC___d641 ; + IF_mmioPlatform_reqBE_39_BIT_4_40_THEN_SEXT_mm_ETC___d637 ; assign MUX_mmioPlatform_curReq$write_1__VAL_1 = (!mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 && - mmioPlatform_mtimecmp_0 != 64'd0) ? + mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357) ? 67'h1AAAAAAAAAAAAAAAA : ((core_0$mmioToPlatform_cRq_first[141:81] >= 61'd33554432 && core_0$mmioToPlatform_cRq_first[141:81] < 61'd33554433) ? @@ -4335,7 +4334,7 @@ module mkProc(CLK, ((core_0$mmioToPlatform_cRq_first[141:81] == 61'd33560575) ? 67'h4AAAAAAAAAAAAAAAA : - IF_core_0_mmioToPlatform_cRq_first__82_BITS_14_ETC___d405))) ; + IF_core_0_mmioToPlatform_cRq_first__78_BITS_14_ETC___d401))) ; assign MUX_mmioPlatform_curReq$write_1__VAL_2 = { 3'd7, mmioPlatform_instSel ? @@ -4348,12 +4347,11 @@ module mkProc(CLK, mmioPlatform_instSel + 1'd1 ; assign MUX_mmioPlatform_mtime$write_1__VAL_2 = mmioPlatform_mtime + 64'd1 ; assign MUX_mmioPlatform_mtip_0$write_1__VAL_2 = - IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 && + IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && !mmioPlatform_mtip_0 ; assign MUX_mmioPlatform_state$write_1__VAL_1 = (!mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 && - mmioPlatform_mtimecmp_0 != 64'd0) ? + mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357) ? 2'd3 : 2'd2 ; assign MUX_mmioPlatform_state$write_1__VAL_2 = @@ -4364,32 +4362,32 @@ module mkProc(CLK, (mmioPlatform_reqBE[0] ? 2'd3 : 2'd1) : 2'd3) ; always@(mmioPlatform_reqFunc or - IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 or + IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 or mmioPlatform_mtip_0) begin case (mmioPlatform_reqFunc[5:4]) 2'd0: MUX_mmioPlatform_state$write_1__VAL_3 = 2'd1; 2'd1: MUX_mmioPlatform_state$write_1__VAL_3 = mmioPlatform_reqFunc[5:4]; default: MUX_mmioPlatform_state$write_1__VAL_3 = - (IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 && + (IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && !mmioPlatform_mtip_0 || - !IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 && + !IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && mmioPlatform_mtip_0) ? 2'd3 : 2'd1; endcase end always@(mmioPlatform_reqFunc or - mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 or + mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 or mmioPlatform_mtip_0) begin case (mmioPlatform_reqFunc[5:4]) 2'd0: MUX_mmioPlatform_state$write_1__VAL_4 = 2'd1; 2'd1: MUX_mmioPlatform_state$write_1__VAL_4 = mmioPlatform_reqFunc[5:4]; default: MUX_mmioPlatform_state$write_1__VAL_4 = - (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && + (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && + !mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && mmioPlatform_mtip_0) ? 2'd3 : 2'd1; @@ -4397,29 +4395,29 @@ module mkProc(CLK, end assign MUX_mmioPlatform_state$write_1__VAL_5 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] ? - (mmioPlatform_fetchingWay_73_ULT_mmioPlatform_r_ETC___d983 ? + (mmioPlatform_fetchingWay_69_ULT_mmioPlatform_r_ETC___d979 ? 2'd2 : 2'd1) : 2'd1 ; assign MUX_mmioPlatform_waitMTIPCRs$write_1__VAL_2 = - mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && + mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && + !mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && mmioPlatform_mtip_0 ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_1 = { mmioPlatform_curReq[63:0], 6'd42, mmioPlatform_reqBE, - x__h48105 } ; + x__h48089 } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_2 = { mmioPlatform_curReq[63:0], - IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_ETC___d481, + IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d477, mmioPlatform_reqBE, mmioPlatform_reqData } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_3 = { mmioPlatform_curReq[63:0], 78'h1AAAAAAAAAAAAAAAAAAA } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_4 = - { x__h50217, 78'h1AAAAAAAAAAAAAAAAAAA } ; + { x__h50201, 78'h1AAAAAAAAAAAAAAAAAAA } ; assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_1 = { 1'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[141:78] } ; assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_3 = @@ -4427,47 +4425,47 @@ module mkProc(CLK, mmio_axi4_adapter_master_xactor_rg_rd_data[66:3] } ; // inlined wires - assign mmioPlatform_toHostQ_enqReq_lat_0$wget = { 1'd1, x__h43017 } ; + assign mmioPlatform_toHostQ_enqReq_lat_0$wget = { 1'd1, x__h43001 } ; assign mmioPlatform_toHostQ_enqReq_lat_0$whas = WILL_FIRE_RL_mmioPlatform_processToHost && mmioPlatform_reqFunc[5:4] == 2'd2 && mmioPlatform_toHostQ_empty && - x__h43017 != 64'd0 ; + x__h43001 != 64'd0 ; assign mmioPlatform_fromHostQ_deqReq_lat_0$whas = WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && !mmioPlatform_fromHostQ_empty && - x__h40951 == 64'd0 ; + x__h40935 == 64'd0 ; assign propDstIdx_0_lat_1$whas = - NOT_enqDst_0_dummy2_0_read__087_088_OR_NOT_enq_ETC___d1103 && - IF_SEL_ARR_propDstIdx_0_dummy2_1_read__066_AND_ETC___d1173 ; + NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 && + IF_SEL_ARR_propDstIdx_0_dummy2_1_read__062_AND_ETC___d1169 ; assign propDstIdx_1_lat_1$whas = - NOT_enqDst_0_dummy2_0_read__087_088_OR_NOT_enq_ETC___d1103 && - x__h61509 ; + NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 && + x__h61493 ; assign propDstData_0_lat_0$wget = { core_0$dCacheToParent_rqToP_first, 1'd0 } ; assign propDstData_1_lat_0$wget = { core_0$iCacheToParent_rqToP_first, 1'd1 } ; assign enqDst_0_lat_0$wget = { 1'd1, - CASE_x1509_0_n__read_addr1691_1_n__read_addr17_ETC__q23, - SEL_ARR_IF_propDstData_0_dummy2_1_read__104_TH_ETC___d1168 } ; + CASE_x1493_0_n__read_addr1675_1_n__read_addr17_ETC__q23, + SEL_ARR_IF_propDstData_0_dummy2_1_read__100_TH_ETC___d1164 } ; assign propDstIdx_1_0_lat_1$whas = - NOT_enqDst_1_0_dummy2_0_read__361_362_OR_NOT_e_ETC___d1377 && - IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__330_A_ETC___d1475 ; + NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 && + IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__326_A_ETC___d1471 ; assign propDstIdx_1_1_lat_1$whas = - NOT_enqDst_1_0_dummy2_0_read__361_362_OR_NOT_e_ETC___d1377 && - x__h80316 ; + NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 && + x__h80300 ; assign propDstData_1_0_lat_0$wget = { core_0$dCacheToParent_rsToP_first, 1'd0 } ; assign propDstData_1_1_lat_0$wget = { core_0$iCacheToParent_rsToP_first, 1'd1 } ; assign enqDst_1_0_lat_0$wget = { 1'd1, - CASE_x0316_0_n__read_addr0494_1_n__read_addr05_ETC__q34, - SEL_ARR_IF_propDstData_1_0_dummy2_1_read__378__ETC___d1470 } ; + CASE_x0300_0_n__read_addr0478_1_n__read_addr05_ETC__q34, + SEL_ARR_IF_propDstData_1_0_dummy2_1_read__374__ETC___d1466 } ; assign llc_mem_server_enqDst_0_lat_0$wget = - { 1'd1, n__read_snd_addr__h123989, n__read_snd_id__h123990 } ; + { 1'd1, n__read_snd_addr__h123973, n__read_snd_id__h123974 } ; assign mmio_axi4_adapter_master_xactor_crg_wr_addr_full$EN_port1__write = mmio_axi4_adapter_master_xactor_crg_wr_addr_full && master1_awready ; @@ -4581,11 +4579,11 @@ module mkProc(CLK, assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 = llc_axi4_adapter_ctr_wr_rsps_pending_crg + 4'd1 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 = - b__h134399 - 4'd1 ; + b__h134383 - 4'd1 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read = CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp ? llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 : - b__h134399 ; + b__h134383 ; // register cfg_verbosity assign cfg_verbosity$D_IN = @@ -4597,10 +4595,10 @@ module mkProc(CLK, // register enqDst_0_rl assign enqDst_0_rl$D_IN = { !CAN_FIRE_RL_doEnq && - IF_enqDst_0_lat_0_whas__042_THEN_enqDst_0_lat__ETC___d1047, + IF_enqDst_0_lat_0_whas__038_THEN_enqDst_0_lat__ETC___d1043, CAN_FIRE_RL_doEnq ? 73'h0AAAAAAAAAAAAAAAAAA : - (NOT_enqDst_0_dummy2_0_read__087_088_OR_NOT_enq_ETC___d1103 ? + (NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 ? enqDst_0_lat_0$wget[72:0] : enqDst_0_rl[72:0]) } ; assign enqDst_0_rl$EN = 1'd1 ; @@ -4608,8 +4606,8 @@ module mkProc(CLK, // register enqDst_1_0_rl assign enqDst_1_0_rl$D_IN = { !CAN_FIRE_RL_doEnq_1 && - IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1283, - IF_enqDst_1_0_lat_1_whas__275_THEN_enqDst_1_0__ETC___d1322 } ; + IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1279, + IF_enqDst_1_0_lat_1_whas__271_THEN_enqDst_1_0__ETC___d1318 } ; assign enqDst_1_0_rl$EN = 1'd1 ; // register llc_axi4_adapter_cfg_verbosity @@ -4648,7 +4646,7 @@ module mkProc(CLK, // register llc_axi4_adapter_master_xactor_rg_rd_addr assign llc_axi4_adapter_master_xactor_rg_rd_addr$D_IN = - { 4'd0, mem_req_rd_addr_araddr__h134692, 29'd851968 } ; + { 4'd0, mem_req_rd_addr_araddr__h134676, 29'd851968 } ; assign llc_axi4_adapter_master_xactor_rg_rd_addr$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ; @@ -4659,13 +4657,13 @@ module mkProc(CLK, // register llc_axi4_adapter_master_xactor_rg_wr_addr assign llc_axi4_adapter_master_xactor_rg_wr_addr$D_IN = - { 4'd0, mem_req_wr_addr_awaddr__h148616, 29'd851968 } ; + { 4'd0, mem_req_wr_addr_awaddr__h148600, 29'd851968 } ; assign llc_axi4_adapter_master_xactor_rg_wr_addr$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ; // register llc_axi4_adapter_master_xactor_rg_wr_data assign llc_axi4_adapter_master_xactor_rg_wr_data$D_IN = - { data64__h148531, strb8__h148532, 1'd1 } ; + { data64__h148515, strb8__h148516, 1'd1 } ; assign llc_axi4_adapter_master_xactor_rg_wr_data$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ; @@ -4677,7 +4675,7 @@ module mkProc(CLK, !llc_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read ; // register llc_axi4_adapter_rg_cline - assign llc_axi4_adapter_rg_cline$D_IN = new_cline__h135394 ; + assign llc_axi4_adapter_rg_cline$D_IN = new_cline__h135378 ; assign llc_axi4_adapter_rg_cline$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps ; @@ -4708,10 +4706,10 @@ module mkProc(CLK, // register llc_mem_server_enqDst_0_rl assign llc_mem_server_enqDst_0_rl$D_IN = { !CAN_FIRE_RL_llc_mem_server_doEnq && - IF_llc_mem_server_enqDst_0_lat_0_whas__680_THE_ETC___d1685, + IF_llc_mem_server_enqDst_0_lat_0_whas__676_THE_ETC___d1681, CAN_FIRE_RL_llc_mem_server_doEnq ? 65'h0AAAAAAAAAAAAAAAA : - (NOT_llc_mem_server_enqDst_0_dummy2_0_read__711_ETC___d1718 ? + (NOT_llc_mem_server_enqDst_0_dummy2_0_read__707_ETC___d1714 ? llc_mem_server_enqDst_0_lat_0$wget[64:0] : llc_mem_server_enqDst_0_rl[64:0]) } ; assign llc_mem_server_enqDst_0_rl$EN = 1'd1 ; @@ -4725,15 +4723,15 @@ module mkProc(CLK, // register llc_mem_server_propDstIdx_0_rl assign llc_mem_server_propDstIdx_0_rl$D_IN = - !NOT_llc_mem_server_enqDst_0_dummy2_0_read__711_ETC___d1718 && - IF_llc_mem_server_propDstIdx_0_lat_0_whas__665_ETC___d1668 ; + !NOT_llc_mem_server_enqDst_0_dummy2_0_read__707_ETC___d1714 && + IF_llc_mem_server_propDstIdx_0_lat_0_whas__661_ETC___d1664 ; assign llc_mem_server_propDstIdx_0_rl$EN = 1'd1 ; // register llc_mem_server_rg_cacheline_cache_addr assign llc_mem_server_rg_cacheline_cache_addr$D_IN = WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ? - line_addr__h102462 : - line_addr__h102548 ; + line_addr__h102446 : + line_addr__h102532 ; assign llc_mem_server_rg_cacheline_cache_addr$EN = WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st || WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld ; @@ -4804,11 +4802,10 @@ module mkProc(CLK, MUX_mmioPlatform_curReq$write_1__VAL_1 : MUX_mmioPlatform_curReq$write_1__VAL_2 ; assign mmioPlatform_curReq$EN = - WILL_FIRE_RL_mmioPlatform_selectReq && - NOT_mmioPlatform_mtip_0_55_64_AND_mmioPlatform_ETC___d379 || + MUX_mmioPlatform_curReq$write_1__SEL_1 || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] && - mmioPlatform_fetchingWay_73_ULT_mmioPlatform_r_ETC___d983 ; + mmioPlatform_fetchingWay_69_ULT_mmioPlatform_r_ETC___d979 ; // register mmioPlatform_cycle assign mmioPlatform_cycle$D_IN = @@ -4821,11 +4818,11 @@ module mkProc(CLK, // register mmioPlatform_fetchedInsts_0 assign mmioPlatform_fetchedInsts_0$D_IN = - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d991 ; + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d987 ; assign mmioPlatform_fetchedInsts_0$EN = WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] && - mmioPlatform_fetchingWay_73_ULT_mmioPlatform_r_ETC___d983 && + mmioPlatform_fetchingWay_69_ULT_mmioPlatform_r_ETC___d979 && !mmioPlatform_fetchingWay ; // register mmioPlatform_fetchingWay @@ -4834,10 +4831,12 @@ module mkProc(CLK, MUX_mmioPlatform_fetchingWay$write_1__VAL_2 ; assign mmioPlatform_fetchingWay$EN = WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_55_OR_NOT_mmioPlatform_mti_ETC___d410 || + (mmioPlatform_mtip_0 || + !mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357) && + core_0$mmioToPlatform_cRq_notEmpty || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] && - mmioPlatform_fetchingWay_73_ULT_mmioPlatform_r_ETC___d983 ; + mmioPlatform_fetchingWay_69_ULT_mmioPlatform_r_ETC___d979 ; // register mmioPlatform_fromHostAddr assign mmioPlatform_fromHostAddr$D_IN = start_fromhostAddr[63:3] ; @@ -4883,15 +4882,17 @@ module mkProc(CLK, MUX_mmioPlatform_instSel$write_1__VAL_2 ; assign mmioPlatform_instSel$EN = WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_55_OR_NOT_mmioPlatform_mti_ETC___d410 || + (mmioPlatform_mtip_0 || + !mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357) && + core_0$mmioToPlatform_cRq_notEmpty || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] && - mmioPlatform_fetchingWay_73_ULT_mmioPlatform_r_ETC___d983 ; + mmioPlatform_fetchingWay_69_ULT_mmioPlatform_r_ETC___d979 ; // register mmioPlatform_mtime assign mmioPlatform_mtime$D_IN = MUX_mmioPlatform_amoResp$write_1__SEL_2 ? - newData__h34977 : + newData__h34961 : MUX_mmioPlatform_mtime$write_1__VAL_2 ; assign mmioPlatform_mtime$EN = WILL_FIRE_RL_mmioPlatform_processMTime && @@ -4900,7 +4901,7 @@ module mkProc(CLK, WILL_FIRE_RL_mmioPlatform_incTime ; // register mmioPlatform_mtimecmp_0 - assign mmioPlatform_mtimecmp_0$D_IN = newData__h32047 ; + assign mmioPlatform_mtimecmp_0$D_IN = newData__h32031 ; assign mmioPlatform_mtimecmp_0$EN = MUX_mmioPlatform_amoResp$write_1__SEL_1 ; @@ -4910,10 +4911,9 @@ module mkProc(CLK, MUX_mmioPlatform_mtip_0$write_1__VAL_2 ; assign mmioPlatform_mtip_0$EN = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 && - mmioPlatform_mtimecmp_0 != 64'd0 || + mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 || WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d585 ; + NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d581 ; // register mmioPlatform_reqAmofunc assign mmioPlatform_reqAmofunc$D_IN = @@ -4983,8 +4983,7 @@ module mkProc(CLK, endcase end assign mmioPlatform_state$EN = - WILL_FIRE_RL_mmioPlatform_selectReq && - NOT_mmioPlatform_mtip_0_55_64_AND_mmioPlatform_ETC___d379 || + MUX_mmioPlatform_curReq$write_1__SEL_1 || WILL_FIRE_RL_mmioPlatform_processMSIP || WILL_FIRE_RL_mmioPlatform_processMTimeCmp || WILL_FIRE_RL_mmioPlatform_processMTime || @@ -5048,7 +5047,7 @@ module mkProc(CLK, mmioPlatform_reqBE[0] ; assign mmioPlatform_waitLowerMSIPCRs$EN = WILL_FIRE_RL_mmioPlatform_processMSIP && - NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d490 ; + NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d486 ; // register mmioPlatform_waitMTIPCRs assign mmioPlatform_waitMTIPCRs$D_IN = @@ -5056,16 +5055,15 @@ module mkProc(CLK, MUX_mmioPlatform_waitMTIPCRs$write_1__VAL_2 ; assign mmioPlatform_waitMTIPCRs$EN = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 && - mmioPlatform_mtimecmp_0 != 64'd0 || + mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 || WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d648 ; + NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d644 ; // register mmioPlatform_waitUpperMSIPCRs assign mmioPlatform_waitUpperMSIPCRs$D_IN = 1'd0 ; assign mmioPlatform_waitUpperMSIPCRs$EN = WILL_FIRE_RL_mmioPlatform_processMSIP && - NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d490 ; + NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d486 ; // register mmio_axi4_adapter_cfg_verbosity assign mmio_axi4_adapter_cfg_verbosity$D_IN = 4'h0 ; @@ -5151,28 +5149,28 @@ module mkProc(CLK, // register propDstData_1_0_rl assign propDstData_1_0_rl$D_IN = - { IF_propDstData_1_0_lat_0_whas__202_THEN_propDs_ETC___d1207, - IF_propDstData_1_0_lat_0_whas__202_THEN_propDs_ETC___d1212, + { IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1203, + IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1208, CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[513] : propDstData_1_0_rl[513], CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[512:1] : propDstData_1_0_rl[512:1], - IF_propDstData_1_0_lat_0_whas__202_THEN_propDs_ETC___d1233 } ; + IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1229 } ; assign propDstData_1_0_rl$EN = 1'd1 ; // register propDstData_1_1_rl assign propDstData_1_1_rl$D_IN = - { IF_propDstData_1_1_lat_0_whas__240_THEN_propDs_ETC___d1245, - IF_propDstData_1_1_lat_0_whas__240_THEN_propDs_ETC___d1250, + { IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1241, + IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1246, CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[513] : propDstData_1_1_rl[513], CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[512:1] : propDstData_1_1_rl[512:1], - IF_propDstData_1_1_lat_0_whas__240_THEN_propDs_ETC___d1271 } ; + IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1267 } ; assign propDstData_1_1_rl$EN = 1'd1 ; // register propDstData_1_rl @@ -5185,36 +5183,36 @@ module mkProc(CLK, // register propDstIdx_0_rl assign propDstIdx_0_rl$D_IN = !propDstIdx_0_lat_1$whas && - IF_propDstIdx_0_lat_0_whas__013_THEN_propDstId_ETC___d1016 ; + IF_propDstIdx_0_lat_0_whas__009_THEN_propDstId_ETC___d1012 ; assign propDstIdx_0_rl$EN = 1'd1 ; // register propDstIdx_1_0_rl assign propDstIdx_1_0_rl$D_IN = !propDstIdx_1_0_lat_1$whas && - IF_propDstIdx_1_0_lat_0_whas__187_THEN_propDst_ETC___d1190 ; + IF_propDstIdx_1_0_lat_0_whas__183_THEN_propDst_ETC___d1186 ; assign propDstIdx_1_0_rl$EN = 1'd1 ; // register propDstIdx_1_1_rl assign propDstIdx_1_1_rl$D_IN = !propDstIdx_1_1_lat_1$whas && - IF_propDstIdx_1_1_lat_0_whas__194_THEN_propDst_ETC___d1197 ; + IF_propDstIdx_1_1_lat_0_whas__190_THEN_propDst_ETC___d1193 ; assign propDstIdx_1_1_rl$EN = 1'd1 ; // register propDstIdx_1_rl assign propDstIdx_1_rl$D_IN = !propDstIdx_1_lat_1$whas && - IF_propDstIdx_1_lat_0_whas__020_THEN_propDstId_ETC___d1023 ; + IF_propDstIdx_1_lat_0_whas__016_THEN_propDstId_ETC___d1019 ; assign propDstIdx_1_rl$EN = 1'd1 ; // register srcRR_0 assign srcRR_0$D_IN = srcRR_0 + 1'd1 ; assign srcRR_0$EN = - NOT_enqDst_0_dummy2_0_read__087_088_OR_NOT_enq_ETC___d1103 ; + NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 ; // register srcRR_1_0 assign srcRR_1_0$D_IN = srcRR_1_0 + 1'd1 ; assign srcRR_1_0$EN = - NOT_enqDst_1_0_dummy2_0_read__361_362_OR_NOT_e_ETC___d1377 ; + NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 ; // submodule core_0 assign core_0$coreReq_perfReq_loc = 4'h0 ; @@ -5323,7 +5321,7 @@ module mkProc(CLK, assign core_0$setMEIP_v = m_external_interrupt_req_set_not_clear ; assign core_0$setSEIP_v = s_external_interrupt_req_set_not_clear ; assign core_0$tlbToMem_respLd_enq_x = - { ld_data__h132647, llc$dma_respLd_first[3] } ; + { ld_data__h132631, llc$dma_respLd_first[3] } ; assign core_0$EN_coreReq_start = EN_start ; assign core_0$EN_coreReq_perfReq = 1'b0 ; assign core_0$EN_coreIndInv_perfResp = 1'b0 ; @@ -5344,13 +5342,13 @@ module mkProc(CLK, MUX_mmioPlatform_fetchingWay$write_1__SEL_1 ; assign core_0$EN_mmioToPlatform_pRs_enq = WILL_FIRE_RL_mmioPlatform_processMSIP && - mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d467 || + mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d463 || WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d571 || + mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d567 || WILL_FIRE_RL_mmioPlatform_processMTime && - mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d636 || + mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d632 || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && - (!mmioPlatform_fetchingWay_73_ULT_mmioPlatform_r_ETC___d983 || + (!mmioPlatform_fetchingWay_69_ULT_mmioPlatform_r_ETC___d979 || !mmio_axi4_adapter_f_rsps_to_core$D_OUT[64]) || WILL_FIRE_RL_mmioPlatform_waitMTimeDone || WILL_FIRE_RL_mmioPlatform_waitMTimeCmpDone || @@ -5361,16 +5359,15 @@ module mkProc(CLK, WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp ; assign core_0$EN_mmioToPlatform_pRq_enq = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 && - mmioPlatform_mtimecmp_0 != 64'd0 || + mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 || WILL_FIRE_RL_mmioPlatform_processMSIP && mmioPlatform_reqFunc[5:4] != 2'd0 && !mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0] || WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d585 || + NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d581 || WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d648 ; + NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d644 ; assign core_0$EN_mmioToPlatform_cRs_deq = (WILL_FIRE_RL_mmioPlatform_waitMTimeDone || WILL_FIRE_RL_mmioPlatform_waitTimerInterruptDone) && @@ -5427,7 +5424,7 @@ module mkProc(CLK, // submodule enqDst_0_dummy2_0 assign enqDst_0_dummy2_0$D_IN = 1'd1 ; assign enqDst_0_dummy2_0$EN = - NOT_enqDst_0_dummy2_0_read__087_088_OR_NOT_enq_ETC___d1103 ; + NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 ; // submodule enqDst_0_dummy2_1 assign enqDst_0_dummy2_1$D_IN = 1'd1 ; @@ -5436,7 +5433,7 @@ module mkProc(CLK, // submodule enqDst_1_0_dummy2_0 assign enqDst_1_0_dummy2_0$D_IN = 1'd1 ; assign enqDst_1_0_dummy2_0$EN = - NOT_enqDst_1_0_dummy2_0_read__361_362_OR_NOT_e_ETC___d1377 ; + NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 ; // submodule enqDst_1_0_dummy2_1 assign enqDst_1_0_dummy2_1$D_IN = 1'd1 ; @@ -5468,17 +5465,17 @@ module mkProc(CLK, assign llc$perf_req_r = 4'h0 ; assign llc$perf_setStatus_doStats = core_0$sendDoStats ; assign llc$to_child_rqFromC_enq_x = - NOT_enqDst_0_dummy2_0_read__087_088_OR_NOT_enq_ETC___d1103 ? + NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 ? enqDst_0_lat_0$wget[72:0] : enqDst_0_rl[72:0] ; assign llc$to_child_rsFromC_enq_x = - { IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1293, - IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1298, - IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1303, - IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1313, - IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1319 } ; + { IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1289, + IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1294, + IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1299, + IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1309, + IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1315 } ; assign llc$to_mem_rsFromM_enq_x = - { new_cline__h135394, + { new_cline__h135378, llc_axi4_adapter_f_pending_reads$D_OUT[4:0] } ; assign llc$EN_to_child_rsFromC_enq = CAN_FIRE_RL_doEnq_1 ; assign llc$EN_to_child_rqFromC_enq = CAN_FIRE_RL_doEnq ; @@ -5554,7 +5551,7 @@ module mkProc(CLK, // submodule llc_mem_server_axi4_slave_xactor_f_rd_data assign llc_mem_server_axi4_slave_xactor_f_rd_data$D_IN = - { 4'd0, dword__h94398, 3'd1 } ; + { 4'd0, dword__h94382, 3'd1 } ; assign llc_mem_server_axi4_slave_xactor_f_rd_data$ENQ = CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req ; assign llc_mem_server_axi4_slave_xactor_f_rd_data$DEQ = @@ -5605,7 +5602,7 @@ module mkProc(CLK, // submodule llc_mem_server_enqDst_0_dummy2_0 assign llc_mem_server_enqDst_0_dummy2_0$D_IN = 1'd1 ; assign llc_mem_server_enqDst_0_dummy2_0$EN = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__711_ETC___d1718 ; + NOT_llc_mem_server_enqDst_0_dummy2_0_read__707_ETC___d1714 ; // submodule llc_mem_server_enqDst_0_dummy2_1 assign llc_mem_server_enqDst_0_dummy2_1$D_IN = 1'd1 ; @@ -5635,11 +5632,11 @@ module mkProc(CLK, // submodule llc_mem_server_propDstIdx_0_dummy2_1 assign llc_mem_server_propDstIdx_0_dummy2_1$D_IN = 1'd1 ; assign llc_mem_server_propDstIdx_0_dummy2_1$EN = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__711_ETC___d1718 ; + NOT_llc_mem_server_enqDst_0_dummy2_0_read__707_ETC___d1714 ; // submodule llc_mem_server_tlbQ assign llc_mem_server_tlbQ$D_IN = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__711_ETC___d1718 ? + NOT_llc_mem_server_enqDst_0_dummy2_0_read__707_ETC___d1714 ? llc_mem_server_enqDst_0_lat_0$wget[64:0] : llc_mem_server_enqDst_0_rl[64:0] ; assign llc_mem_server_tlbQ$ENQ = CAN_FIRE_RL_llc_mem_server_doEnq ; @@ -5857,86 +5854,86 @@ module mkProc(CLK, // remaining internal signals module_amoExec instance_amoExec_0(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h30134 && - mmioPlatform_reqBE_BIT_0___h30174, + mmioPlatform_reqBE_BIT_4___h30118 && + mmioPlatform_reqBE_BIT_0___h30158, 2'd0 }), - .amoExec_current_data(x__h37428), - .amoExec_in_data(mmioPlatform_reqData__h48701), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30134 && - !mmioPlatform_reqBE_BIT_0___h30174), - .amoExec(x__h32158)); + .amoExec_current_data(x__h37412), + .amoExec_in_data(mmioPlatform_reqData__h48685), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30118 && + !mmioPlatform_reqBE_BIT_0___h30158), + .amoExec(x__h32142)); module_amoExec instance_amoExec_1(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h30134 && - mmioPlatform_reqBE_BIT_0___h30174, + mmioPlatform_reqBE_BIT_4___h30118 && + mmioPlatform_reqBE_BIT_0___h30158, 2'd0 }), - .amoExec_current_data(mmioPlatform_mtime__h37280), - .amoExec_in_data(mmioPlatform_reqData__h48701), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30134 && - !mmioPlatform_reqBE_BIT_0___h30174), - .amoExec(x__h35068)); + .amoExec_current_data(mmioPlatform_mtime__h37264), + .amoExec_in_data(mmioPlatform_reqData__h48685), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30118 && + !mmioPlatform_reqBE_BIT_0___h30158), + .amoExec(x__h35052)); module_amoExec instance_amoExec_2(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h30134 && - mmioPlatform_reqBE_BIT_0___h30174, + mmioPlatform_reqBE_BIT_4___h30118 && + mmioPlatform_reqBE_BIT_0___h30158, 2'd0 }), - .amoExec_current_data(mmioPlatform_fromHostQ_data_0__h42761), - .amoExec_in_data(mmioPlatform_reqData__h48701), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30134 && - !mmioPlatform_reqBE_BIT_0___h30174), - .amoExec(x__h40962)); + .amoExec_current_data(mmioPlatform_fromHostQ_data_0__h42745), + .amoExec_in_data(mmioPlatform_reqData__h48685), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30118 && + !mmioPlatform_reqBE_BIT_0___h30158), + .amoExec(x__h40946)); module_amoExec instance_amoExec_3(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h30134 && - mmioPlatform_reqBE_BIT_0___h30174, + mmioPlatform_reqBE_BIT_4___h30118 && + mmioPlatform_reqBE_BIT_0___h30158, 2'd0 }), .amoExec_current_data(64'd0), - .amoExec_in_data(mmioPlatform_reqData__h48701), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30134 && - !mmioPlatform_reqBE_BIT_0___h30174), - .amoExec(x__h43028)); - assign DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_40_BIT_ETC___d684 = + .amoExec_in_data(mmioPlatform_reqData__h48685), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30118 && + !mmioPlatform_reqBE_BIT_0___h30158), + .amoExec(x__h43012)); + assign DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_36_BIT_ETC___d680 = { 1'h0, (mmioPlatform_reqFunc[5:4] == 2'd2) ? { mmioPlatform_toHostQ_empty, 64'hAAAAAAAAAAAAAAAA } : { mmioPlatform_reqFunc[5:4] == 2'd1, - x1_avValue_data__h40433 } } ; - assign IF_IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4__ETC___d559 = - (IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 && + x1_avValue_data__h40417 } } ; + assign IF_IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4__ETC___d555 = + (IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && !mmioPlatform_mtip_0 || - !IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 && + !IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && mmioPlatform_mtip_0) ? core_0$RDY_mmioToPlatform_pRq_enq : core_0$RDY_mmioToPlatform_pRs_enq ; - assign IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d456 = + assign IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d452 = (mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? (mmioPlatform_reqBE[0] ? core_0$RDY_mmioToPlatform_pRq_enq : core_0$RDY_mmioToPlatform_pRs_enq) : !mmioPlatform_reqBE[0] || core_0$RDY_mmioToPlatform_pRq_enq ; - assign IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 = - newData__h32047 <= mmioPlatform_mtime ; - assign IF_NOT_propDstIdx_0_dummy2_1_read__066_067_OR__ETC___d1101 = - NOT_propDstIdx_0_dummy2_1_read__066_067_OR_IF__ETC___d1100 ? + assign IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 = + newData__h32031 <= mmioPlatform_mtime ; + assign IF_NOT_propDstIdx_0_dummy2_1_read__062_063_OR__ETC___d1097 = + NOT_propDstIdx_0_dummy2_1_read__062_063_OR_IF__ETC___d1096 ? propDstIdx_1_dummy2_1$Q_OUT && - IF_propDstIdx_1_lat_0_whas__020_THEN_propDstId_ETC___d1023 : + IF_propDstIdx_1_lat_0_whas__016_THEN_propDstId_ETC___d1019 : propDstIdx_0_dummy2_1$Q_OUT && - IF_propDstIdx_0_lat_0_whas__013_THEN_propDstId_ETC___d1016 ; - assign IF_NOT_propDstIdx_1_0_dummy2_1_read__330_331_O_ETC___d1375 = - NOT_propDstIdx_1_0_dummy2_1_read__330_331_OR_I_ETC___d1374 ? + IF_propDstIdx_0_lat_0_whas__009_THEN_propDstId_ETC___d1012 ; + assign IF_NOT_propDstIdx_1_0_dummy2_1_read__326_327_O_ETC___d1371 = + NOT_propDstIdx_1_0_dummy2_1_read__326_327_OR_I_ETC___d1370 ? propDstIdx_1_1_dummy2_1$Q_OUT && - IF_propDstIdx_1_1_lat_0_whas__194_THEN_propDst_ETC___d1197 : + IF_propDstIdx_1_1_lat_0_whas__190_THEN_propDst_ETC___d1193 : propDstIdx_1_0_dummy2_1$Q_OUT && - IF_propDstIdx_1_0_lat_0_whas__187_THEN_propDst_ETC___d1190 ; - assign IF_SEL_ARR_propDstIdx_0_dummy2_1_read__066_AND_ETC___d1173 = - SEL_ARR_propDstIdx_0_dummy2_1_read__066_AND_IF_ETC___d1097 ? + IF_propDstIdx_1_0_lat_0_whas__183_THEN_propDst_ETC___d1186 ; + assign IF_SEL_ARR_propDstIdx_0_dummy2_1_read__062_AND_ETC___d1169 = + SEL_ARR_propDstIdx_0_dummy2_1_read__062_AND_IF_ETC___d1093 ? !srcRR_0 : propDstIdx_0_dummy2_1$Q_OUT && - IF_propDstIdx_0_lat_0_whas__013_THEN_propDstId_ETC___d1016 ; - assign IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__330_A_ETC___d1475 = - SEL_ARR_propDstIdx_1_0_dummy2_1_read__330_AND__ETC___d1371 ? + IF_propDstIdx_0_lat_0_whas__009_THEN_propDstId_ETC___d1012 ; + assign IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__326_A_ETC___d1471 = + SEL_ARR_propDstIdx_1_0_dummy2_1_read__326_AND__ETC___d1367 ? !srcRR_1_0 : propDstIdx_1_0_dummy2_1$Q_OUT && - IF_propDstIdx_1_0_lat_0_whas__187_THEN_propDst_ETC___d1190 ; - assign IF_core_0_mmioToPlatform_cRq_first__82_BITS_14_ETC___d405 = + IF_propDstIdx_1_0_lat_0_whas__183_THEN_propDst_ETC___d1186 ; + assign IF_core_0_mmioToPlatform_cRq_first__78_BITS_14_ETC___d401 = (core_0$mmioToPlatform_cRq_first[141:81] == mmioPlatform_toHostAddr) ? 67'h5AAAAAAAAAAAAAAAA : @@ -5944,116 +5941,116 @@ module mkProc(CLK, mmioPlatform_fromHostAddr) ? 67'h6AAAAAAAAAAAAAAAA : { 3'd7, core_0$mmioToPlatform_cRq_first[141:78] }) ; - assign IF_enqDst_0_lat_0_whas__042_THEN_enqDst_0_lat__ETC___d1047 = - NOT_enqDst_0_dummy2_0_read__087_088_OR_NOT_enq_ETC___d1103 ? + assign IF_enqDst_0_lat_0_whas__038_THEN_enqDst_0_lat__ETC___d1043 = + NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 ? enqDst_0_lat_0$wget[73] : enqDst_0_rl[73] ; - assign IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1283 = - NOT_enqDst_1_0_dummy2_0_read__361_362_OR_NOT_e_ETC___d1377 ? + assign IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1279 = + NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 ? enqDst_1_0_lat_0$wget[580] : enqDst_1_0_rl[580] ; - assign IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1293 = - NOT_enqDst_1_0_dummy2_0_read__361_362_OR_NOT_e_ETC___d1377 ? + assign IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1289 = + NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 ? enqDst_1_0_lat_0$wget[579:516] : enqDst_1_0_rl[579:516] ; - assign IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1298 = - NOT_enqDst_1_0_dummy2_0_read__361_362_OR_NOT_e_ETC___d1377 ? + assign IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1294 = + NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 ? enqDst_1_0_lat_0$wget[515:514] : enqDst_1_0_rl[515:514] ; - assign IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1303 = - NOT_enqDst_1_0_dummy2_0_read__361_362_OR_NOT_e_ETC___d1377 ? + assign IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1299 = + NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 ? enqDst_1_0_lat_0$wget[513] : enqDst_1_0_rl[513] ; - assign IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1313 = - NOT_enqDst_1_0_dummy2_0_read__361_362_OR_NOT_e_ETC___d1377 ? + assign IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1309 = + NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 ? enqDst_1_0_lat_0$wget[512:1] : enqDst_1_0_rl[512:1] ; - assign IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1319 = - NOT_enqDst_1_0_dummy2_0_read__361_362_OR_NOT_e_ETC___d1377 ? + assign IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1315 = + NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 ? enqDst_1_0_lat_0$wget[0] : enqDst_1_0_rl[0] ; - assign IF_enqDst_1_0_lat_1_whas__275_THEN_enqDst_1_0__ETC___d1321 = + assign IF_enqDst_1_0_lat_1_whas__271_THEN_enqDst_1_0__ETC___d1317 = { CAN_FIRE_RL_doEnq_1 || - IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1303, + IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1299, CAN_FIRE_RL_doEnq_1 ? 512'h55555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555 : - IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1313, - x__h75245 } ; - assign IF_enqDst_1_0_lat_1_whas__275_THEN_enqDst_1_0__ETC___d1322 = + IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1309, + x__h75229 } ; + assign IF_enqDst_1_0_lat_1_whas__271_THEN_enqDst_1_0__ETC___d1318 = { CAN_FIRE_RL_doEnq_1 ? 64'hAAAAAAAAAAAAAAAA : - IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1293, + IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1289, CAN_FIRE_RL_doEnq_1 ? 2'b10 : - IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1298, - IF_enqDst_1_0_lat_1_whas__275_THEN_enqDst_1_0__ETC___d1321 } ; - assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1595 = + IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1294, + IF_enqDst_1_0_lat_1_whas__271_THEN_enqDst_1_0__ETC___d1317 } ; + assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1591 = { (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd7) ? - new_dword__h90089 : + new_dword__h90073 : llc_mem_server_rg_cacheline_cache_data[511:448], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd6) ? - new_dword__h90089 : + new_dword__h90073 : llc_mem_server_rg_cacheline_cache_data[447:384], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd5) ? - new_dword__h90089 : + new_dword__h90073 : llc_mem_server_rg_cacheline_cache_data[383:320], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd4) ? - new_dword__h90089 : + new_dword__h90073 : llc_mem_server_rg_cacheline_cache_data[319:256] } ; - assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1600 = - { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1595, + assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1596 = + { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1591, (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd3) ? - new_dword__h90089 : + new_dword__h90073 : llc_mem_server_rg_cacheline_cache_data[255:192], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd2) ? - new_dword__h90089 : + new_dword__h90073 : llc_mem_server_rg_cacheline_cache_data[191:128] } ; - assign IF_llc_mem_server_enqDst_0_lat_0_whas__680_THE_ETC___d1685 = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__711_ETC___d1718 ? + assign IF_llc_mem_server_enqDst_0_lat_0_whas__676_THE_ETC___d1681 = + NOT_llc_mem_server_enqDst_0_dummy2_0_read__707_ETC___d1714 ? llc_mem_server_enqDst_0_lat_0$wget[65] : llc_mem_server_enqDst_0_rl[65] ; - assign IF_llc_mem_server_propDstIdx_0_lat_0_whas__665_ETC___d1668 = + assign IF_llc_mem_server_propDstIdx_0_lat_0_whas__661_ETC___d1664 = CAN_FIRE_RL_llc_mem_server_srcPropose || llc_mem_server_propDstIdx_0_rl ; - assign IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d833 = + assign IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829 = (mmioPlatform_curReq[2:0] == 3'h0) ? mmioPlatform_reqData : 64'd0 ; - assign IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d884 = + assign IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d880 = (mmioPlatform_curReq[2:0] == 3'h0) ? mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:0] : 64'd0 ; - assign IF_mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioP_ETC___d625 = - ((mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && + assign IF_mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioP_ETC___d621 = + ((mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && !mmioPlatform_mtip_0) ? core_0$RDY_mmioToPlatform_pRq_enq : - mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 || + mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 || !mmioPlatform_mtip_0 || core_0$RDY_mmioToPlatform_pRq_enq) && - (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && + (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && + !mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && mmioPlatform_mtip_0 || core_0$RDY_mmioToPlatform_pRs_enq) ; - assign IF_mmioPlatform_reqBE_43_BIT_4_44_THEN_SEXT_mm_ETC___d577 = + assign IF_mmioPlatform_reqBE_39_BIT_4_40_THEN_SEXT_mm_ETC___d573 = mmioPlatform_reqBE[4] ? { {32{mmioPlatform_mtimecmp_0_BITS_63_TO_32__q9[31]}}, mmioPlatform_mtimecmp_0_BITS_63_TO_32__q9 } : { {32{mmioPlatform_mtimecmp_0_BITS_31_TO_0__q10[31]}}, mmioPlatform_mtimecmp_0_BITS_31_TO_0__q10 } ; - assign IF_mmioPlatform_reqBE_43_BIT_4_44_THEN_SEXT_mm_ETC___d641 = + assign IF_mmioPlatform_reqBE_39_BIT_4_40_THEN_SEXT_mm_ETC___d637 = mmioPlatform_reqBE[4] ? { {32{mmioPlatform_mtime_BITS_63_TO_32__q11[31]}}, mmioPlatform_mtime_BITS_63_TO_32__q11 } : { {32{mmioPlatform_mtime_BITS_31_TO_0__q12[31]}}, mmioPlatform_mtime_BITS_31_TO_0__q12 } ; - assign IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d535 = + assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d531 = { mmioPlatform_reqBE[7] ? mmioPlatform_reqData[63:56] : mmioPlatform_mtimecmp_0[63:56], @@ -6066,23 +6063,23 @@ module mkProc(CLK, mmioPlatform_reqBE[4] ? mmioPlatform_reqData[39:32] : mmioPlatform_mtimecmp_0[39:32] } ; - assign IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d544 = - { IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d535, + assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d540 = + { IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d531, mmioPlatform_reqBE[3] ? mmioPlatform_reqData[31:24] : mmioPlatform_mtimecmp_0[31:24], mmioPlatform_reqBE[2] ? mmioPlatform_reqData[23:16] : mmioPlatform_mtimecmp_0[23:16] } ; - assign IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d552 = - { IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d544, + assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d548 = + { IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d540, mmioPlatform_reqBE[1] ? mmioPlatform_reqData[15:8] : mmioPlatform_mtimecmp_0[15:8], mmioPlatform_reqBE[0] ? mmioPlatform_reqData[7:0] : mmioPlatform_mtimecmp_0[7:0] } ; - assign IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d604 = + assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d600 = { mmioPlatform_reqBE[7] ? mmioPlatform_reqData[63:56] : mmioPlatform_mtime[63:56], @@ -6095,23 +6092,23 @@ module mkProc(CLK, mmioPlatform_reqBE[4] ? mmioPlatform_reqData[39:32] : mmioPlatform_mtime[39:32] } ; - assign IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d609 = - { IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d604, + assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d605 = + { IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d600, mmioPlatform_reqBE[3] ? mmioPlatform_reqData[31:24] : mmioPlatform_mtime[31:24], mmioPlatform_reqBE[2] ? mmioPlatform_reqData[23:16] : mmioPlatform_mtime[23:16] } ; - assign IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d614 = - { IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d609, + assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d610 = + { IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d605, mmioPlatform_reqBE[1] ? mmioPlatform_reqData[15:8] : mmioPlatform_mtime[15:8], mmioPlatform_reqBE[0] ? mmioPlatform_reqData[7:0] : mmioPlatform_mtime[7:0] } ; - assign IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d708 = + assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d704 = { mmioPlatform_reqBE[7] ? mmioPlatform_reqData[63:56] : mmioPlatform_fromHostQ_data_0[63:56], @@ -6124,49 +6121,49 @@ module mkProc(CLK, mmioPlatform_reqBE[4] ? mmioPlatform_reqData[39:32] : mmioPlatform_fromHostQ_data_0[39:32] } ; - assign IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d713 = - { IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d708, + assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d709 = + { IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d704, mmioPlatform_reqBE[3] ? mmioPlatform_reqData[31:24] : mmioPlatform_fromHostQ_data_0[31:24], mmioPlatform_reqBE[2] ? mmioPlatform_reqData[23:16] : mmioPlatform_fromHostQ_data_0[23:16] } ; - assign IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d718 = - { IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d713, + assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d714 = + { IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d709, mmioPlatform_reqBE[1] ? mmioPlatform_reqData[15:8] : mmioPlatform_fromHostQ_data_0[15:8], mmioPlatform_reqBE[0] ? mmioPlatform_reqData[7:0] : mmioPlatform_fromHostQ_data_0[7:0] } ; - assign IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_ETC___d457 = + assign IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d453 = (mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqBE[4]) ? core_0$RDY_mmioToPlatform_pRs_enq : - IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d456 ; - assign IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_1_ETC___d578 = + IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d452 ; + assign IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_1_ETC___d574 = (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtimecmp_0 : - IF_mmioPlatform_reqBE_43_BIT_4_44_THEN_SEXT_mm_ETC___d577 ; - assign IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_1_ETC___d642 = + IF_mmioPlatform_reqBE_39_BIT_4_40_THEN_SEXT_mm_ETC___d573 ; + assign IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_1_ETC___d638 = (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtime : - IF_mmioPlatform_reqBE_43_BIT_4_44_THEN_SEXT_mm_ETC___d641 ; - assign IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_2_ETC___d726 = + IF_mmioPlatform_reqBE_39_BIT_4_40_THEN_SEXT_mm_ETC___d637 ; + assign IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_2_ETC___d722 = (mmioPlatform_reqFunc[5:4] == 2'd2) ? { mmioPlatform_fromHostQ_empty ? - x__h43017 == 64'd0 : - x__h40951 == 64'd0, + x__h43001 == 64'd0 : + x__h40935 == 64'd0, 64'hAAAAAAAAAAAAAAAA } : { mmioPlatform_reqFunc[5:4] == 2'd1, - x1_avValue_data__h45038 } ; + x1_avValue_data__h45022 } ; assign IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__91__ETC___d200 = mmioPlatform_toHostQ_enqReq_lat_0$whas ? mmioPlatform_toHostQ_enqReq_lat_0$wget[64] : mmioPlatform_toHostQ_enqReq_rl[64] ; - assign IF_mmioPlatform_waitLowerMSIPCRs_92_THEN_core__ETC___d500 = + assign IF_mmioPlatform_waitLowerMSIPCRs_88_THEN_core__ETC___d496 = mmioPlatform_waitLowerMSIPCRs ? core_0$RDY_mmioToPlatform_cRs_first && core_0$RDY_mmioToPlatform_cRs_deq : @@ -6174,99 +6171,99 @@ module mkProc(CLK, core_0$RDY_mmioToPlatform_cRs_first) && (!mmioPlatform_waitUpperMSIPCRs || core_0$RDY_mmioToPlatform_cRs_deq) ; - assign IF_mmio_axi4_adapter_f_rsps_to_core_first__64__ETC___d978 = + assign IF_mmio_axi4_adapter_f_rsps_to_core_first__60__ETC___d974 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] ? mmioPlatform_fetchingWay < (mmioPlatform_reqFunc[5:4] == 2'd0 && mmioPlatform_reqFunc[0]) || core_0$RDY_mmioToPlatform_pRs_enq : core_0$RDY_mmioToPlatform_pRs_enq ; - assign IF_mmio_axi4_adapter_f_rsps_to_core_first__64__ETC___d999 = + assign IF_mmio_axi4_adapter_f_rsps_to_core_first__60__ETC___d995 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] ? (mmioPlatform_fetchingWay ? mmioPlatform_fetchedInsts_0 : - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d991) : + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d987) : mmioPlatform_fetchedInsts_0 ; assign IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d103 = mmio_axi4_adapter_soc_map$m_is_IO_addr ? !mmio_axi4_adapter_master_xactor_crg_wr_addr_full$port2__read && !mmio_axi4_adapter_master_xactor_crg_wr_data_full$port2__read : mmio_axi4_adapter_f_rsps_to_core$FULL_N ; - assign IF_propDstData_0_dummy2_1_read__104_THEN_IF_pr_ETC___d1120 = + assign IF_propDstData_0_dummy2_1_read__100_THEN_IF_pr_ETC___d1116 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[8:7] : propDstData_0_rl[8:7]) : 2'd0 ; - assign IF_propDstData_0_dummy2_1_read__104_THEN_IF_pr_ETC___d1130 = + assign IF_propDstData_0_dummy2_1_read__100_THEN_IF_pr_ETC___d1126 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[6:5] : propDstData_0_rl[6:5]) : 2'd0 ; - assign IF_propDstData_1_0_lat_0_whas__202_THEN_propDs_ETC___d1207 = + assign IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1203 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[579:516] : propDstData_1_0_rl[579:516] ; - assign IF_propDstData_1_0_lat_0_whas__202_THEN_propDs_ETC___d1212 = + assign IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1208 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[515:514] : propDstData_1_0_rl[515:514] ; - assign IF_propDstData_1_0_lat_0_whas__202_THEN_propDs_ETC___d1233 = + assign IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1229 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[0] : propDstData_1_0_rl[0] ; - assign IF_propDstData_1_1_lat_0_whas__240_THEN_propDs_ETC___d1245 = + assign IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1241 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[579:516] : propDstData_1_1_rl[579:516] ; - assign IF_propDstData_1_1_lat_0_whas__240_THEN_propDs_ETC___d1250 = + assign IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1246 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[515:514] : propDstData_1_1_rl[515:514] ; - assign IF_propDstData_1_1_lat_0_whas__240_THEN_propDs_ETC___d1271 = + assign IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1267 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[0] : propDstData_1_1_rl[0] ; - assign IF_propDstData_1_dummy2_1_read__109_THEN_IF_pr_ETC___d1124 = + assign IF_propDstData_1_dummy2_1_read__105_THEN_IF_pr_ETC___d1120 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[8:7] : propDstData_1_rl[8:7]) : 2'd0 ; - assign IF_propDstData_1_dummy2_1_read__109_THEN_IF_pr_ETC___d1134 = + assign IF_propDstData_1_dummy2_1_read__105_THEN_IF_pr_ETC___d1130 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[6:5] : propDstData_1_rl[6:5]) : 2'd0 ; - assign IF_propDstIdx_0_lat_0_whas__013_THEN_propDstId_ETC___d1016 = + assign IF_propDstIdx_0_lat_0_whas__009_THEN_propDstId_ETC___d1012 = CAN_FIRE_RL_srcPropose || propDstIdx_0_rl ; - assign IF_propDstIdx_1_0_lat_0_whas__187_THEN_propDst_ETC___d1190 = + assign IF_propDstIdx_1_0_lat_0_whas__183_THEN_propDst_ETC___d1186 = CAN_FIRE_RL_srcPropose_2 || propDstIdx_1_0_rl ; - assign IF_propDstIdx_1_1_lat_0_whas__194_THEN_propDst_ETC___d1197 = + assign IF_propDstIdx_1_1_lat_0_whas__190_THEN_propDst_ETC___d1193 = CAN_FIRE_RL_srcPropose_3 || propDstIdx_1_1_rl ; - assign IF_propDstIdx_1_lat_0_whas__020_THEN_propDstId_ETC___d1023 = + assign IF_propDstIdx_1_lat_0_whas__016_THEN_propDstId_ETC___d1019 = CAN_FIRE_RL_srcPropose_1 || propDstIdx_1_rl ; - assign NOT_enqDst_0_dummy2_0_read__087_088_OR_NOT_enq_ETC___d1103 = + assign NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 = (!enqDst_0_dummy2_0$Q_OUT || !enqDst_0_dummy2_1$Q_OUT || !enqDst_0_rl[73]) && - (SEL_ARR_propDstIdx_0_dummy2_1_read__066_AND_IF_ETC___d1097 || - IF_NOT_propDstIdx_0_dummy2_1_read__066_067_OR__ETC___d1101) ; - assign NOT_enqDst_1_0_dummy2_0_read__361_362_OR_NOT_e_ETC___d1377 = + (SEL_ARR_propDstIdx_0_dummy2_1_read__062_AND_IF_ETC___d1093 || + IF_NOT_propDstIdx_0_dummy2_1_read__062_063_OR__ETC___d1097) ; + assign NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 = (!enqDst_1_0_dummy2_0$Q_OUT || !enqDst_1_0_dummy2_1$Q_OUT || !enqDst_1_0_rl[580]) && - (SEL_ARR_propDstIdx_1_0_dummy2_1_read__330_AND__ETC___d1371 || - IF_NOT_propDstIdx_1_0_dummy2_1_read__330_331_O_ETC___d1375) ; - assign NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801 = + (SEL_ARR_propDstIdx_1_0_dummy2_1_read__326_AND__ETC___d1367 || + IF_NOT_propDstIdx_1_0_dummy2_1_read__326_327_O_ETC___d1371) ; + assign NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797 = llc_axi4_adapter_cfg_verbosity > 4'd1 ; - assign NOT_llc_mem_server_enqDst_0_dummy2_0_read__711_ETC___d1718 = + assign NOT_llc_mem_server_enqDst_0_dummy2_0_read__707_ETC___d1714 = (!llc_mem_server_enqDst_0_dummy2_0$Q_OUT || !llc_mem_server_enqDst_0_dummy2_1$Q_OUT || !llc_mem_server_enqDst_0_rl[65]) && llc_mem_server_propDstIdx_0_dummy2_1$Q_OUT && - IF_llc_mem_server_propDstIdx_0_lat_0_whas__665_ETC___d1668 ; - assign NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d754 = + IF_llc_mem_server_propDstIdx_0_lat_0_whas__661_ETC___d1664 ; + assign NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d750 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -6277,7 +6274,7 @@ module mkProc(CLK, mmioPlatform_state == 2'd2 && (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqFunc[5:4] == 2'd2) ; - assign NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d762 = + assign NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d758 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -6288,7 +6285,7 @@ module mkProc(CLK, mmioPlatform_state == 2'd3 && (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqFunc[5:4] == 2'd2) ; - assign NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d767 = + assign NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d763 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -6300,7 +6297,7 @@ module mkProc(CLK, mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2 ; - assign NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d777 = + assign NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d773 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -6312,7 +6309,7 @@ module mkProc(CLK, mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2 ; - assign NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d968 = + assign NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d964 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -6322,7 +6319,7 @@ module mkProc(CLK, mmioPlatform_curReq[66:64] != 3'd6 && mmioPlatform_state == 2'd2 && mmioPlatform_reqFunc[5:4] == 2'd0 ; - assign NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d981 = + assign NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d977 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -6342,35 +6339,29 @@ module mkProc(CLK, (mmioPlatform_fromHostQ_deqReq_lat_0$whas || mmioPlatform_fromHostQ_deqReq_rl) || mmioPlatform_fromHostQ_empty) ; - assign NOT_mmioPlatform_mtip_0_55_64_AND_mmioPlatform_ETC___d374 = + assign NOT_mmioPlatform_mtip_0_55_62_AND_mmioPlatform_ETC___d370 = !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 && - mmioPlatform_mtimecmp_0 != 64'd0 || + mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 || !core_0$mmioToPlatform_cRq_notEmpty || core_0$RDY_mmioToPlatform_cRq_first && core_0$RDY_mmioToPlatform_cRq_deq ; - assign NOT_mmioPlatform_mtip_0_55_64_AND_mmioPlatform_ETC___d379 = - !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 && - mmioPlatform_mtimecmp_0 != 64'd0 || - core_0$mmioToPlatform_cRq_notEmpty ; - assign NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d490 = + assign NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d486 = mmioPlatform_reqFunc[5:4] != 2'd0 && !mmioPlatform_reqBE[4] && (mmioPlatform_reqBE[0] || mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqFunc[5:4] == 2'd2) ; - assign NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d585 = + assign NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d581 = mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && - (IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 && + (IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && !mmioPlatform_mtip_0 || - !IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 && + !IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && mmioPlatform_mtip_0) ; - assign NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d648 = + assign NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d644 = mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && - (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && + (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && + !mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && mmioPlatform_mtip_0) ; assign NOT_mmioPlatform_toHostQ_clearReq_dummy2_1_rea_ETC___d240 = !mmioPlatform_toHostQ_clearReq_dummy2_1$Q_OUT || @@ -6384,51 +6375,51 @@ module mkProc(CLK, (!mmioPlatform_toHostQ_empty || mmioPlatform_toHostQ_deqReq_rl) || mmioPlatform_toHostQ_empty) ; - assign NOT_propDstData_1_0_dummy2_1_read__378_389_OR__ETC___d1390 = + assign NOT_propDstData_1_0_dummy2_1_read__374_385_OR__ETC___d1386 = !propDstData_1_0_dummy2_1$Q_OUT || (CAN_FIRE_RL_srcPropose_2 ? !propDstData_1_0_lat_0$wget[513] : !propDstData_1_0_rl[513]) ; - assign NOT_propDstData_1_1_dummy2_1_read__380_391_OR__ETC___d1392 = + assign NOT_propDstData_1_1_dummy2_1_read__376_387_OR__ETC___d1388 = !propDstData_1_1_dummy2_1$Q_OUT || (CAN_FIRE_RL_srcPropose_3 ? !propDstData_1_1_lat_0$wget[513] : !propDstData_1_1_rl[513]) ; - assign NOT_propDstIdx_0_dummy2_1_read__066_067_OR_IF__ETC___d1100 = + assign NOT_propDstIdx_0_dummy2_1_read__062_063_OR_IF__ETC___d1096 = !propDstIdx_0_dummy2_1$Q_OUT || !CAN_FIRE_RL_srcPropose && !propDstIdx_0_rl ; - assign NOT_propDstIdx_1_0_dummy2_1_read__330_331_OR_I_ETC___d1374 = + assign NOT_propDstIdx_1_0_dummy2_1_read__326_327_OR_I_ETC___d1370 = !propDstIdx_1_0_dummy2_1$Q_OUT || !CAN_FIRE_RL_srcPropose_2 && !propDstIdx_1_0_rl ; - assign SEL_ARR_IF_propDstData_0_dummy2_1_read__104_TH_ETC___d1168 = - { CASE_x1509_0_IF_propDstData_0_dummy2_1_read__1_ETC__q21, - CASE_x1509_0_IF_propDstData_0_dummy2_1_read__1_ETC__q22, - SEL_ARR_propDstData_0_dummy2_1_read__104_AND_I_ETC___d1167 } ; - assign SEL_ARR_IF_propDstData_1_0_dummy2_1_read__378__ETC___d1470 = - { CASE_x0316_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32, - !CASE_x0316_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__202_THE_ETC___d1463, - x__h82732 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__202_THE_ETC___d1412 = - { CASE_x0316_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24, - CASE_x0316_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__202_THE_ETC___d1429 = - { SEL_ARR_IF_propDstData_1_0_lat_0_whas__202_THE_ETC___d1412, - CASE_x0316_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26, - CASE_x0316_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__202_THE_ETC___d1446 = - { SEL_ARR_IF_propDstData_1_0_lat_0_whas__202_THE_ETC___d1429, - CASE_x0316_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28, - CASE_x0316_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__202_THE_ETC___d1463 = - { SEL_ARR_IF_propDstData_1_0_lat_0_whas__202_THE_ETC___d1446, - CASE_x0316_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30, - CASE_x0316_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 } ; - assign SEL_ARR_propDstData_0_dummy2_1_read__104_AND_I_ETC___d1167 = - { CASE_x1509_0_propDstData_0_dummy2_1_read__104__ETC__q20, - x__h61823, - x__h61830 } ; - assign b__h134399 = + assign SEL_ARR_IF_propDstData_0_dummy2_1_read__100_TH_ETC___d1164 = + { CASE_x1493_0_IF_propDstData_0_dummy2_1_read__1_ETC__q21, + CASE_x1493_0_IF_propDstData_0_dummy2_1_read__1_ETC__q22, + SEL_ARR_propDstData_0_dummy2_1_read__100_AND_I_ETC___d1163 } ; + assign SEL_ARR_IF_propDstData_1_0_dummy2_1_read__374__ETC___d1466 = + { CASE_x0300_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32, + !CASE_x0300_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1459, + x__h82716 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1408 = + { CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24, + CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1425 = + { SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1408, + CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26, + CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1442 = + { SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1425, + CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28, + CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1459 = + { SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1442, + CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30, + CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 } ; + assign SEL_ARR_propDstData_0_dummy2_1_read__100_AND_I_ETC___d1163 = + { CASE_x1493_0_propDstData_0_dummy2_1_read__100__ETC__q20, + x__h61807, + x__h61814 } ; + assign b__h134383 = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ? llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 : llc_axi4_adapter_ctr_wr_rsps_pending_crg ; @@ -6436,23 +6427,23 @@ module mkProc(CLK, mmio_axi4_adapter_ctr_wr_rsps_pending_crg$EN_port0__write ? mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 : mmio_axi4_adapter_ctr_wr_rsps_pending_crg ; - assign data__h31966 = + assign data__h31950 = mmioPlatform_waitLowerMSIPCRs ? { 63'd0, core_0$mmioToPlatform_cRs_first } : - { v__h31759, 32'd0 } ; - assign failed_testnum__h163177 = + { v__h31743, 32'd0 } ; + assign failed_testnum__h163161 = { 1'd0, mmioPlatform_toHostQ_data_0[63:1] } ; - assign line_addr__h102462 = + assign line_addr__h102446 = { llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[92:35], 6'b0 } ; - assign line_addr__h102548 = + assign line_addr__h102532 = { llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[92:35], 6'b0 } ; - assign llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1612 = - line_addr__h102548 == llc_mem_server_rg_cacheline_cache_addr ; - assign llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1534 = - line_addr__h102462 == llc_mem_server_rg_cacheline_cache_addr ; - assign mask__h90085 = + assign llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1608 = + line_addr__h102532 == llc_mem_server_rg_cacheline_cache_addr ; + assign llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1530 = + line_addr__h102446 == llc_mem_server_rg_cacheline_cache_addr ; + assign mask__h90069 = { llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8] ? 8'hFF : 8'h0, @@ -6477,14 +6468,14 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[1] ? 8'hFF : 8'h0 } ; - assign mem_req_rd_addr_araddr__h134692 = - { llc$to_mem_toM_first[68:11], x__h134727 } ; - assign mem_req_wr_addr_awaddr__h148616 = - { llc$to_mem_toM_first[639:582], x__h148641 } ; + assign mem_req_rd_addr_araddr__h134676 = + { llc$to_mem_toM_first[68:11], x__h134711 } ; + assign mem_req_wr_addr_awaddr__h148600 = + { llc$to_mem_toM_first[639:582], x__h148625 } ; assign mmioPlatform_cycle_47_ULT_99___d348 = mmioPlatform_cycle < 7'd99 ; - assign mmioPlatform_fetchingWay_73_ULT_mmioPlatform_r_ETC___d983 = + assign mmioPlatform_fetchingWay_69_ULT_mmioPlatform_r_ETC___d979 = mmioPlatform_fetchingWay < mmioPlatform_reqFunc[0] ; - assign mmioPlatform_fromHostQ_data_0__h42761 = + assign mmioPlatform_fromHostQ_data_0__h42745 = mmioPlatform_fromHostQ_data_0 ; assign mmioPlatform_fromHostQ_enqReq_dummy2_2_read__1_ETC___d331 = mmioPlatform_fromHostQ_enqReq_dummy2_2$Q_OUT && @@ -6495,41 +6486,36 @@ module mkProc(CLK, mmioPlatform_fromHostQ_full ; assign mmioPlatform_mtime_BITS_31_TO_0__q12 = mmioPlatform_mtime[31:0] ; assign mmioPlatform_mtime_BITS_63_TO_32__q11 = mmioPlatform_mtime[63:32] ; - assign mmioPlatform_mtime__h37280 = mmioPlatform_mtime ; - assign mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 = - mmioPlatform_mtimecmp_0 <= newData__h34977 ; + assign mmioPlatform_mtime__h37264 = mmioPlatform_mtime ; + assign mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 = + mmioPlatform_mtimecmp_0 <= newData__h34961 ; assign mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 = mmioPlatform_mtimecmp_0 <= mmioPlatform_mtime ; assign mmioPlatform_mtimecmp_0_BITS_31_TO_0__q10 = mmioPlatform_mtimecmp_0[31:0] ; assign mmioPlatform_mtimecmp_0_BITS_63_TO_32__q9 = mmioPlatform_mtimecmp_0[63:32] ; - assign mmioPlatform_mtip_0_55_OR_NOT_mmioPlatform_mti_ETC___d410 = - (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 || - mmioPlatform_mtimecmp_0 == 64'd0) && - core_0$mmioToPlatform_cRq_notEmpty ; - assign mmioPlatform_reqBE_BIT_0___h30174 = mmioPlatform_reqBE[0] ; - assign mmioPlatform_reqBE_BIT_4___h30134 = mmioPlatform_reqBE[4] ; - assign mmioPlatform_reqData__h48701 = mmioPlatform_reqData ; - assign mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d467 = + assign mmioPlatform_reqBE_BIT_0___h30158 = mmioPlatform_reqBE[0] ; + assign mmioPlatform_reqBE_BIT_4___h30118 = mmioPlatform_reqBE[4] ; + assign mmioPlatform_reqData__h48685 = mmioPlatform_reqData ; + assign mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d463 = mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqBE[4] || mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2 && !mmioPlatform_reqBE[0] ; - assign mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d571 = + assign mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d567 = mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqFunc[5:4] == 2'd1 || - (!IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 || + (!IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 || mmioPlatform_mtip_0) && - (IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 || + (IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 || !mmioPlatform_mtip_0) ; - assign mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d636 = + assign mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d632 = mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqFunc[5:4] == 2'd1 || - (!mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 || + (!mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 || mmioPlatform_mtip_0) && - (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 || + (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 || !mmioPlatform_mtip_0) ; assign mmioPlatform_toHostQ_enqReq_dummy2_2_read__41__ETC___d253 = mmioPlatform_toHostQ_enqReq_dummy2_2$Q_OUT && @@ -6543,235 +6529,235 @@ module mkProc(CLK, (mmio_axi4_adapter_soc_map$m_is_IO_addr ? !mmio_axi4_adapter_master_xactor_crg_rd_addr_full$port2__read : mmio_axi4_adapter_f_rsps_to_core$FULL_N) ; - assign n__read_addr__h61691 = + assign n__read_addr__h61675 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[72:9] : propDstData_0_rl[72:9]) : 64'd0 ; - assign n__read_addr__h61776 = + assign n__read_addr__h61760 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[72:9] : propDstData_1_rl[72:9]) : 64'd0 ; - assign n__read_addr__h80494 = + assign n__read_addr__h80478 = propDstData_1_0_dummy2_1$Q_OUT ? - IF_propDstData_1_0_lat_0_whas__202_THEN_propDs_ETC___d1207 : + IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1203 : 64'd0 ; - assign n__read_addr__h80573 = + assign n__read_addr__h80557 = propDstData_1_1_dummy2_1$Q_OUT ? - IF_propDstData_1_1_lat_0_whas__240_THEN_propDs_ETC___d1245 : + IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1241 : 64'd0 ; - assign n__read_child__h61696 = + assign n__read_child__h61680 = propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[0] : propDstData_0_rl[0]) ; - assign n__read_child__h61781 = + assign n__read_child__h61765 = propDstData_1_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[0] : propDstData_1_rl[0]) ; - assign n__read_child__h80497 = + assign n__read_child__h80481 = propDstData_1_0_dummy2_1$Q_OUT && - IF_propDstData_1_0_lat_0_whas__202_THEN_propDs_ETC___d1233 ; - assign n__read_child__h80576 = + IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1229 ; + assign n__read_child__h80560 = propDstData_1_1_dummy2_1$Q_OUT && - IF_propDstData_1_1_lat_0_whas__240_THEN_propDs_ETC___d1271 ; - assign n__read_id__h61695 = + IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1267 ; + assign n__read_id__h61679 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[3:1] : propDstData_0_rl[3:1]) : 3'd0 ; - assign n__read_id__h61780 = + assign n__read_id__h61764 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[3:1] : propDstData_1_rl[3:1]) : 3'd0 ; - assign n__read_snd_addr__h123989 = + assign n__read_snd_addr__h123973 = llc_mem_server_propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_llc_mem_server_srcPropose ? core_0$tlbToMem_memReq_first[64:1] : llc_mem_server_propDstData_0_rl[64:1]) : 64'd0 ; - assign n__read_snd_id__h123990 = + assign n__read_snd_id__h123974 = llc_mem_server_propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_llc_mem_server_srcPropose ? core_0$tlbToMem_memReq_first[0] : llc_mem_server_propDstData_0_rl[0]) ; - assign newData__h32047 = + assign newData__h32031 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h32158 : - IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d552 ; - assign newData__h34977 = + x__h32142 : + IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d548 ; + assign newData__h34961 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h35068 : - IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d614 ; - assign new_cline__h135394 = + x__h35052 : + IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d610 ; + assign new_cline__h135378 = { llc_axi4_adapter_master_xactor_rg_rd_data[66:3], llc_axi4_adapter_rg_cline[511:64] } ; - assign new_dword__h90089 = x__h91251 | y__h91252 ; - assign op_result__h48717 = - IF_mmioPlatform_reqSz_83_EQ_0b10_90_THEN_SEXT__ETC___d891 + - IF_mmioPlatform_reqSz_83_EQ_0b10_90_THEN_SEXT__ETC___d893 ; - assign op_result__h49247 = w1__h48114 ^ w2__h48116 ; - assign op_result__h49252 = w1__h48114 & w2__h48116 ; - assign op_result__h49257 = w1__h48114 | w2__h48116 ; - assign op_result__h49262 = - (w1__h48114 < w2__h48116) ? w1__h48114 : w2__h48116 ; - assign op_result__h49268 = - (w1__h48114 <= w2__h48116) ? w2__h48116 : w1__h48114 ; - assign op_result__h49275 = - ((IF_mmioPlatform_reqSz_83_EQ_0b10_90_THEN_SEXT__ETC___d891 ^ + assign new_dword__h90073 = x__h91235 | y__h91236 ; + assign op_result__h48701 = + IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d887 + + IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d889 ; + assign op_result__h49231 = w1__h48098 ^ w2__h48100 ; + assign op_result__h49236 = w1__h48098 & w2__h48100 ; + assign op_result__h49241 = w1__h48098 | w2__h48100 ; + assign op_result__h49246 = + (w1__h48098 < w2__h48100) ? w1__h48098 : w2__h48100 ; + assign op_result__h49252 = + (w1__h48098 <= w2__h48100) ? w2__h48100 : w1__h48098 ; + assign op_result__h49259 = + ((IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d887 ^ 64'h8000000000000000) < - (IF_mmioPlatform_reqSz_83_EQ_0b10_90_THEN_SEXT__ETC___d893 ^ + (IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d889 ^ 64'h8000000000000000)) ? - w1__h48114 : - w2__h48116 ; - assign op_result__h49281 = - ((IF_mmioPlatform_reqSz_83_EQ_0b10_90_THEN_SEXT__ETC___d891 ^ + w1__h48098 : + w2__h48100 ; + assign op_result__h49265 = + ((IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d887 ^ 64'h8000000000000000) <= - (IF_mmioPlatform_reqSz_83_EQ_0b10_90_THEN_SEXT__ETC___d893 ^ + (IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d889 ^ 64'h8000000000000000)) ? - w2__h48116 : - w1__h48114 ; - assign propDstData_0_dummy2_1_read__104_AND_IF_propDs_ETC___d1140 = + w2__h48100 : + w1__h48098 ; + assign propDstData_0_dummy2_1_read__100_AND_IF_propDs_ETC___d1136 = propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[4] : propDstData_0_rl[4]) ; - assign propDstData_1_dummy2_1_read__109_AND_IF_propDs_ETC___d1144 = + assign propDstData_1_dummy2_1_read__105_AND_IF_propDs_ETC___d1140 = propDstData_1_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[4] : propDstData_1_rl[4]) ; - assign result__h48160 = + assign result__h48144 = { mmioPlatform_reqData[63:8], - IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923[7:0] } ; - assign result__h48284 = { 56'd0, mmioPlatform_reqData[7:0] } ; - assign result__h48312 = { 56'd0, mmioPlatform_reqData[15:8] } ; - assign result__h48340 = { 56'd0, mmioPlatform_reqData[23:16] } ; - assign result__h48368 = { 56'd0, mmioPlatform_reqData[31:24] } ; - assign result__h48396 = { 56'd0, mmioPlatform_reqData[39:32] } ; - assign result__h48424 = { 56'd0, mmioPlatform_reqData[47:40] } ; - assign result__h48452 = { 56'd0, mmioPlatform_reqData[55:48] } ; - assign result__h48480 = { 56'd0, mmioPlatform_reqData[63:56] } ; - assign result__h48525 = { 48'd0, mmioPlatform_reqData[15:0] } ; - assign result__h48553 = { 48'd0, mmioPlatform_reqData[31:16] } ; - assign result__h48581 = { 48'd0, mmioPlatform_reqData[47:32] } ; - assign result__h48609 = { 48'd0, mmioPlatform_reqData[63:48] } ; - assign result__h48650 = { 32'd0, mmioPlatform_reqData[31:0] } ; - assign result__h48678 = { 32'd0, mmioPlatform_reqData[63:32] } ; - assign result__h48804 = + IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[7:0] } ; + assign result__h48268 = { 56'd0, mmioPlatform_reqData[7:0] } ; + assign result__h48296 = { 56'd0, mmioPlatform_reqData[15:8] } ; + assign result__h48324 = { 56'd0, mmioPlatform_reqData[23:16] } ; + assign result__h48352 = { 56'd0, mmioPlatform_reqData[31:24] } ; + assign result__h48380 = { 56'd0, mmioPlatform_reqData[39:32] } ; + assign result__h48408 = { 56'd0, mmioPlatform_reqData[47:40] } ; + assign result__h48436 = { 56'd0, mmioPlatform_reqData[55:48] } ; + assign result__h48464 = { 56'd0, mmioPlatform_reqData[63:56] } ; + assign result__h48509 = { 48'd0, mmioPlatform_reqData[15:0] } ; + assign result__h48537 = { 48'd0, mmioPlatform_reqData[31:16] } ; + assign result__h48565 = { 48'd0, mmioPlatform_reqData[47:32] } ; + assign result__h48593 = { 48'd0, mmioPlatform_reqData[63:48] } ; + assign result__h48634 = { 32'd0, mmioPlatform_reqData[31:0] } ; + assign result__h48662 = { 32'd0, mmioPlatform_reqData[63:32] } ; + assign result__h48788 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[7:0] } ; - assign result__h48831 = + assign result__h48815 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[15:8] } ; - assign result__h48858 = + assign result__h48842 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[23:16] } ; - assign result__h48885 = + assign result__h48869 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:24] } ; - assign result__h48912 = + assign result__h48896 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[39:32] } ; - assign result__h48939 = + assign result__h48923 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[47:40] } ; - assign result__h48966 = + assign result__h48950 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[55:48] } ; - assign result__h48993 = + assign result__h48977 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:56] } ; - assign result__h49037 = + assign result__h49021 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[15:0] } ; - assign result__h49064 = + assign result__h49048 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:16] } ; - assign result__h49091 = + assign result__h49075 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[47:32] } ; - assign result__h49118 = + assign result__h49102 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:48] } ; - assign result__h49158 = + assign result__h49142 = { 32'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:0] } ; - assign result__h49185 = + assign result__h49169 = { 32'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:32] } ; - assign result__h49302 = + assign result__h49286 = { mmioPlatform_reqData[63:16], - IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923[7:0], + IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[7:0], mmioPlatform_reqData[7:0] } ; - assign result__h49368 = + assign result__h49352 = { mmioPlatform_reqData[63:24], - IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923[7:0], + IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[7:0], mmioPlatform_reqData[15:0] } ; - assign result__h49434 = + assign result__h49418 = { mmioPlatform_reqData[63:32], - IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923[7:0], + IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[7:0], mmioPlatform_reqData[23:0] } ; - assign result__h49500 = + assign result__h49484 = { mmioPlatform_reqData[63:40], - IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923[7:0], + IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[7:0], mmioPlatform_reqData[31:0] } ; - assign result__h49566 = + assign result__h49550 = { mmioPlatform_reqData[63:48], - IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923[7:0], + IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[7:0], mmioPlatform_reqData[39:0] } ; - assign result__h49632 = + assign result__h49616 = { mmioPlatform_reqData[63:56], - IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923[7:0], + IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[7:0], mmioPlatform_reqData[47:0] } ; - assign result__h49698 = - { IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923[7:0], + assign result__h49682 = + { IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[7:0], mmioPlatform_reqData[55:0] } ; - assign result__h49760 = + assign result__h49744 = { mmioPlatform_reqData[63:16], - IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923[15:0] } ; - assign result__h49805 = + IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[15:0] } ; + assign result__h49789 = { mmioPlatform_reqData[63:32], - IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923[15:0], + IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[15:0], mmioPlatform_reqData[15:0] } ; - assign result__h49871 = + assign result__h49855 = { mmioPlatform_reqData[63:48], - IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923[15:0], + IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[15:0], mmioPlatform_reqData[31:0] } ; - assign result__h49937 = - { IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923[15:0], + assign result__h49921 = + { IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[15:0], mmioPlatform_reqData[47:0] } ; - assign result__h49995 = + assign result__h49979 = { mmioPlatform_reqData[63:32], - IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923[31:0] } ; - assign result__h50040 = - { IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923[31:0], + IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[31:0] } ; + assign result__h50024 = + { IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[31:0], mmioPlatform_reqData[31:0] } ; - assign v__h31759 = mmioPlatform_waitUpperMSIPCRs ? v__h31796 : 32'd0 ; - assign v__h31796 = { 31'd0, core_0$mmioToPlatform_cRs_first } ; - assign w18109_BITS_31_TO_0__q15 = w1__h48109[31:0] ; - assign w1___1__h48219 = { 32'd0, w1__h48109[31:0] } ; - assign w28110_BITS_31_TO_0__q16 = w2__h48110[31:0] ; - assign w2___1__h48220 = { 32'd0, w2__h48110[31:0] } ; - assign x1_avValue_data__h40433 = + assign v__h31743 = mmioPlatform_waitUpperMSIPCRs ? v__h31780 : 32'd0 ; + assign v__h31780 = { 31'd0, core_0$mmioToPlatform_cRs_first } ; + assign w18093_BITS_31_TO_0__q15 = w1__h48093[31:0] ; + assign w1___1__h48203 = { 32'd0, w1__h48093[31:0] } ; + assign w28094_BITS_31_TO_0__q16 = w2__h48094[31:0] ; + assign w2___1__h48204 = { 32'd0, w2__h48094[31:0] } ; + assign x1_avValue_data__h40417 = mmioPlatform_toHostQ_empty ? 64'd0 : mmioPlatform_toHostQ_data_0 ; - assign x1_avValue_data__h45038 = + assign x1_avValue_data__h45022 = mmioPlatform_fromHostQ_empty ? 64'd0 : mmioPlatform_fromHostQ_data_0 ; - assign x__h134727 = { llc_axi4_adapter_rg_rd_req_beat, 3'b0 } ; - assign x__h148641 = { llc_axi4_adapter_rg_wr_req_beat, 3'b0 } ; - assign x__h37428 = mmioPlatform_mtimecmp_0 ; - assign x__h40951 = + assign x__h134711 = { llc_axi4_adapter_rg_rd_req_beat, 3'b0 } ; + assign x__h148625 = { llc_axi4_adapter_rg_wr_req_beat, 3'b0 } ; + assign x__h37412 = mmioPlatform_mtimecmp_0 ; + assign x__h40935 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h40962 : - IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d718 ; - assign x__h43017 = + x__h40946 : + IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d714 ; + assign x__h43001 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h43028 : + x__h43012 : { mmioPlatform_reqBE[7] ? mmioPlatform_reqData[63:56] : 8'd0, mmioPlatform_reqBE[6] ? mmioPlatform_reqData[55:48] : 8'd0, mmioPlatform_reqBE[5] ? mmioPlatform_reqData[47:40] : 8'd0, @@ -6780,29 +6766,29 @@ module mkProc(CLK, mmioPlatform_reqBE[2] ? mmioPlatform_reqData[23:16] : 8'd0, mmioPlatform_reqBE[1] ? mmioPlatform_reqData[15:8] : 8'd0, mmioPlatform_reqBE[0] ? mmioPlatform_reqData[7:0] : 8'd0 } ; - assign x__h50217 = { mmioPlatform_curReq[63:3], 3'b0 } ; - assign x__h61509 = - SEL_ARR_propDstIdx_0_dummy2_1_read__066_AND_IF_ETC___d1097 ? + assign x__h50201 = { mmioPlatform_curReq[63:3], 3'b0 } ; + assign x__h61493 = + SEL_ARR_propDstIdx_0_dummy2_1_read__062_AND_IF_ETC___d1093 ? srcRR_0 : - NOT_propDstIdx_0_dummy2_1_read__066_067_OR_IF__ETC___d1100 ; - assign x__h75245 = + NOT_propDstIdx_0_dummy2_1_read__062_063_OR_IF__ETC___d1096 ; + assign x__h75229 = !CAN_FIRE_RL_doEnq_1 && - IF_enqDst_1_0_lat_0_whas__278_THEN_enqDst_1_0__ETC___d1319 ; + IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1315 ; assign x__h7925 = (mmio_axi4_adapter_f_reqs_from_core$D_OUT[71:68] == 4'd0 || mmio_axi4_adapter_f_reqs_from_core$D_OUT[67:64] == 4'd0) ? 3'b010 : 3'b011 ; - assign x__h80316 = - SEL_ARR_propDstIdx_1_0_dummy2_1_read__330_AND__ETC___d1371 ? + assign x__h80300 = + SEL_ARR_propDstIdx_1_0_dummy2_1_read__326_AND__ETC___d1367 ? srcRR_1_0 : - NOT_propDstIdx_1_0_dummy2_1_read__330_331_OR_I_ETC___d1374 ; - assign x__h91251 = old_dword__h90088 & y__h91253 ; - assign x_data__h30549 = { 31'd0, mmioPlatform_reqData[0] } ; - assign y__h91252 = + NOT_propDstIdx_1_0_dummy2_1_read__326_327_OR_I_ETC___d1370 ; + assign x__h91235 = old_dword__h90072 & y__h91237 ; + assign x_data__h30533 = { 31'd0, mmioPlatform_reqData[0] } ; + assign y__h91236 = llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[72:9] & - mask__h90085 ; - assign y__h91253 = + mask__h90069 ; + assign y__h91237 = { llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8] ? 8'd0 : 8'd255, @@ -7015,473 +7001,473 @@ module mkProc(CLK, llc_mem_server_rg_cacheline_cache_data) begin case (llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[34:32]) - 3'd0: dword__h94398 = llc_mem_server_rg_cacheline_cache_data[63:0]; - 3'd1: dword__h94398 = llc_mem_server_rg_cacheline_cache_data[127:64]; - 3'd2: dword__h94398 = llc_mem_server_rg_cacheline_cache_data[191:128]; - 3'd3: dword__h94398 = llc_mem_server_rg_cacheline_cache_data[255:192]; - 3'd4: dword__h94398 = llc_mem_server_rg_cacheline_cache_data[319:256]; - 3'd5: dword__h94398 = llc_mem_server_rg_cacheline_cache_data[383:320]; - 3'd6: dword__h94398 = llc_mem_server_rg_cacheline_cache_data[447:384]; - 3'd7: dword__h94398 = llc_mem_server_rg_cacheline_cache_data[511:448]; + 3'd0: dword__h94382 = llc_mem_server_rg_cacheline_cache_data[63:0]; + 3'd1: dword__h94382 = llc_mem_server_rg_cacheline_cache_data[127:64]; + 3'd2: dword__h94382 = llc_mem_server_rg_cacheline_cache_data[191:128]; + 3'd3: dword__h94382 = llc_mem_server_rg_cacheline_cache_data[255:192]; + 3'd4: dword__h94382 = llc_mem_server_rg_cacheline_cache_data[319:256]; + 3'd5: dword__h94382 = llc_mem_server_rg_cacheline_cache_data[383:320]; + 3'd6: dword__h94382 = llc_mem_server_rg_cacheline_cache_data[447:384]; + 3'd7: dword__h94382 = llc_mem_server_rg_cacheline_cache_data[511:448]; endcase end always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) begin case (llc_axi4_adapter_rg_wr_req_beat) - 3'd0: data64__h148531 = llc$to_mem_toM_first[63:0]; - 3'd1: data64__h148531 = llc$to_mem_toM_first[127:64]; - 3'd2: data64__h148531 = llc$to_mem_toM_first[191:128]; - 3'd3: data64__h148531 = llc$to_mem_toM_first[255:192]; - 3'd4: data64__h148531 = llc$to_mem_toM_first[319:256]; - 3'd5: data64__h148531 = llc$to_mem_toM_first[383:320]; - 3'd6: data64__h148531 = llc$to_mem_toM_first[447:384]; - 3'd7: data64__h148531 = llc$to_mem_toM_first[511:448]; + 3'd0: data64__h148515 = llc$to_mem_toM_first[63:0]; + 3'd1: data64__h148515 = llc$to_mem_toM_first[127:64]; + 3'd2: data64__h148515 = llc$to_mem_toM_first[191:128]; + 3'd3: data64__h148515 = llc$to_mem_toM_first[255:192]; + 3'd4: data64__h148515 = llc$to_mem_toM_first[319:256]; + 3'd5: data64__h148515 = llc$to_mem_toM_first[383:320]; + 3'd6: data64__h148515 = llc$to_mem_toM_first[447:384]; + 3'd7: data64__h148515 = llc$to_mem_toM_first[511:448]; endcase end always@(llc$dma_respLd_first) begin case (llc$dma_respLd_first[2:0]) - 3'd0: ld_data__h132647 = llc$dma_respLd_first[68:5]; - 3'd1: ld_data__h132647 = llc$dma_respLd_first[132:69]; - 3'd2: ld_data__h132647 = llc$dma_respLd_first[196:133]; - 3'd3: ld_data__h132647 = llc$dma_respLd_first[260:197]; - 3'd4: ld_data__h132647 = llc$dma_respLd_first[324:261]; - 3'd5: ld_data__h132647 = llc$dma_respLd_first[388:325]; - 3'd6: ld_data__h132647 = llc$dma_respLd_first[452:389]; - 3'd7: ld_data__h132647 = llc$dma_respLd_first[516:453]; + 3'd0: ld_data__h132631 = llc$dma_respLd_first[68:5]; + 3'd1: ld_data__h132631 = llc$dma_respLd_first[132:69]; + 3'd2: ld_data__h132631 = llc$dma_respLd_first[196:133]; + 3'd3: ld_data__h132631 = llc$dma_respLd_first[260:197]; + 3'd4: ld_data__h132631 = llc$dma_respLd_first[324:261]; + 3'd5: ld_data__h132631 = llc$dma_respLd_first[388:325]; + 3'd6: ld_data__h132631 = llc$dma_respLd_first[452:389]; + 3'd7: ld_data__h132631 = llc$dma_respLd_first[516:453]; endcase end always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) begin case (llc_axi4_adapter_rg_wr_req_beat) - 3'd0: strb8__h148532 = llc$to_mem_toM_first[519:512]; - 3'd1: strb8__h148532 = llc$to_mem_toM_first[527:520]; - 3'd2: strb8__h148532 = llc$to_mem_toM_first[535:528]; - 3'd3: strb8__h148532 = llc$to_mem_toM_first[543:536]; - 3'd4: strb8__h148532 = llc$to_mem_toM_first[551:544]; - 3'd5: strb8__h148532 = llc$to_mem_toM_first[559:552]; - 3'd6: strb8__h148532 = llc$to_mem_toM_first[567:560]; - 3'd7: strb8__h148532 = llc$to_mem_toM_first[575:568]; + 3'd0: strb8__h148516 = llc$to_mem_toM_first[519:512]; + 3'd1: strb8__h148516 = llc$to_mem_toM_first[527:520]; + 3'd2: strb8__h148516 = llc$to_mem_toM_first[535:528]; + 3'd3: strb8__h148516 = llc$to_mem_toM_first[543:536]; + 3'd4: strb8__h148516 = llc$to_mem_toM_first[551:544]; + 3'd5: strb8__h148516 = llc$to_mem_toM_first[559:552]; + 3'd6: strb8__h148516 = llc$to_mem_toM_first[567:560]; + 3'd7: strb8__h148516 = llc$to_mem_toM_first[575:568]; endcase end always@(llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT or llc_mem_server_rg_cacheline_cache_data) begin case (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32]) - 3'd0: old_dword__h90088 = llc_mem_server_rg_cacheline_cache_data[63:0]; + 3'd0: old_dword__h90072 = llc_mem_server_rg_cacheline_cache_data[63:0]; 3'd1: - old_dword__h90088 = llc_mem_server_rg_cacheline_cache_data[127:64]; + old_dword__h90072 = llc_mem_server_rg_cacheline_cache_data[127:64]; 3'd2: - old_dword__h90088 = llc_mem_server_rg_cacheline_cache_data[191:128]; + old_dword__h90072 = llc_mem_server_rg_cacheline_cache_data[191:128]; 3'd3: - old_dword__h90088 = llc_mem_server_rg_cacheline_cache_data[255:192]; + old_dword__h90072 = llc_mem_server_rg_cacheline_cache_data[255:192]; 3'd4: - old_dword__h90088 = llc_mem_server_rg_cacheline_cache_data[319:256]; + old_dword__h90072 = llc_mem_server_rg_cacheline_cache_data[319:256]; 3'd5: - old_dword__h90088 = llc_mem_server_rg_cacheline_cache_data[383:320]; + old_dword__h90072 = llc_mem_server_rg_cacheline_cache_data[383:320]; 3'd6: - old_dword__h90088 = llc_mem_server_rg_cacheline_cache_data[447:384]; + old_dword__h90072 = llc_mem_server_rg_cacheline_cache_data[447:384]; 3'd7: - old_dword__h90088 = llc_mem_server_rg_cacheline_cache_data[511:448]; + old_dword__h90072 = llc_mem_server_rg_cacheline_cache_data[511:448]; endcase end always@(mmioPlatform_curReq or - result__h48284 or - result__h48312 or - result__h48340 or - result__h48368 or - result__h48396 or - result__h48424 or result__h48452 or result__h48480) + result__h48268 or + result__h48296 or + result__h48324 or + result__h48352 or + result__h48380 or + result__h48408 or result__h48436 or result__h48464) begin case (mmioPlatform_curReq[2:0]) 3'h0: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d813 = - result__h48284; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 = + result__h48268; 3'h1: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d813 = - result__h48312; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 = + result__h48296; 3'h2: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d813 = - result__h48340; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 = + result__h48324; 3'h3: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d813 = - result__h48368; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 = + result__h48352; 3'h4: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d813 = - result__h48396; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 = + result__h48380; 3'h5: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d813 = - result__h48424; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 = + result__h48408; 3'h6: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d813 = - result__h48452; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 = + result__h48436; 3'h7: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d813 = - result__h48480; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 = + result__h48464; endcase end always@(mmioPlatform_curReq or - result__h48525 or - result__h48553 or result__h48581 or result__h48609) + result__h48509 or + result__h48537 or result__h48565 or result__h48593) begin case (mmioPlatform_curReq[2:0]) 3'h0: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d826 = - result__h48525; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822 = + result__h48509; 3'h2: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d826 = - result__h48553; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822 = + result__h48537; 3'h4: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d826 = - result__h48581; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822 = + result__h48565; 3'h6: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d826 = - result__h48609; - default: IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d826 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822 = + result__h48593; + default: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822 = 64'd0; endcase end - always@(mmioPlatform_curReq or result__h48650 or result__h48678) + always@(mmioPlatform_curReq or result__h48634 or result__h48662) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13 = - result__h48650; + result__h48634; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13 = - result__h48678; + result__h48662; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13 = 64'd0; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d813 or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d826 or + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 or + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822 or CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13 or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d833) + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829) begin case (mmioPlatform_reqSz) 2'b0: - w2__h48110 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d813; + w2__h48094 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809; 2'b01: - w2__h48110 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d826; + w2__h48094 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822; 2'b10: - w2__h48110 = + w2__h48094 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13; 2'b11: - w2__h48110 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d833; + w2__h48094 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d813 or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d826 or - w2___1__h48220 or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d833) + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 or + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822 or + w2___1__h48204 or + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829) begin case (mmioPlatform_reqSz) 2'b0: - w2__h48116 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d813; + w2__h48100 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809; 2'b01: - w2__h48116 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d826; - 2'b10: w2__h48116 = w2___1__h48220; + w2__h48100 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822; + 2'b10: w2__h48100 = w2___1__h48204; 2'b11: - w2__h48116 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d833; + w2__h48100 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829; endcase end always@(mmioPlatform_curReq or - result__h48804 or - result__h48831 or - result__h48858 or - result__h48885 or - result__h48912 or - result__h48939 or result__h48966 or result__h48993) + result__h48788 or + result__h48815 or + result__h48842 or + result__h48869 or + result__h48896 or + result__h48923 or result__h48950 or result__h48977) begin case (mmioPlatform_curReq[2:0]) 3'h0: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d865 = - result__h48804; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 = + result__h48788; 3'h1: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d865 = - result__h48831; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 = + result__h48815; 3'h2: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d865 = - result__h48858; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 = + result__h48842; 3'h3: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d865 = - result__h48885; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 = + result__h48869; 3'h4: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d865 = - result__h48912; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 = + result__h48896; 3'h5: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d865 = - result__h48939; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 = + result__h48923; 3'h6: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d865 = - result__h48966; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 = + result__h48950; 3'h7: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d865 = - result__h48993; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 = + result__h48977; endcase end always@(mmioPlatform_curReq or - result__h49037 or - result__h49064 or result__h49091 or result__h49118) + result__h49021 or + result__h49048 or result__h49075 or result__h49102) begin case (mmioPlatform_curReq[2:0]) 3'h0: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d877 = - result__h49037; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873 = + result__h49021; 3'h2: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d877 = - result__h49064; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873 = + result__h49048; 3'h4: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d877 = - result__h49091; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873 = + result__h49075; 3'h6: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d877 = - result__h49118; - default: IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d877 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873 = + result__h49102; + default: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873 = 64'd0; endcase end - always@(mmioPlatform_curReq or result__h49158 or result__h49185) + always@(mmioPlatform_curReq or result__h49142 or result__h49169) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14 = - result__h49158; + result__h49142; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14 = - result__h49185; + result__h49169; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14 = 64'd0; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d865 or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d877 or + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 or + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873 or CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14 or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d884) + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d880) begin case (mmioPlatform_reqSz) 2'b0: - w1__h48109 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d865; + w1__h48093 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861; 2'b01: - w1__h48109 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d877; + w1__h48093 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873; 2'b10: - w1__h48109 = + w1__h48093 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14; 2'b11: - w1__h48109 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d884; + w1__h48093 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d880; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d865 or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d877 or - w1___1__h48219 or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d884) + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 or + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873 or + w1___1__h48203 or + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d880) begin case (mmioPlatform_reqSz) 2'b0: - w1__h48114 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d865; + w1__h48098 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861; 2'b01: - w1__h48114 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d877; - 2'b10: w1__h48114 = w1___1__h48219; + w1__h48098 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873; + 2'b10: w1__h48098 = w1___1__h48203; 2'b11: - w1__h48114 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d884; + w1__h48098 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d880; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d865 or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d877 or - w18109_BITS_31_TO_0__q15 or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d884) + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 or + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873 or + w18093_BITS_31_TO_0__q15 or + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d880) begin case (mmioPlatform_reqSz) 2'b0: - IF_mmioPlatform_reqSz_83_EQ_0b10_90_THEN_SEXT__ETC___d891 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d865; + IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d887 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861; 2'b01: - IF_mmioPlatform_reqSz_83_EQ_0b10_90_THEN_SEXT__ETC___d891 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d877; + IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d887 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873; 2'b10: - IF_mmioPlatform_reqSz_83_EQ_0b10_90_THEN_SEXT__ETC___d891 = - { {32{w18109_BITS_31_TO_0__q15[31]}}, - w18109_BITS_31_TO_0__q15 }; + IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d887 = + { {32{w18093_BITS_31_TO_0__q15[31]}}, + w18093_BITS_31_TO_0__q15 }; 2'b11: - IF_mmioPlatform_reqSz_83_EQ_0b10_90_THEN_SEXT__ETC___d891 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d884; + IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d887 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d880; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d813 or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d826 or - w28110_BITS_31_TO_0__q16 or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d833) + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 or + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822 or + w28094_BITS_31_TO_0__q16 or + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829) begin case (mmioPlatform_reqSz) 2'b0: - IF_mmioPlatform_reqSz_83_EQ_0b10_90_THEN_SEXT__ETC___d893 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d813; + IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d889 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809; 2'b01: - IF_mmioPlatform_reqSz_83_EQ_0b10_90_THEN_SEXT__ETC___d893 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d826; + IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d889 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822; 2'b10: - IF_mmioPlatform_reqSz_83_EQ_0b10_90_THEN_SEXT__ETC___d893 = - { {32{w28110_BITS_31_TO_0__q16[31]}}, - w28110_BITS_31_TO_0__q16 }; + IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d889 = + { {32{w28094_BITS_31_TO_0__q16[31]}}, + w28094_BITS_31_TO_0__q16 }; 2'b11: - IF_mmioPlatform_reqSz_83_EQ_0b10_90_THEN_SEXT__ETC___d893 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d833; + IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d889 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829; endcase end always@(mmioPlatform_reqAmofunc or - op_result__h49281 or - w2__h48116 or - op_result__h48717 or - op_result__h49247 or - op_result__h49252 or - op_result__h49257 or - op_result__h49275 or op_result__h49262 or op_result__h49268) + op_result__h49265 or + w2__h48100 or + op_result__h48701 or + op_result__h49231 or + op_result__h49236 or + op_result__h49241 or + op_result__h49259 or op_result__h49246 or op_result__h49252) begin case (mmioPlatform_reqAmofunc) 4'd0: - IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923 = - w2__h48116; + IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 = + w2__h48100; 4'd1: - IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923 = - op_result__h48717; + IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 = + op_result__h48701; 4'd2: - IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923 = - op_result__h49247; + IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 = + op_result__h49231; 4'd3: - IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923 = - op_result__h49252; + IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 = + op_result__h49236; 4'd4: - IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923 = - op_result__h49257; + IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 = + op_result__h49241; 4'd5: - IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923 = - op_result__h49275; + IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 = + op_result__h49259; 4'd7: - IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923 = - op_result__h49262; + IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 = + op_result__h49246; 4'd8: - IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923 = - op_result__h49268; - default: IF_mmioPlatform_reqAmofunc_88_EQ_0_89_THEN_IF__ETC___d923 = - op_result__h49281; + IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 = + op_result__h49252; + default: IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 = + op_result__h49265; endcase end always@(mmioPlatform_curReq or - result__h49760 or - result__h49805 or result__h49871 or result__h49937) + result__h49744 or + result__h49789 or result__h49855 or result__h49921) begin case (mmioPlatform_curReq[2:0]) 3'h0: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d956 = - result__h49760; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d952 = + result__h49744; 3'h2: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d956 = - result__h49805; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d952 = + result__h49789; 3'h4: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d956 = - result__h49871; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d952 = + result__h49855; 3'h6: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d956 = - result__h49937; - default: IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d956 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d952 = + result__h49921; + default: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d952 = 64'd0; endcase end always@(mmioPlatform_curReq or - result__h48160 or - result__h49302 or - result__h49368 or - result__h49434 or - result__h49500 or - result__h49566 or result__h49632 or result__h49698) + result__h48144 or + result__h49286 or + result__h49352 or + result__h49418 or + result__h49484 or + result__h49550 or result__h49616 or result__h49682) begin case (mmioPlatform_curReq[2:0]) 3'h0: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d947 = - result__h48160; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 = + result__h48144; 3'h1: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d947 = - result__h49302; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 = + result__h49286; 3'h2: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d947 = - result__h49368; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 = + result__h49352; 3'h3: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d947 = - result__h49434; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 = + result__h49418; 3'h4: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d947 = - result__h49500; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 = + result__h49484; 3'h5: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d947 = - result__h49566; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 = + result__h49550; 3'h6: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d947 = - result__h49632; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 = + result__h49616; 3'h7: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d947 = - result__h49698; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 = + result__h49682; endcase end - always@(mmioPlatform_curReq or result__h49995 or result__h50040) + always@(mmioPlatform_curReq or result__h49979 or result__h50024) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17 = - result__h49995; + result__h49979; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17 = - result__h50040; + result__h50024; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17 = 64'd0; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d947 or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d956 or + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 or + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d952 or CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17 or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d833) + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829) begin case (mmioPlatform_reqSz) 2'b0: - x__h48105 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d947; + x__h48089 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943; 2'b01: - x__h48105 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d956; + x__h48089 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d952; 2'b10: - x__h48105 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17; + x__h48089 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17; 2'b11: - x__h48105 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_85_EQ_0x_ETC___d833; + x__h48089 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829; endcase end always@(mmioPlatform_reqFunc) begin case (mmioPlatform_reqFunc[5:4]) 2'd0, 2'd1, 2'd2: - IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_ETC___d481 = + IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d477 = mmioPlatform_reqFunc; 2'd3: - IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_ETC___d481 = + IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d477 = { 2'd3, mmioPlatform_reqFunc[3:0] }; endcase end @@ -7489,15 +7475,15 @@ module mkProc(CLK, begin case (mmioPlatform_instSel) 1'd0: - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d991 = + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d987 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:0]; 1'd1: - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d991 = + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d987 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:32]; endcase end always@(mmioPlatform_reqFunc or - IF_IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4__ETC___d559 or + IF_IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4__ETC___d555 or core_0$RDY_mmioToPlatform_pRs_enq) begin case (mmioPlatform_reqFunc[5:4]) @@ -7505,11 +7491,11 @@ module mkProc(CLK, CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q18 = core_0$RDY_mmioToPlatform_pRs_enq; default: CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q18 = - IF_IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4__ETC___d559; + IF_IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4__ETC___d555; endcase end always@(mmioPlatform_reqFunc or - IF_mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioP_ETC___d625 or + IF_mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioP_ETC___d621 or core_0$RDY_mmioToPlatform_pRs_enq) begin case (mmioPlatform_reqFunc[5:4]) @@ -7517,315 +7503,315 @@ module mkProc(CLK, CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q19 = core_0$RDY_mmioToPlatform_pRs_enq; default: CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q19 = - IF_mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioP_ETC___d625; + IF_mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioP_ETC___d621; endcase end always@(srcRR_0 or propDstIdx_0_dummy2_1$Q_OUT or - IF_propDstIdx_0_lat_0_whas__013_THEN_propDstId_ETC___d1016 or + IF_propDstIdx_0_lat_0_whas__009_THEN_propDstId_ETC___d1012 or propDstIdx_1_dummy2_1$Q_OUT or - IF_propDstIdx_1_lat_0_whas__020_THEN_propDstId_ETC___d1023) + IF_propDstIdx_1_lat_0_whas__016_THEN_propDstId_ETC___d1019) begin case (srcRR_0) 1'd0: - SEL_ARR_propDstIdx_0_dummy2_1_read__066_AND_IF_ETC___d1097 = + SEL_ARR_propDstIdx_0_dummy2_1_read__062_AND_IF_ETC___d1093 = propDstIdx_0_dummy2_1$Q_OUT && - IF_propDstIdx_0_lat_0_whas__013_THEN_propDstId_ETC___d1016; + IF_propDstIdx_0_lat_0_whas__009_THEN_propDstId_ETC___d1012; 1'd1: - SEL_ARR_propDstIdx_0_dummy2_1_read__066_AND_IF_ETC___d1097 = + SEL_ARR_propDstIdx_0_dummy2_1_read__062_AND_IF_ETC___d1093 = propDstIdx_1_dummy2_1$Q_OUT && - IF_propDstIdx_1_lat_0_whas__020_THEN_propDstId_ETC___d1023; + IF_propDstIdx_1_lat_0_whas__016_THEN_propDstId_ETC___d1019; endcase end always@(srcRR_1_0 or propDstIdx_1_0_dummy2_1$Q_OUT or - IF_propDstIdx_1_0_lat_0_whas__187_THEN_propDst_ETC___d1190 or + IF_propDstIdx_1_0_lat_0_whas__183_THEN_propDst_ETC___d1186 or propDstIdx_1_1_dummy2_1$Q_OUT or - IF_propDstIdx_1_1_lat_0_whas__194_THEN_propDst_ETC___d1197) + IF_propDstIdx_1_1_lat_0_whas__190_THEN_propDst_ETC___d1193) begin case (srcRR_1_0) 1'd0: - SEL_ARR_propDstIdx_1_0_dummy2_1_read__330_AND__ETC___d1371 = + SEL_ARR_propDstIdx_1_0_dummy2_1_read__326_AND__ETC___d1367 = propDstIdx_1_0_dummy2_1$Q_OUT && - IF_propDstIdx_1_0_lat_0_whas__187_THEN_propDst_ETC___d1190; + IF_propDstIdx_1_0_lat_0_whas__183_THEN_propDst_ETC___d1186; 1'd1: - SEL_ARR_propDstIdx_1_0_dummy2_1_read__330_AND__ETC___d1371 = + SEL_ARR_propDstIdx_1_0_dummy2_1_read__326_AND__ETC___d1367 = propDstIdx_1_1_dummy2_1$Q_OUT && - IF_propDstIdx_1_1_lat_0_whas__194_THEN_propDst_ETC___d1197; + IF_propDstIdx_1_1_lat_0_whas__190_THEN_propDst_ETC___d1193; endcase end - always@(x__h61509 or n__read_id__h61695 or n__read_id__h61780) + always@(x__h61493 or n__read_id__h61679 or n__read_id__h61764) begin - case (x__h61509) - 1'd0: x__h61823 = n__read_id__h61695; - 1'd1: x__h61823 = n__read_id__h61780; + case (x__h61493) + 1'd0: x__h61807 = n__read_id__h61679; + 1'd1: x__h61807 = n__read_id__h61764; endcase end - always@(x__h61509 or n__read_child__h61696 or n__read_child__h61781) + always@(x__h61493 or n__read_child__h61680 or n__read_child__h61765) begin - case (x__h61509) - 1'd0: x__h61830 = n__read_child__h61696; - 1'd1: x__h61830 = n__read_child__h61781; + case (x__h61493) + 1'd0: x__h61814 = n__read_child__h61680; + 1'd1: x__h61814 = n__read_child__h61765; endcase end - always@(x__h61509 or - propDstData_0_dummy2_1_read__104_AND_IF_propDs_ETC___d1140 or - propDstData_1_dummy2_1_read__109_AND_IF_propDs_ETC___d1144) + always@(x__h61493 or + propDstData_0_dummy2_1_read__100_AND_IF_propDs_ETC___d1136 or + propDstData_1_dummy2_1_read__105_AND_IF_propDs_ETC___d1140) begin - case (x__h61509) + case (x__h61493) 1'd0: - CASE_x1509_0_propDstData_0_dummy2_1_read__104__ETC__q20 = - propDstData_0_dummy2_1_read__104_AND_IF_propDs_ETC___d1140; + CASE_x1493_0_propDstData_0_dummy2_1_read__100__ETC__q20 = + propDstData_0_dummy2_1_read__100_AND_IF_propDs_ETC___d1136; 1'd1: - CASE_x1509_0_propDstData_0_dummy2_1_read__104__ETC__q20 = - propDstData_1_dummy2_1_read__109_AND_IF_propDs_ETC___d1144; + CASE_x1493_0_propDstData_0_dummy2_1_read__100__ETC__q20 = + propDstData_1_dummy2_1_read__105_AND_IF_propDs_ETC___d1140; endcase end - always@(x__h61509 or - IF_propDstData_0_dummy2_1_read__104_THEN_IF_pr_ETC___d1120 or - IF_propDstData_1_dummy2_1_read__109_THEN_IF_pr_ETC___d1124) + always@(x__h61493 or + IF_propDstData_0_dummy2_1_read__100_THEN_IF_pr_ETC___d1116 or + IF_propDstData_1_dummy2_1_read__105_THEN_IF_pr_ETC___d1120) begin - case (x__h61509) + case (x__h61493) 1'd0: - CASE_x1509_0_IF_propDstData_0_dummy2_1_read__1_ETC__q21 = - IF_propDstData_0_dummy2_1_read__104_THEN_IF_pr_ETC___d1120; + CASE_x1493_0_IF_propDstData_0_dummy2_1_read__1_ETC__q21 = + IF_propDstData_0_dummy2_1_read__100_THEN_IF_pr_ETC___d1116; 1'd1: - CASE_x1509_0_IF_propDstData_0_dummy2_1_read__1_ETC__q21 = - IF_propDstData_1_dummy2_1_read__109_THEN_IF_pr_ETC___d1124; + CASE_x1493_0_IF_propDstData_0_dummy2_1_read__1_ETC__q21 = + IF_propDstData_1_dummy2_1_read__105_THEN_IF_pr_ETC___d1120; endcase end - always@(x__h61509 or - IF_propDstData_0_dummy2_1_read__104_THEN_IF_pr_ETC___d1130 or - IF_propDstData_1_dummy2_1_read__109_THEN_IF_pr_ETC___d1134) + always@(x__h61493 or + IF_propDstData_0_dummy2_1_read__100_THEN_IF_pr_ETC___d1126 or + IF_propDstData_1_dummy2_1_read__105_THEN_IF_pr_ETC___d1130) begin - case (x__h61509) + case (x__h61493) 1'd0: - CASE_x1509_0_IF_propDstData_0_dummy2_1_read__1_ETC__q22 = - IF_propDstData_0_dummy2_1_read__104_THEN_IF_pr_ETC___d1130; + CASE_x1493_0_IF_propDstData_0_dummy2_1_read__1_ETC__q22 = + IF_propDstData_0_dummy2_1_read__100_THEN_IF_pr_ETC___d1126; 1'd1: - CASE_x1509_0_IF_propDstData_0_dummy2_1_read__1_ETC__q22 = - IF_propDstData_1_dummy2_1_read__109_THEN_IF_pr_ETC___d1134; + CASE_x1493_0_IF_propDstData_0_dummy2_1_read__1_ETC__q22 = + IF_propDstData_1_dummy2_1_read__105_THEN_IF_pr_ETC___d1130; endcase end - always@(x__h61509 or n__read_addr__h61691 or n__read_addr__h61776) + always@(x__h61493 or n__read_addr__h61675 or n__read_addr__h61760) begin - case (x__h61509) + case (x__h61493) 1'd0: - CASE_x1509_0_n__read_addr1691_1_n__read_addr17_ETC__q23 = - n__read_addr__h61691; + CASE_x1493_0_n__read_addr1675_1_n__read_addr17_ETC__q23 = + n__read_addr__h61675; 1'd1: - CASE_x1509_0_n__read_addr1691_1_n__read_addr17_ETC__q23 = - n__read_addr__h61776; + CASE_x1493_0_n__read_addr1675_1_n__read_addr17_ETC__q23 = + n__read_addr__h61760; endcase end - always@(x__h80316 or + always@(x__h80300 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h80316) + case (x__h80300) 1'd0: - CASE_x0316_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24 = + CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[512:449] : propDstData_1_0_rl[512:449]; 1'd1: - CASE_x0316_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24 = + CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[512:449] : propDstData_1_1_rl[512:449]; endcase end - always@(x__h80316 or + always@(x__h80300 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h80316) + case (x__h80300) 1'd0: - CASE_x0316_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 = + CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[448:385] : propDstData_1_0_rl[448:385]; 1'd1: - CASE_x0316_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 = + CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[448:385] : propDstData_1_1_rl[448:385]; endcase end - always@(x__h80316 or n__read_child__h80497 or n__read_child__h80576) + always@(x__h80300 or n__read_child__h80481 or n__read_child__h80560) begin - case (x__h80316) - 1'd0: x__h82732 = n__read_child__h80497; - 1'd1: x__h82732 = n__read_child__h80576; + case (x__h80300) + 1'd0: x__h82716 = n__read_child__h80481; + 1'd1: x__h82716 = n__read_child__h80560; endcase end - always@(x__h80316 or + always@(x__h80300 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h80316) + case (x__h80300) 1'd0: - CASE_x0316_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26 = + CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[384:321] : propDstData_1_0_rl[384:321]; 1'd1: - CASE_x0316_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26 = + CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[384:321] : propDstData_1_1_rl[384:321]; endcase end - always@(x__h80316 or + always@(x__h80300 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h80316) + case (x__h80300) 1'd0: - CASE_x0316_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 = + CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[320:257] : propDstData_1_0_rl[320:257]; 1'd1: - CASE_x0316_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 = + CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[320:257] : propDstData_1_1_rl[320:257]; endcase end - always@(x__h80316 or + always@(x__h80300 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h80316) + case (x__h80300) 1'd0: - CASE_x0316_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28 = + CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[256:193] : propDstData_1_0_rl[256:193]; 1'd1: - CASE_x0316_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28 = + CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[256:193] : propDstData_1_1_rl[256:193]; endcase end - always@(x__h80316 or + always@(x__h80300 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h80316) + case (x__h80300) 1'd0: - CASE_x0316_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 = + CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[192:129] : propDstData_1_0_rl[192:129]; 1'd1: - CASE_x0316_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 = + CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[192:129] : propDstData_1_1_rl[192:129]; endcase end - always@(x__h80316 or + always@(x__h80300 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h80316) + case (x__h80300) 1'd0: - CASE_x0316_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30 = + CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[128:65] : propDstData_1_0_rl[128:65]; 1'd1: - CASE_x0316_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30 = + CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[128:65] : propDstData_1_1_rl[128:65]; endcase end - always@(x__h80316 or + always@(x__h80300 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h80316) + case (x__h80300) 1'd0: - CASE_x0316_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 = + CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[64:1] : propDstData_1_0_rl[64:1]; 1'd1: - CASE_x0316_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 = + CASE_x0300_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[64:1] : propDstData_1_1_rl[64:1]; endcase end - always@(x__h80316 or + always@(x__h80300 or propDstData_1_0_dummy2_1$Q_OUT or - IF_propDstData_1_0_lat_0_whas__202_THEN_propDs_ETC___d1212 or + IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1208 or propDstData_1_1_dummy2_1$Q_OUT or - IF_propDstData_1_1_lat_0_whas__240_THEN_propDs_ETC___d1250) + IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1246) begin - case (x__h80316) + case (x__h80300) 1'd0: - CASE_x0316_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32 = + CASE_x0300_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32 = propDstData_1_0_dummy2_1$Q_OUT ? - IF_propDstData_1_0_lat_0_whas__202_THEN_propDs_ETC___d1212 : + IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1208 : 2'd0; 1'd1: - CASE_x0316_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32 = + CASE_x0300_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32 = propDstData_1_1_dummy2_1$Q_OUT ? - IF_propDstData_1_1_lat_0_whas__240_THEN_propDs_ETC___d1250 : + IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1246 : 2'd0; endcase end - always@(x__h80316 or - NOT_propDstData_1_0_dummy2_1_read__378_389_OR__ETC___d1390 or - NOT_propDstData_1_1_dummy2_1_read__380_391_OR__ETC___d1392) + always@(x__h80300 or + NOT_propDstData_1_0_dummy2_1_read__374_385_OR__ETC___d1386 or + NOT_propDstData_1_1_dummy2_1_read__376_387_OR__ETC___d1388) begin - case (x__h80316) + case (x__h80300) 1'd0: - CASE_x0316_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33 = - NOT_propDstData_1_0_dummy2_1_read__378_389_OR__ETC___d1390; + CASE_x0300_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33 = + NOT_propDstData_1_0_dummy2_1_read__374_385_OR__ETC___d1386; 1'd1: - CASE_x0316_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33 = - NOT_propDstData_1_1_dummy2_1_read__380_391_OR__ETC___d1392; + CASE_x0300_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33 = + NOT_propDstData_1_1_dummy2_1_read__376_387_OR__ETC___d1388; endcase end - always@(x__h80316 or n__read_addr__h80494 or n__read_addr__h80573) + always@(x__h80300 or n__read_addr__h80478 or n__read_addr__h80557) begin - case (x__h80316) + case (x__h80300) 1'd0: - CASE_x0316_0_n__read_addr0494_1_n__read_addr05_ETC__q34 = - n__read_addr__h80494; + CASE_x0300_0_n__read_addr0478_1_n__read_addr05_ETC__q34 = + n__read_addr__h80478; 1'd1: - CASE_x0316_0_n__read_addr0494_1_n__read_addr05_ETC__q34 = - n__read_addr__h80573; + CASE_x0300_0_n__read_addr0478_1_n__read_addr05_ETC__q34 = + n__read_addr__h80557; endcase end @@ -7876,7 +7862,7 @@ module mkProc(CLK, mmioPlatform_fromHostQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0; mmioPlatform_mtime <= `BSV_ASSIGNMENT_DELAY 64'd0; mmioPlatform_mtimecmp_0 <= `BSV_ASSIGNMENT_DELAY 64'd0; - mmioPlatform_mtip_0 <= `BSV_ASSIGNMENT_DELAY 1'd0; + mmioPlatform_mtip_0 <= `BSV_ASSIGNMENT_DELAY 1'd1; mmioPlatform_state <= `BSV_ASSIGNMENT_DELAY 2'd0; mmioPlatform_toHostAddr <= `BSV_ASSIGNMENT_DELAY 61'd0; mmioPlatform_toHostQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0; @@ -8241,36 +8227,36 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (EN_start) begin - v__h163598 = $stime; + v__h163582 = $stime; #0; end - v__h163592 = v__h163598 / 32'd10; + v__h163576 = v__h163582 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_start) $display("%0d: %m.method start: startpc %0h, tohostAddr %0h, fromhostAddr %0h", - v__h163592, + v__h163576, start_startpc, start_tohostAddr, start_fromhostAddr); if (RST_N != `BSV_RESET_VALUE) - if (NOT_enqDst_0_dummy2_0_read__087_088_OR_NOT_enq_ETC___d1103 && - IF_SEL_ARR_propDstIdx_0_dummy2_1_read__066_AND_ETC___d1173 && - NOT_propDstIdx_0_dummy2_1_read__066_067_OR_IF__ETC___d1100) + if (NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 && + IF_SEL_ARR_propDstIdx_0_dummy2_1_read__062_AND_ETC___d1169 && + NOT_propDstIdx_0_dummy2_1_read__062_063_OR_IF__ETC___d1096) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) - if (NOT_enqDst_0_dummy2_0_read__087_088_OR_NOT_enq_ETC___d1103 && - x__h61509 && + if (NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 && + x__h61493 && (!propDstIdx_1_dummy2_1$Q_OUT || !CAN_FIRE_RL_srcPropose_1 && !propDstIdx_1_rl)) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) - if (NOT_enqDst_1_0_dummy2_0_read__361_362_OR_NOT_e_ETC___d1377 && - IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__330_A_ETC___d1475 && - NOT_propDstIdx_1_0_dummy2_1_read__330_331_OR_I_ETC___d1374) + if (NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 && + IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__326_A_ETC___d1471 && + NOT_propDstIdx_1_0_dummy2_1_read__326_327_OR_I_ETC___d1370) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) - if (NOT_enqDst_1_0_dummy2_0_read__361_362_OR_NOT_e_ETC___d1377 && - x__h80316 && + if (NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 && + x__h80300 && (!propDstIdx_1_1_dummy2_1$Q_OUT || !CAN_FIRE_RL_srcPropose_3 && !propDstIdx_1_1_rl)) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); @@ -8280,14 +8266,14 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost) begin - v__h163134 = $stime; + v__h163118 = $stime; #0; end - v__h163128 = v__h163134 / 32'd10; + v__h163112 = v__h163118 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost) $display("%0d: mmioPlatform.rl_tohost: 0x%0x (= %0d)", - v__h163128, + v__h163112, mmioPlatform_toHostQ_data_0, mmioPlatform_toHostQ_data_0); if (RST_N != `BSV_RESET_VALUE) @@ -8297,7 +8283,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0 && mmioPlatform_toHostQ_data_0[63:1] != 63'd0) - $display("FAIL %0d", failed_testnum__h163177); + $display("FAIL %0d", failed_testnum__h163161); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0) $finish(32'd0); @@ -9875,13 +9861,13 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && mmioPlatform_fromHostQ_empty && - x__h43017 != 64'd0) + x__h43001 != 64'd0) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && !mmioPlatform_fromHostQ_empty && - x__h40951 != 64'd0) + x__h40935 != 64'd0) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && @@ -9890,7 +9876,7 @@ module mkProc(CLK, mmioPlatform_reqFunc[5:4] != 2'd1) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) - if (NOT_llc_mem_server_enqDst_0_dummy2_0_read__711_ETC___d1718 && + if (NOT_llc_mem_server_enqDst_0_dummy2_0_read__707_ETC___d1714 && !CAN_FIRE_RL_llc_mem_server_srcPropose && !llc_mem_server_propDstIdx_0_rl) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); @@ -9899,85 +9885,85 @@ module mkProc(CLK, $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) begin - v__h135091 = $stime; + v__h135075 = $stime; #0; end - v__h135085 = v__h135091 / 32'd10; + v__h135069 = v__h135075 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsps: beat %0d ", - v__h135085, + v__h135069, llc_axi4_adapter_rg_rd_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[2:1]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801 && + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797 && llc_axi4_adapter_master_xactor_rg_rd_data[0]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801 && + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797 && !llc_axi4_adapter_master_xactor_rg_rd_data[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) begin - v__h135258 = $stime; + v__h135242 = $stime; #0; end - v__h135252 = v__h135258 / 32'd10; + v__h135236 = v__h135242 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsp: fabric response error; exit", - v__h135252); + v__h135236); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) @@ -10039,135 +10025,135 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(" Response to LLC: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("MemRsMsg { ", "data: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "child: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "id: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("LdMemRqId { ", "refill: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801 && + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797 && llc_axi4_adapter_f_pending_reads$D_OUT[4]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801 && + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797 && !llc_axi4_adapter_f_pending_reads$D_OUT[4]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "mshrIdx: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", llc_axi4_adapter_f_pending_reads$D_OUT[3:0], " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(" }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_wr_req_beat == 3'd0) begin - v__h137361 = $stime; + v__h137345 = $stime; #0; end - v__h137355 = v__h137361 / 32'd10; + v__h137339 = v__h137345 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_wr_req_beat == 3'd0) $display("%d: LLC_AXI4_Adapter.rl_handle_write_req: Wb request from LLC to memory:", - v__h137355); + v__h137339); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && @@ -11365,169 +11351,169 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) begin - v__h154705 = $stime; + v__h154689 = $stime; #0; end - v__h154699 = v__h154705 / 32'd10; + v__h154683 = v__h154689 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h154699); + $display("%0d: ERROR: CreditCounter: overflow", v__h154683); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) $finish(32'd1); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(" To fabric: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("AXI4_Wr_Addr { ", "awid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "awaddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) - $write("'h%h", mem_req_wr_addr_awaddr__h148616); + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + $write("'h%h", mem_req_wr_addr_awaddr__h148600); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "awlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 8'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "awsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 3'b011); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "awburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 2'b01); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "awlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 1'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "awcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 4'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "awprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 3'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "awqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "awregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "awuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 1'h0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("AXI4_Wr_Data { ", "wdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) - $write("'h%h", data64__h148531); + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + $write("'h%h", data64__h148515); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "wstrb: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) - $write("'h%h", strb8__h148532); + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + $write("'h%h", strb8__h148516); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "wlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "wuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 1'h0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_rd_req_beat == 3'd0) begin - v__h134472 = $stime; + v__h134456 = $stime; #0; end - v__h134466 = v__h134472 / 32'd10; + v__h134450 = v__h134456 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_rd_req_beat == 3'd0) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_req: Ld request from LLC to memory: beat %0d", - v__h134466, + v__h134450, llc_axi4_adapter_rg_rd_req_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && @@ -11598,159 +11584,159 @@ module mkProc(CLK, $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("AXI4_Rd_Addr { ", "arid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "araddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) - $write("'h%h", mem_req_rd_addr_araddr__h134692); + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) + $write("'h%h", mem_req_rd_addr_araddr__h134676); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "arlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 8'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "arsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 3'b011); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "arburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 2'b01); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "arlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 1'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "arcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 4'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "arprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 3'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "arqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "arregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "aruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 1'h0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) begin - v__h161399 = $stime; + v__h161383 = $stime; #0; end - v__h161393 = v__h161399 / 32'd10; + v__h161377 = v__h161383 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $display("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: beat %0d ", - v__h161393, + v__h161377, llc_axi4_adapter_rg_wr_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", llc_axi4_adapter_master_xactor_rg_wr_resp[5:2]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", llc_axi4_adapter_master_xactor_rg_wr_resp[1:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__784_U_ETC___d1801) + NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) begin - v__h161907 = $stime; + v__h161891 = $stime; #0; end - v__h161901 = v__h161907 / 32'd10; + v__h161885 = v__h161891 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) $display("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: fabric response error: exit", - v__h161901); + v__h161885); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkTrace_Data2_to_Trace_Data.v b/src_SSITH_P3/Verilog_RTL_sim/mkTrace_Data2_to_Trace_Data.v index 52516d4..e61f0a2 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkTrace_Data2_to_Trace_Data.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkTrace_Data2_to_Trace_Data.v @@ -77,13 +77,13 @@ module mkTrace_Data2_to_Trace_Data(CLK, // remaining internal signals reg [63 : 0] x1_avValue_pc__h3546, x1_avValue_word1__h3550; - reg [11 : 0] CASE_in_put_BITS_475_TO_464_1_in_put_BITS_475__ETC__q2, + reg [11 : 0] CASE_in_put_BITS_475_TO_464_1_in_put_BITS_475__ETC__q1, csr_addr__h5310; - reg [4 : 0] CASE_f_inD_OUT_BITS_624_TO_620_14_5_15_5_16_5_ETC__q1, + reg [4 : 0] CASE_f_inD_OUT_BITS_624_TO_620_14_5_15_5_16_5_ETC__q5, x1_avValue_rd__h3549; - reg [3 : 0] CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q3, - CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q4; - reg [1 : 0] CASE_in_put_BITS_393_TO_392_0_in_put_BITS_393__ETC__q5; + reg [3 : 0] CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q2, + CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q3; + reg [1 : 0] CASE_in_put_BITS_393_TO_392_0_in_put_BITS_393__ETC__q4; wire [63 : 0] td_word2__h3589, td_word2__h3740, td_word3__h3590, @@ -167,13 +167,13 @@ module mkTrace_Data2_to_Trace_Data(CLK, // submodule f_in assign f_in$D_IN = { in_put[861:476], - CASE_in_put_BITS_475_TO_464_1_in_put_BITS_475__ETC__q2, + CASE_in_put_BITS_475_TO_464_1_in_put_BITS_475__ETC__q1, in_put[463:462], in_put[462] ? - CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q3 : - CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q4, + CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q2 : + CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q3, in_put[457:394], - CASE_in_put_BITS_393_TO_392_0_in_put_BITS_393__ETC__q5, + CASE_in_put_BITS_393_TO_392_0_in_put_BITS_393__ETC__q4, in_put[391:0] } ; assign f_in$ENQ = EN_in_put ; assign f_in$DEQ = CAN_FIRE_RL_rl_td2_to_td ; @@ -217,7 +217,7 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[393:392] != 2'd1 && f_in$D_OUT[624:620] == 5'd13) ? 5'd16 : - CASE_f_inD_OUT_BITS_624_TO_620_14_5_15_5_16_5_ETC__q1)))))))))), + CASE_f_inD_OUT_BITS_624_TO_620_14_5_15_5_16_5_ETC__q5)))))))))), x__h4855, f_in$D_OUT[626:625] == 2'b11, f_in$D_OUT[656:625], @@ -227,7 +227,7 @@ module mkTrace_Data2_to_Trace_Data(CLK, x__h5458, x__h5890, x__h5906 } ; - assign f_out$ENQ = f_in$EMPTY_N && f_out$FULL_N ; + assign f_out$ENQ = CAN_FIRE_RL_rl_td2_to_td ; assign f_out$DEQ = EN_out_get ; assign f_out$CLR = 1'b0 ; @@ -466,22 +466,6 @@ module mkTrace_Data2_to_Trace_Data(CLK, default: csr_addr__h5310 = 12'd2303; endcase end - always@(f_in$D_OUT) - begin - case (f_in$D_OUT[624:620]) - 5'd14, 5'd15, 5'd16, 5'd17, 5'd18: - CASE_f_inD_OUT_BITS_624_TO_620_14_5_15_5_16_5_ETC__q1 = 5'd5; - 5'd19, 5'd20: - CASE_f_inD_OUT_BITS_624_TO_620_14_5_15_5_16_5_ETC__q1 = 5'd15; - default: CASE_f_inD_OUT_BITS_624_TO_620_14_5_15_5_16_5_ETC__q1 = - (f_in$D_OUT[393:392] == 2'd1 && - (f_in$D_OUT[624:620] == 5'd2 || - f_in$D_OUT[624:620] == 5'd6 || - f_in$D_OUT[624:620] == 5'd7)) ? - 5'd13 : - 5'd5; - endcase - end always@(in_put) begin case (in_put[475:464]) @@ -529,9 +513,9 @@ module mkTrace_Data2_to_Trace_Data(CLK, 12'd3858, 12'd3859, 12'd3860: - CASE_in_put_BITS_475_TO_464_1_in_put_BITS_475__ETC__q2 = + CASE_in_put_BITS_475_TO_464_1_in_put_BITS_475__ETC__q1 = in_put[475:464]; - default: CASE_in_put_BITS_475_TO_464_1_in_put_BITS_475__ETC__q2 = + default: CASE_in_put_BITS_475_TO_464_1_in_put_BITS_475__ETC__q1 = 12'd2303; endcase end @@ -539,9 +523,9 @@ module mkTrace_Data2_to_Trace_Data(CLK, begin case (in_put[461:458]) 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: - CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q3 = + CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q2 = in_put[461:458]; - default: CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q3 = 4'd15; + default: CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q2 = 4'd15; endcase end always@(in_put) @@ -560,18 +544,34 @@ module mkTrace_Data2_to_Trace_Data(CLK, 4'd11, 4'd12, 4'd13: - CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q4 = + CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q3 = in_put[461:458]; - default: CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q4 = 4'd15; + default: CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q3 = 4'd15; endcase end always@(in_put) begin case (in_put[393:392]) 2'd0, 2'd1: - CASE_in_put_BITS_393_TO_392_0_in_put_BITS_393__ETC__q5 = + CASE_in_put_BITS_393_TO_392_0_in_put_BITS_393__ETC__q4 = in_put[393:392]; - default: CASE_in_put_BITS_393_TO_392_0_in_put_BITS_393__ETC__q5 = 2'd2; + default: CASE_in_put_BITS_393_TO_392_0_in_put_BITS_393__ETC__q4 = 2'd2; + endcase + end + always@(f_in$D_OUT) + begin + case (f_in$D_OUT[624:620]) + 5'd14, 5'd15, 5'd16, 5'd17, 5'd18: + CASE_f_inD_OUT_BITS_624_TO_620_14_5_15_5_16_5_ETC__q5 = 5'd5; + 5'd19, 5'd20: + CASE_f_inD_OUT_BITS_624_TO_620_14_5_15_5_16_5_ETC__q5 = 5'd15; + default: CASE_f_inD_OUT_BITS_624_TO_620_14_5_15_5_16_5_ETC__q5 = + (f_in$D_OUT[393:392] == 2'd1 && + (f_in$D_OUT[624:620] == 5'd2 || + f_in$D_OUT[624:620] == 5'd6 || + f_in$D_OUT[624:620] == 5'd7)) ? + 5'd13 : + 5'd5; endcase end diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkCore.v b/src_SSITH_P3/xilinx_ip/hdl/mkCore.v index 7bcc820..5e6fe7f 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkCore.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkCore.v @@ -4517,13 +4517,13 @@ module mkCore(CLK, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2875, addr__h290070, curData__h192919, - data_out__h738236, - data_warl_xformed__h723335, + data_out__h738339, + data_warl_xformed__h723438, rVal1__h609054, rVal1__h633783, - trap_val__h711388, + trap_val__h711491, x__h197129, - x__h723943; + x__h724046; reg [51 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q19, @@ -4604,7 +4604,7 @@ module mkCore(CLK, CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q298, CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q294, IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d12883, - IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13589; + IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13599; reg [15 : 0] SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359, SEL_ARR_mmio_dataRespQ_data_0_101_BITS_15_TO_0_ETC___d1407; reg [11 : 0] CASE_commitStage_f_rob_dataD_OUT_BITS_180_TO__ETC__q279, @@ -4694,9 +4694,9 @@ module mkCore(CLK, reg [5 : 0] CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q280, CASE_mmio_cRqQ_data_0_BITS_77_TO_76_0_mmio_cRq_ETC__q9, CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q276, - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988; - reg [4 : 0] IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14133, - IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14266; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998; + reg [4 : 0] IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14143, + IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14276; reg [3 : 0] CASE_checkForException_3008_BITS_3_TO_0_0_chec_ETC__q234, CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q250, CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q251, @@ -4710,11 +4710,11 @@ module mkCore(CLK, CASE_v_f_to_TV_0D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q7, CASE_v_f_to_TV_1D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q2, CASE_v_f_to_TV_1D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q3, - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14136, + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14146, IF_fetchStage_pipelines_0_first__2757_BIT_68_2_ETC___d13130, - IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14267, - i__h710364, - i__h710524; + IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14277, + i__h710467, + i__h710627; reg [2 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q284, CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q230, CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q281, @@ -4763,7 +4763,7 @@ module mkCore(CLK, CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q243, CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q244, CASE_fetchStage_pipelines_0_canDeq__2755_AND_N_ETC__q241, - CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q240, + CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q239, CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q237, CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q238, CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q242, @@ -4806,7 +4806,7 @@ module mkCore(CLK, CASE_guard91798_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91, CASE_guard91798_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90, CASE_guard93571_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145, - CASE_k70531_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239, + CASE_k70634_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q240, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6446, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6459, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6463, @@ -4845,31 +4845,31 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d8396, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d8409, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d8428, - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13466, - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13524, - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14127, - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14130, - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13470, - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13494, - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13529, - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13855, - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13877, - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13895, - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13950, - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13952, - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13966, - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13973, - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d14049, - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d14061, - IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14264, - IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14265, - IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13907, - IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14046, - IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14073, - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__344_ETC___d13487, - SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__275_ETC___d14007, - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3443_co_ETC___d13453, - SEL_ARR_fetchStage_pipelines_0_canDeq__2755_AN_ETC___d13777; + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13476, + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13534, + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14137, + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14140, + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13480, + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13504, + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13539, + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13865, + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13887, + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13905, + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13960, + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13962, + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13976, + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13983, + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d14059, + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d14071, + IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14274, + IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14275, + IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13917, + IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14056, + IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14083, + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__345_ETC___d13497, + SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__275_ETC___d14017, + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463, + SEL_ARR_fetchStage_pipelines_0_canDeq__2755_AN_ETC___d13787; wire [581 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3247; wire [569 : 0] IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2510, IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2521, @@ -4878,24 +4878,25 @@ module mkCore(CLK, wire [517 : 0] SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2945; wire [511 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2208, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2938, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16071; - wire [463 : 0] commitStage_f_rob_data_first__4760_BIT_167_485_ETC___d14932; - wire [457 : 0] rob_deqPort_0_deq_data__4344_BITS_161_TO_98_43_ETC___d15316; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16081; + wire [463 : 0] commitStage_f_rob_data_first__4770_BIT_167_486_ETC___d14942; + wire [457 : 0] rob_deqPort_0_deq_data__4354_BITS_161_TO_98_43_ETC___d15326; wire [447 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2008; - wire [393 : 0] IF_commitStage_f_rob_data_first__4760_BITS_97__ETC___d14931; + wire [393 : 0] IF_commitStage_f_rob_data_first__4770_BITS_97__ETC___d14941; wire [383 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2203, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2929, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16062; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16072; wire [321 : 0] basicExec___d11943, basicExec___d12617; wire [319 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2003; wire [255 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2198, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2920, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16053; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16063; wire [191 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1998; + wire [181 : 0] fetchStage_pipelines_0_first__2757_BIT_173_288_ETC___d13411; wire [144 : 0] coreFix_memExe_lsq_getOrigBE_coreFix_memExe_re_ETC___d1706; wire [68 : 0] execFpuSimple___d11056; wire [65 : 0] IF_IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_NOT_ETC___d627, - IF_rob_deqPort_0_deq_data__4344_BITS_97_TO_96__ETC___d14517; + IF_rob_deqPort_0_deq_data__4354_BITS_97_TO_96__ETC___d14527; wire [64 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2570; wire [63 : 0] IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9173, IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12448, @@ -4927,7 +4928,7 @@ module mkCore(CLK, IF_coreFix_memExe_lsq_firstLd__277_BIT_96_342__ETC___d1378, IF_coreFix_memExe_lsq_firstLd__277_BIT_96_342__ETC___d1425, IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8, - IF_rob_deqPort_0_deq_data__4344_BITS_329_TO_32_ETC___d15196, + IF_rob_deqPort_0_deq_data__4354_BITS_329_TO_32_ETC___d15206, _theResult___fst__h603374, _theResult___snd__h603375, a___1__h603093, @@ -4937,9 +4938,9 @@ module mkCore(CLK, b___1__h603094, b___1__h603424, b__h602953, - base__h713309, - base__h713329, - commitStage_rg_serial_num_4333_PLUS_IF_rob_deq_ETC___d15459, + base__h713412, + base__h713432, + commitStage_rg_serial_num_4343_PLUS_IF_rob_deq_ETC___d15469, data___1__h475012, data___1__h475820, data__h475286, @@ -4959,10 +4960,10 @@ module mkCore(CLK, n__read__h611359, n__read__h611550, n__read__h6761, - n__read__h727564, - new_mstatus___1__h726926, - next_pc__h723361, - pc__h713293, + n__read__h727667, + new_mstatus___1__h727029, + next_pc__h723464, + pc__h713396, q___1__h475885, rVal1__h481765, rVal2__h481766, @@ -4984,11 +4985,11 @@ module mkCore(CLK, sip_csr__read__h610020, sstatus_csr__read__h609576, stvec_csr__read__h609689, - trap_val__h710350, + trap_val__h710453, upd__h3994, upd__h5311, upd__h6875, - upd__h727675, + upd__h727778, v__h607938, v__h632822, x__h153734, @@ -5011,18 +5012,18 @@ module mkCore(CLK, x__h617236, x__h639745, x__h639746, - x__h703283, - x__h715551, - x__h715743, - x__h726917, - x__h727058, - x__h733638, + x__h703386, + x__h715654, + x__h715846, + x__h727020, + x__h727161, + x__h733741, x_addr__h314077, x_quotient__h475200, x_reg_ifc__read__h609485, x_remainder__h475201, - y__h731332, - y__h734147, + y__h731435, + y__h734250, y_avValue__h180567, y_avValue__h181173, y_avValue__h478810, @@ -5032,15 +5033,15 @@ module mkCore(CLK, y_avValue__h615060, y_avValue__h633575, y_avValue__h637580, - y_avValue_new_pc__h713085, - y_avValue_new_pc__h713271, - y_avValue_snd_snd_snd_snd_snd_fst__h731355, - y_avValue_snd_snd_snd_snd_snd_fst__h734208, - y_avValue_snd_snd_snd_snd_snd_fst__h734244, - y_avValue_snd_snd_snd_snd_snd_snd_snd__h733620; + y_avValue_new_pc__h713188, + y_avValue_new_pc__h713374, + y_avValue_snd_snd_snd_snd_snd_fst__h731458, + y_avValue_snd_snd_snd_snd_snd_fst__h734311, + y_avValue_snd_snd_snd_snd_snd_fst__h734347, + y_avValue_snd_snd_snd_snd_snd_snd_snd__h733723; wire [62 : 0] IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10652, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9882, - IF_csrf_prv_reg_read__2787_ULE_1_4701_AND_IF_c_ETC___d14925, + IF_csrf_prv_reg_read__2787_ULE_1_4711_AND_IF_c_ETC___d14935, r1__read__h613053, r1__read__h613457, r1__read__h613967, @@ -5378,7 +5379,7 @@ module mkCore(CLK, wire [50 : 0] r1__read__h613067, r1__read__h614244; wire [49 : 0] r1__read__h614353; wire [48 : 0] r1__read__h613069, r1__read__h614246, r1__read__h614355; - wire [47 : 0] r1__read_BITS_61_TO_14___h726985; + wire [47 : 0] r1__read_BITS_61_TO_14___h727088; wire [46 : 0] r1__read__h613071, r1__read__h614248; wire [45 : 0] r1__read__h613073, r1__read__h614250; wire [44 : 0] r1__read__h613075, r1__read__h614252; @@ -5386,8 +5387,8 @@ module mkCore(CLK, wire [42 : 0] r1__read__h614256; wire [41 : 0] r1__read__h614258; wire [40 : 0] r1__read__h614260; - wire [37 : 0] IF_fetchStage_pipelines_0_first__2757_BIT_160__ETC___d14139, - IF_fetchStage_pipelines_1_first__2766_BIT_160__ETC___d14270; + wire [37 : 0] IF_fetchStage_pipelines_0_first__2757_BIT_160__ETC___d14149, + IF_fetchStage_pipelines_1_first__2766_BIT_160__ETC___d14280; wire [31 : 0] IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q133, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q12, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q11, @@ -5402,11 +5403,11 @@ module mkCore(CLK, x__h429285, x__h76239, x_data__h66088, - x_data_imm__h677563, - x_data_imm__h693617; + x_data_imm__h677666, + x_data_imm__h693720; wire [29 : 0] r1__read__h613081, r1__read__h614264; wire [27 : 0] r1__read__h614266; - wire [24 : 0] NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14171, + wire [24 : 0] NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14181, sfd__h354292, sfd__h362874, sfd__h372058, @@ -5514,9 +5515,9 @@ module mkCore(CLK, pend_ints__h651121, y__h651660; wire [13 : 0] r1__read_BITS_13_TO_0___h651670; - wire [12 : 0] IF_rob_deqPort_0_deq_data__4344_BITS_329_TO_32_ETC___d15306, - fetchStage_pipelines_1_first__2766_BIT_173_359_ETC___d13681, - rob_deqPort_0_deq_data__4344_BIT_181_4419_CONC_ETC___d14510; + wire [12 : 0] IF_rob_deqPort_0_deq_data__4354_BITS_329_TO_32_ETC___d15316, + fetchStage_pipelines_1_first__2766_BIT_173_360_ETC___d13691, + rob_deqPort_0_deq_data__4354_BIT_181_4429_CONC_ETC___d14520; wire [11 : 0] IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10431, IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d8946, IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9661, @@ -5547,10 +5548,10 @@ module mkCore(CLK, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5946, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7338, csr_addr__h655332, - renaming_spec_bits__h686145, + renaming_spec_bits__h686248, result__h646700, result__h646751, - spec_bits__h689304, + spec_bits__h689407, w__h646695, x__h364471, x__h410168, @@ -5561,10 +5562,10 @@ module mkCore(CLK, x__h646699, x__h646750, y__h646729, - y__h689317, - y_avValue_fst__h682477, - y_avValue_fst__h682506, - y_avValue_fst__h682540; + y__h689420, + y_avValue_fst__h682580, + y_avValue_fst__h682609, + y_avValue_fst__h682643; wire [10 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10536, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10538, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9056, @@ -5849,11 +5850,11 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4478, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7262, IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2144, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16097, + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16107, x__h181702, - x__h713324; - wire [4 : 0] IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14311, - IF_rob_deqPort_0_canDeq__5338_THEN_IF_NOT_rob__ETC___d15665, + x__h713427; + wire [4 : 0] IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14321, + IF_rob_deqPort_0_canDeq__5348_THEN_IF_NOT_rob__ETC___d15675, _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5169, _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6561, _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7953, @@ -5870,24 +5871,24 @@ module mkCore(CLK, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6573, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7965, checkForException___d13008, - checkForException___d13703, - fflags__h734124, - old_fflags1__h733611, - po_fflags__h728848, - po_fflags__h731495, + checkForException___d13713, + fflags__h734227, + old_fflags1__h733714, + po_fflags__h728951, + po_fflags__h731598, r1__read__h614604, res_fflags__h337874, res_fflags__h383576, res_fflags__h429271, - rob_deqPort_0_deq_data__4344_BIT_166_4360_CONC_ETC___d14409, + rob_deqPort_0_deq_data__4354_BIT_166_4370_CONC_ETC___d14419, rs1__h655333, x__h153728, x__h157275, x__h160091, x__h287282, - y_avValue_fst__h730870, - y_avValue_fst__h734029, - y_avValue_fst__h734061; + y_avValue_fst__h730973, + y_avValue_fst__h734132, + y_avValue_fst__h734164; wire [3 : 0] IF_IF_coreFix_memExe_dTlb_procResp__714_BIT_18_ETC___d1851, IF_IF_coreFix_memExe_dTlb_procResp__714_BIT_18_ETC___d1853, IF_IF_coreFix_memExe_dTlb_procResp__714_BIT_18_ETC___d1855, @@ -5914,13 +5915,13 @@ module mkCore(CLK, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2836, IF_coreFix_memExe_dTlb_procResp__714_BITS_177__ETC___d1796, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1255, - cause_code__h710349, + cause_code__h710452, vm_mode_reg__read__h614207; wire [2 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2539, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2793, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1212, _theResult_____2__h296524, - dcsr_cause__h709868, + dcsr_cause__h709971, next_deqP___1__h296803, v__h295944, v__h296175, @@ -5928,7 +5929,7 @@ module mkCore(CLK, x_decodeInfo_frm__h655017; wire [1 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2789, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1208, - IF_rob_deqPort_0_canDeq__5338_THEN_IF_NOT_rob__ETC___d15684, + IF_rob_deqPort_0_canDeq__5348_THEN_IF_NOT_rob__ETC___d15694, IF_sfdin11103_BIT_4_THEN_2_ELSE_0__q139, IF_sfdin17657_BIT_33_THEN_2_ELSE_0__q74, IF_sfdin45586_BIT_33_THEN_2_ELSE_0__q99, @@ -5971,20 +5972,20 @@ module mkCore(CLK, guard__h571728, guard__h581040, guard__h590109, - prv__h735791, - prv__h735835, + prv__h735894, + prv__h735938, r1__read_BITS_13_TO_12___h655202, sbIdx__h157154, v__h603887, v__h603897, v__h604532, - x__h723465, - x__h734388, - x_prv__h713393, - x_prv__h723923, - y_avValue_snd_snd_snd_fst__h731345, - y_avValue_snd_snd_snd_fst__h734198, - y_avValue_snd_snd_snd_fst__h734234; + x__h723568, + x__h734491, + x_prv__h713496, + x_prv__h724026, + y_avValue_snd_snd_snd_fst__h731448, + y_avValue_snd_snd_snd_fst__h734301, + y_avValue_snd_snd_snd_fst__h734337; wire IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5069, IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5119, IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6461, @@ -6004,8 +6005,8 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9907, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9934, IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d13052, - IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d13761, - IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d13798, + IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d13771, + IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d13808, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10474, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10706, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10707, @@ -6060,11 +6061,11 @@ module mkCore(CLK, IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1629, IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2086, IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2103, - IF_NOT_fetchStage_pipelines_0_canDeq__2755_275_ETC___d13913, - IF_NOT_fetchStage_pipelines_0_canDeq__2755_275_ETC___d13921, - IF_NOT_fetchStage_pipelines_1_first__2766_BITS_ETC___d13836, - IF_NOT_fetchStage_pipelines_1_first__2766_BITS_ETC___d13920, - IF_NOT_rob_deqPort_1_deq_data__5346_BIT_25_534_ETC___d15675, + IF_NOT_fetchStage_pipelines_0_canDeq__2755_275_ETC___d13923, + IF_NOT_fetchStage_pipelines_0_canDeq__2755_275_ETC___d13931, + IF_NOT_fetchStage_pipelines_1_first__2766_BITS_ETC___d13846, + IF_NOT_fetchStage_pipelines_1_first__2766_BITS_ETC___d13930, + IF_NOT_rob_deqPort_1_deq_data__5356_BIT_25_535_ETC___d15685, IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10472, IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10705, IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10900, @@ -6176,18 +6177,18 @@ module mkCore(CLK, IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d3649, IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3634, IF_coreFix_memExe_respLrScAmoQ_enqReq_lat_1_wh_ETC___d3558, - IF_fetchStage_RDY_pipelines_0_first__2754_AND__ETC___d13440, - IF_fetchStage_RDY_pipelines_1_first__2765_AND__ETC___d13838, - IF_fetchStage_RDY_pipelines_1_first__2765_AND__ETC___d13910, - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13959, - IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14089, + IF_fetchStage_RDY_pipelines_0_first__2754_AND__ETC___d13450, + IF_fetchStage_RDY_pipelines_1_first__2765_AND__ETC___d13848, + IF_fetchStage_RDY_pipelines_1_first__2765_AND__ETC___d13920, + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13969, + IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14099, IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmio_c_ETC___d339, IF_mmio_cRsQ_enqReq_lat_1_whas__74_THEN_mmio_c_ETC___d783, IF_mmio_dataReqQ_enqReq_lat_1_whas__7_THEN_mmi_ETC___d46, IF_mmio_dataRespQ_enqReq_lat_1_whas__92_THEN_m_ETC___d201, IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmio_p_ETC___d642, IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_mmio_p_ETC___d491, - IF_rob_deqPort_1_canDeq__5343_THEN_IF_NOT_rob__ETC___d15676, + IF_rob_deqPort_1_canDeq__5353_THEN_IF_NOT_rob__ETC___d15686, NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5221, NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5249, NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d6613, @@ -6195,9 +6196,9 @@ module mkCore(CLK, NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d8005, NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d8033, NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13344, - NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13427, - NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13730, - NOT_IF_NOT_rob_deqPort_0_canDeq__5338_5339_OR__ETC___d15681, + NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13437, + NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13740, + NOT_IF_NOT_rob_deqPort_0_canDeq__5348_5349_OR__ETC___d15691, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10056, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10765, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10807, @@ -6211,13 +6212,13 @@ module mkCore(CLK, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11006, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8556, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9286, - NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13489, - NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14629, - NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14636, - NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14700, - NOT_commitStage_rg_run_state_4350_4351_AND_NOT_ETC___d15010, - NOT_commitStage_rg_run_state_4350_4351_AND_NOT_ETC___d15021, - NOT_commitStage_rg_run_state_4350_4351_AND_NOT_ETC___d15392, + NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13499, + NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14639, + NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14646, + NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710, + NOT_commitStage_rg_run_state_4360_4361_AND_NOT_ETC___d15020, + NOT_commitStage_rg_run_state_4360_4361_AND_NOT_ETC___d15031, + NOT_commitStage_rg_run_state_4360_4361_AND_NOT_ETC___d15402, NOT_coreFix_aluExe_0_bypassWire_0_whas__2202_2_ETC___d12229, NOT_coreFix_aluExe_0_bypassWire_0_whas__2202_2_ETC___d12257, NOT_coreFix_aluExe_1_bypassWire_0_whas__1342_1_ETC___d11369, @@ -6271,36 +6272,36 @@ module mkCore(CLK, NOT_coreFix_memExe_respLrScAmoQ_enqReq_dummy2__ETC___d3589, NOT_coreFix_memExe_respLrScAmoQ_full_952_953_A_ETC___d2082, NOT_csrf_fs_reg_read__1546_EQ_0_2997_2998_OR_N_ETC___d13337, - NOT_csrf_fs_reg_read__1546_EQ_0_2997_2998_OR_N_ETC___d13425, - NOT_csrf_fs_reg_read__1546_EQ_0_2997_2998_OR_N_ETC___d13728, - NOT_csrf_prv_reg_read__2787_ULE_1_4701_4743_OR_ETC___d14747, - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13532, - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13775, - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13819, - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13874, - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13892, - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14041, - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14095, - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14194, - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14199, - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14201, - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14213, - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14257, - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14258, - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14288, + NOT_csrf_fs_reg_read__1546_EQ_0_2997_2998_OR_N_ETC___d13435, + NOT_csrf_fs_reg_read__1546_EQ_0_2997_2998_OR_N_ETC___d13738, + NOT_csrf_prv_reg_read__2787_ULE_1_4711_4753_OR_ETC___d14757, + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13542, + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13785, + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13829, + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13884, + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13902, + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14051, + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14105, + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14204, + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14209, + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14211, + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14223, + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14267, + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14268, + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14298, NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13331, - NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13471, - NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13751, - NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13757, - NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13918, - NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14102, - NOT_fetchStage_pipelines_0_first__2757_BIT_68__ETC___d13482, + NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13481, + NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13761, + NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13767, + NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13928, + NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14112, + NOT_fetchStage_pipelines_0_first__2757_BIT_68__ETC___d13492, NOT_fetchStage_pipelines_1_canDeq__2763_2764_O_ETC___d12772, - NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d13505, - NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d13744, - NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d13861, - NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d14210, - NOT_fetchStage_pipelines_1_first__2766_BIT_68__ETC___d14207, + NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d13515, + NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d13754, + NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d13871, + NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d14220, + NOT_fetchStage_pipelines_1_first__2766_BIT_68__ETC___d14217, NOT_mmio_cRqQ_clearReq_dummy2_1_read__26_27_OR_ETC___d431, NOT_mmio_cRqQ_enqReq_dummy2_2_read__32_47_OR_I_ETC___d452, NOT_mmio_cRsQ_clearReq_dummy2_1_read__18_19_OR_ETC___d823, @@ -6316,21 +6317,21 @@ module mkCore(CLK, NOT_mmio_pRqQ_enqReq_dummy2_2_read__35_50_OR_I_ETC___d755, NOT_mmio_pRsQ_clearReq_dummy2_1_read__88_89_OR_ETC___d593, NOT_mmio_pRsQ_enqReq_dummy2_2_read__94_09_OR_I_ETC___d614, - NOT_regRenamingTable_rename_0_canRename__3408__ETC___d13766, - NOT_regRenamingTable_rename_0_canRename__3408__ETC___d13842, - NOT_regRenamingTable_rename_0_canRename__3408__ETC___d14189, - NOT_regRenamingTable_rename_1_canRename__3535__ETC___d13806, + NOT_regRenamingTable_rename_0_canRename__3418__ETC___d13776, + NOT_regRenamingTable_rename_0_canRename__3418__ETC___d13852, + NOT_regRenamingTable_rename_0_canRename__3418__ETC___d14199, + NOT_regRenamingTable_rename_1_canRename__3545__ETC___d13816, NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13102, - NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13432, - NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13741, - NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13883, - NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13901, - NOT_rob_deqPort_0_canDeq__5338_5339_OR_regRena_ETC___d15380, - NOT_rob_deqPort_0_canDeq__5338_5339_OR_rob_deq_ETC___d15659, - NOT_rob_deqPort_0_deq_data__4344_BITS_329_TO_3_ETC___d14998, - NOT_rob_deqPort_1_deq_data__5346_BIT_25_5347_5_ETC___d15377, - NOT_specTagManager_canClaim__3406_3497_OR_NOT__ETC___d14012, - NOT_specTagManager_canClaim__3406_3497_OR_NOT__ETC___d14079, + NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13442, + NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13751, + NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13893, + NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13911, + NOT_rob_deqPort_0_canDeq__5348_5349_OR_rob_RDY_ETC___d15390, + NOT_rob_deqPort_0_canDeq__5348_5349_OR_rob_deq_ETC___d15669, + NOT_rob_deqPort_0_deq_data__4354_BITS_329_TO_3_ETC___d15008, + NOT_rob_deqPort_1_deq_data__5356_BIT_25_5357_5_ETC___d15387, + NOT_specTagManager_canClaim__3416_3507_OR_NOT__ETC___d14022, + NOT_specTagManager_canClaim__3416_3507_OR_NOT__ETC___d14089, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10132, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10133, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8647, @@ -6364,12 +6365,12 @@ module mkCore(CLK, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6265, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7264, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7657, - _0_OR_NOT_fetchStage_pipelines_0_first__2757_BI_ETC___d13933, - _0_OR_NOT_fetchStage_pipelines_1_first__2766_BI_ETC___d13834, - _0_OR_NOT_fetchStage_pipelines_1_first__2766_BI_ETC___d14025, - _0b0_CONCAT_csrf_external_int_pend_vec_3_read___ETC___d14329, - _0b0_CONCAT_csrf_medeleg_15_reg_read__1645_1646_ETC___d14721, - _0b0_CONCAT_csrf_mideleg_11_reg_read__1653_1654_ETC___d14703, + _0_OR_NOT_fetchStage_pipelines_0_first__2757_BI_ETC___d13943, + _0_OR_NOT_fetchStage_pipelines_1_first__2766_BI_ETC___d13844, + _0_OR_NOT_fetchStage_pipelines_1_first__2766_BI_ETC___d14035, + _0b0_CONCAT_csrf_external_int_pend_vec_3_read___ETC___d14339, + _0b0_CONCAT_csrf_medeleg_15_reg_read__1645_1646_ETC___d14731, + _0b0_CONCAT_csrf_mideleg_11_reg_read__1653_1654_ETC___d14713, _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4012, _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4013, _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5184, @@ -6395,7 +6396,7 @@ module mkCore(CLK, _dfoo16, _dfoo18, _dfoo2, - _dfoo22, + _dfoo20, _dfoo24, _dfoo26, _dfoo32, @@ -6429,7 +6430,7 @@ module mkCore(CLK, _theResult_____2__h318368, _theResult_____2__h328712, _theResult_____2__h331937, - commitStage_commitTrap_4352_BIT_36_4594_AND_co_ETC___d14659, + commitStage_commitTrap_4362_BIT_36_4604_AND_co_ETC___d14669, coreFix_aluExe_0_bypassWire_0_wget__2203_BITS__ETC___d12205, coreFix_aluExe_0_bypassWire_0_wget__2203_BITS__ETC___d12244, coreFix_aluExe_0_bypassWire_1_wget__2216_BITS__ETC___d12218, @@ -6438,7 +6439,7 @@ module mkCore(CLK, coreFix_aluExe_0_bypassWire_2_wget__2224_BITS__ETC___d12254, coreFix_aluExe_0_dispToRegQ_first__2182_BIT_13_ETC___d12267, coreFix_aluExe_0_exeToFinQ_RDY_first__2641_AND_ETC___d12680, - coreFix_aluExe_0_rsAlu_approximateCount__3447__ETC___d13449, + coreFix_aluExe_0_rsAlu_approximateCount__3457__ETC___d13459, coreFix_aluExe_1_bypassWire_0_wget__1343_BITS__ETC___d11345, coreFix_aluExe_1_bypassWire_0_wget__1343_BITS__ETC___d11384, coreFix_aluExe_1_bypassWire_1_wget__1356_BITS__ETC___d11358, @@ -6466,7 +6467,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d10936, coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d10978, coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d11020, - coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__39_ETC___d14032, + coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__39_ETC___d14042, coreFix_memExe_bypassWire_0_wget__569_BITS_70__ETC___d1571, coreFix_memExe_bypassWire_0_wget__569_BITS_70__ETC___d1609, coreFix_memExe_bypassWire_1_wget__582_BITS_70__ETC___d1584, @@ -6528,50 +6529,50 @@ module mkCore(CLK, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1263, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1267, coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2_re_ETC___d3574, - coreFix_memExe_stb_isEmpty__009_AND_coreFix_me_ETC___d14661, + coreFix_memExe_stb_isEmpty__009_AND_coreFix_me_ETC___d14671, csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13045, - csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13507, - csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13796, - csrf_prv_reg_read__2787_ULE_1_4701_AND_IF_comm_ETC___d14723, - csrf_prv_reg_read__2787_ULE_1___d14701, + csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13517, + csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13806, + csrf_prv_reg_read__2787_ULE_1_4711_AND_IF_comm_ETC___d14733, + csrf_prv_reg_read__2787_ULE_1___d14711, csrf_prv_reg_read__2787_ULT_IF_fetchStage_pipe_ETC___d13040, - csrf_rg_dcsr_read__1720_BIT_2_3062_OR_NOT_fetc_ETC___d13503, - epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13739, - epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13881, - epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13899, - f_csr_rsps_i_notFull__5791_AND_f_csr_reqs_firs_ETC___d15894, - fetchStage_RDY_pipelines_0_first__2754_AND_epo_ETC___d13309, - fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14023, - fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14105, - fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14181, - fetchStage_pipelines_0_canDeq__2755_AND_fetchS_ETC___d14093, - fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14029, - fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14036, - fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14058, - fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14070, - fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14301, - fetchStage_pipelines_0_canDeq__2755_AND_specTa_ETC___d14157, + csrf_rg_dcsr_read__1720_BIT_2_3062_OR_NOT_fetc_ETC___d13513, + epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13749, + epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13891, + epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13909, + f_csr_rsps_i_notFull__5801_AND_f_csr_reqs_firs_ETC___d15904, + fetchStage_RDY_pipelines_1_deq__2769_AND_NOT_f_ETC___d14093, + fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14033, + fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14115, + fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14191, + fetchStage_pipelines_0_canDeq__2755_AND_fetchS_ETC___d14103, + fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14039, + fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14046, + fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14068, + fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14080, + fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14311, + fetchStage_pipelines_0_canDeq__2755_AND_specTa_ETC___d14167, fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13038, - fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13750, - fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13849, - fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13961, - fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13967, - fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13984, - fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13996, - fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d14003, - fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d14019, - fetchStage_pipelines_0_first__2757_BITS_199_TO_ETC___d13514, - fetchStage_pipelines_0_first__2757_BIT_68_2786_ETC___d13840, - fetchStage_pipelines_1_first__2766_BITS_194_TO_ETC___d13978, - fetchStage_pipelines_1_first__2766_BITS_199_TO_ETC___d13990, + fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13760, + fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13859, + fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13971, + fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13977, + fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13994, + fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d14006, + fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d14013, + fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d14029, + fetchStage_pipelines_0_first__2757_BITS_199_TO_ETC___d13524, + fetchStage_pipelines_0_first__2757_BIT_68_2786_ETC___d13850, + fetchStage_pipelines_1_first__2766_BITS_194_TO_ETC___d13988, + fetchStage_pipelines_1_first__2766_BITS_199_TO_ETC___d14000, guard__h364336, guard__h410033, guard__h455728, guard__h503481, guard__h542334, guard__h581638, - idx__h686276, - k__h670531, + idx__h686379, + k__h670634, mmio_cRqQ_enqReq_dummy2_2_read__32_AND_IF_mmio_ETC___d444, mmio_cRsQ_enqReq_dummy2_2_read__24_AND_IF_mmio_ETC___d836, mmio_dataPendQ_enqReq_dummy2_2_read__00_AND_IF_ETC___d312, @@ -6580,8 +6581,8 @@ module mkCore(CLK, mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13055, mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13347, mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13365, - mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14097, - mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14099, + mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14107, + mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14109, mmio_pRqQ_enqReq_dummy2_2_read__35_AND_IF_mmio_ETC___d747, mmio_pRsQ_enqReq_dummy2_2_read__94_AND_IF_mmio_ETC___d606, msip__h76124, @@ -6591,37 +6592,37 @@ module mkCore(CLK, next_deqP___1__h328991, next_deqP___1__h332216, r1__read_BIT_20___h655898, - regRenamingTable_RDY_commit_0_commit__4943_AND_ETC___d15003, - regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13946, - regRenamingTable_RDY_rename_1_getRename__4009__ETC___d14027, - regRenamingTable_rename_0_canRename__3408_AND__ETC___d13434, - regRenamingTable_rename_0_canRename__3408_AND__ETC___d13484, - regRenamingTable_rename_0_canRename__3408_AND__ETC___d13498, - regRenamingTable_rename_0_canRename__3408_AND__ETC___d13828, - regRenamingTable_rename_0_canRename__3408_AND__ETC___d13975, - regRenamingTable_rename_0_canRename__3408_AND__ETC___d14117, - regRenamingTable_rename_0_canRename__3408_AND__ETC___d14123, - regRenamingTable_rename_0_canRename__3408_AND__ETC___d14143, - regRenamingTable_rename_0_canRename__3408_AND__ETC___d14151, - regRenamingTable_rename_0_canRename__3408_AND__ETC___d14299, - regRenamingTable_rename_1_canRename__3535_AND__ETC___d13743, - regRenamingTable_rename_1_canRename__3535_AND__ETC___d13885, - regRenamingTable_rename_1_canRename__3535_AND__ETC___d13903, - regRenamingTable_rename_1_canRename__3535_AND__ETC___d14209, - regRenamingTable_rename_1_canRename__3535_AND__ETC___d14253, + regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13309, + regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13956, + regRenamingTable_RDY_rename_1_getRename__4019__ETC___d14037, + regRenamingTable_rename_0_canRename__3418_AND__ETC___d13444, + regRenamingTable_rename_0_canRename__3418_AND__ETC___d13494, + regRenamingTable_rename_0_canRename__3418_AND__ETC___d13508, + regRenamingTable_rename_0_canRename__3418_AND__ETC___d13838, + regRenamingTable_rename_0_canRename__3418_AND__ETC___d13985, + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14127, + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14133, + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14153, + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14161, + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14309, + regRenamingTable_rename_1_canRename__3545_AND__ETC___d13753, + regRenamingTable_rename_1_canRename__3545_AND__ETC___d13895, + regRenamingTable_rename_1_canRename__3545_AND__ETC___d13913, + regRenamingTable_rename_1_canRename__3545_AND__ETC___d14219, + regRenamingTable_rename_1_canRename__3545_AND__ETC___d14263, renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_N_ETC___d13068, renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_N_ETC___d13299, - renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13764, - renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13804, - renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13845, - renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13925, - rg_core_run_state_read__3058_EQ_2_3059_AND_NOT_ETC___d15730, - rob_RDY_enqPort_1_enq__4075_AND_NOT_fetchStage_ETC___d14083, + renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13774, + renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13814, + renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13855, + renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13935, + rg_core_run_state_read__3058_EQ_2_3059_AND_NOT_ETC___d15740, + rob_RDY_deqPort_0_deq__4351_AND_rob_RDY_deqPor_ETC___d15013, sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8294, sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8295, sbCons_lazyLookup_3_get_coreFix_memExe_dispToR_ETC___d1632, - tsr_val__h727178, - tvm_val__h727180, + tsr_val__h727281, + tvm_val__h727283, v__h299289, v__h299807, v__h309803, @@ -6673,7 +6674,7 @@ module mkCore(CLK, { CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q264, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q265, !CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q266, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16071 } ; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16081 } ; assign RDY_dCacheToParent_rsToP_first = !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty ; @@ -6693,7 +6694,7 @@ module mkCore(CLK, assign dCacheToParent_rqToP_first = { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q272, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q273, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16097 } ; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16107 } ; assign RDY_dCacheToParent_rqToP_first = !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty ; @@ -9894,7 +9895,7 @@ module mkCore(CLK, // rule RL_readyToFetch assign CAN_FIRE_RL_readyToFetch = fetchStage$RDY_done_flushing && - rg_core_run_state_read__3058_EQ_2_3059_AND_NOT_ETC___d15730 && + rg_core_run_state_read__3058_EQ_2_3059_AND_NOT_ETC___d15740 && !flush_brpred && fetchStage$iMemIfc_flush_done && fetchStage$flush_predictors_done ; @@ -9994,7 +9995,7 @@ module mkCore(CLK, // rule RL_rl_debug_csr_write assign CAN_FIRE_RL_rl_debug_csr_write = f_csr_reqs$EMPTY_N && - f_csr_rsps_i_notFull__5791_AND_f_csr_reqs_firs_ETC___d15894 && + f_csr_rsps_i_notFull__5801_AND_f_csr_reqs_firs_ETC___d15904 && rg_core_run_state == 2'd1 && f_csr_reqs$D_OUT[76] ; assign WILL_FIRE_RL_rl_debug_csr_write = CAN_FIRE_RL_rl_debug_csr_write ; @@ -10352,19 +10353,19 @@ module mkCore(CLK, // rule RL_commitStage_rl_send_mip_csr_change_to_tv assign CAN_FIRE_RL_commitStage_rl_send_mip_csr_change_to_tv = v_f_to_TV_0$FULL_N && !commitStage_rg_just_after_reset && - !_0b0_CONCAT_csrf_external_int_pend_vec_3_read___ETC___d14329 ; + !_0b0_CONCAT_csrf_external_int_pend_vec_3_read___ETC___d14339 ; assign WILL_FIRE_RL_commitStage_rl_send_mip_csr_change_to_tv = CAN_FIRE_RL_commitStage_rl_send_mip_csr_change_to_tv ; // rule RL_commitStage_doCommitTrap_handle assign CAN_FIRE_RL_commitStage_doCommitTrap_handle = commitStage_f_rob_data$EMPTY_N && - NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14636 && - (commitStage_commitTrap_4352_BIT_36_4594_AND_co_ETC___d14659 || - coreFix_memExe_stb_isEmpty__009_AND_coreFix_me_ETC___d14661) && + NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14646 && + (commitStage_commitTrap_4362_BIT_36_4604_AND_co_ETC___d14669 || + coreFix_memExe_stb_isEmpty__009_AND_coreFix_me_ETC___d14671) && commitStage_commitTrap[165] && !commitStage_rg_run_state && - _0b0_CONCAT_csrf_external_int_pend_vec_3_read___ETC___d14329 ; + _0b0_CONCAT_csrf_external_int_pend_vec_3_read___ETC___d14339 ; assign WILL_FIRE_RL_commitStage_doCommitTrap_handle = CAN_FIRE_RL_commitStage_doCommitTrap_handle && !WILL_FIRE_RL_commitStage_rl_send_tv_reset && @@ -10376,8 +10377,8 @@ module mkCore(CLK, // rule RL_commitStage_doCommitKilledLd assign CAN_FIRE_RL_commitStage_doCommitKilledLd = - epochManager$RDY_incrementEpoch && rob$RDY_deqPort_0_deq && - rob$RDY_deqPort_0_deq_data && + rob$RDY_deqPort_0_deq && rob$RDY_deqPort_0_deq_data && + epochManager$RDY_incrementEpoch && !commitStage_rg_run_state && !commitStage_commitTrap[165] && !rob$deqPort_0_deq_data[167] && @@ -10413,8 +10414,8 @@ module mkCore(CLK, // rule RL_commitStage_doCommitSystemInst assign CAN_FIRE_RL_commitStage_doCommitSystemInst = coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty && - regRenamingTable_RDY_commit_0_commit__4943_AND_ETC___d15003 && - NOT_commitStage_rg_run_state_4350_4351_AND_NOT_ETC___d15021 ; + rob_RDY_deqPort_0_deq__4351_AND_rob_RDY_deqPor_ETC___d15013 && + NOT_commitStage_rg_run_state_4360_4361_AND_NOT_ETC___d15031 ; assign WILL_FIRE_RL_commitStage_doCommitSystemInst = CAN_FIRE_RL_commitStage_doCommitSystemInst && !WILL_FIRE_RL_commitStage_rl_send_tv_reset && @@ -10448,8 +10449,8 @@ module mkCore(CLK, // rule RL_commitStage_doCommitNormalInst assign CAN_FIRE_RL_commitStage_doCommitNormalInst = rob$RDY_deqPort_0_deq_data && - NOT_rob_deqPort_0_canDeq__5338_5339_OR_regRena_ETC___d15380 && - NOT_commitStage_rg_run_state_4350_4351_AND_NOT_ETC___d15392 ; + NOT_rob_deqPort_0_canDeq__5348_5349_OR_rob_RDY_ETC___d15390 && + NOT_commitStage_rg_run_state_4360_4361_AND_NOT_ETC___d15402 ; assign WILL_FIRE_RL_commitStage_doCommitNormalInst = CAN_FIRE_RL_commitStage_doCommitNormalInst && !WILL_FIRE_RL_commitStage_rl_send_tv_reset ; @@ -11417,10 +11418,9 @@ module mkCore(CLK, // rule RL_renameStage_doRenaming_Trap assign CAN_FIRE_RL_renameStage_doRenaming_Trap = - fetchStage$RDY_pipelines_0_deq && + rob$RDY_enqPort_0_enq && fetchStage$RDY_pipelines_0_deq && fetchStage$RDY_pipelines_0_first && epochManager$RDY_incrementEpoch && - rob$RDY_enqPort_0_enq && mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13055 && rob$isEmpty && rg_core_run_state == 2'd2 ; @@ -11432,8 +11432,8 @@ module mkCore(CLK, // rule RL_renameStage_doRenaming_SystemInst assign CAN_FIRE_RL_renameStage_doRenaming_SystemInst = - fetchStage$RDY_pipelines_0_deq && - fetchStage_RDY_pipelines_0_first__2754_AND_epo_ETC___d13309 && + rob$RDY_enqPort_0_enq && + regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13309 && mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13365 && rg_core_run_state == 2'd2 ; assign WILL_FIRE_RL_renameStage_doRenaming_SystemInst = @@ -11476,11 +11476,11 @@ module mkCore(CLK, // rule RL_renameStage_doRenaming assign CAN_FIRE_RL_renameStage_doRenaming = (!fetchStage$pipelines_0_canDeq || - IF_fetchStage_RDY_pipelines_0_first__2754_AND__ETC___d13440) && - IF_NOT_fetchStage_pipelines_0_canDeq__2755_275_ETC___d13913 && - IF_NOT_fetchStage_pipelines_0_canDeq__2755_275_ETC___d13921 && - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14095 && - mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14099 ; + IF_fetchStage_RDY_pipelines_0_first__2754_AND__ETC___d13450) && + IF_NOT_fetchStage_pipelines_0_canDeq__2755_275_ETC___d13923 && + IF_NOT_fetchStage_pipelines_0_canDeq__2755_275_ETC___d13931 && + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14105 && + mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14109 ; assign WILL_FIRE_RL_renameStage_doRenaming = CAN_FIRE_RL_renameStage_doRenaming && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && @@ -11519,10 +11519,10 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_fpr_read ; assign MUX_commitStage_rg_run_state$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap_4352_BIT_36_4594_AND_co_ETC___d14659 ; + commitStage_commitTrap_4362_BIT_36_4604_AND_co_ETC___d14669 ; assign MUX_commitStage_rg_serial_num$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14700 ; + NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 ; assign MUX_commitStage_rg_serial_num$write_1__SEL_2 = WILL_FIRE_RL_commitStage_rl_send_mip_csr_change_to_tv || WILL_FIRE_RL_commitStage_doCommitSystemInst ; @@ -11718,9 +11718,9 @@ module mkCore(CLK, assign MUX_csrf_external_int_en_vec_1$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + (IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd9 || - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd22) ; assign MUX_csrf_external_int_en_vec_3$write_1__SEL_1 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11728,9 +11728,9 @@ module mkCore(CLK, assign MUX_csrf_external_int_pend_vec_1$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + (IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd16 || - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd29) ; assign MUX_csrf_external_int_pend_vec_1$write_1__SEL_2 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11739,20 +11739,20 @@ module mkCore(CLK, assign MUX_csrf_external_int_pend_vec_3$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd29 ; assign MUX_csrf_external_int_pend_vec_3$write_1__SEL_2 = WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd836 ; assign MUX_csrf_fflags_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitNormalInst && - NOT_IF_NOT_rob_deqPort_0_canDeq__5338_5339_OR__ETC___d15681 ; + NOT_IF_NOT_rob_deqPort_0_canDeq__5348_5349_OR__ETC___d15691 ; assign MUX_csrf_fflags_reg$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + (IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd0 || - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd2) ; assign MUX_csrf_fflags_reg$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11761,22 +11761,22 @@ module mkCore(CLK, assign MUX_csrf_frm_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + (IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd1 || - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd2) ; assign MUX_csrf_fs_reg$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + (IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd0 || - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd1 || - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd2 || - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd8 || - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd18) ; assign MUX_csrf_fs_reg$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11788,9 +11788,9 @@ module mkCore(CLK, assign MUX_csrf_ie_vec_0$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + (IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd8 || - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd18) ; assign MUX_csrf_ie_vec_0$write_1__SEL_2 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11800,21 +11800,21 @@ module mkCore(CLK, WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 ; assign MUX_csrf_ie_vec_1$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14700 && - csrf_prv_reg_read__2787_ULE_1_4701_AND_IF_comm_ETC___d14723 ; + NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 && + csrf_prv_reg_read__2787_ULE_1_4711_AND_IF_comm_ETC___d14733 ; assign MUX_csrf_ie_vec_3$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; assign MUX_csrf_ie_vec_3$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14700 && - NOT_csrf_prv_reg_read__2787_ULE_1_4701_4743_OR_ETC___d14747 ; + NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 && + NOT_csrf_prv_reg_read__2787_ULE_1_4711_4753_OR_ETC___d14757 ; assign MUX_csrf_ie_vec_3$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd768 ; assign MUX_csrf_mcause_code_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd27 ; assign MUX_csrf_mcause_code_reg$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11828,7 +11828,7 @@ module mkCore(CLK, assign MUX_csrf_mcycle_ehr_data_dummy2_0$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd30 ; assign MUX_csrf_medeleg_13_11_reg$write_1__SEL_1 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11836,7 +11836,7 @@ module mkCore(CLK, assign MUX_csrf_mepc_csr$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd26 ; assign MUX_csrf_mepc_csr$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11850,7 +11850,7 @@ module mkCore(CLK, assign MUX_csrf_minstret_ehr_data_dummy2_0$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd31 ; assign MUX_csrf_mpp_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; @@ -11860,7 +11860,7 @@ module mkCore(CLK, assign MUX_csrf_mtval_csr$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd28 ; assign MUX_csrf_mtval_csr$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11883,12 +11883,12 @@ module mkCore(CLK, assign MUX_csrf_rg_dcsr$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd40 ; assign MUX_csrf_rg_dpc$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd41 ; assign MUX_csrf_rg_dpc$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11914,7 +11914,7 @@ module mkCore(CLK, assign MUX_csrf_scause_code_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd14 ; assign MUX_csrf_scause_code_reg$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11925,7 +11925,7 @@ module mkCore(CLK, assign MUX_csrf_sepc_csr$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd13 ; assign MUX_csrf_sepc_csr$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11945,7 +11945,7 @@ module mkCore(CLK, assign MUX_csrf_stval_csr$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd15 ; assign MUX_csrf_stval_csr$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11956,13 +11956,13 @@ module mkCore(CLK, assign MUX_epochManager$updatePrevEpoch_0_update_1__SEL_2 = WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14102 && - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13494 ; + NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14112 && + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13504 ; assign MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2 = WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14199 && - NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d14210 && - IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13907 ; + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14209 && + NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d14220 && + IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13917 ; assign MUX_f_run_halt_rsps$enq_1__SEL_1 = WILL_FIRE_RL_rl_debug_halted || WILL_FIRE_RL_rl_debug_halt_req_already_halted ; @@ -11978,7 +11978,7 @@ module mkCore(CLK, csrf_rg_dcsr[2] ; assign MUX_renameStage_rg_m_halt_req$write_1__SEL_2 = WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14199 && + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14209 && csrf_rg_dcsr[2] ; assign MUX_rf$write_3_wr_1__SEL_1 = WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && @@ -12033,13 +12033,13 @@ module mkCore(CLK, assign MUX_commitStage_commitTrap$write_1__VAL_2 = { 1'd1, rob$deqPort_0_deq_data[425:362], - x__h703283, - rob_deqPort_0_deq_data__4344_BIT_166_4360_CONC_ETC___d14409, + x__h703386, + rob_deqPort_0_deq_data__4354_BIT_166_4370_CONC_ETC___d14419, rob$deqPort_0_deq_data[361:330] } ; assign MUX_commitStage_rg_serial_num$write_1__VAL_1 = commitStage_rg_serial_num + 64'd1 ; assign MUX_commitStage_rg_serial_num$write_1__VAL_3 = - commitStage_rg_serial_num + y__h734147 ; + commitStage_rg_serial_num + y__h734250 ; assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_1 = { fetchStage$pipelines_0_first[199:195], IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d12883, @@ -12053,8 +12053,8 @@ module mkCore(CLK, 5'd10, sbAggr$eagerLookup_0_get } ; assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_2 = - (k__h670531 == 1'd0 && - fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14105) ? + (k__h670634 == 1'd0 && + fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14115) ? { fetchStage$pipelines_0_first[199:195], IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d12883, fetchStage$pipelines_0_first[173], @@ -12068,13 +12068,13 @@ module mkCore(CLK, specTagManager$nextSpecTag, sbAggr$eagerLookup_0_get } : { fetchStage$pipelines_1_first[199:195], - IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13589, - fetchStage_pipelines_1_first__2766_BIT_173_359_ETC___d13681, + IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13599, + fetchStage_pipelines_1_first__2766_BIT_173_360_ETC___d13691, fetchStage$pipelines_1_first[160:128], fetchStage$pipelines_1_first[255:232], regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h686145, + renaming_spec_bits__h686248, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -12240,8 +12240,8 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getRq, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getData } ; assign MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1 = - { prv__h735835, - prv__h735835 != 2'd3 && csrf_vm_mode_sv39_reg, + { prv__h735938, + prv__h735938 != 2'd3 && csrf_vm_mode_sv39_reg, csrf_mxr_reg, csrf_sum_reg, csrf_ppn_reg } ; @@ -12387,9 +12387,9 @@ module mkCore(CLK, MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_1 || MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_2 ; assign MUX_csrf_fflags_reg$write_1__VAL_1 = - csrf_fflags_reg | fflags__h734124 ; + csrf_fflags_reg | fflags__h734227 ; assign MUX_csrf_frm_reg$write_1__VAL_1 = - (IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + (IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd1) ? robdeqPort_0_deq_data_BITS_95_TO_32__q245[2:0] : robdeqPort_0_deq_data_BITS_95_TO_32__q245[7:5] ; @@ -12397,10 +12397,10 @@ module mkCore(CLK, (f_csr_reqs$D_OUT[75:64] == 12'd2) ? f_csr_reqs$D_OUT[2:0] : f_csr_reqs$D_OUT[7:5] ; - always@(IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 or + always@(IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 or robdeqPort_0_deq_data_BITS_95_TO_32__q245) begin - case (IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988) + case (IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998) 6'd0, 6'd1, 6'd2: MUX_csrf_fs_reg$write_1__VAL_2 = 2'b11; default: MUX_csrf_fs_reg$write_1__VAL_2 = robdeqPort_0_deq_data_BITS_95_TO_32__q245[14:13]; @@ -12415,55 +12415,55 @@ module mkCore(CLK, end assign MUX_csrf_ie_vec_1$write_1__VAL_1 = (rob$deqPort_0_deq_data[329:325] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + (IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd8 || - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd18)) ? robdeqPort_0_deq_data_BITS_95_TO_32__q245[1] : csrf_prev_ie_vec_1 ; assign MUX_csrf_ie_vec_3$write_1__VAL_1 = (rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd18) ? robdeqPort_0_deq_data_BITS_95_TO_32__q245[3] : csrf_prev_ie_vec_3 ; assign MUX_csrf_minstret_ehr_data_lat_0$wset_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ; assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1 = - n__read__h727564 + 64'd1 ; + n__read__h727667 + 64'd1 ; assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2 = - n__read__h727564 + { 62'd0, x__h734388 } ; + n__read__h727667 + { 62'd0, x__h734491 } ; assign MUX_csrf_mpp_reg$write_1__VAL_1 = (rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd18) ? MUX_csrf_minstret_ehr_data_lat_0$wset_1__VAL_2[12:11] : 2'd0 ; assign MUX_csrf_mtval_csr$write_1__VAL_1 = rob$deqPort_0_deq_data[95:32] ; assign MUX_csrf_prev_ie_vec_1$write_1__VAL_1 = rob$deqPort_0_deq_data[329:325] != 5'd13 || - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 != + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 != 6'd8 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 != + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 != 6'd18 || MUX_csrf_mtval_csr$write_1__VAL_1[5] ; assign MUX_csrf_prev_ie_vec_3$write_1__VAL_1 = rob$deqPort_0_deq_data[329:325] != 5'd13 || - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 != + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 != 6'd18 || MUX_csrf_mtval_csr$write_1__VAL_1[7] ; assign MUX_csrf_prv_reg$write_1__VAL_1 = (rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd40) ? MUX_csrf_mtval_csr$write_1__VAL_1[1:0] : ((rob$deqPort_0_deq_data[329:325] == 5'd19) ? - x__h723465 : + x__h723568 : csrf_mpp_reg) ; assign MUX_csrf_rg_dcsr$write_1__VAL_2 = { 32'b0, csrf_rg_dcsr[31:9], - dcsr_cause__h709868, + dcsr_cause__h709971, csrf_rg_dcsr[5:2], csrf_prv_reg } ; assign MUX_csrf_sepc_csr$write_1__VAL_1 = rob$deqPort_0_deq_data[95:32] ; @@ -12473,13 +12473,13 @@ module mkCore(CLK, amoExec___d880[0] ; assign MUX_csrf_spp_reg$write_1__VAL_1 = rob$deqPort_0_deq_data[329:325] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + (IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd8 || - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd18) && MUX_csrf_sepc_csr$write_1__VAL_1[8] ; assign MUX_csrf_stval_csr$write_1__VAL_1 = rob$deqPort_0_deq_data[95:32] ; - assign MUX_f_csr_rsps$enq_1__VAL_3 = { 1'd1, data_out__h738236 } ; + assign MUX_f_csr_rsps$enq_1__VAL_3 = { 1'd1, data_out__h738339 } ; assign MUX_f_fpr_rsps$enq_1__VAL_3 = { 1'd1, rf$read_4_rd1 } ; assign MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 = { csrf_prv_reg, @@ -12488,12 +12488,12 @@ module mkCore(CLK, csrf_sum_reg, csrf_ppn_reg } ; always@(rob$deqPort_0_deq_data or - next_pc__h723361 or csrf_sepc_csr or csrf_mepc_csr) + next_pc__h723464 or csrf_sepc_csr or csrf_mepc_csr) begin case (rob$deqPort_0_deq_data[329:325]) 5'd19: MUX_fetchStage$redirect_1__VAL_6 = csrf_sepc_csr; 5'd20: MUX_fetchStage$redirect_1__VAL_6 = csrf_mepc_csr; - default: MUX_fetchStage$redirect_1__VAL_6 = next_pc__h723361; + default: MUX_fetchStage$redirect_1__VAL_6 = next_pc__h723464; endcase end assign MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_1 = @@ -12572,7 +12572,7 @@ module mkCore(CLK, fetchStage$pipelines_0_first[194:192] != 3'd2 && fetchStage$pipelines_0_first[194:192] != 3'd3 && fetchStage$pipelines_0_first[194:192] != 3'd4, - NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14171 } ; + NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14181 } ; assign MUX_rob$enqPort_0_enq_1__VAL_2 = { fetchStage$pipelines_0_first[387:324], fetchStage$pipelines_0_first[127:96], @@ -12595,21 +12595,7 @@ module mkCore(CLK, fetchStage$pipelines_0_first[199:195], fetchStage$pipelines_0_first[75:69], 136'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, - fetchStage$pipelines_0_first[173], - IF_fetchStage_pipelines_0_first__2757_BITS_172_ETC___d12973, - 73'h1280000000000000000, - fetchStage$pipelines_0_first[323:260], - 5'd0, - fetchStage$pipelines_0_first[173] && - fetchStage$pipelines_0_first[199:195] == 5'd13 && - (fetchStage$pipelines_0_first[172:161] == 12'd1 || - fetchStage$pipelines_0_first[172:161] == 12'd2 || - fetchStage$pipelines_0_first[172:161] == 12'd3) || - fetchStage$pipelines_0_first[75] && - fetchStage$pipelines_0_first[74], - fetchStage$pipelines_0_first[194:192] != 3'd0, - 13'h1521, - specTagManager$currentSpecBits } ; + fetchStage_pipelines_0_first__2757_BIT_173_288_ETC___d13411 } ; assign MUX_rob$setExecuted_deqLSQ_2__VAL_2 = { 1'd1, CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q277 } ; @@ -12633,19 +12619,19 @@ module mkCore(CLK, 77'h0AAAAAAAAAAAAAAAAAAA, commitStage_f_rob_data$D_OUT[425:181], CASE_commitStage_f_rob_dataD_OUT_BITS_180_TO__ETC__q279, - commitStage_f_rob_data_first__4760_BIT_167_485_ETC___d14932 } ; + commitStage_f_rob_data_first__4770_BIT_167_486_ETC___d14942 } ; assign MUX_v_f_to_TV_0$enq_1__VAL_2 = { commitStage_rg_serial_num, 77'h0AAAAAAAAAAAAAAAAAAA, rob$deqPort_0_deq_data[425:182], - rob_deqPort_0_deq_data__4344_BIT_181_4419_CONC_ETC___d14510, + rob_deqPort_0_deq_data__4354_BIT_181_4429_CONC_ETC___d14520, rob$deqPort_0_deq_data[167], - rob_deqPort_0_deq_data__4344_BIT_166_4360_CONC_ETC___d14409, + rob_deqPort_0_deq_data__4354_BIT_166_4370_CONC_ETC___d14419, rob$deqPort_0_deq_data[161:98], - IF_rob_deqPort_0_deq_data__4344_BITS_97_TO_96__ETC___d14517, - po_fflags__h728848, + IF_rob_deqPort_0_deq_data__4354_BITS_97_TO_96__ETC___d14527, + po_fflags__h728951, rob$deqPort_0_deq_data[26], - new_mstatus___1__h726926, + new_mstatus___1__h727029, 258'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; assign MUX_v_f_to_TV_0$enq_1__VAL_4 = { commitStage_rg_serial_num, @@ -12655,12 +12641,12 @@ module mkCore(CLK, assign MUX_v_f_to_TV_0$enq_1__VAL_5 = { commitStage_rg_serial_num, 77'h0AAAAAAAAAAAAAAAAAAA, - x__h723943, + x__h724046, rob$deqPort_0_deq_data[361:182], - rob_deqPort_0_deq_data__4344_BIT_181_4419_CONC_ETC___d14510, + rob_deqPort_0_deq_data__4354_BIT_181_4429_CONC_ETC___d14520, rob$deqPort_0_deq_data[167], - rob_deqPort_0_deq_data__4344_BIT_166_4360_CONC_ETC___d14409, - rob_deqPort_0_deq_data__4344_BITS_161_TO_98_43_ETC___d15316 } ; + rob_deqPort_0_deq_data__4354_BIT_166_4370_CONC_ETC___d14419, + rob_deqPort_0_deq_data__4354_BITS_161_TO_98_43_ETC___d15326 } ; // inlined wires assign csrf_minstret_ehr_data_lat_0$whas = @@ -12960,7 +12946,7 @@ module mkCore(CLK, MUX_commitStage_rg_run_state$write_1__SEL_1 ; assign commitStage_rg_run_state$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap_4352_BIT_36_4594_AND_co_ETC___d14659 || + commitStage_commitTrap_4362_BIT_36_4604_AND_co_ETC___d14669 || WILL_FIRE_RL_rl_debug_resume ; // register commitStage_rg_serial_num @@ -12989,7 +12975,7 @@ module mkCore(CLK, end assign commitStage_rg_serial_num$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14700 || + NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 || WILL_FIRE_RL_commitStage_rl_send_mip_csr_change_to_tv || WILL_FIRE_RL_commitStage_doCommitSystemInst || WILL_FIRE_RL_commitStage_doCommitNormalInst || @@ -13731,7 +13717,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd772 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd22 ; // register csrf_external_int_pend_vec_0 @@ -13780,7 +13766,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd836 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd29 || EN_setMEIP ; @@ -13802,12 +13788,12 @@ module mkCore(CLK, assign csrf_fflags_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + (IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd0 || - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd2) || WILL_FIRE_RL_commitStage_doCommitNormalInst && - NOT_IF_NOT_rob_deqPort_0_canDeq__5338_5339_OR__ETC___d15681 || + NOT_IF_NOT_rob_deqPort_0_canDeq__5348_5349_OR__ETC___d15691 || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd1 || f_csr_reqs$D_OUT[75:64] == 12'd3) ; @@ -13820,9 +13806,9 @@ module mkCore(CLK, assign csrf_frm_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + (IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd1 || - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd2) || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd2 || @@ -13844,7 +13830,7 @@ module mkCore(CLK, assign csrf_fs_reg$EN = MUX_csrf_fs_reg$write_1__SEL_2 || WILL_FIRE_RL_commitStage_doCommitNormalInst && - NOT_IF_NOT_rob_deqPort_0_canDeq__5338_5339_OR__ETC___d15681 || + NOT_IF_NOT_rob_deqPort_0_canDeq__5348_5349_OR__ETC___d15691 || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd1 || f_csr_reqs$D_OUT[75:64] == 12'd2 || @@ -13878,8 +13864,8 @@ module mkCore(CLK, endcase assign csrf_ie_vec_1$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14700 && - csrf_prv_reg_read__2787_ULE_1_4701_AND_IF_comm_ETC___d14723 || + NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 && + csrf_prv_reg_read__2787_ULE_1_4711_AND_IF_comm_ETC___d14733 || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd256 || f_csr_reqs$D_OUT[75:64] == 12'd768) || @@ -13902,21 +13888,21 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14700 && - NOT_csrf_prv_reg_read__2787_ULE_1_4701_4743_OR_ETC___d14747 || + NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 && + NOT_csrf_prv_reg_read__2787_ULE_1_4711_4753_OR_ETC___d14757 || WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; // register csrf_mcause_code_reg always@(MUX_csrf_mcause_code_reg$write_1__SEL_1 or MUX_csrf_stval_csr$write_1__VAL_1 or MUX_csrf_ie_vec_3$write_1__SEL_2 or - cause_code__h710349 or + cause_code__h710452 or MUX_csrf_mcause_code_reg$write_1__SEL_3 or f_csr_reqs$D_OUT) case (1'b1) MUX_csrf_mcause_code_reg$write_1__SEL_1: csrf_mcause_code_reg$D_IN = MUX_csrf_stval_csr$write_1__VAL_1[3:0]; MUX_csrf_ie_vec_3$write_1__SEL_2: - csrf_mcause_code_reg$D_IN = cause_code__h710349; + csrf_mcause_code_reg$D_IN = cause_code__h710452; MUX_csrf_mcause_code_reg$write_1__SEL_3: csrf_mcause_code_reg$D_IN = f_csr_reqs$D_OUT[3:0]; default: csrf_mcause_code_reg$D_IN = 4'b1010 /* unspecified value */ ; @@ -13925,11 +13911,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd834 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14700 && - NOT_csrf_prv_reg_read__2787_ULE_1_4701_4743_OR_ETC___d14747 || + NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 && + NOT_csrf_prv_reg_read__2787_ULE_1_4711_4753_OR_ETC___d14757 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd27 ; // register csrf_mcause_interrupt_reg @@ -13952,11 +13938,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd834 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14700 && - NOT_csrf_prv_reg_read__2787_ULE_1_4701_4743_OR_ETC___d14747 || + NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 && + NOT_csrf_prv_reg_read__2787_ULE_1_4711_4753_OR_ETC___d14757 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd27 ; // register csrf_mcounteren_cy_reg @@ -13969,7 +13955,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd774 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd24 ; // register csrf_mcounteren_ir_reg @@ -13982,7 +13968,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd774 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd24 ; // register csrf_mcounteren_tm_reg @@ -13995,7 +13981,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd774 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd24 ; // register csrf_mcycle_ehr_data_rl @@ -14012,7 +13998,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd770 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd20 ; // register csrf_medeleg_15_reg @@ -14025,7 +14011,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd770 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd20 ; // register csrf_medeleg_9_0_reg @@ -14038,7 +14024,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd770 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd20 ; // register csrf_mepc_csr @@ -14061,11 +14047,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd833 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14700 && - NOT_csrf_prv_reg_read__2787_ULE_1_4701_4743_OR_ETC___d14747 || + NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 && + NOT_csrf_prv_reg_read__2787_ULE_1_4711_4753_OR_ETC___d14757 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd26 ; // register csrf_mideleg_11_reg @@ -14078,7 +14064,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd771 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd21 ; // register csrf_mideleg_1_0_reg @@ -14091,7 +14077,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd771 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd21 ; // register csrf_mideleg_5_3_reg @@ -14104,7 +14090,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd771 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd21 ; // register csrf_mideleg_9_7_reg @@ -14117,7 +14103,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd771 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd21 ; // register csrf_minstret_ehr_data_rl @@ -14145,8 +14131,8 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14700 && - NOT_csrf_prv_reg_read__2787_ULE_1_4701_4743_OR_ETC___d14747 || + NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 && + NOT_csrf_prv_reg_read__2787_ULE_1_4711_4753_OR_ETC___d14757 || WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; // register csrf_mprv_reg @@ -14159,7 +14145,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd18 ; // register csrf_mscratch_csr @@ -14172,19 +14158,19 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd832 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd25 ; // register csrf_mtval_csr always@(MUX_csrf_mtval_csr$write_1__SEL_1 or rob$deqPort_0_deq_data or MUX_csrf_ie_vec_3$write_1__SEL_2 or - trap_val__h710350 or + trap_val__h710453 or MUX_csrf_mtval_csr$write_1__SEL_3 or f_csr_reqs$D_OUT) case (1'b1) MUX_csrf_mtval_csr$write_1__SEL_1: csrf_mtval_csr$D_IN = rob$deqPort_0_deq_data[95:32]; - MUX_csrf_ie_vec_3$write_1__SEL_2: csrf_mtval_csr$D_IN = trap_val__h710350; + MUX_csrf_ie_vec_3$write_1__SEL_2: csrf_mtval_csr$D_IN = trap_val__h710453; MUX_csrf_mtval_csr$write_1__SEL_3: csrf_mtval_csr$D_IN = f_csr_reqs$D_OUT[63:0]; default: csrf_mtval_csr$D_IN = @@ -14194,11 +14180,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd835 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14700 && - NOT_csrf_prv_reg_read__2787_ULE_1_4701_4743_OR_ETC___d14747 || + NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 && + NOT_csrf_prv_reg_read__2787_ULE_1_4711_4753_OR_ETC___d14757 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd28 ; // register csrf_mtvec_base_hi_reg @@ -14211,7 +14197,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd773 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd23 ; // register csrf_mtvec_mode_low_reg @@ -14224,7 +14210,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd773 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd23 ; // register csrf_mxr_reg @@ -14248,7 +14234,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd384 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd17 ; // register csrf_prev_ie_vec_0 @@ -14278,8 +14264,8 @@ module mkCore(CLK, endcase assign csrf_prev_ie_vec_1$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14700 && - csrf_prv_reg_read__2787_ULE_1_4701_AND_IF_comm_ETC___d14723 || + NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 && + csrf_prv_reg_read__2787_ULE_1_4711_AND_IF_comm_ETC___d14733 || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd256 || f_csr_reqs$D_OUT[75:64] == 12'd768) || @@ -14303,28 +14289,28 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14700 && - NOT_csrf_prv_reg_read__2787_ULE_1_4701_4743_OR_ETC___d14747 || + NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 && + NOT_csrf_prv_reg_read__2787_ULE_1_4711_4753_OR_ETC___d14757 || WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; // register csrf_prv_reg always@(MUX_csrf_prv_reg$write_1__SEL_1 or MUX_csrf_prv_reg$write_1__VAL_1 or MUX_commitStage_rg_serial_num$write_1__SEL_1 or - x_prv__h713393 or + x_prv__h713496 or MUX_csrf_prv_reg$write_1__SEL_3 or f_csr_reqs$D_OUT) case (1'b1) MUX_csrf_prv_reg$write_1__SEL_1: csrf_prv_reg$D_IN = MUX_csrf_prv_reg$write_1__VAL_1; MUX_commitStage_rg_serial_num$write_1__SEL_1: - csrf_prv_reg$D_IN = x_prv__h713393; + csrf_prv_reg$D_IN = x_prv__h713496; MUX_csrf_prv_reg$write_1__SEL_3: csrf_prv_reg$D_IN = f_csr_reqs$D_OUT[1:0]; default: csrf_prv_reg$D_IN = 2'b10 /* unspecified value */ ; endcase assign csrf_prv_reg$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14700 || + NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 || WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd1968 || WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo24 ; @@ -14347,12 +14333,12 @@ module mkCore(CLK, endcase assign csrf_rg_dcsr$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap_4352_BIT_36_4594_AND_co_ETC___d14659 || + commitStage_commitTrap_4362_BIT_36_4604_AND_co_ETC___d14669 || WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd1968 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd40 ; // register csrf_rg_dpc @@ -14371,12 +14357,12 @@ module mkCore(CLK, endcase assign csrf_rg_dpc$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap_4352_BIT_36_4594_AND_co_ETC___d14659 || + commitStage_commitTrap_4362_BIT_36_4604_AND_co_ETC___d14669 || WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd1969 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd41 ; // register csrf_rg_dscratch0 @@ -14389,7 +14375,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1970 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd42 ; // register csrf_rg_dscratch1 @@ -14402,7 +14388,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1971 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd43 ; // register csrf_rg_tdata1_data @@ -14415,7 +14401,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1953 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd37 ; // register csrf_rg_tdata1_dmode @@ -14428,7 +14414,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1953 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd37 ; // register csrf_rg_tdata2 @@ -14441,7 +14427,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1954 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd38 ; // register csrf_rg_tdata3 @@ -14454,7 +14440,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1955 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd39 ; // register csrf_rg_tselect @@ -14467,20 +14453,20 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1952 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd36 ; // register csrf_scause_code_reg always@(MUX_csrf_scause_code_reg$write_1__SEL_1 or MUX_csrf_stval_csr$write_1__VAL_1 or MUX_csrf_ie_vec_1$write_1__SEL_2 or - cause_code__h710349 or + cause_code__h710452 or MUX_csrf_scause_code_reg$write_1__SEL_3 or f_csr_reqs$D_OUT) case (1'b1) MUX_csrf_scause_code_reg$write_1__SEL_1: csrf_scause_code_reg$D_IN = MUX_csrf_stval_csr$write_1__VAL_1[3:0]; MUX_csrf_ie_vec_1$write_1__SEL_2: - csrf_scause_code_reg$D_IN = cause_code__h710349; + csrf_scause_code_reg$D_IN = cause_code__h710452; MUX_csrf_scause_code_reg$write_1__SEL_3: csrf_scause_code_reg$D_IN = f_csr_reqs$D_OUT[3:0]; default: csrf_scause_code_reg$D_IN = 4'b1010 /* unspecified value */ ; @@ -14489,11 +14475,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd322 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14700 && - csrf_prv_reg_read__2787_ULE_1_4701_AND_IF_comm_ETC___d14723 || + NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 && + csrf_prv_reg_read__2787_ULE_1_4711_AND_IF_comm_ETC___d14733 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd14 ; // register csrf_scause_interrupt_reg @@ -14516,11 +14502,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd322 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14700 && - csrf_prv_reg_read__2787_ULE_1_4701_AND_IF_comm_ETC___d14723 || + NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 && + csrf_prv_reg_read__2787_ULE_1_4711_AND_IF_comm_ETC___d14733 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd14 ; // register csrf_scounteren_cy_reg @@ -14533,7 +14519,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd262 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd11 ; // register csrf_scounteren_ir_reg @@ -14546,7 +14532,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd262 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd11 ; // register csrf_scounteren_tm_reg @@ -14559,7 +14545,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd262 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd11 ; // register csrf_sepc_csr @@ -14582,11 +14568,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd321 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14700 && - csrf_prv_reg_read__2787_ULE_1_4701_AND_IF_comm_ETC___d14723 || + NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 && + csrf_prv_reg_read__2787_ULE_1_4711_AND_IF_comm_ETC___d14733 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd13 ; // register csrf_software_int_en_vec_0 @@ -14614,7 +14600,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd772 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd22 ; // register csrf_software_int_pend_vec_0 @@ -14658,7 +14644,7 @@ module mkCore(CLK, mmio_pRqQ_data_0[37:36] != 2'd1 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd29 ; // register csrf_spp_reg @@ -14676,8 +14662,8 @@ module mkCore(CLK, endcase assign csrf_spp_reg$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14700 && - csrf_prv_reg_read__2787_ULE_1_4701_AND_IF_comm_ETC___d14723 || + NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 && + csrf_prv_reg_read__2787_ULE_1_4711_AND_IF_comm_ETC___d14733 || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd256 || f_csr_reqs$D_OUT[75:64] == 12'd768) || @@ -14693,7 +14679,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd320 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd12 ; // register csrf_stats_module_doStats @@ -14704,12 +14690,12 @@ module mkCore(CLK, always@(MUX_csrf_stval_csr$write_1__SEL_1 or rob$deqPort_0_deq_data or MUX_csrf_ie_vec_1$write_1__SEL_2 or - trap_val__h710350 or + trap_val__h710453 or MUX_csrf_stval_csr$write_1__SEL_3 or f_csr_reqs$D_OUT) case (1'b1) MUX_csrf_stval_csr$write_1__SEL_1: csrf_stval_csr$D_IN = rob$deqPort_0_deq_data[95:32]; - MUX_csrf_ie_vec_1$write_1__SEL_2: csrf_stval_csr$D_IN = trap_val__h710350; + MUX_csrf_ie_vec_1$write_1__SEL_2: csrf_stval_csr$D_IN = trap_val__h710453; MUX_csrf_stval_csr$write_1__SEL_3: csrf_stval_csr$D_IN = f_csr_reqs$D_OUT[63:0]; default: csrf_stval_csr$D_IN = @@ -14719,11 +14705,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd323 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14700 && - csrf_prv_reg_read__2787_ULE_1_4701_AND_IF_comm_ETC___d14723 || + NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 && + csrf_prv_reg_read__2787_ULE_1_4711_AND_IF_comm_ETC___d14733 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd15 ; // register csrf_stvec_base_hi_reg @@ -14736,7 +14722,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd261 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd10 ; // register csrf_stvec_mode_low_reg @@ -14749,7 +14735,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd261 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd10 ; // register csrf_sum_reg @@ -14792,7 +14778,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd772 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd22 ; // register csrf_timer_int_pend_vec_0 @@ -14826,7 +14812,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd18 ; // register csrf_tvm_reg @@ -14839,7 +14825,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd18 ; // register csrf_tw_reg @@ -14852,7 +14838,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd18 ; // register csrf_vm_mode_sv39_reg @@ -14865,28 +14851,28 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd384 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd17 ; // register flush_brpred assign flush_brpred$D_IN = MUX_commitStage_rg_run_state$write_1__SEL_1 ; assign flush_brpred$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap_4352_BIT_36_4594_AND_co_ETC___d14659 || + commitStage_commitTrap_4362_BIT_36_4604_AND_co_ETC___d14669 || WILL_FIRE_RL_flushBrPred ; // register flush_caches assign flush_caches$D_IN = MUX_commitStage_rg_run_state$write_1__SEL_1 ; assign flush_caches$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap_4352_BIT_36_4594_AND_co_ETC___d14659 || + commitStage_commitTrap_4362_BIT_36_4604_AND_co_ETC___d14669 || WILL_FIRE_RL_flushCaches ; // register flush_reservation assign flush_reservation$D_IN = !MUX_flush_reservation$write_1__SEL_1 ; assign flush_reservation$EN = WILL_FIRE_RL_prepareCachesAndTlbs && flush_reservation || - WILL_FIRE_RL_commitStage_doCommitTrap_handle && _dfoo22 || + WILL_FIRE_RL_commitStage_doCommitTrap_handle && _dfoo20 || WILL_FIRE_RL_commitStage_doCommitSystemInst ; // register flush_tlbs @@ -14894,11 +14880,11 @@ module mkCore(CLK, assign flush_tlbs$EN = WILL_FIRE_RL_prepareCachesAndTlbs && flush_tlbs || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap_4352_BIT_36_4594_AND_co_ETC___d14659 || + commitStage_commitTrap_4362_BIT_36_4604_AND_co_ETC___d14669 || WILL_FIRE_RL_commitStage_doCommitSystemInst && (rob$deqPort_0_deq_data[329:325] == 5'd16 || rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd17) ; // register mmio_cRqQ_clearReq_rl @@ -15198,7 +15184,7 @@ module mkCore(CLK, WILL_FIRE_RL_renameStage_doRenaming_Trap) && csrf_rg_dcsr[2] || WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14199 && + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14209 && csrf_rg_dcsr[2] || WILL_FIRE_RL_rl_debug_resume || WILL_FIRE_RL_rl_debug_halt_req ; @@ -15232,17 +15218,17 @@ module mkCore(CLK, !MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1 ; assign update_vm_info$EN = WILL_FIRE_RL_prepareCachesAndTlbs && update_vm_info || - WILL_FIRE_RL_commitStage_doCommitTrap_handle && _dfoo22 || + WILL_FIRE_RL_commitStage_doCommitTrap_handle && _dfoo20 || WILL_FIRE_RL_commitStage_doCommitSystemInst ; // submodule commitStage_f_rob_data assign commitStage_f_rob_data$D_IN = { rob$deqPort_0_deq_data[425:182], - rob_deqPort_0_deq_data__4344_BIT_181_4419_CONC_ETC___d14510, + rob_deqPort_0_deq_data__4354_BIT_181_4429_CONC_ETC___d14520, rob$deqPort_0_deq_data[168:167], - rob_deqPort_0_deq_data__4344_BIT_166_4360_CONC_ETC___d14409, + rob_deqPort_0_deq_data__4354_BIT_166_4370_CONC_ETC___d14419, rob$deqPort_0_deq_data[161:98], - IF_rob_deqPort_0_deq_data__4344_BITS_97_TO_96__ETC___d14517, + IF_rob_deqPort_0_deq_data__4354_BITS_97_TO_96__ETC___d14527, rob$deqPort_0_deq_data[31:0] } ; assign commitStage_f_rob_data$ENQ = WILL_FIRE_RL_commitStage_doCommitTrap_flush ; @@ -15685,8 +15671,8 @@ module mkCore(CLK, // submodule coreFix_aluExe_1_rsAlu assign coreFix_aluExe_1_rsAlu$enq_x = - (k__h670531 == 1'd1 && - fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14105) ? + (k__h670634 == 1'd1 && + fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14115) ? { fetchStage$pipelines_0_first[199:195], IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d12883, fetchStage$pipelines_0_first[173], @@ -15700,13 +15686,13 @@ module mkCore(CLK, specTagManager$nextSpecTag, sbAggr$eagerLookup_0_get } : { fetchStage$pipelines_1_first[199:195], - IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13589, - fetchStage_pipelines_1_first__2766_BIT_173_359_ETC___d13681, + IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13599, + fetchStage_pipelines_1_first__2766_BIT_173_360_ETC___d13691, fetchStage$pipelines_1_first[160:128], fetchStage$pipelines_1_first[255:232], regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h686145, + renaming_spec_bits__h686248, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -16343,7 +16329,7 @@ module mkCore(CLK, // submodule coreFix_fpuMulDivExe_0_rsFpuMulDiv assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$enq_x = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3408_AND__ETC___d14117) ? + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14127) ? { IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d12883, regRenamingTable$rename_0_getRename, rob$enqPort_0_getEnqInstTag, @@ -16351,10 +16337,10 @@ module mkCore(CLK, fetchStage$pipelines_0_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_0_get } : - { IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13589, + { IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13599, regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h686145, + renaming_spec_bits__h686248, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -16453,9 +16439,9 @@ module mkCore(CLK, assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_enq = WILL_FIRE_RL_renameStage_doRenaming && (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3408_AND__ETC___d14117 || - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14199 && - regRenamingTable_rename_1_canRename__3535_AND__ETC___d14253) ; + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14127 || + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14209 && + regRenamingTable_rename_1_canRename__3545_AND__ETC___d14263) ; assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRobEnqTime = 1'd1 ; assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_doDispatch = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv ; @@ -17303,44 +17289,44 @@ module mkCore(CLK, // submodule coreFix_memExe_lsq assign coreFix_memExe_lsq$enqLd_dst = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3408_AND__ETC___d14143) ? + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14153) ? regRenamingTable$rename_0_getRename[8:0] : regRenamingTable$rename_1_getRename[8:0] ; assign coreFix_memExe_lsq$enqLd_inst_tag = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3408_AND__ETC___d14143) ? + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14153) ? rob$enqPort_0_getEnqInstTag : rob$enqPort_1_getEnqInstTag ; assign coreFix_memExe_lsq$enqLd_mem_inst = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3408_AND__ETC___d14143) ? + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14153) ? fetchStage$pipelines_0_first[191:174] : fetchStage$pipelines_1_first[191:174] ; assign coreFix_memExe_lsq$enqLd_spec_bits = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3408_AND__ETC___d14143) ? + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14153) ? specTagManager$currentSpecBits : - renaming_spec_bits__h686145 ; + renaming_spec_bits__h686248 ; assign coreFix_memExe_lsq$enqSt_dst = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3408_AND__ETC___d14151) ? + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14161) ? regRenamingTable$rename_0_getRename[8:0] : regRenamingTable$rename_1_getRename[8:0] ; assign coreFix_memExe_lsq$enqSt_inst_tag = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3408_AND__ETC___d14151) ? + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14161) ? rob$enqPort_0_getEnqInstTag : rob$enqPort_1_getEnqInstTag ; assign coreFix_memExe_lsq$enqSt_mem_inst = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3408_AND__ETC___d14151) ? + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14161) ? fetchStage$pipelines_0_first[191:174] : fetchStage$pipelines_1_first[191:174] ; assign coreFix_memExe_lsq$enqSt_spec_bits = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3408_AND__ETC___d14151) ? + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14161) ? specTagManager$currentSpecBits : - renaming_spec_bits__h686145 ; + renaming_spec_bits__h686248 ; assign coreFix_memExe_lsq$getHit_t = MUX_coreFix_memExe_lsq$getHit_1__SEL_1 ? MUX_coreFix_memExe_lsq$getHit_1__VAL_1 : @@ -17772,9 +17758,9 @@ module mkCore(CLK, // submodule coreFix_memExe_rsMem assign coreFix_memExe_rsMem$enq_x = (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3408_AND__ETC___d14123) ? + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14133) ? { fetchStage$pipelines_0_first[191:189], - IF_fetchStage_pipelines_0_first__2757_BIT_160__ETC___d14139, + IF_fetchStage_pipelines_0_first__2757_BIT_160__ETC___d14149, regRenamingTable$rename_0_getRename, rob$enqPort_0_getEnqInstTag, specTagManager$currentSpecBits, @@ -17782,10 +17768,10 @@ module mkCore(CLK, specTagManager$nextSpecTag, sbAggr$eagerLookup_0_get } : { fetchStage$pipelines_1_first[191:189], - IF_fetchStage_pipelines_1_first__2766_BIT_160__ETC___d14270, + IF_fetchStage_pipelines_1_first__2766_BIT_160__ETC___d14280, regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h686145, + renaming_spec_bits__h686248, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -18013,7 +17999,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd2816 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd30 ; // submodule csrf_mcycle_ehr_data_dummy2_1 @@ -18027,7 +18013,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd2818 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd31 ; // submodule csrf_minstret_ehr_data_dummy2_1 @@ -18045,7 +18031,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd2049 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd7 ; assign csrf_stats_module_writeQ$DEQ = EN_sendDoStats ; assign csrf_stats_module_writeQ$CLR = 1'b0 ; @@ -18056,7 +18042,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd2048 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd6 ; assign csrf_terminate_module_terminateQ$DEQ = EN_coreIndInv_terminate ; assign csrf_terminate_module_terminateQ$CLR = 1'b0 ; @@ -18075,8 +18061,8 @@ module mkCore(CLK, fetchStage$pipelines_0_canDeq || WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14102 && - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13494 || + NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14112 && + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13504 || WILL_FIRE_RL_renameStage_doRenaming_SystemInst || WILL_FIRE_RL_renameStage_doRenaming_Trap ; assign epochManager$EN_updatePrevEpoch_1_update = @@ -18084,9 +18070,9 @@ module mkCore(CLK, fetchStage$pipelines_1_canDeq && !epochManager$checkEpoch_1_check || WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14199 && - NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d14210 && - IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13907 ; + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14209 && + NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d14220 && + IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13917 ; assign epochManager$EN_incrementEpoch = WILL_FIRE_RL_commitStage_doCommitTrap_flush && !rob$deqPort_0_deq_data[12] || @@ -18234,7 +18220,7 @@ module mkCore(CLK, assign fetchStage$perf_req_r = 2'h0 ; assign fetchStage$perf_setStatus_doStats = 1'b0 ; always@(MUX_commitStage_rg_serial_num$write_1__SEL_1 or - pc__h713293 or + pc__h713396 or WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or coreFix_aluExe_1_exeToFinQ$first or WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or @@ -18248,7 +18234,7 @@ module mkCore(CLK, begin case (1'b1) // synopsys parallel_case MUX_commitStage_rg_serial_num$write_1__SEL_1: - fetchStage$redirect_pc = pc__h713293; + fetchStage$redirect_pc = pc__h713396; WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T: fetchStage$redirect_pc = coreFix_aluExe_1_exeToFinQ$first[82:19]; WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T: @@ -18296,8 +18282,8 @@ module mkCore(CLK, fetchStage$pipelines_0_canDeq || WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14102 && - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13494 || + NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14112 && + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13504 || WILL_FIRE_RL_renameStage_doRenaming_SystemInst || WILL_FIRE_RL_renameStage_doRenaming_Trap ; assign fetchStage$EN_pipelines_1_deq = @@ -18305,9 +18291,9 @@ module mkCore(CLK, fetchStage$pipelines_1_canDeq && !epochManager$checkEpoch_1_check || WILL_FIRE_RL_renameStage_doRenaming && - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14199 && - NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d14210 && - IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13907 ; + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14209 && + NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d14220 && + IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13917 ; assign fetchStage$EN_iTlbIfc_flush = WILL_FIRE_RL_prepareCachesAndTlbs && flush_tlbs || WILL_FIRE_RL_rl_debug_resume ; @@ -18347,14 +18333,14 @@ module mkCore(CLK, assign fetchStage$EN_stop = 1'b0 ; assign fetchStage$EN_setWaitRedirect = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap_4352_BIT_36_4594_AND_co_ETC___d14659 || + commitStage_commitTrap_4362_BIT_36_4604_AND_co_ETC___d14669 || WILL_FIRE_RL_commitStage_doCommitTrap_flush && !rob$deqPort_0_deq_data[12] || WILL_FIRE_RL_renameStage_doRenaming_SystemInst || WILL_FIRE_RL_renameStage_doRenaming_Trap ; assign fetchStage$EN_redirect = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14700 || + NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 || WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T || WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T || WILL_FIRE_RL_commitStage_doCommitKilledLd || @@ -18668,7 +18654,7 @@ module mkCore(CLK, assign regRenamingTable$rename_1_claimRename_r = fetchStage$pipelines_1_first[95:69] ; assign regRenamingTable$rename_1_claimRename_sb = - renaming_spec_bits__h686145 ; + renaming_spec_bits__h686248 ; assign regRenamingTable$rename_1_getRename_r = fetchStage$pipelines_1_first[95:69] ; assign regRenamingTable$specUpdate_correctSpeculation_mask = @@ -18698,8 +18684,8 @@ module mkCore(CLK, assign regRenamingTable$EN_rename_0_claimRename = WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14102 && - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13494 || + NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14112 && + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13504 || WILL_FIRE_RL_renameStage_doRenaming_SystemInst ; assign regRenamingTable$EN_rename_1_claimRename = MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2 ; @@ -18924,7 +18910,7 @@ module mkCore(CLK, fetchStage$pipelines_1_first[199:195], fetchStage$pipelines_1_first[75:69], 136'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, - fetchStage_pipelines_1_first__2766_BIT_173_359_ETC___d13681, + fetchStage_pipelines_1_first__2766_BIT_173_360_ETC___d13691, 73'h1280000000000000000, fetchStage$pipelines_1_first[323:260], 5'd0, @@ -18936,11 +18922,11 @@ module mkCore(CLK, fetchStage$pipelines_1_first[194:192] != 3'd3 && fetchStage$pipelines_1_first[194:192] != 3'd4, fetchStage$pipelines_1_first[194:192] != 3'd2 || - fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14301 || - IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14264, - IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14311, + fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14311 || + IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14274, + IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14321, 7'd32, - renaming_spec_bits__h686145 } ; + renaming_spec_bits__h686248 } ; assign rob$getOrigPC_0_get_x = coreFix_aluExe_0_dispToRegQ$first[52:41] ; assign rob$getOrigPC_1_get_x = coreFix_aluExe_1_dispToRegQ$first[52:41] ; assign rob$getOrigPC_2_get_x = 12'h0 ; @@ -19226,8 +19212,8 @@ module mkCore(CLK, assign rob$EN_enqPort_0_enq = WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14102 && - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13494 || + NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14112 && + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13504 || WILL_FIRE_RL_renameStage_doRenaming_Trap || WILL_FIRE_RL_renameStage_doRenaming_SystemInst ; assign rob$EN_enqPort_1_enq = @@ -19364,8 +19350,8 @@ module mkCore(CLK, assign sbAggr$EN_setBusy_0_set = WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14102 && - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13494 || + NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14112 && + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13504 || WILL_FIRE_RL_renameStage_doRenaming_SystemInst ; assign sbAggr$EN_setBusy_1_set = MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2 ; @@ -19479,8 +19465,8 @@ module mkCore(CLK, assign sbCons$EN_setBusy_0_set = WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14102 && - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13494 || + NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14112 && + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13504 || WILL_FIRE_RL_renameStage_doRenaming_SystemInst ; assign sbCons$EN_setBusy_1_set = MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2 ; @@ -19542,9 +19528,9 @@ module mkCore(CLK, end assign specTagManager$EN_claimSpecTag = WILL_FIRE_RL_renameStage_doRenaming && - (fetchStage_pipelines_0_canDeq__2755_AND_specTa_ETC___d14157 || - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14199 && - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14288) ; + (fetchStage_pipelines_0_canDeq__2755_AND_specTa_ETC___d14167 || + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14209 && + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14298) ; assign specTagManager$EN_specUpdate_incorrectSpeculation = WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T || WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T || @@ -19581,7 +19567,7 @@ module mkCore(CLK, end assign v_f_to_TV_0$ENQ = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14700 || + NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 || WILL_FIRE_RL_commitStage_doCommitNormalInst && rob$deqPort_0_canDeq || WILL_FIRE_RL_commitStage_rl_send_tv_reset || @@ -19592,7 +19578,7 @@ module mkCore(CLK, // submodule v_f_to_TV_1 assign v_f_to_TV_1$D_IN = - { commitStage_rg_serial_num_4333_PLUS_IF_rob_deq_ETC___d15459, + { commitStage_rg_serial_num_4343_PLUS_IF_rob_deq_ETC___d15469, 77'h0AAAAAAAAAAAAAAAAAAA, rob$deqPort_1_deq_data[425:181], CASE_robdeqPort_1_deq_data_BITS_180_TO_169_1__ETC__q300, @@ -19600,9 +19586,9 @@ module mkCore(CLK, rob$deqPort_1_deq_data[161:98], CASE_robdeqPort_1_deq_data_BITS_97_TO_96_0_ro_ETC__q301, rob$deqPort_1_deq_data[95:32], - po_fflags__h731495, + po_fflags__h731598, rob$deqPort_1_deq_data[26], - x__h733638, + x__h733741, 258'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; assign v_f_to_TV_1$ENQ = WILL_FIRE_RL_commitStage_doCommitNormalInst && @@ -19664,7 +19650,7 @@ module mkCore(CLK, { { fetchStage$pipelines_0_first[173], IF_fetchStage_pipelines_0_first__2757_BITS_172_ETC___d12973 }, fetchStage$pipelines_0_first[160], - x_data_imm__h677563 } }), + x_data_imm__h677666 } }), .checkForException_regs({ fetchStage$pipelines_0_first[95], fetchStage$pipelines_0_first[94:89], { fetchStage$pipelines_0_first[88], @@ -19676,10 +19662,10 @@ module mkCore(CLK, .checkForException_csrState({ x_decodeInfo_frm__h655017, r1__read_BITS_13_TO_12___h655202 != 2'd0, - { prv__h735791, - tvm_val__h727180, + { prv__h735894, + tvm_val__h727283, { r1__read_BIT_20___h655898, - tsr_val__h727178, + tsr_val__h727281, { csrf_mcounteren_cy_reg, csrf_mcounteren_cy_reg && csrf_scounteren_cy_reg, @@ -19691,10 +19677,10 @@ module mkCore(CLK, csrf_scounteren_tm_reg } } } } } }), .checkForException(checkForException___d13008)); module_checkForException instance_checkForException_1(.checkForException_dInst({ fetchStage$pipelines_1_first[199:195], - IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13589, - { fetchStage_pipelines_1_first__2766_BIT_173_359_ETC___d13681, + IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13599, + { fetchStage_pipelines_1_first__2766_BIT_173_360_ETC___d13691, fetchStage$pipelines_1_first[160], - x_data_imm__h693617 } }), + x_data_imm__h693720 } }), .checkForException_regs({ fetchStage$pipelines_1_first[95], fetchStage$pipelines_1_first[94:89], { fetchStage$pipelines_1_first[88], @@ -19706,10 +19692,10 @@ module mkCore(CLK, .checkForException_csrState({ x_decodeInfo_frm__h655017, r1__read_BITS_13_TO_12___h655202 != 2'd0, - { prv__h735791, - tvm_val__h727180, + { prv__h735894, + tvm_val__h727283, { r1__read_BIT_20___h655898, - tsr_val__h727178, + tsr_val__h727281, { csrf_mcounteren_cy_reg, csrf_mcounteren_cy_reg && csrf_scounteren_cy_reg, @@ -19719,7 +19705,7 @@ module mkCore(CLK, { csrf_mcounteren_tm_reg, csrf_mcounteren_tm_reg && csrf_scounteren_tm_reg } } } } } }), - .checkForException(checkForException___d13703)); + .checkForException(checkForException___d13713)); module_execFpuSimple instance_execFpuSimple_4(.execFpuSimple_fpu_inst({ coreFix_fpuMulDivExe_0_regToExeQ$first[233:229], CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q259, coreFix_fpuMulDivExe_0_regToExeQ$first[225] }), @@ -21599,7 +21585,7 @@ module mkCore(CLK, fetchStage$pipelines_0_first[231:200] == 32'h10500073 && csrf_tw_reg && csrf_prv_reg != 2'd3 ; - assign IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d13761 = + assign IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d13771 = IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[0] || IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[1] || IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[2] || @@ -21617,8 +21603,8 @@ module mkCore(CLK, IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[14] || IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[15] || checkForException___d13008[4] || - csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13507 ; - assign IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d13798 = + csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13517 ; + assign IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d13808 = IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[0] || IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[1] || IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[2] || @@ -21635,8 +21621,8 @@ module mkCore(CLK, IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[13] || IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[14] || IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[15] || - checkForException___d13703[4] || - csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13796 ; + checkForException___d13713[4] || + csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13806 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10083 = ((f2_exp__h521138 == 8'd0) ? (f2_sfd__h521139[22] ? @@ -22623,44 +22609,44 @@ module mkCore(CLK, coreFix_memExe_dTlb$procResp[12]) ? CASE_coreFix_memExe_dTlbprocResp_BITS_177_TO__ETC__q20 : CASE_coreFix_memExe_dTlbprocResp_BITS_181_TO__ETC__q21 ; - assign IF_NOT_fetchStage_pipelines_0_canDeq__2755_275_ETC___d13913 = + assign IF_NOT_fetchStage_pipelines_0_canDeq__2755_275_ETC___d13923 = ((!fetchStage$pipelines_0_canDeq || - NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13471) && + NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13481) && fetchStage$pipelines_1_canDeq) ? fetchStage$RDY_pipelines_1_first && (fetchStage$pipelines_1_first[194:192] != 3'd1 || !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first) && - IF_fetchStage_RDY_pipelines_1_first__2765_AND__ETC___d13910 : + IF_fetchStage_RDY_pipelines_1_first__2765_AND__ETC___d13920 : !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first ; - assign IF_NOT_fetchStage_pipelines_0_canDeq__2755_275_ETC___d13921 = + assign IF_NOT_fetchStage_pipelines_0_canDeq__2755_275_ETC___d13931 = ((!fetchStage$pipelines_0_canDeq || - NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13471) && + NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13481) && fetchStage$pipelines_1_canDeq) ? - IF_NOT_fetchStage_pipelines_1_first__2766_BITS_ETC___d13920 : + IF_NOT_fetchStage_pipelines_1_first__2766_BITS_ETC___d13930 : fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13918 ; - assign IF_NOT_fetchStage_pipelines_1_first__2766_BITS_ETC___d13836 = + NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13928 ; + assign IF_NOT_fetchStage_pipelines_1_first__2766_BITS_ETC___d13846 = (fetchStage$pipelines_1_first[194:192] == 3'd3 || fetchStage$pipelines_1_first[194:192] == 3'd4) ? - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13819 : + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13829 : ((fetchStage$pipelines_1_first[194:192] == 3'd2) ? (!fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first) && - (regRenamingTable_rename_0_canRename__3408_AND__ETC___d13828 || - NOT_regRenamingTable_rename_1_canRename__3535__ETC___d13806) : - _0_OR_NOT_fetchStage_pipelines_1_first__2766_BI_ETC___d13834) ; - assign IF_NOT_fetchStage_pipelines_1_first__2766_BITS_ETC___d13920 = - NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d13744 ? - IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13907 || + (regRenamingTable_rename_0_canRename__3418_AND__ETC___d13838 || + NOT_regRenamingTable_rename_1_canRename__3545__ETC___d13816) : + _0_OR_NOT_fetchStage_pipelines_1_first__2766_BI_ETC___d13844) ; + assign IF_NOT_fetchStage_pipelines_1_first__2766_BITS_ETC___d13930 = + NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d13754 ? + IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13917 || fetchStage$pipelines_0_canDeq && (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3408_AND__ETC___d13484 && - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13494 : + regRenamingTable_rename_0_canRename__3418_AND__ETC___d13494 && + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13504 : fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13918 ; + NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13928 ; assign IF_NOT_renameStage_rg_m_halt_req_2784_BIT_4_27_ETC___d13283 = NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13102 ? IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13210 : @@ -22718,7 +22704,7 @@ module mkCore(CLK, 4'd9) ? 4'd14 : 4'd15)))))))))) ; - assign IF_NOT_rob_deqPort_1_deq_data__5346_BIT_25_534_ETC___d15675 = + assign IF_NOT_rob_deqPort_1_deq_data__5356_BIT_25_535_ETC___d15685 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[329:325] == 5'd0 || @@ -22953,16 +22939,16 @@ module mkCore(CLK, checkForException___d13008[4] ? CASE_checkForException_3008_BITS_3_TO_0_0_chec_ETC__q234 : 4'd2 ; - assign IF_commitStage_f_rob_data_first__4760_BITS_97__ETC___d14931 = + assign IF_commitStage_f_rob_data_first__4770_BITS_97__ETC___d14941 = { CASE_commitStage_f_rob_dataD_OUT_BITS_97_TO_9_ETC__q249, commitStage_f_rob_data$D_OUT[95:32], 5'h0A, commitStage_f_rob_data$D_OUT[26], 64'hAAAAAAAAAAAAAAAA, - x_prv__h713393, - pc__h713293, - x__h715551, - x__h715743, + x_prv__h713496, + pc__h713396, + x__h715654, + x__h715846, commitStage_commitTrap[164:101] } ; assign IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2181_ETC___d12213 = (coreFix_aluExe_0_dispToRegQ$RDY_first && @@ -24174,10 +24160,10 @@ module mkCore(CLK, coreFix_memExe_respLrScAmoQ_enqReq_rl[64] ; assign IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8 = csrf_minstret_ehr_data_lat_0$whas ? - upd__h727675 : + upd__h727778 : csrf_minstret_ehr_data_rl ; - assign IF_csrf_prv_reg_read__2787_ULE_1_4701_AND_IF_c_ETC___d14925 = - csrf_prv_reg_read__2787_ULE_1_4701_AND_IF_comm_ETC___d14723 ? + assign IF_csrf_prv_reg_read__2787_ULE_1_4711_AND_IF_c_ETC___d14935 = + csrf_prv_reg_read__2787_ULE_1_4711_AND_IF_comm_ETC___d14733 ? { 43'd8192, csrf_mxr_reg, csrf_sum_reg, @@ -24209,73 +24195,73 @@ module mkCore(CLK, 2'd0, csrf_ie_vec_1, csrf_ie_vec_0 } ; - assign IF_fetchStage_RDY_pipelines_0_first__2754_AND__ETC___d13440 = + assign IF_fetchStage_RDY_pipelines_0_first__2754_AND__ETC___d13450 = (fetchStage$RDY_pipelines_0_first && (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3408_AND__ETC___d13434) ? + regRenamingTable_rename_0_canRename__3418_AND__ETC___d13444) ? fetchStage$RDY_pipelines_0_first : !regRenamingTable$rename_0_canRename || fetchStage$RDY_pipelines_0_first ; - assign IF_fetchStage_RDY_pipelines_1_first__2765_AND__ETC___d13838 = + assign IF_fetchStage_RDY_pipelines_1_first__2765_AND__ETC___d13848 = (fetchStage$RDY_pipelines_1_first && (fetchStage$pipelines_1_first[194:192] == 3'd0 || fetchStage$pipelines_1_first[194:192] == 3'd1)) ? (!fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first) && - (SEL_ARR_fetchStage_pipelines_0_canDeq__2755_AN_ETC___d13777 || + (SEL_ARR_fetchStage_pipelines_0_canDeq__2755_AN_ETC___d13787 || fetchStage$pipelines_1_first[194:192] == 3'd1 && - regRenamingTable_rename_0_canRename__3408_AND__ETC___d13498 || - NOT_regRenamingTable_rename_1_canRename__3535__ETC___d13806) : + regRenamingTable_rename_0_canRename__3418_AND__ETC___d13508 || + NOT_regRenamingTable_rename_1_canRename__3545__ETC___d13816) : fetchStage$RDY_pipelines_1_first && - IF_NOT_fetchStage_pipelines_1_first__2766_BITS_ETC___d13836 ; - assign IF_fetchStage_RDY_pipelines_1_first__2765_AND__ETC___d13910 = + IF_NOT_fetchStage_pipelines_1_first__2766_BITS_ETC___d13846 ; + assign IF_fetchStage_RDY_pipelines_1_first__2765_AND__ETC___d13920 = (fetchStage$RDY_pipelines_1_first && - NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d13505 && - NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d13744) ? - IF_fetchStage_RDY_pipelines_1_first__2765_AND__ETC___d13838 && - (IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13907 || + NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d13515 && + NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d13754) ? + IF_fetchStage_RDY_pipelines_1_first__2765_AND__ETC___d13848 && + (IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13917 || !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first) : !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first ; - assign IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13959 = - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13952 || - fetchStage$RDY_pipelines_0_deq && + assign IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13969 = + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13962 || + rob$RDY_enqPort_0_enq && regRenamingTable$RDY_rename_0_getRename && regRenamingTable$RDY_rename_0_claimRename && - rob$RDY_enqPort_0_enq && + fetchStage$RDY_pipelines_0_deq && (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$RDY_claimSpecTag) ; - assign IF_fetchStage_pipelines_0_first__2757_BIT_160__ETC___d14139 = + assign IF_fetchStage_pipelines_0_first__2757_BIT_160__ETC___d14149 = { fetchStage$pipelines_0_first[159:128], - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14127, - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14130 ? - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14133 : + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14137, + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14140 ? + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14143 : { 1'h0, - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14136 } } ; - assign IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14089 = - IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14046 && - IF_fetchStage_RDY_pipelines_1_first__2765_AND__ETC___d13838 && - (IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14073 || - fetchStage$RDY_pipelines_1_deq && + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14146 } } ; + assign IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14099 = + IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14056 && + IF_fetchStage_RDY_pipelines_1_first__2765_AND__ETC___d13848 && + (IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14083 || + rob$RDY_enqPort_1_enq && regRenamingTable$RDY_rename_1_getRename && regRenamingTable$RDY_rename_1_claimRename && - rob_RDY_enqPort_1_enq__4075_AND_NOT_fetchStage_ETC___d14083) ; - assign IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14311 = + fetchStage_RDY_pipelines_1_deq__2769_AND_NOT_f_ETC___d14093) ; + assign IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14321 = (fetchStage$pipelines_1_first[194:192] == 3'd2 && - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14258 && - IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14265) ? - IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14266 : + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14268 && + IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14275) ? + IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14276 : { 1'h0, - IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14267 } ; - assign IF_fetchStage_pipelines_1_first__2766_BIT_160__ETC___d14270 = + IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14277 } ; + assign IF_fetchStage_pipelines_1_first__2766_BIT_160__ETC___d14280 = { fetchStage$pipelines_1_first[159:128], - IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14264, - IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14265 ? - IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14266 : + IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14274, + IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14275 ? + IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14276 : { 1'h0, - IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14267 } } ; + IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14277 } } ; assign IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmio_c_ETC___d339 = mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[142] : @@ -24300,17 +24286,17 @@ module mkCore(CLK, EN_mmioToPlatform_pRs_enq ? mmio_pRsQ_enqReq_lat_0$wget[67] : mmio_pRsQ_enqReq_rl[67] ; - assign IF_rob_deqPort_0_canDeq__5338_THEN_IF_NOT_rob__ETC___d15665 = - rob$deqPort_0_canDeq ? y_avValue_fst__h730870 : 5'd0 ; - assign IF_rob_deqPort_0_canDeq__5338_THEN_IF_NOT_rob__ETC___d15684 = + assign IF_rob_deqPort_0_canDeq__5348_THEN_IF_NOT_rob__ETC___d15675 = + rob$deqPort_0_canDeq ? y_avValue_fst__h730973 : 5'd0 ; + assign IF_rob_deqPort_0_canDeq__5348_THEN_IF_NOT_rob__ETC___d15694 = rob$deqPort_0_canDeq ? - y_avValue_snd_snd_snd_fst__h731345 : + y_avValue_snd_snd_snd_fst__h731448 : 2'd0 ; - assign IF_rob_deqPort_0_deq_data__4344_BITS_329_TO_32_ETC___d15196 = + assign IF_rob_deqPort_0_deq_data__4354_BITS_329_TO_32_ETC___d15206 = (rob$deqPort_0_deq_data[329:325] == 5'd19) ? csrf_sepc_csr : csrf_mepc_csr ; - assign IF_rob_deqPort_0_deq_data__4344_BITS_329_TO_32_ETC___d15306 = + assign IF_rob_deqPort_0_deq_data__4354_BITS_329_TO_32_ETC___d15316 = (rob$deqPort_0_deq_data[329:325] == 5'd19) ? { csrf_mpp_reg, 3'd0, @@ -24330,12 +24316,12 @@ module mkCore(CLK, 1'b0, csrf_ie_vec_1, csrf_ie_vec_0 } ; - assign IF_rob_deqPort_0_deq_data__4344_BITS_97_TO_96__ETC___d14517 = + assign IF_rob_deqPort_0_deq_data__4354_BITS_97_TO_96__ETC___d14527 = { CASE_robdeqPort_0_deq_data_BITS_97_TO_96_0_ro_ETC__q252, rob$deqPort_0_deq_data[95:32] } ; - assign IF_rob_deqPort_1_canDeq__5343_THEN_IF_NOT_rob__ETC___d15676 = + assign IF_rob_deqPort_1_canDeq__5353_THEN_IF_NOT_rob__ETC___d15686 = rob$deqPort_1_canDeq ? - IF_NOT_rob_deqPort_1_deq_data__5346_BIT_25_534_ETC___d15675 : + IF_NOT_rob_deqPort_1_deq_data__5356_BIT_25_535_ETC___d15685 : rob$deqPort_0_canDeq && rob$deqPort_0_deq_data[26] ; assign IF_sfdin11103_BIT_4_THEN_2_ELSE_0__q139 = sfdin__h511103[4] ? 2'd2 : 2'd0 ; @@ -24431,7 +24417,7 @@ module mkCore(CLK, (fetchStage$pipelines_0_first[231:200] != 32'h10500073 || !csrf_tw_reg || csrf_prv_reg == 2'd3) ; - assign NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13427 = + assign NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13437 = !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[0] && !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[1] && !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[2] && @@ -24449,8 +24435,8 @@ module mkCore(CLK, !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[14] && !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[15] && !checkForException___d13008[4] && - NOT_csrf_fs_reg_read__1546_EQ_0_2997_2998_OR_N_ETC___d13425 ; - assign NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13730 = + NOT_csrf_fs_reg_read__1546_EQ_0_2997_2998_OR_N_ETC___d13435 ; + assign NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13740 = !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[0] && !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[1] && !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[2] && @@ -24467,13 +24453,13 @@ module mkCore(CLK, !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[13] && !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[14] && !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[15] && - !checkForException___d13703[4] && - NOT_csrf_fs_reg_read__1546_EQ_0_2997_2998_OR_N_ETC___d13728 ; - assign NOT_IF_NOT_rob_deqPort_0_canDeq__5338_5339_OR__ETC___d15681 = - (fflags__h734124 & csrf_fflags_reg) != fflags__h734124 || + !checkForException___d13713[4] && + NOT_csrf_fs_reg_read__1546_EQ_0_2997_2998_OR_N_ETC___d13738 ; + assign NOT_IF_NOT_rob_deqPort_0_canDeq__5348_5349_OR__ETC___d15691 = + (fflags__h734227 & csrf_fflags_reg) != fflags__h734227 || csrf_fs_reg != 2'b11 && - (IF_rob_deqPort_1_canDeq__5343_THEN_IF_NOT_rob__ETC___d15676 || - fflags__h734124 != 5'd0) ; + (IF_rob_deqPort_1_canDeq__5353_THEN_IF_NOT_rob__ETC___d15686 || + fflags__h734227 != 5'd0) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10056 = !f2_sfd__h521139[21] && !f2_sfd__h521139[20] && !f2_sfd__h521139[19] && @@ -24595,12 +24581,12 @@ module mkCore(CLK, !f3_sfd__h560443[2] && !f3_sfd__h560443[1] && !f3_sfd__h560443[0] ; - assign NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13489 = - !SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__344_ETC___d13487 && + assign NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13499 = + !SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__345_ETC___d13497 && (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3408_AND__ETC___d13434 ; - assign NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14629 = + regRenamingTable_rename_0_canRename__3418_AND__ETC___d13444 ; + assign NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14639 = (!commitStage_commitTrap[36] || commitStage_commitTrap[35:32] == 4'd0 || commitStage_commitTrap[35:32] == 4'd1 || @@ -24614,12 +24600,12 @@ module mkCore(CLK, (commitStage_commitTrap[36] || commitStage_commitTrap[35:32] != 4'd3 || CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q243) ; - assign NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14636 = - NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14629 || + assign NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14646 = + NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14639 || coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty && fetchStage$iTlbIfc_noPendingReq && coreFix_memExe_dTlb$noPendingReq ; - assign NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14700 = + assign NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 = (!commitStage_commitTrap[36] || commitStage_commitTrap[35:32] != 4'd14) && (!commitStage_commitTrap[36] || @@ -24636,13 +24622,13 @@ module mkCore(CLK, (commitStage_commitTrap[36] || commitStage_commitTrap[35:32] != 4'd3 || CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q243) ; - assign NOT_commitStage_rg_run_state_4350_4351_AND_NOT_ETC___d15010 = + assign NOT_commitStage_rg_run_state_4360_4361_AND_NOT_ETC___d15020 = !commitStage_rg_run_state && !commitStage_commitTrap[165] && !rob$deqPort_0_deq_data[167] && !rob$deqPort_0_deq_data[18] && rob$deqPort_0_deq_data[25] ; - assign NOT_commitStage_rg_run_state_4350_4351_AND_NOT_ETC___d15021 = - NOT_commitStage_rg_run_state_4350_4351_AND_NOT_ETC___d15010 && + assign NOT_commitStage_rg_run_state_4360_4361_AND_NOT_ETC___d15031 = + NOT_commitStage_rg_run_state_4360_4361_AND_NOT_ETC___d15020 && (rob$deqPort_0_deq_data[329:325] == 5'd0 || rob$deqPort_0_deq_data[329:325] == 5'd21 || rob$deqPort_0_deq_data[329:325] == 5'd17 || @@ -24652,9 +24638,9 @@ module mkCore(CLK, rob$deqPort_0_deq_data[329:325] == 5'd15 || rob$deqPort_0_deq_data[329:325] == 5'd19 || rob$deqPort_0_deq_data[329:325] == 5'd20) && - _0b0_CONCAT_csrf_external_int_pend_vec_3_read___ETC___d14329 ; - assign NOT_commitStage_rg_run_state_4350_4351_AND_NOT_ETC___d15392 = - NOT_commitStage_rg_run_state_4350_4351_AND_NOT_ETC___d15010 && + _0b0_CONCAT_csrf_external_int_pend_vec_3_read___ETC___d14339 ; + assign NOT_commitStage_rg_run_state_4360_4361_AND_NOT_ETC___d15402 = + NOT_commitStage_rg_run_state_4360_4361_AND_NOT_ETC___d15020 && rob$deqPort_0_deq_data[329:325] != 5'd0 && rob$deqPort_0_deq_data[329:325] != 5'd21 && rob$deqPort_0_deq_data[329:325] != 5'd17 && @@ -24664,7 +24650,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[329:325] != 5'd15 && rob$deqPort_0_deq_data[329:325] != 5'd19 && rob$deqPort_0_deq_data[329:325] != 5'd20 && - _0b0_CONCAT_csrf_external_int_pend_vec_3_read___ETC___d14329 ; + _0b0_CONCAT_csrf_external_int_pend_vec_3_read___ETC___d14339 ; assign NOT_coreFix_aluExe_0_bypassWire_0_whas__2202_2_ETC___d12229 = (!coreFix_aluExe_0_bypassWire_0$whas || !coreFix_aluExe_0_bypassWire_0_wget__2203_BITS__ETC___d12205) && @@ -25170,7 +25156,7 @@ module mkCore(CLK, NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13331 && !csrf_prv_reg_read__2787_ULT_IF_fetchStage_pipe_ETC___d13040 && csr_addr__h655332 != 12'h8FF) ; - assign NOT_csrf_fs_reg_read__1546_EQ_0_2997_2998_OR_N_ETC___d13425 = + assign NOT_csrf_fs_reg_read__1546_EQ_0_2997_2998_OR_N_ETC___d13435 = (csrf_fs_reg != 2'd0 || (!fetchStage$pipelines_0_first[95] || !fetchStage$pipelines_0_first[94]) && @@ -25182,7 +25168,7 @@ module mkCore(CLK, (fetchStage$pipelines_0_first[231:200] != 32'h10500073 || !csrf_tw_reg || csrf_prv_reg == 2'd3) ; - assign NOT_csrf_fs_reg_read__1546_EQ_0_2997_2998_OR_N_ETC___d13728 = + assign NOT_csrf_fs_reg_read__1546_EQ_0_2997_2998_OR_N_ETC___d13738 = (csrf_fs_reg != 2'd0 || (!fetchStage$pipelines_1_first[95] || !fetchStage$pipelines_1_first[94]) && @@ -25194,102 +25180,102 @@ module mkCore(CLK, (fetchStage$pipelines_1_first[231:200] != 32'h10500073 || !csrf_tw_reg || csrf_prv_reg == 2'd3) ; - assign NOT_csrf_prv_reg_read__2787_ULE_1_4701_4743_OR_ETC___d14747 = - !csrf_prv_reg_read__2787_ULE_1___d14701 || + assign NOT_csrf_prv_reg_read__2787_ULE_1_4711_4753_OR_ETC___d14757 = + !csrf_prv_reg_read__2787_ULE_1___d14711 || (commitStage_commitTrap[36] ? - !_0b0_CONCAT_csrf_mideleg_11_reg_read__1653_1654_ETC___d14703 : - !_0b0_CONCAT_csrf_medeleg_15_reg_read__1645_1646_ETC___d14721) ; - assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13532 = + !_0b0_CONCAT_csrf_mideleg_11_reg_read__1653_1654_ETC___d14713 : + !_0b0_CONCAT_csrf_medeleg_15_reg_read__1645_1646_ETC___d14731) ; + assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13542 = !fetchStage$pipelines_0_canDeq || !regRenamingTable$rename_0_canRename || - fetchStage_pipelines_0_first__2757_BITS_199_TO_ETC___d13514 || - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13529 || + fetchStage_pipelines_0_first__2757_BITS_199_TO_ETC___d13524 || + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13539 || fetchStage$pipelines_0_first[194:192] != 3'd1 ; - assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13775 = + assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13785 = (!fetchStage$pipelines_0_canDeq || fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || - NOT_regRenamingTable_rename_0_canRename__3408__ETC___d13766 || + NOT_regRenamingTable_rename_0_canRename__3418__ETC___d13776 || fetchStage$pipelines_0_first[194:192] != 3'd0 && fetchStage$pipelines_0_first[194:192] != 3'd1 || - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3443_co_ETC___d13453) && + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463) && coreFix_aluExe_1_rsAlu$canEnq && - !coreFix_aluExe_0_rsAlu_approximateCount__3447__ETC___d13449 ; - assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13819 = + !coreFix_aluExe_0_rsAlu_approximateCount__3457__ETC___d13459 ; + assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13829 = (!fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first) && - (regRenamingTable_rename_0_canRename__3408_AND__ETC___d13484 && + (regRenamingTable_rename_0_canRename__3418_AND__ETC___d13494 && (fetchStage$pipelines_0_first[194:192] == 3'd3 || fetchStage$pipelines_0_first[194:192] == 3'd4) || !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq || - NOT_regRenamingTable_rename_1_canRename__3535__ETC___d13806) ; - assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13874 = + NOT_regRenamingTable_rename_1_canRename__3545__ETC___d13816) ; + assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13884 = !fetchStage$pipelines_0_canDeq || !regRenamingTable$rename_0_canRename || - fetchStage_pipelines_0_first__2757_BITS_199_TO_ETC___d13514 || + fetchStage_pipelines_0_first__2757_BITS_199_TO_ETC___d13524 || fetchStage$pipelines_0_first[194:192] != 3'd3 && fetchStage$pipelines_0_first[194:192] != 3'd4 ; - assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13892 = + assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13902 = (!fetchStage$pipelines_0_canDeq || - NOT_regRenamingTable_rename_0_canRename__3408__ETC___d13842 || + NOT_regRenamingTable_rename_0_canRename__3418__ETC___d13852 || fetchStage$pipelines_0_first[194:192] != 3'd2 || - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13524) && + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13534) && coreFix_memExe_rsMem$canEnq && CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q238 ; - assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14041 = + assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14051 = (!fetchStage$pipelines_0_canDeq || - NOT_specTagManager_canClaim__3406_3497_OR_NOT__ETC___d14012) && + NOT_specTagManager_canClaim__3416_3507_OR_NOT__ETC___d14022) && CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q242 && (fetchStage$pipelines_1_first[199:195] == 5'd14 || coreFix_memExe_rsMem$RDY_enq) ; - assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14095 = + assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14105 = (!fetchStage$pipelines_0_canDeq || - fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13961 && - IF_fetchStage_RDY_pipelines_0_first__2754_AND__ETC___d13440) && + fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13971 && + IF_fetchStage_RDY_pipelines_0_first__2754_AND__ETC___d13450) && fetchStage$RDY_pipelines_0_first && - fetchStage_pipelines_0_canDeq__2755_AND_fetchS_ETC___d14093 ; - assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14194 = + fetchStage_pipelines_0_canDeq__2755_AND_fetchS_ETC___d14103 ; + assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14204 = (!fetchStage$pipelines_0_canDeq || fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || - NOT_regRenamingTable_rename_0_canRename__3408__ETC___d14189 || + NOT_regRenamingTable_rename_0_canRename__3418__ETC___d14199 || fetchStage$pipelines_0_first[194:192] != 3'd0 && fetchStage$pipelines_0_first[194:192] != 3'd1 || - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3443_co_ETC___d13453) && + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463) && coreFix_aluExe_1_rsAlu$canEnq && - !coreFix_aluExe_0_rsAlu_approximateCount__3447__ETC___d13449 ; - assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14199 = + !coreFix_aluExe_0_rsAlu_approximateCount__3457__ETC___d13459 ; + assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14209 = (!fetchStage$pipelines_0_canDeq || - NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14102 && - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13470) && + NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14112 && + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13480) && fetchStage$pipelines_1_canDeq ; - assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14201 = + assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14211 = !fetchStage$pipelines_0_canDeq || !regRenamingTable$rename_0_canRename || - renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13925 || - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13529 || + renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13935 || + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13539 || fetchStage$pipelines_0_first[194:192] != 3'd1 ; - assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14213 = - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14199 && - NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d14210 && + assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14223 = + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14209 && + NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d14220 && (fetchStage$pipelines_1_first[194:192] == 3'd0 || fetchStage$pipelines_1_first[194:192] == 3'd1) && - SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__275_ETC___d14007 ; - assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14257 = + SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__275_ETC___d14017 ; + assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14267 = !fetchStage$pipelines_0_canDeq || !regRenamingTable$rename_0_canRename || - renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13925 || + renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13935 || fetchStage$pipelines_0_first[194:192] != 3'd2 || - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13524 ; - assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14258 = - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14257 && + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13534 ; + assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14268 = + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14267 && coreFix_memExe_rsMem$canEnq && CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q238 ; - assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14288 = - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14201 && + assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14298 = + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14211 && specTagManager$canClaim && - regRenamingTable_rename_1_canRename__3535_AND__ETC___d14209 && - IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13907 && + regRenamingTable_rename_1_canRename__3545_AND__ETC___d14219 && + IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13917 && fetchStage$pipelines_1_first[194:192] == 3'd1 ; assign NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13331 = (fetchStage$pipelines_0_first[194:192] != 3'd0 || @@ -25297,54 +25283,54 @@ module mkCore(CLK, rs1__h655333 == 5'd0 && imm__h655334 == 32'd0 || csr_addr__h655332[11:10] != 2'b11 ; - assign NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13471 = + assign NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13481 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3408_AND__ETC___d13434 && - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13470 ; - assign NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13751 = + regRenamingTable_rename_0_canRename__3418_AND__ETC___d13444 && + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13480 ; + assign NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13761 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3408_AND__ETC___d13434 && - fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13750 ; - assign NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13757 = + regRenamingTable_rename_0_canRename__3418_AND__ETC___d13444 && + fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13760 ; + assign NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13767 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3408_AND__ETC___d13434 && + regRenamingTable_rename_0_canRename__3418_AND__ETC___d13444 && (fetchStage$pipelines_0_first[194:192] == 3'd0 || fetchStage$pipelines_0_first[194:192] == 3'd1) && - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3443_co_ETC___d13453 && + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463 && (!coreFix_aluExe_0_rsAlu$canEnq || - !coreFix_aluExe_0_rsAlu_approximateCount__3447__ETC___d13449) ; - assign NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13918 = + !coreFix_aluExe_0_rsAlu_approximateCount__3457__ETC___d13459) ; + assign NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13928 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3408_AND__ETC___d13434 && - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13494 ; - assign NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14102 = + regRenamingTable_rename_0_canRename__3418_AND__ETC___d13444 && + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13504 ; + assign NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14112 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && regRenamingTable$rename_0_canRename && !checkForException___d13008[4] && rob$enqPort_0_canEnq ; - assign NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14171 = + assign NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14181 = { fetchStage$pipelines_0_first[194:192] != 3'd2 || !coreFix_memExe_rsMem$canEnq || - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13524 || - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14127, + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13534 || + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14137, (fetchStage$pipelines_0_first[194:192] == 3'd2 && coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13466 && - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14130) ? - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14133 : + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13476 && + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14140) ? + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14143 : { 1'h0, - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14136 }, + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14146 }, 7'd32, specTagManager$currentSpecBits } ; - assign NOT_fetchStage_pipelines_0_first__2757_BIT_68__ETC___d13482 = + assign NOT_fetchStage_pipelines_0_first__2757_BIT_68__ETC___d13492 = !fetchStage$pipelines_0_first[68] && !checkForException___d13008[4] && - NOT_csrf_fs_reg_read__1546_EQ_0_2997_2998_OR_N_ETC___d13425 && + NOT_csrf_fs_reg_read__1546_EQ_0_2997_2998_OR_N_ETC___d13435 && rob$enqPort_0_canEnq && epochManager$checkEpoch_0_check ; assign NOT_fetchStage_pipelines_1_canDeq__2763_2764_O_ETC___d12772 = @@ -25352,36 +25338,36 @@ module mkCore(CLK, fetchStage$RDY_pipelines_1_first && (epochManager$checkEpoch_1_check || fetchStage$RDY_pipelines_1_deq) ; - assign NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d13505 = + assign NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d13515 = (fetchStage$pipelines_1_first[194:192] != 3'd1 || !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first) && (fetchStage$RDY_pipelines_0_first && fetchStage$pipelines_1_first[194:192] == 3'd1 && - regRenamingTable_rename_0_canRename__3408_AND__ETC___d13498 || - csrf_rg_dcsr_read__1720_BIT_2_3062_OR_NOT_fetc_ETC___d13503) ; - assign NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d13744 = + regRenamingTable_rename_0_canRename__3418_AND__ETC___d13508 || + csrf_rg_dcsr_read__1720_BIT_2_3062_OR_NOT_fetc_ETC___d13513) ; + assign NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d13754 = (fetchStage$pipelines_1_first[194:192] != 3'd1 || - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13532 && + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13542 && specTagManager$canClaim) && - regRenamingTable_rename_1_canRename__3535_AND__ETC___d13743 ; - assign NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d13861 = + regRenamingTable_rename_1_canRename__3545_AND__ETC___d13753 ; + assign NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d13871 = (fetchStage$pipelines_1_first[194:192] != 3'd1 || (!fetchStage$pipelines_0_canDeq || - NOT_regRenamingTable_rename_0_canRename__3408__ETC___d13842 || - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13855 || + NOT_regRenamingTable_rename_0_canRename__3418__ETC___d13852 || + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13865 || fetchStage$pipelines_0_first[194:192] != 3'd1) && specTagManager$canClaim) && - regRenamingTable_rename_1_canRename__3535_AND__ETC___d13743 ; - assign NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d14210 = + regRenamingTable_rename_1_canRename__3545_AND__ETC___d13753 ; + assign NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d14220 = (fetchStage$pipelines_1_first[194:192] != 3'd1 || - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14201 && + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14211 && specTagManager$canClaim) && - regRenamingTable_rename_1_canRename__3535_AND__ETC___d14209 ; - assign NOT_fetchStage_pipelines_1_first__2766_BIT_68__ETC___d14207 = + regRenamingTable_rename_1_canRename__3545_AND__ETC___d14219 ; + assign NOT_fetchStage_pipelines_1_first__2766_BIT_68__ETC___d14217 = !fetchStage$pipelines_1_first[68] && - !checkForException___d13703[4] && - NOT_csrf_fs_reg_read__1546_EQ_0_2997_2998_OR_N_ETC___d13728 && + !checkForException___d13713[4] && + NOT_csrf_fs_reg_read__1546_EQ_0_2997_2998_OR_N_ETC___d13738 && rob$enqPort_1_canEnq && epochManager$checkEpoch_1_check && !csrf_rg_dcsr[2] ; @@ -25464,7 +25450,7 @@ module mkCore(CLK, (mmio_pRsQ_deqReq_dummy2_2$Q_OUT && (mmio_pRsQ_deqReq_lat_0$whas || mmio_pRsQ_deqReq_rl) || mmio_pRsQ_empty) ; - assign NOT_regRenamingTable_rename_0_canRename__3408__ETC___d13766 = + assign NOT_regRenamingTable_rename_0_canRename__3418__ETC___d13776 = !regRenamingTable$rename_0_canRename || fetchStage$pipelines_0_first[199:195] == 5'd0 || fetchStage$pipelines_0_first[199:195] == 5'd21 || @@ -25475,8 +25461,8 @@ module mkCore(CLK, fetchStage$pipelines_0_first[199:195] == 5'd15 || fetchStage$pipelines_0_first[199:195] == 5'd19 || fetchStage$pipelines_0_first[199:195] == 5'd20 || - renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13764 ; - assign NOT_regRenamingTable_rename_0_canRename__3408__ETC___d13842 = + renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13774 ; + assign NOT_regRenamingTable_rename_0_canRename__3418__ETC___d13852 = !regRenamingTable$rename_0_canRename || fetchStage$pipelines_0_first[199:195] == 5'd0 || fetchStage$pipelines_0_first[199:195] == 5'd21 || @@ -25487,14 +25473,14 @@ module mkCore(CLK, fetchStage$pipelines_0_first[199:195] == 5'd15 || fetchStage$pipelines_0_first[199:195] == 5'd19 || fetchStage$pipelines_0_first[199:195] == 5'd20 || - fetchStage_pipelines_0_first__2757_BIT_68_2786_ETC___d13840 ; - assign NOT_regRenamingTable_rename_0_canRename__3408__ETC___d14189 = + fetchStage_pipelines_0_first__2757_BIT_68_2786_ETC___d13850 ; + assign NOT_regRenamingTable_rename_0_canRename__3418__ETC___d14199 = !regRenamingTable$rename_0_canRename || renameStage_rg_m_halt_req[4] || fetchStage$pipelines_0_first[68] || checkForException___d13008[4] || !rob$enqPort_0_canEnq ; - assign NOT_regRenamingTable_rename_1_canRename__3535__ETC___d13806 = + assign NOT_regRenamingTable_rename_1_canRename__3545__ETC___d13816 = !regRenamingTable$rename_1_canRename || fetchStage$pipelines_1_first[199:195] == 5'd0 || fetchStage$pipelines_1_first[199:195] == 5'd21 || @@ -25505,7 +25491,7 @@ module mkCore(CLK, fetchStage$pipelines_1_first[199:195] == 5'd15 || fetchStage$pipelines_1_first[199:195] == 5'd19 || fetchStage$pipelines_1_first[199:195] == 5'd20 || - renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13804 ; + renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13814 ; assign NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13102 = !renameStage_rg_m_halt_req[4] && (fetchStage$pipelines_0_first[68] || @@ -25525,38 +25511,38 @@ module mkCore(CLK, !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[13] && !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[14] && !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[15]) ; - assign NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13432 = + assign NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13442 = !renameStage_rg_m_halt_req[4] && !fetchStage$pipelines_0_first[68] && - NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13427 && + NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13437 && rob$enqPort_0_canEnq && epochManager$checkEpoch_0_check ; - assign NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13741 = + assign NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13751 = !renameStage_rg_m_halt_req[4] && !fetchStage$pipelines_1_first[68] && - NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13730 && + NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13740 && rob$enqPort_1_canEnq && - epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13739 ; - assign NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13883 = + epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13749 ; + assign NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13893 = !renameStage_rg_m_halt_req[4] && !fetchStage$pipelines_1_first[68] && - NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13730 && + NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13740 && rob$enqPort_1_canEnq && - epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13881 ; - assign NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13901 = + epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13891 ; + assign NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13911 = !renameStage_rg_m_halt_req[4] && !fetchStage$pipelines_1_first[68] && - NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13730 && + NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13740 && rob$enqPort_1_canEnq && - epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13899 ; - assign NOT_rob_deqPort_0_canDeq__5338_5339_OR_regRena_ETC___d15380 = + epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13909 ; + assign NOT_rob_deqPort_0_canDeq__5348_5349_OR_rob_RDY_ETC___d15390 = (!rob$deqPort_0_canDeq || - regRenamingTable$RDY_commit_0_commit && rob$RDY_deqPort_0_deq && + rob$RDY_deqPort_0_deq && regRenamingTable$RDY_commit_0_commit && v_f_to_TV_0$FULL_N) && (!rob$deqPort_1_canDeq || rob$RDY_deqPort_1_deq_data && - NOT_rob_deqPort_1_deq_data__5346_BIT_25_5347_5_ETC___d15377) ; - assign NOT_rob_deqPort_0_canDeq__5338_5339_OR_rob_deq_ETC___d15659 = + NOT_rob_deqPort_1_deq_data__5356_BIT_25_5357_5_ETC___d15387) ; + assign NOT_rob_deqPort_0_canDeq__5348_5349_OR_rob_deq_ETC___d15669 = (!rob$deqPort_0_canDeq || rob$deqPort_0_deq_data[25] && !rob$deqPort_0_deq_data[18] && !rob$deqPort_0_deq_data[167] && @@ -25570,15 +25556,15 @@ module mkCore(CLK, rob$deqPort_0_deq_data[329:325] != 5'd19 && rob$deqPort_0_deq_data[329:325] != 5'd20) && rob$deqPort_1_canDeq ; - assign NOT_rob_deqPort_0_deq_data__4344_BITS_329_TO_3_ETC___d14998 = + assign NOT_rob_deqPort_0_deq_data__4354_BITS_329_TO_3_ETC___d15008 = rob$deqPort_0_deq_data[329:325] != 5'd13 || - (IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 != + (IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 != 6'd7 || csrf_stats_module_writeQ$FULL_N) && - (IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 != + (IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 != 6'd6 || csrf_terminate_module_terminateQ$FULL_N) ; - assign NOT_rob_deqPort_1_deq_data__5346_BIT_25_5347_5_ETC___d15377 = + assign NOT_rob_deqPort_1_deq_data__5356_BIT_25_5357_5_ETC___d15387 = !rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[329:325] == 5'd0 || @@ -25590,20 +25576,20 @@ module mkCore(CLK, rob$deqPort_1_deq_data[329:325] == 5'd15 || rob$deqPort_1_deq_data[329:325] == 5'd19 || rob$deqPort_1_deq_data[329:325] == 5'd20 || - regRenamingTable$RDY_commit_1_commit && rob$RDY_deqPort_1_deq && + rob$RDY_deqPort_1_deq && regRenamingTable$RDY_commit_1_commit && v_f_to_TV_1$FULL_N ; - assign NOT_specTagManager_canClaim__3406_3497_OR_NOT__ETC___d14012 = + assign NOT_specTagManager_canClaim__3416_3507_OR_NOT__ETC___d14022 = !specTagManager$canClaim || !regRenamingTable$rename_0_canRename || - fetchStage_pipelines_0_first__2757_BITS_199_TO_ETC___d13514 || - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13952 || + fetchStage_pipelines_0_first__2757_BITS_199_TO_ETC___d13524 || + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13962 || fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$RDY_nextSpecTag ; - assign NOT_specTagManager_canClaim__3406_3497_OR_NOT__ETC___d14079 = + assign NOT_specTagManager_canClaim__3416_3507_OR_NOT__ETC___d14089 = !specTagManager$canClaim || !regRenamingTable$rename_0_canRename || - renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13925 || - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13952 || + renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13935 || + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13962 || fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$RDY_nextSpecTag ; assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2920 = @@ -25624,21 +25610,21 @@ module mkCore(CLK, !CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q268, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2938, x__h291619 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16097 = + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16107 = { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q269, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q270, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q271 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16053 = + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16063 = { CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q253, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q254, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q255, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q256 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16062 = - { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16053, + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16072 = + { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16063, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q257, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q258 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16071 = - { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16062, + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16081 = + { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16072, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q262, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q263 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10131 = @@ -26029,19 +26015,19 @@ module mkCore(CLK, 1'd0, csrf_timer_int_en_vec_1 & csrf_timer_int_pend_vec_1, 1'd0 } ; - assign _0_OR_NOT_fetchStage_pipelines_0_first__2757_BI_ETC___d13933 = + assign _0_OR_NOT_fetchStage_pipelines_0_first__2757_BI_ETC___d13943 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$RDY_nextSpecTag) && - CASE_k70531_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239 ; - assign _0_OR_NOT_fetchStage_pipelines_1_first__2766_BI_ETC___d13834 = + CASE_k70634_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q240 ; + assign _0_OR_NOT_fetchStage_pipelines_1_first__2766_BI_ETC___d13844 = (fetchStage$pipelines_1_first[194:192] != 3'd1 || !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first) && (fetchStage$RDY_pipelines_0_first && fetchStage$pipelines_1_first[194:192] == 3'd1 && - regRenamingTable_rename_0_canRename__3408_AND__ETC___d13498 || - NOT_regRenamingTable_rename_1_canRename__3535__ETC___d13806) ; - assign _0_OR_NOT_fetchStage_pipelines_1_first__2766_BI_ETC___d14025 = + regRenamingTable_rename_0_canRename__3418_AND__ETC___d13508 || + NOT_regRenamingTable_rename_1_canRename__3545__ETC___d13816) ; + assign _0_OR_NOT_fetchStage_pipelines_1_first__2766_BI_ETC___d14035 = (fetchStage$pipelines_1_first[194:192] != 3'd1 || specTagManager$RDY_nextSpecTag) && CASE_fetchStage_pipelines_0_canDeq__2755_AND_N_ETC__q241 ; @@ -26069,12 +26055,12 @@ module mkCore(CLK, (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7338[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7338) ; - assign _0b0_CONCAT_csrf_external_int_pend_vec_3_read___ETC___d14329 = + assign _0b0_CONCAT_csrf_external_int_pend_vec_3_read___ETC___d14339 = mip_csr__read__h611255 == commitStage_rg_old_mip_csr_val ; - assign _0b0_CONCAT_csrf_medeleg_15_reg_read__1645_1646_ETC___d14721 = - medeleg_csr__read__h610374[i__h710364] ; - assign _0b0_CONCAT_csrf_mideleg_11_reg_read__1653_1654_ETC___d14703 = - mideleg_csr__read__h610469[i__h710524] ; + assign _0b0_CONCAT_csrf_medeleg_15_reg_read__1645_1646_ETC___d14731 = + medeleg_csr__read__h610374[i__h710467] ; + assign _0b0_CONCAT_csrf_mideleg_11_reg_read__1653_1654_ETC___d14713 = + mideleg_csr__read__h610469[i__h710627] ; assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4011 = 12'd3074 - { 6'd0, @@ -26662,63 +26648,63 @@ module mkCore(CLK, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7335 ; assign _dfoo12 = fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3408_AND__ETC___d14123 || - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14199 && - regRenamingTable_rename_1_canRename__3535_AND__ETC___d14209 && + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14133 || + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14209 && + regRenamingTable_rename_1_canRename__3545_AND__ETC___d14219 && fetchStage$pipelines_1_first[194:192] == 3'd2 && - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14258 && + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14268 && fetchStage$pipelines_1_first[199:195] != 5'd14 ; assign _dfoo16 = - k__h670531 == 1'd1 && - fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14105 || - (fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14181 || - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14194) == + k__h670634 == 1'd1 && + fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14115 || + (fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14191 || + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14204) == 1'd1 && - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14213 ; + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14223 ; assign _dfoo18 = - k__h670531 == 1'd0 && - fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14105 || - (fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14181 || - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14194) == + k__h670634 == 1'd0 && + fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14115 || + (fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14191 || + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14204) == 1'd0 && - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14213 ; + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14223 ; assign _dfoo2 = fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3408_AND__ETC___d14151 || - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14199 && - regRenamingTable_rename_1_canRename__3535_AND__ETC___d14209 && + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14161 || + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14209 && + regRenamingTable_rename_1_canRename__3545_AND__ETC___d14219 && fetchStage$pipelines_1_first[194:192] == 3'd2 && - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14258 && + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14268 && fetchStage$pipelines_1_first[191:189] != 3'd0 && fetchStage$pipelines_1_first[191:189] != 3'd2 ; - assign _dfoo22 = - commitStage_commitTrap_4352_BIT_36_4594_AND_co_ETC___d14659 || - NOT_commitStage_commitTrap_4352_BIT_36_4594_45_ETC___d14700 ; + assign _dfoo20 = + commitStage_commitTrap_4362_BIT_36_4604_AND_co_ETC___d14669 || + NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 ; assign _dfoo24 = rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd40 || rob$deqPort_0_deq_data[329:325] == 5'd19 || rob$deqPort_0_deq_data[329:325] == 5'd20 ; assign _dfoo26 = rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd18 || rob$deqPort_0_deq_data[329:325] == 5'd20 ; assign _dfoo32 = rob$deqPort_0_deq_data[329:325] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + (IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd8 || - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd18) || rob$deqPort_0_deq_data[329:325] == 5'd19 ; assign _dfoo7 = fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3408_AND__ETC___d14143 || - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14199 && - regRenamingTable_rename_1_canRename__3535_AND__ETC___d14209 && + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14153 || + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14209 && + regRenamingTable_rename_1_canRename__3545_AND__ETC___d14219 && fetchStage$pipelines_1_first[194:192] == 3'd2 && - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14258 && + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14268 && (fetchStage$pipelines_1_first[191:189] == 3'd0 || fetchStage$pipelines_1_first[191:189] == 3'd2) ; assign _dor1coreFix_aluExe_0_bypassWire_2$EN_wset = @@ -29581,11 +29567,11 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[227] ? b___1__h603094 : coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; - assign base__h713309 = { csrf_stvec_base_hi_reg, 2'b0 } ; - assign base__h713329 = { csrf_mtvec_base_hi_reg, 2'b0 } ; - assign cause_code__h710349 = - commitStage_commitTrap[36] ? i__h710524 : i__h710364 ; - assign commitStage_commitTrap_4352_BIT_36_4594_AND_co_ETC___d14659 = + assign base__h713412 = { csrf_stvec_base_hi_reg, 2'b0 } ; + assign base__h713432 = { csrf_mtvec_base_hi_reg, 2'b0 } ; + assign cause_code__h710452 = + commitStage_commitTrap[36] ? i__h710627 : i__h710467 ; + assign commitStage_commitTrap_4362_BIT_36_4604_AND_co_ETC___d14669 = commitStage_commitTrap[36] && commitStage_commitTrap[35:32] != 4'd0 && commitStage_commitTrap[35:32] != 4'd1 && @@ -29599,15 +29585,15 @@ module mkCore(CLK, !commitStage_commitTrap[36] && commitStage_commitTrap[35:32] == 4'd3 && CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q244 ; - assign commitStage_f_rob_data_first__4760_BIT_167_485_ETC___d14932 = + assign commitStage_f_rob_data_first__4770_BIT_167_486_ETC___d14942 = { commitStage_f_rob_data$D_OUT[167:166], commitStage_f_rob_data$D_OUT[166] ? CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q250 : CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q251, - trap_val__h710350, - IF_commitStage_f_rob_data_first__4760_BITS_97__ETC___d14931 } ; - assign commitStage_rg_serial_num_4333_PLUS_IF_rob_deq_ETC___d15459 = - commitStage_rg_serial_num + y__h731332 ; + trap_val__h710453, + IF_commitStage_f_rob_data_first__4770_BITS_97__ETC___d14941 } ; + assign commitStage_rg_serial_num_4343_PLUS_IF_rob_deq_ETC___d15469 = + commitStage_rg_serial_num + y__h731435 ; assign coreFix_aluExe_0_bypassWire_0_wget__2203_BITS__ETC___d12205 = coreFix_aluExe_0_bypassWire_0$wget[70:64] == coreFix_aluExe_0_dispToRegQ$first[84:78] ; @@ -29640,7 +29626,7 @@ module mkCore(CLK, (coreFix_aluExe_0_exeToFinQ$first[326:322] != 5'd9 && coreFix_aluExe_0_exeToFinQ$first[326:322] != 5'd10 || coreFix_trainBPQ_0$FULL_N) ; - assign coreFix_aluExe_0_rsAlu_approximateCount__3447__ETC___d13449 = + assign coreFix_aluExe_0_rsAlu_approximateCount__3457__ETC___d13459 = coreFix_aluExe_0_rsAlu$approximateCount < coreFix_aluExe_1_rsAlu$approximateCount ; assign coreFix_aluExe_1_bypassWire_0_wget__1343_BITS__ETC___d11345 = @@ -29803,11 +29789,11 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107:76] ; assign coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q11 = coreFix_fpuMulDivExe_0_regToExeQ$first[171:140] ; - assign coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__39_ETC___d14032 = + assign coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__39_ETC___d14042 = coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_enq && regRenamingTable$RDY_rename_1_getRename && (!fetchStage$pipelines_0_canDeq || - NOT_specTagManager_canClaim__3406_3497_OR_NOT__ETC___d14012) ; + NOT_specTagManager_canClaim__3416_3507_OR_NOT__ETC___d14022) ; assign coreFix_memExe_bypassWire_0_wget__569_BITS_70__ETC___d1571 = coreFix_aluExe_0_bypassWire_0$wget[70:64] == coreFix_memExe_dispToRegQ$first[61:55] ; @@ -30135,7 +30121,7 @@ module mkCore(CLK, !coreFix_memExe_respLrScAmoQ_deqReq_lat_0$whas && !coreFix_memExe_respLrScAmoQ_deqReq_rl) && coreFix_memExe_respLrScAmoQ_full ; - assign coreFix_memExe_stb_isEmpty__009_AND_coreFix_me_ETC___d14661 = + assign coreFix_memExe_stb_isEmpty__009_AND_coreFix_me_ETC___d14671 = coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty && v_f_to_TV_0$FULL_N && fetchStage$iTlbIfc_noPendingReq && @@ -30157,7 +30143,7 @@ module mkCore(CLK, (fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13038 || csrf_prv_reg_read__2787_ULT_IF_fetchStage_pipe_ETC___d13040 || csr_addr__h655332 == 12'h8FF) ; - assign csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13507 = + assign csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13517 = csrf_fs_reg == 2'd0 && (fetchStage$pipelines_0_first[95] && fetchStage$pipelines_0_first[94] || @@ -30169,7 +30155,7 @@ module mkCore(CLK, fetchStage$pipelines_0_first[231:200] == 32'h10500073 && csrf_tw_reg && csrf_prv_reg != 2'd3 ; - assign csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13796 = + assign csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13806 = csrf_fs_reg == 2'd0 && (fetchStage$pipelines_1_first[95] && fetchStage$pipelines_1_first[94] || @@ -30181,18 +30167,18 @@ module mkCore(CLK, fetchStage$pipelines_1_first[231:200] == 32'h10500073 && csrf_tw_reg && csrf_prv_reg != 2'd3 ; - assign csrf_prv_reg_read__2787_ULE_1_4701_AND_IF_comm_ETC___d14723 = - csrf_prv_reg_read__2787_ULE_1___d14701 && + assign csrf_prv_reg_read__2787_ULE_1_4711_AND_IF_comm_ETC___d14733 = + csrf_prv_reg_read__2787_ULE_1___d14711 && (commitStage_commitTrap[36] ? - _0b0_CONCAT_csrf_mideleg_11_reg_read__1653_1654_ETC___d14703 : - _0b0_CONCAT_csrf_medeleg_15_reg_read__1645_1646_ETC___d14721) ; - assign csrf_prv_reg_read__2787_ULE_1___d14701 = csrf_prv_reg <= 2'd1 ; + _0b0_CONCAT_csrf_mideleg_11_reg_read__1653_1654_ETC___d14713 : + _0b0_CONCAT_csrf_medeleg_15_reg_read__1645_1646_ETC___d14731) ; + assign csrf_prv_reg_read__2787_ULE_1___d14711 = csrf_prv_reg <= 2'd1 ; assign csrf_prv_reg_read__2787_ULT_IF_fetchStage_pipe_ETC___d13040 = csrf_prv_reg < csr_addr__h655332[9:8] ; - assign csrf_rg_dcsr_read__1720_BIT_2_3062_OR_NOT_fetc_ETC___d13503 = + assign csrf_rg_dcsr_read__1720_BIT_2_3062_OR_NOT_fetc_ETC___d13513 = csrf_rg_dcsr[2] || !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first && - IF_fetchStage_RDY_pipelines_0_first__2754_AND__ETC___d13440 ; + IF_fetchStage_RDY_pipelines_0_first__2754_AND__ETC___d13450 ; assign data75286_BITS_31_TO_0__q13 = data__h475286[31:0] ; assign data___1__h475012 = { {32{IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q133[31]}}, @@ -30205,7 +30191,7 @@ module mkCore(CLK, 2'd2) ? x_quotient__h475200 : x_remainder__h475201 ; - assign dcsr_cause__h709868 = + assign dcsr_cause__h709971 = (commitStage_commitTrap[36] && commitStage_commitTrap[35:32] == 4'd14) ? 3'd3 : @@ -30247,27 +30233,27 @@ module mkCore(CLK, assign enabled_ints__h651694 = pend_ints__h651121 & { r1__read_BITS_13_TO_0___h651670, csrf_mideleg_1_0_reg } ; - assign epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13739 = + assign epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13749 = epochManager$checkEpoch_1_check && !csrf_rg_dcsr[2] && (!fetchStage$pipelines_0_canDeq || (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3408_AND__ETC___d13484 && - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13470) ; - assign epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13881 = + regRenamingTable_rename_0_canRename__3418_AND__ETC___d13494 && + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13480) ; + assign epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13891 = epochManager$checkEpoch_1_check && !csrf_rg_dcsr[2] && (!fetchStage$pipelines_0_canDeq || (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3408_AND__ETC___d13484 && - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13877) ; - assign epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13899 = + regRenamingTable_rename_0_canRename__3418_AND__ETC___d13494 && + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13887) ; + assign epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13909 = epochManager$checkEpoch_1_check && !csrf_rg_dcsr[2] && (!fetchStage$pipelines_0_canDeq || (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3408_AND__ETC___d13484 && - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13895) ; + regRenamingTable_rename_0_canRename__3418_AND__ETC___d13494 && + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13905) ; assign f1_exp82144_MINUS_127__q136 = f1_exp__h482144 - 8'd127 ; assign f1_exp__h482144 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == @@ -30299,91 +30285,89 @@ module mkCore(CLK, (coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] : 23'd4194304 ; - assign f_csr_rsps_i_notFull__5791_AND_f_csr_reqs_firs_ETC___d15894 = + assign f_csr_rsps_i_notFull__5801_AND_f_csr_reqs_firs_ETC___d15904 = f_csr_rsps$FULL_N && (f_csr_reqs$D_OUT[75:64] != 12'd2049 || csrf_stats_module_writeQ$FULL_N) && (f_csr_reqs$D_OUT[75:64] != 12'd2048 || csrf_terminate_module_terminateQ$FULL_N) ; assign fcsr_csr__read__h609380 = { 56'd0, x__h613038 } ; - assign fetchStage_RDY_pipelines_0_first__2754_AND_epo_ETC___d13309 = - fetchStage$RDY_pipelines_0_first && - epochManager$RDY_incrementEpoch && - regRenamingTable$RDY_rename_0_getRename && - regRenamingTable$RDY_rename_0_claimRename && - rob$RDY_enqPort_0_enq && - (fetchStage$pipelines_0_first[194:192] != 3'd0 || - coreFix_aluExe_0_rsAlu$RDY_enq) ; - assign fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14023 = + assign fetchStage_RDY_pipelines_1_deq__2769_AND_NOT_f_ETC___d14093 = + fetchStage$RDY_pipelines_1_deq && + (!fetchStage$pipelines_0_canDeq || + NOT_specTagManager_canClaim__3416_3507_OR_NOT__ETC___d14089) && + (fetchStage$pipelines_1_first[194:192] != 3'd1 || + specTagManager$RDY_claimSpecTag) ; + assign fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14033 = fetchStage$pipelines_0_canDeq && (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3408_AND__ETC___d13484 && - fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13750 || + regRenamingTable_rename_0_canRename__3418_AND__ETC___d13494 && + fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13760 || !coreFix_aluExe_0_rsAlu$canEnq || (!fetchStage$pipelines_0_canDeq || - fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d14019) && + fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d14029) && coreFix_aluExe_1_rsAlu$canEnq && - !coreFix_aluExe_0_rsAlu_approximateCount__3447__ETC___d13449 ; - assign fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14105 = + !coreFix_aluExe_0_rsAlu_approximateCount__3457__ETC___d13459 ; + assign fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14115 = fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14102 && + NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14112 && (fetchStage$pipelines_0_first[194:192] == 3'd0 || fetchStage$pipelines_0_first[194:192] == 3'd1) && - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3443_co_ETC___d13453 ; - assign fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14181 = + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463 ; + assign fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14191 = fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14102 && - fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13750 || + NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14112 && + fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13760 || !coreFix_aluExe_0_rsAlu$canEnq ; - assign fetchStage_pipelines_0_canDeq__2755_AND_fetchS_ETC___d14093 = + assign fetchStage_pipelines_0_canDeq__2755_AND_fetchS_ETC___d14103 = fetchStage$pipelines_0_canDeq && - fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13967 || + fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13977 || !fetchStage$pipelines_1_canDeq || fetchStage$RDY_pipelines_1_first && - (fetchStage_pipelines_1_first__2766_BITS_194_TO_ETC___d13978 || + (fetchStage_pipelines_1_first__2766_BITS_194_TO_ETC___d13988 || !regRenamingTable$rename_1_canRename || - fetchStage_pipelines_1_first__2766_BITS_199_TO_ETC___d13990 || - IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14089) && - IF_fetchStage_RDY_pipelines_1_first__2765_AND__ETC___d13910 ; - assign fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14029 = + fetchStage_pipelines_1_first__2766_BITS_199_TO_ETC___d14000 || + IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14099) && + IF_fetchStage_RDY_pipelines_1_first__2765_AND__ETC___d13920 ; + assign fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14039 = fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3408_AND__ETC___d13484 && + regRenamingTable_rename_0_canRename__3418_AND__ETC___d13494 && (fetchStage$pipelines_0_first[194:192] == 3'd3 || fetchStage$pipelines_0_first[194:192] == 3'd4) ; - assign fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14036 = + assign fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14046 = fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3408_AND__ETC___d13484 && + regRenamingTable_rename_0_canRename__3418_AND__ETC___d13494 && fetchStage$pipelines_0_first[194:192] == 3'd2 && - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13466 || + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13476 || !coreFix_memExe_rsMem$canEnq || CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q237 ; - assign fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14058 = - fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14029 || + assign fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14068 = + fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14039 || !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq || fetchStage$pipelines_0_canDeq && (fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || - NOT_regRenamingTable_rename_0_canRename__3408__ETC___d13842 || - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d14049) ; - assign fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14070 = - fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14036 || + NOT_regRenamingTable_rename_0_canRename__3418__ETC___d13852 || + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d14059) ; + assign fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14080 = + fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14046 || fetchStage$pipelines_0_canDeq && (fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || - NOT_regRenamingTable_rename_0_canRename__3408__ETC___d13842 || - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d14061) ; - assign fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14301 = + NOT_regRenamingTable_rename_0_canRename__3418__ETC___d13852 || + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d14071) ; + assign fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14311 = fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3408_AND__ETC___d14299 || + regRenamingTable_rename_0_canRename__3418_AND__ETC___d14309 || !coreFix_memExe_rsMem$canEnq || CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q237 ; - assign fetchStage_pipelines_0_canDeq__2755_AND_specTa_ETC___d14157 = + assign fetchStage_pipelines_0_canDeq__2755_AND_specTa_ETC___d14167 = fetchStage$pipelines_0_canDeq && specTagManager$canClaim && regRenamingTable$rename_0_canRename && !checkForException___d13008[4] && rob$enqPort_0_canEnq && - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13494 && + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13504 && fetchStage$pipelines_0_first[194:192] == 3'd1 ; assign fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13038 = (fetchStage$pipelines_0_first[194:192] == 3'd0 && @@ -30391,64 +30375,64 @@ module mkCore(CLK, rs1__h655333 != 5'd0 || imm__h655334 != 32'd0) && csr_addr__h655332[11:10] == 2'b11 ; - assign fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13750 = + assign fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13760 = (fetchStage$pipelines_0_first[194:192] == 3'd0 || fetchStage$pipelines_0_first[194:192] == 3'd1) && - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3443_co_ETC___d13453 && + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463 && (!coreFix_aluExe_1_rsAlu$canEnq || - coreFix_aluExe_0_rsAlu_approximateCount__3447__ETC___d13449) ; - assign fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13849 = + coreFix_aluExe_0_rsAlu_approximateCount__3457__ETC___d13459) ; + assign fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13859 = fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || - renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13845 ; - assign fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13961 = + renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13855 ; + assign fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13971 = fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || !regRenamingTable$rename_0_canRename || - renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13925 || - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13950 && - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13959 ; - assign fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13967 = + renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13935 || + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13960 && + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13969 ; + assign fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13977 = fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || !regRenamingTable$rename_0_canRename || - renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13925 || - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13966 ; - assign fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13984 = + renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13935 || + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13976 ; + assign fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13994 = fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || !regRenamingTable$rename_0_canRename || fetchStage$pipelines_0_first[68] || checkForException___d13008[4] || !rob$enqPort_0_canEnq || - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13966 ; - assign fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13996 = + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13976 ; + assign fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d14006 = fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || - NOT_regRenamingTable_rename_0_canRename__3408__ETC___d13766 || + NOT_regRenamingTable_rename_0_canRename__3418__ETC___d13776 || fetchStage$pipelines_0_first[194:192] != 3'd0 && fetchStage$pipelines_0_first[194:192] != 3'd1 || - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3443_co_ETC___d13453 || + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463 || coreFix_aluExe_1_rsAlu$canEnq && - !coreFix_aluExe_0_rsAlu_approximateCount__3447__ETC___d13449 ; - assign fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d14003 = + !coreFix_aluExe_0_rsAlu_approximateCount__3457__ETC___d13459 ; + assign fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d14013 = fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || - NOT_regRenamingTable_rename_0_canRename__3408__ETC___d13766 || + NOT_regRenamingTable_rename_0_canRename__3418__ETC___d13776 || fetchStage$pipelines_0_first[194:192] != 3'd0 && fetchStage$pipelines_0_first[194:192] != 3'd1 || - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3443_co_ETC___d13453 || + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463 || coreFix_aluExe_0_rsAlu$canEnq && - coreFix_aluExe_0_rsAlu_approximateCount__3447__ETC___d13449 ; - assign fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d14019 = + coreFix_aluExe_0_rsAlu_approximateCount__3457__ETC___d13459 ; + assign fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d14029 = fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim || !regRenamingTable$rename_0_canRename || - fetchStage_pipelines_0_first__2757_BITS_199_TO_ETC___d13514 || + fetchStage_pipelines_0_first__2757_BITS_199_TO_ETC___d13524 || fetchStage$pipelines_0_first[194:192] != 3'd0 && fetchStage$pipelines_0_first[194:192] != 3'd1 || - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3443_co_ETC___d13453 ; - assign fetchStage_pipelines_0_first__2757_BITS_199_TO_ETC___d13514 = + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463 ; + assign fetchStage_pipelines_0_first__2757_BITS_199_TO_ETC___d13524 = fetchStage$pipelines_0_first[199:195] == 5'd0 || fetchStage$pipelines_0_first[199:195] == 5'd21 || fetchStage$pipelines_0_first[199:195] == 5'd17 || @@ -30461,21 +30445,44 @@ module mkCore(CLK, renameStage_rg_m_halt_req[4] || fetchStage$pipelines_0_first[68] || checkForException___d13008[4] || - csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13507 || + csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13517 || !rob$enqPort_0_canEnq || !epochManager$checkEpoch_0_check ; - assign fetchStage_pipelines_0_first__2757_BIT_68_2786_ETC___d13840 = + assign fetchStage_pipelines_0_first__2757_BIT_173_288_ETC___d13411 = + { fetchStage$pipelines_0_first[173], + IF_fetchStage_pipelines_0_first__2757_BITS_172_ETC___d12973, + 73'h1280000000000000000, + fetchStage$pipelines_0_first[323:260], + 5'd0, + (fetchStage$pipelines_0_first[173] && + fetchStage$pipelines_0_first[199:195] == 5'd13 && + (fetchStage$pipelines_0_first[172:161] == 12'd1 || + fetchStage$pipelines_0_first[172:161] == 12'd2 || + fetchStage$pipelines_0_first[172:161] == 12'd3)) ? + fetchStage$pipelines_0_first[194:192] == 3'd0 && + fetchStage$pipelines_0_first[178:174] == 5'd15 || + (!fetchStage$pipelines_0_first[88] || + fetchStage$pipelines_0_first[87] || + fetchStage$pipelines_0_first[86:82] != 5'd0) && + (!fetchStage$pipelines_0_first[160] || + fetchStage$pipelines_0_first[159:128] != 32'd0) : + fetchStage$pipelines_0_first[75] && + fetchStage$pipelines_0_first[74], + fetchStage$pipelines_0_first[194:192] != 3'd0, + 13'h1521, + specTagManager$currentSpecBits } ; + assign fetchStage_pipelines_0_first__2757_BIT_68_2786_ETC___d13850 = fetchStage$pipelines_0_first[68] || checkForException___d13008[4] || - csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13507 || + csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13517 || !rob$enqPort_0_canEnq || !epochManager$checkEpoch_0_check ; - assign fetchStage_pipelines_1_first__2766_BITS_194_TO_ETC___d13978 = + assign fetchStage_pipelines_1_first__2766_BITS_194_TO_ETC___d13988 = fetchStage$pipelines_1_first[194:192] == 3'd1 && (fetchStage$pipelines_0_canDeq && - regRenamingTable_rename_0_canRename__3408_AND__ETC___d13975 || + regRenamingTable_rename_0_canRename__3418_AND__ETC___d13985 || !specTagManager$canClaim) ; - assign fetchStage_pipelines_1_first__2766_BITS_199_TO_ETC___d13990 = + assign fetchStage_pipelines_1_first__2766_BITS_199_TO_ETC___d14000 = fetchStage$pipelines_1_first[199:195] == 5'd0 || fetchStage$pipelines_1_first[199:195] == 5'd21 || fetchStage$pipelines_1_first[199:195] == 5'd17 || @@ -30487,20 +30494,20 @@ module mkCore(CLK, fetchStage$pipelines_1_first[199:195] == 5'd20 || renameStage_rg_m_halt_req[4] || fetchStage$pipelines_1_first[68] || - checkForException___d13703[4] || - csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13796 || + checkForException___d13713[4] || + csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13806 || !rob$enqPort_1_canEnq || !epochManager$checkEpoch_1_check || csrf_rg_dcsr[2] || fetchStage$pipelines_0_canDeq && - fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13984 ; - assign fetchStage_pipelines_1_first__2766_BIT_173_359_ETC___d13681 = + fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13994 ; + assign fetchStage_pipelines_1_first__2766_BIT_173_360_ETC___d13691 = { fetchStage$pipelines_1_first[173], CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q235 } ; - assign fflags__h734124 = - NOT_rob_deqPort_0_canDeq__5338_5339_OR_rob_deq_ETC___d15659 ? - y_avValue_fst__h734061 : - IF_rob_deqPort_0_canDeq__5338_THEN_IF_NOT_rob__ETC___d15665 ; + assign fflags__h734227 = + NOT_rob_deqPort_0_canDeq__5348_5349_OR_rob_deq_ETC___d15669 ? + y_avValue_fst__h734164 : + IF_rob_deqPort_0_canDeq__5348_THEN_IF_NOT_rob__ETC___d15675 ; assign fflags_csr__read__h609355 = { 59'd0, csrf_fflags_reg } ; assign frm_csr__read__h609366 = { 61'd0, csrf_frm_reg } ; assign guard__h346099 = @@ -30572,19 +30579,19 @@ module mkCore(CLK, assign guard__h590109 = { IF_theResult___snd98045_BIT_4_THEN_2_ELSE_0__q159[1], { _theResult___snd__h598045[3:0], 52'd0 } != 56'd0 } ; - assign idx__h686276 = + assign idx__h686379 = fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13751 || + NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13761 || !coreFix_aluExe_0_rsAlu$canEnq || - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13775 ; + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13785 ; assign imm__h655334 = fetchStage$pipelines_0_first[160] ? fetchStage$pipelines_0_first[159:128] : 32'd0 ; - assign k__h670531 = + assign k__h670634 = !coreFix_aluExe_0_rsAlu$canEnq || coreFix_aluExe_1_rsAlu$canEnq && - !coreFix_aluExe_0_rsAlu_approximateCount__3447__ETC___d13449 ; + !coreFix_aluExe_0_rsAlu_approximateCount__3457__ETC___d13459 ; assign mcause_csr__read__h611022 = { r1__read__h614501, csrf_mcause_code_reg } ; assign mcounteren_csr__read__h610767 = @@ -30649,13 +30656,13 @@ module mkCore(CLK, fetchStage$pipelines_0_first[199:195] == 5'd19 || fetchStage$pipelines_0_first[199:195] == 5'd20) && rob$isEmpty ; - assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14097 = + assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14107 = mmio_pRqQ_empty && epochManager$checkEpoch_0_check && !renameStage_rg_m_halt_req[4] && !fetchStage$pipelines_0_first[68] && - NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13427 ; - assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14099 = - mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14097 && + NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13437 ; + assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14109 = + mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14107 && fetchStage$pipelines_0_first[199:195] != 5'd0 && fetchStage$pipelines_0_first[199:195] != 5'd21 && fetchStage$pipelines_0_first[199:195] != 5'd17 && @@ -30723,11 +30730,11 @@ module mkCore(CLK, upd__h6875 : csrf_mcycle_ehr_data_rl) : 64'd0 ; - assign n__read__h727564 = + assign n__read__h727667 = csrf_minstret_ehr_data_dummy2_1$Q_OUT ? IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8 : 64'd0 ; - assign new_mstatus___1__h726926 = x__h726917 ; + assign new_mstatus___1__h727029 = x__h727020 ; assign next_deqP___1__h296803 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP == 3'd7) ? @@ -30742,12 +30749,12 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP + 1'd1 ; assign next_deqP___1__h328991 = coreFix_memExe_memRespLdQ_deqP + 1'd1 ; assign next_deqP___1__h332216 = coreFix_memExe_forwardQ_deqP + 1'd1 ; - assign next_pc__h723361 = + assign next_pc__h723464 = (rob$deqPort_0_deq_data[329:325] != 5'd13 && rob$deqPort_0_deq_data[97:96] == 2'd0) ? rob$deqPort_0_deq_data[95:32] : rob$deqPort_0_deq_data[425:362] + 64'd4 ; - assign old_fflags1__h733611 = + assign old_fflags1__h733714 = csrf_fflags_reg | rob$deqPort_0_deq_data[31:27] ; assign out___1_sfd__h482208 = { f1_sfd__h482145, 29'd0 } ; assign out___1_sfd__h521202 = { f2_sfd__h521139, 29'd0 } ; @@ -30956,21 +30963,21 @@ module mkCore(CLK, _theResult___snd__h598045[5] ? _theResult___sfd__h598780 : _theResult___snd__h598045[56:5] ; - assign pc__h713293 = - csrf_prv_reg_read__2787_ULE_1_4701_AND_IF_comm_ETC___d14723 ? - y_avValue_new_pc__h713085 : - y_avValue_new_pc__h713271 ; + assign pc__h713396 = + csrf_prv_reg_read__2787_ULE_1_4711_AND_IF_comm_ETC___d14733 ? + y_avValue_new_pc__h713188 : + y_avValue_new_pc__h713374 ; assign pend_ints__h651121 = { _0_CONCAT_csrf_external_int_en_vec_3_read__1664_ETC___d12798, csrf_software_int_en_vec_3 & csrf_software_int_pend_vec_3, 1'd0, csrf_software_int_en_vec_1 & csrf_software_int_pend_vec_1, 1'd0 } ; - assign po_fflags__h728848 = old_fflags1__h733611 ; - assign po_fflags__h731495 = - old_fflags1__h733611 | rob$deqPort_1_deq_data[31:27] ; - assign prv__h735791 = csrf_prv_reg ; - assign prv__h735835 = csrf_mprv_reg ? csrf_mpp_reg : csrf_prv_reg ; + assign po_fflags__h728951 = old_fflags1__h733714 ; + assign po_fflags__h731598 = + old_fflags1__h733714 | rob$deqPort_1_deq_data[31:27] ; + assign prv__h735894 = csrf_prv_reg ; + assign prv__h735938 = csrf_mprv_reg ? csrf_mpp_reg : csrf_prv_reg ; assign q___1__h475885 = 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[127:64] ; @@ -30983,7 +30990,7 @@ module mkCore(CLK, csrf_mideleg_5_3_reg, 1'b0 } ; assign r1__read_BITS_13_TO_12___h655202 = csrf_fs_reg ; - assign r1__read_BITS_61_TO_14___h726985 = + assign r1__read_BITS_61_TO_14___h727088 = { 40'd5120, csrf_tsr_reg, csrf_tw_reg, @@ -31102,24 +31109,25 @@ module mkCore(CLK, assign r___1__h475911 = 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[63:0] ; - assign regRenamingTable_RDY_commit_0_commit__4943_AND_ETC___d15003 = - regRenamingTable$RDY_commit_0_commit && rob$RDY_deqPort_0_deq && - rob$RDY_deqPort_0_deq_data && - v_f_to_TV_0$FULL_N && - fetchStage$iTlbIfc_noPendingReq && - coreFix_memExe_dTlb$noPendingReq && - NOT_rob_deqPort_0_deq_data__4344_BITS_329_TO_3_ETC___d14998 ; - assign regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13946 = + assign regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13309 = regRenamingTable$RDY_rename_0_getRename && - CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q240 && + regRenamingTable$RDY_rename_0_claimRename && + fetchStage$RDY_pipelines_0_deq && + fetchStage$RDY_pipelines_0_first && + epochManager$RDY_incrementEpoch && + (fetchStage$pipelines_0_first[194:192] != 3'd0 || + coreFix_aluExe_0_rsAlu$RDY_enq) ; + assign regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13956 = + regRenamingTable$RDY_rename_0_getRename && + CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q239 && (fetchStage$pipelines_0_first[199:195] == 5'd14 || coreFix_memExe_rsMem$RDY_enq) ; - assign regRenamingTable_RDY_rename_1_getRename__4009__ETC___d14027 = + assign regRenamingTable_RDY_rename_1_getRename__4019__ETC___d14037 = regRenamingTable$RDY_rename_1_getRename && (!fetchStage$pipelines_0_canDeq || - NOT_specTagManager_canClaim__3406_3497_OR_NOT__ETC___d14012) && - _0_OR_NOT_fetchStage_pipelines_1_first__2766_BI_ETC___d14025 ; - assign regRenamingTable_rename_0_canRename__3408_AND__ETC___d13434 = + NOT_specTagManager_canClaim__3416_3507_OR_NOT__ETC___d14022) && + _0_OR_NOT_fetchStage_pipelines_1_first__2766_BI_ETC___d14035 ; + assign regRenamingTable_rename_0_canRename__3418_AND__ETC___d13444 = regRenamingTable$rename_0_canRename && fetchStage$pipelines_0_first[199:195] != 5'd0 && fetchStage$pipelines_0_first[199:195] != 5'd21 && @@ -31130,8 +31138,8 @@ module mkCore(CLK, fetchStage$pipelines_0_first[199:195] != 5'd15 && fetchStage$pipelines_0_first[199:195] != 5'd19 && fetchStage$pipelines_0_first[199:195] != 5'd20 && - NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13432 ; - assign regRenamingTable_rename_0_canRename__3408_AND__ETC___d13484 = + NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13442 ; + assign regRenamingTable_rename_0_canRename__3418_AND__ETC___d13494 = regRenamingTable$rename_0_canRename && fetchStage$pipelines_0_first[199:195] != 5'd0 && fetchStage$pipelines_0_first[199:195] != 5'd21 && @@ -31142,64 +31150,64 @@ module mkCore(CLK, fetchStage$pipelines_0_first[199:195] != 5'd15 && fetchStage$pipelines_0_first[199:195] != 5'd19 && fetchStage$pipelines_0_first[199:195] != 5'd20 && - NOT_fetchStage_pipelines_0_first__2757_BIT_68__ETC___d13482 ; - assign regRenamingTable_rename_0_canRename__3408_AND__ETC___d13498 = - regRenamingTable_rename_0_canRename__3408_AND__ETC___d13484 && - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13494 && + NOT_fetchStage_pipelines_0_first__2757_BIT_68__ETC___d13492 ; + assign regRenamingTable_rename_0_canRename__3418_AND__ETC___d13508 = + regRenamingTable_rename_0_canRename__3418_AND__ETC___d13494 && + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13504 && fetchStage$pipelines_0_first[194:192] == 3'd1 || !specTagManager$canClaim ; - assign regRenamingTable_rename_0_canRename__3408_AND__ETC___d13828 = - regRenamingTable_rename_0_canRename__3408_AND__ETC___d13484 && + assign regRenamingTable_rename_0_canRename__3418_AND__ETC___d13838 = + regRenamingTable_rename_0_canRename__3418_AND__ETC___d13494 && fetchStage$pipelines_0_first[194:192] == 3'd2 && - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13466 || + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13476 || !coreFix_memExe_rsMem$canEnq || CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q237 ; - assign regRenamingTable_rename_0_canRename__3408_AND__ETC___d13975 = + assign regRenamingTable_rename_0_canRename__3418_AND__ETC___d13985 = regRenamingTable$rename_0_canRename && !checkForException___d13008[4] && rob$enqPort_0_canEnq && - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13973 && + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13983 && fetchStage$pipelines_0_first[194:192] == 3'd1 ; - assign regRenamingTable_rename_0_canRename__3408_AND__ETC___d14117 = + assign regRenamingTable_rename_0_canRename__3418_AND__ETC___d14127 = regRenamingTable$rename_0_canRename && !checkForException___d13008[4] && rob$enqPort_0_canEnq && (fetchStage$pipelines_0_first[194:192] == 3'd3 || fetchStage$pipelines_0_first[194:192] == 3'd4) && coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq ; - assign regRenamingTable_rename_0_canRename__3408_AND__ETC___d14123 = + assign regRenamingTable_rename_0_canRename__3418_AND__ETC___d14133 = regRenamingTable$rename_0_canRename && !checkForException___d13008[4] && rob$enqPort_0_canEnq && fetchStage$pipelines_0_first[194:192] == 3'd2 && coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13466 && + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13476 && fetchStage$pipelines_0_first[199:195] != 5'd14 ; - assign regRenamingTable_rename_0_canRename__3408_AND__ETC___d14143 = + assign regRenamingTable_rename_0_canRename__3418_AND__ETC___d14153 = regRenamingTable$rename_0_canRename && !checkForException___d13008[4] && rob$enqPort_0_canEnq && fetchStage$pipelines_0_first[194:192] == 3'd2 && coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13466 && + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13476 && (fetchStage$pipelines_0_first[191:189] == 3'd0 || fetchStage$pipelines_0_first[191:189] == 3'd2) ; - assign regRenamingTable_rename_0_canRename__3408_AND__ETC___d14151 = + assign regRenamingTable_rename_0_canRename__3418_AND__ETC___d14161 = regRenamingTable$rename_0_canRename && !checkForException___d13008[4] && rob$enqPort_0_canEnq && fetchStage$pipelines_0_first[194:192] == 3'd2 && coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13466 && + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13476 && fetchStage$pipelines_0_first[191:189] != 3'd0 && fetchStage$pipelines_0_first[191:189] != 3'd2 ; - assign regRenamingTable_rename_0_canRename__3408_AND__ETC___d14299 = + assign regRenamingTable_rename_0_canRename__3418_AND__ETC___d14309 = regRenamingTable$rename_0_canRename && !checkForException___d13008[4] && rob$enqPort_0_canEnq && fetchStage$pipelines_0_first[194:192] == 3'd2 && - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13466 ; - assign regRenamingTable_rename_1_canRename__3535_AND__ETC___d13743 = + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13476 ; + assign regRenamingTable_rename_1_canRename__3545_AND__ETC___d13753 = regRenamingTable$rename_1_canRename && fetchStage$pipelines_1_first[199:195] != 5'd0 && fetchStage$pipelines_1_first[199:195] != 5'd21 && @@ -31210,8 +31218,8 @@ module mkCore(CLK, fetchStage$pipelines_1_first[199:195] != 5'd15 && fetchStage$pipelines_1_first[199:195] != 5'd19 && fetchStage$pipelines_1_first[199:195] != 5'd20 && - NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13741 ; - assign regRenamingTable_rename_1_canRename__3535_AND__ETC___d13885 = + NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13751 ; + assign regRenamingTable_rename_1_canRename__3545_AND__ETC___d13895 = regRenamingTable$rename_1_canRename && fetchStage$pipelines_1_first[199:195] != 5'd0 && fetchStage$pipelines_1_first[199:195] != 5'd21 && @@ -31222,8 +31230,8 @@ module mkCore(CLK, fetchStage$pipelines_1_first[199:195] != 5'd15 && fetchStage$pipelines_1_first[199:195] != 5'd19 && fetchStage$pipelines_1_first[199:195] != 5'd20 && - NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13883 ; - assign regRenamingTable_rename_1_canRename__3535_AND__ETC___d13903 = + NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13893 ; + assign regRenamingTable_rename_1_canRename__3545_AND__ETC___d13913 = regRenamingTable$rename_1_canRename && fetchStage$pipelines_1_first[199:195] != 5'd0 && fetchStage$pipelines_1_first[199:195] != 5'd21 && @@ -31234,8 +31242,8 @@ module mkCore(CLK, fetchStage$pipelines_1_first[199:195] != 5'd15 && fetchStage$pipelines_1_first[199:195] != 5'd19 && fetchStage$pipelines_1_first[199:195] != 5'd20 && - NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13901 ; - assign regRenamingTable_rename_1_canRename__3535_AND__ETC___d14209 = + NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13911 ; + assign regRenamingTable_rename_1_canRename__3545_AND__ETC___d14219 = regRenamingTable$rename_1_canRename && fetchStage$pipelines_1_first[199:195] != 5'd0 && fetchStage$pipelines_1_first[199:195] != 5'd21 && @@ -31246,14 +31254,14 @@ module mkCore(CLK, fetchStage$pipelines_1_first[199:195] != 5'd15 && fetchStage$pipelines_1_first[199:195] != 5'd19 && fetchStage$pipelines_1_first[199:195] != 5'd20 && - NOT_fetchStage_pipelines_1_first__2766_BIT_68__ETC___d14207 ; - assign regRenamingTable_rename_1_canRename__3535_AND__ETC___d14253 = - regRenamingTable_rename_1_canRename__3535_AND__ETC___d14209 && + NOT_fetchStage_pipelines_1_first__2766_BIT_68__ETC___d14217 ; + assign regRenamingTable_rename_1_canRename__3545_AND__ETC___d14263 = + regRenamingTable_rename_1_canRename__3545_AND__ETC___d14219 && (fetchStage$pipelines_1_first[194:192] == 3'd3 || fetchStage$pipelines_1_first[194:192] == 3'd4) && (!fetchStage$pipelines_0_canDeq || !regRenamingTable$rename_0_canRename || - renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13925 || + renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13935 || fetchStage$pipelines_0_first[194:192] != 3'd3 && fetchStage$pipelines_0_first[194:192] != 3'd4) && coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq ; @@ -31282,20 +31290,20 @@ module mkCore(CLK, IF_fetchStage_pipelines_0_first__2757_BIT_68_2_ETC___d13130 : IF_checkForException_3008_BIT_4_3009_THEN_IF_c_ETC___d13159) == 4'd3 ; - assign renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13764 = + assign renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13774 = renameStage_rg_m_halt_req[4] || fetchStage$pipelines_0_first[68] || - IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d13761 || + IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d13771 || !rob$enqPort_0_canEnq || !epochManager$checkEpoch_0_check ; - assign renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13804 = + assign renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13814 = renameStage_rg_m_halt_req[4] || fetchStage$pipelines_1_first[68] || - IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d13798 || + IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d13808 || !rob$enqPort_1_canEnq || !epochManager$checkEpoch_1_check || - csrf_rg_dcsr_read__1720_BIT_2_3062_OR_NOT_fetc_ETC___d13503 ; - assign renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13845 = + csrf_rg_dcsr_read__1720_BIT_2_3062_OR_NOT_fetc_ETC___d13513 ; + assign renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13855 = renameStage_rg_m_halt_req[4] || fetchStage$pipelines_0_first[68] || IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[0] || @@ -31314,14 +31322,14 @@ module mkCore(CLK, IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[13] || IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[14] || IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[15] ; - assign renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13925 = + assign renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13935 = renameStage_rg_m_halt_req[4] || fetchStage$pipelines_0_first[68] || checkForException___d13008[4] || !rob$enqPort_0_canEnq ; - assign renaming_spec_bits__h686145 = + assign renaming_spec_bits__h686248 = fetchStage$pipelines_0_canDeq ? - y_avValue_fst__h682540 : + y_avValue_fst__h682643 : specTagManager$currentSpecBits ; assign res_data__h337873 = { 32'hFFFFFFFF, x__h337888 } ; assign res_data__h337878 = @@ -31598,7 +31606,7 @@ module mkCore(CLK, guard__h581638 } ; assign result__h646700 = w__h646695 & y__h646729 ; assign result__h646751 = ~x__h646750 ; - assign rg_core_run_state_read__3058_EQ_2_3059_AND_NOT_ETC___d15730 = + assign rg_core_run_state_read__3058_EQ_2_3059_AND_NOT_ETC___d15740 = rg_core_run_state == 2'd2 && !flush_reservation && !flush_tlbs && !update_vm_info && fetchStage$iTlbIfc_flush_done && @@ -31606,13 +31614,14 @@ module mkCore(CLK, !flush_caches ; assign rg_tdata1__read__h612210 = { r1__read__h614604, csrf_rg_tdata1_data } ; - assign rob_RDY_enqPort_1_enq__4075_AND_NOT_fetchStage_ETC___d14083 = - rob$RDY_enqPort_1_enq && - (!fetchStage$pipelines_0_canDeq || - NOT_specTagManager_canClaim__3406_3497_OR_NOT__ETC___d14079) && - (fetchStage$pipelines_1_first[194:192] != 3'd1 || - specTagManager$RDY_claimSpecTag) ; - assign rob_deqPort_0_deq_data__4344_BITS_161_TO_98_43_ETC___d15316 = + assign rob_RDY_deqPort_0_deq__4351_AND_rob_RDY_deqPor_ETC___d15013 = + rob$RDY_deqPort_0_deq && rob$RDY_deqPort_0_deq_data && + regRenamingTable$RDY_commit_0_commit && + v_f_to_TV_0$FULL_N && + fetchStage$iTlbIfc_noPendingReq && + coreFix_memExe_dTlb$noPendingReq && + NOT_rob_deqPort_0_deq_data__4354_BITS_329_TO_3_ETC___d15008 ; + assign rob_deqPort_0_deq_data__4354_BITS_161_TO_98_43_ETC___d15326 = { rob$deqPort_0_deq_data[161:98], (rob$deqPort_0_deq_data[329:325] != 5'd13 && rob$deqPort_0_deq_data[97:96] == 2'd0) ? @@ -31622,21 +31631,21 @@ module mkCore(CLK, { 2'd1, rob$deqPort_0_deq_data[95:32] } : { 2'd2, (rob$deqPort_0_deq_data[329:325] == 5'd13) ? - data_warl_xformed__h723335 : + data_warl_xformed__h723438 : rob$deqPort_0_deq_data[95:32] }), 5'h0A, rob$deqPort_0_deq_data[26], - x__h726917, - x_prv__h723923, + x__h727020, + x_prv__h724026, 64'hAAAAAAAAAAAAAAAA, - x__h727058, + x__h727161, 128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; - assign rob_deqPort_0_deq_data__4344_BIT_166_4360_CONC_ETC___d14409 = + assign rob_deqPort_0_deq_data__4354_BIT_166_4370_CONC_ETC___d14419 = { rob$deqPort_0_deq_data[166], rob$deqPort_0_deq_data[166] ? CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q247 : CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q248 } ; - assign rob_deqPort_0_deq_data__4344_BIT_181_4419_CONC_ETC___d14510 = + assign rob_deqPort_0_deq_data__4354_BIT_181_4429_CONC_ETC___d14520 = { rob$deqPort_0_deq_data[181], CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q246 } ; assign robdeqPort_0_deq_data_BITS_95_TO_32__q245 = @@ -31827,14 +31836,14 @@ module mkCore(CLK, coreFix_memExe_regToExeQ$first[75:12] << x__h181702 ; assign sie_csr__read__h609646 = { r1__read__h613457, 1'b0 } ; assign sip_csr__read__h610020 = { r1__read__h613991, 1'b0 } ; - assign spec_bits__h689304 = specTagManager$currentSpecBits | y__h689317 ; + assign spec_bits__h689407 = specTagManager$currentSpecBits | y__h689420 ; assign sstatus_csr__read__h609576 = { r1__read__h613053, csrf_ie_vec_0 } ; assign stvec_csr__read__h609689 = { r1__read__h613967, csrf_stvec_mode_low_reg } ; - assign trap_val__h710350 = - commitStage_commitTrap[36] ? 64'd0 : trap_val__h711388 ; - assign tsr_val__h727178 = csrf_tsr_reg ; - assign tvm_val__h727180 = csrf_tvm_reg ; + assign trap_val__h710453 = + commitStage_commitTrap[36] ? 64'd0 : trap_val__h711491 ; + assign tsr_val__h727281 = csrf_tsr_reg ; + assign tvm_val__h727283 = csrf_tvm_reg ; assign upd__h3994 = WILL_FIRE_RL_commitStage_doCommitSystemInst ? MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1 : @@ -31844,7 +31853,7 @@ module mkCore(CLK, MUX_csrf_mcycle_ehr_data_dummy2_0$write_1__SEL_1 ? f_csr_reqs$D_OUT[63:0] : rob$deqPort_0_deq_data[95:32] ; - assign upd__h727675 = + assign upd__h727778 = MUX_csrf_minstret_ehr_data_dummy2_0$write_1__SEL_1 ? f_csr_reqs$D_OUT[63:0] : rob$deqPort_0_deq_data[95:32] ; @@ -32078,22 +32087,22 @@ module mkCore(CLK, sbCons$lazyLookup_0_get[2] ? rf$read_0_rd2 : y_avValue__h637580 ; assign x__h646699 = 12'd1 << coreFix_aluExe_1_exeToFinQ$first[15:12] ; assign x__h646750 = 12'd1 << coreFix_aluExe_0_exeToFinQ$first[15:12] ; - assign x__h703283 = + assign x__h703386 = (!rob$deqPort_0_deq_data[166] && (rob$deqPort_0_deq_data[165:162] == 4'd1 || rob$deqPort_0_deq_data[165:162] == 4'd12)) ? rob$deqPort_0_deq_data[161:98] : rob$deqPort_0_deq_data[95:32] ; - assign x__h713324 = { cause_code__h710349, 2'b0 } ; - assign x__h715551 = + assign x__h713427 = { cause_code__h710452, 2'b0 } ; + assign x__h715654 = { csrf_fs_reg == 2'b11, - IF_csrf_prv_reg_read__2787_ULE_1_4701_AND_IF_c_ETC___d14925 } ; - assign x__h715743 = - { commitStage_commitTrap[36], 59'b0, cause_code__h710349 } ; - assign x__h723465 = { 1'b0, csrf_spp_reg } ; - assign x__h726917 = + IF_csrf_prv_reg_read__2787_ULE_1_4711_AND_IF_c_ETC___d14935 } ; + assign x__h715846 = + { commitStage_commitTrap[36], 59'b0, cause_code__h710452 } ; + assign x__h723568 = { 1'b0, csrf_spp_reg } ; + assign x__h727020 = { 1'b1, - r1__read_BITS_61_TO_14___h726985, + r1__read_BITS_61_TO_14___h727088, 2'b11, csrf_mpp_reg, 2'b0, @@ -32106,7 +32115,7 @@ module mkCore(CLK, 1'b0, csrf_ie_vec_1, csrf_ie_vec_0 } ; - assign x__h727058 = + assign x__h727161 = { csrf_fs_reg == 2'b11, 40'd5120, csrf_tsr_reg, @@ -32117,16 +32126,16 @@ module mkCore(CLK, csrf_mprv_reg, 2'd0, csrf_fs_reg, - IF_rob_deqPort_0_deq_data__4344_BITS_329_TO_32_ETC___d15306 } ; - assign x__h733638 = + IF_rob_deqPort_0_deq_data__4354_BITS_329_TO_32_ETC___d15316 } ; + assign x__h733741 = { 1'b1, - y_avValue_snd_snd_snd_snd_snd_snd_snd__h733620[62:15], + y_avValue_snd_snd_snd_snd_snd_snd_snd__h733723[62:15], 2'b11, - y_avValue_snd_snd_snd_snd_snd_snd_snd__h733620[12:0] } ; - assign x__h734388 = - NOT_rob_deqPort_0_canDeq__5338_5339_OR_rob_deq_ETC___d15659 ? - y_avValue_snd_snd_snd_fst__h734198 : - IF_rob_deqPort_0_canDeq__5338_THEN_IF_NOT_rob__ETC___d15684 ; + y_avValue_snd_snd_snd_snd_snd_snd_snd__h733723[12:0] } ; + assign x__h734491 = + NOT_rob_deqPort_0_canDeq__5348_5349_OR_rob_deq_ETC___d15669 ? + y_avValue_snd_snd_snd_fst__h734301 : + IF_rob_deqPort_0_canDeq__5348_THEN_IF_NOT_rob__ETC___d15694 ; assign x__h76239 = mmio_pRqQ_data_0[31:0] ; assign x_addr__h314077 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? @@ -32136,16 +32145,16 @@ module mkCore(CLK, EN_mmioToPlatform_pRq_enq ? mmio_pRqQ_enqReq_lat_0$wget[31:0] : mmio_pRqQ_enqReq_rl[31:0] ; - assign x_data_imm__h677563 = fetchStage$pipelines_0_first[159:128] ; - assign x_data_imm__h693617 = fetchStage$pipelines_1_first[159:128] ; + assign x_data_imm__h677666 = fetchStage$pipelines_0_first[159:128] ; + assign x_data_imm__h693720 = fetchStage$pipelines_1_first[159:128] ; assign x_decodeInfo_frm__h655017 = csrf_frm_reg ; - assign x_prv__h713393 = - csrf_prv_reg_read__2787_ULE_1_4701_AND_IF_comm_ETC___d14723 ? + assign x_prv__h713496 = + csrf_prv_reg_read__2787_ULE_1_4711_AND_IF_comm_ETC___d14733 ? 2'd1 : 2'd3 ; - assign x_prv__h723923 = + assign x_prv__h724026 = (rob$deqPort_0_deq_data[329:325] == 5'd19) ? - x__h723465 : + x__h723568 : csrf_mpp_reg ; assign x_quotient__h475200 = coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[75] ? @@ -32175,15 +32184,15 @@ module mkCore(CLK, ~csrf_mideleg_5_3_reg, 1'd1, ~csrf_mideleg_1_0_reg } ; - assign y__h689317 = 12'd1 << specTagManager$nextSpecTag ; - assign y__h731332 = + assign y__h689420 = 12'd1 << specTagManager$nextSpecTag ; + assign y__h731435 = rob$deqPort_0_canDeq ? - y_avValue_snd_snd_snd_snd_snd_fst__h731355 : + y_avValue_snd_snd_snd_snd_snd_fst__h731458 : 64'd0 ; - assign y__h734147 = - NOT_rob_deqPort_0_canDeq__5338_5339_OR_rob_deq_ETC___d15659 ? - y_avValue_snd_snd_snd_snd_snd_fst__h734208 : - y__h731332 ; + assign y__h734250 = + NOT_rob_deqPort_0_canDeq__5348_5349_OR_rob_deq_ETC___d15669 ? + y_avValue_snd_snd_snd_snd_snd_fst__h734311 : + y__h731435 ; assign y_avValue__h180567 = NOT_coreFix_memExe_bypassWire_0_whas__568_574__ETC___d1595 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : @@ -32220,21 +32229,21 @@ module mkCore(CLK, NOT_coreFix_aluExe_0_bypassWire_0_whas__2202_2_ETC___d12257 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12461 ; - assign y_avValue_fst__h682477 = + assign y_avValue_fst__h682580 = (fetchStage$pipelines_0_first[194:192] == 3'd1) ? - spec_bits__h689304 : + spec_bits__h689407 : specTagManager$currentSpecBits ; - assign y_avValue_fst__h682506 = - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13494 ? - y_avValue_fst__h682477 : + assign y_avValue_fst__h682609 = + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13504 ? + y_avValue_fst__h682580 : specTagManager$currentSpecBits ; - assign y_avValue_fst__h682540 = + assign y_avValue_fst__h682643 = ((fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && - regRenamingTable_rename_0_canRename__3408_AND__ETC___d13434) ? - y_avValue_fst__h682506 : + regRenamingTable_rename_0_canRename__3418_AND__ETC___d13444) ? + y_avValue_fst__h682609 : specTagManager$currentSpecBits ; - assign y_avValue_fst__h730870 = + assign y_avValue_fst__h730973 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[167] || rob$deqPort_0_deq_data[329:325] == 5'd0 || @@ -32248,10 +32257,10 @@ module mkCore(CLK, rob$deqPort_0_deq_data[329:325] == 5'd20) ? 5'd0 : rob$deqPort_0_deq_data[31:27] ; - assign y_avValue_fst__h734029 = - IF_rob_deqPort_0_canDeq__5338_THEN_IF_NOT_rob__ETC___d15665 | + assign y_avValue_fst__h734132 = + IF_rob_deqPort_0_canDeq__5348_THEN_IF_NOT_rob__ETC___d15675 | rob$deqPort_1_deq_data[31:27] ; - assign y_avValue_fst__h734061 = + assign y_avValue_fst__h734164 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[329:325] == 5'd0 || @@ -32263,17 +32272,17 @@ module mkCore(CLK, rob$deqPort_1_deq_data[329:325] == 5'd15 || rob$deqPort_1_deq_data[329:325] == 5'd19 || rob$deqPort_1_deq_data[329:325] == 5'd20) ? - IF_rob_deqPort_0_canDeq__5338_THEN_IF_NOT_rob__ETC___d15665 : - y_avValue_fst__h734029 ; - assign y_avValue_new_pc__h713085 = + IF_rob_deqPort_0_canDeq__5348_THEN_IF_NOT_rob__ETC___d15675 : + y_avValue_fst__h734132 ; + assign y_avValue_new_pc__h713188 = (csrf_stvec_mode_low_reg && commitStage_commitTrap[36]) ? - base__h713309 + { 58'd0, x__h713324 } : - base__h713309 ; - assign y_avValue_new_pc__h713271 = + base__h713412 + { 58'd0, x__h713427 } : + base__h713412 ; + assign y_avValue_new_pc__h713374 = (csrf_mtvec_mode_low_reg && commitStage_commitTrap[36]) ? - base__h713329 + { 58'd0, x__h713324 } : - base__h713329 ; - assign y_avValue_snd_snd_snd_fst__h731345 = + base__h713432 + { 58'd0, x__h713427 } : + base__h713432 ; + assign y_avValue_snd_snd_snd_fst__h731448 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[167] || rob$deqPort_0_deq_data[329:325] == 5'd0 || @@ -32287,7 +32296,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[329:325] == 5'd20) ? 2'd0 : 2'd1 ; - assign y_avValue_snd_snd_snd_fst__h734198 = + assign y_avValue_snd_snd_snd_fst__h734301 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[329:325] == 5'd0 || @@ -32299,12 +32308,12 @@ module mkCore(CLK, rob$deqPort_1_deq_data[329:325] == 5'd15 || rob$deqPort_1_deq_data[329:325] == 5'd19 || rob$deqPort_1_deq_data[329:325] == 5'd20) ? - IF_rob_deqPort_0_canDeq__5338_THEN_IF_NOT_rob__ETC___d15684 : - y_avValue_snd_snd_snd_fst__h734234 ; - assign y_avValue_snd_snd_snd_fst__h734234 = - IF_rob_deqPort_0_canDeq__5338_THEN_IF_NOT_rob__ETC___d15684 + + IF_rob_deqPort_0_canDeq__5348_THEN_IF_NOT_rob__ETC___d15694 : + y_avValue_snd_snd_snd_fst__h734337 ; + assign y_avValue_snd_snd_snd_fst__h734337 = + IF_rob_deqPort_0_canDeq__5348_THEN_IF_NOT_rob__ETC___d15694 + 2'd1 ; - assign y_avValue_snd_snd_snd_snd_snd_fst__h731355 = + assign y_avValue_snd_snd_snd_snd_snd_fst__h731458 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[167] || rob$deqPort_0_deq_data[329:325] == 5'd0 || @@ -32318,7 +32327,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[329:325] == 5'd20) ? 64'd0 : 64'd1 ; - assign y_avValue_snd_snd_snd_snd_snd_fst__h734208 = + assign y_avValue_snd_snd_snd_snd_snd_fst__h734311 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[329:325] == 5'd0 || @@ -32330,10 +32339,10 @@ module mkCore(CLK, rob$deqPort_1_deq_data[329:325] == 5'd15 || rob$deqPort_1_deq_data[329:325] == 5'd19 || rob$deqPort_1_deq_data[329:325] == 5'd20) ? - y__h731332 : - y_avValue_snd_snd_snd_snd_snd_fst__h734244 ; - assign y_avValue_snd_snd_snd_snd_snd_fst__h734244 = y__h731332 + 64'd1 ; - assign y_avValue_snd_snd_snd_snd_snd_snd_snd__h733620 = x__h726917 ; + y__h731435 : + y_avValue_snd_snd_snd_snd_snd_fst__h734347 ; + assign y_avValue_snd_snd_snd_snd_snd_fst__h734347 = y__h731435 + 64'd1 ; + assign y_avValue_snd_snd_snd_snd_snd_snd_snd__h733723 = x__h727020 ; always@(v_f_to_TV_1$D_OUT) begin case (v_f_to_TV_1$D_OUT[475:464]) @@ -32642,9 +32651,9 @@ module mkCore(CLK, always@(commitStage_commitTrap) begin case (commitStage_commitTrap[35:32]) - 4'd0, 4'd3: trap_val__h711388 = commitStage_commitTrap[164:101]; - 4'd2: trap_val__h711388 = { 32'd0, commitStage_commitTrap[31:0] }; - default: trap_val__h711388 = + 4'd0, 4'd3: trap_val__h711491 = commitStage_commitTrap[164:101]; + 4'd2: trap_val__h711491 = { 32'd0, commitStage_commitTrap[31:0] }; + default: trap_val__h711491 = (commitStage_commitTrap[35:32] != 4'd8 && commitStage_commitTrap[35:32] != 4'd9 && commitStage_commitTrap[35:32] != 4'd11) ? @@ -32700,46 +32709,46 @@ module mkCore(CLK, n__read__h611359 or n__read__h611550 or csrf_time_reg) begin case (f_csr_reqs$D_OUT[75:64]) - 12'd1: data_out__h738236 = fflags_csr__read__h609355; - 12'd2: data_out__h738236 = frm_csr__read__h609366; - 12'd3: data_out__h738236 = fcsr_csr__read__h609380; - 12'd256: data_out__h738236 = sstatus_csr__read__h609576; - 12'd260: data_out__h738236 = sie_csr__read__h609646; - 12'd261: data_out__h738236 = stvec_csr__read__h609689; - 12'd262: data_out__h738236 = scounteren_csr__read__h609742; - 12'd320: data_out__h738236 = csrf_sscratch_csr; - 12'd321: data_out__h738236 = csrf_sepc_csr; - 12'd322: data_out__h738236 = scause_csr__read__h609880; - 12'd323: data_out__h738236 = csrf_stval_csr; - 12'd324: data_out__h738236 = sip_csr__read__h610020; - 12'd384: data_out__h738236 = satp_csr__read__h610083; - 12'd768: data_out__h738236 = mstatus_csr__read__h610226; - 12'd769: data_out__h738236 = 64'h800000000014112D; - 12'd770: data_out__h738236 = medeleg_csr__read__h610374; - 12'd771: data_out__h738236 = mideleg_csr__read__h610469; - 12'd772: data_out__h738236 = mie_csr__read__h610593; - 12'd773: data_out__h738236 = mtvec_csr__read__h610675; - 12'd774: data_out__h738236 = mcounteren_csr__read__h610767; - 12'd832: data_out__h738236 = csrf_mscratch_csr; - 12'd833: data_out__h738236 = csrf_mepc_csr; - 12'd834: data_out__h738236 = mcause_csr__read__h611022; - 12'd835: data_out__h738236 = csrf_mtval_csr; - 12'd836: data_out__h738236 = mip_csr__read__h611255; - 12'd1952: data_out__h738236 = csrf_rg_tselect; - 12'd1953: data_out__h738236 = rg_tdata1__read__h612210; - 12'd1954: data_out__h738236 = csrf_rg_tdata2; - 12'd1955: data_out__h738236 = csrf_rg_tdata3; - 12'd1968: data_out__h738236 = csrf_rg_dcsr; - 12'd1969: data_out__h738236 = csrf_rg_dpc; - 12'd1970: data_out__h738236 = csrf_rg_dscratch0; - 12'd1971: data_out__h738236 = csrf_rg_dscratch1; + 12'd1: data_out__h738339 = fflags_csr__read__h609355; + 12'd2: data_out__h738339 = frm_csr__read__h609366; + 12'd3: data_out__h738339 = fcsr_csr__read__h609380; + 12'd256: data_out__h738339 = sstatus_csr__read__h609576; + 12'd260: data_out__h738339 = sie_csr__read__h609646; + 12'd261: data_out__h738339 = stvec_csr__read__h609689; + 12'd262: data_out__h738339 = scounteren_csr__read__h609742; + 12'd320: data_out__h738339 = csrf_sscratch_csr; + 12'd321: data_out__h738339 = csrf_sepc_csr; + 12'd322: data_out__h738339 = scause_csr__read__h609880; + 12'd323: data_out__h738339 = csrf_stval_csr; + 12'd324: data_out__h738339 = sip_csr__read__h610020; + 12'd384: data_out__h738339 = satp_csr__read__h610083; + 12'd768: data_out__h738339 = mstatus_csr__read__h610226; + 12'd769: data_out__h738339 = 64'h800000000014112D; + 12'd770: data_out__h738339 = medeleg_csr__read__h610374; + 12'd771: data_out__h738339 = mideleg_csr__read__h610469; + 12'd772: data_out__h738339 = mie_csr__read__h610593; + 12'd773: data_out__h738339 = mtvec_csr__read__h610675; + 12'd774: data_out__h738339 = mcounteren_csr__read__h610767; + 12'd832: data_out__h738339 = csrf_mscratch_csr; + 12'd833: data_out__h738339 = csrf_mepc_csr; + 12'd834: data_out__h738339 = mcause_csr__read__h611022; + 12'd835: data_out__h738339 = csrf_mtval_csr; + 12'd836: data_out__h738339 = mip_csr__read__h611255; + 12'd1952: data_out__h738339 = csrf_rg_tselect; + 12'd1953: data_out__h738339 = rg_tdata1__read__h612210; + 12'd1954: data_out__h738339 = csrf_rg_tdata2; + 12'd1955: data_out__h738339 = csrf_rg_tdata3; + 12'd1968: data_out__h738339 = csrf_rg_dcsr; + 12'd1969: data_out__h738339 = csrf_rg_dpc; + 12'd1970: data_out__h738339 = csrf_rg_dscratch0; + 12'd1971: data_out__h738339 = csrf_rg_dscratch1; 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: - data_out__h738236 = 64'd0; - 12'd2049: data_out__h738236 = x_reg_ifc__read__h609485; - 12'd2816, 12'd3072: data_out__h738236 = n__read__h611359; - 12'd2818, 12'd3074: data_out__h738236 = n__read__h611550; - 12'd3073: data_out__h738236 = csrf_time_reg; - default: data_out__h738236 = 64'b0; + data_out__h738339 = 64'd0; + 12'd2049: data_out__h738339 = x_reg_ifc__read__h609485; + 12'd2816, 12'd3072: data_out__h738339 = n__read__h611359; + 12'd2818, 12'd3074: data_out__h738339 = n__read__h611550; + 12'd3073: data_out__h738339 = csrf_time_reg; + default: data_out__h738339 = 64'b0; endcase end always@(coreFix_aluExe_1_dispToRegQ$first or @@ -33162,16 +33171,16 @@ module mkCore(CLK, 4'd11, 4'd12, 4'd13: - i__h710364 = commitStage_commitTrap[35:32]; - default: i__h710364 = 4'd15; + i__h710467 = commitStage_commitTrap[35:32]; + default: i__h710467 = 4'd15; endcase end always@(commitStage_commitTrap) begin case (commitStage_commitTrap[35:32]) 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: - i__h710524 = commitStage_commitTrap[35:32]; - default: i__h710524 = 4'd15; + i__h710627 = commitStage_commitTrap[35:32]; + default: i__h710627 = 4'd15; endcase end always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) @@ -37518,15 +37527,15 @@ module mkCore(CLK, 4'd13; endcase end - always@(k__h670531 or + always@(k__h670634 or coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq) begin - case (k__h670531) + case (k__h670634) 1'd0: - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3443_co_ETC___d13453 = + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463 = coreFix_aluExe_0_rsAlu$canEnq; 1'd1: - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3443_co_ETC___d13453 = + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463 = coreFix_aluExe_1_rsAlu$canEnq; endcase end @@ -37535,65 +37544,65 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13466 = + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13476 = coreFix_memExe_lsq$enqLdTag[6]; - default: IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13466 = + default: IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13476 = coreFix_memExe_lsq$enqStTag[6]; endcase end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13466 or - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3443_co_ETC___d13453 or + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13476 or + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13470 = - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3443_co_ETC___d13453; + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13480 = + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463; 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13470 = + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13480 = coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq; - default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13470 = + default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13480 = fetchStage$pipelines_0_first[194:192] != 3'd2 || coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13466; + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13476; endcase end - always@(k__h670531 or + always@(k__h670634 or coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq) begin - case (k__h670531) + case (k__h670634) 1'd0: - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__344_ETC___d13487 = + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__345_ETC___d13497 = !coreFix_aluExe_0_rsAlu$canEnq; 1'd1: - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__344_ETC___d13487 = + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__345_ETC___d13497 = !coreFix_aluExe_1_rsAlu$canEnq; endcase end always@(fetchStage$pipelines_0_first or - regRenamingTable_rename_0_canRename__3408_AND__ETC___d13434 or - NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13489 or + regRenamingTable_rename_0_canRename__3418_AND__ETC___d13444 or + NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13499 or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13466 or + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13476 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13494 = - NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13489; + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13504 = + NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13499; 3'd2: - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13494 = + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13504 = coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13466 && - regRenamingTable_rename_0_canRename__3408_AND__ETC___d13434; + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13476 && + regRenamingTable_rename_0_canRename__3418_AND__ETC___d13444; 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13494 = + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13504 = coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq && - regRenamingTable_rename_0_canRename__3408_AND__ETC___d13434; - default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13494 = - regRenamingTable_rename_0_canRename__3408_AND__ETC___d13434; + regRenamingTable_rename_0_canRename__3418_AND__ETC___d13444; + default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13504 = + regRenamingTable_rename_0_canRename__3418_AND__ETC___d13444; endcase end always@(fetchStage$pipelines_0_first or @@ -37601,32 +37610,32 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13524 = + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13534 = !coreFix_memExe_lsq$enqLdTag[6]; - default: IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13524 = + default: IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13534 = !coreFix_memExe_lsq$enqStTag[6]; endcase end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13524 or - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__344_ETC___d13487 or + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13534 or + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__345_ETC___d13497 or specTagManager$canClaim or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13529 = - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__344_ETC___d13487 || + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13539 = + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__345_ETC___d13497 || fetchStage$pipelines_0_first[194:192] == 3'd1 && !specTagManager$canClaim; 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13529 = + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13539 = !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq; - default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13529 = + default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13539 = fetchStage$pipelines_0_first[194:192] == 3'd2 && (!coreFix_memExe_rsMem$canEnq || - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13524); + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13534); endcase end always@(fetchStage$pipelines_1_first) @@ -37696,36 +37705,36 @@ module mkCore(CLK, begin case (fetchStage$pipelines_1_first[194:192]) 3'd0, 3'd1, 3'd2, 3'd3: - IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13589 = + IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13599 = fetchStage$pipelines_1_first[194:174]; 3'd4: - IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13589 = + IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13599 = { fetchStage$pipelines_1_first[194:192], 9'h0AA, fetchStage$pipelines_1_first[182:178], CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q236, fetchStage$pipelines_1_first[174] }; - default: IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13589 = + default: IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13599 = 21'd1485482; endcase end - always@(idx__h686276 or + always@(idx__h686379 or fetchStage$pipelines_0_canDeq or - NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13751 or + NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13761 or coreFix_aluExe_0_rsAlu$canEnq or - NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13757 or + NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13767 or coreFix_aluExe_1_rsAlu$canEnq) begin - case (idx__h686276) + case (idx__h686379) 1'd0: - SEL_ARR_fetchStage_pipelines_0_canDeq__2755_AN_ETC___d13777 = + SEL_ARR_fetchStage_pipelines_0_canDeq__2755_AN_ETC___d13787 = fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13751 || + NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13761 || !coreFix_aluExe_0_rsAlu$canEnq; 1'd1: - SEL_ARR_fetchStage_pipelines_0_canDeq__2755_AN_ETC___d13777 = + SEL_ARR_fetchStage_pipelines_0_canDeq__2755_AN_ETC___d13787 = fetchStage$pipelines_0_canDeq && - NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13757 || + NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13767 || !coreFix_aluExe_1_rsAlu$canEnq; endcase end @@ -37741,61 +37750,61 @@ module mkCore(CLK, endcase end always@(fetchStage$pipelines_0_first or - renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13845 or - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__344_ETC___d13487 or - fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13849 or + renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13855 or + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__345_ETC___d13497 or + fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13859 or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13524 or + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13534 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13855 = - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__344_ETC___d13487 || - fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13849; + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13865 = + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__345_ETC___d13497 || + fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13859; 3'd2: - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13855 = + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13865 = !coreFix_memExe_rsMem$canEnq || - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13524 || - renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13845; + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13534 || + renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13855; 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13855 = + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13865 = !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq || - renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13845; - default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13855 = - renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13845; + renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13855; + default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13865 = + renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13855; endcase end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13466 or - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3443_co_ETC___d13453) + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13476 or + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13877 = - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3443_co_ETC___d13453; - default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13877 = + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13887 = + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463; + default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13887 = fetchStage$pipelines_0_first[194:192] != 3'd2 || coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13466; + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13476; endcase end always@(fetchStage$pipelines_0_first or - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13466 or - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3443_co_ETC___d13453 or + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13476 or + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13895 = - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3443_co_ETC___d13453; + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13905 = + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463; 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13895 = + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13905 = coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq; - default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13895 = + default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13905 = fetchStage$pipelines_0_first[194:192] != 3'd2 || - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13466; + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13476; endcase end always@(fetchStage$pipelines_1_first or @@ -37810,62 +37819,31 @@ module mkCore(CLK, endcase end always@(fetchStage$pipelines_1_first or - regRenamingTable_rename_1_canRename__3535_AND__ETC___d13743 or - SEL_ARR_fetchStage_pipelines_0_canDeq__2755_AN_ETC___d13777 or - NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d13861 or - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13892 or - regRenamingTable_rename_1_canRename__3535_AND__ETC___d13903 or - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13874 or + regRenamingTable_rename_1_canRename__3545_AND__ETC___d13753 or + SEL_ARR_fetchStage_pipelines_0_canDeq__2755_AN_ETC___d13787 or + NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d13871 or + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13902 or + regRenamingTable_rename_1_canRename__3545_AND__ETC___d13913 or + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13884 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq or - regRenamingTable_rename_1_canRename__3535_AND__ETC___d13885) + regRenamingTable_rename_1_canRename__3545_AND__ETC___d13895) begin case (fetchStage$pipelines_1_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13907 = - !SEL_ARR_fetchStage_pipelines_0_canDeq__2755_AN_ETC___d13777 && - NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d13861; + IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13917 = + !SEL_ARR_fetchStage_pipelines_0_canDeq__2755_AN_ETC___d13787 && + NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d13871; 3'd2: - IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13907 = - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13892 && - regRenamingTable_rename_1_canRename__3535_AND__ETC___d13903; + IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13917 = + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13902 && + regRenamingTable_rename_1_canRename__3545_AND__ETC___d13913; 3'd3, 3'd4: - IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13907 = - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13874 && + IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13917 = + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13884 && coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq && - regRenamingTable_rename_1_canRename__3535_AND__ETC___d13885; - default: IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13907 = - regRenamingTable_rename_1_canRename__3535_AND__ETC___d13743; - endcase - end - always@(k__h670531 or - coreFix_aluExe_0_rsAlu$RDY_enq or coreFix_aluExe_1_rsAlu$RDY_enq) - begin - case (k__h670531) - 1'd0: - CASE_k70531_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239 = - coreFix_aluExe_0_rsAlu$RDY_enq; - 1'd1: - CASE_k70531_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239 = - coreFix_aluExe_1_rsAlu$RDY_enq; - endcase - end - always@(fetchStage$pipelines_0_first or - coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13524 or - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__344_ETC___d13487 or - coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) - begin - case (fetchStage$pipelines_0_first[194:192]) - 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13952 = - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__344_ETC___d13487; - 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13952 = - !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq; - default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13952 = - fetchStage$pipelines_0_first[194:192] == 3'd2 && - (!coreFix_memExe_rsMem$canEnq || - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13524); + regRenamingTable_rename_1_canRename__3545_AND__ETC___d13895; + default: IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13917 = + regRenamingTable_rename_1_canRename__3545_AND__ETC___d13753; endcase end always@(fetchStage$pipelines_0_first or @@ -37873,105 +37851,136 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q240 = + CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q239 = coreFix_memExe_lsq$RDY_enqLd; - default: CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q240 = + default: CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q239 = coreFix_memExe_lsq$RDY_enqSt; endcase end + always@(k__h670634 or + coreFix_aluExe_0_rsAlu$RDY_enq or coreFix_aluExe_1_rsAlu$RDY_enq) + begin + case (k__h670634) + 1'd0: + CASE_k70634_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q240 = + coreFix_aluExe_0_rsAlu$RDY_enq; + 1'd1: + CASE_k70634_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q240 = + coreFix_aluExe_1_rsAlu$RDY_enq; + endcase + end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13524 or - regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13946 or - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3443_co_ETC___d13453 or + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13534 or + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__345_ETC___d13497 or + coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) + begin + case (fetchStage$pipelines_0_first[194:192]) + 3'd0, 3'd1: + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13962 = + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__345_ETC___d13497; + 3'd3, 3'd4: + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13962 = + !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq; + default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13962 = + fetchStage$pipelines_0_first[194:192] == 3'd2 && + (!coreFix_memExe_rsMem$canEnq || + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13534); + endcase + end + always@(fetchStage$pipelines_0_first or + coreFix_memExe_rsMem$canEnq or + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13534 or + regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13956 or + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463 or regRenamingTable$RDY_rename_0_getRename or - _0_OR_NOT_fetchStage_pipelines_0_first__2757_BI_ETC___d13933 or + _0_OR_NOT_fetchStage_pipelines_0_first__2757_BI_ETC___d13943 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq or coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_enq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13950 = - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3443_co_ETC___d13453 || + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13960 = + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463 || regRenamingTable$RDY_rename_0_getRename && - _0_OR_NOT_fetchStage_pipelines_0_first__2757_BI_ETC___d13933; + _0_OR_NOT_fetchStage_pipelines_0_first__2757_BI_ETC___d13943; 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13950 = + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13960 = !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq || coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_enq && regRenamingTable$RDY_rename_0_getRename; - default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13950 = + default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13960 = fetchStage$pipelines_0_first[194:192] != 3'd2 || !coreFix_memExe_rsMem$canEnq || - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13524 || - regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13946; + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13534 || + regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13956; endcase end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13524 or - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3443_co_ETC___d13453 or + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13534 or + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13966 = - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3443_co_ETC___d13453; + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13976 = + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463; 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13966 = + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13976 = !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq; - default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13966 = + default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13976 = fetchStage$pipelines_0_first[194:192] == 3'd2 && (!coreFix_memExe_rsMem$canEnq || - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13524); + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13534); endcase end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13466 or - SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__344_ETC___d13487 or + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13476 or + SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__345_ETC___d13497 or specTagManager$canClaim or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13973 = - !SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__344_ETC___d13487 && + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13983 = + !SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__345_ETC___d13497 && (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim); 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13973 = + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13983 = coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq; - default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13973 = + default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13983 = fetchStage$pipelines_0_first[194:192] != 3'd2 || coreFix_memExe_rsMem$canEnq && - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13466; + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13476; endcase end - always@(idx__h686276 or + always@(idx__h686379 or fetchStage$pipelines_0_canDeq or - fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13996 or + fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d14006 or coreFix_aluExe_0_rsAlu$canEnq or - fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d14003 or + fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d14013 or coreFix_aluExe_1_rsAlu$canEnq) begin - case (idx__h686276) + case (idx__h686379) 1'd0: - SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__275_ETC___d14007 = + SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__275_ETC___d14017 = (!fetchStage$pipelines_0_canDeq || - fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13996) && + fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d14006) && coreFix_aluExe_0_rsAlu$canEnq; 1'd1: - SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__275_ETC___d14007 = + SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__275_ETC___d14017 = (!fetchStage$pipelines_0_canDeq || - fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d14003) && + fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d14013) && coreFix_aluExe_1_rsAlu$canEnq; endcase end - always@(fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14023 or + always@(fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14033 or coreFix_aluExe_0_rsAlu$RDY_enq or coreFix_aluExe_1_rsAlu$RDY_enq) begin - case (fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14023) + case (fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14033) 1'd0: CASE_fetchStage_pipelines_0_canDeq__2755_AND_N_ETC__q241 = coreFix_aluExe_0_rsAlu$RDY_enq; @@ -37993,78 +38002,78 @@ module mkCore(CLK, end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13524 or - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3443_co_ETC___d13453) + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13534 or + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d14049 = - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3443_co_ETC___d13453; - default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d14049 = + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d14059 = + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463; + default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d14059 = fetchStage$pipelines_0_first[194:192] == 3'd2 && (!coreFix_memExe_rsMem$canEnq || - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13524); + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13534); endcase end always@(fetchStage$pipelines_0_first or - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13524 or - SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3443_co_ETC___d13453 or + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13534 or + SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) begin case (fetchStage$pipelines_0_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d14061 = - !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3443_co_ETC___d13453; + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d14071 = + !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463; 3'd3, 3'd4: - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d14061 = + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d14071 = !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq; - default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d14061 = + default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d14071 = fetchStage$pipelines_0_first[194:192] == 3'd2 && - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13524; + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13534; endcase end always@(fetchStage$pipelines_1_first or - fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14070 or - SEL_ARR_fetchStage_pipelines_0_canDeq__2755_AN_ETC___d13777 or - fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14058) + fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14080 or + SEL_ARR_fetchStage_pipelines_0_canDeq__2755_AN_ETC___d13787 or + fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14068) begin case (fetchStage$pipelines_1_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14073 = - SEL_ARR_fetchStage_pipelines_0_canDeq__2755_AN_ETC___d13777; + IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14083 = + SEL_ARR_fetchStage_pipelines_0_canDeq__2755_AN_ETC___d13787; 3'd3, 3'd4: - IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14073 = - fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14058; - default: IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14073 = + IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14083 = + fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14068; + default: IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14083 = fetchStage$pipelines_1_first[194:192] == 3'd2 && - fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14070; + fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14080; endcase end always@(fetchStage$pipelines_1_first or - fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14036 or + fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14046 or regRenamingTable$RDY_rename_1_getRename or - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14041 or - SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__275_ETC___d14007 or - regRenamingTable_RDY_rename_1_getRename__4009__ETC___d14027 or - fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14029 or + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14051 or + SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__275_ETC___d14017 or + regRenamingTable_RDY_rename_1_getRename__4019__ETC___d14037 or + fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14039 or coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq or - coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__39_ETC___d14032) + coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__39_ETC___d14042) begin case (fetchStage$pipelines_1_first[194:192]) 3'd0, 3'd1: - IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14046 = - !SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__275_ETC___d14007 || - regRenamingTable_RDY_rename_1_getRename__4009__ETC___d14027; + IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14056 = + !SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__275_ETC___d14017 || + regRenamingTable_RDY_rename_1_getRename__4019__ETC___d14037; 3'd3, 3'd4: - IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14046 = - fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14029 || + IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14056 = + fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14039 || !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq || - coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__39_ETC___d14032; - default: IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14046 = + coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__39_ETC___d14042; + default: IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14056 = fetchStage$pipelines_1_first[194:192] != 3'd2 || - fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14036 || + fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14046 || regRenamingTable$RDY_rename_1_getRename && - NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14041; + NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14051; endcase end always@(fetchStage$pipelines_0_first or @@ -38072,9 +38081,9 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14130 = + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14140 = !coreFix_memExe_lsq$enqLdTag[5]; - default: IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14130 = + default: IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14140 = !coreFix_memExe_lsq$enqStTag[5]; endcase end @@ -38083,9 +38092,9 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14127 = + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14137 = coreFix_memExe_lsq$enqLdTag[5]; - default: IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14127 = + default: IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14137 = coreFix_memExe_lsq$enqStTag[5]; endcase end @@ -38094,9 +38103,9 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14136 = + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14146 = coreFix_memExe_lsq$enqLdTag[3:0]; - default: IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14136 = + default: IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14146 = coreFix_memExe_lsq$enqStTag[3:0]; endcase end @@ -38105,9 +38114,9 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14133 = + IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14143 = coreFix_memExe_lsq$enqLdTag[4:0]; - default: IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14133 = + default: IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14143 = coreFix_memExe_lsq$enqStTag[4:0]; endcase end @@ -38116,9 +38125,9 @@ module mkCore(CLK, begin case (fetchStage$pipelines_1_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14267 = + IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14277 = coreFix_memExe_lsq$enqLdTag[3:0]; - default: IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14267 = + default: IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14277 = coreFix_memExe_lsq$enqStTag[3:0]; endcase end @@ -38127,9 +38136,9 @@ module mkCore(CLK, begin case (fetchStage$pipelines_1_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14265 = + IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14275 = !coreFix_memExe_lsq$enqLdTag[5]; - default: IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14265 = + default: IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14275 = !coreFix_memExe_lsq$enqStTag[5]; endcase end @@ -38138,9 +38147,9 @@ module mkCore(CLK, begin case (fetchStage$pipelines_1_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14264 = + IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14274 = coreFix_memExe_lsq$enqLdTag[5]; - default: IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14264 = + default: IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14274 = coreFix_memExe_lsq$enqStTag[5]; endcase end @@ -38149,9 +38158,9 @@ module mkCore(CLK, begin case (fetchStage$pipelines_1_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14266 = + IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14276 = coreFix_memExe_lsq$enqLdTag[4:0]; - default: IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14266 = + default: IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14276 = coreFix_memExe_lsq$enqStTag[4:0]; endcase end @@ -38185,112 +38194,112 @@ module mkCore(CLK, begin case (rob$deqPort_0_deq_data[180:169]) 12'd1: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd0; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd0; 12'd2: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd1; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd1; 12'd3: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd2; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd2; 12'd256: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd8; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd8; 12'd260: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd9; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd9; 12'd261: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd10; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd10; 12'd262: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd11; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd11; 12'd320: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd12; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd12; 12'd321: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd13; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd13; 12'd322: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd14; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd14; 12'd323: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd15; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd15; 12'd324: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd16; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd16; 12'd384: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd17; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd17; 12'd768: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd18; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd18; 12'd769: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd19; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd19; 12'd770: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd20; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd20; 12'd771: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd21; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd21; 12'd772: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd22; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd22; 12'd773: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd23; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd23; 12'd774: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd24; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd24; 12'd832: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd25; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd25; 12'd833: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd26; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd26; 12'd834: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd27; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd27; 12'd835: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd28; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd28; 12'd836: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd29; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd29; 12'd1952: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd36; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd36; 12'd1953: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd37; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd37; 12'd1954: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd38; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd38; 12'd1955: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd39; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd39; 12'd1968: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd40; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd40; 12'd1969: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd41; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd41; 12'd1970: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd42; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd42; 12'd1971: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd43; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd43; 12'd2048: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd6; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd6; 12'd2049: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd7; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd7; 12'd2816: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd30; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd30; 12'd2818: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd31; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd31; 12'd3072: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd3; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd3; 12'd3073: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd4; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd4; 12'd3074: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd5; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd5; 12'd3857: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd32; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd32; 12'd3858: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd33; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd33; 12'd3859: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd34; + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd34; 12'd3860: - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = 6'd35; - default: IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 = + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd35; + default: IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd44; endcase end - always@(IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 or + always@(IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 or rob$deqPort_0_deq_data or robdeqPort_0_deq_data_BITS_95_TO_32__q245) begin - case (IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988) + case (IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998) 6'd0: - data_warl_xformed__h723335 = + data_warl_xformed__h723438 = { 59'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[4:0] }; 6'd1, 6'd11, 6'd24: - data_warl_xformed__h723335 = + data_warl_xformed__h723438 = { 61'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[2:0] }; 6'd2: - data_warl_xformed__h723335 = + data_warl_xformed__h723438 = { 56'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[7:0] }; 6'd8: - data_warl_xformed__h723335 = + data_warl_xformed__h723438 = { robdeqPort_0_deq_data_BITS_95_TO_32__q245[14:13] == 2'b11, 43'd8192, robdeqPort_0_deq_data_BITS_95_TO_32__q245[19:18], @@ -38303,7 +38312,7 @@ module mkCore(CLK, 2'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[1:0] }; 6'd9, 6'd16: - data_warl_xformed__h723335 = + data_warl_xformed__h723438 = { 54'd0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[9], 3'd0, @@ -38312,22 +38321,22 @@ module mkCore(CLK, robdeqPort_0_deq_data_BITS_95_TO_32__q245[1], 1'd0 }; 6'd10, 6'd23: - data_warl_xformed__h723335 = + data_warl_xformed__h723438 = { robdeqPort_0_deq_data_BITS_95_TO_32__q245[63:2], 1'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[0] }; 6'd14, 6'd27: - data_warl_xformed__h723335 = + data_warl_xformed__h723438 = { robdeqPort_0_deq_data_BITS_95_TO_32__q245[63], 59'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[3:0] }; 6'd17: - data_warl_xformed__h723335 = + data_warl_xformed__h723438 = { robdeqPort_0_deq_data_BITS_95_TO_32__q245[63], 19'd0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[43:0] }; 6'd18: - data_warl_xformed__h723335 = + data_warl_xformed__h723438 = { robdeqPort_0_deq_data_BITS_95_TO_32__q245[14:13] == 2'b11, 40'd5120, robdeqPort_0_deq_data_BITS_95_TO_32__q245[22:17], @@ -38339,9 +38348,9 @@ module mkCore(CLK, robdeqPort_0_deq_data_BITS_95_TO_32__q245[5:3], 1'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[1:0] }; - 6'd19: data_warl_xformed__h723335 = 64'h800000000014112D; + 6'd19: data_warl_xformed__h723438 = 64'h800000000014112D; 6'd20: - data_warl_xformed__h723335 = + data_warl_xformed__h723438 = { 48'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[15], 1'b0, @@ -38349,7 +38358,7 @@ module mkCore(CLK, 1'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[9:0] }; 6'd21: - data_warl_xformed__h723335 = + data_warl_xformed__h723438 = { 52'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[11], 1'b0, @@ -38359,7 +38368,7 @@ module mkCore(CLK, 1'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[1:0] }; 6'd22, 6'd29: - data_warl_xformed__h723335 = + data_warl_xformed__h723438 = { 52'd0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[11], 1'd0, @@ -38373,12 +38382,12 @@ module mkCore(CLK, 1'd0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[1], 1'd0 }; - 6'd32, 6'd33, 6'd34, 6'd35: data_warl_xformed__h723335 = 64'd0; + 6'd32, 6'd33, 6'd34, 6'd35: data_warl_xformed__h723438 = 64'd0; 6'd37: - data_warl_xformed__h723335 = + data_warl_xformed__h723438 = { 4'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[59:0] }; 6'd40: - data_warl_xformed__h723335 = + data_warl_xformed__h723438 = { 32'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[31:28], 12'b0, @@ -38387,7 +38396,7 @@ module mkCore(CLK, robdeqPort_0_deq_data_BITS_95_TO_32__q245[13:6], 1'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[4:0] }; - default: data_warl_xformed__h723335 = rob$deqPort_0_deq_data[95:32]; + default: data_warl_xformed__h723438 = rob$deqPort_0_deq_data[95:32]; endcase end always@(rob$deqPort_0_deq_data) @@ -38444,13 +38453,13 @@ module mkCore(CLK, endcase end always@(rob$deqPort_0_deq_data or - IF_rob_deqPort_0_deq_data__4344_BITS_329_TO_32_ETC___d15196) + IF_rob_deqPort_0_deq_data__4354_BITS_329_TO_32_ETC___d15206) begin case (rob$deqPort_0_deq_data[329:325]) 5'd19, 5'd20: - x__h723943 = - IF_rob_deqPort_0_deq_data__4344_BITS_329_TO_32_ETC___d15196; - default: x__h723943 = rob$deqPort_0_deq_data[425:362]; + x__h724046 = + IF_rob_deqPort_0_deq_data__4354_BITS_329_TO_32_ETC___d15206; + default: x__h724046 = rob$deqPort_0_deq_data[425:362]; endcase end always@(rob$deqPort_0_deq_data) @@ -41158,7 +41167,7 @@ module mkCore(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4344_BIT_181_4419_T_ETC___d14988 == 6'd6) + IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd6) $display("[Terminate CSR] being written (val = %x), ", "send terminate signal to host", rob$deqPort_0_deq_data[95:32]); @@ -41270,7 +41279,7 @@ module mkCore(CLK, rob$deqPort_1_deq_data[329:325] != 5'd19 && rob$deqPort_1_deq_data[329:325] != 5'd20) $write("instret:%0d PC:0x%0h instr:0x%08h", - commitStage_rg_serial_num_4333_PLUS_IF_rob_deq_ETC___d15459, + commitStage_rg_serial_num_4343_PLUS_IF_rob_deq_ETC___d15469, rob$deqPort_1_deq_data[425:362], rob$deqPort_1_deq_data[361:330], " iType:"); diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkCoreW.v b/src_SSITH_P3/xilinx_ip/hdl/mkCoreW.v index bb0d3be..ea0a6ee 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkCoreW.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkCoreW.v @@ -2716,22 +2716,22 @@ module mkCoreW(RST_N_dm_power_on_reset, // rule RL_rl_dm_hart0_reset_wait assign CAN_FIRE_RL_rl_dm_hart0_reset_wait = (rg_hart0_reset_delay != 8'd1 || - proc$RDY_start && - debug_module$RDY_hart0_reset_client_response_put) && + debug_module$RDY_hart0_reset_client_response_put && + proc$RDY_start) && rg_hart0_reset_delay != 8'd0 ; assign WILL_FIRE_RL_rl_dm_hart0_reset_wait = CAN_FIRE_RL_rl_dm_hart0_reset_wait && !EN_start ; // rule RL_ClientServerRequest assign CAN_FIRE_RL_ClientServerRequest = - proc$RDY_hart0_run_halt_server_request_put && - debug_module$RDY_hart0_client_run_halt_request_get ; + debug_module$RDY_hart0_client_run_halt_request_get && + proc$RDY_hart0_run_halt_server_request_put ; assign WILL_FIRE_RL_ClientServerRequest = CAN_FIRE_RL_ClientServerRequest ; // rule RL_ClientServerResponse assign CAN_FIRE_RL_ClientServerResponse = - proc$RDY_hart0_run_halt_server_response_get && - debug_module$RDY_hart0_client_run_halt_response_put ; + debug_module$RDY_hart0_client_run_halt_response_put && + proc$RDY_hart0_run_halt_server_response_get ; assign WILL_FIRE_RL_ClientServerResponse = CAN_FIRE_RL_ClientServerResponse ; @@ -2743,25 +2743,25 @@ module mkCoreW(RST_N_dm_power_on_reset, // rule RL_mkConnectionGetPut_1 assign CAN_FIRE_RL_mkConnectionGetPut_1 = - proc$RDY_v_to_TV_0_get && v_td2_to_td_0$RDY_in_put ; + v_td2_to_td_0$RDY_in_put && proc$RDY_v_to_TV_0_get ; assign WILL_FIRE_RL_mkConnectionGetPut_1 = CAN_FIRE_RL_mkConnectionGetPut_1 ; // rule RL_mkConnectionGetPut_2 assign CAN_FIRE_RL_mkConnectionGetPut_2 = - tv_encode$RDY_v_cpu_in_0_put && v_td2_to_td_0$RDY_out_get ; + v_td2_to_td_0$RDY_out_get && tv_encode$RDY_v_cpu_in_0_put ; assign WILL_FIRE_RL_mkConnectionGetPut_2 = CAN_FIRE_RL_mkConnectionGetPut_2 ; // rule RL_mkConnectionGetPut_3 assign CAN_FIRE_RL_mkConnectionGetPut_3 = - proc$RDY_v_to_TV_1_get && v_td2_to_td_1$RDY_in_put ; + v_td2_to_td_1$RDY_in_put && proc$RDY_v_to_TV_1_get ; assign WILL_FIRE_RL_mkConnectionGetPut_3 = CAN_FIRE_RL_mkConnectionGetPut_3 ; // rule RL_mkConnectionGetPut_4 assign CAN_FIRE_RL_mkConnectionGetPut_4 = - tv_encode$RDY_v_cpu_in_1_put && v_td2_to_td_1$RDY_out_get ; + v_td2_to_td_1$RDY_out_get && tv_encode$RDY_v_cpu_in_1_put ; assign WILL_FIRE_RL_mkConnectionGetPut_4 = CAN_FIRE_RL_mkConnectionGetPut_4 ; diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkP3_Core.v b/src_SSITH_P3/xilinx_ip/hdl/mkP3_Core.v index b1f7022..1b6b7c2 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkP3_Core.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkP3_Core.v @@ -1434,7 +1434,7 @@ module mkP3_Core(CLK, // rule RL_rl_ndm_reset_wait assign CAN_FIRE_RL_rl_ndm_reset_wait = (rg_ndm_reset_delay != 8'd1 || - corew$RDY_start && corew$RDY_ndm_reset_client_response_put) && + corew$RDY_ndm_reset_client_response_put && corew$RDY_start) && rg_ndm_reset_delay != 8'd0 ; assign WILL_FIRE_RL_rl_ndm_reset_wait = CAN_FIRE_RL_rl_ndm_reset_wait ; diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkProc.v b/src_SSITH_P3/xilinx_ip/hdl/mkProc.v index 8e3867b..5a65043 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkProc.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkProc.v @@ -2104,8 +2104,8 @@ module mkProc(CLK, // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h162860; - reg [31 : 0] v__h162396; + reg [31 : 0] v__h162844; + reg [31 : 0] v__h162380; reg [31 : 0] v__h5520; reg [31 : 0] v__h5693; reg [31 : 0] v__h5953; @@ -2116,13 +2116,13 @@ module mkProc(CLK, reg [31 : 0] v__h9480; reg [31 : 0] v__h9973; reg [31 : 0] v__h10136; - reg [31 : 0] v__h134353; - reg [31 : 0] v__h134520; - reg [31 : 0] v__h136623; - reg [31 : 0] v__h153967; - reg [31 : 0] v__h133734; - reg [31 : 0] v__h160661; - reg [31 : 0] v__h161169; + reg [31 : 0] v__h134337; + reg [31 : 0] v__h134504; + reg [31 : 0] v__h136607; + reg [31 : 0] v__h153951; + reg [31 : 0] v__h133718; + reg [31 : 0] v__h160645; + reg [31 : 0] v__h161153; reg [31 : 0] v__h2664; reg [31 : 0] v__h4337; reg [31 : 0] v__h5514; @@ -2133,282 +2133,280 @@ module mkProc(CLK, reg [31 : 0] v__h9474; reg [31 : 0] v__h9967; reg [31 : 0] v__h10130; - reg [31 : 0] v__h133728; - reg [31 : 0] v__h134347; - reg [31 : 0] v__h134514; - reg [31 : 0] v__h136617; - reg [31 : 0] v__h153961; - reg [31 : 0] v__h160655; - reg [31 : 0] v__h161163; - reg [31 : 0] v__h162390; - reg [31 : 0] v__h162854; + reg [31 : 0] v__h133712; + reg [31 : 0] v__h134331; + reg [31 : 0] v__h134498; + reg [31 : 0] v__h136601; + reg [31 : 0] v__h153945; + reg [31 : 0] v__h160639; + reg [31 : 0] v__h161147; + reg [31 : 0] v__h162374; + reg [31 : 0] v__h162838; // synopsys translate_on // remaining internal signals reg [63 : 0] CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13, CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14, CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17, - CASE_x1277_0_n__read_addr1459_1_n__read_addr15_ETC__q23, - CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24, - CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25, - CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26, - CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27, - CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28, - CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29, - CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30, - CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31, - CASE_x9900_0_n__read_addr0078_1_n__read_addr01_ETC__q34, - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d805, - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d818, - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d857, - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d869, - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d939, - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d948, - IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915, - IF_mmioPlatform_reqSz_75_EQ_0b10_82_THEN_SEXT__ETC___d883, - IF_mmioPlatform_reqSz_75_EQ_0b10_82_THEN_SEXT__ETC___d885, - data64__h147793, - dword__h93798, - ld_data__h131955, - old_dword__h89488, - w1__h47877, - w1__h47882, - w2__h47878, - w2__h47884, - x__h47873; - reg [31 : 0] SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d983; + CASE_x1261_0_n__read_addr1443_1_n__read_addr15_ETC__q23, + CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24, + CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25, + CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26, + CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27, + CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28, + CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29, + CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30, + CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31, + CASE_x9884_0_n__read_addr0062_1_n__read_addr01_ETC__q34, + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801, + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814, + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853, + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865, + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935, + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d944, + IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911, + IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d879, + IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d881, + data64__h147777, + dword__h93782, + ld_data__h131939, + old_dword__h89472, + w1__h47861, + w1__h47866, + w2__h47862, + w2__h47868, + x__h47857; + reg [31 : 0] SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d979; reg [11 : 0] CASE_core_0v_to_TV_0_get_BITS_475_TO_464_1_co_ETC__q5, CASE_core_0v_to_TV_1_get_BITS_475_TO_464_1_co_ETC__q1; - reg [7 : 0] strb8__h147794; - reg [5 : 0] IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_ETC___d481; + reg [7 : 0] strb8__h147778; + reg [5 : 0] IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d477; reg [3 : 0] CASE_core_0v_to_TV_0_get_BITS_461_TO_458_0_co_ETC__q6, CASE_core_0v_to_TV_0_get_BITS_461_TO_458_0_co_ETC__q7, CASE_core_0v_to_TV_1_get_BITS_461_TO_458_0_co_ETC__q2, CASE_core_0v_to_TV_1_get_BITS_461_TO_458_0_co_ETC__q3; - reg [2 : 0] x__h61591; + reg [2 : 0] x__h61575; reg [1 : 0] CASE_core_0v_to_TV_0_get_BITS_393_TO_392_0_co_ETC__q8, CASE_core_0v_to_TV_1_get_BITS_393_TO_392_0_co_ETC__q4, - CASE_x1277_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21, - CASE_x1277_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22, - CASE_x9900_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32; + CASE_x1261_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21, + CASE_x1261_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22, + CASE_x9884_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32; reg CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q18, CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q19, - CASE_x1277_0_propDstData_0_dummy2_1_read__096__ETC__q20, - CASE_x9900_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33, - SEL_ARR_propDstIdx_0_dummy2_1_read__058_AND_IF_ETC___d1089, - SEL_ARR_propDstIdx_1_0_dummy2_1_read__317_AND__ETC___d1358, - x__h61598, - x__h82316; - wire [579 : 0] IF_enqDst_1_0_lat_1_whas__262_THEN_enqDst_1_0__ETC___d1309; - wire [515 : 0] SEL_ARR_IF_propDstData_1_0_dummy2_1_read__365__ETC___d1457; - wire [513 : 0] IF_enqDst_1_0_lat_1_whas__262_THEN_enqDst_1_0__ETC___d1308; - wire [511 : 0] IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1300, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__189_THE_ETC___d1450, - new_cline__h134656; - wire [383 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1582, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__189_THE_ETC___d1433; - wire [255 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1577, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__189_THE_ETC___d1416; - wire [127 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__189_THE_ETC___d1399; - wire [66 : 0] IF_core_0_mmioToPlatform_cRq_first__82_BITS_14_ETC___d405; - wire [65 : 0] DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_40_BIT_ETC___d684; - wire [64 : 0] IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_2_ETC___d723; - wire [63 : 0] IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1280, - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d825, - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d876, - IF_mmioPlatform_reqBE_43_BIT_4_44_THEN_SEXT_mm_ETC___d577, - IF_mmioPlatform_reqBE_43_BIT_4_44_THEN_SEXT_mm_ETC___d641, - IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d552, - IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d614, - IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d715, - IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_1_ETC___d578, - IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_1_ETC___d642, - IF_propDstData_1_0_lat_0_whas__189_THEN_propDs_ETC___d1194, - IF_propDstData_1_1_lat_0_whas__227_THEN_propDs_ETC___d1232, - data__h31966, - failed_testnum__h162439, - line_addr__h101862, - line_addr__h101948, - mask__h89485, - mem_req_rd_addr_araddr__h133954, - mem_req_wr_addr_awaddr__h147878, - mmioPlatform_fromHostQ_data_0__h42667, - mmioPlatform_mtime__h37280, - mmioPlatform_reqData__h48469, - n__read_addr__h61459, - n__read_addr__h61544, - n__read_addr__h80078, - n__read_addr__h80157, - n__read_snd_addr__h123389, - newData__h32047, - newData__h34977, - new_dword__h89489, - op_result__h48485, - op_result__h49015, + CASE_x1261_0_propDstData_0_dummy2_1_read__092__ETC__q20, + CASE_x9884_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33, + SEL_ARR_propDstIdx_0_dummy2_1_read__054_AND_IF_ETC___d1085, + SEL_ARR_propDstIdx_1_0_dummy2_1_read__313_AND__ETC___d1354, + x__h61582, + x__h82300; + wire [579 : 0] IF_enqDst_1_0_lat_1_whas__258_THEN_enqDst_1_0__ETC___d1305; + wire [515 : 0] SEL_ARR_IF_propDstData_1_0_dummy2_1_read__361__ETC___d1453; + wire [513 : 0] IF_enqDst_1_0_lat_1_whas__258_THEN_enqDst_1_0__ETC___d1304; + wire [511 : 0] IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1296, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1446, + new_cline__h134640; + wire [383 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1578, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1429; + wire [255 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1573, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1412; + wire [127 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1395; + wire [66 : 0] IF_core_0_mmioToPlatform_cRq_first__78_BITS_14_ETC___d401; + wire [65 : 0] DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_36_BIT_ETC___d680; + wire [64 : 0] IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_2_ETC___d719; + wire [63 : 0] IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1276, + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d821, + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d872, + IF_mmioPlatform_reqBE_39_BIT_4_40_THEN_SEXT_mm_ETC___d573, + IF_mmioPlatform_reqBE_39_BIT_4_40_THEN_SEXT_mm_ETC___d637, + IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d548, + IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d610, + IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d711, + IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_1_ETC___d574, + IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_1_ETC___d638, + IF_propDstData_1_0_lat_0_whas__185_THEN_propDs_ETC___d1190, + IF_propDstData_1_1_lat_0_whas__223_THEN_propDs_ETC___d1228, + data__h31950, + failed_testnum__h162423, + line_addr__h101846, + line_addr__h101932, + mask__h89469, + mem_req_rd_addr_araddr__h133938, + mem_req_wr_addr_awaddr__h147862, + mmioPlatform_fromHostQ_data_0__h42651, + mmioPlatform_mtime__h37264, + mmioPlatform_reqData__h48453, + n__read_addr__h61443, + n__read_addr__h61528, + n__read_addr__h80062, + n__read_addr__h80141, + n__read_snd_addr__h123373, + newData__h32031, + newData__h34961, + new_dword__h89473, + op_result__h48469, + op_result__h48999, + op_result__h49004, + op_result__h49009, + op_result__h49014, op_result__h49020, - op_result__h49025, - op_result__h49030, - op_result__h49036, - op_result__h49043, - op_result__h49049, - result__h47928, - result__h48052, - result__h48080, - result__h48108, - result__h48136, - result__h48164, - result__h48192, - result__h48220, - result__h48248, - result__h48293, - result__h48321, - result__h48349, - result__h48377, - result__h48418, - result__h48446, - result__h48572, - result__h48599, - result__h48626, - result__h48653, - result__h48680, - result__h48707, - result__h48734, - result__h48761, - result__h48805, - result__h48832, - result__h48859, - result__h48886, - result__h48926, - result__h48953, - result__h49070, - result__h49136, - result__h49202, - result__h49268, - result__h49334, - result__h49400, - result__h49466, - result__h49528, - result__h49573, - result__h49639, - result__h49705, - result__h49763, - result__h49808, - w1___1__h47987, - w2___1__h47988, - x1_avValue_data__h40339, - x1_avValue_data__h44806, - x__h32158, - x__h35068, - x__h37428, - x__h40857, - x__h40868, - x__h42877, - x__h42888, - x__h49985, - x__h90651, - y__h90652, - y__h90653; - wire [47 : 0] IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d544, - IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d609, - IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d710; - wire [31 : 0] IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d535, - IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d604, - IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d705, - IF_mmio_axi4_adapter_f_rsps_to_core_first__56__ETC___d991, + op_result__h49027, + op_result__h49033, + result__h47912, + result__h48036, + result__h48064, + result__h48092, + result__h48120, + result__h48148, + result__h48176, + result__h48204, + result__h48232, + result__h48277, + result__h48305, + result__h48333, + result__h48361, + result__h48402, + result__h48430, + result__h48556, + result__h48583, + result__h48610, + result__h48637, + result__h48664, + result__h48691, + result__h48718, + result__h48745, + result__h48789, + result__h48816, + result__h48843, + result__h48870, + result__h48910, + result__h48937, + result__h49054, + result__h49120, + result__h49186, + result__h49252, + result__h49318, + result__h49384, + result__h49450, + result__h49512, + result__h49557, + result__h49623, + result__h49689, + result__h49747, + result__h49792, + w1___1__h47971, + w2___1__h47972, + x1_avValue_data__h40323, + x1_avValue_data__h44790, + x__h32142, + x__h35052, + x__h37412, + x__h40841, + x__h40852, + x__h42861, + x__h42872, + x__h49969, + x__h90635, + y__h90636, + y__h90637; + wire [47 : 0] IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d540, + IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d605, + IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d706; + wire [31 : 0] IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d531, + IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d600, + IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d701, + IF_mmio_axi4_adapter_f_rsps_to_core_first__52__ETC___d987, mmioPlatform_mtime_BITS_31_TO_0__q12, mmioPlatform_mtime_BITS_63_TO_32__q11, mmioPlatform_mtimecmp_0_BITS_31_TO_0__q10, mmioPlatform_mtimecmp_0_BITS_63_TO_32__q9, - v__h31759, - v__h31796, - w17877_BITS_31_TO_0__q15, - w27878_BITS_31_TO_0__q16, - x_data__h30549; - wire [8 : 0] SEL_ARR_IF_propDstData_0_dummy2_1_read__096_TH_ETC___d1160; - wire [5 : 0] x__h133989, x__h147903; - wire [4 : 0] SEL_ARR_propDstData_0_dummy2_1_read__096_AND_I_ETC___d1159; - wire [3 : 0] b__h133661, b__h2564; - wire [2 : 0] n__read_id__h61463, n__read_id__h61548, x__h7925; - wire [1 : 0] IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1285, - IF_propDstData_0_dummy2_1_read__096_THEN_IF_pr_ETC___d1112, - IF_propDstData_0_dummy2_1_read__096_THEN_IF_pr_ETC___d1122, - IF_propDstData_1_0_lat_0_whas__189_THEN_propDs_ETC___d1199, - IF_propDstData_1_1_lat_0_whas__227_THEN_propDs_ETC___d1237, - IF_propDstData_1_dummy2_1_read__101_THEN_IF_pr_ETC___d1116, - IF_propDstData_1_dummy2_1_read__101_THEN_IF_pr_ETC___d1126; - wire IF_IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4__ETC___d559, - IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d456, - IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554, - IF_NOT_propDstIdx_0_dummy2_1_read__058_059_OR__ETC___d1093, - IF_NOT_propDstIdx_1_0_dummy2_1_read__317_318_O_ETC___d1362, - IF_SEL_ARR_propDstIdx_0_dummy2_1_read__058_AND_ETC___d1165, - IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__317_A_ETC___d1462, - IF_enqDst_0_lat_0_whas__034_THEN_enqDst_0_lat__ETC___d1039, - IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1270, - IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1290, - IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1306, - IF_llc_mem_server_enqDst_0_lat_0_whas__662_THE_ETC___d1667, - IF_llc_mem_server_propDstIdx_0_lat_0_whas__647_ETC___d1650, - IF_mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioP_ETC___d625, - IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_ETC___d457, + v__h31743, + v__h31780, + w17861_BITS_31_TO_0__q15, + w27862_BITS_31_TO_0__q16, + x_data__h30533; + wire [8 : 0] SEL_ARR_IF_propDstData_0_dummy2_1_read__092_TH_ETC___d1156; + wire [5 : 0] x__h133973, x__h147887; + wire [4 : 0] SEL_ARR_propDstData_0_dummy2_1_read__092_AND_I_ETC___d1155; + wire [3 : 0] b__h133645, b__h2564; + wire [2 : 0] n__read_id__h61447, n__read_id__h61532, x__h7925; + wire [1 : 0] IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1281, + IF_propDstData_0_dummy2_1_read__092_THEN_IF_pr_ETC___d1108, + IF_propDstData_0_dummy2_1_read__092_THEN_IF_pr_ETC___d1118, + IF_propDstData_1_0_lat_0_whas__185_THEN_propDs_ETC___d1195, + IF_propDstData_1_1_lat_0_whas__223_THEN_propDs_ETC___d1233, + IF_propDstData_1_dummy2_1_read__097_THEN_IF_pr_ETC___d1112, + IF_propDstData_1_dummy2_1_read__097_THEN_IF_pr_ETC___d1122; + wire IF_IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4__ETC___d555, + IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d452, + IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550, + IF_NOT_propDstIdx_0_dummy2_1_read__054_055_OR__ETC___d1089, + IF_NOT_propDstIdx_1_0_dummy2_1_read__313_314_O_ETC___d1358, + IF_SEL_ARR_propDstIdx_0_dummy2_1_read__054_AND_ETC___d1161, + IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__313_A_ETC___d1458, + IF_enqDst_0_lat_0_whas__030_THEN_enqDst_0_lat__ETC___d1035, + IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1266, + IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1286, + IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1302, + IF_llc_mem_server_enqDst_0_lat_0_whas__658_THE_ETC___d1663, + IF_llc_mem_server_propDstIdx_0_lat_0_whas__643_ETC___d1646, + IF_mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioP_ETC___d621, + IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d453, IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__91__ETC___d200, - IF_mmioPlatform_waitLowerMSIPCRs_92_THEN_core__ETC___d500, - IF_mmio_axi4_adapter_f_rsps_to_core_first__56__ETC___d970, + IF_mmioPlatform_waitLowerMSIPCRs_88_THEN_core__ETC___d496, + IF_mmio_axi4_adapter_f_rsps_to_core_first__52__ETC___d966, IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d103, - IF_propDstData_1_0_lat_0_whas__189_THEN_propDs_ETC___d1220, - IF_propDstData_1_1_lat_0_whas__227_THEN_propDs_ETC___d1258, - IF_propDstIdx_0_lat_0_whas__005_THEN_propDstId_ETC___d1008, - IF_propDstIdx_1_0_lat_0_whas__174_THEN_propDst_ETC___d1177, - IF_propDstIdx_1_1_lat_0_whas__181_THEN_propDst_ETC___d1184, - IF_propDstIdx_1_lat_0_whas__012_THEN_propDstId_ETC___d1015, - NOT_enqDst_0_dummy2_0_read__079_080_OR_NOT_enq_ETC___d1095, - NOT_enqDst_1_0_dummy2_0_read__348_349_OR_NOT_e_ETC___d1364, - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780, - NOT_llc_mem_server_enqDst_0_dummy2_0_read__693_ETC___d1700, - NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d746, - NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d754, - NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d759, - NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d769, - NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d960, - NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d973, + IF_propDstData_1_0_lat_0_whas__185_THEN_propDs_ETC___d1216, + IF_propDstData_1_1_lat_0_whas__223_THEN_propDs_ETC___d1254, + IF_propDstIdx_0_lat_0_whas__001_THEN_propDstId_ETC___d1004, + IF_propDstIdx_1_0_lat_0_whas__170_THEN_propDst_ETC___d1173, + IF_propDstIdx_1_1_lat_0_whas__177_THEN_propDst_ETC___d1180, + IF_propDstIdx_1_lat_0_whas__008_THEN_propDstId_ETC___d1011, + NOT_enqDst_0_dummy2_0_read__075_076_OR_NOT_enq_ETC___d1091, + NOT_enqDst_1_0_dummy2_0_read__344_345_OR_NOT_e_ETC___d1360, + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776, + NOT_llc_mem_server_enqDst_0_dummy2_0_read__689_ETC___d1696, + NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d742, + NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d750, + NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d755, + NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d765, + NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d956, + NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d969, NOT_mmioPlatform_fromHostQ_clearReq_dummy2_1_r_ETC___d318, NOT_mmioPlatform_fromHostQ_enqReq_dummy2_2_rea_ETC___d339, - NOT_mmioPlatform_mtip_0_55_64_AND_mmioPlatform_ETC___d374, - NOT_mmioPlatform_mtip_0_55_64_AND_mmioPlatform_ETC___d379, - NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d490, - NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d585, - NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d648, + NOT_mmioPlatform_mtip_0_55_62_AND_mmioPlatform_ETC___d370, + NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d486, + NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d581, + NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d644, NOT_mmioPlatform_toHostQ_clearReq_dummy2_1_rea_ETC___d240, NOT_mmioPlatform_toHostQ_enqReq_dummy2_2_read__ETC___d261, - NOT_propDstData_1_0_dummy2_1_read__365_376_OR__ETC___d1377, - NOT_propDstData_1_1_dummy2_1_read__367_378_OR__ETC___d1379, - NOT_propDstIdx_0_dummy2_1_read__058_059_OR_IF__ETC___d1092, - NOT_propDstIdx_1_0_dummy2_1_read__317_318_OR_I_ETC___d1361, - llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1594, - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1516, + NOT_propDstData_1_0_dummy2_1_read__361_372_OR__ETC___d1373, + NOT_propDstData_1_1_dummy2_1_read__363_374_OR__ETC___d1375, + NOT_propDstIdx_0_dummy2_1_read__054_055_OR_IF__ETC___d1088, + NOT_propDstIdx_1_0_dummy2_1_read__313_314_OR_I_ETC___d1357, + llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1590, + llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1512, mmioPlatform_cycle_47_ULT_99___d348, - mmioPlatform_fetchingWay_65_ULT_mmioPlatform_r_ETC___d975, + mmioPlatform_fetchingWay_61_ULT_mmioPlatform_r_ETC___d971, mmioPlatform_fromHostQ_enqReq_dummy2_2_read__1_ETC___d331, - mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616, + mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612, mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357, - mmioPlatform_mtip_0_55_OR_NOT_mmioPlatform_mti_ETC___d410, - mmioPlatform_reqBE_BIT_0___h30174, - mmioPlatform_reqBE_BIT_4___h30134, - mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d467, - mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d571, - mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d636, + mmioPlatform_reqBE_BIT_0___h30158, + mmioPlatform_reqBE_BIT_4___h30118, + mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d463, + mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d567, + mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d632, mmioPlatform_toHostQ_enqReq_dummy2_2_read__41__ETC___d253, mmio_axi4_adapter_f_reqs_from_core_i_notEmpty__ETC___d9, - n__read_child__h61464, - n__read_child__h61549, - n__read_child__h80081, - n__read_child__h80160, - n__read_snd_id__h123390, - propDstData_0_dummy2_1_read__096_AND_IF_propDs_ETC___d1132, - propDstData_1_dummy2_1_read__101_AND_IF_propDs_ETC___d1136, - x__h61277, - x__h74829, - x__h79900; + n__read_child__h61448, + n__read_child__h61533, + n__read_child__h80065, + n__read_child__h80144, + n__read_snd_id__h123374, + propDstData_0_dummy2_1_read__092_AND_IF_propDs_ETC___d1128, + propDstData_1_dummy2_1_read__097_AND_IF_propDs_ETC___d1132, + x__h61261, + x__h74813, + x__h79884; // action method start assign RDY_start = mmioPlatform_state == 2'd0 ; @@ -3536,7 +3534,7 @@ module mkProc(CLK, // rule RL_doEnq assign CAN_FIRE_RL_doEnq = llc$RDY_to_child_rqFromC_enq && enqDst_0_dummy2_1$Q_OUT && - IF_enqDst_0_lat_0_whas__034_THEN_enqDst_0_lat__ETC___d1039 ; + IF_enqDst_0_lat_0_whas__030_THEN_enqDst_0_lat__ETC___d1035 ; assign WILL_FIRE_RL_doEnq = CAN_FIRE_RL_doEnq ; // rule RL_srcPropose_2 @@ -3564,7 +3562,7 @@ module mkProc(CLK, // rule RL_doEnq_1 assign CAN_FIRE_RL_doEnq_1 = llc$RDY_to_child_rsFromC_enq && enqDst_1_0_dummy2_1$Q_OUT && - IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1270 ; + IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1266 ; assign WILL_FIRE_RL_doEnq_1 = CAN_FIRE_RL_doEnq_1 ; // rule RL_sendPRq @@ -3725,9 +3723,8 @@ module mkProc(CLK, assign CAN_FIRE_RL_mmioPlatform_selectReq = (mmioPlatform_mtip_0 || !mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 || - mmioPlatform_mtimecmp_0 == 64'd0 || core_0$RDY_mmioToPlatform_pRq_enq) && - NOT_mmioPlatform_mtip_0_55_64_AND_mmioPlatform_ETC___d374 && + NOT_mmioPlatform_mtip_0_55_62_AND_mmioPlatform_ETC___d370 && mmioPlatform_state == 2'd1 ; assign WILL_FIRE_RL_mmioPlatform_selectReq = CAN_FIRE_RL_mmioPlatform_selectReq && @@ -3744,7 +3741,7 @@ module mkProc(CLK, // rule RL_mmioPlatform_processMSIP assign CAN_FIRE_RL_mmioPlatform_processMSIP = - IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_ETC___d457 && + IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d453 && mmioPlatform_curReq[66:64] == 3'd2 && mmioPlatform_state == 2'd2 ; assign WILL_FIRE_RL_mmioPlatform_processMSIP = @@ -3753,7 +3750,7 @@ module mkProc(CLK, // rule RL_mmioPlatform_waitMSIPDone assign CAN_FIRE_RL_mmioPlatform_waitMSIPDone = core_0$RDY_mmioToPlatform_pRs_enq && - IF_mmioPlatform_waitLowerMSIPCRs_92_THEN_core__ETC___d500 && + IF_mmioPlatform_waitLowerMSIPCRs_88_THEN_core__ETC___d496 && mmioPlatform_curReq[66:64] == 3'd2 && mmioPlatform_state == 2'd3 ; assign WILL_FIRE_RL_mmioPlatform_waitMSIPDone = @@ -3799,7 +3796,7 @@ module mkProc(CLK, core_0$RDY_mmioToPlatform_pRs_enq && (mmioPlatform_reqFunc[5:4] != 2'd2 || !mmioPlatform_toHostQ_empty || - x__h42877 == 64'd0 || + x__h42861 == 64'd0 || !mmioPlatform_toHostQ_full) && mmioPlatform_state == 2'd2 && mmioPlatform_curReq[66:64] == 3'd5 ; @@ -3817,7 +3814,7 @@ module mkProc(CLK, // rule RL_mmioPlatform_rl_mmio_to_fabric_req assign CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req = mmio_axi4_adapter_f_reqs_from_core$FULL_N && - NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d746 ; + NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d742 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req = CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req ; @@ -3825,14 +3822,14 @@ module mkProc(CLK, assign CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp = core_0$RDY_mmioToPlatform_pRs_enq && mmio_axi4_adapter_f_rsps_to_core$EMPTY_N && - NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d754 ; + NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d750 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp = CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp ; // rule RL_mmioPlatform_rl_mmio_to_fabric_amo_req assign CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req = mmio_axi4_adapter_f_reqs_from_core$FULL_N && - NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d759 ; + NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d755 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req = CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req ; @@ -3842,22 +3839,22 @@ module mkProc(CLK, mmio_axi4_adapter_f_rsps_to_core$EMPTY_N && (!mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] || mmio_axi4_adapter_f_reqs_from_core$FULL_N) && - NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d769 ; + NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d765 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp = CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp ; // rule RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req assign CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req = mmio_axi4_adapter_f_reqs_from_core$FULL_N && - NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d960 ; + NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d956 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req = CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req ; // rule RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp assign CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp = mmio_axi4_adapter_f_rsps_to_core$EMPTY_N && - IF_mmio_axi4_adapter_f_rsps_to_core_first__56__ETC___d970 && - NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d973 ; + IF_mmio_axi4_adapter_f_rsps_to_core_first__52__ETC___d966 && + NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d969 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp = CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp ; @@ -3939,7 +3936,7 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_f_rd_data$FULL_N && (llc_mem_server_rg_cacheline_cache_state == 3'd3 || llc_mem_server_rg_cacheline_cache_state == 3'd4) && - llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1594 ; + llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1590 ; assign WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req = CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req ; @@ -3957,7 +3954,7 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_f_wr_resp$FULL_N && (llc_mem_server_rg_cacheline_cache_state == 3'd3 || llc_mem_server_rg_cacheline_cache_state == 3'd4) && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1516 ; + llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1512 ; assign WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req = CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ; @@ -3975,7 +3972,7 @@ module mkProc(CLK, llc$RDY_dma_memReq_enq && llc_mem_server_axi4_slave_xactor_f_wr_addr$EMPTY_N && llc_mem_server_rg_cacheline_cache_state == 3'd4 && - !llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1516 ; + !llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1512 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss && !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged ; @@ -3985,7 +3982,7 @@ module mkProc(CLK, llc$RDY_dma_memReq_enq && llc_mem_server_axi4_slave_xactor_f_rd_addr$EMPTY_N && llc_mem_server_rg_cacheline_cache_state == 3'd4 && - !llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1594 ; + !llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1590 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss && !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss && @@ -4005,7 +4002,7 @@ module mkProc(CLK, llc$RDY_dma_memReq_enq && llc_mem_server_axi4_slave_xactor_f_wr_addr$EMPTY_N && llc_mem_server_rg_cacheline_cache_state == 3'd3 && - !llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1516 ; + !llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1512 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ; @@ -4014,7 +4011,7 @@ module mkProc(CLK, llc$RDY_dma_memReq_enq && llc_mem_server_axi4_slave_xactor_f_rd_addr$EMPTY_N && llc_mem_server_rg_cacheline_cache_state == 3'd3 && - !llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1594 ; + !llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1590 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld && !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st && @@ -4046,7 +4043,7 @@ module mkProc(CLK, assign CAN_FIRE_RL_llc_mem_server_doEnq = llc_mem_server_tlbQ$FULL_N && llc_mem_server_enqDst_0_dummy2_1$Q_OUT && - IF_llc_mem_server_enqDst_0_lat_0_whas__662_THE_ETC___d1667 ; + IF_llc_mem_server_enqDst_0_lat_0_whas__658_THE_ETC___d1663 ; assign WILL_FIRE_RL_llc_mem_server_doEnq = CAN_FIRE_RL_llc_mem_server_doEnq ; @@ -4119,13 +4116,13 @@ module mkProc(CLK, (llc_axi4_adapter_rg_rd_req_beat != 3'd7 || llc$RDY_to_mem_toM_deq) && !llc$to_mem_toM_first[640] && - b__h133661 == 4'd0 ; + b__h133645 == 4'd0 ; assign WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ; // rule RL_llc_axi4_adapter_rl_discard_write_rsp assign CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp = - b__h133661 != 4'd0 && + b__h133645 != 4'd0 && llc_axi4_adapter_master_xactor_crg_wr_resp_full && (llc_axi4_adapter_rg_wr_rsp_beat != 3'd7 || llc_axi4_adapter_f_pending_writes$EMPTY_N) ; @@ -4135,8 +4132,7 @@ module mkProc(CLK, // inputs to muxes for submodule ports assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 && - mmioPlatform_mtimecmp_0 != 64'd0 ; + mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_2 = WILL_FIRE_RL_mmioPlatform_processMSIP && mmioPlatform_reqFunc[5:4] != 2'd0 && @@ -4144,22 +4140,22 @@ module mkProc(CLK, mmioPlatform_reqBE[0] ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_3 = WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d585 ; + NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d581 ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_4 = WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d648 ; + NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d644 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_processMSIP && - mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d467 ; + mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d463 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_2 = WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d571 ; + mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d567 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_3 = WILL_FIRE_RL_mmioPlatform_processMTime && - mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d636 ; + mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d632 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_4 = WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && - (!mmioPlatform_fetchingWay_65_ULT_mmioPlatform_r_ETC___d975 || + (!mmioPlatform_fetchingWay_61_ULT_mmioPlatform_r_ETC___d971 || !mmio_axi4_adapter_f_rsps_to_core$D_OUT[64]) ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_5 = WILL_FIRE_RL_mmioPlatform_waitMTimeDone || @@ -4184,10 +4180,14 @@ module mkProc(CLK, mmioPlatform_reqFunc[5:4] != 2'd1 ; assign MUX_mmioPlatform_curReq$write_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_selectReq && - NOT_mmioPlatform_mtip_0_55_64_AND_mmioPlatform_ETC___d379 ; + (!mmioPlatform_mtip_0 && + mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 || + core_0$mmioToPlatform_cRq_notEmpty) ; assign MUX_mmioPlatform_fetchingWay$write_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_55_OR_NOT_mmioPlatform_mti_ETC___d410 ; + (mmioPlatform_mtip_0 || + !mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357) && + core_0$mmioToPlatform_cRq_notEmpty ; assign MUX_mmioPlatform_state$write_1__SEL_6 = WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp || @@ -4222,20 +4222,20 @@ module mkProc(CLK, llc$to_child_toC_first[515:0] } ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_2 = { 1'd0, - IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_ETC___d481, + IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d477, (mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? mmioPlatform_reqData[31:0] : - x_data__h30549 } ; + x_data__h30533 } ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_3 = { 7'd106, - (IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 && + (IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && !mmioPlatform_mtip_0) ? 32'd1 : 32'd0 } ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_4 = { 7'd106, - (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && + (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && !mmioPlatform_mtip_0) ? 32'd1 : 32'd0 } ; @@ -4249,35 +4249,35 @@ module mkProc(CLK, (mmioPlatform_reqFunc[5:4] == 2'd0) ? 66'h155555554AAAAAAAA : { 2'h1, - IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_1_ETC___d578 } } ; + IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_1_ETC___d574 } } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_3 = { mmioPlatform_reqFunc[5:4] != 2'd0, (mmioPlatform_reqFunc[5:4] == 2'd0) ? 66'h155555554AAAAAAAA : { 2'h1, - IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_1_ETC___d642 } } ; + IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_1_ETC___d638 } } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_4 = { 1'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] && mmioPlatform_fetchingWay, - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d983, + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d979, mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] || mmioPlatform_fetchingWay, - IF_mmio_axi4_adapter_f_rsps_to_core_first__56__ETC___d991 } ; + IF_mmio_axi4_adapter_f_rsps_to_core_first__52__ETC___d987 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_5 = { 3'd5, mmioPlatform_amoResp } ; - assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6 = { 3'd5, data__h31966 } ; + assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6 = { 3'd5, data__h31950 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_7 = { mmioPlatform_reqFunc[5:4] != 2'd0, (mmioPlatform_reqFunc[5:4] == 2'd0) ? 66'h155555554AAAAAAAA : - DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_40_BIT_ETC___d684 } ; + DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_36_BIT_ETC___d680 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_8 = { mmioPlatform_reqFunc[5:4] != 2'd0, (mmioPlatform_reqFunc[5:4] == 2'd0) ? 66'h155555554AAAAAAAA : { 1'h0, - IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_2_ETC___d723 } } ; + IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_2_ETC___d719 } } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_9 = { 2'd2, mmio_axi4_adapter_f_rsps_to_core$D_OUT } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_10 = @@ -4291,10 +4291,10 @@ module mkProc(CLK, llc_mem_server_rg_cacheline_cache_data, 5'd10 } ; assign MUX_llc$dma_memReq_enq_1__VAL_2 = - { line_addr__h101862, + { line_addr__h101846, 581'h0000000000000000155555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555554A } ; assign MUX_llc$dma_memReq_enq_1__VAL_3 = - { line_addr__h101948, + { line_addr__h101932, 581'h0000000000000000155555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555554A } ; assign MUX_llc$dma_memReq_enq_1__VAL_4 = { llc_mem_server_tlbQ$D_OUT[64:1], @@ -4302,29 +4302,28 @@ module mkProc(CLK, llc_mem_server_tlbQ$D_OUT[0], llc_mem_server_tlbQ$D_OUT[6:4] } ; assign MUX_llc_mem_server_rg_cacheline_cache_data$write_1__VAL_1 = - { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1582, + { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1578, (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd1) ? - new_dword__h89489 : + new_dword__h89473 : llc_mem_server_rg_cacheline_cache_data[127:64], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd0) ? - new_dword__h89489 : + new_dword__h89473 : llc_mem_server_rg_cacheline_cache_data[63:0] } ; assign MUX_llc_mem_server_rg_cacheline_cache_dirty_delay$write_1__VAL_2 = llc_mem_server_rg_cacheline_cache_dirty_delay - 10'd1 ; assign MUX_mmioPlatform_amoResp$write_1__VAL_1 = (mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtimecmp_0 : - IF_mmioPlatform_reqBE_43_BIT_4_44_THEN_SEXT_mm_ETC___d577 ; + IF_mmioPlatform_reqBE_39_BIT_4_40_THEN_SEXT_mm_ETC___d573 ; assign MUX_mmioPlatform_amoResp$write_1__VAL_2 = (mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtime : - IF_mmioPlatform_reqBE_43_BIT_4_44_THEN_SEXT_mm_ETC___d641 ; + IF_mmioPlatform_reqBE_39_BIT_4_40_THEN_SEXT_mm_ETC___d637 ; assign MUX_mmioPlatform_curReq$write_1__VAL_1 = (!mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 && - mmioPlatform_mtimecmp_0 != 64'd0) ? + mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357) ? 67'h1AAAAAAAAAAAAAAAA : ((core_0$mmioToPlatform_cRq_first[141:81] >= 61'd33554432 && core_0$mmioToPlatform_cRq_first[141:81] < 61'd33554433) ? @@ -4335,7 +4334,7 @@ module mkProc(CLK, ((core_0$mmioToPlatform_cRq_first[141:81] == 61'd33560575) ? 67'h4AAAAAAAAAAAAAAAA : - IF_core_0_mmioToPlatform_cRq_first__82_BITS_14_ETC___d405))) ; + IF_core_0_mmioToPlatform_cRq_first__78_BITS_14_ETC___d401))) ; assign MUX_mmioPlatform_curReq$write_1__VAL_2 = { 3'd7, mmioPlatform_instSel ? @@ -4348,12 +4347,11 @@ module mkProc(CLK, mmioPlatform_instSel + 1'd1 ; assign MUX_mmioPlatform_mtime$write_1__VAL_2 = mmioPlatform_mtime + 64'd1 ; assign MUX_mmioPlatform_mtip_0$write_1__VAL_2 = - IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 && + IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && !mmioPlatform_mtip_0 ; assign MUX_mmioPlatform_state$write_1__VAL_1 = (!mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 && - mmioPlatform_mtimecmp_0 != 64'd0) ? + mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357) ? 2'd3 : 2'd2 ; assign MUX_mmioPlatform_state$write_1__VAL_2 = @@ -4364,32 +4362,32 @@ module mkProc(CLK, (mmioPlatform_reqBE[0] ? 2'd3 : 2'd1) : 2'd3) ; always@(mmioPlatform_reqFunc or - IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 or + IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 or mmioPlatform_mtip_0) begin case (mmioPlatform_reqFunc[5:4]) 2'd0: MUX_mmioPlatform_state$write_1__VAL_3 = 2'd1; 2'd1: MUX_mmioPlatform_state$write_1__VAL_3 = mmioPlatform_reqFunc[5:4]; default: MUX_mmioPlatform_state$write_1__VAL_3 = - (IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 && + (IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && !mmioPlatform_mtip_0 || - !IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 && + !IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && mmioPlatform_mtip_0) ? 2'd3 : 2'd1; endcase end always@(mmioPlatform_reqFunc or - mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 or + mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 or mmioPlatform_mtip_0) begin case (mmioPlatform_reqFunc[5:4]) 2'd0: MUX_mmioPlatform_state$write_1__VAL_4 = 2'd1; 2'd1: MUX_mmioPlatform_state$write_1__VAL_4 = mmioPlatform_reqFunc[5:4]; default: MUX_mmioPlatform_state$write_1__VAL_4 = - (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && + (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && + !mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && mmioPlatform_mtip_0) ? 2'd3 : 2'd1; @@ -4397,29 +4395,29 @@ module mkProc(CLK, end assign MUX_mmioPlatform_state$write_1__VAL_5 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] ? - (mmioPlatform_fetchingWay_65_ULT_mmioPlatform_r_ETC___d975 ? + (mmioPlatform_fetchingWay_61_ULT_mmioPlatform_r_ETC___d971 ? 2'd2 : 2'd1) : 2'd1 ; assign MUX_mmioPlatform_waitMTIPCRs$write_1__VAL_2 = - mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && + mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && + !mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && mmioPlatform_mtip_0 ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_1 = { mmioPlatform_curReq[63:0], 6'd42, mmioPlatform_reqBE, - x__h47873 } ; + x__h47857 } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_2 = { mmioPlatform_curReq[63:0], - IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_ETC___d481, + IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d477, mmioPlatform_reqBE, mmioPlatform_reqData } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_3 = { mmioPlatform_curReq[63:0], 78'h1AAAAAAAAAAAAAAAAAAA } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_4 = - { x__h49985, 78'h1AAAAAAAAAAAAAAAAAAA } ; + { x__h49969, 78'h1AAAAAAAAAAAAAAAAAAA } ; assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_1 = { 1'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[141:78] } ; assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_3 = @@ -4427,47 +4425,47 @@ module mkProc(CLK, mmio_axi4_adapter_master_xactor_rg_rd_data[66:3] } ; // inlined wires - assign mmioPlatform_toHostQ_enqReq_lat_0$wget = { 1'd1, x__h42877 } ; + assign mmioPlatform_toHostQ_enqReq_lat_0$wget = { 1'd1, x__h42861 } ; assign mmioPlatform_toHostQ_enqReq_lat_0$whas = WILL_FIRE_RL_mmioPlatform_processToHost && mmioPlatform_reqFunc[5:4] == 2'd2 && mmioPlatform_toHostQ_empty && - x__h42877 != 64'd0 ; + x__h42861 != 64'd0 ; assign mmioPlatform_fromHostQ_deqReq_lat_0$whas = WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && !mmioPlatform_fromHostQ_empty && - x__h40857 == 64'd0 ; + x__h40841 == 64'd0 ; assign propDstIdx_0_lat_1$whas = - NOT_enqDst_0_dummy2_0_read__079_080_OR_NOT_enq_ETC___d1095 && - IF_SEL_ARR_propDstIdx_0_dummy2_1_read__058_AND_ETC___d1165 ; + NOT_enqDst_0_dummy2_0_read__075_076_OR_NOT_enq_ETC___d1091 && + IF_SEL_ARR_propDstIdx_0_dummy2_1_read__054_AND_ETC___d1161 ; assign propDstIdx_1_lat_1$whas = - NOT_enqDst_0_dummy2_0_read__079_080_OR_NOT_enq_ETC___d1095 && - x__h61277 ; + NOT_enqDst_0_dummy2_0_read__075_076_OR_NOT_enq_ETC___d1091 && + x__h61261 ; assign propDstData_0_lat_0$wget = { core_0$dCacheToParent_rqToP_first, 1'd0 } ; assign propDstData_1_lat_0$wget = { core_0$iCacheToParent_rqToP_first, 1'd1 } ; assign enqDst_0_lat_0$wget = { 1'd1, - CASE_x1277_0_n__read_addr1459_1_n__read_addr15_ETC__q23, - SEL_ARR_IF_propDstData_0_dummy2_1_read__096_TH_ETC___d1160 } ; + CASE_x1261_0_n__read_addr1443_1_n__read_addr15_ETC__q23, + SEL_ARR_IF_propDstData_0_dummy2_1_read__092_TH_ETC___d1156 } ; assign propDstIdx_1_0_lat_1$whas = - NOT_enqDst_1_0_dummy2_0_read__348_349_OR_NOT_e_ETC___d1364 && - IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__317_A_ETC___d1462 ; + NOT_enqDst_1_0_dummy2_0_read__344_345_OR_NOT_e_ETC___d1360 && + IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__313_A_ETC___d1458 ; assign propDstIdx_1_1_lat_1$whas = - NOT_enqDst_1_0_dummy2_0_read__348_349_OR_NOT_e_ETC___d1364 && - x__h79900 ; + NOT_enqDst_1_0_dummy2_0_read__344_345_OR_NOT_e_ETC___d1360 && + x__h79884 ; assign propDstData_1_0_lat_0$wget = { core_0$dCacheToParent_rsToP_first, 1'd0 } ; assign propDstData_1_1_lat_0$wget = { core_0$iCacheToParent_rsToP_first, 1'd1 } ; assign enqDst_1_0_lat_0$wget = { 1'd1, - CASE_x9900_0_n__read_addr0078_1_n__read_addr01_ETC__q34, - SEL_ARR_IF_propDstData_1_0_dummy2_1_read__365__ETC___d1457 } ; + CASE_x9884_0_n__read_addr0062_1_n__read_addr01_ETC__q34, + SEL_ARR_IF_propDstData_1_0_dummy2_1_read__361__ETC___d1453 } ; assign llc_mem_server_enqDst_0_lat_0$wget = - { 1'd1, n__read_snd_addr__h123389, n__read_snd_id__h123390 } ; + { 1'd1, n__read_snd_addr__h123373, n__read_snd_id__h123374 } ; assign mmio_axi4_adapter_master_xactor_crg_wr_addr_full$EN_port1__write = mmio_axi4_adapter_master_xactor_crg_wr_addr_full && master1_awready ; @@ -4581,11 +4579,11 @@ module mkProc(CLK, assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 = llc_axi4_adapter_ctr_wr_rsps_pending_crg + 4'd1 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 = - b__h133661 - 4'd1 ; + b__h133645 - 4'd1 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read = CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp ? llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 : - b__h133661 ; + b__h133645 ; // register cfg_verbosity assign cfg_verbosity$D_IN = @@ -4597,10 +4595,10 @@ module mkProc(CLK, // register enqDst_0_rl assign enqDst_0_rl$D_IN = { !CAN_FIRE_RL_doEnq && - IF_enqDst_0_lat_0_whas__034_THEN_enqDst_0_lat__ETC___d1039, + IF_enqDst_0_lat_0_whas__030_THEN_enqDst_0_lat__ETC___d1035, CAN_FIRE_RL_doEnq ? 73'h0AAAAAAAAAAAAAAAAAA : - (NOT_enqDst_0_dummy2_0_read__079_080_OR_NOT_enq_ETC___d1095 ? + (NOT_enqDst_0_dummy2_0_read__075_076_OR_NOT_enq_ETC___d1091 ? enqDst_0_lat_0$wget[72:0] : enqDst_0_rl[72:0]) } ; assign enqDst_0_rl$EN = 1'd1 ; @@ -4608,8 +4606,8 @@ module mkProc(CLK, // register enqDst_1_0_rl assign enqDst_1_0_rl$D_IN = { !CAN_FIRE_RL_doEnq_1 && - IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1270, - IF_enqDst_1_0_lat_1_whas__262_THEN_enqDst_1_0__ETC___d1309 } ; + IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1266, + IF_enqDst_1_0_lat_1_whas__258_THEN_enqDst_1_0__ETC___d1305 } ; assign enqDst_1_0_rl$EN = 1'd1 ; // register llc_axi4_adapter_cfg_verbosity @@ -4648,7 +4646,7 @@ module mkProc(CLK, // register llc_axi4_adapter_master_xactor_rg_rd_addr assign llc_axi4_adapter_master_xactor_rg_rd_addr$D_IN = - { 4'd0, mem_req_rd_addr_araddr__h133954, 29'd851968 } ; + { 4'd0, mem_req_rd_addr_araddr__h133938, 29'd851968 } ; assign llc_axi4_adapter_master_xactor_rg_rd_addr$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ; @@ -4659,13 +4657,13 @@ module mkProc(CLK, // register llc_axi4_adapter_master_xactor_rg_wr_addr assign llc_axi4_adapter_master_xactor_rg_wr_addr$D_IN = - { 4'd0, mem_req_wr_addr_awaddr__h147878, 29'd851968 } ; + { 4'd0, mem_req_wr_addr_awaddr__h147862, 29'd851968 } ; assign llc_axi4_adapter_master_xactor_rg_wr_addr$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ; // register llc_axi4_adapter_master_xactor_rg_wr_data assign llc_axi4_adapter_master_xactor_rg_wr_data$D_IN = - { data64__h147793, strb8__h147794, 1'd1 } ; + { data64__h147777, strb8__h147778, 1'd1 } ; assign llc_axi4_adapter_master_xactor_rg_wr_data$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ; @@ -4677,7 +4675,7 @@ module mkProc(CLK, !llc_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read ; // register llc_axi4_adapter_rg_cline - assign llc_axi4_adapter_rg_cline$D_IN = new_cline__h134656 ; + assign llc_axi4_adapter_rg_cline$D_IN = new_cline__h134640 ; assign llc_axi4_adapter_rg_cline$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps ; @@ -4708,10 +4706,10 @@ module mkProc(CLK, // register llc_mem_server_enqDst_0_rl assign llc_mem_server_enqDst_0_rl$D_IN = { !CAN_FIRE_RL_llc_mem_server_doEnq && - IF_llc_mem_server_enqDst_0_lat_0_whas__662_THE_ETC___d1667, + IF_llc_mem_server_enqDst_0_lat_0_whas__658_THE_ETC___d1663, CAN_FIRE_RL_llc_mem_server_doEnq ? 65'h0AAAAAAAAAAAAAAAA : - (NOT_llc_mem_server_enqDst_0_dummy2_0_read__693_ETC___d1700 ? + (NOT_llc_mem_server_enqDst_0_dummy2_0_read__689_ETC___d1696 ? llc_mem_server_enqDst_0_lat_0$wget[64:0] : llc_mem_server_enqDst_0_rl[64:0]) } ; assign llc_mem_server_enqDst_0_rl$EN = 1'd1 ; @@ -4725,15 +4723,15 @@ module mkProc(CLK, // register llc_mem_server_propDstIdx_0_rl assign llc_mem_server_propDstIdx_0_rl$D_IN = - !NOT_llc_mem_server_enqDst_0_dummy2_0_read__693_ETC___d1700 && - IF_llc_mem_server_propDstIdx_0_lat_0_whas__647_ETC___d1650 ; + !NOT_llc_mem_server_enqDst_0_dummy2_0_read__689_ETC___d1696 && + IF_llc_mem_server_propDstIdx_0_lat_0_whas__643_ETC___d1646 ; assign llc_mem_server_propDstIdx_0_rl$EN = 1'd1 ; // register llc_mem_server_rg_cacheline_cache_addr assign llc_mem_server_rg_cacheline_cache_addr$D_IN = WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ? - line_addr__h101862 : - line_addr__h101948 ; + line_addr__h101846 : + line_addr__h101932 ; assign llc_mem_server_rg_cacheline_cache_addr$EN = WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st || WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld ; @@ -4804,11 +4802,10 @@ module mkProc(CLK, MUX_mmioPlatform_curReq$write_1__VAL_1 : MUX_mmioPlatform_curReq$write_1__VAL_2 ; assign mmioPlatform_curReq$EN = - WILL_FIRE_RL_mmioPlatform_selectReq && - NOT_mmioPlatform_mtip_0_55_64_AND_mmioPlatform_ETC___d379 || + MUX_mmioPlatform_curReq$write_1__SEL_1 || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] && - mmioPlatform_fetchingWay_65_ULT_mmioPlatform_r_ETC___d975 ; + mmioPlatform_fetchingWay_61_ULT_mmioPlatform_r_ETC___d971 ; // register mmioPlatform_cycle assign mmioPlatform_cycle$D_IN = @@ -4821,11 +4818,11 @@ module mkProc(CLK, // register mmioPlatform_fetchedInsts_0 assign mmioPlatform_fetchedInsts_0$D_IN = - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d983 ; + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d979 ; assign mmioPlatform_fetchedInsts_0$EN = WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] && - mmioPlatform_fetchingWay_65_ULT_mmioPlatform_r_ETC___d975 && + mmioPlatform_fetchingWay_61_ULT_mmioPlatform_r_ETC___d971 && !mmioPlatform_fetchingWay ; // register mmioPlatform_fetchingWay @@ -4834,10 +4831,12 @@ module mkProc(CLK, MUX_mmioPlatform_fetchingWay$write_1__VAL_2 ; assign mmioPlatform_fetchingWay$EN = WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_55_OR_NOT_mmioPlatform_mti_ETC___d410 || + (mmioPlatform_mtip_0 || + !mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357) && + core_0$mmioToPlatform_cRq_notEmpty || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] && - mmioPlatform_fetchingWay_65_ULT_mmioPlatform_r_ETC___d975 ; + mmioPlatform_fetchingWay_61_ULT_mmioPlatform_r_ETC___d971 ; // register mmioPlatform_fromHostAddr assign mmioPlatform_fromHostAddr$D_IN = start_fromhostAddr[63:3] ; @@ -4883,15 +4882,17 @@ module mkProc(CLK, MUX_mmioPlatform_instSel$write_1__VAL_2 ; assign mmioPlatform_instSel$EN = WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_55_OR_NOT_mmioPlatform_mti_ETC___d410 || + (mmioPlatform_mtip_0 || + !mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357) && + core_0$mmioToPlatform_cRq_notEmpty || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] && - mmioPlatform_fetchingWay_65_ULT_mmioPlatform_r_ETC___d975 ; + mmioPlatform_fetchingWay_61_ULT_mmioPlatform_r_ETC___d971 ; // register mmioPlatform_mtime assign mmioPlatform_mtime$D_IN = MUX_mmioPlatform_amoResp$write_1__SEL_2 ? - newData__h34977 : + newData__h34961 : MUX_mmioPlatform_mtime$write_1__VAL_2 ; assign mmioPlatform_mtime$EN = WILL_FIRE_RL_mmioPlatform_processMTime && @@ -4900,7 +4901,7 @@ module mkProc(CLK, WILL_FIRE_RL_mmioPlatform_incTime ; // register mmioPlatform_mtimecmp_0 - assign mmioPlatform_mtimecmp_0$D_IN = newData__h32047 ; + assign mmioPlatform_mtimecmp_0$D_IN = newData__h32031 ; assign mmioPlatform_mtimecmp_0$EN = MUX_mmioPlatform_amoResp$write_1__SEL_1 ; @@ -4910,10 +4911,9 @@ module mkProc(CLK, MUX_mmioPlatform_mtip_0$write_1__VAL_2 ; assign mmioPlatform_mtip_0$EN = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 && - mmioPlatform_mtimecmp_0 != 64'd0 || + mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 || WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d585 ; + NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d581 ; // register mmioPlatform_reqAmofunc assign mmioPlatform_reqAmofunc$D_IN = @@ -4983,8 +4983,7 @@ module mkProc(CLK, endcase end assign mmioPlatform_state$EN = - WILL_FIRE_RL_mmioPlatform_selectReq && - NOT_mmioPlatform_mtip_0_55_64_AND_mmioPlatform_ETC___d379 || + MUX_mmioPlatform_curReq$write_1__SEL_1 || WILL_FIRE_RL_mmioPlatform_processMSIP || WILL_FIRE_RL_mmioPlatform_processMTimeCmp || WILL_FIRE_RL_mmioPlatform_processMTime || @@ -5048,7 +5047,7 @@ module mkProc(CLK, mmioPlatform_reqBE[0] ; assign mmioPlatform_waitLowerMSIPCRs$EN = WILL_FIRE_RL_mmioPlatform_processMSIP && - NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d490 ; + NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d486 ; // register mmioPlatform_waitMTIPCRs assign mmioPlatform_waitMTIPCRs$D_IN = @@ -5056,16 +5055,15 @@ module mkProc(CLK, MUX_mmioPlatform_waitMTIPCRs$write_1__VAL_2 ; assign mmioPlatform_waitMTIPCRs$EN = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 && - mmioPlatform_mtimecmp_0 != 64'd0 || + mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 || WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d648 ; + NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d644 ; // register mmioPlatform_waitUpperMSIPCRs assign mmioPlatform_waitUpperMSIPCRs$D_IN = 1'd0 ; assign mmioPlatform_waitUpperMSIPCRs$EN = WILL_FIRE_RL_mmioPlatform_processMSIP && - NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d490 ; + NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d486 ; // register mmio_axi4_adapter_cfg_verbosity assign mmio_axi4_adapter_cfg_verbosity$D_IN = 4'h0 ; @@ -5151,28 +5149,28 @@ module mkProc(CLK, // register propDstData_1_0_rl assign propDstData_1_0_rl$D_IN = - { IF_propDstData_1_0_lat_0_whas__189_THEN_propDs_ETC___d1194, - IF_propDstData_1_0_lat_0_whas__189_THEN_propDs_ETC___d1199, + { IF_propDstData_1_0_lat_0_whas__185_THEN_propDs_ETC___d1190, + IF_propDstData_1_0_lat_0_whas__185_THEN_propDs_ETC___d1195, CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[513] : propDstData_1_0_rl[513], CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[512:1] : propDstData_1_0_rl[512:1], - IF_propDstData_1_0_lat_0_whas__189_THEN_propDs_ETC___d1220 } ; + IF_propDstData_1_0_lat_0_whas__185_THEN_propDs_ETC___d1216 } ; assign propDstData_1_0_rl$EN = 1'd1 ; // register propDstData_1_1_rl assign propDstData_1_1_rl$D_IN = - { IF_propDstData_1_1_lat_0_whas__227_THEN_propDs_ETC___d1232, - IF_propDstData_1_1_lat_0_whas__227_THEN_propDs_ETC___d1237, + { IF_propDstData_1_1_lat_0_whas__223_THEN_propDs_ETC___d1228, + IF_propDstData_1_1_lat_0_whas__223_THEN_propDs_ETC___d1233, CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[513] : propDstData_1_1_rl[513], CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[512:1] : propDstData_1_1_rl[512:1], - IF_propDstData_1_1_lat_0_whas__227_THEN_propDs_ETC___d1258 } ; + IF_propDstData_1_1_lat_0_whas__223_THEN_propDs_ETC___d1254 } ; assign propDstData_1_1_rl$EN = 1'd1 ; // register propDstData_1_rl @@ -5185,36 +5183,36 @@ module mkProc(CLK, // register propDstIdx_0_rl assign propDstIdx_0_rl$D_IN = !propDstIdx_0_lat_1$whas && - IF_propDstIdx_0_lat_0_whas__005_THEN_propDstId_ETC___d1008 ; + IF_propDstIdx_0_lat_0_whas__001_THEN_propDstId_ETC___d1004 ; assign propDstIdx_0_rl$EN = 1'd1 ; // register propDstIdx_1_0_rl assign propDstIdx_1_0_rl$D_IN = !propDstIdx_1_0_lat_1$whas && - IF_propDstIdx_1_0_lat_0_whas__174_THEN_propDst_ETC___d1177 ; + IF_propDstIdx_1_0_lat_0_whas__170_THEN_propDst_ETC___d1173 ; assign propDstIdx_1_0_rl$EN = 1'd1 ; // register propDstIdx_1_1_rl assign propDstIdx_1_1_rl$D_IN = !propDstIdx_1_1_lat_1$whas && - IF_propDstIdx_1_1_lat_0_whas__181_THEN_propDst_ETC___d1184 ; + IF_propDstIdx_1_1_lat_0_whas__177_THEN_propDst_ETC___d1180 ; assign propDstIdx_1_1_rl$EN = 1'd1 ; // register propDstIdx_1_rl assign propDstIdx_1_rl$D_IN = !propDstIdx_1_lat_1$whas && - IF_propDstIdx_1_lat_0_whas__012_THEN_propDstId_ETC___d1015 ; + IF_propDstIdx_1_lat_0_whas__008_THEN_propDstId_ETC___d1011 ; assign propDstIdx_1_rl$EN = 1'd1 ; // register srcRR_0 assign srcRR_0$D_IN = srcRR_0 + 1'd1 ; assign srcRR_0$EN = - NOT_enqDst_0_dummy2_0_read__079_080_OR_NOT_enq_ETC___d1095 ; + NOT_enqDst_0_dummy2_0_read__075_076_OR_NOT_enq_ETC___d1091 ; // register srcRR_1_0 assign srcRR_1_0$D_IN = srcRR_1_0 + 1'd1 ; assign srcRR_1_0$EN = - NOT_enqDst_1_0_dummy2_0_read__348_349_OR_NOT_e_ETC___d1364 ; + NOT_enqDst_1_0_dummy2_0_read__344_345_OR_NOT_e_ETC___d1360 ; // submodule core_0 assign core_0$coreReq_perfReq_loc = 4'h0 ; @@ -5323,7 +5321,7 @@ module mkProc(CLK, assign core_0$setMEIP_v = m_external_interrupt_req_set_not_clear ; assign core_0$setSEIP_v = s_external_interrupt_req_set_not_clear ; assign core_0$tlbToMem_respLd_enq_x = - { ld_data__h131955, llc$dma_respLd_first[3] } ; + { ld_data__h131939, llc$dma_respLd_first[3] } ; assign core_0$EN_coreReq_start = EN_start ; assign core_0$EN_coreReq_perfReq = 1'b0 ; assign core_0$EN_coreIndInv_perfResp = 1'b0 ; @@ -5344,13 +5342,13 @@ module mkProc(CLK, MUX_mmioPlatform_fetchingWay$write_1__SEL_1 ; assign core_0$EN_mmioToPlatform_pRs_enq = WILL_FIRE_RL_mmioPlatform_processMSIP && - mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d467 || + mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d463 || WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d571 || + mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d567 || WILL_FIRE_RL_mmioPlatform_processMTime && - mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d636 || + mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d632 || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && - (!mmioPlatform_fetchingWay_65_ULT_mmioPlatform_r_ETC___d975 || + (!mmioPlatform_fetchingWay_61_ULT_mmioPlatform_r_ETC___d971 || !mmio_axi4_adapter_f_rsps_to_core$D_OUT[64]) || WILL_FIRE_RL_mmioPlatform_waitMTimeDone || WILL_FIRE_RL_mmioPlatform_waitMTimeCmpDone || @@ -5361,16 +5359,15 @@ module mkProc(CLK, WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp ; assign core_0$EN_mmioToPlatform_pRq_enq = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 && - mmioPlatform_mtimecmp_0 != 64'd0 || + mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 || WILL_FIRE_RL_mmioPlatform_processMSIP && mmioPlatform_reqFunc[5:4] != 2'd0 && !mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0] || WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d585 || + NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d581 || WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d648 ; + NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d644 ; assign core_0$EN_mmioToPlatform_cRs_deq = (WILL_FIRE_RL_mmioPlatform_waitMTimeDone || WILL_FIRE_RL_mmioPlatform_waitTimerInterruptDone) && @@ -5427,7 +5424,7 @@ module mkProc(CLK, // submodule enqDst_0_dummy2_0 assign enqDst_0_dummy2_0$D_IN = 1'd1 ; assign enqDst_0_dummy2_0$EN = - NOT_enqDst_0_dummy2_0_read__079_080_OR_NOT_enq_ETC___d1095 ; + NOT_enqDst_0_dummy2_0_read__075_076_OR_NOT_enq_ETC___d1091 ; // submodule enqDst_0_dummy2_1 assign enqDst_0_dummy2_1$D_IN = 1'd1 ; @@ -5436,7 +5433,7 @@ module mkProc(CLK, // submodule enqDst_1_0_dummy2_0 assign enqDst_1_0_dummy2_0$D_IN = 1'd1 ; assign enqDst_1_0_dummy2_0$EN = - NOT_enqDst_1_0_dummy2_0_read__348_349_OR_NOT_e_ETC___d1364 ; + NOT_enqDst_1_0_dummy2_0_read__344_345_OR_NOT_e_ETC___d1360 ; // submodule enqDst_1_0_dummy2_1 assign enqDst_1_0_dummy2_1$D_IN = 1'd1 ; @@ -5468,17 +5465,17 @@ module mkProc(CLK, assign llc$perf_req_r = 4'h0 ; assign llc$perf_setStatus_doStats = core_0$sendDoStats ; assign llc$to_child_rqFromC_enq_x = - NOT_enqDst_0_dummy2_0_read__079_080_OR_NOT_enq_ETC___d1095 ? + NOT_enqDst_0_dummy2_0_read__075_076_OR_NOT_enq_ETC___d1091 ? enqDst_0_lat_0$wget[72:0] : enqDst_0_rl[72:0] ; assign llc$to_child_rsFromC_enq_x = - { IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1280, - IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1285, - IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1290, - IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1300, - IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1306 } ; + { IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1276, + IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1281, + IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1286, + IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1296, + IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1302 } ; assign llc$to_mem_rsFromM_enq_x = - { new_cline__h134656, + { new_cline__h134640, llc_axi4_adapter_f_pending_reads$D_OUT[4:0] } ; assign llc$EN_to_child_rsFromC_enq = CAN_FIRE_RL_doEnq_1 ; assign llc$EN_to_child_rqFromC_enq = CAN_FIRE_RL_doEnq ; @@ -5554,7 +5551,7 @@ module mkProc(CLK, // submodule llc_mem_server_axi4_slave_xactor_f_rd_data assign llc_mem_server_axi4_slave_xactor_f_rd_data$D_IN = - { 4'd0, dword__h93798, 3'd1 } ; + { 4'd0, dword__h93782, 3'd1 } ; assign llc_mem_server_axi4_slave_xactor_f_rd_data$ENQ = CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req ; assign llc_mem_server_axi4_slave_xactor_f_rd_data$DEQ = @@ -5605,7 +5602,7 @@ module mkProc(CLK, // submodule llc_mem_server_enqDst_0_dummy2_0 assign llc_mem_server_enqDst_0_dummy2_0$D_IN = 1'd1 ; assign llc_mem_server_enqDst_0_dummy2_0$EN = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__693_ETC___d1700 ; + NOT_llc_mem_server_enqDst_0_dummy2_0_read__689_ETC___d1696 ; // submodule llc_mem_server_enqDst_0_dummy2_1 assign llc_mem_server_enqDst_0_dummy2_1$D_IN = 1'd1 ; @@ -5635,11 +5632,11 @@ module mkProc(CLK, // submodule llc_mem_server_propDstIdx_0_dummy2_1 assign llc_mem_server_propDstIdx_0_dummy2_1$D_IN = 1'd1 ; assign llc_mem_server_propDstIdx_0_dummy2_1$EN = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__693_ETC___d1700 ; + NOT_llc_mem_server_enqDst_0_dummy2_0_read__689_ETC___d1696 ; // submodule llc_mem_server_tlbQ assign llc_mem_server_tlbQ$D_IN = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__693_ETC___d1700 ? + NOT_llc_mem_server_enqDst_0_dummy2_0_read__689_ETC___d1696 ? llc_mem_server_enqDst_0_lat_0$wget[64:0] : llc_mem_server_enqDst_0_rl[64:0] ; assign llc_mem_server_tlbQ$ENQ = CAN_FIRE_RL_llc_mem_server_doEnq ; @@ -5857,86 +5854,86 @@ module mkProc(CLK, // remaining internal signals module_amoExec instance_amoExec_0(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h30134 && - mmioPlatform_reqBE_BIT_0___h30174, + mmioPlatform_reqBE_BIT_4___h30118 && + mmioPlatform_reqBE_BIT_0___h30158, 2'd0 }), - .amoExec_current_data(x__h37428), - .amoExec_in_data(mmioPlatform_reqData__h48469), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30134 && - !mmioPlatform_reqBE_BIT_0___h30174), - .amoExec(x__h32158)); + .amoExec_current_data(x__h37412), + .amoExec_in_data(mmioPlatform_reqData__h48453), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30118 && + !mmioPlatform_reqBE_BIT_0___h30158), + .amoExec(x__h32142)); module_amoExec instance_amoExec_1(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h30134 && - mmioPlatform_reqBE_BIT_0___h30174, + mmioPlatform_reqBE_BIT_4___h30118 && + mmioPlatform_reqBE_BIT_0___h30158, 2'd0 }), - .amoExec_current_data(mmioPlatform_mtime__h37280), - .amoExec_in_data(mmioPlatform_reqData__h48469), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30134 && - !mmioPlatform_reqBE_BIT_0___h30174), - .amoExec(x__h35068)); + .amoExec_current_data(mmioPlatform_mtime__h37264), + .amoExec_in_data(mmioPlatform_reqData__h48453), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30118 && + !mmioPlatform_reqBE_BIT_0___h30158), + .amoExec(x__h35052)); module_amoExec instance_amoExec_2(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h30134 && - mmioPlatform_reqBE_BIT_0___h30174, + mmioPlatform_reqBE_BIT_4___h30118 && + mmioPlatform_reqBE_BIT_0___h30158, 2'd0 }), - .amoExec_current_data(mmioPlatform_fromHostQ_data_0__h42667), - .amoExec_in_data(mmioPlatform_reqData__h48469), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30134 && - !mmioPlatform_reqBE_BIT_0___h30174), - .amoExec(x__h40868)); + .amoExec_current_data(mmioPlatform_fromHostQ_data_0__h42651), + .amoExec_in_data(mmioPlatform_reqData__h48453), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30118 && + !mmioPlatform_reqBE_BIT_0___h30158), + .amoExec(x__h40852)); module_amoExec instance_amoExec_3(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h30134 && - mmioPlatform_reqBE_BIT_0___h30174, + mmioPlatform_reqBE_BIT_4___h30118 && + mmioPlatform_reqBE_BIT_0___h30158, 2'd0 }), .amoExec_current_data(64'd0), - .amoExec_in_data(mmioPlatform_reqData__h48469), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30134 && - !mmioPlatform_reqBE_BIT_0___h30174), - .amoExec(x__h42888)); - assign DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_40_BIT_ETC___d684 = + .amoExec_in_data(mmioPlatform_reqData__h48453), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30118 && + !mmioPlatform_reqBE_BIT_0___h30158), + .amoExec(x__h42872)); + assign DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_36_BIT_ETC___d680 = { 1'h0, (mmioPlatform_reqFunc[5:4] == 2'd2) ? { mmioPlatform_toHostQ_empty, 64'hAAAAAAAAAAAAAAAA } : { mmioPlatform_reqFunc[5:4] == 2'd1, - x1_avValue_data__h40339 } } ; - assign IF_IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4__ETC___d559 = - (IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 && + x1_avValue_data__h40323 } } ; + assign IF_IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4__ETC___d555 = + (IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && !mmioPlatform_mtip_0 || - !IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 && + !IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && mmioPlatform_mtip_0) ? core_0$RDY_mmioToPlatform_pRq_enq : core_0$RDY_mmioToPlatform_pRs_enq ; - assign IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d456 = + assign IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d452 = (mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? (mmioPlatform_reqBE[0] ? core_0$RDY_mmioToPlatform_pRq_enq : core_0$RDY_mmioToPlatform_pRs_enq) : !mmioPlatform_reqBE[0] || core_0$RDY_mmioToPlatform_pRq_enq ; - assign IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 = - newData__h32047 <= mmioPlatform_mtime ; - assign IF_NOT_propDstIdx_0_dummy2_1_read__058_059_OR__ETC___d1093 = - NOT_propDstIdx_0_dummy2_1_read__058_059_OR_IF__ETC___d1092 ? + assign IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 = + newData__h32031 <= mmioPlatform_mtime ; + assign IF_NOT_propDstIdx_0_dummy2_1_read__054_055_OR__ETC___d1089 = + NOT_propDstIdx_0_dummy2_1_read__054_055_OR_IF__ETC___d1088 ? propDstIdx_1_dummy2_1$Q_OUT && - IF_propDstIdx_1_lat_0_whas__012_THEN_propDstId_ETC___d1015 : + IF_propDstIdx_1_lat_0_whas__008_THEN_propDstId_ETC___d1011 : propDstIdx_0_dummy2_1$Q_OUT && - IF_propDstIdx_0_lat_0_whas__005_THEN_propDstId_ETC___d1008 ; - assign IF_NOT_propDstIdx_1_0_dummy2_1_read__317_318_O_ETC___d1362 = - NOT_propDstIdx_1_0_dummy2_1_read__317_318_OR_I_ETC___d1361 ? + IF_propDstIdx_0_lat_0_whas__001_THEN_propDstId_ETC___d1004 ; + assign IF_NOT_propDstIdx_1_0_dummy2_1_read__313_314_O_ETC___d1358 = + NOT_propDstIdx_1_0_dummy2_1_read__313_314_OR_I_ETC___d1357 ? propDstIdx_1_1_dummy2_1$Q_OUT && - IF_propDstIdx_1_1_lat_0_whas__181_THEN_propDst_ETC___d1184 : + IF_propDstIdx_1_1_lat_0_whas__177_THEN_propDst_ETC___d1180 : propDstIdx_1_0_dummy2_1$Q_OUT && - IF_propDstIdx_1_0_lat_0_whas__174_THEN_propDst_ETC___d1177 ; - assign IF_SEL_ARR_propDstIdx_0_dummy2_1_read__058_AND_ETC___d1165 = - SEL_ARR_propDstIdx_0_dummy2_1_read__058_AND_IF_ETC___d1089 ? + IF_propDstIdx_1_0_lat_0_whas__170_THEN_propDst_ETC___d1173 ; + assign IF_SEL_ARR_propDstIdx_0_dummy2_1_read__054_AND_ETC___d1161 = + SEL_ARR_propDstIdx_0_dummy2_1_read__054_AND_IF_ETC___d1085 ? !srcRR_0 : propDstIdx_0_dummy2_1$Q_OUT && - IF_propDstIdx_0_lat_0_whas__005_THEN_propDstId_ETC___d1008 ; - assign IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__317_A_ETC___d1462 = - SEL_ARR_propDstIdx_1_0_dummy2_1_read__317_AND__ETC___d1358 ? + IF_propDstIdx_0_lat_0_whas__001_THEN_propDstId_ETC___d1004 ; + assign IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__313_A_ETC___d1458 = + SEL_ARR_propDstIdx_1_0_dummy2_1_read__313_AND__ETC___d1354 ? !srcRR_1_0 : propDstIdx_1_0_dummy2_1$Q_OUT && - IF_propDstIdx_1_0_lat_0_whas__174_THEN_propDst_ETC___d1177 ; - assign IF_core_0_mmioToPlatform_cRq_first__82_BITS_14_ETC___d405 = + IF_propDstIdx_1_0_lat_0_whas__170_THEN_propDst_ETC___d1173 ; + assign IF_core_0_mmioToPlatform_cRq_first__78_BITS_14_ETC___d401 = (core_0$mmioToPlatform_cRq_first[141:81] == mmioPlatform_toHostAddr) ? 67'h5AAAAAAAAAAAAAAAA : @@ -5944,116 +5941,116 @@ module mkProc(CLK, mmioPlatform_fromHostAddr) ? 67'h6AAAAAAAAAAAAAAAA : { 3'd7, core_0$mmioToPlatform_cRq_first[141:78] }) ; - assign IF_enqDst_0_lat_0_whas__034_THEN_enqDst_0_lat__ETC___d1039 = - NOT_enqDst_0_dummy2_0_read__079_080_OR_NOT_enq_ETC___d1095 ? + assign IF_enqDst_0_lat_0_whas__030_THEN_enqDst_0_lat__ETC___d1035 = + NOT_enqDst_0_dummy2_0_read__075_076_OR_NOT_enq_ETC___d1091 ? enqDst_0_lat_0$wget[73] : enqDst_0_rl[73] ; - assign IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1270 = - NOT_enqDst_1_0_dummy2_0_read__348_349_OR_NOT_e_ETC___d1364 ? + assign IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1266 = + NOT_enqDst_1_0_dummy2_0_read__344_345_OR_NOT_e_ETC___d1360 ? enqDst_1_0_lat_0$wget[580] : enqDst_1_0_rl[580] ; - assign IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1280 = - NOT_enqDst_1_0_dummy2_0_read__348_349_OR_NOT_e_ETC___d1364 ? + assign IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1276 = + NOT_enqDst_1_0_dummy2_0_read__344_345_OR_NOT_e_ETC___d1360 ? enqDst_1_0_lat_0$wget[579:516] : enqDst_1_0_rl[579:516] ; - assign IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1285 = - NOT_enqDst_1_0_dummy2_0_read__348_349_OR_NOT_e_ETC___d1364 ? + assign IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1281 = + NOT_enqDst_1_0_dummy2_0_read__344_345_OR_NOT_e_ETC___d1360 ? enqDst_1_0_lat_0$wget[515:514] : enqDst_1_0_rl[515:514] ; - assign IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1290 = - NOT_enqDst_1_0_dummy2_0_read__348_349_OR_NOT_e_ETC___d1364 ? + assign IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1286 = + NOT_enqDst_1_0_dummy2_0_read__344_345_OR_NOT_e_ETC___d1360 ? enqDst_1_0_lat_0$wget[513] : enqDst_1_0_rl[513] ; - assign IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1300 = - NOT_enqDst_1_0_dummy2_0_read__348_349_OR_NOT_e_ETC___d1364 ? + assign IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1296 = + NOT_enqDst_1_0_dummy2_0_read__344_345_OR_NOT_e_ETC___d1360 ? enqDst_1_0_lat_0$wget[512:1] : enqDst_1_0_rl[512:1] ; - assign IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1306 = - NOT_enqDst_1_0_dummy2_0_read__348_349_OR_NOT_e_ETC___d1364 ? + assign IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1302 = + NOT_enqDst_1_0_dummy2_0_read__344_345_OR_NOT_e_ETC___d1360 ? enqDst_1_0_lat_0$wget[0] : enqDst_1_0_rl[0] ; - assign IF_enqDst_1_0_lat_1_whas__262_THEN_enqDst_1_0__ETC___d1308 = + assign IF_enqDst_1_0_lat_1_whas__258_THEN_enqDst_1_0__ETC___d1304 = { CAN_FIRE_RL_doEnq_1 || - IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1290, + IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1286, CAN_FIRE_RL_doEnq_1 ? 512'h55555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555 : - IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1300, - x__h74829 } ; - assign IF_enqDst_1_0_lat_1_whas__262_THEN_enqDst_1_0__ETC___d1309 = + IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1296, + x__h74813 } ; + assign IF_enqDst_1_0_lat_1_whas__258_THEN_enqDst_1_0__ETC___d1305 = { CAN_FIRE_RL_doEnq_1 ? 64'hAAAAAAAAAAAAAAAA : - IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1280, + IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1276, CAN_FIRE_RL_doEnq_1 ? 2'b10 : - IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1285, - IF_enqDst_1_0_lat_1_whas__262_THEN_enqDst_1_0__ETC___d1308 } ; - assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1577 = + IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1281, + IF_enqDst_1_0_lat_1_whas__258_THEN_enqDst_1_0__ETC___d1304 } ; + assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1573 = { (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd7) ? - new_dword__h89489 : + new_dword__h89473 : llc_mem_server_rg_cacheline_cache_data[511:448], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd6) ? - new_dword__h89489 : + new_dword__h89473 : llc_mem_server_rg_cacheline_cache_data[447:384], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd5) ? - new_dword__h89489 : + new_dword__h89473 : llc_mem_server_rg_cacheline_cache_data[383:320], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd4) ? - new_dword__h89489 : + new_dword__h89473 : llc_mem_server_rg_cacheline_cache_data[319:256] } ; - assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1582 = - { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1577, + assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1578 = + { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1573, (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd3) ? - new_dword__h89489 : + new_dword__h89473 : llc_mem_server_rg_cacheline_cache_data[255:192], (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd2) ? - new_dword__h89489 : + new_dword__h89473 : llc_mem_server_rg_cacheline_cache_data[191:128] } ; - assign IF_llc_mem_server_enqDst_0_lat_0_whas__662_THE_ETC___d1667 = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__693_ETC___d1700 ? + assign IF_llc_mem_server_enqDst_0_lat_0_whas__658_THE_ETC___d1663 = + NOT_llc_mem_server_enqDst_0_dummy2_0_read__689_ETC___d1696 ? llc_mem_server_enqDst_0_lat_0$wget[65] : llc_mem_server_enqDst_0_rl[65] ; - assign IF_llc_mem_server_propDstIdx_0_lat_0_whas__647_ETC___d1650 = + assign IF_llc_mem_server_propDstIdx_0_lat_0_whas__643_ETC___d1646 = CAN_FIRE_RL_llc_mem_server_srcPropose || llc_mem_server_propDstIdx_0_rl ; - assign IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d825 = + assign IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d821 = (mmioPlatform_curReq[2:0] == 3'h0) ? mmioPlatform_reqData : 64'd0 ; - assign IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d876 = + assign IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d872 = (mmioPlatform_curReq[2:0] == 3'h0) ? mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:0] : 64'd0 ; - assign IF_mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioP_ETC___d625 = - ((mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && + assign IF_mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioP_ETC___d621 = + ((mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && !mmioPlatform_mtip_0) ? core_0$RDY_mmioToPlatform_pRq_enq : - mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 || + mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 || !mmioPlatform_mtip_0 || core_0$RDY_mmioToPlatform_pRq_enq) && - (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && + (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && + !mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && mmioPlatform_mtip_0 || core_0$RDY_mmioToPlatform_pRs_enq) ; - assign IF_mmioPlatform_reqBE_43_BIT_4_44_THEN_SEXT_mm_ETC___d577 = + assign IF_mmioPlatform_reqBE_39_BIT_4_40_THEN_SEXT_mm_ETC___d573 = mmioPlatform_reqBE[4] ? { {32{mmioPlatform_mtimecmp_0_BITS_63_TO_32__q9[31]}}, mmioPlatform_mtimecmp_0_BITS_63_TO_32__q9 } : { {32{mmioPlatform_mtimecmp_0_BITS_31_TO_0__q10[31]}}, mmioPlatform_mtimecmp_0_BITS_31_TO_0__q10 } ; - assign IF_mmioPlatform_reqBE_43_BIT_4_44_THEN_SEXT_mm_ETC___d641 = + assign IF_mmioPlatform_reqBE_39_BIT_4_40_THEN_SEXT_mm_ETC___d637 = mmioPlatform_reqBE[4] ? { {32{mmioPlatform_mtime_BITS_63_TO_32__q11[31]}}, mmioPlatform_mtime_BITS_63_TO_32__q11 } : { {32{mmioPlatform_mtime_BITS_31_TO_0__q12[31]}}, mmioPlatform_mtime_BITS_31_TO_0__q12 } ; - assign IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d535 = + assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d531 = { mmioPlatform_reqBE[7] ? mmioPlatform_reqData[63:56] : mmioPlatform_mtimecmp_0[63:56], @@ -6066,23 +6063,23 @@ module mkProc(CLK, mmioPlatform_reqBE[4] ? mmioPlatform_reqData[39:32] : mmioPlatform_mtimecmp_0[39:32] } ; - assign IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d544 = - { IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d535, + assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d540 = + { IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d531, mmioPlatform_reqBE[3] ? mmioPlatform_reqData[31:24] : mmioPlatform_mtimecmp_0[31:24], mmioPlatform_reqBE[2] ? mmioPlatform_reqData[23:16] : mmioPlatform_mtimecmp_0[23:16] } ; - assign IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d552 = - { IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d544, + assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d548 = + { IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d540, mmioPlatform_reqBE[1] ? mmioPlatform_reqData[15:8] : mmioPlatform_mtimecmp_0[15:8], mmioPlatform_reqBE[0] ? mmioPlatform_reqData[7:0] : mmioPlatform_mtimecmp_0[7:0] } ; - assign IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d604 = + assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d600 = { mmioPlatform_reqBE[7] ? mmioPlatform_reqData[63:56] : mmioPlatform_mtime[63:56], @@ -6095,23 +6092,23 @@ module mkProc(CLK, mmioPlatform_reqBE[4] ? mmioPlatform_reqData[39:32] : mmioPlatform_mtime[39:32] } ; - assign IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d609 = - { IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d604, + assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d605 = + { IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d600, mmioPlatform_reqBE[3] ? mmioPlatform_reqData[31:24] : mmioPlatform_mtime[31:24], mmioPlatform_reqBE[2] ? mmioPlatform_reqData[23:16] : mmioPlatform_mtime[23:16] } ; - assign IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d614 = - { IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d609, + assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d610 = + { IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d605, mmioPlatform_reqBE[1] ? mmioPlatform_reqData[15:8] : mmioPlatform_mtime[15:8], mmioPlatform_reqBE[0] ? mmioPlatform_reqData[7:0] : mmioPlatform_mtime[7:0] } ; - assign IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d705 = + assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d701 = { mmioPlatform_reqBE[7] ? mmioPlatform_reqData[63:56] : mmioPlatform_fromHostQ_data_0[63:56], @@ -6124,49 +6121,49 @@ module mkProc(CLK, mmioPlatform_reqBE[4] ? mmioPlatform_reqData[39:32] : mmioPlatform_fromHostQ_data_0[39:32] } ; - assign IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d710 = - { IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d705, + assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d706 = + { IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d701, mmioPlatform_reqBE[3] ? mmioPlatform_reqData[31:24] : mmioPlatform_fromHostQ_data_0[31:24], mmioPlatform_reqBE[2] ? mmioPlatform_reqData[23:16] : mmioPlatform_fromHostQ_data_0[23:16] } ; - assign IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d715 = - { IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d710, + assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d711 = + { IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d706, mmioPlatform_reqBE[1] ? mmioPlatform_reqData[15:8] : mmioPlatform_fromHostQ_data_0[15:8], mmioPlatform_reqBE[0] ? mmioPlatform_reqData[7:0] : mmioPlatform_fromHostQ_data_0[7:0] } ; - assign IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_ETC___d457 = + assign IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d453 = (mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqBE[4]) ? core_0$RDY_mmioToPlatform_pRs_enq : - IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d456 ; - assign IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_1_ETC___d578 = + IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d452 ; + assign IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_1_ETC___d574 = (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtimecmp_0 : - IF_mmioPlatform_reqBE_43_BIT_4_44_THEN_SEXT_mm_ETC___d577 ; - assign IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_1_ETC___d642 = + IF_mmioPlatform_reqBE_39_BIT_4_40_THEN_SEXT_mm_ETC___d573 ; + assign IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_1_ETC___d638 = (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtime : - IF_mmioPlatform_reqBE_43_BIT_4_44_THEN_SEXT_mm_ETC___d641 ; - assign IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_2_ETC___d723 = + IF_mmioPlatform_reqBE_39_BIT_4_40_THEN_SEXT_mm_ETC___d637 ; + assign IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_2_ETC___d719 = (mmioPlatform_reqFunc[5:4] == 2'd2) ? { mmioPlatform_fromHostQ_empty ? - x__h42877 == 64'd0 : - x__h40857 == 64'd0, + x__h42861 == 64'd0 : + x__h40841 == 64'd0, 64'hAAAAAAAAAAAAAAAA } : { mmioPlatform_reqFunc[5:4] == 2'd1, - x1_avValue_data__h44806 } ; + x1_avValue_data__h44790 } ; assign IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__91__ETC___d200 = mmioPlatform_toHostQ_enqReq_lat_0$whas ? mmioPlatform_toHostQ_enqReq_lat_0$wget[64] : mmioPlatform_toHostQ_enqReq_rl[64] ; - assign IF_mmioPlatform_waitLowerMSIPCRs_92_THEN_core__ETC___d500 = + assign IF_mmioPlatform_waitLowerMSIPCRs_88_THEN_core__ETC___d496 = mmioPlatform_waitLowerMSIPCRs ? core_0$RDY_mmioToPlatform_cRs_first && core_0$RDY_mmioToPlatform_cRs_deq : @@ -6174,99 +6171,99 @@ module mkProc(CLK, core_0$RDY_mmioToPlatform_cRs_first) && (!mmioPlatform_waitUpperMSIPCRs || core_0$RDY_mmioToPlatform_cRs_deq) ; - assign IF_mmio_axi4_adapter_f_rsps_to_core_first__56__ETC___d970 = + assign IF_mmio_axi4_adapter_f_rsps_to_core_first__52__ETC___d966 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] ? mmioPlatform_fetchingWay < (mmioPlatform_reqFunc[5:4] == 2'd0 && mmioPlatform_reqFunc[0]) || core_0$RDY_mmioToPlatform_pRs_enq : core_0$RDY_mmioToPlatform_pRs_enq ; - assign IF_mmio_axi4_adapter_f_rsps_to_core_first__56__ETC___d991 = + assign IF_mmio_axi4_adapter_f_rsps_to_core_first__52__ETC___d987 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] ? (mmioPlatform_fetchingWay ? mmioPlatform_fetchedInsts_0 : - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d983) : + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d979) : mmioPlatform_fetchedInsts_0 ; assign IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d103 = mmio_axi4_adapter_soc_map$m_is_IO_addr ? !mmio_axi4_adapter_master_xactor_crg_wr_addr_full$port2__read && !mmio_axi4_adapter_master_xactor_crg_wr_data_full$port2__read : mmio_axi4_adapter_f_rsps_to_core$FULL_N ; - assign IF_propDstData_0_dummy2_1_read__096_THEN_IF_pr_ETC___d1112 = + assign IF_propDstData_0_dummy2_1_read__092_THEN_IF_pr_ETC___d1108 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[8:7] : propDstData_0_rl[8:7]) : 2'd0 ; - assign IF_propDstData_0_dummy2_1_read__096_THEN_IF_pr_ETC___d1122 = + assign IF_propDstData_0_dummy2_1_read__092_THEN_IF_pr_ETC___d1118 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[6:5] : propDstData_0_rl[6:5]) : 2'd0 ; - assign IF_propDstData_1_0_lat_0_whas__189_THEN_propDs_ETC___d1194 = + assign IF_propDstData_1_0_lat_0_whas__185_THEN_propDs_ETC___d1190 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[579:516] : propDstData_1_0_rl[579:516] ; - assign IF_propDstData_1_0_lat_0_whas__189_THEN_propDs_ETC___d1199 = + assign IF_propDstData_1_0_lat_0_whas__185_THEN_propDs_ETC___d1195 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[515:514] : propDstData_1_0_rl[515:514] ; - assign IF_propDstData_1_0_lat_0_whas__189_THEN_propDs_ETC___d1220 = + assign IF_propDstData_1_0_lat_0_whas__185_THEN_propDs_ETC___d1216 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[0] : propDstData_1_0_rl[0] ; - assign IF_propDstData_1_1_lat_0_whas__227_THEN_propDs_ETC___d1232 = + assign IF_propDstData_1_1_lat_0_whas__223_THEN_propDs_ETC___d1228 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[579:516] : propDstData_1_1_rl[579:516] ; - assign IF_propDstData_1_1_lat_0_whas__227_THEN_propDs_ETC___d1237 = + assign IF_propDstData_1_1_lat_0_whas__223_THEN_propDs_ETC___d1233 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[515:514] : propDstData_1_1_rl[515:514] ; - assign IF_propDstData_1_1_lat_0_whas__227_THEN_propDs_ETC___d1258 = + assign IF_propDstData_1_1_lat_0_whas__223_THEN_propDs_ETC___d1254 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[0] : propDstData_1_1_rl[0] ; - assign IF_propDstData_1_dummy2_1_read__101_THEN_IF_pr_ETC___d1116 = + assign IF_propDstData_1_dummy2_1_read__097_THEN_IF_pr_ETC___d1112 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[8:7] : propDstData_1_rl[8:7]) : 2'd0 ; - assign IF_propDstData_1_dummy2_1_read__101_THEN_IF_pr_ETC___d1126 = + assign IF_propDstData_1_dummy2_1_read__097_THEN_IF_pr_ETC___d1122 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[6:5] : propDstData_1_rl[6:5]) : 2'd0 ; - assign IF_propDstIdx_0_lat_0_whas__005_THEN_propDstId_ETC___d1008 = + assign IF_propDstIdx_0_lat_0_whas__001_THEN_propDstId_ETC___d1004 = CAN_FIRE_RL_srcPropose || propDstIdx_0_rl ; - assign IF_propDstIdx_1_0_lat_0_whas__174_THEN_propDst_ETC___d1177 = + assign IF_propDstIdx_1_0_lat_0_whas__170_THEN_propDst_ETC___d1173 = CAN_FIRE_RL_srcPropose_2 || propDstIdx_1_0_rl ; - assign IF_propDstIdx_1_1_lat_0_whas__181_THEN_propDst_ETC___d1184 = + assign IF_propDstIdx_1_1_lat_0_whas__177_THEN_propDst_ETC___d1180 = CAN_FIRE_RL_srcPropose_3 || propDstIdx_1_1_rl ; - assign IF_propDstIdx_1_lat_0_whas__012_THEN_propDstId_ETC___d1015 = + assign IF_propDstIdx_1_lat_0_whas__008_THEN_propDstId_ETC___d1011 = CAN_FIRE_RL_srcPropose_1 || propDstIdx_1_rl ; - assign NOT_enqDst_0_dummy2_0_read__079_080_OR_NOT_enq_ETC___d1095 = + assign NOT_enqDst_0_dummy2_0_read__075_076_OR_NOT_enq_ETC___d1091 = (!enqDst_0_dummy2_0$Q_OUT || !enqDst_0_dummy2_1$Q_OUT || !enqDst_0_rl[73]) && - (SEL_ARR_propDstIdx_0_dummy2_1_read__058_AND_IF_ETC___d1089 || - IF_NOT_propDstIdx_0_dummy2_1_read__058_059_OR__ETC___d1093) ; - assign NOT_enqDst_1_0_dummy2_0_read__348_349_OR_NOT_e_ETC___d1364 = + (SEL_ARR_propDstIdx_0_dummy2_1_read__054_AND_IF_ETC___d1085 || + IF_NOT_propDstIdx_0_dummy2_1_read__054_055_OR__ETC___d1089) ; + assign NOT_enqDst_1_0_dummy2_0_read__344_345_OR_NOT_e_ETC___d1360 = (!enqDst_1_0_dummy2_0$Q_OUT || !enqDst_1_0_dummy2_1$Q_OUT || !enqDst_1_0_rl[580]) && - (SEL_ARR_propDstIdx_1_0_dummy2_1_read__317_AND__ETC___d1358 || - IF_NOT_propDstIdx_1_0_dummy2_1_read__317_318_O_ETC___d1362) ; - assign NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780 = + (SEL_ARR_propDstIdx_1_0_dummy2_1_read__313_AND__ETC___d1354 || + IF_NOT_propDstIdx_1_0_dummy2_1_read__313_314_O_ETC___d1358) ; + assign NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776 = llc_axi4_adapter_cfg_verbosity > 4'd1 ; - assign NOT_llc_mem_server_enqDst_0_dummy2_0_read__693_ETC___d1700 = + assign NOT_llc_mem_server_enqDst_0_dummy2_0_read__689_ETC___d1696 = (!llc_mem_server_enqDst_0_dummy2_0$Q_OUT || !llc_mem_server_enqDst_0_dummy2_1$Q_OUT || !llc_mem_server_enqDst_0_rl[65]) && llc_mem_server_propDstIdx_0_dummy2_1$Q_OUT && - IF_llc_mem_server_propDstIdx_0_lat_0_whas__647_ETC___d1650 ; - assign NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d746 = + IF_llc_mem_server_propDstIdx_0_lat_0_whas__643_ETC___d1646 ; + assign NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d742 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -6277,7 +6274,7 @@ module mkProc(CLK, mmioPlatform_state == 2'd2 && (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqFunc[5:4] == 2'd2) ; - assign NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d754 = + assign NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d750 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -6288,7 +6285,7 @@ module mkProc(CLK, mmioPlatform_state == 2'd3 && (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqFunc[5:4] == 2'd2) ; - assign NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d759 = + assign NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d755 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -6300,7 +6297,7 @@ module mkProc(CLK, mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2 ; - assign NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d769 = + assign NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d765 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -6312,7 +6309,7 @@ module mkProc(CLK, mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2 ; - assign NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d960 = + assign NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d956 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -6322,7 +6319,7 @@ module mkProc(CLK, mmioPlatform_curReq[66:64] != 3'd6 && mmioPlatform_state == 2'd2 && mmioPlatform_reqFunc[5:4] == 2'd0 ; - assign NOT_mmioPlatform_curReq_35_BITS_66_TO_64_36_EQ_ETC___d973 = + assign NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d969 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -6342,35 +6339,29 @@ module mkProc(CLK, (mmioPlatform_fromHostQ_deqReq_lat_0$whas || mmioPlatform_fromHostQ_deqReq_rl) || mmioPlatform_fromHostQ_empty) ; - assign NOT_mmioPlatform_mtip_0_55_64_AND_mmioPlatform_ETC___d374 = + assign NOT_mmioPlatform_mtip_0_55_62_AND_mmioPlatform_ETC___d370 = !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 && - mmioPlatform_mtimecmp_0 != 64'd0 || + mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 || !core_0$mmioToPlatform_cRq_notEmpty || core_0$RDY_mmioToPlatform_cRq_first && core_0$RDY_mmioToPlatform_cRq_deq ; - assign NOT_mmioPlatform_mtip_0_55_64_AND_mmioPlatform_ETC___d379 = - !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 && - mmioPlatform_mtimecmp_0 != 64'd0 || - core_0$mmioToPlatform_cRq_notEmpty ; - assign NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d490 = + assign NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d486 = mmioPlatform_reqFunc[5:4] != 2'd0 && !mmioPlatform_reqBE[4] && (mmioPlatform_reqBE[0] || mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqFunc[5:4] == 2'd2) ; - assign NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d585 = + assign NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d581 = mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && - (IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 && + (IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && !mmioPlatform_mtip_0 || - !IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 && + !IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 && mmioPlatform_mtip_0) ; - assign NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ__ETC___d648 = + assign NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d644 = mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && - (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && + (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 && + !mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 && mmioPlatform_mtip_0) ; assign NOT_mmioPlatform_toHostQ_clearReq_dummy2_1_rea_ETC___d240 = !mmioPlatform_toHostQ_clearReq_dummy2_1$Q_OUT || @@ -6384,51 +6375,51 @@ module mkProc(CLK, (!mmioPlatform_toHostQ_empty || mmioPlatform_toHostQ_deqReq_rl) || mmioPlatform_toHostQ_empty) ; - assign NOT_propDstData_1_0_dummy2_1_read__365_376_OR__ETC___d1377 = + assign NOT_propDstData_1_0_dummy2_1_read__361_372_OR__ETC___d1373 = !propDstData_1_0_dummy2_1$Q_OUT || (CAN_FIRE_RL_srcPropose_2 ? !propDstData_1_0_lat_0$wget[513] : !propDstData_1_0_rl[513]) ; - assign NOT_propDstData_1_1_dummy2_1_read__367_378_OR__ETC___d1379 = + assign NOT_propDstData_1_1_dummy2_1_read__363_374_OR__ETC___d1375 = !propDstData_1_1_dummy2_1$Q_OUT || (CAN_FIRE_RL_srcPropose_3 ? !propDstData_1_1_lat_0$wget[513] : !propDstData_1_1_rl[513]) ; - assign NOT_propDstIdx_0_dummy2_1_read__058_059_OR_IF__ETC___d1092 = + assign NOT_propDstIdx_0_dummy2_1_read__054_055_OR_IF__ETC___d1088 = !propDstIdx_0_dummy2_1$Q_OUT || !CAN_FIRE_RL_srcPropose && !propDstIdx_0_rl ; - assign NOT_propDstIdx_1_0_dummy2_1_read__317_318_OR_I_ETC___d1361 = + assign NOT_propDstIdx_1_0_dummy2_1_read__313_314_OR_I_ETC___d1357 = !propDstIdx_1_0_dummy2_1$Q_OUT || !CAN_FIRE_RL_srcPropose_2 && !propDstIdx_1_0_rl ; - assign SEL_ARR_IF_propDstData_0_dummy2_1_read__096_TH_ETC___d1160 = - { CASE_x1277_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21, - CASE_x1277_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22, - SEL_ARR_propDstData_0_dummy2_1_read__096_AND_I_ETC___d1159 } ; - assign SEL_ARR_IF_propDstData_1_0_dummy2_1_read__365__ETC___d1457 = - { CASE_x9900_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32, - !CASE_x9900_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__189_THE_ETC___d1450, - x__h82316 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__189_THE_ETC___d1399 = - { CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24, - CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__189_THE_ETC___d1416 = - { SEL_ARR_IF_propDstData_1_0_lat_0_whas__189_THE_ETC___d1399, - CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26, - CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__189_THE_ETC___d1433 = - { SEL_ARR_IF_propDstData_1_0_lat_0_whas__189_THE_ETC___d1416, - CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28, - CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__189_THE_ETC___d1450 = - { SEL_ARR_IF_propDstData_1_0_lat_0_whas__189_THE_ETC___d1433, - CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30, - CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 } ; - assign SEL_ARR_propDstData_0_dummy2_1_read__096_AND_I_ETC___d1159 = - { CASE_x1277_0_propDstData_0_dummy2_1_read__096__ETC__q20, - x__h61591, - x__h61598 } ; - assign b__h133661 = + assign SEL_ARR_IF_propDstData_0_dummy2_1_read__092_TH_ETC___d1156 = + { CASE_x1261_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21, + CASE_x1261_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22, + SEL_ARR_propDstData_0_dummy2_1_read__092_AND_I_ETC___d1155 } ; + assign SEL_ARR_IF_propDstData_1_0_dummy2_1_read__361__ETC___d1453 = + { CASE_x9884_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32, + !CASE_x9884_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1446, + x__h82300 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1395 = + { CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24, + CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1412 = + { SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1395, + CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26, + CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1429 = + { SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1412, + CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28, + CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1446 = + { SEL_ARR_IF_propDstData_1_0_lat_0_whas__185_THE_ETC___d1429, + CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30, + CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 } ; + assign SEL_ARR_propDstData_0_dummy2_1_read__092_AND_I_ETC___d1155 = + { CASE_x1261_0_propDstData_0_dummy2_1_read__092__ETC__q20, + x__h61575, + x__h61582 } ; + assign b__h133645 = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ? llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 : llc_axi4_adapter_ctr_wr_rsps_pending_crg ; @@ -6436,23 +6427,23 @@ module mkProc(CLK, mmio_axi4_adapter_ctr_wr_rsps_pending_crg$EN_port0__write ? mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 : mmio_axi4_adapter_ctr_wr_rsps_pending_crg ; - assign data__h31966 = + assign data__h31950 = mmioPlatform_waitLowerMSIPCRs ? { 63'd0, core_0$mmioToPlatform_cRs_first } : - { v__h31759, 32'd0 } ; - assign failed_testnum__h162439 = + { v__h31743, 32'd0 } ; + assign failed_testnum__h162423 = { 1'd0, mmioPlatform_toHostQ_data_0[63:1] } ; - assign line_addr__h101862 = + assign line_addr__h101846 = { llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[92:35], 6'b0 } ; - assign line_addr__h101948 = + assign line_addr__h101932 = { llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[92:35], 6'b0 } ; - assign llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1594 = - line_addr__h101948 == llc_mem_server_rg_cacheline_cache_addr ; - assign llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1516 = - line_addr__h101862 == llc_mem_server_rg_cacheline_cache_addr ; - assign mask__h89485 = + assign llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1590 = + line_addr__h101932 == llc_mem_server_rg_cacheline_cache_addr ; + assign llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1512 = + line_addr__h101846 == llc_mem_server_rg_cacheline_cache_addr ; + assign mask__h89469 = { llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8] ? 8'hFF : 8'h0, @@ -6477,14 +6468,14 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[1] ? 8'hFF : 8'h0 } ; - assign mem_req_rd_addr_araddr__h133954 = - { llc$to_mem_toM_first[68:11], x__h133989 } ; - assign mem_req_wr_addr_awaddr__h147878 = - { llc$to_mem_toM_first[639:582], x__h147903 } ; + assign mem_req_rd_addr_araddr__h133938 = + { llc$to_mem_toM_first[68:11], x__h133973 } ; + assign mem_req_wr_addr_awaddr__h147862 = + { llc$to_mem_toM_first[639:582], x__h147887 } ; assign mmioPlatform_cycle_47_ULT_99___d348 = mmioPlatform_cycle < 7'd99 ; - assign mmioPlatform_fetchingWay_65_ULT_mmioPlatform_r_ETC___d975 = + assign mmioPlatform_fetchingWay_61_ULT_mmioPlatform_r_ETC___d971 = mmioPlatform_fetchingWay < mmioPlatform_reqFunc[0] ; - assign mmioPlatform_fromHostQ_data_0__h42667 = + assign mmioPlatform_fromHostQ_data_0__h42651 = mmioPlatform_fromHostQ_data_0 ; assign mmioPlatform_fromHostQ_enqReq_dummy2_2_read__1_ETC___d331 = mmioPlatform_fromHostQ_enqReq_dummy2_2$Q_OUT && @@ -6495,41 +6486,36 @@ module mkProc(CLK, mmioPlatform_fromHostQ_full ; assign mmioPlatform_mtime_BITS_31_TO_0__q12 = mmioPlatform_mtime[31:0] ; assign mmioPlatform_mtime_BITS_63_TO_32__q11 = mmioPlatform_mtime[63:32] ; - assign mmioPlatform_mtime__h37280 = mmioPlatform_mtime ; - assign mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 = - mmioPlatform_mtimecmp_0 <= newData__h34977 ; + assign mmioPlatform_mtime__h37264 = mmioPlatform_mtime ; + assign mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 = + mmioPlatform_mtimecmp_0 <= newData__h34961 ; assign mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 = mmioPlatform_mtimecmp_0 <= mmioPlatform_mtime ; assign mmioPlatform_mtimecmp_0_BITS_31_TO_0__q10 = mmioPlatform_mtimecmp_0[31:0] ; assign mmioPlatform_mtimecmp_0_BITS_63_TO_32__q9 = mmioPlatform_mtimecmp_0[63:32] ; - assign mmioPlatform_mtip_0_55_OR_NOT_mmioPlatform_mti_ETC___d410 = - (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 || - mmioPlatform_mtimecmp_0 == 64'd0) && - core_0$mmioToPlatform_cRq_notEmpty ; - assign mmioPlatform_reqBE_BIT_0___h30174 = mmioPlatform_reqBE[0] ; - assign mmioPlatform_reqBE_BIT_4___h30134 = mmioPlatform_reqBE[4] ; - assign mmioPlatform_reqData__h48469 = mmioPlatform_reqData ; - assign mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d467 = + assign mmioPlatform_reqBE_BIT_0___h30158 = mmioPlatform_reqBE[0] ; + assign mmioPlatform_reqBE_BIT_4___h30118 = mmioPlatform_reqBE[4] ; + assign mmioPlatform_reqData__h48453 = mmioPlatform_reqData ; + assign mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d463 = mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqBE[4] || mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2 && !mmioPlatform_reqBE[0] ; - assign mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d571 = + assign mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d567 = mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqFunc[5:4] == 2'd1 || - (!IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 || + (!IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 || mmioPlatform_mtip_0) && - (IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4_41__ETC___d554 || + (IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 || !mmioPlatform_mtip_0) ; - assign mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_42_ETC___d636 = + assign mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d632 = mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqFunc[5:4] == 2'd1 || - (!mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 || + (!mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 || mmioPlatform_mtip_0) && - (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d616 || + (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 || !mmioPlatform_mtip_0) ; assign mmioPlatform_toHostQ_enqReq_dummy2_2_read__41__ETC___d253 = mmioPlatform_toHostQ_enqReq_dummy2_2$Q_OUT && @@ -6543,235 +6529,235 @@ module mkProc(CLK, (mmio_axi4_adapter_soc_map$m_is_IO_addr ? !mmio_axi4_adapter_master_xactor_crg_rd_addr_full$port2__read : mmio_axi4_adapter_f_rsps_to_core$FULL_N) ; - assign n__read_addr__h61459 = + assign n__read_addr__h61443 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[72:9] : propDstData_0_rl[72:9]) : 64'd0 ; - assign n__read_addr__h61544 = + assign n__read_addr__h61528 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[72:9] : propDstData_1_rl[72:9]) : 64'd0 ; - assign n__read_addr__h80078 = + assign n__read_addr__h80062 = propDstData_1_0_dummy2_1$Q_OUT ? - IF_propDstData_1_0_lat_0_whas__189_THEN_propDs_ETC___d1194 : + IF_propDstData_1_0_lat_0_whas__185_THEN_propDs_ETC___d1190 : 64'd0 ; - assign n__read_addr__h80157 = + assign n__read_addr__h80141 = propDstData_1_1_dummy2_1$Q_OUT ? - IF_propDstData_1_1_lat_0_whas__227_THEN_propDs_ETC___d1232 : + IF_propDstData_1_1_lat_0_whas__223_THEN_propDs_ETC___d1228 : 64'd0 ; - assign n__read_child__h61464 = + assign n__read_child__h61448 = propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[0] : propDstData_0_rl[0]) ; - assign n__read_child__h61549 = + assign n__read_child__h61533 = propDstData_1_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[0] : propDstData_1_rl[0]) ; - assign n__read_child__h80081 = + assign n__read_child__h80065 = propDstData_1_0_dummy2_1$Q_OUT && - IF_propDstData_1_0_lat_0_whas__189_THEN_propDs_ETC___d1220 ; - assign n__read_child__h80160 = + IF_propDstData_1_0_lat_0_whas__185_THEN_propDs_ETC___d1216 ; + assign n__read_child__h80144 = propDstData_1_1_dummy2_1$Q_OUT && - IF_propDstData_1_1_lat_0_whas__227_THEN_propDs_ETC___d1258 ; - assign n__read_id__h61463 = + IF_propDstData_1_1_lat_0_whas__223_THEN_propDs_ETC___d1254 ; + assign n__read_id__h61447 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[3:1] : propDstData_0_rl[3:1]) : 3'd0 ; - assign n__read_id__h61548 = + assign n__read_id__h61532 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[3:1] : propDstData_1_rl[3:1]) : 3'd0 ; - assign n__read_snd_addr__h123389 = + assign n__read_snd_addr__h123373 = llc_mem_server_propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_llc_mem_server_srcPropose ? core_0$tlbToMem_memReq_first[64:1] : llc_mem_server_propDstData_0_rl[64:1]) : 64'd0 ; - assign n__read_snd_id__h123390 = + assign n__read_snd_id__h123374 = llc_mem_server_propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_llc_mem_server_srcPropose ? core_0$tlbToMem_memReq_first[0] : llc_mem_server_propDstData_0_rl[0]) ; - assign newData__h32047 = + assign newData__h32031 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h32158 : - IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d552 ; - assign newData__h34977 = + x__h32142 : + IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d548 ; + assign newData__h34961 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h35068 : - IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d614 ; - assign new_cline__h134656 = + x__h35052 : + IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d610 ; + assign new_cline__h134640 = { llc_axi4_adapter_master_xactor_rg_rd_data[66:3], llc_axi4_adapter_rg_cline[511:64] } ; - assign new_dword__h89489 = x__h90651 | y__h90652 ; - assign op_result__h48485 = - IF_mmioPlatform_reqSz_75_EQ_0b10_82_THEN_SEXT__ETC___d883 + - IF_mmioPlatform_reqSz_75_EQ_0b10_82_THEN_SEXT__ETC___d885 ; - assign op_result__h49015 = w1__h47882 ^ w2__h47884 ; - assign op_result__h49020 = w1__h47882 & w2__h47884 ; - assign op_result__h49025 = w1__h47882 | w2__h47884 ; - assign op_result__h49030 = - (w1__h47882 < w2__h47884) ? w1__h47882 : w2__h47884 ; - assign op_result__h49036 = - (w1__h47882 <= w2__h47884) ? w2__h47884 : w1__h47882 ; - assign op_result__h49043 = - ((IF_mmioPlatform_reqSz_75_EQ_0b10_82_THEN_SEXT__ETC___d883 ^ + assign new_dword__h89473 = x__h90635 | y__h90636 ; + assign op_result__h48469 = + IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d879 + + IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d881 ; + assign op_result__h48999 = w1__h47866 ^ w2__h47868 ; + assign op_result__h49004 = w1__h47866 & w2__h47868 ; + assign op_result__h49009 = w1__h47866 | w2__h47868 ; + assign op_result__h49014 = + (w1__h47866 < w2__h47868) ? w1__h47866 : w2__h47868 ; + assign op_result__h49020 = + (w1__h47866 <= w2__h47868) ? w2__h47868 : w1__h47866 ; + assign op_result__h49027 = + ((IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d879 ^ 64'h8000000000000000) < - (IF_mmioPlatform_reqSz_75_EQ_0b10_82_THEN_SEXT__ETC___d885 ^ + (IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d881 ^ 64'h8000000000000000)) ? - w1__h47882 : - w2__h47884 ; - assign op_result__h49049 = - ((IF_mmioPlatform_reqSz_75_EQ_0b10_82_THEN_SEXT__ETC___d883 ^ + w1__h47866 : + w2__h47868 ; + assign op_result__h49033 = + ((IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d879 ^ 64'h8000000000000000) <= - (IF_mmioPlatform_reqSz_75_EQ_0b10_82_THEN_SEXT__ETC___d885 ^ + (IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d881 ^ 64'h8000000000000000)) ? - w2__h47884 : - w1__h47882 ; - assign propDstData_0_dummy2_1_read__096_AND_IF_propDs_ETC___d1132 = + w2__h47868 : + w1__h47866 ; + assign propDstData_0_dummy2_1_read__092_AND_IF_propDs_ETC___d1128 = propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[4] : propDstData_0_rl[4]) ; - assign propDstData_1_dummy2_1_read__101_AND_IF_propDs_ETC___d1136 = + assign propDstData_1_dummy2_1_read__097_AND_IF_propDs_ETC___d1132 = propDstData_1_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[4] : propDstData_1_rl[4]) ; - assign result__h47928 = + assign result__h47912 = { mmioPlatform_reqData[63:8], - IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915[7:0] } ; - assign result__h48052 = { 56'd0, mmioPlatform_reqData[7:0] } ; - assign result__h48080 = { 56'd0, mmioPlatform_reqData[15:8] } ; - assign result__h48108 = { 56'd0, mmioPlatform_reqData[23:16] } ; - assign result__h48136 = { 56'd0, mmioPlatform_reqData[31:24] } ; - assign result__h48164 = { 56'd0, mmioPlatform_reqData[39:32] } ; - assign result__h48192 = { 56'd0, mmioPlatform_reqData[47:40] } ; - assign result__h48220 = { 56'd0, mmioPlatform_reqData[55:48] } ; - assign result__h48248 = { 56'd0, mmioPlatform_reqData[63:56] } ; - assign result__h48293 = { 48'd0, mmioPlatform_reqData[15:0] } ; - assign result__h48321 = { 48'd0, mmioPlatform_reqData[31:16] } ; - assign result__h48349 = { 48'd0, mmioPlatform_reqData[47:32] } ; - assign result__h48377 = { 48'd0, mmioPlatform_reqData[63:48] } ; - assign result__h48418 = { 32'd0, mmioPlatform_reqData[31:0] } ; - assign result__h48446 = { 32'd0, mmioPlatform_reqData[63:32] } ; - assign result__h48572 = + IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[7:0] } ; + assign result__h48036 = { 56'd0, mmioPlatform_reqData[7:0] } ; + assign result__h48064 = { 56'd0, mmioPlatform_reqData[15:8] } ; + assign result__h48092 = { 56'd0, mmioPlatform_reqData[23:16] } ; + assign result__h48120 = { 56'd0, mmioPlatform_reqData[31:24] } ; + assign result__h48148 = { 56'd0, mmioPlatform_reqData[39:32] } ; + assign result__h48176 = { 56'd0, mmioPlatform_reqData[47:40] } ; + assign result__h48204 = { 56'd0, mmioPlatform_reqData[55:48] } ; + assign result__h48232 = { 56'd0, mmioPlatform_reqData[63:56] } ; + assign result__h48277 = { 48'd0, mmioPlatform_reqData[15:0] } ; + assign result__h48305 = { 48'd0, mmioPlatform_reqData[31:16] } ; + assign result__h48333 = { 48'd0, mmioPlatform_reqData[47:32] } ; + assign result__h48361 = { 48'd0, mmioPlatform_reqData[63:48] } ; + assign result__h48402 = { 32'd0, mmioPlatform_reqData[31:0] } ; + assign result__h48430 = { 32'd0, mmioPlatform_reqData[63:32] } ; + assign result__h48556 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[7:0] } ; - assign result__h48599 = + assign result__h48583 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[15:8] } ; - assign result__h48626 = + assign result__h48610 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[23:16] } ; - assign result__h48653 = + assign result__h48637 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:24] } ; - assign result__h48680 = + assign result__h48664 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[39:32] } ; - assign result__h48707 = + assign result__h48691 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[47:40] } ; - assign result__h48734 = + assign result__h48718 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[55:48] } ; - assign result__h48761 = + assign result__h48745 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:56] } ; - assign result__h48805 = + assign result__h48789 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[15:0] } ; - assign result__h48832 = + assign result__h48816 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:16] } ; - assign result__h48859 = + assign result__h48843 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[47:32] } ; - assign result__h48886 = + assign result__h48870 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:48] } ; - assign result__h48926 = + assign result__h48910 = { 32'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:0] } ; - assign result__h48953 = + assign result__h48937 = { 32'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:32] } ; - assign result__h49070 = + assign result__h49054 = { mmioPlatform_reqData[63:16], - IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915[7:0], + IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[7:0], mmioPlatform_reqData[7:0] } ; - assign result__h49136 = + assign result__h49120 = { mmioPlatform_reqData[63:24], - IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915[7:0], + IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[7:0], mmioPlatform_reqData[15:0] } ; - assign result__h49202 = + assign result__h49186 = { mmioPlatform_reqData[63:32], - IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915[7:0], + IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[7:0], mmioPlatform_reqData[23:0] } ; - assign result__h49268 = + assign result__h49252 = { mmioPlatform_reqData[63:40], - IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915[7:0], + IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[7:0], mmioPlatform_reqData[31:0] } ; - assign result__h49334 = + assign result__h49318 = { mmioPlatform_reqData[63:48], - IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915[7:0], + IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[7:0], mmioPlatform_reqData[39:0] } ; - assign result__h49400 = + assign result__h49384 = { mmioPlatform_reqData[63:56], - IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915[7:0], + IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[7:0], mmioPlatform_reqData[47:0] } ; - assign result__h49466 = - { IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915[7:0], + assign result__h49450 = + { IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[7:0], mmioPlatform_reqData[55:0] } ; - assign result__h49528 = + assign result__h49512 = { mmioPlatform_reqData[63:16], - IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915[15:0] } ; - assign result__h49573 = + IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[15:0] } ; + assign result__h49557 = { mmioPlatform_reqData[63:32], - IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915[15:0], + IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[15:0], mmioPlatform_reqData[15:0] } ; - assign result__h49639 = + assign result__h49623 = { mmioPlatform_reqData[63:48], - IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915[15:0], + IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[15:0], mmioPlatform_reqData[31:0] } ; - assign result__h49705 = - { IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915[15:0], + assign result__h49689 = + { IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[15:0], mmioPlatform_reqData[47:0] } ; - assign result__h49763 = + assign result__h49747 = { mmioPlatform_reqData[63:32], - IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915[31:0] } ; - assign result__h49808 = - { IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915[31:0], + IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[31:0] } ; + assign result__h49792 = + { IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911[31:0], mmioPlatform_reqData[31:0] } ; - assign v__h31759 = mmioPlatform_waitUpperMSIPCRs ? v__h31796 : 32'd0 ; - assign v__h31796 = { 31'd0, core_0$mmioToPlatform_cRs_first } ; - assign w17877_BITS_31_TO_0__q15 = w1__h47877[31:0] ; - assign w1___1__h47987 = { 32'd0, w1__h47877[31:0] } ; - assign w27878_BITS_31_TO_0__q16 = w2__h47878[31:0] ; - assign w2___1__h47988 = { 32'd0, w2__h47878[31:0] } ; - assign x1_avValue_data__h40339 = + assign v__h31743 = mmioPlatform_waitUpperMSIPCRs ? v__h31780 : 32'd0 ; + assign v__h31780 = { 31'd0, core_0$mmioToPlatform_cRs_first } ; + assign w17861_BITS_31_TO_0__q15 = w1__h47861[31:0] ; + assign w1___1__h47971 = { 32'd0, w1__h47861[31:0] } ; + assign w27862_BITS_31_TO_0__q16 = w2__h47862[31:0] ; + assign w2___1__h47972 = { 32'd0, w2__h47862[31:0] } ; + assign x1_avValue_data__h40323 = mmioPlatform_toHostQ_empty ? 64'd0 : mmioPlatform_toHostQ_data_0 ; - assign x1_avValue_data__h44806 = + assign x1_avValue_data__h44790 = mmioPlatform_fromHostQ_empty ? 64'd0 : mmioPlatform_fromHostQ_data_0 ; - assign x__h133989 = { llc_axi4_adapter_rg_rd_req_beat, 3'b0 } ; - assign x__h147903 = { llc_axi4_adapter_rg_wr_req_beat, 3'b0 } ; - assign x__h37428 = mmioPlatform_mtimecmp_0 ; - assign x__h40857 = + assign x__h133973 = { llc_axi4_adapter_rg_rd_req_beat, 3'b0 } ; + assign x__h147887 = { llc_axi4_adapter_rg_wr_req_beat, 3'b0 } ; + assign x__h37412 = mmioPlatform_mtimecmp_0 ; + assign x__h40841 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h40868 : - IF_mmioPlatform_reqBE_43_BIT_7_19_THEN_mmioPla_ETC___d715 ; - assign x__h42877 = + x__h40852 : + IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d711 ; + assign x__h42861 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h42888 : + x__h42872 : { mmioPlatform_reqBE[7] ? mmioPlatform_reqData[63:56] : 8'd0, mmioPlatform_reqBE[6] ? mmioPlatform_reqData[55:48] : 8'd0, mmioPlatform_reqBE[5] ? mmioPlatform_reqData[47:40] : 8'd0, @@ -6780,29 +6766,29 @@ module mkProc(CLK, mmioPlatform_reqBE[2] ? mmioPlatform_reqData[23:16] : 8'd0, mmioPlatform_reqBE[1] ? mmioPlatform_reqData[15:8] : 8'd0, mmioPlatform_reqBE[0] ? mmioPlatform_reqData[7:0] : 8'd0 } ; - assign x__h49985 = { mmioPlatform_curReq[63:3], 3'b0 } ; - assign x__h61277 = - SEL_ARR_propDstIdx_0_dummy2_1_read__058_AND_IF_ETC___d1089 ? + assign x__h49969 = { mmioPlatform_curReq[63:3], 3'b0 } ; + assign x__h61261 = + SEL_ARR_propDstIdx_0_dummy2_1_read__054_AND_IF_ETC___d1085 ? srcRR_0 : - NOT_propDstIdx_0_dummy2_1_read__058_059_OR_IF__ETC___d1092 ; - assign x__h74829 = + NOT_propDstIdx_0_dummy2_1_read__054_055_OR_IF__ETC___d1088 ; + assign x__h74813 = !CAN_FIRE_RL_doEnq_1 && - IF_enqDst_1_0_lat_0_whas__265_THEN_enqDst_1_0__ETC___d1306 ; + IF_enqDst_1_0_lat_0_whas__261_THEN_enqDst_1_0__ETC___d1302 ; assign x__h7925 = (mmio_axi4_adapter_f_reqs_from_core$D_OUT[71:68] == 4'd0 || mmio_axi4_adapter_f_reqs_from_core$D_OUT[67:64] == 4'd0) ? 3'b010 : 3'b011 ; - assign x__h79900 = - SEL_ARR_propDstIdx_1_0_dummy2_1_read__317_AND__ETC___d1358 ? + assign x__h79884 = + SEL_ARR_propDstIdx_1_0_dummy2_1_read__313_AND__ETC___d1354 ? srcRR_1_0 : - NOT_propDstIdx_1_0_dummy2_1_read__317_318_OR_I_ETC___d1361 ; - assign x__h90651 = old_dword__h89488 & y__h90653 ; - assign x_data__h30549 = { 31'd0, mmioPlatform_reqData[0] } ; - assign y__h90652 = + NOT_propDstIdx_1_0_dummy2_1_read__313_314_OR_I_ETC___d1357 ; + assign x__h90635 = old_dword__h89472 & y__h90637 ; + assign x_data__h30533 = { 31'd0, mmioPlatform_reqData[0] } ; + assign y__h90636 = llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[72:9] & - mask__h89485 ; - assign y__h90653 = + mask__h89469 ; + assign y__h90637 = { llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8] ? 8'd0 : 8'd255, @@ -7015,473 +7001,473 @@ module mkProc(CLK, llc_mem_server_rg_cacheline_cache_data) begin case (llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[34:32]) - 3'd0: dword__h93798 = llc_mem_server_rg_cacheline_cache_data[63:0]; - 3'd1: dword__h93798 = llc_mem_server_rg_cacheline_cache_data[127:64]; - 3'd2: dword__h93798 = llc_mem_server_rg_cacheline_cache_data[191:128]; - 3'd3: dword__h93798 = llc_mem_server_rg_cacheline_cache_data[255:192]; - 3'd4: dword__h93798 = llc_mem_server_rg_cacheline_cache_data[319:256]; - 3'd5: dword__h93798 = llc_mem_server_rg_cacheline_cache_data[383:320]; - 3'd6: dword__h93798 = llc_mem_server_rg_cacheline_cache_data[447:384]; - 3'd7: dword__h93798 = llc_mem_server_rg_cacheline_cache_data[511:448]; + 3'd0: dword__h93782 = llc_mem_server_rg_cacheline_cache_data[63:0]; + 3'd1: dword__h93782 = llc_mem_server_rg_cacheline_cache_data[127:64]; + 3'd2: dword__h93782 = llc_mem_server_rg_cacheline_cache_data[191:128]; + 3'd3: dword__h93782 = llc_mem_server_rg_cacheline_cache_data[255:192]; + 3'd4: dword__h93782 = llc_mem_server_rg_cacheline_cache_data[319:256]; + 3'd5: dword__h93782 = llc_mem_server_rg_cacheline_cache_data[383:320]; + 3'd6: dword__h93782 = llc_mem_server_rg_cacheline_cache_data[447:384]; + 3'd7: dword__h93782 = llc_mem_server_rg_cacheline_cache_data[511:448]; endcase end always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) begin case (llc_axi4_adapter_rg_wr_req_beat) - 3'd0: data64__h147793 = llc$to_mem_toM_first[63:0]; - 3'd1: data64__h147793 = llc$to_mem_toM_first[127:64]; - 3'd2: data64__h147793 = llc$to_mem_toM_first[191:128]; - 3'd3: data64__h147793 = llc$to_mem_toM_first[255:192]; - 3'd4: data64__h147793 = llc$to_mem_toM_first[319:256]; - 3'd5: data64__h147793 = llc$to_mem_toM_first[383:320]; - 3'd6: data64__h147793 = llc$to_mem_toM_first[447:384]; - 3'd7: data64__h147793 = llc$to_mem_toM_first[511:448]; + 3'd0: data64__h147777 = llc$to_mem_toM_first[63:0]; + 3'd1: data64__h147777 = llc$to_mem_toM_first[127:64]; + 3'd2: data64__h147777 = llc$to_mem_toM_first[191:128]; + 3'd3: data64__h147777 = llc$to_mem_toM_first[255:192]; + 3'd4: data64__h147777 = llc$to_mem_toM_first[319:256]; + 3'd5: data64__h147777 = llc$to_mem_toM_first[383:320]; + 3'd6: data64__h147777 = llc$to_mem_toM_first[447:384]; + 3'd7: data64__h147777 = llc$to_mem_toM_first[511:448]; endcase end always@(llc$dma_respLd_first) begin case (llc$dma_respLd_first[2:0]) - 3'd0: ld_data__h131955 = llc$dma_respLd_first[68:5]; - 3'd1: ld_data__h131955 = llc$dma_respLd_first[132:69]; - 3'd2: ld_data__h131955 = llc$dma_respLd_first[196:133]; - 3'd3: ld_data__h131955 = llc$dma_respLd_first[260:197]; - 3'd4: ld_data__h131955 = llc$dma_respLd_first[324:261]; - 3'd5: ld_data__h131955 = llc$dma_respLd_first[388:325]; - 3'd6: ld_data__h131955 = llc$dma_respLd_first[452:389]; - 3'd7: ld_data__h131955 = llc$dma_respLd_first[516:453]; + 3'd0: ld_data__h131939 = llc$dma_respLd_first[68:5]; + 3'd1: ld_data__h131939 = llc$dma_respLd_first[132:69]; + 3'd2: ld_data__h131939 = llc$dma_respLd_first[196:133]; + 3'd3: ld_data__h131939 = llc$dma_respLd_first[260:197]; + 3'd4: ld_data__h131939 = llc$dma_respLd_first[324:261]; + 3'd5: ld_data__h131939 = llc$dma_respLd_first[388:325]; + 3'd6: ld_data__h131939 = llc$dma_respLd_first[452:389]; + 3'd7: ld_data__h131939 = llc$dma_respLd_first[516:453]; endcase end always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) begin case (llc_axi4_adapter_rg_wr_req_beat) - 3'd0: strb8__h147794 = llc$to_mem_toM_first[519:512]; - 3'd1: strb8__h147794 = llc$to_mem_toM_first[527:520]; - 3'd2: strb8__h147794 = llc$to_mem_toM_first[535:528]; - 3'd3: strb8__h147794 = llc$to_mem_toM_first[543:536]; - 3'd4: strb8__h147794 = llc$to_mem_toM_first[551:544]; - 3'd5: strb8__h147794 = llc$to_mem_toM_first[559:552]; - 3'd6: strb8__h147794 = llc$to_mem_toM_first[567:560]; - 3'd7: strb8__h147794 = llc$to_mem_toM_first[575:568]; + 3'd0: strb8__h147778 = llc$to_mem_toM_first[519:512]; + 3'd1: strb8__h147778 = llc$to_mem_toM_first[527:520]; + 3'd2: strb8__h147778 = llc$to_mem_toM_first[535:528]; + 3'd3: strb8__h147778 = llc$to_mem_toM_first[543:536]; + 3'd4: strb8__h147778 = llc$to_mem_toM_first[551:544]; + 3'd5: strb8__h147778 = llc$to_mem_toM_first[559:552]; + 3'd6: strb8__h147778 = llc$to_mem_toM_first[567:560]; + 3'd7: strb8__h147778 = llc$to_mem_toM_first[575:568]; endcase end always@(llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT or llc_mem_server_rg_cacheline_cache_data) begin case (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32]) - 3'd0: old_dword__h89488 = llc_mem_server_rg_cacheline_cache_data[63:0]; + 3'd0: old_dword__h89472 = llc_mem_server_rg_cacheline_cache_data[63:0]; 3'd1: - old_dword__h89488 = llc_mem_server_rg_cacheline_cache_data[127:64]; + old_dword__h89472 = llc_mem_server_rg_cacheline_cache_data[127:64]; 3'd2: - old_dword__h89488 = llc_mem_server_rg_cacheline_cache_data[191:128]; + old_dword__h89472 = llc_mem_server_rg_cacheline_cache_data[191:128]; 3'd3: - old_dword__h89488 = llc_mem_server_rg_cacheline_cache_data[255:192]; + old_dword__h89472 = llc_mem_server_rg_cacheline_cache_data[255:192]; 3'd4: - old_dword__h89488 = llc_mem_server_rg_cacheline_cache_data[319:256]; + old_dword__h89472 = llc_mem_server_rg_cacheline_cache_data[319:256]; 3'd5: - old_dword__h89488 = llc_mem_server_rg_cacheline_cache_data[383:320]; + old_dword__h89472 = llc_mem_server_rg_cacheline_cache_data[383:320]; 3'd6: - old_dword__h89488 = llc_mem_server_rg_cacheline_cache_data[447:384]; + old_dword__h89472 = llc_mem_server_rg_cacheline_cache_data[447:384]; 3'd7: - old_dword__h89488 = llc_mem_server_rg_cacheline_cache_data[511:448]; + old_dword__h89472 = llc_mem_server_rg_cacheline_cache_data[511:448]; endcase end always@(mmioPlatform_curReq or - result__h48052 or - result__h48080 or - result__h48108 or - result__h48136 or - result__h48164 or - result__h48192 or result__h48220 or result__h48248) + result__h48036 or + result__h48064 or + result__h48092 or + result__h48120 or + result__h48148 or + result__h48176 or result__h48204 or result__h48232) begin case (mmioPlatform_curReq[2:0]) 3'h0: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d805 = - result__h48052; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 = + result__h48036; 3'h1: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d805 = - result__h48080; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 = + result__h48064; 3'h2: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d805 = - result__h48108; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 = + result__h48092; 3'h3: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d805 = - result__h48136; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 = + result__h48120; 3'h4: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d805 = - result__h48164; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 = + result__h48148; 3'h5: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d805 = - result__h48192; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 = + result__h48176; 3'h6: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d805 = - result__h48220; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 = + result__h48204; 3'h7: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d805 = - result__h48248; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 = + result__h48232; endcase end always@(mmioPlatform_curReq or - result__h48293 or - result__h48321 or result__h48349 or result__h48377) + result__h48277 or + result__h48305 or result__h48333 or result__h48361) begin case (mmioPlatform_curReq[2:0]) 3'h0: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d818 = - result__h48293; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814 = + result__h48277; 3'h2: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d818 = - result__h48321; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814 = + result__h48305; 3'h4: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d818 = - result__h48349; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814 = + result__h48333; 3'h6: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d818 = - result__h48377; - default: IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d818 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814 = + result__h48361; + default: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814 = 64'd0; endcase end - always@(mmioPlatform_curReq or result__h48418 or result__h48446) + always@(mmioPlatform_curReq or result__h48402 or result__h48430) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13 = - result__h48418; + result__h48402; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13 = - result__h48446; + result__h48430; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13 = 64'd0; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d805 or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d818 or + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 or + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814 or CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13 or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d825) + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d821) begin case (mmioPlatform_reqSz) 2'b0: - w2__h47878 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d805; + w2__h47862 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801; 2'b01: - w2__h47878 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d818; + w2__h47862 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814; 2'b10: - w2__h47878 = + w2__h47862 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13; 2'b11: - w2__h47878 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d825; + w2__h47862 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d821; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d805 or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d818 or - w2___1__h47988 or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d825) + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 or + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814 or + w2___1__h47972 or + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d821) begin case (mmioPlatform_reqSz) 2'b0: - w2__h47884 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d805; + w2__h47868 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801; 2'b01: - w2__h47884 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d818; - 2'b10: w2__h47884 = w2___1__h47988; + w2__h47868 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814; + 2'b10: w2__h47868 = w2___1__h47972; 2'b11: - w2__h47884 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d825; + w2__h47868 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d821; endcase end always@(mmioPlatform_curReq or - result__h48572 or - result__h48599 or - result__h48626 or - result__h48653 or - result__h48680 or - result__h48707 or result__h48734 or result__h48761) + result__h48556 or + result__h48583 or + result__h48610 or + result__h48637 or + result__h48664 or + result__h48691 or result__h48718 or result__h48745) begin case (mmioPlatform_curReq[2:0]) 3'h0: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d857 = - result__h48572; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 = + result__h48556; 3'h1: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d857 = - result__h48599; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 = + result__h48583; 3'h2: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d857 = - result__h48626; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 = + result__h48610; 3'h3: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d857 = - result__h48653; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 = + result__h48637; 3'h4: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d857 = - result__h48680; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 = + result__h48664; 3'h5: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d857 = - result__h48707; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 = + result__h48691; 3'h6: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d857 = - result__h48734; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 = + result__h48718; 3'h7: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d857 = - result__h48761; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 = + result__h48745; endcase end always@(mmioPlatform_curReq or - result__h48805 or - result__h48832 or result__h48859 or result__h48886) + result__h48789 or + result__h48816 or result__h48843 or result__h48870) begin case (mmioPlatform_curReq[2:0]) 3'h0: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d869 = - result__h48805; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865 = + result__h48789; 3'h2: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d869 = - result__h48832; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865 = + result__h48816; 3'h4: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d869 = - result__h48859; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865 = + result__h48843; 3'h6: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d869 = - result__h48886; - default: IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d869 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865 = + result__h48870; + default: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865 = 64'd0; endcase end - always@(mmioPlatform_curReq or result__h48926 or result__h48953) + always@(mmioPlatform_curReq or result__h48910 or result__h48937) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14 = - result__h48926; + result__h48910; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14 = - result__h48953; + result__h48937; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14 = 64'd0; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d857 or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d869 or + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 or + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865 or CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14 or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d876) + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d872) begin case (mmioPlatform_reqSz) 2'b0: - w1__h47877 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d857; + w1__h47861 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853; 2'b01: - w1__h47877 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d869; + w1__h47861 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865; 2'b10: - w1__h47877 = + w1__h47861 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q14; 2'b11: - w1__h47877 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d876; + w1__h47861 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d872; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d857 or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d869 or - w1___1__h47987 or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d876) + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 or + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865 or + w1___1__h47971 or + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d872) begin case (mmioPlatform_reqSz) 2'b0: - w1__h47882 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d857; + w1__h47866 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853; 2'b01: - w1__h47882 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d869; - 2'b10: w1__h47882 = w1___1__h47987; + w1__h47866 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865; + 2'b10: w1__h47866 = w1___1__h47971; 2'b11: - w1__h47882 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d876; + w1__h47866 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d872; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d857 or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d869 or - w17877_BITS_31_TO_0__q15 or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d876) + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853 or + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865 or + w17861_BITS_31_TO_0__q15 or + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d872) begin case (mmioPlatform_reqSz) 2'b0: - IF_mmioPlatform_reqSz_75_EQ_0b10_82_THEN_SEXT__ETC___d883 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d857; + IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d879 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d853; 2'b01: - IF_mmioPlatform_reqSz_75_EQ_0b10_82_THEN_SEXT__ETC___d883 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d869; + IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d879 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d865; 2'b10: - IF_mmioPlatform_reqSz_75_EQ_0b10_82_THEN_SEXT__ETC___d883 = - { {32{w17877_BITS_31_TO_0__q15[31]}}, - w17877_BITS_31_TO_0__q15 }; + IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d879 = + { {32{w17861_BITS_31_TO_0__q15[31]}}, + w17861_BITS_31_TO_0__q15 }; 2'b11: - IF_mmioPlatform_reqSz_75_EQ_0b10_82_THEN_SEXT__ETC___d883 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d876; + IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d879 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d872; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d805 or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d818 or - w27878_BITS_31_TO_0__q16 or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d825) + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801 or + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814 or + w27862_BITS_31_TO_0__q16 or + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d821) begin case (mmioPlatform_reqSz) 2'b0: - IF_mmioPlatform_reqSz_75_EQ_0b10_82_THEN_SEXT__ETC___d885 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d805; + IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d881 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d801; 2'b01: - IF_mmioPlatform_reqSz_75_EQ_0b10_82_THEN_SEXT__ETC___d885 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d818; + IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d881 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d814; 2'b10: - IF_mmioPlatform_reqSz_75_EQ_0b10_82_THEN_SEXT__ETC___d885 = - { {32{w27878_BITS_31_TO_0__q16[31]}}, - w27878_BITS_31_TO_0__q16 }; + IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d881 = + { {32{w27862_BITS_31_TO_0__q16[31]}}, + w27862_BITS_31_TO_0__q16 }; 2'b11: - IF_mmioPlatform_reqSz_75_EQ_0b10_82_THEN_SEXT__ETC___d885 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d825; + IF_mmioPlatform_reqSz_71_EQ_0b10_78_THEN_SEXT__ETC___d881 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d821; endcase end always@(mmioPlatform_reqAmofunc or - op_result__h49049 or - w2__h47884 or - op_result__h48485 or - op_result__h49015 or - op_result__h49020 or - op_result__h49025 or - op_result__h49043 or op_result__h49030 or op_result__h49036) + op_result__h49033 or + w2__h47868 or + op_result__h48469 or + op_result__h48999 or + op_result__h49004 or + op_result__h49009 or + op_result__h49027 or op_result__h49014 or op_result__h49020) begin case (mmioPlatform_reqAmofunc) 4'd0: - IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915 = - w2__h47884; + IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911 = + w2__h47868; 4'd1: - IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915 = - op_result__h48485; + IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911 = + op_result__h48469; 4'd2: - IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915 = - op_result__h49015; + IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911 = + op_result__h48999; 4'd3: - IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915 = - op_result__h49020; + IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911 = + op_result__h49004; 4'd4: - IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915 = - op_result__h49025; + IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911 = + op_result__h49009; 4'd5: - IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915 = - op_result__h49043; + IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911 = + op_result__h49027; 4'd7: - IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915 = - op_result__h49030; + IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911 = + op_result__h49014; 4'd8: - IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915 = - op_result__h49036; - default: IF_mmioPlatform_reqAmofunc_80_EQ_0_81_THEN_IF__ETC___d915 = - op_result__h49049; + IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911 = + op_result__h49020; + default: IF_mmioPlatform_reqAmofunc_76_EQ_0_77_THEN_IF__ETC___d911 = + op_result__h49033; endcase end always@(mmioPlatform_curReq or - result__h49528 or - result__h49573 or result__h49639 or result__h49705) + result__h49512 or + result__h49557 or result__h49623 or result__h49689) begin case (mmioPlatform_curReq[2:0]) 3'h0: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d948 = - result__h49528; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d944 = + result__h49512; 3'h2: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d948 = - result__h49573; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d944 = + result__h49557; 3'h4: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d948 = - result__h49639; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d944 = + result__h49623; 3'h6: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d948 = - result__h49705; - default: IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d948 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d944 = + result__h49689; + default: IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d944 = 64'd0; endcase end always@(mmioPlatform_curReq or - result__h47928 or - result__h49070 or - result__h49136 or - result__h49202 or - result__h49268 or - result__h49334 or result__h49400 or result__h49466) + result__h47912 or + result__h49054 or + result__h49120 or + result__h49186 or + result__h49252 or + result__h49318 or result__h49384 or result__h49450) begin case (mmioPlatform_curReq[2:0]) 3'h0: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d939 = - result__h47928; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935 = + result__h47912; 3'h1: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d939 = - result__h49070; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935 = + result__h49054; 3'h2: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d939 = - result__h49136; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935 = + result__h49120; 3'h3: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d939 = - result__h49202; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935 = + result__h49186; 3'h4: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d939 = - result__h49268; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935 = + result__h49252; 3'h5: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d939 = - result__h49334; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935 = + result__h49318; 3'h6: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d939 = - result__h49400; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935 = + result__h49384; 3'h7: - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d939 = - result__h49466; + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935 = + result__h49450; endcase end - always@(mmioPlatform_curReq or result__h49763 or result__h49808) + always@(mmioPlatform_curReq or result__h49747 or result__h49792) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17 = - result__h49763; + result__h49747; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17 = - result__h49808; + result__h49792; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17 = 64'd0; endcase end always@(mmioPlatform_reqSz or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d939 or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d948 or + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935 or + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d944 or CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17 or - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d825) + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d821) begin case (mmioPlatform_reqSz) 2'b0: - x__h47873 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d939; + x__h47857 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d935; 2'b01: - x__h47873 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d948; + x__h47857 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d944; 2'b10: - x__h47873 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17; + x__h47857 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q17; 2'b11: - x__h47873 = - IF_mmioPlatform_curReq_35_BITS_2_TO_0_77_EQ_0x_ETC___d825; + x__h47857 = + IF_mmioPlatform_curReq_31_BITS_2_TO_0_73_EQ_0x_ETC___d821; endcase end always@(mmioPlatform_reqFunc) begin case (mmioPlatform_reqFunc[5:4]) 2'd0, 2'd1, 2'd2: - IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_ETC___d481 = + IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d477 = mmioPlatform_reqFunc; 2'd3: - IF_mmioPlatform_reqFunc_40_BITS_5_TO_4_41_EQ_0_ETC___d481 = + IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d477 = { 2'd3, mmioPlatform_reqFunc[3:0] }; endcase end @@ -7489,15 +7475,15 @@ module mkProc(CLK, begin case (mmioPlatform_instSel) 1'd0: - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d983 = + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d979 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:0]; 1'd1: - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d983 = + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d979 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:32]; endcase end always@(mmioPlatform_reqFunc or - IF_IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4__ETC___d559 or + IF_IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4__ETC___d555 or core_0$RDY_mmioToPlatform_pRs_enq) begin case (mmioPlatform_reqFunc[5:4]) @@ -7505,11 +7491,11 @@ module mkProc(CLK, CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q18 = core_0$RDY_mmioToPlatform_pRs_enq; default: CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q18 = - IF_IF_NOT_mmioPlatform_reqFunc_40_BITS_5_TO_4__ETC___d559; + IF_IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4__ETC___d555; endcase end always@(mmioPlatform_reqFunc or - IF_mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioP_ETC___d625 or + IF_mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioP_ETC___d621 or core_0$RDY_mmioToPlatform_pRs_enq) begin case (mmioPlatform_reqFunc[5:4]) @@ -7517,315 +7503,315 @@ module mkProc(CLK, CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q19 = core_0$RDY_mmioToPlatform_pRs_enq; default: CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q19 = - IF_mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioP_ETC___d625; + IF_mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioP_ETC___d621; endcase end always@(srcRR_0 or propDstIdx_0_dummy2_1$Q_OUT or - IF_propDstIdx_0_lat_0_whas__005_THEN_propDstId_ETC___d1008 or + IF_propDstIdx_0_lat_0_whas__001_THEN_propDstId_ETC___d1004 or propDstIdx_1_dummy2_1$Q_OUT or - IF_propDstIdx_1_lat_0_whas__012_THEN_propDstId_ETC___d1015) + IF_propDstIdx_1_lat_0_whas__008_THEN_propDstId_ETC___d1011) begin case (srcRR_0) 1'd0: - SEL_ARR_propDstIdx_0_dummy2_1_read__058_AND_IF_ETC___d1089 = + SEL_ARR_propDstIdx_0_dummy2_1_read__054_AND_IF_ETC___d1085 = propDstIdx_0_dummy2_1$Q_OUT && - IF_propDstIdx_0_lat_0_whas__005_THEN_propDstId_ETC___d1008; + IF_propDstIdx_0_lat_0_whas__001_THEN_propDstId_ETC___d1004; 1'd1: - SEL_ARR_propDstIdx_0_dummy2_1_read__058_AND_IF_ETC___d1089 = + SEL_ARR_propDstIdx_0_dummy2_1_read__054_AND_IF_ETC___d1085 = propDstIdx_1_dummy2_1$Q_OUT && - IF_propDstIdx_1_lat_0_whas__012_THEN_propDstId_ETC___d1015; + IF_propDstIdx_1_lat_0_whas__008_THEN_propDstId_ETC___d1011; endcase end always@(srcRR_1_0 or propDstIdx_1_0_dummy2_1$Q_OUT or - IF_propDstIdx_1_0_lat_0_whas__174_THEN_propDst_ETC___d1177 or + IF_propDstIdx_1_0_lat_0_whas__170_THEN_propDst_ETC___d1173 or propDstIdx_1_1_dummy2_1$Q_OUT or - IF_propDstIdx_1_1_lat_0_whas__181_THEN_propDst_ETC___d1184) + IF_propDstIdx_1_1_lat_0_whas__177_THEN_propDst_ETC___d1180) begin case (srcRR_1_0) 1'd0: - SEL_ARR_propDstIdx_1_0_dummy2_1_read__317_AND__ETC___d1358 = + SEL_ARR_propDstIdx_1_0_dummy2_1_read__313_AND__ETC___d1354 = propDstIdx_1_0_dummy2_1$Q_OUT && - IF_propDstIdx_1_0_lat_0_whas__174_THEN_propDst_ETC___d1177; + IF_propDstIdx_1_0_lat_0_whas__170_THEN_propDst_ETC___d1173; 1'd1: - SEL_ARR_propDstIdx_1_0_dummy2_1_read__317_AND__ETC___d1358 = + SEL_ARR_propDstIdx_1_0_dummy2_1_read__313_AND__ETC___d1354 = propDstIdx_1_1_dummy2_1$Q_OUT && - IF_propDstIdx_1_1_lat_0_whas__181_THEN_propDst_ETC___d1184; + IF_propDstIdx_1_1_lat_0_whas__177_THEN_propDst_ETC___d1180; endcase end - always@(x__h61277 or n__read_id__h61463 or n__read_id__h61548) + always@(x__h61261 or n__read_id__h61447 or n__read_id__h61532) begin - case (x__h61277) - 1'd0: x__h61591 = n__read_id__h61463; - 1'd1: x__h61591 = n__read_id__h61548; + case (x__h61261) + 1'd0: x__h61575 = n__read_id__h61447; + 1'd1: x__h61575 = n__read_id__h61532; endcase end - always@(x__h61277 or n__read_child__h61464 or n__read_child__h61549) + always@(x__h61261 or n__read_child__h61448 or n__read_child__h61533) begin - case (x__h61277) - 1'd0: x__h61598 = n__read_child__h61464; - 1'd1: x__h61598 = n__read_child__h61549; + case (x__h61261) + 1'd0: x__h61582 = n__read_child__h61448; + 1'd1: x__h61582 = n__read_child__h61533; endcase end - always@(x__h61277 or - propDstData_0_dummy2_1_read__096_AND_IF_propDs_ETC___d1132 or - propDstData_1_dummy2_1_read__101_AND_IF_propDs_ETC___d1136) + always@(x__h61261 or + propDstData_0_dummy2_1_read__092_AND_IF_propDs_ETC___d1128 or + propDstData_1_dummy2_1_read__097_AND_IF_propDs_ETC___d1132) begin - case (x__h61277) + case (x__h61261) 1'd0: - CASE_x1277_0_propDstData_0_dummy2_1_read__096__ETC__q20 = - propDstData_0_dummy2_1_read__096_AND_IF_propDs_ETC___d1132; + CASE_x1261_0_propDstData_0_dummy2_1_read__092__ETC__q20 = + propDstData_0_dummy2_1_read__092_AND_IF_propDs_ETC___d1128; 1'd1: - CASE_x1277_0_propDstData_0_dummy2_1_read__096__ETC__q20 = - propDstData_1_dummy2_1_read__101_AND_IF_propDs_ETC___d1136; + CASE_x1261_0_propDstData_0_dummy2_1_read__092__ETC__q20 = + propDstData_1_dummy2_1_read__097_AND_IF_propDs_ETC___d1132; endcase end - always@(x__h61277 or - IF_propDstData_0_dummy2_1_read__096_THEN_IF_pr_ETC___d1112 or - IF_propDstData_1_dummy2_1_read__101_THEN_IF_pr_ETC___d1116) + always@(x__h61261 or + IF_propDstData_0_dummy2_1_read__092_THEN_IF_pr_ETC___d1108 or + IF_propDstData_1_dummy2_1_read__097_THEN_IF_pr_ETC___d1112) begin - case (x__h61277) + case (x__h61261) 1'd0: - CASE_x1277_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21 = - IF_propDstData_0_dummy2_1_read__096_THEN_IF_pr_ETC___d1112; + CASE_x1261_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21 = + IF_propDstData_0_dummy2_1_read__092_THEN_IF_pr_ETC___d1108; 1'd1: - CASE_x1277_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21 = - IF_propDstData_1_dummy2_1_read__101_THEN_IF_pr_ETC___d1116; + CASE_x1261_0_IF_propDstData_0_dummy2_1_read__0_ETC__q21 = + IF_propDstData_1_dummy2_1_read__097_THEN_IF_pr_ETC___d1112; endcase end - always@(x__h61277 or - IF_propDstData_0_dummy2_1_read__096_THEN_IF_pr_ETC___d1122 or - IF_propDstData_1_dummy2_1_read__101_THEN_IF_pr_ETC___d1126) + always@(x__h61261 or + IF_propDstData_0_dummy2_1_read__092_THEN_IF_pr_ETC___d1118 or + IF_propDstData_1_dummy2_1_read__097_THEN_IF_pr_ETC___d1122) begin - case (x__h61277) + case (x__h61261) 1'd0: - CASE_x1277_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22 = - IF_propDstData_0_dummy2_1_read__096_THEN_IF_pr_ETC___d1122; + CASE_x1261_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22 = + IF_propDstData_0_dummy2_1_read__092_THEN_IF_pr_ETC___d1118; 1'd1: - CASE_x1277_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22 = - IF_propDstData_1_dummy2_1_read__101_THEN_IF_pr_ETC___d1126; + CASE_x1261_0_IF_propDstData_0_dummy2_1_read__0_ETC__q22 = + IF_propDstData_1_dummy2_1_read__097_THEN_IF_pr_ETC___d1122; endcase end - always@(x__h61277 or n__read_addr__h61459 or n__read_addr__h61544) + always@(x__h61261 or n__read_addr__h61443 or n__read_addr__h61528) begin - case (x__h61277) + case (x__h61261) 1'd0: - CASE_x1277_0_n__read_addr1459_1_n__read_addr15_ETC__q23 = - n__read_addr__h61459; + CASE_x1261_0_n__read_addr1443_1_n__read_addr15_ETC__q23 = + n__read_addr__h61443; 1'd1: - CASE_x1277_0_n__read_addr1459_1_n__read_addr15_ETC__q23 = - n__read_addr__h61544; + CASE_x1261_0_n__read_addr1443_1_n__read_addr15_ETC__q23 = + n__read_addr__h61528; endcase end - always@(x__h79900 or + always@(x__h79884 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h79900) + case (x__h79884) 1'd0: - CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24 = + CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[512:449] : propDstData_1_0_rl[512:449]; 1'd1: - CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24 = + CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[512:449] : propDstData_1_1_rl[512:449]; endcase end - always@(x__h79900 or + always@(x__h79884 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h79900) + case (x__h79884) 1'd0: - CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 = + CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[448:385] : propDstData_1_0_rl[448:385]; 1'd1: - CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 = + CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[448:385] : propDstData_1_1_rl[448:385]; endcase end - always@(x__h79900 or n__read_child__h80081 or n__read_child__h80160) + always@(x__h79884 or n__read_child__h80065 or n__read_child__h80144) begin - case (x__h79900) - 1'd0: x__h82316 = n__read_child__h80081; - 1'd1: x__h82316 = n__read_child__h80160; + case (x__h79884) + 1'd0: x__h82300 = n__read_child__h80065; + 1'd1: x__h82300 = n__read_child__h80144; endcase end - always@(x__h79900 or + always@(x__h79884 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h79900) + case (x__h79884) 1'd0: - CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26 = + CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[384:321] : propDstData_1_0_rl[384:321]; 1'd1: - CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26 = + CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[384:321] : propDstData_1_1_rl[384:321]; endcase end - always@(x__h79900 or + always@(x__h79884 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h79900) + case (x__h79884) 1'd0: - CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 = + CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[320:257] : propDstData_1_0_rl[320:257]; 1'd1: - CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 = + CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[320:257] : propDstData_1_1_rl[320:257]; endcase end - always@(x__h79900 or + always@(x__h79884 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h79900) + case (x__h79884) 1'd0: - CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28 = + CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[256:193] : propDstData_1_0_rl[256:193]; 1'd1: - CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28 = + CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[256:193] : propDstData_1_1_rl[256:193]; endcase end - always@(x__h79900 or + always@(x__h79884 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h79900) + case (x__h79884) 1'd0: - CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 = + CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[192:129] : propDstData_1_0_rl[192:129]; 1'd1: - CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 = + CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[192:129] : propDstData_1_1_rl[192:129]; endcase end - always@(x__h79900 or + always@(x__h79884 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h79900) + case (x__h79884) 1'd0: - CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30 = + CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[128:65] : propDstData_1_0_rl[128:65]; 1'd1: - CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30 = + CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[128:65] : propDstData_1_1_rl[128:65]; endcase end - always@(x__h79900 or + always@(x__h79884 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h79900) + case (x__h79884) 1'd0: - CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 = + CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[64:1] : propDstData_1_0_rl[64:1]; 1'd1: - CASE_x9900_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 = + CASE_x9884_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[64:1] : propDstData_1_1_rl[64:1]; endcase end - always@(x__h79900 or + always@(x__h79884 or propDstData_1_0_dummy2_1$Q_OUT or - IF_propDstData_1_0_lat_0_whas__189_THEN_propDs_ETC___d1199 or + IF_propDstData_1_0_lat_0_whas__185_THEN_propDs_ETC___d1195 or propDstData_1_1_dummy2_1$Q_OUT or - IF_propDstData_1_1_lat_0_whas__227_THEN_propDs_ETC___d1237) + IF_propDstData_1_1_lat_0_whas__223_THEN_propDs_ETC___d1233) begin - case (x__h79900) + case (x__h79884) 1'd0: - CASE_x9900_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32 = + CASE_x9884_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32 = propDstData_1_0_dummy2_1$Q_OUT ? - IF_propDstData_1_0_lat_0_whas__189_THEN_propDs_ETC___d1199 : + IF_propDstData_1_0_lat_0_whas__185_THEN_propDs_ETC___d1195 : 2'd0; 1'd1: - CASE_x9900_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32 = + CASE_x9884_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q32 = propDstData_1_1_dummy2_1$Q_OUT ? - IF_propDstData_1_1_lat_0_whas__227_THEN_propDs_ETC___d1237 : + IF_propDstData_1_1_lat_0_whas__223_THEN_propDs_ETC___d1233 : 2'd0; endcase end - always@(x__h79900 or - NOT_propDstData_1_0_dummy2_1_read__365_376_OR__ETC___d1377 or - NOT_propDstData_1_1_dummy2_1_read__367_378_OR__ETC___d1379) + always@(x__h79884 or + NOT_propDstData_1_0_dummy2_1_read__361_372_OR__ETC___d1373 or + NOT_propDstData_1_1_dummy2_1_read__363_374_OR__ETC___d1375) begin - case (x__h79900) + case (x__h79884) 1'd0: - CASE_x9900_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33 = - NOT_propDstData_1_0_dummy2_1_read__365_376_OR__ETC___d1377; + CASE_x9884_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33 = + NOT_propDstData_1_0_dummy2_1_read__361_372_OR__ETC___d1373; 1'd1: - CASE_x9900_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33 = - NOT_propDstData_1_1_dummy2_1_read__367_378_OR__ETC___d1379; + CASE_x9884_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q33 = + NOT_propDstData_1_1_dummy2_1_read__363_374_OR__ETC___d1375; endcase end - always@(x__h79900 or n__read_addr__h80078 or n__read_addr__h80157) + always@(x__h79884 or n__read_addr__h80062 or n__read_addr__h80141) begin - case (x__h79900) + case (x__h79884) 1'd0: - CASE_x9900_0_n__read_addr0078_1_n__read_addr01_ETC__q34 = - n__read_addr__h80078; + CASE_x9884_0_n__read_addr0062_1_n__read_addr01_ETC__q34 = + n__read_addr__h80062; 1'd1: - CASE_x9900_0_n__read_addr0078_1_n__read_addr01_ETC__q34 = - n__read_addr__h80157; + CASE_x9884_0_n__read_addr0062_1_n__read_addr01_ETC__q34 = + n__read_addr__h80141; endcase end @@ -7876,7 +7862,7 @@ module mkProc(CLK, mmioPlatform_fromHostQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0; mmioPlatform_mtime <= `BSV_ASSIGNMENT_DELAY 64'd0; mmioPlatform_mtimecmp_0 <= `BSV_ASSIGNMENT_DELAY 64'd0; - mmioPlatform_mtip_0 <= `BSV_ASSIGNMENT_DELAY 1'd0; + mmioPlatform_mtip_0 <= `BSV_ASSIGNMENT_DELAY 1'd1; mmioPlatform_state <= `BSV_ASSIGNMENT_DELAY 2'd0; mmioPlatform_toHostAddr <= `BSV_ASSIGNMENT_DELAY 61'd0; mmioPlatform_toHostQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0; @@ -8241,14 +8227,14 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (EN_start) begin - v__h162860 = $stime; + v__h162844 = $stime; #0; end - v__h162854 = v__h162860 / 32'd10; + v__h162838 = v__h162844 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_start) $display("%0d: %m.method start: startpc %0h, tohostAddr %0h, fromhostAddr %0h", - v__h162854, + v__h162838, start_startpc, start_tohostAddr, start_fromhostAddr); @@ -8258,14 +8244,14 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost) begin - v__h162396 = $stime; + v__h162380 = $stime; #0; end - v__h162390 = v__h162396 / 32'd10; + v__h162374 = v__h162380 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost) $display("%0d: mmioPlatform.rl_tohost: 0x%0x (= %0d)", - v__h162390, + v__h162374, mmioPlatform_toHostQ_data_0, mmioPlatform_toHostQ_data_0); if (RST_N != `BSV_RESET_VALUE) @@ -8275,7 +8261,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0 && mmioPlatform_toHostQ_data_0[63:1] != 63'd0) - $display("FAIL %0d", failed_testnum__h162439); + $display("FAIL %0d", failed_testnum__h162423); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0) $finish(32'd0); @@ -9840,85 +9826,85 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $finish(32'd1); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) begin - v__h134353 = $stime; + v__h134337 = $stime; #0; end - v__h134347 = v__h134353 / 32'd10; + v__h134331 = v__h134337 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsps: beat %0d ", - v__h134347, + v__h134331, llc_axi4_adapter_rg_rd_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[2:1]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780 && + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776 && llc_axi4_adapter_master_xactor_rg_rd_data[0]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780 && + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776 && !llc_axi4_adapter_master_xactor_rg_rd_data[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) begin - v__h134520 = $stime; + v__h134504 = $stime; #0; end - v__h134514 = v__h134520 / 32'd10; + v__h134498 = v__h134504 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsp: fabric response error; exit", - v__h134514); + v__h134498); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) @@ -9980,135 +9966,135 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(" Response to LLC: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("MemRsMsg { ", "data: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(", ", "child: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(", ", "id: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("LdMemRqId { ", "refill: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780 && + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776 && llc_axi4_adapter_f_pending_reads$D_OUT[4]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780 && + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776 && !llc_axi4_adapter_f_pending_reads$D_OUT[4]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(", ", "mshrIdx: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("'h%h", llc_axi4_adapter_f_pending_reads$D_OUT[3:0], " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(" }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_wr_req_beat == 3'd0) begin - v__h136623 = $stime; + v__h136607 = $stime; #0; end - v__h136617 = v__h136623 / 32'd10; + v__h136601 = v__h136607 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_wr_req_beat == 3'd0) $display("%d: LLC_AXI4_Adapter.rl_handle_write_req: Wb request from LLC to memory:", - v__h136617); + v__h136601); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && @@ -11306,169 +11292,169 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) begin - v__h153967 = $stime; + v__h153951 = $stime; #0; end - v__h153961 = v__h153967 / 32'd10; + v__h153945 = v__h153951 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h153961); + $display("%0d: ERROR: CreditCounter: overflow", v__h153945); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) $finish(32'd1); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(" To fabric: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("AXI4_Wr_Addr { ", "awid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(", ", "awaddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) - $write("'h%h", mem_req_wr_addr_awaddr__h147878); + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + $write("'h%h", mem_req_wr_addr_awaddr__h147862); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(", ", "awlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("'h%h", 8'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(", ", "awsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("'h%h", 3'b011); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(", ", "awburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("'h%h", 2'b01); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(", ", "awlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("'h%h", 1'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(", ", "awcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("'h%h", 4'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(", ", "awprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("'h%h", 3'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(", ", "awqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(", ", "awregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(", ", "awuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("'h%h", 1'h0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("AXI4_Wr_Data { ", "wdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) - $write("'h%h", data64__h147793); + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + $write("'h%h", data64__h147777); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(", ", "wstrb: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) - $write("'h%h", strb8__h147794); + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + $write("'h%h", strb8__h147778); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(", ", "wlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(", ", "wuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("'h%h", 1'h0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_rd_req_beat == 3'd0) begin - v__h133734 = $stime; + v__h133718 = $stime; #0; end - v__h133728 = v__h133734 / 32'd10; + v__h133712 = v__h133718 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_rd_req_beat == 3'd0) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_req: Ld request from LLC to memory: beat %0d", - v__h133728, + v__h133712, llc_axi4_adapter_rg_rd_req_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && @@ -11539,159 +11525,159 @@ module mkProc(CLK, $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("AXI4_Rd_Addr { ", "arid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(", ", "araddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) - $write("'h%h", mem_req_rd_addr_araddr__h133954); + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) + $write("'h%h", mem_req_rd_addr_araddr__h133938); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(", ", "arlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("'h%h", 8'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(", ", "arsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("'h%h", 3'b011); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(", ", "arburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("'h%h", 2'b01); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(", ", "arlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("'h%h", 1'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(", ", "arcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("'h%h", 4'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(", ", "arprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("'h%h", 3'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(", ", "arqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(", ", "arregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(", ", "aruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("'h%h", 1'h0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) begin - v__h160661 = $stime; + v__h160645 = $stime; #0; end - v__h160655 = v__h160661 / 32'd10; + v__h160639 = v__h160645 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $display("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: beat %0d ", - v__h160655, + v__h160639, llc_axi4_adapter_rg_wr_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("'h%h", llc_axi4_adapter_master_xactor_rg_wr_resp[5:2]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("'h%h", llc_axi4_adapter_master_xactor_rg_wr_resp[1:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__763_U_ETC___d1780) + NOT_llc_axi4_adapter_cfg_verbosity_read__759_U_ETC___d1776) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) begin - v__h161169 = $stime; + v__h161153 = $stime; #0; end - v__h161163 = v__h161169 / 32'd10; + v__h161147 = v__h161153 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) $display("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: fabric response error: exit", - v__h161163); + v__h161147); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkTrace_Data2_to_Trace_Data.v b/src_SSITH_P3/xilinx_ip/hdl/mkTrace_Data2_to_Trace_Data.v index 52516d4..e61f0a2 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkTrace_Data2_to_Trace_Data.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkTrace_Data2_to_Trace_Data.v @@ -77,13 +77,13 @@ module mkTrace_Data2_to_Trace_Data(CLK, // remaining internal signals reg [63 : 0] x1_avValue_pc__h3546, x1_avValue_word1__h3550; - reg [11 : 0] CASE_in_put_BITS_475_TO_464_1_in_put_BITS_475__ETC__q2, + reg [11 : 0] CASE_in_put_BITS_475_TO_464_1_in_put_BITS_475__ETC__q1, csr_addr__h5310; - reg [4 : 0] CASE_f_inD_OUT_BITS_624_TO_620_14_5_15_5_16_5_ETC__q1, + reg [4 : 0] CASE_f_inD_OUT_BITS_624_TO_620_14_5_15_5_16_5_ETC__q5, x1_avValue_rd__h3549; - reg [3 : 0] CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q3, - CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q4; - reg [1 : 0] CASE_in_put_BITS_393_TO_392_0_in_put_BITS_393__ETC__q5; + reg [3 : 0] CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q2, + CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q3; + reg [1 : 0] CASE_in_put_BITS_393_TO_392_0_in_put_BITS_393__ETC__q4; wire [63 : 0] td_word2__h3589, td_word2__h3740, td_word3__h3590, @@ -167,13 +167,13 @@ module mkTrace_Data2_to_Trace_Data(CLK, // submodule f_in assign f_in$D_IN = { in_put[861:476], - CASE_in_put_BITS_475_TO_464_1_in_put_BITS_475__ETC__q2, + CASE_in_put_BITS_475_TO_464_1_in_put_BITS_475__ETC__q1, in_put[463:462], in_put[462] ? - CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q3 : - CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q4, + CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q2 : + CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q3, in_put[457:394], - CASE_in_put_BITS_393_TO_392_0_in_put_BITS_393__ETC__q5, + CASE_in_put_BITS_393_TO_392_0_in_put_BITS_393__ETC__q4, in_put[391:0] } ; assign f_in$ENQ = EN_in_put ; assign f_in$DEQ = CAN_FIRE_RL_rl_td2_to_td ; @@ -217,7 +217,7 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[393:392] != 2'd1 && f_in$D_OUT[624:620] == 5'd13) ? 5'd16 : - CASE_f_inD_OUT_BITS_624_TO_620_14_5_15_5_16_5_ETC__q1)))))))))), + CASE_f_inD_OUT_BITS_624_TO_620_14_5_15_5_16_5_ETC__q5)))))))))), x__h4855, f_in$D_OUT[626:625] == 2'b11, f_in$D_OUT[656:625], @@ -227,7 +227,7 @@ module mkTrace_Data2_to_Trace_Data(CLK, x__h5458, x__h5890, x__h5906 } ; - assign f_out$ENQ = f_in$EMPTY_N && f_out$FULL_N ; + assign f_out$ENQ = CAN_FIRE_RL_rl_td2_to_td ; assign f_out$DEQ = EN_out_get ; assign f_out$CLR = 1'b0 ; @@ -466,22 +466,6 @@ module mkTrace_Data2_to_Trace_Data(CLK, default: csr_addr__h5310 = 12'd2303; endcase end - always@(f_in$D_OUT) - begin - case (f_in$D_OUT[624:620]) - 5'd14, 5'd15, 5'd16, 5'd17, 5'd18: - CASE_f_inD_OUT_BITS_624_TO_620_14_5_15_5_16_5_ETC__q1 = 5'd5; - 5'd19, 5'd20: - CASE_f_inD_OUT_BITS_624_TO_620_14_5_15_5_16_5_ETC__q1 = 5'd15; - default: CASE_f_inD_OUT_BITS_624_TO_620_14_5_15_5_16_5_ETC__q1 = - (f_in$D_OUT[393:392] == 2'd1 && - (f_in$D_OUT[624:620] == 5'd2 || - f_in$D_OUT[624:620] == 5'd6 || - f_in$D_OUT[624:620] == 5'd7)) ? - 5'd13 : - 5'd5; - endcase - end always@(in_put) begin case (in_put[475:464]) @@ -529,9 +513,9 @@ module mkTrace_Data2_to_Trace_Data(CLK, 12'd3858, 12'd3859, 12'd3860: - CASE_in_put_BITS_475_TO_464_1_in_put_BITS_475__ETC__q2 = + CASE_in_put_BITS_475_TO_464_1_in_put_BITS_475__ETC__q1 = in_put[475:464]; - default: CASE_in_put_BITS_475_TO_464_1_in_put_BITS_475__ETC__q2 = + default: CASE_in_put_BITS_475_TO_464_1_in_put_BITS_475__ETC__q1 = 12'd2303; endcase end @@ -539,9 +523,9 @@ module mkTrace_Data2_to_Trace_Data(CLK, begin case (in_put[461:458]) 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: - CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q3 = + CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q2 = in_put[461:458]; - default: CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q3 = 4'd15; + default: CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q2 = 4'd15; endcase end always@(in_put) @@ -560,18 +544,34 @@ module mkTrace_Data2_to_Trace_Data(CLK, 4'd11, 4'd12, 4'd13: - CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q4 = + CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q3 = in_put[461:458]; - default: CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q4 = 4'd15; + default: CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q3 = 4'd15; endcase end always@(in_put) begin case (in_put[393:392]) 2'd0, 2'd1: - CASE_in_put_BITS_393_TO_392_0_in_put_BITS_393__ETC__q5 = + CASE_in_put_BITS_393_TO_392_0_in_put_BITS_393__ETC__q4 = in_put[393:392]; - default: CASE_in_put_BITS_393_TO_392_0_in_put_BITS_393__ETC__q5 = 2'd2; + default: CASE_in_put_BITS_393_TO_392_0_in_put_BITS_393__ETC__q4 = 2'd2; + endcase + end + always@(f_in$D_OUT) + begin + case (f_in$D_OUT[624:620]) + 5'd14, 5'd15, 5'd16, 5'd17, 5'd18: + CASE_f_inD_OUT_BITS_624_TO_620_14_5_15_5_16_5_ETC__q5 = 5'd5; + 5'd19, 5'd20: + CASE_f_inD_OUT_BITS_624_TO_620_14_5_15_5_16_5_ETC__q5 = 5'd15; + default: CASE_f_inD_OUT_BITS_624_TO_620_14_5_15_5_16_5_ETC__q5 = + (f_in$D_OUT[393:392] == 2'd1 && + (f_in$D_OUT[624:620] == 5'd2 || + f_in$D_OUT[624:620] == 5'd6 || + f_in$D_OUT[624:620] == 5'd7)) ? + 5'd13 : + 5'd5; endcase end