From f0bcd2ccd1552d7075c9ebb7060af24e46ed2fb2 Mon Sep 17 00:00:00 2001 From: Peter Rugg Date: Mon, 11 May 2020 23:52:04 +0100 Subject: [PATCH] Don't write on CSpecialRW from R0 --- src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv | 2 +- src_Core/RISCY_OOO/procs/lib/Decode.bsv | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv index 119c5ca..b60ec82 100755 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv @@ -332,7 +332,7 @@ module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline); // The above case will never be valid due to assertions above, but the below one will be in the case of CJALR. // This means that we will have instructions that both write SCR registers and also get mispredictions, unlike // the CSR file. Given the assertions above, this seems dangerous... - scrData: isValid(x.dInst.scr) ? Valid (exec_result.scrData) : tagged Invalid, + scrData: isValid(x.dInst.scr) && x.dInst.iType == Scr ? Valid (exec_result.scrData) : tagged Invalid, capException: exec_result.capException, check: exec_result.boundsCheck, `ifdef RVFI diff --git a/src_Core/RISCY_OOO/procs/lib/Decode.bsv b/src_Core/RISCY_OOO/procs/lib/Decode.bsv index 2d7d8ae..0a28a82 100755 --- a/src_Core/RISCY_OOO/procs/lib/Decode.bsv +++ b/src_Core/RISCY_OOO/procs/lib/Decode.bsv @@ -900,7 +900,7 @@ function DecodeResult decode(Instruction inst, Bool cap_mode); f3_cap_ThreeOp: begin case (funct7) f7_cap_CSpecialRW: begin - dInst.iType = Scr; + dInst.iType = rs1 == 0 ? Cap : Scr; regs.dst = Valid(tagged Gpr rd); regs.src1 = Valid(tagged Gpr rs1); regs.src2 = Invalid;