From f6bd0b0e1bf99e99620447df944381d2f4aff6a4 Mon Sep 17 00:00:00 2001 From: Franz Fuchs Date: Tue, 11 May 2021 14:13:02 +0100 Subject: [PATCH 1/3] first attempts to fix inhibit mismatch --- src_Core/CPU/CsrFile.bsv | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/src_Core/CPU/CsrFile.bsv b/src_Core/CPU/CsrFile.bsv index e6db11b..924e1ee 100644 --- a/src_Core/CPU/CsrFile.bsv +++ b/src_Core/CPU/CsrFile.bsv @@ -245,7 +245,7 @@ endfunction interface PerfCountersVec; interface Vector#(No_Of_Ctrs, Reg#(Data)) counter_vec; interface Vector#(No_Of_Ctrs, Reg#(Data)) event_vec; - interface Reg#(Data) inhibit; + interface Reg#(Bit#(No_Of_Ctrs)) inhibit; method Action send_performance_events (Vector #(No_Of_Evts, Bit#(Report_Width)) evts); endinterface (* synthesize *) @@ -283,8 +283,8 @@ module mkPerfCountersToooba (PerfCountersVec); interface counter_vec = counters; interface event_vec = events; interface inhibit = interface Reg; - method Action _write(Data x) = writeCounterInhibitFF.enq(truncate(x)); - method Data _read = zeroExtend(perf_counters.read_ctr_inhibit); + method Action _write(Bit#(No_Of_Ctrs) x) = writeCounterInhibitFF.enq(truncate(x)); + method Bit#(No_Of_Ctrs) _read = (perf_counters.read_ctr_inhibit); endinterface; method send_performance_events = perf_counters.send_performance_events; endmodule @@ -821,8 +821,19 @@ module mkCsrFile #(Data hartid)(CsrFile); Reg#(CapReg) mScratchC_reg <- mkCsrReg(nullCap); Ehr#(2, CapReg) mepcc_reg <- mkConfigEhr(defaultValue); +`ifdef PERFORMANCE_MONITORING + // Performance monitoring + Reg#(Bit#(1)) mcountinhibit_cy_reg <- mkReg(0); + Reg#(Bit#(1)) mcountinhibit_ir_reg <- mkReg(0); + Reg#(Data) mcountinhibit_reg = concatReg5(readOnlyReg(32'h00000000), perf_counters.inhibit, mcountinhibit_ir_reg, readOnlyReg(1'b0), mcountinhibit_cy_reg); +`endif + rule incCycle; +`ifdef PERFORMANCE_MONITORING + if(unpack(mcountinhibit_cy_reg)) mcycle_ehr[1] <= mcycle_ehr[1] + 1; +`else mcycle_ehr[1] <= mcycle_ehr[1] + 1; +`endif endrule // Function for getting a csr given an index @@ -880,7 +891,8 @@ module mkCsrFile #(Data hartid)(CsrFile); csrAddrMHARTID: mhartid_csr; csrAddrMCCSR: mccsr_csr; `ifdef PERFORMANCE_MONITORING - csrAddrMCOUNTERINHIBIT: perf_counters.inhibit; + //csrAddrMCOUNTERINHIBIT: perf_counters.inhibit; + csrAddrMCOUNTERINHIBIT: mcountinhibit_reg; `endif `ifdef SECURITY csrAddrMEVBASE: mevbase_csr; From fcea3a1f4e218ad401967a8c55ff7f676852424e Mon Sep 17 00:00:00 2001 From: Franz Fuchs Date: Tue, 11 May 2021 19:28:49 +0100 Subject: [PATCH 2/3] included suggestions from Peter (pdr32) --- src_Core/CPU/CsrFile.bsv | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/src_Core/CPU/CsrFile.bsv b/src_Core/CPU/CsrFile.bsv index 924e1ee..2441e38 100644 --- a/src_Core/CPU/CsrFile.bsv +++ b/src_Core/CPU/CsrFile.bsv @@ -283,7 +283,7 @@ module mkPerfCountersToooba (PerfCountersVec); interface counter_vec = counters; interface event_vec = events; interface inhibit = interface Reg; - method Action _write(Bit#(No_Of_Ctrs) x) = writeCounterInhibitFF.enq(truncate(x)); + method Action _write(Bit#(No_Of_Ctrs) x) = writeCounterInhibitFF.enq(x); method Bit#(No_Of_Ctrs) _read = (perf_counters.read_ctr_inhibit); endinterface; method send_performance_events = perf_counters.send_performance_events; @@ -823,14 +823,14 @@ module mkCsrFile #(Data hartid)(CsrFile); `ifdef PERFORMANCE_MONITORING // Performance monitoring - Reg#(Bit#(1)) mcountinhibit_cy_reg <- mkReg(0); - Reg#(Bit#(1)) mcountinhibit_ir_reg <- mkReg(0); + Reg#(Bit#(1)) mcountinhibit_cy_reg <- mkCsrReg(0); + Reg#(Bit#(1)) mcountinhibit_ir_reg <- mkCsrReg(0); Reg#(Data) mcountinhibit_reg = concatReg5(readOnlyReg(32'h00000000), perf_counters.inhibit, mcountinhibit_ir_reg, readOnlyReg(1'b0), mcountinhibit_cy_reg); `endif rule incCycle; `ifdef PERFORMANCE_MONITORING - if(unpack(mcountinhibit_cy_reg)) mcycle_ehr[1] <= mcycle_ehr[1] + 1; + if(!unpack(mcountinhibit_cy_reg)) mcycle_ehr[1] <= mcycle_ehr[1] + 1; `else mcycle_ehr[1] <= mcycle_ehr[1] + 1; `endif @@ -1373,7 +1373,11 @@ module mkCsrFile #(Data hartid)(CsrFile); }; method Action incInstret(SupCnt x); +`ifdef PERFORMANCE_MONITORING + if(!unpack(mcountinhibit_cy_reg)) minstret_ehr[1] <= minstret_ehr[1] + zeroExtend(x); +`else minstret_ehr[1] <= minstret_ehr[1] + zeroExtend(x); +`endif endmethod method Action setTime(Data t); From d78a2799d396f0f02ebeb900eee8f32e2de9db3c Mon Sep 17 00:00:00 2001 From: Franz Fuchs Date: Wed, 12 May 2021 10:46:07 +0100 Subject: [PATCH 3/3] Fixed small mistake pointed out by Peter(pdr32) --- src_Core/CPU/CsrFile.bsv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src_Core/CPU/CsrFile.bsv b/src_Core/CPU/CsrFile.bsv index 2441e38..77ca3a6 100644 --- a/src_Core/CPU/CsrFile.bsv +++ b/src_Core/CPU/CsrFile.bsv @@ -1374,7 +1374,7 @@ module mkCsrFile #(Data hartid)(CsrFile); method Action incInstret(SupCnt x); `ifdef PERFORMANCE_MONITORING - if(!unpack(mcountinhibit_cy_reg)) minstret_ehr[1] <= minstret_ehr[1] + zeroExtend(x); + if(!unpack(mcountinhibit_ir_reg)) minstret_ehr[1] <= minstret_ehr[1] + zeroExtend(x); `else minstret_ehr[1] <= minstret_ehr[1] + zeroExtend(x); `endif