From f1e04486b7aaf98adbba6a442e7843ce9bba668f Mon Sep 17 00:00:00 2001 From: Peter Rugg Date: Thu, 16 Apr 2020 20:53:08 +0100 Subject: [PATCH] Work on SCR-related instructions --- src_Core/ISA/ISA_Decls_CHERI.bsv | 28 +++++++++++++++++-- .../procs/RV64G_OOO/AluExePipeline.bsv | 3 ++ src_Core/RISCY_OOO/procs/lib/Decode.bsv | 24 ++++++++++++++-- src_Core/RISCY_OOO/procs/lib/Exec.bsv | 6 ++-- src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv | 6 +++- 5 files changed, 59 insertions(+), 8 deletions(-) diff --git a/src_Core/ISA/ISA_Decls_CHERI.bsv b/src_Core/ISA/ISA_Decls_CHERI.bsv index d421127..435f162 100755 --- a/src_Core/ISA/ISA_Decls_CHERI.bsv +++ b/src_Core/ISA/ISA_Decls_CHERI.bsv @@ -98,8 +98,32 @@ typedef enum { SCR_MTCC = 5'd28, SCR_MTDC = 5'd29, SCR_MScratchC = 5'd30, - SCR_MEPCC = 5'd31 -} SCR deriving(Bits, Eq, FShow); + SCR_MEPCC = 5'd31, + + // As with CSRs, SCR that catches all unimplemented SCRs + SCR_None = 5'd10 +} SCR deriving(Bits, Eq, FShow, Bounded); + +function SCR unpackSCR(Bit#(5) x); + return (case(x) + pack(SCR'(SCR_PCC )): (SCR_PCC ); + pack(SCR'(SCR_DDC )): (SCR_DDC ); +// pack(SCR'(SCR_UTCC )): (SCR_UTCC ); +// pack(SCR'(SCR_UTDC )): (SCR_UTDC ); +// pack(SCR'(SCR_UScratchC)): (SCR_UScratchC); +// pack(SCR'(SCR_UEPCC )): (SCR_UEPCC ); + pack(SCR'(SCR_STCC )): (SCR_STCC ); + pack(SCR'(SCR_STDC )): (SCR_STDC ); + pack(SCR'(SCR_SScratchC)): (SCR_SScratchC); + pack(SCR'(SCR_SEPCC )): (SCR_SEPCC ); + pack(SCR'(SCR_MTCC )): (SCR_MTCC ); + pack(SCR'(SCR_MTDC )): (SCR_MTDC ); + pack(SCR'(SCR_MScratchC)): (SCR_MScratchC); + pack(SCR'(SCR_MEPCC )): (SCR_MEPCC ); + + default : (SCR_None ); + endcase); +endfunction function CapPipe update_scr_via_csr (CapPipe old_scr, WordXL new_csr); let new_scr = setOffset(old_scr, new_csr); diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv index 671b719..727f98e 100755 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv @@ -256,6 +256,9 @@ module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline); // get rVal2 (check bypass) CapPipe rVal2 = nullCap; + if(x.dInst.scr matches tagged Valid .scr) begin + rVal2 = cast(inIfc.scaprf_rd(scr)); + end if(x.regs.src2 matches tagged Valid .src2 &&& src2 != 0) begin rVal2 <- readRFBypass(src2, regsReady.src2, inIfc.rf_rd2(src2), bypassWire); end diff --git a/src_Core/RISCY_OOO/procs/lib/Decode.bsv b/src_Core/RISCY_OOO/procs/lib/Decode.bsv index 7c31bd4..0ed0ebc 100755 --- a/src_Core/RISCY_OOO/procs/lib/Decode.bsv +++ b/src_Core/RISCY_OOO/procs/lib/Decode.bsv @@ -753,7 +753,21 @@ function DecodeResult decode(Instruction inst); f3_cap_ThreeOp: begin case (funct7) f7_cap_CSpecialRW: begin - // TODO + // TODO capChecks + + dInst.iType = Alu; + regs.dst = Valid(tagged Gpr rd); + regs.src1 = Valid(tagged Gpr rs1); + regs.src2 = Invalid; + dInst.scr = Valid (unpackSCR(rs2)); + + let scrType = case (rs2[1:0]) + 0: TCC; + 3: EPCC; + default: Normal; + endcase; + + dInst.execFunc = CapModify (SpecialRW (scrType)); end f7_cap_CSetBounds: begin illegalInst = True; @@ -922,7 +936,13 @@ function DecodeResult decode(Instruction inst); dInst.iType = Alu; regs.dst = Valid(tagged Gpr rd); regs.src1 = Valid(tagged Gpr rs1); - regs.src2 = Valid(tagged Gpr rs2); + if (rs2 == 0) begin + regs.src2 = Invalid; + dInst.scr = Valid (SCR_DDC); + end else begin + regs.src2 = Valid (tagged Gpr rs2); + dInst.scr = Invalid; + end dInst.imm = Invalid; dInst.execFunc = CapInspect (ToPtr); end diff --git a/src_Core/RISCY_OOO/procs/lib/Exec.bsv b/src_Core/RISCY_OOO/procs/lib/Exec.bsv index aa9e935..69b9cda 100755 --- a/src_Core/RISCY_OOO/procs/lib/Exec.bsv +++ b/src_Core/RISCY_OOO/procs/lib/Exec.bsv @@ -116,8 +116,8 @@ function CapPipe capModify(CapPipe a, CapPipe b, CapModifyFunc func); modifyOffset(a, getAddr(b), offsetOp == IncOffset).value; tagged SetBounds .boundsOp : setBoundsALU(a, getAddr(b), boundsOp); - //tagged SpecialRW : - // error("SpecialRW not yet implemented"); + tagged SpecialRW .scrType : + a; //TODO masking of various bits tagged SetAddr .addrSource : setAddr(a, addrSource == Src2Type ? (isSealed(b) ? zeroExtend(getType(b)) : -1) : getAddr(b)).value; tagged Seal : @@ -277,7 +277,7 @@ function ExecResult basicExec(DecodedInst dInst, CapPipe rVal1, CapPipe rVal2, C Ld, St, Lr, Sc, Amo : nullWithAddr(alu_result); default : nullWithAddr(cf.nextPc); endcase); - CapPipe scr_data = rVal1; + CapPipe scr_data = modify_result; return ExecResult{data: data, csrData: csr_data, scrData: scr_data, addr: addr, controlFlow: cf, capException: capException}; endfunction diff --git a/src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv b/src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv index f7fbb84..822bf90 100755 --- a/src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv +++ b/src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv @@ -423,6 +423,10 @@ typedef enum { SetBounds, CRRL, CRAM } SetBoundsFunc deriving(Bits, Eq, FShow); +typedef enum { + TCC, EPCC, Normal +} SpecialRWFunc deriving(Bits, Eq, FShow); + typedef enum { Src2Type, Src2Addr } AddrSource deriving(Bits, Eq, FShow); @@ -434,7 +438,7 @@ typedef enum { typedef union tagged { ModifyOffsetFunc ModifyOffset; SetBoundsFunc SetBounds; - void SpecialRW; + SpecialRWFunc SpecialRW; AddrSource SetAddr; void Seal; SrcSelector Unseal;